| submitted | available | document details (if available) | source link |
|---|---|---|---|
| Important Instructions Antenna House PDF Output Library 6.3.762 (Linux64) |
| various | User Manual | Users Manual | 1.52 MiB |
Important Instructions WARNING This kit is to be installed in accordance with the manufacturers instructions and all codes and re-
quirements of the authority having jurisdiction. In Canada, this conversion/installation shall be carried out in accordance with the requirements of the pro-
vincial authorities having jurisdiction and in accord-
ance with the requirements of the CAN/CGA-B149.1 and CAN/CGA-B149.2 installation code. Failure to follow instructions could result in serious injury, death or property damage. The qualified agency per-
forming this work assumes all responsibility for this kit installation. W013R4 WARNING To reduce the risk of electric shock, fire, explosion, serious injury or death:
Disconnect electric power to the machine before Close gas shut-off valve to the machine before Close steam gate valve to the machine before Never start the machine with any guards/panels servicing. servicing. servicing. removed. Whenever ground wires are removed during serv-
icing, these ground wires must be reconnected to ensure that the machine is properly grounded. W017 Kit consists of:
204890 Wireless Network Control F8674006 D503661 55881 XXXXXX F8673901 XXXXXX 8-18-253EN Wireless Network Harness Screws Wire Ties Conversion Label Network Option Diagram Wireless Control Label Kit Instructions 1 1 2 2 1 1 1 1 Special Tools required for this kit:
Magnetic 5/16 in. Socket IMPORTANT: This kit must be installed by a qualified service person. NOTE: Refer to appropriate service manual to aid in the installation of this kit. IMPORTANT: When reference is made to directions
(right or left) in this instructions, it is from operator's position facing front of machine. FCC COMPLIANCE STATEMENT CAUTION Changes or modifications not expressly approved could void your authority to use this equipment . This device complies with Part 15 of the FCC Rules. Operation to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interfer-
Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 1 Form No. 8-18-253EN October 2018 IMPORTANT: Be careful not to damage control panel overlay when prying up tabs. 1 1. Do Not Bend Figure 2 TLW1683K 5. 4. Adjust the compliance jumpers on the 204890 Wireless Net-
work Control. Refer to Compliance Jumper (H1) section at the end of these instructions. Remove double sided tape backing from 204890 Wireless Network Control. Position 204890 Wireless Network Control so that the mounting tabs on the Network Board go in front of the tabs on the control panel and the assembly mounts to the right of the mounting tabs, as shown in Figure 3 . (The control should be to the right of the mounting tabs.) Then attach using the (2) D503661 Screws. Refer to Figure 3 . 6. ence received, including interference that may cause undesired operation. INDUSTRY CANADA STATEMENT This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada ap-
plicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit ac-
cepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. 1. IMPORTANT - Disconnect electrical power to machine. Control will not recognize network board until power is cy-
cled to machine. 2. Remove two control panel attaching screws and lay assembly forward on protective padding. NOTE: There are four tabs located on backside of con-
trol panel frame. Only the two tabs closest to the con-
trol must be bent upward. Refer to Figure 1 and Figure 2 . 1 2 3 1. Screwdriver 2. Pliers 3. Tabs TLW1682K Figure 1 3. Use a flat blade screwdriver and slightly bend each tab up on-
ly far enough to allow getting the jaws of a pliers under each tab and bend to 90 degrees. Make sure each tab is bent up square and straight. Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 2 Form No. 8-18-253EN 7. Install F8674006 Wireless Network Harness between network board "H3" and the electronic control "H1". Refer to Figure 4 . 8. Secure the F8674006 Wireless Network Harness using the (2) 55881 Wire Ties as shown in Figure 4 . 9. Place F8673901 Network Option Diagram in control cabinet with existing diagrams. 10. Place XXXXXX Wireless Control Label in the control hood be-hind the control panel. 11. Fill out and place XXXXXX Conversion Label in control hood behind control panel. 12. Reconnect electrical power to the machine. NOTE: The machine control MUST have been powered down prior to connecting the wireless control in order for the control to recognize the board and to allow communication with it. 1 1. D503661 Screws Figure 3 TLW1680K_SVG 1. "H1"
2. 55881 Wire Ties 3. "H3"
4. 204890 Wireless Network Control 5. F8674006 Wireless Network Harness 6. Electronic Control Figure 4 Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 3 Form No. 8-18-253EN 1. IMPORTANT - Disconnect electrical power to machine. Control will not recognize network board until power is cy-
cled to machine. 2. Open access panel to gain access to the control area. Refer to Service Manual. 1 2 4. 3. Adjust the compliance jumpers on the 204890 Wireless Net-
work Control. Refer to Compliance Jumper (H1) section at the end of these instructions. Install the F8674006 Wireless Network Harness between the network board "H3" refer to Figure 6 , and the electronic con-
trol "H1". Refer to Figure 7 . Remove double sided tape backing from 204890 Wireless Network Control. 5. 6. Place the tab on 204890 Wireless Network Control into slot in front bulkhead and secure opposite end with one D503661 Screw. Refer to Figure 5 . Washer Illustrated 1. 204890 Wireless Network Control 2. Slot 3. D503661 Screw Figure 5 4 3 FLW226K_SVG 1. Electronic Control 2. "H1"
3. "H3"
4. F8674006 Wireless Network Harness Figure 6 Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 4 Form No. 8-18-253EN D503661 Screw. Refer to Figure 8 . Repeat for installing sec-
ond network board. 1 2 3 FLW227K 4 3 SWD273K_SVG 1. 204890 Wireless Network Control (Washer) 2. Slot 3. 204890 Wireless Network Control (Dryer) 4. D503661 Screws Figure 8 6. Install F8674006 Wireless Network Harness between network board "H3", refer to Figure 9 , and electronic control "H1". Refer to Figure 10 . 1 2 3 1 2 1. Electronic Control 2. "H1"
3. F8674006 Wireless Network Harness Figure 7 7. 8. Place F8673901 Network Option Diagram in control cabinet with existing diagrams. Place XXXXXX Wireless Control Label in control cabinet be-hind control panel. 1 9. Fill out and place XXXXXX Conversion Label in control cabinet 2 located behind control panel. 10. Close access panel. 11. Reconnect electrical power to the machine. NOTE: The machine control MUST have been powered down prior to connecting the wireless control assem-
bly in order for the control to recognize the board and to allow communication with it. 1. IMPORTANT - Disconnect electrical power to machine. Control will not recognize network board until power is cy-
cled to machine. 2. Open access panel to gain access to the control area. Refer to Service Manual. 3. Adjust the compliance jumpers on the 204890 Wireless Net-
work Control. Refer to Compliance Jumper (H1) section at the end of these instructions. 4. Remove double sided tape backing from 204890 Wireless Network Control. 5. Place tab on 204890 Wireless Network Control into slot in front bulkhead and secure opposite end with one 5 4 SWD274K_SVG 1. "H3"
2. Electronic Control (Washer) 3. Electronic Control (Dryer) 4. "H3"
5. F8674006 Wireless Network Harness Figure 9 Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 5 Form No. 8-18-253EN 7. Add one 55881 Wire Tie to backside of electronic control as shown in Figure 10 . 8. Place F8673901 Wiring Diagram in control cabinet with ex-
isting diagrams. 9. Place XXXXXX Wireless Control Label in the control cabinet. 10. Fill out and place XXXXXX Conversion Label in control cabinet located behind control panel. 11. Reconnect electrical power to the machine. NOTE: The machine control MUST have been powered down prior to connecting the wireless control assem-
bly in order for the control to recognize the board and to allow communication with it. NOTE: Refer to network installation manual for ma-
chine connections to network. 2 3 1 7 1. Electronic Control (Dryer) 2. Electronic Control (Washer) 3. Tape 4. "H1" Connection (Washer) 5. F8674006 Wireless Network Harness 6. 55881 Wire Tie 7. "H1" Connection (Dryer) 4 5 6 SWD275K Figure 10 Compliance Jumper (H1) The compliance jumper is used to enforce limits set by local agencies on WiFi channel usage and output power. This jumper must be placed on the pins described in this section that corre-
spond to the location where the Wireless Network Control will be operated. If the jumper is set incorrectly, the Wireless Network Control will be out of compliance with local agencies. If the jumper is not set at all, the Wireless Network Control will operate Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 6 Form No. 8-18-253EN at a reduced power-level, which will reduce the performance of the Wireless Network Control. NOTE: It is the responsibility of the installer to make sure that the Compliance Jumper is set to meet local standards. Incorrect settings will cause the board to be out of compliance and may lead to reduced range and loss of WiFi channels. The jumper must be placed in one of three locations on header
"H1". The three locations are shown in the table below and also in Figure 11 . Region Hi Jumper Location H1 Pins US EU JP 9 & 10 Left Most Posi-
tion Second From Left 7 & 8 Third From Left 5, 7, 6 1 2 3 COM238K 1. US 2. EU Accepting 3. JP Figure 11 Copyright, Alliance Laundry Systems LLC -
DO NOT COPY or TRANSMIT 7 Form No. 8-18-253EN CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 4 Terminal Configuration and Functions 4.1 Pin Diagram Figure 4-1 shows pin assignments for the 64-pin VQFN package. www.ti.com NC = No internal connection Figure 4-1. VQFN 64-Pin Assignments Top View 10 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF VDD_RAMGPIO0RTC_XTAL_PRTC_XTAL_NGPIO30VIN_IO2GPIO1VDD_DIG2GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO94950515253545556575859606162636448474645444342414039383736353433VDD_ANA1VDD_ANA2DCDC_ANA2_SW_NDCDC_ANA2_SW_PVIN_DCDC_DIGDCDC_DIG_SWDCDC_PA_OUTDCDC_PA_SW_NDCDC_PA_SW_PVIN_DCDC_PADCDC_ANA_SWVIN_DCDC_ANALDO_IN1SOP0SOP1VDD_PA_IN32313029282726252423222120191817nRESETRF_BGANTSEL2ANTSEL1NCNCNCLDO_IN2VDD_PLLWLAN_XTAL_PWLAN_XTAL_NSOP2TMSTCKGPIO28TDO12345678910111213141516GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16GPIO17VDD_DIG1VIN_IO1FLASH_SPI_CLKFLASH_SPI_DOUTFLASH_SPI_DINFLASH_SPI_CSGPIO22TDI www.ti.com 4.2 Pin Attributes and Pin Multiplexing CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and register control. TI highly recommends using Pin Mux Tool to obtain the desired pinout. NOTE The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 4-1 and Table 4-2 list the pin descriptions and attributes. Table 4-3 lists the signal descriptions. Table 4-4 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers. The following special considerations apply:
All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin. All I/Os support 10-A pullup and pulldown resistors. The VIO and VBAT supply must be tied together at all times. By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW. All digital I/Os are nonfail-safe. NOTE If an external device drives a positive voltage to the signal pads and the CC3220x device is not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3220x device can occur. To prevent current draw, TI recommends any one of the following conditions:
All devices interfaced to the CC3220x device must be powered from the same power rail as the chip. Use level shifters between the device and any external devices fed from other independent rails. The nRESET pin of the CC3220x device must be held low until the VBAT supply to the device is driven and stable. All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state. NO. PINS NAME 1 2 3 4 5 6 7 8 9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 VDD_DIG1 Table 4-1. Pin Descriptions TYPE DESCRIPTION I/O I/O I/O I/O I/O I/O I/O I/O Power General-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output Internal digital core voltage SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAG No Yes No Yes No No No Yes N/A No No No No No No No No N/A No No No No No No No No N/A Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 11 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 www.ti.com Table 4-1. Pin Descriptions (continued) NO. PINS NAME 10 11 12 13 14 15 16 17 18 19 20 VIN_IO1 FLASH_SPI_CLK FLASH_SPI_DOUT FLASH_SPI_DIN FLASH_SPI_CS GPIO22 TDI TDO GPIO28 TCK TMS 21(1) SOP2 WLAN_XTAL_N WLAN_XTAL_P VDD_PLL LDO_IN2 NC NC NC ANTSEL1 ANTSEL2 RF_BG nRESET VDD_PA_IN SOP1 SOP0 LDO_IN1 22 23 24 25 26 27 28 29(2) 30(2) 31 32 33 34 35 36 37 38 TYPE Power O O I O I/O I/O I/O I/O I/O I/O I Analog Analog Power Power O O RF I Power I I Power DESCRIPTION I/O power supply (same as battery voltage) Serial flash interface: SPI clock Serial flash interface: SPI data out Serial flash interface: SPI data in Serial flash interface: SPI chip select General-purpose input or output JTAG interface: data input JTAG interface: data output General-purpose input or output JTAG/SWD interface: clock JTAG/SWD interface: mode select or SWDIO Configuration sense-on-power 2 40-MHz crystal. Pulldown if external TCXO is used. 40-MHz crystal or TCXO clock input Internal analog voltage Internal analog RF supply from analog DC/DC output No connect Reserved Reserved Antenna selection control Antenna selection control RF BG band: 2.4-GHz TX, RX Master chip reset input. Active low input. Internal RF power amplifier (PA) input from PA DC/DC output Configuration sense-on-power 1 Configuration sense-on-power 0 Internal Analog RF supply from analog DC/DC output Analog DC/DC supply input
(same as battery voltage [VBAT]) Internal Analog DC/DC converter switching node SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAG N/A N/A N/A N/A N/A No No Yes No No No No N/A N/A N/A N/A N/A N/A N/A No No N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A No No No No No No No N/A N/A N/A N/A N/A N/A N/A User configuration not required (3) User configuration not required (3) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A No Muxed with JTAG TDI Muxed with JTAG TDO No Muxed with JTAG/
SWD-TCK Muxed with JTAG/
SWD-TMSC No N/A N/A N/A N/A N/A N/A N/A No No N/A N/A N/A N/A N/A N/A N/A N/A VIN_DCDC_ANA DCDC_ANA_SW Power
(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(2) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities.
(3) Device firmware automatically enables the digital path during ROM boot. 12 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Copyright 20162018, Texas Instruments Incorporated www.ti.com NO. PINS NAME 39 40 41 42 43 44 VIN_DCDC_PA DCDC_PA_SW_P DCDC_PA_SW_N DCDC_PA_OUT DCDC_DIG_SW VIN_DCDC_DIG 45(4) DCDC_ANA2_SW_P 46 47 48 49 50 51 DCDC_ANA2_SW_N VDD_ANA2 VDD_ANA1 VDD_RAM GPIO0 RTC_XTAL_P 53 54 55 56 GPIO30 VIN_IO2 GPIO1 VDD_DIG2 57(7) GPIO2 58(7) GPIO3 59(7) GPIO4 60(7) GPIO5 CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-1. Pin Descriptions (continued) TYPE Power Power Power Power Power Power I/O Power Power Power Power DESCRIPTION PA DC/DC converter input supply
(same as battery voltage [VBAT]) Internal PA DC/DC converter
+ve switching node Internal PA DC/DC converter ve switching node Internal PA buck DC/DC converter output Internal Digital DC/DC converter switching node Digital DC/DC converter supply input (same as battery voltage
[VBAT]) Analog2 DC/DC converter
+ve switching node Internal Analog2 DC/DC converter ve switching node Internal Analog2 DC/DC output Internal Analog1 power supply fed by analog2 DC/DC converter output Internal SRAM LDO output I/O General-purpose input or output Analog 32.768-kHz XTAL_P or external CMOS level clock input I/O General-purpose input or output Power I/O Power I/O I/O I/O I/O device supply voltage (VBAT) General-purpose input or output internal digital core voltage Analog input (up to 1.5-V ) or general-purpose input or output Analog input (up to 1.5-V ) or general-purpose input or output Analog input (up to 1.5-V ) or general-purpose input or output Analog input (up to 1.5 V) or general-purpose input or output General-purpose input or output General-purpose input or output General-purpose input or output SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAG N/A N/A N/A N/A N/A N/A No N/A N/A N/A N/A No N/A N/A No N/A No N/A Yes No Yes No N/A N/A N/A N/A N/A N/A User configuration not required (3) N/A N/A N/A N/A User configuration not required (3) N/A User configuration not required (3)(6) User configuration not required (3) N/A No N/A See (8) See (8) See (8) See (8) N/A N/A N/A N/A N/A N/A No N/A N/A N/A N/A No N/A No No N/A No N/A No No No No GPIO6 GPIO7 GPIO8 61 62 63
(4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the I/O I/O I/O No No No No No No No No No CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to automatically detect this configuration, a 100-k pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.
(6) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-k resistor.
(7) This pin is shared by the ADC inputs and digital I/O pad cells.
(8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch. Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 13 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF 52(5) RTC_XTAL_N Analog 32.768-kHz XTAL_N CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 www.ti.com Table 4-1. Pin Descriptions (continued) PINS NAME GPIO9 NO. 64 GND_TAB TYPE I/O DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAG General-purpose input or output Thermal pad and electrical ground No N/A No N/A No N/A Table 4-2. Pin Attributes PIN NO. 1 2 3 4 5 SIGNAL NAME(1) GPIO10 (PN) I2C_SCL GT_PWM06 UART1_TX SDCARD_CLK GT_CCP01 GPIO11 (PN) I2C_SDA GT_PWM07 pXCLK (XVCLK) SDCARD_CMD UART1_RX GT_CCP02 McAFSX GPIO12 (PN) McACLK pVS (VSYNC) I2C_SCL UART0_TX GT_CCP03 GPIO13 (PN) I2C_SDA pHS (HSYNC) UART0_RX GT_CCP04 GPIO14 (PN) I2C_SCL GSPI_CLK pDATA8 (CAM_D4) GT_CCP05 SIGNAL TYPE(2) PIN MUX ENCODING I/O I/O I/O I/O I/O 0 1 3 7 6 12 0 1 3 4 6 7 12 13 0 3 4 5 7 12 0 5 4 7 12 0 5 7 4 12 PAD STATES LPDS(3) Hib(4) nRESET = 0 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 0 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 0 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z SIGNAL DIRECTION I/O I/O (open drain) O O O I I/O I/O (open drain) O O I/O (open drain) I I O I/O O I I/O (open drain) O I I/O I/O (open drain) I I I I/O I/O (open drain) I/O I I
(1) Signals names with (PN) denote the default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need. configuration), according to the need. 14 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-2. Pin Attributes (continued) PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING GPIO15 (PN) I2C_SDA GSPI_MISO pDATA9 (CAM_D5) GT_CCP06 SDCARD_DATA0 GPIO16 (PN) GSPI_MOSI pDATA10 (CAM_D6) UART1_TX GT_CCP07 SDCARD_CLK GPIO17 (PN) UART1_RX GSPI_CS pDATA11 (CAM_D7) SDCARD_CMD VDD_DIG1 (PN) VIN_IO1 FLASH_SPI_CLK FLASH_SPI_DOUT FLASH_SPI_DIN FLASH_SPI_CS GPIO22 (PN) McAFSX GT_CCP04 TDI (PN) GPIO23 UART1_TX I2C_SCL TDO (PN) GPIO24 PWM0 UART1_RX I2C_SDA GT_CCP06 McAFSX GPIO28 TCK (PN) GT_PWM03 6 7 8 9 10 11 12 13 14 15 16 17 18 19 I/O I/O I/O O O I O I/O O I I/O I/O I/O I/O 0 5 7 4 13 8 0 7 4 5 13 8 0 5 7 4 8 N/A N/A N/A N/A N/A N/A 0 7 5 1 0 2 9 1 0 5 2 9 4 6 0 1 8 I/O I I I/O I/O I/O I O I O I/O I I/O I I/O N/A N/A O O I O I/O O I I I/O O PAD STATES LPDS(3) Hib(4) nRESET = 0 SIGNAL DIRECTION I/O I/O (open drain) Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive 0 Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive N/A N/A Hi-Z, Pull, Drive(5) Hi-Z, Pull, Drive(5) Hi-Z, Pull, Drive(5) 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 N/A N/A Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive I/O (open drain) Hi-Z, Pull, Drive O I/O O I I/O (open drain) I O I/O I O Hi-Z, Pull, Drive Driven high in SWD;
driven low in 4-wire JTAG Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z N/A N/A Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins. Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 15 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-2. Pin Attributes (continued) SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION LPDS(3) PIN NO. 20 21(6) TMS (PN) GPIO29 GPIO25 GT_PWM02 McAFSX TCXO_EN SOP2 (PN) 22 WLAN_XTAL_N 23 WLAN_XTAL_P 24 25 26 27 28 VDD_PLL LDO_IN2 NC NC NC 29(9) ANTSEL1 30(9) ANTSEL2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 RF_BG nRESET VDD_PA_IN SOP1 SOP0 LDO_IN1 VIN_DCDC_ANA DCDC_ANA_SW VIN_DCDC_PA DCDC_PA_SW_P DCDC_PA_SW_N DCDC_PA_OUT DCDC_DIG_SW VIN_DCDC_DIG I/O O O O 1 0 0 9 2 N/A
(see (7)) N/A
(see (8)) N/A
(see (7)) N/A N/A N/A N/A N/A N/A 0 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A I/O Hi-Z, Pull, Drive O O O O I N/A N/A N/A N/A N/A N/A N/A O O N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 0 Hi-Z, Pull, Drive N/A N/A N/A N/A N/A N/A N/A Hi-Z, Pull, Drive Hi-Z, Pull, Drive N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A www.ti.com PAD STATES Hib(4) Hi-Z, Pull, Drive nRESET = 0 Hi-Z Driven low Hi-Z N/A N/A N/A N/A N/A N/A N/A Hi-Z, Pull, Drive Hi-Z, Pull, Drive N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Hi-Z Hi-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) For details on proper use, see Section 4.5.
(8) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(9) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities. 16 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 Table 4-2. Pin Attributes (continued) GPIO31 UART0_RX McAFSX UART1_RX McAXR0 GSPI_CLK DCDC_ANA2_SW_P
(PN) DCDC_ANA2_SW_N VDD_ANA2 VDD_ANA1 VDD_RAM GPIO0 (PN) UART0_CTS McAXR1 GT_CCP00 GSPI_CS UART1_RTS UART0_RTS McAXR0 RTC_XTAL_P RTC_XTAL_N (PN) GPIO32 McACLK McAXR0 UART0_RTS GSPI_MOSI GPIO30 (PN) UART0_TX McACLK McAFSX GT_CCP05 GSPI_MISO VIN_IO2 GPIO1 (PN) UART0_TX pCLK (PIXCLK) UART1_TX GT_CCP01 VDD_DIG2 45(10) 46 47 48 49 50 51 52(11) 53 54 55 56 I/O I/O O I/O I/O 0 9 12 2 6 7 N/A
(see (7)) N/A N/A N/A N/A 0 12 6 7 9 10 3 4 N/A N/A 0 2 4 6 8 0 9 2 3 4 7 N/A 0 3 4 6 7 N/A I/O I O I I/O I/O N/A N/A N/A N/A N/A I/O I I/O I I/O O O I/O N/A N/A O O O O O I/O O O O I I/O N/A I/O O I O I N/A Hi-Z Hi-Z Hi-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Hi-Z, Pull, Drive Hi-Z N/A N/A Hi-Z, Pull, Drive Hi-Z N/A N/A N/A N/A N/A Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 1 Hi-Z, Pull, Drive N/A N/A Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive N/A N/A Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive N/A N/A Hi-Z N/A Hi-Z N/A
(10) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100-k pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions. Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 17 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 www.ti.com Table 4-2. Pin Attributes (continued) SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) 57(12) ADC_CH0 GPIO2 (PN) UART0_RX UART1_RX GT_CCP02 ADC_CH1 58(12) GPIO3 (PN) UART1_TX pDATA7 (CAM_D3) ADC_CH2 59(12) GPIO4 (PN) UART1_RX pDATA6 (CAM_D2) 60(12) 61 62 63 64 ADC_CH3 GPIO5 (PN) pDATA5 (CAM_D1) McAXR1 GT_CCP05 GPIO6 (PN) UART0_RTS pDATA4 (CAM_D0) UART1_CTS UART0_CTS GT_CCP06 GPIO7 (PN) McACLKX UART1_RTS UART0_RTS UART0_TX GPIO8 (PN) SDCARD_IRQ McAFSX GT_CCP06 GPIO9 (PN) GT_PWM05 SDCARD_DATA0 McAXR0 GT_CCP00 Analog input
(up to 1.5 V) or digital I/O Analog input
(up to 1.5 V) or digital I/O Analog input
(up to 1.5 V) or digital I/O Analog input
(up to 1.5 V) or digital I/O I/O I/O I/O I/O PIN MUX ENCODING N/A
(see (7)) 0 3 6 7 N/A
(see (7)) 0 6 4 N/A
(see (7)) 0 6 4 N/A
(see (7)) 0 4 6 7 0 5 4 3 6 7 0 13 3 10 11 0 6 7 12 0 3 6 7 12 N/A I I/O I I I I I/O O I I I/O I I I I/O I I/O I I/O O I I I I I/O O O O O I/O I O I I/O O I/O I/O I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z, Pull, Drive 1 Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z Hi-Z Hi-Z N/A GND_TAB
(12) This pin is shared by the ADC inputs and digital I/O pad cells. N/A N/A N/A 18 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 NOTE The ADC inputs are tolerant up to 1.8 V (see Table 5-18 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For more information about drive strength and reset states for analog-digital multiplexed pins, see Section 4.5. I/Os corresponding to the desired ADC channel (that the digital 4.3 Signal Descriptions FUNCTION SIGNAL NAME ADC Antenna selection Clock JTAG / SWD I2C ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ANTSEL1 ANTSEL2 TCX0_EN WLAN_XTAL_N WLAN_XTAL_P RTC_XTAL_P RTC_XTAL_N TDI TDO TCK TMS I2C_SCL I2C_SDA Table 4-3. Signal Descriptions PIN TYPE I/O I/O I/O I/O O O O I/O I/O I/O I/O SIGNAL DIRECTION DESCRIPTION I I I I O O O I O I I/O ADC channel 0 input (maximum of 1.5 V) ADC channel 1 input (maximum of 1.5 V) ADC channel 2 input (maximum of 1.5 V) ADC channel 3 input (maximum of 1.5 V) Antenna selection control 1 Antenna selection control 2 Enable to optional external 40-MHz TCXO 40-MHz crystal; pull down if external TCXO is used 40-MHz crystal or TCXO clock input Connect 32.768-kHz crystal or force external CMOS level clock Connect 32.768-kHz crystal or connect 100-k resistor to supply voltage JTAG TDI. Reset default pinout. JTAG TDO. Reset default pinout. JTAG/SWD TCK. Reset default pinout. JTAG/SWD TMS. Reset default pinout. I/O I/O (open drain) I2C clock data I/O I/O (open drain) I2C data PIN NO. 57 58 59 60 29 30 21 22 23 51 52 16 17 19 20 1 3 5 16 2 4 6 17 Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 19 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME Timers GT_PWM06 GT_CCP01 GT_PWM07 GT_CCP02 GT_CCP03 GT_CCP04 GT_CCP05 GT_CCP06 GT_CCP07 PWM0 GT_PWM03 GT_PWM02 GT_CCP00 GT_CCP05 GT_CCP01 GT_CCP02 GT_CCP05 GT_PWM05 PIN NO. 1 1 2 2 3 4 15 5 6 17 61 63 7 17 19 21 50 64 53 55 57 60 64 PIN TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I I/O SIGNAL DIRECTION DESCRIPTION O I O I I I I I I I I I I O O O I I I I I I O Pulse-width modulated O/P Timer capture port Pulse-width modulated O/P Timer capture port Pulse-width modulated output Timer capture port Pulse-width modulated output 20 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com FUNCTION SIGNAL NAME GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO22 GPIO23 GPIO24 GPIO28 GPIO29 GPIO25 GPIO31 GPIO0 GPIO32 GPIO30 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 McAFSX McACLK McAXR1 McAXR0 McACLKX GPIO McASP I2S or PCM CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-3. Signal Descriptions (continued) PIN NO. 1 2 3 4 5 6 7 8 15 16 17 18 20 21 45 50 52 53 55 57 58 59 60 61 62 63 64 2 15 17 21 45 53 63 3 52 53 50 60 45 50 52 64 62 PIN TYPE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I I/O I/O O I/O I/O SIGNAL DIRECTION DESCRIPTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose input or output General-purpose output only General-purpose input or output General-purpose output only General-purpose input or output O I2S audio port frame sync O O O I/O I/O I/O I/O O I/O O I2S audio port clock output I2S audio port data 1 (RX and TX) I2S audio port data 0 (RX and TX) I2S audio port data (only output mode is supported on pin 52) I2S audio port data (RX and TX) I2S audio port clock Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 21 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME Multimedia card
(MMC or SD) Parallel interface
(8-bit ) Power SDCARD_CLK SDCARD_CMD SDCARD_DATA0 SDCARD_IRQ pXCLK (XVCLK) pVS (VSYNC) pHS (HSYNC) pDATA8 (CAM_D4) pDATA9 (CAM_D5) pDATA10 (CAM_D6) pDATA11 (CAM_D7) pCLK (PIXCLK) pDATA7 (CAM_D3) pDATA6 (CAM_D2) pDATA5 (CAM_D1) pDATA4 (CAM_D0) VDD_DIG1 VIN_IO1 VDD_PLL LDO_IN2 VDD_PA_IN LDO_IN1 VIN_DCDC_ANA DCDC_ANA_SW VIN_DCDC_PA DCDC_PA_SW_P DCDC_PA_SW_N DCDC_PA_OUT DCDC_DIG_SW VIN_DCDC_DIG DCDC_ANA2_SW_P DCDC_ANA2_SW_N VDD_ANA2 VDD_ANA1 VDD_RAM VIN_IO2 VDD_DIG2 PIN NO. 1 7 2 8 6 64 63 2 3 4 5 6 7 8 55 58 59 60 61 9 10 24 25 33 36 37 38 39 40 41 42 43 44 45 46 47 48 49 54 56 PIN TYPE SIGNAL DIRECTION DESCRIPTION I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O SD card clock data I/O (open drain) I/O I/O I O I I I I I I I I I I I SD card command line SD card data Interrupt from SD card (future support) Free clock to parallel camera Parallel camera vertical sync Parallel camera horizontal sync Parallel camera data bit 4 Parallel camera data bit 5 Parallel camera data bit 6 Parallel camera data bit 7 Pixel clock from parallel camera sensor Parallel camera data bit 3 Parallel camera data bit 2 Parallel camera data bit 1 Parallel camera data bit 0 Internal digital core voltage Device supply voltage (VBAT) Internal analog voltage Internal analog RF supply from analog DC/DC output Internal PA supply voltage from PA DC/DC output Internal analog RF supply from analog DC/DC output Analog DC/DC input (connected to device input supply
[VBAT]) Internal analog DC/DC switching node PA DC/DC input (connected to device input supply
[VBAT]) Internal PA DC/DC switching node Internal PA buck converter output Internal digital DC/DC switching node Digital DC/DC input (connected to device input supply
[VBAT]) Analog to DC/DC converter +ve switching node Internal analog to DC/DC converter ve switching node Internal analog to DC/DC output Internal analog supply fed by ANA2 DC/DC output Internal SRAM LDO output Device supply voltage (VBAT) Internal digital core voltage 22 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-3. Signal Descriptions (continued) SIGNAL DIRECTION DESCRIPTION www.ti.com FUNCTION SIGNAL NAME SPI FLASH SPI GSPI_CLK GSPI_MISO GSPI_CS GSPI_MOSI FLASH_SPI_CLK FLASH_SPI_DOUT FLASH_SPI_DIN FLASH_SPI_CS UART1_TX UART1_RX UART1_RTS UART1_CTS UART0_TX UART0_RX UART0_CTS UART0_RTS SOP2 SOP1 SOP0 nRESET RF_BG UART Sense-on-
Power PIN NO. 5 45 6 53 8 50 7 52 11 12 13 14 1 7 16 55 58 2 8 17 45 57 59 50 62 61 3 53 55 62 4 45 57 50 61 50 52 61 62 21(1) 34 35 32 31 PIN TYPE I/O I/O I/O I/O I/O I/O I/O O O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O O I/O I/O I/O I/O I/O I/O I/O O O O I O O O O O O I I I I I I O O I O O O O I I I I I O O O O I General SPI clock General SPI MISO General SPI chip select General SPI MOSI Clock to SPI serial flash (fixed default) Data to SPI serial flash (fixed default) Data from SPI serial flash (fixed default) Device select to SPI serial flash (fixed default) UART1 TX data UART1 RX data UART1 request-to-send (active low) UART1 clear-to-send (active low) UART0 TX data UART0 RX data UART0 clear-to-send input (active low) UART0 request-to-send (active low) Sense-on-power 2 Configuration sense-on-power 1 Configuration sense-on-power 0 Global master device reset (active low) WLAN analog RF 802.11 b/g bands Reset RF
(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 23 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 4.4 Pin Multiplexing REGISTER ADDRESS REGISTER NAME PIN ANALOG OR SPECIAL FUNCTION JTAG 0 1 www.ti.com Table 4-4. Pin Multiplexing DIGITAL FUNCTION (XXX FIELD ENCODING)(1) GPIO_PAD_CONFIG_10 GPIO_PAD_CONFIG_11 GPIO_PAD_CONFIG_12 GPIO_PAD_CONFIG_13 GPIO_PAD_CONFIG_14 GPIO_PAD_CONFIG_15 GPIO_PAD_CONFIG_16 GPIO_PAD_CONFIG_17 GPIO_PAD_CONFIG_22 GPIO_PAD_CONFIG_23 GPIO_PAD_CONFIG_24 GPIO_PAD_CONFIG_40 GPIO_PAD_CONFIG_28 GPIO_PAD_CONFIG_29 1 2 3 4 5 6 7 8 15 16 17 18 19 20 GPIO10 I2C_SCL GPIO11 I2C_SDA GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO22 2 Muxed with JTAG Muxed with JTAG TDO GPIO23 TDI UART1_TX GPIO24 TDO UART1_RX GPIO28 Muxed with JTAG or SWD and TCK Muxed with JTAG or SWD and TMSC TCK GPIO29 TMS GPIO_PAD_CONFIG_25 21(2) GPIO_PAD_CONFIG_26 GPIO_PAD_CONFIG_27 29 30 GPIO25 ANTSEL1(3) ANTSEL2(3) McAFSX 6 7 3 GT_PWM06 GT_PWM07 McACLK 4 pXCLK
(XVCLK) pVS
(VSYNC) 5 I2C_SCL SDCARD_ CLK SDCARD_ CMD pHS I2C_SDA I2C_SCL
(HSYNC) pDATA8
(CAM_D4) pDATA9
(CAM_D5) pDATA10
(CAM_D6) UART1_TX pDATA11
(CAM_D7) UART1_RX I2C_SDA GT_CCP04 GT_CCP06 PWM0 McAFSX 8 SDCARD_ DATA0 SDCARD_ CLK SDCARD_ CMD GT_ PWM03 9 I2C_SCL I2C_SDA GT_ PWM02 10 11 12 GT_CCP01 13 GT_CCP02 MCAFSX GT_CCP03 GT_CCP04 GT_CCP05 GT_CCP06 GT_CCP07 UART1_TX UART1_RX UART0_TX UART0_RX GSPI_CLK GSPI_ MISO GSPI_ MOSI GSPI_CS McAFSX 0x4402 E0C8 0x4402 E0CC 0x4402 E0D0 0x4402 E0D4 0x4402 E0D8 0x4402 E0DC 0x4402 E0E0 0x4402 E0E4 0x4402 E0F8 0x4402 E0FC 0x4402 E100 0x4402 E140 0x4402 E110 0x4402 E114 0x4402 E104 0x4402 E108 0x4402 E10C
(1) Pin mux encodings with (RD) denote the default encoding after reset release.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need. 24 Terminal Configuration and Functions Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com REGISTER ADDRESS REGISTER NAME PIN ANALOG OR SPECIAL FUNCTION JTAG 0 0x4402 E11C 0x4402 E0A0 0x4402 E120 0x4402 E118 0x4402 E0A4 0x4402 E0A8 0x4402 E0AC 0x4402 E0B0 0x4402 E0B4 0x4402 E0B8 0x4402 E0BC 0x4402 E0C0 0x4402 E0C4 GPIO_PAD_CONFIG_31 GPIO_PAD_CONFIG_0 GPIO_PAD_CONFIG_32 GPIO_PAD_CONFIG_30 GPIO_PAD_CONFIG_1 GPIO_PAD_CONFIG_2 GPIO_PAD_CONFIG_3 GPIO_PAD_CONFIG_4 GPIO_PAD_CONFIG_5 GPIO_PAD_CONFIG_6 GPIO_PAD_CONFIG_7 GPIO_PAD_CONFIG_8 GPIO_PAD_CONFIG_9 45 50 52 53 55 57 58 59 60 61 62 63 64
-
-
GPIO31 GPIO0 GPIO32 GPIO30 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 Table 4-4. Pin Multiplexing (continued) DIGITAL FUNCTION (XXX FIELD ENCODING)(1) 1 2 UART1_RX 3 4 UART0_ RTS McAXR0 McACLK McAXR0 McACLK McAFSX GT_CCP05 UART0_TX pCLK
(PIXCLK) UART0_RX UART1_ CTS UART1_ RTS GT_PWM05 pDATA7
(CAM_D3) pDATA6
(CAM_D2) pDATA5
(CAM_D1) pDATA4
(CAM_D0) 5 6 7 McAXR0 GSPI_CLK McAXR1 GT_CCP00 UART0 _ RTS GSPI_ MISO UART1_TX GT_CCP01 UART1_RX GT_CCP02 UART1_TX UART1_RX McAXR1 GT_CCP05 UART0_ RTS UART0_ CTS GT_CCP06 SDCARD_ IRQ SDCARD_ DATA0 McAFSX McAXR0 8 9 UART0_RX 10 GSPI_CS UART1_ RTS GSPI_ MOSI UART0_TX 11 12 McAFSX UART0_ CTS 13 McACLKX UART0_ RTS UART0_TX GT_CCP06 GT_CCP00 Copyright 20162018, Texas Instruments Incorporated Terminal Configuration and Functions 25 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 5 Specifications www.ti.com All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over process and voltage, unless otherwise indicated. 5.1 Absolute Maximum Ratings All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process, voltage, and operating free-air temperature range (unless otherwise noted)(1)(2) Pins: 10, 54 Pins: 37, 39, 44 VBAT and VIO VIO VBAT (differential) Digital inputs RF pins Analog pins, crystal Operating temperature, TA Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings MAX 3.8 VBAT and VIO should be tied together VIO + 0.5 2.1 2.1 85 125 0.5 0.5 0.5 40 55 Pins: 22, 23, 51, 52 V V V C C MIN 0.5 only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. UNIT V V
(2) All voltage values are with respect to VSS, unless otherwise noted. 5.2 ESD Ratings VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged device model (CDM), per JEDEC specification JESD22-C101(2) VALUE 2000 500 UNIT V
(1)
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Power-On Hours (POH) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. TA up to 85C(1)
(1) The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device can be in any other state. OPERATING CONDITION POWER-ON HOURS [POH]
(hours) 87,600 28 Specifications Copyright 20162018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF www.ti.com CC3220R, CC3220S, CC3220SF SWAS035B SEPTEMBER 2016REVISED NOVEMBER 2018 5.6 Current Consumption Summary (CC3220SF) TA = 25C, VBAT = 3.6 V PARAMETER TEST CONDITIONS(1) (2) MIN TX power level = maximum TX power level = maximum 4 TX power level = maximum TX power level = maximum 4 TX power level = maximum TX power level = maximum 4 TX power level = maximum TX power level = maximum 4 TX power level = maximum TX power level = maximum 4 TX power level = maximum TX power level = maximum 4 TX power level = 0 TX power level = 4 TX power level = 0 TX power level = 4 TX power level = 0 TX power level = 4 1 DSSS 6 OFDM 54 OFDM 1 DSSS 54 OFDM 1 DSSS 6 OFDM 54 OFDM 1 DSSS 54 OFDM 1 DSSS 6 OFDM 54 OFDM 1 DSSS 54 OFDM 120 A at 64KB 135 A at 256KB MCU ACTIVE NWP ACTIVE TX RX NWP idle connected(3) MCU SLEEP NWP ACTIVE TX RX NWP idle connected(3) NWP active MCU LPDS TX RX NWP LPDS(4) NWP idle connected(3) MCU SHUTDOWN MCU HIBERNATE MCU shutdown MCU hibernate Peak calibration current(5) VBAT = 3.6 V VBAT = 3.3 V VBAT = 2.1 V VBAT = 1.85 V mA TYP MAX UNIT 286 202 255 192 232 174 74 74 25.2 282 198 251 188 228 170 70 70 21.2 266 184 242 176 217 154 53 53 mA mA 135 710 1 4.5 420 450 670 700 A mA
(1) TX power level = 0 implies maximum power (see Figure 5-1, Figure 5-2, and Figure 5-3). TX power level = 4 implies output power backed off approximately 4 dB.
(2) The CC3220x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
(3) DTIM = 1
(4) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 A.
(5) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly, typically when coming out of HIBERNATE and only if temperature has changed by more than 20C. The calibration event can be controlled by a configuration file in the serial Flash.. Copyright 20162018, Texas Instruments Incorporated Specifications 31 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Federal Communications Commission (FCC) Interference Statement The modular transmitter is only FCC authorized for the specific rule part (FCC Part15.247) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generate, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. OEM/Host integrator is responsible for complying with the instructions and requirements for each transmitter they choose to integrate into a host product. RF exposure warning This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This product may not be collocated or operated in conjunction with any other antenna or transmitter. This equipment must be installed and operated in accordance with provided instructions and the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20cm from all persons and must not be collocated or operating in conjunction with any other antenna or transmitter. Additional text needed for the host product manufacturer to provide to end users in their end-product manuals. Industry Canada (IC) CAN ICES-3 (B)/NMB-3(B) This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and
(2) this device must accept any interference received, including interference that may cause undesired operation. Cetappareilestconforme la norme RSS d'Industrie Canada. Son fonctionnementestsujet aux deux conditions suivantes:
(1) ledispositif ne doit pas produire de brouillageprjudiciable, et
(2) cedispositifdoit accepter tout brouillagereu, y compris un brouillage susceptible de provoquer un fonctionnementindsirable. IMPORTANT NOTE:
Radiation Exposure Statement:
This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator and your body. Dclarationd'exposition aux radiations:
Cetquipementestconforme aux limitesd'exposition aux rayonnements IC tablies pour unenvironnement non contrl. Cetquipementdoittreinstalletutilis avec un minimum de 20cm de distance entre la source de rayonnement et votre corps. OEM Integration Instructions This device is intended only for OEM integrators under the following conditions
(1). This module limit can be used to install in the host below. Product name: Wireless Network Control Host model: Wireless Network Control
(2). The antenna(s) used for this transmitter must be installed to the provided separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter.
(3). The module shall be only used with the integral antenna(s) that has been originally tested and certified with this module. As long as 3 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirement with this module installed (for example, digital device emission, PC peripheral requirements, etc.) IMPORTANT NOTE In the event that these conditions cannot be met (for example certain laptop configuration or co-location with another transmitter), then the FCC authorization for this module in combination with the host equipment is no longer considered valid and the FCC ID of the module cannot be used on the final product. In these and circumstance, the OEM integrator will be responsible for re-evaluating. The end product (including the transmitter) and obtaining a separate FCC authorization. The final end product must be labeled in a visible area with the following:
Contains Transmitter Module FCC ID: 2ANOT-204890 or Contains FCC ID: 2ANOT-204890. Antenna Specification:
Antenna Type Manufacturer Dipole Antenna Pulse Frequency Range Maximum Peak Antenna
(MHz) 2400 - 2500 Gain(dBi) 2.0 Note: The device didnt support beam-forming technology and Cyclic Delay Diversity (CDD) technology, and the transmit signals are uncorrected, so no add array gain to the band power and band PSD. IMPORTANT NOTE This Wireless Module (IC: 23166-204890) has been approved by Industry Canada to operate with the antenna types listed below with the maximum permissible gain indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. The Host Marketing Name(HMN) must be displayed (according to e-labelling requirements) or indicated at any location on the exterior of the host product or product packaging or product literature, which shall be available with the host product or online. The host product shall be properly labelled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labelled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows: Contains IC: 23166-204890. Antenna Specification:
Antenna Type Manufacturer Dipole Antenna Pulse Frequency Range Maximum Peak Antenna
(MHz) 2400 - 2500 Gain(dBi) 2.0 Note: The device didnt support beam-forming technology and Cyclic Delay Diversity (CDD) technology, and the transmit signals are uncorrected, so no add array gain to the band power and band PSD.
This product uses the FCC Data API but is not endorsed or certified by the FCC