FCC ID: VLV867029165569 Bluetooth Audio Module

DIGISINE ENERGYTECH BDP-8670 DATASHEET Oct,1Feb 2017 Version1.1 Datasheet by Yu-Hsun Lin. Author Yu-Hsun Lin Reversion History Data 2017-10-1 Version 1.1 Description First Release 2 CONTENT 1. INTRODUCTION..... .... ...5 1.1 Description..5 1.2 Features..5 1.3 Applications..5 1.4 Block Diagram6 2.GENERAL SPECIFICATION..... ..7 3.PHYSICAL CHARACTERISTIC..................................... ......8 3.1 Pin Configurations..................................................... .... ....9 4.PHSICAL INTERFACE................................................ .... .... 12 4.1 USB............................................................................. .... .... ....12 4.2 UART............................................................................. .... .... .12 4.3 Programming and Debug Interface........ .. ....... ..... .. .. .. .. 13 4.4 Analogue I/O Ports......................................................................13 4.5 LED Drivers........ .. ....... ..... .. .. .. .. .. .. .. .. .. .. .. .... ..13 4.6 RF Port........ .. ....... ..... .. .. .. .. .. .. .. .. .. .. .. .... .... ...13 4.7Audio Code Interface........ ....... ... .. .. .. .. .. .. .. .. .. .. ...13 4.7.1 ADC........ ....... ... .. .. .. .. .. . .. . .. . .. . .. .. .. .. .. ... 14 4.7.2 ADC Sample Rate Selection........ ..... ... .. . .. .. .. .. .. ... 14 4.7.3 ADC Digital Gain........ ......... ... .. . .. .... .. .. ... .. .. ... .14 4.7.4 DAC Sample Rate Selection........ ......... ... . .. .. .... .. ... .14 4.7.4 DAC Sample Rate Selection........ ......... ... ..... .. .... .. ... .15 4.7.5 DAC Digital Gain........ ......... ... .. . .. ...... .. ..... .. .. ... .15 4.7.6 DAC Analogue Gain........ ......... ... .. . .... .... .. .. . ...... .16 4.7.7 IEC 60958 Interface........ ......... ... .. . .... ..... .. .. . ...... .16 4.7.8 Microphone Input....... ......... ... .. . .... ..... .. .. .. ...... .16 4.7.8 Microphone Input....... ......... ... .. . .... ..... .. .. .. ...... .16 4.7.9 Digital Microphone Inputs...... ......... ... .. . .... .. .. ...... .16 3 4.7.10 Line input...... .... ....... .............. ... .. . .... .. .. ....... .16 4.7.11 Audio Output Stage...... .... ...... ..... .. ... .. . ... .. .. .16 4.7.12 PCM Interface...... .... ...... .... .. ... .. . ... .. .. .. .17 4.7.13 Digital Audio Interface(I2S). .... .... ... .. .. . . ... .. . . .17 4.8 Reset........ .. ....... ..... .. .. .. .. .. .. .. .. .. .. ... .... ...... ....17 4.9 Battery Charger........ .. ....... ..... ... .. .. .. ... .. .. .. ... ..18 4.10VREG_EN... ........ ...... .. ....... ..... .. .. .. .. .. .. .. .. .. .. ..18 5.ELECTRICAL CHARACTERISTICS..... ... ....... ..... .. ..19 5.1 Absolute maximum ratings............ .............................. ..... ...19 5.2 Recommended operating conditions............ ..............................19 5.3 Battery Charger............................................. ..............................20 5.4 RF characteristics............................................. ..........................20 6.RECOMMEND PCB LAYOUT PATTERN...........................21 7.RECOMMEND SOLDER PROFILE.......................................22 8. STATEMENT.......................................................................................23 4 1. INTRODUCTION 1.1 DESCRIPTION BDP-8670 is a Bluetooth sub-system using CSR8670 chipset from Cambrige Silicon Radio. The BlueCore CSR8670 BGA consumer audio platform for wired and wireless applications integrates an ultra-low-power DSP and application processor with embedded flash memory, a high-performance stereo codec, a power management subsystem, LED and LCD drivers in a SOC IC. BDP-8670 is slim and light so the designers can have better flexibilities for the product shapes. 1.2 FEATURES Bluetooth V4.2 Compliant. USB and UART Host Interface. Integrated Switched-Mode Regulator. Integrated Battery Charger. Integrated Microphone bias. Integrated LED Driver. Built in 16-bit Stereo Codec- 95dB SNR for DAC ; Music Enhancements: SBC,MP3,and AAC+, Fast stream code,AtpX,5-band EQ,3D stereo separation and so on. Multi-Configurable I2S, PCM or SPDIF Interface. Factory configurable to either 1.8V or 3.3V supply. 16Mb internal flash memory (64-bit wide, 45ns); optional support for 64Mb of external SPI flash. Supported Bluetooth Profile: HSP, HFP, A2DP, AVRCP, PBAP, MAP, SPP, iAP. Enhanced Audibility and Noise Cancellation. Class2more than 10 Meters. Low Power Consumption. Temperature range from -40C to +85C. Weight: 0.8g. 1.3 APPLICATIONS Wired or wireless Stereo headset or headphones Wired or wireless sound bars Smart remote controllers Hands free car kits Wearable audio with sensors 5 1.4 BLOCK DIAGRAM Figure1: Block diagram of BDP-8670 6 2. GENERAL SPECIFICATIONS Operation Freqency Band Compliance Max. output power Channels Modulation Type USB specification Audio interface Dimension 2.400GHz-2.4835GHz unlicensed ISM band Bluetooth specification,version4.2 10dBm(Max) 79 GFSK(1 Mbps) USB specification, version 2.0 (full- speed) Analogue and audio in Analogue and Digital audio out 15mm x 11mm x 2.8mm. 7 3. PHYSICAL CHARACTERISTIC Figure2: BDP-8670 8 3.1 PIN CONFIGURATIONS Figure3: BDP-8670 pin description PIN NO. NAME 1 AIO0 TYPE Bidirectional 2 3 4 AIO1 Bidirectional GND PCM_OUT Bidirectional GND DESCRIPTION Analogue programmable input /

output line 0. Analogue programmable input /

output line 1. Ground Synchronous Data Output, 9 REMARK PCM_SYN C with weak pull-

down Bidirectional with weak pull-

down PCM_CLK Bidirectional PCM_IN GND SPI_CLK with weak pull-

down Bidirectional with strong pull-

down GND Input with weak pull down Alternative function PIO18 Synchronous Data Sync, Alternative function PIO19 Synchronous Data Clock, Alternative function PIO20 Synchronous Data Input, Alternative function PIO17 Ground Serial Peripheral Interface Clock SPI_MISO Output with SPI_CSB weak pull down Input with strong pull-up SPI_MOSI Input with weak pull down UART_RX Bidirectional Serial Peripheral Interface Data Output Chip Select For Synchronous Serial Interface (Active Low) Serial Peripheral Interface Data Input UART data input. (Active High) 5 6 7 8 9 10 11 12 13 14 UART_TX Bidirectional with strong pull-up 15 16 17 18 with weak pull-up Open drain LED0 LED1 Open drain LED2 Open drain RESET Input with strong pull-up 19 PIO4 20 PIO5 21 PIO12 22 PIO13 23 PIO6 Bidirectional with weak pull-

down Bidirectional with weak pull-

down Bidirectional with weak pull-

down Bidirectional with weak pull-

down Bidirectional with weak pull-

down UART Data Output (Active High) LED driver. Alternative function PIO[29]. LED driver. Alternative function PO[30]. LED driver. Alternative function PO[31]. Reset if low. Input debounced so must be low for >5ms to cause a reset. Programmable input / output line Programmable input / output line Programmable input / output line Programmable input / output line Programmable input / output line 10 24 PIO7 Bidirectional with weak pull-

down Power supply and control V_BAT_SE NSE USB_DP Bidirectional USB_DN CHG_EXT Bidirectional Power supply and control 25 26 27 28 29 V5_IN Power supply 30 31 1.8V_OUT VDD_PAD S Power supply Power supply and control 32 VDD_MEN Power supply 33 VREG_EN and control Power supply and control 34 35 36 VBAT GND PIO21 37 PIO22 38 PIO23 39 PIO24 Power supply and control GND Bidirectional with strong pull-

down Bidirectional with strong pull-

down Bidirectional with strong pull-

up Bidirectional with strong pull-

up Programmable input / output line Battery charger sense input. Connect directly to the battery positive pin. USB data plus with selectable internal1.5k pull-up resistor. USB data minus. External battery charger control. External battery charger transistor base control when using external charger boost. Otherwise leave unconnected. Charger input. Typically connected to VBUS

(USB supply) 1.8V DC/DC convertor output. 1.7V to 3.6V positive supply input for input/output ports:

RST#

UART PCM SPI PIO[15:0]

1.7V to 3.6V positive supply input for input/output ports:

Serial quad I/O flash port Regulator enable input. Can also be sensed as an input. Regulator enable and multifunction button. A high input (tolerant to VBAT) enables the on-chip regulators, which can then be latched on internally and the button used as a multifunction input. Battery positive terminal. Ground SPI flash clock. Alternative function PIO[21]. SPI RAM clock. Alternative function PIO[22]. SPI flash chip select. Alternative function PIO[23]

SPI RAM chip select. Alternative function PIO[24]. 11 40 PIO25 41 PIO26 42 PIO27 43 PIO28 Bidirectional with strong pull-

down Bidirectional with strong pull-

down Bidirectional with strong pull-

down Bidirectional with strong pull-

down GND Analogue out Serial quad I/O flash data bit 0. Alternative function PIO[25]. Serial quad I/O flash data bit 1. Alternative function PIO[26]. Serial quad I/O flash data bit 2. Alternative function PIO[27]. Serial quad I/O flash data bit 3. Alternative function PIO[28]. Ground Microphone bias A. Analogue out Microphone bias B. Analogue in Microphone input negative, right. Microphone input positive, right. Analogue in Microphone input negative, left. Microphone input positive, left. GND Analogue Analogue Analogue Analogue GND Ground Speaker output negative, left Speaker output positive, left Speaker output negative, right Speaker output positive, right Ground Bluetooth 50 transmitter output

/receiver input Ground GND MIC_BIAS _A MIC_BIAS _B MIC_RN MIC_RP MIC_LN MIC_LP GND SPK_LN SPK_LP SPK_RN SPK_RP GND RF_IN GND GND 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4. PHYSICAL INTERFACE 4.1 USB The module supports the Universal Serial Bus (USB) interface as a full speed Universal Serial Bus for communicating with other compatible digital devices. The USB interface acts as a USB peripheral, responding to requests from a master host controller such as a Personal Computer(PC).The module contains internal USB termination resistors and requires no external resistor matching. The module supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supports USB standard charger detection and fully supports the USB Battery Charging Specification . 12 4.2 UART The module has one optional standard UART serial interface that provides a simple mechanism for communicating with other serial devices using the RS232 protocol, including for test and debug. The UART interface is multiplexed with PIOs and other functions, and hardware flow control is optional. 4.3 Programming and Debug Interface A debug SPI interface is supplied for programming, configuring (PS Keys) and debugging Access to this interface is required in production. Tonly provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required. All are available from Tonly. 4.4 Analogue I/O Ports The general-purpose analogue interface pins, AIO_0,AIO_1, are supplied by the module. Typically, this connects to a thermistor for battery pack temperature measurements during charge control. 4.5 LED Drivers An 3-pad synchronised PWM LED driver is supplied for driving RGB LEDs for producing a wide range of colours. All LEDs are controlled by firmware. The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current-limiting resistor. 4.6 RF Port An on-chip balun combines the balanced outputs of the PA on transmit and produces the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode impedance is 50 and the transmitter has been optimised to deliver power into a 50 load. 4.7 Audio code Interface Stereo and mono analogue input for voice band and audio band

. Stereo and mono analogue output for voice band and audio band Support for stereo digital a Support for IEC The main features of the interface are:

AES3(also known as AES/EBU). Support for PCM interfaces including PCM master c udio bus standards such as I2S.

-60958 standard stereo digital audio bus standards, e.g. SPDIF and oded that require an external system clock. 13 Figure4 (Audio Codec Input and Output Stages) 4.7.1 ADC Figure 4 shows the CSR8670 consists of 2 high-quality ADCs:

Each ADC has a second Each ADC is a separate channel with identical functionality There are 2 gain stages for each

-order Sigma-Delta converter other is a digital gain stages 4.7.2 ADC Sample Rate Selection channel,1 of which is an analogue gain stage and the Each ADC supports the following pre-defined sample rates, although other rates are 8kHz 11.025 kHz 16kHz 22. 24kHz 32 kHz 44.1kHz 48 kHz programable,e.g.40kHz:

050kHz 4.7.3 ADC Digital Gain A digital gain stage inside the ADC varies from -24dB to 21.5dB,see as below, there is also a fine gain interface with 9-bit gain setting allowing gain changes in 1/32 steps. The Firmware controls the audio input gain. 14 4.7.4 DAC Sample Rate Selection 4.7.5 DAC Digital Gain 8kHz 11.025kHz 16kHz 22.050kHz 32kHz 40kHz 44.1kHz 48kHz 96kHz A digital gain stage inside the DAC varies from -24dB to 21.5dB, see as below, there is also a Fine gain interface with 9-bit gain setting enabling gain changes in 1/32 steps. The overall gain control of the ADC is controlled by the firmware. Its setting is a combined. function of the digital and analogue amplifier settings 15 4.7.6 DAC Analogue Gain As below shows that the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB steps. The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue amplifier settings. 4.7.7 IEC 60958 Interface The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimise the DC content of the transmitted signal and enables the receiver to decode the clock information from the transmitted signal. The IEC 60958 specification is based on the 2 industry standards:

AES3(

Sony and Philips interface specification SPDIF also known as AES/EBU) The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4 The SPDIF interface signals are SPDIF-IN and SPDIF-OUT and are shared on the PCM interface pin. 4.7.8 Microphone Input The CSR8670 contains 2 independent low-noise microphone bias generators. The microphone bias generators are recommended for biasing electret condensor micro phones. A biasing circuit for microphones with a sensitivity between about -40dB to -60dB(0dB=1V/Pa). 4.7.9 Digital Microphone Inputs The CSR8670 interfaces to 6 digital MEMS microphones. Figure 4 shows that 4 of the inputs have dedicated codec channels and 2 are multiplexed with the high quality ADC channels. 4.7.10 Line input If the pre-amplifier audio input gain is set at a low gain level it acts as an audio line level amplifier. In this line input mode the input impendance varies from 6kohm to 30kohm,depending on the volume setting. 4.7.11 Audio Output Stage The output digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to a 2Mbits/sec multi-bit stream, which is fed into the analogue output circuitry. The output circuit comprises a digital to analogue converter with gain setting and output Amplifier. Its class-AB output-stage is capable of driving a signal on both channels of up to 2V pk-pk differential into a load of 16. The output is available as a differential signal between SPK_RP and SPK_RN for the right channel ; and between SPK_LP and SPK_LN for the left 16 channel. The output is capable of driving a speaker directly if its impedance is at least 8 if only one channel is connected or an external regulator is used. The gain of the output stage is controlled by a 3-bit programmable resistive divider, which sets the gain in steps of approximately 3dB. The multi-bit stream from the digital circuitry is low pass filtered by a second order biquad Continuous transmission and reception of PCM encoded audio data over Bluetooth. Processor overhead reduction through hardware support for continual filter with a pole at 20kHz. The signal is then amplified in the fully differential output stage, which has a gain bandwidth of typically 1MHz. 4.7.12 PCM Interface The audio PCM interface on the TBM_C870 supports:

On -chip routing to Kalimba DSP. And reception of PCM data the firmware .It does not pass through the HCI protocol layer. Hardware on the Up to 3 SCO PCM interface PCM interface slave, Various clock formats including:

connections on the PCM interface at any one time. master, generating PCM_SYNC and PCM_CLK. accepting externally generated PCM_SYNC and PCM_CLK. TBM_C870 for sending data to and from a SCO connection. A bidirectional digital audio interface that routes directly into the baseband layer of transmmision Long Frame Sync Short Frame Sync GCI timing environments Receives and transmits on any selection of 3 the first 4 slots following PCM_SYNC. 13 -bit or 16-bit linear,8-bit u-law or A-law companded sample formats. PCM configuration options are enabled by setting the PS Key .PSKEY_PCM_CONFIG32. 4.7.13 Digital Audio Interface(I2S) The digital audio interface supports the industry standard formats for I2S,left-justified or right justified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table as below lists these alternative functions The 4.8 Reset The BT_Reset pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. Tonly recommends applying BT_Reset for a period >5ms. 17 4.9 Battery Charger The internal charger circuit can provide up to 200mA of charge current, for currents higher than this , you should use external charger mode. The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across a resistor, Rsense, connected in series with the external pass device. The voltage drop is determined by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across Rsense is typically 200mV. The value of the external series resistor determines the charger current. This current can be trimmed with a PS Key. 4.10 VREG_EN The module boots-up when this VREG_EN pin is pulling high typically for 10 to 15ms, enableing the regulators in the module. The firmware then latches the regulators on. The voltage regulator enable pin can then be released. The status of the VREG_EN pin is available to firmware through an internal connection. VREG_EN pin should be asserted after the VBAT supply when VREGENABLE is not used as a power-on button. 18 5.ELECTRIAL CHARACTERSTICS 5.1 Absolute maximum ratings Rating Storage temperature Supply Voltage VCHG VBAT VREG VDD_PADS Min

-40

-0.40

-0.40

-0.40

-0.40 Max 105 5.75 4.40 4.40 3.60 Unit C V V V V The module should not continuously run under these conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Table1: Absolute maximum ratings 5.2 Recommended operating conditions Rating Operating temperature Supply Voltage VCHG VBAT VREG VDD_PADS Min

-40 4.75 2.5 0 1.8 Max 85 5.75 4.25 4.25 3.60 Unit C V V V V Table2: Recommended operating conditions 19 5.3 Battery Charger Min Type Max Trickle Charge Mode Charge current I trickle, as percentage of fast charge current 8

-

V fast rising threshold V fast falling threshold

-

Fast Charge Mode 194 Charge current during constant current mode, Ifast Maximum charge setting(VCHG-VBAT > 0.55V) Fast charge current, Ifast (External Charge Mode(a)) V float threshold, calibrated Charge termination current Iterm, as percentage of fast Standby Mode Voltage hysteresis on VBAT, Vhyst

(a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical characteristics are listed in this table. 200 4.16 4.20 7 100 500 4.24 20 150 12

-

-

206 10 2.9 2.8 200 10 mA V

%

mV Unit

%

V V mA Table3: Battery charger 5.4 RF characteristics Transmi tter Output Power Chann el 2402 2441 2480 Average Bluetooth Receiver Spec.

-6 dBm

~+10 dBm Sensitivity at 0.1% BER 4.00 dBm 4.80 dBm 4.97 dBm Chann el 2402 Average Bluetooth Spec.

-81 dBm <=-70dBm 2441 2480

-81 dBm

-81 dBm Table4:RF characteristics 20 6. RECOMMEND PCB LAYOUT PATTERN 21 Figture4 Recommended PCB land pattern for BDP-8670 7. RECOMMEND SOLDER PROFILE The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder re-flow. There are four zones:

1. Preheat Zone - This zone raises the temperature at a controlled rate, typically 1-2.5C/s. 2. Equilibrium Zone - This zone brings the board to a uniform temperature and also activates the flux. The duration in this zone (typically 2-3 minutes) will need to be adjusted to optimize the out gassing of the flux. 3. Reflow Zone - The peak temperature should be high enough to achieve good wetting but not so high as to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth which can result in a brittle joint. 4. Cooling Zone - The cooling rate should be fast, to keep the solder grains small which will give a longer lasting joint. Typical rates will be 2-5C/s. Figture5 Recommended solder profile Key features of the profile:

Initial ramp = 1-2.5C/sec to 175C 25C equilibrium Equilibrium time = 60 to 180 seconds Ramp to maximum temperature (245C) = 3C/sec max. Time above liquidus temperature (217C): 45-90 seconds Device absolute maximum reflow temperature: 260C 22 8. STATEMENT This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help.

Any changes or modifications not expressly approved by the party responsible for compliance could void the authority to operate equipment.

This device and its antenna must not be co-

located or operating in conjunction with any other antenna or transmitter.

End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. Module This module is intended for OEM integrator. The OEM integrator is still responsible for the FCC compliance requirement of the end product, which integrates this module. 20cm minimum distance has to be able to be maintained between the antenna and the users for the host this module is integrated into. Under such configuration, the FCC radiation exposure limits set forth for an population/uncontrolled environment can be satisfied. Any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment. USERS MANUAL OF THE END PRODUCT:

In the users manual of the end product, the end user has to be informed to keep at least 20cm separation with the antenna while this end product is installed and operated. The end user has to be informed that the FCC radio-frequency exposure guidelines for an uncontrolled environment can be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment. 23 If the size of the end product is smaller than 8x10cm, then additional FCC part 15.19 statement is required to be available in the users manual: This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation. LABEL OF THE END PRODUCT:

The final end product must be labeled in a visible area with the following " Contains TX FCC ID: VLV867029165569". If the size of the end product is larger than 8x10cm, then the following FCC part 15.19 statement has to also be available on the label: This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation. 24