SPBT2632C2A Bluetooth technology class-2 module Datasheet production data Features Bluetooth radio Fully embedded Bluetooth v3.0 with profiles Class 2 module Complete RF ready module 128-bit encryption security Integrated antenna Multipoint capability ST micro Cortex-M3 microprocessor up to 72 MHz Memory 256 kb Flash memory 48 kb RAM memory Data rate 1.5 Mbps maximum data rate Serial interface UART up to 2.0 Mbps SPI interface General I/O 7 general purpose I/Os 1 LPO input User interface AT2 command set (abSerial) Firmware upgrade over UART FCC and Bluetooth qualified EPL (end product listing) fulfilled Single voltage supply: 2.5 V typical Micro-sized form factor: 11.6 x 13.5 x 2.9 mm Operating temperature range: -40 C to 85 C. August 2012 Doc ID 022833 Rev 4 This is information on a product in full production. 1/27 www.st.com 27 Contents Contents SPBT2632C2A 1 2 3 4 5 6 7 Description . 6 RoHS compliance . 7 Applications . 7 Software architecture . 8 Lower layer stack . 8 4.1 4.2 4.3 4.4 Upper layer stack: Amp'ed UP . 8 AT command set: abSerial . 8 Bluetooth firmware implementation . 9 Hardware specifications . 10 Recommended operating conditions . 10 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Absolute maximum ratings . 10 High speed CPU mode current consumption . 11 Standard CPU mode current consumption . 11 I/O operating characteristics . 12 Selected RF characteristics . 12 Pin assignment . 13 Pin placement . 14 Layout drawing . 14 Hardware block diagram . 15 Hardware design . 16 Module reflow installation . 16 7.1 7.2 7.3 7.4 7.5 GPIO interface . 17 UART interface . 17 PCB layout guidelines . 18 Reset circuit . 19 External reset circuit . 19 7.5.1 7.5.2 Internal reset circuit . 19 2/27 Doc ID 022833 Rev 4 SPBT2632C2A Contents 7.6 7.7 External LPO input circuit . 20 Apple iOS CP reference design . 21 Regulatory compliance . 23 Ordering information . 25 Revision history . 26 8 9 10 Doc ID 022833 Rev 4 3/27 List of tables List of tables SPBT2632C2A Recommended operating conditions . 10 Table 1. Absolute maximum ratings . 10 Table 2. High speed CPU mode current consumption . 11 Table 3. Standard CPU mode current consumption . 11 Table 4. I/O operating characteristics . 12 Table 5. Selected RF characteristics . 12 Table 6. Pin assignment . 13 Table 7. Soldering. 16 Table 8. Table 9. System configuration variables. 20 Table 10. Ordering information . 25 Table 11. Document revision history . 26 4/27 Doc ID 022833 Rev 4 SPBT2632C2A List of figures List of figures FW architecture . 9 Figure 1. Pin placement . 14 Figure 2. Layout drawing . 14 Figure 3. SPBT2632C2A.AT2 module block diagram . 15 Figure 4. Soldering profile . 17 Figure 5. Connection to host device . 17 Figure 6. Typical RS232 circuit . 18 Figure 7. PCB layout guidelines. 18 Figure 8. External reset circuit . 19 Figure 9. Figure 10. Internal reset circuit . 19 Figure 11. External LPO circuit . 20 Figure 12. BT module . 21 Figure 13. Co-processor . 21 Figure 14. Power switch. 22 Doc ID 022833 Rev 4 5/27 Description 1 Description SPBT2632C2A The SPBT2632C2A.AT2 is an easy to use Bluetooth module, compliant with Bluetooth v3.0. The module is the smallest form factor available which provides a complete RF platform. The SPBT2632C2A.AT2 enables electronic devices with wireless connectivity, not requiring any RF experience or expertise for integration into the final product. The SPBT2632C2A.AT2 module, being a certified solution, optimizes the time to market of the final applications. The module is designed for maximum performance in a minimal space including fast speed UART and 7 general purpose I/O lines, several serial interface options, and up to 1.5 Mbps data throughput. Optimized design allows the integration of a complete working Bluetooth modem, including antenna, in the minimum possible size; only an additional external LPO (low power oscillator) is required to enable low power mode capability. The SPBT2632C2A.AT2 is a surface mount PCB module that provides fully embedded, ready to use Bluetooth wireless technology. The reprogrammable Flash memory contains embedded firmware for serial cable replacement using the Bluetooth SPP profile. Embedded Bluetooth AT2 command firmware is a friendly interface, which realizes a simple control for cable replacement, enabling communication with most Bluetooth enabled devices, provided that the devices support the SPP profile. The SPBT2632C2A.AT2 , supporting iAP profile, provides communication with Android, smartphone, and Apple iOS Bluetooth enabled devices. An Apple authentication IC is required to exchange data with an Apple device or access an Apple device application. The AT2 FW includes the Bluetooth SPP profile capable of recognizing the Apple authentication chip. Customers using the Apple authentication IC must register as developers to become an Apple certified MFI member. License fees may apply, for additional information visit:
http://developer.apple.com/programs/which-program/index.html. Certified MFI developers developing electronic accessories that connect to the iPod, iPhone, and iPad gain access to technical documentation, hardware components, technical support and certification logos. Customized firmware for peripheral device interaction, power optimization, security, and other proprietary features may be supported and can be ordered pre-loaded and configured. 6/27 Doc ID 022833 Rev 4 SPBT2632C2A RoHS compliance 2 RoHS compliance ST modules are RoHS compliant and comply with ECOPACK norms. 3 Applications Serial cable replacement M2M industrial control Service diagnostic Data acquisition equipment Machine control Sensor monitoring Security system Mobile health. Doc ID 022833 Rev 4 7/27 Software architecture SPBT2632C2A 4 Software architecture 4.1 Lower layer stack Bluetooth v3.0 Device power modes: active, sleep and deep sleep Wake on Bluetooth feature optimized power consumption of host CPU Authentication and encryption Encryption key length from 8 bits to 128 bits Persistent Flash memory for BD address and user parameter storage All ACL (asynchronous connection less) packet types Sniff mode: fully supported to maximum allowed intervals Multipoint capability Master slave switch supported during connection and post connection Dedicated inquiry access code for improved inquiry scan performance Dynamic packet selection channel quality driven data rate to optimize link performance Dynamic power control 802.11b co-existence AFH. 4.2 Upper layer stack: Amp'ed UP SPP, IAP, SDAP and GAP protocols RFComm, SDP, and L2CAP supported Multipoint with simultaneous slaves. 4.3 AT command set: abSerial Please see command list reported in the SPBT2532C2.AT datasheet, Appendix D, for details. The complete command list including the iAP commands will be reported in the user manual UM1547. 8/27 Doc ID 022833 Rev 4 SPBT2632C2A Software architecture 4.4 Bluetooth firmware implementation Figure 1. FW architecture
Doc ID 022833 Rev 4 9/27 Hardware specifications SPBT2632C2A 5 Hardware specifications General conditions (VIN = 2.5 V and 25 C). 5.1 Recommended operating conditions Table 1. Recommended operating conditions Rating Operating temperature range Supply voltage VIN Signal pin voltage RF frequency Min.
-40 2.1
2400 Typical Max. Unit
2.5 2.1
85 3.6
C V V 2483.5 MHz 5.2 Absolute maximum ratings Table 2. Absolute maximum ratings Rating Storage temperature range Supply voltage, VIN I/O pin voltage, VIO RF input power Min.
-55
-0.3
-0.3
Typical
Max.
+105
+ 5.0
+ 5.5
-5 Unit C V V dBm 10/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware specifications 5.3 High speed CPU mode current consumption High speed CPU mode CPU 32 MHz UART supports up to 921 Kbps Data throughput up to 1.5 Mbps Shallow sleep enabled. Table 3. High speed CPU mode current consumption Modes (typical power consumption) Avg. Unit ACL data 115 K baud UART at max. throughput (master) ACL data 115 K baud UART at max. throughput (slave) Connection, no data traffic, master Connection, no data traffic, slave Connection 375 ms sniff (external LPO required) Standby, without deep sleep Standby, with deep sleep, no external LPO Standby, with deep sleep, with external LPO Page/inquiry scan, with deep sleep, no external LPO Page/inquiry scan, with deep sleep, with external LPO Bluetooth power down / CPU standby, no external LPO 23 27.5 9.1 11.2 490 8.6 1.7 70 2.7 520 25 mA mA mA mA A mA mA A mA A A 5.4 Standard CPU mode current consumption Standard CPU mode CPU 8 MHz UART supports up to 115 Kbps Data throughput up to 200 Kbps Shallow sleep enabled. Table 4. Standard CPU mode current consumption Modes (typical power consumption) Avg. Unit ACL data 115 K baud UART at max. throughput (master) ACL data 115 K baud UART at max. throughput (slave) Connection, no data traffic, master Connection, no data traffic, slave Connection 375 ms sniff (external LPO required) Standby, without deep sleep Standby, with deep sleep, no external LPO 16.7 18 4.9 7.0 490 4.2 1.7 mA mA mA mA A mA mA Doc ID 022833 Rev 4 11/27 Hardware specifications SPBT2632C2A Table 4. Standard CPU mode current consumption (continued) Modes (typical power consumption) Avg. Unit Standby, with deep sleep, with external LPO Page/inquiry scan, with deep sleep, no external LPO Page/inquiry scan, with deep sleep, with external LPO Bluetooth power-down / CPU standby, no external LPO 70 2.6 520 25 A mA A A 5.5 I/O operating characteristics Table 5. I/O operating characteristics Symbol Parameter Min. Max. Unit Conditions VIL VIH VOL VOH IOL IOH RPU RPD Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Low -level output current High-level output current Pull-up resistor Pull-down resistor
1.4
1.8
80 80 0.6
0.4
4.0 4.0 120 120 V V V V mA mA k k VIN, 2.1 V VIN, 2.1 V VIN, 2.1 V VIN, 2.1 V VOL = 0.4 V VOH = 1.8 V Resistor turned on Resistor turned on 5.6 Selected RF characteristics Table 6. Selected RF characteristics Parameters Antenna load Conditions Radio receiver Typical(1) 50 Sensitivity level BER < .001 with DH5 Maximum usable level BER < .001 with DH1 Input VSWR Maximum output power Radio transmitter 50 load Initial carrier frequency tolerance 20 dB bandwidth for modulated carrier
-86 0 2.5:1 0 0 935 1. RF characteristics can be influenced by physical characteristics of final application. Unit ohm dBm dBm dBm kHz kHz 12/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware specifications 5.7 Pin assignment Table 7. Pin assignment Name Type Pin#
Description ALT function(1) RXD TXD RTS CTS Boot 0 Vin GND RESETN LPO GPIO [1]
GPIO [2]
GPIO [3]
GPIO [4]
GPIO [5]
GPIO [6]
GPIO [7]
I O O I I I I I/O I/O I/O I/O I/O I/O I/O 13 14 12 11 9 8 7 UART interface Receive data Transmit data ADC 3 ADC 2 Request to send (active low) Clear to send (active low) ADC 0 I2C clock/aux UART Rx ADC 1 I2C data/aux UART Tx Boot loader Boot 0 Power and ground Vin GND Reset 10 Reset input (active low for 5 ms) LPO 15 LPO input GPIO - general purpose input/output General purpose input/output SPI MISO General purpose input/output SPI MOSI/I2S_SD General purpose input/output SPI SCLK/I2S_CK General purpose input/output SPI SS/I2S_WS General purpose input/output General purpose input/output 16 General purpose input/output DAC ADC 4 1 2 3 4 5 6 5 V tolerant Y Y Y Y 2.5 V max. Y Y Y Y Y Y Y 1. Please note that the usage of ALT function is dependant upon the firmware that is loaded into the module, and is beyond the scope of this document. The AT command interface uses the main UART by default. Doc ID 022833 Rev 4 13/27 Hardware specifications 5.8 Pin placement Figure 2. Pin placement SPBT2632C2A 5.9 Layout drawing Figure 3. Layout drawing
14/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware block diagram 6 Hardware block diagram Figure 4. SPBT2632C2A.AT2 module block diagram
Doc ID 022833 Rev 4 15/27 Hardware design SPBT2632C2A 7 Hardware design Note:
7.1 The SPBT2632C2A module without AT2 command embedded FW supports UART, SPI, I2C and GPIO hardware interfaces. Note that the usage of these interfaces is dependent upon the firmware that is loaded into the module, and is beyond the scope of this document. The AT2 command interface uses the main UART by default. 1 2 3 4 All unused pins should be left floating; do not ground. All GND pins must be well grounded. The area around the module should be free of any ground planes, power planes, trace routings, or metal for 6 mm from the antenna in all directions. Traces should not be routed underneath the module. Module reflow installation The SPB2632C2A is a surface mount Bluetooth module supplied on a 16-pin, 6-layer PCB. The final assembly recommended reflow profiles are indicated here below. The soldering phase must be executed with care: In order to avoid undesired melting phenomenon, particular attention must be paid to the setup of the peak temperature. The following are some suggestions for the temperature profile based on IPC/JEDEC J-
STD-020C, July 2004 recommendations. Table 8. Soldering Profile feature Average ramp-up rate (TSMAX to TP) Preheat:
Temperature min. (TS min.) Temperature max. (TS max.) Time (ts min. to ts max.)(ts) Time maintained above:
Temperature TL Temperature TL Peak temperature (TP) Time within 5 C of actual peak temperature (TP) Ramp-down rate PB-free assembly 3 C/sec max 150 C 200 C 60-100 sec 217 C 60-70 sec 240 + 0 C 10-20 sec 6 C/sec Time from 25 C to peak temperature 8 minutes max. 16/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware design Figure 5. Soldering profile
7.2 7.3 GPIO interface All GPIOs are capable of sinking and sourcing 4 mA of I/O current. GPIO [1] to GPIO [7] are internally pulled down with 100 k (nominal) resistors. UART interface The UART is compatible with the 16550 industry standard. Four signals are provided with the UART interface. The TXD and RXD pins are used for data while the CTS and RTS pins are used for flow control. Figure 6. Connection to host device
Doc ID 022833 Rev 4 17/27 Hardware design SPBT2632C2A Figure 7. Typical RS232 circuit 7.4 PCB layout guidelines Figure 8. PCB layout guidelines
18/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware design 7.5 Reset circuit Two types of system reset circuits are detailed below. 7.5.1 External reset circuit Figure 9. External reset circuit
Note:
RPU ranges from 30 k to 50 k internally. 7.5.2 Internal reset circuit Figure 10. Internal reset circuit
Note:
1 RPU ranges from 30 k to 50 k internally. 2 RRST should be from 1 k to 10 k.
Doc ID 022833 Rev 4 19/27 Hardware design SPBT2632C2A 7.6 External LPO input circuit An optional low power oscillator input may be added to allow Deep sleep and Sniff modes. Frequency: 32.768 kHz Tolerance: 150 ppm Voltage levels Low: 0.5 V High: 1.8 V Input capacitance: 2.5 pF maximum LPO parameters:
Configurations:
Use two configuration variables: UseExtLPO and AllowSniff. Table 9. System configuration variables Variable Name Default Description Var37 UseExtLPO True Var43 AllowSniff True True when a 32.768 kHz low power oscillator is present, and false if not present Enables Sniff mode. Figure 11. External LPO circuit
20/27 Doc ID 022833 Rev 4 SPBT2632C2A Hardware design 7.7 Apple iOS CP reference design The figures below give an indicative overview of what the hardware concept looks like. A specific MFI co-processor layout is available for licensed MFI developers from the MFI program. Figure 12. BT module Figure 13. Co-processor
Doc ID 022833 Rev 4 21/27 Hardware design SPBT2632C2A Figure 14. Power switch
22/27 Doc ID 022833 Rev 4 SPBT2632C2A Regulatory compliance 8 Regulatory compliance FCC and IC This module has been tested and found to comply with the FCC part 15 and IC RSS-210 rules. These limits are designed to provide reasonable protection against harmful interference in approved installations. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference may not occur in a particular installation. This device complies with part 15 of the FCC rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and
(2) this device must accept any interference received, including interference that may cause undesired operation. Modifications or changes to this equipment not expressly approved by the part responsible for compliance may render void the user's authority to operate this equipment. Modular approval, FCC and IC FCC ID: X3ZBTMOD4 IC: 8828A-MOD4 In accordance with FCC part 15, the SPBT2632C2A.AT2 is listed above as a modular transmitter device. Label instructions When integrating the SPBT2632C2A.AT2 into the final product, it must be ensured that the FCC labelling requirements, as specified below, are satisfied. Based on the Public Notice from FCC, the product into which the ST transmitter module is installed must display a label referring to the enclosed module. The label should use wording such as the following:
Contains Transmitter Module FCC ID: X3ZBTMOD4 IC: 8828A-MOD4 Any similar wording that expresses the same meaning may be used. BQB BQB qualified design, QD ID: B019224 Product type: End Product TGP version: Core 3.0 Core spec version: 3.0 Product descriptions: Bluetooth module, spec V3.0 Doc ID 022833 Rev 4 23/27 Regulatory compliance SPBT2632C2A CE Measurements have been performed in accordance with (report available on CE Expert opinion: 0448-ARAM00003 request):
EN 300 328 V 1.7.1 (2006-10) (a) EN 301 489-17 V 2.1.1 (2009) (b) EN60950-1:2006 +A11:2009+A1:2010 (c) CE certified:
a. EN 300 328 V 1.7.1 (2006-10): electromagnetic compatibility and radio spectrum Matters (ERM); Wideband transmission systems; data transmission equipment operating in the 2.4 GHZ ISM band and using wideband modulation techniques; harmonized EN covering essential requirements under article 3.2 of the R&TTE directive. b. EN 301 489-17 V 2.1.1 (2009): electromagnetic compatibility and radio spectrum Matters (ERM);
electromagnetic compatibility (EMC) standard for radio equipment and services; part 17: specific condition for 2.4 GHz wideband transmission systems and 5 GHz high performance RLAN equipment. c. EN60950-1:2006 +A11:2009+A1:2010: Information technology equipment - safety. 24/27 Doc ID 022833 Rev 4 SPBT2632C2A Ordering information 9 Ordering information Table 10. Ordering information Order code Description SPBT2632C2A.AT2 Class 2 OEM Bluetooth antenna module Doc ID 022833 Rev 4 25/27 Revision history SPBT2632C2A 10 Revision history Table 11. Document revision history Date Revision Changes 03-Apr-2012 16-Apr-2012 12-Jun-2012 07-Aug-2012 1 2 3 4 First release. Modified: Section 8 Document status promoted from preliminary data to production data Modified: Figure 1 Added: notes in Table 6 and 7 Modified: Section 7 26/27 Doc ID 022833 Rev 4 SPBT2632C2A Please Read Carefully:
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