| submitted | available | document details (if available) | source link |
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| Microsoft Word - AV6301 Datasheet Rev 0.4.docx sdols Acrobat Distiller 6.0.1 (Windows) |
| various | Datasheet | Users Manual | 401.44 KiB |
Preliminary Datasheet AV6301 Wireless Audio Sender IC General Description The AV6301 / 6302 chipset is optimized for building wireless gaming headsets and point to multi-point audio distribution solutions such as rear speakers and subwoofers in home theater systems..The chipset is comprised of two ICs: AV6301 (sender) and AV6302 (client). These devices share the VMI RF Protocol and may be mixed and matched with other VMI chips (AAV6200, V6201, and AV6202). The AV6301 / 02 chipset achieves the goal of enabling a single core design to service multiple game platforms (PC or Console), External Digital Signal Processing (DSP) is also easily supported for all gaming platforms. The chip set provides all functions necessary to complete a bidirectional wireless audio link with high quality voice and music performance. Operation in the worldwide 2.4 GHz spectrum addresses the need for global application. System / Chipset Features
Stereo audio path: >93 dB SNR, 20 kHz BW
Mono voice path: >70 dB SNR, 6.5 kHz voice Sophisticated audio routing and mixing options to meet demands of multiple gaming headset platforms Over-the-air (OTA) serial interface: >2 kbps, bi-directional, full duplex Works within 3 inches of WIFI Client without impairment to Audio or WIFI throughput Advanced forward error correction coding, error detection, and audio-specific error concealment Diversity antenna support Low and Fixed Latency: <16 ms, Long Range: 15m (non-line-of-site) Auto search/sync/standby/wake-
up/shutdown
All Voltage Regulators on-chip
Interoperability with VMI (AV6201 / 02) Chipset is a highly transceiver and a AV6301 The AV6301 integrated, single-chip, wireless audio sender IC. It integrates the following: a complete 2.4 GHz RF transceiver, PHY & MAC, advanced power management hardware, audio DSP, USB 2.0 full complement of programmable digital interfaces to support a wide range of end-product user-interface requirements, including SPI and TWI interfaces. The device incorporates a complete USB 2.0 transceiver and enumerates as a USB Audio device as well as USB Human Interface Device (HID) without the need for external drivers, enabling true plug &
play. Additionally, the device makes available 3 independent I2S interfaces, allowing independent processing of non-USB audio sources. Simultaneous use of the USB and I2S ports is enhanced by additional audio processing capability, allowing for independent control and mixing of the different audio sources. AV6301 Features
Advanced Signal Routing Capability USB Port Enumerates as Audio and / or
Human interface device (HID)
Three available I2S ports
Simultaneous operation of USB and I2S ports
Expansive Digital I/O Capability
20 General Purpose Input / Output Pins
Master and Slave SPI and TWI interfaces
Pulse Width Modulated (PWM) I/O support Straightforward implementation of external EEPROM, DSP, Audio Codec and Host uC for advanced applications On-Chip One-Time-Programmable (OTP) Memory
Applications PC Game Wireless Headset Game Console Wireless Headset I2S based Wireless Audio Wireless Rear Speakers CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 1 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA Packaging The AV6301 is packaged in a 7 x 7 mm, 48 pin QFN and is rated for operation over the commercial temperature range (0 to 70 degrees C) CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 2 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 Revision History Revision Change Summary 0.1 0.2 Preliminary release of datasheet Add AV6xxx Selection Grid, Update Audio Routing, Block Diagram, Application Circuit, Pin Out and Pin Description. RF TX Electrical characteristics update. Update Selector Grid CORRECTION to I2S assignments to GPIO ports (stereo in, stereo out and mono out have all changed).I2S assignments reflected in Applications Diagram. Update of selection grid. 0.3 0.4 Release Date 10/7/11 10/27/11 11/4/11 11/15/11 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 3 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 4 3 2 Table of Contents General Description.............................................................................................................................................................. 1 System / Chipset Features ................................................................................................................................................... 1 AV6301................................................................................................................................................................................. 1 AV6301 Features.................................................................................................................................................................. 1 Applications .......................................................................................................................................................................... 1 Packaging............................................................................................................................................................................. 2 Revision History.................................................................................................................................................................... 3 Table 0-1 AV6xxx Selection Grid.......................................................................................................................................... 6 1 REFERENCE DIAGRAMS.......................................................................................................................................... 7 1.1 Wireless Arbiter Solution Diagram.......................................................................................................................... 7 1.2 Functional Diagram ................................................................................................................................................ 8 1.3 Audio Signal Routing Diagram ............................................................................................................................... 8 1.4 Application Circuit Wireless Universal Gaming Arbiter ........................................................................................ 9 PIN INFORMATION .................................................................................................................................................. 10 2.1 Pin Diagram.......................................................................................................................................................... 10 2.2 Pin Description ..................................................................................................................................................... 11 ELECTRICAL SPECIFICATIONS ............................................................................................................................. 13 3.1 Absolute Maximum Ratings.................................................................................................................................. 13 3.2 DC Electrical Characteristics ................................................................................................................................ 14 3.3 Electrical Characteristics Voltage Supervisory Circuit ....................................................................................... 14 3.4 Electrical Characteristics RF Receiver .............................................................................................................. 15 3.5 Electrical Characteristics RF Transmitter .......................................................................................................... 15 3.6 Electrical Characteristics End-to-end Audio Characteristics.............................................................................. 15 PACKAGE INFORMATION....................................................................................................................................... 16 4.1 Package Outline Drawing..................................................................................................................................... 16 4.2 Package Marking.................................................................................................................................................. 17 CONTACT INFO & LEGAL DISCLAIMER................................................................................................................. 18 5 List of Tables Table 0-1 AV6xxx Selection Grid.......................................................................................................................................... 6 Table 2-2-1 AV301 pin description...................................................................................................................................... 11 Table 3-1 Absolute Maximum Ratings ................................................................................................................................ 13 Table 3-2 AV6301 DC Electrical Characteristics ................................................................................................................ 14 Table 3-3 AV6301 Electrical Characteristics - Voltage Supervisory ................................................................................... 14 Table 3-4 AV6301 Electrical Characteristics - RF Receiver................................................................................................ 15 Table 3-5 AV6301 Electrical Characteristics - RF Transmitter............................................................................................ 15 Table 3-6 AV6301 Electrical Characteristics - End-to-End Audio Characteristics............................................................... 15 List of Figures Figure 1-1 AV6301 Wireless Arbiter Solution ....................................................................................................................... 7 Figure 1-2 AV6301 Functional Diagram................................................................................................................................ 8 Figure 1-3 AV6301 Audio Routing ........................................................................................................................................ 8 Figure 1-4 AV6301 Application Circuit .................................................................................................................................. 9 Figure 2-1 AV6301 Pin Diagram......................................................................................................................................... 10 Figure 4-1 AV6301 48 Pin QFN Outline Drawing ............................................................................................................... 16 Figure 4-2 Package Marking Layout................................................................................................................................... 17 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 4 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 5 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 Table 0-1 AV6xxx Selection Grid Part Number AV6200 AV6201 AV6301 AV6200 AV6202 AV6302 Role I2S IN I2S Out USB Port MIC Amp Headphone Driver Amp Battery Charger General Purpose ADCs Button Support Rotary Encoder Support LED Support I2S Loop-
Back
(external DSP) MIC path input to I2S out MIC Side-
tone Mix Game / Chat Mix on TX Game / Chat Mix at RX Stereo N/A No No No No 0 Yes No Yes No Sender No No Audio /
HID No No Stereo Stereo Mono Audio /
HID No No No 0 Yes No Yes No No 0 Yes No Yes Yes N/A Stereo Receiver Mono Stereo No No No No 0 Yes No Yes No HID Yes Yes Yes 0 Yes Yes Yes No Mono Stereo Mono HID Yes Yes Yes 3 Yes Yes Yes No N/A N/A N/A N/A No Yes N/A N/A N/A N/A No N/A N/A Yes N/A N/A N/A No Yes N/A No Yes N/A Yes CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 6 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 1 REFERENCE DIAGRAMS 1.1 Wireless Arbiter Solution Diagram Figure 1-1 AV6301 Wireless Arbiter Solution CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 7 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) 1.2 Functional Diagram revision 0.2 VDC V3P6 RFP RFN 3.6V LDO USB Spnd XTAL SUP VBG REF DIG Regs 3.3V REG RF/IF Transceiver MCU ROM RAM OTP GPIO 20 PHY Audio Proc USB Figure 1-2 AV6301 Functional Diagram GPIO DSCP,DSCN SPI, I2C GPIO (Buttons, LEDs) I2S DP DM 1.3 Audio Signal Routing Diagram Figure 1-3 AV6301 Audio Routing CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 8 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 1.4 Application Circuit Wireless Universal Gaming Arbiter Figure 1-4 AV6301 Application Circuit CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 9 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 2 PIN INFORMATION 2.1 Pin Diagram Figure 2-1 AV6301 Pin Diagram CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 10 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 2.2 Pin Description Table 2-2-1 AV301 pin description Pin No. 1 Symbol GPIO1 DSCN DPA-EN GPIO0 DSCP DSC XTALP XTALN VDDXO N/C IREF BGOUT VDDRXADC RFP RFN VDC V3P6 RESETN GPIO16 PWM2 GPIO15 I2S MONO OUT PWM1 GPIO14 I2S STEREO IN GPIO13 I2S STEREO OUT GPIO12 WCLK GPIO11 BCLK PWM1 VDDIO GPIO10 MCLK PWM0 GPIO9 M_MISO (SPI Mater) M_SCL (TWI Master) SCL (TWI) GPIO8 M_MOSI (SPI Master) M_SDA (TWI Master) SDA (TWI) GPIO7 M_SCLK (SPI Master) PWM1 GPIO6 M_SSB (SPI Master) PWM0 GPIO19 2 3 4 5 6,8,10-14, 16, 19, 20, 23 7 9 15 17 18 21 22 24 25 26 27 28 29 30 32 31 33 34 35 36 37 Pin Type Digital Output Digital Output Analog input Analog input Analog
-
Analog pin Analog bypass Bypass RF I/O RF I/O Supply pin Bypass Digital input Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Supply Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Description GPIO port 1; Usage is programmable to GPIO OR to Antenna Diversity Switch OR to Power Amplifier Enable GPIO port 0; Usage is programmable to GPIO OR to Antenna Diversity Switch + OR to Single Polarity Diversity Switch Control External crystal input External crystal input Crystal oscillator regulator bypass pin No connection Leave unconnected Do not Ground Reference current setting resistor connection Bandgap reference bypass pin Bypass pin for Receiver Data Converter Supply RF input/output positive RF input/output negative 5V input supply voltage from USB Bypass pin for 3.6V main regulator RESET signal; active low GPIO port 16, usage is programmable to GPIO OR to PWM resource #2 GPIO port 15, usage is programmable to GPIO OR to I2S port 2 MONO OUT Data PWM resource #1 GPIO port 14; usage is programmable to GPIO OR to I2S Port 1 STEREO IN Data GPIO port 13; usage is programmable to GPIO OR to I2S Port 0 STEREO OUT Data GPIO port 12; usage is programmable to GPIO OR to I2S Word Clock GPIO port 11; usage is programmable to GPIO OR to I2S Bit Clock OR to PWM resource #1 Supply bypass capacitor pin for digital I/O GPIO port 10; usage is programmable to GPIO OR to I2S Master Clock OR to PWM resource #0 GPIO port 9; usage is programmable to GPIO OR to M_MISO OR to M_SCL OR to SCL GPIO port 8; usage is programmable to GPIO OR to M-MOSI OR to M_SDA OR to SDA GPIO port 7; usage is programmable to GPIO OR to M_SCLK OR to PWM resource #1 GPIO port 6; usage is programmable to GPIO OR to M-SSB OR to PWM resource #0 GPIO port 19, usage is programmable to GPIO OR to CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 11 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 Pin No. 38 39 40 41 42 43 44 45 46 47 48 Symbol PWM2 VDDDIG VDD18 VDDIO DM DP GPIO18 PWM1 GPIO5 S_MISO (SPI Slave) S_SCL (TWI Slave) GPIO4 S_MOSI (SPI Slave) S_SDA (TWI Slave) GPIO3 S_SCLK (SPI Slave) UART_RX PWM1 GPIO2 S_SSB (SPI Slave) UART_TX PWM0 GPIO17 PWM2 Pin Type Bypass Bypass Bypass USB I/O USB I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Description PWM resource #2 Bypass capacitor pin for 1.35V digital core regulator Bypass capacitor pin for 1.8V digital regulator (LDO) Bypass capacitor pin for 3.3V digital I/O regulator USB negative input USB positive input GPIO port 18, usage is programmable to GPIO OR to PWM resource #1 GPIO port 5; usage is programmable to GPIO OR to S_MISO OR to S_SCL GPIO port 4; usage is programmable to GPIO OR to S_MOSI OR to S_SDA GPIO port 3; usage is programmable to GPIO OR to S_SCLK OR to The UART Receiver OR to PWM resource #1 GPIO port 2; usage is programmable to GPIO OR to S_SSB OR to The UART Transmitter OR to PWM resource #0 GPIO port 17, usage is programmable to GPIO OR to PWM resource #2 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 12 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. Table 3-1 Absolute Maximum Ratings CONDITION Supply (relative to AGND and DGND) Input Voltage Range Digital Inputs Input Voltage Range Analog Inputs Short circuit to GND (any pin) Operating Temperature Storage Temperature Lead Temperature (10s) Static Discharge Voltage HBM (All pins ) Static Discharge Voltage MM
-0.3
-0.3
-0.3
--
-40
-40
--
V V V C C C V V
+85
+100
+300 6.0 3.6 3.6 3000 300 continuous Units MAX VDC MIN Note:
1) HBM = ESD Human Body Model; C = 100pF, R = 1k 2) MM = ESD Machine Model; C = 100pF; R = 300 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 13 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 MAX 5.5 MIN 4.4 3.2 DC Electrical Characteristics Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V. Table 3-2 AV6301 DC Electrical Characteristics PARAMETER VDC Supply Voltage Input V3P6 VDDIO (Digital 3.3V I/O) Reg. Voltage VDDDIG (Digital Core) Reg. Voltage VDD1P8 Supply Current (IVDC) USB chip GPIO Source Current CMOS I/O Logic Levels 3.3V I/O Input Voltage Logic Low, VIL Input Voltage Logic High, VIH Output Voltage Logic Low, VOL Output Voltage Logic High, VOH USB Interface DP Logic Output High CONDITIONS Internally regulated voltage Internally regulated voltage Internally regulated voltage Internally regulated voltage Reset USB Suspend Mode Arbiter Search Mode Arbiter Headset Link Mode VVDDIO = 3.3V VVDDIO = 3.3V VVDDIO = 3.3V ; ILOAD=1mA VVDDIO = 3.3V; ILOAD=1mA refer to USB spec; voltage relative to VDDIO TYP 5.0 3.6 3.3 1.35 1.8 TBD 1.0 TBD 55 4 0.8*VDD 2.9 2.0 0.8 0.4 TBD TBD TBD IO DM Logic Output Low refer to USB spec; voltage relative to VDDIO DP Logic Input High DM Logic Input Low USB Differential Input Sensitivity USB Differential Common Mode USB Single Ended RX Threshold USB IO Pin Static Output (Low) refer to USB spec; voltage relative to VDDIO refer to USB spec; voltage relative to VDDIO Rl=1.5k to 3.6V 0.2 0.8 0.8 0.2*VDD IO 0.7*VDD IO 0.3*VDD IO 2.5 2.0 0.3 3.3 Electrical Characteristics Voltage Supervisory Circuit Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V. Table 3-3 AV6301 Electrical Characteristics - Voltage Supervisory PARAMETER Voltage Monitor Low Thres. (assert reset) Voltage Monitor High Thres. (de-assert reset) Brownout bandwidth Reset Threshold (assert) Reset Threshold (de-assert) RESETN Minimum Time CONDITIONS Monitoring the voltage on V3P6 Monitoring the voltage on V3P6 Monitoring the voltage on V3P6 0.1uF external capacitor TYP 2.7 3.0 100 2.2 1.1 11 MIN MAX UNIT V V V V V mA mA mA mA V V V V V V V V V V V V UNIT V V kHz V V ms CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 14 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 3.4 Electrical Characteristics RF Receiver Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; RF Channel Freq = 2403.35-2477.35MHz, measured at the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25C, VDC = 5.0V. Table 3-4 AV6301 Electrical Characteristics - RF Receiver PARAMETER RF Channel Frequency Range MIN 2402 TYP MAX 2478 2479.35 Modulated Signal Offset from LO Sensitivity (Note 1) Max input signal (desired signal) (Note 1) Input Blocker Level High Gain mode Out-of-band blocker level Spurious RF outputs CONDITIONS LO frequency (driving the mixers) RF carrier frequency TA=25C, LNA = High gain mode; max IF gain TA=25C, LNA = low gain mode; min IF gain
> 2MHz offset
<2400 MHz; >2483.5 MHz
<2400 MHz
>2483.5 MHz 2403.35 1.35
-89
-5
-45 TBD
-75
-75 Note 1: Sensitivity and max signal level are defined as the onset of 0.2% Block Error Rate. )BLER) 3.5 Electrical Characteristics RF Transmitter Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; RF Channel Freq = 2403.35-2477.35MHz, measured at the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25C, VDC = 5.0V. Table 3-5 AV6301 Electrical Characteristics - RF Transmitter PARAMETER RF Channel Frequency Range MIN 2402 TYP MAX 2478 2479.35 2403.35 Modulated Signal Offset from LO Modulated Signal Bandwidth Output Power Output harmonics Out-of-band Spurious Output Output Noise Floor CONDITIONS LO frequency (driving the mixers) RF carrier frequency
-10dB point Pi/4 DQPSK modulated signal ACPR: Adj < -23dBc, Alt < -30dBc 2nd harmonic, Pout = 0dBm 3rd harmonic, Pout = 0dBm RF < 2390MHz, > 2483.5MHz, 1MHz RBW RF < 2390MHz, > 2483.5MHz, 1MHz RBW 1.35 1.8
+2
-52
-50
<-62
<-62 UNIT MHz MHz MHz dBm dBm dBm dBm dBm dBm UNIT MHz MHz MHz MHz dBm dBm dBm dBm dBm 3.6 Electrical Characteristics End-to-end Audio Characteristics Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V. Table 3-6 AV6301 Electrical Characteristics - End-to-End Audio Characteristics PARAMETER SNR Audio/Voice Bandwidth UNITS MAX MIN CONDITIONS Forward stereo path Reverse mono path End-to-end audio BW; 0.1dB point End-to-end audio BW; 0.1dB point AV6201 USB to AV6202 analog output AV6201 I2S to AV6202 I2S output AV6202 analog input to AV6201 USB output dB dB kHz kHz msec msec msec TYP 93 68 20 6.5
<16
<16
<16 Audio Latency Voice Latency CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 15 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 4 PACKAGE INFORMATION 4.1 Package Outline Drawing Figure 4-1 AV6301 48 Pin QFN Outline Drawing CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 16 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) 4.2 Package Marking A V D D D D revision 0.2 C C Y Y W W X X L L L L L L T T A Figure 4-2 Package Marking Layout Abbreviations:
AVDDDD Product number (i.e. AV6301) CC YY WW XX LLLLLL TT A Country Code (i.e. MY for Malaysia) 2 digit year code 2 digit work week Production revision Silicon Lot number Wafer split (1 by default) Assembly Lot CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 17 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6301 Datasheet (Preliminary) revision 0.2 5 CONTACT INFO & LEGAL DISCLAIMER Avnera Corporation 16505 Bethany Court, Suite 100 Beaverton, Oregon 97006 U.S.A. Main: +1.503.718.4100 Fax: +1.503.718.4101 www.avnera.com Avnera Corporation reserves the right to make changes without notice to the product to improve function, reliability, or performance. Avnera Corporation does not assume any liability arising from the application or use of the products or circuits described herein. CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 18 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA
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