FCC ID: 2ATYV-B102802 Bluetooth module

Buffalo-B Spec Product:

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Revision History Data 2017/04/17 2017/06/02 Buffalo-B Product Specification Buffalo / Bluetooth 4.2BLE module Buffalo-B VER 1.2 Suzhou Pairlink Network Technology Co.,Ltd. Room 117, No.55, Su hong xi Road,Suzhou Industrial Park, Suzhou City, Jiangsu Province, China. Change Description Initial release Add 3.3.1 PCB-Antenna Characteristics 1:Modify Bluetooth Core Version Add Note 1 2:Modify Packing Information Add 9.3: Label Information Revision 1.0 1.1 2018/08/08 1.2 Note 1: ST released new Stack which is Bluetooth Core V4.2 in June 2018.Buffalo-B has upgraded. But this Stack didnt support the feature "LE Data Length Extension". All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec FEATURES performance, ultra-low power regulator and DC-DC Bluetooth specification compliant master, slave and multiple roles simultaneously, single-mode Bluetooth low energy system-on-chip Operating supply voltage: from 1.7 to 3.6V Integrated linear step-down converter Operating temperature range: -40 C to 105 C High Cortex-M0 32-bit based architecture core High performance, ultra-low power Cortex-M0 32-bit based architecture core Programmable 160 KB Flash 24 KB RAM with retention (two 12 KB banks) 1 x UART interface 1 x SPI interface 2 x I2C interface 15 GPIO 2 x multifunction timer 10-bit ADC Watchdog & RTC 2 x PWM source DMA controller PDM stream processor 16 or 32 MHz crystal oscillator 32 kHz crystal oscillator Battery voltage monitor and temperature sensor Up to +8 dBm available output power (at antenna connector) Excellent RF link budget (up to 96 dB) Accurate RSSI to allow power control 8.2 mA maximum TX current

(@ 0 dBm, 3.0 V) Down to 3uA current consumption with active BLE stack (sleep mode) Package type:20.5*14.0*2.4mm FR4 PCB APPLICATIONS Automotive product Watches Fitness, wellness and sports Consumer medical Remote control Home and industrial automation Assisted living Lighting All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 1. Functional Characteristics Buffalo-B is a Soc module developed based on the Bluetooth 4.2 standards. the internal integration architecture Corrtex-M0 processor.It has the advantage of small volume, low power consumption, long distance transmission, strong anti-jamming capability, low cost.Specifically applied to bluetooth low power control area,and suitable for various occasions short distance wireless communication. Buffalo-B integral compact, simplifies the design in hardware and institution for user. The module interface open completely to make the users has more flexible secondary development space. Buffalo-B is a Bluetooth Low Energy module with 25 pads located around the perimeter. Primary component on the module is the ST_BlueNRG-1 which is a Bluetooth 4.2 compliant basic rate single-chip. The baseband and radio have been integrated into a single chip implemented in standard digital CMOS. Block diagram of the module is shown in Figure 1. Buffalo-B Supported Pairlink BLE Mesh Protocol.Suitable for IOT systems. Buffalo-B Supported Pairlink UART Protocol.Suitable all kinds of wireless system. Pairlink provide APK/APP software product design and development at the same time . Figure 1:Block Diagram All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec Contents 1. Functional Characteristics.........................................................................................................- 3 -

2. Module Interface Description...................................................................................................- 5 -

2.1. Pin Assignment and Pin Description.............................................................................. - 5 -

2.2. GPIO Description............................................................................................................- 6 -

2.2.1. GPIO Introduction............................................................................................... - 6 -

2.2.2. GPIO Functional Description...............................................................................- 6 -

2.2.3. GPIO Interrupts...................................................................................................- 7 -

2.2.4. GPIO Characteristics........................................................................................... - 7 -

3. Module Specification................................................................................................................ - 8 -

3.1. Electrical Characteristics................................................................................................ - 8 -

3.2. Absolute Maximum Ratings...........................................................................................- 9 -

3.3. RF General Characteristics........................................................................................... - 10 -

3.3.1. PCB-Antenna Characteristics............................................................................ - 11 -

3.4. Power Management .................................................................................................. - 15 -

3.4.1. States Description............................................................................................. - 15 -

3.5. Buffalo-B Power-On Sequence.................................................................................... - 17 -

3.6. Reset Management......................................................................................................- 18 -

4. Functional Details................................................................................................................... - 19 -

4.2. ADC.............................................................................................................................. - 19 -

4.1.1. Introduction...................................................................................................... - 19 -

4.1.2. Functional Overview......................................................................................... - 19 -

4.2. UART............................................................................................................................ - 22 -

4.2.1. Introduction...................................................................................................... - 22 -

4.2.2. Functional Description......................................................................................- 22 -

4.3. SPI................................................................................................................................ - 24 -

4.3.1. Introduction...................................................................................................... - 24 -

4.3.2. Functional Overview......................................................................................... - 24 -

4.4. IIC................................................................................................................................. - 26 -

4.4.1. Introduction...................................................................................................... - 26 -

4.4.2. Functional Description......................................................................................- 26 -

5. Reference Design.................................................................................................................... - 28 -

6. Appearance and Dimensions.................................................................................................. - 29 -

7. Recommended Land Pattern.................................................................................................. - 30 -

8. Module Layout Guideline........................................................................................................- 31 -

9. Packing Information................................................................................................................- 32 -

9.1. Rolling Information...................................................................................................... - 32 -

9.2. Master Carton Information..........................................................................................- 33 -

9.3. Label Information.........................................................................................................- 34 -

10. Standard Operation Procedure (SOP)................................................................................... - 35 -

All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 2. Module Interface Description 2.1. Pin Assignment and Pin Description Buffalo-B Pin definition can refer to Figure 15. Table 1: Module Pin Description Pin Number Pin Name 10 3,6,16,25 11 VBAT GND RESET 5 1 2 4 7 8 9 12 13 14 15 17 18 19 20 21 22 23 24 DIO7/BOOT XTALO XTALI DIO6 DIO9 DIO10 DIO14 ADC1 ADC2 DIO13 DIO12 DIO0 DIO11_RX DIO8_TX DIO5 DIO4 DIO3 DIO2 DIO1 I/O VBAT GND I I/O I I I/O I/O I/O O I I O O I/O I/O I/O I/O I/O I/O I/O I/O Alternate Function Description Power Supply Connect to Ground System Reset Bootloader Pin GPIO:P7 32kHz crystal 32kHz crystal GPIO: P6 GPIO: P9 GPIO: P10 GPIO: P14 10bit ADC input: ADC1 10bit ADC input: ADC2 GPIO: P13 OD structure GPIO: P12 OD structure GPIO: P0 GPIO: P11 UART_RX GPIO: P8 UART_TX GPIO: P5 I2C2_DAT GPIO: P4 I2C2_CLK GPIO: P3 SPI_IN GPIO: P2 SPI_OUT GPIO: P1 SPI_CS PWM1 PWM0 All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 2.2. GPIO Description 2.2.1. GPIO Introduction The Buffalo-B offers 15 GPIOs. The programmable I/O pin can be configured for operating as:

Programmable GPIOs Peripheral input or output line of standard communication interfaces 2 PWM sources (PWM0 and PWM1 independently configurable) and 4 PWM output pins

(IO2, IO3, IO4 and IO5). 5 wakeup sources from standby and sleep mode Each I/O can generate an interrupt independently to the selected mode. Interrupts are generated depending on a level or edge 2.2.2. GPIO Functional Description In the table below is reported the GPIO configuration table where at each IO pin is associated the related functions. Table 2: IO Functional Map All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 2.2.3. GPIO Interrupts Each IO in GPIO mode can be used as interrupt source from external signal. The trigger event is both edge and level sensitive according to configuration. All the configuration are reported in table below. Table 3: GPIO Interrupts modes 2.2.4. GPIO Characteristics By default all the GPIO pins are configured as input with related pull-up or pull-down resistor enabled according to table below. Table 4: GPIO Characteristics Table 12:IO Pull Values All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3. Module Specification 3.1. Electrical Characteristics Table 5: Recommended Operating Conditions Symbol VBAT TA Parameter Operating battery supply voltage Operating Ambient temperature range Operating Ambient temperature range For automotive grade level Value 1.7 to +3.6

-40 to +105

-40 to +105 Unit V Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 C, VBAT = 3.0 V. All performance data are referred to a 50 PCB antenna. Table 6: Electrical Characteristics All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.2. Absolute Maximum Ratings Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referred to GND. Table 7: Absolute Maximum Ratings Symbol VBAT TSTG VESD-HBM Current Parameter DC voltage for Buffalo-B Storage temperature range Electrostatic discharge voltage Current consumption @ 3.0V Value

-0.3 to +3.9

-40 to +125 2.0 0~20 Unit V KV mA All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.3. RF General Characteristics Characteristics measured over recommended operating conditions unless otherwise specified. Typical value are referred to TA = 25 C, VBAT =3.0 V. All performance data are referred to a 50 PCB antenna. Table 8: RF Transmitter Characteristics Table 9: Buffalo-B RF Performance Parameter Channel Buffalo-B

(-2dBm) Buffalo-B

(0dBm) Buffalo-B

(8dBm) CH 0(2402MHz) CH 19(2440MHz) CH 39(2480MHz) CH 0(2402MHz) CH 19(2440MHz) CH 39(2480MHz) CH 0(2402MHz) CH 19(2440MHz) CH 39(2480MHz) AVG Output Power(dBm)

-3.21

-3.52 Frequency Accuracy

(KHz) 2401.734 2439.734 RX Sensitivity

(PER<30.8)

-85dBm

-85dBm 2479.734 2401.734 2439.734 2479.734 2401.734 2439.734 2479.734

-84dBm

-85dBm

-85dBm

-84dBm

-85dBm

-85dBm

-84dBm

-3.80

-0.79

-1.11

-1.34 7.64 7.77 7.74

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All rights reserved Suzhou Pairlink Network Technology Co., Ltd. Buffalo-B Spec 3.3.1. PCB-Antenna Characteristics Figure 2: Antenna Characteristics Radiation Pattern and Gain were dependent on measurement Buffalo-B PCB design. Figure 3: E1 plane All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec Figure 4: E2 Plane All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec Figure 5: H Plane Figure 6: X-Y scheme

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All rights reserved Suzhou Pairlink Network Technology Co., Ltd. Buffalo-B Spec All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.4. Power Management The Buffalo-B integrates both a low dropout voltage regulator (LDO) and a step-down DC-DC converter to supply the internal Buffalo-B circuitry. The Buffalo-B most efficient power management configuration is with DC-DC converter active where best power consumption is obtained without compromising performances. Nevertheless, a configuration based on LDO can also be used, if needed. A simplified version of the state machine is shown below. Figure 7: Buffalo-B Power Management State Machine 3.4.1. States Description 3.4.1.1 Preactive State The preactive state is the default state after a POR event. In this state:

All the digital power supplies are stable. The high frequency clock runs on internal fast clock RC oscillator (16 MHz). The low frequency clock runs on internal RC oscillator (32.768 kHz). 3.4.1.2 Active State In this state:

The high frequency runs on the accurate clock (16 MHz 50 ppm) provided by the external XO. The internal fast clock RO oscillator is switched off. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.4.1.3 Standby State In this state:

Only the digital power supplies necessary to keep the RAM in retention are used. The wake-up from this low power state is driven by the following sources:

IO9 IO10 IO11 IO12 IO13 If they have been programmed as wake-up source in the system controller registers. 3.4.1.4 Sleep State In this state:

Only the digital power supplies necessary to keep the RAM in retention are used. The low frequency oscillator is switched on. The wake-up from this low power state is driven by the following sources:

IO9 IO10 IO11 IO12 IO13 If they have been programmed as wake-up source in the system controller registers and from the internal timers of the BLE radio. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.5. Buffalo-B Power-On Sequence Buffalo-B is provided with an automatic Power-On Reset (POR) circuit which is designed to generate a RESETN active (low) level for a time TRESET after the VBAT reaches the Reset Release Threshold voltage VRRT, as shown in Figure 3. Figure 8: Power-On Sequence The parameters VRRT and TRESET are fixed by design in order to guarantee a reliable reset procedure of the state machine. Typical and extreme values are reported in Table 10. Table 10: Reset Characteristics 3.5.1. Buffalo-B Transition Time Figure 9:Buffalo-B Transition Time All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 3.6. Reset Management Figure 5: "Reset and Wakeup Generation" shows the general principle of reset. Releasing the Reset pin puts the chip out of shutdown state. The wakeup logic is powered and receives the POR. Each time the wake-up controller decides to exit sleep or standby modes, it will generate a reset for the core logic. The core logic can also be reset by:

Watchdog Reset request from the processor (system reset) LOCKUP state of the Cortex-M0. The SWD logic is reset by the POR. It is important to highlight that reset pin actually power down chip, so it is not possible to perform debug access with system under reset. Figure 10: Reset and Wakeup Generation All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4. Functional Details 4.2. ADC 4.1.1. Introduction The Buffalo-B integrates a 10-bit Analog-to-Digital Converter (ADC) for sampling an external signal. Main features are:

Sampling frequency 1 MHz One channel in single ended or differential input through the pins ADC1 and ADC2 Battery level conversion The conversion are either continuous or single step acquisition An integrated digital filter is used to process a PDM data stream from a MEMS microphone 4.1.2. Functional Overview The Figure 6 below shows a top diagram of the ADC. Figure 11: Block Diagram of ADC All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec Several channels are available for conversion, the CHSEL selects the channel according to Table 11 Table 11: ADC Channels The conversion can be single (CONT = 0) or continuous (CONT = 1). In continuous mode, the conversion runs with a preprogrammed sampling rate, while in single step mode the ADC performs a conversion and then stops. The output data rate depends on DECIM_RATE according to the table below. Table 12: ADC data rate DECIM 0(2000) 1(100) 2(64) 3(32) Output data rate[Ksample/s]

5 10 15.625 31.25 All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.1.2.1. ADC Start Conversion The ADC both analog and digital sub-system are switched on by setting ADCON and SWSTART. The conversion operation consists of four phases. 1. The wake-up phase lasts 5 us, is present at the beginning of a single acquisition, with the goal to let the analog system to settle before to start the acquisition. 2. If the CALEN is set, a calibration phase is performed. It permits to compensate the offset in the analog part. The conversion status is tracked by SR status register. At the beginning of the conversion the BUSY bit is set and masks any attempt to change CONF, up to the end of the conversion. At end of this conversion, the ENDCAL flag is generated and the OFFSET register is written with the converted offset voltage. 3. The acquisition phase is regulated by a timeout depending on the resolution. In this phase, digital filter chain processes the data coming from ADC. 4.1.2.2 ADC Offset The ADC can correct automatically the offset and the gain error. To enable the automatic offset correction the CALEN and the OFFSET_UPDATE must be set. The result of the last calibration is stored in the OFFSET register. The correction of the offset can be also done manually, for example by making a conversion of the internal channel InP = InN = 0.6 V and after that, writing the result of conversion in the OFFSET register. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.2. UART 4.2.1. Introduction The Buffalo-B integrates a universal asynchronous receiver/transmitter that support much of the functionality of the industry-standard 16C650 UART. Main features are:

Programmable baud rates up to 2 Mbps. Programmable data frame of 5, 6, 7 or 8 bits of data. Even, odd, stick or no-parity bit generation and detection. Programmable 1 or 2 stop bit. Support of hardware flow control using CTS and RTS pins. Support of software flow control using programmable Xon/Xoff characters False start bit detection. Line break generation and detection. Programmable 8-bit wide, 64-deep transmit FIFO and 12-bit wide (8-bit data and 4-bit status) , 64-deep receive FIFO. Support for Direct Memory Access (DMA). 4.2.2. Functional Description The UART performs serial-to-parallel conversion on data asynchronously received from a peripheral device on the UART_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on the UART_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte with 4-bit status

(break, frame, parity, and overrun) for receive. FIFOs may be burst-loaded or emptied by the system processor from 1 to 16 words per transfer. 4.2.2.1. Data Transmission or Reception Data received or transmitted is stored in two 64-byte FIFOs. The receive FIFO has an extra four bits per character for the status information:

Error bits 8 to 10 are associated with a particular character: break error, parity error and framing error. Overrun indicator bit 11 is set when the FIFO is full, and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character is received, the state of the overrun bit is copied into the received FIFO along with the received character. The overrun state is then cleared. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec Table 13: RX FIFO errors For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in LCRH_TX. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY flag in the UARTFR register is set as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted while data is being transmitted. BUSY is cleared only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be set even though the UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined, and one sample is taken either side of it. When the receiver detect a start bit, the receive counter runs and data is sampled on the 8th cycle of that counter in normal UART mode. The start bit is valid if UART_RX signal is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit is valid, successive data bits are sampled on every 16th cycle of Baud16 (that is 1-bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Lastly, a valid stop bit is confirmed if UART_RX signal is high, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that. The UART character frame is shown in Figure 7: "UART character frame" below. Figure 12: UART Character Frame All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.3. SPI 4.3.1. Introduction The Buffalo-B integrates a serial peripheral interface compatible with Motorola standard. Main features are:

Maximal supported baud rate is 1 MHz in slave mode and 8 MHz in master mode. Parallel-to-serial conversion on data written to an internal 32-bit wide, 16-location deep transmitter FIFO. Serial-to-parallel conversion on received data, buffering in a 32-bit wide 16-location deep receive FIFO. Programmable data frame size from 4-bit to 32-bit. Programmable clock bit rate and prescaler. Programmable clock phase and polarity in SPI mode. Support for Direct Memory Access (DMA). 4.3.2. Functional Overview The SPI performs serial-to-parallel conversion on data received from a peripheral device on the SPI_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on the SPI_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 x 32-bit values to be stored independently in both transmit and receive modes. FIFOs may be burst-loaded or emptied by the system processor or by the DMA, from one to eight words per transfer. Each 32-bit word from the system fills one entry in FIFO. The SPI includes a programmable bitrate clock divider and prescaler to generate the serial output clock signal from the SPI_CLK pin. 4.3.2.1. Procedure for Enabling SPI The SPI initialization procedure is the following (assuming clocks already enabled):

1. Clear the SSE bit in the CR1 register. This step is not required after a hardware or software Reset of the Buffalo-B. 2. Empty the receive FIFO. This step is not required after a hardware or software Reset of the device Buffalo-B. 3. Program IO_MODE to route SPI port signals on those GPIOs. See Section GPIO operating modes. 4. Program the SPI clock prescaler register (CPSR), then program the configuration registers CR0 and CR1. 5. The transmit FIFO can optionally be filled before enabling the SPI. 6. Set the SSE bit to enable SPI operation. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.3.2.2. SPI bit Rate Generation The SPI bitrate is derived by dividing down the peripheral clock (CLK) by an even prescaler value CPSDVSR from 2 to 254, the clock is further divided by a value from 1 to 256, which is 1+SCR. The SPI frequency clock duty cycle is always 0.5. 4.3.2.3. SPI Data Endianness All transfers can be sent and received with configurable endianness according the setting of the

(T/R)ENDN bit in the CR1 registers. The cases "00b" and "11b" of TENDN and RENDN are implemented for data frame size from 4- to 32-bit. The cases "01b" and "10b" of TENDN and RENDN are implemented only for the following data frame sizes: 16-bit, 24-bit and 32-bit. Transmit data endianness:

TENDN in CR1:

Table 14: SPI TX Endianness Table 15: SPI RX Endianness All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.4. IIC 4.4.1. Introduction The Buffalo-B integrates two I2C controllers. The I2C controller is an interface designed to support the physical and data link layer according to the I2C standard revision 3.0 and provides a low-cost interconnection between ICs. Main features are:

Up to 400 Kb/s in fast mode and up to 100 Kb/s in standard mode. Operating modes supported are master mode, slave mode, master/slave mode for multi-master system with bus arbitration. Programmable 7-bit or 10-bit addressing (also with combined formats). Programmable start byte procedure. 16-byte depth RX FIFO and 16-byte depth TX FIFO. Spike digital filtering on the SDA and SCL lines. Control timing constraint defined by the I2C standard. Support for Direct Memory Access (DMA). 4.4.2. Functional Description Two wires, serial data (SDA) and serial clock (SCL) carry information between the devices connected to the bus. Each device has a unique address and can operate as either a transmitter or receiver, depending on the function of the device. A master is the device that initiates a data transfer on the bus and generates the clock signal. Any device addressed is considered at that time a slave. The I2C bus is a multi-master bus where more than one device is capable of controlling the bus. This means that more than one master could try to initiate a data transfer at I2C the same time. The arbitration procedure relies on the wired-AND connection of all interfaces to the I2C bus. If two or more masters try to put information onto the bus, the first to produce a one when the other produces a zero will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line. Generation of clock signals on the I2C bus is always the responsibility of master devices; each master generates its own clock signals when transferring data to the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line, or by another master when arbitration occurs. Two modes:

Standard mode with bit rate up to 100 Kb/s Fast mode with bit rate up to 400 Kb/s All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 4.4.2.1. IIC Configuration Following a Reset, the I2C logic is disabled and must be configured when in this state. The control register (CR) and baud rate register (BRCR) need to be programmed to configure the following parameters of the peripheral:

Master or slave. 7- or 10-bit addressing mode Speed mode Clock rate Then, if in master mode, the MCR register is used to define the transaction:

Read or write. Slave addresses (7- or 10-bit) to communicate with. Addressing a 7- or 10-bit slave address. Stop condition, to generate a stop or restart condition at the end of the transaction (for consecutive transactions). Transaction length All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 5. Reference Design The most recent schematic and design example, bill of material, and layout file are available from Pairlink Network Technology Co., Ltd. Contact us for details. Figure 13: Module Reference Design Circuit Description:

1: If the HW IIC function is selected, external pull-up resistors are needed. 2: Pin12(ADC1) and Pin13(ADC2) are ADC sampling interface. 3: There are two ways can wakeup module when Buffalo in deep sleep mode. A). Wakeup from IO9, IO10, IO11, IO12, IO13. B). Wakeup from internal timer: BLE timer 1 or BLE timer 2. 4: GPIO12 and GPIO13 are OD structure, needs to add pull-up resistor when use. 5: DIO7 multiplexing BOOT function. Buffalo will into BOOT mode when user pull-up DIO7 at power on. 6: Pin22 and Pin23 multiplexing for hardware PWM function.when user to use PWM interface and SPI interface at the same time,ask Pairlink to get a reasonable configuration.

* 7: Section A:If the RTC function is selected, external 32.768K Crystal is needed

* 8: Section B:Battery Detect.

* 9: Section C:Interface J1 for debugging, user can select and reserve.

* 10: Section D:If the noise of power is big, a external electrolytic capacitor(22uF) is needed. 11: Pin RESET_L vacant or connect to the host.Don't be an external capacitor and resistor. All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 6. Appearance and Dimensions Figure 9 shows the size of the module.The components and prominent structure are not allowed put in this size range(20.5mm*14.0mm*2.40mm), Figure 14: Module Appearance All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 7. Recommended Land Pattern The following land pattern size is recommended for user board design. However, user can modify it according PCB soldering conditions. Sufficient examination is necessary if use the modified land pattern. Figure 15: Mechanical Information All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 8. Module Layout Guideline The layout on user PCB should be designed according to the following guidelines. Figure 16: Module Placement All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 9. Packing Information 9.1. Rolling Information All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 9.2. Master Carton Information ROHS All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 9.3. Label Information A) Label on module B) Label on vacuum bag C) Label on box All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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Buffalo-B Spec 10. Standard Operation Procedure (SOP) All rights reserved Suzhou Pairlink Network Technology Co., Ltd.

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This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Caution: Any changes or modifications to this device not explicitly approved by manufacturer could void your authority to operate this equipment. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. The device has been evaluated to meet general RF exposure requirement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.

2023-03-02 Nemko Canada Inc 303 River Road Ottawa, Ontario, Canada K1V 1H2 Attn: Director of Certification Authority to Act as Agent On our behalf, I appoint Shenzhen Alpha Product Testing Co., Ltd. Address: Building i, No.2, Lixin Road, Fuyong Street, Baoan District, 518103, Shenzhen, Guangdong, China

(Name and addressperson). to act as our agent in Person: Mark Zhu the preparation of this application for equipment certification. I certify that submitted documents properly describe the device or system for which equipment certification is sought. I also certify that each unit manufactured, imported or marketed, as defined in the Federal Communications Commissions regulations will have affixed to it a label identical to that submitted for approval with this application. For instances where our authorized agent signs the application for certification on our behalf, I acknowledge that all responsibility for complying with the terms and conditions for certification, as specified by Nemko Canada Inc, still resides with Scangrip A/S. Address: Rytterhaven 9, DK-5700 Svendborg. (Applicant name and address). Signature:

Name Position Company Name Address Tel Fax Email Jasar Elezaj Quality Manager Scangrip A/S Rytterhaven 9, DK-5700 Svendborg

+45 6320 6320

+45 6320 6321 je@scangrip.com

2023-03-02 Equipment Autorisation Division Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 FCC ID: 2ATYV-B102802 Product Name: Bluetooth module Request for Confidentiality Pursuant to Sections 0.457 and 0.459 of the commissions rules, we hereby request that the following documents be held confidential:

Schematics Long-term confidential Block diagram Long-term confidential Operation description Long-term confidential These materials contain trade secrets and proprietary information and are not customarily released to the public. The public disclosure of this information might be harmful to the company and provide unjustified benefits to our competitors. Signature:

Name Position Company Name Address Tel Fax Email Jasar Elezaj Quality Manager Scangrip A/S Rytterhaven 9, DK-5700 Svendborg

+45 6320 6320

+45 6320 6321 je@scangrip.com

SCANGRIP A/S Covered Equipment Certification Attestation Letter 3/2/2023 Nemko North America, Inc. 303 River Road Ottawa K1V 1H2 Canada ATTN.: Reviewing Engineer FCC ID: 2ATYV-B102802 SCANGRIP A/S(the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Note: If the equipment for which the applicant seeks authorization is produced by any of the entities identified on the current Covered List, the applicant should include an explanation on why the equipment is not covered equipment. SCANGRIP A/S(the applicant) certifies that, as of the date of the filing of the application, the applicant is not identified on the Covered List as an entity producing covered equipment. Signed:

Printed name: Mr. Jasar Elezaj Title: Quality Manager Company Name: SCANGRIP A/S Date: 3/1/2023

Scangrip A/S Rytterhaven 9, DK-5700 Svendborg We Scangrip A/S declare that this EUT (FCC ID: 2ATYV-B102802) doesnt have Ad Hoc Mode function on "non-US/Canada frequencies". In addition, the frequency selection feature is disabled by firmware for devices marketed to the US/Canada. For DTS part of this device, only channels 140 will be used in North America. Country code selection is disabled. DateMarch 2, 2023 Should you have any questions or comments regarding this matter, please have my best attention. Sincerely yours, Signature:

Name Position Jasar Elezaj Quality Manager Company Name Scangrip A/S Address Rytterhaven 9, DK-5700 Svendborg Tel Fax Email

+45 6320 6320

+45 6320 6321 je@scangrip.com

FCC Modular Approval Request To the FCC or FCC TCB handling this application Hereby we, Company (grantee) Scangrip A/S Addresss Rytterhaven 9, DK-5700 Svendborg City / ZIP / State / Country Denmark request modular approval for the certification of our equipment within this application, identified by:

FCC ID:

2ATYV-B102802 The table below contains justification for modular approval of this equipment. Requirement per DA 00-1407 1. The modular transmitter must have its own RF shielding. 2.The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with Part 15 requirements under conditions of excessive data rates or over-modulation. 3. The modular transmitter must have its own power supply regulation. Explanation from grantee Has RF shielding. The modular have buffered modulation/data inputs. The modular transmitter have its own power supply regulation. 4.The modular transmitter must comply with the antenna requirements of Section 15.203 and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable).. This module is equipped with a PCB antenna, please refer to the External Photo for the detail. 5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. 6. The modular transmitter must be labeled with its own FCC ID number, and, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: ?????????? or Contains FCC ID: 2ATCG-BB810QI4A Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization. 7. The modular transmitter must comply with any specific rule or operating requirements applicable to the transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. For example, there are very strict operational and timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. 8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimetre wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance in accordance with Section 15.247(b)(4). Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. Attestation (by grantee) City and Country:

Function:

Date:

Name:

(this must be a person) The module was tested in a stand-alone configuration, please refer to the Setup Photo for the detail Please refer to label sample exhibit - host labeling is described in integration manual The required FCC rule has been fulfilled and all the instructions for the maintaining compliance have been clearly stated in the User Manual. The MPE evaluation with 20cm distance restriction is submitted for the compliance of RF Exposure requirement. Signature:

(or official company stamp) DK-5700 Svendborg, Denmark 2023.03.02 Jasar Elezaj Quality Manager

SCANGRIP A/S U.S. Agent Designation for Service of Process -

Certification Attestation Letter 2/20/2023 Nemko North America, Inc. 303 River Road Ottawa K1V 1H2 Canada ATIN.: Reviewing Engineer FCC ID: 2ATYV-B102802 Per section 2.911(d)(7) of the FCC rules, SCANGRIP A/S(the applicant) certifies that the equipment for which authorization is sought is designated to the following U.S. agent* for service of process:

Company Name: SCANGRIP North America Inc. Physical U.S. Company Address: 1201 Peachtree Street NE Ste 100 USA-30361 Atlanta, Georgia Agent contact name/Title: Mr. Mathias Nielsen, Area Sales Manager Agent Email Address: mn@scangrip.com Tel No.: (+1) 310 8665607 FRN No.: 0033472689 The above contact person accepts the obligation for service of process. The applicant accepts to maintain an agent for no less than one year after the grantee has terminated all marketing and importation or the conclusion of any Commission-related proceeding involving the equipment. licant):

Applicant Signed: Agent Signed (if different to A Signed: QesvEi Signed: Mlb Nip Printed name: Jasar Elezaj Printed name: Mathias Nielsen

. Title: Sales Manager, USA Title: Quality Manager ao Company Name: SCANGRIP A/S Company Name: SCANGRIP North America Inc. Date: 3/13/2023 Date: 3/13/202 the applicant must designate a contact located in the United States for purposes of acting as the applicant's agent for service of process, regardless of whether the applicant is a domestic or foreign entity. An applicant located in the United States may designate itself as the agent for service of process.