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FSC-BT806 Datasheet Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Bluetooth Module Datasheet Version 1.2 FSC-BT806 Datasheet Copyright 2013-2019 Feasycom Technology. All Rights Reserved. Feasycom Technology reserves the right to make corrections, modifications, and other changes to its products, documentation and services at anytime. Customers should obtain the newest relevant information before placing orders. To minimize customer product risks, customers should provide adequate design and operating safeguards. Without written permission from Feasycom Technology, reproduction, transfer, distribution or storage of part or all of the contents in this document in any form is prohibited. Revision History Version Data 2018/05/25 2019/10/22 Notes Initial Version 1. Add Ordering Informationand modify some incorrect descriptions 2. UpdateGeneral Specifications 2020/03/25 Update module picture, block diagram 1.0 1.1 1.2 Devin Wan Devin Wan Devin Wan Contact Us Shenzhen Feasycom Technology Co.,LTD Email: sales@feasycom.com Address: Room 2004-2005,20th Floor,Huichao Technology Building,Jinhai Road, Xixiang ,Baoan District,Shenzhen,518100,China. Tel: 86-755-27924639,86-755-23062695 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Contents 1. INTRODUCTION ............................................................................................................................................................... 5 2. GENERAL SPECIFICATION ................................................................................................................................................. 7 3. HARDWARE SPECIFICATION ............................................................................................................................................. 9 3.2 PIN DEFINITION DESCRIPTIONS ................................................................................................................................................. 9 4. PHYSICAL INTERFACE ..................................................................................................................................................... 12 4.1 POWER MANAGEMENT .......................................................................................................................................................... 12 4.1.1 Power Supply ............................................................................................................................................................ 12 4.1.2Battery Charger ............................................................................................................................................................ 12 4.1.2.1Battery Charger Hardware Operating Modes ........................................................................................................... 12 4.1.2.2 Battery Charger Trimming and Calibration ........................................................................................................... 14 4.1.2.3 VM Battery Charger Control.................................................................................................................................. 14 4.1.2.4 Battery Charger Firmware and PS Keys ................................................................................................................. 14 4.2 RESET ................................................................................................................................................................................. 14 4.2.1Digital Pin States on Reset ........................................................................................................................................... 15 4.2.2Status After Reset ......................................................................................................................................................... 15 4.2.3Automatic Reset Protection ......................................................................................................................................... 15 4.3 GENERAL PURPOSE ANALOG IO ............................................................................................................................................... 16 4.4 GENERAL PURPOSE DIGITAL IO ................................................................................................................................................ 16 4.5 RF INTERFACE ...................................................................................................................................................................... 16 4.6 SERIAL INTERFACES ................................................................................................................................................................ 16 4.6.1 UART Interface ......................................................................................................................................................... 16 4.6.2 I2C Interface .............................................................................................................................................................. 18 4.6.3USB Interface ................................................................................................................................................................ 18 4.7LED DRIVERS .......................................................................................................................................................................... 19 4.8AUDIO INTERFACES ................................................................................................................................................................... 20 4.8.1 Audio Input and Output ........................................................................................................................................... 21 4.8.2 Audio Codec Interface .............................................................................................................................................. 21 4.8.3 Output Stage ............................................................................................................................................................ 29 4.8.4 PCM Controller ......................................................................................................................................................... 29 4.8.5 I2S Controller ............................................................................................................................................................ 34 4.9PROGRAMMING AND DEBUG INTERFACE ....................................................................................................................................... 36 5. ELECTRICAL CHARACTERISTICS ...................................................................................................................................... 37 5.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 37 5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................................................. 37 5.3 INPUT/OUTPUT TERMINAL CHARACTERISTICS .............................................................................................................................. 38 5.3.1 Digital ....................................................................................................................................................................... 38 5.3.2Battery Charger ............................................................................................................................................................ 38 5.3.3USB ............................................................................................................................................................................... 39 5.3.4LED Driver Pads ............................................................................................................................................................ 39 5.4 STEREO CODEC ..................................................................................................................................................................... 40 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 5.4.1 Analogue to Digital Converter .................................................................................................................................. 40 5.4.1 Digital to Analogue Converter .................................................................................................................................. 40 5.5AUXILIARY ADC ....................................................................................................................................................................... 41 5.6AUXILIARY DAC ....................................................................................................................................................................... 41 5.7I2C DYNAMIC CHARACTERISTICS .................................................................................................................................................. 42 5.8PCM DYNAMIC CHARACTERISTICS ............................................................................................................................................... 43 5.9I2S DYNAMIC CHARACTERISTICS .................................................................................................................................................. 44 5.10 POWER CONSUMPTIONS ....................................................................................................................................................... 44 6. MSL &ESDPROTECTION ................................................................................................................................................. 45 6.1USB ELECTROSTATIC DISCHARGE IMMUNITY .................................................................................................................................. 45 7. RECOMMENDED TEMPERATURE REFLOW PROFILE ........................................................................................................ 46 8. MECHANICAL DETAILS ................................................................................................................................................... 47 8.1 MECHANICAL DETAILS ............................................................................................................................................................ 47 9. HARDWARE INTEGRATION SUGGESTIONS ..................................................................................................................... 48 9.1 SOLDERING RECOMMENDATIONS ............................................................................................................................................. 48 9.2 LAYOUT GUIDELINES(INTERNAL ANTENNA)................................................................................................................................. 48 9.3 LAYOUT GUIDELINES(EXTERNAL ANTENNA) ................................................................................................................................ 49 9.3.1 Antenna Connection and Grounding Plane Design ..................................................................................................... 49 10. PRODUCT PACKAGING INFORMATION ......................................................................................................................... 50 10.1 DEFAULTPACKING ................................................................................................................................................................ 50 10.2 PACKING BOX(OPTIONAL) ................................................................................................................................................... 51 11. APPLICATION SCHEMATIC ............................................................................................................................................ 52 11.1APPLICATION CIRCUIT DIAGRAM(DEFAULT) .................................................................................................................................. 52 11.2APPLICATION CIRCUIT DIAGRAM(EARPHONE) ............................................................................................................................... 53 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 1. INTRODUCTION Overview FSC-BT806 is a Bluetooth 5.0 dual-mode module. It provides a Bluetooth Low Energy fully compliant system for audio and data communication with Feasycom stack. FSC-BT806 integrates an ultra-low-power DSP and application processor with embedded flash memory, a high-performance stereo codec, a power management subsystem, I2S,LED drivers and ADC I/O in a SOC IC. The dual-core architecture with flash memory enables manufacturers to easily differentiate their products with new features without extending development cycles. By default, FSC-BT806 module is equipped with powerful and easy-to-use Feasycom firmware. Its easy-to-use and completely encapsulated. Feasycom firmware enables users to access Bluetooth functionality with simple ASCII commands delivered to the module over serial interface -
it's just like a Bluetooth modem. Therefore, FSC-BT806 provides an ideal solution for developers who want to integrate Bluetooth wireless technology into their design. Bluetooth v5.0/4.0/3.0/2.1/2.0/1.2/1.1, Class 1.5 80MHz RISC MCU and 80MIPS Kalimba DSP Stereo codec with 2 channels of ADC and up to 4 microphone inputs (includes bias generators anddigital microphone support) Support for CSRs latest CVC technology for narrow-band and wideband voice connections including wind noise reduction Audio interfaces: IS/PCM and SPDIF Music Enhancements: SBC,MP3,AAC and AAC+,Faststream codec,atpX,5-band EQ,3D stereo separation and so on. Support HSP, HFP, A2DP, AVRCP,PBAP,MAP,SPP,BLE Multipoint support for HFP connection to 2 handsets profile for voice Multipoint support for A2DP connection to 2 A2DP source for music playback 3 Hardware LED controllers(for RGB) UART,I2C,SPI,PIO,AIO,USBcontrol interfaces Postage stamp sized form factor MFI Support Built-in RF combo filter,Built-in PCB antenna to support external antenna Fast charging support up to 200mA with no externalcomponents RoHS compliant Industrial temperature range from -40C to +85C Application Bluetooth headphones Smart remote controllers Wired or wireless sound bars Wired or wireless speakers applications) Stereo (AV) Transmitter Automotive Hands-Free Kits Wearable audio with sensors(health and well-being Features Smart watches&Bluetooth bracelets Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Module picture as below showing Figure 1: FSC-BT806 Picture Ordering Information Device CSR8670 CSR8675 Order Number FSC-BT806A FSC-BT806 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 2. General Specification Table 1:General Specifications Categories Features On-board chip Implementation CSR8670/CSR8675 V5.0 Dual-mode Bluetooth low energy radio Software complies with the Bluetooth Core v5.0 Specification Wireless Specification Bluetooth Low energy Support for Bluetooth basic rate / EDR and low energyConnections 3 Bluetooth low energy connections at the same time asbasic rate A2DP Frequency 2.402 - 2.480 GHz Transmit Power
+10 dBm (Maximum) Receive Sensitivity
-88 dBm(Typical) Raw Data Rates (Air) 3 Mbps(Classic BT - BR/EDR) Real-time digitised RSSI available to application Host Interface and Peripherals UART Interface GPIO I2C Interface SPI Interface TX, RX, CTS, RTS General Purpose I/O Default 115200,N,8,1 Baudrate support from 1200 to 921600 8 data bit character 23(maximum configurable) lines O/P drive strength (4 mA) Pull-up resistor (33 K) control Read pin-level 1 (hardware I2C interface). Up to 400 kbps Master and slave I2C interface SPI debug and programming interface with read accessdisable locking Analog input voltage range: 0~ 1.3V ADC Interface Supports single a 10-bit ADC and a 10-bit DAC 1 channels (configured from GPIO total) USB Interface 1 full-speed (12Mbps) 80MHz RISC MCU and 80MIPS Kalimba DSP Digital parameters--CSR8670 audio 16-bit audio Digital parameters--CSR8675 audio 24-bit audio Supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1,48 and 96kHz (DAC only) 80 MHz RISC MCU and 120 MHz Kalimba DSP Up to 120MIPS DSP for intensive digital signal processing algorithms Supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1,48,96kHz and 192kHz (DAC only) SPP (Serial Port Profile) - Up to 600 Kbps A2DP/AVRCP/HFP/HSP/HID/PBAP/SPP Profiles support Profiles BR/EDR Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Bluetooth Low Energy GATT Client & Peripheral - Any Custom Services Simultaneous BR/EDR and BLE support BR/EDR up to 7 active slaves Bluetooth Low Energy 1 connection as peripheral , up to 5 connections as central Supply Voltage Supply VDD_IO: 1.7 ~ 3.6V; VBAT_IN: 2.8V~ 4.3V Power Consumption Standby Doze (Waitevent) - <1mA (TBD) Max Peak Current(TX Power @ +10dBm TX): 85mA Physical Dimensions 13mm(W) X 26.9mm(L) X 2.2mm(H); Pad Pitch 1mm Via UART USB SPI Deep Sleep - ~300uA(TBD)
-40C to +85C
-40C to +105C Lead-free and RoHS compliant One Year 10% ~ 90% non-condensing MSL 3 (With JEDEC J-STD-020) Human Body Model: Class-2 Machine Model: Class-200V Charged Device Model: ClassII FSC-BT806 Datasheet Maximum Connections FW upgrade Operating Storage Lead Free Warranty Environmental Miscellaneous Humidity MSL grade:
ESD grade:
Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 3. HARDWARE SPECIFICATION Figure 3: FSC-BT806 PIN Diagram(Top View) 3.2 PIN Definition Descriptions Table 2:Pindefinition Pin Pin Name 1 GND 2 3 4 AIO0 AIO1 I2S_CLK Type Pin Descriptions Power Ground Vss I/O I/O I/O Analogue 1 programmable input/output line. Analogue 2 programmable input/output line. I2S/PCM synchronous data clock. Alternative Function: Programmable input/output line Notes Note 8 Note 8 Note 6 Note 6 5 I2S_IN I/O I2S/PCM synchronous data input. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 GND AIO0 AIO1 I2S_CLK I2S_IN I2S_OUT I2S_WS RESET SPI_CSB SPI_MOSI SPI_MISO SPI_CLK BT_TX BT_RX BT_CTS BT_RTS LED0 LED1 LED2 PIO0 PIO1 GND EXT_ANT GND SPK_LP SPK_LN SPK_RP SPK_RN MIC_L_BIAS MIC_LN MIC_LP MIC_R_BIAS MIC_RN MIC_RP VCC_CHG USB_DN USB_DP VDD_IO 1.8V_OUT VREGENABLE VBAT_IN GND 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
. T U O _ V 3 3
B S U _ D D V D N G 2 O P I 3 O P I 4 O P I 5 O P I 6 O P I 7 O P I 4 1 O P I 5 1 O P I 22 23 24 25 26 27 28 29 30 31 27 FSC-BT806 Datasheet 6 I2S_OUT 7 I2S_WS 8 RESET 9 10 11 12 SPI_CSB SPI_MOSI SPI_MISO SPI_CLK 13 BT_TX 14 BT_RX 15 BT_CTS 16 BT_RTS 17 18 19 20 21 23 24 25 26 27 LED0 LED1 LED2 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 28 PIO7 29 30 PIO14 PIO15 32 GND 33 VBAT_IN 34 VREGENABLE 35 1.8V_OUT 36 VDD_IO 37 USB_DP Alternative Function: Programmable input/output line I2S/PCM synchronous data output. Alternative Function: Programmable input/output line I2S/PCM synchronous data sync. Alternative Function: Programmable input/output line External reset input: Active LOW, with an inter an internal pull-up. Set this pin low reset to initial state. (>5mS) Chip select for SPI, active low.(Debug) SPI data input. (Debug) SPI data output. (Debug) SPI clock. (Debug) UART Data output Alternative Function: Programmable input/output line UART Data input Alternative Function: Programmable input/output line UART clear to send, active low. Alternative Function: Programmable input/output line UARTrequest to send, active low. Alternative Function: Programmable input/output line LED driver. (RED LED) LED driver. (BLUE LED) LED driver. (GREEN LED) Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Alternative Function:I2C_SCL Programmable input/output line Alternative Function:I2C_SDA Programmable input/output line Programmable input/output line Power Ground Note 6 Note 6 Note6 Note 6 Note6 Note 6 Note 6 Note 6 Note 6 Note 5 Note 5 Note 3 Note 1 Note 2 Note 4 I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Vss I/O I/O I/O I/O I/O I/O I/O I/O Vdd Vss Vdd I Vdd Vdd I/O 31 VDD_USB/3.3V_OUT Positive supply for USB ports/ 3.3V bypass linear regulator output Note 7 Power supply voltage 2.8V~ 4.3V(Battery positive terminal) Power enable
* The PIN on electricity than VBAT_IN and VDD_IO foot 100 ms delay. 1.8V switch-mode power regulator output Power supply voltage 1.7V ~ 3.6V (for input/output ports) USB data positive Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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22 GND Power Ground Note 4 Note 4 42 MIC_R_BIAS O Microphone R bias 45 MIC_L_BIAS O Microphone L bias I/O Vdd USB data negative Battery charger input (5V) Microphone input positive, right Microphone input negative, right I I I I O O O O Vss RF Vss Microphone input positive, left Microphone input negative, left Speaker output negative, right Speaker output positive, right Speaker output negative, left Speaker output positive, left Power Ground Power Ground FSC-BT806 Datasheet 38 USB_DN 39 VCC_CHG 40 MIC_RP 41 MIC_RN 43 MIC_LP 44 MIC_LN 46 47 48 49 SPK_RN SPK_RP SPK_LN SPK_LP 50 GND 51 EXT_ANT 52 GND Module Pin Notes:
Note 1 Bluetooth 50transmitter output /receiver input Note 9 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 The internal output of 1.8 V power supply provides maximum 30MA current, and the specific use method can see the application circuit diagram Provid voltage reference to I/O, such asPIO, UART, SPI, I2S, PCM,etc Regulator enable input.Can also be sensed as an input. Regulator enable and multifunction button. A high input (tolerant to VBAT) enables the on-chip regulators, which can then be latched on internally and the button used as a multifunction input.
* The PIN on electricity than VBAT_IN and VDD_IO foot 100 ms delay. Using USB function and Lithium battery charging function, the pin should connect 5V voltage I2C Serial Clock and Data. It is essential to remember that pull-up resistors on both SCL and SDA lines are not provided in the module and MUST be provided external to the module. For customized module, this pin can be work as I/O Interface. 1, When you need to use the USB function, this pin needs to be connected to 3.3V (voltage range: 3.1V~3.6V) 2, when the No. 39 PIN (VCC_CHG) with a 5V input pin, this pin outputs 3.2V ~ 3.4V (maximum current: 250mA) Analog input voltage range: 0~ 1.3V By default, this PIN is an empty feet. This PIN can connect to an external antenna to improve the Bluetooth signal coverage. If you need to use an external antenna, by modifying the module on the 0R resistance to block out the on-board antenna; Or contact Feasycom for modification. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 4. PHYSICAL INTERFACE 4.1 Power Management 4.1.1 Power Supply The transient response of the regulator is important. If the power rails of the module are supplied from an external voltage source, the transient response of any regulator used should be 20s or less. It is essential that the power rail recovers quickly. 4.1.2Battery Charger 4.1.2.1Battery Charger Hardware Operating Modes The default mode for the FSC-BT806 battery charger is OFF. The internal charger circuit can provide up to 200mA of charge current. Disabled Trickle charge Error: charging input voltage, VCHG, is too low Fast charge Standby: fully charged or float charge The battery charger hardware is controlled by the VM, see picture below.The battery charger has 5 modes:
The battery charger operating mode is determined by the battery voltage and current, see the table below and the picture below. Table 3: Battery Charger Operating Modes Determined by Battery Voltage and Current Battery Charger Enabled VBAT_SENSE(internal) Parameter Off Trickle charge Fast charge Standby Error No Yes Yes Yes Yes X
>0 and <Vfast
>Vfast and <Vfloat
(a) and >(Vfloat - Vhyst) Iterm
>(VCC_CHG - 50mV)
(a)Iterm is 10% of Ifast for a given Ifast setting The picture belowshows the mode-to-mode transition voltages. These voltages are fixed and calibrated. The transition between modes can occur at any time. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Figure 4:Battery Charger Mode-to-Mode Transition Diagram In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals. In the trickle charge mode, when the voltage on VBAT_SENSE is lower than the Vfastthreshold, a current of approximately 10% of the fast charge current, Ifast, is sourced from the VBAT_IN pin. The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes. Disabled Mode Trickle Charge Mode Fast Charge Mode When the voltage on VBAT_SENSE is greater than Vfast, the current sourced from the VBAT pin increases to Ifast. Ifast is between 10mA and 200mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to correct for process variation in the charger circuit. The current is held constant at Ifast until the voltage at VBAT_SENSE reaches Vfloat, then the charger reduces the current sourced to maintain a constant voltage on the VBAT_SENSE pin. When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standby mode. Iterm is typically 10% of the fast charge current. Standby Mode When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltageon the VBAT_SENSE pin is monitored, and when it drops below a threshold set at Vhyst below the final chargingvoltage, Vfloat, the charger re-enters fast charge mode. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Error Mode The charger enters the error mode if the voltage on the VCC_CHG pin is too low to operate the charger correctly(VBAT_SENSE is greater than VCC_CHG - 50mV (typical)). In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation. 4.1.2.2 Battery Charger Trimming and Calibration The battery charger default trim values are written into internal flash when each IC is characterised. Please contact Feasycom regarding to PS keys. 4.1.2.3 VM Battery Charger Control The VM charger code has overall supervisory control of the battery charger and is responsible for:
Responding to charger power connection/disconnection events Monitoring the temperature of the battery Monitoring the temperature of the die to protect against silicon damage Monitoring the time spent in the various charge states Enabling/disabling the charger circuitry based on the monitored information Driving the user visible charger status LED(s) 4.1.2.4 Battery Charger Firmware and PS Keys The battery charger firmware sets up the charger hardware based on the PS Key settings and call traps from the VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery capacity and type, which are set by the user in the PS Keys. 4.2 Reset FSC-BT806 is reset from several sources:
RST# pin Power-on reset USB charger attach reset UART break character Software configured watchdog timer The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. Feasycomrecommends applying RST# for a period >5ms. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate. Following a reset,FSC-BT806 assumes the maximum XTAL_IN frequency, which ensures that the internal clocks run at a safe(low) frequency until FSC-BT806 is configured for the actual XTAL_IN frequency. If no clock is present atXTAL_IN, the oscillator in FSC-BT806 free runs, again at a safe frequency. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a period greater than 5ms. At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The PIOs have weak pull-ups. This table shows the pin states of FSC-BT806 on reset. PU and PD default to weak values unless specifiedotherwise. 4.2.1Digital Pin States on Reset Table 4: Pin States on Reset Pin Name/Group USB_DP USB_DN BT_TX BT_RX BT_CTS BT_RTS SPI_CSB SPI_CLK SPI_MISO SPI_MOSI RESET I2S_IN I2S_OUT I2S_WS I2S_CLK RESET I/O Type Digitalbidirectional Digitalbidirectional Digitalbidirectional with PU Digitalbidirectional with PU Digital bidirectional with PD Digitalbidirectional with PU Digital input with PU Digital input with PD Digital tristate output with PD Digital input with PD Digital input with PU Digital bidirectional with PD Digital bidirectional with PD Digital bidirectional with PD Digital bidirectional with PD Digital input with PU Full Chip Reset N/A N/A Weak PU Strong PU Weak PD Strong PU Strong PU Weak PD Weak PD Weak PD Strong PU Weak PD Weak PD Weak PD Weak PD Strong PU Weak PD PIO0,1,2,3,4,5,6,7,14,15 Digital bidirectional with PD 4.2.2Status After Reset The status of FSC-BT806 after a reset is:
Warm reset: baud rate and RAM data remain available Cold reset: baud rate and RAM data not available 4.2.3Automatic Reset Protection FSC-BT806 includes an automatic reset protection circuit which restarts/resets CSR8670 WLCSP when anunexpected reset occurs, e.g. ESD strike or lowering of RST#. The automatic reset protection circuit enables resetsfrom the VM without the requirement for external circuitry. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Note:
The reset protection is cleared after typically 2s (1.6s min to 2.4s max). If RST# is held low for >2.4s FSC-BT806 turns off. A rising edge on VREGENABLE or VCC_CHG is requiredto power on FSC-BT806 4.3 General Purpose Analog IO FSC-BT806 has 1 general-purpose analogue interface pins, AIO1, for accessing internal circuitry and controlsignals. Auxiliary functions available on the analogue interface include a 10-bit ADC and a 10-bit DAC. Signalsselectable on this interface include the band gap reference voltage. When configured for analogue signals the voltagerange is constrained by the analogue supply voltage. When configured to drive out digital level signals generatedfrom within the analogue part of the device, the output voltage level is determined by VDD_AUX(internal). 4.4 General Purpose Digital IO 10 lines of programmable bidirectional I/O are available on the FSC-BT806. Some of the PIOs on the FSC-BT806 have alternative functions:
3 digital microphone interfaces for control of up to 3 digital microphones:
Clock on any even PIOs as determined by the software Data on any odd PIOs as determined by the software IC interface on any PIOs as determined by the software LED[2:0] directly map to PO[31:29]
I2S/PCM interface on PIO[20:17]
4.5 RF Interface For this module, the antenna must be connected to work properly. The user can connect a 50ohm antenna directly to the RF port. 24022480 MHz Bluetooth 5.0 Dual Mode (BT and BLE); 1 Mbps to 3 Mbps over the air data rate. TX output power of +10dBm(MAX). Receiverto achieve maximum sensitivity -88dBm @ 1 Mbps BLE or Classic BT, 2 Mbps, 3 Mbps). 4.6 Serial Interfaces 4.6.1 UART Interface FSC-BT806provides one channels of Universal Asynchronous Receiver/Transmitters(UART)(Full-duplex asynchronous communications). The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports ten types of interrupts. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet This is a standard UART interface for communicating with other serial devices. The UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. When the module is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. This module output is at 3.3V CMOS logic levels (tracks VCC). Level conversion must be added to interface with an RS-232 level compliant interface. Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend linking CTS and RTS except for testing and prototyping. If these pins are linked and the host sends data when the FSC-BT806 deasserts its RTS signal, there is significant risk that internal receive buffers will overflow, which could lead to an internal processor crash. This drops the connection and may require a power cycle to reset the module. We recommend that you adhere to the correct CTS/RTS handshaking protocol for proper operation. Table 5: Possible UART Settings Parameter Baudrate Flow control Parity Number of stop bits Bits per channel Minimum Standard Maximum Possible Values 1200 baud (2%Error) 115200bps(1%Error) 4Mbaud(1%Error) RTS/CTS, or None None, Odd or Even 1 /2 8 When connecting the module to a host, please make sure to follow . Figure 5: UART Connection The UART interface resets FSC-BT806 on reception of a break signal. A break is identified by a continuous logic low (0V) on the UART_RX terminal, as belowpicture shows. If t BRK is longer than the value defined by the PSKEY_HOSTIO_ UART _RESET_TIMEOUT, a reset occurs. This feature enables a host to initialise the system toa known state. Also, FSC-BT806 can issue a break character for waking the host. Figure 6: Break Signal Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Module Host TX RX CTS RTS GND RX TX RTS CTS GND The UART interface is tristate while FSC-BT806 is being held in reset. This enables the user to connect otherdevices onto the physical UART bus. The restriction with this method is that any devices connected to this bus musttristate when FSC-BT806 reset is de-asserted and the firmware begins to run. FSC-BT806 Datasheet 4.6.2 I2C Interface FSC-BT806 includes a configurable I2C interface. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the following figure for more details about I2C Bus Timing. Figure 7: I2C Bus Timing The device on-chip I2C logic provides the serial interface that meets the I2C bus standard modespecification. The I2C port handles byte transfers autonomously. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set the pins function to I2C in advance. 4.6.3USB Interface FSC-BT806 has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The USB interface on FSC-BT806 acts as a USB peripheral, responding to requests from a master host controller. FSC-BT806 supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification) and USB Battery Charging Specification , available from http://www.usb.org. For more information on how to integrate the USB interface on FSC-BT806 see the Bluetooth and USB Design Considerations Application Note . As well as describing USB basics and architecture, the application note describes:
Power distribution for high and low bus-powered configurations Power distribution for self-powered configuration, which includes USB VBUS monitoring (when VBUS is>3.1) USB enumeration Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects offerrite beads Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet USB suspend modes and Bluetooth low-power modes:
Global suspend Selective suspend, includes remote wake Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend Suspend mode current draw PIO status in suspend mode Resume, detach and wake PIOs Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration USB termination when interface is not in use Internal modules, certification and non-specification compliant operation 4.7LED Drivers with a current-limiting resistor. FSC-BT806 includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide rangeof colours. All LEDs are controlled by firmware. The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series Figure 8: LED Equivalent Circuit If a known value of current is required throughthe LED to give a specific luminous intensity, then the value of RLED is calculated. For the LED pads to act as resistance, the external series resistor, RLED , needs to be such that the voltage dropacross it, V R , keeps V PAD below 0.5V. ILED=
VDD-VF RLED+RON VDD=VF+VR+VPAD Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Note:
The LED current adds to the overall current. Conservative LED selection extends battery life. 4.8Audio Interfaces The audio interface circuit consists of:
Stereo/dual-mono audio codec Dual analogue audio inputs Dual analogue audio outputs 2 digital MEMS microphone inputs A configurable PCM, IS or SPDIF interface Figure 9: Audio Interface The interface for the digital audio bus shares the same pins as the PCM codec interface described. which means each of the audio buses are mutually exclusive in their usage. Table 6: Alternative functions of the digital audio bus interface on the PCM interface PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK SPDIF Interface SPDIF_OUT SPDIF_IN I2S Interface I2S_OUT I2S_IN I2S_WS I2S_CLK Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 4.8.1 Audio Input and Output The audio input circuitry consists of:
2 independent 16-bit high-quality ADC channels:
Programmable as either microphone or line input Programmable as either stereo or dual-mono inputs Multiplexed with 2 of the digital microphone inputs Each channel is independently configurable to be either single-ended or fully differential Each channel has an analogue and digital programmable gain stage for optimisation of differentmicrophones 2 digital MEMS microphone channels, of which 4 have independent codec channels and 2 share their codecs with the 2 high-quality audio inputs The audio output circuitry consists of a dual differential class A-B output stage. Note:
FSC-BT806 is designed for a differential audio output. If a single-ended audio output is required, use anexternal differential to single-ended converter. 4.8.2 Audio Codec Interface The main features of the interface are:
Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for stereo digital audio bus standards such as IS Support for IEC-60958 standard stereo digital audio bus standards, e.g. SPDIF and AES3 (also known as AES/EBU) Support for PCM interfaces including PCM master codecs that require an external system clock Note:
To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel for audio output. With respect to audio input, software and any registers, channel 0 or channel A represents the left channel and channel 1 or channel B represents the right channel. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Audio Codec Block Diagram Figure 10: Audio Codec Input and Output Stages FSC-BT806 audio codec uses a fully differential architecture in the analogue signal path, which resultsin low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operatesfrom a dual power supply, VDD_AUDIO(internal) for the audio circuits and VDD_AUDIO_DRV (internal)for the audio driver circuits. The picture aboveshows the FSC-BT806 consists of 2 high-quality ADCs Each ADC has a second-order Sigma-Delta converter. Each ADC is a separate channel with identical functionality. There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digitalgain stage ADC Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet ADC Sample Rate Selection Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:
8kHz 11.025kHz 16kHz 22.050kHz 24kHz 32kHz 44.1kHz 48kHz ADC Audio Input Gain The picture below shows that the FSC-BT806 audio input gain consists of:
An analogue gain stage based on a pre-amplifier and an analogue gain amplifier A digital gain stage Figure 11: Audio Input Gain ADC Pre-amplifier and ADC Analogue Gain FSC-BT806 has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:
The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB The ADC analogue amplifier gain is -3dB to 12dB in 3dB steps The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps At mid to high gain levels it acts as a microphone pre-amplifier At low gain levels it acts as an audio line level amplifier ADC Digital Gain A digital gain stage inside the ADC varies from -24dB to 21.5dB, see following table. There is also a fine gain interface with a 9-bit gain setting allowing gain changes in 1/32 steps, for more infomation contact Feasycom. The firmware controls the audio input gain. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Digital Gain Selection ADC Digital Gain Setting(dB) Digital Gain Selection ADC Digital Gain Setting(dB) Value 8 9 10 11 12 13 14 15
-24
-20.5
-18
-14.5
-12
-8.5
-6
-2.5 A long IIR filter suitable for music (>44.1kHz) G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance(which is the best selection for 8kHz / 16kHz / voice) 2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain FSC-BT806 Datasheet Table 7: ADC Audio Input Gain Rate Value 0 1 2 3 4 5 6 7 3.5 0 6 9.5 12 15.5 18 21.5 ADC Digital IIR Filter The ADC contains 2 integrated anti-aliasing filters:
For more information contact Feasycom. DAC The DAC consists of:
DAC Sample Rate Selection Each DAC supports the following sample rates:
functionality stage. 8kHz 11.025kHz 16kHz 22.050kHz 32kHz 40kHz 44.1kHz 48kHz 96kHz Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet DAC Digital Gain A digital gain stage inside the DAC varies from -24dB to 21.5dB, see following table.There is also a fine gain interface with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR. The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and analogue amplifier settings. Table 8: DAC Digital Gain Rate Selection Digital Gain Selection DAC Digital Gain Setting(dB) Digital Gain Selection DAC Digital Gain Setting(dB) Value 3.5 0 6 9.5 12 15.5 18 21.5 0
-3
-6
-9 Value 8 9 10 11 12 13 14 15 3 2 1 0
-24
-20.5
-18
-14.5
-12
-8.5
-6
-2.5
-12
-15
-18
-21 DAC Analogue Gain The following table shows that the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dBsteps. The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue amplifier settings. Table 9: DAC Analogue Gain Rate Selection Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain Value Setting(dB) Value Setting(dB) 0 1 2 3 4 5 6 7 7 6 5 4 DAC Digital FIR Filter The DAC contains an integrated digital FIR filter with the following modes:
A default long FIR filter for best performance at >= 44.1kHz. A short FIR to reduce latency. A narrow FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8kHz / 16kHz. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet IEC 60958 Interface The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimise the DC content of the transmitted signal and enables the receiver to decode the clock information from the transmitted signal. The IEC 60958 specification is based on the 2 industry standards:
AES3 (also known as AES/EBU) Sony and Philips interface specification SPDIF The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4. The SPDIF interface signals are SPDIF_IN and SPDIF_OUT and are shared on the PCM interface pins. The inputand output stages of the SPDIF pins interface to:
A 75 coaxial cable with an RCA connector An optical link that uses Toslink optical components Figure 12: Example Circuit for SPDIF Interface(Co-axial) Figure 13: Example Circuit for SPDIF Interface(Optical) Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Microphone Input Where:
FSC-BT806 contains an independent low-noise microphone bias generator. The microphone bias generator is recommended for biasing electret condensor microphones. Figure 9.6 shows a biasing circuit for microphoneswith a sensitivity between about -40 to -60dB (0dB = 1V/Pa). The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its output. The microphone bias generator maintains regulation within the limits 70uA to 2.8mA, supporting a 2mAsource typically required by 2 electret condensor microphones. If the microphone sits below these limits,then the microphone output must be pre-loaded with a large value resistor to ground. Biasing resistors R1 and R2 equal 2.2k. When the input pre-amplifier is enabled, the input impedance at MIC_LN, MIC_LP, MIC_RN and MIC_RPvaries between 6k(pre-amplifier gain >0dB) and 12k(pre-amplifier gain = 0dB). C1, C2, C3 and C4 are 100/150nF if bass roll-off is required to limit wind noise on the microphone. R1 and R2 set the microphone load impedance and are normally around 2.2k. Figure 14: Microphone Biasing The microphone bias characteristics include:
Power supply:
FSC-BT806 microphone supply is VBAT or 3V3_USB(inernal) Minimum input voltage = Output voltage + drop-out voltage Maximum input voltage is 4.3V 300mV maximum Drop-out voltage:
Output voltage:
Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 1.8V or 2.6V Tolerance 90% to 110%
Output current:
70uA to 2.8mA No load capacitor required Digital Microphone Inputs FSC-BT806 interfaces to 2 digital MEMS microphones. shows that 4 of the inputs have dedicated codec channels and 2 are multiplexed with the high-quality ADC channels. Clock lines shared between 2 microphone outputs, linked to any even-numbered PIO pin as determinedby the firmware. Note:
Multiple digital microphones can share the same clock if they are configured for the same frequency, e.g. 1 clock for 6 digital microphones. Data lines shared between 2 microphone inputs, linked to any odd-numbered PIO as determined by thefirmware. Note:
For the digital microphone interface to work in this configuration ensure the microphone uses a tristatebetween edges. The left and right selection for the digital microphones are appropriately pulled up or down for selection on the PCB. Line Input The picture belowshow 2 circuits for line input operation and show connections for either differential or single-ended inputs. In line input mode, the input impedance of the pins to ground varies from 6kto 34kdepending on input gainsetting. Figure 15: Differential Input Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Figure 16: Single-ended Input 4.8.3 Output Stage The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB outputstage amplifier. The picture below shows that the output is available as a differential signal between SPKR_LN and SPKR_LPfor the left channel, and between SPKR_RN and SPKR_RP for the right channel. Figure 17: Speaker Output 4.8.4 PCM Controller The audio PCM interface on the FSC-BT806 supports:
On-chip routing to Kalimba DSP Continuous transmission and reception of PCM encoded audio data over Bluetooth. Processor overhead reduction through hardware support for continual transmission and reception ofPCM data A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does notpass through the HCI protocol layer. Hardware on the CSR8670 WLCSP for sending data to and from a SCO connection. Up to 3 SCO connections on the PCM interface at any one time. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet PCM interface master, generating PCM_SYNC and PCM_CLK. PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK. Various clock formats including:
Long Frame Sync Short Frame Sync GCI timing environments 13-bit or 16-bit linear, 8-bit -law or A-law companded sample formats. Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC. PCM Interface Master/Slave Figure 18:PCM Interface Master Figure 19:PCM Interface Slave Long Frame Sync Figure 20:Long Frame Sync (shown with 8-bit Companded Sample) Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Short Frame Sync Figure 21: Short Frame Sync (shown with 16-bitSample) Multi-slot Operation Figure 22:Multi Slot Operation with 2 Slots and 8-bit Companded Samples GCI Interface Figure 23:GCI Interface Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Slots and Sample Formats FSC-BT806 receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durationsare either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats. 16 clocks cycles for 8-bit, 13-bit or 16-bit sample formats. FSC-BT806 supports:
13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. A sample rate of 8ksamples/s, 16ksamples/s or 32ksamples/s. Little or big endian bit order. For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or aprogrammable 3-bit audio attenuation compatible with some codecs. Figure 24:16-bit Slot Length and Sample Formats Additional Features FSC-BT806 has a mute facility that forces PCM_OUT to be 0. In master mode, FSC-BT806 is compatiblewith some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Figure 25:PCM Master Timing Long Frame Sync Figure 26: PCM Master Timing Short Frame Sync Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Figure 27: PCM Slave Timing Long Frame Sync Figure 28: PCM Slave Timing Short Frame Sync 4.8.5 I2S Controller The digital audio interface supports the industry standard formats for IS, left-justified or right-justified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. This Table lists these alternative functions. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Table 10: Alternative functions of the digital audio bus interface on the PCM interface PCM Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK I2S Interface I2S_OUT I2S_IN I2S_WS I2S_CLK Figure 29Digital Audio Interface Modes Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet Figure 30Digital Audio Interface Slave Timing Figure 31Digital Audio Interface Master Timing 4.9Programming and Debug Interface Important Note:
The SPI is for programming, configuring (PS Keys) and debugging the FSC-BT806. It is required in production. Ensure the 4 SPI signals are brought out to either test points or a header. Feasycom provides development and production tools to communicate over the SPI from a PC, although a leveltranslator circuit is often required. FSC-BT806 uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when the internal processor is running or is stopped. Data is written or read one word at a time, or the auto-increment feature is available for block access. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 5. ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings Absolute maximum ratings for supply voltage and voltages on digital and analogue pins of the module are listedbelow. Exceeding these values causes permanent damage. The average PIO pin output current is defined as the average current value flowing through any one of thecorresponding pins for a 100mS period. The total average PIO pin output current is defined as the average currentvalue flowing through all of the corresponding pins for a 100mS period. The maximum output current is definedas the value of the peak current flowing through any one of the corresponding pins. Table 11:Absolute Maximum Rating Parameter 5V(VCC_CHG)
+5.75 / 6.50 (a) Min
-0.4 Max Unit V
(a) Standard maximum input voltage is 5.75V, a 6.50V maximum depends on firmware version and implementation of over-temperatureprotection software, for more information contact Feasycom. 5.2 Recommended Operating Conditions Table 12:Recommended Operating Conditions Parameter 4.75 / 3.10 (a) 5.75 / 6.50 (b) Max Unit
-0.4 2.7
-0.4
-0.4
-40
-40 VSS-0.4 VDD+0.4
+4.4
+5.75
+4.4
+3.6
+85
+105 4.30 4.30 4.30 3.6
+85
+85 V V V V V C C V V V V V C C Min 1.10 2.8 0 1.7
-40
-40 Type 5 3.70 3.3 3.3 3.3 25 25 BATTERY(LED 0,1,2) BATTERY(VBAT_IN) BATTERY(VREGENABLE) VDD_IO Other terminal voltages TA - Operating Temperature TST - Storage Temperature 5V(VCC_CHG) BATTERY(LED 0,1,2) BATTERY(VBAT_IN) BATTERY(VREGENABLE) VDD_IO TA - Operating Temperature TST - Storage Temperature
(a) Minimum input voltage of 4.75V is required for full specification, regulator operates at reduced load current from3.1V
(b) Standard maximum input voltage is 5.75V, a 6.50V maximum depends on firmware version and implementation of over-temperatureprotection software, for more information contact Feasycom. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 5.3 Input/output Terminal Characteristics 5.3.1 Digital Table 13: DC Characteristics (VDD - VSS = 3 ~ 3.6 V, TA = 25C) Parameter Input Voltage VIL - Standard IO Low levelinput voltage VIH - Standard IO Low levelinput voltage Tr/Tf Output Voltage VOL - Low Level Output Voltage, IOL=4mA VOH - High Level Output Voltage, IOH=-4mA Tr/Tf 0.7XVDD_IO Input and Tristate Currents Strong pull-up Strong pull-down Weak pull-up Weak pull-down C I Input Capacitance 5.3.2Battery Charger Table 14:Battery Charger Battery Charger Input voltage, VCHG Type Max Unit 0.7XVDD_IO VDD_IO+0.4 Min
-0.4
-150 10
-5 0.33 1.0 8
-40 40
-1.0 1.0 10 2.9 0.1 2.8 200 10 V V nS V V nS uA uA uA uA pF V
V V V 0.4 25 0.4
5
-10 150
-0.33 5.0 5.0
12 Parameter Min Type Max Unit
(a)Reduced specification from 3.1V to 4.75V. Full specification >4.75V.
(b) Standard maximum input voltage is 5.75V, a 6.50V maximum depends on firmware version and implementation of over-temperatureprotection software, for more information contact Feasycom. 4.75 / 3.10(a) 5.00 5.75 /6.50(b) Trickle Charge Mode Charge current Itrickle, as percentage of fast charge current Vfast rising threshold Vfast rising threshold trim step size Vfast falling threshold Fast Charge Mode Charge current during constantcurrent mode, Ifast Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Max, headroom >0.55V Min, headroom >0.55V 194 206 mA mA FSC-BT806 Datasheet Mid, headroom =0.15V 50 Reduced headroom charge current,as a percentage of Ifast Charge current step size Vfloat threshold, calibrated Charge termination current Iterm, as percentage of Ifast 10 4.20 10 100
4.24 20
mA V
150 mV 50 mV
V V V V
Min Type Max 0.55 5 10 40 Unit uA mA V 4.16 100
7
0 2.8
3V3_USB for correct USB operation(internal) Parameter Min 3.10 Type 3.30 Max 3.60 Unit V 0.7X3V3_USB 0.3X3V3_USB 0.2 3V3_USB Output Voltage Levels to Correctly Termlnated USB Cable VOL - output logic level low VOH - output logic level high Standby Mode Voltage hysteresis on VBAT_IN, Vhyst Error Charge Mode Headroom(a) error falling threshold
(a) Headroom = VCC_CHG VBAT_IN 5.3.3USB Table 15:USB Input Threshold VIL - input logic level low VIH - input logic level high 5.3.4LED Driver Pads Table 16:LED Driver Pads Parameter Current, IPAD - High impedance state Current, IPAD -Current sink state LED pad voltage, VPADIPAD = 10mA LED pad resistanceVPAD< 0.5V Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Ccnditions Min Type Max 16 48 Unit Bits KHz Pre-amplifier setting = 0dB, 9dB, 21dB or30dB Analogue setting = -3dB to 12dB in 3dBsteps Stereo separation (crosstalk)
-24
-3 21.5 42 FSC-BT806 Datasheet 5.4 Stereo Codec 5.4.1 Analogue to Digital Converter Table 17:Analogue to Digital Converter Parameter Resolution Input Sample Rate, F sample SNR THD+N Digital gain Analogue gain
f in = 1kHz B/W = 20Hz->F sample /2
(20kHz max) A-Weighted THD+N < 0.1%
1.6V pk-pk input f in = 1kHz B/W = 20Hz->F sample /2
(20kHz max) 1.6V pk-pk input Digital gain resolution = 1/32 F sample 8kHz 16kHz 32kHz 44.1kHz 48kHz F sample 8kHz 48kHz 5.4.1 Digital to Analogue Converter Table 18:Digital to Analogue Converter Parameter Resolution Output Sample Rate, F sample SNR THD+N F sample Load f in = 1kHz B/W = 20Hz->20KHz A-Weighted THD+N < 0.1%
0dBFS input f in = 1kHz B/W = 20Hz->20kHz 0dBFS input F sample 48kHz 48kHz 48kHz 8kHz 8kHz 8kHz Load 100K 32 16 100K 32 16 48kHz 100K Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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8
8
93 92 92 92 92 0.004 0.008
-89
96 96 96 0.002 0.002 0.003 0.003
dB dB dB dB dB
dB dB dB dB dB dB
Ccnditions Min Type Max 16 96 Unit Bits KHz 48kHz 48kHz 32 16
-24
-21
0.003 0.004
-88 21.5 0 778
dB dB mV rms dB Parameter Min Type FSC-BT806 Datasheet Digital gain Digital gain resolution = 1/32 Analogue gain Analogue Gain Resolution = 3dB Output voltage Full-scale swing (differential) Stereo separation (crosstalk) 5.5Auxiliary ADC Table 19:Auxiliary ADC Resolution Input voltage range (a) Offset Gain error Input bandwidth Conversion time Sample rate (b) Accuracy INL
(Guaranteed monotonic) DHL Parameter 5.6Auxiliary DAC Table 20:Auxiliary DAC Resolution Supply voltage, VDD_AUX Output voltage range Full-scale output voltage LSB size Offset Integral non-linearity Settling time (a)
(a) The settling time does not include any capacitive load
0
-1 0
-1
-0.8 1.38
Min
1.30 0
-1 1.30 0
-1.32
-1 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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100 1.69 Type 1.35 1.35 1.32
0 0
Max 10 1.8 1 1 1
0.8 2.75 700 Unit Bits V LSB LSB LSB
KHz uS Samples/s VDD_AUX Max 10 1.40 1.40 2.64 1.32 1 250 Unit Bits V V V mV mV LSB nS
(a) LSB size = 1.8V/1023
(b) The auxiliary ADC is accessed through a VM function.The sample rate given is achieved as part of this function. FSC-BT806 Datasheet 5.7I2C Dynamic Characteristics Table 21: I2C Dynamic Characteristics Parameter Standard Mode[1][2]
Min 4.7 Max Fast Mode[1][2]
Min Max 1.2
Unit
4 4 4 uS uS uS uS uS uS 0.6 0.6 1.2 4.7 0.6 100 250 0[4]
4.7[3]
1.2[3]
3.45[5]
tLOW - SCL low period THIGH - SCL high period tSU; STA - Repeated START condition setup time tHD; STA - START condition hold time tSU; STO - STOP condition setup time tBUF - Bus free time tSU;DAT - Data setup time tHD;DAT - Data hold time tr - SCL/SDA rise time tf- SCL/SDA fall time Cb - Capacitive load for each bus line Note:
1. Guaranteed by design, not tested in production. 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 20+0.1CB 0.8[5]
1000 0[4]
400 400 300 300 300 pF uS uS uS uS
Figure 32: I2C Timing Diagram Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Parameter Min Max FSC-BT806 Datasheet 5.8PCM Dynamic Characteristics Table 22:PCM Dynamic Characteristics PCM Master Timing fmclk - PCM_CLK frequency 4MHz DDS generation.Selection of frequencyis programmable. fmclk - PCM_CLK frequency 48MHz DDSgeneration. Selectionof frequency isprogrammable. PCM_SYNC frequency for SCO connection t mclkh (a) - PCM_CLK high4MHz DDS generation t mclkl (a)- PCM_CLK low 4MHz DDS generation PCM_CLK jitter48MHz DDS generation t dmclksynch - Delay time from PCM_CLK high to PCM_SYNChigh t dmclkpout - Delay time from PCM_CLK high to valid PCM_OUT t dmclklsyncl - Delay time from PCM_CLK low to PCM_SYNClow (Long Frame Sync only) t dmclkhsyncl - Delay time from PCM_CLK high to PCM_SYNClow t dmclklpoutz - Delay time from PCM_CLK low to PCM_OUT high t dmclkhpoutz - Delay time from PCM_CLK high to PCM_OUT high impedance impedance t supinclkl - Set-up time for PCM_IN valid to PCM_CLK low t hpinclkl - Hold time for PCM_CLK low to PCM_IN invalid PCM Slave Timing f sclk - PCM clock frequency (Slave mode: input) f sclk - PCM clock frequency (GCI mode) t sclkl - PCM_CLK low time t sclkh - PCM_CLK high time t hsclksynch - Hold time from PCM_CLK low to PCM_SYNC high t susclksynch - Set-up time for PCM_SYNC high to PCM_CLK low t dpout - Delay time from PCM_SYNC or PCM_CLK, whichever is later, to valid PCM_OUT data (Long Frame Sync only) t dsclkhpout - Delay time from CLK high to PCM_OUT valid data t dpoutz - Delay time from PCM_SYNC or PCM_CLK low,whichever is later, to PCM_OUT data line high impedance t supinsclkl - Set-up time for PCM_IN valid to CLK low t hpinsclkl - Hold time for PCM_CLK low to PCM_IN invalid Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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2.9 980 730 20 0 64 128 200 200 2 20
20 2 Typ 128 256 512
8
Unit KHz KHz KHz nS nS ns pk-pk nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS 21 20 20 20 20 20 20
20 15 15
2048 4096 kHz kHz
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced. Parameter Min Typ Max Unit FSC-BT806 Datasheet 5.9I2S Dynamic Characteristics Table 23: I2S Dynamic Characteristics Digital Audio Interface Slave Timing SCK Frequency WS Frequency tch - SCK high time tcl - SCK low time I2S Slave Mode Timing tssu- WS valid to SCK high set-uptime tsh- SCK high to WS invalid holdtime topd - SCK low to SD_OUT valid delay time tisu- SD_IN valid to SCK high set-uptime tin- SCK high to SD_IN invalid hold time Digital Audio Interface Master Timing SCK Frequency WS Frequency tspd- SCK low to WS valid delay time topd - SCK low to SD_OUT valid delay time tisu - SD_IN valid to SCK high set-uptime tih- SCK high to SD_IN invalid holdtime 5.10 Power consumptions Table 24: Power consumptions I2S Master Mode Timing Parameters,WS and SCK as Outputs
80 80 20 2.5
20 2.5
0 18.44
Parameter Test Conditions Type Unit Bluetooth 2.1 Operation Mode Current Consumption, Power supply 3.0V Power on, discoverable and connectable. Idle Searching
(e)SCO traffic RX/TX active Connected Standby Connected, no data traffic Searching devices Handsfree calling UART data traffic Bluetooth 4.0 Operation Mode Advertising Connected Standby RX/TX active Current Consumption, Power supply 3.0V Advertising Connected, no data traffic UART data traffic Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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6.2 9.6 MHz KHz 6.2 9.6 20
39.27 18.44
~3.8
~6.8
~3.7
~16
~8
~3.8
~4.3
~3.6 MHz KHz nS nS nS nS nS nS nS nS nS nS nS mA mA mA mA mA mA mA mA FSC-BT806 Datasheet Bluetooth 2.1 Operation Mode Current Consumption, Power supply 3.3V Power on, discoverable and connectable. Connected Standby Connected, no data traffic Searching devices Handsfree calling UART data traffic Idle Searching
(e)SCO traffic RX/TX active Bluetooth 4.0/5.0Operation Mode Advertising Connected Standby RX/TX active Current Consumption, Power supply 3.3V Advertising Connected, no data traffic UART data traffic
~3.6
~6.3
~3.4
~15
~7
~3.8
~4.0
~4.1 mA mA mA mA mA mA mA mA 6. MSL &ESDProtection Table 25:MSL and ESD Parameter MSL grade(with JEDEC J-STD-020) Human Body Model Contact Discharge per ANSI/ESDA/JEDEC JS-001 Machine Model Contact Discharge per JEDEC/EIA JESD22-A115 Charged Device Model Contact Discharge per JEDEC/EIA JESD22-C101 Class Max Rating MSL 3 200V 200V (all pins) 200V (all pins) 2kV 2 II 6.1USB Electrostatic Discharge Immunity FSC-BT806 has integrated ESD protection on the USB_DP and USB_DN pins as detailed in IEC 61000-4-2. Table 26:USB Electrostatic Discharge Protection Level IEC 61000-4-2 ESD Test Voltage Level
(Positive and Negative) IEC 61000-4-2 Classification 2kV contact / 2kV air 4kV contact / 4kV air Class 1 Class 1 Normal performance within specificationlimits Normal performance within specificationlimits 6kV contact / 8kV air Class 2 or class 3 Temporary degradation or operatorintervention 8kV contact / 15kV air Class 2 or class 3 Temporary degradation or operatorintervention Comments required required 1 2 3 4 Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 7. RECOMMENDED TEMPERATURE REFLOW PROFILE Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained during storage and shipment. If directed to bake units on the card, please check the below Table 27and follow instructions specified by IPC/JEDEC J-STD-033. Note: The shipping tray cannot be heated above 65C. If baking is required at the higher temperatures displayed in the below Table 27, the modules must be removed from the shipping tray. Any modules not manufactured before exceeding their floor life should be re-packaged with fresh desiccate and a new humidity indicator card. Floor life for MSL (Moisture Sensitivity Level) 3 devices is 168 hours in ambient environment 30C/60%RH. Table 27:Recommended baking times and temperatures 125C Baking Temp. 90C/ 5%RH Baking Temp. 40C/ 5%RH Baking Temp. Saturated @
30C/85%
Floor Life Limit
+ 72 hours @
Saturated @
30C/85%
Floor Life Limit
+ 72 hours @
Saturated@
30C/85%
9 hours 33 hours 13 days 9 days 30C/60%
7 hours 30C/60%
23 hours Floor Life Limit
+ 72 hours @
30C/60%
MSL 3 Feasycom surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB. Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven temperatures during reflow meet the requirements of the solder paste. Feasycom surface mount modules conform to J-STD-020D1 standards for reflow temperatures. The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder reflow. Figure 33: Typical Lead-free Re-flow Pre-heat zone (A) This zone raises the temperature at a controlled rate, typically 0.5 2 C/s. The purpose of this zone is to preheat the PCB board and components to 120 ~ 150 C. This stage is required to distribute the heat uniformly to the PCB board and completely remove solvent to reduce the heat shock to components. Equilibrium Zone 1 (B) In this stage the flux becomes soft and uniformly encapsulates solder particles and spread over PCB board, preventing them from being re-oxidized. Also with elevation of temperature and liquefaction of flux, Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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250 217 210 25 0 A B C D 1 2 3 4 5 E 6 min FSC-BT806 Datasheet each activator and rosin get activated and start eliminating oxide film formed on the surface of each solder particle and PCB board. The temperature is recommended to be 150 to 210 for 60 to 120 second for this zone. Equilibrium Zone 2 (C) (optional) In order to resolve the upright component issue, it is recommended to keep the temperature in 210 217 for about 20 to 30 second. Reflow Zone (D) The profile in the figure is designed for Sn/Ag3.0/Cu0.5. It can be a reference for other lead-free solder. The peak temperature should be high enough to achieve good wetting but not so high as to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth which can result in a brittle joint. The recommended peak temperature (Tp) is 230 ~ 250 C. The soldering time should be 30 to 90 second when the temperature is above 217 C. Cooling Zone (E) The cooling ate should be fast, to keep the solder grains small which will give a longer-lasting joint. Typical cooling rate should be 4 C. 8. MECHANICAL DETAILS 8.1 Mechanical Details Dimension: 13mm(W) x 26.9mm(L) x 2.2mm(H) Tolerance: 0.1mm Module size: 13mm X 26.9mm Tolerance: 0.2mm Pad size: 1.6mmX0.6mm Tolerance: 0.2mm Pad pitch: 1.0mm Tolerance: 0.1mm Figure 34: FSC-BT806footprint Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 9. HARDWARE INTEGRATION SUGGESTIONS 9.1 Soldering Recommendations FSC-BT806 is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations. Feasycom will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering. Since the profile used is process and layout dependent, the optimum profile should be studied case by case. Thus following recommendation should be taken as a starting point guide. 9.2 Layout Guidelines(Internal Antenna) It is strongly recommended to use good layout practices to ensure proper operation of the module. Placing copper or any metal near antenna deteriorates its operation by having effect on the matching properties. Metal shield around the antenna will prevent the radiation and thus metal case should not be used with the module. Use grounding vias separated max 3 mm apart at the edge of grounding areas to prevent RF penetrating inside the PCB and causing an unintentional resonator. Use GND vias all around the PCB edges. The mother board should have no bare conductors or vias in this restricted area, because it is not covered by stop mask print. Also no copper (planes, traces or vias) are allowed in this area, because of mismatching the on-board antenna. Figure 35:FSC-BT806 Restricted Area Following recommendations helps to avoid EMC problems arising in the design. Note that each design is unique and the following list do not consider all basic design rules such as avoiding capacitive coupling between signal lines. Following list is aimed to avoid EMC problems caused by RF part of the module. Use good consideration to avoid problems arising from digital signals in the design. Ensure that signal lines have return paths as short as possible. For example if a signal goes to an inner layer through a via, always use ground vias around it. Locate them tightly and symmetrically around the signal vias. Routing of any sensitive signals should be done in the inner layers of the PCB. Sensitive traces should have a ground area above and under the line. If this is not possible, make sure that the return path is short by other means (for example using a ground line next to the signal line). Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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26.9 0 2 5 Max.0.5
. 5 3 4
. 5 0
. x a M 8 1 3 1 0 1 no bare copper(exept solder pads for module) no copper and components on any layer no components on any layer 20 10 Applic. PCB do not place any conductive parts in this area Provide solid ground plane(s) as large as possible around area FSC-BT806 Datasheet 9.3 Layout Guidelines(External Antenna) Placement and PCB layout are critical to optimize the performances of a module without on-board antenna designs. The trace from the antenna port of the module to an external antenna should be 50 and must be as short as possible to avoid any interference into the transceiver of the module. The location of the external antenna and RF-IN port of the module should be kept away from any noise sources and digital traces. A matching network might be needed in between the external antenna and RF-IN port to better match the impedance to minimize the return loss. As indicated in Figure below, RF critical circuits of the module should be clearly separated from any digital circuits on the system board. All RF circuits in the module are close to the antenna port. The module, then, should be placed in this way that module digital part towards your digital section of the system PCB. Figure 36: Placement the Module on a System Board 9.3.1 Antenna Connection and Grounding Plane Design Figure 37: Leave 5mm Clearance Space from the Antenna General design recommendations are:
The length of the trace or connection line should be kept as short as possible. Distance between connection and ground area on the top layer should at least be as large as the dielectric thickness. Routing the RF close to digital sections of the system board should be avoided. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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Non enmitting circuits Non enmitting circuits A n t e n n a RF_IN Digital Part Digital & Analog Circuits PCB A n t e n n a RF & heat enmitting circuits Digital Part RF_IN Digital & Analog Circuits RF & heat enmitting circuits PCB Antenna Matching Network RF_IN 5mm FSC-BT806 Datasheet To reduce signal reflections, sharp angles in the routing of the micro strip line should be avoided. Chamfers or fillets are preferred for rectangular routing; 45-degree routing is preferred over Manhattan style 90-degree routing. Figure 38: Recommended Trace Connects Antenna and the Module Routing of the RF-connection underneath the module should be avoided. The distance of the micro strip line to the ground plane on the bottom side of the receiver is very small and has huge tolerances. Therefore, the impedance of this part of the trace cannot be controlled. Use as many vias as possible to connect the ground planes. 10. PRODUCT PACKAGING INFORMATION 10.1 DefaultPacking a, Tray vacuum b, Tray Dimension: 180mm * 195mm Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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A n t e n n a A n t e n n a A n t e n n a PCB Wrong PCB Better PCB Best FSC-BT806 Datasheet Figure 39: Tray vacuum 10.2 Packing box(Optional)
* If require any other packing, must be confirmed with customer
* Package: 2000PCS Per Carton (Min Carton Package) Figure 40: Packing Box Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 11. APPLICATION SCHEMATIC 11.1Application circuit diagram(Default) Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet 11.2Application circuit diagram(Earphone) FCC/IC Statements
(OEM) Integrator has to assure compliance of the entire end-product incl. the integrated RF Module. For 15 B
(15.107 and if applicable 15.109) compliance, the host manufacturer is required to show compliance with 15 while the module is installed and operating. Furthermore the module should be transmitting and the evaluation should confirm that the module'sintentional emissions (15C) are compliant (fundamental / out-of-band). Finally the integrator has to apply the appropriate equipment authorization (e.g. Verification) for the new host device per definition in 15.101. Integrator is reminded to assure that these installation instructionswill not be made available to the end-user of the final host device. The final host device, into which this RF Module isintegrated" hasto be labeled with an auxiliary label stating the FCC IDofthe RF Module, such as "Contains FCC ID: 2AMWOFSC-BT806
"This device complies with part 15 of the FCC rules. Operation is subject to the following two conditions:
(1)this device may not cause harmful interference, and
(2)this device must accept any interference received, including interference that may cause undesired operation."
"Changes or modifications to this unit not expressly approved by the party responsible for compliance could void the users authority to operate the equipment."
the Integrator will be responsible to satisfy SAR/ RF Exposure requirements, when the module integrated into the host device. RF Exposure Warning Statements:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment shall be installed and operated with minimum distance 20cm between the radiator & body. The final host device, into which this RF Module is integrated" has to be labeledwith an auxiliary label stating the IC ofthe RF Module,such as"Contains transmitter module IC: 23872-FSCBT806 avec Le unetiquetteauxiliaireindiquant le CI du module RF, tel que" Contient le module metteur IC: 23872-FSCBT806 This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the danslequelce module RF priphriquehte
"doittretiquet estintgr final, Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet l'utilisateur de l'appareildoit accepter tout brouillageradiolectriquesubi, mmesi following two conditions: (1)this device may not cause interference, and(2) this device must accept any interference, includinginterference that may cause undesired operation of the device. Le prsentappareilestconforme aux CNR d'Industrie Canada applicablesauxappareils radio exempts de licence. L'exploitationestautorise aux deux conditions suivantes :(1) l'appareil ne doit pas produire de brouillage, et(2) le brouillageest susceptible d'encompromettrelefonctionnement. Radio Frequency Exposure Statement for IC The device has been evaluated to meet general RF exposure requirements. The device can be used in mobile exposure conditions. The min separation distance is 20cm. Dclaration d'exposition aux radiofrquences pour IC L'appareil a t valu pour rpondre aux exigences gnrales en matire d'exposition aux RF. L'appareil peut tre utilis dans des conditions d'exposition mobiles. La distance de sparation minimale est de 20 cm. Module statement The single-modular transmitter is a self-contained, physically delineated, component for which compliance can be demonstrated independent of the host operating conditions, and which complies with all eight requirements of 15.212(a)(1) as summarized below. 1) The radio elements have the radio frequency circuitry shielded. 2) The module has buffered modulation/data inputs to ensure that the device will complywith Part 15 requirements with any type of input signal. 3) The module contains power supply regulation on the module. 4) The module contains a permanently attached antenna. 5) The module demonstrates compliance in a stand-alone configuration. 6) The module is labeled with its permanently affixed FCC ID label. 7) The module complies with all specific rules applicable to the transmitter, including all the conditions provided in the integration instructions by the grantee. 8) The module complies with RF exposure requirements. NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
- Reorient or relocate the receiving antenna. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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FSC-BT806 Datasheet
- Increase the separation between the equipment and receiver.
-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-Consult the dealer or an experienced radio/TV technician for help Co-location Warning:
This equipment could not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with the FCC multi-transmitter product procedures. Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
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1 2 | Agent Authorization Rev 1.0 | Cover Letter(s) | 14.21 KiB | November 11 2020 |
Shenzhen Feasycom Technology Co., LTD Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District, Shenzhen, China Agent Authorization Company: Shenzhen Feasycom Technology Co., LTD Address: Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District, Shenzhen, China Product Name: Bluetooth module Model Number(s): FSC-BT806 Product Description: Bluetooth module We authorize MiCOM Labs Inc., 575 Boulder Court, Pleasanton, California 94566, USA, to act on our behalf on all matters concerning the certification of above named equipment. We declare that MiCOM Labs Inc. is allowed to forward all information related to the approval and certification of equipment to the regulatory agencies as required and to discuss any issues concerning the approval application. Any and all acts carried out by MiCOM Labs on our behalf shall have the same effect as acts of our own. Signature:
Date: Nov. 05, 2020 Name:
Wan Zhifu Title:
General Manager Company: Shenzhen Feasycom Technology Co., LTD
1 2 | FCC Long Term Only Confidentiality Request | Cover Letter(s) | 833.79 KiB | November 11 2020 |
Shenzhen Feasycom Technology Co., LTD Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District, Shenzhen, China Office of Engineering Technology Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 USA Date: Nov. 05, 2020 Subject; Request for Confidentiality FCC ID: 2AMWOFSC-BT806 To Whom It May Concern, Pursuant to the provisions of the Commissions rules Title 47 Sections 0.457 and 0.459, we are requesting the Commission to withhold the following attachment(s) as confidential documents from public disclosure indefinitely. These documents contain detailed system and equipment descriptions and are considered as proprietary information in operation of the equipment. The public disclosure of these documents might be harmful to our company and would give competitors an unfair advantage in the market.
[<] Schematic Diagram Block Diagram
[x] Operational Description
[_] Parts List
[_] Tune-up Procedure It is our understanding that all measurement test reports, FCC ID label format and correspondence during the certification review process cannot be granted as confidential documents and this information will be available for public review once the grant of equipment authorization is issued. Sincerely, Signature:
Name: Wan Zhifu Title: General Manager
1 2 | Modular Approval Justification | Cover Letter(s) | 17.94 KiB | November 11 2020 |
Shenzhen Feasycom Technology Co., LTD Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District, Shenzhen, China RE FCC ID: 2AMWOFSC-BT806 To the certification reviewer:
We are hereby applying for [full] modular approval of the above-referenced FCC ID, based on compliance with [all] of the criteria as detailed below. Sincerely, Part 15 Unlicensed Single Modular Transmitter Approval Justification per 15.212
[Wan Zhifu]
[General Manager]
(i)
(ii) Requirement per 15.212 radio elements of the modular their own RF The transmitter must have shielding. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided.
(iii) The modular transmitter must have its own power supply regulation. transmission
(iv) The modular transmitter must comply with system the antenna and requirements of 15.203, 15.204(b) and 15.204(c). The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with Part 15 parameters.
(v)
(vi) The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number. If the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is label referring to the enclosed module. installed must also display a reference Shielding is provided by a metal cover over the circuitry. All modulation and data inputs are buffered by circuitry on the transmitter chip. Power supply regulation is provided by circuitry on the transmitter chip. The antenna is fixed. Testing was performed in a stand-alone configuration as shown in the test setup photos. The modular was labeled with its own FCC ID. The outside of device in to which the module is installed will labeled Contains TX FCC ID: 2AMWOFSC-
BT806, Please refer to User Manual. Shenzhen Feasycom Technology Co., LTD Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District, Shenzhen, China
(vii) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. The modular is comply with all applicable FCC rules. Any modifications, not expressly approved by the manufacturer could void the authority to operate in these regions.
(viii) The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. This module operates under Part 15 .247 which is exempt from RF exposure evaluation owing to the very low operating power.
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2020-11-11 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Original Equipment |
2 | 2402 ~ 2480 | DTS - Digital Transmission System |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 | Effective |
2020-11-11
|
||||
1 2 | Applicant's complete, legal business name |
Shenzhen Feasycom Technology Co.,Ltd
|
||||
1 2 | FCC Registration Number (FRN) |
0026678862
|
||||
1 2 | Physical Address |
Room 2004A, 20th Floor, Huichao Technology Building, Jinhai Road, Xixiang, Baoan District,
|
||||
1 2 |
Room 2004A, 20th Floor, Huichao Technology
|
|||||
1 2 |
Shenzhen, N/A
|
|||||
1 2 |
China
|
|||||
app s | TCB Information | |||||
1 2 | TCB Application Email Address |
c******@micomlabs.com
|
||||
1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 | Grantee Code |
2AMWO
|
||||
1 2 | Equipment Product Code |
FSC-BT806
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 | Name |
W******** Z****
|
||||
1 2 | Telephone Number |
+86-7********
|
||||
1 2 | Fax Number |
+86-7********
|
||||
1 2 |
z******@feasycom.com
|
|||||
app s | Technical Contact | |||||
1 2 | Firm Name |
Shenzhen Feasycom Technology Co., LTD
|
||||
1 2 | Physical Address |
China
|
||||
1 2 |
z******@feasycom.com
|
|||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
1 2 | DTS - Digital Transmission System | |||||
1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Bluetooth module | ||||
1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 | Modular Equipment Type | Single Modular Approval | ||||
1 2 | Purpose / Application is for | Original Equipment | ||||
1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 | Grant Comments | Single Modular Approval. Output power listed is maximum conducted power. The antenna used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter, except in accordance with FCC multi- transmitter product procedures. End-Users must be provided with transmitter operation conditions for satisfying RF exposure compliance. OEM integrators must be provided with antenna installation instructions. The OEM integrators must be instructed to ensure that the end user has no manual instructions to remove or install the device.OEM integrators and end-users must be provided with transmitter operation conditions for satisfying RF exposure compliance. Only those antennas tested with the device or similar antennas with equal or lesser gain may be used with this transmitter. | ||||
1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 | Firm Name |
Attestation of Global Compliance (Shenzhen) Co., L
|
||||
1 2 | Name |
D******** L********
|
||||
1 2 | Telephone Number |
+86-7********
|
||||
1 2 |
d******@agc-cert.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0085000 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0086000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
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