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1 2 3 | Cover Letter(s) | January 10 2015 | ||||||
1 2 3 | Cover Letter(s) | January 10 2015 | ||||||
1 2 3 | Cover Letter(s) | January 10 2015 | ||||||
1 2 3 | External Photos | January 10 2015 | ||||||
1 2 3 | RF Exposure Info | January 10 2015 | ||||||
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1 2 3 | User Manual | Users Manual | 621.80 KiB |
Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 1/40 User manual Product references Product code:
TELEMACO/RC2015/ERMETE Product description:
Telematics platform for data acquisition Telemaco,RC2015,Ermete Review Check (DT) Editing Authorization (DG) 0.5 M. Freguglia F. Gallo Date 15/10/2015 Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 2/40 Rev. 0.0 0.1 0.2 0.3 0.4 0.5 Date Editing A.Pizzato A.Pizzato A.Pizzato 11/06/13 20/06/13 10/07/13 10/04/15 M. Freguglia 08/05/15 M. Freguglia 15/10/15 M. Freguglia REVISIONS HISTORY Par. / Pag. Description First draft General review English translation and general review General upgrade Added warnings in installation paragraph Added warnings in installation paragraph
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Doc: ANNEX II M-RP_01-02 Rev.03 Computers Index 1. 2. 3. USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 3/40 3.1. Overview ................................................................................................................................................. 6 System Components ............................................................................................................................. 6 2.1. Box ..................................................................................................................................................... 6 2.2. Options and expansions ..................................................................................................................... 6 Declaration ......................................................................................................................................... 6 2.3. External connections ............................................................................................................................ 7 Vehicle side ........................................................................................................................................ 7 3.1.1. Automotive connector .................................................................................................................... 8 3.1.1.1. Main power - PWR and PWR_GND ............................................................................................ 9 3.1.1.2. Digital wake-up signals - WU_INX ............................................................................................. 9 3.1.1.3. High-speed CAN lines - CANXL and CANXH .............................................................................. 9 3.1.1.4. Low-speed CAN lines - CANBL and CANBH ........................................................................... 10 3.1.1.5. High-speed K lines - KX .......................................................................................................... 10 3.1.1.6. Digital input/output - DIG_IOX .................................................................................................. 10 Inputs ................................................................................................................................ 10 3.1.1.6.1. 3.1.1.6.2. Outputs ............................................................................................................................. 11 3.1.1.7. High-power digital outputs - DIG_OUT1 and DIG_OUT2 .......................................................... 11 3.1.1.8. RS232 serial lines - RS232CXY and RS232RXY ......................................................................... 11 3.1.1.9. RS2485 serial line - RS485X ................................................................................................... 12 3.1.1.10. Ethernet line - LANX ................................................................................................................ 12 3.1.1.11. USB line - USBX ...................................................................................................................... 12 3.1.1.12. Microphone line - MICX ........................................................................................................... 12 3.1.1.13. Future expansion ................................................................................................................... 12 3.1.2. SMA connector for GSM antenna X4 ....................................................................................... 13 3.1.3. SMA connector for GPS antenna X3 ........................................................................................ 13 3.1.4. SMA-R connector for WiFi antenna X2 .................................................................................... 13 3.1.5. SMA-R connector for BT antenna X1 ....................................................................................... 13 User side .......................................................................................................................................... 14 3.2.1. Jack connector for auxiliary power supply X6 .......................................................................... 14 3.2.2. USB device connector X7 ......................................................................................................... 14 3.2.3. HDMI connector X8 .................................................................................................................. 15 3.2.4. Ethernet connector X9 .............................................................................................................. 15 3.2.5. USB host connector (single) X10 ............................................................................................. 15 3.2.6. USB host connector (double) X11 ............................................................................................ 15 3.2.7. SIM e SD holders X12 ............................................................................................................ 15 Internal modules .................................................................................................................................. 16 Core module ..................................................................................................................................... 16 4.1.1. Printed circuit board ..................................................................................................................... 16 4.1.2. Boot configuration ........................................................................................................................ 16 4.1.2.1. Boot from board settings ........................................................................................................ 17 4.1.2.1.1. Boot from SD .................................................................................................................... 17 4.1.2.1.2. Boot from MMC ................................................................................................................ 17 4.1.2.1.3. Boot da SATA ................................................................................................................... 17 4.1.3. Pinout of the interface connectors ............................................................................................... 18 4.1.3.1. Connector J2 .......................................................................................................................... 18 4.1.3.2. Connector J5 .......................................................................................................................... 20 4.1.3.3. Connector J6 .......................................................................................................................... 22 4.1.4. Peripherals and available interfaces ............................................................................................ 23 4.1.4.1. Power supply and control signals .......................................................................................... 23 4.1.4.2. Asynchronous serial channels ............................................................................................... 24 I2C channels ........................................................................................................................... 25 4.1.4.3. 4.1.4.4. CAN channels ........................................................................................................................ 25 4.1.4.5. SPI channels .......................................................................................................................... 25 4.1. 3.2. 4. Doc: ANNEX II M-RP_01-02 Rev.03 5. 6. Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 4/40 4.2. 4.1.4.6. USB channels ........................................................................................................................ 26 4.1.4.7. PCIe channel.......................................................................................................................... 26 4.1.4.8. SATA channel ........................................................................................................................ 27 4.1.4.9. Ethernet channel .................................................................................................................... 27 4.1.4.10. Secure Digital channels ......................................................................................................... 28 4.1.4.11. HDMI channel ........................................................................................................................ 28 4.1.4.12. LVDS channels ...................................................................................................................... 29 4.1.4.13. Audio channels....................................................................................................................... 30 4.1.4.14. Parallel RGB channel ............................................................................................................. 30 4.1.4.15. GPIOs .................................................................................................................................... 31 Carrier module .................................................................................................................................. 32 4.2.1. Printed circuit board ..................................................................................................................... 32 4.2.2. Vehicle-side connector J9......................................................................................................... 33 4.2.3. User-side connector J3, J4, J6, J10, J12 and J15 ................................................................... 33 4.2.4. Connector for communication module J20 ............................................................................... 33 4.2.5. Connector for diagnostic module J19 ....................................................................................... 34 4.2.6. Connectors for expansion module J8 and J14 ......................................................................... 35 4.2.7. Connectors for debug J1 and J5 .............................................................................................. 36 4.2.8. Connectors for backup battery J17 ........................................................................................... 36 Communication module.................................................................................................................... 36 4.3.1. Printed circuit board ..................................................................................................................... 36 4.3.2. Connector for carrier board connection J2 ............................................................................... 37 Mechanical ........................................................................................................................................... 39 Top view ........................................................................................................................................... 39 Installation ............................................................................................................................................ 40 6.1. General warnings ............................................................................................................................. 40 Connections ..................................................................................................................................... 40 6.2. 4.3. 5.1. Index of figures Figure 1: vehicle side view ................................................................................................................................ 7 Figure 2: main connector ................................................................................................................................... 8 Figure 3: user side view ................................................................................................................................... 14 Figure 4: RC2core component placement .................................................................................................... 16 Figure 5: RC2carrier component placement ................................................................................................ 32 Figure 6: RC2comm component placement ................................................................................................. 37 Index of tables Table 1: main connector pinout, left section (48 pins) ....................................................................................... 8 Table 2: main connector pinout, right section (32 pins) ..................................................................................... 9 Table 3: main power .......................................................................................................................................... 9 Table 4: digital wake-up signals ........................................................................................................................ 9 Table 5: high-speed CAN lines ........................................................................................................................ 10 Table 6: low-speed CAN line ........................................................................................................................... 10 Table 7: high-speed K lines ............................................................................................................................. 10 Table 8: digital inputs ....................................................................................................................................... 11 Table 9: digital outputs..................................................................................................................................... 11 Table 10: high-power digital outputs ................................................................................................................ 11 Table 11: RS232 serial lines ............................................................................................................................ 11 Table 12: RS485 serial line ............................................................................................................................. 12 Table 15: microphone line ............................................................................................................................... 12 Table 16: RC2core boot modes .................................................................................................................... 16 Table 17: RC2core boot pins at reset ........................................................................................................... 17 Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 5/40 TELEMACO/RC 2015/ERMETE Table 18: RC2core boot from SD ................................................................................................................. 17 Table 19: RC2core boot from MMC .............................................................................................................. 17 Table 20: RC2core boot from SATA ............................................................................................................. 17 Table 21: RC2core special power supply ..................................................................................................... 18 Table 22: RC2core - J2 connector pinout ........................................................................................................ 20 Table 23: RC2core J5 connector pinout ....................................................................................................... 22 Table 24: RC2core J6 connector pinout ....................................................................................................... 23 Table 25: RC2core power supply and control signals .................................................................................. 23 Table 26: RC2core auxiliary power supply on W3 connector ...................................................................... 23 Table 27: RC2core - asynchronous serial channels ........................................................................................ 24 Table 28: RC2core auxiliary connector for console ...................................................................................... 25 Table 29: RC2core I2C channels .................................................................................................................. 25 Table 30: RC2core CAN channels ............................................................................................................... 25 Table 31: RC2core SPI channels ................................................................................................................. 26 Table 32: RC2core USB channels ................................................................................................................ 26 Table 33: RC2core PCIe channels ............................................................................................................... 27 Table 34: RC2core SATA channel ............................................................................................................... 27 Table 35: RC2core Ethernet channel ........................................................................................................... 27 Table 36: RC2core SD-card channel ............................................................................................................ 28 Table 37: RC2core HDMI channel ................................................................................................................ 29 Table 38: RC2core LVDS channel ............................................................................................................... 29 Table 39: RC2core LVDS channel ............................................................................................................... 30 Table 40: RC2core parallel RGB channel .................................................................................................... 31 Table 41: RC2core GPIO ............................................................................................................................. 32 Table 42: RC2carrier connector pinout of communication module .............................................................. 34 Table 43: RC2carrier connector pinout of diagnosis module ....................................................................... 35 Table 44: RC2carrier connector pinout of expansion module ...................................................................... 35 Table 45: RC2carrier auxiliary input connector for console.......................................................................... 36 Table 46: RC2carrier auxiliary output connector for console ....................................................................... 36 Table 47: RC2carrier auxiliary output connector for console ....................................................................... 36 Table 48: RC2comm connector pinout of communication module ............................................................... 38 Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 6/40 TELEMACO/RC 2015/ERMETE the components of the system and the most common options the placement of the connectors and pinouts the specifications of connection and use of the devices connected to the system the features and specifications of use of internal peripherals the container and the characteristics of mounting and assembly 1. Overview This document contains the specifications for installation and use of the product named Telemaco, RC2015 or Ermete depending on commercialization brand. Below are described:
2. System Components 2.1. Box The box constitutes the processing unit and the interface with the world; it is equipped with:
plastic housing with fixing brackets for mounting on vehicle automotive connector for connectivity to the world dedicated connectors for connectivity with administrator or technical operator 2.2. Options and expansions The system is usually accompanied by the following options:
antennas or trivalent antenna wiring for the automotive connector 2.3. Declaration DMD Computers declares that the Telemaco, RC2015 or Ermete is connectors for antennas (GPS, WiFi, GSM and BT) internal connectors for other options and debugging compliant to the regulations of mechanical resistance:
ISO 16750-3:2012 o EN 60068-2-64:2012 o o EN 60068-2-27:2012 o IVECO STD. 18-2252 compliant to the regulations of electromagnetic compatibility (CE/99/05) and further modification compliant with UN ECE R10 (CE/28/2006) for "automotive" aspects compliant to the Iveco rules (STD 18-2252) Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 7/40 3. External connections The box is provided to the outside of the following connectors:
Vehicle side 1 automotive connector MULTILOCK double section 1 SMA connector for GPS antenna 1 SMA-R antenna WiFi 1 SMA antenna for GSM 1 SMA-R BT antenna User side 1 jack plug for auxiliary power 1 USB 2.0 host connector (single port) 2 USB 2.0 host connector (double port) 1 USB 2.0 device 1 HDMI connector 1 Ethernet 10/100/1000 connector 1 SIM holder 1 SD holder (optional)
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3.1. Vehicle side Figure 1 shows the vehicle side view of the box. The figure shows the numbering of the connectors, as described in the following paragraphs. Figure 1: vehicle side view X1: SMA-R connector for BT antenna X2: SMA-R connector for WiFi antenna X3: SMA connector for GPS antenna X4: SMA connector for GSM antenna Doc: ANNEX II M-RP_01-02 Rev.03 USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 8/40 Computers TELEMACO/RC 2015/ERMETE 3.1.1. Automotive connector The main connector is an automotive connector MULTILOCK double section with 80 pins. The image of the connector and pin numbering is shown in Figure 2. M L K J H G F E D C B A A B C D E F G H 4 3 2 1 1 2 3 4 The assignment of the signals is summarized, for the left section with 48 pins, in Table 1. Figure 2: main connector Pin 1A 1B 1C 1D 1E 1F 1G 1H 1J 1K 1L 1M Signal GND_RF GND CAN4H CAN4L CAN3H CAN3L CAN1L CAN1H CAN2H CAN2L MIC_GND MIC_IN Pin 2A 2B 2C 2D 2E 2F 2G 2H 2J 2K 2L 2M Signal LAN_RX-
LAN_RX+
LAN_TX-
LAN_TX+
USB_GND USB_DM USB_DP USB_VCC RS485_N RS485_P DIG-OUT2 DIG-OUT1 Pin 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M Signal GND RS232c_RI RS232c_DCD RS232c_CTS RS232c_RX RS232c_DTR RS232c_RTS RS232c_TX RS232c_DSR GND WU_IN2 PWR Pin 4A 4B 4C 4D 4E 4F 4G 4H 4J 4K 4L 4M Signal WU_IN1 DIG_IO8 DIG_IO7 DIG_IO6 DIG_IO5 DIG_IO4 DIG_IO3 DIG_IO2 DIG_IO1 GND WU_IN3 PWR_GND Table 1: main connector pinout, left section (48 pins) Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 9/40 TELEMACO/RC 2015/ERMETE The assignment of the signals is summarized, for the right section with 32 pins, in Table 2. Pin 1A 1B 1C 1D 1E 1F 1G 1H Signal EXP_1 EXP_2 EXP_3 EXP_4 EXP_5 EXP_6 EXP_7 EXP_8 Pin 2A 2B 2C 2D 2E 2F 2G 2H Signal EXP_9 EXP_10 EXP_11 EXP_12 EXP_13 EXP_14 EXP_15 EXP_16 Pin 3A 3B 3C 3D 3E 3F 3G 3H Signal RS232r_TX RS232r_RX GND K1 K2 K3 EXP_17 EXP_18 Pin 4A 4B 4C 4D 4E 4F 4G 4H Signal CAN5L CAN5H CAN6L CAN6H CANBH CANBL GND TACHO Table 2: main connector pinout, right section (32 pins) 3.1.1.1. Main power - PWR and PWR_GND The power supply of the system is automotive compliant. The associated connector pins are PWR and PWR_GND. rated voltage voltage protection maximum continuous voltage tolerated load-dump current short-circuit protection Min. 8 Typ. 24 n.a. Max. 40 36 100 200 7 V V V V A Table 3: main power The power supply accepts input voltages in the range of 840V, is protected against reverse battery and load-dump and is capable of operating up to 100V persistent; under 8V it does not guarantee its proper operation, above 36V (VPWRPROT) a protection circuit decouples the power supply from external battery and the system is powered from the backup battery. 3.1.1.2. Digital wake-up signals - WU_INX They are 3 digital inputs, active high, that allow to wake up the system. The associated connector pins are WU_INX. Min. Typ. rated voltage maximum continuous voltage tolerated load-dump impedance short-circuit protection 6 100k yes Max. PWR 100 200 V V V Table 4: digital wake-up signals 3.1.1.3. High-speed CAN lines - CANXL and CANXH They are 6 high-speed CAN lines. The associated connector pins are CANXL and CANXH. The CAN1 line has wake-up capabilities. rated voltage dominant state rated voltage recessive state maximum continuous voltage tolerated load-dump impedance CANH CANL CANH/L CANH/L CANH/L Min. 3 0.5 2
-27
-200 Typ. 3.6 1.4 2.5 20k Max. 4.25 1.75 3
+40
+200 V V V V V Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 10/40 communication speed short-circuit protection Min. Typ. yes Max. 1M bps Table 5: high-speed CAN lines All the CAN lines are, by default, not terminated. However, with a simple soldering point, a 120 termination can be inserted. Low-speed CAN lines - CANBL and CANBH 3.1.1.4. It is a low-speed and fault-tolerant CAN line. The associated connector pins are CANBL and CANBH. rated voltage dominant state rated voltage recessive state maximum continuous voltage tolerated load-dump impedance communication speed short-circuit protection CANH CANL CANH CANL CANH/L CANH/L Min. 3.6 0 0 4.8
-58
-200 Typ. 330k yes Max. 5 1.4 0.2 5
+58
+200 125k V V V V V V bps Table 6: low-speed CAN line This CAN line is, by default, not terminated. However, with a simple soldering point, a 120 termination can be inserted. 3.1.1.5. High-speed K lines - KX They are 6 high-speed K lines. The associated connector pins are KX. rated voltage dominant state rated voltage recessive state rated voltage dominant state rated voltage recessive state maximum continuous voltage tolerated load-dump impedance communication speed short-circuit protection TxD RxD Min. 0.95 x VPWR 0.65 x VPWR
-16 500 Typ. yes Table 7: high-speed K lines Max. 0.2 x VPWR 0.35 x VPWR
+36 250k V V V V V bps The hot side of the K line is connected to the protected battery voltage VPWRPROT. If the vehicle battery is 24V, the pull-up on each line is 1k; if the vehicle battery is 12V, the pull-up is 500; the selection is done automatically by the power-management processor. On each line, a boost function is available; it allows to reach the maximum communication speed (up to 250kbps), even on lines long several meters. 3.1.1.6. Digital input/output - DIG_IOX They are 8 digital signals configurable, in HW, as inputs or outputs. The default configuration provides 2 inputs and 6 outputs. Inputs 3.1.1.6.1. They are 2 TTL compatible inputs but tolerant until the battery voltage. The associated connector pins are DIG_IO1 and DIG_IO2. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 11/40 Min. Typ. rated voltage maximum continuous voltage tolerated load-dump impedance short-circuit protection 3 10k yes Max. VPWR 100 200 V V V Table 8: digital inputs The 2 inputs include a pull-up that maintains a well-known logic level if the pins are left floating. 3.1.1.6.2. Outputs They are 6 outputs capable of providing, on command, a voltage of 5V. The associated connector pins are DIG_IO3DIG_IO8. Min. Typ. rated voltage maximum continuous voltage tolerated load-dump impedance short-circuit protection
-1 5 yes Table 9: digital outputs Max. 15m 40 V A V V The 6 outputs are able to supply 15mA ensuring 5V; if the load circuit tends to draw more power, a thermal protection intervenes and limits the current and the voltage available. The same thermal protection ensures the protection against short-circuits; however, a prolonged state of thermal protection determines a stress condition in the device and this limits its operational life. 3.1.1.7. High-power digital outputs - DIG_OUT1 and DIG_OUT2 They are 2 high-side digital outputs, connected to the protected battery voltage VPWRPROT. The associated connector pins are DIG_OUT1 and DIG_OUT2. Min. Typ. rated voltage maximum continuous voltage tolerated load-dump impedance short-circuit protection yes Max. VPWR 500m 40 V A V V Table 10: high-power digital outputs 3.1.1.8. RS232 serial lines - RS232CXY and RS232RXY They are 2 serial lines in standard RS232, one is complete with 8 wires, and the other is minimal with 2 wire. The associated connector pins are RS232CXY and RS232RXY. rated voltage high level rated voltage low level rated voltage high level rated voltage low level maximum continuous voltage tolerated load-dump impedance communication speed short-circuit protection TxD RxD TxD Min. Typ. Max. 5 1.2
-13 3k
-5 2.4 13 7k 1M only TxD to Ground V V V V V V bps Table 11: RS232 serial lines Doc: ANNEX II M-RP_01-02 Rev.03 Computers 3.1.1.9. RS2485 serial line - RS485X It is a serial line in standard RS485 with 2 wires. The associated connector pins are RS485X. USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 12/40 differential voltage hysteresis voltage maximum continuous voltage tolerated load-dump impedance communication speed short-circuit protection TxD RxD Min. 1.5
-9 Typ. 35m 120 only to Ground Max. 14 32M V V V V bps Table 12: RS485 serial line 3.1.1.10. Ethernet line - LANX It is a 10/100 Ethernet line. The associated connector pins are LANX. The electrical characteristics are compatible with the LAN specifications for 10/100Mbps 3.1.1.11. USB line - USBX It is a USB 2.0 host line. The associated connector pins are USBX. The electrical characteristics are compatible with USB 2.0 specifications 3.1.1.12. Microphone line - MICX It is a line for passive microphone. The associated connector pins are MICX. rated voltage maximum continuous voltage tolerated load-dump impedance programmable gain SNR short-circuit protection Min.
-24 Typ. 1.8 2k 91 only to Ground Max. 2 24 V V V dB dB Table 13: microphone line The microphone input includes an internal 2.2k bias pull-up. 3.1.1.13. Future expansion They are 20 general purpose signals can be used for future expansion. The associated connector pins are EXPX. They are available on the connector but are not "mapped" on any device. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 13/40 3.1.2. SMA connector for GSM antenna X4 X4 is an SMA male connector used for connection to a GSM antenna. The connector is electrically connected to the module. The antenna cable must be a female coaxial with 50 impedance. 3.1.3. SMA connector for GPS antenna X3 X3 is a SMA female connector used for connection to a GPS antenna. The connector is electrically connected to the module. The antenna cable must be a female coaxial with 50 impedance. 3.1.4. SMA-R connector for WiFi antenna X2 X2 is a male SMA-R connector used to connect with WiFi antenna. The connector is electrically connected to the module. The antenna cable must be a female coaxial with 50 impedance. 3.1.5. SMA-R connector for BT antenna X1 X1 is a male SMA-R connector used to connect with WiFi antenna. The connector is electrically connected to the module. The antenna cable must be a female coaxial with 50 impedance Doc: ANNEX II M-RP_01-02 Rev.03 USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 14/40 Computers TELEMACO/RC 2015/ERMETE 3.2. User side Figure 3 shows the vehicle side view of the box. The figure shows the numbering of the connectors, as described in the following paragraphs. X12 X11 X10 X7 X6 X9 X8 Figure 3: user side view X6: jack connector for auxiliary power supply X7: USB device connector X8: HDMI connector X9: Ethernet connector X10: USB host connector (three masters) X11: USB slave connector (console) X12: SIM (above) and SD (below) holders Jack connector for auxiliary power supply X6 3.2.1. On the user side an auxiliary connector is available; it is compatible with the power jack of the laptop PC, allowing to power the system without being connected to the vehicle battery. CAUTION: is strongly recommended to connect the auxiliary power supply only for use at the lab and do not connect anything to the auxiliary power supply if the system is already connected to the vehicle battery. USB device connector X7 3.2.2. On the user side a Type-B standard receptacle for USB 2.0 is available. This connector provides an USB OTG interface used in device mode. To avoid any problem of ground-shift, this USB channel is optically isolated. Even if used in device mode, the Remote Check cannot be powered by this connector. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 15/40 HDMI connector X8 3.2.3. On the user side a standard HDMI connector is available. The interface is compatible with the version 1.4 support a graphic full-HD @ 1920x1080 pixel. Ethernet connector X9 3.2.4. On the user side a standard RJ45 for 10/100/1000 Ethernet is available. USB host connector (single) X10 3.2.5. On the user side a Type-A standard single receptacle for USB 2.0 is available. This connector provides an USB interface used in device mode. USB host connector (double) X11 3.2.6. On the user side a Type-A standard double receptacle for USB 2.0 is available. This connector provides an USB interface used in device mode. 3.2.7. SIM e SD holders X12 On the user side 2 holders push-pull type are available. The upper support is for the SIM and the other is for SD card. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 16/40 TELEMACO/RC 2015/ERMETE Internal modules 4. 4.1. Core module This chapter defines the characteristics of a device, hereinafter referred as "core logic" or core module, intended to provide an embedded platform based on iMX6 Freescale ARM processor. This platform integrates the processor, the DDR3 volatile memory bank, the on-chip MMC non-volatile memory bank for storage and the "physical layer" Ethernet for LAN connection. There is also a PMIC for the intelligent management of power supplies and operating states (off, sleep, idle, run). All peripherals of the processor, described below, are available on 3 high density and high speed connectors.
-Connettore J5-
) 4 J
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-PMIC-
-J7- -W3-
4.1.1. Printed circuit board Figure 4 shows the location of the elements on the circuit board of the core logic.
-DDR3-
-DDR3-
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2 J e r o
-MMC-
-iMX6-
e n n o C PHY G A T J t t
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-PMIC-
-DDR3-
-DDR3-
-Connettore J6-
Figure 4: RC2core component placement The PCB is almost square and measures 71x75mm. The left image is the upper side of the core logic, the right is the bottom side. In case of quad/dual core, 4 banks of DDR3 RAM are installed, and in this case the memory bus is 64 bit wide. In case of single core, only 2 banks are installed and the access to the bus is 32 bit wide. 4.1.2. Boot configuration The boot mode can be selected by mounting/dismounting appropriate resistances. There are 3 main ways to boot, summarized in Table 14:
Boot mode Boot from fuses Boot from serial Boot from board settings R32 pull-down pull-down pull-up R34 pull-down pull-up pull-down Table 14: RC2core boot modes The boot from fuses requires that the fuses, internal to the processor, have been previously programmed;
the programming of these fuses cannot be undone once performed. Boot from serial executes a bootloader on UART1 and requires an appropriate programmer. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 17/40 TELEMACO/RC 2015/ERMETE The boot form board setting is the default; at reset, the processor samples the logic state of some pin (ref. Errore. L'origine riferimento non stata trovata.); these pins define the external boot device. 4.1.2.1. Boot from board settings 4.1.2.1. Boot from board settings In this boot mode, the processor, after the reset, samples the state of some pins in order to determine the storage device boot. Because, after the reset, these pins become usable by the application, it is important that all devices connected to these pins, through the interface connectors, do not alter their state during reset. Table 15 lists the sampled pin during the reset. Reset level Signal SPI2_SS1 SPI2_SS0 EIM_A16 EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A23 EIM_DA8 EIM_WAIT Connector 1 pin 41 1 pin 40 3 pin 26 3 pin 20 3 pin 23 3 pin 22 3 pin 16 3 pin 24 3 pin 18 3 pin 28 3 pin 21 H H L L L L L L L L L Table 15: RC2core boot pins at reset iMX6 pin EIM_LBA EIM_RW EIM_A16 EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A23 EIM_DA8 EIM_WAIT In theory, the processor can boot from many sources, including memories connected to the SPI and I2C channels. However, the core logic excludes these possibilities, reducing the possible boot sources to channels SD3, SD4 (where the MMC is connected) and SATA. 4.1.2.1.1. Boot from SD Boot from Secure Digital card is implemented if the card is plugged on the 3rd SD channel (SD3), available on connector J2. Table 16 summarizes how some resistors must be installed to boot from SD. 1-bit boot 4-bit bot R65 yes R64 no R63 no R75 no yes Table 16: RC2core boot from SD 4.1.2.1.2. Boot from MMC Boot from Multimedia Card is implemented on the 4th SD channel (SD4), where an on-chip MMC is connected and available on connector J2. Table 17 summarizes how some resistors must be installed to boot from MMC. 8-bit boot R65 yes R64 yes R63 yes R75 no Table 17: RC2core boot from MMC 4.1.2.1.3. Boot da SATA Boot from SATA is implemented if the device is connected to the SATA channel, available on connector J2. Table 18 summarizes how some resistors must be installed to boot from SATA. Boot a 8bit R65 no R64 yes R63 no R75
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Table 18: RC2core boot from SATA Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 18/40 TELEMACO/RC 2015/ERMETE 4.1.3. Pinout of the interface connectors Below are described the pinout of the connectors interface between the core logic and the carrier board. The following information is reported:
Position: connector pin number Name: signal name Vdd: signal supply Direction: signal direction (from core logic point of view) Description: short description of the signal With regard to "Vdd" item, Table 19 summarizes the possible values of some "special power supply":
iMX6 pin: iMX6s pin where the signal is connected/associated Vdd VDD_SYS LICELL VSNVS Valore [V]
3.7 4.4 3.0 4.4
~3.0 Table 19: RC2core special power supply Warning: there are some signs whose dynamics is not the "classic" 3.3V but only 1.8V. A level shifter may have to be provided on carrier board. Vdd 3.3V 3.3V 3.3V 3.3V VDD_SYS VDD_SYS VDD_SYS VDD_SYS LICELL VDD_SYS VSNVS VSNVS iMX6 pin
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-
-
-
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ONOFF KEY-ROW3 Dir. IN IN IN IN IN IN IN IN BI OUT GPIO_3 OUT KEY_COL3 BI BI OUT OUT GPIO_7 OUT KEY_COL4 IN IN
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4.1.3.1. Connector J2 Table 20 lists the pinout of the connector J2, which provides most of the interfaces of core logic. Pos. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Description Main power supply Main power supply Main power supply Main power supply Stand-by power supply Main power Global reset (iMX6 and PMIC) Power On/Off Data signal of 2nd I2C channel Clock signal of 2nd I2C channel Clock signal of 3rd I2C channel Data signal of 3rd I2C channel Processor reset PMIC SW2 power supply TX signal of 1st CAN channel TX signal of 2nd CAN channel RX signal of 1st CAN channel RX signal of 2nd CAN channel Ground reference Ground reference TX signal of 1st UART channel RX signal of 1st UART channel RX signal of 4th UART channel TX signal of 4th UART channel CTS of 3rd UART channel RTS of 4th UART channel TX signal of 3rd UART channel CTS of 4th UART channel RX signal of 3rd UART channel TX signal of 2nd UART channel RTS of 3rd UART channel VDD_SYS_4V2 VDD_SYS_4V2 VDD_SYS_4V2 VDD_SYS_4V2 P3V3_LICELL VDD_SYS_4V2 PWRON CPU-ONOFF I2C2_SDA I2C3_SCL I2C2_SCL I2C3_SDA POR_B VDD_3V3 CAN1_TX CAN2_TX CAN1_RX CAN2_RX GND GND UART1_TX UART1_RX UART4_RX UART4_TX UART3_CTS UART4_RTS UART3_TX UART4_CTS UART3_RX UART2_TX UART3_RTS OUT CSI0_DAT10 CSI0_DAT11 IN IN CSI0_DAT13 OUT CSI0_DAT12 IN OUT CSI0_DAT16 OUT EIM_D24 CSI0_DAT17 IN IN EIM_D25 OUT EIM_D26 OUT EIM_D31 1.8V 1.8V 1.8V 1.8V 3.3V 1.8V 3.3V 1.8V 3.3V 3.3V 3.3V GPIO_8 KEY_ROW4
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VSNVS 3.3V 3.3V 3.3V 3.3V 3.3V GPIO_6 POR_B
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EIM_D23
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Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 19/40 Pos. Name 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 UART2_RX SPI2_SCLK SPI2_MOSI SPI2_MISO SPI2_SS0 SPI2_SS1 GND GND USB_HOST_DN USB_OTG_DN USB_HOST_DP USB_OTG_DP GND GND VDD_USB_H VDD_USB_O USB_OTG_ID USB_OTG_OC#
USB_OTG_PWR USB_H1_OC#
USB_H1_PWR USB_OTG_OK GND GND PCIE_PWR_EN PCIE_RXM PCIE_WAKE_B PCIE_RXP PCIE_RST_B GND GND PCIE_TXP CLK1_P PCIE_TXM CLK1_N GND GND SD3_DAT1 SD3_DAT0 SD3_DAT6 SD3_CLK SD3_DAT4 SD3_DAT2 SD3_DAT5 SD3_DAT3 SD3_CMD SD3_WP SD3_DAT7 SD3_CD_B GND GND Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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5.0V 5.0V 5.0V 5.0V
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1.8V 3.3V 3.3V 3.3V 1.8V 1.8V
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3.3V 1.35V 3.3V 1.35V 3.3V
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1.35V 1.35V 1.35V 1.35V
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3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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Dir. IN iMX6 pin EIM_D27 OUT EIM_CS0 OUT EIM_CS1 IN EIM_OE OUT EIM_RW OUT EIM_LBA
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USB_HOST_DN BI USB_OTG_DN BI USB_HOST_DP BI USB_OTG_DP BI
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USB_H1_VBUS IN USB_OTG_VBUS IN ENET_RX_ER IN IN EIM_D21 OUT EIM_D22 IN EIM_D30 OUT ENET_TXD1 ENET_RXD0 IN
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OUT EIM_D19 IN IN IN OUT GPIO_17 PCIE_RXM CSI0_DATA_EN PCIE_RXP
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OUT PCIE_TXP OUT CLK1_P OUT PCIE_TXM OUT CLK1_N
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SD3_DAT1 BI SD3_DAT0 BI BI SD3_DAT6 OUT SD3_CLK SD3_DAT4 BI BI SD3_DAT2 SD3_DAT5 BI BI SD3_DAT3 OUT SD3_CMD IN NANDF_D1 SD3_DAT7 BI NANDF_D0 IN
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Description RX signal of 2nd UART channel Clock signal of 2nd SPI channel MOSI signal of 2nd SPI channel MISO signal of 2nd SPI channel Chip-select 0 of 2nd SPI channel Chip-select 1 of 2nd SPI channel Ground reference Ground reference Data- signal of USB host channel Data- signal of USB OTG channel Data+ signal of USB host channel Data+ signal of USB OTG channel Ground reference Ground reference Power supply of USB host channel Power supply of USB OTG channel ID signal of USB OTG channel Overcurrent flag of USB OTG channel Enable signal of USB OTG channel Overcurrent flag of USB host channel Enable signal of USB host channel Feedback signal of USB OTG channel Ground reference Ground reference Enable signal of PCIe channel RX- signal of PCIe channel Wake-up signal of PCIe channel RX+ signal of PCIe channel Reset signal of PCIe channel Ground reference Ground reference TX+ signal of PCIe channel CLK+ signal of PCIe channel TX- signal of PCIe channel CLK- signal of PCIe channel Ground reference Ground reference Data1 signal of 3rd SD channel Data0 signal of 3rd SD channel Data6 signal of 3rd SD channel Clock signal of 3rd SD channel Data4 signal of 3rd SD channel Data2 signal of 3rd SD channel Data5 signal of 3rd SD channel Data3 signal of 3rd SD channel Command signal of 3rd SD channel Write-protect signal of 3rd SD channel Data7 signal of 3rd SD channel Card-detect signal of 3rd SD channel Ground reference Ground reference Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 20/40 Pos. Name 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 SD2_DAT3 SD2_DAT2 SD2_DAT0 SD2_DAT7 SD2_DAT4 SD2_CD_B SD2_DAT5 SD2_CLK SD2_WP SD2_DAT1 SD2_DAT6 SD2_CMD GND GND SATA_TXM SATA_RXM SATA_TXP SATA_RXP GND GND GBE_MDI3-
GBE_MDI1-
GBE_MDI3+
GBE_MDI1+
GND GND GBE_MDI2-
GBE_MDI0-
GBE_MDI2+
GBE_MDI0+
GND GND GBE_LED1 GBE_LED2 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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1.35V 1.35V 1.35V 1.35V
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3.3V 3.3V 3.3V 3.3V
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3.3V 3.3V 3.3V 3.3V
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3.3V 3.3V iMX6 pin SD2_DAT3 SD2_DAT2 SD2_DAT0 NANDF_D7 NANDF_D4 NANDF_D2 NANDF_D5 Dir. BI BI BI BI BI IN BI OUT SD2_CLK NANDF_D3 IN SD2_DAT1 BI BI NANDF_D6 OUT SD2_CMD
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OUT SATA_TXM IN SATA_RXM OUT SATA_TXP SATA_RXP IN
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BI
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BI
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BI
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BI
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BI
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BI
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BI BI
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OUT OUT Description Data3 signal of 2nd SD channel Data2 signal of 2nd SD channel Data0 signal of 2nd SD channel Data7 signal of 2nd SD channel Data4 signal of 2nd SD channel CardDetect signal of 2nd SD channel Data5 signal of 2nd SD channel Clock signal of 2nd SD channel WriteProtect signal of 2nd SD channel Data1 signal of 2nd SD channel Data6 signal of 2nd SD channel Command signal of 2nd SD channel Ground reference Ground reference TX- signal of SATA channel RX- signal of SATA channel TX+ signal of SATA channel RX+ signal of SATA channel Ground reference Ground reference Gigabit Ethernet negative signal 4th pair Gigabit Ethernet negative signal 2nd pair Gigabit Ethernet positive signal 4th pair Gigabit Ethernet positive signal 2nd pair Ground reference Ground reference Gigabit Ethernet negative signal 3rd pair Gigabit Ethernet negative signal 1st pair Gigabit Ethernet positive signal 3rd pair Gigabit Ethernet positive signal 1st pair Ground reference Ground reference Gigabit Ethernet led activity 1 Gigabit Ethernet led activity 2 Table 20: RC2core - J2 connector pinout
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Vdd 4.1.3.2. Connector J5 Table 21 lists the pinout of the connector J5. Pos. Name GND 1 2 GND LVDS1_TX0_N 3 LVDS1_TX3_P 4 LVDS1_TX0_P 5 6 LVDS1_TX3_N GND 7 GND 8 LVDS1_TX1_P 9 LVDS1_CLK_N 10 11 LVDS1_TX1_N LVDS1_CLK_P 12 GND 13 14 GND 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
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Dir.
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OUT OUT OUT OUT OUT OUT OUT OUT iMX6 pin
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LVDS1_TX0_N LVDS1_TX3_P LVDS1_TX0_P LVDS1_TX3_N
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LVDS1_TX1_P LVDS1_CLK_N LVDS1_TX1_N LVDS1_CLK_P
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Description Ground reference Ground reference TX- signal of 1st pair on 2nd LVDS channel TX+ signal of 4th pair on 2nd LVDS channel TX+ signal of 1st pair on 2nd LVDS channel TX- signal of 4th pair on 2nd LVDS channel Ground reference Ground reference TX+ signal of 2nd pair on 2nd LVDS channel CLK- signal of 2nd LVDS channel TX- signal of 2nd pair on 2nd LVDS channel CLK+ signal of 2nd LVDS channel Ground reference Ground reference Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 21/40 Pos. Name 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 LVDS0_TX0_N LVDS1_TX2_P LVDS0_TX0_P LVDS1_TX2_N GND GND LVDS0_CLK_N LVDS0_TX3_N LVDS0_CLK_P LVDS0_TX3_P GND GND LVDS0_TX1_N LVDS0_TX2_N LVDS0_TX1_P LVDS0_TX2_P GND GND NANDF_CS3 NANDF_CS2 NANDF_CLE NANDF_ALE GND GND MICROPHONE_DET GPIO_0_CLKO KEY_VOL_DN CODEC_PWR_EN KEY_VOL_UP AUD3_RXD AUD3_TXC AUD3_TXD AUD3_TXFS HEADPHONE_DET SD1_DAT3 I2C1_SDA VDD_5V_PMIC I2C1_SCL GND GND HDMI_D0P HDMI_CEC_IN HDMI_D0M HDMI_HPD GND GND HDMI_D1P HDMI_D2P HDMI_D1M HDMI_D2M GND GND HDMI_DDC_SCL HDMI_CLKM HDMI_DDC_SDA Vdd 2.5V 2.5V 2.5V 2.5V
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2.5V 2.5V 2.5V 2.5V
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2.5V 2.5V 2.5V 2.5V
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3.3V 3.3V 3.3V 3.3V
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3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.8V 1.8V 1.8V 3.3V 1.8V 1.8V 5.0V 1.8V
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1.35V 3.3V 1.35V 1.35V
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1.35V 1.35V 1.35V 1.35V
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3.3V 1.35V 3.3V
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OUT OUT OUT OUT OUT OUT OUT OUT Dir. OUT OUT OUT OUT iMX6 pin LVDS0_TX0_N LVDS1_TX2_P LVDS0_TX0_P LVDS1_TX2_N
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LVDS0_CLK_N LVDS0_TX3_N LVDS0_CLK_P LVDS0_TX3_P
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LVDS0_TX1_N LVDS0_TX2_N LVDS0_TX1_P LVDS0_TX2_P
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NANDF_CS3 BI NANDF_CS2 BI NANDF_CLE BI NANDF_ALE BI
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GPIO_9 IN OUT GPIO_0 BI GPIO_5 OUT KEY_COL2 BI GPIO_4 IN CSI0_DAT7 OUT CSI0_DAT4 OUT CSI0_DAT5 OUT CSI0_DAT6 IN BI BI OUT OUT CSI0_DAT9 SD3_RST SD1_DAT3 CSI0_DAT8
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OUT HDMI_D0P IN KEY_ROW2 OUT HDMI_D0M OUT HDMI_HPD
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OUT HDMI_D1P OUT HDMI_D2P OUT HDMI_D1M OUT HDMI_D2M
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OUT KEY_COL3 OUT HDMI_CLKM IN KEY-ROW3 Description TX- signal of 1st pair on 1st LVDS channel TX+ signal of 3rd pair on 2nd LVDS channel TX+ signal of 1st pair on 1st LVDS channel TX- signal of 3rd pair on 2nd LVDS channel Ground reference Ground reference CLK- signal of 1st LVDS channel TX- signal of 4th pair on 1st LVDS channel CLK+ signal of 1st LVDS channel TX+ signal of 4th pair on 1st LVDS channel Ground reference Ground reference TX- signal of 2nd pair on 1st LVDS channel TX- signal of 3rd pair on 1st LVDS channel TX+ signal of 2nd pair on 1st LVDS channel TX+ signal of 3rd pair on 1st LVDS channel Ground reference Ground reference General purpose IO General purpose IO General purpose IO General purpose IO Ground reference Ground reference Audio microphone detection signal Audio clock signal Audio decrease volume control Audio enable signal Audio increase volume control Audio ADC digital audio data Audio bit clock Audio DAC digital audio data Audio left / right clock Audio headphone detection signal General purpose IO Data signal of 1st I2C channel PMIC SWBST power supply Clock signal of 1st I2C channel Ground reference Ground reference D+ signal of 1st pair on HDMI channel CEC signal on HDMI channel D- signal of 1st pair on HDMI channel HDP signal on HDMI channel Ground reference Ground reference D+ signal of 2nd pair on HDMI channel D+ signal of 3rd pair on HDMI channel D- signal of 2nd pair on HDMI channel D- signal of 3rd pair on HDMI channel Ground reference Ground reference Clock signal of I2C channel on HDMI channel CLK- signal on HDMI channel Data signal of I2C channel on HDMI channel Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 22/40 Pos. Name 70 HDMI_CLKP Vdd 1.35V iMX6 pin Dir. OUT HDMI_CLKP Description CLK+ signal on HDMI channel Table 21: RC2core J5 connector pinout
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3.3V 1.8V 1.8V 1.8V 1.8V 1.8V Vdd 3.3V 3.3V 4.1.3.3. Connector J6 Table 22 lists the pinout of the connector J6. Pos. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GPIO_16 GPIO_19 GND GPIO_2 UART5_TX GND UART5_CTS UART5_RX GND UART5_RTS ENET_TXD0 GND EIM_BCLK EIM_D16 EIM_D28 EIM_A20 NANDF_WP_B EIM_A23 NANDF_CS0 EIM_A17 EIM_WAIT EIM_A19 EIM_A18 EIM_A21 NANDF_CS1 EIM_A16 NANDF_RB0 EIM_DA8 GND GND SD1_DAT1 SD1_CLK SD1_DAT2 SD1_DAT0 GND SD1_CMD DISP0_CLK GND DISP0_VSYNC DISP0_HSYNC DISP0_DAT1 DISP0_DRDY DISP0_DAT4 DISP0_DAT16 DISP0_DAT3 DISP0_DAT15 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.8V 1.8V 1.8V 1.8V 3.3V
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iMX6 pin GPIO_16 GPIO_19
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GPIO_2 Dir. BI BI
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BI OUT CSI0_DAT14
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IN IN
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CSI0_DAT19 CSI0_DAT15
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OUT CSI0_DAT18 ENET_TXD0 BI
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BI EIM_BCLK EIM_D16 BI EIM_D28 BI EIM_A20 BI BI NANDF_WP_B EIM_A23 BI NANDF_CS0 BI EIM_A17 BI BI EIM_WAIT EIM_A19 BI EIM_A18 BI EIM_A21 BI BI NANDF_CS1 EIM_A16 BI NANDF_RB0 BI EIM_DA8 BI
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SD1_DAT1 BI SD1_CLK BI SD1_DAT2 BI BI SD1_DAT0
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BI SD1_CMD OUT DIO_DISP_CLK
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OUT DIO_PIN3 OUT DIO_PIN2 OUT DISP0_DAT1 OUT DIO_PIN15 OUT DISP0_DAT4 OUT DISP0_DAT16 OUT DISP0_DAT3 OUT DISP0_DAT15 Description General purpose IO General purpose IO Ground reference General purpose IO TX signal of 5th UART channel Ground reference CTS signal of 5th UART channel RX signal of 5th UART channel Ground reference RTS signal of 5th UART channel General purpose IO Ground reference General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO Ground reference Ground reference General purpose IO General purpose IO General purpose IO General purpose IO Ground reference General purpose IO Clock signal of parallel video output Ground reference Vsync signal of parallel video output Hsync signal of parallel video output Data1 signal of parallel video output Data Enable signal of parallel video output Data4 signal of parallel video output Data16 signal of parallel video output Data3 signal of parallel video output Data15 signal of parallel video output Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 23/40 Pos. Name 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 DISP0_CNTRST DISP0_DAT20 DISP0_DAT0 DISP0_DAT10 GND GND DISP0_DAT5 DISP0_DAT2 DISP0_DAT7 DISP0_DAT8 DISP0_DAT9 DISP0_DAT6 DISP0_DAT12 DISP0_DAT13 GND GND DISP0_DAT14 DISP0_DAT11 DISP0_DAT17 DISP0_DAT21 DISP0_DAT18 DISP0_DAT19 DISP0_DAT22 DISP0_DAT23 Vdd 3.3V 3.3V 3.3V 3.3V
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3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Dir. iMX6 pin OUT DIO_PIN4 OUT DISP0_DAT20 OUT DISP0_DAT0 OUT DISP0_DAT10
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OUT DISP0_DAT5 OUT DISP0_DAT2 OUT DISP0_DAT7 OUT DISP0_DAT8 OUT DISP0_DAT9 OUT DISP0_DAT6 OUT DISP0_DAT12 OUT DISP0_DAT13
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OUT DISP0_DAT14 OUT DISP0_DAT11 OUT DISP0_DAT17 OUT DISP0_DAT21 OUT DISP0_DAT18 OUT DISP0_DAT19 OUT DISP0_DAT22 OUT DISP0_DAT23 Description Contrast signal of parallel video output Data20 signal of parallel video output Data0 signal of parallel video output Data10 signal of parallel video output Ground reference Ground reference Data5 signal of parallel video output Data2 signal of parallel video output Data7 signal of parallel video output Data8 signal of parallel video output Data9 signal of parallel video output Data6 signal of parallel video output Data12 signal of parallel video output Data13 signal of parallel video output Ground reference Ground reference Data14 signal of parallel video output Data11 signal of parallel video output Data17 signal of parallel video output Data21 signal of parallel video output Data18 signal of parallel video output Data19 signal of parallel video output Data22 signal of parallel video output Data23 signal of parallel video output 4.1.4. Peripherals and available interfaces Table 22: RC2core J6 connector pinout Power supply and control signals 4.1.4.1. Table 23 summarizes the power supply and control signals of the core logic, all available on the connector J2. Signal VDD_SYS_4V2 P3V3_LICELL VDD_3V3 PWRON CPU-ONOFF POR_B Vdd Pos. Conn. 1,2,3,4,6 iMX6 pin
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ONOFF POR_B Table 23: RC2core power supply and control signals VDD_SYS LICELL 3.3V 3.0V 3.0V 3.0V Dir. IN IN OUT IN IN BI J2 J2 J2 J2 J2 J2 5 14 7 8 13 VDD_SYS_4V2 is the main power supply of all core logic. It delivers all the current absorbed by the core and must be connected to a voltage regulator, with dynamic compatible with "VDD_SYS" (ref. Table 19), capable of providing approximately 10W. On the control board, is better to "strengthen" the corresponding pins with a low ESR capacitor greater than 100F. Through the connector W3 is possible to power the core logic without using the main connector J2. The pinout of this auxiliary connector is summarized in Table 24. Signal VDD_SYS_4V2 GND Pos. 1 2 Table 24: RC2core auxiliary power supply on W3 connector P3V3_LICELL is the power supply for the stand-by management. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 24/40 TELEMACO/RC 2015/ERMETE It can be connected to a battery with dynamic compatible with "LICELL" (ref. Table 19) or to a source of energy always present and with similar dynamics. If the stand-by state is not required, this signal can be left floating. VDD_3V3 is the 3.3V power supply used for most of the devices of the core. It is made available on the connector only for reference and/or to inform the carrier board that the processor is "on". It is not recommended to use this signal to supply other components. PWRON is the signal that allow the brutal restart of the core logic. The signal has a pull-up and is active low; can be connected to a switch or a device that closes it to ground. If PWRON is asserted, the system resets and restarts with complete re-boot. CPU-ONOFF is the signal that allows the power management of the processor. The signal has a pull-up and is active low; can be connected to a switch or a device that closes it to ground. Since it is referred to the stand-by voltage (VSNVS), the signal allows the "intelligent" management of the supply core logic. In particular:
if CPU-ONOFF is asserted for less than 1 processor goes into stand-by if CPU-ONOFF is asserted for more than 5 processor turns off (shutdown) if CPU-ONOFF is asserted for less than 1 the processor starts the system, with complete boot if the processor is on:
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if the processor is off:
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if the processor is in stand-by state:
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if CPU-ONOFF is asserted for less than 1 the processor restart the system, without boot POR_B is the signal that allows the processor reset. The signal has a pull-up and is active low; in order to execute the reset, it can be connected to a switch or a device that closes it to ground; at the same time, it can be monitored from the carrier board, reading it in high impedance. 4.1.4.2. Asynchronous serial channels Table 25 summarizes the asynchronous serial channels provided by the core logic. In total, 5 serial ports are available, 2 lines have 2 wire and the other 3 have 4 wires. The flow control signals of the 4-wire serial ports are of course optional. If any signal of the table is not used, it can be set as general purpose IO. All serial ports have a maximum transmission speed of 4Mbps. Signal UART1_TX UART1_RX UART2_TX UART2_RX UART3_TX UART3_RX UART3_RTS UART3_CTS UART4_TX UART4_RX UART4_RTS UART4_CTS UART5_TX UART5_RX UART5_RTS UART5_CTS Conn. J2 J2 J2 J2 J2 J2 J2 J2 J2 J2 J2 J2 J6 J6 J6 J6 Pos. 21 22 30 32 27 29 31 25 24 23 26 28 5 8 10 7 Vdd 1.8V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V iMX6 pin Dir. OUT CSI0_DAT10 IN CSI0_DAT11 OUT EIM_D26 IN EIM_D27 OUT EIM_D24 IN EIM_D25 OUT EIM_D31 IN EIM_D23 OUT CSI0_DAT12 IN CSI0_DAT13 OUT CSI0_DAT16 IN CSI0_DAT17 OUT CSI0_DAT14 IN CSI0_DAT15 OUT CSI0_DAT18 IN CSI0_DAT19 Table 25: RC2core - asynchronous serial channels The UART1 dynamics is 1.8V and the UART1_RX signal has a pull-up. Since this serial is uses as OS console, it would be appropriate to use it always just for this purpose. The UART1 is also available on connector J7, in order to be able to connect a console to the core logic without using the main connector J2. The J7 connector pinout is resumed on Table 26. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 25/40 Signal ENABLE TX-DEBUG RX-DEBUG GND Pos. 1 2 3 4 Vdd 3.3V 3.3V 3.3V
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Dir. IN IN OUT
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Table 26: RC2core auxiliary connector for console Between the connector J7 and UART1 port, a level shifter is provided; it adapts all UART1 signals to 3.3V. The signal TX-DEBUG is headed to UART1_RX; signal RX-DEBUG is headed to UART1_TX. If the ENABLE signal is connected to 3.3V then level shifter is enabled, else the translator is forced into high impedance. The UART2 dynamics is 3.3V and its 2 signals have no pull-up/down. The UART3 dynamics is 3.3V and its 4 signals have no pull-up/down. The UART4 dynamics is 1.8V and its 4 signals have no pull-up/down. The UART5 dynamics is 1.8V and its 4 signals have no pull-up/down. I2C channels 4.1.4.3. Table 27 summarizes the I2C channels provided by the core logic. All I2C channels have a maximum transmission rate of 400kbps. Signal I2C1_SDA I2C1_SCL I2C2_SDA I2C2_SCL I2C3_SDA I2C3_SCL Conn. 2 2 1 1 1 1 Pos. 50 52 9 11 12 10 Vdd 1.8V 1.8V 3.3V 3.3V 3.3V 3.3V iMX6 pin Dir. BI CSI0_DAT8 OUT CSI0_DAT9 BI KEY-ROW3 OUT KEY_COL3 BI GPIO_6 OUT GPIO_3 Table 27: RC2core I2C channels The I2C1 dynamics is 1.8V and its 2 signals have pull-up. The I2C2 dynamics is 3.3V and its 2 signals have pull-up. The I2C3 dynamics is 3.3V and its 2 signals have pull-up. 4.1.4.4. CAN channels Table 28 summarizes the CAN channels provided by the core logic. All CAN channels have a maximum transmission rate of 1Mbps. Signal CAN1_TX CAN1_RX CAN2_TX CAN2_RX Conn. 1 1 1 1 Pos. 15 17 16 18 Vdd 3.3V 3.3V 3.3V 3.3V Dir. iMX6 pin OUT GPIO_7 IN GPIO_8 OUT KEY_COL4 KEY_ROW4 IN Table 28: RC2core CAN channels The CAN1 dynamics is 3.3V and its 2 signals have no pull-up/down. The CAN2 dynamics is 3.3V and its 2 signals have no pull-up/down. SPI channels 4.1.4.5. Table 29 summarizes the SPI channels provided by the core logic. The first channel (SPI1) has only 1 chip-select; the second channel (SPI2) has 2 chip-selects. All SPI channels have a maximum transmission rate of 50Mbps. Signal Conn. Pos. Vdd Dir. iMX6 pin Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 26/40 Signal SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SS0 SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SS0 SPI2_SS1 Conn. 1 1 1 1 1 1 1 1 1 Pos. 33 35 34 36 39 38 37 40 41 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V iMX6 pin Dir. IN KEY_COL1 OUT KEY_ROW0 OUT KEY_COL0 OUT KEY_ROW1 IN EIM_OE OUT EIM_CS1 OUT EIM_CS0 OUT EIM_RW OUT EIM_LBA Table 29: RC2core SPI channels The SPI1 dynamics is 3.3V; SPI1_SS0 has pull-up, the others have no pull-up/down. The SPI2 dynamics is 3.3V; SPI2_SS0 and SPI2_SS1 have pull-up, the others have no pull-up/down. 4.1.4.6. USB channels Table 30 summarizes the USB channels provided by the core logic. The first channel is a HSB host 2.0; the second channel is a USB OTG 2.0. Both USB channels have a maximum transmission rate of 480Mbps. Signal USB_HOST_DN USB_HOST_DP USB_H1_OC#
USB_H1_PWR VDD_USB_H USB_OTG_DN USB_OTG_DP USB_OTG_ID USB_OTG_OC#
USB_OTG_PWR USB_OTG_OK VDD_USB_O Conn. 1 1 1 1 1 1 1 1 1 1 1 1 Pos. 44 46 55 56 50 45 47 52 53 54 57 51 Vdd 5.0V 5.0V 3.3V 1.8V
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5.0V 5.0V 1.8V 3.3V 3.3V 1.8V
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iMX6 pin USB_HOST_DN USB_HOST_DP EIM_D30 Dir. BI BI IN OUT ENET_TXD1 USB_H1_VBUS IN USB_OTG_DN BI USB_OTG_DP BI ENET_RX_ER IN EIM_D21 IN OUT EIM_D22 IN IN ENET_RXD0 USB_OTG_VBUS Table 30: RC2core USB channels USB_HOST_DN and USB_HOST_DP are the USB host data. USB_H1_OC# dynamics is 3.3V; it is the over-current flag, is active low and has a pull-up. USB_H1_PWR dynamics is 1.8V; it is the enable signal for the USB host power supply, is active high and has a pull-down. It is used to turn on an external voltage regulator able to providing VDD_USB_H. VDD_USB_H dynamics is 5V; it is the USB transceiver power supply (internal to the processor). USB_OTG_DN and USB_OTG_DP are the USB OTG data. USB_OTG_ID dynamics is 1.8V; it is the IDentification signal. USB_OTG_OC# dynamics is 3.3V; it is the over-current flag, is active low and has a pull-up. USB_OTG_PWR dynamics is 3.3V; it is the enable signal for the USB OTG power supply, is active high and has a pull-down. It is used to turn on an external voltage regulator able to providing VDD_USB_O. USB_OTG_OK dynamics is 1.8V; it allows to the processor to know if the supply VDD_USB_O is correct; it is active low ahd has a pull-up. VDD_USB_O dynamics is 5V; it is the USB OTG transceiver power supply (internal to the processor). Caution: the USB channels deliver high-frequency signals. PCIe channel 4.1.4.7. Table 31 summarizes the PCIe channel provided by the core logic. The PCIe channel have a maximum transmission rate of 2.5Gbps. Signal Conn. Pos. Vdd Dir. iMX6 pin Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 27/40 Signal PCIE_TXM PCIE_TXP PCIE_RXM PCIE_RXP CLK1_N CLK1_P PCIE_RST_B PCIE_PWR_EN PCIE_WAKE_B Conn. 1 1 1 1 1 1 1 1 1 Pos. 69 67 61 63 70 68 64 60 62 Vdd 1.35V 1.35V 1.35V 1.35V 1.35V 1.35V 3.3V 3.3V 3.3V iMX6 pin Dir. OUT PCIE_TXM OUT PCIE_TXP PCIE_RXM IN IN PCIE_RXP OUT CLK1_N OUT CLK1_P OUT GPIO_17 OUT EIM_D19 IN CSI0_DATA_EN Table 31: RC2core PCIe channels PCIE_TXM and PCIE_TXP are the Tx differential pair. PCIE_RXM and PCIE_RXP are the Rx differential pair. CLK1_N and CLK1_P are the Clk differential pair. PCIE_RST_B dynamics is 3.3V; it allows to reset any device connected to PCIe channel; it is active low e has no pull-up/down. PCIE_PWR_EN dynamics is 3.3V; it allows to control the power supply of any device connected to PCIe channel; it is active high e has no pull-up/down. PCIE_WAKE_B dynamics is 3.3V; it is the wake-up signal from PCIe channel; the signal is optional because the wake-up is typically required with an appropriate message on the channel PCIe. Caution: the PCIe channel deliver high-frequency signals. SATA channel 4.1.4.8. Table 32 summarizes the SATA channel provided by the core logic. The SATA channel have a maximum transmission rate of 3Gbps. Signal SATA_TXM SATA_TXP SATA_RXM SATA_RXP Conn. 1 1 1 1 Pos. 101 103 102 104 Vdd 1.35V 1.35V 1.35V 1.35V iMX6 pin Dir. OUT SATA_TXM OUT SATA_TXP IN SATA_RXM SATA_RXP IN Table 32: RC2core SATA channel SATA _TXM and SATA _TXP are the Tx differential pair. SATA _RXM and SATA _RXP are the Rx differential pair. Caution: the SATA channel deliver high-frequency signals. Ethernet channel 4.1.4.9. Table 33 summarizes the Ethernet channel provided by the core logic. All the signals are provided by a PHY compatible with the formats 10/100/1000Mbit. The carrier board must provide the connection with a transformer or a switch. Signal GBE_MDI0-
GBE_MDI0+
GBE_MDI1-
GBE_MDI1+
GBE_MDI2-
GBE_MDI2+
GBE_MDI3-
GBE_MDI3+
GBE_LED1 GBE_LED2 Conn. 1 1 1 1 1 1 1 1 1 1 Pos. 114 116 108 110 113 115 107 109 119 120 iMX6 pin
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Table 33: RC2core Ethernet channel Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Dir. BI BI BI BI BI BI BI BI BI BI Doc: ANNEX II M-RP_01-02 Rev.03 USER MANUAL PRODUCT NAME:
Computers TELEMACO/RC 2015/ERMETE GBE_MDI0- and GBE_MDI0+ are the 1st pair. For a 10/100Mbit connection, this is the TX pair. GBE_MDI1- and GBE_MDI1+ are the 2nd pair. For a 10/100Mbit connection, this is the RX pair GBE_MDI2- and GBE_MDI2+ are the 3rd pair. GBE_MDI3- and GBE_MDI3+ are the 4th pair. GBE_LED1 and GBE_LED2 are the led-activity signals. Caution: the Ethernet channel deliver high-frequency signals. 15/10/2015 Rev.0.5 Pag. 28/40 4.1.4.10. Secure Digital channels Table 34 summarizes the SD-card channels provided by the core logic. They are 2 complete SD-card channels able to connect card in 1, 4, 8-bit mode. Signal SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD2_DAT4 SD2_DAT5 SD2_DAT6 SD2_DAT7 SD2_CLK SD2_CMD SD2_CD_B SD2_WP SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 SD3_DAT4 SD3_DAT5 SD3_DAT6 SD3_DAT7 SD3_CLK SD3_CMD SD3_CD_B SD3_WP Conn. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pos. 89 96 88 87 91 93 97 90 94 98 92 95 74 73 78 80 77 79 75 83 76 81 84 82 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V iMX6 pin SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 NANDF_D4 NANDF_D5 NANDF_D6 NANDF_D7 Dir. BI BI BI BI BI BI BI BI OUT SD2_CLK OUT SD2_CMD NANDF_D2 IN NANDF_D3 IN SD3_DAT0 BI BI SD3_DAT1 SD3_DAT2 BI SD3_DAT3 BI SD3_DAT4 BI SD3_DAT5 BI BI SD3_DAT6 BI SD3_DAT7 OUT SD3_CLK OUT SD3_CMD IN NANDF_D0 NANDF_D1 IN Table 34: RC2core SD-card channel The SD2 dynamics is 3.3V and all signals have no pull-up/down. The SD3 dynamics is 3.3V and all signals have no pull-up/down. The CardDetect signals are active low; the WriteProtect signals are active high. 4.1.4.11. HDMI channel Table 35 summarizes the HDMI channel provided by the core logic. This video output supports resolutions up to 1920x1200 and a pixel-rate up to 266MHz. The carrier board must provide a level-shifter for the EDID signals and the ESD protections. Signal HDMI_D0M HDMI_D0P HDMI_D1M HDMI_D1P HDMI_D2M HDMI_D2P HDMI_CLKM Conn. 2 2 2 2 2 2 2 Pos. 57 55 63 61 64 62 68 Vdd 1.35V 1.35V 1.35V 1.35V 1.35V 1.35V 1.35V iMX6 pin Dir. OUT HDMI_D0M OUT HDMI_D0P OUT HDMI_D1M OUT HDMI_D1P OUT HDMI_D2M OUT HDMI_D2P OUT HDMI_CLKM Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 29/40 Signal HDMI_CLKP HDMI_DDC_SDA HDMI_DDC_SCL HDMI_HPD HDMI_CEC_IN VDD_5V_PMIC Conn. iMX6 pin 2 2 2 2 2 2 Pos. 70 69 67 58 56 51 Dir. OUT HDMI_CLKP IN KEY-ROW3 OUT KEY_COL3 OUT HDMI_HPD KEY_ROW2 IN OUT
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Table 35: RC2core HDMI channel Vdd 1.35V 3.3V 3.3V 1.35V 3.3V 5.0V HDMI_D0M and HDMI_D0P are the 1st pair. HDMI_D1M and HDMI_D1P are the 2nd pair. HDMI_D2M and HDMI_D2P are the 3rd pair. HDMI_CLKM and HDMI_CLKP are the Clk pair. HDMI_HPD is the HDP (Hot Plug Detect) signal. HDMI_CEC_IN is the CEC (Consumer Electronics Control) signal. HDMI_DDC_SDA and HDMI_DDC_SCL dynamics is 3.3V; they are the dedicated I2C channel (EDID). VDD_5V_PMIC is the 5V voltage required to supply the level translator for EDID signals. Caution: the HDMI channel deliver high-frequency signals. 4.1.4.12. LVDS channels Table 36 summarizes the LVDS channels provided by the core logic. This video output supports resolutions up to 1920x1200 and a pixel-rate up to 170MHz. Signal LVDS0_TX0_N LVDS0_TX0_P LVDS0_TX1_N LVDS0_TX1_P LVDS0_TX2_N LVDS0_TX2_P LVDS0_TX3_N LVDS0_TX3_P LVDS0_CLK_N LVDS0_CLK_P LVDS1_TX0_N LVDS1_TX0_P LVDS1_TX1_N LVDS1_TX1_P LVDS1_TX2_N LVDS1_TX2_P LVDS1_TX3_N LVDS1_TX3_P LVDS1_CLK_N LVDS1_CLK_P Conn. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Pos. 15 17 27 29 28 30 22 24 21 23 3 5 11 9 18 16 6 4 10 12 Dir. OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Table 36: RC2core LVDS channel Vdd 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V iMX6 pin LVDS0_TX0_N LVDS0_TX0_P LVDS0_TX1_N LVDS0_TX1_P LVDS0_TX2_N LVDS0_TX2_P LVDS0_TX3_N LVDS0_TX3_P LVDS0_CLK_N LVDS0_CLK_P LVDS1_TX0_N LVDS1_TX0_P LVDS1_TX1_N LVDS1_TX1_P LVDS1_TX2_N LVDS1_TX2_P LVDS1_TX3_N LVDS1_TX3_P LVDS1_CLK_N LVDS1_CLK_P LVDS0_TX0_N and LVDS0_TX0_P are the 1st pair on 1st channel. LVDS0_TX1_N and LVDS0_TX1_P are the 2nd pair on 1st channel. LVDS0_TX2_N and LVDS0_TX2_P are the 3rd pair on 1st channel. LVDS0_TX3_N and LVDS0_TX3_P are the 4th pair on 1st channel. Lvds0_Clk_N and Lvds0_Clk_P are the Clk pair on 1st channel. LVDS1_TX0_N and LVDS1_TX0_P are the 1st pair on 2nd channel. LVDS1_TX1_N and LVDS1_TX1_P are the 2nd pair on 2nd channel. LVDS1_TX2_N and LVDS1_TX2_P are the 3rd pair on 2nd channel. LVDS1_TX3_N and LVDS1_TX3_P are the 4th pair on 2nd channel. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 30/40 Lvds1_Clk_N and Lvds1_Clk_P are the Clk pair on 2nd channel. The LVDS dynamics is 2.5V. Caution: the LVDS channel deliver high-frequency signals. 4.1.4.13. Audio channels Table 37 summarizes the digital audio channels provided by the core logic. This audio output supports two AC97 stereo channels up to 1.4Mbps. Signal AUD3_TXC AUD3_TXFS AUD3_TXD AUD3_RXD GPIO_0_CLKO MICROPHONE_DET HEADPHONE_DET KEY_VOL_UP KEY_VOL_DN CODEC_PWR_EN Conn. 2 2 2 2 2 2 2 2 2 2 Pos. 45 47 46 44 40 39 48 43 41 42 Vdd 1.8V 1.8V 1.8V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V iMX6 pin Dir. OUT CSI0_DAT4 OUT CSI0_DAT6 OUT CSI0_DAT5 IN CSI0_DAT7 OUT GPIO_0 GPIO_9 IN SD3_RST IN BI GPIO_4 BI GPIO_5 OUT KEY_COL2 Table 37: RC2core LVDS channel AUD3_TXC dynamics is 1.8V and it is the bit clock. AUD3_TXFS dynamics is 1.8V and it is the left/right clock. AUD3_TXD dynamics is 1.8V and it is the digital output stream (from processor to codec). AUD3_RXD dynamics is 1.8V and it is the digital input stream (from codec to processor). GPIO_0_CLKO dynamics is 3.3V and it is the master clock for the external codec. MICROPHONE_DET dynamics is 3.3V and it is the microphone detection signal, is active low and has no pull-
up/down. HEADPHONE_DET dynamics is 3.3V and it is the headphone detection signal, is active low and has no pull-
up/down. KEY_VOL_UP dynamics is 3.3V and it is the volume increase control; is active low and has no pull-up/down. KEY_VOL_DN dynamics is 3.3V and it is the volume decrease control. attivo basso e non ha nessun pull-
up. CODEC_PWR_EN dynamics is 3.3V and it is the codec enable, is active high e has no pull-up/down. 4.1.4.14. Parallel RGB channel Table 38 summarizes the parallel RGB channel provided by the core logic. This video output manages a 24 bit bus (8 bit per pixel) and support resolutions up to 1920x1200 and a pixel-rate up to 100MHz. Signal DISP0_CLK DISP0_HSYNC DISP0_VSYNC DISP0_DRDY DISP0_CNTRST DISP0_DAT0 DISP0_DAT1 DISP0_DAT2 DISP0_DAT3 DISP0_DAT4 DISP0_DAT5 DISP0_DAT6 DISP0_DAT7 DISP0_DAT8 Conn. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pos. 37 40 39 42 47 49 41 54 45 43 53 58 55 56 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V iMX6 pin Dir. OUT DIO_DISP_CLK OUT DIO_PIN2 OUT DIO_PIN3 OUT DIO_PIN15 OUT DIO_PIN4 OUT DISP0_DAT0 OUT DISP0_DAT1 OUT DISP0_DAT2 OUT DISP0_DAT3 OUT DISP0_DAT4 OUT DISP0_DAT5 OUT DISP0_DAT6 OUT DISP0_DAT7 OUT DISP0_DAT8 Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 31/40 Signal DISP0_DAT9 DISP0_DAT10 DISP0_DAT11 DISP0_DAT12 DISP0_DAT13 DISP0_DAT14 DISP0_DAT15 DISP0_DAT16 DISP0_DAT17 DISP0_DAT18 DISP0_DAT19 DISP0_DAT20 DISP0_DAT21 DISP0_DAT22 DISP0_DAT23 Conn. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pos. 57 50 64 59 60 63 46 44 65 67 68 48 66 69 70 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V iMX6 pin Dir. OUT DISP0_DAT9 OUT DISP0_DAT10 OUT DISP0_DAT11 OUT DISP0_DAT12 OUT DISP0_DAT13 OUT DISP0_DAT14 OUT DISP0_DAT15 OUT DISP0_DAT16 OUT DISP0_DAT17 OUT DISP0_DAT18 OUT DISP0_DAT19 OUT DISP0_DAT20 OUT DISP0_DAT21 OUT DISP0_DAT22 OUT DISP0_DAT23 Table 38: RC2core parallel RGB channel DISP0_CLK dynamics is 3.3V and it is the pixel clock. DISP0_HSYNC dynamics is 3.3V and it is the horizontal sync pulses. DISP0_VSYNC dynamics is 3.3V and it is the vertical sync pulses. DISP0_DRDY dynamics is 3.3V and it is the pixel enable. DISP0_CNTRST dynamics is 3.3V and it is the contrast signal. Conn. 4.1.4.15. GPIOs Table 38 summarizes the GPIOs provided by the core logic. Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.8V 1.8V 1.8V 1.8V Signal NANDF_CS3 NANDF_CS2 NANDF_CLE NANDF_ALE GPIO_16 GPIO_19 GPIO_2 ENET_TXD0 EIM_BCLK EIM_D16 EIM_D28 EIM_A20 NANDF_WP_B EIM_A23 NANDF_CS0 EIM_A17 EIM_WAIT EIM_A19 EIM_A18 EIM_A21 NANDF_CS1 EIM_A16 NANDF_RB0 EIM_DA8 SD1_DAT1 SD1_CLK SD1_DAT2 SD1_DAT0 Pos. 33 34 35 36 1 2 4 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31 32 33 34 J5 J5 J5 J5 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 J6 Dir. BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI iMX6 pin NANDF_CS3 NANDF_CS2 NANDF_CLE NANDF_ALE GPIO_16 GPIO_19 GPIO_2 ENET_TXD0 EIM_BCLK EIM_D16 EIM_D28 EIM_A20 NANDF_WP_B EIM_A23 NANDF_CS0 EIM_A17 EIM_WAIT EIM_A19 EIM_A18 EIM_A21 NANDF_CS1 EIM_A16 NANDF_RB0 EIM_DA8 SD1_DAT1 SD1_CLK SD1_DAT2 SD1_DAT0 Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 32/40 Signal SD1_CMD Conn. J6 Pos. 36 Vdd 1.8V Dir. BI iMX6 pin SD1_CMD Table 39: RC2core GPIO Caution: some signals have 1.8V dynamics, all other 3.3V, therefore on carrier board a level-shifter may be needed. The direction of all the GPIO is "bi-directional", with means that the direction is not fixed, as all other signals, but is programmable via SW. 4.2. Carrier module This chapter defines the characteristics of a device, hereinafter referred as "carrier module", intended to provide the support base and all the connectivity for the core logic to the external world.
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9 1 J
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4.2.1. Printed circuit board Figure 4 shows the location of the elements on the circuit board of the core logic.
-J10-
-J11-
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7 J
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5 J
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Figure 5: RC2carrier component placement
-J14-
-J9-
Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 33/40 J3 is the jack connector per the auxiliary power supply, J4 is the connector for the USB device, J6 is the HDMI connector, J10 is the Ethernet connector, J12 and J15 are the connectors for USB host J9 is the automotive connector vehicle-side;
J7 and J11 are the connectors for the core logic;
in the left side, are visible:
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J20 is the connector for the communication module;
J19 is the connector for the diagnosis module;
J8 e J14 are the connectors for the expansion module;
J1 can be connected to the debug connector on logic core (J7, ref. Table 26); this allow to translate the logic level signal into RS232 levels; the converted signals are available in connector J5 J17 is the connector per the internal backup battery The PCB is almost square and measures 161x146mm. In the carrier board the LVDS, RGB-parallel, SATA, SPI and some GPIO are completely unused; the serial lines, USB, PCIe, HDMI, Ethernet and SD interfaces are instead needed by the devices installed on carrier and communication modules; this allows to use only 2 of the 3 high density connectors on the bottom face of the core logic; therefore, the carrier module only uses the connectors J7 and J11 (associated with J2 and J5 on the core logic). For the pinout of connector J7, refer to 4.1.3.2; for the pinout of connector J11, refer to 4.1.3.1. 4.2.2. Vehicle-side connector J9 For all details, refer to 3.1.1. 4.2.3. User-side connector J3, J4, J6, J10, J12 and J15 For all details, refer to 3.2. 4.2.4. Connector for communication module J20 The connector for the communication module provides the power supply and all peripherals necessary for communication with devices on the module itself. Below are listed the devices present on communication module:
GPS module with dead-reckoning (Ublox NEO6V); it requires 1 channel USB 2.0;
UMTS and CDMA module (Cinterion PXS8); it requires 1 channel USB 2.0;
BT module (Bluegiga BT111); it requires 1 channel USB 2.0;
WiFi b/g/n module (Bluegiga WF111); it requires 1 channel SDIO;
some generic signals for future uses; this for guarantee the use of another communication module that integrates on board different devices from those listed above. Table 40 lists the pinout of the connector J20. Signal VCC VCC N6_USB_EN N6_USB_DP N6_USB_D-
N6_VCC_EN N6_TX N6_RX BT_USB_EN BT_USB_D-
Pin 1 2 3 4 5 6 7 8 9 10 11 Vdd 5.0V 5.0V 5.0V 5.0V 5.0V 3.3V 3.3V 3.3V 5.0V 5.0V Dir. Out Out Out Bi Bi Out In Out Out Bi Description 5V power supply 5V power supply n.c. Power supply enable of USB channel for GPS Data+ signal of USB channel for GPS Data- signal of USB channel for GPS Power supply enable of GPS TX signal for GPS RX signal for GPS Power supply enable of USB channel for BT Data- signal of USB channel for BT Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 34/40 Signal BT_USB_D+
PLDC_EXP9 PLDC_EXP8 PLDC_EXP7 PLDC_EXP6 PLDC_EXP5 VCC3 SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD2_CLK SD2_CMD WF_ON PLDC_EXP1 PLDC_EXP2 PLDC_EXP3 PLDC_EXP4 VCC3_KL GSM_PWR_ON SYNC PXS8_USB_D-
PXS8_USB_D+
WU_GSM PXS8_USB _EN GSM_-ON/OFF GSM_RST VDD_SYS_3V8 VDD_SYS_3V8 VDD_SYS_3V8 VDD_SYS_3V8 GND GND GND GND GND Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Vdd 5.0V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 3.3V 5.0V 3.3V 3.3V 3.8V 3.8V 3.8V 3.8V
-
-
-
-
-
Dir. Bi Bi Bi Bi Bi Bi Out Bi Bi Bi Bi Bi Bi Out Bi Bi Bi Bi Out Out In Bi Bi In Out Out Out Out Out Out Out
-
-
-
-
-
Description Data+ signal of USB channel for BT General purpose IO for future use General purpose IO for future use General purpose IO for future use General purpose IO for future use General purpose IO for future use 3.3V power supply Data0 signal of 2nd SD channel for WiFi Data1 signal of 2nd SD channel for WiFi Data2 signal of 2nd SD channel for WiFi Data3 signal of 2nd SD channel for WiFi Clk signal of 2nd SD channel for WiFi Cmd signal of 2nd SD channel for WiFi Power supply enable of WiFi General purpose IO for future use General purpose IO for future use General purpose IO for future use General purpose IO for future use Stand-by power supply Power supply enable of modem n.c. Sync signal from modem Data- signal of USB channel for modem Data+ signal of USB channel for modem WakeUp signal from modem Power supply enable of USB channel for modem On/Off signal of modem n.c. Reset signal of modem Power supply for modem Power supply for modem Power supply for modem Power supply for modem n.c. Ground reference Ground reference Ground reference Ground reference Ground reference Table 40: RC2carrier connector pinout of communication module All enable signal listed on Table 40 are active high. 4.2.5. Connector for diagnostic module J19 The connector for the diagnostic module provides the power for the LED matrix and display needed to provide diagnostic system. In order to reduce the dimensions of this connector, the philosophy adopted is to realize the diagnosis with a small processor mounted on the module; this processor communicates with the FPGA, through the connector, and manages the matrix LEDs and display; in this way, all diagnostic messages are encoded and communicated via serial line. Doc: ANNEX II M-RP_01-02 Rev.03 Computers Table 41 lists the pinout of the connector J19. USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 35/40 Signal VCC RX_DIAG TX_DIAG VCC3 USER_LAN_ACT SYNC GND Pin 1 2 3 4 5 6 7 Vdd 5.0V 3.3V 3.3V 3.3V 3.3V 3.3V
-
Dir. Out In Out Out Out Out
-
Description 5V power supply RX signal from diagnosis module TX signal to diagnosis module 3.3V power supply activity LED for Ethernet user side modem sync Ground reference Table 41: RC2carrier connector pinout of diagnosis module The matrix of LEDs present on the diagnosis module is used to highlight the behavior of the various elements present in the system, in particular can be highlighted:
CAN and K lines activity;
vehicle-side Ethernet activity;
BT, WiFi and modem activity;
GPS fix;
In the full version, the alphanumeric display allows to add additional details as already indicated by the matrix LEDs. the power supply status of and its possible failures. 4.2.6. Connectors for expansion module J8 and J14 The pins on the vehicle-side connector (J9) currently free are available on connector J14 and some free signals of the FPGA are present on the connector J8. This allows to realize a possible expansion module to add specific functionalities to the system. Table 42 lists the pinout of the connector J14. Signal VPWRPROT EXP_10 EXP_12 EXP_13 EXP_2 EXP_5 EXP_3 EXP_4 EXP_7 EXP_15 Pin 1 3 5 7 9 11 13 15 17 19 Signal GND EXP_9 EXP_11 EXP_14 EXP_1 EXP_6 EXP_18 EXP_17 EXP_16 EXP_8 Pin 2 4 6 8 10 12 14 16 18 20 Table 42: RC2carrier connector pinout of expansion module All the signal EXPxy are also present in the right section of the vehicle-side connector, as shown in Table 2. Caution: on pin 1 the protected power supply from external battery is available. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 36/40 4.2.7. Connectors for debug J1 and J5 Connector J1 can be connected to the debug connector on logic core (J7, ref. Table 26); this allow to translate the logic level signal into RS232 levels; the converted signals are available in connector J5. The J1 connector pinout is resumed on Table 43. Dir. Out Out In
-
Description Enable the buffer on Tx-Rx signal in the core logic RX signal of debug console TX signal of debug console Reference ground RX-DEBUG TX-DEBUG Vdd 3.3V 3.3V 3.3V Pin 1 2 3 4 Signal ENABLE GND
-
Table 43: RC2carrier auxiliary input connector for console The J5 connector pinout is resumed on Table 44. Dir. Out In
-
TX-DEBUG-232 RX-DEBUG-232 Pin 1 2 3 Vdd 5V 5V Signal GND
-
Description RS232 TX signal of debug console RS232 RX signal of debug console Reference ground Table 44: RC2carrier auxiliary output connector for console 4.2.8. Connectors for backup battery J17 The internal backup battery must be connected to connector J17; in this way, the circuit for power management is supplied with a buffered and always available voltage; moreover, the charge circuit is also connected to this connector, in order to guarantee the optimal charge-state of the backup battery. The J17 connector pinout is resumed on Table 45. Dir.
-
Bi In Description Reference ground Backup battery positive pole Temperature sensing signal Signal GND VBATT NTC Pin 1 2 3 LICELL LICELL Vdd
-
Table 45: RC2carrier auxiliary output connector for console Note: the backup battery voltage is also connected to the logic core on pin 5 (P3V3_LICELL) of connector J2;
in this way, the keep-alive circuit on the processor is supplied with and always available voltage. 4.3. Communication module This chapter defines the characteristics of a device, hereinafter referred as "communication module", intended to provide the connectivity for the core logic to the external world. All signals between the core and communication module pass through the carrier board. Below are listed the devices present on communication module:
GPS module with dead-reckoning (Ublox NEO6V); it requires 1 channel USB 2.0 UMTS and CDMA module (Cinterion PXS8); it requires 1 channel USB 2.0 BT module (Bluegiga BT111); it requires 1 channel USB 2.0 WiFi b/g/n module (Bluegiga WF111); it requires 1 channel SDIO 4.3.1. Printed circuit board Figure 6 shows the location of the elements on the circuit board of the communication module. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 37/40
-BT-
-WiFi-
-Modem-
-GPS-
-SIM-
-holder-
-J2-
The PCB is rectangular (shaped) and measures 61x87mm. The left image is the upper side of the core logic, the right is the bottom side. Figure 6: RC2comm component placement 4.3.2. Connector for carrier board connection J2 This connector matched the J20 connector on carrier board (rif. Table 42). Table 46 lists the pinout of the connector J2. Signal VCC VCC N6_USB_EN N6_USB_DP N6_USB_D-
N6_VCC_EN N6_TX N6_RX BT_USB_EN BT_USB_D-
BT_USB_D+
VCC3 SD2_DAT0 SD2_DAT1 SD2_DAT2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Vdd 5.0V 5.0V 5.0V 5.0V 5.0V 3.3V 3.3V 3.3V 5.0V 5.0V 5.0V 3.3V 3.3V 3.3V 3.3V Dir. Out Out Out Bi Bi Out In Out Out Bi Bi Out Bi Bi Bi Description 5V power supply 5V power supply n.c. Power supply enable of USB channel for GPS Data+ signal of USB channel for GPS Data- signal of USB channel for GPS Power supply enable of GPS TX signal for GPS RX signal for GPS Power supply enable of USB channel for BT Data- signal of USB channel for BT Data+ signal of USB channel for BT n.c. n.c. n.c. n.c. n.c. 3.3V power supply Data0 signal of 2nd SD channel for WiFi Data1 signal of 2nd SD channel for WiFi Data2 signal of 2nd SD channel for WiFi Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 38/40 Signal SD2_DAT3 SD2_CLK SD2_CMD WF_ON VCC3_KL GSM_PWR_ON SYNC PXS8_USB_D-
PXS8_USB_D+
WU_GSM PXS8_USB _EN GSM_-ON/OFF GSM_RST VDD_SYS_3V8 VDD_SYS_3V8 VDD_SYS_3V8 VDD_SYS_3V8 GND GND GND GND GND Pin 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Vdd 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 3.3V 5.0V 3.3V 3.3V 3.8V 3.8V 3.8V 3.8V
-
-
-
-
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Dir. Bi Bi Bi Out Out Out In Bi Bi In Out Out Out Out Out Out Out
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-
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Description Data3 signal of 2nd SD channel for WiFi Clk signal of 2nd SD channel for WiFi Cmd signal of 2nd SD channel for WiFi Power supply enable of WiFi n.c. n.c. n.c. n.c. Stand-by power supply Power supply enable of modem n.c. Sync signal from modem Data- signal of USB channel for modem Data+ signal of USB channel for modem WakeUp signal from modem Power supply enable of USB channel for modem On/Off signal of modem n.c. Reset signal of modem Power supply for modem Power supply for modem Power supply for modem Power supply for modem n.c. Ground reference Ground reference Ground reference Ground reference Ground reference Table 46: RC2comm connector pinout of communication module Doc: ANNEX II M-RP_01-02 Rev.03 USER MANUAL PRODUCT NAME:
TELEMACO/RC 2015/ERMETE 15/10/2015 Rev.0.5 Pag. 39/40 Computers 5. Mechanical 5.1. Top view Hole fixing quotes. Doc: ANNEX II M-RP_01-02 Rev.03 Computers USER MANUAL PRODUCT NAME:
15/10/2015 Rev.0.5 Pag. 40/40 TELEMACO/RC 2015/ERMETE Installation 6. 6.1. General warnings This manual is an integral and essential to the product. Carefully read the instructions contained herein as they provide important information regarding the safe use and maintenance. This equipment is to be used only for the purposes it was designed to. Any other use is considered improper and therefore dangerous. The manufacturer can not be held responsible for any damage caused by improper, incorrect or unreasonable. DMD is only responsible for the device in its original setting. Any changes to the structure or operating cycle of the device must be performed or authorized by the technical department of the DMD. DMD is not responsible for the consequences resulting from the use of non original aftermarket parts. DMD reserves the right to make any technical changes to this manual and the device without prior notice. If you discover any typographical or other, the corrections will be included in new versions of the manual. DMD is only responsible of the information contained in the original version of the Italian manual. reserved - Reproduction prohibited. DMD enforces its rights on the drawings and catalogs according to the law. The box is composed of a plastic box with aluminum inserts designed to facilitate better heat dissipation and to be easily anchored in the designated location. For installations above 60 C ambient temperature consider to protect device metallic parts from accidental contact. 6.2. Antenna mounting Pay close attention to the minimum distance between the antennas and the driver: must be more than 50 cm 6.3. Connections The unit is supplied with a battery connected internally to the system. Consequently, even if the wiring is disconnected (or however with VBATT and BGND not connected), a small portion of the system may be
"turned on"; the internal PC, all devices are "off". Where possible, keep the connecting cables away from sources and radio antennas. Doc: ANNEX II M-RP_01-02 Rev.03
1 2 3 | User Manual and Installations | Users Manual | 525.41 KiB |
WF111 802.11 B/G/N MODULE DATA SHEET Wednesday, 11 July 2012 Version 1.1.4 Copyright 2000-2012 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegigas products are not authorized for use as critical components in life support devices or systems. The WRAP, Bluegiga Access Server, Access Point and iWRAP are registered trademarks of Bluegiga Technologies. The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies. All other trademarks listed herein are owned by their respective owners. Bluegiga Technologies Oy VERSION HISTORY Version Comment 1.0 1.1 1.1.1 1.1.2 1.1.3 1.1.4 First public version Product codes updated Added sleep clock specifications Added frequency variation table FCC and IC information added WT111-N layout guide Bluegiga Technologies Oy 5.1 4.2 4.1 TABLE OF CONTENTS 1 Product description ....................................................................................................................................... 6 2 Ordering Information..................................................................................................................................... 7 3 Pinout and terminal descriptions .................................................................................................................. 8 4 Interfaces .................................................................................................................................................... 12 Host interfaces ................................................................................................................................... 12 4.1.1 Host selection ................................................................................................................................ 12 4.1.2 SDIO interface ............................................................................................................................... 12 4.1.3 CSR Serial Peripheral Interface (CSPI) ......................................................................................... 13 4.1.4 SDIO/CSPI deep-sleep control schemes ...................................................................................... 15 4.1.5 CCCR and CIS register defaults .................................................................................................... 16 Other interfaces ................................................................................................................................. 20 4.2.1 Debug SPI interface ....................................................................................................................... 20 4.2.2 Bluetooth coexistence .................................................................................................................... 20 4.2.3 Configurable I/O pads .................................................................................................................... 21 5 Clock generation ......................................................................................................................................... 22 32.768 kHz external reference clock ................................................................................................. 22 6 Power Control and Regulation ................................................................................................................... 23 Power Control and Regulation ........................................................................................................... 23 REGEN .............................................................................................................................................. 24 RESET ............................................................................................................................................... 24 7 Example Application Schematic ................................................................................................................. 26 8 Wi-Fi radio .................................................................................................................................................. 28 8.1 Wi-Fi receiver ..................................................................................................................................... 28 8.2 Wi-Fi transmitter ................................................................................................................................ 28 Antenna switch for Bluetooth coexistence ......................................................................................... 28 8.3 9 Electrical characteristics ............................................................................................................................. 29 Absolute maximum ratings ................................................................................................................ 29 Recommended Operating Conditions ............................................................................................... 29 Input/Output terminal characteristics ................................................................................................. 30 RF Characteristics ................................................................................................................................. 31 Power Consumption .............................................................................................................................. 33 Physical Dimensions .............................................................................................................................. 35 Layout Guidelines .................................................................................................................................. 36 13.1 WF111-A ............................................................................................................................................ 36 13.2 WF111-E ............................................................................................................................................ 36 13.3 WF111-N ............................................................................................................................................ 36 13.4 Thermal considerations ..................................................................................................................... 38 10 11 12 13 6.1 6.2 6.3 9.1 9.2 9.3 Bluegiga Technologies Oy 14 15 13.5 EMC considerations ........................................................................................................................... 38 Soldering Recommendations................................................................................................................. 40 Certifications .......................................................................................................................................... 41 15.1 Wi-Fi ................................................................................................................................................... 41 15.2 CE ...................................................................................................................................................... 41 15.3 FCC and IC ........................................................................................................................................ 41 FCC et IC ................................................................................................................................... 43 15.4 Qualified Antenna Types for WF111-E .............................................................................................. 46 Contact Information ........................................................................................................................................... 47 15.3.1 Bluegiga Technologies Oy 1 Product description DESCRIPTION WF111 is a fully integrated single 2.4GHz band 802.11 b/g/n module, intended for portable and battery powered applications, where Wi-Fi connectivity is needed. WF111 integrates an IEEE 802.11 b/g/n radio, antenna or U.FL antenna connector and SDIO or CSPI host interfaces. WF111 provides a low cost and simple Wi-Fi solution for devices that run an operating system and a TCP/IP stack on-board, but still offers the benefits of a module small form factor, easy integration and certifications. Bluegiga also provides WF111 drivers for the Linux operating system. for Wi-Fi WF111 has hardware support for various co-
encryption protocols and existence schemes which enables exceptional performance during simultaneous use of IEEE 802.11 and Bluetooth with a single antenna. TARGET APPLICATIONS:
radios and audio PoS terminals RFID and laser scanners Wi-Fi internet streaming products Wireless cameras Portable navigation devices Portable handheld devices Wi-Fi medical sensors Wireless picture frames KEY FEATURES:
IEEE 802.11 b/g/n radio o Single 2.4 GHz band o Symbol rate up to 72.2Mbps Integrated antenna or U.FL connector Hardware support for WEP, WPA and WPA2 encryption Hardware support for Wi-Fi Direct and soft-AP Advanced support Bluetooth coexistence Temperature range: -40oC - +85oC SDIO or CSPI host interfaces Fully CE, FCC, IC and South-Korea qualified (in progress) Operating system drivers for Linux PHYSICAL OUTLOOK:
Figure 1: WF111-A Bluegiga Technologies Oy 2 Ordering Information WF111 Product Numbering WF1 1 1- X Antenna:
A = Internal antenna E = External N = RF pin Confirmed products and codes Product code Description WF111-A WF111-E WF111-N DKWF111 WF111 module with internal chip antenna WF111 module with U.FL connector for external antenna WF111 module with 50 RF pin (contact sales@bluegiga.com for availability) WF111-A SDIO evaluation kit Bluegiga Technologies Oy Page 7 of 47 3 Pinout and terminal descriptions 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2
5 O P I T S R S C _ P S I
1 O P I D N G A P _ D D V
0 T A D _ O D S I
1 T A D _ O D S I
2 T A D _ O D S I
3 T A D _ O D S I K L C _ O D S I D M C _ O D S I A N A _ D D V D N G T B I O S M _ P S I N E G E R K L C _ P S I
0 O P I I S O M _ P S I D N G PIO[3]
VDD_PADS PIO[4]
VDD_REGIN PIO[2]
VDD_SDIO D N G 20 19 18 17 16 15 30 31 32 GND ANT GND 33 GND_PAD D N G 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 Figure 2: WF111 pinout Bluegiga Technologies Oy Page 8 of 47 POWER SUPPLIES VDD_REGIN REGEN GND GND_PAD VDD_ANA VDD_PADS VDD_SDIO VDD_PA PIN NUMBER DESCRIPTION 17 23 Input for the internal regulators Pull high to enable internal voltage regulators (2.0V max) 1, 8, 14, 21, 29, 30, 32 Ground 33 10 19 15 28 Thermal pad, on bottom of WF111 Positive supply for PA control Positive supply for the digital interfaces Positive supply for the SDIO interface Positive supply for the power amplifier Table 1: Supply Terminal Descriptions PIO PORT PIO[0]
PIO[1]
PIO[2]
PIO[3]
PIO[4]
PIO[5]
PIN NUMBER PAD TYPE DESCRIPTION 22 24 16 20 18 27 Bi-directional, programmable strength internal pull-down/pull-up Programmable input/output line. Can be used for Bluetooth co-
existence. Table 2: GPIO Terminal Descriptions Bluegiga Technologies Oy Page 9 of 47 SDIO/CSPI Interfaces PIN NUMBER PAD TYPE DESCRIPTION SDIO_DATA[0]
SDIO_SPI_DI 2 CSPI_MISO SDIO_DATA[1]
SDIO_SPI_INT CSPI_INT SDIO_DATA[2]
SDIO_DATA[3]
3 4 SDIO_SPI_CS#
5 CSPI_CS#
SDIO_CLK SDIO_SPI_SCLK 6 CSPI_CLK SDIO_CMD SDIO_SPI_MOSI 7 CSPI_MOSI Bi-directional, tri-
state, weak internal pull-up Bi-directional, weak/strong internal pull-up Input, weak internal pull-up Bi-directional, weak internal pull-up Synchronous data input/output SDIO SPI data output CSPI data output Synchronous data input/output SDIO SPI interrupt output CSPI data input Synchronous data input/output Synchronous data input/output SDIO SPI chip select, active low CSPI chip select, active low SDIO clock SDIO SPI clock CSPI clock SDIO data input SDIO SPI data input CSPI data input Table 3: Host Interface Terminal Descriptions Bluegiga Technologies Oy Page 10 of 47 PAD TYPE DESCRIPTION Input, weak internal pull-
up, active low System reset RF, DC blocked Antenna output on N variant, on A and E variants not connected RF, DC blocked Bluetooth antenna sharing RF input Table 4: Other Terminal Descriptions OTHER SIGNALS PIN NUMBER 25 31 9 RST ANT BT DEBUG SPI INTERFACE PIN NUMBER SPI_MISO SPI_CLK SPI_MOSI SPI_CS 11 12 13 26 PAD TYPE DESCRIPTION Output, tri-state, weak internal pull-down Input, weak internal pull-down Synchronous data output Synchronous clock input Synchronous data input Debug SPI Chip select, active low Table 5: Debug SPI Terminal Descriptions Bluegiga Technologies Oy Page 11 of 47 Interfaces 4 4.1 Host interfaces WF111 can be interfaced by the host using SDIO in 1bit or 4bit mode, SDIO SPI or CSR proprietary CSPI connection. The host connection buses can be clocked up to 50MHz. 4.1.1 Host selection WF111 will default to 1-bit SDIO mode. The host interface can be set with 1-bit SDIO or SDIO SPI commands to the required mode. After mode selection, it will then remain in that mode until the module is reset either with the RESET pin or the internal power supply supervisor. 4.1.2 SDIO interface This is a host interface which allows a Secure Digital Input Output (SDIO) host to gain access to the internals of the chip. All defined slave modes (SPI, SD 1bit, SD 4bit) are provided. Two functions are supported:
Function 0 is mandatory function used for SDIO slave configuration. This contains CCCR, FBR and CIS. CCCR registers support sleep and wakeup signaling. Function 1 provides access to the IEEE 802.11 functionality. Command IO_RW_DIRECT (CMD52) is used to directly access internal registers. IO_RW_EXTENDED (CMD53) is used for block transfer to/from module MMU buffers. Command GO_IDLE_STATE (CMD0) SEND_RELATIVE_ADDR (CMD3) IO_SEND_OP_COND (CMD5) SELECT/DESELECT_CARD (CMD7) GO_INACTIVE_STATE (CMD15) IO_RW_DIRECT (CMD52) IO_RW_EXTENDED (CMD53) CRC_ON_OFF (CMD59) SD Mode (1/4 bit) SDIO SPI Mode Y Y Y Y Y Y Y N Y N Y N N Y Y Y For more information and detailed descriptions of above functions and commands, see the following specifications:
Table 6: Supported commands per mode SD Specifications Part 1 Physical Layer Specification v.1.10 SD Specification Part E1 SDIO Specification v.1.10 Bluegiga Technologies Oy Page 12 of 47 4.1.3 CSR Serial Peripheral Interface (CSPI) The CSPI is a host interface which shares pins with the SDIO. It contains a number of modifications on the SDIO SPI specification aimed at increasing the host bus efficiency in hosts supporting SPI but not SDIO. The main advantages compared to SDIO SPI are:
Burst transfer is continuous instead of blocks with CRC Timings are deterministic (fixed number of clocks) reducing the required interaction 16 bit registers are transferred as a single command instead of two 8 bit writes MMU buffers are accessed using burst read/writes. The command and address fields are used to select the correct buffer. The CSPI is able to generate an interrupt to the host when a memory access fails. This interrupt line is shared with the SDIO functions. The CSPI Interface is an extension of the basic SPI Interface, with the access type determined by the following fields:
8-bit command 24-bit address 16-bit burst length (optional). Only applicable for burst transfers into or out of the MMU 4.1.3.1 CSPI read/write cycles Register read/write cycles are used to access Function 0, Bluetooth acceleration and MCU registers. Burst read/write cycles are used to access the MMU. 4.1.3.2 CSPI register write cycle The command and address are locked into the slave, followed by 16bits of write data. An Error Byte is returned on the MISO signal indicating whether or not the transfer has been successful. Figure 3: CSPI Register Write Cycle 4.1.3.3 CSPI register read cycle The command and address field are clocked into the slave, the slave then returns the following:
Bytes of padding data (MISO held low) Error byte 16-bits of read data Figure 4: CSPI Register Read Cycle Bluegiga Technologies Oy Page 13 of 47 4.1.3.4 CSPI register burst write cycle Burst transfers are used to access the MMU buffers. They cannot be used to access registers. Burst read/write cycles are selected by setting the nRegister/Burst bit in the command field to 1. Burst transfers are byte orientated, have a minimum length of 0 bytes and a maximum length of 64kbytes. Setting the length field to 0 results in no data being transferred to or from the MMU. As with a register access, the command and address fields are transferred first. There is an optional length field transferred after the address. The use of the length field is controlled by the LengthFieldPresent bit in the Function 0 registers, which is cleared on reset. Figure 5: CSPI Burst Write Cycle 4.1.3.5 CSPI register read cycle Burst reads have a programmable amount of padding data that is returned by the slave. 0-15 bytes are returned as defined in the BurstPadding register. Following this the Error byte is returned followed by the data. Once the transfer has started, no further padding is needed. A FIFO within SDIO_TOP will pre-fetch the data. The address is not retransmitted, and is auto-updated within the slave. The length field is transmitted if LengthFieldPresent in the Function 0 registers is set. In the absence of a length field the CSB signal is used to indicate the end of the burst. Figure 6: CSPI Burst Read Cycle Bluegiga Technologies Oy Page 14 of 47 4.1.4 SDIO/CSPI deep-sleep control schemes The module automatically enters deep sleep to minimize power consumption after a while of idling. Deep sleep is the lowest power mode, where the processor, the internal reference (fast) clock, and much of the digital and analogue hardware are shut down. The SDIO communication system however remains on, and is clocked by the host system. During deep sleep only the function 0 is available, while attempts to access Function 1 will likely result in bus timeouts. Control of when the module is allowed to enter deep sleep is done via Vendor Unique Register in CCCR in function 0. Wake-up is also initiated through this register. The module will initiate an SDIO interrupt when the wake-up is complete. Bluegiga Technologies Oy Page 15 of 47 4.1.5 CCCR and CIS register defaults Address 0x00 0x01 0x07 0x08 Bits 3-0 7-4 3-0 6 0 1 2 3 4 6 7 Fieldname Value CCRx: CCCR format version number 0x2(a); CCCR/FBR version 1.20 SDIOx: SDIO spec. version 0x3(a); SDIO 2.00 SDx: SD format version number 0x1; SD Physical Specification 1.10 SCSI: Support continuous SPI interrupt 0x1 supported SDC: Card supports direct commands 0x1; IO_RW_DIRECT can be executed during data transfer while transfer in progress SMB: Card supports multiblock 0x1; IO_RW_EXTENDED can be executed in block mode SRW: Card supports read wait 0x1; Wait signal is supported on SDIO_DAT[2]
SBS: Card supports suspend/resume 0x0; Operations can't be suspended S4MI: Supports interrupt between data 0x0; Block interrupts not supported in blocks in 4-bit SD 4-bit multi-block transfer LSC: Card is a low-speed card 4BLS: 4-bit support for low-speed cards 0x0; Full-speed card 0x0; Full-speed card 0x09-0x0B 23-0 Pointer to card's common CIS 0x001000; Pointer to the start of Card 0x12 0x13 0 0 SMPC: Support master power control SHS: Support high-speed Information Structure 0x1; Total card current may exceed 200mA (EMPC, SPS and EPS are available) 0x1(a); High speed mode supported
(enabled by the host via the EHS bit) Table 7: SDIO CCCR values, (a) can be modified by software Bluegiga Technologies Oy Page 16 of 47 Address 0x100 Bits 3-0 Fieldname Value Standard SDIO Function interface code 0x0; No SDIO standard interface supported by this function (no defined interface for IEEE 802.11 0x101 6 7-0 Supports CSA 0x0; No Code Storage Area Extended Standard SDIO Function 0x00; No SDIO standard interface 0x102 0 interface SPS supported by this function 0x1; This function has two power modes which are selected by EPS 0x109-0x10B 23-0 Pointer to standard Function 1 CIS 0x002000; Pointer to the start of the CIS for this function Table 8: SDIO FBR values for Function 1 Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Fieldname TPL_CODE TPL_LINK TPLFID_FUNCTION TPFLID_SYSINIT TPL_CODE TPL_LINK TPLFE_TYPE 0x07-0x08 TPLFE_FN0_BLK_SIZE 0x09 0x0A 0x0B 0x0C-0x0D 0x0E-0x0F 0x10 TPLFE_MAX_TRAN_SPEED TPL_CODE TPL_LINK TPLMID_MAND_CODE TPLMID_CARD TPL_CODE Value 0x21; CISTPL_FUNCID: Function identification tuple 0x02; Link to next tuple 0x0C; Card function tuple 0x00; System init bit mask (not used) 0x22; CISTPL_FUNCE: Function extension tuple 0x05; Link to next tuple 0x00; Type of extended data = Function 0 0x0200; Maximum block size and byte count =
512 0x5A(a); Maximum transfer speed per line = 50 Mbps 0x20; CISTPL_MANDIF: Manufacturer identification string tuple 0x04; Link to next tuple 0x032A(a); Card manufacturer code = CSR 0x0007(a); Manufacturer information - UniFi CSR6031 0xFF; End-of-chain tuple Table 9: SDIO CIS values for Function 0, (a) can be modified by software Bluegiga Technologies Oy Page 17 of 47 Fieldname TPL_CODE TPL_LINK TPLFID_FUNCTION TPFLID_SYSINIT TPL_CODE TPL_LINK TPLFE_TYPE Value 0x21; CISTPL_FUNCID: Function identification tuple 0x02; Link to next tuple 0x0C; Card function tuple 0x00; System init bit mask (not used) 0x22; CISTPL_FUNCE: Function extension tuple 0x05; Link to next tuple 0x00; Type of extended data = Function 1-7 TPLFE_FUNCTION_INFO 0x01(a); FNWUS: Wake up support = 1 (card can TPLFE_STD_IO_REV TPL_CARD_PSN TPLFE_CSA_SIZE TPLFE_CSA_PROPERTY TPLFE_MAX_BLOCK_SIZE TPLFE_OCR TPLFE_OP_MIN_PWR TPLFE_OP_AVG_PWR TPLFE_OP_MAX_PWR TPLFE_SB_MIN_PWR TPLFE_SB_AVG_PWR TPLFE_SB_MAX_PWR TPLFE_MIN_BW wake up host with SDIO clock stopped) 0x00; No SDIO standard function supported 0x00000000(a); Product serial number 0x00000000; No code storage area 0x00; No code storage area 0x0200; Maximum block size and byte count = 512 0x00FF8000(a); 2.7-3.6V operation supported 0x14(a); Minimum operating current = 20mA 0x32(a); Average operating current = 50mA 0xC8(a); Maximum operating current = 500mA 0x05(a); Minimum current in standby = 5mA 0x07(a); Average current in standby = 7mA 0x0A(a); Maximum current in standby = 10mA 0x0BB8(a); Minimum data transfer bandwidth =
3000kBps (24Mbps) TPLFE_OPT_BW 0x1B58(a); Optimum data transfer bandwidth =
7000kBps (54Mbps) Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09-0x0C 0x0D-0x10 0x11 0x12-0x13 0x14-0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E-0x1F 0x20-0x21 0x22-0x23 TPLFE_ENABLE_TIMEOUT_VAL 0x001F4; Function's timeout after being enabled =
5s 0x24-0x25 TPLFE_SP_AVG_PWR_3.3V 0x0032(a); Average current when operating =
50mA (copy of TPLFE_OP_AVG_PWR) 0x26-0x27 TPLFE_SP_MAX_PWR_3.3V 0x00C8(a); Maximum current when operating =
200mA (copy of TPLFE_OP_MAX_PWR) 0x28-0x29 TPLFE_HP_AVG_PWR_3.3V 0x00C8(a); Average current when operating in higher current mode = 200mA 0x2A-0x2B TPLFE_HP_MAX_PWR_3.3V 0x015E(a); Maximum current when operating in higher current mode = 350mA 0x2C-0x2D TPLFE_LP_AVG_PWR_3.3V 0x078(a); Average current when operating in lower current mode = 120mA 0x2E-0x2F TPLFE_LP_MAX_PWR_3.3V 0x00C8(a); Maximum current when operating in lower current mode = 200mA Bluegiga Technologies Oy Page 18 of 47 0x30 TPL_CODE 0xFF; CISTPL_END: End-of-chain tuple Table 11: SDIO CIS values for Function 1, (a) can be modified by software; current consumption figures are conservative values for the host power control Bluegiga Technologies Oy Page 19 of 47 4.2 Other interfaces 4.2.1 Debug SPI interface A separate SPI bus is provided at the module pads for device access during testing and uploading settings during application development and manufacturing. This interface cannot be used as a host interface. It is recommended to bring these to a header in case RF tests or changes to the stored internal MIB are required after production. The debug SPI bus has logic levels set by the VDD_PADS reference supply line. 4.2.2 Bluetooth coexistence Bluetooth coexistence systems allow co-located Wi-Fi and Bluetooth devices to be aware of each other and to avoid simultaneous transfers that would degrade link performance. There are many ways of implementing such connections, from host driver negotiated channel and time sharing, to hardware signalling between the two devices. WF111 supports a number of different coexistence schemes with up to 6 control lines for hardware communication between the two devices. Wi-Fi and Bluetooth may also use separate antennas, or share a single antenna through a switch and/or a coupler. With a shared antenna, usually two additional signals are needed to control the front end switch. WF111 contains an internal switch for separating Wi-Fi and Bluetooth transmissions as well as a shared low noise amplifier that allows both Wi-Fi and Bluetooth to receive simultaneously using the same amplifier. For use with CSR-based Bluetooth (BC4 to BC6 with firmware version 21 or later, BC7 and onwards with all versions), Unity-3e+ is recommended as the coexistence scheme. Unity-3e is an enhanced version of the 3-
wire Unity-3 scheme that uses tighter timings and uses the three control lines also for antenna switch control, removing the need for the two separate switch control lines. Unity-3e+, or Unity-3e with Unity+ adds an additional BT_PERIODIC signal to communicate the need for a periodic transmission from the Bluetooth to the Wi-Fi, allowing a guaranteed low-latency throughput for certain Bluetooth applications despite high Wi-Fi usage. This allows reliable audio connections that would otherwise suffer from the Wi-Fis higher priority. Figure 7: Coexistence signals between WF111 and WT21 Bluetooth module (not showing antenna sharing connection) Bluegiga Technologies Oy Page 20 of 47 The required MIB values for the coexistence scheme in Figure 7 are:
unifiCoexScheme ::= 3 unifiCoexPTABTStatusPIO ::= 3 unifiCoexPTABTInbandPIO ::= -1 unifiCoexPTABTActivePIO ::= 5 unifiCoexPTAWLANDenyPIO ::= 4 unifiCoexPeriodicPIO ::= 2 The corresponding PSKEYs for the WT21 are:
PSKEY_LC_COMBO_DISABLE_PIO_MASK (0x0028) = 0x0200 0x0000 0x0000 PSKEY_LC_COMBO_DOT11_CHANNEL_PIO_BASE (0x002A) = 0x0011 PSKEY_LC_COMBO_DOT11_ESCO_RTX_PRIORITY ( 0x0050) = 0x0001 PSKEY_LC_COMBO_DOT11_PULL_DISABLE_MASK (0x005A) = 0x0200 PSKEY_LC_COMBO_DOT11_PERIODIC_PIO_MASK (0x005C) = 0x0010 0x0000 PSKEY_LC_COMBO_DOT11_T1 (0x005E) = 0x0043 PSKEY_LC_COMBO_DOT11_T2 (0x005F) = 0x000A PSKEY_TXRX_PIO_CONTROL (0x0209) = 0x0001 For other coexistence schemes, please contact Bluegiga technical support. 4.2.3 Configurable I/O pads A number of programmable bi-directional input/outputs (I/O) are provided. PIO[0:5] logic levels are referred to the VDD_PADS supply line. PIO lines can be configured through software to implement various automated functions or as generic inputs or outputs. As inputs the lines can be configured to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. In addition to the coexistence functions, any of the PIO lines can be configured as interrupt request lines, wake-up lines from sleep modes, status led drivers with multiple internally generated modes, general I/O pins controlled by the host, or as a 32.768 kHz sleep clock input. For further information, please contact Bluegiga technical support. Note: All unused signals can be left floating. Bluegiga Technologies Oy Page 21 of 47 5 Clock generation WF111 uses an internal 26 MHz crystal as the RF reference clock. All WF111 internal digital clocks except sleep timing are generated using phase locked loops, which are locked to the 26 MHz reference clock. 5.1 32.768 kHz external reference clock The module contains an integrated RC oscillator for sleep timing. If more accurate timing is required, an external 32.768 kHz clock can be applied to a PIO pin configured as a clock input to implement a more accurate sleep clock. The Wi-Fi packet timing is derived from the 26MHz crystal and so is unaffected by tolerances in the sleep clock. The pin chosen as a clock input is an ordinary digital input and the clock waveform should be a logic level square wave. Configuring an input as a clock input requires a setting in the MIB. For further information, please contact Bluegiga technical support. Bluegiga Technologies Oy Page 22 of 47 6 6.1 Power Control and Regulation Power Control and Regulation Figure 8: System block diagram WF111 contains four linear regulators supplying clean voltages for the different parts of the system. All of them produce a 1.2V output voltage, and are fed from a common input, VDD_REGIN. This input can be supplied with a voltage between 1.45-2.0V, typically 1.5V or 1.8V. The VDD_REGIN supply should be relatively clean of ripple and switching spikes in order to avoid degrading the RF performance. WF111 also needs four other supply lines connected in addition to VDD_REGIN:
VDD_PADS provides a reference voltage for matching voltage levels of the host system to the GPIO pins used for Bluetooth coexistence and other functions. This can range from 1.7V to 3.6V. The current drawn from this supply is negligible. VDD_SDIO provides a reference voltage for matching voltage levels of the host system to the SDIO connection. This can range from 1.7V to 3.6V. The current drawn from this supply depends on bus usage, but with no active data transfer will be negligible. VDD_ANA provides a reference voltage for communication between the Wi-Fi chip and the power amplifier. This should be between 1.7V and 3.6V. The current drawn from this supply is negligible. Note for WF111 engineering sample version without RF shield:
o VDD_ANA provides a reference voltage for communication between the Wi-Fi chip and the power amplifier. This should be between 2.7V and 3.6V. The current drawn from this supply is negligible. In the production version, the voltage range for VDD_ANA has been extended for more flexible supplying. VDD_PA is a separate supply voltage for the Wi-Fi power amplifier. This supply will draw considerable currents in pulses and should be bypassed with a relatively large capacitor close to the module, and the power traces should be relatively wide. This voltage can range from 2.7V to 4.8V making use Bluegiga Technologies Oy Page 23 of 47 directly from a single lithium cell possible. A higher supply voltage will not affect the power amplifiers current draw significantly. These voltages are not tied to each other and any combination of supply voltages within the specified limits can be used. In a 3.3V logic level host system all other supplies would usually be tied to the 3.3V supply, with a separate regulator providing the 1.45-2.0V supply for the Wi-Fi core. A switch mode regulator with 1.5V output is recommended for minimum power consumption. Please see the example schematic in this datasheet. In a 1.8V logic level host system, all other supplies can be connected to the 1.8V supply rail except VDD_PA which should be connected to a 2.7-4.8V supply. Note for WF111 engineering sample version without RF shield:
In a 1.8V logic level host system VDD_PA would be connected to a 2.7-4.8V supply, VDD_ANA to a 2.7-3.6V supply and the rest of the supplies to the 1.8V supply rail. The higher voltage supplies should be powered before or at the same time as the core supply line, i.e. the VDD_REGIN should be powered up last. Powering the core first may lead to the GPIO and SDIO blocks booting into an inaccessible state. External high frequency bypassing of the supply lines is not required. Note: All supply voltages and ground lines must be connected. 6.2 REGEN The regulator enable pin REGEN is used to enable the WF111. REGEN enables the regulators of the digital and analog core supply voltages. The pin is active high, with a logic threshold of around 1V, and has a weak pull-down. REGEN can tolerate voltages up to 2.0V, and may be connected directly to the internal voltage regulator input (VDD_REGIN) to permanently enable the device. Part of the regulators can also be disabled by firmware in power saving modes. The VDD_REGIN supply can also be externally switched off while leaving the other supply voltages powered. Cutting power to the core will fully shut down the module internal processors and returning power will cause a power-on reset, requiring a full initialization of the module. The REGEN pin will not disable system blocks not supplied by the core supply, meaning the coexistence interface and the SDIO Function 0 are available even when the core is powered off. 6.3 RESET WF111 may be reset from several sources: RESET pin, power-on reset, via software configured watchdog timers as well as through the SDIO/CSPI host interface. The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset is performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a period greater than 5ms. The power-on reset occurs when the core supply (generated by the internal 1.2V linear regulator) falls below typically 1.05V and is released when core voltage rises above typically 1.10V. At reset regardless of the source the digital I/O pins are set to a high impedance state with weak pull-downs, except RESET and DEBUG_SPI_CS# which have a weak pull-up. The host connection interface is only reset by the RESET pin or a power-on reset. A power-on reset can be achieved through powering down the digital core by either externally cutting the VDD_REGIN supply or giving a low pulse to the REGEN-pad. If REGEN is connected to the host system for powering down the module, or a separate core power switch is implemented, the RESET pin can be tied permanently to a supply voltage line. Bluegiga Technologies Oy Page 24 of 47 Following a reset, WF111 automatically generates internally the clocks needed for safe boot-up of the internal processors. The crystal oscillator is then configured by software with the correct input frequency. Bluegiga Technologies Oy Page 25 of 47 7 Example Application Schematic 100uF T E S E R 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 30 31 32 GND ANT GND 33 GND_PAD D N G
0 T A D _ O D S I
1 T A D _ O D S I
2 T A D _ O D S I
3 T A D _ O D S I D N G A P _ D D V
5 O P I T S R S C _ P S I
1 O P I N E G E R
0 O P I D N G PIO[3]
VDD_PADS PIO[4]
VDD_REGIN PIO[2]
K L C _ O D S I D M C _ O D S I A N A _ D D V D N G T B I O S M _ P S I K L C _ P S I I S O M _ P S I VDD_SDIO D N G 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 3.3V regulator 3 VIN VOUT 2 1.5/1.8V D N G 1
0 T A D
1 T A D
2 T A D
3 T A D K L C D M C V 3 3
. SDIO bus Figure 9: An example application circuit with SDIO host connection, 3.3V level host logic and 1.5/1.8V core supply, REGEN hard wired to the core supply and RST pad used to reset the module (Note: with N-variant ANT-pad and associated grounds would also be connected) Bluegiga Technologies Oy Page 26 of 47 2.7-4.8V 100uF N E G E R 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2
5 O P I T S R S C _ P S I
1 O P I D N G A P _ D D V
0 T A D _ O D S I
1 T A D _ O D S I
2 T A D _ O D S I
3 T A D _ O D S I K L C _ O D S I D M C _ O D S I A N A _ D D V D N G T B I O S M _ P S I N E G E R
0 O P I D N G PIO[3]
VDD_PADS PIO[4]
VDD_REGIN PIO[2]
K L C _ P S I I S O M _ P S I VDD_SDIO D N G 30 31 32 GND ANT GND 33 GND_PAD D N G 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1
0
T A D
1
T A D
2
T A D
3
T A D K L C D M C V 8
. 1
SDIO bus 20 19 18 17 16 15 Figure 10: An example application circuit with SDIO host connection, 1.8V level host logic and a separate power amplifier supply, RST hard wired to the core supply and REGEN pad used to power off and reset the module (Note: with N-variant ANT-pad and associated grounds would also be connected)(Note: engineering samples will require VDD_ANA to be 2.7-3.6V) Bluegiga Technologies Oy Page 27 of 47 8 Wi-Fi radio 8.1 Wi-Fi receiver The receiver features direct conversion architecture. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the receiver to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitized. High-order baseband filters ensure good performance against in-band interference. 8.2 Wi-Fi transmitter The transmitter features a direct IQ modulator. Digital baseband transmit circuitry provides the required spectral shaping and on-chip trims are used to reduce IQ modulator distortion. Transmitter gain can be controlled on a per-packet basis, allowing the optimization of the transmit power as a function of modulation scheme. The internal Power Amplifier (PA) has a maximum output power of +15dBm for IEEE 802.11g/n and +17dBm for IEEE 802.11b. The module internally compensates for PA gain and reference oscillator frequency drifts with varying temperature and supply voltage. 8.3 Antenna switch for Bluetooth coexistence WF111 supports sharing the integrated antenna or antenna connector with a Bluetooth device through the BT_RF pad. The module contains a bypass switch to route the Bluetooth signal directly to the antenna, and supports using the internal LNA for Bluetooth reception. The switch is controlled through the coexistence interface. Bluegiga Technologies Oy Page 28 of 47 9 9.1 Electrical characteristics Absolute maximum ratings Rating Storage temperature VDD_PADS, VDD_ANA, VDD_SDIO VDD_REGIN, REGEN VDD_PA Other terminal voltages Min
-40
-0.4
-0.4
-0.4 Max 85 3.6 2.5 6 VSS+0.3 VDD+0.3 9.2 Recommended Operating Conditions Table 10: Absolute Maximum Ratings Rating Operating temperature range (a) VDD_PADS, VDD_SDIO, VDD_ANA Engineering samples: VDD_ANA*
VDD_PA VDD_REGIN Min
-40 1.7 2.7 2.7 1.45 Max 85 3.6 3.6 4.8 2 Unit C V V V V Unit C V V V V Table 11: Recommended Operating Conditions
(a) The module will heat up depending on use, at high transmit duty cycles the maximum operating temperature may need to be derated. See chapter 13.4
*) This applies to WF111 modules with no RF shield. Bluegiga Technologies Oy Page 29 of 47 9.3 Input/Output terminal characteristics Digital Terminals Input Voltage Levels VIL input logic level low 1.7V VDD 3.6V Min
-0.3 VIH input logic level low 1.7V VDD 3.6V 0.625*Vdd Output Voltage Levels VOL output logic level low 1.7V VDD 3.6V,
(Io = 4.0 mA) VOH output logic level low 1.7V VDD 3.6V,
(Io = -4.0 mA) Input Tri-state Current with:
Typ Max Unit
-40 40
-1 1 0
0.25*Vdd VDD+0.3 0.4 Vdd
-10 150
-0.33 5 1 5 V V V V A A A A A pF
0.75*Vdd
-150 10
-5 0.33
-1 1 Table 12: Digital terminal electrical characteristics Min Typ max 32.748 32.768 32.788
-20
-150 30 0.625Vdd
-0.3 50
+20
+150 70 50 Vdd+0.3 0.25Vdd kHz ppm ppm
ns V V Table 13: External sleep clock specifications Bluegiga Technologies Oy Page 30 of 47 Strong pull-up Strong pull-down Weak pull-up Weak pull-down I/O pad leakage current Pad input capacitance Frequency Deviation @25oC Deviation over temperature Duty cycle Rise time Input high level Input low level 10 RF Characteristics Min Channel 1 Frequency 2412 max 13 2472 Note: channel 14 can be set but proper operation is not guaranteed and its use should be avoided. MHz Standard 802.11b 802.11g Table 14: Supported frequencies Supported bit rates 1, 2, 5.5, 11Mbps 6, 9, 12, 18, 24, 36, 48, 54Mbps 802.11n, HT, 20MHz, 800ns 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps 802.11n, HT, 20MHz, 400ns 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65, 72.2Mbps Table 15: Supported modulations 802.11b Typ 802.11g Typ 802.11n short GI Typ 802.11n long GI Typ 1 Mbps
-97 dBm 6 Mbps
-92 dBm 6.5 Mbps
-91 dBm 7.2 Mbps 2 Mbps
-95 dBm 9 Mbps
-91 dBm 13 Mbps
-87 dBm 14.4 Mbps 5.5 Mbps
-93 dBm 12 Mbps
-89 dBm 19.5 Mbps
-85 dBm 21.7 Mbps 11 Mbps
-89 dBm 18 Mbps
-87 dBm 26 Mbps
-82 dBm 28.9 Mbps 24 Mbps
-84 dBm 39 Mbps
-78 dBm 43.3 Mbps 36 Mbps
-80 dBm 52 Mbps
-74 dBm 57.8 Mbps 48 Mbps
-75 dBm 58.5 Mbps
-71 dBm 65 Mbps 54 Mbps
-73 dBm 65 Mbps
-68 dBm 72.2 Mbps Table 16: Receiver sensitivity
-92 dBm
-90 dBm
-87 dBm
-84 dBm
-80 dBm
-75 dBm
-72 dBm
-69 dBm Bluegiga Technologies Oy Page 31 of 47 Modulation type 802.11b 802.11g 802.11n Min
+16
+14
+14 Typ
+17
+15
+15 Table 17: Transmitter output power at maximum setting Operating mode TX loss RX gain (using internal LNA) Internal LNA noise figure Min
-2.5 8 Typ
-3 10 2.0 Table 18: BT antenna sharing interface properties Max
+17.6
+15.6
+15.6 Max
-3.5 12 2.5 Variation between individual units Variation with temperature Typ
+/-5
+/-3 Max
+/-10
+/-10 802.11 limit (total error)
+/-25
+/-25 Table 19: Carrier frequency accuracy dBm dBm dBm dB dB dB ppm ppm Bluegiga Technologies Oy Page 32 of 47 90 mA 104 mA 114 mA 75 A 11 Power Consumption Operating mode VDD_PA/peak VDD_PA/typ VDD_REGIN/peak VDD_REGIN/typ 248 mA 190 mA 240 mA 100 mA Transmit (802.11b, 1M,
+17dBm) Transmit (802.11b, 1M,
+8dBm) Transmit (802.11g, 54M,
+15dBm) 144 mA 154 mA Receive, no data 12 mA 10.5 mA 240 mA Deep sleep 16 A Table 20: Current consumption during specific operating modes Operating mode Transmit/802.11n Transmit/802.11g Transmit/802.11b Transmit/802.11b Bit rate 65 Mbps 18 Mbps 11 Mbps 1 Mbps Transmit/802.11n 72.2 Mbps Transmit/802.11g Transmit/802.11g Transmit/802.11b Transmit/802.11b Receive Receive Idle, associated Idle, non-associated 54 Mbps 18 Mbps 11 Mbps 2 Mbps 72 Mbps 72 Mbps Throughput (limited) Current/3.3V 12 Mbps 5.9 Mbps 4.8 Mbps 920 kbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps 16.5 Mbps 1 Mbps 144 mA 192 mA 192 mA 184 mA 74 mA*
78 mA 86 mA 94 mA 158 mA 88 mA 70 mA*
3.2 mA**
0.6mA Table 21: Average current consumption in normal use with various constant throughputs measured from evaluation board test point (Preliminary)
*) Note 1: The module draws about 70mA in idle mode without power saves enabled. With default power save timing settings transferring short packets with short intervals will not allow the Wi-Fi core to go to a power save mode, and the average consumption will approximate 70mA when the relative duration of actual transfers is Bluegiga Technologies Oy Page 33 of 47 minimal. However, when longer packets are transferred with longer intervals, the Wi-Fi core will be able to sleep during the interval, reducing power consumption considerably.
**) Note 2: Idle current when associated varies considerably, with 1mA to 8mA measured with different access points in a noisy office environment. Bluegiga Technologies Oy Page 34 of 47 12 Physical Dimensions Figure 11: Physical dimensions Figure 12: WF111 recommended PCB land pattern Bluegiga Technologies Oy Page 35 of 47 13 Layout Guidelines 13.1 WF111-A Figure 13: Recommended layouts, on board corner and on board edge See figure 13: recommended layout for the suggested module layout. The impedance matching of the antenna is designed for a layout similar to the module evaluation board. For an optimal performance of the antenna the layout should strictly follow the layout example shown in figure 8 and the thickness of FR4 should be between 1 and 2 mm, preferably 1.6mm. Any dielectric material close to the antenna will change the resonant frequency and it is recommended not to place a plastic case or any other dielectric closer than 5 mm from the antenna. ANY metal in close proximity of the antenna will prevent the antenna from radiating freely. It is recommended not to place any metal or other conductive objects closer than 20 mm to the antenna except in the directions of the ground planes of the module itself. For optimal performance, place the antenna end of the module outside any metal surfaces and objects in the application, preferably on the device corner. The larger the angle in which no metallic object obstructs the antenna radiation, the better the antenna will work. DO NOT place WF111-A in the middle of the application board. Even with a board cutout around the antenna the range will be bad. The three pads on the antenna end of the WF111-A can be connected to the ground or left unsoldered. 13.2 WF111-E RF output can be taken directly from the U.FL connector of the module, and no antenna clearances need to be made for the module. The three pads on the antenna end of the module can be connected to the ground or left unsoldered. 13.3 WF111-N Antenna connection is routed to pad 31. Pads 30 and 32 beside the antenna connection should be properly connected to the ground plane. No antenna clearances are needed for the module itself. The antenna trace should be properly impedance controlled and kept short. Figure 14 shows a typical 50 ohm trace from the RF pin to a SMA connector. Bluegiga Technologies Oy Page 36 of 47 Figure 14: Typical 50 trace for WF111-N A transmission line impedance calculator, such as TX-Line made by AWR, can be used to approximate the dimensions for the 50 ohm transmission line. Figure 15 shows an example for two different 50 ohm transmission lines. CPW Ground W = 0.15 mm G = 0.25 mm RF GROUND h = 0.076 mm GND stitching vias MICROSTRIP W = 1.8 mm h = 1 mm RF GROUND Prepreg, r = 3.7 RF GROUND FR4, r = 4.6 FR4, r = 4.6 RF GROUND Figure 15: Example cross section of two different 50 ohm transmission line Bluegiga Technologies Oy Page 37 of 47 13.4 Thermal considerations The WF111 module may at continuous full power transmit consume up to 1 W of DC power, most of which is drawn by the power amplifier. Most of this will be dissipated as heat. In any application where high ambient temperatures and constant transmissions for more than a few seconds can occur, it is important that a sufficient cooling surface is provided to dissipate the heat. The thermal pad in the bottom of the module must be connected to the application board ground planes by soldering. The application board should provide a number of vias under and around the pad to conduct the produced heat to the board ground planes, and preferably to a copper surface on the other side of the board in order to dissipate the heat into air. The module internal thermal resistance should in most cases be negligible compared to the thermal resistance from the module into air, and common equations for surface area required for cooling can be used to estimate the temperature rise of the module. Only copper planes on the circuit board surfaces with a solid thermal connection to the module ground pad will dissipate heat. For an application with high transmit duty cycles
(low bit rate, high throughput, long bursts or constant streaming) the maximum allowed ambient temperature should be reduced due to inherent heating of the module, especially with small fully plastic enclosed applications where heat transfer to ambient air is low due to low thermal conductivity of plastic. The module measured on the evaluation board exhibits a temperature rise of about 25oC above ambient temperature when continuously transmitting IEEE 802.11b at full power with minimal off-times and no collision detection (a worst case scenario regarding power dissipation). An insufficiently cooled module will rapidly heat beyond operating range in ambient room temperature. 13.5 EMC considerations Following recommendations helps to avoid EMC problems arising in the design. Note that each design is unique and the following list do not consider all basic design rules such as avoiding capacitive coupling between signal lines. Following list is aimed to avoid EMC problems caused by RF part of the module. Do not remove copper from the PCB more than needed. For proper operation the antenna requires a solid ground plane with as much surface area as possible. Use ground filling as much as possible. Connect all grounds together with multiple vias. Do not leave small floating unconnected copper areas or areas connected by just one via, these will act as additional antennas and raise the risk of unwanted radiations. Do not place a ground plane underneath the antenna. The grounding areas under the module should be designed as shown in Figure 13: Recommended layout. When using overlapping ground areas use conductive vias separated max. 3 mm apart at the edge of the ground areas. This prevents RF from penetrating inside the PCB. Use ground vias extensively all over the PCB. All the traces in (and on) the PCB are potential antennas. Especially board edges should have grounds connected together at short intervals (stitching) to avoid resonances. Avoid current loops. Keep the traces with sensitive, high current or fast signals short, and mind the return current path, having a short signal path is not much use if the associated ground path between the ends of the signal trace is long. Remember, ground is also a signal trace. The ground will conduct the same current as the signal path and at the same frequency, power and sensitivity. Split a ground plane ONLY if you know exactly what you are doing. Splitting the plane may cause more harm than good if applied incorrectly. The ground plane acts as a part of the antenna system. Insufficient ground planes or large separate sensitive signal ground planes will easily cause the coupled transmitted pulses to be AM-demodulated by semiconductor junctions around the board, degrading system performance. Bluegiga Technologies Oy Page 38 of 47 Overlapping GND layers without GND stitching vias Overlapping GND layers with GND stitching vias shielding the RF energy Figure 16: Use of stitching vias to avoid emissions from the edges of the PCB Bluegiga Technologies Oy Page 39 of 47 14 Soldering Recommendations WF111 is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations. Bluegiga Technologies will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering. Since the profile used is process and layout dependent, the optimum profile should be studied case by case. Thus following recommendation should be taken as a starting point guide.
- Refer to technical documentations of particular solder paste for reflow profile configurations
- Avoid using more than one flow.
- Reliability of the solder joint and self-alignment of the component are dependent on the solder volume. Minimum of 150m stencil thickness is recommended.
- Aperture size of the stencil should be 1:1 with the pad size.
- A low residue, no clean solder paste should be used due to low mounted height of the component.
If the vias used on the application board have a diameter larger than 0.3mm, it is recommended to mask the via holes at the module side to prevent solder wicking through the via holes. Solders have a habit of filling holes and leaving voids in the thermal pad solder junction, as well as forming solder balls on the other side of the application board which can in some cases be problematic. Bluegiga Technologies Oy Page 40 of 47 15 Certifications WF111 is compliant to the following specifications:
15.1 Wi-Fi TBD 15.2 CE TBD 15.3 FCC and IC This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and
(2) this device must accept any interference received, including interference that may cause undesired operation. FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This transmitter is considered as mobile device and should not be used closer than 20 cm from a human body. To allow portable use in a known host class 2 permissive change is required. Please contact support@bluegiga.com for detailed information. IC Statements:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. If detachable antennas are used:
This radio transmitter (identify the device by certification number, or model number if Category II) has been approved by Industry Canada to operate with the antenna types listed below with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. See table 22 for the approved antennas for WF111-E and WF111-N. Bluegiga Technologies Oy Page 41 of 47 OEM Responsibilities to comply with FCC and Industry Canada Regulations The WF111 Module has been certified for integration into products only by OEM integrators under the following conditions:
The antenna(s) must be installed such that a minimum separation distance of 20cm is maintained between the radiator (antenna) and all persons at all times. The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter. As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions cannot be met (for certain configurations or co-location with another transmitter), then the FCC and Industry Canada authorizations are no longer considered valid and the FCC ID and IC Certification Number cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC and Industry Canada authorization. End Product Labeling The WF111 Module is labeled with its own FCC ID and IC Certification Number. If the FCC ID and IC Certification Number are not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case, the final end product must be labeled in a visible area with the following:
Contains Transmitter Module FCC ID: QOQWF111 Contains Transmitter Module IC: 5123A-BGTWF111 or Contains FCC ID: QOQWF111 Contains IC: 5123A-BGTWF111 The OEM of the WF111 Module must only use the approved antenna(s) described in table 22, which have been certified with this module. The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change RF related parameters in the user manual of the end product. To comply with FCC and Industry Canada RF radiation exposure limits for general population, the antenna(s) used for this transmitter must be installed such that a minimum separation distance of 20cm is maintained between the radiator (antenna) and all persons at all times and must not be co-
located or operating in conjunction with any other antenna or transmitter. Bluegiga Technologies Oy Page 42 of 47 15.3.1 FCC et IC Cet appareil est conforme lalina 15 des rgles de la FCC. Deux conditions sont respecter lors de son utilisation :
(1) cet appareil ne doit pas crer dinterfrence susceptible de causer un quelconque dommage et,
(2) cet appareil doit accepter toute interfrence, quelle quelle soit, y compris les interfrences susceptibles dentraner un fonctionnement non requis. Dclaration de conformit FCC dexposition aux radiofrquences (RF):
Ce matriel respecte les limites dexposition aux radiofrquences fixes par la FCC dans un environnement non contrl. Les utilisateurs finaux doivent se conformer aux instructions dutilisation spcifies afin de satisfaire aux normes dexposition en matire de radiofrquence. Ce transmetteur ne doit pas tre install ni utilis en concomitance avec une autre antenne ou un autre transmetteur. Ce transmetteur est assimil un appareil mobile et ne doit pas tre utilis moins de 20 cm du corps humain. Afin de permettre un usage mobile dans le cadre dun matriel de catgorie 2, il est ncessaire de procder quelques adaptations. Pour des informations dtailles, veuillez contacter le support technique Bluegiga : support@bluegiga.com. Dclaration de conformit IC :
Ce matriel respecte les standards RSS exempt de licence dIndustrie Canada. Son utilisation est soumise aux deux conditions suivantes :
(1) lappareil ne doit causer aucune interfrence, et
(2) lappareil doit accepter toute interfrence, quelle quelle soit, y compris les interfrences susceptibles dentraner un fonctionnement non requis de lappareil. Selon la rglementation dIndustrie Canada, ce radio-transmetteur ne peut utiliser quun seul type dantenne et ne doit pas dpasser la limite de gain autorise par Industrie Canada pour les transmetteurs. Afin de rduire les interfrences potentielles avec dautres utilisateurs, le type dantenne et son gain devront tre dfinis de telle faon que la puissance isotrope rayonnante quivalente (EIRP) soit juste suffisante pour permettre une bonne communication. Lors de lutilisation dantennes amovibles :
Ce radio-transmetteur (identifi par un numro certifi ou un numro de modle dans le cas de la catgorie II) a t approuv par Industrie Canada pour fonctionner avec les antennes rfrences ci-dessous dans la limite de gain acceptable et limpdance requise pour chaque type dantenne cit. Les antennes non rfrences possdant un gain suprieur au gain maximum autoris pour le type dantenne auquel elles Bluegiga Technologies Oy Page 43 of 47 appartiennent sont strictement interdites dutilisation avec ce matriel. Veuillez vous rfrer au tableau 22 concernant les antennes approuves pour les WF111. Les responsabilits de lintgrateur afin de satisfaire aux rglementations de la FCC et dIndustrie Canada :
Les modules WF111 ont t certifis pour entrer dans la fabrication de produits exclusivement raliss par des intgrateurs dans les conditions suivantes :
Lantenne (ou les antennes) doit tre installe de faon maintenir tout instant une distance minimum de 20cm entre la source de radiation (lantenne) et toute personne physique. Le module transmetteur ne doit pas tre install ou utilis en concomitance avec une autre antenne ou un autre transmetteur. Tant que ces deux conditions sont runies, il nest pas ncessaire de procder des tests supplmentaires sur le transmetteur. Cependant, lintgrateur est responsable des tests effectus sur le produit final afin de se mettre en conformit avec dventuelles exigences complmentaires lorsque le module est install (exemple :
missions provenant dappareils numriques, exigences vis--vis de priphriques informatiques, etc.) ;
IMPORTANT : Dans le cas o ces conditions ne peuvent tre satisfaites (pour certaines configurations ou installation avec un autre transmetteur), les autorisations fournies par la FCC et Industrie Canada ne sont plus valables et les numros didentification de la FCC et de certification dIndustrie Canada ne peuvent servir pour le produit final. Dans ces circonstances, il incombera lintgrateur de faire rvaluer le produit final
(comprenant le transmetteur) et dobtenir une autorisation spare de la part de la FCC et dIndustrie Canada. Etiquetage du produit final Chaque module WF111 possde sa propre identification FCC et son propre numro de certification IC. Si lidentification FCC et le numro de certification IC ne sont pas visibles lorsquun module est install lintrieur dun autre appareil, alors lappareil en question devra lui aussi prsenter une tiquette faisant rfrence au module inclus. Dans ce cas, le produit final doit comporter une tiquette place de faon visible affichant les mentions suivantes :
Contient un module transmetteur certifi FCC QOQWF111 Contient un module transmetteur certifi IC 5123A-BGTWF111 ou Inclut la certification FCC QOQWF111 Bluegiga Technologies Oy Page 44 of 47 Inclut la certification IC 5123A-BGTWF111 Lintgrateur du module WF111 ne doit utiliser que les antennes rpertories dans le tableau 25 certifies pour ce module. Lintgrateur est tenu de ne fournir aucune information lutilisateur final autorisant ce dernier installer ou retirer le module RF, ou bien changer les paramtres RF du module, dans le manuel dutilisation du produit final. Afin de se conformer aux limites de radiation imposes par la FCC et Industry Canada, lantenne (ou les antennes) utilise pour ce transmetteur doit tre installe de telle sorte maintenir une distance minimum de 20cm tout instant entre la source de radiation (lantenne) et les personnes physiques. En outre, cette antenne ne devra en aucun cas tre installe ou utilise en concomitance avec une autre antenne ou un autre transmetteur. Bluegiga Technologies Oy Page 45 of 47 15.4 Qualified Antenna Types for WF111-E This device has been designed to operate with the antennas listed below, and having a maximum gain of 2.14 dBi. Antennas not included in this list or having a gain greater than 2.14 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. Antenna Type Dipole Qualified Antenna Types for WF111-E Maximum Gain 2.14 dBi Table 22: Qualified Antenna Types for WF111-E Any antenna that is of the same type and of equal or less directional gain as listed in table above can be used without a need for retesting. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that permitted for successful communication. Using an antenna of a different type or gain more than 2.14 dBi will require additional testing for FCC, CE and IC. Please, contact support@bluegiga.com for more information. Bluegiga Technologies Oy Page 46 of 47 Contact Information Sales:
Technical support:
sales@bluegiga.com support@bluegiga.com http://techforum.bluegiga.com orders@bluegiga.com Orders:
WWW:
Head Office / Finland:
Postal address / Finland:
Sales Office / USA:
Sales Office / Hong-Kong:
www.bluegiga.com www.bluegiga.hk Phone: +358-9-4355 060 Fax: +358-9-4355 0660 Sinikalliontie 5A 02630 ESPOO FINLAND P.O. BOX 120 02631 ESPOO FINLAND Phone: +1 770 291 2181 Fax: +1 770 291 2183 Bluegiga Technologies, Inc. 3235 Satellite Boulevard, Building 400, Suite 300 Duluth, GA, 30096, USA Phone: +852 3182 7321 Fax: +852 3972 5777 Bluegiga Technologies, Inc. 19/F Silver Fortune Plaza, 1 Wellington Street, Central Hong Kong Bluegiga Technologies Oy Page 47 of 47
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2015-11-18 | 2412 ~ 2462 | DTS - Digital Transmission System | Class II permissive change or modification of presently authorized equipment |
2 | 2015-10-01 | 2412 ~ 2462 | DTS - Digital Transmission System | |
3 | 2012-09-26 | 2412 ~ 2462 | DTS - Digital Transmission System | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 3 | Effective |
2015-11-18
|
||||
1 2 3 |
2015-10-01
|
|||||
1 2 3 |
2012-09-26
|
|||||
1 2 3 | Applicant's complete, legal business name |
Silicon Laboratories Finland Oy
|
||||
1 2 3 | FCC Registration Number (FRN) |
0007782659
|
||||
1 2 3 | Physical Address |
Alberga Business Park, Bertel Jungin aukio 3
|
||||
1 2 3 |
Espoo, N/A 02600
|
|||||
1 2 3 |
Finland
|
|||||
app s | TCB Information | |||||
1 2 3 | TCB Application Email Address |
h******@acbcert.com
|
||||
1 2 3 |
T******@intertek.com
|
|||||
1 2 3 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 3 | Grantee Code |
QOQ
|
||||
1 2 3 | Equipment Product Code |
WF111
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 3 | Name |
P****** R****
|
||||
1 2 3 | Title |
Staff HW Engineer
|
||||
1 2 3 | Telephone Number |
+3589********
|
||||
1 2 3 | Fax Number |
+3589********
|
||||
1 2 3 |
p******@silabs.com
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 3 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
1 2 3 | Yes | |||||
1 2 3 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 3 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 3 | Equipment Class | DTS - Digital Transmission System | ||||
1 2 3 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | IEEE 802.11b/g/n Wi-Fi module WF111 | ||||
1 2 3 | IEEE 802.11 b/g/n Wi-Fi module WF111 | |||||
1 2 3 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 3 | Modular Equipment Type | Limited Single Modular Approval | ||||
1 2 3 | Single Modular Approval | |||||
1 2 3 | Purpose / Application is for | Class II permissive change or modification of presently authorized equipment | ||||
1 2 3 | Original Equipment | |||||
1 2 3 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 2 3 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 3 | Grant Comments | Power Output listed is Conducted. Modular Approval. This device is granted for use in Mobile configurations. Co-location with other transmitters requires use of FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. The Grantee is responsible for providing the documentation required for modular use. The responsibility for the use of this module in all configurations utilized or contemplated, remains with the Grantee. Class 2 Permissive Change for Limited Modular use inside specific host, as shown in this filing. | ||||
1 2 3 | Power Output listed is Conducted. Modular Approval. This device is granted for use in Mobile configurations in which the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and not be co-located with any other transmitters except in accordance with FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. The Grantee is responsible for providing the documentation required for modular use. The responsibility for the use of this module in all configurations utilized or contemplated, remains with the Grantee. Class II Permissive Change | |||||
1 2 3 | Power Output listed is Conducted. Modular Approval. This device is granted for use in Mobile configurations in which the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and not be co-located with any other transmitters except in accordance with FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. The Grantee is responsible for providing the documentation required for modular use. The responsibility for the use of this module in all configurations utilized or contemplated, remains with the Grantee. | |||||
1 2 3 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 3 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 3 | Firm Name |
Prima Ricerca & Sviluppo S.r.l.
|
||||
1 2 3 |
Intertek Semko AB
|
|||||
1 2 3 |
SGS Fimko Oy
|
|||||
1 2 3 | Name |
E****** B********
|
||||
1 2 3 |
P******** I********
|
|||||
1 2 3 |
J**** M********
|
|||||
1 2 3 | Telephone Number |
39-03********
|
||||
1 2 3 |
46-8-********
|
|||||
1 2 3 |
358-9********
|
|||||
1 2 3 | Fax Number |
39-03********
|
||||
1 2 3 |
/********
|
|||||
1 2 3 |
358-9********
|
|||||
1 2 3 |
e******@primaricerca.it
|
|||||
1 2 3 |
p******@intertek.com
|
|||||
1 2 3 |
j******@sgs.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2412.00000000 | 2462.00000000 | 0.0820000 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | 2412.00000000 | 2462.00000000 | 0.0820000 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
3 | 1 | 15C | 2412.00000000 | 2462.00000000 | 0.0820000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC