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APX4 WIRELESS SYSTEM-ON-MODULE DATA SHEET Tuesday, 23 July 2013 Version 1.01 Copyright 2000-2013 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegigas products are not authorized for use as critical components in life support devices or systems. The WRAP, Bluegiga Access Server, Access Point and iWRAP are registered trademarks of Bluegiga Technologies. The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies. All owners. trademarks respective owned herein listed other their are by Bluegiga Technologies Oy VERSION HISTORY Version Comment 0.1 0.2 0.3.1 0.3 0.4 0.4.1 0.4.2 0.4.3 0.5 0.6 0.7 0.8 0.9 1.0 1.01 First draft Defined screws and attachment to motherboard Some small fixes and additions TBDs defined Review Small fix to part number clarification Updated document name, product description and contact information Added Bluetooth RF specifications Clarified pins etc. Fixed layout. Removed software version from part number. Styles updated and fixed Added notes about missing information Added Mouser part number for the SO-DIMM receptacle Chapter 6.5.1 removed Added FCC/IC texts, removed battery related texts Typos Bluegiga Technologies Oy TABLE OF CONTENTS 1 Ordering Information......................................................................................................................................7 1.1 Part number decoder .............................................................................................................................7 2 APx4 pin descriptions ....................................................................................................................................8 2.1 2.2 2.3 2.4 Receptacle ............................................................................................................................................8 Power contacts on the left side .............................................................................................................8 Debug UART on the right side ..............................................................................................................8 SO-DIMM connection pin descriptions ..................................................................................................9 3 Power subsystem ....................................................................................................................................... 22 3.1 3.2 PSWITCH_OUT pin 14 ...................................................................................................................... 23 RESETN ............................................................................................................................................. 23 4 Processor subsystem ................................................................................................................................. 24 4.1 Bootmodes ......................................................................................................................................... 24 5 Wireless interfaces ..................................................................................................................................... 25 5.1 Bluetooth ............................................................................................................................................ 25 5.1.1 Bluetooth GPIOs ........................................................................................................................... 25 5.1.2 Bluetooth Audio interface .............................................................................................................. 25 5.1.3 Bluetooth PCM slots and formats.................................................................................................. 26 5.1.4 Bluetooth I2S interface .................................................................................................................. 26 5.2 Wi-Fi ................................................................................................................................................... 27 6 Peripheral interfaces................................................................................................................................... 28 6.1 6.2 6.3 6.4 6.5 6.6 Ethernet .............................................................................................................................................. 28 USB .................................................................................................................................................... 29 I2C ...................................................................................................................................................... 29 PWM outputs ...................................................................................................................................... 30 SDIO / SPI / MMC .............................................................................................................................. 31 UARTs ................................................................................................................................................ 32 6.6.1 UART 0 .......................................................................................................................................... 32 6.6.2 UART 2 .......................................................................................................................................... 32 6.6.3 UART 3 .......................................................................................................................................... 32 6.6.4 UART 4 .......................................................................................................................................... 33 6.6.5 Debug UART ................................................................................................................................. 33 6.7 6.8 6.9 CAN .................................................................................................................................................... 34 Processor Audio ................................................................................................................................. 34 LCD .................................................................................................................................................... 35 6.10 LRADC0-6 (Touch interface) .............................................................................................................. 36 6.11 HSADC (High-Speed ADC) ................................................................................................................ 37 Bluegiga Technologies Oy 6.12 JTAG .................................................................................................................................................. 37 7 Electrical Characteristics ............................................................................................................................ 39 7.1 7.2 7.3 Absolute Maximum Ratings................................................................................................................ 39 Recommended Operating Conditions ................................................................................................ 39 Power Consumption ........................................................................................................................... 40 8 RF Characteristics ...................................................................................................................................... 41 9 Physical Dimensions .................................................................................................................................. 43 10 11 Attachment to motherboard ................................................................................................................ 44 Layout Guidelines ............................................................................................................................... 45 11.1 Internal antenna: Optimal module placement .................................................................................... 45 11.2 External antenna ................................................................................................................................ 45 11.3 Thermal Considerations ..................................................................................................................... 45 11.4 EMC Considerations for Motherboard ................................................................................................ 45 12 Certifications ....................................................................................................................................... 47 12.1 CE ....................................................................................................................................................... 47 12.2 FCC .................................................................................................................................................... 47 12.3 IC ........................................................................................................................................................ 48 12.4 IC ........................................................................................................................................................ 49 12.5 MIC, formerly TELEC ......................................................................................................................... 51 12.6 Qualified Antenna Types for APx4-E ................................................................................................. 51 13 Contact Information ............................................................................................................................ 52 Bluegiga Technologies Oy DESCRIPTION KEY FEATURES that includes The Bluegiga APx4 is a small form factor, low power system-on-module the latest wireless connectivity standards: 802.11 b/g/n and Bluetooth 4.0. APx4 is based on Freescale's i.MX28 processor family and runs an embedded Linux operating system based on the Yocto ProjectTM. In addition to integrating the 454MHz ARM9 processor, the wireless connectivity technologies, Linux operating system the APx4 also includes with several built in 802.11 such and Bluetooth 4.0 stacks, Continua v.1.5 compliant IEEE manager and many more. This combination provides an ideal platform for designing multi-radio wireless gateways that enables fast time-to-market and minimum R&D risks. applications, the as The Bluegiga APx4 software can be easily extended or tailored customizing the Linux operating system with applications. The motherboards for the APx4 can be easily extended to include almost anything from 3G modems to Ethernet and audio interfaces to and touch screen displays. The Bluegiga APx4 is an ideal product for applications requiring wireless or wired connectivity technologies and the processing power of the ARM9 processor, such as health and fitness gateways, building and home automation gateways, M2M, point-of-sale and industrial connectivity. APPLICATIONS:
Health gateways M2M connectivity Fitness gateways Home and building automation Point-of-sale gateways People and asset tracking APx4 is a computing platform:
454MHz ARM9 core (Freescale i.MX28) 64MB RAM 128MB Flash Real Time Clock Linux operating system SO-DIMM form factor A connectivity platform:
Bluetooth 4.0 dual-mode radio 2.4GHz 802.11 b/g/n radio Wi-Fi Access Point mode 10/100 Ethernet USB 2.0 High Speed With many extension options:
Up to 800 x 480, 24bit display Resistive touch screen MMC/SDIO Multiple SPI, UART and IC PWM, GPIO and AIO IS Linux operating system:
Based on the Yocto Project(TM) Thousands of open source software packets available Qualifications:
Bluetooth CE FCC and IC Figure 1: Physical outlook Bluegiga Technologies Oy 1 Ordering Information Product code CPU and memories Connectivity Antenna APX4-367CC-A i.MX283 Bluetooth + Wi-Fi Temperature range
-10 50C Internal antenna APX 4 3 6 7 C C A 64MB DDR2 128MB Flash 1.1 Part number decoder Product category APX Product generation 4 Processor 3: i.MX283 Memory Flash 6: 64MB 7: 128MB Connectivity C: Bluetooth and Wi-Fi Temperature C: Commercial I: Industrial (contact sales@bluegiga.com) Antenna A: Internal antenna E: External antenna Note: Not all variants are available. Minimum order quantities and lead times may apply for special variants. Please contact Bluegiga Technologies Oy for more information. Bluegiga Technologies Oy Page 7 of 52 2 APx4 pin descriptions The APX4 connector uses a standard DDR1 SO-DIMM connector with 2.5V keying. Odd numbered pins are located on top layer Even numbered pins are located on bottom layer There is a pitch (0.3mm) offset from top layer pins to bottom layer pins. Note that most receptacles also have 0.3mm offset from odd pins to even pins. 2.1 Receptacle Suitable receptacles are available from multiple vendors. For example TE Connectivitys part number 1473005-1, Mouser part number: 571-1473005-1 and Digi-Keys part number: A99605-ND. PCB footprint and schematic symbol for the mentioned part number will be available for download from Techforum in Mentor Graphics PADS format. 2.2 Power contacts on the left side In addition to the 200 pins/finger contacts there are two pairs of plated through holes on the left side of the module which can be used for powering the module stand-alone (not assembled on any motherboard). The pitch between the holes is 2.54mm. Leave the holes unconnected if the module is assembled on a motherboard. Name GND VIN GND Function Ground
+5V input Ground VBATTERY Battery positive input/output 2.3 Debug UART on the right side Table 1: Power supply pins On the right side there are four plated through holes for PWM or debug port stand-alone (not assembled on any motherboard). The vertical distance between the holes is 1.27mm:
Name 3V3 Function 3.3V output (for current limits, see Table 50) PWM1/DUART TxD Debug UART data transmit, logic level 3.3V PWM0/DUART RxD Debug UART data receive, logic level 3.3V GND Ground Table 2: Debug UART pins Bluegiga Technologies Oy Page 8 of 52 2.4 SO-DIMM connection pin descriptions Note: Signals/nets marked with a star (*) are not present on standard version Pin# Default function Net name Note 5V input 5V input 5V input 5V input VIN VIN VIN VIN Battery input/output VBATTERY Battery input/output VBATTERY Battery input/output VBATTERY 1 2 3 4 5 6 7 8 9 Bootmode 3.3V output 10 3.3V output 11 3.3V output 12 3.3V output BOOTMODE 3V3 3V3 3V3 3V3 Pins 9-10 may source up to 200mA combined. Pins 9-10 may source up to 200mA combined. Pins 9-10 may source up to 200mA combined. Pins 9-10 may source up to 200mA combined. RTC battery VBACKUP PS switch PSWITCH_OUT NC NC NC NC Reset in - Master reset RESETN Ground GND Table 3: Main power pins 13 14 15 16 17 18 Bluegiga Technologies Oy Page 9 of 52 Pin#
Default function Ethernet TX -
GND Ethernet TX +
3.3V output Ethernet RX -
Ethernet LED Ethernet RX +
GND 19 20 21 22 23 24 25 26
* See 6.1 for detailed function. Pin#
Default function 27 28 29 30 31 32 USB External VBUS enable USB D-
USB D+
Ground Net name ETN_TXN GND ETN_TXP 3V3 ETN_RXN ETN_LED1N*
ETN_RXP GND Table 4: Ethernet Net name SPDIF*
NC USB1DM NC USB1DP GND Table 5: USB Host Bluegiga Technologies Oy Page 10 of 52 Pin#
Default function USB OTG id USB D-
USB D+
Ground 33 34 35 36 37 38 39 Pin#
Default function I2C Data I2C Clock 40 41 Pin#
Default function PWM (Backlight) Status led 42 43 Net name USB0_ID NC USB0DM NC USB0DP NC GND Table 6: USB On-the-go Net name I2C0_SDA I2C0_SCL Table 7: I2C 0 Net name PWM4 PWM3 Table 8: Dedicated PWMs Bluegiga Technologies Oy Page 11 of 52 Pin#
Default function Net name Slave select 1 Slave select 2 SDIO_DAT1_OUT*
SDIO_DAT2_OUT*
Command - Master out, slave in SDIO_CMD_OUT*
Data 0, Master in, slave out SDIO_DAT0_OUT*
Clock SDIO_CLK_OUT*
Ready - Slave select 0 SDIO_DAT3_OUT*
Ground GND Table 9: SSP2 SDIO/MMC/SPI 44 45 46 47 48 49 50 Pin#
Default function Card detect Data 0 Data 1 Data 2 Data 3 Command Clock Ground 51 52 53 54 55 56 57 58 Pin#
Default function UART transmit UART receive UART clear-to-send UART request-to-send 59 60 61 62 Net name SSP0_DETECT SSP0_DATA0 SSP0_DATA1 SSP0_DATA2 SSP0_DATA3 SSP0_CMD SSP0_SCK GND Table 10: SSP0 SDIO/MMC/SPI Net name AUART0_TX AUART0_RX AUART0_CTS AUART0_RTS Table 11: UART 0 Bluegiga Technologies Oy Page 12 of 52 Pin#
Default function UART transmit UART receive 63 64 65 66 Pin#
Default function UART transmit UART receive Ground 67 68 69 70 71 Pin#
Default function Bluetooth GPIO Bluetooth GPIO Bluetooth GPIO Bluetooth GPIO 72 73 74 75 Net name SSP2_MOSI SSP2_SCK NC NC Table 12: UART 2 Net name SSP2_SS0 SSP2_MISO NC NC GND Table 13: UART 3 Net name BT_PIO7 BT_PIO8 BT_PIO9 BT_PIO25 Table 14: Bluetooth GPIO Bluegiga Technologies Oy Page 13 of 52 Pin#
Default function CAN 0 transmit Ground CAN 1 transmit CAN 1 receive Ground CAN 0 receive Ground 76 77 78 79 80 81 82 Pin#
Default function MCLK Data line 1 Data line 0 Bit clock Left/Right clock GND 83 84 85 86 87 88 Net name GPMI_RDY2*
GND GPMI_CE2N*
GPMI_CE3*
GND GPMI_RDY3*
GND Table 15: CAN Net name SAIF0_MCLK SAIF1_SDATA0 SAIF0_SDATA0 SAIF0_BITCLK SAIF0_LRCLK GND Table 16: Primary audio / UART 4 Bluegiga Technologies Oy Page 14 of 52 Pin#
Default function Net name 89 90 91 92 93 94 95 96 97 98 99 100 Ground NC NC NC NC NC GND NC NC NC NC NC NC Table 17: Reserved group 1 Bluegiga Technologies Oy Page 15 of 52 Pin#
Default function Net name Ground 1.4V output*
1.8V output*
4.2V output*
Ground 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 NC GND NC NC NC NC 1V4_CPU 1V8 4V2_CPU NC GND NC NC NC NC GND Table 18: Reserved group 2
*Important: Pins 107-109 are only meant for manufacturing test. Please leave unconnected. Do not pull any current from these outputs. Doing so may create a black hole in the universe. Bluegiga Technologies Oy Page 16 of 52 Pin#
Default function Net name 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Ground Data 12 Data 13 Data 14 Data 15 Data 16 Data 17 Data 18 Data 19 Data 20 Data 21 Data 22 Data 23 Ground LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 GND LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23 GND Bluegiga Technologies Oy Page 17 of 52 Pin#
Default function Net name Table 19 LCD data lines Horizontal Sync Vertical Sync LCD Enable Dot clock Ground 143 144 145 146 147 LCD_WR_RWN LCD_RD_E LCD_CS LCD_RS GND Table 20: LCD control lines Pin#
Function Net name 148 Debug UART RX or I2C1_SDA 149 Debug UART TX or I2C1_SCL PWM0 (also connected to PTH pins on right side) PWM1 (also connected to PTH pins on right side) 150 151 LCD reset / GPIO LCD_RESET NC Table 21: Debug UART / PWM / I2C1 / GPIO Bluegiga Technologies Oy Page 18 of 52 Pin#
Function Net name 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Ground Ground Ground Ground Ground Ground NC NC NC NC NC NC NC GND GND NC NC GND GND NC NC GND GND NC WiFi Activity Ground WIFI_ACT GND Table 22: Reserved group 3 Bluegiga Technologies Oy Page 19 of 52 Pin#
Function Net name Wi-Fi Debug SPI - MISO SPI_WIFI_MISO Wi-Fi Debug SPI CLK SPI_WIFI_CLK Wi-Fi Debug SPI MOSI SPI_WIFI_MOSI Wi-Fi Debug SPI - CS SPI_WIFI_CS RTC interrupt INT_EXT_RTC_N Factory reset button / JTAG return clock JTAG_RTCK JTAG test clock JTAG test data in JTAG test data out JTAG test mode state JTAG test reset Ground JTAG enable boundary scan JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST GND DEBUG Table 23: Misc 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin#
Function Net name 185 186 187 188 189 190 191 192 193 194 Touch controller XN Touch controller XP Touch controller YN Touch controller YP Touch controller WIPER Generic ADC 0 Generic ADC 1 High speed ADC Ground Ground LRADC4 LRADC2 LRADC5 LRADC3 LRADC6 LRADC0 LRADC1 HSADC0 GND GND Table 24: ADC Bluegiga Technologies Oy Page 20 of 52 Pin #
Function Net name Bluetooth debug enable BT_SPI_PCM1N PCM in PCM out PCM clock PCM sync Ground BT_PCM1_IN BT_PCM1_OUT BT_PCM1_CLK BT_PCM1_SYNC GND Table 25: Bluetooth audio 195 196 197 198 199 200 Bluegiga Technologies Oy Page 21 of 52 3 Power subsystem Pin#
Function APx4 net name Description 5V input VIN Main power input Battery input/output VBATTERY 3.3V output 3V3 rechargeable A connected battery can be For maximum current draw, see Table 50 RTC battery VBACKUP RTC battery backup power Power switch PSWITCH_OUT Power switch Reset in - Master reset RESETN Active low master reset. Resets the entire board. Table 26: Power supply pins 1-4 5-7 9-12, 22 13 14 17 The module is powered through the 5V input. It is recommended that all the pins (1-4) are connected together on the application board. The external battery connectable to VBATTERY is currently not supported. VBACKUP is connected to the Real-Time clock battery and the VDD input of the Real Time Clock. This pin can be used to power the real time clock in cases where the battery is not placed on the module. 3V3 VDD Real Time Clock Pin 13:VBACKUP On-board battery Figure 2: VBACKUP and battery connection Bluegiga Technologies Oy Page 22 of 52 3.1 PSWITCH_OUT pin 14 Note: In most cases the user can ignore the PSWITCH pin. Leave unconnected for normal operation. The SWITCH_OUT (pin 14) has three levels: low, mid and high. A 10k pull-up to mid-level is applied on the module to the PSWITCH line, causing the device to start booting immediately once power is applied. Boot-up requires a mid-level voltage to be present for >100ms. If the PSWITCH is pulled high for over 5 seconds, for example by connecting it to 3.3V, a special Freescale USB recovery mode is entered. For further details about the power switch, refer to Freescales Reference Manual, Section 11.4. This mode can also be entered using the BOOTMODE pin. 3.2 RESETN Power-on reset is generated internally. If a reset from external pins is required use the RESETN pin. RESETN is internally pulled up to 3.3V. The RESETN pin must be kept low for at least 100ms and then released in order to guarantee a proper reset. 100ms NRESET Figure 3: NRESET Bluegiga Technologies Oy Page 23 of 52 4 Processor subsystem The processor belongs to the Freescale i.MX28-family and integrates an ARM9 core operating at 454MHz. The standard APX4 variant uses the i.MX283 processor. The module also has 128MB of SLC NAND flash and 64MB of DDR2-400 memory. For more details regarding the features the processor offers, please see the Freescale Reference Manual. By default the module boots from the NAND flash into the U-Boot boot loader environment. From there the boot loader loads a Linux kernel which boots into the Bluegiga Linux userspace. 4.1 Bootmodes The module supports booting from multiple different media including NAND Flash, Secure Digital (SD) cards, MMC cards, I2C EEPROM and USB (in a device mode). The selected boot media can be selected using the LCD_DATA[0-3] signals or in the case of USB recovery boot, by tying the BOOTMODE pin to ground. By default the module boots from internal NAND flash, meaning that LCD_DATA[3], LCD_DATA[1] and LCD_DATA[0] have pull-downs on the module and LCD_DATA[2] has a pull-up. that when Default boot mode LCD_DATA[0]..LCD_DATA[3] are left unconnected the module boots from internal NAND. After boot the LCD_DATA lines can be used fro any purpose. face. The module has pull-ups and pull-downs so in bold LCD_DATA[3]
LCD_DATA[2]
LCD_DATA[1]
LCD_DATA[0] Port 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 USB0 device mode boot EEPROM connected to I2C0 SPI flash on SSP2 (non-Wi-Fi version only) SPI flash on SSP3 (not available on standard versions) Modules internal NAND Flash Wait for JTAG connection SPI EEPROM on SSP3 (not available on standard versions) SD/MMC card on SSP0 SD/MMC on SSP1 (not available on standard versions) Table 27: Bootmodes Bluegiga Technologies Oy Page 24 of 52 5 Wireless interfaces The wireless connectivity on the module is implemented using two separate chips which share a 2.4GHz antenna. 5.1 Bluetooth The module is a fully qualified Bluetooth 4.0, Class 1, system, supporting both classical Bluetooth as well as Bluetooth Smart (Bluetooth low energy) devices simultaneously. 5.1.1 Bluetooth GPIOs Pin#
Function 72 73 74 75 Bluetooth GPIO 7 Bluetooth GPIO 8 Bluetooth GPIO 9 Bluetooth GPIO 25 Net name BT_PIO7 BT_PIO8 BT_PIO9 BT_PIO25 Table 28: Bluetooth GPIO These GPIOs are controlled by the Bluetooth baseband chip. The main processor can read and write them by issuing special commands to the Bluetooth chip, making them suitable for use as status indicators, but not for high speed signals. For the current status of software support, please refer to the software documentation. Contact support if needed. The pins are bidirectional pins with internal programmable strength pull-up or pull-down. By default they are inputs with a weak pull-down. 5.1.2 Bluetooth Audio interface Pin # Net name PCM function I2S function Debug interface 195 BT_SPI_PCM1N Select Audio: GND Select Audio: GND Select Debug: +3.3V 196 BT_PCM1_IN PCM in Serial in (SD_IN) MOSI 197 BT_PCM1_OUT PCM out Serial out (SD_OUT) MISO 198 BT_PCM1_CLK PCM clock Serial clock (SCK) Clock 199 BT_PCM1_SYNC PCM sync Write sync (WS) Chip select (active low) Table 29: Bluetooth audio and debug interface The Bluetooth audio functionality can be configured to work in either I2S or PCM mode. In addition, the Bluetooth chips debug interface is multiplexed with the audio pins. The audio interface supports continuous transmission and reception of PCM audio data over Bluetooth. Operation in either master or slave mode are supported and many different clock modes can be supported. A maximum of 3 SCO audio links can be transmitted through the PCM interface at any one time. Bluegiga Technologies Oy Page 25 of 52 5.1.3 Bluetooth PCM slots and formats The module receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats. 16 clocks cycles for 8-bit, 13-bit or 16-bit sample formats. The supported formats are:
13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. A sample rate of 8ksamples/s. Little or big endian bit order. For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some codecs. There is also a compatibility mode that forces PCM_OUT to be 0. In master mode, this allows for compatibility with some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running. 5.1.4 Bluetooth I2S interface The I2S mode supports left-justified and right-justified data. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. The digital audio interface is configured using the PSKEY_DIGITAL_AUDIO_CONFIG in the Bluetooth PS Key configuration. The internal representation of audio samples within CSR8811 is 16-bit and data on SD_OUT is limited to 16-
bit per channel. Symbol Parameter Minimum Maximum Unit
tch tcl tssu tsh topd tisu tih SCK frequency SCK frequency SCK high time SCK low time WS valid to SCK high setup time SCK high to WS invalid hold time SCK low to SD_OUT valid delay time SD_IN valid to SCK high setup time SCK high to SD_IN invalid hold time
80 80 20 2.5
20 2.5 6.2 96
20
MHz kHz ns ns ns ns ns ns ns Table 30: I2S Slave mode timing Bluegiga Technologies Oy Page 26 of 52 Symbol Parameter Minimum Maximum Unit
tspd topd tisu tih SCK Frequency WS Frequency SCK low to WS valid delay time SCK low to SD_OUT valid delay time SD_IN valid to SCK high setup time SCK high to SD_IN invalid hold time
18.44 0 6.2 96 39.27 18.44
MHz kHz ns ns ns ns Table 31: I2S Master mode timing 5.2 Wi-Fi The on board Wi-Fi is designed for IEEE 802.11b/g/n in the 2.4GHz band. Hardware encryption support for WEP40/64, WEP104/128, TKIP, CCMP (AES), BIP and CKIP provides functionality for WPA, WPA2, IEEE 802.11i, IEEE 802.11w and CCX advanced security mechanisms. The following modulations are supported:
All mandatory IEEE 802.11b modulations: 1, 2, 5.5, 11Mbps All IEEE 802.11g OFDM modulations: 6, 9, 12, 18, 24, 36, 48, 54Mbps Single stream IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps STBC (Space Time Block Coding) reception for IEEE 802.11n HT modulations MCS0-7 The receiver features direct conversion architecture. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the receiver to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitized. High-order baseband in-band interference. filters ensure good performance against The transmitter features a direct conversion IQ transceiver. Digital baseband transmit circuitry provides the required spectral shaping and on-chip trims are used to reduce IQ modulator distortion. Transmitter gain can be controlled on a per-packet basis, allowing the optimization of the transmit power as a function of modulation scheme. The modulator supports digital predistortion to reduce non-linarites in the power amplifier. The module supports automatic PA thermal drift compensation by measuring the transmit power through an internal power coupler. Bluegiga Technologies Oy Page 27 of 52 6 Peripheral interfaces The module allows for several kinds of different interfaces to peripherals to be used. 6.1 Ethernet Pin#
Function 19 20 21 22 23 24 25 26 Ethernet TX -
GND Ethernet TX +
3.3V output Ethernet RX -
Ethernet LED Ethernet RX +
GND Net name ETN_TXN GND ETN_TXP 3V3 ETN_RXN ETN_LED1N ETN_RXP GND Table 32: Ethernet pins The Ethernet I/O lines are connected on the module to a standard 10Base-T/100Base-TX physical layer transceiver (PHY). A connector board will only need to have the magnetics as well as an RJ45 jack in order to have fully functioning Ethernet. Multiple vendors also supply RJ45 jacks with integrated magnetics under brand names such as MagJack and PulseJack which further simplify design. A reference schematic for such a design is available in the APx4 reference design. When routing the Ethernet signals, care should be taken to route the differential signals together, meaning that for example ETN_TXN and ETN_TXP should be kept close together. The traces must also be kept short in order to avoid EMC issues. The Ethernet LED pin (ETN_LED1N) indicates link and activity and has a maximum output drive current of 8 mA. The ETN_LED is high when no Link is present (typically connected so that a physical LED is off), low when a Link is present (physical LED on) and toggled on activity (physical LED is blinking). Make sure that the driving capability of 8mA is not exceeded. Pin state HIGH LOW Toggle LED Off On Blinking Meaning No Link Link Activity Table 33: ETN_LED1N pin Figure 4 Typical external LED connection Bluegiga Technologies Oy Page 28 of 52 6.2 USB Pin#
Function Net name USB OTG Host External VBUS enable SPDIF*
USB Host D-
USB Host D+
USB OTG ID USB OTG D-
USB OTG D+
USB1_DM USB1_DP USB0_ID USB0_DM USB0_DP Table 34: USB pins 27 29 31 33 35 37 The module has two USB high-speed controllers, one which supports USB Host mode only and another which support USB On-the-Go (OTG). The USB On-the-Go controller is capable of operating as a USB Host or a USB Device and support the OTG role negotiation via the USB OTG-ID signal. For the current software support, please see the software documentation. The USB D+ and D- signals can be directly connected to a USB connector, however when using a connector, protection against electrostatic discharge (ESD) should be taken into account. Because USB high-speed is a very high frequency digital signal (480Mbps), care must be taken to route the D+ and D- signals as close together as possible and to have a ground plane follow them. The traces must also be kept as short as possible. The USB Host External VBUS enable signal is not present in the standard model, and has a fixed pull-up. For more details refer to the i.MX28 Applications Processor Reference Manual (MCIMX28RM) chapters 31 and 32. 6.3 I2C Pin#
I2C function Alternate Functions Net name 40 41 I2C 0 Data I2C 0 Clock 148 I2C 1 Data 149 I2C 1 Clock I2C0_SDA I2C0_SCL PWM0, Debug UART TX PWM0/I2C1_SDA PWM1, Debug UART RX PWM1/I2C1_SCL Table 35: I2C interface The Inter Integrated Circuit bus (I2C) is a standard two-wire interface used for communication between peripherals and the host. The interface supports both standard speed (up to 100kbps) and as fast speed
(400kbps) I2C connection to multiple devices with the processor acting in either master or slave mode. Bluegiga Technologies Oy Page 29 of 52 The primary I2C interface (I2C 0, pins 40 and 41) is also connected to the modules Real Time Clock (RTC) chip and thus some additional restrictions for the communication apply. The processor is always the master. The standard 2K pull-ups are located on APx4. Do not place additional pull-ups on I2C 0. One I2C slave address (1010001X) on I2C 0 is reserved for the Real Time Clock PCF8563T on the APx4:
Read: 0xA3 (10100011) Write: 0xA2 (10100010) The secondary I2C (I2C 1) is available on pins 148 and 149 and can be used freely in either master or slave mode. By default it is configured to provide the Debug UART. I2C 1 does not have built-in pull-ups. For more details about I2C, please refer to the i.MX28 Applications Processor Reference Manual, chapter 27. 6.4 PWM outputs Pin# Default function PWM function Additional function Net name 42 43 LCD Backlight (PWM4) PWM4 Status led (PWM3) PWM3 PWM4 PWM3 148 Debug UART TX PWM0 I2C 1 bus data PWM0/I2C1_SDA 149 Debug UART RX PWM1 I2C 1 bus clock PWM1/I2C1_SCL MCLK Data line 1 Data line 0 Bit clock Left/Right clock 83 84 85 86 87 PWM3 PWM7 PWM6 PWM5 PWM4 UART4 CTS SAIF0_MCLK SAIF1_SDATA0 UART 4 TX SAIF0_SDATA0 UART4 RX SAIF0_BITCLK UART4 RTS SAIF0_LRCLK Table 36: PWM outputs The module has up to seven Pulse Width Modulator outputs available. Independent output control of each phase allows 0, 1 or high-impedance to be independently selected for the active and inactive phases. Two dedicated PWM outputs are at pins 42 and 43, and are typically used for the LCDs backlight and as a status led, respectively. The same PWM outputs are available also on pins 83 and 87. The Debug UART on pins 148 and 149 can be disabled and used for two independent PWM outputs instead. For more details about PWM, please refer to the i.MX28 Applications Processor Reference Manual, chapter 28. Bluegiga Technologies Oy Page 30 of 52 6.5 SDIO / SPI / MMC Pin#
SDIO/SD/MMC SPI mode Net name 51 52 53 54 55 56 57 58 Card detect SSP0_DETECT Data 0 Data 1 Data 2 Data 3 Command Clock Ground MISO SSP0_DATA0 SSP0_DATA1 SSP0_DATA2 Slave Select SSP0_DATA3 MOSI Clock SSP0_CMD SSP0_SCK GND Table 37: SDIO/SPI/MMC The Synchronous Serial Port subsystem provides support for MMC cards, SD cards, SDIO devices, SPI master and slave communication and eMMC 4.4 devices. In a standard configuration 1-bit and 4-bit modes for MMC/SD/SDIO/eMMC is available. On versions without Wi-Fi support the 8-bit mode can also be configured. For use with removable cards, a hardware card detect pin is provided. For further information, please refer to the i.MX28 Applications Processor Reference Manual, chapter 17. Bluegiga Technologies Oy Page 31 of 52 6.6 UARTs The module can be configured to support up to five UARTs simultaneously, two with hardware flow control, two without hardware flow control and one for debugging. The UART interfaces offer similar functionality to the industry-standard 16C550 UART device, and the regular UARTs support baud rates of up to 3.25Mbits/s. For further information about UARTs 0, 2, 3 and 4, please refer to the i.MX28 Applications Processor Reference Manual, chapter 30. Debug UART is covered in chapter 24. 6.6.1 UART 0 Pin#
UART 0 Debug UART UART 4 Direction Net name 59 60 61 62 Transmit Request-to-send Receive Clear-to-Send Output from module AUART0_TX Input to module AUART0_RX Clear-to-send Receive Receive Input to module AUART0_CTS Request-to-send Transmit Transmit Output from module AUART0_RTS The first UART section (pins 59-62) is by default configured to provide UART 0 with hardware flow control. The hardware supports selecting the function of each pin separately. For example pins 59 and 60 could be configured for UART 0 and 61 and 62 for UART 4. Table 38: UART0 6.6.2 UART 2 Pin#
UART 2 function Alternative function Net name 63 64 TX - Transmit SAIF 0 SDATA 2 SSP3_MOSI RX - Receive SAIF 0 SDATA 1 SSP2_SCK The pins 63 and 64 provide UART 2 functions. UART 2 does not have hardware flow control available. They can alternatively be configured as additional processor audio data lines. Table 39: UART 2 6.6.3 UART 3 Pin#
UART 3 function Alternative function Net name 67 68 TX - Transmit SAIF 1 SDATA 2 SSP2_SS0 RX - Receive SAIF 1 SDATA 1 SSP2_MISO The pins 67 and 68 provide UART 3 functions. UART 3 does not have hardware flow control available. They can alternatively be configured as additional processor audio data lines. Table 40: UART 3 Bluegiga Technologies Oy Page 32 of 52 6.6.4 UART 4 Pin#
UART 4 Other functions Net name 61 62 83 85 86 87 Receive Transmit DUART RX, AUART 0 CTS AUART0_CTS DUART TX, AUART 0 RTS AUART0_RTS Clear-to-send SAIF0_MCLK, PWM 3 SAIF0_MCLK Transmit Receive SAIF0_SDATA0, PWM 6 SAIF0_SDATA0 SAIF0_BITCLK, PWM 5 SAIF0_BITCLK Request-to-send SAIF0_LRCLK, PWM 4 SAIF0_LRCLK Table 41: UART 4 The fourth UART is not available by default, but can be configured to be available from two different locations. Using UART 4 disables either CPU Audio or UART 0s hardware flow-control lines. If hardware flow control is required, then the CPU Audio pins (83-87) can be configured to provide the UART 4 functionality instead of CPU Audio. Using UART 4 with hardware flow control at the same time as CPU Audio is not possible. If hardware flow control is not required for UART 4 or for UART 0, then the hardware flow control lines of UART 0 can be configured to provide UART 4 RX/TX instead. 6.6.5 Debug UART Pin#
Debug UART Alternative functions UART I/O direction Net name 148 Receive I2C1 SDA, PWM0 Input to module PWM0 149 Transmit I2C1 SCL, PWM1 Output from module PWM1 59 60 61 62 Request-to-send UART 0 TX Output from module AUART0_TX Clear-to-Send UART 0 RX Input to module AUART0_RX Receive UART 0 CTS, UART 4 RX Input to module AUART0_CTS Transmit UART 0 RTS, UART 4 TX Output from module AUART0_RTS Table 42: DEBUG UART By default the Debug UART is provided on pins 148 and 149 without using hardware flow control. This will prevent the use of the second I2C port. Alternatively the Debug UART can be configured to be available from the pins of UART 0 as seen in the table above. The main difference between the Debug UART and the Application UARTs is that there is no DMA for the Debug UART and the maximum baud rate is 115.2Kb/s. It unsuitable for any high throughput use-cases and consumes more processor resources than the other UART interfaces, making it best suited for debugging. In Bluegiga Technologies Oy Page 33 of 52 theory the Debug UART can be used for other UART applications instead of debugging, but it is primarily intended for simple console access to the processor. For further information, please refer to the i.MX28 Applications Processor Reference Manual, chapter 30. 6.7 CAN Pin#
Function Net name 76 78 79 81 CAN 0 transmit GPMI_RDY2*
CAN 1 transmit GPMI_CE2*
CAN 1 receive GPMI_CE3*
CAN 0 receive GPMI_RDY3*
Table 43: CAN The standard model does not include CAN support and pins 76, 78, 79 and 81 are not to be connected as they cannot be used. On the model with CAN support, the pins can be used as described in the i.MX28 Applications Processor Reference Manual, chapter 25. 6.8 Processor Audio Pin# Audio function SAIF 0 SAIF 1 Alternate functions Net name 83 Master clock MCLK AUART4 CTS SAIF0_MCLK 84 Data line SDATA1 SDATA0 PWM 7 SAIF1_SDATA0 85 Data line SDATA0 86 Bit clock BITCLK 87 Left/Right clock LRCLK 63 Data line SDATA2 64 Data line SDATA1 AUART4 TX, PWM 6 SAIF0_SDATA0 AUART4 RX, PWM 5 SAIF0_BITCLK AUART4 RTS, PWM 4 SAIF0_LRCLK UART 2 TX SSP2_MOSI UART 2 RX SSP2_SCK 67 Data line 68 Data line DATA2 UART 3 TX SSP2_SS0 DATA1 UART 3 RX SSP2_MISO Table 44: AUDIO The serial audio interface provides a serial interface to the industrys most common analog codecs. On the processor side, there are two serial audio interface subsystems, SAIF0 and SAIF1. These two can be used together to provide full-duplex stereo audio transfers, where SAIF0 is used as an output and for managing the clocks while SAIF1 is used as a slave to SAIF0 and for audio input. Bluegiga Technologies Oy Page 34 of 52 Each data line carries two channels of audio data, meaning that if SDATA0, SDATA1 and SDATA2 are all used, bi-directional 6 channel audio is possible. Please note that when the pins for UART 2 and UART 3 are used as audio data lines, they cannot be used as UARTs. Each function can be configured separately, so in case for example only one channel stereo is required, only the data line on pin 84 or 85 need to be used, allowing for the rest of the data lines to be used for other purposes. For example if bi-directional audio is not required, the data input line on pin 84 can alternatively be configured as a second SAIF0 data line (SAIF0_SDATA1), meaning it is possible to have 4-channel audio input or output without sacrificing UART 2 or UART 3. The module has been tested with the Freescale SGTL5000 audio codec which is used in the reference design. If the optional master clock is not used, it can be configured to operate as a GPIO. For more information about the serial audio interfaces, please refer to refer to the i.MX28 Applications Processor Reference Manual, chapter 35. 6.9 LCD Pin#
Default function Net name 143 144 145 146 147 Horizontal Sync Vertical Sync LCD Enable Dot clock Ground LCD_WR_RWN LCD_RD_E LCD_CS LCD_RS GND 117-141 Data lines, see Table 19 LCD_D0-LCD_D23 Table 45: LCD signals The LCDIF provides display data for external LCD panels from simple text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time. The LCDIF supports RGB (DOTCLK) modes as well as system mode including both VSYNC and WSYNC modes. Features:
Display resolution up to 800x480. AXI-based bus master mode for LCD writes and DMA operating modes for LCD reads requiring minimal CPU overhead. 8/16/18/24 bit per pixel. Programmable timing and parameters for system, MPU, VSYNC and DOTCLK LCD interfaces to support a wide variety of displays. ITU-R BT.656 mode including progressive-to-interlace feature and RGB to YCbCr 4:2:2 color space conversion to support 525/60 and 625/50 operation. Ability to drive 24-bit RGB/DOTCK displays up to WVGA at 60 Hz. High robustness guaranteed by 512-pixel FIFO with under-run recovery. Bluegiga Technologies Oy Page 35 of 52 Support for full 24-bit system mode (8080/6080/VSYNC/WSYNC). ITU-R/BT.656 compliant D1 digital video output mode with on-the-fly RGB to YCbCr color-space-
conversion. Support for a wide variety of input and output formats that allows for conversion between input and output (for example, RGB565 input to RGB888 output). For more information refer to the i.MX28 Applications Processor Reference Manual, chapter 33. 6.10 LRADC0-6 (Touch interface) Resolution Maximum sampling rate DC input voltage Expected plate resistance Function 12 bits 428kHz 0-1.85V 2000-50000 ohm Table 46: LRADC LRADC 0 - 6 measure the voltage on the seven application-dependent LRADC pins. The auxiliary channels can be used for a variety of uses, including a resistor-divider-based wired remote control, external temperature sensing, touch-screen, button and so on. Pin#
4-wire touch 5-wire touch Other Net name 185 186 187 188 189 190 191 X-
X+
Y-
Y+
UR UL LR LL Generic ADC 4 LRADC4 Generic ADC 2 LRADC2 Generic ADC 5 LRADC5 Generic ADC 3 LRADC3 WIPER Generic ADC 6 LRADC6 Generic ADC 0 LRADC0 Generic ADC 1 LRADC1 Table 47: LRADC For pull-up or pull-down switch control on LRADC2~5 pins, please refer to HW_LRADC_CTRL0 register. LRADC 0 can be used for button and external temperature sensing, they cannot be enabled at same time in hardware configuration. LRADC 1 can be used for button as well as LRADC 0. For an example of how LRADC can be used for connecting multiple buttons, please see Freescales reference design for the i.MX28 processor. For more information refer to the i.MX28 Applications Processor Reference Manual. Bluegiga Technologies Oy Page 36 of 52 6.11 HSADC (High-Speed ADC) Function Value Input sampling capacitance (Cs) 1.0pF typical Resolution Maximum sampling rate DC input voltage Power-up time 12 bits 2MHz 0.5 VDDA-0.5 1 sample cycles The processor contains a high speed, high resolution analog to digital converter which can be used when the lower resolution ADCs do not provide enough sampling speed or resolution. For more information refer to refer to the i.MX28 Applications Processor Reference Manual. Table 48: HSADC 6.12 JTAG Pin#
Function Net name Note 118 Mode 177 JTAG reset) LCD_D1 LCD_D1=HIGH: CPU is ready, waiting for JTAG connection return clock
(Factory JTAG_RTCK* During normal operation, this pin is reserved for use as a factory reset button by the software. 178 JTAG test clock JTAG_TCK 179 JTAG test data in JTAG_TDI 180 JTAG test data out JTAG_TDO 181 JTAG test mode select JTAG_TMS 182 JTAG test reset JTAG_TRST 183 Ground GND 184 JTAG enable boundary scan DEBUG**
DEBUG=0: JTAG interface works for boundary scan. DEBUG=1:
debugging. JTAG interface works for ARM
* Most JTAG adapters do not use the Return Test Clock in which case it can be used for other purposes. E.g. on the APX4 reference design this pin is used for Factory Reset button.
** DEBUG pin is pulled down inside CPU. Leave unconnected for ordinary boundary scan. Table 49: JTAG pins Bluegiga Technologies Oy Page 37 of 52 In case ARM debugging is needed the board must be powered on in JTAG mode (Wait JTAG connection mode), i. e. LCD_D1 (pin 118) must be high. Bluegiga Technologies Oy Page 38 of 52 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Vin Voltage on ordinary I/O 3V3 current drain*
Permissible ambient temperature
(Commercial version) Min Max Unit
-0.3
-0.3 0 7.0 3.63 200 70 V V mA C C C Permissible ambient temperature
-40 85
(Industrial version) Storage temperature
-40 85
*Pins 9, 10, 11, 12 are 3.3V outputs intended for 3.3V low power devices. Table 50: Absolute Maximum ratings Stresses beyond those listed in Table 50 may cause permanent damage to the device. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 50 gives stress ratings onlyfunctional operation of the device is not implied beyond the conditions indicated in Table 51. 7.2 Recommended Operating Conditions Parameter Vin Voltage on ordinary I/O Board temperature (Industrial version) Ambient temperature with high Wi-Fi use
(Industrial version) Min Max Unit 4.75 5.25 3.1
-40
-40 3.4 85 60 V V C C Table 51: Recommended Operating Conditions Bluegiga Technologies Oy Page 39 of 52 7.3 Power Consumption Condition During Boot Idle
(Linux booted, but no active processes) Wi-Fi transmitting Min 1.0 0.8 1.7 Typ 1.2 0.9 1.8 Max Unit 1.3 1.0 1.9 W W W Table 52: Power consumption (no power saving enabled) Bluegiga Technologies Oy Page 40 of 52 8 RF Characteristics Channels Frequency Channels Frequency min 1 2412 max 13
(1-11 when used in USA) 2472 (2462) MHz Table 53: Supported frequencies for Wi-Fi transceiver min 0 2402 max 78 2480 MHz Table 54: Supported frequencies for Bluetooth transceiver 802.11b 802.11g Standard Supported bit rates 1, 2, 5.5, 11Mbps 6, 9, 12, 18, 24, 36, 48, 54Mbps 802.11n, HT, 20MHz, 800ns 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps 802.11n, HT, 20MHz, 400ns 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65, 72.2Mbps Table 55: Supported modulations for Wi-Fi transceiver Accuracy min
-20 max
+20 ppm For all environmental conditions Table 56: Carrier frequency accuracy for both WiFi and Bluetooth Bluegiga Technologies Oy Page 41 of 52 802.11b Typ 802.11g Typ 802.11n short GI Typ 802.11n long GI Typ 1 Mbps
-97 dBm 6 Mbps
-92 dBm 6.5 Mbps
-91 dBm 7.2 Mbps
-92 dBm 2 Mbps
-95 dBm 9 Mbps
-91 dBm 13 Mbps
-87 dBm 14.4 Mbps
-90 dBm 5.5 Mbps
-93 dBm 12 Mbps
-89 dBm 19.5 Mbps
-85 dBm 21.7 Mbps
-87 dBm 11 Mbps
-89 dBm 18 Mbps
-87 dBm 26 Mbps
-82 dBm 28.9 Mbps
-84 dBm 24 Mbps
-84 dBm 39 Mbps
-78 dBm 43.3 Mbps
-80 dBm 36 Mbps
-80 dBm 52 Mbps
-74 dBm 57.8 Mbps
-75 dBm 48 Mbps
-75 dBm 58.5 Mbps
-71 dBm 65 Mbps
-72 dBm 54 Mbps
-73 dBm 65 Mbps
-68 dBm 72.2 Mbps
-69 dBm Table 57: Wi-Fi receiver sensitivity (at external antenna connector) Modulation type DH1 DH3 DH5 2-DH1 2-DH3 2-DH5 3-DH1 3-DH3 3-DH5 Typ
-89
-89
-89
-92
-92
-92
-86
-85
-85 dBm dBm dBm dBm dBm dBm dBm dBm dBm Table 58: Bluetooth receiver sensitivity (at external antenna connector) Modulation type Wi-Fi Bluetooth/Bluetooth LE Min
+14
+5.5 Typ
+15
+8.1 Max
+15.6 dBm
+9 dBm Table 59: Transmitter output power at maximum setting Bluegiga Technologies Oy Page 42 of 52 9 Physical Dimensions Figure 5: Physical dimensions Bluegiga Technologies Oy Page 43 of 52 10 Attachment to motherboard In order to ease assembly of the APx4 module, it has slightly oval attachment holes. The size of the hole is
~2.2x3.0mm. This makes it possible to attach a screw and nut to the motherboard before inserting the module. Parameter Size Diameter M2 Note Length
<= 10mm, 8mm recommenced Length excluding head Head diameter
<= 3.8mm Material Steel or similar
*Do not use plastic material Parameter Size Size M2 Table 60: Screw size Note Material Steel or similar
*Do not use plastic material
*Use metal screws and nuts that connect to ground, as that improves the function of the APx4 integrated antenna. Nylon/plastic screws/nuts may be used only if the motherboards locking clips are grounded. Metal screws and nuts will also improve the heat conductivity compared to nylon/plastic. Table 61: Nut size For automatic assembly Phillips, Pozi or Torx head is recommended. A suitable screw is Bossards PN 1151495 with following features:
BN 380 - ISO 7048 Cross recessed cheese head screw Phillips H ISO 7048 SN 213307 Bluegiga Technologies Oy Page 44 of 52 11 Layout Guidelines Layout is very important for proper antenna operation when using the integrated antenna. 11.1 Internal antenna: Optimal module placement Key points to remember are APx4 should be placed so that the antenna faces away from large GND planes. Typically the best placement is along one of the motherboard edges. Antenna facing out from board Antenna preferably in corner or placed outside the motherboard edge Important: The motherboards locking clips must be attached to GND. Optionally attach APx4 to the motherboard with metal screws and nuts as described in this document Either:
o Create a board cutout under the entire antenna part or o Place the module so that the antenna is outside the board edge We recommend issuing the motherboard design to Bluegiga for review in good time before ordering the PCBs. Please allow for several days for such a review. Figure 6: Example placement w/motherboard cut-out Figure 7: Example placement, antenna outside motherboard Important: The motherboards locking clips must be attached to GND. 11.2 External antenna In case external antenna is used the RF output can be taken directly from the U.FL connector of the module. In this case internal antenna placement can be ignored. See chapter 12.6 for approved antennas. 11.3 Thermal Considerations APx4 will heat up to some extent during use, especially due to Wi-Fi power consumption during high-
throughput transmissions. APx4 can be attached to the motherboard with metal bolts to allow some heat transfer to the application board ground plane. 11.4 EMC Considerations for Motherboard Unwanted electromagnetic radiation may arise from a combination of APx4 and a motherboard if not carefully designed. Bluegiga Technologies Oy Page 45 of 52 The number of layers required depends on the application. The simplest application with no high speed signals connected, 2 layers might be enough, but with a high number of the APx4 signals in use with high clock speeds, 6 layers is recommended, with solid power and ground planes. Place the peripherals (connectors etc.) as close as possible to APX4. One example is USB and Ethernet. Make the lines as short as possible. USB lines: Use 45 ohms single-line (90 ohms differential) impedance. Route the lines as differential pairs Ethernet lines: Use 50 ohms single-line (100 ohms differential) impedance. Route the lines as differential pairs. Make sure that Ethernet Tx and Rx lines are well separated in order to minimize cross talk. If there is excessive cross talk the PHY may receive its own packets. Be careful with clocks, e.g. SAIF0_MCLK. Do not route them longer than absolutely necessary. Place the destination components as close as possible to the APx4. If clock traces are routed e.g. across the board they easily cause radiation which may exceed allowed limits. The power supply should be designed for 5V and at least 500mA continuous current. We recommend issuing the motherboard design to Bluegiga for review in good time before ordering the PCBs. Please allow for several days for such a review. Bluegiga Technologies Oy Page 46 of 52 12 Certifications APx4 is compliant to the following specifications:
12.1 CE TBD 12.2 FCC This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and
(2) this device must accept any interference received, including interference that may cause undesired operation. FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This transmitter is considered as mobile device and should not be used closer than 20 cm from a human body. To allow portable use in a known host class 2 permissive change is required. Please contact support@bluegiga.com for detailed information. OEM Responsibilities to comply with FCC Regulations The APx4 Module has been certified for integration into products only by OEM integrators under the following conditions:
The antenna(s) must be installed such that a minimum separation distance of 25mm is maintained between the radiator (antenna) and all persons at all times. The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter. As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions cannot be met (for certain configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. End Product Labeling The APx4 Module is labeled with its own FCC ID. If the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case, the final end product must be labeled in a visible area with the following:
Contains Transmitter Module FCC ID: QOQAPX4 or Contains FCC ID: QOQAPX4 Bluegiga Technologies Oy Page 47 of 52 The OEM of the APx4 Module must only use the approved antenna(s) described in Table 62 External Antenna Parameters, which have been certified with this module. The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change RF related parameters in the user manual of the end product. 12.3 IC This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. If detachable antennas are used:
This radio transmitter (identify the device by certification number, or model number if Category II) has been approved by Industry Canada to operate with the antenna types listed below with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. See Table 62 External Antenna Parameters for the approved antennas. OEM Responsibilities to comply with Industry Canada Regulations The APx4 Module has been certified for integration into products only by OEM integrators under the following conditions:
The antenna(s) must be installed such that a minimum separation distance of 20cm is maintained between the radiator (antenna) and all persons at all times. The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter. As long as the two conditions above are met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions cannot be met (for certain configurations or co-location with another transmitter), then the Industry Canada authorization is no longer considered valid and the IC Certification Number cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Industry Canada authorization. End Product Labeling The APx4 Module is labeled with its own IC Certification Number. If the IC Certification Number are not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case, the final end product must be labeled in a visible area with the following:
Contains Transmitter Module IC: 5123A-BGTAPX4 or Contains IC: 5123A-BGTAPX4 Bluegiga Technologies Oy Page 48 of 52 The OEM of the APx4 Module must only use the approved antenna(s) described in Table 62 External Antenna Parameters, which have been certified with this module. The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change RF related parameters in the user manual of the end product. To comply with Industry Canada RF radiation exposure limits for general population, the antenna(s) used for this transmitter must be installed such that a minimum separation distance of 20cm is maintained between the radiator (antenna) and all persons at all times and must not be co-located or operating in conjunction with any other antenna or transmitter. 12.4 IC Dclaration de conformit IC :
Ce matriel respecte les standards RSS exempt de licence dIndustrie Canada. Son utilisation est soumise aux deux conditions suivantes :
(1) lappareil ne doit causer aucune interfrence, et
(2) lappareil doit accepter toute interfrence, quelle quelle soit, y compris les interfrences susceptibles dentraner un fonctionnement non requis de lappareil. Selon la rglementation dIndustrie Canada, ce radio-transmetteur ne peut utiliser quun seul type dantenne et ne doit pas dpasser la limite de gain autorise par Industrie Canada pour les transmetteurs. Afin de rduire les interfrences potentielles avec dautres utilisateurs, le type dantenne et son gain devront tre dfinis de telle faon que la puissance isotrope rayonnante quivalente (EIRP) soit juste suffisante pour permettre une bonne communication. Lors de lutilisation dantennes amovibles :
Ce radio-transmetteur (identifi par un numro certifi ou un numro de modle dans le cas de la catgorie II) a t approuv par Industrie Canada pour fonctionner avec les antennes rfrences ci-dessous dans la limite de gain acceptable et limpdance requise pour chaque type dantenne cit. Les antennes non rfrences possdant un gain suprieur au gain maximum autoris pour le type dantenne auquel elles appartiennent sont strictement interdites dutilisation avec ce matriel. Veuillez vous rfrer au Table 62 External Antenna Parameters, concernant les antennes approuves pour les APx4. Les responsabilits de lintgrateur afin de satisfaire aux rglementations dIndustrie Canada :
Les modules APx4 ont t certifis pour entrer dans la fabrication de produits exclusivement raliss par des intgrateurs dans les conditions suivantes :
Bluegiga Technologies Oy Page 49 of 52 Lantenne (ou les antennes) doit tre installe de faon maintenir tout instant une distance minimum de 20cm entre la source de radiation (lantenne) et toute personne physique. Le module transmetteur ne doit pas tre install ou utilis en concomitance avec une autre antenne ou un autre transmetteur. Tant que ces deux conditions sont runies, il nest pas ncessaire de procder des tests supplmentaires sur le transmetteur. Cependant, lintgrateur est responsable des tests effectus sur le produit final afin de se mettre en conformit avec dventuelles exigences complmentaires lorsque le module est install (exemple :
missions provenant dappareils numriques, exigences vis--vis de priphriques informatiques, etc.) ;
IMPORTANT : Dans le cas o ces conditions ne peuvent tre satisfaites (pour certaines configurations ou installation avec un autre transmetteur), les autorisations fournies par Industrie Canada ne sont plus valables et les numros didentification de certification dIndustrie Canada ne peuvent servir pour le produit final. Dans ces circonstances, il incombera lintgrateur de faire rvaluer le produit final (comprenant le transmetteur) et dobtenir une autorisation spare dIndustrie Canada. Etiquetage du produit final Chaque module APx4 possde son propre numro de certification IC. Si le numro de certification IC ne sont pas visibles lorsquun module est install lintrieur dun autre appareil, alors lappareil en question devra lui aussi prsenter une tiquette faisant rfrence au module inclus. Dans ce cas, le produit final doit comporter une tiquette place de faon visible affichant les mentions suivantes :
Contient un module transmetteur certifi IC 5123A-BGTAPX4 ou Inclut la certification IC 5123A-BGTAPX4 Lintgrateur du module APx4 ne doit utiliser que les antennes rpertories dans le tableau 25 certifies pour ce module. Lintgrateur est tenu de ne fournir aucune information lutilisateur final autorisant ce dernier installer ou retirer le module RF, ou bien changer les paramtres RF du module, dans le manuel dutilisation du produit final. Afin de se conformer aux limites de radiation imposes par Industry Canada, lantenne (ou les antennes) utilise pour ce transmetteur doit tre installe de telle sorte maintenir une distance minimum de 20cm tout instant entre la source de radiation (lantenne) et les personnes physiques. En outre, cette antenne ne devra en aucun cas tre installe ou utilise en concomitance avec une autre antenne ou un autre transmetteur. Bluegiga Technologies Oy Page 50 of 52 12.5 MIC, formerly TELEC TBD 12.6 Qualified Antenna Types for APx4-E This device has been designed to operate with a standard 2.14 dBi dipole antenna. Any antenna of a different type or with a gain higher than 2.14 dBi is strictly prohibited for use with this device. Using an antenna of a different type or gain more than 2.14 dBi will require additional testing for FCC, CE and IC. Please contact support@bluegiga.com for more information. The required antenna impedance is 50 ohms. Qualified Antenna Types for APX4-E Antenna Type Maximum Gain Dipole 2.14 dBi Table 62 External Antenna Parameters To reduce potential radio interference to other users, the antenna type and its gain should be chosen so that the equivalent isotropic radiated power (e.i.r.p.) is not more than that permitted for successful communication. Bluegiga Technologies Oy Page 51 of 52 13 Contact Information Inquiries/ Support: www.bluegiga.com Head office, Finland Phone: +358-9-4355 060 Fax: +358-9-4355 0660 Bluegiga Technologies Oy Sinikalliontie 5A, 5th floor 02630 Espoo, FINLAND USA office Phone: +1 770 291 2181 Fax: +1 770 291 2183 Bluegiga Technologies, Inc. 3235 Satellite Boulevard, Building 400, Suite 300, Duluth, GA, 30096, USA Hong Kong office Phone: +852 3972 2186 Bluegiga Technologies Ltd. Unit 10-18, 32/F, Tower 1, Millennium City 1, 388 Kwun Tong Road, Kwun Tong, Kowloon, Hong Kong Bluegiga Technologies Oy Page 52 of 52
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2013-07-24 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Original Equipment |
2 | 2412 ~ 2462 | DTS - Digital Transmission System |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 | Effective |
2013-07-24
|
||||
1 2 | Applicant's complete, legal business name |
Silicon Laboratories Finland Oy
|
||||
1 2 | FCC Registration Number (FRN) |
0007782659
|
||||
1 2 | Physical Address |
Alberga Business Park, Bertel Jungin aukio 3
|
||||
1 2 |
Espoo, N/A 02600
|
|||||
1 2 |
Finland
|
|||||
app s | TCB Information | |||||
1 2 | TCB Application Email Address |
h******@acbcert.com
|
||||
1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 | Grantee Code |
QOQ
|
||||
1 2 | Equipment Product Code |
APX4
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 | Name |
P******** R****
|
||||
1 2 | Title |
Staff HW Engineer
|
||||
1 2 | Telephone Number |
+3589********
|
||||
1 2 | Fax Number |
+3589********
|
||||
1 2 |
p******@silabs.com
|
|||||
app s | Technical Contact | |||||
1 2 | Firm Name |
Bluegiga Technologies Inc.
|
||||
1 2 | Name |
P****** R******
|
||||
1 2 | Physical Address |
Sinikalliontie 5A
|
||||
1 2 |
Espoo, 02630
|
|||||
1 2 |
Finland
|
|||||
1 2 | Telephone Number |
358 4********
|
||||
1 2 |
p******@bluegiga.com
|
|||||
app s | Non Technical Contact | |||||
1 2 | Firm Name |
Bluegiga Technologies Inc.
|
||||
1 2 | Name |
P****** R******
|
||||
1 2 | Physical Address |
Sinikalliontie 5A
|
||||
1 2 |
Espoo, 02630
|
|||||
1 2 |
Espo, 02630
|
|||||
1 2 |
Finland
|
|||||
1 2 | Telephone Number |
358 4********
|
||||
1 2 |
p******@bluegiga.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
1 2 | DTS - Digital Transmission System | |||||
1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Wireless System-on-Module | ||||
1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 | Modular Equipment Type | Single Modular Approval | ||||
1 2 | Purpose / Application is for | Original Equipment | ||||
1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 | Grant Comments | Power Output listed is conducted. Single Modular Approval. This device is granted for use in mixed mobile and portable configurations in which the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 2.5 cm from all persons and not be co-located with any other transmitters except in accordance with FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. The Grantee is responsible for providing the documentation required for modular use. The responsibility for the use of this module, in all configurations utilized or contemplated, remains with the Grantee. | ||||
1 2 | Power output listed is conducted. Single Modular Approval. This device is granted for use in mixed mobile and portable configurations in which the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 2.5 cm from all persons and not be co-located with any other transmitters except in accordance with FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. The Grantee is responsible for providing the documentation required for modular use. The responsibility for the use of this module, in all configurations utilized or contemplated, remains with the Grantee. | |||||
1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 | Firm Name |
SGS Fimko Ltd
|
||||
1 2 | Name |
J**** M********
|
||||
1 2 | Telephone Number |
35896********
|
||||
1 2 | Fax Number |
35896********
|
||||
1 2 |
j******@sgs.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0075300 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | CC | 2412 | 2462 | 0.0339 | |||||||||||||||||||||||||||||||||||
2 | 2 | 15C | CC | 2402 | 2480 | 0.0065 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC