TIS-03 Tire Pressure Monitoring System User Manual

 

Functional description TIS-03 1 of 4 1. SYSTEM OVERVIEW The tire pressure monitoring system (referred as TG for Tire Guard) consists of the following units:

- Tire guard wheel unit type TIS-03 which includes an integrated pressure, temperature and acceleration sensor and a RF transmitter.

- LF receiver unit which includes a LF receiver (not described in this document) The TG monitors a vehicle's tire pressure while driving or stationary. An electronic unit (wheel unit) inside each tire, mounted to the valve stem, periodically measures the actual tire pressure. By means of RF communication, this pressure information is transmitted to the RF transmitter. 2. TECHNICAL DESCRIPTION Carrier frequency:

Number of channels:

Type of modulation:

Baud rate:

Rated Output Power:

Antenna:

Voltage supply range :

433.92 MHz 1 Frequency Shift Keying (FSK) 9600bps

< 10mW Internal 2.1 up to 3.2V 3. TYPICAL USAGE PATTERN 3.1 AVERAGE FACTOR CALCULATION (Standard 47 CFR Part 15C (periodic intentional transmitter)) Maximum transmitting duration in whatever 100ms windows: 10.31ms

Averaging factor = 20xlog(10.31/100)=-19.73dB Note : The time between inter frames is always higher than the 100ms FCC window. ANT E NN A C rystal:2 6 M Hz 4. BLOCK DIAGRAM The block diagram below shows the main electronic units of the wheel unit:

Sensor Block Diagram R F CIRC UIT

(T un n in g C o m po n en ts) F X TH 87 0 x5

(P re ssure , te m pe ra tu re, Le a rnin g LF co il

(1 axe C o il @

L ITHIUM B ATT ERY 4 3 3.92 M H z o r 3 1 5M H z 3 V C R 20 5 0H R a ccele ratio n se nso r, co ntro ller & R F T ran sm itte r) 1 25 K H z) 2 of 4 IC Block Diagram: FXTH870x5 The FXTH870x5 contains:

and RF transmitter (MCU) Optional ranges on pressure transducers Z-axis acceleration transducer Microcontroller with accelerometer and pressure sensor interfaces, The MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers connect to the MCU using custom analog interfaces and inter-chip bonding wires. 5. PICTURE 3 of 4 6. LABEL 1.1. USA Continental TIS-03 FCC ID: KR5TIS-03 This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 1.2. CANADA Continental TIS-03 IC: 7812D-TIS03 Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 4 of 4 Freescale Semiconductor Data Sheet: Advance Information An Energy-Efficient Solution by Freescale Document Number: FXTH870x6 Rev. 1.5, 02/2015 FXTH870x6 Tire Pressure Monitor Sensor The FXTH870x6 family is comprised of the following functions all within the same package. Features Pressure sensor with one of two calibrated pressure ranges 100 - 450 kPa 100 - 900 kPa Temperature sensor Optional XZ- or Z-axis accelerometer with adjustable offset option Voltage reference measured by ADC10 Six-channel, 10-bit analog-to-digital converter (ADC10) with two external I/O inputs 8-bit MCU S08 Core with SIM and interrupt 512 RAM 8K FLASH (in addition to 8K providing factory firmware and trim data) 64-byte, low-power, parameter registers Dedicated state machines to sequence routine measurement and transmission processes for reduced power consumption Internal 315-/434-MHz RF transmitter External crystal oscillator PLL-based output with fractional-n divider OOK and FSK modulation capability Programmable data rate generator Manchester, Bi-Phase or NRZ data encoding 256-bit RF data buffer variable length interrupt Direct access to RF transmitter from MCU for unique formats Low power consumption (less than 8 mA at 434 MHz, 5 dBM at 3.0 V, 25 C) Differential input LF detector/decoder on independent signal pins Seven multipurpose GPIO pins FXTH870x6 Top and bottom view 24-Pin, 1-hole lid 7 x 7 QFN Top view ID Feature on top lid 0 B T P 4 2

/

C N 3 2

/

C N 2 2

/

C N 1 2

/

C N 0 2

/

C N 9 1 PTB1 PTA2 PTA1 PTA0 RESET VSS 1 2 3 4 5 6 18 PTA3 17 LFA 16 LFB 15 BKGD/PTA4 14 X0 13 X1 7 D D V 8 9 A D D V A S S V 0 1 S S V F R 1 1 F R 2 1 G E R V Pin connections Four pins can be connected to optional internal pullups/pulldowns and STOP4 wakeup interrupt Two of seven pins can be connected to a channel on the ADC10 Two of seven pins can be connected to a channel on the TPM1 Real-Time Interrupt driven by LFO with interrupt intervals of 8, 16, 32, 64, 128, 256, 512 or 1024 ms Low-power, wakeup timer and periodic reset driven by LFO Watchdog timeout with selectable times and clock sources Two-channel general purpose timer/PWM module (TPM1) This document contains information on a new product. Specifications and information herein are subject to change without notice. 2014-2015 Freescale Semiconductor, Inc. All rights reserved. Internal oscillators MCU bus clock of 0.5, 1, 2 and 4 MHz (1, 2, 4 and 8 MHz HFO) Low frequency, low power time clock (LFO) with 1 ms period Medium frequency, controller clock (MFO) of 8 sec period Low-voltage detection Normal temperature restart in hardware (over- or under-temperature detected by software) Part number FXTH8705026T1 FXTH8705116T1 FXTH8709026T1 FXTH8709116T1 FXTH8709126T1 ORDERING INFORMATION Accelerometer axis Package Z XZ Z XZ XZ Ext. Range 2264 (7 x 7, 1-hole lid) 2264 (7 x 7, 1-hole lid) 2264 (7 x 7, 1-hole lid) 2264 (7 x 7, 1-hole lid) 2264 (7 x 7, 1-hole lid) Range 100-450 kPa 100-450 kPa 100-900 kPa 100-900 kPa 100-900 kPa FXTH8709226T1 XZ 2264 (7 x 7, 1-hole lid) 100-900 kPa Code1

$08

$0C

$18

$1C

$1E Code1

$1C Code0 Rel11 Related Documentation The FXTH870x6 device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents:

1. Go to the Freescale homepage at:

http://www.freescale.com/

2. In the Keyword search box at the top of the page, enter the device number FXTH870x6. Sensors Freescale Semiconductor, Inc. FXTH870x6 2 2 Contents 1 General Information . 6 1.1 Overall Block Diagram . 6 1.2 Multi-Chip Interface . 6 1.3 System Clock Distribution. 6 1.4 Reference Documents . 8 Pins and Connections . 9 2.1 Package Pinout . 9 2.2 Recommended Application. 9 Signal Properties . 10 2.3 3 Modes of Operation . 13 Features . 13 3.1 3.2 RUN Mode . 13 3.3 WAIT Mode. 13 ACTIVE BACKGROUND Mode . 13 3.4 STOP Modes . 14 3.5 4 Memory . 17 4.1 MCU Memory Map . 17 4.2 Reset and Interrupt Vectors . 17 4.3 MCU Register Addresses and Bit Assignments . 18 4.4 High Address Registers . 22 4.5 MCU Parameter Registers . 22 4.6 MCU RAM . 22 FLASH . 23 4.7 Security. 28 4.8 4.9 FLASH Registers and Control Bits . 29 5 Reset, Interrupts and System Configuration . 33 5.1 Features . 33 5.2 MCU Reset . 33 5.3 Computer Operating Properly (COP) Watchdog . 33 5.4 SIM Test Register (SIMTST) . 34 Interrupts . 35 5.5 Low-Voltage Detect (LVD) System. 38 5.6 System Clock Control . 38 5.7 5.8 Keyboard Interrupts . 38 5.9 Real Time Interrupt. 39 5.10 Temperature Sensor and Restart System . 40 5.11 Reset, Interrupt and System Control Registers And Bits . 40 5.12 System STOP Exit Status Register (SIMSES) . 45 6 General Purpose I/O . 46 6.1 Unused Pin Configuration. 48 6.2 Pin Behavior in STOP Modes. 48 6.3 General Purpose I/O Registers . 48 6.4 Port A Registers . 48 Port B Registers . 49 6.5 7 Keyboard Interrupt . 51 7.1 Features . 51 7.2 Modes of Operation . 51 7.3 Block Diagram . 51 7.4 External Signal Description . 51 7.5 Register Definitions . 52 Functional Description . 53 7.6 8 Central Processing Unit. 54 8.1 Introduction. 54 8.2 Features . 54 8.3 Programmers Model and CPU Registers . 55 8.4 Addressing Modes . 57 8.5 Special Operations . 58 8.6 HCS08 Instruction Set Summary . 59 Sensors Freescale Semiconductor, Inc. FXTH870x6 3 9 Timer Pulse-Width Module. 70 Features . 70 9.1 TPM1 Configuration Information. 70 9.2 9.3 External Signal Description . 71 9.4 Register Definition . 72 Functional Description . 77 9.5 TPM1 Interrupts . 80 9.6 10 .Other MCU Resources. 82 10.1 Pressure Measurement . 82 10.2 Temperature Measurements . 83 10.3 Voltage Measurements. 83 10.4 Optional Acceleration Measurements. 83 10.5 Optional Battery Condition Check . 83 10.6 Measurement Firmware . 85 10.7 Thermal Shutdown . 87 11 Periodic Wakeup Timer . 89 11.1 Block Diagram . 89 11.2 Wakeup Divider Register - PWUDIV . 90 11.3 PWU Control/Status Register 0 - PWUCS0 . 90 11.4 PWU Control/Status Register 1 - PWUCS1 . 91 11.5 PWU Wakeup Status Register - PWUS . 92 11.6 Functional Modes . 92 12 LF Receiver . 93 12.1 Features . 94 12.2 Modes of Operation . 94 12.3 Power Management . 94 12.4 Input Amplifier. 95 12.5 LFR Data Mode States . 95 12.6 Carrier Detect . 95 12.7 Auto-Zero Sequence . 97 12.8 Data Recovery . 97 12.9 Data Clock Recovery and Synchronization . 97 12.10 Manchester Decode . 97 12.11 Duty-Cycle For Data Mode . 98 12.12 Input Signal Envelope. 99 12.13 Telegram Verification . 100 12.14 Error Detection and Handling . 101 12.15 Continuous ON Mode . 101 12.16 Initialization Information . 101 12.17 LFR Register Definition . 102 13 RF Module . 113 13.1 RF Data Modes . 113 13.2 RF Output Buffer Data Frame . 114 13.3 Transmission Randomization . 116 13.4 RFM in STOP1 Mode . 119 13.5 Data Encoding . 119 13.6 RF Output Stage. 121 13.7 RF Interrupt . 122 13.8 Datagram Transmission Times. 122 13.9 RFM Registers . 123 13.10 RFM Control Register 1 - RFCR1. 123 13.11 RFM Control Register 2 - RFCR2. 124 13.12 RFM Control Register 3 - RFCR3. 127 13.13 RFM Control Register 4 - RFCR4. 128 13.14 RFM Control Register 5 - RFCR5. 128 13.15 RFM Control Register 6 - RFCR6. 129 13.16 RFM Control Register 7 - RFCR7. 129 13.17 PLL Control Registers A- PLLCR[1:0], RPAGE = 0 . 130 13.18 PLL Control Registers B- PLLCR[3:2], RPAGE = 0 . 131 13.19 EPR Register - EPR (RPAGE = 1) . 132 13.20 RF DATA Registers - RFD[31:0] . 133 13.21 VCO Calibration Machine . 134 FXTH870x6 4 Sensors Freescale Semiconductor, Inc. 14 Firmware . 135 14.1 Software Jump Table . 135 14.2 Function Documentation. 135 14.3 Memory Resource Usage. 140 15 Development Support . 141 15.1 Introduction. 141 15.2 Background Debug Controller (BDC) . 141 15.3 Register Definition . 146 16 Battery Charge Consumption Modeling. 149 16.1 Standby Current . 149 16.2 Measurement Events . 149 16.3 Transmission Events . 149 16.4 Total Consumption . 149 17 Electrical Specifications . 150 17.1 Maximum Ratings. 150 17.2 Operating Range . 150 17.3 Electrical Characteristics . 151 17.4 Power Consumption (MCU) . 152 17.5 Control Timing . 153 17.6 Voltage Measurement Characteristics . 154 17.7 Temperature Measurement Characteristics . 155 17.8 Pressure Measurement Characteristic (100 to 450 kPa ranges) . 156 17.9 Pressure Measurement Characteristic (100 to 900 kPa Ranges) . 157 17.10 Optional Acceleration Sensor Characteristics . 158 17.11 LFR Sensitivity . 161 17.12 LFR Characteristics . 162 17.13 LFR Power Consumption . 162 17.14 RF Output Stage. 164 17.15 Power Consumption RF Transmissions . 166 18 Mechanical Specifications. 168 18.1 Maximum Ratings. 168 18.2 Media Compatibility . 168 18.3 Mounting Recommendations . 168 19 Package Outline . 170 20 Revision History . 174 Sensors Freescale Semiconductor, Inc. FXTH870x6 5 1 General Information Overall Block Diagram 1.1 The block diagram of the FXTH870x6 is shown in Figure 1. This diagram covers all the main blocks mentioned above and their main signal interactions. Power management controls and bus control signals are not shown in this block diagram for clarity. Multi-Chip Interface 1.2 The FXTH870x6 contains two to three devices using the best process technology for each. Microcontroller with accelerometer and pressure sensor interfaces, and RF transmitter (MCU) As shown in Figure 1 the MCU interfaces to the RF transmitter using a standard memory mapped registers. The transducers connect to the MCU using custom analog interfaces and inter-chip bonding wires. Optional ranges on pressure transducers Optional XZ- or Z-axis acceleration transducer System Clock Distribution 1.3 The various clock sources and their distribution are shown in Figure 2. All clock sources except the low frequency oscillator, LFO, can be turned off by software control in order to conserve power. FXTH870x6 6 Sensors Freescale Semiconductor, Inc. SMI MCU T N E M E R U S A E M R O S N E S E C A F R E T N I

) I M S

(

TRANSDUCERS P PRESS SENSOR XZ ACCEL

(OPTION) Z ACCEL

(OPTION) XZ Z TEMP TEMP SENSOR VTP BANDGAP REF V0 VSENS OSC ADC10 10-BIT 6-CHAN MFO 8 Sec MFO V1 VREG V2 AVDD VOLT REG RFVDD XTAL OSC VCO/PLL FRACTL DIVIDER RF AMP RFM VREG XI XO RF RVSS DX BIT RATE GEN RF LVD 256-BIT DATA BUFFER DATA ENCODE R E L L O R T N O C F R LFO PWU TIMER RTI TIMER MCU CORE S08 VDD AVDD 64 Byte PARAMETER REGISTER LFO 1 ms LVD TEMP RESTART 1, 2, 4 or 8 HFO MHz RAM MEMORY 512 8K USER FLASH MEMORY 8K FIRMWARE MEMORY TPM1 TIMER/PWM 2-CHAN LF RECVR

(LFR) LFI KEY BOARD WAKEUP GP I/O KBI Figure 1. FXTH870x6 Overall Block Diagram Sensors Freescale Semiconductor, Inc. BKGD/

PTA4 VDD AVDD AVSS VSS RESET LFA LFB PTA0 PTA1 PTA2 PTA3 PTB0 PTB1 FXTH870x6 7 RTICLKS SYSTEM CONTROL LOGIC ADC10 CLOCK MCU LFO OSC 1 mS PERIOD BUSCLKS[1:0]

HFO OSC 1, 2, 4, and 8 MHz fOSC CPU BDC PWU fMFO RTI fBUS 2 COPCLKS WATCH DOG fLFO (1 kHz) TCLKDIV DX (500 kHz) 8 XTL OSC 26 MHz XI XO fXCO BIT RATE GEN RF STATE MACHINE PLL VCO DATA BUFFER RF OUT ADC10 PAR REG RAM FLASH ADCCLK ADC10 CLSA, CLKSB TPM1 LFR LFRO OSCILL CH0 CH1 fLFO (1 kHz) fMFO LFOSEL MFO OSC 8 Sec 4 kbps LF

(125 kHz) PTA3 RANDOM

(0 - 1 MHz) PTA2 RANDOM

(0 - 1 MHz) SENSOR MEASUREMENT INTERFACE 41.67 kHz Sampling 41.67 kHz Sampling 41.67 kHz Sampling PRESSURE SENSOR X-AXIS SENSOR Z-AXIS SENSOR TRANSDUCERS Figure 2. Clock Distribution Reference Documents 1.4 The FXTH870x6 utilizes the standard product MC9S08 CPU core. The user can obtain further detail on the full capabilities of this core by referring to the HCS08 Family Reference Manual (HCS08RMV1). FXTH870x6 8 Sensors Freescale Semiconductor, Inc. Pins and Connections 2 This section describes the pin layout and general function of each pin. Package Pinout 2.1 The pinout for the FXTH870x6 device QFN package is shown in Figure 3 for the orientation of the pressure port up. The orientation of the internal Z-axis accelerometer is shown in Figure 4. ID Feature on top lid Top View 0 B T P 4 2 C N

/

3 2 C N

/

2 2 C N

/

1 2 C N

/

0 2 C N

/

9 1 PTB1 PTA2 PTA1 PTA0 RESET VSS 1 2 3 4 5 6 7 D D V 8 9 A D D V A S S V 0 1 S S V F R 1 1 F R 2 1 G E R V 18 PTA3 17 LFA 16 LFB 15 BKGD/PTA4 BKGD/PTA4 14 X0 13 X1

-X

+Y

-Y Y-AXIS ORIENTATION

+X X-AXIS ORIENTATION N/C = No Connect: Do not connect PCB pads to signal traces, power/ground or multi-layer via. Figure 3. FXTH870x6 QFN Package Pinout Pressure Port

+Z Z-AXIS ORIENTATION Side View POSITIVE ACCELERATION MOVES MASS IN +Z DIRECTION (VALUE INCREASES)

-Z Figure 4. FXTH870x6 QFN Optional Z-axis Accelerometer Orientation Recommended Application 2.2 Example of a simple OOK/FSK tire pressure monitors using the internal PLL-based RF output stage is shown in Figure 5. Any of the PTA[3:0] pins can also be used as general purpose I/O pins. Any of the PTA[3:0] pins that are not used in the application should be handled as described in Section 6.1. Sensors Freescale Semiconductor, Inc. FXTH870x6 9 2.3 The following sections describe the general function of each pin. Signal Properties R2 and R3, <10 k recommended for highest EMC resistance 3.0 V BATTERY 0.1 F 0.1 F R2 R3 BKGD/PTA4 RESET AVDD VDD L1 and matching network optimized for specific PWB and antenna layout. Recommend 0603 minimum size for L1 and other matching network inductors for maximum efficiency. ANT L1 RF MATCHING NETWORK VSS AVSS LFA LFB PTA0 PTA1 PTA2 PTA3 PTB0 PTB1 LF COIL R1 C1 C1 and R1 optimized for coil used, but recommended RC < 15.3 sec. GENERAL PURPOSE I/O FXTH870xxx RVSS VREG XI XO C4*

C2, C3, C4 optimized for crystal XTAL C2 C3 470 nF C5 The device C4, although drawn here as a capacitor, may be any type of passive component(s) sufficient to block or reduce unwanted external radiated signals from corrupting the crystal oscillator circuit: PCB traces for the LFA

/ LFB, AVDD / VDD, and VSS / AVSS pins and bypass capacitors should be minimized to reduce unwanted external radiated signals from corrupting the power input circuits. Figure 5. FXTH870x6 Example Application VDD and VSS Pins 2.3.1 The digital circuits operate from a single power supply connected to the FXTH870x6 through the VDD and VSS pins. VDD is the positive supply and VSS is the ground. The conductors to the power supply should be connected to the VDD and VSS pins and locally decoupled as shown in Figure 6. Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a star connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6. 2.3.2 The analog circuits operate from a single power supply connected to the FXTH870x6 through the AVDD and AVSS pins. AVDD is the positive supply and AVSS is the ground. The conductors to the power supply should be connected to the AVDD and AVSS pins and locally decoupled as shown in Figure 6. AVDD and AVSS Pins FXTH870x6 10 Sensors Freescale Semiconductor, Inc. Care should be taken to reduce measurement signal noise by separating the VDD, VSS, AVDD, AVSS and RVSS pins using a star connection such that each metal trace does not share any load currents with other external devices as shown in Figure 6. Bypass capacitors closely coupled to the package pins FXTH870xxx and Other Load Currents star connected to battery terminals FXTH870xxx VDD 0.1 F 0.1 F VSS AVDD AVSS RVSS IDD ILOAD Battery to other loads The decoupling devices, although drawn here as 0.1 F capacitors, may be any type of passive component(s) sufficient to block or reduce unwanted external radiated signals from corrupting the power input protection circuits;

application tuning may be required. Figure 6. Recommended Power Supply Connections RF Pin VREG Pin RVSS Pin XO, XI Pins 2.3.3 The internal regulator for the analog circuits requires an external stabilization capacitor to AVSS. 2.3.4 Power in the RF output amplifier is returned to the supply through the RVSS pin. This conductor should be connected to the power supply as shown in Figure 6 using a star connection such that each metal trace does not share any load currents with other supply pins. 2.3.5 The RF pin is the RF energy data supplied by the FXTH870x6 to an external antenna. 2.3.6 The XO and XI pins are for an external crystal to be used by the internal PLL for creating the carrier frequencies and data rates for the RF pin. 2.3.7 The LF[A:B] pins can be used by the LF receiver (LFR) as one differential input channel for sensing low level signals from an external low frequency (LF) coil. The external LF coil should be connected between the LFA and the LFB pins. Signaling into the LFR pins can place the FXTH870x6 into various diagnostic or operational modes. The LFR is comprised of the detector and the decoder. Each LF[A:B] pin will always have an impedance of approximately 500 k to VSS due to the LFR input circuitry. The LFA/LFB pins are used by the LFR when the LFEN control bit is set and are not functional when the LFEN control bit is clear. 2.3.8 The PTA[1:0] pins are general purpose I/O pins. These two pins can be configured as normal bidirectional I/O pins with programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input channels of the A/D converter module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled. User software must configure the general purpose I/O pins so that they do not result in floating inputs as described in Section 6.1. PTA[1:02] map to keyboard Interrupt function bits [1:0]. PTA[1:0] Pins LF[A:B] Pins Sensors Freescale Semiconductor, Inc. FXTH870x6 11 PTA[3:2] Pins BKGD/PTA4 Pin 2.3.9 The PTA[3:2] pins are general purpose I/O pin. These two pins can be configured as normal bidirectional I/O pin with programmable pullup or pulldown devices and/or wakeup interrupt capability; or one or both can be connected to the two input channels of the Timer Pulse Width (TPM1) module. The pulldown devices can only be activated if the wakeup interrupt capability is enabled. User software must configure the general purpose I/O pins so that they do not result in floating inputs as described in Section 6.1. PTA[3:2] map to keyboard Interrupt function bits [3:2]. 2.3.10 The BKGD/PTA4 pin is used to place the FXTH870x6 in the BACKGROUND DEBUG mode (BDM) to evaluate MCU code and to also transfer data to/from the internal memories. If the BKGD/PTA4 pin is held low when the FXTH870x6 comes out of a power-

on reset the device will go into the ACTIVE BACKGROUND DEBUG mode (BDM). The BKGD/PTA4 pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter BDM operation after the device as been soldered into the PWB. If in-circuit BDM is desired the BKGD/PTA4 pin can be left unconnected, but should be connected to VDD through a low impedance resistor (< 10 k) which can be over-driven by an external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event. 2.3.11 The RESET pin is used for test and establishing the BDM condition and providing the programming voltage source to the internal FLASH memory. This pin can also be used to direct to the MCU to the reset vector as described in Section 5.2. The RESET pin has an internal pullup device and can connected to VDD in the application unless there is a need to enter BDM operation after the device as been soldered to the PWB. If in-circuit BDM is desired the RESET pin can be left unconnected; but should be connected to VDD through a low impedance resistor (< 10 k) which can be over-driven by an external signal. This low impedance resistor reduces the possibility of getting into the debug mode in the application due to an EMC event. Activation of the external reset function occurs when the voltage on the RESET pin goes below 0.3 x VDD for at least 100 nsec before rising above 0.7 x VDD as shown in Figure 7. RESET Pin RESET 0.3 VDD

> 100 nsec 0.7 VDD Reset Initiated Figure 7. RESET Pin Timing PTB[1:0] Pins 2.3.12 The PTB[1:0] pins are general purpose I/O pins. These two pins can be configured as nominal bidirectional I/O pins with programmable pullup. User software must configure the general purpose I/O pins so that they do not result in floating inputs as described in Section 6.1 FXTH870x6 12 Sensors Freescale Semiconductor, Inc. Modes of Operation 3 The operating modes of the FXTH870x6 are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.1 Features ACTIVE BACKGROUND DEBUG mode for code development STOP modes:

System clocks stopped STOP1: Power down of most internal circuits, including RAM, for maximum power savings; voltage regulator in standby STOP4: All internal circuits powered and full voltage regulation maintained for fastest recovery RUN Mode 3.2 This is the normal operating mode for the FXTH870x6. This mode is selected when the BKGD/PTA4 pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory following a reset with execution beginning at address specified by the reset pseudo-vector ($DFFE and $DFFF). WAIT Mode 3.3 The WAIT mode is also present like other members of the Freescale S08 family members; but is not normally used by the FXTH870x6 firmware or typical TPMS applications. ACTIVE BACKGROUND Mode 3.4 The ACTIVE BACKGROUND mode functions are managed through the BACKGROUND DEBUG controller (BDC) in the HCS08 core. The BDC provides the means for analyzing MCU operation during software development. ACTIVE BACKGROUND mode is entered in any of four ways:

When the BKGD/PTA4 pin is low at the rising edge of a power up reset When a BACKGROUND command is received through the BKGD/PTA4 pin When a BGND instruction is executed by the CPU When encountering a BDC breakpoint Once in ACTIVE BACKGROUND mode, the CPU is held in a suspended state waiting for serial BACKGROUND commands rather than executing instructions from the users application program. Background commands are of two types:

Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/PTA4 pin while the MCU is in RUN mode; non-intrusive commands can also be executed when the MCU is in the ACTIVE BACKGROUND mode. Non-intrusive commands include:

Memory access commands Memory-access-with-status commands BDC register access commands The BACKGROUND command ACTIVE BACKGROUND commands, which can only be executed while the MCU is in ACTIVE BACKGROUND mode. ACTIVE BACKGROUND commands include commands to:

Read or write CPU registers Trace one user program instruction at a time Leave ACTIVE BACKGROUND mode to return to the users application program (GO) The ACTIVE BACKGROUND mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in RUN mode for the first time. When the FXTH870x6 is shipped from the Freescale factory, the FLASH program memory is erased by default (unless specifically requested otherwise) so there is no program that could be executed in RUN mode until the FLASH memory is initially programmed. The ACTIVE BACKGROUND mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. Sensors Freescale Semiconductor, Inc. FXTH870x6 13 STOP Modes 3.5 One of two stop modes are entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all STOP modes, all internal clocks are halted except for the low frequency 1 kHz oscillator (LFO) which runs continuously whenever power is applied to the VDD and VSS pins. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter any of the STOP modes and an illegal opcode reset is forced. The STOP modes are selected by setting the appropriate bits in SPMSC2. Table 1 summarizes the behavior of the MCU in each of the STOP1 and STOP4 modes. The STOP2 mode found in other Freescale S08 family members is not available; but the STOP3 mode is present like other members of the Freescale S08 family members. 3.5.1 The STOP1 mode provides the lowest possible standby power consumption by causing the internal circuitry of the MCU to be powered down. When the MCU is in STOP1 mode, all internal circuits that are powered from the voltage regulator are turned off. The voltage regulator is in a low-power standby state. STOP1 is exited by asserting either a reset or an interrupt function to the MCU. Entering STOP1 mode automatically asserts LVD. STOP1 cannot be exited until the VDD is greater than VLVDH or VLV/DL rising

(VDD must rise above the LVI re-arm voltage). Upon wakeup from STOP1 mode, the MCU will start up as from a power-on reset (POR) by taking the reset vector. STOP1 Mode If there are any pending interrupts that have yet to be serviced then the device will not go into the STOP1 mode. Be certain that all interrupt flags have been cleared before entry to STOP1 mode. NOTE STOP4 LVD Enabled in STOP Mode 3.5.2 The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the voltage regulator remains active during STOP mode. If the user attempts to enter the STOP1 with the LVD enabled in STOP

(LVDSE = 1), the MCU will enter STOP4 instead. Table 1. STOP Mode Behavior Mode LFO Oscillator, PWU Real-Time Interrupt (RTI)(1) MFO Oscillator(2) HFO Oscillator CPU RAM Parameter Registers FLASH TPM1 2-Chan Timer/PWM Digital I/O Sensor Measurement Interface (SMI) Pressure P-cell Optional Acceleration g-cell Temperature Sensor (in ADC10) Normal Temperature Restart Voltage Reference (in ADC10) LFR Detector(4) LFR Decoder RF Controller, Data Buffer, Encoder RF Transmitter(5) ADC10 FXTH870x6 14 STOP1 STOP4 Always On & Clocking Always On if using LFO as Clock Optionally On Optionally On Off Off Off On Off Off Disabled Off Off Off Off Optionally On Off Periodically On Optionally On Optionally On Optionally On Off Off Standby Standby On Standby Off Standby Optionally On Optionally On Optionally On Optionally On(3) Optionally On Optionally On(3) Periodically On Optionally On Optionally On Optionally On Optionally On(3) Sensors Freescale Semiconductor, Inc. Table 1. STOP Mode Behavior (continued) Mode STOP1 STOP4 Regulator I/O Pins Wakeup Methods 1. RTI can be used in STOP1 or STOP4 if the clock selected is the LFO. To use the HFO as the clock the MCU must be in the RUN mode. 2. MFO oscillator started if the LFR detectors are periodically sampled, the LFR detectors detect an input signal; a pressure or acceleration Interrupts, resets Interrupts, resets States Held Off Hi-Z On reading is in progress or the RF state machine is sending data. 3. Requires internal ADC10 clock to be enabled. 4. Period of sampling set by MCU. 5. RF data buffer may be set up to run while the CPU is in the STOP modes. Active BDM Enabled in STOP Mode MCU On-Chip Peripheral Modules in STOP Modes Specific to the tire pressure monitoring application the parameter registers and the LFO with wakeup timer are powered up at all times whenever voltage is applied to the supply pins. The LFR detector and MFO may be periodically powered up by the LFR decoder. 3.5.3 Entry into the ACTIVE BACKGROUND DEBUG mode from RUN mode is enabled if the ENBDM bit in BDCSCR is set. The BDCSCR register is not memory mapped so it can only be accessed through the BDM interface by use of the BDM commands READ_STATUS and WRITE_CONTROL. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the BACKGROUND DEBUG logic remain active when the MCU enters STOP mode so BACKGROUND DEBUG communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter the STOP1 with ENDBM set, the MCU will instead enter this mode which is STOP4 with system clocks running. Most BACKGROUND commands are not available in STOP mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in STOP mode. The BACKGROUND command can be used to wake the MCU from stop and enter ACTIVE BACKGROUND mode if the ENDBM bit is set. Once in BACKGROUND DEBUG mode, all BACKGROUND commands are available. 3.5.4 When the MCU enters any STOP mode, system clocks to the internal peripheral modules except the wakeup timer and LFR detectors/decoder are stopped. Even in the exception case (ENDBM = 1), where clocks are kept alive to the BACKGROUND debug logic, clocks to the peripheral systems are halted to reduce power consumption. I/O Pins If the MCU is configured to go into STOP1 mode, the I/O pins are forced to their default reset state (Hi-Z) upon entry into stop. This means that the I/O input and output buffers are turned off and the pullup is disconnected. Memory All module interface registers will be reset upon wakeup from STOP1 and the contents of RAM are not preserved. The MCU must be initialized as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the STOP modes. Parameter Registers The 64 bytes of parameter registers are kept active in all modes of operation as long as power is applied to the supply pins. The contents of the parameter registers behave like RAM and are unaffected by any reset. LFO The LFO remains active regardless of any mode of operation. MFO The medium frequency oscillator (MFO) will remain powered up when the MCU enters the STOP mode only when the SMI has been initiated to make a pressure or acceleration measurement; or when the RF transmitters state machine is processing data. HFO The HFO is halted in all STOP modes. PWU The PWU remains active regardless of any mode of operation. Sensors Freescale Semiconductor, Inc. FXTH870x6 15 ADC10 The internal asynchronous ADC10 clock is always used as the conversion clock. The ADC10 can continue operation during STOP4 mode. Conversions can be initiated while the MCU is the STOP4 mode. All ADC10 module registers contain their reset values following exit from STOP1 mode. LFR When the MCU enters STOP mode the detectors in the LFR will remain powered up depending on the states of the bits selecting the periodic sampling. Refer to Section 12 for more details. Bandgap Reference The bandgap reference is enabled whenever the sensor measurement interface requires sensor or voltage measurements. TPM1 When the MCU enters STOP mode, the clock to the TPM1 module stops and the module halts operation. If the MCU is configured to go into STOP1 mode, the TPM1 module will be reset upon wakeup from STOP and must be re-initialized. Voltage Regulator The voltage regulator enters a low-power standby state when the MCU enters any of the STOP modes except STOP4 (LVDSE

= 1 or ENBDM = 1). Temperature Sensor The temperature sensor is powered up on command from the MCU. Temperature Restart When the MCU enters a STOP mode the temperature restart will remain powered up if the TRE bit is set. If the temperature restart level is reached the MCU will restart from the reset vector. 3.5.5 The RFMs external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer, data encoder, and RF output stage will remain powered up in STOP modes during a transmission, or if the SEND bit has been set and DIRECT mode has been enabled. RF Output When the RFM finishes a transmission sequence the external crystal oscillator (XCO), bit rate generator, PLL, VCO, RF data buffer, data encoder, and RF output stage will remain powered up if the SEND bit is set. 3.5.6 The P-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered down. 3.5.7 The g-cell is powered up only during a measurement if scheduled by the sensor measurement interface. Otherwise it is powered down. Optional g-Cell in STOP Modes RFM Module in STOP Modes P-cell in STOP Modes FXTH870x6 16 Sensors Freescale Semiconductor, Inc. Memory 4 The overall memory map of the FXTH870x6 resides on the MCU. MCU Memory Map 4.1 As shown in Figure 8, MCU on-chip memory in the FXTH870x6 consists of parameter registers, RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into four groups:

Direct-page registers ($0000 through $004F) Parameter registers ($0050 through $008F) RAM ($0090 through $028F) High-page registers ($1800 through $182B) DIRECT PAGE REGISTERS PARAMETER REGISTERS RAM 512 BYTES UNIMPLEMENTED 5488 BYTES HIGH PAGE REGISTERS 41964 BYTES USER FLASH 8128 BYTES USER VECTORS FIRMWARE JUMP TABLE FIRMWARE FLASH 8128 BYTES

$0000

$004F

$0050

$008F

$0090

$028F

$0290

$17FF

$1800

$182B

$182C

$BFFF

$C000

$DFBF

$DFC0

$DFFF

$E000

$E03F

$E040

$FFFF Figure 8. FXTH870x6 MCU Memory Map The total programmable FLASH memory map is 16K, but the upper 8K is used for firmware and test software. Upon power up the firmware will initialize the device and redirect all vectors to the user area from $DFC0 through $DFFF. Any calls to the firmware subroutines are accessed through a jump table starting at location $E000 (see Section 14). Reset and Interrupt Vectors 4.2 Table 2 shows address assignments for jump table to the reset and interrupt vectors. The vector names shown in this table are the labels used in the equate file provided by Freescale in the CodeWarrior project file. Table 2. Vector Summary User Vector Addr

$DFE0:DFE1

$DFE2:DFE3

$DFE4:DFE5

$DFE6:DFE7

$DFE8:DFE9

$DFEA:DFEB

$DFEC:DFED Sensors Freescale Semiconductor, Inc. Vector Name Vkbi Vrti Vlfrcvr Vadc1 Vrf Reserved Reserved Module Source KBI Sys Ctrl - RTI LFR ADC10 RFM FXTH870x6 17 Table 2. Vector Summary (continued) User Vector Addr Vector Name Module Source

$DFEE:DFEF

$DFF0:DFF1

$DFF2:DFF3

$DFF4:DFF5

$DFF6:DFF7

$DFF8:DFF9

$DFFA:DFFB

$DFFC:DFFD

$DFFE:DFFF Vsm Vtpm1ovf Vtpm1ch1 Vtpm1ch0 Vwuktmr Vlvd Vswi Vreset SMI TPM1 TPM1 TPM1 PWU Reserved Sys Ctrl - LVD SWI opcode Sys Ctrl - POR, PRF, COP, LVD Temp Restart, Illegal opcode or address MCU Register Addresses and Bit Assignments 4.3 The registers in the FXTH870x6 are divided into these four groups:

Direct-page registers are located in the first 80 locations in the memory map; these are accessible with efficient direct addressing mode instructions. The parameter registers begin at address $0050; these are also accessible with efficient direct addressing mode instructions. High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register locations include:

Three values that are loaded into working registers at reset An 8-byte back door comparison key that optionally allows the user to gain controlled access to secure memory. Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 3 is a summary of all user-accessible direct-page registers and control bits. Those related to the TPMS application and modules are described in detail in this specification. The register names in column two of the following tables are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. Table 3. MCU Direct Page Register Summary Register Name Bit 7 6 5 4 3 2 PTAD[4:0]

1 Bit 0 PTAPE[3:0]

PTADD[3:0]

PTBD[1:0]

PTBPE[1:0]

PTBDD[1:0]

0 0 0 0 KBF KBACK KBIE KBIMOD Sensors Freescale Semiconductor, Inc. Address

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C PTAD PTAPE Reserved PTADD PTBD PTBPE Reserved PTBDD Reserved Reserved Reserved Reserved KBISC FXTH870x6 18 3 2 1 Bit 0 KBIPE[3:0]

KBEDG[3:0]

CLKSA PS2 PS1 PS0 ELS0B ELS0A ELS1B ELS1A 0 0 Bit [15:8]

Bit [7:0]

Bit [15:8]

Bit [7:0]

Bit [15:8]

Bit [7:0]

Bit [15:8]

Bit [7:0]

Table 3. MCU Direct Page Register Summary (continued) 4 5 6 TOF Bit 7 TOIE CH1F CH0F MS1B MS0A MS0B MS1A CH1IE CH0IE CLKSB CPWMS Register Name KBIPE KBIES Reserved TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL TPM1C1SC TPM1C1VH TPM1C1VL Reserved PWUDIV PWUCS0 PWUCS1 PWUS LFR Registers ADSC1 ADSC2 ADRH ADRL ADCVH ADCVL ADCFG ADPCTL1 Address

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

$0020-27

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030-4F RFM Registers

$0050-8F Parameter Reg Note: Shaded bits are recommended to only be controlled by firmware or factory test. WUF PRF PSEL WUFAK PRFAK AIEN ADTRG COCO ADACT ADCO ACFE ADIV[1:0]

ADLSMP ADCFGT ADLPC 0 0 0 0 0 0 0 0 0 WDIV[5:0]

WUT[5:0]

PRST[5:0]

CSTAT[5:0]

LFR Registers, see Table 4 and Table 5 0 ADCH[4:0]

0 0 ADR[11:8]

ADCV[11:8]

MODE[1:0]

ADICLK[1:0]

ADR[7:0]

ADCV[7:0]

ADPC[7:0]

RFM Registers, see Table 6 and Table 7 PARAM[63:0]

0 0 0 Table 4. LFR Register Summary - LPAGE = 0 Address

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027 Register Name LFCTL1 LFCTL2 LFCTL3 LFCTL4 LFS LFDATA LFIDL LFIDH Sensors Freescale Semiconductor, Inc. Bit 7 LFEN 6 5 4 3 2 SRES CARMOD LPAGE IDSEL[1:0]

1 Bit 0 SENS[1:0]

LFSTM[3:0]

SYNC[1:0]

LFONTM[3:0]

LFCDTM[3:0]

LFDO LFDRIE LFDRF TOGMOD LFERIE LFERF LFCDIE LFCDF LFIDIE LFIDF DECEN LFOVF VALEN LFEOMF TIMOUT[1:0]

LPSM LFIAK RXDATA[7:0]

ID[7:0]

ID[15:8]

FXTH870x6 19 Table 5. LFR Register Summary - LPAGE = 1 4 5 6 SRES LPAGE CARMOD Bit 7 LFEN Register Name Address

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027 Note: Shaded bits are recommended to only be controlled by firmware or factory test. LFCTL1 LFCTRLE LFCTRLD LFCTRLC LFCTRLB LFCTRLA Reserved Reserved AVFOF[1:0}

AMPGAIN[1:0]

TESTSEL[3:0]

FINSEL[1:0]

HYST[1:0]

LFCAF LFFAF DEQS 3 2 IDSEL[1:0]

1 Bit 0 SENS[1:0]

TRIMEE AZSC[2:0]

AZDC[1:0]

AZEN LFPOL ONMODE CHK125[1:0]

LOWQ[1:0]

DEQEN LFCPTAZ[2:0]

LFCC[3:0]

Table 6. RFM Register Summary - RPAGE = 0 3 2 1 Bit 0 PWR[4:0]

FNUM[3:0]

LFSR[6:0]

RFFT[5:0]

RFIEN RFLVDEN RCTS RFMRST POL CF CODE[1:0]

MOD CKREF BPS[7:0]

FRM[7:0]

RFBT[7:0]

4 5 6 IFID Bit 7 RFVF RFEF RFIAK BOOST AFREQ[4:0]

BFREQ[4:0]

EOM ISPC SEND DATA Register Name RPAGE IFPD VCO_GAIN[1:0]

RFIF Address

$0030

$0031

$0032

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

$003C

$003D

$003E

$003F

$0040

$0041

$0042

$0043

$0044

$0045

$0046

$0047

$0048

$0049

$004A

$004B

$004C

$004D

$004E

$004F Note: Shaded bits are recommended to only be controlled by firmware or factory test. RFCR0 RFCR1 RFCR2 RFCR3 RFCR4 RFCR5 RFCR6 RFCR7 PLLCR0 PLLCR1 PLLCR2 PLLCR3 RFD0 RFD1 RFD2 RFD3 RFD4 RFD5 RFD6 RFD7 RFD8 RFD9 RFD10 RFD11 RFD12 RFD13 RFD14 RFD15 Reserved Reserved Reserved Reserved AFREQ[12:5]

BFREQ[12:5]

RFD[7:0]

RFD[15:8]

RFD[23:16]

RFD[31:24]

RFD[39:32]

RFD[47:40]

RFD[55:48]

RFD[63:56]

RFD[71:64]]

RFD[79:72]

RFD[87:80]

RFD[95:88]

RFD[103:96]

RFD[111:104]

RFD[119:112]

RFD[127:120]

FXTH870x6 20 Sensors Freescale Semiconductor, Inc. Table 7. RFM Register Summary - RPAGE = 1 3 2 1 Bit 0 PWR[4:0]

FNUM[3:0]

BPS[7:0]

FRM[7:0]

RFBT[7:0]

LFSR[6:0]

RFFT[5:0]

RFIEN RFLVDEN RCTS PA_SLOPE RFMRST VCD_EN 4 5 6 IFID Bit 7 RFVF RFEF RFIAK BOOST

/VCD3 EOM ISPC SEND DATA Register Name RPAGE IFPD PLL_LPF_[2:0]/VCD[2:0]

VCO_GAIN[1:0]

RFIF Address

$0030

$0031

$0032

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

$003C

$003D

$003E

$003F

$0040

$0041

$0042

$0043

$0044

$0045

$0046

$0047

$0048

$0049

$004A

$004B

$004C

$004D

$004E

$004F Note: Shaded bits are recommended to only be controlled by firmware or factory test. RFCR0 RFCR1 RFCR2 RFCR3 RFCR4 RFCR5 RFCR6 RFCR7 EPR Reserved Reserved Reserved RFD0 RFD1 RFD2 RFD3 RFD4 RFD5 RFD6 RFD7 RFD8 RFD9 RFD10 RFD11 RFD12 RFD13 RFD14 RFD15 Reserved Reserved Reserved Reserved RFD[135:128]

RFD[143:136]

RFD[151:144]

RFD[159:152]

RFD[167:160]

RFD[175:168]

RFD[183:176]

RFD[191:184]

RFD[199:192]

RFD[207:200]

RFD[215:208]

RFD[223:216]

RFD[231:224]

RFD[239:232]

RFD[247:240]

RFD[255:248]

Sensors Freescale Semiconductor, Inc. FXTH870x6 21 High Address Registers 4.4 High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. The registers control system level features as given in Table 8. Table 8. MCU High Address Register Summary Address

$1800

$1801

$1802

$1803

$1804

$1805

$1806

$1807

$1808

$1809

$180A

$180B

$180C

$180D

$180E

$180F

$1810-1F

$1820

$1821

$1822

$1823

$1824

$1825

$1826 Register Name SRS SBDFR SIMOPT1 SIMOPT2 Reserved Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved SPMSC3 SIMSES SOTRM SIMTST Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Bit 7 POR 0 6 PIN 0 5 COP 0 COPE COPCLKS STOPE 4 ILOP 0 RFEN 3 ILAD 0 TRE 2 PWU 0 TRH 0 COPT[2:0]

LFOSEL TCLKDIV 1 LVD 0 Bit 0 0 BDFR BKGDPE 1 BUSCLKS[1:0]

REV[3:0]

ID[11:8]

RTIF LVDF 0 RTIACK LVDACK RTICLKS LVDIE 0 0 LVWF LVWACK LVDV KBF TRH[2:0]

ID[7:0]

RTIE LVDRE PDF LVWV IRQF 0 LVDSE 0 0 TRF LVDE PPDACK 0 PWUF RTIS{2:0]

0 PDC 0 LFF SOTRM[7:0]

BGBE 0 0 RFF TRO DIVLD KEYEN PRDIV8 FNORED 0 0 0 KEYACC 0 0 FCCF FPVIOL FPS[7:1]

FACCERR FCBEF FERASE DIV[5:0]

0 0 FBLANK 0 0 0 FCMD[6:0]

SEC0[1:0}

0 0 0 FPDIS 0 Reserved

$1827-3F Note: Reserved bits shown as 0 must always be written to 0. Reserved bits shown as 1 must always be written to 1. Shaded bits are recommended to only be controlled by firmware or factory test. MCU Parameter Registers 4.5 The 64 bytes of parameter registers are located at addresses $0050 through $008F. These registers are powered up at all times and may be used to store temporary or history data during the times that the MCU is in any of the STOP modes. The parameter register at $008F is used by the firmware for interrupt flags. MCU RAM 4.6 The FXTH870x6 includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit-manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power WAIT, STOP3 or STOP4 modes. At power-on or after wakeup from STOP1, the contents of RAM are not initialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention (VRAM). When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or through code executing from non-secure memory. See Section 4.8 for a detailed description of the security feature. FXTH870x6 22 Sensors Freescale Semiconductor, Inc. None of the RAM locations are used directly by the firmware provided by Freescale. The firmware routines utilize RAM only through stack operations; and the user needs to be aware of stack depth required by each routine as described in the CodeWarrior project files supplied by Freescale. FLASH Features User Program FLASH Size 8192 bytes (16 pages of 512 bytes each) Single power supply program and erase Command interface for fast program and erase operation Up to 100,000 program/erase cycles at typical voltage and temperature Flexible block protection Security feature for FLASH and RAM Auto power-down for low-frequency read accesses 4.7 The FLASH memory is intended primarily for program storage. The operating program can be loaded into the FLASH memory after final assembly of the application product using the single-wire BACKGROUND DEBUG interface. Because no special voltages are needed for FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale document order number HCS08RMV1/D. 4.7.1 Features of the FLASH memory include:

4.7.2 Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and 200 kHz. This register can be written only once, so normally this write is performed during reset initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these timing pulses are used by the command processor to complete a program or erase command. Table 9 shows program and erase times. The bus clock frequency and FCDIV determine the frequency of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number of cycles of FCLK and as an absolute time for the case where tFCLK = 5 s. Program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. Program and Erase Times Table 9. Program and Erase Times Parameter Byte program Byte program (burst) Page erase Mass erase 1. Excluding start/end overhead Cycles of FCLK Time if FCLK = 200 kHz 9 4 4000 20,000 45 s 20 s(1) 20 ms 100 ms Program and Erase Command Execution 4.7.3 The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are:

1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512 bytes are the smallest block of FLASH that may be erased. Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH. Sensors Freescale Semiconductor, Inc. FXTH870x6 23 2. Write the command code for the desired command to FCMD. The five valid commands are blank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). Burst Program Execution A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error flag which must be cleared before starting a new command. A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the possibility of any unintended changes to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command. Figure 9 is a flowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 4.7.4 The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH memory must be enabled to supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst program command is issued, the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met:

The next burst program command has been queued before the current program operation has completed. The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. FXTH870x6 24 Sensors Freescale Semiconductor, Inc. WRITE TO FCDIV (1) Note 1: Required only once after reset. FLASH PROGRAM AND ERASE FLOW START 0 FACCERR?

1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT FPVIOL OR FACCERR?

NO FCCF?

1 DONE 0 Programming time for the FLASH through the BDM function is dependent on the specific external BDM interface tool and software being used. Consult tool vendor for programming times. Figure 9. FLASH Program and Erase Flowchart Sensors Freescale Semiconductor, Inc. FXTH870x6 25 WRITE TO FCDIV (1) Note 1: Required only once after reset. FLASH BURST PROGRAM FLOW START FACCERR?

1 CLEAR ERROR FCBEF?

1 0 0 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND ($25) TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. FPVIO OR FACCERR?

NO YES ERROR EXIT YESNEW BURST COMMAND?

0 NO FCCF?

1 DONE Figure 10. FLASH Burst Program Flowchart Access Errors 4.7.5 An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed. Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the command buffer is empty.) Writing a second time to a FLASH address before launching the previous command (There is only one write to FLASH for every command.) Writing a second time to FCMD before launching the previous command (There is only one write to FCMD for every command.) Writing to any FLASH control register other than FCMD after writing to a FLASH address Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the command) after writing the command to FCMD. The MCU enters STOP mode while a program or erase command is in progress (The command is aborted.) FXTH870x6 26 Sensors Freescale Semiconductor, Inc. Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a BACKGROUND DEBUG command while the MCU is secured (the BACKGROUND DEBUG controller can only do blank check and mass erase commands when the MCU is secure.) FLASH Block Protection Writing 0 to FCBEF to cancel a partial command. 4.7.6 The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is controlled through the FLASH Protection Register (FPROT). When enabled, block protection begins at any 512-byte boundary below the last address of FLASH, 0xFFFF. (see Section 4.9.4). After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application software so a runaway program cannot alter the block protection settings. Because NVPROT is within the last 512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through BACKGROUND DEBUG commands which allows a way to erase and reprogram a protected FLASH memory. The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value 0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 1 1 1 1 1 1 1 1 1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 11. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. 4.7.7 Vector Redirection Not recommended for TPMS applications where Freescale firmware has been included in the final image. NOTE Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the FLASH memory must be block protected by programming the NVPROT register located at address 0xFFBD. All of the interrupt vectors (memory locations 0xFFC00xFFFD) are redirected, though the reset vector (0xFFFE:FFFF) is not. For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through 0xFFFF. The interrupt vectors (0xFFC00xFFFD) are redirected to the locations 0xFDC00xFDFD. Now, if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. Sensors Freescale Semiconductor, Inc. FXTH870x6 27 Security 4.8 The FXTH870x6 includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When security is engaged, FLASH and RAM are considered secure resources. Direct-page registers, high-page registers, and the BACKGROUND DEBUG controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing from an unsecured memory space or through the BACKGROUND DEBUG interface are blocked (writes are ignored and reads return all 0s). Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC0[1:0]) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location, which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC[1:0] = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate BACKGROUND DEBUG controller can still be used for background memory access commands, but the MCU cannot enter ACTIVE BACKGROUND mode except by holding BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure user program can temporarily disengage security by:

1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a FLASH program or erase command. 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be done on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the FLASH locations, SEC[1:0] are automatically changed to 1:0 and security will be disengaged until the next reset. The security key can be written only from secure memory (either RAM or FLASH), so it cannot be entered through BACKGROUND commands without the cooperation of a secure user program. The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of FLASH as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. Block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the BACKGROUND DEBUG interface by taking these steps:

1. Disable any block protections by writing FPROT. FPROT can be written only with BACKGROUND DEBUG commands, not from application software. 2. Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC[1:0] = 1:0. NOTE Enabling the security feature disables Freescale ability to perform failure analysis without first completely erasing all flash memory contents. If the security feature is implemented, customer shall be responsible for providing to Freescale unsecured parts for any failure analysis to begin or supplying the entire contents of the device flash memory data as part of the return process, to allow Freescale to erase and subsequently restore the device to its original condition. FXTH870x6 28 Sensors Freescale Semiconductor, Inc. FLASH Registers and Control Bits 4.9 The FLASH module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile register space in FLASH memory which are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 8 and Table 9 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.9.1 Bit 7 of this register is a read-only status flag. Bits 6 through 0 can be read at any time but can be written only once. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. FLASH Clock Divider Register (FCDIV)

$1820 R W Reset:

7 DIVLD 6 5 PRDIV8 DIV5 0 0 0

= Reserved 4 DIV4 0 3 DIV3 0 2 DIV2 0 1 DIV1 0 0 DIV0 0 Figure 12. FLASH Clock Divider Register (FCDIV) Table 10. FCDIV Register Field Descriptions Field 7 DIVLD 6 PRDIV8 5:0 DIV[5:0]

Description Divisor Loaded Status Flag When set, this read-only status flag indicates that the FCDIV register has been written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH 1 FCDIV has been written since reset; erase and program operations enabled for FLASH Prescale (Divide) FLASH Clock by 8 0 Clock input to the FLASH clock divider is the bus rate clock 1 Clock input to the FLASH clock divider is the bus rate clock divided by 8 Divisor for FLASH Clock Divider The FLASH clock divider divides the bus rate clock (or the bus rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5 s to 6.7 s. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. if PRDIV8 = 0 fFCLK = fBus ([DIV5:DIV0] + 1) if PRDIV8 = 1 fFCLK = fBus (8 ([DIV5:DIV0] + 1)) Table 11 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies. Table 11. FLASH Clock Divider Settings fBus 20 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 200 kHz 150 kHz PRDIV8

(Binary) DIV5:DIV0

(Decimal) 1 0 0 0 0 0 0 0 12 49 39 19 9 4 0 0 fFCLK 192.3 kHz 200 kHz 200 kHz 200 kHz 200 kHz 200 kHz 200 kHz 150 kHz Program/Erase Timing Pulse

(5 s Min, 6.7s Max) 5.2 s 5 s 5 s 5 s 5 s 5 s 5 s 6.7 s Sensors Freescale Semiconductor, Inc. FXTH870x6 29 FLASH Options Register (FOPT and NVOPT) 4.9.2 During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5 through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset.

$1821 7 6 KEYEN FNORED 5 0 4 0 3 0 2 0 1 0 SEC01 SEC00 R W Reset:

This register is loaded from nonvolatile location NVOPT during reset.

= Reserved Figure 13. FLASH Options Register (FOPT) Table 12. FOPT Register Field Descriptions Field 7 KEYEN 6 FNORED 1:0 SEC0[1:0]

Description Backdoor Key Mechanism Enable When this bit is 0, the backdoor key mechanism cannot be used to disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed information about the backdoor key mechanism, refer to Section 4.8. 0 No backdoor key access allowed 1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset Vector Redirection Disable When this bit is 1, then vector redirection is disabled. 0 Vector redirection enabled 1 Vector redirection disabled Security State Code This 2-bit field determines the security state of the MCU as shown in Table 13. When the MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the BACKGROUND DEBUG interface. For more detailed information about security, refer to Section 4.8. SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. Table 13. Security States SEC01:SEC00 0:0 0:1 1:0 1:1 Description secure secure unsecured secure FLASH Configuration Register (FCNFG) 4.9.3 Bits 7 through 5 can be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.

$1823 R W Reset:

7 0 0 6 0 0 5 KEYACC 0 4 0 0

= Reserved 3 0 0 2 0 0 1 0 0 0 0 0 Figure 14. FLASH Configuration Register (FCNFG) FXTH870x6 30 Sensors Freescale Semiconductor, Inc. Table 14. FCNFG Register Field Descriptions Field 5 KEYACC Enable Writing of Access Key This bit enables writing of the backdoor comparison key. For more detailed information about the backdoor key mechanism, refer to Section 4.8. 0 Writes to 0xFFB00xFFB7 are interpreted as the start of a FLASH programming or erase command 1 Writes to NVBACKKEY (0xFFB00xFFB7) are interpreted as comparison key writes Description FLASH Protection Register (FPROT and NVPROT) 4.9.4 During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. Bits 0, 1, and 2 are not used and each always reads as 0. This register can be read at any time, but user program writes have no meaning or effect. BACKGROUND DEBUG commands can write to FPROT.

$1824 R W Reset:

7 FPS7

(1) 6 FPS6

(1) 5 FPS5

(1) 4 FPS4

(1) 3 FPS3

(1) 2 FPS2

(1) 1 FPS1

(1) 0 FPDIS

(1) This register is loaded from nonvolatile location NVPROT during reset. 1. Background commands can be used to change the contents of these bits in FPROT. Figure 15. FLASH Protection Register (FPROT) Table 15. FPROT Register Field Descriptions Field 7:1 FPS[7:1]

0 FPDIS Description FLASH Protect Select Bits When FPDIS = 0, this 7-bit field determines the ending address of unprotected FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed. FLASH Protection Disable 0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed) 1 No FLASH block is protected FLASH Status Register (FSTAT) 4.9.5 Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions.

$1825 7 R W Reset:

FCBEF 1 6 FCCF 5 4 FPVIOL FACCERR 1 0 0

= Reserved 3 0 0 2 FBLANK 0 1 0 0 0 0 0 Figure 16. FLASH Status Register (FSTAT) Table 16. FSTAT Register Field Descriptions Field 7 FCBEF Description FLASH Command Buffer Empty Flag The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a one to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands) 1 A new burst program command can be written to the command buffer Sensors Freescale Semiconductor, Inc. FXTH870x6 31 Table 16. FSTAT Register Field Descriptions (continued) Field 6 FCCF 5 FPVIOL 4 FACCERR 2 FBLANK Description FLASH Command Complete Flag FCCF is set automatically when the command buffer is empty and no command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete Protection Violation Flag FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation 1 An attempt was made to erase or program a protected location Access Error Flag FACCERR is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters STOP while a command was in progress. For a more detailed discussion of the exact actions that are considered access errors, see Section 4.7.5. FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error 1 An access error has occurred FLASH Verified as All Blank (erased) Flag FBLANK is set automatically at the conclusion of a blank check command if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not completely erased 1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is completely erased

(all 0xFF) FLASH Command Register (FCMD) 4.9.6 Only five command codes are recognized in normal user modes as shown in Table 17. Refer to Section 4.7.3, for a detailed discussion of FLASH programming and erase operations.

$1826 R W Reset:

7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0 0 0 0 0 0 0 0 Figure 17. FLASH Command Register (FCMD) Table 17. FLASH Commands Command Blank check Byte program Byte program burst mode Page erase (512 bytes/page) Mass erase (all FLASH) FCMD 0x05 0x20 0x25 0x40 0x41 Equate File Label mBlank mByteProg mBurstProg mPageErase mMassErase All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. FXTH870x6 32 Sensors Freescale Semiconductor, Inc. Reset, Interrupts and System Configuration 5 This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the FXTH870x6. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this product specification. This section gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems, but are part of the system control logic. Features 5.1 Reset and interrupt features include:

Multiple sources of reset for flexible system configuration and reliable operation Reset status register (SRS) to indicate source of most recent reset Separate interrupt vectors for each module (reduces polling overhead) MCU Reset 5.2 Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector ($DFFE:$DFFF). On-chip peripheral modules are disabled and any I/O pins are initially configured as general-purpose high-impedance inputs with any pullup devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. The SP is forced to $00FF at reset. The FXTH870x6 has seven sources for reset:

Each of these sources has an associated bit in the system reset status register with the exception of the BACKGROUND DEBUG forced reset and the periodic hardware reset, PRST, that is indicated by the PRF bit in the PWUCS1 register. Power-on reset (POR) Low-voltage detect (LVD) Computer operating properly (COP) timer Periodic hardware reset (PRST) Illegal opcode detect Illegal address detect BACKGROUND DEBUG forced reset Computer Operating Properly (COP) Watchdog 5.3 The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it times out, a system reset is generated to force the system back to a known starting point. The COP watchdog is enabled by the COPE bit in SIMOPT1 register. The COP timer is reset by writing any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP timer. The timeout period can be selected by the COPCLKS and the COPT[2:0] bits as shown in Table 18. The COPCLKS bit selects either the LFO or the CPU bus clock as the clocking source and the COPT[2:0] bits select the clock count required for a timeout. The tolerances of these timeout periods is dependent on the selected clock source (LFO or HFO). Table 18. COP Watchdog Timeout Period COPCLKS 0 0 0 0 0 0 COPT 1 0 0 1 1 0 0 0 0 1 0 1 0 1 2 0 0 0 0 1 1 Clock Source COP Overflow Count LFO LFO LFO LFO LFO LFO 25 26 27 28 29 210 Sensors Freescale Semiconductor, Inc. COP Overflow Time

(ms, nominal) 32 64 128 256 512 1024 FXTH870x6 33 Table 18. COP Watchdog Timeout Period (continued) COPCLKS 0 0 1 1 1 1 1 1 1 1 COPT 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 2 1 1 0 0 0 0 1 1 1 1 Clock Source LFO LFO COP Overflow Count 211 211 Bus Clock Bus Clock Bus Clock Bus Clock Bus Clock Bus Clock Bus Clock Bus Clock 213 214 215 216 217 218 219 219 COP Overflow Time

(ms, nominal) 2048 2048 BUSCLKS[1:0]

1:1 (0.5 MHz) 1:0 (1 MHz) 0:1 (2 MHz) 0:0 (4MHz) 16.384 32.768 65.536 131.072 262.144 524.288 1048.576 1048.576 8.192 16.384 32.768 65.536 131.072 262.144 524.288 524.288 4.096 8.192 16.384 32.768 65.536 131.072 262.144 262.144 2.048 4.096 8.192 16.384 32.768 65.536 131.072 131.072 After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE bit in the write-once SIMOPT1 register. Even if the application will use the reset default settings in COPE, COPCLKS and COPT[2:0], the user should still write to write-

once SIMOPT1 during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application program gets lost. The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. When the MCU is in ACTIVE BACKGROUND DEBUG mode, the COP timer is temporarily disabled. 5.4 The output of the temperature monitor is available using the SIM Test register as shown in Figure 18. SIM Test Register (SIMTST)

$180F Bit 7 R W RESET:

0 6 0

= Reserved 5 TRH 1 4 1 3 1 2 0 1 0 Bit 0 TRO 1 Figure 18. SIM Test Register (SIMTST) Table 19. SIMTST Register Field Descriptions Field 7 reserved 6:4 TRH 3:1 reserved 0 TRO FXTH870x6 34 Description Reserved Bit These bits are reserved for factory trim and should not be altered by the user. Temperature Restart High threshold Binary coded from 0x00 to 0x07; recommend applications overwrite to 0x06 at each wakeup cycle. Reserved Bit These bits are reserved for factory trim and should not be altered by the user. Temperature Restart Outside 1 TR module is outside the TREARM temperature range and will restart the MCU if the TRE bit is set and temperature falls back within the TRESET temperature range. 0 TR module is within the TRESET temperature range and the MCU cannot be armed to restart when temperature falls back to the TRESET range. The TRE bit cannot be set. Sensors Freescale Semiconductor, Inc. Interrupts 5.5 Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events. The debug module can also generate an SWI under certain circumstances. If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I bit in the CCR must be a logic 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction and consists of:

Saving the CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest-priority interrupt that is currently pending Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre interrupt values by reading the previously saved information off the stack. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first. For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it just before the RTI that is used to return from the ISR. 5.5.1 Figure 18 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered from the stack. The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR. Interrupt Stack Frame Sensors Freescale Semiconductor, Inc. FXTH870x6 35 UNSTACKING ORDER 7 Towards LOWER Addresses 0 5 4 3 2 1 1 2 3 4 5 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER* (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW STACKING ORDER Towards HIGHER Addresses

* High byte (H) of index register is not automatically stacked. Figure 19. Interrupt Stack Frame SP after interrupt stacking SP before the interrupt Vector Summary 5.5.2 Table 20 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table (at the higher vector addresses). All of these vectors are a 2-byte address that the firmware uses as the destination address. This allows the firmware to intercept all vectors and add additional processing as needed. The additional process latency for each interrupt will be described in Section 14. Therefore, the high-order byte of the address for the users interrupt service routine is located at the lower address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the higher address. When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is set, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. The triggering of any of these vector fetches will wake the MCU from any of the STOP modes. FXTH870x6 36 Sensors Freescale Semiconductor, Inc. Table 20. Vector Summary Vector Priority Vector No. 15 14 13 12 Jump Table Vector Addr

(High/Low)

$DFE0 - $DFE1

$DFE2 - $DFE3

$DFE4 - $DFE5 Vector Name Vkbi Module Source KBI Flags Enables Description KBF KBIE Reserved Reserved Keyboard interrupt pins PTA[3:0]

$DFE6 - $DFE7 Vrti Sys Ctrl RTIF RTIE LFIDF LFIDIE LFCDF LFCDIE LFERF LFERIE LFDRF LFDRIE RFIF RFEF Reserved RFIEN Reserved TOF TOIE CH1F CH1IE CH0F CH0IE WUKI WUK[5:0]

Interrupt from the RTI when the periodic wakeup timer has timed out. Interrupt from LFR in data mode when a valid wake ID has been received. Interrupt from LFR in carrier mode when a carrier present for the required time. Interrupt from LFR in the manchester decode mode when an error is detected. Interrupt from LFR in the manchester decode mode when an 8-bit data byte has been successfully received. Interrupt from the RFM when the data buffer has been completely sent. Interrupt from the RFM when transmission error detected. Interrupt from the TPM1 when the timer overflows. Interrupt from the TPM1 when the selected event for channel 1 occurs. Interrupt from the TPM1 when the selected event for channel 0 occurs. Interrupt from the PWU when the wakeup time interval has elapsed. Interrupt from the LVD when the supply voltage has dropped below the LVD threshold. 11

$DFE8 - $DFE9 Vlfrcvr LFR Lower 10

$DFEA - $DFEB

$DFEC - $DFED Vrf RFM

$DFEE - $DFEF

$DFF0 - $DFF1 Vtpm1ovf

$DFF2 - $DFF3 Vtpm1ch1

$DFF4 - $DFF5 Vtpm1ch0

$DFF6 - $DFF7 Vwuktmr TPM1 TPM1 TPM1 PWU 9 8 7 6 5 4 3 2 1 Higher

$DFF8 - $DFF9 Vlvd Sys Ctrl LVDF LVDIE

$DFFA - $DFFB Reserved

$DFFC - $DFFD Vswi SWI opcode Sys Ctrl - POR Interrupt from the CPU when an SWI instruction has been executed. Reset from power on sequence. 0

$DFFE -$DFFF Vreset Sys Ctrl - PRF PRF Sys Ctrl - COP Sys Ctrl - LVD Temp Restart Illegal opcode Illegal address PRST[5:0] Reset from PWU when the reset interval COPE elapsed. Reset when COP watchdog times out. Reset from the LVD when the supply voltage has dropped below the LVD threshold. Reset when the temperature falls below the temperature restart threshold Reset from the CPU when trying to execute an illegal opcode. Reset from the CPU when trying to access an illegal address. LVDRE TRE Sensors Freescale Semiconductor, Inc. FXTH870x6 37 LVD Reset Operation Power-On Reset Operation Low-Voltage Detect (LVD) System 5.6 The FXTH870x6 includes a system to detect low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in SPMSC3. The LVD is disabled upon entering any of the STOP modes unless the LVDSE bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter STOP1. 5.6.1 When power is initially applied to the FXTH870x6, or when the supply voltage drops below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the level determined by LVDV bit. Both the POR bit and the LVD bit in SRS are set following a POR. 5.6.2 The LVD can be configured to generate a reset upon detection of a low voltage condition has occurred by setting LVDRE to 1 when the supply voltage has fallen below the level determined by LVDV bit. After an LVD reset has occurred, the LVD system will hold the FXTH870x6 in reset until the supply voltage has risen above the level determined by LVDV bit. The threshold for falling and rising differ by a small amount of hysteresis. The LVD bit in the SRS register is set following either an LVD reset or POR. 5.6.3 When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur. 5.6.4 The LVD system has a low voltage warning flag, LVWF, to indicate to the user that the supply voltage is approaching, but is still above, the LVD reset voltage. The LVWF can be reset by writing a logical one to the LVWACK bit. The LVW does not have an interrupt associated with it. There are two user selectable trip voltages for the LVW as selected by LVWV in SPMSC3. The LVWF is set when the supply voltage falls below the selected level and cannot be reset until the supply voltage has risen above the selected level. The threshold for falling and rising differ by a small amount of hysteresis. Low-Voltage Warning (LVW) LVD Interrupt Operation System Clock Control 5.7 Several clock rate selections are possible with the FXTH870x6 using the BUSCLKS[1:0] control bits to select the clock frequency division of the HFO as given in Table 21. These bits are cleared by any MCU reset. Table 21. HFO Frequency Selections BUSCLKS1 BUSCLKS0 HFO Frequency

(MHz) CPU Bus Frequency (MHz) 0 0 1 1 0 1 0 1 8 4 2 1 4 2 1 0.5 5.8 The keyboard interrupts can be used to wake the MCU. These are assigned to specific general I/O pins as given in Table 22. Keyboard Interrupts Table 22. Keyboard Interrupt Assignments KBI 0 1 2 3 Pin PTA0 PTA1 PTA2 PTA3 Pin Function General I/O General I/O General I/O General I/O FXTH870x6 38 Sensors Freescale Semiconductor, Inc. Real Time Interrupt 5.9 The RTI uses the internal low frequency oscillator (LFO) as its clock source. The RTI can be used as a periodic interrupt in MCU RUN mode, or can be used as a periodic wakeup from all low power modes. The LFO is always active and cannot be powered off by any software control. The control bits for the RTI are shown in Figure 20.

$1808 R W RESET:

POR:

Bit 7 RTIF 0 0 6 0 RTIACK 0 0

= Reserved 5 4 RTICLKS RTIE 0 0 0 0 3 0 0 0 2 0 0 1 Bit 0 RTIS[2:0]

0 0 0 0 Figure 20. RTI Status/Control Register (SRTISC) Table 23. SRTISC Register Field Descriptions Field 7 RTIF 6 RTIACK 5 RTICLKS 4 RTIE 3 Unused 2:0 RTIS[2:0]

Description RTI Interrupt Flag The RTIF bit indicates when a wakeup interrupt has been generated by the RTI. This bit is cleared by writing a one to the RTIACK bit. Writing a zero to this bit has no effect. Reset clears this bit. 0 Wakeup interrupt not generated or was previously acknowledged. 1 Wakeup interrupt generated. Acknowledge RTIF Interrupt Flag The RTIACK bit clears the RTIF bit if written with a one. Writing a zero to the RTIACK bit has no effect on the RTIF bit. Reading the RTIACK bit returns a zero. Reset has no effect on this bit. 0 No effect. 1 Clear RTIF bit. RTI Interrupt Clock Select This read-write bit selects the clock source for the real-time interrupt request 0 Real-time interrupt request clock source is the LFO. 1 Real-time interrupt request clock source is the HFO (MCU must be in the RUN mode). RTIF Interrupt Enable The RTIE bit enables RTI interrupts if written with a one. Reset clears this bit. 0 Disable RTI interrupts. 1 Enable RTI interrupts. Unused RTI Interrupt Delay Selects The RTIS[2:0] bits select the timing of the RTI interrupts as given in Table 24. Reset clears these bits. Sensors Freescale Semiconductor, Inc. FXTH870x6 39 Table 24. Real-Time Interrupt Period RTIS2 RTIS1 RTIS0 Delay Timing (ms)

(Dependent on 1-kHz LFO) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 OFF 2 4 8 16 32 64 128 Temperature Sensor and Restart System 5.10 The FXTH870x6 has two temperature sensing mechanisms. The first is an accurate sensor which is accessible through the ADC10 channel 1. The second is a less accurate, very low power sensor which generates a wakeup from STOP1 when the temperature crosses its threshold of detection. This is the temperature restart wakeup which is used as follows:

1. The temperature restart wakeup is enabled by software following detection of an over temperature condition using the temperature sensor connected to the ADC10. 2. User software enables the temperature restart detector and then instructs the MCU to enter STOP1 mode to halt execution during the out-of-range temperature condition. 3. When the temperature crosses the temperature restart threshold back into the normal range of operation, a wakeup is generated to wake the MCU. Exit from STOP1 will reset the device. The temperature sensor is enabled whenever the ADC10 is enabled. The temperature restart wakeup is enabled by setting the TRE bit in SIMOPT1 register and whether the detector interrupts the MCU from a very low or a very high temperature is determined by the TRH bit in the SIMOPT1 register. Reset, Interrupt and System Control Registers And Bits 5.11 One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. 5.11.1 The SRS register at $1800 includes seven read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. System Reset Status Register (SRS)

$1800 R W POR Reset:

LVD Reset:

Any Other Reset:

Bit 7 POR 1 1 0 6 PIN 0 0

(1)

= Reserved 5 COP 0 0

(1) 4 ILOP 0 0

(1) 3 ILAD 0 0

(1) 2 PWU 0 0 0 1 LVD 1 1 0 Bit 0 0 0 0 0 1. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared. Figure 21. System Reset Status Register (SRS) FXTH870x6 40 Sensors Freescale Semiconductor, Inc. Table 25. SRS Register Field Descriptions Field 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 PWU 1 LVD Description Power-On Reset This bit indicates reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the internal supply was below the LVR threshold. 0 Reset not caused by POR 1 POR caused reset External Reset Pin This bit indicates reset was caused by an active-low level on the external reset pin if the device was in either the STOP1 or RUN modes. This bit is not set if the external reset pin is pulled low when the device is in the STOP1 mode. 0 Reset not caused by external reset pin 1 Reset came from external reset pin Computer Operating Properly (COP) Watchdog This bit indicates that reset was caused by the COP watchdog timer timing out. This reset source may be blocked by COPE = 0. 0 Reset not caused by COP timeout 1 Reset caused by COP timeout Illegal Opcode This bit indicates reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is considered illegal if STOP is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if ACTIVE BACKGROUND mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode 1 Reset caused by an illegal opcode Illegal Address This bit indicates reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 Reset not caused by an illegal address 1 Reset caused by an illegal address Programmable Wakeup This bit indicates reset was caused by a PWU reset in run, WAIT, STOP4, and STOP3. After STOP1 exit, PRF in PWUCSI indicates PWU was the source of a wakeup. 0 Reset not caused by PWU. 1 Reset caused by PWU. Low Voltage Detect If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 0 Unused Unused Bit This bit always reads as a logical zero. Writes System Options Register 1 (SIMOPT1) 5.11.2 The following clock source and frequency selections are available using the system option register 1 as shown in Figure 22.

$1802 Bit 7 6 5 4 R W RESET:

COPE COPCLKS STOPE RFEN 1 0 0

-

= Reserved 3 TRE 0 2 1 Bit 0 TRH BKGDPE 0 1 1 Figure 22. System Option Register 1 (SIMOPT1) Table 26. SIMOPT1 Register Field Descriptions Field 7 COPE COP Enable This control bit enables the COP watchdog. This bit is a write-once bit so that only the first write after reset is honored. Reset sets the COPE bit. 0 COP Watchdog disabled. 1 COP Watchdog enabled. Description Sensors Freescale Semiconductor, Inc. FXTH870x6 41 Table 26. SIMOPT1 Register Field Descriptions (continued) Field 6 COPCLKS 5 STOPE 4 RFEN 3 TRE 2 TRH 1 BKGDPE 0 Reserved Description COP Clock Select This control bit selects the clock source for the COP watchdog timer. This bit is a write-once bit so that only the first write after reset is honored. This bit is cleared by an MCU reset. 0 Select the LFO oscillator output. 1 Select the CPU bus clock. STOP Mode Select This control bit enables/disables the STOP instruction to enter a STOP mode defined by the SPMSCR2 register. This bit is a write-once bit so that only the first write after reset is honored. This bit is cleared by an MCU reset. 0 Disable STOP modes. 1 Enable STOP modes. RF Module Enable This bit enables or disables the RF module. This bit is not affected by any reset or power on after STOP exit. It is only initialized at the first power up. This bit can be written anytime. 1 RF module enabled. 0 RF module disabled. Temperature Restart Enable This control bit enables the temperature restart circuit to interrupt the MCU after being shutdown at either a very high or very low temperature. This bit is cleared by an MCU reset. 0 Temperature restart disabled. 1 Temperature restart enabled. Temperature Restart Level This control bit selects whether the temperature restart circuit will interrupt the MCU after being shutdown on returning from either a very high or very low temperature. This bit is cleared by an MCU reset. 0 Temperature restart interrupts MCU on return from a very low temperature. 1 Temperature restart interrupts MCU on return from a very high temperature. BKGD Pin Enable BKGDPE can be used to allow the BKGD/PTA4 pin to be shared in applications as an input-only general purpose I/O pin:

0 BKGD function disabled, PTA4 enabled. 1 BKGD function enabled, PTA4 disabled. Reserved register bit, always reads 1. System Operation Register 2 (SIMOPT2) 5.11.3 The following clock source and frequency selections are available using the system option register 2 as shown in Figure 23.

$1803 Bit 7 R W RESET:

0 0 6 1 5 COPT[2:0]

1 4 1 3 2 1 Bit 0 LFOSEL TCLKDIV BUSCLKS[1:0]

0 0 0 0 Figure 23. System Option Register 2 (SIMOPT2) Table 27. SIMOPT2 Register Field Descriptions Field 7 Unused 6:4 COPT[2:0]

3 LFOSEL 2 TCLKDIV FXTH870x6 42 Unused Bit This bit is unused and reads as a logic zero. Description COP Watchdog Time Out These control bits select the timeout period for the COP watchdog timer as given in Table 18. These bits are set by an MCU reset to select the longest watchdog timeout period. These bits are write-once after power up. TPM1 Channel 0 Clock Source This bit determines which signal is connected to the TPM1 Channel 0, see Section 9. 0 Select clock input driven by PTA2. 1 Select clock input driven by the LFO. TPM1 Channel 0 CLock Source Divider The divider for the clock Source for TPM1 Channel 0, see Section 9. 0 Select RFM Dx clock source divided by 1. 1 Select RFM Dx clock source divided by 8. Sensors Freescale Semiconductor, Inc. Table 27. SIMOPT2 Register Field Descriptions (continued) Field 1:0 BUSCLKS

[1:0]

Description Bus Clock Select Bus clock frequency selection by changing HFO FLL ratio as shown in Figure 2. The bus clock frequency is always the HFO frequency divided by two. These bits are cleared by a reset and can be written at any time. 00 Bus Frequency = 4 MHz (HFO = 8 MHz) 01 Bus Frequency = 2 MHz (HFO = 4 MHz) 10 Bus Frequency = 1 MHz (HFO = 2 MHz) 11 Bus Frequency = 0.5 MHz (HFO = 1 MHz) 5.11.4 System Power Management Status and Control 1 Register (SPMSC1)

$1809 R W Reset:

7 LVDF 0 6 0 LVDACK 0

= Reserved 5 4 3 2 LVDIE LVDRE(2) LVDSE LVDE(2) 0 1 1 1 1(1) 0 0 0 BGBE 0 1. Bit 1 is a reserved bit that must always be written to 0. 2. This bit can be written only one time after reset. Additional writes are ignored. Figure 24. System Power Management Status and Control 1 Register (SPMSC1) Table 28. SPMSC1 Register Field Descriptions Field 7 LVDF 6 LVDACK 5 LVDIE 4 LVDRE 3 LVDSE 2 LVDE 0 Reserved 0 BGBE Description Low-Voltage Detect Flag Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event. Low-Voltage Detect Acknowledge This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads always return logic 0. Low-Voltage Detect Interrupt Enable This read/write bit enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling) 1 Request a hardware interrupt when LVDF = 1 Low-Voltage Detect Reset Enable This read/write bit enables LVDF events to generate a hardware reset (provided LVDE

= 1). 0 LVDF does not generate hardware resets 1 Force an MCU reset when LVDF = 1 Low-Voltage Detect Stop Enable Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in STOP mode. 0 Low-voltage detect disabled during STOP mode 1 Low-voltage detect enabled during STOP mode Low-Voltage Detect Enable This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 LVD logic disabled 1 LVD logic enabled Reserved Bit This bit is reserved should not be altered by the user. Any read returns a logical zero. Any write should be a logical zero. Bandgap Buffer Enable The BGBE bit is used to enable an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels. 0 Bandgap buffer disabled 1 Bandgap buffer enabled Sensors Freescale Semiconductor, Inc. FXTH870x6 43 System Power Management Status and Control 2 Register (SPMSC2) 5.11.5 This register is used to configure the STOP mode behavior of the MCU.

$180A R W Power-on reset:

Any other reset:

7 0 0 0 6 0 0 0

= Reserved 5 0 0 U 4 PDF 0 U 3 0 0 0 2 0 PPDACK 0 0 1 PDC(1) 0 0 U = Unaffected by reset 0 0 0 0 1. This bit can be written only one time after reset. Additional writes are ignored. Figure 25. System Power Management Status and Control 2 Register (SPMSC2) Table 29. SPMSC2 Register Field Descriptions Field 7:5 Reserved 4 PDF 3 Reserved 2 PPDACK 1 PDC 0 Reserved Description Reserved Bits These bits are reserved should not be altered by the user. Any read returns a logical zero. Power Down Flag This read-only status bit indicates the MCU has recovered from STOP1 mode. 0 MCU has not recovered from STOP1 mode 1 MCU recovered from STOP1 mode Reserved Bit This bit is reserved should not be altered by the user. Any read returns a logical zero. Partial Power Down Acknowledge Writing a logic 1 to PPDACK clears the PDF bit. Power Down Control The PDC bit controls entry into the power down (STOP1) mode 0 Power down mode are disabled 1 Power down mode are enabled Reserved Bit This bit is reserved should not be altered by the user. Any read returns a logical zero. Any write should be a logical zero. 5.11.6 System Power Management Status and Control 3 Register (SPMSC3)

$180C R W Power-on reset:

LVD reset:

Any other reset:

7 LVWF 0(1) 0(1) 0(1) 6 0 LVWACK 0 0 0

= Reserved 5 4 LVDV LVWV 0 U U 0 U U 3 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 U = Unaffected by reset 1. LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW. Figure 26. System Power Management Status and Control 3 Register (SPMSC3) Table 30. SRTISC Register Field Descriptions Low-Voltage Warning Flag The LVWF bit indicates the low voltage warning status. 0 Low voltage warning not present 1 Low voltage warning is present or was present Description Field 7 LVWF FXTH870x6 44 Sensors Freescale Semiconductor, Inc. Table 30. SRTISC Register Field Descriptions (continued) Field 6 LVWACK 5 LVDV 4 LVWV 3:0 Reserved Description Low-Voltage Warning Acknowledge The LVWF bit indicates the low voltage warning status. Writing a logic 1 to LVWACK clears LVWF to a logic 0 if a low voltage warning is not present. Low-Voltage Detect Voltage Select The LVDV bit selects the LVD trip point voltage (VLVD). 0 Low trip point selected (VLVD = VLVDL) 1 High trip point selected (VLVD = VLVDH) Low-Voltage Warning Voltage Select The LVWV bit selects the LVW trip point voltage (VLVW). 0 Low trip point selected (VLVW = VLVDL) 1 High trip point selected (VLVW = VLVDH) Reserved Bits These bits are reserved should not be altered by the user. Any read returns a logical zero. System STOP Exit Status Register (SIMSES) 5.12 The SIMSES register at $180D can be used to determine the source of an MCU wakeup from the STOP modes. The flags are as shown in Figure 27. All of the flags are automatically cleared when the MCU goes into a STOP mode. Writes to any of these bits are ignored.

$180D Bit 7 R W RESET:

0 Reserved 6 0

= Reserved 5 KBF 0 4 IRQF 0 3 TRF 0 2 PWUF 0 1 LFF 0 Bit 0 RFF 0 Figure 27. SIM STOP Exit Status (SIMSES) Table 31. SIMSES Register Field Descriptions Field 7:6 Reserved 5 KBF 4 IRQF 3 TRF 2 PWUF 1 LFF 0 RFF Description Reserved Bits These bits are reserved for Freescale firmware control. Application software shall assure these two bits are never overwritten. Keyboard Flag This bit indicates that any keyboard pin caused the last exit from STOP mode. 0 Keyboard pin did not cause the last exit from STOP mode 1 Keyboard pin caused the last exit from STOP mode IRQ Flag This bit indicates that IRQ pin caused the last exit from STOP mode. 0 IRQ pin did not cause the last exit from STOP mode 1 IRQ pin caused the last exit from STOP mode Temperature Restart Flag This bit indicates that the temperature restart module caused the last exit from STOP mode. 0 TR module did not cause the last exit from STOP mode 1 TR module caused the last exit from STOP mode PWU Flag This bit indicates that the PWU module caused the last exit from STOP mode. 0 PWU module did not cause the last exit from STOP mode 1 PWU module caused the last exit from STOP mode LFR Flag This bit indicates that the LFR module caused the last exit from STOP mode. 0 LFR module did not cause the last exit from STOP mode 1 LFR module caused the last exit from STOP mode RFM Flag This bit indicates that the RFM module caused the last exit from STOP mode. 0 RFM module did not cause the last exit from STOP mode 1 RFM module caused the last exit from STOP mode Sensors Freescale Semiconductor, Inc. FXTH870x6 45 General Purpose I/O 6 This section explains software controls related to general purpose input/output (I/O) and pin control. The FXTH870x6 has seven general-purpose I/O pins which are comprised of a general use 5-bit port A and a 2-bit port B. PTA[4:0] pins are shared with on-chip peripheral functions. PTB[1:0] pins are GPIO only and are mutually exclusive with the LF receiver, such that PTB[1:0] pins become high impedance when the LF is enabled (see Section 6.5 for additional details regarding mutually exclusive operations). The peripheral modules have priority over the general purpose I/O so that when a peripheral is enabled, the general purpose I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are controlled by the general purpose I/O. All of the general purpose I/O are configured as inputs (PTxDDn = 0) with pullup devices disabled (PTxPEn = 0). To avoid extra current drain from floating input pins, the users application software must configure these pins so that they do not float (see Section 6.1). Reading and writing of general purpose I/O is performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers. The general purpose I/O port function for an individual pin is illustrated in the block diagram in Figure 28. PTxDDn QD PTxDn QD Output Enable Output Data Port Read Data BUSCLKS 1 0 Synchronizer Input Data Figure 28. General Purpose I/O Block Diagram FXTH870x6 46 Sensors Freescale Semiconductor, Inc. PTA[3:0]

only KBEDEy KBIPGy PTxPEn PTxDDn Write PTxDn Read PTxDn KBI interrupt KBACK KBMOD PTA[3:0]

only KBEDGy KBIPEy PTxPEn VDD RPU Port pin RPD Figure 29. General Purpose I/O Logic Table 32. Truth Table for Pullup and Pulldown Resistors PTAPE[3:0]

(pull enable) PTADD[3:0]

(data direction) KBIPE[3:0]

(KBI pin enable) KBEDG[3:0]

(KBI Edge Select) 0 1 x 1 1 0 0 1 0 0 PTBPE[1:0]

(pull enable) PTBDD[1:0]

(data direction) 0 1 x 0 0 1 x 0 x 1 1 x x x x x x 0 1 x x x Pullup disabled enabled disabled enabled disabled disabled enabled disabled Pulldown disabled disabled disabled disabled enabled x x x The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function. When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data direction register bit still controls the source for reads of the port data register. When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. Sensors Freescale Semiconductor, Inc. FXTH870x6 47 An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers

(PTxPEn). The pullup device is disabled if the pin is configured as an output by the general purpose I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function. Unused Pin Configuration 6.1 Any general purpose I/O pins which are not used in the application must be properly configured to avoid a floating input that could cause excessive supply current, IDD. When the device comes out of the reset state the Freescale supplied firmware will not configure any of the general purpose I/O pins. Recommended configuration methods are:

1. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the pin connected to the VDD source; use a pullup resistor of 10-51 k to assure sufficient noise immunity. 2. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the internal pullup activated (PTxPEn = 1) and leave the pin disconnected. 3. Configure the general purpose I/O pin as an output (PTxDDn = 1) and drive the pin low (PTxDn = 0) and leave the pin disconnected. In cases where GPIOs are directly connected to AVDD, VDD, AVSS, VSS or RVSS, user application should configure the GPIO as an input with the internal pull-up disabled, in order to prevent software code faults from causing excessive supply current states should these pins become outputs. Pin Behavior in STOP Modes 6.2 Pin behavior following execution of a STOP instruction depends on the STOP mode that is entered. An explanation of pin behavior for the various STOP modes follows:

In STOP1 mode, all internal registers including general purpose I/O control and data registers are powered off. Each of the pins assumes its default reset state (input buffer, output buffer and internal pullup disabled). Upon exit from STOP1, all pins must be reconfigured the same as if the MCU had been reset. In STOP4 mode, all pin states are maintained because internal logic stays powered up. Upon recovery, all pin functions are the same as before entering STOP4. General Purpose I/O Registers 6.3 This section provides information about the registers associated with the general purpose I/O ports and pin control functions. These general purpose I/O registers are located in page zero of the memory map and the pin control registers are located in the high page register section of memory. 6.4 Port A general purpose I/O function is controlled by the registers described in this section. Port A Registers

$0000 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 PTAD[4:0]

0 1 0 Bit 0 0 Figure 30. Port A Data Register (PTAD) FXTH870x6 48 Sensors Freescale Semiconductor, Inc. Table 33. Port A Data Register Field Descriptions Field 4:0 PTAD

[4:0]

Description Port A Data Register Bit For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.

$0001 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 PTAPE[3:0]

1 0 Bit 0 0 Figure 31. Internal Pullup Enable for Port A Register (PTAPE) Table 34. Port A Register Pullup Enable Field Descriptions Field 3:0 PTAPE

[3:0]

Description Internal Pullup Enable for Port A Bit n Each of these control bits determines if the internal pullup device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port A bit n. 1 Internal pullup device enabled for port A bit n.

$0003 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 PTADD[3:0]

1 0 Bit 0 0 Figure 32. Data Direction for Port A Register (PTADD) Table 35. Port A Data Direction Field Descriptions Field 3:0 PTADD

[3:0]

Data Direction for Port A Bit n These read/write bits control the direction of port A pins and what is read for PTADD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTADD reads return the contents of PTADDn. PTA4 is input-only, therefore bit 4 will always be 0. Description Port B Registers 6.5 Port B PTB[1:0] functions are multiplexed with the LF receiver block such that the port B GPIOs become high impedance when the LF block has been enabled. When the LF block is disabled, port B pins operate as described here.

$0004 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 1 0 PTBD[1:0]

Bit 0 0 Figure 33. Port B Data Register (PTBD) Sensors Freescale Semiconductor, Inc. FXTH870x6 49 Table 36. Port B Data Register Field Descriptions Field 1:0 PTBD

[1:0]

Description Port B Data Register Bit n For port B pins that are inputs, reads return the logic level on the pin. For port B pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled.

$0005 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 1 0 Bit 0 PTBPE[1:0]

0 Figure 34. Internal Pullup Enable for Port B Register (PTBPE) Table 37. Port B Register Pullup Enable Field Descriptions Field 1:0 PTBPE

[1:0]

Description Internal Pullup Enable for Port B Bit n Each of these control bits determines if the internal pullup device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pullup device disabled for port B bit n. 1 Internal pullup device enabled for port B bit n.

$0007 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 1 0 Bit 0 PTBDD[1:0]

0 Figure 35. Data Direction for Port B Register (PTBDD) Table 38. Port B Data Direction Field Descriptions Field 1:0 PTBDD

[1:0]

Data Direction for Port B Bit n These read/write bits control the direction of port B pins and what is read for PTBDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBDD reads return the contents of PTBDDn. Description FXTH870x6 50 Sensors Freescale Semiconductor, Inc. Keyboard Interrupt 7 The FXTH870x6 has a KBI module with general purpose I/O pins. 7.1 Features The KBI features include:

Up to four keyboard interrupt pins with individual pin enable bits. Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. One software enabled keyboard interrupt. Exit from low-power modes. KBI in STOP Modes Modes of Operation 7.2 This section defines the KBI operation in WAIT, STOP, and BACKGROUND DEBUG modes. 7.2.1 The KBI operates asynchronously in STOP4 mode if enabled before executing the STOP instruction. Therefore, an enabled KBI pin (KBPE[3:0]) can be used to bring the MCU out of STOP4 mode if the KBI interrupt is enabled (KBIE = 1). During STOP1 mode, the KBI is disabled. In some systems, the pins associated with the KBI may be sources of wakeup from STOP1, see the STOP modes section in the Section 3. Upon wakeup from STOP1 mode, the KBI module will be in the reset state. 7.2.2 When the microcontroller is in ACTIVE BACKGROUND mode, the KBI will continue to operate normally. KBI in ACTIVE BACKGROUND mode 7.3 The block diagram for the keyboard interrupt module is shown Figure 36. Block Diagram KBIPE0 VDD Q CLR D CK KBACK RESET BUSCLK KBF SYNCHRONIZER KEYBOARD INTERRUPT FF STOP STOP BYPASS KBI INTERRUP KBIPEn KBMOD KBIE 1 0 S 1 0 S KBIP0 KBEDG0 KBIPn KBEDGn Figure 36. KBI Block Diagram External Signal Description 7.4 The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. PTA[3:0] map to KBIPE and KBEDG function bits [3:0]. The signal properties of KBI are shown in Table 39. Table 39. Signal Properties Signal KBIPn Function Keyboard interrupt pins I/O I Sensors Freescale Semiconductor, Inc. FXTH870x6 51 Register Definitions 7.5 The KBI includes three registers:

7.5.1 KBISC contains the status flag and control bits, which are used to configure the KBI. An 4-bit pin status and control register. An 4-bit pin enable register. An 4-bit edge select register. KBI Status and Control Register (KBISC)

$000C R W Reset:

7 0 0 6 0 0

= Reserved 5 0 0 4 0 0 3 KBF 0 2 0 KBACK 0 1 0 KBIE KBMOD 0 0 Figure 37. KBI Status and Control Register Table 40. KBISC Register Field Descriptions Field 7:4 3 KBF 2 KBACK 1 KBIE 0 KBMOD Unused register bits, always read 0. Keyboard Interrupt Flag KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected. Description Keyboard Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads as 0. Keyboard Interrupt Enable KBIE determines whether a keyboard interrupt is requested. 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. Keyboard Detection Mode KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins. 0 Keyboard detects edges only. 1 Keyboard detects both edges and levels. KBI Pin Enable Register (KBIPE) 7.5.2 KBIPE contains the pin enable control bits.

$000D R W Reset:

7 0 6 0 5 0 4 0 3 2 1 0 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 Figure 38. KBI Pin Enable Register Table 41. KBIPE Register Field Descriptions Field 3:0 KBIPEn FXTH870x6 52 Keyboard Pin Enables Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. Description Sensors Freescale Semiconductor, Inc. KBI Edge Select Register (KBIES) 7.5.3 KBIES contains the edge select control bits.

$000E R W Reset:

7 0 6 0 5 0 4 0 3 2 1 0 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0 0 0 0 Figure 39. KBI Edge Select Register Table 42. KBIES Register Field Descriptions Field 3:0 KBEDGn Keyboard Edge Selects Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level. Description Edge Only Sensitivity Functional Description 7.6 This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from STOP or WAIT low-power modes. The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPE[3:0] bits in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDG[3:0] bits in the keyboard interrupt edge select register (KBIES). Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at the reset logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the reset level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 7.6.1 A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC. 7.6.2 A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC provided all enabled keyboard inputs are at their reset levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 7.6.3 The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the resistor is a pullup (KBEDG[3:0] = 0) or a pulldown (KBEDG[3:0] = 1). 7.6.4 When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user should do the following:

KBI Pullup/Pulldown Resistors Edge and Level Sensitivity KBI Initialization If using internal pullup/pulldown device, configure the associated pullup enable bits in PTAPE[3:0]. 1. Mask keyboard interrupts by clearing KBIE in KBISC. 2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES. 3. 4. Enable the KBI pins by setting the appropriate KBIPE[3:0] bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. Sensors Freescale Semiconductor, Inc. FXTH870x6 53 8 Central Processing Unit Introduction 8.1 This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new BACKGROUND DEBUG system which replaces the monitor mode of earlier M68HC08 microcontrollers (MCU). Features 8.2 Features of the HCS08 CPU include:

Many instructions treat X as a second general-purpose 8-bit register Object code fully upward-compatible with M68HC05 and M68HC08 Families All registers and memory are mapped to a single 64-Kbyte address space 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) 16-bit index register (H:X) with powerful indexed addressing modes 8-bit accumulator (A) Seven addressing modes:

Inherent Operands in internal registers Relative 8-bit signed offset to branch destination Immediate Operand in next object code byte(s) Direct Operand in memory at 0x00000x00FF Extended Operand anywhere in 64-Kbyte address space Indexed relative to H:X Five submodes including auto-increment Indexed relative to SP Improves C efficiency dramatically Memory-to-memory data move instructions with four address mode combinations Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations Efficient bit manipulation instructions Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions STOP and WAIT instructions to invoke low-power operating modes FXTH870x6 54 Sensors Freescale Semiconductor, Inc. 8.3 Figure 40 shows the five CPU registers. CPU registers are not part of the memory map. Programmers Model and CPU Registers 7 0 ACCUMULATOR 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 15 8 INDEX REGISTER (LOW) 0 7 STACK POINTER 15 PROGRAM COUNTER CONDITION CODE REGISTER 7 V 1 1 H I N Z 0 0 C A X SP PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWOS COMPLEMENT OVERFLOW Figure 40. CPU Registers Accumulator (A) Index Register (H:X) 8.3.1 The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after arithmetic and logical operations. The accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 8.3.2 This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect on the contents of X. 8.3.3 This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM

(from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer. Stack Pointer (SP) Sensors Freescale Semiconductor, Inc. FXTH870x6 55 Program Counter (PC) 8.3.4 The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state. 8.3.5 The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Condition Code Register (CCR) CONDITION CODE REGISTER 7 V 1 1 H I N Z 0 C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWOS COMPLEMENT OVERFLOW Figure 41. Condition Code Register Table 43. CCR Register Field Descriptions Field Description 7 V 4 H 3 I 2 N 1 Z Twos Complement Overflow Flag The CPU sets the overflow flag when a twos complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-

carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 Interrupt Mask Bit When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the most significant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result FXTH870x6 56 Sensors Freescale Semiconductor, Inc. Table 43. CCR Register Field Descriptions (continued) Field 0 C Description Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions such as bit test and branch, shift, and rotate also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 Addressing Modes Relative Addressing Mode (REL) Immediate Addressing Mode (IMM) 8.4 Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space. Some instructions use more than one addressing mode. For instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 8.4.1 Inherent Addressing Mode (INH) In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands. 8.4.2 Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit offset value is located in the memory location immediately following the opcode. During execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 8.4.3 In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 8.4.4 In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x00000x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit address for the operand. 8.4.5 In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.4.6 Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 8.4.6.1 This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. 8.4.6.2 This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of the operand needed to complete the instruction. The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions. Extended Addressing Mode (EXT) Direct Addressing Mode (DIR) Indexed, No Offset with Post Increment (IX+) Indexed Addressing Mode Indexed, No Offset (IX) Sensors Freescale Semiconductor, Inc. FXTH870x6 57 Indexed, 8-Bit Offset (IX1) Indexed, 8-Bit Offset with Post Increment (IX1+) 8.4.6.3 This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4.6.4 This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. The index register pair is then incremented

(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction. 8.4.6.5 This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4.6.6 This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4.6.7 This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. SP-Relative, 16-Bit Offset (SP2) SP-Relative, 8-Bit Offset (SP1) Indexed, 16-Bit Offset (IX2) Reset Sequence Special Operations 8.5 The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations. 8.5.1 Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to Section 5, Reset, Interrupts and System Configuration. The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction. 8.5.2 When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is:

Interrupt Sequence 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are FXTH870x6 58 Sensors Freescale Semiconductor, Inc. WAIT Mode Operation STOP Mode Operation certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 8.5.3 The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from WAIT mode. When an interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally. If a serial BACKGROUND command is issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in WAIT mode, CPU clocks will resume and the CPU will enter ACTIVE BACKGROUND mode where other serial BACKGROUND commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in WAIT mode. 8.5.4 Usually, all system clocks, including the crystal oscillator (when used), are halted during STOP mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in STOP mode and to issue a signal to wakeup the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in STOP mode. This optionally allows an internal periodic signal to wake the target MCU from STOP mode. When a host debug system is connected to the BACKGROUND DEBUG pin (BKGD) and the ENBDM control bit has been set by a serial command through the BACKGROUND interface (or because the MCU was reset into ACTIVE BACKGROUND mode), the oscillator is forced to remain active when the MCU enters STOP mode. In this case, if a serial BACKGROUND command is issued to the MCU through the BACKGROUND DEBUG interface while the CPU is in STOP mode, CPU clocks will resume and the CPU will enter ACTIVE BACKGROUND mode where other serial BACKGROUND commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in STOP mode. Recovery from STOP mode depends on the particular HCS08 and whether the oscillator was stopped in STOP mode. Refer to the Section 3 for more details. 8.5.5 The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the ACTIVE BACKGROUND mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the BACKGROUND DEBUG interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to ACTIVE BACKGROUND mode rather than continuing the user program. BGND Instruction HCS08 Instruction Set Summary 8.6 Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 44. Operators

( )

&

|

:

+

=

=

=

=

=

=

=

=

=

=

Contents of register or memory location shown inside parentheses Is loaded with (read: gets) Boolean AND Boolean OR Boolean exclusive-OR Multiply Divide Concatenate Add Negate (twos complement) CPU registers A

=

CCR =

H

=

Accumulator Condition code register Index register, higher order (most significant) 8 bits Sensors Freescale Semiconductor, Inc. FXTH870x6 59 X PC PCH PCL SP

=

=

=

=

=

Index register, lower order (least significant) 8 bits Program counter Program counter, higher order (most significant) 8 bits Program counter, lower order (least significant) 8 bits Stack pointer Memory and addressing M M:M + 0x0001

=

=

A memory location or absolute data, depending on addressing mode A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher sequential address. Condition code register (CCR) bits V H I N Z C

=

=

=

=

=

=

Twos complement overflow indicator, bit 7 Half carry, bit 4 Interrupt mask, bit 3 Negative indicator, bit 2 Zero indicator, bit 1 Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation 0 1 U

=

=

=

=

=

Bit not affected Bit forced to 0 Bit forced to 1 Bit set or cleared according to results of operation Undefined after the operation Machine coding notation

=

=

=

=

=

=

=

=

=

Low-order 8 bits of a direct address 0x00000x00FF (high byte assumed to be 0x00) Upper 8 bits of 16-bit offset Lower 8 bits of 16-bit offset or 8-bit offset One byte of immediate data High-order byte of a 16-bit immediate data value Low-order byte of a 16-bit immediate data value High-order byte of 16-bit extended address Low-order byte of 16-bit extended address Relative offset dd ee ff ii jj kk hh ll rr Source form Everything in the source forms columns, except expressions in italic characters, is literal information that must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs

(#), parentheses, and plus signs (+) are literal characters. Any label or expression that evaluates to a single integer in the range 07 Any label or expression that evaluates to an 8-bit immediate value Any label or expression that evaluates to a 16-bit immediate value Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit value as the low order 8 bits of an address in the direct page of the 64-Kbyte address space (0x00xx). Any label or expression that evaluates to a 16-bit value. The instruction treats this value as an address in the 64-Kbyte address space. Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit address bus, this can be either a signed or an unsigned value. Any label or expression that refers to an address that is within 128 to +127 locations from the next address after the last byte of object code for the current instruction. The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. n opr8i opr16i opr8a opr16a oprx8 oprx16 rel FXTH870x6 60 Sensors Freescale Semiconductor, Inc. Address modes INH

=

IMM =

DIR

=

=

EXT

=

IX IX+

=

=

IX1 IX1+

=

IX2 REL SP1 SP2

=

=

=

=

Inherent (no operands) 8-bit or 16-bit immediate 8-bit direct 16-bit extended 16-bit indexed no offset 16-bit indexed no offset, post increment (CBEQ and MOV only) 16-bit indexed with 8-bit offset from H:X 16-bit indexed with 8-bit offset, post increment

(CBEQ only) 16-bit indexed with 16-bit offset from H:X 8-bit relative offset Stack pointer with 8-bit offset Stack pointer with 16-bit offset Table 44. HCS08 Instruction Set Summary (Sheet 1 of 8) Source Form ADC #opr8i ADC opr8a ADC opr16a ADC oprx16,X ADC oprx8,X ADC ,X ADC oprx16,SP ADC oprx8,SP ADD #opr8i ADD opr8a ADD opr16a ADD oprx16,X ADD oprx8,X ADD ,X ADD oprx16,SP ADD oprx8,SP AIS #opr8i AIX #opr8i AND #opr8i AND opr8a AND opr16a AND oprx16,X AND oprx8,X AND ,X AND oprx16,SP AND oprx8,SP ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M Add with Carry A (A) + (M) + (C) Add without Carry A (A) + (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 Add Immediate Value

(Signed) to Stack Pointer Add Immediate Value

(Signed) to Index Register (H:X) SP (SP) + (M) M is sign extended to a 16-bit value H:X (H:X) + (M) M is sign extended to a 16-bit value IMM IMM Logical AND A (A) & (M) 0 Arithmetic Shift Left

(Same as LSL) C b7 b0 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 Sensors Freescale Semiconductor, Inc. e d o c p O A9 B9 C9 D9 E9 F9 9ED9 9EE9 AB BB CB DB EB FB 9EDB 9EEB d n a r e p O ii dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff A7 ii AF ii A4 B4 C4 D4 E4 F4 9ED4 9EE4 38 48 58 68 78 9E68 ii dd hh ll ee ff ff ee ff ff dd ff ff

) 1

(

s e l c y C s u B 2 3 4 4 3 3 5 4 2 3 4 4 3 3 5 4 2 2 2 3 4 4 3 3 5 4 5 1 1 5 4 6 FXTH870x6 61 Table 44. HCS08 Instruction Set Summary (Sheet 2 of 8) Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M e d o c p O d n a r e p O Source Form ASR opr8a ASRA ASRX ASR oprx8,X ASR ,X ASR oprx8,SP BCC rel Arithmetic Shift Right b7 C b0 Branch if Carry Bit Clear Branch if (C) = 0 DIR INH INH IX1 IX SP1 REL BCLR n,opr8a Clear Bit n in Memory Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) l

) 1

(

s e c y C s u B 5 1 1 5 4 6 3 5 5 5 5 5 5 5 5 dd ff 37 47 57 67 77 9E67 ff 24 rr 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd Branch if Carry Bit Set

(Same as BLO) Branch if Equal Branch if Greater Than or Equal To

(Signed Operands) Enter ACTIVE BACK-

GROUND if ENBDM = 1 Branch if Greater Than

(Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same

(Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low Bit Test Branch if Less Than or Equal To

(Signed Operands) Branch if Lower

(Same as BCS) Branch if Lower or Same Branch if Less Than

(Signed Operands) Branch if Interrupt Mask Clear BCS rel BEQ rel BGE rel BGND BGT rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr8i BIT opr8a BIT opr16a BIT oprx16,X BIT oprx8,X BIT ,X BIT oprx16,SP BIT oprx8,SP BLE rel BLO rel BLS rel BLT rel BMC rel FXTH870x6 62 Branch if (C) = 1 REL Branch if (Z) = 1 REL Branch if (N V REL 25 rr 27 rr 90 rr 3 3 3 Waits For and Processes BDM Commands Until GO, TRACE1, or TAGGO INH 82 5+

Branch if (Z)| (N V REL Branch if (H) = 0 REL Branch if (H) = 1 REL Branch if (C) | (Z) = 0 REL Branch if (C) = 0 REL Branch if IRQ pin = 1 Branch if IRQ pin = 0

(A) & (M)

(CCR Updated but Operands Not Changed) REL REL IMM DIR EXT IX2 IX1 IX SP2 SP1 0 Branch if (Z)| (N V 1 REL Branch if (C) = 1 REL Branch if (C) | (Z) = 1 REL Branch if (N V 1 REL Branch if (I) = 0 REL 92 rr 28 rr 29 rr 22 rr 24 rr 2F rr 2E rr A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 9ED5 9EE5 ee ff ff 93 rr 25 rr 23 rr 91 rr 2C rr 3 3 3 3 3 3 3 2 3 4 4 3 3 5 4 3 3 3 3 3 Sensors Freescale Semiconductor, Inc. Table 44. HCS08 Instruction Set Summary (Sheet 3 of 8) Source Form Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M e d o c p O d n a r e p O BMI rel BMS rel BNE rel BPL rel BRA rel Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if (N) = 1 Branch if (I) = 1 Branch if (Z) = 0 Branch if (N) = 0 No Test REL REL REL REL REL BRCLR n,opr8a,rel Branch if Bit n in Memory Clear Branch if (Mn) = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never Uses 3 Bus Cycles REL BRSET n,opr8a,rel Branch if Bit n in Memory Set Branch if (Mn) = 1 BSET n,opr8a Set Bit n in Memory Mn 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 2B rr 2D rr 26 rr 2A rr 20 rr 01 03 05 07 09 0B 0D 0F 21 rr 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd PC (PC) + 0x0002 push (PCL); SP (SP) 0x0001 push (PCH); SP (SP) 0x0001 PC (PC) + rel Branch if (A) = (M) Branch if (A) = (M) Branch if (X) = (M) Branch if (A) = (M) Branch if (A) = (M) Branch if (A) = (M) C 0 I 0 M 0x00 A 0x00 X 0x00 H 0x00 M 0x00 M 0x00 M 0x00 REL AD rr DIR IMM IMM IX1+

IX+

SP1 0 INH 0 INH DIR INH INH INH IX1 IX SP1 0 0 1 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F dd rr ii rr ii rr ff rr rr ff rr dd ff ff BSR rel Branch to Subroutine CBEQ opr8a,rel CBEQA #opr8i,rel CBEQX #opr8i,rel CBEQ oprx8,X+,rel CBEQ ,X+,rel CBEQ oprx8,SP,rel CLC CLI CLR opr8a CLRA CLRX CLRH CLR oprx8,X CLR ,X CLR oprx8,SP Compare and Branch if Equal Clear Carry Bit Clear Interrupt Mask Bit Clear Sensors Freescale Semiconductor, Inc. l

) 1

(

s e c y C s u B 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 5 5 6 1 1 5 1 1 1 5 4 6 FXTH870x6 63 Source Form CMP #opr8i CMP opr8a CMP opr16a CMP oprx16,X CMP oprx8,X CMP ,X CMP oprx16,SP CMP oprx8,SP COM opr8a COMA COMX COM oprx8,X COM ,X COM oprx8,SP CPHX opr16a CPHX #opr16i CPHX opr8a CPHX oprx8,SP CPX #opr8i CPX opr8a CPX opr16a CPX oprx16,X CPX oprx8,X CPX ,X CPX oprx16,SP CPX oprx8,SP DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP Table 44. HCS08 Instruction Set Summary (Sheet 4 of 8) Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M 0 1 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 EXT IMM DIR SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1

(CCR Updated But Operands Not

(A) (M) Changed) M (M)= 0xFF (M) A (A) = 0xFF (A) X (X) = 0xFF (X) M (M) = 0xFF (M) M (M) = 0xFF (M) M (M) = 0xFF (M)

(H:X) (M:M + 0x0001)

(CCR Updated But Operands Not Changed)

(CCR Updated But Operands Not

(X) (M) Changed) Compare Accumulator with Memory Complement

(Ones Complement) Compare Index Register

(H:X) with Memory Compare X (Index Register Low) with Memory Decimal Adjust Accumulator After ADD or ADC of BCD Values Decrement and Branch if Not Zero Decrement A, X, or M Branch if (result) 0 DBNZX Affects X Not H Decrement

(A)10 U INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 M (M) 0x01 A (A) 0x01 X (X) 0x01 M (M) 0x01 M (M) 0x01 M (M) 0x01 A (H:A)(X) H Remainder INH A (A M) 0 M (M) + 0x01 A (A) + 0x01 X (X) + 0x01 M (M) + 0x01 M (M) + 0x01 M (M) + 0x01 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIV Divide Exclusive OR Memory with Accumulator Increment EOR #opr8i EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP FXTH870x6 64 e d o c p O A1 B1 C1 D1 E1 F1 9ED1 9EE1 33 43 53 63 73 9E63 3E 65 75 9EF3 A3 B3 C3 D3 E3 F3 9ED3 9EE3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 A8 B8 C8 D8 E8 F8 9ED8 9EE8 3C 4C 5C 6C 7C 9E6C d n a r e p O ii dd hh ll ee ff ff ee ff ff dd ff ff hh ll jj kk dd ff ii dd hh ll ee ff ff ee ff ff dd rr rr rr ff rr rr ff rr dd ff ff ii dd hh ll ee ff ff ee ff ff dd ff ff l

) 1

(

s e c y C s u B 2 3 4 4 3 3 5 4 5 1 1 5 4 6 6 3 5 6 2 3 4 4 3 3 5 4 1 7 4 4 7 6 8 5 1 1 5 4 6 6 2 3 4 4 3 3 5 4 5 1 1 5 4 6 Sensors Freescale Semiconductor, Inc. Table 44. HCS08 Instruction Set Summary (Sheet 5 of 8) Source Form JMP opr8a JMP opr16a JMP oprx16,X JMP oprx8,X JMP ,X JSR opr8a JSR opr16a JSR oprx16,X JSR oprx8,X JSR ,X LDA #opr8i LDA opr8a LDA opr16a LDA oprx16,X LDA oprx8,X LDA ,X LDA oprx16,SP LDA oprx8,SP LDHX #opr16i LDHX opr8a LDHX opr16a LDHX ,X LDHX oprx16,X LDHX oprx8,X LDHX oprx8,SP LDX #opr8i LDX opr8a LDX opr16a LDX oprx16,X LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP MOV opr8a,opr8a MOV opr8a,X+

MOV #opr8i,opr8a MOV ,X+,opr8a MUL NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP NOP Operation Description Effect on CCR V H I N Z C Jump PC Jump Address Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) 0x0001 Push (PCH); SP (SP) 0x0001 PC Unconditional Address Load Accumulator from Memory A (M) 0 Load Index Register

(H:X) from Memory H:X M:M+ 0x0001 0 Load X (Index Register Low) from Memory X (M) 0 Logical Shift Left

(Same as ASL) Logical Shift Right Move Unsigned multiply Negate

(Twos Complement) No Operation C b7 0 b7 0 C b0 b0

(M)destination (M)source H:X (H:X) + 0x0001 in IX+/DIR and DIR/IX+ Modes X:A (X) (A) M (M) = 0x00 (M) A (A) = 0x00 (A) X (X) = 0x00 (X) M (M) = 0x00 (M) M (M) = 0x00 (M) M (M) = 0x00 (M) Uses 1 Bus Cycle 0 0 0 0 INH DIR INH INH IX1 IX SP1 INH s s e r d d A e d o M DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX IX2 IX1 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DIR/DIR DIR/IX+

IMM/DIR IX+/DIR d n a r e p O dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ee ff ff jj kk dd hh ll ee ff ff ff ii dd hh ll ee ff ff ee ff ff dd ff ff dd ff ff dd dd dd ii dd dd dd ff ff e d o c p O BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9ED6 9EE6 45 55 32 9EAE 9EBE 9ECE 9EFE AE BE CE DE EE FE 9EDE 9EEE 38 48 58 68 78 9E68 34 44 54 64 74 9E64 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D l

) 1

(

s e c y C s u B 3 4 4 3 3 5 6 6 5 5 2 3 4 4 3 3 5 4 3 4 5 5 6 5 5 2 3 4 4 3 3 5 4 5 1 1 5 4 6 5 1 1 5 4 6 5 5 4 5 5 5 1 1 5 4 6 1 Sensors Freescale Semiconductor, Inc. FXTH870x6 65 Table 44. HCS08 Instruction Set Summary (Sheet 6 of 8) Source Form NSA ORA #opr8i ORA opr8a ORA opr16a ORA oprx16,X ORA oprx8,X ORA ,X ORA oprx16,SP ORA oprx8,SP PSHA PSHH PSHX PULA PULH PULX ROL opr8a ROLA ROLX ROL oprx8,X ROL ,X ROL oprx8,SP ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP RSP RTI RTS SBC #opr8i SBC opr8a SBC opr16a SBC oprx16,X SBC oprx8,X SBC ,X SBC oprx16,SP SBC oprx8,SP SEC SEI FXTH870x6 66 Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M e d o c p O d n a r e p O l

) 1

(

s e c y C s u B Nibble Swap Accumulator A (A[3:0]:A[7:4]) INH Inclusive OR Accumulator and Memory A (A) | (M) 0 IMM DIR EXT IX2 IX1 IX SP2 SP1 Push Accumulator onto Stack Push H (Index Register High) onto Stack Push X (Index Register Low) onto Stack Pull Accumulator from Stack Pull H (Index Register High) from Stack Pull X (Index Register Low) from Stack Push (A); SP (SP) 0x0001 INH Push (H); SP (SP) 0x0001 INH Push (X); SP (SP) 0x0001 INH SP (SP + 0x0001); PullA INH SP (SP + 0x0001); PullH INH SP (SP + 0x0001); PullX INH Rotate Left through Carry C b7 b0 Rotate Right through Carry b7 C b0 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 Reset Stack Pointer SP 0xFF

(High Byte Not Affected) INH Return from Interrupt Return from Subroutine SP (SP) + 0x0001; Pull (CCR) SP (SP) + 0x0001; Pull (A) SP (SP) + 0x0001; Pull (X) SP (SP) + 0x0001; Pull (PCH) SP (SP) + 0x0001; Pull (PCL) SP SP + 0x0001PullPCH) SP SP + 0x0001; Pull (PCL) Subtract with Carry A (A) (M) (C) Set Carry Bit Set Interrupt Mask Bit C 1 I 1 INH INH IMM DIR EXT IX2 IX1 IX SP2 SP1 1 INH 1 INH 62 AA BA CA DA EA FA 9EDA 9EEA ii dd hh ll ee ff ff ee ff ff 87 8B 89 86 8A 88 dd ff ff dd ff ff 39 49 59 69 79 9E69 36 46 56 66 76 9E66 9C 80 81 A2 B2 C2 D2 E2 F2 9ED2 9EE2 99 9B ii dd hh ll ee ff ff ee ff ff 1 2 3 4 4 3 3 5 4 2 2 2 3 3 3 5 1 1 5 4 6 5 1 1 5 4 6 1 9 6 2 3 4 4 3 3 5 4 1 1 Sensors Freescale Semiconductor, Inc. Table 44. HCS08 Instruction Set Summary (Sheet 7 of 8) Source Form STA opr8a STA opr16a STA oprx16,X STA oprx8,X STA ,X STA oprx16,SP STA oprx8,SP STHX opr8a STHX opr16a STHX oprx8,SP STOP STX opr8a STX opr16a STX oprx16,X STX oprx8,X STX ,X STX oprx16,SP STX oprx8,SP SUB #opr8i SUB opr8a SUB opr16a SUB oprx16,X SUB oprx8,X SUB ,X SUB oprx16,SP SUB oprx8,SP Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M Store Accumulator in Memory M (A) 0 Store H:X (Index Reg.)

(M:M + 0x0001) (H:X) 0 DIR EXT IX2 IX1 IX SP2 SP1 DIR EXT SP1 e d o c p O B7 C7 D7 E7 F7 9ED7 9EE7 35 96 9EFF d n a r e p O dd hh ll ee ff ff ee ff ff dd hh ll ff l

) 1

(

s e c y C s u B 3 4 4 3 2 5 4 4 5 5 I bit 0; Stop Processing 0 INH 8E 2+

Enable Interrupts:

Stop Processing Refer to MCU Documen-

tation Store X (Low 8 Bits of Index Register) in Memory M (X) 0 DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 BF CF DF EF FF 9EDF 9EEF A0 B0 C0 D0 E0 F0 9ED0 9EE0 dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 2 3 4 4 3 3 5 4 Subtract A (A) (M) SWI Software Interrupt TAP TAX TPA TST opr8a TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP TSX TXA TXS Transfer Accumulator to CCR Transfer Accumulator to X (Index Register Low) Transfer CCR to Accu-

mulator Test for Negative or Zero Transfer SP to Index Reg. Transfer X (Index Reg. Low) to Accumulator Transfer Index Reg. to SP Sensors Freescale Semiconductor, Inc. PC (PC) + 0x0001 Push (PCL); SP (SP) 0x0001 Push (PCH); SP (SP) 0x0001 Push (X); SP (SP) 0x0001 Push (A); SP (SP) 0x0001 Push (CCR); SP (SP) 0x0001 I 1;

PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte 1 INH 83 11 CCR (A) INH X (A) INH A (CCR)

(M) 0x00

(A) 0x00

(X) 0x00

(M) 0x00

(M) 0x00

(M) 0x00 INH 0 DIR INH INH IX1 IX SP1 H:X (SP) + 0x0001 INH A (X) INH SP (H:X) 0x0001 INH 84 97 85 3D 4D 5D 6D 7D 9E6D dd ff ff 95 9F 94 1 1 1 4 1 1 4 3 5 2 1 2 FXTH870x6 67 31 5 CBEQ DIR 3 32 5 LDHX 3 EXT 4 41 CBEQA IMM 3 42 1 5 MUL INH 4 51 CBEQX IMM 3 52 1 6 DIV INH 61 5 CBEQ IX1+

3 62 1 1 NSA INH 71 5 CBEQ IX+

2 72 1 1 DAA INH Table 44. HCS08 Instruction Set Summary (Sheet 8 of 8) Source Form Operation Description Effect on CCR V H I N Z C s s e r d d A e d o M e d o c p O d n a r e p O l

) 1

(

s e c y C s u B WAIT Enable Interrupts; Wait for Interrupt I bit 0; Halt CPU 0 INH 8F 2+

1. Bus clock frequency is one-half of the CPU clock frequency. Table 45. Opcode Map (Sheet 1 of 2) Bit-Manipulation Branch 00 BRSET0 3 DIR 10 5 BSET0 2 DIR 3 BRA REL 20 5 2 30 5 NEG 2 DIR Read-Modify-Write 40 1 NEGA INH 50 1 NEGX INH 60 1 1 2 5 NEG 70 4 NEG IX1 1 IX Control 90 9 RTI INH 2 3 BGE A0 2 SUB B0 3 SUB Register/Memory C0 D0 4 SUB 4 SUB E0 3 SUB F0 3 SUB REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 80 1 81 1 6 RTS INH 82 5+

BGND INH 1 83 1 84 1 85 1 11 SWI INH 1 TAP INH 1 TPA INH 86 3 PULA INH 1 87 2 PSHA INH 1 88 3 PULX INH 1 89 2 PSHX INH 1 8A 3 PULH INH 1 91 2 92 2 93 2 94 1 95 1 3 BLT REL 3 BGT REL 3 BLE REL 2 TXS INH 2 TSX INH 96 5 STHX 3 EXT 97 1 98 1 99 1 1 TAX INH 1 CLC INH 1 SEC INH 9A 1 9B 1 1 CLI INH 1 SEI INH 9C 1 RSP INH 1 1 63 2 5 COM IX1 73 1 4 COM IX 64 2 5 LSR IX1 3 65 CPHX IMM 3 74 1 4 LSR IX 5 75 CPHX DIR 2 66 2 5 ROR IX1 76 1 4 ROR IX 67 2 68 2 69 2 5 ASR IX1 5 LSL IX1 5 ROL IX1 77 1 78 1 79 1 4 ASR IX 4 LSL IX 4 ROL IX 6A 5 DEC 2 7A 4 DEC IX1 1 IX 6B 7 DBNZ IX1 3 7B 6 DBNZ IX 2 6C 2 5 INC IX1 7C 1 4 INC IX 8B 2 PSHH INH 1 8C 1 CLRH INH 1 2 2 2 2 2 2 2 2 A1 2 CMP IMM B1 2 3 CMP DIR C1 3 4 CMP EXT D1 3 4 CMP IX2 E1 2 3 CMP IX1 F1 1 3 CMP IX A2 2 SBC B2 3 SBC C2 4 SBC D2 4 SBC E2 3 SBC F2 3 SBC IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 A3 2 CPX B3 3 CPX C3 4 CPX D3 4 CPX E3 3 CPX F3 3 CPX IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 A4 2 AND B4 3 AND C4 4 AND D4 4 AND E4 3 AND F4 3 AND IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 A5 2 A6 2 A7 2 2 BIT IMM 2 LDA IMM 2 AIS IMM B5 2 B6 2 B7 2 3 BIT DIR 3 LDA DIR 3 STA DIR 3 3 C5 3 4 BIT EXT D5 3 4 BIT IX2 C6 4 LDA D6 4 LDA EXT 3 IX2 C7 4 STA D7 4 STA EXT 3 IX2 E5 2 E6 2 E7 2 3 BIT IX1 3 LDA IX1 3 STA IX1 F5 1 F6 1 F7 1 3 BIT IX 3 LDA IX 2 STA IX A8 2 EOR B8 3 EOR C8 4 EOR D8 4 EOR E8 3 EOR F8 3 EOR IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 A9 2 ADC B9 3 ADC C9 4 ADC D9 4 ADC E9 3 ADC F9 3 ADC IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 AA 2 ORA IMM BA 3 ORA CA 4 ORA DA 4 ORA EA 3 ORA FA 3 ORA 2 DIR 3 EXT 3 IX2 2 IX1 1 AB 2 ADD BB 3 ADD CB 4 ADD DB 4 ADD EB 3 ADD FB 3 ADD IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 BC 3 JMP CC 4 JMP DC 4 JMP EC 3 JMP FC 3 JMP 2 DIR 3 EXT 3 IX2 2 IX1 1 IX IX IX IX IX IX IX IX IX IX 33 2 5 COM DIR 34 2 5 LSR DIR 35 4 STHX DIR 2 36 2 5 ROR DIR 37 2 38 2 39 2 5 ASR DIR 5 LSL DIR 5 ROL DIR 3A 5 DEC 2 DIR 3B 7 DBNZ DIR 3 3C 2 5 INC DIR 43 1 COMA INH 1 53 1 COMX INH 1 44 1 LSRA INH 1 54 1 LSRX INH 1 45 3 LDHX IMM 3 55 4 LDHX DIR 2 46 1 RORA INH 1 56 1 RORX INH 1 47 1 ASRA INH 1 57 1 ASRX INH 1 48 1 1 LSLA INH 58 1 1 LSLX INH 49 1 ROLA INH 1 59 1 ROLX INH 1 4A 1 DECA INH 1 4 4B DBNZA 2 INH 5A 1 DECX INH 1 4 5B DBNZX 2 INH 4C 1 INCA INH 1 4D 1 TSTA INH 4E 3 5 MOV DD 5C 1 INCX INH 1 5D 1 TSTX INH 1 5E 2 5 MOV DIX+

2D 3 BMS 3D 4 TST REL 2 DIR 1 2E 2 2F 2 3 BIL REL 3E 6 CPHX 3 EXT 3 BIH REL 3F 2 5 CLR DIR 6D 4 TST 7D 3 TST IX1 1 IX 9D 1 NOP AD 5 BSR BD 5 JSR CD 6 JSR DD 6 JSR ED 5 JSR FD 5 JSR INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 6E 4 MOV IMD 7E 2 5 MOV IX+D 8E 2+

STOP INH 1 9E Page 2 AE 2 LDX BE 3 LDX CE 4 LDX DE 4 LDX EE 3 LDX FE 3 LDX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 2 3 4F 1 CLRA INH 1 5F 1 CLRX INH 1 6F 2 5 CLR IX1 7F 1 4 CLR IX 8F 2+

WAIT INH 1 9F 1 1 TXA INH AF 2 2 AIX IMM BF 3 STX CF 4 STX DF 4 STX EF 3 STX 2 DIR 3 EXT 3 IX2 2 IX1 2 STX IX 1 FF 1 21 2 22 2 23 2 24 2 25 2 26 2 27 2 3 BRN REL 3 BHI REL 3 BLS REL 3 BCC REL 3 BCS REL 3 BNE REL 3 BEQ REL 28 3 BHCC REL 2 29 3 BHCS REL 2 2A 2 2B 2 3 BPL REL 3 BMI REL 2C 3 BMC REL 2 2 5 01 BRCLR0 DIR 3 11 5 BCLR0 DIR 2 5 02 BRSET1 3 DIR 12 5 BSET1 2 DIR 5 03 BRCLR1 3 DIR 13 5 BCLR1 2 DIR 5 04 BRSET2 3 DIR 14 5 BSET2 2 DIR 5 05 BRCLR2 3 DIR 15 5 BCLR2 2 DIR 5 06 BRSET3 3 DIR 16 5 BSET3 2 DIR 5 07 BRCLR3 3 DIR 17 5 BCLR3 2 DIR 5 08 BRSET4 3 DIR 18 5 BSET4 2 DIR 5 09 BRCLR4 3 DIR 19 5 BCLR4 2 DIR 5 0A BRSET5 3 DIR 1A 5 BSET5 2 DIR 5 0B BRCLR5 3 DIR 1B 5 BCLR5 2 DIR 5 0C BRSET6 3 DIR 1C 5 BSET6 2 DIR 5 0D BRCLR6 3 DIR 1D 5 BCLR6 2 DIR 5 0E BRSET7 3 DIR 1E 5 BSET7 2 DIR 5 0F BRCLR7 3 DIR 1F 5 BCLR7 2 DIR SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+

Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment INH Inherent IMM Immediate DIR Direct EXT Extended DD DIR to DIR IX+D IX+ to DIR REL Relative IX IX1 IX2 IMD IMM to DIR DIX+ DIR to IX+

Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset FXTH870x6 68 Opcode in Hexadecimal F0 Number of Bytes 1 3 SUB IX HCS08 Cycles Instruction Mnemonic Addressing Mode Sensors Freescale Semiconductor, Inc. Table 45. Opcode Map (Sheet 2 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 9E60 6 NEG 3 SP1 9E61 6 CBEQ SP1 4 9E63 6 COM SP1 3 9E64 6 LSR 3 SP1 9E66 6 ROR SP1 3 9E67 6 ASR SP1 3 3 3 3 3 3 9E68 6 LSL SP1 9E69 6 ROL SP1 9E6A 6 DEC SP1 9E6B 8 DBNZ SP1 4 9E6C 6 INC SP1 9E6D 5 TST SP1 9EAE 5 LDHX IX 2 9EBE 6 LDHX IX2 4 9ECE 5 LDHX IX1 3 9E6F 6 CLR 3 SP1 4 4 4 4 4 4 4 4 4 4 4 4 9ED0 5 SUB 9EE0 4 SUB 4 SP2 3 SP1 9ED1 5 CMP SP2 4 9EE1 4 CMP SP1 3 9ED2 5 SBC 9EE2 4 SBC SP2 3 SP1 9ED3 5 CPX 9EE3 4 CPX SP2 3 SP1 9ED4 5 AND 9EE4 4 AND SP2 3 SP1 9ED5 5 BIT 9EE5 4 BIT SP2 3 SP1 9ED6 5 LDA 9EE6 4 LDA SP2 3 SP1 9ED7 5 STA 9EE7 4 STA SP2 3 SP1 9ED8 5 EOR 9EE8 4 EOR SP2 3 SP1 9ED9 5 ADC 9EE9 4 ADC SP2 3 SP1 9EDA 5 ORA 9EEA 4 ORA SP2 3 SP1 9EDB 5 ADD 9EEB 4 ADD SP2 3 SP1 9EDE 5 LDX 9EEE 4 LDX SP2 3 SP1 9EDF 5 STX 9EEF 4 STX SP2 3 SP1 9EF3 6 CPHX SP1 3 9EFE 5 LDHX SP1 3 9EFF 5 STHX SP1 3 INH Inherent IMM Immediate DIR Direct EXT Extended DD DIR to DIR IX+D IX+ to DIR REL Relative IX IX1 IX2 IMD IMM to DIR DIX+ DIR to IX+

Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+

Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in Hexadecimal Number of Bytes 9E60 6 NEG 3 SP1 HCS08 Cycles Instruction Mnemonic Addressing Mode Sensors Freescale Semiconductor, Inc. FXTH870x6 69 Timer Pulse-Width Module 9 The timer pulse-width module (TPM1) is a two channel timer system that supports traditional input capture, output compare, or edge-aligned PWM on each channel. All the features and functions of the TPM1 are as described in the MC9S08RC16 product specification. The user has the option to connect the two timer channels to the PTA[3:2] pins, if those pins are not needed for an LFR channel or other general purpose I/O function. The following clock source and frequency selections are available using the system option register 2 as shown in Figure 23 and Table 27. In addition one channel of the TPM1 can be connected to a 500 kHz clock (DX) derived from the crystal oscillator on the RFM. This selection is made by setting the TPM1 to use an external clock. This clock source allows time calibration of the LFO as described in the Section 14. Features 9.1 The TPM1 has the following features:

May be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels Clock sources independently selectable Selectable clock sources (device dependent): bus clock, fixed system clock Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 16-bit free-running or up/down (CPWM) count operation 16-bit modulus register to control counter range Timer system enable One interrupt per channel plus a terminal count interrupt Channel features:

Each channel may be input capture, output compare, or buffered edge-aligned PWM Rising-edge, falling-edge, or any-edge input capture trigger Set, clear, or toggle output compare action Selectable polarity on PWM outputs TPM1 Configuration Information 9.2 The device provides one two-channel timer/pulse-width modulator (TPM1). An easy way to measure the low frequency oscillator (LFO) is to connect the LFO directly to TPM1 channel 0. The LFOSEL bit in the SOPTZ determines whether TPM1CH0 is connected to PTAZ or the LFO. TPM1 clock source selection for the TPM1 is shown in the table below. Table 46. TPM1 Clock Source Selection CLKSB CLKSA 0 0 1 1 0 1 0 1 Clock Source No source; TPM1 disabled BUSCLK unused Internal DX pin FXTH870x6 70 Sensors Freescale Semiconductor, Inc. Block Diagram 9.2.1 Figure 42 shows the structure of a TPM1. BUSCLK DX CPWMS MAIN 16-BIT COUNTER 16-BIT COMPARATOR TPMMODH:TPMMO CHANNEL 0 16-BIT COMPARATOR TPMC0VH:TPMC0VL 16-BIT LATCH S U B L A N R E T N I CHANNEL 1 16-BIT COMPARATOR TPMC1VH:TPMC1VL 16-BIT LATCH CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT SYNC PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB CLKSA PS2 PS1 PS0 COUNTER RESET TOF TOIE INTERRUPT LOGIC ELS0B ELS0A CH0F MS0B MS0A CH0IE ELS1B ELS1A CH1F MS1B MS1A CH1IE PORT LOGIC TPMCH0 INTERRUPT LOGIC PORT LOGIC TPMCH1 INTERRUPT LOGIC Figure 42. TPM1 Block Diagram The central component of the TPM1 is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-

/down-counter when the TPM1 is configured for center-aligned PWM. The TPM1 counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMMODH:TPMMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence. Any write to either byte of the TPMCNT counter resets the counter regardless of the data value written. All TPM1 channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. External Signal Description 9.3 When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM1 modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. Each TPM1 channel is associated with an I/O pin on the MCU. The function of this pin depends on the configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). See the Section 2 for additional information about shared pin functions. Sensors Freescale Semiconductor, Inc. FXTH870x6 71 Register Definition An 8-bit status and control register (TPMSC) A 16-bit counter (TPMCNTH:TPMCNTL) A 16-bit modulo register (TPMMODH:TPMMODL) 9.4 The TPM1 includes:

Each timer channel has:

9.4.1 TPM1SC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM1 configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. An 8-bit status and control register (TPMCnSC) A 16-bit channel value register (TPMCnVH:TPMCnVL) Timer Status and Control Register (TPM1SC)

$0010 R W Reset 7 TOF 0 6 5 4 3 TOIE CPWMS CLKSB CLKSA 0 0 0 0 2 PS2 0 1 PS1 0 0 PS0 0

= Reserved Figure 43. Timer Status and Control Register (TPM1SC) Table 47. TPM1SC Register Field Descriptions Field 7 TOF 6 TOIE 5 CPWMS 4:3 CLKS[B:A]

2:0 PS[2:0]

Description Timer Overflow Flag This flag is set when the TPM1 counter changes to 0x0000 after reaching the modulo value programmed in the TPM1 counter modulo registers. When the TPM1 is configured for CPWM, TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear TOF by reading the TPM1 status and control register when TOF is set and then writing a 0 to TOF. If another TPM1 overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect. 0 TPM1 counter has not reached modulo value or overflow 1 TPM1 counter has overflowed Timer Overflow Interrupt Enable This read/write bit enables TPM1 overflow interrupts. If TOIE is set, an interrupt is generated when TOF equals 1. Reset clears TOIE. 0 TOF interrupts inhibited (use software polling) 1 TOF interrupts enabled Center-Aligned PWM Select This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM1 operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM1 to operate in up-/down-counting mode for CPWM functions. Reset clears CPWMS. 0 All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channels status and control register 1 All TPM channels operate in center-aligned PWM mode Clock Source Select As shown in Table 46, this 2-bit field is used to disable the TPM1 system or select one of three clock sources to drive the counter prescaler. The internal DX source is synchronized to the bus clock by an on-chip synchronization circuit. Prescale Divisor Select This 3-bit field selects one of eight divisors for the TPM1 clock input as shown in Table 48. This prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the TPM1 system. FXTH870x6 72 Sensors Freescale Semiconductor, Inc. Table 48. Prescale Divisor Selection PS2:PS1:PS0 TPM1 Clock Source Divided-By 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 1 2 4 8 16 32 64 128 Timer Counter Registers (TPM1CNTH:TPM1CNTL) 9.4.2 The two read-only TPM1 counter registers contain the high and low bytes of the value in the TPM1 counter. Reading either byte

(TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPM1CNTH or TPM1CNTL, or any write to the timer status/control register (TPM1SC). Reset clears the TPM1 counter registers.

$0011 R W Reset

$0012 R W Reset 7 Bit 15 0 7 Bit 7 0 6 14 0 6 6 0 4 12 2 5 13 10 Any write to TPMCNTH clears the 16-bit counter. 0 0 3 11 0 0 Figure 44. Timer Counter Register High (TPM1CNTH) 4 4 2 5 5 2 Any write to TPMCNTL clears the 16-bit counter. 0 0 3 3 0 0 1 9 0 1 1 0 0 Bit 8 0 0 Bit 0 0 Figure 45. Timer Counter Register Low (TPM1CNTL) Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) When BACKGROUND mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the BACKGROUND mode became active even if one or both bytes of the counter are read while BACKGROUND mode is active. 9.4.3 The read/write TPM1 modulo registers contain the modulo value for the TPM1 counter. After the TPM1 counter reaches the modulo value, the TPM1 counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down

(CPWMS = 1), and the overflow flag (TOF) becomes set. Writing to TPM1MODH or TPM1MODL inhibits TOF and overflow interrupts until the other byte is written. Reset sets the TPM1 counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled).

$0013 7 R W Reset Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 0 Bit 8 0 Figure 46. Timer Counter Modulo Register High (TPM1MODH) Sensors Freescale Semiconductor, Inc. FXTH870x6 73

$0014 R W Reset 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 0 Bit 0 0 Figure 47. Timer Counter Modulo Register Low (TPM1MODL) It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM1 counter before writing to the TPM1 modulo registers to avoid confusion about when the first counter overflow will occur. 9.4.4 TPM1C0SC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. Timer Channel 0 Status and Control Register (TPM1C0SC)

$0015 7 6 5 4 3 2 R W Reset CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0 0 0 0 1 0 0 0 0 0

= Reserved Figure 48. Timer Channel 0 Status and Control Register (TPM1C0SC) Table 49. TPM1C0SC Register Field Descriptions Field 7 CH0F 6 CH0IE 5 MS0B 4 MS0A 3:2 ELS0[B:A]

Description Channel 0 Flag When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. When channel 0 is an output compare or edge-aligned PWM channel, CH0F is set when the value in the TPM1 counter registers matches the value in the TPM1 channel 0 value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CH0F is set and interrupts are enabled (CH0IE = 1). Clear CH0F by reading TPM1C0SC while CH0F is set and then writing a 0 to CH0F. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CH0F would remain set after the clear sequence was completed for the earlier CH0F. This is done so a CH0F interrupt request cannot be lost by clearing a previous CH0F. Reset clears CH0F. Writing a 1 to CH0F has no effect. 0 No input capture or output compare event occurred on channel 0 1 Input capture or output compare event occurred on channel 0 Channel 0 Interrupt Enable This read/write bit enables interrupts from channel 0. Reset clears CH0IE. 0 Channel 0 interrupt requests disabled (use software polling) 1 Channel 0 interrupt requests enabled Mode Select B for TPM1 Channel 0 When CPWMS = 0, MS0B = 1 configures TPM1 channel 0 for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 50. Mode Select A for TPM1 Channel 0 When CPWMS = 0 and MS0B = 0, MS0A configures TPM1 channel 0 for input capture mode or output compare mode. Refer to Table 50 for a summary of channel mode and setup controls. Edge/Level Select Bits Depending on the operating mode for the timer channel as set by CPWMS:MS0B:MSnA and shown in Table 50, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELS0B:ELS0A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. FXTH870x6 74 Sensors Freescale Semiconductor, Inc. Table 50. Mode, Edge, and Level Selection CPWMS MS0B:MS0A ELS0B:ELS0A Mode Configuration X 0 1 XX 00 01 1X XX 00 01 10 11 00 01 10 11 10 X1 10 X1 Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert to general-purpose I/O Input capture Output compare Edge-aligned PWM Center-aligned PWM Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 9.4.5 These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. Timer Channel Value Registers (TPM1C0VH:TPM1C0VL)

$0016 7 R W Reset

$0017 R W Reset Bit 15 0 7 Bit 7 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 Figure 49. Timer Channel 0 Value Register High (TPM1C0VH) 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 Figure 50. Timer Channel 0 Value Register Low (TPM1C0VL) 1 9 0 1 1 0 0 Bit 8 0 0 Bit 0 0 In input capture mode, reading either byte (TPM1C0VH or TPM1C0VL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C0SC register is written. In output compare or PWM modes, writing to either byte (TPM1C0VH or TPM1C0VL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPM1C0SC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. Sensors Freescale Semiconductor, Inc. FXTH870x6 75 Timer Channel 1 Status and Control Register (TPM1C1SC) 9.4.6 TPM1C1SC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function.

$0018 7 6 5 4 3 2 R W Reset CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0 0 0 0 1 0 0 0 0 0

= Reserved Figure 51. Timer Channel 1 Status and Control Register (TPM1C1SC) Table 51. TPM1C1SC Register Field Descriptions Field 7 CH1F 6 CH1IE 5 MS1B 4 MS1A 3:2 ELS1[B:A]

Description Channel 1 Flag When channel n is configured for input capture, this flag bit is set when an active edge occurs on the channel n pin. When channel 1 is an output compare or edge-aligned PWM channel, CH1F is set when the value in the TPM1 counter registers matches the value in the TPM1 channel 1 value registers. This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. A corresponding interrupt is requested when CH1F is set and interrupts are enabled (CH1IE = 1). Clear CH1F by reading TPM1C1SC while CH1F is set and then writing a 0 to CH1F. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CH1F would remain set after the clear sequence was completed for the earlier CH1F. This is done so a CH1F interrupt request cannot be lost by clearing a previous CH1F. Reset clears CH1F. Writing a 1 to CH1F has no effect. 0 No input capture or output compare event occurred on channel 1 1 Input capture or output compare event occurred on channel 1 Channel 1 Interrupt Enable This read/write bit enables interrupts from channel 1. Reset clears CH1IE. 0 Channel 1 interrupt requests disabled (use software polling) 1 Channel 1 interrupt requests enabled Mode Select B for TPM1 Channel 1 When CPWMS = 0, MS1B = 1 configures TPM1 channel 1 for edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 50. Mode Select A for TPM1 Channel 1 When CPWMS = 0 and MS1B = 0, MS1A configures TPM1 channel 1 for input capture mode or output compare mode. Refer to Table 50 for a summary of channel mode and setup controls. Edge/Level Select Bits Depending on the operating mode for the timer channel as set by CPWMS:MS1B:MS1A and shown in Table 50, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELS1B:ELS1A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer channel functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. Table 52. Mode, Edge, and Level Selection CPWMS MS1B:MS1A ELS1B:ELS1A Mode Configuration XX 00 01 1X X 0 FXTH870x6 76 00 01 10 11 00 01 10 11 10 X1 Pin not used for TPM1 channel; use as an external clock for the TPM1 or revert to general-purpose I/O Input capture Output compare Edge-aligned PWM Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) Sensors Freescale Semiconductor, Inc. Table 52. Mode, Edge, and Level Selection (continued) CPWMS MS1B:MS1A ELS1B:ELS1A Mode Configuration 1 XX 10 X1 Center-aligned PWM High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior. 9.4.7 These read/write registers contain the captured TPM1 counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. Timer Channel Value Registers (TPM1C1VH:TPM1C1VL)

$0019 7 R W Reset

$001A R W Reset Bit 15 0 7 Bit 7 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 Figure 52. Timer Channel 1 Value Register High (TPM1C1VH) 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 Figure 53. Timer Channel 1 Value Register Low (TPM1C1VL) 1 9 0 1 1 0 0 Bit 8 0 0 Bit 0 0 In input capture mode, reading either byte (TPM1C1VH or TPM1C1VL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPM1C1SC register is written. In output compare or PWM modes, writing to either byte (TPM1C1VH or TPM1C1VL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPM1C1SC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. Functional Description 9.5 All TPM1 functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the TPM1. Each TPM1 channel is optionally associated with an MCU pin and a maskable interrupt function. The TPM1 has center-aligned PWM capabilities controlled by the CPWMS control bit in TPM1SC. When CPWMS is set to 1, timer counter TPM1CNT changes to an up-/down-counter and all channels in the associated TPM1 act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. 9.5.1 All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset. After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM1 is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source for the TPM1 can be selected to be off, the bus Counter Sensors Freescale Semiconductor, Inc. FXTH870x6 77 clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate. Refer to Section 9.4.1 and Table 49 for more information about clock source selection. When the microcontroller is in ACTIVE BACKGROUND mode, the TPM1 temporarily suspends all counting until the microcontroller returns to normal user operating mode. During STOP mode, all TPM1 clocks are stopped; therefore, the TPM1 is effectively disabled until clocks resume. During WAIT mode, the TPM1 continues to operate normally. The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPM1MODH:TPM1MODL. When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPM1MODH:TPM1MODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1. The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the main 16-

bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPM1CNTH or TPM1CNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. The main timer counter can be reset manually at any time by writing any value to either byte of the timer count TPM1CNTH or TPM1CNTL. Resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. 9.5.2 Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and buffered edge-aligned PWM. Input Capture Mode With the input capture function, the TPM1 can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TPM1 latches the contents of the TPM1 counter into the channel value registers

(TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to the channel status/control register

(TPM1CnSC). An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. Output Compare Mode With the output compare function, the TPM1 can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM1 can set, clear, or toggle the channel pin. In output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset by writing to the channel status/control register (TPM1CnSC). An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request. Channel Mode Selection FXTH870x6 78 Sensors Freescale Semiconductor, Inc. Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can be used when other channels in the same TPM1 are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the timer channel value register (TPM1CnVH:TPM1CnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure 54 shows, the output compare value in the TPM1 channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output compare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMCH OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 54. PWM Period and Pulse Width (ELSnA = 0) When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel value register

(TPMCnVH:TPMCnVL) to a value greater than the modulus setting, 100% duty cycle can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register, TPM1CnVH or TPM1CnVL, write to buffer registers. In edge-PWM mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the value in the 1TPMCNTH:TPM1CNTL counter is 0x0000. (The new duty cycle does not take effect until the next full period.) 9.5.3 This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPM1CnVH:TPM1CnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPM1MODH:TPM1MODL. TPM1MODH:TPM1MODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELS0A will determine the polarity of the CPWM output. Center-Aligned PWM Mode pulse width =2 x (TPM1CnVH:TPM1CnVL) period = 2 x (TPM1MODH:TPM1MODL);

for TPM1MODH:TPM1MODL = 0x00010x7FFF If the channel value register TPM1CnVH:TPM1CnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPM1MODH:TPM1MODL = 0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. Figure 55 shows the output compare value in the TPM1 channel registers (multiplied by 2), which determines the pulse width

(duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPM1MODH:TPM1MODL, then counts down until it reaches zero. This sets the period equal to two times TPM1MODH:TPM1MODL. Sensors Freescale Semiconductor, Inc. FXTH870x6 79 TPMMODH:TPMMODL COUNT =

TPMMODH:TPMMODL OUTPUT COMPARE

(COUNT DOWN) COUNT = 0 OUTPUT COMPARE

(COUNT UP) COUNT =

TPMMODH:TPMMODL TPM1CHn PULSE WIDTH 2x PERIOD 2x Figure 55. CPWM Period and Pulse Width (ELSnA = 0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers, TPM1MODH, TPM1MODL, TPM1CnVH, and TPM1CnVL, actually write to buffer registers. Values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-

counting at the end of the terminal count in the modulus register). This TPM1CNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPM1CNTH:TPM1CNTL = TPM1MODH:TPM1MODL, the TPM1 can generate a TOF interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they will all update simultaneously at the start of a new period. Writing to TPM1SC cancels any values written to TPM1MODH and/or TPM1MODL and resets the coherency mechanism for the modulo registers. Writing to TPM1C0SC cancels any values written to the channel value registers and resets the coherency mechanism for TPM1C0VH:TPM1C0VL. TPM1 Interrupts 9.6 The TPM1 generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. See Section 5 for absolute interrupt vector addresses, priority, and local interrupt mask control bits. For each interrupt source in the TPM1, a flag bit is set on recognition of the interrupt condition such as timer overflow, channel input capture, or output compare events. This flag may be read (polled) by software to verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine. 9.6.1 TPM1 interrupt flags are cleared by a two-step process that includes a read of the flag bit while it is set (1) followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 9.6.2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode (up or up/down). In up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.) Clearing Timer Interrupt Flags FXTH870x6 80 Sensors Freescale Semiconductor, Inc. Channel Event Interrupt Description 9.6.3 The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described in Section 9.6.1. When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence described in Section 9.6.1. 9.6.4 For channels that are configured for PWM operation, there are two possibilities:

When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel PWM End-of-Duty-Cycle Events value register that marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described in Section 9.6.1. Sensors Freescale Semiconductor, Inc. FXTH870x6 81

.Other MCU Resources 10 It is not intended that physical parameter measurements be made during the time that LFR may be actively receiving/decoding LF signals; or during the time that the RFM may be actively powered up and/or transmitting RF data. The resulting interactions will degrade the accuracy of the measurements. The FXTH870x6 measures six physical parameters for use in the tire pressure monitoring application: pressure, temperature, battery voltage, two external voltages and an optional X- and/or Z-axis acceleration. Each parameter is accessed in a different manner and all use firmware subroutine calls as described in Section 14. These subroutines initialize some control bits within the sensor measurement interface, SMI, and then place the MCU into the STOP4 mode until the measurement is completed with an interrupt back to the MCU. The accuracy, power consumption and timing specified for any measurement given in the electrical specifications in Section 17 are only guaranteed if the user obtains a reading using the specified firmware subroutine call in Section 14. The FXTH870x6 uses a 6-channel, 10-bit analog-to-digital converter (ADC10) module. The ADC10 module is an analog-to-digital converter using a successive approximation register (SAR) architecture with sample and hold. Capture of pressure and acceleration sensor readings is controlled by the sensor measurement interface (SMI) and capture of temperature and voltage readings are controlled by the MCU. When making measurements of the various analog voltages the individual blocks will first be powered up long enough to stabilize their outputs before a conversion is started. The ADC channels are connected in hardware. Conversions are started and ended synchronously with the sampling of the voltages. The accuracy, power consumption and timing specifications given in the electrical specifications in Section 17 are based on using the assigned firmware subroutines in Section 14 to make these measurements and convert them into an 8-bit, 9-bit or 10-bit transfer function. These measurement accuracy specifications cannot be guaranteed if the user creates custom software routines to convert these measurements. Table 53. ADC10 Channel Assignments ADC10 Channel Input Select Firmware Call(s) Characteristic AD0 AD1 AD2 AD3 AD4 AD5 Pressure Sensor Optional X-axis Acceleration Sensor Optional Z-axis Acceleration Sensor Temperature Sensor Bandgap Reference GPIO PTA0 GPIO PTA1 VREG Monitor TPMS_READ_COMP_PRESSURE TPMS_READ_COMP_ACCEL_X TPMS_READ_COMP_ACCEL_Z TPMS_READ_COMP_TEMP_8 TPMS_READ_COMP_VOLTAGE TPMS_READ_V0 TPMS_READ_V1 TPMS_WIRE_CHECK PCODE AXCODE AZCODE TCODE VCODE G0CODE G1CODE Pressure Measurement 10.1 The pressure measurement consists of an interface to a pressure sensing element. Control bits on the MCU operate the SMI to power up the P-Cell and capture a voltage which is converted by the ADC10. The resulting pressure transfer equation for the 100-450 kPa range:

The transfer equation of the 100-900 kPa range is:

P

=

P450 PCODE

+

100 P450 P

=

P900 PCODE

+

100 P900 Eqn. 1 Eqn. 2 Due to calibration routines and parameters stored in the FXTH870x6, the pressure range is selected at production and cannot be changed in the field. NOTE Lack of change of the pressure measurement over time may indicate the package pressure port to be blocked or the internal section of the sensor to be contaminated. User application should maintain either locally or at the system data receiver a record of pressure measurements along with temperature and/or accelerometer measurements, and possibly identify the pressure port as blocked or contaminated if no changes are recorded over time. FXTH870x6 82 Sensors Freescale Semiconductor, Inc. Temperature Measurements 10.2 The temperature is measured from a VB sensor built into channel 1 of the ADC10 in the same manner as is done in the FXTH870x6 devices with the resulting transfer equation:

T

=

T TCODE 55 Eqn. 3 Voltage Measurements 10.3 Voltage measurements can be made on the internal bandgap to estimate the supply voltage on VDD. 10.3.1 An internal bandgap voltage reference is provided to take measurements of the supply voltage. The resulting transfer equation:

Internal Bandgap VINT

=

VINT VCODE 1.22

+

Eqn. 4 External Voltages 10.3.2 Measurements of an external voltage on either the PTA0 or PTA1 pins can be made and referenced to the internal bandgap voltage. The resulting transfer equation:

VPTAx

=

VEXT GxCODE Eqn. 5 where x = 0, 1 refers to PTA0 or PTA1. Optional Acceleration Measurements 10.4 The acceleration measurement consists of an interface to an optional acceleration sensing element. Control bits on the MCU operate the SMI to power up the g-Cell and capture a voltage which is converted by the ADC10. The data from the ADC10 is then pre-processed by a dynamic range firmware routine that will return the two values necessary to calculate the acceleration, Ay, (y = X-axis or Z-axis, depending on selection) in conjunction with values taken from the table in Section 17.10.1. The first value from the firmware routine is the offset step identifier, STEP, with integer values 0 to 15 (i.e. the 16 offset steps). The other value is the ADC10 data, AyCODE, with integer values 0 to 511. AyCODE values 1 through 510 are usable; values 0 and 511 indicate fault conditions. The X-axis acceleration is scaled for ~20g range within each of the 16 offset steps, ~10g per step. The Z-axis acceleration is scaled for ~80g range within each of the 16 offset steps, ~80g or ~60g. The steps are at ~40g or ~30g increments, allowing for adequate overlaps. Section 17.10.1 provides a table of acceleration values resulting from characterizations. Acceleration sensitivity, Ay-STEP, varies between each offset step, and should be calculated by dividing the range of gs for each offset step by the usable AyCODE range (i.e. 510):

Ay-STEP

=

Ay-STEP @ AyCODE510 Ay-STEP @ AyCODE1 510 Eqn. 6 Once the sensitivity Ay-STEP has been calculated, the acceleration Ay can be calculated by the re-using the Ay-STEP @ AyCODE 1 value of the offset step and the returned AyCODE value with the following transfer function:

Ay

=

Ay-STEP AyCODE

+

Ay-STEP @ AyCODE1 Ay-STEP Eqn. 7 The pressure, and optional X or Z-axis accelerometer also share the same signal path in the Transducer interface and all the sensors share the same ADC. Therefore only one of the sensors can be accessed at a given moment. The included accelerometers are designed with a self-test feature. Consult sales/application support for information regarding the recommended use of the accelerometer self-test features. NOTE Optional Battery Condition Check 10.5 The condition of the battery can be periodically checked to determine the batterys internal impedance, RBATT, which is a function of both temperature and the remaining battery capacity. This can be performed by user supplied software routine and an external load resistor, RLOAD, connected from the PTA0 pin to VSS as shown in Figure 56 (any of the PTA[3:0] can be used for this purpose). Sensors Freescale Semiconductor, Inc. FXTH870x6 83 FXTH870xxx VDD PTA0 VSS IDD RLOAD RBATT VBATT

+

FXTH870xxx VDD IDD + ILOAD PTA0 ILOAD VSS RLOAD RBATT VBATT

+

Port Pin Driven Low Port Pin Driven High VDD0

=

VBATT IDD0 RBATT VDD1

=

VBATT VDD1

=

VBATT Figure 56. Battery Check Circuit IDD1 IDD1

+

+

ILOAD RBATT VDD1

---------------------

RLOAD RBATT The battery voltage can first be checked using the method given in Section 10.3 with the selected PTA0 pin set as an output and driven low and then high to determine VDD where only IDD flows or when IDD plus ILOAD flows. The resulting battery impedance can then be calculated as:

RBATT

=

VDD1 VDD0

---------------------------------------------------------------

VDD1

---------------------

IDD0 RLOAD IDD1

+

If it is assumed that IDD0 and IDD1 are not appreciably different at the small change in VDD, then the resulting battery impedance can be approximated as:

RBATT

=

VDD1 VDD0

---------------------------------------

=

VDD1

---------------------

RLOAD RLOAD VDD1 VDD0

-------------------------------------------------------------------------

VDD1 where:

VDD0 is the voltage determined with the external load resistor connected to VSS VDD1 is the voltage determined with the external load resistor connected to VDD RLOAD is the resistance of the external load resistance in ohms RBATT is the implied battery impedance in ohms It is recommended that this calculation be performed with a reasonable current load on the battery of approximately 3 mA (RLOAD approximately 1000 ohms). FXTH870x6 84 Sensors Freescale Semiconductor, Inc. Eqn. 8 Eqn. 9 Measurement Firmware 10.6 The firmware for making measurements is comprised of two function calls as described in Section 14. Each measurement is a combination of a read that returns the raw ADC output data and a comp routine which compensates that raw reading based on information contained in the Universal Uncompensated Measurement Array (UUMA) assigned in RAM memory. The read routines fill specific locations in the UUMA with raw data; but the compensation routines depend what is already present in the UUMA as shown in the data flow in Figure 57. The user therefore has the option to decide how often each measurement (and its component terms) are made. The resulting power consumption is then the sum of using these components are defined in the electrical specifications in Section 17. A typical flow for a compensated pressure measurement would be:

1. Call the TPMS_READ_PRESSURE routine which yields a raw pressure value and fills the UUMA with this data. 2. Call the TPMS_READ_TEMPERATURE routine which yields a raw temperature value and fills the UUMA with this data. 3. Call the TPMS_READ_VOLTAGE routine which yields a raw voltage value and fills the UUMA with this data. 4. Call the TPMS_COMP_PRESSURE routine which then takes the raw pressure, temperature and voltage values from the UUMA and compensates to provide a true pressure reading to the accuracy as specified in Section 17. Sensors Freescale Semiconductor, Inc. FXTH870x6 85 Figure 57. Data Flow For Measurements FXTH870x6 86 Sensors Freescale Semiconductor, Inc. Thermal Shutdown Low Temperature Shutdown High Temperature Shutdown 10.7 When the package temperature becomes too low or too high the MCU can be placed into a STOP mode to suspend operation and prevent transmission of RF signals which may be corrupted at the temperature extremes. Return to normal operation after the temperature falls back within the recovery temperature range. The presence of either the low or high temperature shutdown will disable the PWU from causing either a periodic wakeup or a periodic reset. The MCU, temperature sensor and ADC10 are all functional over the full temperature range from TL to TH. 10.7.1 Low temperature shutdown is achieved using temperature readings taken by the ADC10 as described in Section 10.2 and enabling the thermal restart circuit by setting the TRE bit and selecting the low temperature threshold by clearing the TRH bit. When the software programmed low temperature is reached the MCU will turn off all operating functions and enter the STOP1 mode. 10.7.2 The high temperature shutdown level is determined from a measurement of the temperature sensor by the ADC10 as described in Section 10.2 and enabling the thermal restart circuit by setting the TRE bit and selecting the high temperature threshold by setting the TRH bit. When the software programmed high temperature is reached the MCU will turn off all operating functions and enter the STOP1 mode. 10.7.3 The MCU can be restarted by the Temperature Restart (TR) module when the temperature returns within the normal temperature range, TRESET. When this occurs the MCU will be reset and begin execution from the reset vector located at $DFFE/$DFFF. The TR module can be enabled using the TRE bit in the SIMOPT1 register. The TR module can be powered on and off by setting or clearing the TRE bit located at bit 3 in the SIMOPT1 register at address $1802. The TRE bit is cleared by an MCU reset. When the TRE bit is set the TR module can then be set to detect a recovery from either a high temperature or a low temperature using the TRH in the SIMOPT1 register. The TRH bit is cleared by an MCU reset. The TR module does not activate an MCU restart and reset unless it has first moved outside the re-arming temperature range, TREARM, as shown in Figure 58. The status of the TR can be checked by reading the TRO bit located at bit 0 in the SIMTST register at address $180F. The TRO bit is set high by an MCU reset. The state of the TRO bit is as follows:

Temperature Shutdown Recovery 1 = TR module is outside the TREARM temperature range and will restart the MCU if the TRE bit is set and temperature falls back within the TRESET temperature range. 0 = TR module is within the TRESET temperature range and the MCU cannot be armed to restart when temperature falls back to the TRESET range. The TRE bit cannot be set. TRH = 0 TRO TREARML TRESETL TRH = 1 TRESETH TREARMH TREARM TRESET SHUTDOWN ACTIVE SHUTDOWN TRO = 1 TRO = 0 Figure 58. Temperature Restart Response TEMPERATURE FXTH870x6 87 Sensors Freescale Semiconductor, Inc. This sequence is further explained by the user software flowchart in Figure 59. Figure 59. Flowchart for Using TR Module FXTH870x6 88 Sensors Freescale Semiconductor, Inc. Periodic Wakeup Timer 11 The periodic wakeup timer (PWU) generates a periodic interrupt to wakeup the MCU from any of the STOP modes. It also has an optional periodic reset to restart the MCU. It is driven by the LFO oscillator in the RTI module which generates a clock at a nominal one millisecond interval. The LFO and the wakeup timer are always active and cannot be powered off by any software control. The control bits are set so that there is either a periodic wakeup, a periodic reset, or both a wakeup interrupt and a periodic reset. No combination of control bits will disable both the wakeup interrupt and the periodic reset. In addition, there is no hardware control that can mask a wakeup interrupt once it is generated by the PWU. Block Diagram 11.1 The block diagram of the wakeup timer is shown in Figure 60. This consists of a programmable prescaler with 64 steps that can be used to adjust for variations in the value of the LFO period. Finally there are two cascaded programmable 6-bit dividers to set wakeup and/or reset time intervals. LFO PROGRAMMBLE PRESCALER WCLK 6-BIT WAKEUP DIVIDER RCLK 6-BIT PERIODIC RESET DIVIDER TRE TRO PRFAK WUFAK CONTROL LOGIC PRST PRF WUKI WUF WDIV[5:0]

WUT[5:0]

PRST[5:0]

Figure 60. Wakeup Timer Block Diagram The wakeup divider (PWUDIV) register selects a division of the incoming 1 ms clock to generate a wakeup clock, WCLK. The WCLK frequency can be calibrated against the more precise external oscillator using the TPMS_LFOCOL firmware subroutine as described in Section 14. This subroutine turns on the RFM crystal oscillator and feeds a 500 kHz clock to the TPM1 for one cycle of the LFO. The measured time is used to calculate the correct value for the WDIV[5:0] bits for a WCLK period of 1 second. The TPMS_LFOCOL subroutine cannot be used while the RFM is transmitting or the TPM1 is being used for another task. The wakeup time register (PWUSC0) selects the number of WCLK pulses that are needed to generate a wakeup interrupt to the MCU. The periodic reset register (PWUSC1) selects the number of wakeup pulses that are needed to generate a periodic reset of the MCU. Both the wakeup time counter and the periodic reset timer are incrementing counters that generate their interrupt or reset when the desired count is reached and are then reset to zero. Reading the status of either of these counters will return a zero content if done immediately after the interrupt or reset is generated. If both the reset and the interrupt occur on the same clock cycle the reset will have precedence and the interrupt will not be generated. In order to prevent wakeup or reset from an extreme temperature event both the wakeup interrupt or periodic reset are disabled if the thermal restart is activated and the TRO bit indicates that the device is still outside of the TRESET range. The wakeup and periodic reset counters will still run. The state of these counters can be read using the PSEL bit in the PWUS register. The wakeup interrupt (WUKI) cannot be masked by clearing the I-bit. Sensors Freescale Semiconductor, Inc. FXTH870x6 89 11.2 The PWUDIV register contains six bits to select the division of the incoming 1 ms clock period as described in Figure 61. Wakeup Divider Register - PWUDIV

$0038 Bit 7 R W RESET:

POR:

0 0 6 0 0

= Reserved 5 0 4 1 3 1 WDIV[5:0]

2 1 1 1 Bit 0 1 Figure 61. PWU Divider Register (PWUDIV) Table 54. PWUDIV Register Field Descriptions Field 7:6 Unused Unused Description Wakeup Divider Value The WDIV[5:0] bits select an incoming prescaler for the incoming 1 ms clock period from 504 to 1512. This results in a clocking of the 6-bit wakeup divider at rates from a nominal 0.504 to 1.512 sec per wakeup clock, WCLK. The user can use this prescaler to fine tune the wakeup time based on the variation in the LFO frequency. The conversion from the decimal value of the WDIV bits to the nominal WCLK period is given as:

5:0 WDIV[5:0]

tWCLK

=

+

504 16 WDIV

-------------------------------------------------

fLFO A power on reset presets these bits to a value of $1F (decimal 31) which yields a nominal 1 second output period for WCLK. Other resets have no effect on these bits. PWU Control/Status Register 0 - PWUCS0 11.3 The PWUCS0 register contains six bits to select the division of the incoming WCLK clock period and provide interrupt flag and acknowledge bits as described in Figure 62. The period of the resulting interrupt also generates the clock, RCLK, for the periodic reset timing.

$0039 R W RESET:

Bit 7 WUF 0 6 0 WUFAK 5 1 4 1 3 1 WUT[5:0]

2 1 1 1 Bit 0 1 Figure 62. PWU Control/Status Register 0 (PWUCS0) Table 55. PWUSC0 Register Field Descriptions Field 7 WUF 6 WUFAK FXTH870x6 90 Description Wakeup Interrupt Flag The WUF bit indicates when a wakeup interrupt has been generated by the PWU. This bit is cleared by writing a one to the WUFAK bit. Writing a zero to this bit has no effect. Reset clears this bit. 0 Wakeup interrupt not generated or was previously acknowledged. 1 Wakeup interrupt generated. Acknowledge WUF Interrupt Flag The WUFAK bit clears the WUF bit if written with a one. Writing a zero to the WUFAK bit has no effect on the WUF bit. Reading the WUFAK bit returns a zero. Reset has no effect on this bit. 0 No effect. 1 Clear WUF bit. Sensors Freescale Semiconductor, Inc. Table 55. PWUSC0 Register Field Descriptions (continued) Field 5:0 WUT[5:0]

Description WUF Time Interval These control bits select the number of WCLK clocks that are needed before the next wakeup interrupt is generated. The count gives a range of wakeup times from 1 to 63 WCLK clocks. Depending on the value of the bits for the WDIV[5:0] this time interval can nominally be from 1 to 63 seconds in 1 second steps. Whenever the WUT[5:0] bits are changed the timeout period is restarted. Writing the same data to the WUT[5:0] bits has no effect. Writing zeros to all of the WUT[5:0] bits forces the wakeup divider to a value of $3F and disables the wakeup interrupt. However, writing all zeros to the WUT[5:0] bits is inhibited if all of the PRST[5:0] bits are already cleared to zero. This prevents disabling both the periodic wakeup and the periodic reset at the same time. See Table 56. The WUT[5:0] bits are preset to a value of $3F (decimal 63) by any resets. Table 56. Limitations on Clearing WUT/PRST Control Bits State of Control Bits Control Bits to be Cleared Resulting Action WUT[5:0]

PRST[5:0]

non-zero all zero non-zero all zero PRST[5:0]

WUT[5:0]

Allowed Inhibited Allowed Inhibited Resulting Wakeup Interrupt Enabled(1) Disabled(2) Disabled Enabled(1) Resulting Periodic Reset Disabled Enabled(1) Enabled(1) Disabled 1. Using previous values. 2. Wakeup divider preset to $3F. PWU Control/Status Register 1 - PWUCS1 11.4 The PWUSC1 register contains six bits to select the division of the incoming RCLK clock period and provide interrupt flag and acknowledge bits as described in Figure 63.

$003A R W RESET:

Bit 7 PRF 0 6 0 PRFAK 0

= Reserved 5 1 4 1 3 1 PRST[5:0]

2 1 1 1 Bit 0 1 Figure 63. PWU Control/Status Register 1 (PWUCS1) Table 57. PWUSC1 Register Field Descriptions Field 7 PRF 6 PRFAK 5:0 PRST[5:0]

Description Periodic Reset Flag The PRF bit indicates when a periodic reset has been generated by the PWU. MCU writes to this bit have no effect. This bit is cleared by writing a one to the PRFAK bit. This bit is cleared by a power on reset, but is unaffected by other resets. 0 Periodic reset not generated or previously acknowledged. 1 Periodic reset generated. Acknowledge PRF Interrupt Flag The PRFAK bit clears the PRF bit if written with a one. Writing a zero to the PRFAK bit has no effect on the PRF bit. Reading the PRFAK bit returns a zero. Reset has no effect on this bit. 0 No effect. 1 Clear PRF bit. Periodic Reset Time Interval These control bits select the number of wakeup interrupts that are needed before the next periodic reset is generated. The decimal count gives a range of periodic reset times from 1 to 63 wakeup interrupts. Depending on the value of the bits for the WDIV[5:0] and WUT[5:0] this time interval can nominally be from 1 second to 66 minutes with steps from 1 to 63 seconds. Whenever the PRST[5:0] bits are changed the timeout period is restarted. Writing the same data to the PRST[5:0] bits has no effect. Writing zeros to all of the PRST[5:0] bits forces the periodic reset to be disabled if at least one of the WUT[5:0] bits is set to a one. This assures that there will be at least a wakeup interrupt. However, writing all zeros to the PRST[5:0] bits is inhibited if all of the WUT[5:0] bits are already cleared to zero. This prevents disabling both the periodic wakeup and the periodic reset at the same time. See Table 56. The PRST[5:0] bits are preset to a value of 63 by any resets. Sensors Freescale Semiconductor, Inc. FXTH870x6 91 PWU Wakeup Status Register - PWUS 11.5 The PWUS register shows the current status of the two PWU counters as described in Figure 63. The counter contents are captured when the register is read.

$001F R W RESET:

Bit 7 PSEL 0 6 0

= Reserved 5 4 3 CSTAT 2 1 Bit 0 Figure 64. PWU Wakeup Status Register (PWUS) Table 58. PWUS Register Field Descriptions Field 7 PSEL 6 unused 5:0 CSTAT Page Selection The PSEL read/write bit selects whether the other bits are read from the WUT or PRST counters. This bit is cleared by a power on reset that is not created by an exit from the STOP mode, but is unaffected by other resets. 0 CSTAT = WUT counter status 1 CSTAT = PRST counter status Description Unused An unused bit that always reads as a logical zero. Counter Status These read-only bits show the status of the counter selected by the PSEL bit. The effects of any reset on these bits depends on how the reset affects the selected counter. Reading these counters immediately after a WUF or PRF generated flag will return zero contents. RUN Mode STOP4 Mode Functional Modes 11.6 PWU module will work in each of the MCU operating modes as follows:

11.6.1 If the module generates a wakeup interrupt the PC (Program Counter) will be redirected to the wakeup timer interrupt vector. The WUF flag will be set to indicate wakeup timer interrupt; write 1 to WUFACK to clear this flag. If the module generates a reset the PC will be redirected to the reset vector. The PRF flag will be set to indicate periodic reset;

write 1 to PRFACK to clear this flag. All registers will continue to hold their programmed values after interrupt or reset is taken. 11.6.2 If the module generates a wakeup interrupt the bus and core clocks will be restarted and the PC will be redirected to the wakeup timer interrupt vector. The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag. If the module generates a periodic reset the bus and core clocks will be restarted and the PC will be redirected to the reset vector. The PRF flag will be set to indicate periodic reset; write 1 to PRFACK to clear this flag. All registers will continue to hold their programmed values after interrupt or reset is taken. 11.6.3 If the module generates a wakeup interrupt the module will cause the MCU to exit the power saving mode as a POR. MCU will have the wakeup interrupt pending and once CLI opcode is executed PC will be redirected to wakeup interrupt vector address. The WUF flag will be set to indicate wakeup timer interrupt, write 1 to WUFACK to clear this flag. If the module generates a periodic reset the module will cause the MCU to exit the power saving mode as a POR. The PRF flag will be set to indicate periodic reset; write 1 to PRFACK to clear this flag. The SRS register will have just the POR bit set. In this STOP mode exit all registers will continue to hold their programmed values. 11.6.4 The PWU is frozen in ACTIVE BACKGROUND mode or executing foreground commands, so PWU counters will also be stopped. Normal PWU operation will resume as MCU exits BDM or foreground command is finished. Active BDM/Foreground Commands STOP1 Mode FXTH870x6 92 Sensors Freescale Semiconductor, Inc. LF Receiver 12 The low-frequency receiver (LFR) is a very low-power, low-frequency, receiver system for short-range communication in TPMS. The module allows an external coil to be connected to two dedicated differential input pins. In TPMS systems a single coil may be oriented for optimal coupling between the receiver in the tire or wheel and a transmitter coil on the vehicle body or chassis. This LFR system minimizes power consumption by allowing flexibility in choosing the ratio of on to off times and by turning off power to blocks of circuitry until they are needed during signal reception and protocol recognition. In addition, this LFR system can autonomously listen for valid LF signals, check for protocol and ID information so the main MCU can remain in a very low power standby mode until valid message data has been received. The LFR can be configured for various message protocols and telegrams to allow it to be used in a broad range of applications. The message preamble must be a series of Manchester coded bits at the nominal 3.906-kbps data rate. A synchronization pattern is used to mark the boundary between the preamble and the beginning of Manchester encoded information in the message body. The synchronization pattern is a non-Manchester specific TPMS pattern. Messages can optionally include none, an 8-bit or a 16-

bit ID value. Messages may contain any number of data bytes with the end-of-message indicated by detecting an illegal Manchester bit at a data byte boundary. It is not intended that LFR may be actively receiving/decoding LF signals while physical parameter measurements are being made; or during the time that the RFM may be actively powered up and/or transmitting RF data. The resulting interactions will degrade the accuracy of the LF detection. Clamp Clamp R R R V V V LFA LFB Summator Data Data Slicer Slicer Average Filter Rectifier0 Rectifier1 Rectifier2 Rectifier3 Amp1 Buff1 Amp2 Buff2 Amp3 Buff3 Sensitivity Vref_sensitivity Carrier Carrier Detector Detector Logic Block 1:

- On/Off cycling

- Carrier Detection MFO 129 kHz 32kHz Typ Logic Block 2:

- Data decoding 1kHz_clock 1 kHz_clock Typ Figure 65. Block Diagram For definitions of the acronyms and detailed descriptions of the bits and/or byte registers, please refer to Section 12.17. Sensors Freescale Semiconductor, Inc. FXTH870x6 93 Features 12.1 Major features of the LFR module include:

Differential input LF detector (two dedicated pins):

Selectable sensitivity (two levels: Low Sens (LS) and High Sens (HS)). Thresholds trimmed at the factory with trim setting saved in nonvolatile memory. LFR has a reference oscillator (LFRO) trimmed at the factory with trim setting saved in nonvolatile memory. Selectable signal sampling time interval and on-time. Sample interval and on times controlled by LFR state machine or directly by the MCU. Configurable receive mode:

Simple LF carrier detection/Telegram decode. (CARMOD) Configurable message protocol (telegram structure):

Various SYNC decoding (SYNC[1:0]) 6-bit time SYNC requirements 7.5-bit time SYNC requirements 9-bit time SYNC requirements Optional ID (ID[1:0]) 8-bit or 16-bit ID On or off 0-n bytes of message data. End-of-data marked by loss of Manchester at a byte boundary. Optional continuous monitoring and decode of the LF detector. Selectable MCU interrupt when a received data byte is ready in an LFR buffer, when a Manchester error is detected in the frame, when an ID is received or when a valid carrier has been detected. Modes of Operation 12.2 The LFR is a peripheral module on an MCU. After being configured by application software, the LFR can operate autonomously to detect and verify incoming LF messages. When a valid message or carrier pulse is received and verified the LFR can wake the MCU from standby modes to read received data or act upon a carrier detection. The primary modes of operation for the LFR are:

Disabled. Everything off and drawing minimal leakage current. LFR register contents will be retained. Carrier detect/listen. Minimum circuitry enabled to detect any incoming LF signal, check it for the appropriate signal level, frequency and duration. TPMS protocol verification. Data reception. Power Management 12.3 In addition to using low power circuit design techniques, the LFR module provides system-level features to minimize system energy requirements. In an MCU that includes the LFR module, all MCU circuitry except a very low current 1-kHz oscillator (LFO) and minimum regulator circuitry can be disabled. After a reset, the MCU would initialize the LFR module and then enter a very low power standby mode (depending upon the MCU, this could be lower than 1 uA for the MCU portion). The LFR module includes everything it needs to periodically listen for LF messages, perform Manchester decoding, verify the message telegram, and assemble incoming data into 8-bit bytes. The LFR does not wake the MCU unless a valid message is being received and a data byte is ready to be read. The LFR cycles between an off state, where everything is disabled, and an on state, where it listens for a carrier signal. The on time is controlled by LFONTM[3:0] control bits in the LFCTL2 register. The time between the start of each sample on time is controlled by LFSTM[3:0] control bits in the LFCTL2 register. Even lower duty cycles can be achieved by using the MCU to wake once per second and maintain a software counter to delay for an arbitrarily long time before enabling the LFR to perform a series of carrier detect cycles. Within the LFR, circuits remain disabled until they are needed. When the LFR is listening for a carrier signal, only a 1-kHz clock source, a portion of the input amplifier and a periodic auto-zero are running. After a carrier signal is detected, with high enough amplitude, frequency and duration the LFRO oscillator is enabled so the LFR can begin to decode the incoming information. The LFR module has a power up settling time of 2-LFO period before any active operations. In the ON/OFF cycle, those 2 ms are hidden in the sampling time during the off time. FXTH870x6 94 Sensors Freescale Semiconductor, Inc. Input Amplifier 12.4 The LFR module receives LF modulated signals through a dedicated differential pair of inputs which is connected to an external coil. The enable control (LFEN) allows the user to enable the LF input depending on the application requirements. The SENS[1:0]

bits in the LFCTL1 register allows the user to select one of two input sensitivity thresholds which determines the signal level required before the input carrier will be detected. The sensitivity setting is used during carrier detection but does not affect reception after the carrier has been detected. When the CARMOD bit is cleared, after a carrier with sufficient amplitude, frequency and duration has been detected the output stage of the amplifier is turned on to allow data reception. 12.5 The modes of operation the LFR state machine will sequence as shown in Figure 66. LFR Data Mode States Carrier Detect 12.6 Carrier detection includes a check for a certain number of edges on a signal that is greater than the input sensitivity threshold. During the check for carrier edges, only the 1kHz low frequency oscillator (LFO) clock source is running so power consumption remains very low. During carrier detection the incoming signal is amplified and passed through a sensitivity threshold comparator. The SENS[1:0]

bits in the LFCTL1 register selects two levels of sensitivity and determines the signal amplitude that is needed to allow edges to be seen at the output of the sensitivity threshold comparator. When a carrier is above this threshold, a block is powered on and validates the carrier. This frequency and duration check function can be disabled by clearing the VALEN bit. If VALEN is set, the block checks for the carrier duration and the carrier frequency. The time needed to validate a carrier is programmed by the LFCDTM register. The carrier frequency should be 125 kHz. If the signal above the threshold is not within the frequency range or not present during enough time, then the carrier will not be validated and the validation block will turn off. If no carrier signal is validated within the on time of the LFR, the state machine returns to the off state and the alternating cycle of on time and off time continues. Carrier edge counts start at zero when a new on time begins. In the data mode (CARMOD = 0), if the required number of carrier edges are detected before the end of the ON time, the LFR will remain ON to complete the reception of a message telegram. In the carrier detect mode (CARMOD = 1) there is no need to enable other LFR circuitry to evaluate any other message components after the required number of carrier edges are detected. One or several consecutive carriers can be validated by this process before the LFCDF flag is set. The LFCC control bits are used to program the number of consecutive ON times where a complete carrier validation is needed before interrupting the MCU. In this case, the LFCDF flag is set and, provided the LFCDIE interrupt enable is also set, an interrupt is issued to wake the MCU. In carrier detect mode, the LFCDIE control bit should always be set because the intended purpose of the carrier detect mode is to wake the MCU when a carrier is detected. When LFCDF is set, the LFR waits until it is cleared before it continues the alternating cycle of on time and off time, starting with an off time. In data mode, when a carrier is detected the averaging filter is powered on and the LFR continues to the next state to look for the rest of a message telegram; and the LFR module will search for valid SYNC word (with length programmed through the SYNC bits in the LFCTL3 register depending on preamble type). If the external LF field is not a TPMS frame, a timeout will turn off the LFR module. This timeout can be program through TIMOUT bit the LFCTL4 register. Sensors Freescale Semiconductor, Inc. FXTH870x6 95

Figure 66. FXTH870x6 LFR State Machine Diagram FXTH870x6 96 Sensors Freescale Semiconductor, Inc. Auto-Zero Sequence 12.7 An auto-zero sequence is performed periodically on the input amplifier to cancel offset errors. During reception of the SYNC pattern and body of the message, auto-zero operations are synchronized to data edges of the incoming signal to avoid interfering with normal reception. During the auto-zero sequence, the input amplifier is temporarily disconnected from the external coil and connected to ground. The auto-zero sequence takes roughly 64 sec. It is performed at each LFO period in carrier mode and on one over four decoded data edges in data mode. When the DECEN bit is cleared, the auto-zero sequence is performed at each LFO period. During the 64 sec of the auto-zero sequence, the receiver is holding the state 0 or 1' previously decoded. Since the LFR receiver is not active during this time, the possible data-rate that the analog can detect is at least limited by this duration. Data Recovery 12.8 Rectified signals from the amplifier output are connected to the input of an averaging filter and data slicer. The slicer thus compares the rectified signal with its own average value to decode the data. When a carrier is present, the slicer output voltage rises and when the carrier stops the slicer output voltage falls. The output of this comparator provides a binary digital signal that indicates whether the carrier is present or not. This digital signal is connected to the data clock recovery circuit, the SYNC detect circuit, and the Manchester decoder circuit. The Manchester decoder uses the digital output of the data slicer to detect the logic level of each incoming data bit and to synchronize the decoder state machine. The LFPOL polarity bit in the LFCTRLA register selects the expected encoding of the Manchester data bit. If a strong signal (above roughly 100 mV p-p differential) is entered into the LFR, the input impedance will switch instantaneously to a lower programmed value (the LOWQ[1:0] bits in the LFCTRLC) and be maintained during the current data packet if the DEQEN bit is set. At the next ON time, the default high input impedance will be set again. The strong signal detection and the automatic impedance change can be disabled by clearing the DEQEN bit. Data Clock Recovery and Synchronization 12.9 Data clock recovery and synchronization takes place during the SYNC portion of an incoming message. The preamble must be modulated Manchester data. The type of required SYNC pattern determines the allowed preamble type depending on the SYNC[1:0] control bits. The design data rate is 3.906 kbps which gives a bit time equivalent to about 32 cycles of the LF carrier frequency. In a Manchester encoded bit time, the carrier should be present for either the first half or the second half of the bit time depending on whether the bit is a logic zero or a logic one. The LFRO clock source is 32 times the target data rate. The LFRO is used for decoding data and also sequencing auto-zero operations. 12.10 Manchester Decode When the LFPOL bit is clear, a logic one bit is defined as no LF carrier present for the first half of the bit time; and a logic zero bit is defined as LF carrier present for the first half of the bit time as shown in Figure 67. Another way to say this from the point of view of the data slicer output is that a logic zero bit has a falling edge at the middle of the bit time and a logic one bit has a rising edge at the middle of the bit time. The data slicer threshold is dynamically adjusted to the midpoint between the carrier-

present and no-carrier levels at the summing node for the rectified output of the LF input amplifier. Sensors Freescale Semiconductor, Inc. FXTH870x6 97 Data Slicer Threshold 0.5T T Logic 0 LF Input

(shaded area is LF carrier) 0.5T Data Bit

(data slicer output) T Logic 1 T = 1 Bit Time at the data rate (ex. 256 us at data rate of 3.906 kbps) Figure 67. Manchester Encoded Datagram for LFPOL = 0 When the LFPOL bit is set, a logic one bit is defined as LF carrier present for the first half of the bit time; and a logic zero bit is defined as no LF carrier present for the first half of the bit time as shown in Figure 68. Data Slicer Threshold LF Input

(shaded area is LF carrier) 0.5T Data Bit

(data slicer output) T Logic 0 0.5T T Logic 1 T = 1 Bit Time at the data rate (ex. 256 s at data rate of 3.906 kbps) Figure 68. Manchester Encoded Datagram for LFPOL = 1 Duty-Cycle For Data Mode 12.11 The definition of the duty-cycle for the Manchester encoded data depends on the relative rise and fall times of the incoming LF carrier as shown in Figure 69. 60 40 40 60 1 0 Regarding the SYNC pattern which is non-Manchester coded, the duty cycle is applied on all falling edges with the same proportion as a 1T Manchester symbol, as shown in Figure 70. Figure 69. Definition of Duty-Cycle of 40%

FXTH870x6 98 Sensors Freescale Semiconductor, Inc. Figure 70. Impact of Duty-Cycle on SYNC Pattern Input Signal Envelope 12.12 The combination of the external LF antenna and any external components as shown in Figure 71 should not significantly filter the envelope of the LF carrier as shown in Figure 72. Excessive filtering will cause the received message error rate (MER) to increase. C R LFA LFB Antenna Q-factor acts as a 1st order low pass filter on the LF envelop Filter time constant : t = R.C Recommended< 15.3 sec Antenna model SUZUKA Figure 71. Antenna Q-factor Equivalent Model for the LF Envelope Recommended< 15.3 sec Figure 72. LF Envelope Filtering Sensors Freescale Semiconductor, Inc. FXTH870x6 99 Telegram Verification 12.13 The LFR has control bits to allow flexibility in the telegram format and protocol to allow the LFR to adapt to a variety of systems. The LFR can operate in a normal data receive mode where it receives complete telegrams, or in a carrier detect mode where it only checks for a carrier. In the carrier detect mode, as soon as a carrier is detected, the LFCDF flag is set. If LFCDIE is also set, an interrupt request is sent to wake the MCU The format of the complete Manchester encoded datagram is comprised of a Manchester data preamble (series of Manchester 1s or 0s), a synchronization period, an optional ID, and zero to n data bytes. The synchronization period can be used for synchronizing the beginning of the data packet. The SYNC pattern that follows the preamble can be either a 6-, 7.5- or 9 bit-time non-Manchester pattern as shown in Figure 73. 6-bit

(6T) Pattern SYNC[1:0] = 01 7.5-bit

(7.5T) Pattern SYNC[1:0] = 10 9-bit

(9T) Pattern SYNC[1:0] = 11 1.5T 3T T T 2T 2T T T 1.5T T T 2T T 2T T T T T 2T 2T T Figure 73. SYNC Patterns These patterns would normally not appear anywhere in the Manchester encoded portion of a message so there is no possibility that the LFR could accidentally synchronize to a message that was already in progress when the LFR started listening for a message. These patterns are also complex enough so that it is very unlikely that noise or interference could be mistaken for these SYNC patterns. In the data mode and after the detection of a valid carrier, the LFR will decode the data stream waiting for the SYNC word. Should this carrier not be an accepted TPMS type, no SYNC will be received and the LFR module will stay in data receive mode forever. A timeout counter is thus started after a carrier detection and will stop the receiver if reaching the programmed value selected by the TIMOUT[1:0] bits in the LFCTL4 register. This timeout counter is clocked by the internal LFRO clock. The LFR can be configured to have an optional 0, 8-bit or 16-bit ID after the SYNC pattern. If the ID value matches the received ID, the message is accepted. The ID value can be used to identify a specific receiver, a message type, or some other identifier as defined by application software. Any number of data bytes can be included after the ID. The LFR begins to assemble data bytes from the incoming signal as soon as the ID check is complete. If the first bit-time after the last bit of the ID does not conform to Manchester coding requirements, the LFR considers the message complete and terminates the LFR operation without setting the data ready flag (LFDRF). If data follows the ID, it is serially received and when 8 bits have been received the LFR copies this byte into the LFDATA register and sets the LFDRF flag. If the LFDRIE interrupt enable is also set (and it should be), an interrupt request is sent to wake the MCU so it can read the data and process it according to the instructions in the application program. Additional bytes are received until a bit time that is not Manchester encoded is found. If a non-Manchester bit time is found, the LFERF bit will be set and indicates a Manchester coding error. If this happens on the first bit of the next byte of the message the LFEOMF bit will also be set. The preamble is a period of Manchester bits before the SYNC pattern as shown in Figure 74. The SYNC pattern will only be matched for the bit times specified by the SYNC[1:0] control bits. Depending on the expected SYNC pattern the allowed preambles is as described for the SYNC[1:0] bits in the LFCTL3 register. FXTH870x6 100 Sensors Freescale Semiconductor, Inc. PREAMBLE SYNC HIGH ID LOW ID DATA DATA tLFPRE 6, 7.5 or 9T 0, 8T or 16T IDSEL[1:0]

8T Repeat for 0-n bytes Figure 74. Telegram Format (Carrier Preamble) Error Detection and Handling 12.14 When the DECEN bit is set, LFR messages are monitored for data rate or SYNC errors, incorrect message ID, and Manchester coding errors. When an error is detected the LFR goes back to sniff mode until the end of ON time completion, if ONMODE is set; or turns off until the start of the next scheduled sampling interval, if ONMODE is cleared. Because the MCU uses more power than the LFR module, it is desirable to keep the MCU in low power standby modes as much as possible. Therefore the handling of these errors will be performed by the LFR and not require additional software processing by the MCU. When the DECEN bit is clear, there is no monitoring on data. The MCU needs to poll the state of the LFDO bit and create its own decoding scheme within software on the detected signal. To be able to start the polling only when data are received, the carrier detection flag is enabled in data mode when DECEN = 0. During data reception, the auto-zero sequence is performed at each LFO period. The MCU needs also to determine the end of the telegram and turn off the LFR (LFEN = 0) during two LFO cycles before any other operations. 12.15 Continuous ON Mode In the Continuously ON mode, the LFR module will remain on continuously while the LFEN bit is set. The Continuously ON mode is controlled by setting the LFSTM[3:0] bits. In the Continuously ON mode, if a signal is successfully processed by the digital, the LFR module will stop and restart automatically. The gap is 2-3 LFO periods. Also if TOGMOD bit is set, the LFR module will stop after the ON time cycle and re-

start automatically, after having changed the CARMOD bit. Initialization Information 12.16 When power is applied to the MCU, the LFR must be initialized and configured before it can begin to receive LF messages. Several systems in the LFR require factory trimming to ensure operation within specified limits. After these trim values are written, they remain constant until the next MCU reset. The application program must set up control bits and registers to configure the LFR to determine the structure of the message telegram, the input sensitivity, and other LFR options. It is good practice to clear the flags in the LFS register before enabling interrupt sources in order to avoid any immediate interrupt requests. Sensors Freescale Semiconductor, Inc. FXTH870x6 101 LFR Register Definition 12.17 The LFR module uses eight addresses in the MCU memory map for data, control, and status registers.This section consists of register descriptions. Each control register (LFCTLx) should be modify when the LF is off (LFEN = 0). Modification of the control registers on-the-fly might lead to unknown state. Each turn off of the LFR (LFEN = 0) should be followed by at least two LFO cycles before trying to restart the LFR (LFEN = 1). 12.17.1 LF Control Register 1 (LFCTL1) LFCTL1 contains the main LF enable control, detection protocol format controls, and input sensitivity controls. The LFCTL1 register also contains a register select bit, LPAGE.

$0020 R W Reset:

Bit 7 LFEN 0 6 0 SRES 0 5 4 CARMOD LPAGE 0 0 3 0 IDSEL[1:0]

2 0 1 0 SENS[1:0]

Bit 0 0 Figure 75. LFR Control Register 1 (LFCTL1) Table 59. LFCTL1 Register Field Descriptions Field 7 LFEN 6 SRES 5 CARMOD 4 LPAGE 3:2 IDSEL[1:0]

1:0 SENS[1:0]

FXTH870x6 102 Description LF Enable This read-write control bit is used to enable or disable the LF receiver. Once this bit is set the LFR will go through a power-up sequence that starts on the next rising edge of the LFO clock. The first complete cycle of the LFO is used to power up the LFR circuits. Following this startup time the auto-zero sequence is performed for 64sec and then the LFR is ready to receive signals. 0 LF receiver in standby. 1 LF receiver active. Note: Enabling the LF receiver function disables the GPIO Port B functions - see Section 6.5. Soft Reset This read/write bit controls the soft reset of the LFR. The bit is self reset and always reads as a logical zero. 0 Reset completed 1 Start a soft reset. Carrier Mode This read/write control bit selects the basic operating mode for the LFR. 0 Data receive mode. 1 Carrier detect mode - wake the MCU when a carrier signal is detected if LFCDIE is set. LFR Page Select This read/write bit is used is used to select the register page access. The LPAGE bit has no effect on the LFCTL1 and LFCTL2 registers. This bit is cleared by LFR reset. 0 Access page 0. 1 Access page 1. Wakeup ID Selection Selects the existence and length of the wakeup ID. Reset clears these bits. 00 01 10 11 Sensitivity Control These two read/write control bits select the sensitivity thresholds for the LFR input. These thresholds apply to the detection portion of a message. If the input level is below the SNODET_x level, no signal will be detected. If the level is above SDET_x, the signal will be detected. Sensitivity settings are only used in the carrier detect path and do not affect reception of the message body. 00 01 10 11 No ID expected 8-bit ID based on the contents of the LFIDL register 16-bit ID based on the contents of the LFIDH and LFIDL registers 8-bit ID matches the contents of either the LFIDH or LFIDL registers Performance not specified. Low sensitivity (SDET_L; SNODET_L) High sensitivity (SDET_H; SNODET_H) Performance not specified. Sensors Freescale Semiconductor, Inc. 12.17.2 LF Control Register 2 (LFCTL2) LFCTL2 contains the selection bits for the length of the LF sampling ON time and the time interval between samples as shown in Figure 76.

$0021 Bit 7 R W Reset:

0 6 1 LFSTM[3:0]

5 1 4 0 3 0 2 0 LFONTM[3:0]

1 0 Bit 0 0 Figure 76. LFR Control Register 2 (LFCTL2) Table 60. LFCTL2 Register Field Descriptions Field 7:4 LFSTM

[3:0]

3:0 LFONTM

[3:0]

Description LF Sampling Time Interval Select These read/write control bits select the length of time between when the LFR input detector is turned on as set by the LFONTM bits in LFCTL2 register. The initial sampling interval starts with the LFO clock following a write to these bits. A reset of the LFR results in the value being set to binary 0110. 0000 Continuous ON mode (see Section 12.15) 0001 Sampled decoding mode every 16 LFO clock periods (16 milliseconds nominal) 0010 Sampled decoding mode every 32 LFO clock periods (32 milliseconds nominal) 0011 Sampled decoding mode every 64 LFO clock periods (64 milliseconds nominal) 0100 Sampled decoding mode every 128 LFO clock periods (128 milliseconds nominal) 0101 Sampled decoding mode every 256 LFO clock periods (256 millisecond nominal) 0110 Sampled decoding mode every 512 LFO clock periods (512 milliseconds nominal) 0111 Sampled decoding mode every 1024 LFO clock periods (1024 milliseconds nominal) 1000 Sampled decoding mode every 2048 LFO clock periods (2048 milliseconds nominal) 1001 Sampled decoding mode every 4096 LFO clock periods (4096 milliseconds nominal) 1010-1xxxContinuous ON mode (see Section 12.15) LF Sampling ON Time Select These read/write control bits select the length of time that the LFR input detector is turned on at the beginning of each sampling interval set by the LFSTM bits. This ON time is the net sampling time with any initialization time (maximum of 2 ms) included in the OFF time prior to the sample ON time (see Figure 77). If a signal is successfully detected, the length of time the detector remains ON depends on the operating mode. In carrier detect mode

(CARMOD = 1) the detector will be turned off early if the evaluation of the carrier signal is completed before the end of the scheduled ON time. In data receive mode (CARMOD = 0) the detector will remain ON until the end of the message, an error is detected or timeout occurrence. Reset forces the LFONTM bits to 0:0:0. 0000 1 LFO clock cycle (1 millisecond nominal) 0001 2 LFO clock cycle (2 milliseconds nominal) 0010 4 LFO clock cycle (4 milliseconds nominal) 0011 8 LFO clock cycle (8 milliseconds nominal) 0100 16 LFO clock cycle (16 milliseconds nominal) 0101 32 LFO clock cycle (32 milliseconds nominal) 0110 64 LFO clock cycle (64 milliseconds nominal) 0111 128 LFO clock cycle (128 milliseconds nominal) 1000 256 LFO clock cycle (256 milliseconds nominal) 1001 512 LFO clock cycle (512 milliseconds nominal) 1010 1024 LFO clock cycles (1024 milliseconds nominal) 1011 1024 LFO clock cycles (1024 milliseconds nominal) 11xx 1024 LFO clock cycles (1024 milliseconds nominal) Note: The LFONTM selected time must be less than the LFSTM selected time, otherwise the Continuously ON mode is present. Sensors Freescale Semiconductor, Inc. FXTH870x6 103 LFONTM Power Up Settling Time LFR Detector Active tDEC Power Up Settling Time LFSTM time segments not to scale LFONTM LF searching for SYNC pattern Figure 77. LF Detector Sampling Timing 12.17.3 LF Control Register 3 (LFCTL3) LFCTL3 contains the control bits for the LF sampling interval and the minimum required carrier detection time when using the carrier detect mode.

$0022 R W Reset:

Bit 7 LFDO 6 TOGMOD 0

= Reserved 5 0 SYNC[1:0]

4 1 3 0 2 0 LFCDTM[3:0]

1 0 Bit 0 0 Figure 78. LFR Control Register 3 (LFCTL3) Table 61. LFCTL3 Register Field Descriptions Field 7 LFDO 6 TOGMOD 5:4 SYNC[1:0]

Description LF Detector Output This read-only bit follows the bit slicer output signal that goes high during the presence of a carrier. It may change at any time. This bit is read only and unaffected by any reset. 0 LF detector output low (no signal above threshold) 1 LF detector output high (received signal above threshold) LFR Mode Toggle This read/write bit enables the toggling of the CARMOD bit at each new LFON sequence. Reset clears this bit. 0 CARMOD bit does not change and determines detector mode. 1 CARMOD bit will be toggled every LFON detection sequence, starting by CARMOD selection. Therefore the reception chain will alternately look for a carrier frame or for a data frame. LF SYNC Selection Selects the type of SYNC pattern as described in Figure 73. Reset presets these bits to the 01 (6T SYNC) option. Compatible with preamble consisting of minimum 2 ms Manchester data to allow for proper averaging filter operation. 00 01 10 11 For factory test purposes, not intended for use in any application. 6T SYNC pattern 7.5T SYNC pattern 9T SYNC pattern FXTH870x6 104 Sensors Freescale Semiconductor, Inc. Table 61. LFCTL3 Register Field Descriptions (continued) Field Description LF Carrier Detect Time These read/write control bits select the length of time which the LFR input detector must detect a carrier before validating it. In carrier mode (CARMOD = 1), if the carrier is active for at least the time selected by the LFCDTM[3:0]

bits and the LFCC counter value is reached, the LFCDF flag in the LFS register will be set; and if the LFCDIE control bit is also set, the MCU will be interrupted (wakeup). In the data receive mode (CARMOD = 0) the LFCDTM[3:0] bits select the length of time which the LFR input detector must detect a carrier before the effective receive chain is powered on. Once the carrier has been validated the LFCDTM[3:0] bits ignored during the decode of the rest of the data. Reset of the LFR results in LFCDTM[3:0] being reset to 0:0:0:0. The resulting carrier detect times are defined by the following number of carrier periods needed to validate the carrier, with the corresponding time for a carrier at 125 kHz in parenthesis:

3:0 LFCDTM

[3:0]

0000 Carrier detect = 8 (64 sec)Data mode detect = 8 (64 sec) 0001 Carrier detect = 16 (128 sec)Data mode detect = 8 (64 sec) 0010 Carrier detect = 32 (256 sec)Data mode detect = 8 (64 sec) 0011 Carrier detect = 64 (512 sec)Data mode detect = 8 (64 sec) 0100 Carrier detect = 128 (1024 sec)Data mode detect = 8 (64 sec) 0101 Carrier detect = 256 (2048 sec)Data mode detect = 8 (64 sec) 0110 Carrier detect = 512 (4096 sec)Data mode detect = 8 (64 sec) 0111 Carrier detect = 1024 (8192 sec)Data mode detect = 8 (64 sec) 1000 Carrier detect = 8 (64 sec)Data mode detect = 8 (64 sec) 1001 Carrier detect = 16 (128 sec)Data mode detect = 16 (128 sec) 1010 Carrier detect = 32 (256 sec)Data mode detect = 32 (256 sec) 1011 Carrier detect = 64 (512 sec)Data mode detect = 64 (512 sec) 1100 Carrier detect = 128 (1024 sec)Data mode detect = 128 (1024 sec) (see note) 1101 Carrier detect = 256 (2048 sec)Data mode detect = 256 (2048 sec) (see note) 1110 Carrier detect = 512 (4096 sec)Data mode detect = 512 (4096 sec) (see note) 1111 Carrier detect = 1024 (8192 sec)Data mode detect = 1024 (8192 sec) (see note) NOTE The auto-zero sequence needs to be performed every 1 ms. Therefore LFR detection times of 1024, 2048, 4096 and 8192 sec the auto-zero sequence will be done at each 1 ms interval. This auto-zero sequence lasts for 64 sec. If the carrier is detected again at the end of the auto-zero sequence it is assumed that the carrier was there for the complete 64 sec period of the auto-zero. Sensors Freescale Semiconductor, Inc. FXTH870x6 105 12.17.4 LFR Control Register 4 (LFCTL4) LFCTL4 contains local interrupt enable control bits. The provided I-interrupts are not globally masked by the I bit in the CPUs CCR, setting one or more of these interrupt enable control bits will cause a CPU interrupt to be requested whenever the flag bit associated with the corresponding LFR interrupt source becomes set. It is good practice to clear any flag bits in the LFS register before setting interrupt enable bits in this register in order to avoid an immediate interrupt request.

$0023 Bit 7 6 5 4 3 2 R W Reset:

LFDRIE LFERIE LFCDIE LFIDIE DECEN VALEN 0 0 0 0 1 1 Figure 79. LFR Control Register 4 (LFCTL4) 1 0 Bit 0 TIMOUT[1:0]

0 Table 62. LFCTL4 Register Field Descriptions Field 7 LFDRIE 6 LFERIE 5 LFCDIE 4 LFIDIE 3 DECEN 2 VALEN 1:0 TIMOUT

[1:0]

Description LFR Data Register Full Interrupt Enable This read/write bit enables interrupts to be requested when the LFR data register is full. Reset clears LFDRIE. 0 LFDRF interrupts disabled. Use software polling. 1 LFR Data Register Full interrupts are enabled. If LFDRIE is set, then an interrupt is requested when LFDRF = 1. LFR Error Interrupt Enable This read/write bit enables interrupts to be requested when the LFR detects an error in reception of a non-Manchester encoded bit time following the SYNC time. Reset clears LFERIE. 0 LFERF interrupts disabled. Use software polling. 1 LFERF interrupts are enabled. If LFERIE is set, then an interrupt is requested when LFERF = 1. LFR Carrier Detect Interrupt Enable This read/write bit enables the LFCDF interrupt when the LFR detects the number of samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register. The LFCDIE is ignored when the LFR is operating in the data mode (CARMOD = 0), except when DECEN is cleared. Reset clears LFCDIE. 0 LFCDF interrupts disabled. 1 LFR LFCDF interrupts are enabled. If LFCDIE is set, then an interrupt is requested when LFCDF = 1. LFR ID Detect Interrupt Enable This read/write bit enables interrupts to be requested when the LFR detects a match to the ID code selected in the LFIDH:L registers. Reset clears LFIDIE. 0 LFIDF interrupts disabled. 1 LFIDF interrupts are enabled. If LFIDIE is set, then an interrupt is requested when LFIDF = 1. LF Digital Decode Enable This read/write bit enables the data processing by the digital decoder. When disabled, the frame format (Manchester, data-rate, SYNC, data) is not checked. There is no more error flag assertion (data, error, ID). The MCU should then poll the LFDO bit to extract from the analog detector the bit stream. Reset sets the DECEN bit. 0 Digital decoder is disabled. 1 Digital decoder is enabled. LF Validation Enable This read/write bit enables the carrier validation process. Reset sets this bit. 0 Carrier Validation disabled. 1 Carrier Validation enabled. SYNC Time Out Select These two read/write bits select the period of time that the LFR will search for a SYNC pattern in the data mode. If the SYNC pattern is not detected the LFR will be turned off after this delay time. These time intervals are clocked by the internal LFRO clock. Reset clears TIMOUT bit. 00 01 10 11 SYNC word is continuously searched no timeout. SYNC search time set to nominal 8 milliseconds. SYNC search time set to nominal 24 milliseconds. SYNC search time set to nominal 48 milliseconds. FXTH870x6 106 Sensors Freescale Semiconductor, Inc. 12.17.5 LFR Status Register (LFS, LPAGE = 0) LFS contains the data ready status flags. It is only accessible when the LPAGE bit is clear.

$0024 R W Reset:

Bit 7 LFDRF 0 6 5 LFERF LFCDF 4 LFIDF 3 2 LFOVF LFEOMF 0

= Reserved 0 0 0 0 Figure 80. LFR Status Register (LFS, LPAGE = 0) 1 LPSM 1 Bit 0 0 LFIAK 0 Table 63. LFS Register Field Descriptions Field 7 LFDRF 6 LFERF 5 LFCDF 4 LFIDF 3 LFOVF 2 LFEOMF 1 LPSM 0 LFIAK Description LF Data Ready Flag This read-only status flag is set when a complete byte of data has been received by the LFR. An interrupt is sent to the MCU if the LFDRIE bit is set. Clear LFDRF by writing a one to the LFIAK bit or reading the LFDATA register. LFDRF is also cleared by reset. 0 No new data in LFDATA register. 1 A new byte of data has been received and can be read from the LFDATA register. LF Receive Error Flag In data receive mode, this read-only status flag is set when a non-standard bit time is detected in the Manchester data mode. Any received data bits before the error occurs are placed in the data buffer. In carrier detect mode, this read-only status flag is not used and remains clear. An interrupt is sent to the MCU if the LFERIE bit is set. Clear LFERF by writing a one to the LFIAK bit. LFERF is also cleared by reset. 0 Normal operation. 1 Error detected in the Manchester data mode. LF Carrier Pulse Detect Flag In carrier detect mode, this read-only status flag is set when the number of consecutive carrier validations set by the LFCC bits in is reached. Note that the LFCC function is not working if TOGMOD = 1. Clear LFCDF by writing a one to the LFIAK bit. LFCDF is also cleared by reset. 0 Normal operation. 1 Carrier detection has occurred. LF ID Detect Flag In data receive mode, this read-only status flag is set when the received ID matches the stored value. This interrupt can be generated even if no data bits follow the ID. An interrupt is sent to the MCU if the LFIDIE bit is set. Clear LFIDF by writing a one to the LFIAK bit. LFIDF is also cleared by reset. 0 Normal operation. 1 wakeup ID has been detected. LF Receive Data Overflow Flag In data receive mode, this read-only status flag is set when a complete byte of data has been received and written into the LFDATA register, but the previously received byte was not read from LFDATA register yet. This indicates that the MCU has lost the previously received data byte. In carrier detect mode, this read-only status flag is not used and remains cleared. No separate interrupt is generated by this specific flag bit because the LFDRF flag would serve that purpose. Clear LFOVF by writing a one to the LFIAK bit. LFOVF is also cleared by reset. 0 Normal operation. 1 Previous data over-written before MCU read it. LF Receive Data EOM Flag In data receive mode, this read-only status flag is set when a complete byte of data has been received and written into the LFDATA register and an end-of-message Manchester encoding error occurs. In carrier detect mode, this read-only status flag is not used and remains clear. No interrupt is generated by this flag bit because the LFERF flag would serve that purpose. Clear LFEOMF by writing a one to the LFIAK bit. LFEOMF is also cleared by reset. 0 No EOM detected. 1 EOM detected. Low Power Sniff Mode This bit used to activate the low power consumption during SNIFF mode. It saves approximately 1 A with a trade-off of an additional 200 s in transition from carrier to data mode. LPSM is set by reset. 0 Low time transition from carrier to data mode 1 Low consumption during sniff mode LF Interrupt Acknowledge Writing a one to the LFIAK bit clears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits. When a one is written to the LFIAK, it is automatically cleared at the next positive edge of the MCU bus clock. Then, reading the LFIAK bit is allowed but will always return zero. Writing a zero the LFIAK bit has no effect. Reset has no effect on this bit. 0 No effect. 1 Clears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits. Sensors Freescale Semiconductor, Inc. FXTH870x6 107 12.17.6 LFR Data Register (LFDATA, LPAGE = 0) The LFDATA is a read-only register that contains the most recent received data value. It is only accessible when the LPAGE bit is clear. As data is serially received by the LFR, it is assembled into 8-bit values. When a new complete 8-bit value is received, it is moved into the LFDATA register, over-writing any previous value, and the LFDRF data ready flag is set to indicate a value is available for the MCU to read. If a previous value was ready but was not read out of the LFDATA register before a new data byte is ready, the LFOVF overflow flag is also set to indicate this overflow condition. Writes to LFDATA have no meaning or effect.

$0025 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 RXDATA[7:0]

4 0 3 0 2 0 1 0 Bit 0 0 Figure 81. LFR Data Register (LFDATA) when LPAGE = 0 Table 64. LFDATA Register Field Descriptions Field 7:0 RXDATA

[7:0]

Receive Data [7:0] This is the received data from the LFR when in the data mode. All bits are read-only and any writes to these bits will be ignored. Reading this register will clear the LFDRF. Description 12.17.7 LFR ID Registers (LFIDH:LFIDL, LPAGE = 0) These two 8-bit read/write registers hold one of two ID values for LF messages. They are only accessible when the LPAGE bit is clear. The type of ID checking can be selected or disabled by using the IDSEL[1:0] bits in the LFCTL1 register. When ID checking is enabled, the ID value received through the LFR must match the contents of the LFIDH and/or LFIDL registers depending on the IDSEL bits or the message will be ignored and the MCU will remain in standby mode to minimize power consumption. All these bits are cleared by a reset.

$0026 Bit 7 R W Reset:

0

$0027 Bit 7 R W Reset:

0 6 0 6 0 5 0 4 0 ID[0:7]

3 0 Figure 82. LFR ID Low Byte (LFIDL) 5 0 4 0 ID[15:8]

3 0 Figure 83. LFR ID High Byte (LFIDH) 2 0 2 0 1 0 1 0 Bit 0 0 Bit 0 0 Table 65. LFR ID Register Field Description Field ID[15:0]

ID bits 15 through 0 These read/write bits contain bits 15 through 0 of the 16-bit ID value. Description FXTH870x6 108 Sensors Freescale Semiconductor, Inc. 12.17.7.1 LF Control E - LFCTRLE

$0021 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 1 Bit 0 AZSC2 AZSC1 AZSC0 0 0 0 Figure 84. LF Control E (LFCTRLE) Table 66. LFCTRLE Register Field Description Field 7-3 Reserved 2-0 AZSC Description Reserved bits Not for user access. LOGAMP AZ Sequencer Control Control bits for AZ and trim within the LOGAMP. X00 Nominal AZ sequence - recommended setting X01 Short amp output release, max delay with Rects X10 Short amp output release, max delay with Amp input X11 All short, max delay with end of AZ 0XX Nominal sensitivity trim - recommended setting 1XX Sensitivities shifted by - 4 trim steps 12.17.8 LFR Control Register D (LFCTRLD, LPAGE = 1) The LFCTRLD register contains two control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0022 Bit 7 R W Reset:

AVFOF[1:0]

0 6 0 5 DEQS 0 4 0 AZDC[1:0]

3 0 2 ONMODE 0 1 0 Bit 0 CHK125[1:0]

0 Figure 85. LFR Control Register D (LFCTRLD, LPAGE = 1) Table 67. LFCTRLD Register Field Descriptions Field 7-6 AVFOF

[1:0]

5 DEQS 4-3 AZDC

[1:0]

2 ONMODE Description SUM AZ release delay Control the delay between falling edge of SUM d_az_en input and falling edge of internal AZ control line. 00 No delay 01 No delay 10 One-half of 125 kHz clock period delay - recommended setting 11 One and one-half of 125 kHz clock periods delay DeQing status register This read-only status bit allows the reading of the effective activation of the DeQing System. 0 DeQing system not activated 1 DeQing system activated AZ Digital Control of AZ triggering In data receive mode, this bits control the triggering of AZ sequence with respect to both LFCPTAZ value (ref. LFCTRLB register) and the state of the demodulation input data state. 00 AZ starts after LFCPTAZ numbers of input data edges. 01 Z starts randomly adding -1, 0 or 1 to LFCPTAZ value between each AZ. 10 AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 0. 11 AZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 1 -

ON Behavior Mode This read/write bit selects how an error will affect the ON time. This bit is cleared by reset. 0 Any error will stop the ON time. 1 If remaining ON time, the LFR will go back to sniff mode at any error - recommended setting. recommended setting. Sensors Freescale Semiconductor, Inc. FXTH870x6 109 Table 67. LFCTRLD Register Field Descriptions (continued) Field Description Accurate 125 kHz Check The bit controls the CARVAL frequency check method. 00 CARVAL validates on n (2*32 s packets), n depending on LFCDTM value - recommended setting for Low Sensitivity mode. CARVAL validates on n (1*32 s packet + 4*8 s packets), n depending on LFCDTM value - optional recommended setting for High Sensitivity mode. CARVAL validates on n (8*8 s packet), n depending on LFCDTM value - optional recommended setting for High Sensitivity mode. Same as 00. 1-0 CHK125

[1:0]

01 10 11 Setting CHK125[1:0] to either 0x01 or 0x10 increases the immunity to noise and therefore carries the side effect of narrowing the 125 kHz carrier bandwidth tolerance. NOTE 12.17.9 LFR Control Register C (LFCTRLC, LPAGE = 1) The LFCTRLC register contains control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0023 Bit 7 R W Reset:

AMPGAIN[1:0]

1 6 1 5 0 FINSEL[1:0]

4 0 3 AZEN 1 2 0 LOWQ[1:0]

1 0 Bit 0 DEQEN 1 Figure 86. LFR Control Register C (LFCTRLC, LPAGE = 1) Table 68. LFCTRLC Register Field Descriptions Field 7-6 AMPGAIN

[1:0]

5-4 FINSEL

[1:0]

3 AZEN 2-1 LOWQ

[1:0]

0 DEQEN FXTH870x6 110 Description Gain of 2 - recommended setting Gain of 3 Gain of 4 Gain of 6 Continuous time biasing - Fixed Gain 6 Continuous time biasing - Programmable Gain - recommended setting 4th rectifier disabled 4th rectifier disabled 3rd Amplifier gain These bits controls the 3rd amplifier gain. 00 01 10 11 Final stage select These bits select the final stage of the LOGAMP. 00 01 10 11 Data AZ enable This bit allows the AZ sequence during data frame. 0 AZ during data disabled 1 AZ during data enabled - recommended setting DeQing Resistor These bits select the resistor added in parallel to the input network. 00 01 10 11 DeQing System enable The bit controls the DeQing system. 0 DeQing disabled. 1 DeQing enabled. 4 k 2 k 1 k 500 Sensors Freescale Semiconductor, Inc. 12.17.10 LFR Control Register B (LFCTRLB, LPAGE = 1) The LFCTRLB register contains control bits for the LF detector and decoder. It is only accessible when the LPAGE bit is set.

$0024 Bit 7 R W Reset:

HYST[1:0]

1 6 1 5 4 3 LFFAF LFCAF LFPOL 0 0 0 2 1 1 Bit 0 LCPTAZ[2:0]

0 0 Figure 87. LFR Control Register B (LFCTRLB, LPAGE = 1) Table 69. LFCTRLB Register Field Descriptions Field 7-6 HYST

[1:0]

5-4 LFFAF;

LFCAF 3 LFPOL 2-0 LFCPTAZ

[2:0]

Description Control slicer hysteresis 00 20 mV hysteresis 40 mV hysteresis 01 50 mV hysteresis 10 11 30 mV hysteresis - recommended setting Average filter bi-phase filtering control Activates bi-phase filtering and control offset value 00 01 10 11 LF Manchester Polarity Select This read/write bit selects the polarity of the transition in the middle of the bit time. The LFPOL is not used in Carrier mode. Reset clears LFPOL bit. 0 1 Standard low pass filtering activated - recommended setting Standard low pass filtering activated Bi-phase filtering activated - Low offset from input signal low level Bi-phase filtering activated - High offset from input signal low level Zero is falling edge in middle of a bit time, one is a rising edge in the middle of bit time. Zero is rising edge in middle of a bit time, one is a falling edge in the middle of bit time. LF auto-zero counter Applications to set these bits to 0x06 for proper LF operation. These bits tune the minimum number of data edges between two auto-zero requests during a data frame. Sensors Freescale Semiconductor, Inc. FXTH870x6 111 12.17.11 LFR Control Register A (LFCTRLA, LPAGE = 1) The LFCTRLA register contains control bits for the LF detector and factory test selects. It is only accessible when the LPAGE bit is set.

$0025 Bit 7 R W Reset:

0 6 0

= Reserved 5 0 4 0 3 0 2 0 LFCC[3:0]

1 0 Bit 0 0 Figure 88. LFR Control Register A (LFCTRLA, LPAGE = 1) Table 70. LFCTRLA Register Field Descriptions Field 7-4 Reserved 3-0 LFCC

[3:0]

Reserved bits Not for user access. Description LF Successive Carrier Validations Counter The value of the LFCC[3:0] bits define how many times the carrier detect sample ON time detected an LF carrier signal before the LFCDF flag bit set. The flag will be risen when the number of ON samples with a detected carrier greater than the LFCDTM[3:0] reaches the value of the LFCC[3:0] bits plus one. The internal count of detected carrier pulses will increment the count as long as they are consecutive samples. When a sample is encountered without any detected carrier the count will be reset. The LFCC register is considered reset in data mode. The first carrier validation will lead to start up of the receiver chain. This feature allows the user to define a number of consecutive carrier detections are required before the flag is risen; and is useful in detecting long duration carrier pulses. This counter is disabled if TOGMOD = 1. FXTH870x6 112 Sensors Freescale Semiconductor, Inc. RF Module 13 It is not intended that the RFM may be actively powered up and/or transmitting RF data while physical parameter measurements are being made; or during the time that the LFR may be actively receiving/decoding LF signals. The resulting interactions will degrade the performance of the RF output spectrum. The FXTH870x6 consists of an RF module (RFM) with external crystal-driven oscillator, VCO, fractal-n PLL and RF output amplifier (PA) for an antenna. It also contains a small state machine controller, random time generator and hardware data buffer for automated output or direct control from the MCU. The overall block diagram is shown in Figure 89. 256-BIT DATA BUFFER RF DX 500 kHz RINT MFO MCU XI XO AVDD AVSS VREG RF STATE MACHINE LFSR RANDOM GEN MODULATION CONTROL RF AMP CONTROL REGISTERS AND LOGIC FRACTIONAL-N DIVIDER CRYSTAL OSCILLATOR PHASE DETECTOR LOW-PASS FILTER VCO RF LVD VOLT REG RF AVDD Figure 89. RF Transmitter Block Diagram RF Data Modes RF Data Buffer Mode 13.1 There are two modes of operation in using the RF output in either the data buffer mode or MCU direct mode. 13.1.1 In the RF data buffer mode the transmissions are sent by dedicated logic hardware while the MCU can be put into a low power mode until the transmission is completed. This RF state machine is clocked by the MFO which is enabled when the SEND bit is set and when any of the LFR, SMI or MCU are operating. The RF data buffer consists of a dedicated RFM state machine and a 256-bit data buffer. The RF data buffer is loaded with whatever data pattern the user software creates. The number of data bits to be sent is selected by the FRM[7:0] control bits. The control logic is triggered by the SEND control bit when it is time to transmit the data which is sent to the RF stage after being encoded as either Manchester, Bi-Phase or NRZ data according to the method selected by the CODE[1:0] bits as described in Section 13.17. Before the data can be transmitted the RFM control logic enables the external crystal oscillator and phase-locked-loop to initialize before the RF output stage can begin transmission. Sensors Freescale Semiconductor, Inc. FXTH870x6 113 The external crystal connected to the X0 and XI pins provides the carrier frequency as well as the data rate clock needed for the data rates associated with the OOK or FSK modulation. Therefore the tolerance on the data rate will depend on the characteristics of the external crystal. Once the data buffer is emptied the data transfer stops; the RF output stage is turned off; and the SEND control bit is cleared and an interrupt of the MCU may be generated to wake it from the STOP1 mode. The user can test that the transmission has completed by reading back the state of the SEND control bit or the RFIF status bit. There is also the option to send the same data frame from 1 to 16 times with interlaced time intervals when the RF transmitter PA output stage is off. If multiple frames of data are to be transmitted within a datagram the spacing before the first frame and between subsequent frames can be controlled by the RFM state machine in several ways:

1. Use of a programmable timer (random, base time, time adder). 2. No time delays. In addition, the RFM crystal oscillator, VCO and PLL can be turned off during any interframe timing by use of the IFPD bit. When using the data buffer mode the users software should not change any bits in the RFM registers after the SEND has been set and the transmission is still in progress. Changing RFM register contents during a transmission can lead to data faults or errors. 13.1.2 MCU Direct Mode When the CODE[1:0] bits are both set the encoding is controlled directly by the MCU where the data to the RF output depends on the state of the DATA bit and the selected modulation scheme. In this mode the user software must control the RF output stage to power up (using the SEND control bit), WAIT for the RF output stage to stabilize (monitor the RCTS status bit) and clock the DATA to the RF output stage. In this mode the data rate and its stability will depend on the internal HFO oscillator. Any transfers of data from the MCU will use the DATA bit which will be reflected as modulated data on the RF pin once the RF output stage is set up to transmit. The maximum data rate in this mode will depend on the complexity of the user software and the MCU clock rate. The POL bit in this case simply inverts the state of the DATA bit before it drives the RF output stage. The accuracy of the data rate in the MCU direct mode is directly dependant on the HFO accuracy. RF Output Buffer Data Frame 13.2 When using the RF data buffer mode each frame of data is sent as 2 to 256 bits per frame with a possible two trailing bits for an end-of-message, EOM, as shown in Figure 90. The actual data being transmitted in a given data frame and any combinations of data frames into a single datagram is dependent on the user software. The number of frames sent in a given datagram can be from 1 to 16 based on the FNUM[3:0] bits in the RFCR3. The 256-bit buffer is divided into two pages of 128 bits as selected by the RPAGE bit in the RFCR2. The data buffer is unloaded to the RF output starting with the least significant bit (RFD0) in the least significant byte (RFB0) up through the most significant bit (RFD127) in the most significant byte (RFB15). This is often referred to as little-endian data ordering. FXTH870x6 114 Sensors Freescale Semiconductor, Inc. Maximum 258-Bit Format RFB0 RFB1 RFB2 RFB3 RFB4 256 RFB5 RFBA RFBB RFBC RFBD RFBE 2 M O E RFBF 80-Bit Format RFB0 RFB1 RFB2 53-Bit Format RFB0 RFB1 RFB2 80 RFB3 53 RFB3 2 Minimum 2-Bit Format RFB0 Bits [1:0]

RFB4 RFB5 RFB6 RFB7 RFB8 RFB9 RFB4 RFB5 2 M O E RFB6 Bits [2:0]

Optional EOM with all byte lengths Data in each byte defined by user software Figure 90. Data Frame Formats Data Buffer Length 13.2.1 The number of bits sent in a given transmission frame is selected by the FRM[7:0] control bits encoded as a direct binary number plus one. This gives a range of 2 through 256 bits. Data written to data buffer bits above the highest bit number will be ignored. Transmission always begins with the data written in the RFB0 location. When the requested number of bits have been transmitted an interrupt to the MCU can be generated if the RFIE bit is set. 13.2.2 If the EOM control bit is set, then at the end of the data frame there will be carrier for a period of two bit times at level high for the OOK modulation modes or fDATA1 for the FSK modulation modes. Following the EOM period there will be no carrier for either the OOK or FSK modes. If the EOM control bit is clear, no EOM period will be added to the transmission. End of Message (EOM) Sensors Freescale Semiconductor, Inc. FXTH870x6 115 Transmission Randomization 13.3 When there are two or more different transmitters, the clock rates of each may drift into synchronism with each other; and there is the possibility of RF data collisions and the loss of data from both transmitters. In order to reduce possible RF data collisions each transmission will contain from 1 to 16 frames of data. Each frame may be spaced at after the initially timed transmission start time and between any two data frames as shown in Figure 91. Time Not To Scale t0 1 to 16 Data Frames With Identical Data SPACE DATA FRAME SPACE DATA FRAME SPACE DATA FRAME Start of Time Interval for Datagram Interframe Intervals Initial Interval tDATA Space Intervals have No Carrier Frequency Output, equivalent to Data = 0 and may have the RFM crystal oscillator, VCO and PLL turned off by the IFPD bit. Figure 91. Datagram Overview The generation of the initial and interframe time intervals can be done with a combination of a programmable counter, a pseudo-

random interval generator and a frame counter as shown in Figure 92. The initial time interval can be done by adjusting the start time using the MCU or using this interval timing generator. Time Not To Scale t0 Initial Interval Interframe Interval 1 Interframe Interval 2 tBASE 40 x tRAND tBASE tRAND tFN tBASE tRAND tFN Start of Time Interval for Datagram tBASE, tRAND and tFN may be all zero in the initial interval. tBASE, tRAND and tFN may be all zero in an interframe interval. All interframe intervals may have different tBASE, tRAND and tFN times. Note: If tBASE and tFN are both set to non-zero, and tRAND is set to 0, the system will decrement both tBASE and tFN simultaneously rather than serially, such that the effective Interframe Interval will be equal to the larger of tBASE or tFN settings. Figure 92. Initial and Interframe Timing FXTH870x6 116 Sensors Freescale Semiconductor, Inc. Initial Time Interval 13.3.1 When generating an initial time interval the MCU loads the RFM interval generator variables and then goes into the STOP1 mode. When the initial time interval ends the data in the RFM data buffer is automatically sent and the MCU will wake at the end of the transmission. The initial time interval is made up of two components:

tINIT

=

tBASE 40

+

tRAND Eqn. 10 where:

tINIT = Total time interval before first frame is transmitted in ms tBASE = Base time in ms; 5 ms not recommended tRAND = Pseudo-random time in ms based on a Galois 7-bit LFSR Interframe Time Intervals The components of this time are described in the following sections. 13.3.2 When generating an interframe time interval the MCU loads the RFM interval generator variables and then goes to the STOP1 mode. When the interframe time interval ends the data in the RFM data buffer is automatically sent and the MCU will wake at the end of the transmission. The interframe time interval is made up of three components:

tIFRM tBASE tRAND tFN

=

+

+

Eqn. 11 where:

tIFRM = Total time interval between each transmitted frame in ms tBASE = Base time in ms; 5 ms not recommended tFN = Time adder in ms for frame number tRAND = Pseudo-random time in ms based on a Galois 7-bit LFSR Base Time Interval Pseudo-Random Time Interval The components of this time are described in the following sections. 13.3.3 The base time interval, tBASE, is used in the initial time interval and in datagram transmissions with two or more frames. The programmable frame space interval is based on a simple 8-bit, count-down timer as described by the RFBT[7:0] control bits in the RFCR4 register. This time interval is forced to zero when the RFBT[7:0] are all clear. The range of the base time must be set to 0 or between 5 and 255 ms using a clock generated from the MFO divided by 125. 13.3.4 The pseudo-random time interval, tRAND, is used both in the initial and the interframe time intervals if the LFSR[6;0] bits are set to something other than all zeros. When the ISPC bit is set the pseudo-random initial time interval before the first data frame will be 40 times the value of tRAND. When the LFSR[6:0] bits are used the tRAND time will vary based on a pseudo-random generated binary number using a Galois linear feedback shift register (LFSR) implemented using the primitive polynomial for a 7-stage register as shown in Figure 93. This LFSR creates a sequence of 127 binary numbers including $01 through $3F which are each repeated only once in each sequence of 127 clocks of the shift register. The LFSR is initialized to $40 during power up of the device. When a random interval is to be determined the contents of the LFSR are sampled as the random number for calculating the required interval time. Following the use of the random interval the LFSR is clocked once to advance it to the next pseudo-random number. The range of the pseudo-random time is 1 to 127 ms using a clock generated from the MFO divided by 125. The current value of the LFSR can be changed and/or read by the LFSR[6:0] bits in the RFCR5 register. Sensors Freescale Semiconductor, Inc. FXTH870x6 117 S0 S1 S2 7-BIT Random Number S3 S4 S5 S6 D Q D Q D Q D Q D Q D Q S D Q R R R R R R CLK RFMRST Galois Primitive Polynomial = X 7 3

+ 1

+ X Figure 93. LFSR Implementation A value of all zeros in the LFSR will remain unchanged with every clock input and cannot be used as a starting seed. The resulting range of times for the initial and interframe pseudo-random time will be as given in Table 71 for both the design center and the variation resulting from the tolerance of the MFO clock. Table 71. Randomization Interval Times Time Interval Initial Interframe Randomization Number Ideal Time Interval (ms) 1 127 1 127 40 5080 1 127 Time Interval Including MFO Tolerance (ms) Minimum 37.2 4347.2 0.93 118.1 Maximum 42.8 5434.6 1.07 135.9 Frame Number Time 13.3.5 The frame number time, tFN, is only used between frames and is based on a selectable time from 0 to 63 ms and the number of the frame that was just transmitted as given in Table 72. If the frame number time is not used, the value of the selected time should be set to zero. The maximum number of frames is defined by the FNUM[3:0] control bits. The range of the frame number time is a multiple of 0 to 63 ms using a clock generated from the MFO divided by 125. The value of this time multiple can be changed by the RFFT[5:0] bits in the RFCR6 register. Table 72. Frame Number Interval Times Value of FNUM[3:0]

Number of Frames Frame Interval Where Time Added Nominal Frame Number Time Interval Added (ms) Minimum Maximum 0 1 2 3 4 5 6 7 8 FXTH870x6 118 1 2 3 4 5 6 7 8 9 None 1 - 2 2 - 3 3 - 4 4 - 5 5 - 6 6 - 7 7 - 8 8 - 9 n/a 1 2 3 4 5 6 7 8 n/a 63 126 189 252 315 378 441 504 Sensors Freescale Semiconductor, Inc. Table 72. Frame Number Interval Times (continued) Value of FNUM[3:0]

Number of Frames Frame Interval Where Time Added Nominal Frame Number Time Interval Added (ms) Minimum Maximum 9 10 11 12 13 14 15 10 11 12 13 14 15 16 9 - 10 10 - 11 11 - 12 12 - 13 13 - 14 14 - 15 15 - 16 9 10 11 12 13 14 15 567 630 693 756 819 882 945 RFM in STOP1 Mode 13.4 The entire RF transmitter digital section can remain powered up, if enabled by the RFEN bit (see Section 5.3), when the MCU goes into the STOP1 mode. Data Encoding 13.5 The CODE[1:0] control bits select either Manchester, Bi-Phase, NRZ or MCU direct data encoding of each data bit being transferred from the RF data buffer to the RF output stage. Further, the polarity of the selected encoding method can be inverted using the POL control bit. 13.5.1 Manchester Encoding When the CODE[1:0] bits are both clear the data is Manchester encoded format, with data transmitted as a transition in voltage occurring in the middle of the bit time. The polarity of this transition is selected by the POL bit. When the POL bit is cleared, then a logical LOW is defined as an increase in signal in the middle of a bit time and a logical HIGH is defined as a decrease in signal in the middle of a bit time as shown in Figure 94. When the POL bit is set, then a logical LOW is defined as an decrease in signal in the middle of a bit time and a logical HIGH is defined as a increase in signal in the middle of a bit time as shown in Figure 95. Since there is always a transition in the middle of the bit time there must also be a transition at the start of a bit time if consecutive 1 or 0 data are present. 13.5.2 When the CODE[1:0] bits are 0:1 then the data is Bi-Phase encoded format, with data transmitted as the presence or absence of a transition in signal in the middle of the bit time. The polarity of this transition is selected by the POL bit. Unlike Manchester coding there is always a signal transition at the boundaries of each bit time. When the POL bit is cleared, then a logical HIGH is defined as no change in signal in the middle of a bit time and a logical LOW is defined as a change in the signal in the middle of a bit time as shown in Figure 96. When the POL bit is set, then a logical HIGH is defined as a change in signal in the middle of a bit time and a logical LOW is defined as no change in the signal in the middle of a bit time as shown in Figure 97. Since there is always a transition at the ends of the bit time consecutive bits of the same state may have two signal states (high or low) during the middle of the bit time. 13.5.3 When the CODE[1:0] bits are 1:0 then the data is NRZ encoded format, with data transmitted as either a high or low for the complete bit time. The polarity of this state is selected by the POL bit. The Manchester and Bi-Phase encoding can actually be created using NRZ encoding running at twice the desired data rate. Bi-Phase Encoding NRZ Encoding Sensors Freescale Semiconductor, Inc. FXTH870x6 119 LOW BIT HIGH BIT Bit Time Bit Time OOK = fRF OOK = OFF FSK = fRF+ f FSK = fRF - f Consecutive 0 Data Bits Consecutive 1 Data Bits 001101 Data Bits Figure 94. Manchester Data Bit Encoding (POL = 0) LOW BIT HIGH BIT Bit Time Bit Time OOK = fRF OOK = OFF FSK = fRF+ f FSK = fRF - f Consecutive 0 Data Bits Consecutive 1 Data Bits 001101 Data Bits Figure 95. Manchester Data Bit Encoding (POL = 1) FXTH870x6 120 Sensors Freescale Semiconductor, Inc. LOW BIT LOW BIT HIGH BIT HIGH BIT OOK = fRF OOK = OFF Bit Time Bit Time Bit Time Bit Time Figure 96. Bi-Phase Data Bit Encoding (POL = 0) LOW BIT LOW BIT HIGH BIT HIGH BIT Bit Time Bit Time Bit Time Bit Time OOK = fRF OOK = OFF FSK = fRF+ f FSK = fRF - f Consecutive 0 Data Bits Consecutive 1 Data Bits 001101 Data Bits FSK = fRF+ f FSK = fRF - f Consecutive 0 Data Bits Consecutive 1 Data Bits 001101 Data Bits Figure 97. Bi-Phase Data Bit Encoding (POL = 1) RF Output Stage 13.6 The RF output stage consists of a PLL, control logic and an output RF amplifier. Data is sent to the RF output stage from either the RF data buffer or the DATA bit in the RFCR3 depending on the selected mode of operation as described in Section 13.1. The RF output stage is enabled by the state of the SEND control bit. The PLL in the RF output stage will signal back via the RCTS status bit when the PLL is locked and ready to transmit. 13.6.1 Modulation Method The modulation control bit, MOD, described in Section 13.18, sets the modulation of the RF signal will be either amplitude shift keying (OOK) or frequency shift keying (FSK) with several options for the frequency shift. When operating in the FSK mode the internal, fractional-n PLL divider will be used to create the two carrier frequencies for data zero and data one. This method is more effective and robust than pulling the external crystal in order to shift the carrier frequency. Sensors Freescale Semiconductor, Inc. FXTH870x6 121 Carrier Frequency 13.6.2 The carrier frequency is established mainly by the external crystal used, but a centering of the fractional-n PLL provides more precise control. If the CF control bit is clear the PLL will be configured for a carrier center frequency of the 315 MHz. If the CF control bit is set the PLL will be configured for a carrier center frequency of the 434 MHz. 13.6.3 The maximum power output from the RF pin can be adjusted to one of 21 levels using the PWR[4:0] bits. 13.6.4 Any transmission will be aborted if one of the following occurs:

Transmission Error RF Power Output 1. The RCTS signal does not become active within the tLOCK time. 2. The PLL falls out of lock after once being set and the SEND bit is still active. 3. The XCO monitor output falls. Supply Voltage Check During RF Transmission If either of these cases occurs the RF output will be turned off; the SEND control bit will be cleared; and the transmission error status flag, RFEF, will be set. The RFEF bit triggers an interrupt of the MCU if the RFIEN is set. The RFEF bit is cleared by writing a logical one to the RFIAK bit. 13.6.5 A separate low voltage detector can be enabled during the RF transmission and a status bit checked for low voltage drops due to a weak battery during the higher transmission currents. This RF LVD can be enabled by setting the RFLVDEN bit and the resulting status is reported on the RFVF bit. The RFVF bit can be cleared by writing a logical one to the RFIAK bit if the supply voltage has risen above the detect threshold. Further, if the voltage falls far enough for the VCO and PLL to fall out-of-lock, then the RF output will be turned off and the transmission will be terminated. 13.6.6 The RF state machine, crystal oscillator, PLL and VCO can be reset to the initial off state by the RFMRST signal generated by one of the following methods:

RF Reset (RFMRST) Internal RFM power-on reset (RFPOR). 1. 2. Writing a one to the RFMRST bit in the RFCR7. Any of these reset methods will not alter any data stored in the data buffer. RF Interrupt 13.7 The RFM will interrupt the MCU when the SEND bit is cleared at the end of a data buffer transmission. This interrupt occurs at the end of a programmed set of frames. If the number of frame count FNUM[3:0] is set to zero, then only one frame is sent and the interrupt occurs at the end of that first frame transmitted. If the number of the frame count is greater than zero, then the interrupt will be generated depending on the state of the IFID bit. The interrupt will also create a flag bit, RFIF, which can be cleared by writing a logical one to the RFIAK bit. The interrupt can be enabled/disabled by the RFIEN bit. Datagram Transmission Times 13.8 In order to comply with FCC requirements in the US market the periodically transmitted datagram must be less than 1 second in length and be separated by an off time that is at least 10 seconds or at least 30 times longer than the transmission time, whichever is longer. The user software must adhere to this ruling for products intended for the US market. FXTH870x6 122 Sensors Freescale Semiconductor, Inc. RFM Registers 13.9 The RFM contains twelve registers to control its functions and 32 registers to provide access to the output data buffer. 13.9.1 The RFCR0 register contains eight control bits for setting the output data rate of the RFM as described in Figure 98. RFM Control Register 0 - RFCR0

$0030 R W RFMRST:

Bit 7 0 6 0 5 1 4 1 BPS[7:0]

3 0 2 1 1 0 Bit 0 0 Figure 98. RFM Control Register 0 (RFCR0) Table 73. RFCR0 Field Descriptions Field Description Data Rate - The BPS[7:0] control bits select the data rate for the transmitted datagrams as described by the following equation:

70 BPS[7:0]

where:

fDATA

=

fXTAL

-------------------------------------

52 BPS 1+

=

5x105

-------------------------

BPS 1+

fDATA= Data rate in bits/second fXTAL= External crystal frequency in Hz = 26 MHz BPS= Value of data rate code (BPS[7:0]) Examples of the value for common data rates are given in Table 74. The BPS[7:0] control bits are set to $34 by the RFMRST signal which results in a default data rate of 9600 bits/sec. Table 74. Data Rate Option Examples Data Rate Target 2000 bps 2400 bps 4000 bps 4500 bps Nominal 2000.0 2403.8 4000.0 4504.5 BPS[7:0]

Decimal Value fXTAL = 26 MHz 249 207 124 110 Data Rate Target 4800 bps 5000 bps 9600 bps 19200 bps Nominal 4807.7 5000.0 9615.4 19230.8 BPS[7:0]

Decimal Value fXTAL = 26 MHz 103 99 51 25 The BPS[7:0] bits are set to $34 by an RFMRST signal which results in a default data rate of approximately 9600 bps. 13.10 RFM Control Register 1 - RFCR1 The RFCR1 register contains eight control bits for the RFM as described in Figure 99.

$0031 R W RFMRST:

Bit 7 0 6 0 5 0 4 0 FRM[7:0]

3 0 2 0 1 0 Bit 0 0 Figure 99. RFM Control Register 1 (RFCR1) Sensors Freescale Semiconductor, Inc. FXTH870x6 123 Table 75. RFCR1 Field Descriptions Field 7-0 FRM[7:0]

Frame Bit Length - The FRM[7:0] control bits select the number of bits in each datagram. The number of bits is determined by the binary value of the FRM[7:0] bits plus one. This makes the range of bits from 2 to 256. A value of $00 for the FRM[7:0] control bits will result in no frames being sent. The FRM[7:0] control bits are cleared by RFMRST signal. Description 13.11 The RFCR2 register contains eight control bits for the RFM as described in Figure 100. RFM Control Register 2 - RFCR2

$0032 R W RFMRST:

Bit 7 SEND 0 6 5 RPAGE EOM 0 0 4 0 3 0 2 PWR[4:0]

0 1 0 Bit 0 0 Figure 100. RFM Control Register 2 (RFCR2) Table 76. RFCR2 Field Descriptions Field 7 SEND 6 RPAGE 5 EOM Description Transmission Start Control- The SEND control bit starts the transmission of data held in the RFM data buffer according to the bit length specified by the FRM[7:0] bits. The SEND control bit is automatically cleared when the data buffer transmission has ended or by the RFMRST signal. A transmission can be prematurely interrupted by writing a logical zero to the SEND bit. 0 Data transmission ended or transmission not in progress. 1 Start data transmission or transmission in progress. Buffer Page Select The RPAGE bit will select the lower or upper 16 bytes of the RFM data buffer when writing/reading to the RFD0-RD15 registers. This bit also selects between the lower and upper banks of RFM registers at addresses $0038 through

$003B. This bit is cleared by a reset of the MCU. 0 Select the lower 16 bytes of the RFM data buffer. 1 Select the upper 16 bytes of the RFM data buffer. End Of Message - The EOM control bit selects whether there will be two data bit times of data 1 carrier state at the end of each datagram. The EOM control bit is cleared by a RFMRST. 0 EOM bit times not added. 1 EOM bit times added. FXTH870x6 124 Sensors Freescale Semiconductor, Inc. Table 76. RFCR2 Field Descriptions (continued) Field Description 4:0 PWR[4:0]

RF Amplifier Power Level - The PWR[4:0] control bits select the optimum power output of the RF power amplifier. These power output levels assume optimal matching network to the RF pin. The PWR[4:0] control bits are cleared a RFM reset. The PWR control bits are initially set to 0x00. This setting targets -10 dBm typical power output. The PWR control bits scale the typical output power level from -1.5 to 8 dBm in steps of 0.5 dB and fixes the low power level mode to -10 dBm, The power control range is defined as follows:

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Codes greater than 10100 are reserved for test purposes and should not be used. set output power level to -10 dBm (Default Value) set output power level to -1.5 dBm set output power level to -1.0 dBm set output power level to -0.5 dBm set output power level to 0.0 dBm set output power level to 0.5 dBm set output power level to 1.0 dBm set output power level to 1.5 dBm set output power level to 2.0 dBm set output power level to 2.5 dBm set output power level to 3.0 dBm set output power level to 3.5 dBm set output power level to 4.0 dBm set output power level to 4.5 dBm set output power level to 5.0 dBm set output power level to 5.5 dBm set output power level to 6.0 dBm set output power level to 6.5 dBm set output power level to 7.0 dBm set output power level to 7.5 dBm set output power level to 8.0 dBm Sensors Freescale Semiconductor, Inc. FXTH870x6 125 13.11.1 Power Working Domains The working areas of the RF transmitter are divided into several domains as defined in Figure 101. PTYP TA = 25 C to 60 C and VDD = 2.5 V to 3.6 V PTYP is where the power step is adjusted to guarantee 5 dBm. The power consumption in this domain is specified at 5 dBm output power step at nominal conditions of TA = 25 C and VDD = 3 VDC. PMIN PMIN is where the power step is adjusted to guarantee a minimum of 3 dBm as shown in Figure 101. The power consumption in this domain is given as the maximum consumption at whatever temperature of supply voltage condition. The PMIN domain is subdivided into two areas according to the lowest supply voltage encountered (1.8 or 2.5 VDC). PMIN_COLD PMIN_HOT TA = -40 C to 0 C and VDD = 1.8 V to 3.6 V TA = 0 C to 25 C and VDD = 2.5 V to 3.6 V TA = 60 C to 125 C and VDD = 2.5 V to 3.6 V Typical Consumption VDD = 3.6 V VDD = 3.0 V VDD = 2.5 V VDD = 1.8 V PMIN_COLD PMIN_HOT PTYP PMIN_HOT TA = -40 C TA = 0 C TA = 25 C TA = 60 C TA = 125C Figure 101. RF Power Domains FXTH870x6 126 Sensors Freescale Semiconductor, Inc. 13.12 RFM Control Register 3 - RFCR3 The RFCR3 register contains five control bits for the RFM as described in Figure 102 which sets the number of frames in each RF datagram.

$0033 R W RFMRST Bit 7 DATA 0 6 IFPD 0 5 ISPC 0 4 IFID 0 3 0 2 0 FNUM[3:0 1 0 Bit 0 0 Figure 102. RFM Control Register 3 (RFCR3) Table 77. RFCR3 Field Descriptions Field 7 DATA 6 IFPD 5 ISPC 4 IFID 3-0 FNUM

[3:0]

Description Data State - The DATA bit determines the output state of the RF power amplifier when the RFM is in the MCU direct control mode

(CODE[1:0] = 11) 0 RF output state low. 1 RF output state high. Interframe Power Down The IFPD control bit selects whether the XCO and associated analog blocks are powered down during interframe timing caused by the RFM. The IFPD control bit is cleared by the RFMRST signal. 0 The XCO remains powered up as long as the SEND bit is set. 1 The XCO is powered down during RFM controlled interframe timing events. The restart of these functions will start 1 ms before the end of the timing interval if another frame is to be transmitted. Initial Random Space When the ISPC bit is set the initial time delay before the first frame will be enabled. This bit is cleared by an RFM reset. 0 No initial time interval. 1 Initial time interval enabled. Interframe Interrupt Delay The IFID control bit selects whether the RFIF bit is set and the MCU is interrupted at the end of each frame sent or at the end of the last frame in a multiple frame message. The IFID control bit is cleared by the RFMRST signal. 0 The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, after the last frame transmitted. 1 The RFIF bit is set and the MCU interrupted if the RFIEN bit is set, only after the last frame plus an additional interframe message is transmitted. FNUM[3:0] The FNUM[3:0] bits set the number of frames transmitted in each RF datagram. The frames will be randomly spaced apart as described it Section 13.3.These bits are cleared by an RFM reset. The number of frame transmitted is the binary number plus one. Sensors Freescale Semiconductor, Inc. FXTH870x6 127 13.13 RFM Control Register 4 - RFCR4 The RFCR4 register contains eight control bits to set the initial and interframe timing base timing variable as described in Figure 103. A RFMRST signal clears the RFBT[7:0] bits.

$0034 R W RFMRST:

Bit 7 1 6 0 5 0 4 0 RFBT[7:0]

3 0 2 0 1 0 Bit 0 0 Figure 103. RFCR4 Register - Base Time Variable Table 78. RFCR4 Field Descriptions Field 7:0 RFBT

[7:0]

Base Timer - The RFBT[7:0] control bits select the interframe timing between multiple frames of transmission. The base time value is equal to a nominal one millisecond for each count of the RFBT[7:0] bits. The RFBT[7:0] control bits are cleared by the RFMRST signal and must be set to either 0 or between 5 and 255. Description 13.14 RFM Control Register 5 - RFCR5 The RFCR5 register contains eight control bits to set the initial and interframe random timing variable as described in Figure 104. A RFMRST signal clears the LFSR[6:0] bits causing the random time variable to be ignored.

$0035 R W RFMRST:

Bit 7 BOOST 0 6 0 5 0 4 0 3 LFSR[6:0]

0 2 0 1 0 Bit 0 0 Figure 104. RFCR5 Register - Pseudo-Random Time Variable Table 79. RFCR5 Field Descriptions Field 7 BOOST 6:0 LFSR[6:0]

Description BOOST - This bit controls the VCO power consumption in order to decrease the phase noise required by the Japanese regulation. The BOOST control bit is cleared by the RFMRST signal. 0 The VCO runs at its lower power consumption level (higher phase noise). 1 The VCO runs at its higher power consumption level (lower phase noise). Pseudo-Random Timer- The LFSR[6:0] bits select the current seed value of the LFSR when enabling pseudo-random timing intervals when any of the LFSR[6:0] bits are set. The value written to this register is loaded into the actual LFSR when the SEND bit is set. The time value is equal to a nominal one millisecond for each count of the resulting LFSR[6:0] bits. A value of $00 placed in the LFSR causes the LFSR to stay at the $00 state on each clocking of the LFSR. To cause the LFSR to cycle through its pseudo-random number sequence requires that any value other than $00 be written to the LFSR[6:0] bits. If RFBT[7:0] and RFFT[5:0] are both set to non-zero, and LFSR[6:0] is set to 0x00, the system will decrement both RFBT and RFFT simultaneously rather than serially, such that the effective Interframe Interval will be equal to the larger of RFBT or RFFT settings. NOTE FXTH870x6 128 Sensors Freescale Semiconductor, Inc. 13.15 RFM Control Register 6 - RFCR6 The RFCR6 register contains eight control bits to set the initial and interframe frame number timing variable as described in Figure 105. A RFMRST signal clears the RFFT[5:0] bits.

$0036 R W RFMRST:

Bit 7 6 VCO_GAIN[1:0]

1 0 5 0 4 0 3 0 RFFT[5:0}

2 0 1 0 Bit 0 0 Figure 105. RFCR6 Register - Frame Number Time - RFTS[1:0] = 1:0 Table 80. RFCR6 Field Descriptions Field 7:6 VCO_GAIN

[1:0]

5:0 RFFT[5:0]

Description VCO Gain Selection - These bits control the VCO gain. The VCO_GAIN[1] bit is set and the VCO_GAIN[0] bit is cleared by the RFMRST signal. Not normally need to be adjusted by the end user. Frame Number Timer - The RFFT[5:0] control bits select the interframe timing between multiple frames of transmission. The time value is equal to a nominal one millisecond for each count of the RFFT[5:0] bits multiplied by the frame number of the last transmitted frame. The RFFT[5:0] control bits are cleared by the RFMRST signal. 13.16 RFM Control Register 7 - RFCR7 The RFCR7 register contains four control bits and four status bits for the RFM as described in Figure 106.

$0037 R W RFMRST:

Bit 7 RFIF 0 6 RFEF 0

= Reserved 5 RFVF 0 4 0 RFIAK 0 3 2 1 RFIEN RFLVDEN RCTS 0 0 0 Bit 0 0 RFMRST 0 Figure 106. RFM Transmit Control Registers (RFCR7) Table 81. RFCR7 Field Descriptions Field 7 RFIF 6 RFEF 5 RFVF 4 RFIAK Description RF Interrupt Flag The read-only RFIF status bit indicates if the RF transmission has ended properly when using the data buffer mode and the SEND bit has been cleared. Writes to this bit will be ignored. The RFIF status bit is cleared by writing a logical one to the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit. 0 RF transmission in progress or not in the data buffer mode. 1 RF transmission completed in the data buffer mode. RF Transmission Error Flag The read-only RFEF status bit indicates if there was an error in the current or prior RF transmission as described in Section 13.6.4. Writes to this bit will be ignored. The RFEF status bit is cleared by writing a logical one to the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit. 0 No RF transmission error occurred. 1 RF transmission error occurred. RF LVD Trigger Flag When the RF LVD is enabled and the supply voltage falls below the threshold, the read-only RFVF flag will be set if the RFLVDEN bit is set. Writes to this bit will be ignored. The RFVF status bit is cleared by writing a logical one to the RFIAK bit or the RFMRST bit. RFMRST signal clears this bit 0 Voltage is and has been above RF LVD rising threshold or the RF LVD is disabled. 1 Voltage has dropped below the RF LVD falling threshold since last reset of this bit. Acknowledge RF Interrupt Flags Writing a one to the RFIAK bit clears the RFIF, RFEF and RFVF flag bits. Writing a zero to the RFIAK bit has no effect on the RFIF, RFEF and RFVF flag bits. The RFMRST signal has no effect on this bit. 0 No effect. 1 Clear the RFIF, RFEF, and RFVF bits. Sensors Freescale Semiconductor, Inc. FXTH870x6 129 Table 81. RFCR7 Field Descriptions (continued) Field 3 RFIEN 2 RFLVDEN 1 RCTS 0 RFMRST Description RF Interrupt Enable The RFIEN bit enables the RFIF, the RFEF and the RFVF bits to generate an interrupt to the MCU. The RFMRST signal clears this bit. 0 RF interrupts disabled. 1 RF interrupts enabled. RF LVD Enable When the RFLVDEN bit is set, the RF LVD circuit will be enabled, and the RF LVD events are routed to the RF LVD Trigger Flag. This bit is cleared by the RFMRST signal. 0 RF LVD disabled. 1 RF LVD enabled. RF Clear To Send Status When the RCTS bit is set the RF XCO, VCO and PLL have started and locked and the RFM is ready to send data. This bit is cleared by the RFMRST signal. 0 RFM not ready to send. 1 RFM ready to send. RFM Reset Writing a one to the RFMRST bit will completely reset the RFM and its registers. This bit is not affected by a reset of the MCU. This bit will always read as a zero. 0 No effect. 1 Reset RFM. PLL Control Registers A- PLLCR[1:0], RPAGE = 0 13.17 The PLLCR[1:0] registers contain 16 control bits for the RFM as described in Figure 107. These bits are only accessible when the RPAGE bit is cleared.

$0038 R W RFMRST:

$0039 R W RFMRST:

Bit 7 0 0 AFREQ[12:5]

6 0 0 5 0 AFREQ[4:0]

0 4 0 0 3 0 0 2 0 POL 0 1 0 0 Bit 0 0 0 CODE Figure 107. PLL Control Registers A (PLLCR[1:0], RPAGE = 0) Table 82. PLLCR[1:0] Field Descriptions Field PLLCR0 7:0 AFREQ 12:5 PLLCR1 7:3 AFREQ 4:0 2 POL FXTH870x6 130 Description PLL Divider Ratio A- The AFREQ[12:0] control bits select the PLL divider ratio for a data zero in the FSK mode of modulation as described by the following equation:

where:

fDATA0

=

fXTAL 12 4 CF+

AFREQ

---------------------

+

8192 fDATA0 = RF Carrier frequency for a data zero in MHz fXTAL = External crystal frequency in MHz, 26 MHz CF = State of the CF carrier select bit AFREQ = Decimal value of the AFREQ[12:0] binary weighted bits The AFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of AFREQ[12:0] = 3.17 kHz. Data Polarity - The POL control bit selects the polarity of the data encoding selected by the CODE[1:0] bits. The POL control bit is cleared by the RFMRST signal. 0 NRZ and MCU direct DATA bit data non-inverted and Manchester encoding polarity as in Figure 95 and Bi-Phase encoding polarity as in Figure 97. 1 NRZ and MCU direct DATA bit data inverted and Manchester encoding polarity as in Figure 94 and Bi-Phase encoding polarity as in Figure 96. Sensors Freescale Semiconductor, Inc. Table 82. PLLCR[1:0] Field Descriptions (continued) Field 1:0 CODE

[1:0]

Description Data Encoding and Source- The CODE[1:0] control bits select the type of data encoding and source of data for the RF output. The CODE[1:0] control bits are cleared by the RFMRST signal. 00 01 10 11 Manchester encoded data from the RFM data buffer. Bi-Phase encoded data from the RFM data buffer. NRZ direct data from the RFM data buffer (can be mixed NRZ and Manchester at 2X the data rate). MCU direct mode with RF output driven by the state of the DATA bit. PLL Control Registers B- PLLCR[3:2], RPAGE = 0 13.18 The PLLCR[3:2] registers contain 16 control bits for the RFM as described in Figure 108. These bits are only accessible when the RPAGE bit is cleared.

$003A Bit 7 R W RFMRST:

$003B R W RFMRST:

0 0 BFREQ[12:5]

6 0 0 5 0 BFREQ[4:0]

0 4 0 0 3 0 0 2 0 CF 0 1 0 Bit 0 0 MOD CKREF 0 0 Figure 108. PLL Control Registers B (PLLCR[3:2], RPAGE = 0) Table 83. PLLCR[3:2] Field Descriptions Field PLLCR2 7:0 BFREQ 12:5 PLLCR3 7:3 BFREQ 4:0 2 CF 1 MOD 0 CKREF PLL Divider Ratio B- The BFREQ[12:0] control bits select the PLL divider ratio for a data one in either the OOK or FSK modes of modulation as described by the following equation:

Description fDATA1

=

fXTAL 12 4 CF+

BFREQ

--------------------

+

8192 where:

fCARRIER = RF Carrier frequency in MHz fXTAL = External crystal frequency in MHz CF = State of the CF carrier select bit BFREQ = Decimal value of the BFREQ[12:0] binary weighted bits The BFREQ[12:0] control bits are cleared by the RFMRST signal. 1 LSB of BFREQ[12:0] = 3.17 kHz. Carrier Frequency - The CF control bit selects the optimal VCO setup and correct divider for the 500 kHz reference clock to the MCU on DX based on the external crystals required for the desired carrier frequency. The CF control bit is cleared by the RFMRST signal. 0 Configured for 315 MHz, 12.1154 PLL divider using a 26.000 MHz external crystal. 1 Configured for 434 MHz, 16.6923 PLL divider using a 26.000 MHz external crystal. RF Modulation Method - The MOD control bit selects the method of modulating the RF. The MOD control bit is cleared by the RFMRST signal. 0 Configured for OOK. 1 Configured for FSK. Generated Clock Reference - Generates the DX signal to the TPM1 module for determining the other clock frequencies:

0 DX signal not generated. 1 DX 500 kHz signal connected to the TPM1 module. Sensors Freescale Semiconductor, Inc. FXTH870x6 131 EPR Register - EPR (RPAGE = 1) 13.19 The EPR register contains eight control bits for the RFM as described in Figure 109. The function of the upper 4 bits depends on the state of the VCD_EN bit.

$0038 R W RFMRST:

$0038 R W RFMRST:

Bit 7 0 Bit 7 6 0 5 PLL_LPF_[2:0]

1 4 1 3 0 2 0

= Reserved Figure 109. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 0) 6 VCD[3:0]

5

= Reserved 4 3 0 2 0 Figure 110. RFM EPR Registers (EPR, RPAGE = 1, VCD_EN = 1) 1 Bit 0 PA_SLOPE VCD_EN 1 1 0 Bit 0 PA_SLOPE VCD_EN 1 0 Table 84. EPR Field Descriptions Field 7 Reserved 6-4 PLL_LPF_[2:0]

7-4 VCD[3:0]

3-2 Reserved 1 PA_SLOPE 0 VCD_EN Reserved bit Not for user access if the VCD_EN bit is clear. Description Low Pass Filter Selection - These read/write bits select the PLL low pass filter. A reset sets these bits to $03. These bits are only accessible if the VCD_EN bit is clear. VCO Calibration Count Difference - These read-only bits show the count difference from ideal when the VCO calibration machine is finished (see Section 13.21). These bits are only accessible when the VCD_EN bit is set. Writing to these bits when the VCD_EN bit is set has no effect. The reset state is undefined. Reserved bits Not for user access. PA Output Slope Selection This read/write bit controls the output slope of the RFM PA output. This bit is set by the RFMRST signal. VCD Enable bit This bit allows access to the VCD[3:0] bits. This bit is cleared by the RFMRST signal. 0 PLL_LPF_[2:0] bits accessed. 1 VCD[3:0] bits accessed. FXTH870x6 132 Sensors Freescale Semiconductor, Inc. 13.20 RF DATA Registers - RFD[31:0]

The RFD registers contain 256 read/write bits for the RFM to use when outputting data as described in Section 13.2. The 256-

bit buffer is divided into two pages of 128 bits as selected by the RPAGE bit in the RFCR2. These as described in Figure 111. These bits are unaffected by any reset. The data buffer is unloaded to the RF output starting with the least significant bit (RFD0) in the least significant byte (RFB0) up through the most significant bit (RFD255) in the most significant byte (RFB31). This is often referred to as little-endian data ordering. The output of this data by the RFM in all 256 bits locations is not dependent on the state of the RPAGE bit. Bit 7 6 5 4 3 2 1 Bit 0

$003C

$003D

$003E

$003F

$0040

$0041

$0042

$0043

$0044

$0045

$0046

$0047

$0048

$0049

$004A

$004B RFD[7:0] for RPAGE = 0, RFD[135:128] for RPAGE = 1 RFD[15:8] for RPAGE = 0, RFD[143:136] for RPAGE = 1 RFD[23:16] for RPAGE = 0, RFD[151:144] for RPAGE = 1 RFD[31:24] for RPAGE = 0, RFD[159:152] for RPAGE = 1 RFD[39:32] for RPAGE = 0, RFD[167:160] for RPAGE = 1 RFD[47:40] for RPAGE = 0, RFD[175:168] for RPAGE = 1 RFD[55:48] for RPAGE = 0, RFD[183:176] for RPAGE = 1 RFD[63:56] for RPAGE = 0, RFD[191:184] for RPAGE = 1 RFD[71:64] for RPAGE = 0, RFD[199:192] for RPAGE = 1 RFD[79:72] for RPAGE = 0, RFD[207:200] for RPAGE = 1 RFD[87:80] for RPAGE = 0, RFD[215:208] for RPAGE = 1 RFD[95:88] for RPAGE = 0, RFD[223:216] for RPAGE = 1 RFD[103:96] for RPAGE = 0, RFD[231:224] for RPAGE = 1 RFD[111:104] for RPAGE = 0, RFD[239:232] for RPAGE = 1 RFD[119:112] for RPAGE = 0, RFD[247:240] for RPAGE = 1 RFD[127:120] for RPAGE = 0, RFD[255:248] for RPAGE = 1 Figure 111. RF Data Registers (RFD[31:0]) Table 85. RFD[31:0] Field Descriptions Field RFD 15:0 Description RPAGE = 0 RF Data Registers Lower 128 bits - These are read/write bits that hold the lower 128 bits of possible data to be sent by the RFM. Access to the lower 128 bits occurs when the RPAGE bit is clear. These bits are unaffected by any reset. RFD

[127:0]

RFD 31:16 RPAGE = 1 RF Data Registers Upper 128 bits - These are read/write bits that hold the upper 128 bits of possible data to be sent by the RFM. Access to the lower 128 bits occurs when the RPAGE bit is clear. These bits are unaffected by any reset. RFD

[255:128]

Sensors Freescale Semiconductor, Inc. FXTH870x6 133 VCO Calibration Machine 13.21 The RFM incorporates a VCO calibration machine which works in conjunction with the VCO. The calibration machine selects the optimal VCO sub-band with respect to a predefined reference voltage applied to the VCO. Calibration supports maxband VCO sub-bands. maxband corresponds to the band where the VCO frequency is maximum. A successive approximation algorithm is used to calculate the optimum sub-band. Fc, the Center Frequency (AFREQ+BFREQ)/2 is used as the reference frequency for the VCO calibration in FSK mode

(MOD = 1). BFREQ is used as the reference frequency for the VCO calibration in OOK mode (MOD = 0). Calibration occurs every time the VCO is enabled. The calibration takes approximately 5s. The state machine of the calibration is shown in Figure 112.

- maxband is the number of sub-band of the VCO

- Bestband is the band which is going to be chosen

- Difference is an internal variable. VCOband=maxband/2 Bestband=maxband/2 Difference=maxband/4 Count the number of cycles of the VCO Difference=Difference/2 NO Difference=1?

Compare VCOcount and Targetedcount VCOcount>Targetedcount VCOcount<Targetedcount VCOcount=Targetedcount VCOband=VCOband-Difference VCOband=VCOband+Difference Bestband=VCOband VCOband=VCOband-Difference YES Bestband is first best band found or the closest band found Figure 112. VCO Calibration State Machine FXTH870x6 134 Sensors Freescale Semiconductor, Inc. Firmware 14 This section describes the software subroutines contained in the firmware section of the FLASH memory that the user can call for various tasks and to reduce the software development time for the main internal operations. Software Jump Table 14.1 All subroutines are accessed through a jump table located at the bottom of the firmware FLASH memory as described in Table 86. This allows upgrades in firmware without changing the software code of the user. All subroutines should be accessed with the JSR instruction. Function Documentation 14.2 The following subsections describe the details of the firmware routines. Further details can be found in the latest version of the FXTH870x6 Embedded Firmware User Guide. 14.2.1 General Rules 1. No output parameter can use the extreme codes (all zeros or all ones). 2. The all zeros output code will always indicate a fault and the status byte will indicate the source of the error. 3. While firmware is processing, CPU resources are unavailable for application. 4. Each measured parameter will return a limit code ($00, $FF or $1FF) if an error occurs in its acquisition, except for the external ADC voltage measurements on the PTA[1:0] pins. 5. External ADC voltage measurements on the PTA[1:0] pins will return a full range code that is ratiometric to the supply voltage. FXTH870x02 Single Z-axis Firmware Routines 14.2.1.1 The details on the use and execution of each firmware routine is documented in the CodeWarrior project file that is supplied by Freescale. Any future updates to these firmware routines will be contained in that file. A summary of the firmware routines available is given in Table 86. The firmware table is comprised of 3-byte entries where the first byte is the operational code for the JMP instruction, and the following two bytes are the absolute address pointing to the location of the firmware function. Table 86. FXTH870x02 Single Z-axis Firmware Summary and Jump Table Address Routine Description E000 E003 E006 E009 E00C E00F E012 E015 E018 E01B E01E E021 E024 E027 E02A E02D E030 E033 E036 E039 TPMS_RESET TPMS_READ_VOLTAGE TPMS_COMP_VOLTAGE TPMS_READ_TEMPERATURE TPMS_COMP_TEMPERATURE TPMS_READ_PRESSURE TPMS_COMP_PRESSURE TPMS_READ_ACCELERATION TPMS_COMP_ACCELERATION TPMS_READ_V0 TPMS_READ_V1 TPMS_LFOCAL TPMS_MFOCAL TPMS_WAVG TPMS_RF_RESET TPMS_RF_READ_DATA TPMS_RF_READ_DATA_REVERSE TPMS_RF_WRITE_DATA TPMS_RF_WRITE_DATA_REVERSE TPMS_RF_CONFIG_DATA Master reset of complete device 10-bit uncompensated bandgap voltage reading 8-bit compensation of 10-bit voltage reading 10-bit uncompensated temperature reading 8-bit compensation of 10-bit temperature reading 10-bit uncompensated pressure reading 9-bit compensation of 10-bit pressure reading 10-bit uncompensated acceleration reading 9-bit compensation of 10-bit acceleration reading 10-bit uncompensated voltage reading on PTA0 pin 10-bit uncompensated voltage reading on PTA1 pin LFO clock calibration MFO clock calibration Weighted average (2, 4, 8, 16 or 32) Master reset of RFM Read RFM data buffer Read RFM data buffer in reverse bit order Write RFM data buffer Write RFM data buffer in reverse bit order Configure RFM Sensors Freescale Semiconductor, Inc. FXTH870x6 135 Table 86. FXTH870x02 Single Z-axis Firmware Summary and Jump Table (continued) Address Routine Description E03C E03F E042 E045 E048 E04B E04E E051 E054 E057 E05A E05D E060 E063 E066 E069 E06C E06F E072 E075 E078 E07B E07E E081 E084 E087 E08A E08D Reserved TPMS_RF_SET_TX TPMS_RF_DYNAMIC_POWER TPMS_MSG_INIT TPMS_MSG_READ TPMS_MSG_WRITE TPMS_CHECKSUM_XOR TPMS_CRC8 TPMS_CRC16 TPMS_SQUARE_ROOT TPMS_READ_ID TPMS_LF_ENABLE TPMS_LF_READ_DATA TPMS_WIRE_AND_ADC_CHECK TPMS_FLASH_WRITE TPMS_FLASH_CHECK TPMS_FLASH_ERASE TPMS_READ_DYNAMIC_ACCEL TPMS_RF_ENABLE TPMS_FLASH_PROTECTION Reserved TPMS_MULT_SIGN_INT16 TPMS_VREG_CHECK TPMS_PRECHARGE_VREG Reserved TPMS_READ_ACCEL_CONT_START TPMS_READ_ACCEL_CONT TPMS_READ_ACCEL_CONT_STOP Reserved Initiate RF transmission Adjusts PA for uniform power output Initialization of the emulated serial communication Reading data from emulated serial interface Writing data on emulated serial interface Calculates a checksum for given buffer in XOR Calculates CRC8 on portion of memory Calculates CRC16 on portion of memory Calculates square root Reads device ID stored in FLASH Enable/Disable LF for Carrier or Data Reading LF data Performs checks of internal bond wires Write to FLASH Performs checksum on Freescale firmware FLASH Erases one page (512 bytes) of FLASH at a time Offsets Z-axis acceleration with one of 15 steps Enable RFM Lock out FLASH Reserved Multiple two signed 16-bit numbers together Verify that external capacitor connected to VREG pin Precharge external capacitor on VREG pin Reserved Enable the TPMS_READ_ACCEL_CONT function. Take continuous acceleration readings and store to assigned location. Disable the TPMS_READ_ACCEL_CONT function. FXTH870x11 Dual XZ-axis Firmware Routines 14.2.1.2 The details on the use and execution of each firmware routine is documented in the CodeWarrior project file that is supplied by Freescale. Any future updates to these firmware routines will be contained in that file. A summary of the firmware routines available is given in Table 87. The firmware table is comprised of 3-byte entries where the first byte is the operational code for the JMP instruction, and the following two bytes are the absolute address pointing to the location of the firmware function. Table 87. FXTH870x11 Dual XZ-axis Firmware Summary and Jump Table Address Routine Description E000 E003 E006 E009 E00C E00F E012 E015 TPMS_RESET TPMS_READ_VOLTAGE TPMS_COMP_VOLTAGE TPMS_READ_TEMPERATURE TPMS_COMP_TEMPERATURE TPMS_READ_PRESSURE TPMS_COMP_PRESSURE TPMS_READ_ACCELERATION_X Master reset of complete device 10-bit uncompensated bandgap voltage reading 8-bit compensation of 10-bit voltage reading 10-bit uncompensated temperature reading 8-bit compensation of 10-bit temperature reading 10-bit uncompensated pressure reading 9-bit compensation of 10-bit pressure reading 10-bit uncompensated X-axis accel reading FXTH870x6 136 Sensors Freescale Semiconductor, Inc. Table 87. FXTH870x11 Dual XZ-axis Firmware Summary and Jump Table (continued) Address Routine Description E018 E01B E01E E021 E024 E027 E02A E02D E030 E033 E036 E039 E03C E03F E042 E045 E048 E04B E04E E051 E054 E057 E05A E05D E060 E063 E066 E069 E06C E06F E072 E075 E078 E07B E07E E081 E084 E087 E08A E08D E090 TPMS_READ_DYNAMIC_ACCEL_X TPMS_COMP_ACCELERATION_X TPMS_READ_ACCELERATION_Z TPMS_READ_DYNAMIC_ACCEL_Z TPMS_COMP_ACCELERATION_Z TPMS_READ_ACCELERATION_XZ TPMS_READ_DYNAMIC_ACCEL_XZ TPMS_COMP_ACCELERATION_XZ TPMS_READ_V0 TPMS_READ_V1 TPMS_LFOCAL TPMS_MFOCAL TPMS_RF_ENABLE TPMS_RF_RESET TPMS_RF_READ_DATA TPMS_RF_READ_DATA_REVERSE TPMS_RF_WRITE_DATA TPMS_RF_WRITE_DATA_REVERSE TPMS_RF_CONFIG_DATA Reserved TPMS_RF_SET_TX TPMS_RF_DYNAMIC_POWER TPMS_MSG_INIT TPMS_MSG_READ TPMS_MSG_WRITE TPMS_CHECKSUM_XOR TPMS_CRC8 TPMS_CRC16 TPMS_SQUARE_ROOT TPMS_READ_ID TPMS_LF_ENABLE TPMS_LF_READ_DATA TPMS_WIRE_AND_ADC_CHECK TPMS_FLASH_WRITE TPMS_FLASH_CHECK TPMS_FLASH_ERASE TPMS_FLASH_PROTECTION Reserved TPMS_MULT_SIGN_INT16 TPMS_WAVG Reserved 10-bit uncompensated X-axis accel reading with dynamic offset adjustment. 9-bit compensation of 10-bit X-axis accel reading 10-bit uncompensated Z-axis accel reading 10-bit uncompensated Z-axis accel reading with dynamic offset adjustment. 9-bit compensation of 10-bit Z-axis accel reading 10-bit uncompensated X-axis and Z-axis accel readings 10-bit uncompensated X-axis and Z-axis accel readings with dynamic offset adjustment. 9-bit compensation of 10-bit X-axis and Z-axis accel readings 10-bit uncompensated voltage reading on PTA0 pin 10-bit uncompensated voltage reading on PTA1 pin LFO clock calibration MFO clock calibration Enable and set up RFM Master reset of RFM Read RFM data buffer Read RFM data buffer in reverse bit order Write RFM data buffer Write RFM data buffer in reverse bit order Configure RFM Reserved Initiate RF transmission Adjusts PA for uniform power output Initialization of the emulated serial communication Reading data from emulated serial interface Writing data on emulated serial interface Calculates a checksum for given buffer in XOR Calculates CRC8 on portion of memory Calculates CRC16 on portion of memory Calculates square root Reads device ID stored in FLASH Enable/Disable LF for Carrier or Data Reading LF data Performs checks of internal bond wires Write to FLASH Performs checksum on Freescale firmware FLASH Erases one page (512 bytes) of FLASH at a time Lock out FLASH Reserved Multiple two signed 16-bit numbers together Weighted average Reserved Sensors Freescale Semiconductor, Inc. FXTH870x6 137 Device Identification 14.2.2 The bytes assigned to identify the device and its options are described below. This data can be read by use of the TPMS_READ_ID routine. Table 88. Device ID Coding Summary ID Address 00 01 02 03 04 05 Register Name CODE0 CODE1 CODE2 CODE3 CODE4 CODE5 Inital Address

$E0A0

$FF10

$FF11

$FF12

$FF13

$FF14 Updated Address

$E0A0

$FDF2

$FDF3

$FDF4

$FDF5

$FDF6 Bit 7 6 5 4 3 2 1 Bit 0 Reserved - Firmware Revision/Software Information ES2 ID7 ID15 ID23 ID31 ES1 ID6 ID14 ID22 ID30 ES0 ID5 ID13 ID21 ID29 PRESS ID4 ID12 ID20 ID28 ACC1 ID3 ID11 ID19 ID27 ACC0 ID2 ID10 ID18 ID26 SPCLA SPCLP ID1 ID9 ID17 ID25 ID0 ID8 ID16 ID24 ID12:0 Device ID within each lot, maximum 8,192 per lot ID13:26 Assembly lot ID, 100 through 16383 ID27 Always 0 for FXTH87 family ID28:31 Always 0x08 to identify Freescale as supplier Table 89. Device ID Coding Descriptions Field CODE0 7:0 Reserved CODE1 7:5 ES Description Reserved for Freescale firmware description. Note: FXTH870922 = Rel1x, all other part numbers = Rel2x Revision number for the multiple-chip-module silicon. 000 - MCU version 0 111 - MCU version 7 CODE1 Calibrated range for pressure. The range is a combination of this bit and the PRESS-L bit, below. 4 PRESS-H bit 0 = 0, bit 4 = 0 indicates a 100-450 kPa range bit 0 = 0, bit 4 = 1 indicates a 100-900 kPa range CODE1 3:2 ACC CODE1 1 Type of accelerometer. 00 - None 01 - One accelerometer with X-axis orientation 10 - One accelerometer with Z-axis orientation 11 - Two accelerometers with X- and Z-axis orientations Special calibration for accelerometer. 0 = standard -240 to +270 g Z-axis 1 = extended -270 to +400 g Z-axis CODE1 Calibrated range for pressure. The range is a combination of this bit and the PRESS-H bit, above. 0 PRESS-L CODE2:4 7:0 CODE5 3:0 ID27:0 CODE5 7:4 ID31:28 FXTH870x6 138 bit 0 = 0, bit 4 = 0 indicates a 100-450 kPa range bit 0 = 0, bit 4 = 1 indicates a 100-900 kPa range 28-bit serial number for each device. All numbers to be unique with numbering sequence being a sequential counter for each product type. 4-bit number assigned to vendor type. If these bits are unspecified as part of the complete FLASH programming by the customer, then these 4 bits are programmed to binary 1 0 0 0. Sensors Freescale Semiconductor, Inc. Definition of Signal Ranges 14.2.3 Each measured parameter (pressure, voltage, temperature, acceleration) results from an ADC10 conversion of an analog signal. This ADC10 result may then be passed by the firmware to the application software as either the raw ADC10 result or further compensated and scaled for an output between one and the maximum digital value minus one. The minimum digital value of zero and the maximum digital value are reserved as error codes. The signal ranges and their significant data points are shown in Figure 113. In this definition the signal source would normally output a signal between SINLO and SINHI. Due to process, temperature and voltage variations this signal may increase its range to SINMIN to SINMAX. In all cases the signal will be between the supply rails, so that the ADC10 will convert it to a range of digital numbers between 0 and 1023. These digital numbers will have corresponding DINMIN, DINLO, DINHI, DINMAX values. The ADC10 digital value is taken by the firmware and compensated and scaled to give the required output code range. VDD SINMAX SINHI UPPER ERROR CASE OVERFLOW CASE 1023 DINMAX DINHI NORMAL CASE FORCE OUTPUT TO 511 511 510 SIGNAL SOURCE VDD/2 ADC10 512 FIRMWARE ROUTINE 256 SENSOR ANALOG VOLTAGE SINLO SINMIN VDD ADC10 RAW DIGITAL

(10-BIT CONVERSION) CALCULATED DIGITAL

(9-BIT EXAMPLE) DINLO DINMIN 0 UNDERFLOW CASE 1 0 FORCE OUTPUT TO ZERO LOWER ERROR CASE Figure 113. Measurement Signal Range Definitions Digital input values below DINMIN and above DINMAX are immediately flagged as being out of range and generate error bits and the output is forced to the 0 value. Digital values below DINLO (but above DINMIN) or above DINHI (but not DINMAX) will most likely cause an output that would be less than 1 or greater than 510, respectively. These cases are considered underflow or overflow, respectively. Underflow results will be forced to a value of 1. Overflow results will be forced to a value of 510. Sensors Freescale Semiconductor, Inc. FXTH870x6 139 Digital values between DINLO and DINHI will normally produce an output between 1 to 510 (for a 9-bit result). In some isolated cases due to compensation calculations and rounding the result may be less than 1 or greater than 510, in which case the underflow and overflow rule mentioned above is used. Memory Resource Usage 14.3 The firmware uses the top 8192 bytes of the FLASH memory map. The firmware uses no specific bytes of the RAM but will cause additional stacking of temporary values. The firmware uses two bytes ($008E and $008F) of the Parameter Registers for global flags for all routines. Software Stack The RESET firmware function sets the SP register to the last address in the RAM. The user can change the default stack location to meet its own application needs. FXTH870x6 140 Sensors Freescale Semiconductor, Inc. 15 Development Support Features Introduction 15.1 This chapter describes the single-wire BACKGROUND DEBUG mode (BDM), which uses the on-chip BACKGROUND DEBUG controller (BDC) module. 15.1.1 Features of the BDC module include:

Single pin for mode selection and background communications BDC registers are not located in the memory map SYNC command to determine target communications rate Non-intrusive commands for memory access ACTIVE BACKGROUND mode commands for CPU register access GO and TRACE1 commands BACKGROUND command can wake CPU from STOP or WAIT modes One hardware address breakpoint built into BDC Oscillator runs in STOP mode, if BDC enabled COP watchdog disabled while in ACTIVE BACKGROUND mode Background Debug Controller (BDC) 15.2 All MCUs in the HCS08 Family contain a single-wire BACKGROUND DEBUG interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups:

ACTIVE BACKGROUND mode commands require that the target MCU is in ACTIVE BACKGROUND mode (the user program is not running). ACTIVE BACKGROUND mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from ACTIVE BACKGROUND mode. Non-intrusive commands can be executed at any time even while the users program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the BACKGROUND DEBUG controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire BACKGROUND DEBUG system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD/PTA4 pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. BKGD 1 NO CONNECT 3 NO CONNECT 5 2 4 6 GND RESET VDD Figure 114. BDM Tool Connector Sensors Freescale Semiconductor, Inc. FXTH870x6 141 BKGD/PTA4 Pin Description 15.2.1 BKGD/PTA4 is the single-wire BACKGROUND DEBUG interface pin. The primary function of this pin is for bidirectional serial communication of ACTIVE BACKGROUND mode commands and data. During reset, this pin is used to select between starting in ACTIVE BACKGROUND mode or starting the users application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for BACKGROUND DEBUG serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section 15.2.2. If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD/PTA4 is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 15.2.2, for more detail. When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD/PTA4 chooses normal operating mode. When a debug pod is connected to BKGD/PTA4 it is possible to force the MCU into ACTIVE BACKGROUND mode after reset. The specific conditions for forcing ACTIVE BACKGROUND depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the BACKGROUND DEBUG interface. 15.2.2 The BDC serial interface requires the external controller to generate a falling edge on the BKGD/PTA4 pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD/PTA4 is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD/PTA4 pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. Figure 115 shows an external host transmitting a logic 1 or 0 to the BKGD/PTA4 pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD/PTA4 pin. Typically, the host actively drives the pseudo-open-drain BKGD/PTA4 pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD/PTA4 pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. Communication Details FXTH870x6 142 Sensors Freescale Semiconductor, Inc. BDC CLOCK

(TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME 10 CYCLES TARGET SENSES BIT LEVEL EARLIEST START OF NEXT BIT Figure 115. BDC Host-to-Target Serial Bit Timing Figure 116 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the perceived start of the bit time in the target MCU. The host holds the BKGD/PTA4 pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK

(TARGET MCU) HOST DRIVE TO BKGD/PTA4 PIN TARGET MCU SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD/PTA4 PIN HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE R-C RISE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD/PTA4 PIN Figure 116. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 117 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD/PTA4 to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD/PTA4 pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. Sensors Freescale Semiconductor, Inc. FXTH870x6 143 BDC CLOCK

(TARGET MCU) HOST DRIVE TO BKGD/PTA4 PIN TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD/PTA4 PIN HIGH-IMPEDANCE SPEEDUP PULSE 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD/PTA4 PIN Figure 117. BDM Target-to-Host Serial Bit Timing (Logic 0) BDC Commands 15.2.3 BDC commands are sent serially from a host computer to the BKGD/PTA4 pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. ACTIVE BACKGROUND mode commands require that the target MCU is currently in the ACTIVE BACKGROUND mode while non-intrusive commands may be issued at any time whether the target MCU is in ACTIVE BACKGROUND mode or running a user application program. Table 90 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 90 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first)

=

/

=

d AAAA =

=

RD WD

=

RD16 =

WD16 =

=

SS CC

=

RBKP =

WBKP =

separates parts of the command delay 16 target BDC clock cycles a 16-bit address in the host-to-target direction 8 bits of read data in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of read data in the target-to-host direction 16 bits of write data in the host-to-target direction the contents of BDCSCR in the target-to-host direction (STATUS) 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) FXTH870x6 144 Sensors Freescale Semiconductor, Inc. Table 90. BDC Command Summary Command Mnemonic SYNC ACK_ENABLE ACK_DISABLE BACKGROUND READ_STATUS WRITE_CONTROL READ_BYTE READ_BYTE_WS READ_LAST WRITE_BYTE WRITE_BYTE_WS READ_BKPT WRITE_BKPT GO TRACE1 TAGGO READ_A READ_CCR READ_PC READ_HX READ_SP READ_NEXT READ_NEXT_WS WRITE_A WRITE_CCR WRITE_PC WRITE_HX WRITE_SP WRITE_NEXT WRITE_NEXT_WS Active BDM/

Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Coding Structure n/a(1) D5/d D6/d 90/d E4/SS C4/CC E0/AAAA/d/RD E1/AAAA/d/SS/RD E8/SS/RD C0/AAAA/WD/d C1/AAAA/WD/d/SS E2/RBKP C2/WBKP 08/d 10/d 18/d 68/d/RD 69/d/RD 6B/d/RD16 6C/d/RD16 6F/d/RD16 70/d/RD 71/d/SS/RD 48/WD/d 49/WD/d 4B/WD16/d 4C/WD16/d 4F/WD16/d 50/WD/d 51/WD/d/SS Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter ACTIVE BACKGROUND mode if enabled (ignore if ENBDM bit equals 0) Read BDC status from BDCSCR Write BDC controls in BDCSCR Read a byte from target memory Read a byte and report status Re-read byte from address just read and report status Write a byte to target memory Write a byte and report status Read BDCBKPT breakpoint register Write BDCBKPT breakpoint register Go to execute the user application program starting at the address currently in the PC Trace 1 user instruction at the address in the PC, then return to ACTIVE BACKGROUND mode Same as GO but enable external tagging (HCS08 devices have no external tagging pin) Read accumulator (A) Read condition code register (CCR) Read program counter (PC) Read H and X register pair (H:X) Read stack pointer (SP) Increment H:X by one then read memory byte located at H:X Increment H:X by one then read memory byte located at H:X. Report status and data. Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status. 1. The SYNC command is a special operation that does not have a command code. The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host:

Drives the BKGD/PTA4 pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) Sensors Freescale Semiconductor, Inc. FXTH870x6 145 Drives BKGD/PTA4 high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) Removes all drive to the BKGD/PTA4 pin so it reverts to high impedance Delays 16 cycles to allow the host to STOP driving the high speedup pulse Drives BKGD/PTA4 low for 128 BDC clock cycles Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD/PTA4 Removes all drive to the BKGD/PTA4 pin so it reverts to high impedance Monitors the BKGD/PTA4 pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications):

Waits for BKGD/PTA4 to return to a logic high The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 15.2.4 The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter ACTIVE BACKGROUND mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter ACTIVE BACKGROUND mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. BDC Hardware Breakpoint Register Definition BDC Registers and Control Bits 15.3 This section contains the descriptions of the BDC registers and control bits. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.3.1 The BDC has two registers:

The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the BACKGROUND DEBUG controller. The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU

(so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in ACTIVE BACKGROUND mode. (This prevents the ambiguous condition of the control bit forbidding ACTIVE BACKGROUND mode while the MCU is already in ACTIVE BACKGROUND mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. FXTH870x6 146 Sensors Freescale Semiconductor, Inc. BDC Status and Control Register (BDCSCR) 15.3.2 This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. R W Normal Reset Reset in Active BDM:

7 ENBDM 6 BDMACT 5 BKPTEN 0 1 0 1

= Reserved 0 0 4 FTS 0 0 3 CLKSW 0 1 2 WS 0 0 1 WSF 0 0 0 DVF 0 0 Figure 118. BDC Status and Control Register (BDCSCR) Table 91. BDCSCR Register Field Descriptions Field 7 ENBDM 6 BDMACT 5 BKPTEN 4 FTS 3 CLKSW 2 WS 1 WSF 0 DVF Description Enable BDM (Permit ACTIVE BACKGROUND Mode) Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow ACTIVE BACKGROUND mode commands BACKGROUND Mode Active Status This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands BDC Breakpoint Enable If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled Force/Tag Select When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters ACTIVE BACKGROUND mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter ACTIVE BACKGROUND mode if CPU attempts to execute that instruction 1 Breakpoint match forces ACTIVE BACKGROUND mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock WAIT or STOP Status When the target CPU is in WAIT or STOP mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of WAIT or STOP and into ACTIVE BACKGROUND mode where all BDC commands work. Whenever the host forces the target MCU into ACTIVE BACKGROUND mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in ACTIVE BACKGROUND mode (was not in WAIT or STOP mode when BACKGROUND became active) 1 Target CPU is in WAIT or STOP mode, or a BACKGROUND command was used to change from WAIT or STOP to ACTIVE BACKGROUND mode WAIT or STOP Failure Status This status bit is set if a memory access command failed due to the target CPU executing a WAIT or STOP instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of WAIT or STOP mode into ACTIVE BACKGROUND mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the WAIT or STOP instruction.) 0 Memory access did not conflict with a WAIT or STOP instruction 1 Memory access command failed because the CPU entered WAIT or STOP mode Data Valid Failure Status This status bit is not used in the MC9S08RA16 because it does not have any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access Sensors Freescale Semiconductor, Inc. FXTH870x6 147 BDC Breakpoint Match Register (BDCBKPT) 15.3.3 This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in ACTIVE BACKGROUND mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 15.2.4. 15.3.4 This register contains a single write-only control bit. A serial BACKGROUND mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. System Background Debug Force Reset Register (SBDFR) R W Reset 7 0 0 6 0 0

= Reserved 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 BDFR(1) 0 1. BDFR is writable only through serial BACKGROUND mode debug commands, not from user programs. Figure 119. System Background Debug Force Reset Register (SBDFR) Table 92. SBDFR Register Field Description Field 0 BDFR Background Debug Force Reset A serial ACTIVE BACKGROUND mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Description FXTH870x6 148 Sensors Freescale Semiconductor, Inc. Battery Charge Consumption Modeling 16 The supply current consumed by the FXTH870x6 can be estimated using the following basic model. 16.1 The overall charge consumed by the standby features is:

Standby Current QSTDBY

=

tTOT ISTDBY ILF

--------------------------------------------

+

1000 Eqn. 12 where:

QSTDBY = Standby charge over lifetime, tTOT, in mA-hr tTOT = Total lifetime in hours ISTDBY = General standby current in A ILF = LFR detector (if used) current in A 16.2 The overall charge consumed by the measurements is:

Measurement Events QMEAS

=

1

------------

1000 where:

nPRESS QPRESS nTEMP QTEMP nVOLT QVOLT

+

+

QMEAS = Total measurement charge over lifetime in mA-sec QPRESS = Measurement charge per pressure measurement in A-sec QTEMP = Measurement charge per temperature measurement in A-sec QVOLT = Measurement charge per voltage measurement in A-sec nPRESS = Total number of pressure measurements over lifetime nTEMP = Total number of temperature measurements over lifetime nVOLT = Total number of voltage measurements over lifetime 16.3 The overall charge consumed by the transmissions is:

Transmission Events QXMT

=

QFRM

----------------- F 1000 nXMT where:

QXMT = Transmit charge over lifetime, tTOT, in mA-hr QFRM = Transmit charge per frame of data in A-sec nXMT = Number of transmissions over lifetime F = Frames transmitted during each datagram 16.4 The overall charge consumed is:

Total Consumption where:

QTOT

=

QSTDBY QMEAS QXMT

------------------------------------------------------------------------------------

+

+

1 Y SD 100 QTOT = Total charge over lifetime, tTOT, in mA-hr QSTDBY = Standby charge over lifetime in mA-hr QMEAS = Measurement charge over lifetime in mA-hr QXMT = Transmit charge over lifetime in mA-hr Y = Lifetime in years SD = Battery self-discharge rate in%/year Additional margin in battery capacity can be added to the calculated value of QTOT. Sensors Freescale Semiconductor, Inc. Eqn. 13 Eqn. 14 Eqn. 15 FXTH870x6 149 17 Electrical Specifications Maximum Ratings 17.1 Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD.

#

100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Rating Supply Voltage (VDD, AVDD) Input Voltage X1 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 BKGD/PTA4, RESET LFA, LFB Input Current X1 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 BKGD/PTA4, RESET LFA, LFB Substrate Current Injection Current from any pin to VSS - 0.3 VDC XI, PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4, RESET LFA, LFB Latchup Current Current to/from any pin to supply rails + 0.3 VDC Electrostatic Discharge Human Body Model (HBM), all pins other than RF Human Body Model (HBM), RF pin Charged Device Model (CDM) Maximum Storage Temperature Range Symbol VDD Value

-0.3 to +3.8 Unit V VIN VIN VIN VIN IIN IIN IIN IIN ISUB ISUB ILATCH VESD VESD VESD Tstg

-0.3 to VDD+0.3

-0.3 to VDD+0.3

-0.3 to VDD+0.3

-0.3 to VDD+0.3 10 10 10 10 600 2 100 2000 3000 500

-50 to +150 Note: Refer to page 169 for description of notes. 17.2 The limits normally expected in the application which define range of operation. Operating Range

#

200 201 202 203 204 205 206 207 208 209 Characteristic Symbol Operating Supply Voltage (VDD = AVDD) Measurements Pressure, Temperature, Acceleration Voltage LFR Operation (-20 < TA< +85 C) RF Transmissions MCU operation (CPU, ADC10, RAM, TPM1) FLASH write (-40 to +125 C) FLASH write (-20 to +85 C) FLASH read Parameter registers data retention Operating Temperature Range Continuous Temperature Range STOP1 mode (note 5) VDD VDD VDD VDD VDD VDD VDD VDD TA TA Note: Refer to page 169 for description of notes. Min VL 2.3 1.8 2.3 1.8 2.3 2.1 1.8 1.2 TL

-40

-40 Typ 3.0 3.0 3.0 3.0 3.0 3.0 3.0 Max VH 3.6 3.6 3.6 3.6 3.6 3.6 3.6 TH

+125

+150

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(3)

(3) V V V V mA mA mA mA A mA mA V V V C Units V V V V V V V V C C FXTH870x6 150 Sensors Freescale Semiconductor, Inc. Electrical Characteristics 17.3 1.8 VDD 3.6, TL TA TH, unless otherwise specified.

#

300 301 302 303 304 305 306 307 308 309 310 311 312 Characteristic Symbol Min Typ Max Units Output High Voltage (ILoad = 5 mA) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 Output Low Voltage (ILoad = -5 mA) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 Input High Voltage (2.3 VDD VH) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 Input High Voltage (VL VDD 2.3) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 Input Low Voltage (2.3 VDD VH) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 Input Low Voltage (VL VDD 2.3) PTA0, PTA1, PTA2, PTA3, PTB0, PTB1, BKGD/PTA4 Input High Current (at min VIH) BKGD/PTA4 PTA0, PTA1, PTA2, PTA3 (pulldown off) PTA0, PTA1, PTA2, PTA3 (pulldown active) Input Low Current (at max VIL) BKGD/PTA4 PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 (pullup off) PTA0, PTA1, PTA2, PTA3 (pullup active) Pin Capacitance (3 V) BKGD/PTA4, PTA0, PTA1, PTA2, PTA3, PTB0, PTB1 VOH VOL VIH VIH VIL VIL IIH IIH IIH IIL IIL IIL C VDD-0.35 0.7 x VDD 0.85 x VDD VSS VSS

-1

-1 0

-120

-1

-120 0 0.35 0.35 x VDD 0.28 x VDD

+1

+1

+120 0

+1 0 15 V V V V V V A A A A A A pF

(2)

(2)

(2)

(3)

(2)

(3)

(1)

(2)

(2)

(1)

(2)

(2)

(3) Note: Refer to page 169 for description of notes. Sensors Freescale Semiconductor, Inc. FXTH870x6 151 Power Consumption (MCU) 17.4 1.8 VDD 3.6, TA 0 to 125 C unless otherwise specified.

#

400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 Characteristic Symbol Min Typ Max Units Standby Supply Current STOP1 mode, LFR, LVD and TR all off TA = -40 C, VDD = 3.0 V TA = 0 C, VDD = 3.0 V TA = 25 C, VDD = 1.8 V TA = 25 C, VDD = 3.0 V TA = 25 C, VDD = 3.6 V TA = 70 C, VDD = 3.0 V TA = 125 C, 3.0 V VDD 3.6 V Standby Supply Current STOP4 mode, LFR and TR off, LVD or RFLVD on TA = -40 C, VDD = 3.0 V TA = 0 C, VDD = 3.0 V TA = 25 C, VDD = 1.8 V TA = 25 C, VDD 3.0 V TA = 70 C, VDD = 3.0 V TA = 125 C, 3.0 V VDD 3.6 V MCU Operate Current (1.8 VDD 3.0 V, -40 C TA 125 C) Instruction Speed = 0.333 MIP/fBUS 0.5 MHz fBUS, BUSCLKS[1:0] = 11 1 MHz fBUS, BUSCLKS[1:0] = 10 2 MHz fBUS, BUSCLKS[1:0] = 01 4 MHz fBUS, BUSCLKS[1:0] = 00 Standby Current Adder for Temperature Restart VDD = 1.8 V, TA = 125 C VDD = 3.0 V, TA = 125 C MCU Wakeup Consumption (+25 C, 3 V) From STOP1 to first instruction, fBUS = 4 MHz External Battery Model Series impedance at end-of-life Open circuit voltage at end-of-life ISTDBY1 ISTDBY1 ISTDBY1 ISTDBY1 ISTDBY1 ISTDBY1 ISTDBY1 ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 ISTDBY4 IDD IDD IDD IDD IDD IDD QWAKE ZEOL VEOL 0 2.7 0.5 73 0.72 0.94 1.46 2.50 10 10 0.05 0.9 0.9 0.8 0.7 0.9 1.5 13 100 100 95 95 100 140 1.0 1.1 1.7 2.9 15 15 0.1 60 A A A A A A A A A A A A A mA mA mA mA A A

(3)

(3)

(3)

(2)

(3)

(3)

(3)

(3)

(3)

(3)

(2)

(3)

(3)

(3)

(3)

(3)

(1)

(3)

(3) A-sec

(3) V

(4)

(4) Note: Refer to page 169 for description of notes. FXTH870x6 152 Sensors Freescale Semiconductor, Inc. Control Timing 17.5 1.8 VDD 3.6, TL TA TH, unless otherwise specified.

#

500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 Characteristic Symbol Min Internal Clock Frequency Initial startup frequency Final frequency Limited temperature range, -20 C to +85 C Full temperature range, -40 C to +125 C Complete stabilization time (see Figure 120) MCU Bus Frequency Medium frequency clock (MFO) Limited temperature range, -20 C to +85 C Full temperature range, -40 C to +125 C Low frequency clock (LFO) Limited temperature range, 0 C to +70 C Full temperature range, -40 C to +125 C LFR clock (derived from LFRO) Power-On Reset Response Supply voltage rise time Recovery time below VDD = 0.5 V MCU Wakeup Time (see Figure 120) From STOP1 to first instruction, fBUS = 4 MHz From STOP4 to first instruction, fBUS = 4 MHz FLASH Data Retention Time fOSCINIT fOSC fOSC tOSCSU fBUS fMFO fMFO fLFO fLFO fLFRO tVDDR tVDDOFF tMCUWAKE tMCUWAKE tDR 6 7.2 6.8 115 106 833 770 122 0 10 Note: Refer to page 169 for description of notes. Typ 8 300 0.5 fOSC 125 129 50 100 Max 10 8.1 8.1 1000 128 128 1250 1429 135 1 70 70 155 Units MHz MHz MHz sec MHz kHz kHz Hz Hz kHz sec sec sec sec year

(3)

(2)

(3)

(3)

(2)

(2)

(3)

(2)

(3)

(1)

(3)

(3)

(3)

(3)

(4) HFO Clock STOP1 Wakeup execute instructions HFO = fOSCINIT HFO = fOSC tOSCSU tMCUWAKE Figure 120. MCU Startup Delays TEST POINT 50 pF VDD 6.32 k 10.91 k Figure 121. Control Timing Test Load for Digital Pins Sensors Freescale Semiconductor, Inc. FXTH870x6 153 Voltage Measurement Characteristics 17.6 1.8 VDD 3.6, TL TA TH, unless otherwise specified.

#

600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 Characteristic Symbol Lower LVD detect threshold (note 15) VDD falling VDD rising Voltage drop detection time (note 16) Higher LVD detect threshold (note 15) VDD falling VDD rising Voltage drop detection time (note 16) Lower LVW detect threshold (LVWV = 0, note 15) VDD falling VDD rising Voltage drop detection time (note 16) Higher LVW detect threshold (LVWV = 1, note 15) VDD falling VDD rising Voltage drop detection time (note 16) RF LVD detect threshold, VDD falling (note 15) Voltage drop detection time (note 16) Power-On Reset Voltage (note 15) Rising Voltage to Recover Falling Voltage to Reset Internal Voltage (VDD, monotonic response). VCODE = 0

= 58

= 88

= 108

= 128

= 158

= 208

= 238

= 255 Voltage sensitivity External Voltage (PTA[1:0], monotonic response, conversion is ratiometric to VDD) GxCODE, where x = 0, 1 refers to PTA0 or PTA1 Voltage sensitivity ADC INL ADC DNL Voltage Measurement

(internal voltage or external pin) Sensor measurement time (note 7) Peak current (note 8) Power consumption (note 22) Raw measurement, 10-bit Compensation, 8-bit Basic compensated reading, 8-bit Full compensated reading, 8-bit VLVDL VLVDL tLVDL VLVDH VLVDH tLVDH VLVWL VLVWL tLVWL VLVWH VLVWH tLVWH VLVDRF tLVDRF VPORR VPORF VINT VINT VINT VINT VINT VINT VINT VINT VINT VINT n VEXT INL DNL tVM IV QV QV QV QV Min 1.79 1.87 2.05 2.12 2.05 2.12 2.28 2.34 1.60 0.8 1.6 2.0 2.2 2.4 2.7 3.2 3.5

-1

-1 Typ 1.88 1.79 FAULT 1.8 2.1 2.3 2.5 2.8 3.3 3.6 FAULT 10 1023 (VIN/VDD) VDD/1023 0.45 3.2 0.13 0.40 0.53 0.53 Max 1.96 2.03 10 2.3 2.3 10 2.3 2.3 10 2.54 2.61 10 1.95 10 2.1 2.0 2.2 2.4 2.6 2.9 3.4 3.7

+1

+1 0.53 3.9 0.3 0.64 0.9 0.9 Units V V sec V V sec V V sec V V sec V sec V V V V V V V V V V V mV/count count V/count LSB LSB ms mA A-sec A-sec A-sec A-sec

(2)

(3)

(3)

(1)

(3)

(3)

(1)

(3)

(3)

(1)

(3)

(3)

(2)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(1)

(3)

(3)

(3)

(3)

(4)

(4)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3) Note: Refer to page 169 for description of notes FXTH870x6 154 Sensors Freescale Semiconductor, Inc. Temperature Measurement Characteristics 17.7 2.3 VDD 3.6, TL TA TH, unless otherwise specified.

#

700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 Characteristic Symbol Temperature measurement (monotonic response) (note 11) TCODE = 0

= 15

= 35

= 55

= 84

= 125

= 140

= 180

= 255 Temperature sensitivity Temperature measurement stability range (note 10) Thermal Shutdown Recovery (TRE = 1) High Re-Arming Temperature (TRH = 1, note 13) High Reset Temperature (TRH = 1) Low Re-Arming Temperature (TRH = 0, note 13) Low Reset Temperature (TRH = 0) Temperature Measurement Sensor measurement time (note 7) Peak current (note 8) Power consumption (note 22) Raw measurement, 12-bit Compensation, 8-bit Basic compensated reading, 8-bit Full compensated reading, 8-bit T T T T T T T T T T TSTAB TREARMH TRESETH TREARML TRESETL tTM IT QT QT QT QT Note: Refer to page 169 for description of notes. Min

-45

-23

-3 26 67 81 120 95

-90 Typ Max Units FAULT

-40

-20 0 29 70 85 125 FAULT 1.0 0.6 3.0 0.19 0.43 0.62 0.62

-35

-17 3 32 73 89 130 2 125 4 0.7 3.9 0.3 0.6 0.82 0.82 C C C C C C C C C C/count count C C C C ms mA A-sec A-sec A-sec A-sec

(3)

(3)

(1)

(3)

(3)

(3)

(1)

(3)

(3)

(3)

(3)

(4)

(4)

(4)

(4)

(3)

(3)

(3)

(3)

(3)

(3) Sensors Freescale Semiconductor, Inc. FXTH870x6 155 Pressure Measurement Characteristic (100 to 450 kPa ranges) 17.8 2.3 VDD 3.6, TL TA TH, unless otherwise specified. Pressure accuracy specified for pressure drops slower than 1 kPa/sec. Characteristic Symbol Min Typ Max Units Pressure Measurement (note 6) 0 C TA +70 C

#

800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820

-20 C TA 0 C, 70 C TA 85 C

-40 C TA -20 C, 85 C TA 125 C PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 821*

Pressure Sensitivity 822**

Pressure Measurement Stability Range

* FSL D-FMEA class 163.

**FSL D-FMEA class 164. Note: Refer to page 169 for description of notes. PRANGE PSTAB P P P P P P P P P P P P P P P P P P P P P 93 100 268 436 443 89.5 96.5 264.5 432.5 439.5 83.2 90.2 258.2 426.2 433.2 FAULT 100 107 275 443 450 FAULT FAULT 100 107 275 443 450 FAULT FAULT 100 107 275 443 450 FAULT 0.688 107 114 282 450 457 110.5 117.5 285.5 453.5 460.5 116.8 123.8 291.8 459.8 466.8 6 kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa/count count

(3)

(4)

(3)

(3)

(3)

(4)

(3)

(3)

(4)

(3)

(1)

(3)

(4)

(3)

(3)

(4)

(3)

(3)

(3)

(4)

(3)

(3)

(3) FXTH870x6 156 Sensors Freescale Semiconductor, Inc. Pressure Measurement Characteristic (100 to 900 kPa Ranges) 17.9 2.3 VDD 3.6, TL TA TH, unless otherwise specified. Pressure accuracy specified for pressure drops slower than 1 kPa/sec. Characteristic Symbol Min Typ Max Units Pressure Measurement (note 6) 0 C TA +70 C

#

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921*

-20 C TA 0 C, 70 C TA 85 C

-40 C TA -20 C, 85 C TA 125 C PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 PCODE = 0

= 1

= 10

= 255

= 499

= 510

= 511 Pressure Range 922** Pressure Measurement Stability Range Pressure Sensitivity to Z-Axis Acceleration

(note 12) 0-500g

>500g Pressure Measurement Sensor measurement time (note 7) Peak current (note 8) Power consumption (note 22 Raw measurement, 10-bit Compensation, 9-bit Basic compensated reading, 9-bit Full compensated reading 923 924 925 926 927 928 929 930

* FSL D-FMEA class 194.

**FSL D-FMEA class 195. Note: Refer to page 169 for description of notes. P P P P P P P P P P P P P P P P P P P P P PRANGE PSTAB PACC PACC tPM IP QP QP QP QP 90 106 491 874 890 85 101 486 869 885 76 92 477 860 876 0

-6.5 FAULT 100 116 501 884 900 FAULT FAULT 100 116 501 884 900 FAULT FAULT 100 116 501 884 900 FAULT 1.572

-4.5 4.0 3.0 2.1 1.8 3.9 4.3 110 126 511 894 910 115 131 516 899 915 124 140 525 908 924 4 0

-2 4.4 3.4 3.25 2.3 5.3 5.85 kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa kPa/count count Pa/g Pa/g ms mA A-sec A-sec A-sec A-sec

(3)

(4)

(3)

(3)

(3)

(4)

(3)

(3)

(4)

(3)

(1)

(3)

(4)

(3)

(3)

(4)

(3)

(3)

(3)

(4)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3) Sensors Freescale Semiconductor, Inc. FXTH870x6 157 17.10 Optional Acceleration Sensor Characteristics 17.10.1 Example Z-Axis Acceleration Sensor Calculations (similar for X-Axis) As an example, consider that the dynamic firmware routine has returned STEP = 6 indicating offset step 6, and AZCODE = 256. First, refer to lines 1001 and 1009 to retrieve the step number 6 values for AZCODE = 510 and for AZCODE = 1. Then apply the following to calculate the sensitivity for offset step 6:

AZ-6

=

=

=

AZ-6 @ AZCODE510 AZ-6 @ AZCODE1 42.1 510 42.9 510 0.167g per AZCODE integer Eqn. 16 Once the sensitivity AZ-6 has been calculated, the acceleration AZ can be calculated with the following transfer function:

AZ

=

=

AZ-6 AZCODE 42.9 0.167 256

+

+

AZ-6 @ AZCODE1 AZ-6 0.167

=

0.3g Another example where STEP has been returned as 15 and AZCODE has been returned as 256:

AZ-15

=

=

AZ-15 @ AZCODE510 402 510 315

+

AZ-15

@ AZCODE1 510

=

0.171g per AZCODE integer Then:

AZ

=

=

AZ-15 AZCODE 0.171 315 256

+

+

AZ-15 @ AZCODE1 AZ-15 0.171

= 359g Eqn. 17 Eqn. 18 Eqn. 19 FXTH870x6 158 Sensors Freescale Semiconductor, Inc. 17.10.2 Acceleration Measurement Characteristics (Z and X ranges) 2.3 VDD 3.6, TL TA TH, unless otherwise specified. Acceleration accuracy specified for pressure drops slower than 1 kPa/sec. Characteristic Symbol FXTH870x02 family (Z-axis) FXTH870x11 family (Z-axis) Acceleration Measurement (note 9) Min Typ Max Min Typ Max Min FXTH870x11 family (X-axis) Typ Max ACODE = 0

= 1

= 16

= 196

= 250

= 256

= 262

= 316

= 496

= 510

= 511 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6

-42.9

-40.4

-10.3 FAULT FAULT FAULT

-51.9

-49.2

-14.7

-4.2

-3

-2.1 5.4 31.2 33.0 FAULT FAULT FAULT

-33.2

-31.1

-5.7 2.1 3 4.2 14.4 49.3 51.8

-1 0 1 9.7 39.8 42.1 Offset STEP = 7 Offset STEP = 7 See See Aaverage 0.167 0.118 0.039 g/count g/Offset 42 30 10 39.5 37 AINCR ASTAB 4 5 4

#

1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 ACODE Offset STEP ACODE Offset STEP ACODE Average Accel Sensitivity (1 to 510 counts) Average Offset step at acceleration output

= 256. VDD = 3 V Acceleration measurement stability range

(note 10) Minimum range of acceleration measurement for each offset code. Average Offset STEP= 0

= 1

= 256

= 510

= 1

= 1

= 256

= 510

= 2

= 1

= 256

= 510

= 3

= 1

= 256

= 510

= 4

= 1

= 256

= 510

= 5

= 1

= 256

= 510

= 6

= 1

= 256

= 510 Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE Units g g g g g g g g g g Step count

(3)

(3)

(3)

(3)

(3)

(1)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3) A0 A1 A2 A3 A4 A5 A6

-304

-215

-264

-173

-223

-132

-181

-88

-140

-48

-88

-45

-2

-271

-231

-191

-234

-193

-153

-197

-156

-114

-158

-117

-75

-120

-78

-36

-81

-39 4 238

-167

-204

-133 170 97

-136

-62

-100

-24

-74

-33 9 See lines 1001-1009

-210

-180

-150

-180

-150

-120

-150

-120

-90

-120

-90

-60

-90

-60

-30

-60

-30 0

-30 0 30

-80

-70

-60

-70

-60

-50

-60

-50

-40

-50

-40

-30

-40

-30

-20

-30

-20

-10

-20

-10 0 g g g g g g g Sensors Freescale Semiconductor, Inc. FXTH870x6 159

#

Characteristic Symbol FXTH870x02 family (Z-axis) FXTH870x11 family (Z-axis) Min Typ Max Min Typ Max Min FXTH870x11 family (X-axis) Typ Max A8 A7 A9 A10

-10 32 74 61 138 23 100 97 173 Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 2.3 VDD 3.6, -20 C TA 85 C, unless otherwise specified.

= 7

= 1

= 256

= 510

= 8

= 1

= 256

= 510

= 9

= 1

= 256

= 510

= 10

= 1

= 256

= 510

= 11

= 1

= 256

= 510

= 12

= 1

= 256

= 510

= 13

= 1

= 256

= 51

= 14

= 1

= 256

= 510

= 15

= 1

= 256

= 510 Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE Offset STEP ACODE 134 210 204 280 240 317 170 246 274 350 A12 A15 A13 A14 A11

#

1078 1079 1080 1081 Characteristic Acceleration cross-axis sensitivity Acceleration sensitivity variation Z-axis Acceleration Measurement Sensor measurement time (note 7) Peak current (note 8) Power consumption 1082 1083 1084 1085 Note: Refer to page 169 for description of notes. Raw measurement, 10-bit Compensation, 9-bit Basic compensated reading, 9-bit Full compensated reading, 9-bit Symbol ACROSS AZ tAM IA QC QC QC QC

-5 38 80 35 78 121 75 118 160 115 158 201 155 198 241 195 238 281 235 279 322 275 319 362 315 359 402 Min

-5

-15 1 44 87 47 142 88 183 133 229 176 273 221 317 267 364 310 408 356 455

-3 22 46 0 30 60 30 60 90 60 90 120 90 120 150 120 150 180 150 180 210 180 210 240 210 240 270 240 270 300 All families Typ 0 4.0 3.0 2.1 1.9 4.0 4.4

+3 38 74

-14

-3 6

-10 0 10

-6

+3 14 0 10 20 10 20 30 20 30 40 30 40 50 40 50 60 50 60 70 60 70 80 70 80 90 Max 5 15 4.8 3.4 3.6 2.3 6.0 6.0 Units g g g g g g g g g Units

%

%

ms mA A-sec A-sec A-sec A-sec

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(4)

(4)

(3)

(3)

(3)

(3)

(3)

(3) FXTH870x6 160 Sensors Freescale Semiconductor, Inc. LFR Sensitivity 17.11 2.3 VDD 3.6, -20 C TA 85 C, unless otherwise specified. Detection and no detection criteria defined by notes 19 and 20. Characteristic Symbol Min Typ Max Units

#

1100 1101 1102 1103 1104 1105 1106 1107 LFR Input Sensitivity in carrier mode, 125 kHz carrier, LFCDTM = 256 s UOS Very Low Sensitivity, SENS(1:0) = 00 Detect level, LFA:B No detect level, LFA:B Low Sensitivity, SENS(1:0) = 00 Detect level, LFA:B No detect level, LFA:B High Sensitivity, SENS[1:0] = 10, CHK125 = 01 Detect level, LFA:B No detect level, LFA:B Sensitivity Shift in High Sensitivity, SENS[1:0] = 10, CHK125 = 00 SDET_VL SNODET_VL SDET_L SNODET_L SDET_H SNODET_H Detect level, LFA:B, (typical difference observed between CHK125 = 00 and 01 No detect level, LFA:B, No detect level, LFA:B (typical difference observed between CHK125 = 00 and 01) SDET_H SNODET_H 24 2 0.5 LFR Input Sensitivity in data mode 125 kHz carrier, LFCDTM = 64 sec Valid reception of 10 consecutive frames of 16-bit Manchester bit preamble + 9T SYNC +16-bit ID + 4 bytes of data. Continuously ON High Sensitivity, SENS[1:0] = 10, CHK125 = 01 1108 1109 Data detect level Data no detect level SPER_H SNOPER_H 0.25 LFR Input Sensitivity in data mode 125 kHz carrier, LFCDTM = 64 sec Valid reception of 10 consecutive frames of 16-bit Manchester bit preamble + 9T SYNC +16-bit ID + 4 bytes of data. Continuously ON Low Sensitivity, SENS[1:0] = 01, CHK125 = 00 1110 1111 Data detect level Data no detect level Note: Refer to page 169 for description of notes. SPER_L SNOPER_L 2

-0.12

-0.12 60 14 3.5 mV p-p mV p-p mV p-p mV p-p mV p-p mV p-p mV p-p mV p-p

(4)

(4)

(4)

(4)

(2)

(2)

(3)

(3) 3.5 mV p-p mV p-p

(2)

(2) 14 mV p-p mV p-p

(3)

(3) Sensors Freescale Semiconductor, Inc. FXTH870x6 161 LFR Characteristics 17.12 2.3 VDD 3.6, -20 C TA 85 C, unless otherwise specified.

#

1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 Characteristic Symbol Min Typ Max Units LF Input Signal Characteristics Relative to High Sensitivity Data Mode Always Detect, SPER_H Dynamic Range, DEQEN = 0 LFR Input Signal Characteristics

(Manchester Data Mode) Modulation Depth (Data 1 - Data 0)/Data 1 Data bit time Bit Duty Cycle LFR Differential Input (LFA to LFB, Figure 122) Differential Resistance Differential Capacitance (C3) LFR Carrier Frequency Range VALEN = 1, LFCDTM = 256 sec Always accepted carrier Always rejected carrier, rejected frequencies upper limit Always rejected carrier, rejected frequencies lower limit VALEN = 0, LFCDTM = 256 ms High Cutoff Freq, 5 mV p-p input, SENS[1:0] = 00 LFR Detector Power Up Settling Time (2 LFO cycles) LFR Preamble Decoder Settling Time Data Mode Only, LFCDTM plus tDEC LPSM = 0 LPSM = 1 VIN MR tDATA MDC RLFDF CLFDF fLFC fLFCH fLFCL fLFCO tPU tDEC tDEC 56 70 248 45 1 2 121.25 210 1.4 dB

(3) 256 3.8 350 2.0 100 264 55 4 6 128.75 80 2.6 200 400

%

sec

%

M pF kHz kHz kHz kHz ms sec sec

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(4)

(4)

(4)

(4) Note: Refer to page 169 for description of notes. LFR Power Consumption 17.13 2.3 VDD 3.6, -20 C TA 85 C, unless otherwise specified. All parameters based upon DEQEN = 0 setting.

#

1300 1301 1302 1303 1304 1305 1306 1307 Characteristic Symbol Min Typ Max Units LFR Supply Current, Carrier Detect Mode Monitor for carrier with VALEN = 0, LPSM = 1 TA = 25 C, 3.0 V VDD TA = -40 C to 125 C, 2.3 to 3.6 V VDD Frequency validation with VALEN = 1, LPSM = 1 and CHK125 = 00 TA = 25 C, 3.0 V VDD TA = -40 C to 125 C, 2.3 to 3.6 V VDD Frequency validation with VALEN = 1, LPSM = 1 and CHK125 = 01 TA = 25 C, 3.0 V VDD TA = -40 C to 125 C, 2.3 to 3.6 V VDD LFR Supply Current, Manchester Data Mode Decoding of data stream after carrier detected TA = 25 C, 3.0 V VDD TA = -40 C to 125 C, 2.3 to 3.6 V VDD ILFR ILFR ILFR ILFR 3.9 5.6 5.8 5.5 7.5 8.0 A

(3) A

(3) A

(1) 11.8 13.5 A

(3) Note: Refer to page 169 for description of notes. FXTH870x6 162 Sensors Freescale Semiconductor, Inc. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZS VAS L RS C LS R CS Pad leakage due to input protection RS, CS LFA

+

VLFIN RLFDF CLFDF Pad leakage due to input protection LFB Recommended RC < 15.3 sec SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN R1 R2 Input Amplifier SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN Figure 122. LFR Detector Input Equivalent Circuit Sensors Freescale Semiconductor, Inc. FXTH870x6 163 17.14 RF Output Stage 1.8 VDD 3.6, TL TA TH, unless otherwise specified. Power output based on using Dynamic RF Power Correction firmware routine. Output load of 50 resistance as shown in Figure 125 unless otherwise specified. MCU in STOP1 mode during all RF tests. RF output will shutdown when the total RF IDD causes VDD to fall below 1.8 V (VDD = VBATT - IBATT x RBATT). See Figure 126. Characteristic Symbol Min Typ Max Units

#

1400 1401 1402*

1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 Nominal Output Power with 50 matching network

(note 21) 315 MHz, TA = 25 C, VDD = 3 V, PWR[4:0] = 01110 434 MHz, TA = 25 C, VDD = 3 V, PWR[4:0] = 01111 Nominal Output Power with 50 matching network at maximum power step, PWR[4:0] = 10100. Temperature and voltage range defined by Figure 123 and Figure 124. Programmable Power Adjustment PWR[4:0] = 00000 through 11111 Low Power Mode (PWR[4:0] = 00000) Range (nominal, (PWR[4:0] > 00000) Adjustment step (-1.5 to +8 dBm) Programmable Frequency Steps Carrier & FSK Deviation

(AFREQ[12:0] and BFREQ[12:0]) External Crystal Frequency (note 14) Fixed portion of RF start process, Variable portion of RF start process Total RF transmit start time from write of SEND bit to start of RF @ 2,000 bps tRF = tS-RCTS + (Bits * bps-1) Total RF transmit start time from write of SEND bit to start of RF @ 9,600 bps tRF = tS-RCTS + (Bits * bps-1) Total RF transmit start time from write of SEND bit to start of RF @ 20,000 bps tRF = tS-RCTS + (Bits * bps-1) OOK Modulation Depth Manchester Encoding Data Rate 1414 Bit Rate Dependent on accuracy of MFO (note 18). 1415 Modulation Duty-Cycle (OOK and FSK) 1416 XTAL Oscillator Margin (over 26 MHz) (note 17) Harmonic 2 Level (315 and 434 MHz bands, with matching reference network) VDD = 3 V, TA = 25 C, PWR[4:0] = 01110 1.8 VDD 3.6, TL TA TH, power step adjusted to reach the targeted power in each domain Harmonic 4 Level and above (315 and 434 MHz bands, with matching reference network) VDD = 3 V, TA = 25 C, PWR[4:0] = 01110 1.8 VDD 3.6, TL TA TH, power step adjusted to reach the targeted power in each domain 1417 1418 1419 1420 PRF PRF PRF PLPM PRF PADJ fSTEP fXTAL tS-RCTS Bits tRF2 tRF9.6 tRF20 MOOK DR DC ML H2 H2 H4 H4 4.0 3.5 3

-1.5 50 45 600 5.2 4.9

-10 0.5 3.174 26.000 3 50

-35

-25 6.0 6.0 8.0 300 1.8 613 450 5 55

-22

-20

-30

-30 dBm dBm

(1)

(1) dBm

(3) dBm dBm dBm kHz MHz sec bit times ms sec sec dBc

%

%

dBc dBc dBc dBc

(3)

(3)

(3)

(3)

(3)

(3)

(4)

(3)

(3)

(3)

(3)

(3)

(3)

(4)

(3)

(3)

(3)

(3) FXTH870x6 164 Sensors Freescale Semiconductor, Inc.

#

1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 Characteristic Symbol Min Typ Max Units Harmonic 3 Level (315 and 434 MHz bands, with matching reference network) VDD = 3 V, TA = 25 C, PWR[4:0] = 01110 1.8 VDD 3.6, TL TA TH, power step adjusted to reach the targeted power in each domain Noise for BOOST = 0 Phase Noise (315 MHz) fRF 10 kHz fRF 100 kHz fRF 1 MHz Phase Noise (434 MHz) fRF 10 kHz fRF 100 kHz fRF 1 MHz fRF fREF Spurious Noise (315 and 434 MHz bands) Occupied Bandwidth (Korea, MIC 2007-63) For FSK up to 45 kHz and 9600 bit/sec and for OOK up to 9600 bit/sec Analyzed setup: RBW = VBW up to 10 kHz, Span up to 1.25 MHz, and MaxHold Noise for BOOST = 1 Phase Noise (315 MHz) fRF 10 kHz fRF 100 kHz fRF 1 MHz fRF fREF Spurious Noise (315 MHz bands) Occupied Bandwidth (Japan, ARIB STD-T93) For FSK up to 45 kHz and 9600 bit/sec For OOK up to 9600 bit/sec Analyzed setup: RBW = VBW up to 30 kHz, Span up to 3.5 MHz, and MaxHold H3 H3 NPH NPH NPH NPH NPH NPH NSPUR OBWK NPH NPH NPH NSPUR OBWJ OBWJ

-31

-27

-86

-92

-84

-84

-89

-82

-45

-75

-80

-95

-45

-28

-25

-78

-86

-82

-76

-83

-80

-40 180

-67

-76

-93

-40 400 600 dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc kHz dBc/Hz dBc/Hz dBc/Hz dBc kHz kHz

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3) RF Oscillator Frequency Accuracy, XCO (note 21) excluding external crystal and component variations fXCO

-30

+30 ppm

(3)

* FSL D-FMEA class 306. Note: Refer to page 169 for description of notes. Sensors Freescale Semiconductor, Inc. FXTH870x6 165 Power Consumption RF Transmissions 17.15 1.8 VDD 3.6, TA 25 C unless otherwise specified.

#

1500 1501 1502 1503 1504 1505 1506 1507 Characteristic Symbol Min Typ Max Units RF Supply Transmission Current VDD = 3.0 V, PWR[4:0] set for nominal 5 dBm 315 MHZ Power delta for BOOST = 1 315 MHZ Carrier Frequency, BOOST = 0 Data 1, FSK or OOK 434 MHZ Carrier Frequency, BOOST = 0 Data 1, FSK or OOK Interframe period, IFPD = 0. Interframe period, IFPD = 0, 1.8 VDD 3.6, TL TA TH Interframe period, IFPD = 1, DRLPEN = 1, 1.8 VDD 3.6, TL TA TH Interframe period, IFPD = 1, DRLPEN = 0 Interframe period, IFPD = 1, DRLPEN = 0, 1.8 VDD 3.6, TL TA TH IDD IDD IDD IDD IDD IDD IDD IDD 6.0 6.6 617 20 77 0.55 7.0 7.6 696 789 29 96 125 mA mA mA A A A A A

(2)

(1)

(1)

(3)

(3)

(3)

(3)

(3) Note: Refer to page 169 for description of notes. Using the TPMS_RF_DYNAMIC_POWER firmware routine (see Section 14) allows adjusting power step in order to compensate variations of output power versus temperature and voltage. This routine will be associated to a part to part trimming that initially adjusts the power step to compensate for process variations. Both these trim and look-up table allow to guarantee by characterization the typical values of power consumption as presented below (average values among 100 parts plus improvements prediction from design). 5.3mA 5.3mA 5.0mA 5.2mA 5.3mA 5.3mA

-40C

-40C FXTH870x6 166 6mA 6mA 6.2mA 6mA 6mA 6.2mA

. 6.2mA 6.2mA 6.4mA 5.8mA 5.8mA 5.8mA 5dBm 5dBm 5dBm 3dBm 3dBm 6.4mA 6.3mA 6.3mA 6.5mA 6.6mA 6.6mA 5.8mA 5.7mA 5.7mA 3dBm 3dBm 3dBm 3.6V 3.6V 5.5mA 5.5mA 5.3mA 3V 3V 3dBm 3dBm 2.5V 2.5V 5.4mA 5.5mA 5.5mA 1.8V 1.8V 0C 0C 25C 25C 60C 60C 125C 125C Figure 123. Dynamic Power Adjustment - 315 MHz Sensors Freescale Semiconductor, Inc. 5.5mA 5.5mA 5.6mA 5.8mA 6.3mA 6.3mA

-40C

-40C 6.7mA 6.7mA 6.9mA 6.6mA 6.6mA 6.9mA

. 6.8mA 6.8mA 7.1mA 6.4mA 6.4mA 6.6mA 5dBm 5dBm 5dBm 3dBm 3dBm 7.0mA 7.1mA 7.1mA 7.5mA 7.8mA 7.8mA 7.0mA 6.8mA 6.8mA 3dBm 3dBm 3dBm 3.6V 3.6V 5.7mA 5.7mA 5.8mA 3V 3V 3dBm 3dBm 2.5V 2.5V 6.2mA 6.5mA 6.5mA 1.8V 1.8V 0C 0C 25C 25C 60C 60C 125C 125C Figure 124. Dynamic Power Adjustment - 434 MHz 100 pF 100 nF VDD FXTH870xxx RF L2 L1 1 nF RVSS Figure 125. RF Output Power Measurement Configuration FXTH870xxx AVDD 50 IBATT RBATT 1 F VBATT 2.7V AVSS Figure 126. Battery Performance Test Configuration Sensors Freescale Semiconductor, Inc. FXTH870x6 167 18 Mechanical Specifications Maximum Ratings 18.1 Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD.

#

1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 Rating Symbol Value Maximum Pressure (absolute) Continuous Pulsed, 5 seconds, 25 C Centrifugal Force Effects (Z-axis) Sustained acceleration (Z-axis) Powered Shock (peak, 0.1 ms, half-sine, 6-axis) Drop Test (onto concrete, unpowered) Pressure Sensor Resonance Resonant frequency Damping Ratio Optional X-axis Accelerometer Sensor Resonance Resonant frequency (no-peak, over-damped) Damping Ratio Maximum acceleration before limit stops are reached Optional Z-axis Accelerometer Sensor Resonance Resonant frequency (no-peak, over-damped) Damping Ratio Maximum acceleration before limit stops are reached Package Weight pmax pmax gCENT gshock hDROP fP0 QP fX0 QX gMAX fZ0 QZ gMAX w 1500 2000 2600 6000 1.2 5.5 1 12.5 0.1 180 9 5 800 0.30 Unit kPa kPa g g m MHz kHz g kHz g gm

(3)

(3)

(3)

(3)

(3)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(3) Note: Refer to page 169 for description of notes. Media Compatibility 18.2 Media compatibility is based on media and test method described in Freescale specification 12MWS10081G, Media Test for TPMS MCM Automotive Pressure Sensors. Consult your sales representative for more details and specific requirements. Mounting Recommendations 18.3 The package should be mounted with the pressure port pointing away from the axis of tire rotation so that centrifugal force will propel any contaminants out of the pressure port. In cases where the application must orient the pressure port pointing inward, care must be taken to assure contaminants do not reach inside the pressure port. A plugged port will exhibit no change in pressure and can be cross checked in the users software using the method described in Section 10.1. Please refer to application note AN1902 for proper printed circuit board attributes and recommendations. FXTH870x6 168 Sensors Freescale Semiconductor, Inc. Notes:

1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. 4. For information only, may be determined by simulation. 5. Total of three hours over the life of the device. 6. Fully compensated pressure reading using TPMS_READ_PRESSURE followed by TPMS_COMP_PRESSURE routine with single reading and 500 Hz low-pass filter ON. 7. Measurement times for one complete compensated reading; and times dependent on clock tolerances. 8. Peak currents measured as the current over 10 MCU bus cycles immediately after the ADC wakes up the MCU using the external network shown in Figure 126 with RBATT equal to zero-ohm resistance. 9. Fully compensated acceleration reading using TPMS_READ_ACCELERATION followed by TPMS_COMP_ACCELERATION routine with single reading and 500 Hz low-pass filter ON. 10. Total range of variation over 30 consecutive measurements, using compensated output format. 11. Temperature error for MCU or RFM powered up at less the 10% duty-cycle 12. Package mounted with pressure port facing radially outward from axis of rotation. 13. Temperature shutdown points trimmed at final test. Limits when TRH ($180F bits 6:4) overwritten by customer application to 0x06. 14. Suggested crystal is NDK NX3225SA, 26.000 MHz. 15. Low voltage detection and warning thresholds defined for voltage change rates less than 20 mV/s. Hysteresis thresholds may decrease above 85 C. 16. Response time to VDD of more than 100 mV below the minimum VDD falling threshold. 17. Crystal oscillator margin is the value of the total series resistance including the XTAL ESR, that can be applied before the XCO does not start up. This definition does not define any specific start up time. 18. Accuracy of the RF data rate when using the data buffer is dependent on the overall oscillator function (i.e. including external crystal and internal circuit tolerances). 19. LFR detection is tested to assure > 90% message success rate. LFR no detection is tested to assure < 10%

message success rate. In carrier detect mode the applied input pulse is at least 2x the LFCDTM selected. In all cases the envelop of the input waveform must have a RC time constant less than 15.3 sec. LF sensitivity limits are measured while the device is in the STOP1 mode, which is characterized as a worst-case condition; sensi-

tivity in the other modes are improved versus the STOP1 modes. 20. Using firmware release $28 or higher for FXTH870x02, FXTH870x11 and FXTH870x12; using firmware release

$11 for FXTH870x22. 21. Actual final test value degraded by losses in the tester. Correlation study done as characterization to infer actual value. 22. Power consumption values refer to the firmware data flow in Figure 57. The BASIC Compensated value includes just the raw measurement and compensation routine for that parameter. Other raw readings needed for full com-

pensation will be pulled from the UUMA. The FULL Compensated value includes taking all required raw read-

ings and using the compensation routine for that parameter. Sensors Freescale Semiconductor, Inc. FXTH870x6 169 19 Package Outline Figure 127. QFN Case Outline FXTH870x6 170 Sensors Freescale Semiconductor, Inc. Figure 128. QFN Case Outline Sensors Freescale Semiconductor, Inc. FXTH870x6 171 Figure 129. QFN Case Outline FXTH870x6 172 Sensors Freescale Semiconductor, Inc. Sensors Freescale Semiconductor, Inc. FXTH870x6 173 Revision History Initial data sheet. 20 Rev. 0, 05/2014 Rev. 1, 07/2014 Rev. 1.1, 07/2014 Rev. 1.2, 08/2014 Corrected Ordering Information table. Figure 5: Updated paragraph in figure to include PCB traces for the LFA/LFB and note regarding L1. Section 5.4: Updated register figure to include TRO bit on Bit 0. Added Description to Table 19 and update reserved bit fields. Section 6.1: Updated last paragraph in section. Section 10.1: Added NOTE. Section 10.4: Added NOTE. Section 14.2.2: Added definitions for ID codes. Section 17.10.2: Changed column content reference from See lines 1042-1045 to See Offset STEP = 7. Corrected Min, Typ and Max values for lines 1042-1045 for FXTH870x11 family (X-Axis). Section 17.12: Updated Characteristic and Min Value for line 1200. Updated Characteristic and note reference for line 1210. Section 17.4: Updated Symbols for lines 400 through 412 and lines 417 and 418. Section 17.6: Updated Max value for line 612 and updated note reference and Symbol for line 613. Section 17.7: Updated note references for lines 711-714. Section 17.9: Updated Typ and Max values for line 924. Updated Typ values for lines 927 through 930. Section 17.10.2: Deleted line 1078 and updated Typ values for lines 1083 through 1086. Section 17.11: Updated Typ value for line 1106. Deleted lines 1108-1113, duplicated information. Section 17.12: Updated Symbols for lines 1208 through 1210 and updated Characteristics for lines 1208 and 1209. Section 17.13: Update Max value for line 1301. Section 18.1: Updated Max value for line 1800. First page: Updated bullet Six multipurpose GPIO pins to Seven multipurpose GPIO pins and sub-bullets Section 2.3.8: Updated paragraph with additional content. Section 2.3.9: Updated title and paragraphs with corrected pin numbers and added text to paragraph. Section 2.3.12: Updated content in paragraph. Section 3.5.4: Updated header title for I/O Pins, deleted (Optional PTA[3:0]). Section 4.3: Table 3, updated Bit contents for Address columns $0000, $0001 and $0003. Section 6: Updated content in first two paragraphs. Updated Figure 29, added boxes and note for emphasis on PTA[3:0]

usage. Updated title and column heads in Table 32 and added rows for PTAPE, PTBPE, PTADD and PTBDD. Updated first paragraph in Section 6.5. Section 7: Section 7.1: Updated 1st bullet. Section 7.2.1: Updated content in first paragraph. Section 7.5: Updated bulleted text. Sections 7.5.2 and 7.5.3: Updated tables and figures to show bits reserved for firmware or factory test. Section 7.6:

Updated content in second paragraph. Section 7.6.3: Updated content in paragraph. Section 7.6.4: Updated list number 3 and 4. Section 12.17.1: Updated LF Enable description in Table 59. Section 12.17.8: Added Note after Table 67 regarding setting the CHK125 bits and updated Description for Field 1-0, CHK125[1:0]. Section 17.3: Updated Characteristic for line 311. Section 17.12: Updated Min and Max values for line 1206 and updated Characteristic. Section 17.14: Redefined lines 1408 through 1411 and added line 1412, Section 18.1: Updated Value for line 1802. Notes page: Updated Notes 18,19, 20 and added note 25. FXTH870x6 174 Sensors Freescale Semiconductor, Inc. Rev. 1.3, 09/2014 Section 4.3: Table 3, updated Addresses $0001 and $0003 Bit 4 column to reserved and text corrected to [3:0]. Section 5.11.2: Table 26, updated Description for BKGDPE Field Section 6: Updated 2nd paragraph. Updated column heads for Table 32. Figure 31 and Table 34, updated Bit 4 to Reserved and updated Field name. Figure 32 and Table 35, updated Bit 4 to Reserved and updated Field name. Section 7.6.3: Updated paragraph contents. Section 12.17.4: Table 62, removed Use Software polling from LFCDIE and LFIDIE Descriptions. Section 12.17.8: Table 67, updated Description for CHK125. Section 14.2.1.1: Table 86, changed Routine and Description columns for E084 to Reserved. Table 87, changed Routine and Description columns for E090 to Reserved. Section 17.1: Added Value to line 108. Section 17.4: Updated Characteristic for line 412. Section 17.6 Updated Value for line 631. Section 17.8: Added asterisk notes to lines 821 and 822. Section 17.9: Added asterisk notes to lines 921 and 922. Section 17.13: Updated introduction paragraph. Section 17.14: Added asterisk note to line 1402. Section 17.15: Updated Characteristic for line 1500. Updated Typ value for line 1505. Notes page: Updated note 2. Section 17.3: Updated Characteristic column for lines 303, 305, 307, 308, 310, and 311. Changed note reference for lines 306 and 309. Updated Min and Max values for lines 308 and 311. Section 17.6: Changed note reference for lines 603, 606, and 609. Section 17.6: Updated Max value for line 711. Updated Min Value for line 712. Section 17.15: Changed note reference for lines 1502 and 1504. Replaced Figures 123 and 124. Notes page: Updated note 13. Replaced case outline with current version. Section 14.2.2: Table 88, added two columns, Initial Address and Updated Address. Rev. 1.4, 01/2015 Rev. 1.5, 02/2015 Sensors Freescale Semiconductor, Inc. FXTH870x6 175 How to Reach Us:

Home Page:

freescale.com Web Support:

freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customers technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:

freescale.com/salestermsandconditions. Freescale, the Freescale logo and CodeWarrior are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. 2015 Freescale Semiconductor, Inc. Document Number: FXTH870x6 Rev. 1.5 02/2015