submitted | available | document details (if available) | source link |
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various | Users Manual | Users Manual | 2.57 MiB | July 27 2020 / July 28 2020 |
FIBOCOM L850-GL Series Hardware Guide Version: V1.1.5 Date: 2020-06-20 No. Product Model Description Applicability Type 1 2 3 4 5 6 7 8 9 L850-GL-00 L850-GL-01 L850-GL-02 L850-GL-03 L850-GL-05 L850-GL-10 L850-GL-10-06 L850-GL-12 L850-GL-20 NA NA NA NA NA NA NA NA L850-GL-10 series (except L850-GL-10-06) Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 2 of 59 Copyright Copyright 2020 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or distribute the document in any form. Notice The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide. All the statements, information and suggestions contained in the document do not constitute any explicit or implicit guarantee. Trademark The trademark is registered and owned by Fibocom Wireless Inc. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 3 of 59 Change History Version Author Date Remark V1.1.5 Shu Ying 2020-06-20 Section 3.4.1.2, change PEWAKE# pull high resistor to Section 3.3.1, add FCPO# controlling GPIO request V1.1.4 Li Senhao 2020-04-01 V1.1.3 Guan Xiangyang 2019-12-26 Section 3.4.1.2, add a pull-up resistor on CLKREQ#
Section 3.3.5, add timing application instruction V1.1.2 Guan Xiangyang 2019-09-06 Add L850-GL-20 product model V1.1.1 Guan Xiangyang 2019-08-22 Section 3.4, add Chrome OS support in USB interface 100K note Section 3.1.2, add GPIO design request Section 3.3.4, add CLKREQ# and PEWAKE# requests Section 3.3.1.2, add minimum PCIe detection time Section 3.9, add note about the direction of MIPI signal Section 4.1.4, add RF connector assembly Section 4.5, update GNSS performance table Add L850-GL-10-06 and L850-GL-20 part numbers Section 2.2, list supporting RF bands of all product Section 3.3, add note of PERST# control timing in USB Section 4.3, modify LTE Band5 TX power range Section 3.2.3, update power consumption Section 3.3, update module control timing Section 4.5, update GNSS consumption Section 3.3.4.1, add D0 L1.2 timing Section 3.9, modify MIPI-RFFE power domain Section 5.6, update packing Section 3.4.1.2, fix Figure 3-12 abnormal display in PDF converting V1.1.0 Lei Daijun 2019-05-05 V1.0.9 Lei Daijun 2018-08-06 Add L850-GL-12 part no V1.0.8 Lei Daijun 2018-07-13 Modify band 30 TX power range of L850-GL-03 serial module Update package V1.0.7 Lei Daijun 2018-06-26 Add note about PERST#/CLK_REQ# 3.3V support Add antenna of B30 requirement, update power V1.0.6 Lei Daijun 2018-02-26 consumption and RX sensitivity Modify COEX pin define Delete L850-GL-02 product model Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 4 of 59 Version Author Date Remark V1.0.5 Lei Daijun 2018-01-16 Modify description of power consumption condition Modify CA combinations and TDD data throughput V1.0.4 Lei Daijun 2017-12-06 V1.0.3 Lei Daijun 2017-07-26 Update power consumption, TX power, RX sensitivity Optimize power on/off/reset timing Update Storage and packing and PCIe signal description, power consumption, CA combine Update timing of power on/off and reset Update PCIe, add USB support and other data Update the content of PCIe Add the power Consumption of 3CA Modify the PCIe Interface Application;
Update the Pin Definition: change pin65 to NC V1.0.2 Lei Daijun 2017-02-09 V1.0.1 Lei Daijun 2016-12-16 V1.0.0 Lei Daijun 2016-12-08 Initial version Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 5 of 59 Contents 1 Foreword ........................................................................................................................ 9 Introduction ..................................................................................................................... 9 Reference Standard ....................................................................................................... 9 Related Documents ........................................................................................................ 9 2 Overview ...................................................................................................................... 10 Introduction ................................................................................................................... 10 Specification ................................................................................................................. 10 CA Combinations .......................................................................................................... 12 Application Framework ................................................................................................. 13 Hardware Block Diagram ............................................................................................. 14 1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 3 Application Interface ................................................................................................... 15 3.1 M.2 Interface ................................................................................................................ 15 3.1.1 Pin Map........................................................................................................................ 15 3.1.2 Pin Definition ................................................................................................................ 16 3.2 Power Supply ............................................................................................................... 20 3.2.1 Power Supply ............................................................................................................... 20 3.2.2 Logic Level ................................................................................................................... 22 3.2.3 Power Consumption .................................................................................................... 22 3.3 Control Signal ............................................................................................................... 25 3.3.1 Module Start-Up ........................................................................................................... 25 3.3.1.1 Start-up Circuit ............................................................................................................................ 25 3.3.1.2 Start-up Timing Sequence ........................................................................................................... 26 3.3.2 Module Shutdown ........................................................................................................ 27 3.3.3 Module Reset ............................................................................................................... 28 3.3.4 PCIe Link State ............................................................................................................ 29 3.3.4.1 D0 L1.2 ........................................................................................................................................ 30 3.3.4.2 D3cold L2 ...................................................................................................................................... 30 3.3.5 Timing Application ........................................................................................................ 32 3.4 IPC Interface ................................................................................................................ 32 3.4.1 PCIe Interface .............................................................................................................. 33 3.4.1.1 PCIe Interface Definition ............................................................................................................. 33 3.4.1.2 PCIe Interface Application ........................................................................................................... 34 3.4.2 USB Interface .............................................................................................................. 35 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 6 of 59 3.4.2.1 USB Interface Definition .............................................................................................................. 36 3.4.2.2 USB2.0 Interface Application ....................................................................................................... 36 3.4.2.3 USB3.0 Interface Application ....................................................................................................... 36 3.5 USIM Interface ............................................................................................................. 37 3.5.1 USIM Pins .................................................................................................................... 37 3.5.2 USIM Interface Circuit .................................................................................................. 38 3.5.2.1 N.C. SIM Card Slot ...................................................................................................................... 38 3.5.2.2 N.O. SIM Card Slot...................................................................................................................... 38 3.5.3 USIM Hot-Plug ............................................................................................................. 39 3.5.4 USIM Design ................................................................................................................ 39 3.6 Status Indicator ............................................................................................................ 40 3.6.1 LED#1 Signal ............................................................................................................... 40 3.7 Interrupt Control ........................................................................................................... 41 3.7.1 W_DISABLE1# ............................................................................................................ 41 3.7.2 BODYSAR ................................................................................................................... 41 Clock Interface ............................................................................................................. 41 ANT Tunable Interface ................................................................................................. 42 3.10 Configuration Interface ................................................................................................. 42 4 Radio Frequency ......................................................................................................... 44 4.1 RF Interface .................................................................................................................. 44 4.1.1 RF Interface Functionality ............................................................................................ 44 4.1.2 RF Connector Characteristic ........................................................................................ 44 4.1.3 RF Connector Dimension ............................................................................................. 44 4.1.4 RF Connector Assembly .............................................................................................. 46 Operating Band ............................................................................................................ 48 Transmitting Power ...................................................................................................... 49 Receiver Sensitivity ...................................................................................................... 50 GNSS ........................................................................................................................... 51 Antenna Design ............................................................................................................ 52 5 Structure Specification ............................................................................................... 54 Product Appearance ..................................................................................................... 54 Dimension of Structure ................................................................................................. 54 M.2 Interface Model ...................................................................................................... 55 M.2 Connector .............................................................................................................. 55 3.8 3.9 4.2 4.3 4.4 4.5 4.6 5.1 5.2 5.3 5.4 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 7 of 59 5.5 Storage ......................................................................................................................... 56 5.5.1 Storage Life ................................................................................................................. 56 5.6 Packing ......................................................................................................................... 56 5.6.1 Tray Package ............................................................................................................... 56 5.6.2 Tray Size ...................................................................................................................... 59 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 8 of 59 1 Foreword 1.1 Introduction The document describes the electrical characteristics, RF performance, dimensions and application environment, etc. of L850-GL (hereinafter referred to as L850). With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of L850 modules and develop products. 1.2 Reference Standard The design of the product complies with the following standards:
3GPP TS 34.121-1 V8.11.0: User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification 3GPP TS 34.122 V11.13.0: Technical Specification Group Radio Access Network; Radio transmission and reception (TDD) 3GPP TS 36.521-1 V11.4.0: User Equipment (UE) conformance specification; Radio transmission and reception; Part 1: Conformance testing 3GPP TS 21.111 V10.0.0: USIM and IC card requirements 3GPP TS 51.011 V4.15.0: Specification of the Subscriber Identity Module -Mobile Equipment (SIM-
3GPP TS 31.102 V10.11.0: Characteristics of the Universal Subscriber Identity Module (USIM) ME) interface application 3GPP TS 31.11 V10.16.0: Universal Subscriber Identity Module (USIM) Application Toolkit(USAT) 3GPP TS 36.124 V10.3.0: Electro Magnetic Compatibility (EMC) requirements for mobile terminals and ancillary equipment 3GPP TS 27.007 V10.0.8: AT command set for User Equipment (UE) 3GPP TS 27.005 V10.0.1: Use of Data Terminal Equipment - Data Circuit terminating Equipment
(DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) PCI Express M.2 Specification Rev1.2 1.3 Related Documents FIBOCOM Design Guide_RF Antenna Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 9 of 59 2 Overview 2.1 Introduction world. 2.2 Specification Specification L850 is a highly integrated 4G WWAN module which uses M.2 form factor interface. It supports LTE FDD/LTE TDD/WCDMA systems and can be applied to most cellular networks of mobile carrier in the L850-GL-00, L850-GL-01, LTE FDD: Band 1, 2, 3, 4, 5, 7, 8, 11, 12, 13, 17, 18, L850-GL-02, L850-GL-03, 19, 20, 21, 26, 28, 29, 30, 66 L850-GL-05, L850-GL-10 series (except L850-GL-
LTE TDD: Band 38, 39, 40, 41 WCDMA/HSPA+: Band 1, 2, 4, 5, 8 Operating Band 10-06) L850-GL-12 L850-GL-20 L850-GL-10-06 LTE FDD: Band 2, 4, 5, 13 GNSS LTE UMTS Support GPS, GLONASS, BDS 3GPP Release 11 3GPP Release 8 LTE FDD 450Mbps DL(Cat 9)/50Mbps UL(Cat 4) 347Mbps DL(Cat 9)/30Mbps UL(Cat 4) Data Transmission LTE TDD When LTE TDD achieves maximum DL rate, its UL rate can reach 10Mbps only UMTS: 384 kbps DL/384 kbps UL UMTS/HSPA+
DC-HSPA+: 42Mbps DL(Cat 24)/5.76Mbps UL(Cat6) Power Supply DC 3.135V~4.4V, Typical 3.3V Normal operating temperature: -10C~+55C Temperature Extended operating temperature: -20C~+65C Storage temperature: -40C~+85C Physical characteristics Interface: M.2 Key-B Dimension30422.3mm Weight: About 6.2 g Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 10 of 59 Interface Antenna Connector WWAN Main Antenna 1 WWAN Diversity Antenna 1 USB 3.1 Gen1 (Base on Android/Linux) Function Interface BodySAR USIM 3V/1.8V PCIe Gen1 1 USB 2.0 W_Disable#
LED Clock Tunable antenna I2S (Reserved) I2C (Reserved) Software Protocol Stack IPV4/IPV6 AT commands 3GPP TS 27.007 and 27.005 Firmware update PCIe Other feature Windows MBIM support Multiple carrier Windows update Note:
When temperature goes beyond normal operating temperature range of -10C~+55C, RF performance of module may be slightly off 3GPP specifications. For normal operating temperature, LTE FDD Band 4 and 13 can support temperature ranging from -20C to +60C. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 11 of 59 L850-GL-00, L850-GL-01, L850-GL-02, L850-GL-03, L850-GL-05, L850-GL-10 series (except L850-
2.3 CA Combinations CA Combinations GL-10-06),L850-GL-12, L850-GL-20 Inter-band 2CA 1+3, 5, 8, 11, 18, 19, 20, 21, 26 2+4, 5, 12, 13, 17, 29, 30, 66 3+5, 7, 8, 19, 20, 28 4+5, 12, 13, 17, 29, 30 5+7, 30, 66 7+20, 28 8+11 12+30 13+66 29+30 Intra-band (non-contiguous) 2, 3, 4, 7, 41 Intra-band (contiguous) 2, 3, 7, 40, 41 Inter-band 1+3+7, 1+3+81+3+19, 1+3+20, 1+3+28, 1+7+20, 1+7+28, 1+8+11, 1+19+21 2+4+5, 2+4+13, 2+5+30, 2+12+30, 2+29+30, 2+5+66, 2+13+66 3+7+20, 3+7+28 4+5+30, 4+12+30, 4+29+30 3CA 2 intra-band (non-contiguous) 2+2+5, 2+2+13 plus inter-band 4+4+5, 4+4+13 2 intra-band (contiguous) 3+3+1, 3+3+5, 3+3+7, 3+3+20, 3+3+28 plus inter-band 2+66+66, 5+66+66, 13+66+66 2+2+29 7+7+3, 7+7+28 Intra-band (non-contiguous) 41, 66 Intra-band (contiguous) 40, 41, 66 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 12 of 59 CA Combinations L850-GL-10-06 Inter-band 2CA 2+4, 5, 13 4+5, 13 Intra-band (non-contiguous) 2, 4 Intra-band (contiguous) 2 Inter-band 2+4+5, 2+4+13 3CA 2 intra-band (non-contiguous) 2+2+5, 2+2+13 plus inter-band 4+4+5, 4+4+13 2.4 Application Framework The peripheral applications for L850 module are shown in Figure 2-1:
Main ANT Div ANT Module Power Supply ON/OFF# RESET#
SIM PCIe USB2.0 USB3.1 EINT Indicator Control SIM Card Figure2-1 Application framework Host application Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 13 of 59 2.5 Hardware Block Diagram The hardware block diagram in Figure 2-2 shows the main hardware functions of L850 module, including baseband and RF functions. Baseband contains the followings:
UMTS/LTE TDD/LTE FDD controller PMU NAND/internal LPDDR2 RAM Application interface RF contains the followings:
RF Transceiver RF Power/PA RF Front end RF Filter Antenna Connector FULL_CARD_POWER_OFF#
PMU NAND
+3.3V RESET#
PCIe USB2.0 USB 3.0 USIM EINT WOWWAN#
LED I2S I2C CLOCK Tunable ANT e c a f r e t n i i n p 5 7 B
y e K 2 M
. Baseband TCXO
(UMTS/LTE TDD/LTE FDD controller) RF Transceiver 2nd LPDDR2 RAM Main RX TX Div RX RF Part Duplexer Main LB FEMiD Main MB FEMiD SAW PA r e x e p D i l r e x e p D i l Div LB FEM Div MB FEM GNSS/
Beidou RF Transceiver 1st TX PA DCDC Main RX Div RX SAW Figure 2-2 Hardware block diagram Main ANT Div ANT Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 14 of 59 3 Application Interface 3.1 M.2 Interface The L850 module applies standard M.2 Key-B interface, with a total of 75 pins. 3.1.1 Pin Map Figure 3-1 Pin map Note:
Pin Notch represents the gap of the gold fingers. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 15 of 59 3.1.2 Pin Definition The pin definition is as follows:
Pin Pin Name I/O Reset Value Pin Description Type 1 CONFIG_3 O NC the WWAN PCIe, USB3.1 interface
NC, L850 M.2 module is configured as PI
PI
I
PU FULL_CARD_ POWER_OFF#
USB D+
I/O
Power input Power input type GND GND internal pull up USB data plus Power enable, module power on input, 8 W_DISABLE1#
I PD WWAN disable, active low 9 USB D-
I/O
USB data minus 10 LED1#
O T System status LED, output open drain,
Power Supply 3.3V GND Notch Notch Notch Notch Notch Notch Notch Notch
+3.3V GND
+3.3V GND 2 3 4 5 6 7 11 GND 12 Notch 13 Notch 14 Notch 15 Notch 16 Notch 17 Notch 18 Notch 19 Notch
I 20 I2S_CLK O PD I2S serial clock, Reserved 21 CONFIG_0 GND the WWAN PCIe, USB3.1 interface
GND, L850 M.2 module is configured as 22 I2S_RX PD type I2S serial receive data, Reserved Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 16 of 59 Power Supply Power Supply Power Supply Power Supply 3.3/1.8V 0.3---3V 3.3/1.8V 0.3---3V 3.3V 1.8V 1.8V 34 UIM_DATA I/O L SIM data input/output 1.8V/3V I I
O O O O
I O I
I PU PU
L
L
26 W_DISABLE2#
27 GND 29 USB3.0_TX-
30 UIM_RESET 31 USB3.0_TX+
32 UIM_CLK 33 GND 35 USB3.0_RX-
36 UIM_PWR 37 USB3.0_RX+
38 NC 39 GND Pin Pin Name I/O Reset Value Pin Description 23 WOWWAN#
O PD 24 I2S_TX O PD 25 DPR BodySAR detect, active low 3.3/1.8V 28 I2S_WA O PD I2S word alignment/select, Wake up host, Reserved I2S serial transmit data, Reserved GNSS disable, active low, Reserved GND Reserved 3.3/1.8V Power Supply 1.8V USB3.0 transmit data minus SIM reset signal 1.8V/3V USB3.0 transmit data plus SIM clock signal GND 1.8V/3V Power Supply USB3.0 receive data minus SIM power supply, 3V/1.8V 1.8V/3V USB3.0 receive data plus Power Supply 40 GNSS_SCL PU I2C serial clock input, 41 PETn0 O
PCIe TX differential signal 42 GNSS_SDA I/O PU I2C serial data input/output, 43 PETp0 O
PCIe TX differential signal 44 GNSS_IRQ O PD GNSS interrupt request output, NC GND Reserved Negative Reserved Positive Reserved GND 45 GND
Power Supply Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 17 of 59 Type 1.8V 1.8V
1.8V 1.8V 1.8V Pin Pin Name I/O Reset Value Pin Description 46 SYSCLK O PD 26M clock output 47 PERn0 I
48 TX_BLANKING O PD 49 PERp0 I
PCIe RX differential signal Negative PA blanking timer, Reserved PCIe RX differential signal Positive Type 1.8V 1.8V
50 PERST#
I PU it will reset whole module, not only PCIe 3.3V 51 GND
GND Power Supply 52 CLKREQ#
I/O PU also used by L1 PM Sub states 3.3V Asserted to reset module PCIe interface default. If module went into core dump, interface. Active low, internal pull up(10K) Asserted by device to request a PCIe reference clock be available (active clock state) in order to transmit data. It mechanism, asserted by either host or device to initiate an L1 exit. Active low, internal pull up(10K) PCIe reference clock signal, Negative
Asserted to wake up system and reactivate PCIe link from L2 to L0, it depends on system Active low, open drain output and should add external pull up(100K) on PCIe reference clock signal, MIPI interface tunable ANT, platform Positive RFFE clock GND RFFE data MIPI interface tunable ANT,
1.8V 1.8V Power Supply 53 REFCLKN I
55 REFCLKP 56 RFFE_SCLK O 57 GND 58 RFFE_SDATA O I
54 PEWAKE#
O L whether supports wake up functionality. 3.3V Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 18 of 59 Pin Pin Name I/O Reset Value Pin Description 59 ANTCTL0 O
Tunable ANT CTRL0, bit0 60 COEX3 I/O PD 61 ANTCTL1 O
Tunable ANT CTRL1, bit1 1.8V 62 COEX_RXD I T coexistence protocol. UART receive 1.8V 63 ANTCTL2 O
Tunable ANT CTRL2, bit2 1.8V Wireless coexistence between WWAN and WiFi/BT modules, based on BT-SIG coexistence protocol. COEX_EXT_FTA, Reserved Wireless coexistence between WWAN and WiFi/BT modules, based on BT-SIG signal(WWAN module side) Reserved Wireless coexistence between WWAN and WiFi/BT modules, based on BT-SIG coexistence protocol. UART transmit signal(WWAN module side), Reserved SIM detect, internal pull up(390K), active high WWAN reset input, internal pull up(10K), active low Type 1.8V 1.8V 1.8V 1.8V 1.8V
64 COEX_TXD O T 65 NC NC 66 SIM_DETECT PD
I I
PI
PI
PI
67 RESET#
68 NC 70
+3.3V 71 GND 72
+3.3V 73 GND 74
+3.3V NC type GND GND type Power input Power input Power input 69 CONFIG_1 O GND the WWAN PCIe, USB3.1 interface GND, L850 M.2 module is configured as 75 CONFIG_2 O GND the WWAN PCIe, USB3.1 interface
GND, L850 M.2 module is configured as Power Supply Power Supply Power Supply Power Supply Power Supply Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 19 of 59 Reset Value: The initial status after module reset, not the status when working. H: High Voltage Level L: Low Voltage Level PD: Pull-Down PU: Pull-Up T: Tristate OD: Open Drain PP: Push-Pull PI: Power Input PO: Power Output Note:
Digital IO pins CANNOT be connected to power directly. The unused pins can be left floating. All 3.3V ports are based on +3.3V power domain. When the power supply range is 3.135V~4.4V, the 3.3V ports voltage will follow the change of power supply range. 3.2 Power Supply The power interface of L850 module is shown in the following table:
Pin Pin Name I/O Pin Description Minimum Typical Maximum 2, 4, 70, 72, 74 +3.3V PI Power supply input 36 UIM_PWR PO USIM power supply L850 module uses PCIe interface. According to the PCIe specification, the PCIe Vmain should be used as the +3.3V power source, not the Vaux. The Vaux is the PCIe backup power source and it is not sufficient as the power supply. In addition, the DC/DC power supply other than PCIe ports should not be used as the external power cannot control the module status through the PCIe protocol. DC Parameter (V) Value 3.135
Value Value 3.3 4.4 1.8V/3V
3.2.1 Power Supply Figure 3-2:
The L850 module should be powered through the +3.3V pins, and the power supply design is shown in Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 20 of 59 Figure 3-2 Power supply design The filter capacitor design for power supply is shown in the following table:
Recommended Capacitance Application Description 220uF2 Voltage-stabilizing LDO or DC/DC power supply requires the capacitors capacitor of no less than 440uF Reduce power fluctuations of the module in operation, requiring capacitors with low ESR. The capacitor for battery power supply can be reduced to 100~200uF and digital signals Filter out the interference generated from the clock Filter out low frequency band RF interference 1uF, 100nF Digital signal noise 700/800, 850/900 MHz frequency band 1500/1700/1800/1900, 39pF, 33pF 18pF, 8.2pF, 6.8pF 2100/2300, 2500/2600MHz frequency band interference Filter out medium/high frequency band RF The stable power supply can ensure the normal operation of L850 module; and the ripple of the power supply should be less than 300mV in design. When the module operates with the maximum emission power, the maximum operating current can reach 1.5A, so the power source should be not lower than 3.135V, or the module may shut down or reboot. The power supply limits are shown in Figure 3-3:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 21 of 59 Burst transmit Burst transmit Ripple300mV Drop VBAT3.135V Power supply min:3.135V 1.8V logic level VIH VIL VIH VIL 3.3V logic level Figure 3-3 Power supply limit 3.2.2 Logic Level The L850 module 1.8V logic level definition is shown in the following table:
Parameter Minimum Typical Maximum Unit The L850 module 3.3V logic level definition is shown in the following table:
Parameter Minimum Typical Maximum Unit 1.71 1.3
-0.3 3.135 2.3
-0.3 1.8 1.8 0 3.3 3.3 0 1.89 1.89 0.3 3.465 3.465 0.3 V V V V V V 3.2.3 Power Consumption In the condition of 3.3V power supply, the L850 power consumption is shown in the following table:
Parameter Mode Condition Ioff Power off Power supply, module power off DRX=6 WCDMA DRX=8 ISleep DRX=9 LTE FDD Paging cycle #128 frames (1.28s DRx cycle) LTE TDD Paging cycle #128 frames (1.28s DRx cycle) Average Current (mA) 0.05 3.4 2.8 2.4 3.5 3.8 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 22 of 59 Parameter Mode Condition Radio Off AT+CFUN=4, Flight mode WCDMA Data call Band 1 @+23.5dBm WCDMA Data call Band 2 @+23.5dBm IWCDMA-RMS WCDMA WCDMA Data call Band 4 @+23.5dBm Average Current (mA) WCDMA Data call Band 5 @+23.5dBm WCDMA Data call Band 8 @+23.5dBm LTE FDD Data call Band 1 @+23dBm LTE FDD Data call Band 2 @+23dBm LTE FDD Data call Band 3 @+23dBm LTE FDD Data call Band 4 @+23dBm LTE FDD Data call Band 5 @+23dBm LTE FDD Data call Band 7 @+23dBm LTE FDD Data call Band 8 @+23dBm LTE FDD Data call Band 11 @+23dBm LTE FDD Data call Band 12 @+23dBm LTE FDD Data call Band 17 @+23dBm LTE FDD Data call Band 18 @+23dBm LTE FDD Data call Band 19 @+23dBm LTE FDD Data call Band 20 @+23dBm LTE FDD Data call Band 21 @+23dBm LTE FDD Data call Band 26 @+23dBm LTE FDD Data call Band 28 @+23dBm LTE FDD Data call Band 30 @+23dBm LTE FDD Data call Band 66 @+23dBm LTE FDD LTE FDD Data call Band 13 @+23dBm ILTE-RMS 1.8 580 650 550 500 520 700 770 740 760 560 880 570 840 640 660 650 600 550 620 870 570 580 800 700 430 LTE TDD LTE TDD Data call Band 38 @+23dBm Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 23 of 59 Parameter Mode Condition LTE TDD Data call Band 39 @+23dBm LTE TDD Data call Band 40 @+23dBm LTE TDD Data call Band 41 @+23dBm Average Current (mA) 340 380 430 In 3CA mode, the L850 power consumption is shown in the following table:
3CA Combination Condition Average
(Maximum Data Transfer) Current (mA) 1+3+7, 1+3+81+3+19, 1+3+20, Band 4 @+22dBm 1+3+28, 1+7+20, 1+7+28, 1+8+11, 2+4+5, 2+4+13, 2+5+30, 2+12+30, 1+19+21 2+29+30 3+7+20, 3+7+28 4+5+30, 4+12+30, 4+29+30 5+66+2, 13+66+2 2+2+5, 2+2+13, 2+2+29 3+3+7, 3+7+7, 3+3+20 4+4+5, 4+4+13 5+66+66, 13+66+66, 66+66+2, 66+66+66 7+7+28, 3+3+28, 3+3+5, 1+3+3 40+40+40, 41+41+41 Band 1 @+22dBm Band 2 @+22dBm Band 3 @+22dBm Band 5 @+22dBm Band 7 @+22dBm Band 8 @+22dBm Band 11 @+22dBm Band 12 @+22dBm Band 13 @+22dBm Band 19 @+22dBm Band 20 @+22dBm Band 21 @+22dBm Band 28 @+22dBm Band 30 @+22dBm Band 40 @+22dBm Band 41 @+22dBm Band 66 @+22dBm 720 820 870 820 750 1060 650 1040 760 760 750 720 950 670 1160 460 520 740 Note The data above is an average value tested on some samples at 25C temperature. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 24 of 59 3.3 Control Signal the following table:
The L850 module provides two control signals for power on/off and reset operations. The pin is defined in Pin Pin Name I/O Reset Value Functions Type 6 FULL_CARD_POWER_OFF# I PU 3.3/1.8V 67 RESET#
I
Module power on/off input, internal pull up Power on: High/Floating Power off: Low WWAN reset input, internal pull up(10K), active low 1.8V Asserted to reset module PCIe interface default. If module went module, not only PCIe interface. Active low, internal pull up(10K) 50 PERST#
I PU into core dump, it will reset whole 3.3V Note RESET# and PERST# need to be controlled by independent GPIO, and not shared with other devices on the host. RESET# and PERST# are sensitive signals, so they should keep away from RF interference and be protected by GND. It should be neither near PCB edge nor route on surface layer to avoid module abnormal reset caused by ESD. 3.3.1 Module Start-Up 3.3.1.1 Start-up Circuit The FCPO# (FULL_CARD_POWER_OFF#) pin needs an external 3.3V or 1.8V pull up for booting up. AP
(Application Processor) controls module start-up. The recommended design is using a default PD port to control FCPO#. It also should reserve a 100K pull down resistor on AP side. The reference design is shown in Figure3-4:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 25 of 59 Figure 3-4 Circuit for module start-up controlled by AP 3.3.1.2 Start-up Timing Sequence When power supply is ready, the PMU of module will power on and start initialization process by pulling high FCPO# signal. After about 10s, module will complete initialization process. The start-up timing is shown in Figure 3-5:
ton1 ton2 typical 10s tpr
+3.3V FCPO#
RESET#
PERST#
Note Module State OFF Initialization Activation(AT Command Ready) Figure 3-5 Timing control for start-up Index Min. Recommended Max. Comments tpr 0ms
The delay time of power supply rising from 0V up to 3.135V. If power supply always ready, it can be ignored ton1 8ms 20ms RESET# should be de-asserted after FCPO#
ton2 50ms 100ms The time delay of PERST# de-asserted after FCPO#, PERST# must always be the last to get de-asserted The minimum detection time of PCIe link is about 45ms after PERST# de-asserted. When USB is used as data transfer interface, follow timing above in PERST# connecting with host, otherwise dont control PERST# in PERST# floating condition. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 26 of 59 3.3.2 Module Shutdown The module can be shut down by the following controls:
Shutdown Control Action Condition Software Sending AT+CFUN=0 command Normal shutdown(recommend) Hardware Pull down FCPO# pin occurs and the software control cannot be Only used when a hardware exception used. The module can be shut down by sending AT+CFUN=0 command. When the module receives the software shutdown command, the module will start the finalization process (the reverse process of initialization), and it will be completed after tsd time (tsd is the time which AP receive OK of AT+CFUN=0, if there is no response, the max tsd is 5s). In the finalization process, the module will save the network, SIM card and some other parameters from memory, and then clear the memory and shut down PMU. The control timing is shown in Figure 3-6:
+3.3V FCPO#
RESET#
PERST#
tpd toff2 toff1 AT+CFUN=0 tsd Module State Activation Finalization OFF Figure 3-6 Shutdown timing control Index Min. Recommended Max. Comments toff1 toff2 16ms 20ms 2ms 10ms tpd 10ms 100ms Note
RESET# should be asserted after PERST#
FCPO# should be asserted after RESET#
+3.3V power supply goes down time. If power supply is always on, it can be ignored When USB is used as data transfer interface, follow timing above in PERST# connecting with host, otherwise dont control PERST# in PERST# floating condition. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 27 of 59 3.3.3 Module Reset The L850 module can reset to its initial status by pulling down the RESET# signal for more than 2ms (10ms is recommended), and module will restart after RESET# signal is released. When customer executes RESET# function, the PMU remains its power inside the module. The recommended circuit design is shown in the Figure 3-7:
Figure 3-7 Recommended design for reset circuit There are two reset control timings as below:
Reset timing 1st in Figure 3-8, PMU of module internal always on in reset sequence, recommend using in FW upgrade and module recovery;
Reset timing 2nd in Figure 3-9, PMU of module internal will be off in reset sequence (including whole power off and power on sequence, tsd can refer section 3.3.2), recommend using in system warm boot.
+3.3V FCPO#
RESET#
PERST#
Module State Activation Baseband reset Initialization Activation toff2 typical 10s Figure 3-8 Reset timing 1st Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 28 of 59 AT+CFUN=0
+3.3V FCPO#
RESET#
PERST#
toff toff2 toff1 ton1 ton2 tsd typical 10s Module State Activation Finalization OFF Initialization Activation Index Min. Recommended Max. Comments Figure 3-9 Reset timing 2nd RESET# should be asserted after PERST#, refer section 3.3.2 FCPO# should be asserted after RESET#, refer section 3.3.2 Time to allow the WWAN module to fully discharge any residual voltages before the pin could be de-asserted again. This is required for both Pre-OS as well as Runtime flow RESET# should be de-asserted after FCPO#, refer section 3.3.1.2 The time delay of PERST# de-asserted after FCPO#, toff1 16ms 20ms toff2 2ms 10ms toff 500ms 500ms ton1 8ms 20ms Note
ton2 50ms 100ms PERST# must always be the last to get de-asserted. refer section 3.3.1.2 When USB is used as data transfer interface, follow timing above in PERST# connecting with host, otherwise dont control PERST# in PERST# floating condition. 3.3.4 PCIe Link State Modem has the lowest power consumption in D0 L1.2 PCIe link state. D3cold L2 will increase extra about 0.5mA power consumption. CLKREQ# can assert or de-assert in D3cold L2, but CLKREQ# shouldnt be changed again during D3cold L2. When CLKREQ# asserts in D3cold L2, it will increase extra 0.3mA power consumption compared with CLKREQ# de-asserted in D3cold L2. We recommend keep CLKREQ# de-
asserted in D3cold L2. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 29 of 59 H L L H H L D0 L1.2 D3cold L2 3.3.4.1 D0 L1.2 PCIe Link State PERST# CLKREQ#
Description Power Consumption
(mA) Isleep Isleep+0.5 Isleep+0.8 Refer 3.2.3 Power Consumption The extra 0.5mA is consumed on PERST# pull down The extra 0.3mA is consumed on CLKREQ# pull down Module supports PCIe goes into D0 L1.2 state in Win10 system. The D0 L0@S0/S0ix D0 L1.2@S0/S0ixD0 L0@S0/S0ix timing is shown in figure 3-10:
+3.3V FCPO#
RESET#
PERST#
CLKREQ#
Note Module State D0 L0@S0/S0ix D0 L1.2@S0/S0ix D0 L0@S0/S0ix Figure 3-10 D0 L1.2 timi When USB is used as data transfer interface in Chrome/Android/Linux OS, there is no PCIe link state. But when USB goes into suspend it also needs to follow the timing above (If PERST# and CLKREQ# are floating, dont control PERST# and CLKREQ#). 3.3.4.2 D3cold L2 Module supports PCIe goes into D3cold L2 state in Win10 system. In D3cold L2 state, PCIe link can be woken up by both modem and host. The D0 L0@S0/S0ixD3cold L2@S0/S0ixD0 L0@S0/S0ix timing is shown in Figure 3-11 and Figure 3-12:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 30 of 59
+3.3V FCPO#
RESET#
PERST#
CLKREQ#
PEWAKE#
+3.3V FCPO#
RESET#
CLKREQ#
PEWAKE#
Note Host assert Host de-assert Module State D0 L0@S0/S0ix D3cold L2@S0/S0ix D0 L0@S0/S0ix Figure 3-11 D3cold L2 timing (Host wakeup) PERST#
Host assert Host de-assert Module State D0 L0@S0/S0ix D3cold L2@S0/S0ix D0 L0@S0/S0ix Modem assert Modem de-assert Figure 3-12 D3cold L2 timing (Modem wakeup) When USB is used as data transfer interface in Chrome/Android/Linux OS, there is no PCIe link state, so dont need to follow timing above. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 31 of 59 3.3.5 Timing Application The recommended timing application in Win10 OS is as below table:
System status Timing Application S0ix
(Modem standby) S3, S4, S5 Power on
(back to S0) Power off
(out of S0) D0 L1.2 Refer to section 3.3.4.1 Figure 3-10 D0 L1.2 Timing D3cold L2 Refer to section 3.3.4.2 Figure 3-11/3-12 D3cold L2 timing Refer to section 3.3.1.2 Figure 3-5 Timing control for start-up Refer to section 3.3.2 Figure 3-6 Software power off timing G3 boot Power on Refer to section 3.3.1.2 Figure 3-5 Timing control for start-up Warm boot Refer to section 3.3.3 Figure 3-9 Reset timing 2nd Modem FW upgrade / Modem recovery Refer to section 3.3.3 Figure 3-8 Reset timing 1st Intel X86 platforms must follow the table above. AMD X86 platforms should follow the table above and meet the special request of platform itself. The recommended timing application in Chrome/Android/Linux OS is as below table:
System status Timing Application Power on Shut down Connect standby Restart Modem FW upgrade / Modem recovery 3.4 IPC Interface Refer to section 3.3.1.2 Figure 3-5 Timing control for start-up Refer to section 3.3.2 Figure 3-6 Software power off timing Refer to section 3.3.4.1 Figure 3-10 D0 L1.2 Timing Refer to section 3.3.3 Figure 3-9 Reset timing 2nd Refer to section 3.3.3 Figure 3-8 Reset timing 1st L850 module supports PCIe and USB interface for data request. PCIe & USB interface functions are as below table:
Interface System Priority Description PCIe Win10 High USB Chrome OS
/Android/Linux Low Priority: PCIe>USB If PCIe and USB ports both connected with PC, module will initial PCIe first, then disable USB port It must disconnect PCIe port, only keep USB connecting. If keep PCIe and USB connecting both, it needs disable PCIe by BIOS/UEFI of PC Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 32 of 59 3.4.1 PCIe Interface L850 module supports PCIe Gen1 interface and one data transmission channel. BIOS configuration must follow X86 platform BKC (Best Know Configuration) reference design. PCIe interface is initialized with host driver, and then mapped MBIM & GNSS port in Win10 OS. The MBIM interface is used for data transfer and GNSS port is used for receiving GNSS data. 3.4.1.1 PCIe Interface Definition Pin# Pin Name I/O Reset Value Description Type 41 PETn0 O
PCIe TX differential signal 43 PETP0 O
PCIe TX differential signal 47 PERn0 49 PERP0 I I
PCIe RX differential signal PCIe RX differential signal 53 REFCLKN I
PCIe reference clock signal 55 REFCLKP I
PCIe reference clock signal Negative Positive Negative Positive Negative Positive
50 PERST#
I PU 52 CLKREQ#
I/O PU Asserted to reset module PCIe interface default. If module went into coredump, it will reset whole module, not only PCIe interface. 3.3V Active low, internal pull up(10K) Asserted by device to request a PCIe reference clock be available (active clock state) in order to transmit data. It also used by L1 PM Sub states mechanism, asserted by either host or device to initiate an L1 exit. 3.3V Active low, internal pull up(10K) Asserted to wake up system and reactivate PCIe link from L2 to L0, it depends on system Active low, open drain output and should add external pull up (100K) on platform 54 PEWAKE# O L whether supports wake up functionality. 3.3V Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 33 of 59 3.4.1.2 PCIe Interface Application The reference circuit is shown in Figure 3-13:
AP side PERn0 PERP0 PETn0 PETP0 REFCLKN REFCLKP PERST#
CLKREQ#
WAKE#
AC Caps
+3.3V/1.8V 100K 10K i n p 5 7 B
y e K 2 M
. r o t c e n n o C Module side AC Caps PETn0(pin41) PETP0(pin43) PERn0(pin47) PERP0(pin49) REFCLKN(pin53) REFCLKP(pin55) PERST#(pin50) CLKREQ#(pin52) PEWAKE#(pin54) PCB Layout:
for AP end;
Figure 3-13 Reference circuit for PCIe interface L850 module supports PCIe Gen1 interface, one lane. The PCIe interface including three differential pairs:
transmit pair TXP/N, receiving pair RXP/N and clock pair CLKP/N. PCIe can achieve the maximum transmission rate of 2.5 GT/s, and must strictly follow the rules below in The differential signal pair lines should be parallel and equal in length;
The differential signal pair lines should be short if possible and be controlled within 15 inch (380 mm) The impedance of differential signal pair lines is recommended to be 100, and can be controlled to 80~120 in accordance with PCIe protocol;
Try to avoid the discontinuous reference ground, such as segment and space;
When the differential signal lines go through different layers, the via hole of grounding signal should be in close to that of signal, and generally, each pair of signals require 1-3 grounding signal via holes and the lines should never cross the segment of plane;
Try to avoid bended lines and avoid introducing common-mode noise in the system, which will influence the signal integrity and EMI of difference pair. As shown in Figure 3-14, the bending angle of all lines should be equal or greater than 135, the spacing between difference pair lines should be larger than 20mil, and the line caused by bending should be greater than 1.5 times line width at least. When a serpentine line is used for length match with another line, the bended length of each segment Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 34 of 59 should be at least 3 times the line width ( 3W). The largest spacing between the bended part of the serpentine line and another one of the differential lines must be less than 2 times the spacing of normal differential lines (S1 < 2S);
1.5W 5 3 1 PCIe Difference Pair 1 S S1<2S 3W W 20mil PCIe Difference Pair 2 Figure 3-14 Requirement of PCIe line The difference in length of two data lines in difference pair should be within 5mil, and the length match is required for all parts. When the length match is conducted for the differential lines, the designed position of correct match should be close to that of incorrect match, as shown in Figure 3-
15. However, there is no specific requirements for the length match of transmit pair and receiving pair, which means the length match is only required by intra differential pair rather than inter differential pair. Correct match Dismatched end Matched end Incorrect match Figure 3-15 Length match design of PCIe difference pair 3.4.2 USB Interface The L850 module supports USB2.0 which is compatible with USB High-Speed (480 Mbps) and USB Full-
Speed (12 Mbps). It supports USB3.1 Gen1 using for LTE cat9 high speed data throughput at the same time. For the USB timing and electrical specification of L850 module, please refer to Universal Serial Bus Specification 2.0 and Universal Serial Bus Specification 3.0. USB interface initialized with host driver, and then mapped NCM and ACM ports in Chrome/Linux/Android OS. The NCM ports are used for data transfer. The ACM port is used for AT command. The port can be Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 35 of 59 configured in practical application. 3.4.2.1 USB Interface Definition Pin#
Pin Name I/O Description USB_D+
I/O USB data plus 7 9 29 31 35 37 USB_D-
I/O USB data minus USB3.0_TX-
USB3.0_TX+
USB3.0_RX-
USB3.0_RX+
O O I I USB3.0 transmit data minus USB3.0 transmit data plus USB3.0 receive data minus USB3.0 receive data plus 3.4.2.2 USB2.0 Interface Application The reference circuit is shown in Figure 3-16:
Type 0.3---3V, USB2.0 0.3---3V, USB2.0
Figure 3-16 Reference circuit for USB 2.0 interface USB_D- and USB_D+ are high speed differential signal lines with the maximum transfer rate of 480 Mbps, so the following rules should be followed carefully in the case of PCB layout:
USB_D- and USB_D+ signal lines should have the differential impedance of 90. USB_D- and USB_D+ signal lines should be parallel and have the equal length. The right angle routing should be avoided. USB_D- and USB_D+ signal lines should be routed on the layer that is adjacent to the ground layer, and wrapped with GND vertically and horizontally. 3.4.2.3 USB3.0 Interface Application The reference circuit is shown in Figure 3-17:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 36 of 59 Figure 3-17 Reference circuit for USB3.0 interface USB3.0 signals are super speed differential signal lines with the maximum transfer rate of 5 Gbps. So the following rules should be followed carefully in the case of PCB layout:
USB3.0_TX-/USB3.0_TX+ and USB3.0_RX-/ USB3.0_RX+ are two pairs differential signal lines. The differential impedance should be controlled as 90. The two pairs differential signal lines should be parallel and have the equal length. The right angle The two pairs differential signal lines should be routed on the layer that is adjacent to the ground layer, routing should be avoided. and wrapped with GND vertically and horizontally. 3.5 USIM Interface The L850 module has a built-in USIM card interface, which supports 1.8V and 3V SIM cards. 3.5.1 USIM Pins The USIM pins description is shown in the following table:
Pin Pin Name I/O Reset Value Description 36 UIM_PWR 30 UIM_RESET 32 UIM_CLK 34 UIM_DATA PO O O
L L I/O L USIM power supply USIM reset USIM clock Type 1.8V/3V 1.8V/3V 1.8V/3V 66 SIM_DETECT I PD Active high, and high level indicates 1.8V USIM data, internal pull up(4.7K) 1.8V/3V USIM card detect, internal 390K pull-
up. SIM card is inserted; and low level indicates SIM card is detached. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 37 of 59 3.5.2 USIM Interface Circuit 3.5.2.1 N.C. SIM Card Slot The reference circuit design for N.C. (Normally Closed) SIM card slot is shown in Figure 3-18:
The principles of the N.C.SIM card slot are described as follows:
Figure 3-18 Reference circuit for N.C. SIM card slot When the SIM card is detached, it connects the short circuit between CD and SW pins, and drives When the SIM card is inserted, it connects an open circuit between CD and SW pins, and drives the the SIM_DETECT pin low. SIM_DETECT pin high. 3.5.2.2 N.O. SIM Card Slot The reference circuit design for N.O. (Normally Open) SIM card slot is shown in Figure 3-19:
The principles of the N.O.SIM card slot are described as follows:
Figure 3-19 Reference circuit for N.O. SIM card slot When the SIM card is detached, it connects an open circuit between CD and SW pins, and drives the SIM_DETECT pin low. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 38 of 59 When the SIM card is inserted, it connects the short circuit between CD and SW pins, and drives the SIM_DETECT pin high. 3.5.3 USIM Hot-Plug The L850 module supports the SIM card hot-plug function, which determines whether the SIM card is inserted or detached by detecting the SIM_DETECT pin state of the SIM card slot. The SIM card hot-plug function can be configured by AT+MSMPD command, and the description for AT command is shown in the following table:
AT Command Hot-plug Detection Function Description AT+MSMPD=1 Enable enabled. Default value, the SIM card hot-plug detection function is The module can detect whether the SIM card is inserted or not through the SIM_DETECT pin state. The SIM card hot-plug detect function is disabled. AT+MSMPD=0 Disable The module reads the SIM card when starting up, and the SIM_DETECT status will not be detected. After the SIM card hot-plug detection function is enabled, the module detects that the SIM card is inserted when the SIM_DETECT pin is high, then executes the initialization program and finish the network registration after reading the SIM card information. When the SIM_DETECT pin is low, the module determines that the SIM card is detached and does not read the SIM card. SIM_DETECT is active high. It can be swapped to active low by AT CMD. Note:
3.5.4 USIM Design should be noted in design:
The SIM card circuit design should meet the EMC standards and ESD requirements with the improved capability to resist interference, to ensure that the SIM card can work stably. The following guidelines The SIM card slot should be placed as close as possible to the module, and away from the RF antenna, DC/DC power supply, clock signal lines, and other strong interference sources. The SIM card slot with a metal shielding housing can improve the anti-interference ability. The trace length between the SIM card slot and the module should not exceed 100mm, or it could reduce the signal quality. The UIM_CLK and UIM_DATA signal lines should be isolated by GND to avoid crosstalk interference. If it is difficult for the layout, the whole SIM signal lines should be wrapped with GND as a group at Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 39 of 59 least. 3.6 Status Indicator The filter capacitors and ESD devices for SIM card signals should be placed near to the SIM card slot, and the ESD devices with 22~33pF capacitance should be used. The L850 module provides three signals to indicate the operating status of the module, and the status indicator pins is shown in the following table:
Pin Pin Name I/O Reset Value Pin Description 10 LED1#
23 WOWWAN#
O O PD PD System status LED, drain output. Module wakes up Host (AP)Reserved 1.8V 48 TX_BLANKING O PD PA blanking output, external GPS control signalReserved Type 3.3V 1.8V The LED#1 signal is used to indicate the operating status of the module, and the detailed description is 3.6.1 LED#1 Signal shown in the following table:
Module Status LED1# Signal RF function ON Low level (LED On) RF function OFF High level (LED Off) The LED driving circuit is shown in Figure 3-20:
Figure 3-20 LED driving circuit The resistance of LED current-limiting resistor is selected according to the driving voltage and the Note:
driving current. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 40 of 59 3.7 Interrupt Control 8 W_DISABLE1#
25 DPR 26 W_DISABLE2#
I I I PD PU PU 3.7.1 W_DISABLE1#
The L850 module provides three interrupt signals, and the pin definition is as follows:
Pin Pin Name I/O Reset Value Pin Description Enable/Disable RF network BodySAR detection GNSS disable signal, Reserved Type 3.3/1.8V 3.3/1.8V 3.3/1.8V The module provides a hardware pin to enable/disable WWAN RF function, and the function can also be controlled by the AT command. The module enters into flight mode after the RF function is disabled. The definition of W_DISABLE1# signal is as follows:
W_DISABLE1# signal Function High/Floating WWAN function is enabled, the module exits the flight mode. Low WWAN function is disabled, the module enters into flight mode. The function of W_DISABLE1# is enabled by default. It can be disabled by customers request. Note 3.7.2 BODYSAR The L850 module supports BodySAR function by detecting the DPR pin. The voltage level of DPR is high by default, and when the SAR sensor detects the closing human body, the DPR signal will be pulled down. As the result, the module then lowers down its emission power to its default threshold value, thus reducing the RF radiation on the human body. The threshold of emission power can be set by the AT Commands. The definition of DPR signal is shown in the following table:
DPR signal Function High/Floating The module keeps the default emission power Low Lower the maximum emission power to the threshold value of the module. 3.8 Clock Interface The L850 module supports a clock interface. It can output 26MHz clock. Pin Pin Name I/O Reset Value Pin Description 46 SYSCLK O
26M clock output used for external audio codec and GNSS, etc., default disabled Type 1.8V Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 41 of 59 3.9 ANT Tunable Interface The module supports ANT Tunable interfaces with two different control modes, i.e. MIPI interface and 3bit GPO interface. Through cooperating with external antenna adapter switch via ANT Tunable, it can flexibly configure the bands of LTE antenna to improve the antennas working efficiency and save space for the antenna. Pin Pin Name I/O Pin Description Type 56 RFFE_SCLK O Tunable ANT control, MIPI Interface, 58 RFFE_SDATA O Tunable ANT control, MIPI Interface, RFFE clock RFFE data 1.8V 1.8V 1.8V 1.8V 1.8V Tunable ANT control, GPO interface, Tunable ANT control, GPO interface, Tunable ANT control, GPO interface, O O O bit0 bit1 bit2 59 ANTCTL0 61 ANTCTL1 63 ANTCTL2 Note The MIPI signal is limited to unidirectional function only. 3.10 Configuration Interface The L850 module provides four pins to define WWAN-PCIe, USB3.1 type M.2 module:
Pin Pin Name I/O Reset Value Pin Description Type 1 CONFIG_3 21 CONFIG_0 69 CONFIG_1 75 CONFIG_2 O O O O
L L L NC Internally connected to GND Internally connected to GND Internally connected to GND
The M.2 module configuration is shown in the following table:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 42 of 59 Config_0 Config_1 Config_2 Config_3 Module Type and Main Port
(pin21)
(pin69)
(pin75)
(pin1) Host Interface Configuration GND GND GND NC 0 WWANUSB3.1 Gen1, PCIe Gen1 Please refer to PCI Express M.2 Specification Rev1.2 for more details. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 43 of 59 4 Radio Frequency 4.1 RF Interface 4.1.1 RF Interface Functionality The L850 module supports two RF connectors used for external antenna connection. As the Figure 4-1 shows, M is for Main antenna, which is used to receive and transmit RF signal; D/G is for Diversity antenna, which is used to receive the diversity RF and GNSS signals. Figure 4-1 RF connectors 4.1.2 RF Connector Characteristic Rated Condition Environment Condition Frequency Range DC~6GHz Characteristic Impedance 50 Temperature Range: 40C~+85C 4.1.3 RF Connector Dimension L850 module uses standard M.2 RF connectors. The RF connector part number is 818004607 manufactured by ECT Corporation, and the size is 220.6mm. The connector dimension is shown as following picture:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 44 of 59 Figure 4-2 RF connector dimensions Figure 4-3 0.81mm coaxial antenna dimensions Figure 4-4 Schematic diagram of 0.81mm coaxial antenna connected to the RF connector Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 45 of 59 4.1.4 RF Connector Assembly Mate RF connector parallel refer Figure 4-5, do not slant mate with strong force. To avoid damage in RF connector unmating, it is recommended using pulling JIG as Figure 4-6, and the pulling JIG must be lifted up vertically to PCB surface (see Figure 4-7 and 4-8). Figure 4-5 Mate RF connector Figure 4-6 Pulling JIG Figure 4-7 Lift up pulling JIG Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 46 of 59 Figure 4-8 Pulling direction Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 47 of 59 4.2 Operating Band The operating bands of L850 module are shown in the following table:
Operating Band Description Mode Tx (MHz) Rx (MHz) Band 1 Band 2 Band 3 Band 4 Band 5 Band 7 Band 8 Band 11 Band 12 Band 13 Band 17 Band 18 Band 19 Band 20 Band 21 Band 26 Band 28 Band 29 Band 30 Band 66 Band 38 Band 39 Band 40 Band 41 GPS L1 2100MHz LTE FDD/WCDMA 1920 - 1980 2110 - 2170 1900MHz LTE FDD/WCDMA 1850 - 1910 1930 - 1990 1800MHz LTE FDD 1710 - 1785 1805 - 1880 1700MHz LTE FDD/WCDMA 1710 - 1755 2110 - 2155 850MHz LTE FDD/WCDMA 824 - 849 869 - 894 2600Mhz LTE FDD 2500 - 2570 2620 - 2690 900MHz LTE FDD/WCDMA 880 - 915 925 - 960 1500MHz LTE FDD 1427.9 - 1447.9 1475.9 - 1495.9 700MHz LTE FDD 699 - 716 729 - 746 700MHz LTE FDD 777 - 787 746 - 756 700MHz LTE FDD 704 - 716 734 - 746 800MHz LTE FDD 815 - 830 860 - 875 800MHz LTE FDD 830 - 845 875 - 890 800MHz LTE FDD 832 - 862 791 - 821 1500MHz LTE FDD 1447.9 - 1462.9 1495.9 - 1510.9 850MHz LTE FDD 814 - 849 859 - 894 700MHz LTE FDD 703 - 748 758 - 803 700MHz LTE FDD N/A 716 - 728 2300MHz LTE FDD 2305 - 2315 2350 - 2360 1700MHz LTE FDD 1710 - 1780 2110 - 2200 2600MHz LTE TDD 2570 - 2620 1900MHZ LTE TDD 1880 - 1920 2300MHz LTE TDD 2300 - 2400 2500MHZ LTE TDD 2496 - 2690 GLONASS L1 BDS
1575.421.023 1602.56254 1561.0982.046 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 48 of 59 4.3 Transmitting Power Band 1 24+1.7/-3.7 Band 2 24+1.7/-3.7 WCDMA Band 4 24+1.7/-3.7 The transmitting power for each band of L850 module is shown in the following table:
Mode Band 3GPP Requirement (dBm) Note Tx Power
(dBm) 23.51 23.51 23.51 23.51 23.51
Band 5 232.7 23+2/-1 10MHz Bandwidth, 1 RB Band 5 24+1.7/-3.7 Band 8 24+1.7/-3.7 Band 1 232.7 Band 2 232.7 Band 3 232.7 Band 4 232.7 Band 7 232.7 Band 8 232.7 Band 11 232.7 Band 12 232.7 Band 17 232.7 Band 18 232.7 Band 19 232.7 Band 20 232.7 Band 21 232.7 Band 26 232.7 LTE FDD Band 13 232.7 Band 28 23+2.7/-3.2 Band 30 232.7 Band 66 232.7 Band 38 232.7 Band 39 232.7 LTE TDD 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 49 of 59 Mode Band 3GPP Requirement (dBm) Note Tx Power
(dBm) 231 231 10MHz Bandwidth, 1 RB 10MHz Bandwidth, 1 RB Band 40 232.7 Band 41 232.7 Note:
Band 30 TX power range of L850-GL-03 serial module is between 221dBm, not 231dBm. 4.4 Receiver Sensitivity The receiver sensitivity for each band of the L850 module is shown in the following table:
Mode Band 3GPP Requirement
(dBm) Rx Sensitivity (dBm) Typical Note WCDMA Band 4
-106.7 Band 1
-106.7 Band 2
-104.7 Band 5
-104.7 Band 8
-103.7 Band 1
-96.3 Band 2
-94.3 Band 3
-93.3 Band 4
-96.3 Band 5
-94.3 Band 7
-94.3 Band 8
-93.3 Band 12
-93.3 Band 13
-93.3 Band 17
-93.3 Band 18
-96.3 Band 19
-96.3 Band 20
-93.3 Band 21
-96.3 LTE FDD Band 11
-96.3
-109.5
-110
-109.5
-111
-110
-101.5
-101.5
-101.5
-101.5
-102.5
-101
-102.5
-99
-100.5
-102.5
-102.5
-102.5
-103
-102.5
-99 BER < 0.1%
BER < 0.1%
BER < 0.1%
BER < 0.1%
BER < 0.1%
10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 50 of 59 Mode Band 3GPP Requirement
(dBm) Rx Sensitivity (dBm) Typical Note
-103
-103
-101
-100.5
-101
-101
-101.5
-100.5
-100 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth 10MHz Bandwidth Band 26
-93.8 Band 28
-94.8 Band 29
-93.3 Band 30
-95.3 Band 66
-95.8 Band 38
-96.3 Band 39
-96.3 Band 40
-96.3 Band 41
-94.3 LTE TDD Note:
4.5 GNSS The above values are measured for the dual antennas situation (Main+Diversity). For single main antenna (without Diversity), the sensitivity will drop around 3dBm for each band of LTE. L850 module supports GNSS with D/G antenna, including GPS/GLONASS/BDS. GNSS feature and performance are as below table. Description Condition Test Result MAX Typical GPS fixing 140mA@-130dBm 120mA@-130dBm Current GPS tracking 140mA@-130dBm 120mA@-130dBm GPS Sleep 3.5 mA@-130dBm 2.0mA@-130dBm Cold start 50s@-130dBm 39s@-130dBm TTFF Warm start 45s@-130dBm 33s@-130dBm Hot Start 3s@-130dBm 2s@-130dBm Tracking
-156dBm Acquisition
-144dBm
-160dBm
-149dBm Sensitivity Note:
Please note that GNSS current is tested with RF disabled. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 51 of 59 4.6 Antenna Design are shown in the following table:
L850 Module Main Antenna Requirements The L850 module provides main and diversity antenna interfaces, and the antenna design requirements Frequency range The most proper antenna to adapt the frequencies should be used. WCDMA band 1(2100): 250 MHz WCDMA band 2(1900): 140 MHz Bandwidth(WCDMA) WCDMA band 4(1700): 445 MHz Bandwidth(LTE) WCDMA band 5(850): 70 MHz WCDMA band 8(900): 80 MHz LTE band 1(2100): 250 MHz LTE band 2(1900): 140 MHz LTE Band 3(1800): 170 MHz LTE band 4(1700): 445 MHz LTE band 5(850): 70 MHz LTE band 7(2600): 190 MHz LTE Band 8(900): 80 MHz LTE Band 11(1500): 68 MHz LTE Band 12(700): 47 MHz LTE Band 13(700): 41 MHz LTE Band 17(700): 42 MHz LTE Band 18(800): 80 MHz LTE Band 19(800): 80 MHz LTE band 20(800): 71 MHz LTE band 21(1500): 63 MHz LTE band 26(850): 80 MHz LTE band 28(700): 100 MHz LTE band 29(700): 12 MHz LTE band 30(2300): 55 MHz LTE band 66(1700): 490 MHz LTE band 38(2600): 50 MHz LTE Band 39(1900): 40 MHz Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 52 of 59 L850 Module Main Antenna Requirements LTE band 40(2300): 100 MHz LTE band 41(2500): 194 MHz GPS: 2 MHz BDS: 4 MHz 50
> 26dBm average power WCDMA & LTE Bandwidth(GNSS) GLONASS: 8 MHz Impedance Input power ratio (SWR) Note:
Recommended standing-wave 2: 1 responsibility. ANT on B30 suggestion: Peak gain < 0dBi, for FCC EIRP requirement, Efficient > 50% for carrier TRP requirement. If integrator doesn't follow the instruction, Fibocom doesn't take Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 53 of 59 5 Structure Specification 5.1 Product Appearance The product appearance for L850 module is shown in Figure5-1:
Figure 5-1 Module appearance 5.2 Dimension of Structure The structural dimension of the L850 module is shown in Figure 5-2:
Figure 5-2 Dimension of structure Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 54 of 59 5.3 M.2 Interface Model The L850 M.2 module adopts 75-pin gold finger as external interface, where 67 pins are signal pins and 8 pins are notch pins as shown in Figure 3-1. For module dimension, please refer to 5.2 Dimension of Structure. Based on the M.2 interface definition, L850 module adopts Type 3042-S3-B interface (30x42mm, the component maximum height on t top layer is 1.5mm, PCB thickness is 0.8mm, and KEY ID is B). Figure 5-3 M.2 interface model 5.4 M.2 Connector L850 module connects with host by M.2 connector which is built in host. The recommended part number is APCI0026-P001A manufactured by LOTES Corporation, and the dimensions is shown in Figure 5-4. The package of connector, please refer to the specification. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 55 of 59 Figure 5-4 M.2 dimension of structure 5.5 Storage 5.5.1 Storage Life 5.6 Packing extent. Note Storage Conditions (recommended): Temperature is 23 5C, relative humidity is less than RH 60%. Storage period: Under the recommended storage conditions, the storage life is 12 months. The L850 module uses the tray sealed packing, combined with the outer packing method using the hard cartoon box, so that the storage, transportation and the usage of modules can be protected to the greatest The module is a precision electronic product, and may suffer permanent damage if no correct electrostatic protection measures are taken. 5.6.1 Tray Package L850-GL-01 serial module uses tray package, 20 pcs are packed in each tray, with 5 trays including one empty tray on top in each box and 5 boxes in each case. Tray packaging process is shown in Figure 5-5:
Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 56 of 59 Figure 5-5 Tray packaging process Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 57 of 59 Other L850(except L850-GL-01 serial) module uses tray package, 20 pcs are packed in each tray, with 5 trays including one empty tray on top in each box and 6 boxes in each case. Tray packaging process is shown in Figure 5-6:
Figure 5-6 Tray packaging process Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 58 of 59 5.6.2 Tray Size The pallet size of L850 module is 3151706.5mm, as shown in Figure 5-7:
Figure 5-7 Tray size (unit: mm) DIM (Unit: mm) ITEM L W H T A B C D E F G 315.02.0 170.02.0 6.50.3 0.80.1 43.00.3 31.00.3 79.00.2 60.00.2 180.00.2 60.00.2 40.00.2 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved. FIBOCOM L850-GL Series Hardware Guide Page 59 of 59
This product uses the FCC Data API but is not endorsed or certified by the FCC