| submitted | available | document details (if available) | source link |
|---|---|---|---|
| February 06 2015 | January 08 2015 | Microsoft Word - TM01LA-N_User Manual_Rev03 user Acrobat Distiller 9.0.0 (Windows) |
| various | Users Manual | Users Manual | 573.74 KiB | February 06 2015 / January 08 2015 |
Technical Specification (TM01LA-N) History Ver. Date Contents Written Checked Approved by by by Note
/30 Contents 1. Product Introduction ...................................................................................................... 5 1.1 Block Diagram ...................................................................................................... 5 1.2 Environmental Specifications ............................................................................... 6 1.3 Electrical Specifications ....................................................................................... 6 1.3.1 Absolute Maximum and ESD Ratings ........................................................... 6 1.3.2 Current Consumption .................................................................................... 7 1.4 Mechanical Specifications .................................................................................. 7 1.4.1 Physical Dimensions and Connection Interface ............................................ 7 1.4.2 Mechanical Drawing ...................................................................................... 7 1.4.3 Footprint ........................................................................................................ 7 1.5 PCB information ............................................................................................... 8 1.5.1 PCB Stack up ................................................................................................ 8 1.5.2 PCB VIA Stack up ......................................................................................... 8 2. Pin Definitions ............................................................................................................... 9 2.1 VCOIN ................................................................................................................ 12 2.2 ON/OFF Control ................................................................................................. 12 2.2.1 ON/OFF Timing ........................................................................................... 12 2.2.2 Deep Sleep .................................................................................................. 13 2.2.3 Sequence to Enter Deep Sleep Mode ......................................................... 15 2.3 USB .................................................................................................................... 15 2.4 UART ................................................................................................................. 15 2.5 UIM Interface ..................................................................................................... 16 2.6 General Purpose IO ........................................................................................... 16 2.7 Secure Digital IO ................................................................................................ 16 2.8 I2C Interface ..................................................................................................... 17 2.9 RESET ............................................................................................................... 17 2.10 ADC .................................................................................................................. 18 2.11 LED driver ....................................................................................................... 19 2.13 SPI Interface .................................................................................................. 19 2.14 HSIC Interface ................................................................................................ 20 2.15 JTAG Interface ............................................................................................... 20 3 RF Specification ......................................................................................................... 21 3.1. WCDMA B1, B2, B4, B5 Specification .............................................................. 21 3.2. LTE B1, B2, B4, B5, B7, B12 Specification..22 3.3. GSM 850/900/1800/1900 Specification ............................................................ 24
/30 4. GNSS ........................................................................................................................ 25 4.1 GNSS Characteristics ........................................................................................ 26 4.2 GNSS Antenna Interface .................................................................................... 26 4.3 Active antenna Powering the External LNA ....................................................... 26
/30 1. Product Introuction The TM01LA-N are designed for the automotive industry. They support LTE, WCDMA and GSM air Interface standards. They also have Global Navigation satellite system (GNSS) capabilities including GPS and GLONASS. The TM01LA-N are based on the Qualcomm MDM9215 wireless chipsets and support the following bands. Table 1. Supported Band NA Comments TML1-C TML1-E Region LTE WCDM A Band B2/B4/B5/B7/
B12/B17 B2/B4/B5 GSM GSM850/PCS1900 O O GNSS Voice 1.1 Block Diagram Figure 1.1. TML1-N Block diagram 5/30 1.2 Environmental Specifications The environmental specification for operating and storage of the TM01LA-N are defined in the the table below. Table 2. Environmental Specifications Parameter Operating Temperature Storage Temperature Humidity Temperature Range
-40 to 85
-40 to +90 95% or less 1.3 Electrical Specifications This section provides details for some of the key electrical specifications of the TM01LA-N embedded modules. 1.3.1 Absolute Maximum Rating and ESD Ratings This section defines the Absolute Maximum and Electrostatic Discharge (ESD) Ratings of the TM01LA-N embedded modules. Warning: If these parameters are exceeded, even momentarily, damage may occur to the device. Table 3. Absolute Maximum Ratings Parameter
+3.7V_VPWR Power Supply Input VIN Maximum Voltage applied to antenna interface pins VANT Voltage on any digital input or output pin VREG_MDME+0.5 Max tbd Units Min V V
-
-
Primary Antenna Diversity Antenna GNSS Antenna tbd tbd tbd V V V ESD Ratings ESD1 Primary, Diversity and GNSS antenna pads - Contact All other signal pads - Contact tbd tbd kV kV 1 The ESD Simulator configured with 330pF, 1000. Caution: The TM01LA-N embedded modules are sensitive to Electrostatic Discharge. ESD countermeasures and handling methods must be used when handling the TM01LA-N devices. 6/30 1.3.2 Current Consumption Table 4. TM01LA-N Current Consumption (TBD) Mode Parameter Band 2, Max TX Output Power Band 4, Max TX Output Power Band 5, Max TX Output Power Band 5, Max TX Output Power Band2, Max TX Output /Full RB Band4, Max TX Output /Full RB Band5, Max TX Output /Full RB Band7, Max TX Output /Full RB Band12, Max TX Output /Full RB Band17, Max TX Output /Full RB 850/900MHz PCL5 1800/1900MHz PCL0 Idle, Registered Idle, Registered Idle, Registered Sleep Mode, Average Current Sleep Mode, Average Current Sleep Mode, Average Current WCDMA LTE GSM WCDMA LTE GSM WCDMA LTE GSM Typical Max Units mA mA mA mA mA mA mA mA mA 1.4 Mechanical Specifications 1.4.1 Physical Dimensions and Connection Interface The TM01LA-N embedded modules are a Land Grid Array (LGA) form factor device. The device does not have a System or RF connectors. All electrical and mechanical connections are made via the 206 pad TM01LA-N on the underside of the PCB. Table5. TM01LA-N Embedded Module Dimensions Max Parameter 35.35 x 35.35 Overall Dimension Overall Module Height 3.85 1.1 PCB Thickness 0.1 Flatness Specification Weight 1.4.2 Mechanical Drawing Nominal 35 x 35 3.5 1.0 tbd Units mm mm mm mm g 7/30
[TOP View] [Side view]
1.4.3 Footprint
[TOP View]
8/30 0.75mm(R0.2) 0.85mm(R0.2) 0.95mm
[TOP View]
1.5 PCB information 1.5.1 PCB Stack up Layer Meterial PSR Copper Pre-Preg Copper Pre-Preg Copper Pre-Preg Copper Pre-Preg Copper 1 2 3 4 5 0.025 0.035 0.060 0.025 0.060 0.025 0.060 0.025 0.110 0.015 9/30 DK 3.98 3.98 3.98 4.15 6 7 8 9 10 Core Copper Pre-Preg Copper Pre-Preg Copper Pre-Preg Copper Pre-Preg Copper PSR 1.5.2 PCB via structure 4.41 4.15 3.98 3.98 3.98 0.100 0.015 0.110 0.025 0.060 0.025 0.060 0.025 0.060 0.035 0.025 0.980 2. Pin Definitions Pin No. RF Antenna Pads 12 15 GNSS Antenna Pad 126 Power Supply Pads 81,82,91,92 114 84 135 Name ANT_MAIN ANT_DIVERSITY ANT_GNSS
+3.7V_VPWR VREG_MDME VDD_AUDIO_3.3V VCOIN_3.3V Description Power Supply Input Voltage Reference Output (1.8V) Audio codec power supply (typ 3.3V) Coin Battery Input Direction Input/Output Input Input Input Output Input Input 10/30 USB Pads 185 198 183 199 UART Pads 153 169 154 170 UIM Pads 146 177 162 161 163 GPIO I/F Pads 172 128 150 164 139 189 137 138 148 130 Analog Audio I/F Pads 2 3 17 18 19 48 64 73 HSIC I/F Pads 195 194 196 Reset Pads 147 133 USB_VBUS USB_D+
USB_D-
USB_ID UART_RXD UART_TXD UART2_RXD UART2_TXD VREG_USIM UIM_DET UIM_RESET UIM_DATA UIM_CLK GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 AUDIO_INP1 AUDIO_INN1 AUDIO_INP2 AUDIO_INN2 AUDIO_LINE_IN SPK_OUT3 SPK_OUT1 SPK_OUT2 HSIC_STB HSIC_DATA HSIC_CAL RESET_N RESOUT_N Input Input/Output Input/Output Input USB Power Supply Differential data interface positive Differential data interface negative USB ID Output Input Output Input Receive Data (UART1) Transmit Data (UART1) UART2 Receive Data UART2 Transmit Data Output Input Output Input/Output Output Supply output for an UIM card Detection of an external UIM card Reset output to an external UIM card Data connection with an external UIM card Clock output to an external UIM card Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Input Input Input Input Input Output Output Output Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Microphone 1 input positive Microphone 1 input negative Microphone 2 input positive Microphone 2 input negative Audio LINE_IN input Speaker 3 output Speaker 1 output Speaker 2 output Input/Output Input/Output Input/Output HSIC Strobe signal HSIC data signal HSIC calibration pad Input Output External H/W Reset Input MDM Reset Output 11/30 ADC I/F Pads 129 204 LED I/F Pad 188 SPI I/F Pads 171 186 201 202 ON/OFF Pad 173 SDIO I/F Pads 140 122 141 142 131 132 I2C I/F Pads 117 109 JTAG I/F Pads 159 124 190 175 143 174 206 166 113 Reserved 203 74 75 93 94 99 100 101 102 103 110 111 ADC2 ADC1 LED SPI_CLK SPI_MISO SPI_MOSI SPI_CS_N ON/OFF SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK I2C_SCL I2C_SDA Input Input Analog to Digital Converter Input Analog to Digital Converter Input Output LED Driver control Output Input Output Output SPI Serial Clock SPI Serial input SPI Serial output SPI Chip Select Input ON/OFF Control Input/Output Input/Output Input/Output Input/Output Output Output SDIO Data bit 0 SDIO Data bit 1 SDIO Data bit 2 SDIO Data bit 3 SDIO Command SDIO Clock Output I2C Clock output Input/Output I2C Data TRST/
TDI TMS TCK RTCK TDO JTAG_PS_HOLD JTAG_RESIN_NN VREG_MDME Input Input Input Input Output Output Input Input Output ADC5 AUDIO_RST/
DEBUG_AUDIO_RST/
DEBUG_SDOUT3 I2S_DOUT DEBUG_I2C_SCL DEBUG_I2C_SDA DEBUG_SDOUT2 I2S_CLK I2S_WS I2S_DIN WIFI_PM_EN 12/30 Debugging Debugging Debugging Debugging Debugging Debugging Debugging Debugging Power Supply JTAG (1.8V) Reserved (PMIC MPP_05) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Clock WIFI_CLK_REQ WIFI_RESET_N GPIO68 GPIO65 GPIO66 GPIO67 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PBL_STATUS/HSIC_RST_N XO_OUT UART_RTS/
UART_CTS/
TCU_PCM_RXD WAKE_N TCU_PCM_CLK TCU_PCM_FRAME TCU_PCM_TXD I2S_MCLK NDR_PULSE GPIO_49 112 120 180 181 182 197 158 145 155 156 160 165 176 191 192 200 205 149 Ground 1,4,5,6,7, 8,9,10,11,13, 14,16,20,21,22, 23,24,25,26,27, 28,29,30,31,32, 33,34,35,36,37, 38,39,40,41,42, 43,44,45,46,47, 49,50,51,52,53, 54,55,56,57,58, 59,60,61,62,63, 65,66,67,68,69, 70,71,72,76,77, 78,79,80,83,85, 86,87,88,89,90, 95,96,97,98,104, 105,106,107,108,115, 116,118,119,121,123, 125,127,134,136,144, 151,152,157,167,168, 178,179,184,187,193 2.1 VCOIN The TM01LA-N provides an interface for a coin cell to maintain the internal RTC when
+3.7V_VPWR is removed from the TM01LA-N device. Whenever +3.7V_VPWR is applied the RTC is powered from the +3.7V_VPWR supply. Table7. VCOIN Interface Specification VCOIN DC Power Input Range Current Draw 2.2 ON/OFF Control Units V A Max 3.2 2.0 Typ 3 1.1 Min 2 Ground GND GND 13/30 The ON/OFF signal is internally pulled up to an internal 1.8V reference voltage. An open drain transistor should be connected to this pin to generate a low pulse. This pin should not be driven high external to the TM01LA-N embedded module. 2.2.1 ON/OFF Timing (TBD) The ON/OFF pin is a low pulse toggle control. The first pulse powers the TM01LA-N ON, a second pulse instructs the TM01LA-N to begin the Shutdown process. The diagram below illustrates the recommended application implementation for ON/OFF control. The diagram below illustrates an alternate application implementation that holds ON/OFF low during operation. 14/30 Table8. Power-ON Sequence Symbol Definitions (TBD) Symbol t ON t OFF t pwroff t pwrrmv Parameter Turn ON Pulse duration Turn OFF Pulse duration Time to Power OFF Time +3.7V_VPWR must be maintained after VREG_MDME goes inactive Time required for ON/OFF to be high prior to OFF pulse. Boot t HI Min TBD TBD
-
TBD Typ TBD TBD TBD Max TBD In process Complete TBD TBD T pwroff is the time between when a power OFF pulse is complete and when shutdown is completed by the TM01LA-N devices. This duration is network and device dependent, i.e. in a CDMA network a power down registration is initiated by the TM01LA-N device, when the acknowledgement is received from the network power OFF completes. Detection of power down can be accomplished by monitoring for one of the following:
+WIND: 10 output on the AT Command interface USB ports are de-enumerated The application must wait for a power down to be detected prior to removing power from the TM01LA-N device. If a timeout is required, it is recommended to be in excess of 30s prior to removing power from the TM01LA-N device. 2.2.2 Deep Sleep The TM01LA-N embedded modules support a low power mode in which the device is registered on the LTE/GSM/WCDMA network and sleeps in between wake intervals where it listens for pages. The following table lists the parameter that defines the wake interval period for the various devices. Table9. Period of Wake Intervals 15/30 Device TM01LA-N Network Standard GSM WCDMA LTE Parameter DRX DRX DRX The DRX cycle index values are broadcast by the wireless network on which the TM01LA-N embedded module is registered. While in Deep Sleep mode the functions of the TM01LA-N are limited as defined in the following table. Table10. Deep Sleep Function Availability Function Paging GNSS Time measurement USB UART Digital IO Events that cause the TM01LA-N to wake-up from Deep Sleep mode include:
Conditions GNSS is powered down USB_VBUS is not applied Digital IO pins maintained last state Availability Incoming call Expiration of an internal timer in the TM01LA-N USB_VBUS is applied to the TM01LA-N WAKE_N is asserted (low) UART1 DTR is asserted (high) if UART1 DTR has been enabled as a sleep control
(AT+W32K=1,1) and AT Command Service is mapped to UART1 GNSS location fix request is initiated from an Embedded Application 2.2.3 Sequence to Enter Deep Sleep Mode The following list defines the sequence needed by the application to allow the TM01LA-N to enter Deep Sleep mode:
1. TM01LA-N has registered on the WWAN network (or callbox), and is not in a call. 2. End GNSS Tracking session. 3. Turn off GNSS Antenna bias. 4. Confirm WAKE_N is not held low (pulled-up in TM01LA-N). 5. Issue AT command to request AR device to enter deep sleep (AT+W32K=1,x). 6. If AT+W32K=1,1 is used, DTR must also be de-asserted to allow sleep. 7. Ensure UARTs are in the inactive state. 8. Remove VBUS from being applied to the AR device. 2.3 USB 16/30 The TM01LA-N has a High Speed USB2.0 compliant, peripheral only interface. The TM01LA-N dont support OTG. The TM01LA-N will not be damaged if a valid USB_VBUS is supplied while the main DC power is not supplied. Table10. USB Characteristics USB USB_VBUS Value 2.0 5.25 1 10 Units V mA F Voltage range Maximum Current draw 1 Maximum Input Capacitance
(Min ESR = 50 m) Direction Output Input Output Input Output Input Name UART_RXD UART_TXD UART2_RXD UART2_TXD UART_RTS/
UART_CTS/
Description Receive Data (UART1) Transmit Data (UART1) Receive Data (UART2) Transmit Data (UART2) Request To Send(UART1) Clear To Send(UART1) 1 With the TM01LA-N device powered ON. 2.4 UART The TM01LA-N has two UART interfaces. The primary UART is an 4-wire electrical interface and the secondary UART is a 2-wire electrical interface. Table11. UART Interface PADs Pin No. 153 169 154 170 155 156 2.5 UIM Interface The UIM interface of the TM01LA-N supports a USIM for LTE, WCDMA and GSM. Table13. UIM Interface PADs Pin No. 146 177 162 161 163 2.6 General Purpose IO Direction Output Input Output Input/Output Data connection with an external UIM card Output Description Supply output for an UIM card Detection of an external UIM card Reset output to an external UIM card Name VREG_USIM UIM_DET UIM_RESET UIM_DATA UIM_CLK Clock output to an external UIM card 17/30 Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 Direction Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Description Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO Available-GPIO The TM01LA-N defines 10 GPIOs for customer use. Table14. GPIO Inferface PADs Pin No. 172 128 150 164 139 189 137 138 148 130 2.7 Secure Digital IO The TM01LA-N defines a 1.8V SDIO interface for future use. Table15. SDIO Inferface PADs Pin No. 140 122 141 142 131 132 2.8 I2C Interface The TM01LA-N provides an I2C interface. The I2C signals are open drain outputs with 2.2 k pull-up resistors toVREG_MDME (1.8V) internal to the TM01LA-N. Table16. I2C Inferface PADs Pin No. 117 109 2.9 RESET Direction Input/Output SDIO Data bit 0 Input/Output SDIO Data bit 1 Input/Output SDIO Data bit 2 Input/Output SDIO Data bit 3 SDIO Command Output Output SDIO Clock Name SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK Description I2C Clock output I2C Data Direction Output Input/Output Name I2C_SCL I2C_SDA Description 18/30 The TM01LA-N provides an interface to allow an external application to RESET the module as well as an output to indicate the current RESET state or control an external device. The RESIN_N signal is pulled-up internal to the TM01LA-N. An open collector transistor or equivalent should be used to Ground the signal when necessary to RESET the module. Note: Use of the RESIN_N signal to RESET the TM01LA-N could result in memory corruption if used inappropriately. This signal should only be used if the TM01LA-N has become unresponsive and it is not possible to perform a power cycle. Table17. Reset Timing Parameter Symbol Trdet Duration of RESIN_N signal before firmware detects it
(debounce timer) Duration reset asserted Delay between minimum Reset duration and Internal Reset generated Trlen Trdel Typ tbd Min
-
tbd
-
tbd Max Figure . Illustration of Reset Timing When RESIN_N < Trdel Figure. Illustration of Reset Timing When RESIN_N Held Low > Trdet+Trdel 2.10 ADC 19/30 The TM01LA-N provides two ADC inputs. The interface information is provided in the tables below. Table18. ADC Interface Characteristics ADC ADCx Full-Scale Voltage Level Resolution Sample rate Input Impedance Value 0.05 ~ 1.75 15 1.15 (tbd)
>4 Units V bit KHz M Name LED Direction Output Description LED Driver control 2.11 LED driver The TM01LA-N provides an LED driver. The LED driver is a programmable current sink. Table19. LED Inferface PAD Pin No. 188 2.12 Audio The TM01LA-N supports Analog audio interfaces. The ADC blocks supports Stereo 24-bit Inputs (Differential, Single-ended) and Mono 24-bit
(Line-In). The DAC blocks supports Stereo 24-bit output (Stereo) and Line output (Single-ended). Table20. Audio Inferface PADs Pin No. 2 3 17 18 19 48 64 73 2.13 SPI Interface The TM01LA-N embedded module provides one SPI bus (4-wire interface). SPI bus interface includes:
Description Microphone 1 input positive Microphone 1 input negative Microphone 2 input positive Microphone 2 input negative Audio LINE_IN input Speaker 3 output Speaker 1 output Speaker 2 output Name AUDIO_INP1 AUDIO_INN1 AUDIO_INP2 AUDIO_INN2 AUDIO_LINE_IN SPK_OUT3 SPK_OUT1 SPK_OUT2 Direction Input Input Input Input Input Output Output Output 20/30 A CLK signal An O signal An I signal A CS (Chip Select) signal The following features are available on the SPI bus :
Master-only mode operation SPI speed is from 128 kbit/s to 26Mbit/s in master mode operation 4-wire interface 4 to 32 bits data length. (TBD) Direction Output Input Output Output Name SPI_CLK SPI_MISO SPI_MOSI SPI_CS_N Description SPI Serial Clock SPI Serial input SPI Serial output SPI Chip Select Table21. SPI Inferface PADs Pin No. 171 186 201 202 2.14 HSIC Interface The TM01LA-N embedded module provides one HSIC bus (2-wire interface). HSIC bus interface includes:
HSIC strobe signal HSIC data signal Calibration pad for HSIC port signal Description Name HSIC_STB HSIC_DATA HSIC_CAL Direction Input/Output HSIC Strobe signal Input/Output HSIC data signal Input/Output HSIC calibration pad Table22. HSIC Inferface PADs Pin No. 195 194 196 2.15 JTAG Interface JTAG test points on customer application are recommended for possible failure analysis if necessary in the future. Table23. JTAG Inferface PADs Pin No. 159 Description Debugging Direction Input Name TRST/
21/30 124 190 175 143 174 206 166 TDI TMS TCK RTCK TDO JTAG_PS_HOLD JTAG_RESIN_NN Input Input Input Output Output Input Input Debugging Debugging Debugging Debugging Debugging Debugging Debugging Output VREG_MDME Power Supply JTAG (1.8V) 113 3. RF Specification The specifications for the LTE, GSM and WCDMA interfaces are defined. TM01LA-N is designed to be compliant with the standard shown in the table below. Table24. Standards Compliance Technology UMTS (WCDMA) Standards 3GPP Release 5 3GPP Release 6 3GPP Release 7 3GPP Release 8 3GPP Release 8 3GPP Release R99 LTE GSM/GPRS/EDGE 3.1 WCDMA B1, B2, B4, B5 Specification 3.1.1 WCDMA TX Output Power The Maximum / Minimum Transmitter Output Power of the TM01LA-N are specified in the following table. 22/30 Table25. Band Method (UL CH) Specification WCDMA Band 2 Power Level WCDMA Band 4 Power Level WCDMA Band 5 Power Level Measure Max and Min Transmit Power of Low Channel (CH=9263) in WCDMA B2 Mode Measure Max and Min Transmit Power of Middle Channel (CH=9400) in WCDMA B2 Mode Measure Max and Min Transmit Power of High Channel (CH=9537) in WCDMA B2 Mode Measure Max and Min Transmit Power of Low Channel (CH=1313) in WCDMA B4 Mode Measure Max and Min Transmit Power of Middle Channel (CH=1413) in WCDMA B4 Mode Measure Max and Min Transmit Power of High Channel (CH=1513) in WCDMA B4 Mode Measure Max and Min Transmit Power of Low Channel (CH=4133) in WCDMA B5 Mode Measure Max and Min Transmit Power of Middle Channel (CH=4183) in WCDMA B5 Mode Measure Max and Min Transmit Power of High Channel (CH=4232) in WCDMA B5 Mode Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm Max Power : 21.5~25.5dBm Min Power : -50dBm 3.1.2 WCDMA RX Sensitivity The Receiver Sensitivity of the TM01LA-N are specified in the following table. Table26. Conducted RX (Receive) Sensitivity UMTS Bands Specification 0~0.1% @<-104.7dBm 0~0.1% @<-104.7dBm 0~0.1% @<-104.7dBm 0~0.1% @<-106.7dBm 0~0.1% @<-106.7dBm 0~0.1% @<-106.7dBm 0~0.1% @<-104.7dBm 0~0.1% @<-104.7dBm 0~0.1% @<-104.7dBm Item Method (DL CH) WCDMA Band 2 BER(Bit Error Rate) WCDMA Band 4 BER(Bit Error Rate) WCDMA Band 5 BER(Bit Error Rate) Measure BER of Low Channel (CH=9663) in WCDMA B2 Mode Measure BER of Middle Channel (CH=9800) in WCDMA B2 Mode Measure BER of High Channel (CH=9937) in WCDMA B2 Mode Measure BER of Low Channel (CH=1538) in WCDMA B4 Mode Measure BER of Middle Channel (CH=1675) in WCDMA B4 Mode Measure BER of High Channel (CH=1737) in WCDMA B4 Mode Measure BER of Low Channel (CH=4358) in WCDMA B5 Mode Measure BER of Middle Channel (CH=4400) in WCDMA B5 Mode Measure BER of High Channel (CH=4457) in WCDMA B5 Mode 3.2. LTE B1, B2, B4, B5, B7, B12 Specification 3.2.1 LTE TX Output Power 23/30 The Maximum / Minimum Transmitter Output Power of the TM01LA-N are specified in the following table. Table27. Conducted TX (Transmit) Max output Power Tolerances LTE Bands BAND Method (UL CH) BAND2 UE Maximum Output Power BAND4 UE Maximum Output Power BAND5 UE Maximum Output Power BAND7 UE Maximum Output Power BAND12 UE Maximum Output Power BAND17 UE Maximum Output Power Measure Max and Min Transmit Power of Low Channel (18650) Measure Max and Min Transmit Power of Mid Channel (18900) Measure Max and Min Transmit Power of High Channel (19150) Measure Max and Min and Min Transmit Power of Low Channel (20000) Measure Max and Min Transmit Power of Mid Channel (20175) Measure Max and Min Transmit Power of High Channel (20350) Measure Max and Min and Min Transmit Power of Low Channel (20450) Measure Max and Min Transmit Power of Mid Channel (20525) Measure Max and Min Transmit Power of High Channel (20600) Measure Max and Min and Min Transmit Power of Low Channel (20800) Measure Max and Min Transmit Power of Mid Channel (21100) Measure Max and Min Transmit Power of High Channel (21400) Measure Max and Min and Min Transmit Power of Low Channel (23060) Measure Max and Min Transmit Power of Mid Channel (23095) Measure Max and Min Transmit Power of High Channel (23130) Measure Max and Min and Min Transmit Power of Low Channel (23735) Measure Max and Min Transmit Power of Mid Channel (23790) Measure Max and Min Transmit Power of High Channel (23845) Specification Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm Max Power : 20.8~26.2dBm Min Power : -39dBm 3.2.2 LTE RX Sensitivity The Receiver Sensitivity of the TM01LA-N are specified in the following table. Table28. Conducted RX (Receive) Sensitivity LTE Bands BAND BAND2 Reference Method (DL CH) Measure BLER of Low Channel (650) in Band1 Specification sensitivity : -95 BLER : 5%
24/30 sensitivity level(DUAL) BAND 4 Reference sensitivity level(DUAL) BAND 5 Reference sensitivity level(DUAL) BAND 7 Reference sensitivity level(DUAL) BAND 12 Reference sensitivity level(DUAL) BAND 17 Reference sensitivity level(DUAL) Measure BLER of Mid Channel (900) in Band1 Measure BLER of High Channel (1150) in Band1 Measure BLER of Low Channel (2000) in Band4 Measure BLER of Mid Channel (2175) in Band4 Measure BLER of High Channel (2350) in Band4 Measure BLER of Low Channel (2450) in Band5 Measure BLER of Mid Channel (2525) in Band5 Measure BLER of High Channel (2600) in Band5 Measure BLER of Low Channel (2800) in Band7 Measure BLER of Mid Channel (3100) in Band7 Measure BLER of High Channel (3400) in Band7 Measure BLER of Low Channel (5060) in Band12 Measure BLER of Mid Channel (5095) in Band12 Measure BLER of High Channel (5130) in Band12 Measure BLER of Low Channel (5735) in Band12 Measure BLER of Mid Channel (5790) in Band12 Measure BLER of High Channel (5845) in Band12 sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -97 BLER : 5%
sensitivity : -97 BLER : 5%
sensitivity : -97 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -95 BLER : 5%
sensitivity : -94 BLER : 5%
sensitivity : -94 BLER : 5%
sensitivity : -94 BLER : 5%
sensitivity : -94 BLER : 5%
sensitivity : -94 BLER : 5%
sensitivity : -94 BLER : 5%
3.3 GSM 850/900/1800/1900 Specification 3.3.1 GSM TX Output Power The Maximum Transmitter Output Power of the TM01LA-N are specified in the following table. Table29. Conducted TX (Transmit) Max output Power Tolerances GSM/EDGE Bands Item Method (DL CH) Specification Measure Max Transmit Power of Low Channel
(CH=128) in GSM850 Mode Measure Max Transmit Power of Middle Channel
(CH=189) in GSM850 Mode Measure Max Transmit Power of High Channel
(CH=251) in GSM850 Mode Measure Max Transmit Power of Low Channel
(CH=975) in EGSM Mode Measure Max Transmit Power of Middle Channel
(CH=38) in EGSM Mode Measure Max Transmit Power of High Channel
(CH=124) in EGSM Mode Max Power : 31.0~33.5dBm Max Power : 31.0~33.5dBm Max Power : 31.0~33.5dBm Max Power : 31.0~33.5dBm Max Power : 31.0~33.5dBm Max Power : 31.0~33.5dBm 25/30 GSM850 Power Level EGSM900 Power Level DCS1800 Power Level PCS1900 Power Level Measure Max Transmit Power of Low Channel
(CH=512) in DCS1800 Mode Measure Max Transmit Power of Middle Channel
(CH=660) in DCS1800 Mode Measure Max Transmit Power of High Channel
(CH=885) in DCS1800 Mode Measure Max Transmit Power of Low Channel
(CH=512) in DCS1900 Mode Measure Max Transmit Power of Middle Channel
(CH=660) in DCS1900 Mode Measure Max Transmit Power of High Channel
(CH=810) in DCS1900 Mode Max Power : 28.0~30.5dBm Max Power : 28.0~30.5dBm Max Power : 28.0~30.5dBm Max Power : 28.0~30.5dBm Max Power : 28.0~30.5dBm Max Power : 28.0~30.5dBm 3.3.2 GSM RX Sensitivity The Receiver Sensitivity of the TM01LA-N are specified in the following table. Table30. Conducted RX (Receive) Sensitivity GSM/EDGE Bands Item Method (DL CH) GSM850 BER(Bit Error Rate) EGSM900 BER(Bit Error Rate) DCS1800 BER(Bit Error Rate) PCS1900 BER(Bit Error Rate) Measure BER of Low Channel (CH=128) in GSM850 Mode Measure BER of Middle Channel (CH=189) in GSM850 Mode Measure BER of High Channel (CH=251) in GSM850 Mode Measure BER of Low Channel (CH=975) in EGSM Mode Measure BER of Middle Channel (CH=38) in EGSM Mode Measure BER of High Channel (CH=124) in EGSM Mode Measure BER of Low Channel (CH=512) in DCS1800 Mode Measure BER of Middle Channel (CH=660) in DCS1800 Mode Measure BER of High Channel (CH=885) in DCS1800 Mode Measure BER of Low Channel (CH=512) in PCS1900 Mode Measure BER of Middle Channel (CH=660) in PCS1900 Mode Measure BER of High Channel (CH=810) in PCS1900 Mode Specification 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 0~2.439% @<-102dBm 4. GNSS The TM01LA-N includes optional Global Navigation Satellite System(GNSS) capabilities via the Qualcomm gpsOne Gen8A Engine, capable of operation in assisted and stand-alone GPS modes as well as GPS+GLONASS mode. Table30. Position location and navigation summary(gpsOne) Standard Feature descriptions 26/30 gpsOne with global navigation satellite system (GNSS) support Global positioning system (GPS) Next-generation gpsOne solution with enhanced GNSS engine and low power tracking Enhanced navigation 3.0, dynamic power optimization, and on-demand positioning Support for Wi-Fi positioning MS/UE-based, MS/UE-assisted, hybrid modes with AFLT (CDMA), NMR (GSM), and MRL(UMTS, WCDMA, LTE), standalone and network-aware modes Gen8A gpsOneXTRA Assistance for enhanced standalone GNSS performance Control plane: IS-801, IS-881, and UMTS CP assisted-GNSS protocols User plane: v1/v2 trusted mode and OMA SUPL 2.0 assisted-GPS protocols Wideband processing of GPS signals helps resolve multipath interference, promoting improved measurement accuracy Support for GLONASS standalone mode GLONASS capability increases the number of satellites available to the positioning engine, resulting in an expanded area of coverage over traditional GPS receivers 4.1 GNSS Characteristics The GNSS implementation supports GPS L1 operation and GLONASS L1 FDMA operation. Table31. GNSS Characteristics Value TBD TBD TBD
<2m CEP-50
~30 SVs Yes 5 m 1 s 29 s 32 s TBD NMEA Parameter Sensitivity Standalone or MS Based Tracking Sensitivity Cold Start Sensitivity MS Assisted Synchronous A-GNSS Acquisition Sensitivity Accuracy in Open Sky (1 Hz tracking) Total number of SV available Support for Predicted Orbits Predicted Orbit CEP-50 Accuracy Standalone Time To First Fix (TTFF) Super Hot Warm Cold Number of channels GNSS Message Protocols Note: Acquisition/Tracking Sensitivity performance figures assume open sky w/ active patch GNSS antenna and a 2.5 dB Noise Figure. 4.2 GNSS Antenna Interface Table31. GNSS Antenna Interface Characteristics Characteristics Frequency GNSS 1575.42 20 MHz GPS L1 (Wideband) 27/30 Glonass L1 FDMA 1597.5 1605.8 MHz 50 2:1 RX RF Impedance VSWR max 4.3 Active antenna Powering the External LNA The external LNA needs a source of power. Many of the active antennas accept a 3 volt or 5 volt DC voltage that is impressed upon the RF signal line. This voltage is not supplied by the TM01LA-N, but can be easily supplied by the host design. 4.3.1 External LNA Enable The electrical characteristics of the GNSS_LNA_EN signal are:
Table32. GNSS_LNA EN Table Parameter GNSS_LNA_EN Typ Max 1.9 0.2 Units V V Output high level Output low level Min 1.6 0 An example of GPS Antenna Supply circuit is shown in the following image:
28/30 GPIO7 : GNSS POWER EN 29/30
<FCC Warning Statements>
FCC Part 15.19 Statements:
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. FCC Part 15.21 statement Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. RF Exposure Statement The antenna(s) must be installed such that a minimum separation distance of at least 20 cm is maintained between the radiator (antenna) and all persons at all times. This device must not be co-located or operating in conjunction with any other antenna or transmitter. The highest permitted antenna gains including cable loss for use with this device are: GSM850 /
WCDMA850 : -3.25 dBi, GSM1900 / WCDMA1900 : 1.26 dBi, WCDMA1700 : -0.13 dBi, LTE Band 2:
1.26 dBi, LTE Band 5: -3.25 dBi, LTE Band 17: -3.03 dBi, LTE Band 4: -0.13 dBi, LTE Band 7: -0.22 dBi, LTE Band 12: -3.03 dBi.. End Product Labeling The module is labeled with its own FCC ID. If the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. In that case, the final end product must be labeled in a visible area with the following:
Contains FCC ID: BEJLGAJ10 OEM Responsibilities to comply with FCC Regulations The module has been certified for integration into products only by OEM integrators under the following condition:
- The antenna(s) must be installed such that a minimum separation distance of at least 20 cm is maintained between the radiator (antenna) and all persons at all times.
- The transmitter module must not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with FCC multi-transmitter product procedures. As long as the two condition above is met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions can t be met (for certain configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID cant be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product
(including the transmitter) and obtaining a separate FCC authorization. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module or change RF related parameters in the user manual of the end product. 30/30
This product uses the FCC Data API but is not endorsed or certified by the FCC