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HAC-033B Module Installation Manual Assembly drawing HAC-033 / HAC-034 Lower Housing Battery Battery Holder HAC-033B HAC-033 / HAC-034 Upper Housing Specifications 1.1 Electrical Characteristics Table 1 shows the maximum electrical rating for voltages referenced to VDD pin. Table 1. Absolute Maximum Voltages Requirement Parameter Ambient Temperature of Operation Storage temperature ESD Tolerance HBM ESD Tolerance MM ESD Tolerance CDM Latch-up VDD Core VDD IO VDD RF (excluding class 1 PA) Specification Minimum Nominal Maximum 30 40 2000 100 500 1.14 1.62 1.14 25 200 1.2 3.3 1.2 85 150 2000 100 500 1.26 3.6 1.26 Unit C C V V V mA V V V Table 2 shows the power supply characteristics for the range TJ = 0C to 125C. Table 2. Power Supply Specifications Parameter Conditions VBAT input Operating temperature Junction temperature Total system leakage Max value is defined at temp = 85C PMU turn-on time VBAT is ready. Min. 1.62 40 TBD Typical Max. Unit 3.3 50 0.5 3.6 125 1.3 300 V C A s Table 3 showsthedigitallevelcharacteristicsfor(VSS=0V). Table 3. VDDC LDO Electrical Specifications Parameter Input Voltage Nominal Output Voltage Conditions DC Accuracy Accuracy at any step, including bandgap reference. Output Voltage Programmability Load Current Dropout Voltage Line Regulation Load Regulation Range Step Size Iload = 40 mA Vin from 1.62V to 3.6V, Iload = 40 mA Iload = 1 mA to 40 mA, Vout = 1.2V, Package + PCB R = 0.3 Quiescent Current No load @Vin = 3.3V Max load @Vin = 3.3V Power down Current Vin = 3.3V @25C Output Noise PSRR Vin = 3.6 @80C Iload = 15 mA, 100 kHz Iload = 15 mA, 2 MHz Vin = 3.3, Vout = 1.2V, Iload = 40 mA Over Current Limit 1 kHz 10 kHz 100 kHz Turn-on Time In-rush current during turn-on Transient Perfor-
mance External Output Capacitor External Input Capacitor VBAT = 3.3V, BG already on, LDO OFF to ON, Co = 1 F, 90% of Vout During start-up, Co = 1 F Iload = 1 mA to 15 mA and 15 mA to 1 mA in 1 s Iload = 15 mA to 40 mA and 40 mA to 15 mA in 1 s Ceramic cap with ESR 0.5 Ceramic, X5R, 0402, 20%, 10V. Min. 1.62 5 0.89 65 60 55 100 0.8 Typical 3.3 1.2 30 0.02 18 0.2 TBD 1 1 Max. 3.6 5 1.34 40 200 0.2 0.05 23 0.56 0.65 40 14 100 60 40 25 4.7 Unit V V
%
V mV mA mV
%Vo/V
%Vo/mA A mA A nV/sqrtHz nV/sqrtHz dB dB dB mA s mA mV F F Table 4. ADC Microphone Specifications (Cont.) Parameter Symbol Conditions/Comments Min. Typical Max. MIC bias noise ADC SNR ADC THD + N GPIO input voltage GPIO source impedancea I PGA input referred. 6 dB attenuation is assumed from MIC bias output to PGA input. I 20 Hz to 8 kHz I A-weighted I A-weighted I 0 dB PGA gain I 3 dBFS input I 0 dB PGA gain Must be lower than VBAT Resistance Capacitance 78 74 3 3.6 1 10 Unit V dB dB V k pF a. Conditional requirement for the measurement time of 10 s. Relaxed with longer measurement time for each GPIO input channel. Table 5. Digital I/O Characteristics Characteristics Symbol Minimum Typical Maximum Unit Input low voltage (VDDO = 3.3V) Input high voltage (VDDO = 3.3V) Input low voltage (VDDO = 1.8V) Input high voltage (VDDO = 1.8V) Output low voltage Output high voltage Input low current Input high current Output low current
(VDDO = 3.3V, VOL = 0.4V) Output high current
(VDDO = 3.3V, VOH = 2.9V) Output high current
(VDDO = 1.8V, VOH = 1.4V) Input capacitance Note:
VIL VIH VIL VIH VOL VOH IIL IIH IOL IOH IOH CIN 2.0 1.1 VDDO 0.4V 0.8 0.6 0.4 1.0 1.0 8.0 8.0 4.0 0.4 V V V V V V A A mA mA mA pF In Table 5, current consumption measurements are t aken at VBAT with the assumption that VBAT is connected to VDDIO and LDOIN. Table 6. Bluetooth Current Consumption, Class1 Operating Mode Typical Unit DM1/DH1 DM3/DH3 DM5/DH5 3DH5/3DH5 Page scan Sniff slave (495 ms) Sniff slave (22.5 ms) Sniff slave (11.25 ms) HIDOFF (deep sleep) BLE scana BLE ADV unconnectable 1.00 sec BLE connected 600 ms interval 32.15 38.14 38.46 37.10 486 254 2.6 4.95 2.69 355 176 211 mA mA mA mA A A mA mA A A A A a. No devices present. A 1.28 second interval with a scan window of 11.25 ms. Table 7. Bluetooth Current Consumption, Class 2(0 dbm ) Operating Mode Typical Unit DM1/DH1 DM3/DH3 DM5/DH5 3DH5/3DH5 HIDOFF (deep sleep) BLE scana BLE ADV unconnectable 1.00 sec a. No devices present. A 1.28 second interval with a scan window of 11.25 ms. 27.5 31.34 32.36 31.57 2.69 368 174 mA mA mA mA A A A 2 RF Specifications Note:
I All specifications in Table 8 are for industrial temperatures. I All specifications in Table 8 are single-ended. Unused inputs are left open. Table 8. Receiver RF Specifications Parameter Conditions Minimum Typical a Maximum Unit Frequency range RX sensitivity b Maximum input Maximum input 2402 General GFSK, 0.1% BER, 1 Mbps LE GFSK, 0.1% BER, 1 Mbps S/4-DQPSK, 0.01% BER, 2 Mbps 8-DPSK, 0.01% BER, 3 Mbps GFSK, 1 Mbps S/4-DQPSK, 8-DPSK, 2/3 Mbps Interference Performance C/I cochannel GFSK, 0.1% BER C/I 1 MHz adjacent channel GFSK, 0.1% BER C/I 2 MHz adjacent channel GFSK, 0.1% BER C/I > 3 MHz adjacent channel GFSK, 0.1% BER C/I image channel GFSK, 0.1% BER C/I 1 MHz adjacent to image channel GFSK, 0.1% BER C/I cochannel S/4-DQPSK, 0.1% BER C/I 1 MHz adjacent channel S/4-DQPSK, 0.1% BER C/I 2 MHz adjacent channel S/4-DQPSK, 0.1% BER C/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER C/I image channel S/4-DQPSK, 0.1% BER C/I 1 MHz adjacent to image channel S/4-DQPSK, 0.1% BER C/I cochannel 8-DPSK, 0.1% BER C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER C/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER C/I Image channel 8-DPSK, 0.1% BER C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER Out-of-Band Blocking Performance (CW)c 30 MHz2000 MHz 20002399 MHz 24983000 MHz 3000 MHz12.75 GHz 0.1% BER 0.1% BER 0.1% BER 0.1% BER 10.0 27 27 10.0 93.5 96.5 95.5 89.5 9.5 5 40 49 27 37 11 8 40 50 27 40 17 5 40 47 20 35 2480 20 20 11 0 30.0 40.0 9.0 20.0 13 0 30.0 40.0 7.0 20.0 21 5 25.0 33.0 0 13.0 MHz dBm dBm dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm dBm dBm Table 8. Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical a Maximum Unit Out-of-Band Blocking Performance, Modulated Interferer 776764 MHz 824849 MHz 18501910 MHz 824849 MHz 880915 MHz 17101785 MHz 18501910 MHz 18501910 MHz 19201980 MHz BT, Df = 5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 65 MHz to 108 MHz 746 MHz to 764 MHz 851894 MHz 925960 MHz 18051880 MHz 19301990 MHz 21102170 MHz CDMA CDMA CDMA EDGE/GSM EDGE/GSM EDGE/GSM EDGE/GSM WCDMA WCDMA Intermodulation Performancee Spurious Emissionsf 39.0 FM RX CDMA CDMA EDGE/GSM EDGE/GSM PCS WCDMA 10d 10d 23d 10d 10d 23d 23d 23d 23d 147 147 147 147 147 147 147 62 47 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz a. Typical operating conditions are 1.22V operating voltage and 25C ambient temperature. b. The receiver sensitivity is measured at BER of 0.1% on the device interface. c. Meets this specification using front-end band pass filter. d. Numbers are referred to the pin output with an external BPF filter. e. f0 = -64 dBm Bluetooth-modulated signal, f1 = 39 dBm sine wave, f2 = 39 dBm Bluetooth-modulated signal, f0 = 2f1 f2, and |f2 f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. Includes baseband radiated emissions. f. Note:
I All specifications in Table 9 are for industrial temperatures. I All specifications in Table 9 are single-ended. Unused inputs are left open. Table 9. Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range Class1: GFSK TX powera Class1: EDR TX powerb Class 2: GFSK TX power Power control step S/4-DQPSK Frequency Stability S/4-DQPSK RMS DEVM S/4-QPSK Peak DEVM S/4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM 8-DPSK 99% DEVM 1.0 MHz < |M N| < 1.5 MHz 1.5 MHz < |M N| < 2.5 MHz
|M N| > 2.5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz General Modulation Accuracy In-Band Spurious Emissions Out-of-Band Spurious Emissions 2402 2 10 10 12 9 2 4 2480 8 10 20 35 30 10 13 25 20 26 20 40 36.0c 30.0c, d 47.0 47.0 MHz dBm dBm dBm dB kHz
%
%
%
kHz
%
%
%
dBc dBm dBm dBm dBm dBm dBm a. TBD dBm output for GFSK measured with PAVDD = 2.5V. b. TBD dBm output for EDR measured with PAVDD = 2.5V. c. Maximum value is the value required for Bluetooth qualification. d. Meets this spec using a front-end band-pass filter. Table 10. BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range RX sensea TX powerb Mod Char: Delta F1 average Mod Char: Delta F2 maxc Mod Char: Ratio N/A GFSK, 0.1% BER, 1 Mbps N/A N/A N/A N/A 2402 225 99.9 0.8 96.5 9 255 0.95 2480 275 MHz dBm dBm kHz
%
%
a. Dirty TX is Off. b. The BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm EIRP specification limit. c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. 3 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 11. UART Timing Specifications Reference Characteristics Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high 1 2 3 Min. Max. 24 10 2 Unit Baud out cycles ns Baud out cycles Figure 9. UART Timing Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name I/O Power Domain Description RFOP IFVDD1P2 LNAVDD1P2 VCOVDD1P2 PLLVDD1P2 PAVDD Radio I/O A1 RF Power Supplies D1 B1 C1 B2 A3 Power Supplies F1, G3 A9, K1 B6 A5 A8 Ground A2, A10, B5, C2, C3, D3, F2, J1, K10 B8 Clock Generator and Crystal Interface B4 VDDC VDDO MIC_AVDD ADC_AVBAT ADC_AVDDC XTALI AVSS VSS XTALO XTALI32K XTALO32K TM1 JTAG_SEL MICP MICN MIC_BIAS I I I I O A4 E6 F6 Core H3 F5 E5 Microphone A7 B7 A6 PCM2/I2S J3 I/O PAVDD RF antenna port I I I I O I I I I I I I I O I O IFVDD1P2 LNAVDD1P2 VCOVDD1P2 PLLVDD1P2 PAVDD VDDC VDDO MIC_AVDD ADC_AVBAT ADC_AVDDC IFPLL power supply RF front-end supply VCO supply RFPLL and crystal oscillator supply PA supply Baseband core supply I/O pad and core supply Microphone supply ADC supply ADC supply VSS AVSS Ground Analog ground PLLVDD1P2 PLLVDD1P2 PLLVDD1P2 PLLVDD1P2 Crystal oscillator input. See Crystal Oscillator on page 10 for options. Crystal oscillator output. Low-power oscillator input. Low-power oscillator output. RESET_N I/O PU VDDO VDDO VDDO Active-low system reset with open-drain output and internal pull-up resistor. Device test mode control. Connect to GND for all applications. ARM JTAG debug mode control. Connect to GND for all applications. MIC_AVDD MIC_AVDD MIC_AVDD Microphone positive input Microphone negative input Microphone bias supply PCM_SYNC I/O, PD VDDO K2 PCM_CLK I/O, PD VDDO Frame synchronization for PCM interface. Alternate function:
I2S word select Clock for PCM interface. Alternate function:
I2S clock Table 1. Pin Descriptions (Cont.) Pin Number Pin Name PCM_IN I/O I, PU Power Domain VDDO PCM_OUT O, PD VDDO Description Data input for PCM interface. Alternate function:
I2S data input SDA Data output for PCM interface. Alternate function:
I2S data output SCL UART_RXD I VDDO UART_TXD O, PU VDDO UART_RTS_N O, PU VDDO UART_CTS_N I, PU VDDO UART serial input Serial data input for the HCI UART interface. UART serial output Serial data output for the HCI UART interface. Request to send (RTS) for HCI UART interface. Leave unconnected if not used. Clear to send (CTS) for HCI UART interface. Leave uncon-
nected if not used. K3 J2 UART H5 H4 J4 J5 SPI_MISO_SCL SPI_MOSI_SDA SPI_CLK SPI_CSN BSC/SPI H1 G1 G2 H2 LDO Regulator Power Supplies B3 E1 Reserved F4 D5 E3 E4 D4 Reserved0 Reserved1 Reserved2 Reserved3 Reserved4 VBAT VDDC_OUT I/O I/O I/O I/O I O I I I I I VDDO VDDO VDDO VDDO BSC clock BSC data Serial flash SPI clock Serial flash active-low chip select VBAT VDDC_OUT 1.2V LDO input 1.2V LDO output VDDO VDDO VDDO VDDO VDDO Reserved. Leave unconnected. Reserved. Leave unconnected. Reserved. Connect to GND. Reserved. Leave unconnected. Reserved. Connect to GND. Table 2. GPIO Pin Descriptionsa Pin Number G7 Pin Name P0 Default Di-
rection Input POR State Floating Post-Reset Stateb Floating Power Do-
main VDDO G6 P1 Input Floating Floating VDDO C9 P2 Input Floating Floating VDDO E9 P3 Input Floating Floating VDDO G10 P4 Input Floating Floating VDDO K4 P5 Input Floating Floating VDDO Alternate Function Description GPIO: P0 Keyboard scan input (row): KSI0 A/D converter input 29 Peripheral UART: puart_tx SPI_1: MOSI (master and slave) IR_RX 60Hz_main Note: Not available during TM1 = 1. GPIO: P1 Keyboard scan input (row): KSI1 A/D converter input 28 Peripheral UART: puart_rts SPI_1: MISO (master and slave) IR_TX GPIO: P2 Keyboard scan input (row): KSI2 Quadrature: QDX0 Peripheral UART: puart_rx SPI_1: SPI_CS (slave only) SPI_1: MOSI (master only) GPIO: P3 Keyboard scan input (row): KSI3 Quadrature: QDX1 Peripheral UART: puart_cts SPI_1: SPI_CLK (master and slave) GPIO: P4 Keyboard scan input (row): KSI4 Quadrature: QDY0 Peripheral UART: puart_rx SPI_1: MOSI (master and slave) IR_TX GPIO: P5 Keyboard scan input (row): KSI5 Quadrature: QDY1 Peripheral UART: puart_tx SPI_1: MISO (master and slave) BSC: SDA Table 2. GPIO Pin Descriptionsa (Cont.) Pin Number G4 Pin Name P6 Default Di-
rection Input POR State Floating Post-Reset Stateb Floating Power Do-
main VDDO B10 P7 Input Floating Floating VDDO D7 P8 Input Floating Floating VDDO D9 P9 Input Floating Floating VDDO G8 P10 Input Floating Floating VDDO G9 P11 Input Floating Floating VDDO C10 P12 Input Floating Floating VDDO E8 P13 Input Floating Floating VDDO Alternate Function Description GPIO: P6 Keyboard scan input (row): KSI6 Quadrature: QDZ0 Peripheral UART: puart_rts SPI_1: SPI_CS (slave only) 60Hz_main GPIO: P7 Keyboard scan input (row): KSI7 Quadrature: QDZ1 Peripheral UART: puart_cts SPI_1: SPI_CLK (master and slave) BSC: SCL GPIO: P8 Keyboard scan output (column): KSO0 A/D converter input 27 External T/R switch control: ~tx_pd GPIO: P9 Keyboard scan output (column): KSO1 A/D converter input 26 External T/R switch control: tx_pd GPIO: P10 Keyboard scan output (column): KSO2 A/D converter input 25 External PA ramp control: ~PA_Ramp GPIO: P11 Keyboard scan output (column): KSO3 A/D converter input 24 GPIO: P12 Keyboard scan output (column): KSO4 A/D converter input 23 GPIO: P13 Keyboard scan output (column): KSO5 A/D converter input 22 PWM3 Triac control 3 Table 2. GPIO Pin Descriptionsa (Cont.) Pin Number J7 Pin Name P14 Default Di-
rection Input POR State Floating Post-Reset Stateb Input enable, pull-down Power Do-
main VDDO J8 P15 Input Floating Input enable, pull-up VDDO B9 P16 Input Floating Floating VDDO J10 P17 Input Floating Floating VDDO F9 H7 P18 Input Floating Floating VDDO P19 Input Floating Floating VDDO F10 P20 Input Floating Floating VDDO D10 P21 Input Floating Floating VDDO E6 P22 Input Floating Floating VDDO F6 P23 Input Floating Floating VDDO Alternate Function Description GPIO: P14 Keyboard scan output (column): KSO6 A/D converter input 21 PWM2 Triac control 4 GPIO: P15 Keyboard scan output (column): KSO7 A/D converter input 20 IR_RX 60Hz_main GPIO: P16 Keyboard scan output (column): KSO8 A/D converter input 19 GPIO: P17 Keyboard scan output (column): KSO9 A/D converter input 18 GPIO: P18 Keyboard scan output (column): KSO10 A/D converter input 17 GPIO: P19 Keyboard scan output (column): KSO11 A/D converter input 16 GPIO: P20 Keyboard scan output (column): KSO12 GPIO: P21 Keyboard scan output (column): KSO13 A/D converter input 14 Triac control 3 GPIO: P22 Keyboard scan output (column): KSO14 A/D converter input 13 Triac control 4 XTALO32K GPIO: P23 Keyboard scan output (column): KSO15 A/D converter input 12 XTALI32K Table 2. GPIO Pin Descriptionsa (Cont.) Pin Number G5 Pin Name P24 Default Di-
rection Input POR State Floating Post-Reset Stateb Floating Power Do-
main VDDO F7 P25 Input Floating Floating VDDO K8 P26 PWM0 Input Floating Input enable, pull-down VDDO K9 P27 PWM1 Input Floating Floating VDDO K7 K6 P28 PWM2 Input Floating Input enable, pull-up VDDO P29 PWM3 Input Floating Floating VDDO J9 P30 Input Floating Floating VDDO H6 P31 Input Floating Floating VDDO Alternate Function Description GPIO: P24 Keyboard scan output (column): KSO16 SPI_1: SPI_CLK (master and slave) Peripheral UART: puart_tx GPIO: P25 Keyboard scan output (column): KSO17 SPI_1: MISO (master and slave) Peripheral UART: puart_rx GPIO: P26 Keyboard scan output (column): KSO18 SPI_1: SPI_CS (slave only) Optical control output: QOC0 Triac control 1 Current: 16 mA sink GPIO: P27 Keyboard scan output (column): KSO19 SPI_1: MOSI (master and slave) Optical control output: QOC1 Triac control 2 Current: 16 mA sink GPIO: P28 Optical control output: QOC2 A/D converter input 11 LED1 Current: 16 mA sink GPIO: P29 Optical control output: QOC3 A/D converter input 10 LED2 Current: 16 mA sink GPIO: P30 A/D converter input 9 Peripheral UART: puart_rts GPIO: P31 A/D converter input 8 Peripheral UART: puart_tx Table 2. GPIO Pin Descriptionsa (Cont.) Pin Number H9 Pin Name P32 Default Di-
rection Input POR State Floating Post-Reset Stateb Floating Power Do-
main VDDO H10 P33 Input Floating Floating VDDO H8 P34 Input Floating Floating VDDO F8 P35 Input Floating Floating VDDO D8 P36 Input Floating Floating VDDO E7 P37 Input Floating Floating VDDO Alternate Function Description GPIO: P32 A/D converter input 7 Quadrature: QDX0 SPI_1: SPI_CS (slave only) Auxiliary clock output: ACLK0 Peripheral UART: puart_tx GPIO: P33 A/D converter input 6 Quadrature: QDX1 SPI_1: MOSI (slave only) Auxiliary clock output: ACLK1 Peripheral UART: puart_rx GPIO: P34 A/D converter input 5 Quadrature: QDY0 Peripheral UART: puart_rx External T/R switch control: tx_pd GPIO: P35 A/D converter input 4 Quadrature: QDY1 Peripheral UART: puart_cts BSC: SDA GPIO: P36 A/D converter input 3 Quadrature: QDZ0 SPI_1: SPI_CLK (master and slave) Auxiliary Clock Output: ACLK0 External T/R switch control: ~tx_pd GPIO: P37 A/D converter input 2 Quadrature: QDZ1 SPI_1: MISO (slave only) Auxiliary clock output: ACLK1 BSC: SCL Table 2. GPIO Pin Descriptionsa (Cont.) Pin Number D6 Pin Name P38 Default Di-
rection Input POR State Floating Post-Reset Stateb Floating Power Do-
main VDDO J6 P39 Input Floating Floating VDDO a. During power-on reset, all inputs are disabled. b. The post-reset state is the GPIO state just after a power-on reset before firmware gets loaded. Alternate Function Description GPIO: P38 A/D converter input 1 SPI_1: MOSI (master and slave) IR_TX GPIO: P39 SPI_1: SPI_CS (slave only) Infrared control: IR_RX External PA ramp control: PA_Ramp 60Hz_main Note: This content can be viewed on the web. FCC StatementFCC and ISED Module Information The module is limited to OEM installation ONLY. This module is intended for OEM integrators under the following conditions:
1. 2. 3. This module is restricted to installation in products for use only in portable applications. The antenna(s) used for this transmitter must follow the specific operating instructions for satisfying RF exposure compliance. The antenna(s) used for this transmitter must not transmit simultaneously with any other antenna or transmitter. The OEM integrator is still responsible for 1. 2. 3. ensuring that the end-user has no manual instructions to remove or install module the FCC compliance requirement of the end product, which integrates this module. Appropriate measurements (e.g. 15 B compliance) and if applicable additional equipment authorizations (e.g. Verification, Doc) of the host device to be addressed by the integrator/manufacturer. 4. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations Guidance to the Host Manufacturer:
1. We hereby acknowledge our responsibility to provide guidance to the host manufacturer in the event that they require assistance for ensuring compliance with the Part 15 Subpart B requirements. 2. The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with the Part 15 Subpart B requirements, the host manufacturer is required to show compliance with the Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the modules intentional emissions are compliant (i.e. fundamental and out of band emissions) with the Radio essential requirements. The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in the Part 15 Subpart B or emissions are complaint with the Radio aspects. The user manual of the end product should include 1. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. 2. 3. 4. the restriction of operating this device in indoor could void the users authority to operate the equipment. This device and its antenna(s) must not be co-located or operating in conjunction with any other antenna or transmitter. This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End user must follow the specific operating instructions for satisfying RF exposure compliance. 5. The FCC part 15.19 statement: This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Label of the end product:
The final end product must be labeled in a visible area with the following " Contains FCC ID: BKEHAC033B ". The end product shall bear the following 15.19 statement: This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. If the labelling area is considered too small and therefore it is impractical (smaller than the palm of the hand) to display the compliance statement, then the statement may be placed in the user manual or product packaging. ISED Statement OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed. IMPORTANT NOTE: In the event that these conditions cannot be met, then the IC authorization is no longer considered valid and the IC No. cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate IC authorization. Modular OEM Integrator Notice End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed must follow the specific operating instructions for satisfying RF exposure compliance.. The final end product must be labeled in a visible area with the following: Contains IC: 4360A-HAC033B. This device is intended only for OEM integrators under the following conditions:
1) The antenna must follow the specific operating instructions for satisfying RF exposure compliance. 2) The transmitter module may not be co-located with any other transmitter or antenna. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit suivre les instructions d'utilisation spcifiques pour satisfaire la conformit l'exposition RF. 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Modular OEM Integrator Notice IMPORTANT NOTE for OEM integrator:
This module is intended for OEM integrator. The OEM integrator is still responsible for 1. 2. 3. ensuring that the end-user has no manual instructions to remove or install module the ISED compliance requirement of the end product, which integrates this module. Appropriate measurements and if applicable additional equipment authorizations of the host device to be addressed by the integrator/manufacturer. 4. The separate approval is required for all other operating configurations, including portable configurations and different antenna configurations
This product uses the FCC Data API but is not endorsed or certified by the FCC