| submitted | available | document details (if available) | source link |
|---|---|---|---|
| September 25 2014 | September 25 2014 |
| various | Datasheet | Users Manual | 811.81 KiB | September 25 2014 |
Preliminary Datasheet AV6302 Wireless Audio Receiver General Description AV6302 The AV6301 / 6302 chipset is optimized for building wireless gaming headsets and point to multi-point audio distribution solutions such as rear speakers and subwoofers in home theater systems.The chipset is comprised of two ICs: AV6301 (sender) and AV6302
(client). These devices share the VMI RF Protocol and may be mixed and matched with other VMI chips
(AV6200 / AV6201 / AV6202). family expands increased signal The AV63xx the capabilities of Avneras world-class VMI wireless audio protocol by providing to accommodate a wide range of gaming headset applications. The AV6301 / 02 chipset achieves the goal of enabling a single core design to service multiple game platforms (PC or Console), External Digital Signal Processing (DSP) is also easily supported for all gaming platforms. flexibility routing The chip set provides all functions necessary to complete a bidirectional wireless audio link with high quality voice and music performance. Operation in the worldwide 2.4 GHz spectrum addresses the need for global application. System / Chipset Features Stereo audio path: >93 dB SNR, 20 kHz BW Mono voice path: >70 dB SNR, 6.5 kHz voice BW with on chip MIC path (>93 dB SNR with external 16 ADC) Over-the-air (OTA) serial interface: >2 kbps, bi-
directional, full duplex Advanced forward error correction coding, error detection, and audio-specific error concealment Diversity antenna support Low and Fixed Latency: <16 ms, Long Range: 15m (non-line-of-site) Auto search/sync/standby/wake-up/shutdown All Voltage Regulators on-chip Interoperability with AV6200 and AV6201 The core functionality of the AV6302 is identical to that of the AV6301 and it integrates all of the same functions. To minimize external Bill of Materials
(BOM) for a complete headset client the AV6302 integrates additional analog functions. SPI and TWI interfaces are retained as well as a full USB transceiver. Enumeration as a high current device during charging as well as simplified field update of firmware on the Headset is enabled. A complete battery charging system is added to the significant power management functions already on chip. The battery charger includes a temperature monitor and is compliant with Lithium Ion and Lithium polymer battery types. An Integrated high quality audio CODEC directly drives on-chip low impedance headphone amplifiers and interfaces to electret and condenser microphone transducers. On-chip audio DSP, for both the stereo forward audio path and mono microphone path, performs fully programmable functions including gain control, equalization and compression, providing the headset designer with the essential tools to create custom voicing across Headset models or applications. 18 General purpose I/O ports are available, including support for LEDs and Encoders. In addition, a 3 channel general purpose ADC is provided that can support up to 2 potentiometers. A unique feature of the AV6302 Client chip is its ability to accept I2S input in addition to Microphone input for advanced routing of Chat and Microphone signals. Advanced audio routing options include the ability to utilize the microphone preamp, gain control and DSP before outputting the signal to an I2S out. This is a key feature when interfacing to XBOX controller radios. CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 1 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Features On Chip Audio Codec includes Data-Converters, microphone amplifier and headphone amplifiers Audio DSP: EQ, gain control, mix-back, muting Complete Battery Charging System USB HID interface for USB compliant charging and firmware update Noise Gates on Mic and Chat paths Applications PC Game Wireless Headset Game Console Wireless Headset I2S based Wireless Audio Wireless Rear Speakers Wireless Subwoofer 18 General Purpose I/O pins with support for:
Packaging Master and Slave SPI and TWI interfaces 3 PWM outputs 2 Rotary Encoder Inputs 1 Stereo I2s Out 1 mono I2S In 1 mono I2S Out 3 Channel General Purpose ADC 3 Dedicated Analog inputs Supports 2 potentiometers - game and chat levels The AV6302 is available in an 8 x 8 mm, 56 pin QFN package and the commercial temperature range (0 to 70 degrees C) for operation over rated is CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 2 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA Revision History Revision Change Summary 0.1 0.2 0.3 Preliminary release of datasheet Audio Routing Diagram Update. Package Drawing Update. Pin Description minor updates. Add Selector Grid Update Selector Grid, Update to Front page general description and Features. 11/4/11 Release Date 9/29/11 10/28/11 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 3 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 Table of Contents 2 General Description .............................................................................................................................................................. 1 System / Chipset Features ................................................................................................................................................... 1 AV6302 ................................................................................................................................................................................. 1 AV6302 Features .................................................................................................................................................................. 2 Applications .......................................................................................................................................................................... 2 Packaging ............................................................................................................................................................................. 2 Revision History .................................................................................................................................................................... 3 Table 0-1 AV6xxx Selection Grid .......................................................................................................................................... 5 REFERENCE DIAGRAMS .......................................................................................................................................... 6 1 1.1 Wireless Headset Solution ..................................................................................................................................... 6 1.2 Functional Diagram ................................................................................................................................................ 7 1.3 Audio Signal Routing Diagram ............................................................................................................................... 7 1.4 Application Circuit - Universal Wireless Gaming Headset ...................................................................................... 8 PIN INFORMATION .................................................................................................................................................... 9 2.1 Pin Diagram ............................................................................................................................................................ 9 2.2 PIN DESCRIPTION .............................................................................................................................................. 10 ELECTRICAL SPECIFICATIONS ............................................................................................................................. 12 3.1 Absolute Maximum Ratings .................................................................................................................................. 12 3.2 DC Electrical Characteristics ................................................................................................................................ 13 3.3 Electrical Characteristics Voltage Supervisory Circuit ....................................................................................... 13 3.4 Electrical Characteristics RF Receiver .............................................................................................................. 14 3.5 Electrical Characteristics RF Transmitter .......................................................................................................... 14 3.6 Electrical Characteristics End-to-end Audio Characteristics .............................................................................. 15 3.7 Electrical Characteristics Audio DAC and Headphone Amp .............................................................................. 15 3.8 Electrical Characteristics MIC pre-amp and Voice ADC .................................................................................... 16 3.9 Electrical Characteristics Battery Charger ......................................................................................................... 16 PACKAGE INFORMATION ....................................................................................................................................... 17 4.1 Package Drawing and Details .............................................................................................................................. 17 4.2 Package Marking .................................................................................................................................................. 18 CONTACT INFO & LEGAL DISCLAIMER................................................................................................................. 19 3 4 5 List of Tables Table 0-1 AV6xxx Selection Grid .......................................................................................................................................... 5 Table 2-1 AV6302 Pin Description ...................................................................................................................................... 10 Table 3-1 AV6302 Absolute Maximum Ratings .................................................................................................................. 12 Table 3-2 AV6302 DC Electrical Characteristics ................................................................................................................ 13 Table 3-3 AV6302 Electrical Characteristics - Voltage Supervisory.................................................................................... 13 Table 3-4 AV6302 Electrical Characteristics - RF Receiver ................................................................................................ 14 Table 3-5 AV6302 Electrical Characteristics - RF Transmitter ............................................................................................ 14 Table 3-6 AV6302 Electrical Characteristics End-to-end Audio Characteristics .............................................................. 15 Table 3-7 AV6302 Electrical Characteristics - Audio DAC and Headphone Amp ............................................................... 15 Table 3-8 AV6302 Electrical Characteristics - MIC pre-amp and Voice ADC ..................................................................... 16 Table 3-9 AV6302 Electrical Characteristics - Battery Charger .......................................................................................... 16 List of Figures Figure 1-1 AV6302 Universal Gaming Headset .................................................................................................................... 6 Figure 1-2 AV6302 Block Diagram ....................................................................................................................................... 7 Figure 1-3 AV6302 Audio Routing Diagram .......................................................................................................................... 7 Figure 1-4 AV6302 Application Circuit .................................................................................................................................. 8 Figure 2-1 AV6302 Pin Diagram ........................................................................................................................................... 9 Figure 4-1 56 pin QFN Mechanical Drawing ....................................................................................................................... 17 Figure 4-2 Package Marking Layout ................................................................................................................................... 18 CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 4 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 Table 0-1 AV6xxx Selection Grid Part Number AV6200 AV6201 AV6301 AV6200 AV6202 AV6302 Role I2S IN I2S Out USB Port MIC Amp Headphone Driver Amp Battery Charger General Purpose ADCs Button Support Rotary Encoder Support LED Support I2S Loop-
Back
(external DSP) MIC path input to I2S out MIC Side-
tone Mix Game / Chat Mix on TX Game / Chat Mix at RX Yes Yes No No No No 0 Sender No No Yes Yes Audio /
Audio /
HID No No HID No No No No 0 0 Yes Yes No No No No 0 Receiver No Yes HID Yes Yes Yes Yes HID Yes Yes Yes Yes 0 3 Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes No Yes No Yes Yes Yes No Yes No Yes No N/A N/A N/A N/A No Yes N/A N/A N/A N/A Yes Yes N/A No Yes N/A N/A N/A N/A N/A N/A No No Yes CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 5 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 1 REFERENCE DIAGRAMS 1.1 Wireless Headset Solution Figure 1-1 AV6302 Universal Gaming Headset CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 6 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302Headset chipXTALBalun USB cablePrintedAntennaPrintedAntennaRF SWVbattLeftdriverRightdriverMic Li IonBatteryLEDsPOTsI2SMONOINMONOOUTSTEREO+5VD+D-Diversity controlChargeButtonsEncodersCodecXBOX ControllerMICCHAT AV6302 Datasheet (Preliminary) revision 0.3 1.2 Functional Diagram Figure 1-2 AV6302 Block Diagram 1.3 Audio Signal Routing Diagram Figure 1-3 AV6302 Audio Routing Diagram CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 7 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA PWRV3P618GPIODSCP,DSCNSPI, I2CGPIO (Buttons, LEDs)I2SAudioCODECMICNMICPVDDMICDAC_GNDHPRVCMHPLBGOUTVDDXOIREFPHYEQDigital BlockRESETNMCUXLATPXTALNGPIOSRCRFPRFNROMRAMOTP3.6VLDOVBGSUPREFDIGRegs3.3V REGPwrSWXTALVDD1P8VDDDIGVDDIORF/IF TransceiverBattChgrPWRpinCFNCFPVBATVDCVIN3ADCADCUSBDPDMHPLDACDACHPRDACMCLKWCLKBCLKI2SCLKGENI2S MONO INI2S MONO OUTI2SSTEREO OUTADCMICTONEGENERATORAUDIOEQAUDIOPROCALCAutoLevelControlMICEQRADIOMicGainMix backChat Mixback GainGainPre-AmpHP-AmpGainGainGainToneNGThresholdNoiseGateThreshold AV6302 Datasheet (Preliminary) revision 0.3 1.4 Application Circuit - Universal Wireless Gaming Headset Figure 1-4 AV6302 Application Circuit CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 8 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA 2.2KHeadphone drivers and MIC element0.22uFVDDIO0.22uF2.2uF220uF220uFto USB +5V or AC-DC adapatorto 3.6V Li Ion batteryto battery temp. sensePower (On / Off) / Pair4.7uF.1u1uFMICNMICPHPLHPRHP_GNDVBATVDC4.7uF10k10k0.1uFTSEEPROMM_SDAM_SCLChat Vol -Chat Vol +VDDIOAV63021GPIO4234GPIO3GPIO2GPIO15GPIO0678GPIO16XTALPXTALN9VDDXO101112IREFBGOUTADC03132N/CVDC33V3P6343536VBATVINBGND373839PWRTSRESETN40GPIO154142GPIO14GPIO13MICPMICNVDDMICN/CN/CRFNRFPN/CVDDRXADCN/CN/CN/CGPIO5GPIO6GPIO7GPIO8CFNGPIO9GPIO17VDDIOVDD18CFPVDDDIGDP / GPIO1015161718192021222324252656555453525150494847464513142728VCMHP_GNDADC1ADC22930HPLHPRDM / GPIO11GPIO1243442.2K2.2uF1uF.1u12pF12pF16MHz63.4K0.22uF0.1uFDSCPDSCN220Link Status220DSP ModeI2S Stereo In / OutI2S Mono OUtI2S Mono InI2S Word ClockI2S Bit ClockI2S Master ClkMuteDSP ModeENC 0ENC 0Game Vol-Game Vol+ENCoder 0(option)ENCoder 1(option)GPIO9 pin 52GPIO8 pin 53GPIO4 pin 1to USB connector2222D+D-Pin 2 DSCNPin 1 DSCPVDDIOGPIO5 pin 56Chat VolumeGame Volume1.5k10k10k1 uF8.2pFdiscretebalunSPDT RF switchANT 1ANT 08.2pF8.2pFTBDTBDTBDTBDANTENNA 0ANTENNA 1TBDTBD2.7nH1.2pF1.2pF2.7nH1.2pF1.2pFTBDTBD AV6302 Datasheet (Preliminary) revision 0.3 2 PIN INFORMATION 2.1 Pin Diagram Figure 2-1 AV6302 Pin Diagram CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 9 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302GPIO4GPIO3GPIO2GPIO1VDDXOIREFBGOUTADC0V3P6VBATVDDMICN/CN/CRFNRFPN/CVDDRXADCN/CN/CGPIO7GPIO6GPIO8VDD18CFNGPIO9GPIO5GPIO17VDDION/CN/CGPIO0GPIO16XTALPXTALN151617181920212223242526123456789101112565554535251504948474645393837363534333231424140MICNMICPVDCVINPWRBGNDTSRESETNGPIO15GPIO14GPIO13CFPVDDDIGDP / GPIO10ADC1ADC21314HPL3029HPR2728HP_GNDVCM4443 DM / GPIO11GPIO12 AV6302 Datasheet (Preliminary) revision 0.3 2.2 PIN DESCRIPTION Table 2-1 AV6302 Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-17, 19, 22-
23, 31, 51 18 20 21 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39 40 GPIO4 S_MOSI (SPI Slave) S_SDA (TWI Slave) ENC1A GPIO3 S_SCLK (SPI Slave) UART_RX PWM1 GPIO2 S_SSB (SPI Slave) UART_TX PWM0 GPIO1 DSCN PA_EN GPIO0 DSCP DSC GPIO16 I2S STEREO OUT CEN PWM2 XTALP XTALN VDDXO IREF BGOUT ADC0 ADC1 ADC2 N/C VDDRXADC RFP RFN VDDMIC MICN MICP HP_GND VCM HPL HPR VDC V3P6 VBAT VIN BGND PWR TS RESETN GPIO15 Pin Type Digital I/O Digital I/O Digital I/O Digital Output Digital Output Digital Output Analog input Analog input Analog Analog pin Description GPIO port 4; usage is programmable to GPIO OR to S_MOSI OR to S_SDA OR to Encoder resource # 1 (A) GPIO port 3; usage is programmable to GPIO OR to S_SCLK OR to UART Receiver OR to PWM resource # 1 GPIO port 2; usage is programmable to GPIO OR to S_SSB OR to The UART Transmitter OR to PWM resource # 0 GPIO port 1; Usage is programmable to GPIO OR to Diversity Switch OR to Power Amp Enable GPIO port 0; Usage is programmable to GPIO OR to Diversity Switch + OR to DSC GPIO port 16; Usage is programmable to GPIO OR to I2S port 0 Stereo Out OR to CEN OR to PWM resource #2 External crystal input External crystal input Crystal oscillator regulator bypass pin Reference current setting resistor connection Analog bypass Bandgap reference bypass and resistor pin Analog Input Analog Input Analog Input
-
Muxed ADC port 0 Muxed ADC port 1 Muxed ADC port 2 No connection Do Not Ground Bypass RF I/O RF I/O Bypass pin for Receiver IF Data Converter RF input/output positive RF input/output negative Analog bypass Microphone supply voltage bypass Analog input Analog input Analog ground Analog bypass Analog output Analog output Supply pin Bypass Bypass Analog Digital input Analog input Digital input Digital I/O Microphone pre-amp negative input Microphone pre-amp positive input Headphone ground Headphone/DAC common mode bypass pin Headphone left Headphone right 5V input supply voltage from +5V AC/DC adaptor Bypass pin for 3.6V main regulator Li Ion battery or regulator output connection Input voltage for the chip Connect directly to Ground Power on/off pin Temperature sense for battery charger RESET signal; active low; 3.3V CMOS I/O GPIO port 15; usage is programmable to GPIO OR to CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 10 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol I2S MONO OUT ENC1B PWM2 GPIO14 I2S MONO IN ENC1A PWM0 GPIO13 WCLK ENC0B PWM2 GPIO12 BCLK ENC0A PWM1 DM DP VDDDIG CFN CFP VDD18 VDDIO GPIO17 MCLK PWM1 PWM2 GPIO9 M_SSB (SPI Master) ENC0B MICIN GPIO8 M_SCLK (SPI Master) ENC0A MICCLK GPIO7 M_MOSI (SPI Master) M_SDA (TWI Master) SDA (TWI) GPIO6 M_MISO (SPI Master) M_SCL (TWI Master) SCL (TWI) GPIO5 S_MISO (SPI Slave) S_SCL (TWI Slave) ENC1B Pin Type Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Bypass Analog Analog Bypass Bypass Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Description I2S Port 1 Mono Out Data OR to Encoder resource #1 (B) OR to PWM resource # 2 GPIO port 14; usage is programmable to GPIO OR to I2S Port 2 Mono In Data OR to Encoder resource #1 (A) OR to PWM resource # 0 GPIO port 12; usage is programmable to GPIO OR to I2S Word Clock OR to Encoder resource #0 (B) OR to PWM resource #2 GPIO port 12; usage is programmable to GPIO OR to I2S Bit Clock OR to Encoder resource #0 (A) OR to PWM resource #1 USB minus i/O USB plus I/O Bypass pin for 1.35V digital core regulator Switching regulator capacitor positive Switching regulator capacitor negative Bypass pin for 1.8V digital regulator (LDO) Bypass pin for 3.3V digital I/O regulator GPIO port 17; usage is programmable to GPIO or to I2S Master Clock OR to PWM resource #1 OR to PWM resource #2 GPIO port 9; usage is programmable to GPIO or to M-SSB OR to Encoder resource # 0 (B) OR to Digital Microphone Signal Input GPIO port 8; usage is programmable to GPIO OR to M_SCLK OR to Encoder resource # 0 (A) OR to Digital Microphone Clock Input GPIO port 7; usage is programmable to GPIO OR to M-MOSI OR to M_SDA OR to SDA GPIO port 6; usage is programmable to GPIO OR to M_MISO OR to M_SCL OR to SCL GPIO port 5; usage is programmable to GPIO OR to S_MISO OR to S_SCL OR to Encoder resource # 1 (B) CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 11 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings The Absolute Maximum Rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown). Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. Table 3-1 AV6302 Absolute Maximum Ratings CONDITION Supply (relative to AGND and DGND) VDC VIN, VBAT Input Voltage Range Digital Inputs Input Voltage Range Analog Inputs Short circuit to GND (any pin) Operating Temperature Storage Temperature Lead Temperature (10s) Static Discharge Voltage HBM (All pins ) Static Discharge Voltage MM Note:
1) HBM = ESD Human Body Model; C = 100pF, R = 1k 2) MM = ESD Machine Model; C = 100pF; R = 300 MIN
-0.3
-0.3
-0.3
-0.3
--
-40
-40
--
3000 300 MAX Units 6.0 4.5 3.6 3.6 continuous
+85
+100
+300 V V V V C C C V V CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 12 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 3.2 DC Electrical Characteristics Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-2 AV6302 DC Electrical Characteristics CONDITIONS MIN TYP MAX UNIT PARAMETER VDC Supply Voltage Input VIN Supply Voltage Range VBAT Voltage Input Range V3P6 Internally regulated voltage VDDIO (Digital 3.3V I/O) Reg. Voltage Internally regulated voltage VDDDIG (Digital Core) Reg. Voltage Internally regulated voltage VDD1P8 Supply Current (IVIN) Internally regulated voltage Shutdown Mode (PWR pin active) Client Sleep Mode Client No audio (header only) Link mode Client Std. Headset Link Mode CMOS I/O Logic Levels 3.3V I/O Input Voltage Logic Low, VIL Input Voltage Logic High, VIH VVDDIO = 3.3V VVDDIO = 3.3V Output Voltage Logic Low, VOL VVDDIO = 3.3V ; ILOAD=1mA Output Voltage Logic High, VOH VVDDIO = 3.3V; ILOAD=1mA PWR pin headset chip Low threshold High threshold PWR pin current source GPIO Pin source current 4.4 3.2 0 2.0 2.9 1.2 5.0 3.6 3.6 3.3 1.35 1.8 25 1.2 16 46 4 5.5 4.3 4.3 50 19 55 0.8 0.4 0.6 3.0 V V V V V V V uA uA mA mA V V V V V V uA mA 3.3 Electrical Characteristics Voltage Supervisory Circuit Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V or VIN = 3.6V. Table 3-3 AV6302 Electrical Characteristics - Voltage Supervisory PARAMETER CONDITIONS MIN TYP MAX UNIT Voltage Monitor Low Thres. (assert reset) Monitoring the voltage on V3P6 Voltage Monitor High Thres. (de-assert reset) Monitoring the voltage on V3P6 Brownout bandwidth Reset Threshold (assert) Reset Threshold (de-assert) Monitoring the voltage on V3P6 RESETN Minimum Time 0.1uF external capacitor VDC_OK threshold Rising falling 2.7 3.0 100 2.2 1.2 11 4.1 3.9 V V kHz V V ms V V CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 13 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 3.4 Electrical Characteristics RF Receiver Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; RF Channel Freq = 2403.35-2477.35MHz, measured at the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-4 AV6302 Electrical Characteristics - RF Receiver PARAMETER CONDITIONS MIN TYP MAX UNIT RF Channel Frequency Range LO frequency (driving the mixers) RF carrier frequency 2402 2478 2403.35 2479.35 Modulated Signal Offset from LO 1.35 Sensitivity (Note 1) TA=25C, LNA = High gain mode; max IF gain
-86 Max input signal (desired signal) (Note 1) TA=25C, LNA = low gain mode; min IF gain Input Blocker Level High Gain mode
> 2MHz offset Out-of-band blocker level
<2400 MHz; >2483.5 MHz Spurious RF outputs
<2400 MHz
>2483.5 MHz Note 1: Sensitivity and max signal level are defined as the onset of 0.2% BLER Block Error Rate.
-89
-5
-45 TBD
-75
-75 MHz MHz MHz dBm dBm dBm dBm dBm dBm 3.5 Electrical Characteristics RF Transmitter Operating Conditions: VDC = 4.4V to 5.5V, VDDIO = 3.3V, TA = 0C to +70 C; RF Channel Freq = 2403.35-2477.35MHz, measured at the single-ended input of the RF balun (with external impedance matching). Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-5 AV6302 Electrical Characteristics - RF Transmitter PARAMETER CONDITIONS MIN TYP MAX UNIT RF Channel Frequency Range LO frequency (driving the mixers) RF carrier frequency 2402 2478 2403.35 2479.35 Modulated Signal Offset from LO Modulated Signal Bandwidth
-10dB point Output Power Output harmonics Pi/4 DQPSK modulated signal ACPR: Adj < -23dBc, Alt < -30dBc 2nd harmonic, Pout = 0dBm 3rd harmonic, Pout = 0dBm Out-of-band Spurious Output RF < 2390MHz, > 2483.5MHz, 1MHz RBW Output Noise Floor RF < 2390MHz, > 2483.5MHz, 1MHz RBW 1.35 1.8
+2
-52
-50
<-62
<-62 MHz MHz MHz MHz dBm dBm dBm dBm dBm CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 14 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 3.6 Electrical Characteristics End-to-end Audio Characteristics Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-6 AV6302 Electrical Characteristics End-to-end Audio Characteristics PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Audio Bandwidth Voice Bandwidth Audio Latency Voice Latency Headset Mode Forward stereo path Headset Mode Reverse mono path End-to-end audio BW; 0.1dB point End-to-end audio BW; 0.1dB point AV6301 USB to AV6202 analog output AV6301 to AV6302 I2S output AV6302 analog input to AV6301 USB output 96 68 20 6.5
<16
<16
<16 dB dB kHz kHz msec msec msec 3.7 Electrical Characteristics Audio DAC and Headphone Amp Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-7 AV6302 Electrical Characteristics - Audio DAC and Headphone Amp PARAMETER CONDITIONS MIN TYP MAX UNITS Full scale output voltage swing 0dB FS, sine wave, gain = 0dB SNR (A-weighted) Dynamic Range Total Harmonic Distortion I2S test signal input I2S test signal input 1kHz, RL=32, 0dB FS, PO=1mW, gain=0dB 1kHz, RL=32, -3dB FS, PO=10mW, gain=0dB 1kHz, RL=32, -13dB FS, PO=1mW, gain=0dB Full power bandwidth (-1dB point) 0dB FS, sine wave, gain = 0dB Bandwidth (-1dB point) Max Output Power I2S test signal input RL=32, signal=FS, gain=0dB, THD < 10%
RL=16, signal=FS, gain=0dB DAC Channel Separation 1kHz, -3dB FS and no signal Output Voltage Noise 20Hz 20kHz; all zeros signal Mute activated 2.0 96 96
-60
-70
-80 20 20 15 30 70 15 10 Vpp dB dB dBc dBc dBc kHz kHz mW mW dB Vrms Vrms CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 15 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 3.8 Electrical Characteristics MIC pre-amp and Voice ADC Operating Conditions: VDC = 4.4V to 5.5V or VIN = 3.2V to 4.3V, VDDIO = 3.3V, TA = 0C to +70 C; Typical specifications at TA = 25C, VDC = 5.0V or VIN=3.6V. Table 3-8 AV6302 Electrical Characteristics - MIC pre-amp and Voice ADC PARAMETER Max Input Signal Level SNR Dynamic Range THD Bandwidth (-1dB) Input Equivalent Noise Input Resistance Input Capacitance MIC Gain range MIC Gain Steps CONDITIONS Max gain setting Min gain setting A-weighted, 0dB gain, fS=16ksps A-weighted, 0dB gain, fS=16ksps
-3dB input, 0dB gain I2S test output Min to max gain range Combination of coarse and fine register setting MIN TYP MAX UNITS 4 450 68 68
-60 6.5 TBD TBD TBD 34 TBD TBD 1 mVrms mVrms dB dB dBc kHz Vrms pF dB dB 3.9 Electrical Characteristics Battery Charger Operating Conditions: TA= 0C to +70 C, VDC VBAT + 0.3V; Typical specifications at TA = 25C, VDC = 5.0V Table 3-9 AV6302 Electrical Characteristics - Battery Charger PARAMETER VDC Input Voltage Range Maximum ICH (Note 1) Temperature Sense Shutoff Voltage Temperature Sense Threshold CONDITIONS VVDC input Deep-discharged battery state;
VBAT < 3.15V High Low High, Rising High, Falling Low, Falling Low, Rising MIN 4.4 TYP 5.0 500 VDDIO *0.8 VDDIO * 0.5 VDDIO*0.80 VDDIO*0.76 VDDIO*0.50 VDDIO*0.52 MAX UNIT 5.5 680 V mA V V V V V Notes:
Note 1: Maximum constant charge current is relative to VDC VBAT and TA CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 16 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 4 PACKAGE INFORMATION 4.1 Package Drawing and Details Figure 4-1 56 pin QFN Mechanical Drawing CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 17 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 4.2 Package Marking A V D D D D C C Y Y W W X X L L L L L L T T A Figure 4-2 Package Marking Layout Abbreviations:
AVDDDD Product number (i.e. AV6302) CC YY WW XX Country Code (i.e. MY for Malaysia) 2 digit year code 2 digit work week Production revision LLLLLL Silicon Lot number TT A Wafer split (1 by default) Assembly Lot CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 18 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA AV6302 Datasheet (Preliminary) revision 0.3 5 CONTACT INFO & LEGAL DISCLAIMER Avnera Corporation 16505 Bethany Court, Suite 100 Beaverton, Oregon 97006 U.S.A. Main: +1.503.718.4100 Fax: +1.503.718.4101 www.avnera.com Avnera Corporation reserves the right to make changes without notice to the product to improve function, reliability, or performance. Avnera Corporation does not assume any liability arising from the application or use of the products or circuits described herein. CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 19 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA
This product uses the FCC Data API but is not endorsed or certified by the FCC