| submitted | available | document details (if available) | source link |
|---|---|---|---|
| January 10 2020 | February 24 2020 | zhangzhr TextMaker |
| various | User manual | Users Manual | 2.32 MiB | January 10 2020 / February 24 2020 | delayed release |
2.4GHz Module DKL 1613_V.1 User Manual Single Chip 2.4GHz Module http://www.panchip.com Copyright 2015 Panchip Electronics 2.4GHz Module TV and STB remote controls Wireless Mouse and keyboard Toys and wireless audio Wireless gamepads Active RFID Smart home automation FEATURES FEATURES FEATURES Low Power 16mA TX at 0dBm output 15mA RX at 1Mbps air data power rate 2uA in power down Low Cost BOM Few external components Four Capacitors, One crystal oscillator High Performance Excellent Receiver sensitivity
-88dBm@1Mbps
-93dBm@250Kbps Programmable Output Power Up to 13dBm APPLICATIONS APPLICATIONS APPLICATIONS http://www.panchip.com Copyright 2015 Panchip Electronics 2.4GHz Module GENERAL DESCRIPTION GENERAL DESCRIPTION GENERAL DESCRIPTION The XN297L is a single chip 2.4GHz transceiver, designed for operation in the worldwide ISM frequency band at 2.400~2.483GHz. The XN297L integrates radio frequency (RF) transmitter and receiver, frequency synthesizer, crystal oscillator, baseband GFSK modem, and other function blocks. The XN297L supports multiple networks and communication with ACK. TX power, frequency channel, and data rate can be set by SPI. 1Mbps, 250kbps optional data rate Support 32 and 64 bytes payload length Compact 20-pin 33mm QFN package Support 20ppm 16MHz crystal GFSK Modulation Up to 8Mbps SPI interface rate Operating voltage is 2.2V~3.3V Support automatic reply and automatic retransmission Support Data whitening and CRC Support RSSI detector http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module lectrical Characteristics lectrical C 111 EEElectrical C haracteristics haracteristics Table1 XN297L Electrical Characteristics Symbol at VCC = 3V5%, T=25 Min Parameter Max Unit Condition Sleep Standby I Standby III Standby TX at -35dBm output TX at -20dBm output power power TX at 0dBm output power TX at 2dBm output power TX at 8dBm output power TX at 13dBm output power RX at 1Mbps RX at 250kbps General RF PLL Programming resolution Crystal frequency Frequency deviation at Frequency deviation at 250kbps 1Mbps Channel spacing at 250Kbps Channel spacing at 1Mbps Operating frequency 2400 2483 MHz DR Data rate 0.25 1 250 KHz Transmitter Typical output power Output Power Range 2
-35 13 13 dBm dBm 20dB Bandwidth for Modulated Carrier at 1Mbps http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co uA uA uA uA mA mA mA mA mA mA mA mA MHz MHz Mbp s KHz MHz MHz MHz Typ 2 30 650 780 9 9.5 16 19 30 66 15.5 15 16 125 160 1 1 8 1 20dB Bandwidth for Modulated Carrier at 250Kbps Receiver Maximum received signal at <0.1% BER Sensitivity (0.1%BER)
@1Mbps Sensitivity (0.1%BER)
@250Kbps C/I Co-channel (@1Mbps) C/I Co-channel (@250Kbps) 1st Adjacent Channel Selectivity C/I 2nd Adjacent Channel Selectivity C/I 3rd Adjacent Channel Selectivity C/I 4th Adjacent Channel Selectivity C/I 5th Adjacent Channel Selectivity C/I 6th Adjacent Channel Selectivity C/I 1st Adjacent Channel Selectivity C/I 2nd Adjacent Channel Selectivity C/I 3rd Adjacent Channel Selectivity C/I 4th Adjacent Channel Selectivity C/I 5th Adjacent Channel Selectivity C/I 6th Adjacent Channel Selectivity C/I 2.4GHz Module 500 KHz 0
-87
-93 10 1
-18
-23
-28
-32
-35 2
-8
-18
-24
-28
-32
-35 3 0 3 dBm dBm dBm dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc V V V V V Operating conditions Supply voltage 2.2 3.3 Ground Output high level voltage Output low level voltage Input high level voltage VDD-0. 3 VSS 2.0 VDD VSS+0. 3 3.6 http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module VSS+0. 3 V Input low level voltage VSS
* Note: In the channels, such as 2416 and 2432 MHz, integer times of 16MHz crystal, receiver sensitivity degrades about 2dB; and modulation quality of the emission signal (EVM) falls by 10%.
* Note: In 250Kbps mode, payload length should not be more than 16 bytes, because of frequency drift in open-loop transmitting mode. Absolute Maximum Ratings Absolute Maximum R 222 Absolute Maximum R atings atings Table 2 XN297L Absolute Maximum Ratings Symbo l Condition Parameter Min Typ Max maximum ratings Supply voltage Input voltage Output voltage Total Power Dissipation TA=-40~85 Operating Temperature Storage Temperature
-0.3
-0.3 VSS
-40
-40 Unit V V mW 3.6 5 VDD 300 85 125
* Note: Exceeding one or more of the limiting values may cause permanent damage to XN297L.
* Caution: Electrostatic sensitive device, comply with protection rules when operating. http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module 555 Operational Modes Operational Modes Operational Modes This chapter describes XN297Ls all kinds of working modes, and is used to control the chip into the working mode method. XN297Ls state machine is controlled by chip internal registers configuration values and external signal pin. Table 4 shows six kinds of work modes, which gives the corresponding mode of control registers and FIFO registers. Table 4 Control BIT and Function Description MODE PWR_DN STB1 STB3 STB2 RX TX 1 0 0 X X X X X 1 1 0 X X X X 1 1 1 0 X X 1 1 1 1 X 1 1 1 0 X State Diagram State D 555.1.1.1 State D iagram iagram CONTROL BIT PWR_UP EN_PM CE PRIM_RX FUNCTION DESCRIPTIO N SPI operation Keep register value Crystal oscillator work Crystal oscillator output Main power management work TX work RX work 0 0 0 X X X X X X State Diagram State D 555...222 State D iagram iagram Figure 3 shows XN297Ls working state diagram, giving six working modes between jump XN297L in VDD is larger than 2.2V to work properly into sleeping http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module mode, the MCU can be sent via SPI configuration commands and CE pin into the other five states. Figure3 State Diagram 555...333 IRQ PIN IRQ PIN IRQ PIN When the status register TX_DS RX_DR or MAX_RT is 1, reporting and the corresponding interrupt enable bit is 0, IRQ pins interrupts trigger. The MCU writes 1 to the corresponding interrupt source, clear the interrupt. IRQ pins interrupt trigger can be blocked or enabled, report by setting the interrupt enable bit is 1, ban IRQ pins interrupt triggered. http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 6 DATA FIFO 6 DATA FIFO 6 DATA FIFO 2.4GHz Module The XN297L contains TX FIFO and RX FIFO. It is sent via SPI read/write command. Figure 4 FIFO Block Diagram It writes TX FIFO in TX mode by W_TX_PAYLOAD and W_TX_NO_ACK instructions. If MAX_RT interruption, data will be cleared in the TX FIFO. It reads PAYLOAD in RX FIFO in receiving mode by R_RX_PAYLOAD, and it reads the length of the PAYLOAD by R_RX_PL_WID instruction. FIFO_STATUS register indicates FIFO states. http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module 777 SPI CONTROL SPI CONTROL SPI CONTROL The XN297L is controlled by SPI port for read and write registers, and command. The XN297L is a slave terminal, SPI transfer rate depends on the MCU interface speed, and the maximum data transfer rate is 8 Mbps. SPI interface is a standard SPI interface are shown in table 5, you can use the general I/O for MCU simulation SPI interface. CSN pin to 0, SPI interface instructions to be performed. From 1 to 0 a CSN pin changes execute one instruction. After the change from 1 to 0 CSN pin can be read by MISO status register contents. Table 5 SPI Port DIRECTION I/O Input Input Input FUNCTION DESCRIPTION SPI Chip Select Clock Serial Data Input Output Serial Data Output PIN CSN SCK MOS I MIS O 1 SPI Commands 1 SPI 7.7.7.1 SPI Commands Commands Table 6 SPI Command Format
<Command word: MSBit to LSBit (one byte)>
<Data bytes: LSByte to MSByte, MSBit in each byte first>
COMMAND COMMAN D WORD
(BINARY) DATA BYTES R_REGISTER 000A AAAA 1 to 5 AAAAA =5 bit Register Map W_REGISTER 001A AAAA 1 to 5 Address OPERATION Read registers. Address Write registers. AAAAA = 5 bit Register Map Executable in power down or standby modes only. Read RX-payload. A read operation starts at byte 0. Payload is deleted from RX R_RX_PAYLOAD 0110 0001 1 to 32/64 http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module FIFO after it is read. Used in RX mode. Write TX-payload. A write operation starts at byte 0. Used in TX payload. Flush TX FIFO, used in TX Flush RX FIFO, used in RX mode mode Used for a PTX device, reuse last transmitted payload. Packets are repeatedly retransmitted as long as CE is high. TX payload reuse is active until W_TX_PAYLOAD or FLUSH_TX is executed. This write command followed by data 0x73 activates the following features:
R_RX_PL_WID W_TX_PAYLOAD_NOACK W_ACK_PAYLOAD This is executable in power down or standby modes only. This write command followed by data 0x8C deactivates the following features:
Read RX-payload width for the top, R_RX_PAYLOAD in the RX FIFO. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum two ACK packet payloads can be pending. Payloads with same PPP are handled using first in
- first out principle. Write Payload to be transmitted, used in TX mode. Disable auto ACK on this packet. SPI command CE internal logic 1, use the command followed by the data 0x00 W_TX_PAYLOAD 1010 0000 1 to 32/64 FLUSH_TX 1110 0001 FLUSH_RX 1110 0010 REUSE_TX_PL 1110 0011 0 0 0 ACTIVATE DEACTIVE 0101 0000 1 R_RX_PL_WID 0110 0000 0 W_ACK_PAYLOAD 1010 1PPP 1 to 32/64 W_TX_PAYLOAD_NO ACK 1011 0000 1 to 32/64 CE_FSPI_ON 1111 1101 1 http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co CE_FSPI_OFF 1111 1100 1 RST_FSPI_HOLD RST_FSPI_RELS 0101 0011 NOP 1111 1111 1 0 2.4GHz Module SPI command CE internal logic 0, use the command followed by the data 0x00 With the command followed by data 0x5A, makes the XN297L into reset and maintain With the command followed by data 0xA5, release the XN297 reset and start to work normally No Operation. The R_REGISTER and W_REGISTER commands can operate on single or multi-byte registers. When accessing multi-byte registers, firstly read or write the MSBit of LSByte. Terminate the writing before all bytes in a multi-byte register are written, then it leaves the unwritten MSByte(s) unchanged. For example, the LSByte of RX_ADDR_P0 can be modified by writing only one byte to the RX_ADDR_P0 register. 777...222 SPISPISPI Timing Timing Timing Figure 5 SPI read operation Figure 6 SPI Write Operation http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module Figure 7 SPI NOP Timing Diagram ontrol Registers ontrol 8 C8 C8 Control Registers Registers You can configure and control XN297L by accessing the register map through the SPI by using read and write commands. Table 9 Control Registers(The Registers with * need to be modified) ADDRESS HEX 00*
CONFIG REGISTERS BIT AFTER EXPLANATION DEFAULT VALUE RESTORATION READ AND WRITE EN_PM 7 R/W MASK_RX_DR 6 R/W MASK_TX_DS 5 R/W 0 0 0 Configuration Register Into STB3 mode When PWR_UP=1 1: Into STB3 mode 0: Into STB1 mode When changing to other modes, wait more than 50us in STB3 mode The interrupt when receiving data successfully reports to the Enable_bit. 1: Interrupt not reflected on the IRQ pin. 0: Reflect RX_DR as active low interrupt on the IRQ pin. The interrupt when sending data successfully reports to the Enable_bit. 1: interrupt not reflect on the IRQ pin. 0: reflect TX_DS as active low interrupt on the IRQ pin. http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co MASK_MAX_RT 4 R/W EN_CRC N/A PWR_UP PRIM_RX EN_AA Enhanced Burst Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 Reserved ERX_P5 ERX_P4 ERX_P3 ERX_P2 ERX_P1 ERX_P0 01 02 EN_RXADDR 3 2 1 0 7:6 5 4 3 2 1 0 7:6 5 4 3 2 1 0 7:2 0 1 0 0 0 00 0 0 0 0 0 1 00 0 0 0 0 0 1 2.4GHz Module to reports interrupt interrupt not reflected on the IRQ The reaching maximum transmission times when sending data unsuccessfully the Enable_bit 1:
pin. 0:
interrupt on the IRQ pin. Enable CRC.. 1: CRC enable2byte 0: CRC disable and verification. reflect MAX_RT as active low The Enable_bit 1: POWER_UP 0: POWER_DOWN RX/TX Control 1: PRX 0: PTX The auto_response enable of reception channel If the EN_AA of receiving terminal isnt 0X00, to enhancement mode the system is set R/W Retain and set to 1 R/W R/W R/W R/W Only 00 allowed R/W Enable pipe5 auto-response R/W Enable pipe4 auto-response R/W Enable pipe3 auto-response R/W Enable pipe2 auto-response R/W Enable pipe1 auto-response R/W Enable pipe0 auto-response Enable reception channel R/W Only 00 allowed R/W enable data pipe 5 R/W enable data pipe 4 R/W enable data pipe 3 R/W enable data pipe 2 R/W enable data pipe 1 R/W enable data pipe 0 RX/TX Address Field Width 00: Illegal 01: 3 bytes 10: 4 bytes 11: 5 bytes LSByte is used if address width is below 5 bytes 03 SETUP_AW Reserved 000000 R/W Only 000000 allowed Setup of Address Widths AW 1:0 11 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 04 SETUP_RETR ARD 7:4 0000 R/W ARC 3:0 0011 R/W 05 RF_CH Reserved RF_CH 7 6:0 06*
RF_SETUP 0 R/W Only 0 allowed 1001110 RF_DR 7:6 00 PA_GC 5:3 111 PA_PWR 2:0 111 07 STATUS Reserved RX_DR 7 6 5 0 0 0 TX_DS R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module Setup of Automatic Retransmission Auto Retransmit Delay 0000 :250s 0001 :500s 0010 :750s 1111: 4000s Auto retransmit count 0000: re-transmit disabled 00011111: Enhance mode 0001: up to 1 re-transmit on fail of AA 0010: up to 2 re-transmit on fail of AA 1111: up to 15 re-transmit on fail of AA RF channel R/W R/W Set the frequency channel RF_CH +
2400 RF Setup Register Data rate 01: retain 00: 1Mbps 11: 250kbps 10: retain The output amplitude of PAs driver can adjust the transmitting power. 111: The amplitude is high. 000: The amplitude is low. The output amplitude of PAs output power can adjust the transmitting power. 111: The output power is high. 000: The output power is low. Status Registers R/W Only 0 allowed R/W R/W Data ready RX FIFO interrupt. Asserted R/W when new data arrives RX FIFO. Write 1 to clear bit. Data sent TX FIFO interrupt. Asserted when packet if AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. transmitted on TX. R R R R R R R R R R R R 2.4GHz Module to for 15, read the payload retransmitted packets. lost packets. The counter Maximum number of TX retransmits interrupt write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable furtuer communication. Data pipe number available for reading from RX_FIFO. 000-101: pipe number 110: Not Used 111: RX_FIFO empty TX FIFO full flag 1: TX FIFO full 0: Available locations in TX FIFO Transmit Observe Register is Count overflow protected and discontinues at max until reset. The counter is reset by writing to RF_CH. Count The counter is reset when transmission of a new packet starts. Data registersDATAOUT_SEL=0 The 3rd bit of value(the maxmum bit)(for test) The 2nd bit of value(the maxmum bit)(for test) The value(the maxmum bit)(for test) The 0 bit of receivers RSSI value(the maxmum bit)(for test) The 3rd bit of packet(the maximum bit) The 2nd bit of receivers receiving packet The 1st bit of receivers receiving packet The 0 bit of packet Receive address data pipe 0.5 bytes maximum length.(LSByte is written first. Write the number of bytes defined by SETUP_AW) Receive address data pipe 1 bytes maximum length.(LSByte is written first. Write the number of bytes defined by SETUP_AW) receivers receiving receivers receiving receivers RSSI receivers RSSI receivers RSSI 1st bit of MAX_RT 4 0 R/W RX_P_NO 3:1 111 TX_FULL 0 08 OBSERVE_TX PLOS_CNT 7:4 ARC_CNT 3:0 09*
DATAOUT ANADATA7 ANADATA6 ANADATA5 ANADATA4 ANADATA3 ANADATA2 ANADATA1 ANADATA0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0A RX_ADDR_P0 39:0 0B RX_ADDR_P1 39:0 0xE7E7E 7E7E7 0xC2C2C 2C2C2 R/W R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 0C RX_ADDR_P2 7:0 0xC3 R/W 0D RX_ADDR_P3 7:0 0xC4 R/W 0E 0F RX_ADDR_P4 7:0 0xC5 R/W RX_ADDR_P5 7:0 0xC6 R/W 10 TX_ADDR 39:0 R/W 0xE7E7E 7E7E7 11 RX_PW_P0 Reserved 7 0 R/W Only 0 allowed RX_PW_P0 6:0 0000000 R/W 12 RX_PW_P1 Reserved 7 0 R/W Only 0 allowed RX_PW_P1 6:0 0000000 R/W 13 RX_PW_P2 Reserved 7 0 R/W Only 0 allowed RX_PW_P2 6:0 0000000 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module Receive address data pipe 2 bytes maximum length. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8]
Receive address data pipe 3 bytes maximum length. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8]
Receive address data pipe 4 bytes maximum length. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8]
Receive address data pipe 5 bytes maximum length. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8]
Transmit address. Used for a PTX device only.(LSByte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX Device with enhanced shockburst enabled. The data length of data pipe 0s RX payload Number of bytes in RX payload in data pipe 0(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64=32/64 bytes The data length of data pipe 1s RX payload. Number of bytes in RX payload in data pipe 1(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64=32/64 bytes The data length of data pipe 2s RX payload. Number of bytes in RX payload in data pipe 2(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64 = 32/64 bytes 14 RX_PW_P3 Reserved 7 0 R/W Only 0 allowed RX_PW_P3 6:0 0000000 R/W 15 RX_PW_P4 Reserved 7 0 R/W Only 0 allowed RX_PW_P4 6:0 0000000 R/W 16 RX_PW_P5 Reserved 7 0 R/W Only 0 allowed RX_PW_P5 6:0 0000000 R/W 17*
FIFO_STATUS N/A 7 6 5 4 3 2 1 TX_REUSE TX_FULL TX_EMPTY N/A N/A RX_FULL 0 0 0 1 0 0 0 R R R R R R R http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module The data length of data pipe 3s RX payload. Number of bytes in RX payload in data pipe 3(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64 = 32/64 bytes The data length of data pipe 4s RX payload. Number of bytes in RX payload in data pipe 4(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64 = 32/64 bytes The data length of data pipe 5s RX payload. the high. packet Number of bytes in RX payload in data pipe 5(1 to 32/64 bytes) 0 pipe not used 1=1 byte 32/64 = 32/64 bytes FIFO Status Register retain Reuse last transmitted data packet if set repeatedly retransmitted as long as CE is high. TX_REUSE is set by the SPI command REUSE_TX_PLand is reset by the SPI commands W_TX_PAYLOAD_NOACKDEACTIVATE FLUSH TX. TX FIFO full flag. 1:TX FIFO full. 0:Available locations in TX FIFO. TX FIFO empty flag. 1:TX FIFO empty. 0:Data in TX FIFO. Retain Retain RX FIFO full flag. 1: RX FIFO full. RX_EMPTY 0 N/A TX_PLD 255:0 N/A RX_PLD 255:0 19*
DEMOD_CAL 7:0 R W R 1 X X 0 CHIP 7 R/W CARR 6:5 00 R/W GAUS_CAL 4:1 0111 R/W 2.4GHz Module 0: Available locations in RX FIFO. RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. Written by separate SPI command TX data payload register 2-32 bytes or 1-
64 bytes FIFO. Written by separate SPI command RX data payload register 2-32 bytes or 1-
64 bytes FIFO. All RX channels share the same FIFO. Modulation-demodulation parameter registers(configure by program) Configure if the chip is in test mode 1: Enter test mode 0: Quit test mode Configure if the chip is in carrier test mode 11: Enter single carrier mode and the chip is set to 1 00: Quit single carrier mode The amplitude adjustment of signal from Gaussian filter to DAC, which is one of the key factor to decide the value transmitting modulation frequency offset. of 1111: The amplitude is high
. 1000: The amplitude is average
. 0000: The amplitude is high If the scrambler function is enabled. Open scrambler function can make a vernacular operation to the ready-to-
sent data, which reduces the length of 1 & the length of 0. enable srambler function needs a same configuration in both of the receiving and transmitting terminals. 1: Enable scrambler function 0: Turn off scrambler function Add RF recommended) registers(Default value is Scramble_en 0 1 R/W 1A*
RF_CAL2 N/A 47:0 47:46 BW_500K 45 01 0 R/W Retain R/W The bandwidth of filter 0: Narrow bandwidth http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co GC_500K 44 IRQ_inv_sel 43 CLKOUT_Z_sel 42 MISO_Z_sel 40 IRQ_Z_sel 39 1 0 0 0 0 0 R/W R/W R/W R/W R/W CE_L_sel 41 R/W PA_ramp_sel 38:37 01 R/W OSC_IC 36 1 R/W CLK_SEL 35:34 10 R/W EN_STBII_RX2T X 33 1 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module in high in high the pins of CE weak pulldown 1: Wide bandwidth The gain of filter 0Low gain 1High gain If the output of IRQ(EN_PA)is inverse. 1The output is inverse 0The output isnt inverse If the pin of CLKOUT is output in high resistance. 1CLKOUT PIN is output resistance. 0CLKOUT PIN is as output. If resistors are enabled. 1The pins of CE weak pulldown resistors are enabled 0The pins of CE weak pulldown resistors arent enabled. If the pins of MISO is output in high resistance. 1MISO PIN is output resistance. 0MISO PIN is output. If the pins of IRQ are output in high resistance. 1IRQ PIN is resistance. 0IRQ PIN is output. Choose the way of PA ramp up 00No ramp up 014us ramp each step 10ramp begins with half current 112us ramp each step Choose OSCs exciting current 11 00.75 Choose the output internal crystal signal. 00: 16MHz 01: 8MHz 10: 4MHz 11: 2MHz PTX terminal enters standby-II mode from briefly transmitting mode receiving mode. The other LDOs except DVDD are once when entering standy-II mode. frequency of converting powered output down when high into in 2.4GHz Module of of the the gain receiving bandwidth 1: Enable 0: Disenable 1dB Choose receiving intermediate-frequency filter. 1: 1 0: 0.85 Choose intermediate-frequency filter. 1: 5dB 0: 19dB Choose the driving MIXH current. 00: 600uA 01: 800uA 10: 1mA 11: 1.2mA Choose the VCO load capacitors. 00: There are few capacitors, and the frequency of VCO is high. 11: There are more capacitors, and the frequency of VCO is low. Choose the autocorrection reference voltage. 1: 1.15V 0: 1.25V The process of VCO single trigger autocorrection when is configured from 0 to 1. In addition, when changing work channel and entering sending and receiving state, the VCO can also be autocorrected. Choose the driver load capacitors. 000: 399fF 100: 171fF 111: 0fF Choose bandwidth. 1: Wide bandwidth 0: Narrow bandwidth Choose frequency(load capacitors) 00: 2.45GHz 01: 2.52GHz 10: 2.59GHz 11: 2.66GHz Enable Receiving bandwidth filters autocorrenction function. 1: Enable resonant filtering DACs LNAs this the bit BPF_CTRL_BW 32 BPF_CTRL_GAIN 31 R/W R/W VCOBUF_IC 30:29 01 R/W VCO_CT 28:27 01 R/W CAL_VREF_SEL 26 R/W 0 1 1 0 SPI_CAL_EN 25 R/W PREAMP_CTM 24:22 011 R/W DA_LPF_BW 21 1 R/W RX_CTM 20:19 01 R/W RCCAL_EN 18 1 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co EN_VCO_CAL 17 1 R/W PRE_BC 16:14 100 R/W VCO_CODE_IN 13:10 1000 R/W RCCAL_IN 9:4 010100 R/W CPSEL 3:2 01 R/W DATAOUT_SEL R/W Configure the data-read bit to 0. 1 0 0 1 RSSI_SEL R/W 1B DEM_CAL2 23:0 PIN 23:21 000 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module VCOs enable 0: Disable The to bit autocorrenction 1: Enable 0: Disable Choose the prescalers direct current 000: 1 001&010: 1.5 100&011: 2 101&110: 2.5 111: 3 Choose VCOs frequency band Only enable when EN_VCO_CAL is 0 1111: High frequency band 0000: Low frequency band intermediate Low intermediate mid-
Configure the receiving band-pass filters frequency correction. Only available when RCCAL_EN is 0 111111:
frequency 000000: High frequency Configure the PLL charge pumps current. RX 00: 26uA 01: 26uA 10: 52uA 11: 78uA 26uA 52uA 78uA 104uA intermediate mid-
TX Choose RSSI signal sampling points. 1: The RSSI signal goes through filter. 0: The RSSI signal doesnt go through filter. Replenish and demodulate reference registers(use default value in general) operation mode Configure the output PIN after the chip entering test mode(MISO pin/IRQ pin) 000(the chip is 0) data output and interrupt output 000(the chip is 1) mode output 110(the chip is 1) mode testing receiving output in 2 different ways in testing sensitivity demodulate data and clock EN_RX 20 DELAY1 19 R/W R/W DELAY0 18 R/W TH1 17 R/W PTH 16:13 0110 R/W SYNC_SEL 12 R/W DECOD_INV 11 R/W 0 0 0 1 1 1 GAIN1 10:7 1110 R/W GAIN2 6:1 000101 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module the the is enabled, demodulator both limit I and Q If both the receiving channel and PLL are open at the same time 1: Open at the same time 0: Open at the different time If the PLLs open loop is enabled, the enabling of PLLs open loop state can test the transmitting of carrier drift 1: PLL open loop enables. 0: PLL open loop is controlled by state machine. If the demodulator can add the initial offset, which doesnt add the initial offset can test the receiving sensitivity. 1: do not add initial offset. 0: add initial offset, counteract error code in receiving state. In standby-II mode, if the LDO(except DVDDs LDO) in test mode, the bit is configured to 1 when testing transmitting single carrier and receiving sensitivity. 1: Enable 0: Dienable Configure the threshold value of receiver digital demodulators lead code. The threshold of 24bits lead code=PTH+16 1000: 24bits 0110: 22bits 0000: 16bits Receiver digital demodulators 4 times some relevant data. 1: 3bit 0: 2bit If reverse the lead code, configure to 1 in general. Enable this function in the both the receiving and transmitting terminals. 1: Do not reverse in bits 0: Reverse in bits Adjust the central amplitude of the loop reference waveform, configure to 1110 Adjust the speed of the loop reference waveform, configure to 000101 sampling, calculate AGGRESSIVE 0 R/W 1C 7:6 00 R/W Only 00 allowed 2.4GHz Module Choose the speed of demodulators code unit rate synchronizaton 1: Adjust in large steps, the speed is fast 0: Adjust in small steps, the speed is low Enable dynamic PAYLOADs length Enable the length of PIPE 5s dynamic PAYLOAD(EN_DPL and ENAA_P5 are needed) Enable the length of PIPE 4s dynamic PAYLOAD(EN_DPL and ENAA_P4 are needed) Enable the length of PIPE 3s dynamic PAYLOAD(EN_DPL and ENAA_P3 are needed) Enable the length of PIPE 2s dynamic PAYLOAD(EN_DPL and ENAA_P2 are needed) Enable the length of PIPE 1s dynamic PAYLOAD(EN_DPL and ENAA_P1 are needed) Enable the length of PIPE 0s dynamic PAYLOAD(EN_DPL and ENAA_P0 are needed) Choose IRQ signal output or EN_PA signal output to PIN 0IRQ signal output to PIN 1EN_PA signal output to PIN Open CE with command mode 0CE is controlled by pins 1CE is controlled by command Choose the length of data 11: 64byte512bit mode 00: 32byte256bit mode Enable of PAYLOAD dynamic length the enable W_TX_PAYLOAD_NOACK command RF parameter programme) registers(configure by Choose the external crystal signal 1: clock signal output to CLK_OUTs R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable ACK which has PAYLOAD 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1D*
DPL_P0 FEATURE Reserved 7:0 7 R/W Feature registers R/W Only 00 allowed DATA_LEN_SEL 4:3 00 1E*
RF_CAL 23:0 EN_CLK_OUT 23 http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co DYNPD Reserved DPL_P5 DPL_P4 DPL_P3 DPL_P2 DPL_P1 MUX_PA_IRQ CE_SEL EN_DPL EN_ACK_PAY EN_NOACK 5 4 3 2 1 0 6 5 2 1 0 2.4GHz Module PAD 2: no output The reference voltage of DACs comparison circuit If the reference voltage is high, the DACs output range is high 111: positive reference voltage is high 000: positive reference voltage is low The reference voltage of DACs comparison circuit If the reference voltage is high, the DACs output range is high 111: negative reference voltage is high 000: negative reference voltage is low The command bit of DACs output range 1: output range0.8 0: output range0.5 Enable RSSI 1: RSSI enable 0: RSSI disenable The bit to choose RSSIs signal gain attenuation. 00: no attenuation 01: -6dB 10: -12dB 11: -18dB Choose the gain of receiving MIXL 1: 14dB 0: 8dB Choose PAs output direct current 00: 1 01: 2 10: 3 11: 4 Choose LNAs gain 11: 17dB 10: 11dB 01: 5.4dB 00: -0.4dB Configure VCOs current 000: 900uA 001: 1050uA 010: 1200uA 011: 1350uA 100: 1500uA 101: 1650uA 110: 1800uA DA_VREF_MB 22:20 101 R/W DA_VREF_LB 19:17 110 R/W RSSI_Gain_CTR 14:13 01 R/W DA_LPF_CTRL 16 RSSI_EN 15 MIXL_GC 12 PA_BC 11:10 1 0 1 11 R/W R/W R/W R/W LNA_GC 9:8 11 R/W VCO_BIAS 7:5 111 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co RES_SEL 4:3 10 LNA_HCURR MIXL_BC IB_BPF_TRIM 2 1 0 7:0 15:8 23:16 31:24 39:32 39:32 INVERTER 31 DAC_MODE 30 1 1 0 1 0 R/W R/W R/W R/W R/W 1F*
BB_CAL R/W Digital registers(default value in general) base bandwidth Reserved 01000110 R/W Only 0X01000110 allowed 2.4GHz Module 111: 1950uA Choose chip offset current load 00: 26kR 01: 24kR 10: 22kR 11: 20kR Configure LNAs high current 1: high current 0: low current Choose MIXLs receiving current 1: 1 0: 0.5 Choose receiving bandwidth filters current 1: 1 0: 0.5 If reverse the data before entering RX_block 1: reverse 0: retain If reverseddac_out[5:0]
output terminal 1:dac_out[5:0]<= [0:5]
0:dac_out[5:0]<= [5:0]
be DACs dac_out[5:0]
need to is internal of Transmitting PLL The internal from PLLs open-loop state to data-sending state, the length of time is:
TRX_TIME8+7.5the unit is us The enabling PA, the length of time is:
EX_PA_TIME16the unit is us The enabling PA, the length of time is:
TX_SETUP_TIME16the unit is us The stable time of RF RX circuit RX_SETUP_TIME16the unit is us Transmitting PLL internal of The longest time of PTX converting to receiving mode, its a failure when time is out. DAC_BASAL 29:24 011100 R/W Pre-sending DACs initial value TRX_TIME 23:21 011 R/W EX_PA_TIME 20:16 00111 R/W TX_SETUP_TIME 15:11 01101 R/W RX_SETUP_TIME 10:6 10100 R/W RX_ACK_TIME 5:0 001010 R/W http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module The length of time in 1Mbps mode:
RX_ACK_TIME32the unit is us The length of time in 250kbps mode:
RX_ACK_TIME128the unit is us Packet Format Description Packet Format D 999 Packet Format D escription escription ormal Burst ormal ormat for Nfor Nfor Normal ormat Packet Format Packet F 999.1.1.1 Packet F Burst Burst Table 7 Packet Format for Normal Burst Preamble
(3 byte) Address
(3~5 byte) Payload
(1~32/64 byte) CRC
(0/2 byte) It can choose Address and Payload part to scramble, according to scrambler configuration bits. ormat for Enhanced Burst ormat Packet Format Packet F 999.2.2.2 Packet F for Enhanced Burst for Enhanced Burst Table 8 Packet Format for Enhanced Burst Preambl e
(3 byte) Addres s
(3~5 byte) Package control field (10bit) Payload length (7bit) PID
(2bit) NO_ACK
(1bit) Payload
(1~32/64 byte) CRC
(0/2 byte) It can choose Address, Package control field and Payload part to scramble, according to scrambler configuration bits. ormat for Enhanced Burst ACK ormat Packet Format Packet F 999.3.3.3 Packet F for Enhanced Burst ACK for Enhanced Burst ACK Table 9 Packet Format for Enhanced Burst ACK Preambl e
(3 byte) Addres s
(3~5 byte) Package control field (10bit) Payload length (7bit) PID
(2bit) NO_ACK
(1bit) CRC
(0/2 byte) It can choose Address, Package control field to scramble, according to scrambler http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co Package S 111111 Package S Package Sizeizeize 2.4GHz Module Figure 9 QFN20L 0303 Package Size http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module Specification Operation frequency:2402MHz~2465MHz Maximum power: 6.27dBm(EIRP) The device complies with RF specifications when the device used at This product is a category 1 receiver device. The operating temperature of the EUT cant exceed 55 and shouldnt Statement 1. 0mm form your body. 2. 3. be lower than -20. 4. This product can be used across EU member states. Hereby, DA KAI INDUSTRIES LIMITED. declares that the product compliance with essential requirements and other relevant provisions of Directive 2014/53/EU. http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module configuration bits. FCC Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
-- Reorient or relocate the receiving antenna.
-- Increase the separation between the equipment and receiver.
-- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-- Consult the dealer or an experienced radio/TV technician for help. 15.19 Labeling requirements. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. 15.21 Information to user. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. RF exposure This equipment complies with FCC and ISED radiation exposure limits set forth for an uncontrolled environment. The RF exposure compliance of the distance of 0 mm between the radiator and your body. Antenna gain must be below 0.4dBi. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093. If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. Labelling Requirements for the Host device The host device shall be properly labeled to identify the modules within the host device. The certification label of the module shall be clearly visible at all times when installed in the host device, otherwise the host device must be labelled to display the FCC ID and ISED of the module, preceded by the words "Contains transmitter module", or the word "Contains", or similar wording expressing the same meaning, as follows:
Model: 2.4G module Contains FCC ID2APYU-DKL1613 The host OEM user manual must also contain clear instructions on how end users canfind and/or access the module and the FCC ID and ISED. Model: 2.4G module Contains FCC ID2APYU-DKL1613 The transmitter module may not be co-located with any other transmitter or antenna. Module Antenna Type: Integral Antenna,ANT Gain: 0.4dBi http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co 2.4GHz Module OEM Statement a. The module manufacturer must show how compliance can be demonstrated only for specific host or hosts b. The module manufacturer must limit the applicable operating conditions in which t transmitter will be used, and c. The module manufacturer must disclose that only the module grantee can make the te evaluation that the module is compliant in the host. When the module grantee either refuses to make this evaluation, or does not think it is necessary, the module certification is rendered invalid for use in the host, and the host manufacturer has no choice other than to use a different module, or take responsibility ( 2.929) and obtain a new FCC ID for the product. d. The module manufacturer must provide the host manufacturer with the follow requirements:
e. The host manufacturer is responsible for additional testing to verify compliance as composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the modules intentional emissions are compliant (i.e. fundamental and out of band emissions). Validity of using the module certification:
In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization for this module in combination with the host equipment is no longer considered valid and the FCC ID of the module cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. In such cases, please involve a FCC certification specialist in order to determine if a Permissive Class II Change or new Certification is required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). The end-product may need Verification testing, Declaration of Conformity testing, a Permissive Class II Change or new Certification. Please involve a FCC certification specialist in order to determine what will be exactly applicable for the end-product. KDB Ref Sect Requirements of KDB 996369 D03 Description 2.2 List of applicable FCC rules This product compliance with FCC Part 15C section 15.249, section 15.203,section 15.207,section 15.209, section 15.215. 2.3 Summarize the specific This product has an Integral antenna operational use conditions Limited module procedures This product is a limited module Trace antenna designs This product without trace antenna designs RF exposure considerations race antenna designs compliance RF exposure limits Antennas This product has an Integral antenna 2.4 2.5 2.6 2.7 2.8 Label and compliance The host system using this module , should label in a visible area indicated information the following texts: Contains FCC ID : 2APYU-DKL1613 2.9 Information on test modes and Data transfer module demo can control the EUT works in RF test mode and additional testing requirements specified channel 2.10 Additional testing, Part 15 The module without unintentional-radiator digital circuit, so the module does Subpart B disclaimer not require an evaluation by FCC part 15 Subpart B. The host should be evaluated by FCC part 15 Subpart B http://www.panchip.com Copyright 2015 Panchip Microelectronics, Ltd. Co
This product uses the FCC Data API but is not endorsed or certified by the FCC