Habanero Data Sheet Habanero system on module (SOM) is based on an IPQ4019/IPQ4029 SoC from Qualcomm, which incorporates a powerful quad-core ARM Cortex A7 processor with NEON and FPU. It is ideal for resource demanding applications including routers, gateways and access points. Habanero comes with a high-power, dual-band concurrent radio supporting 802.11ac Wave2 technology (2x2 MiMo). QCA8075C PHY gives support to 5 x Gigabit Ethernet ports. It also has 1 x USB3.0 and 1 x USB2.0 ports and supports other miscellaneous interfaces, which can be configured as general-
purpose I/O pins. Hardware based NAT engine and security features like crypto engine, secure boot make it ideal for high-end, fast and secure networking applications. Habanero comes in commercial and industrial temperature versions. Commercial temperature range: 0-65C, industrial temperature range: -40-85C. Quick specs Wi-Fi 5 (802.11a/n/ac Wave2) 5GHz with 2x2 MU-MiMo, 866.7Mbps data-rate Wi-Fi 5 (802.11b/g/n/ac) 2.4GHz, 400Mbps data-rate MIPI DBI v2.0 type B interface CPU - IPQ4019/IPQ4029 ( 716.8MHz) OpenWRT Linux flash image 24-25 dBm per chain RF output power Size - 45 by 49 mm Available interfaces 46 x GPIO, 1 x PCie 2.0, 1 x USB3.0, 1 x USB2.0, 2 x UART, 1 x SPI, 2 x I2C, 4 x PWM, 1 x JTAG, 1 x I2S/TDM, 5 x 1000/100/10 ethernets, 1 x RGMII, 1 x SDIO3.0/eMMC and parallels for NAND flash memory and LCD controller 3. Module pinout and Pin description Table of Contents 1. Product Overview 1.1 Features 2. Block diagram 4. Electrical characteristics 5. Power management 5.1. Power consumption 6. Radio characteristics 7. Mechanical characteristics 8. Design considerations 8.1. Ethernet interface 8.2. USB 8.3. Parallel NAND flash / LCD 8.4. I2C 8.5. SD/eMMC 8.6. PCIe 8.7. JTAG 9. Thermal considerations 10. Development board 10.1 DVK dimensions 10.2 DVK interfaces 10.3 LEDs 10.4 BOOTSTRAP switch 10.5 DVK header pinout 10.6 DVK heatsink 11. Habanero packaging and ordering info 12. Document Revision History 3 3 4 5 16 16 16 17 18 18 19 19 20 21 22 23 24 24 25 25 26 27 27 28 29 30 31 2 IEEE 802.11 b/g/n/ac 2x2 MU-MIMO 2.4GHz 20/40 MHz 256 QAM 2402-2482MHz 25dBm IEEE 802.11 b/g/n/ac 2x2 MU-MIMO 5GHz 20/40/80 MHz 256 QAM 4920-5920MHz 24dBm TABLE 1-1. 8DEV6000 HABANERO FEATURES 1. Features 1.1. Features Feature list Integrated core Core clock frequency Core type Cache DRAM Memory NOR FLASH NAND FLASH (external) WIFI RF pin RF signal is fed to 2 external module pins LCD controller Display MIPI DBI v2.0 type B interface (Intel 8080 9bit parallel) PCIe USB UART SPI I2C GPIO PWM Parallel Ethernet RGMII Reset PCIe 2.0 USB 3.0 USB 2.0 Universal asynchronous receiver transmitter serial ports Serial peripheral interface port Inter-integrated circuit interfaces for peripheral devices IN/OUT/INT Audio Pulse Width Modulation interface For parallel NAND flash memory For parallel LCD controller Copper 10BASE-Te/100BASE-TX/1000BASE-T Fiber 100BASE-FX/1000BASE-X Reduced gigabit media independent interface Reset button controlled via voltage monitor SDIO3.0/eMMC Secure Digital Input Output / Embedded Multi Media Card Peripherals JTAG Debug interface I2S/TDM Multichannel interfaces for digital audio support 8DEV6000 Habanero ARM Cortex-A7 IPQ4019/IPQ4029 DDR3L 512MB (up to 1GB) 716.8MHz 256KB L2 32MB 1GB(tested) 46 2 1 1 1 1 1 2 1 2 4 1 1 1 1 5 1 1 1 1 3 2. Block diagram The following figure provides a basic overview of the 8DEV6000 Habanero module. FIGURE 2-1. 8DEV6000 HABANERO MODULE BLOCK DIAGRAM PCIe USB 3.0 USB 2.0 JTAG RGMII UART I2C SPI Master PWM 8DEV6000 Habanero Module 2x RFFM8528
(5GHz Wi-fi PA) 2x RFFM8228
(2.4GHz Wi-fi PA) QCA8075C
(5 port GEth PHY) DDR3L 512MB 48MHz Clock NOR FLASH 32MB Qualcomm IPQ4019/
IPQ4029 I2S/TDM SDIO3.0/eMMC GPIO Ethernet SFP 2.4GHz Wi-FI 2x2 11n 5GHz Wi-FI 2x2 11ac Parallel lines for NAND/LCD 4 3. Module pinout and Pin description FIGURE 3-1. PIN ASSIGNMENTS 2 1 1 A 1 1 1 A 0 1 1 A 9 0 1 A 8 0 1 A 7 0 1 A 6 0 1 A 5 0 1 A 4 0 1 A 3 0 1 A 2 0 1 A 1 0 1 A 0 0 1 A 9 9 A 8 9 A 7 9 A 6 9 A 5 9 A 4 9 A 3 9 A 2 9 A 1 9 A 0 9 A 9 8 A 8 8 A 7 8 A 6 8 A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 8 2 B 9 2 B 0 3 B 1 3 B 2 3 B 3 3 B 4 3 B 5 3 B 6 3 B 7 3 B 8 3 B 9 3 B 0 4 B 1 4 B 2 4 B 3 4 B 4 4 B 5 4 B 6 4 B 7 4 B 8 4 B 9 4 B 0 5 B 1 5 B 2 5 B 3 5 B 0 3 A 1 3 A 2 3 A 3 3 A 4 3 A 5 3 A 6 3 A 7 3 A 8 3 A 9 3 A 0 4 A 1 4 A 2 4 A 3 4 A 4 4 A 5 4 A 6 4 A 7 4 A 8 4 A 9 4 A 0 5 A 1 5 A 2 5 A 3 5 A 4 5 A 5 5 A 6 5 A B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 A85 A84 A83 A82 A81 A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 5 TABLE 3-1. I/O DESCRIPTION (PAD TYPE) PARAMETERS Description Analog input Analog output Ground RF input/output Digital input signal Digital output signal Digital bidirectional signal Open drain A1, A7, A27, A54, A86, B52, B70 DVDD33 3.3V digital power TABLE 3-2. POWER, GROUND AND RESET A12, A20, A29, A30, A38, A47, A55, A57, A75, A87, A88, A89, A90, A91, A92, A93, A94, A95, A97, A98, A99, A100, A101, A102, A104, A105, A106, A107, A108, A109, A110, A111, A112, B1, B2, B3, B4, B5, B6, B7, B16, B31, B40, B76, B77, B78, B79, B80 Pin name Type Description DVDD_2.7V_Malibu 2.7V digital power output GND GND Ground RESET_SOC CHIP_RST_OUT Reset SoC Reset GEPHY I O I I Symbol AI AO GND RF In/Out I O IO OD Pin ID B49 A6 B9 Pin ID A103 A96 Pin ID B57 A61 B51 A53 B50 A52 TABLE 3-3. RADIO TABLE 3-4. PCIE 2.0 Pin name Type Description TX0 TX1 RF In/Out Signal line for antenna RF In/Out Signal line for antenna Pin name PE_CLKN PE_CLKP PERXN PERXP PETXN PETXP Type AO AO AI AI AO AO Description Clock to PCIe endpoint - negative Clock to PCIe endpoint - positive PCIe receive lane - negative PCIe receive lane - positive PCIe transmit lane - negative PCIe transmit lane - positive 6 Pin name USB1_DP USB1_DM USB1_SS_RX_P USB1_SS_RX_N USB1_SS_TX_P USB1_SS_TX_N Type AI, AO AI, AO AI AI AO AO Description USB HS data positive USB HS data negative USB SS receive data positive USB SS receive data negative USB SS transmit data positive USB SS transmit data negative Pin name USB2_DP USB2_DM Type AI, AO AI, AO Description USB HS data positive USB HS data negative TABLE 3-7. GIGABIT ETHERNET Pin ID Pin name Type Description TABLE 3-5. USB 3.0 TABLE 3-6. USB 2.0 Pin ID A60 B56 A59 B55 B53 A56 Pin ID B54 A58 B23 A23 B24 A24 B25 A25 B26 A26 A28 B27 A31 B28 A32 B29 A33 B30 B32 A34 B33 P0_TRX0-
AI, AO P0_TRX0+
AI, AO P0_TRX1-
AI, AO P0_TRX1+
AI, AO P0_TRX2-
AI, AO P0_TRX2+
AI, AO P0_TRX3-
AI, AO P0_TRX3+
AI, AO P1_TRX0-
AI, AO P1_TRX0+
AI, AO P1_TRX1-
AI, AO P1_TRX1+
AI, AO P1_TRX2-
AI, AO P1_TRX2+
AI, AO P1_TRX3-
AI, AO P1_TRX3+
AI, AO P2_TRX0-
AI, AO P2_TRX0+
AI, AO P2_TRX1-
AI, AO PHY0 MDI pair0 negative, connect to transformer PHY0 MDI pair0 positive, connect to transformer PHY0 MDI pair1 negative, connect to transformer PHY0 MDI pair1 positive, connect to transformer PHY0 MDI pair2 negative, connect to transformer PHY0 MDI pair2 positive, connect to transformer PHY0 MDI pair3 negative, connect to transformer PHY0 MDI pair3 positive, connect to transformer PHY1 MDI pair0 negative, connect to transformer PHY1 MDI pair0 positive, connect to transformer PHY1 MDI pair1 negative, connect to transformer PHY1 MDI pair1 positive, connect to transformer PHY1 MDI pair2 negative, connect to transformer PHY1 MDI pair2 positive, connect to transformer PHY1 MDI pair3 negative, connect to transformer PHY1 MDI pair3 positive, connect to transformer PHY2 MDI pair0 negative, connect to transformer PHY2 MDI pair0 positive, connect to transformer PHY2 MDI pair1 negative, connect to transformer 7 Pin ID Pin name Type Description A35 B34 A36 B35 A37 A39 B36 A40 B37 A41 B38 A42 B39 B41 A43 B42 A44 B43 A45 B44 A46 A48 B45 A49 B46 B20 B21 A21 B22 B19 A22 A50 B47 A51 B48 P2_TRX1+
AI, AO P2_TRX2-
AI, AO P2_TRX2+
AI, AO P2_TRX3-
AI, AO P2_TRX3+
AI, AO P3_TRX0-
AI, AO P3_TRX0+
AI, AO P3_TRX1-
AI, AO P3_TRX1+
AI, AO P3_TRX2-
AI, AO P3_TRX2+
AI, AO P3_TRX3-
AI, AO P3_TRX3+
AI, AO P4_TRX0-
AI, AO P4_TRX0+
AI, AO P4_TRX1-
AI, AO P4_TRX1+
AI, AO P4_TRX2-
AI, AO P4_TRX2+
AI, AO P4_TRX3-
AI, AO P4_TRX3+
AI, AO SFP_SOP SFP_SON SFP_SIP SFP_SIN P0_100_LED P0_1000_LED P1_100_LED P1_1000_LED P2_100_LED P2_1000_LED P3_100_LED P3_1000_LED P4_100_LED P4_1000_LED AO AO AI AI O O O O O O O O O O PHY2 MDI pair1 positive, connect to transformer PHY2 MDI pair2 negative, connect to transformer PHY2 MDI pair2 positive, connect to transformer PHY2 MDI pair3 negative, connect to transformer PHY2 MDI pair3 positive, connect to transformer PHY3 MDI pair0 negative, connect to transformer PHY3 MDI pair0 positive, connect to transformer PHY3 MDI pair1 negative, connect to transformer PHY3 MDI pair1 positive, connect to transformer PHY3 MDI pair2 negative, connect to transformer PHY3 MDI pair2 positive, connect to transformer PHY3 MDI pair3 negative, connect to transformer PHY3 MDI pair3 positive, connect to transformer PHY4 MDI pair0 negative, connect to transformer PHY4 MDI pair0 positive, connect to transformer PHY4 MDI pair1 negative, connect to transformer PHY4 MDI pair1 positive, connect to transformer PHY4 MDI pair2 negative, connect to transformer PHY4 MDI pair2 positive, connect to transformer PHY4 MDI pair3 negative, connect to transformer PHY4 MDI pair3 positive, connect to transformer 1.25 Gbps differential data positive output for SGMII or 1000BASE-X 1.25 Gbps differential data negative output for SGMII or 1000BASE-X 1.25 Gbps differential data positive input for SGMII or 1000BASE-X 1.25 Gbps differential data negative input for SGMII or 1000BASE-X LED output for 100BASE-TX or 10BASE-Te of PHY0 LED output for 1000BASE-T of PHY0 LED output for 100BASE-TX or 10BASE-Te of PHY1 LED output for 1000BASE-T of PHY1 LED output for 100BASE-TX or 10BASE-Te of PHY2 LED output for 1000BASE-T of PHY2 LED output for 100BASE-TX or 10BASE-Te of PHY3 LED output for 1000BASE-T of PHY3 LED output for 100BASE-TX or 10BASE-Te of PHY4 LED output for 1000BASE-T of PHY4 8 TABLE 3-8. NAND/LCD CONTROLLER Pin ID Pin name Type B67 A73 A76 B71 A69 B66 A72 B65 B75 A66 A67 B63 A70 A68 B64 QPIC_PAD_DAT0 QPIC_PAD_DAT1 QPIC_PAD_DAT2 QPIC_PAD_DAT3 QPIC_PAD_DAT4 QPIC_PAD_DAT5 QPIC_PAD_DAT6 QPIC_PAD_DAT7 QPIC_PAD_DAT8 NAND_WE_N NAND_OE_N NAND_CLE_N NAND_CS_N NAND_ALE_N O O O O O O O O O O O O O O Description NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller data NAND/LCD controller write enable NAND/LCD controller read enable NAND controller chip select NAND controller ALE. Active high JTAG test data in JTAG test clock JTAG test mode state JTAG test data out JTAG reset for debug JTAG test reset 9 NAND_BUSY_N I, OD NAND controller busy_not_ready input. Active low NAND controller CLE/LCD controller DCX. CLE is command latch enable. Active high. DCX is data/command. 1 is data, o is command Pin ID Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage Type Description TABLE 3-9. GPIO A84 GPIO0 A83 GPIO1 A85 GPIO2 A81 GPIO3 A82 GPIO4 A80 GPIO5 GPIO JTAG TDI1 GPIO JTAG TCK1 GPIO JTAG TMS1 GPIO JTAG TDO1 BOOT_CONFIG(0) JTAG RST_N1 GPIO GPIO JTAG TRST_N1 0 1
0 1
0 1
0 1 0 1 0 1
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 I I I I I IO O TABLE 3-9. GPIO Pin ID Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage Type Description A8 GPIO16 BLSP_UART0_RXD LED(0) Rx data Led_clk or led_dar or led_strobe O O O O I I I I I I I O O O O I I O GPIO 3.3 GPIO 3.3 GPIO 3.3 BLSP_UART1_TXD WIFI0_UART_TXD WIFI1_UART_TXD BLSP_UART1_RXD WIFI0_UART_RXD(0) WIFI1_UART_RXD(0) BLSP_UART1_CTS WIFI1_UART_CTS(0) BLSP_UART1_RTS WIFI0_UART_RTS WIFI1_UART_RTS GPIO GPIO LED(1) GPIO GPIO 3.3 3.3 3.3 3.0 3.3 0 1 2
0 1 2 3
0 1 2 3
5 0 1 2 3 4 0 1 2 3 4 0 1 0 1 2 0 1 2
0 1 2 0 1 2 WIFI0_UART_TXD Wi-Fi UART output GPIO 3.3 A4 GPIO10 WIFI0_UART_CTS(0) BLSP_I2C0_SCK(0) I/O, OD GPIO 3.3 BLSP_I2C0_SDA(0) I/O, OD BLSP_SPI0_MOSI(0) SPI0 Master-out Slave-in data A9 GPIO18 WIFI0_UART_CTS(1) WIFI1_UART_CTS(1) BLSP_UART0_TXD GPIO 3.3 UART output Led_clk or led_dar or led_strobe BLSP_I2C0_SCK(1) AUDIO_RXMCLK(0) I/O, OD I/O I2C0 SCK Master clock source of Audio I2S/TDM Rx interface A11 GPIO21 BLSP_I2C0_SDA(1) I/O, OD I2C0 SDA AUDIO_RXBCLK(1) 3.0 I/O Bit clock of Audio I2S/TDM Rx interface A2 GPIO8 A5 GPIO9 A3 GPIO11 A10 GPIO14 B8 GPIO17 B10 GPIO20 Tx data Wi-Fi UART output Wi-Fi UART output Rx data Wi-Fi UART input Wi-Fi UART input Clear to send Wi-Fi UART input Wi-Fi UART input I2C0 SCK Ready to send Wi-Fi UART output Wi-Fi UART output I2C0 SDA Wi-Fi UART input Wi-Fi UART input 10 Pin ID Pin name GPIO CFG. FUNC_SEL Configurable Function GPIO B11 GPIO22 AUDIO_RXFSYNC(1) Voltage Type Description RGMII_RXD(0) 1.5(2.0)/2.5(1.0) RGMII Data input 0 0 1 2 0 1 2 3 A13 GPIO23 B12 GPIO24 A14 GPIO25 B13 GPIO26 A15 GPIO27 AUDIO_TXBCLK(0) I/O Bit clock of Audio I2S/TDM Tx interface 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 GPIO SDIO_DAT(0) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_RXD(1) 1.5(2.0)/2.5(1.0) AUDIO_RXD(1) GPIO SDIO_DAT(1) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_RXD(2) 1.5(2.0)/2.5(1.0) AUDIO_TXMCLK(0) SDIO_DAT(2) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_RXD(3) 1.5(2.0)/2.5(1.0) GPIO GPIO SDIO_DAT(3) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_RX_CTL 1.5(2.0)/2.5(1.0) AUDIO_TXFSYNC(0) GPIO SDIO_CLK SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_TXC 1.5(2.0)/2.5(1.0) AUDIO_TD1 GPIO AUDIO_TD2 GPIO 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 I/O I/O I/O I/O I/O I I I I I I I/O I/O O O O I/O O O I/O O O Left or Right indication of Audio I2S Rx interface and frame start indication of Audio TDM Rx interface SDIO Data input 0 RGMII Data input 1 Serial digital data of Audio Rx interface SDIO Data input 1 RGMII Data input 2 Master clock source of Audio I2S/TDM Tx interface SDIO Data input 2 RGMII Data input 3 SDIO Data input 3 RGMII Rx control Left or Right indication of Audio I2S Tx interface and frame start indication of Audio TDM Tx interface SDIO CLK RGMII Tx clock Serial digital data output 1 of Audio Multi-channel I2S Tx interface and serial digital data of Audio TDM Tx interface SDIO CMD RGMII Tx Data 0 Serial digital data output 2 of Audio Multi-channel I2S Tx interface SDIO Data input 4 RGMII Tx Data 1 Serial digital data output 3 of Audio Multi-channel I2S Tx interface 11 A16 GPIO28 SDIO_CMD SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_TXD(0) 1.5(2.0)/2.5(1.0) B14 GPIO29 SDIO_DAT(4) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_TXD(1) 1.5(2.0)/2.5(1.0) AUDIO_TD3 3.0 Pin ID Pin name GPIO CFG. FUNC_SEL Configurable Function Voltage Type Description A17 GPIO30 B15 GPIO31 A18 GPIO32 GPIO 3.3 SDIO_DAT(5) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_TXD(2) 1.5(2.0)/2.5(1.0) SDIO_DAT(6) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_TXD(3) 1.5(2.0)/2.5(1.0) SDIO_DAT(7) SDIO: 1.8/3.0;
eMMC: 1.8 RGMII_RXC 1.5(2.0)/2.5(1.0) AUDIO_PWM0 GPIO AUDIO_PWM1 GPIO AUDIO_PWM2 GPIO AUDIO_PWM3 GPIO Audio Pulse Width Modulation interface 0 SDIO Data input 5 RGMII Tx Data 2 SDIO Data input 6 RGMII Tx Data 3 SDIO Data input 7 RGMII Rx clock Audio Pulse Width Modulation interface 1 Audio Pulse Width Modulation interface 2 Audio Pulse Width Modulation interface 3 I2C1 SCK Audio SPDIF input B17 GPIO33 RGMII_TX_CTL 1.5(2.0)/2.5(1.0) RGMII Tx control A19 GPIO34 BLSP_I2C1_SCK(1) I/O, OD AUDIO_SPDIFIN(0) GPIO B18 GPIO35 BLSP_I2C1_SDA(1) I/O, OD I2C1 SDA AUDIO_SPDIFOUT Audio SPDIF output 3.0 (confirm standard I/O voltage) A62 GPIO36 RGMII0_TXD(0) B58 GPIO37 RGMII0_TXD(1) WIFI0_WCI_OUT WIFI1_WCI_OUT A64 GPIO38 RMII0_TX_EN GPIO LED(2) LED(0) GPIO LED(1) GPIO LED(2) GPIO LED(3) B59 GPIO39 RMII0_RX_ER I/O RMII Rx error when master mode; RMII Tx error when slave mode PCIE_CLK_REQ_N(0) OD PCIe clock request (only use input mode) RGMII0 Tx data 0 led_clk or led_dat or led_strobe led_clk or led_dat or led_strobe RGMII0 Tx data 1 Wi-Fi 0 LTE Coex output Wi-Fi 1 LTE Coex output led_clk or led_dat or led_strobe RMII0 Tx enable led_clk or led_dat or led_strobe led_clk or led_dat or led_strobe 12 I/O O O I/O O O I/O I O O O I O O O O O O 3.0 3.3 3.0 3.3 3.0 3.3 3.3 3.3 3.0 3.3 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 0 1 2 0 1 2 0 1 2 3 0 1 2 3 4 0 1 2 0 1 2 3 Pin ID Pin name GPIO CFG. FUNC_SEL Voltage Type Description A63 GPIO40 2 WIFI0_RFSILIENT_BB(0) 3 WIFI1_RFSILIENT_BB(0) A65 GPIO41 2 WIFI0_CAL_XPA_ACTIVE 3 WIFI1_CAL_XPA_ACTIVE B60 GPIO42 B68 GPIO43 Configurable Function GPIO RMII0_REFCLK
#PCIE_WAKEUP_N#
LED(4) GPIO RMII0_RXD(0) GPIO RMII0_RXD(1) WIFI_WCI_IN(0) GPIO RMII0_DV WIFI_WCI_IN(1) GPIO RMII1_REFCLK SMART_ANT4(0) GPIO RMII1_RXD(0) SMART_ANT5(0) LED(6) GPIO RMII1_RXD(1) SMART_ANT6(0) 0 1
5 6 0 1
0 1 2 0 1 2 0 1 2 3 0 1 2 4 5 0 1 2 3 4 B61 GPIO45 BLSP_SPI1_SS0_N 1.8/3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.0 I/O I I OD I O O I I I I I/O O I/O I O I/O I O I/O Input reference clock when Slave mode. Output clock when Master mode Wi-Fi 0 RF silent signal (RF_Kill) Wi-Fi 1 RF silent signal (RF_Kill) led_clk or led_dat or led_strobe RMII0 Rx data 0 Wi-Fi I0 XPA control signal used for test purposes Wi-Fi I1 XPA control signal used for test purposes RMII0 Rx data 1 Wi-Fi LTE Coex input RMII0 Rx valid Wi-Fi LTE Coex input Input reference clock when Slave mode. Output clock when Master mode wifi_2g TXPCU_ANTENNA_INFO[0]
(from MAC) wifi_2g serial clock for smart antenna (serial mode) RMII1 Rx data 0 SPI1 chip select 0 wifi_2g TXPCU_ANTENNA_INFO[1]
(from MAC) wifi_2g serial Data for smart antenna (serial mode) led_clk or led_dat or led_strobe RMII1 Rx data 1 wifi_5g TXPCU_ANTENNA_INFO[0]
(from MAC) wifi_5g serial clock for smart antenna (serial mode) 13 B74 GPIO46 BLSP_SPI1_MOSI 1.8/3.0 SPI1 Master-out Slave-in data LED(7) led_clk or led_dat or led_strobe B62 GPIO44 BLSP_SPI1_SCK 1.8/3.0 SPI1 serial clock Pin ID Pin name GPIO CFG. FUNC_SEL Voltage Type Description A74 GPIO47 BLSP_SPI1_MISO 1.8/3.0 SPI1 Master-in Slave-out data B69 GPIO48 AUD_PIN_PCM_DTX Transmitted data of Audio PCM interface A71 GPIO49 AUD_PIN_PCM_DRX I Received data of Audio PCM interface Configurable Function GPIO RMII1_DV SMART_ANT7(0) LED(8) GPIO RMII1_TX_EN LED(9) GPIO RMII1_RX_ER LED(10) GPIO RMII1_TXD(0) AUD_PIN_PCM_PCLK 4 WIFI1_RFSILIENT_BB(1) LED(11)
#PCIE_WAKEUP_N#
GPIO RMII1_TXD(1) 2 AUD_PIN_PCM_FSYNC 3 WIFI0_CAL_XPA_ACTIVE 4 WIFI1_CAL_XPA_ACTIVE QPIC_PAD_TE MDC AUDIO_TXMCLK(1) BOOT_CONFIG(13) 0 1 2 3 4 0 1 2
4 0 1 2
0 1 2 5 6 0 1 0 2 3 4 B72 GPIO50 3 WIFI0_RFSILIENT_BB(1) B73 GPIO51 3.3 3.0 3.3 3.0 3.3 3.3 3.0 3.3 3.0 3.3 3.0 3.3 3.3 3.3 3.0 I I I/O O O O O I I OD O OD O I/O RMII1 Rx valid wifi_5g TXPCU_ANTENNA_INFO[1]
(from MAC) wifi_5g serial Data for smart antenna (serial mode) led_clk or led_dat or led_strobe RMII Tx enable led_clk or led_dat or led_strobe I/O RMII Rx error when master mode; RMII Tx error when slave mode led_clk or led_dat or led_strobe RMII1 Tx data 0 Clock of Audio PCM interface Wi-Fi 0 RF silent signal (RF_Kill) Wi-Fi 1 RF silent signal (RF_Kill) led_clk or led_dat or led_strobe RMII1 Tx data 1 Frame start indication of Audio PCM interface Wi-Fi 0 XPA control signal used for test purposes Wi-Fi 1 XPA control signal used for test purposes LCD control info, V sync Management Data Clock Master clock source of Audio I2S/TDM Tx interface 14 A77 GPIO52 PCIE_CLK_REQ_N(1) PCIe clock request (only use input mode) Pin ID Pin name GPIO CFG. FUNC_SEL Voltage Type Description Configurable Function GPIO QPIC_PAD_LCD_RS_N BLSP_SPI0_SS0_N(1) AUDIO_TD1 GPIO QPIC_PAD_LCD_CS_N BLSP_UART0_TXD SMART_ANT5(1) SMART_ANT3(3) LED(1) AUDIO_TXFSYNC(2) AUDIO_RXFSYNC(2) 0 1 2 3 0 1 2 3 4 5 6 7 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 O O O O O I/O I/O O I/O I/O LCD controller RESX, reset signal. Active low SPI0 chip select 0 Serial digital data output 1 of Audio Multi-channel I2S Tx interface and serial digital data of Audio TDM Tx interface LCD controller chip select UART transmit data Smart antenna Smart antenna Audio transmit frame sync Audio receiver frame sync A79 GPIO54 A78 GPIO61 TABLE 3-10. PIN STATUS ON BOOT Pin ID Pin name Signal name Bootstrap value description Bootstrap default value A81 A10 B73 NC*
B16 A62 B58 A64 A67 B63 A70 B64 GPIO3 Apps_auth_enable GPIO14 GPIO51 boot_interface [0]
Boot_interface [1]
Boot_interface[1:0]=00: use spi as boot Boot_interface[1:0]=01: use emmc as boot Boot_interface[1:0]=10: use qpic as boot Boot_interface[1:0]=00: boot from usb GPIO15 Watchdog_enable GPIO33 All_use_serial_num_inv Use serial num for secure boot authentication 0: Use serial num 1: Use OEM ID (default) Authentication enable 0: no auth 1: auth required Watchdog_enable 0: watchdog disable 1: watchdog enable GPIO36 Boot_from_rom GPIO37 Apps pbl boot speed [0]
GPIO38 Apps pbl boot speed [1]
Force_usb_boot GPIO55 GPIO56 GPIO62 0: boot from code RAM 1: boot from ROM APPS PBL BOOT SPEED (APSS PLL) 00 XO clock 48MHz 01 FE_PLL clock 200MHz 10 FE_PLL clock 500MHz 11 Reserved 0: not force boot from USB 1: force boot from USB pi_mode 0: Function mode Jtag_boot_en 0: GPIO0-GPIO5 are normal GPIO 1: GPIO0-GPIO5 are used as JTAG interface GPIO69 Pk_hash_index_src Select ROM PK hash index source 0: from QC ffuse 1: From OEM efuse 00 00 0 1 1 0 0 0 0 0 15 4. Electrical characteristics TABLE 4-1. POWER SUPPLY DC CHARACTERISTICS Symbol DVDD33 Parameter Minimum Typical Maximum 3.3V Supply Voltage 3.0 3.3 3.6 TABLE 4-2. TEMPERATURE LIMIT RATINGS Parameter Minimum Maximum Units
-40
-40 0
-40 10 5
+70
+90
+65
+85 90 90 Storage Temperature (Commercial) Storage Temperature (Industrial) Commercial Operating Temperature Industrial Operating Temperature Humidity Storage humidity 5. Power management 5.1. Power consumption TABLE 5-1. POWER CONSUMPTION DBS Tx Rx Voltage Current Total power in Watts 2x2 2x2 MCS0 MCS9 MCS0 MCS9 12 12 12 12 0.96 0.8 0.55 0.64 NOTE: Power consumption was measured while generating throughput via WiFi and all Ethernet ports using DVK Units V C C C C
%RH
%RH 11.5 9.6 6.6 7.6 16 6. Radio characteristics 2.4GHz 802.11g 20MHz 6 9 Mbps Mbps 12 Mbps 18 Mbps 24 Mbps 36 Mbps 48 Mbps 54 Mbps Transmitter Power (dBm) Receiver sensitivity (dBm) 22
-94 22
-93 21
-92 21
-90 21
-87 20
-86 19
-81 18
-79
MCS 0 MCS 1 MCS 2 MCS 3 MCS 4 MCS 5 MCS 6 MCS 7 MCS 8 Transmitter Power (dBm) Receiver sensitivity (dBm) 22
-93 21
-90 21
-88 20
-85 18
-80 17
-76 15
-74 14
-72 13
-68 2.4GHz 802.11n/ac 20MHz 2.4GHz 802.11n/ac 40MHz MCS 0 MCS 1 MCS 2 MCS 3 MCS 4 MCS 5 MCS 6 MCS 7 MCS 8 MCS 9 Transmitter Power (dBm) Receiver sensitivity (dBm) 22
-90 21
-88 21
-85 20
-82 18
-77 17
-73 15
-73 14
-70 13
-66 12
-64 5GHz 802.11n/ac 20MHz 5GHz 802.11n/ac 40MHz 5GHz 802.11ac 80MHz MCS 0 MCS 1 MCS 2 MCS 3 MCS 4 MCS 5 MCS 6 MCS 7 MCS 8 Transmitter Power (dBm) Receiver sensitivity (dBm) 21
-92 21
-89 20
-86 19
-83 18
-80 17
-76 16
-74 16
-73 15
-68 MCS 0 MCS 1 MCS 2 MCS 3 MCS 4 MCS 5 MCS 6 MCS 7 MCS 8 MCS 9 Transmitter Power (dBm) Receiver sensitivity (dBm) 21
-89 21
-86 20
-84 19
-81 18
-78 17
-73 16
-72 16
-70 15
-68 14
-67 5GHz 802.11ac VHT80 MCS 0 MCS 1 MCS 2 MCS 3 MCS 4 MCS 5 MCS 6 MCS 7 MCS 8 MCS 9 Transmitter Power (dBm) Receiver sensitivity (dBm) 21
-86 20
-83 19
-80 19
-77 18
-74 17
-70 16
-69 16
-67 15
-63 14
-61 Note:
2. 1. Receiver sensitivity and Transmitter Power tolerance is +-2dB In the table above output power is specified per chain, each radio 2.4GHz and 5GHz has two chain each, because total power is double or 3dB higher.
17 7. Mechanical characteristics 1.08 10%
1.22 3.3
. 0 9 4
. 5 5 4 0 5
. 5 3
. 5 3
. 0 5
. 5 5 4 5 2 4
. 5 7 5
. 5 2 3 4
. 45.0 42.0 4.5 3.0 3.0 4.5 42.0 A 3.00 3.75 4.50 5.25 41.25 42.00 PCB footprint 45.00 42.25 42.00 4.50 3.00 2.75 0 0
. 9 4 5 2
. 6 4 0 5
. 5 4 5 2
. 3 4 5 7
. 5 0 0
. 5 5 2
. 4 0 5
. 3 5 7
. 2 5 2 3 4
. 5 7 5
. 5 2 4
. A 3.75 5.25 41.25 0.95 1.9 R0.45 R0.50 R0.50 9
. 0 0
. 1 1.05 DETAIL A SCALE 8 : 1 0 5
. 3 5 2
. 4 0 0
. 5 5 7
. 5 5 2
. 3 4 0 5
. 5 4 Cut on Motherboard Side Module Outline 1.80 0.75 0
. 1 0
. 1 DETAIL A SCALE 8 : 1 R0.5 R0.5 2.00 2.25 18 8. Design considerations 8.1. Ethernet interface ETHERNET DESIGN GUIDELINES:
Category Groups Route type Length Guidelines/Remarks P[0..4]_TRX[0..3]+, P[0..4]_TRX[0..3]-
Differential pair, 100 Ohm impedance
< 1.5 in., try to route as short as possible Length match within pair
+-5 mils Length match across pairs There is no requirement to length match the Tx and Rx pairs Spacing requirements 3 W spacing between pairs and to other signals Vias/layer transitions Minimize layer transitions; where necessary limit to 2 vias per signal trace. Provide return vias interconnecting the GNDs in the immediate vicinity of signal vias Other Each pair needs magnetic module (or combo module for all pairs) between PHY and Ethernet port USB 3.0 DESIGN GUIDELINES:
Guidelines/Remarks USB_TXP, USB_TXN USB_RXP, USB_RXN Differential pair, 100 Ohm impedance 8.2. USB Category Groups Route type Return path Length Length match within pair
+- 5 mils
< 5 in. Length match across pairs There is no requirement to length match the Tx and Rx pairs Spacing requirements 3 W spacing between pairs and to other signals Vias/layer transitions Avoid layer transitions and vias Differential pair, 90 Ohm impedance for the super speed pairs according to USB3.0 specification Ensure continuous and unbroken return path without voids AC coupling Use 0.1 uF capacitors on each signal line of the Tx pair from Habanero module; place them symmetrically at the same point on the pair Other Clear the GND pour under the signal pads of the connector where SMD connectors are used 19 USB 2.0 DESIGN GUIDELINES:
Category Groups Route type Return path Length Guidelines/Remarks
(USB2_DP, USB2_DM) and (USB1_DP, USB1_DM) Differential pair, 90 Ohm impedance for the USB2.0 pair according to USB2.0 specification Ensure continuous and unbroken return path without voids
< 5 in. Length match within pair
+- 5 mils Length match across pairs Not applicable Spacing requirements 3 W spacing between pairs and to other signals Vias/layer transitions Avoid layer transitions and vias AC coupling Not applicable; the lines must be DC connected Other Clear the GND pour under the signal pads of the connector where SMD connectors are used 8.3. Parallel NAND flash / LCD NAND FLASH DESIGN GUIDELINES:
Category Guidelines/Remarks Signal/group Route type Return path Length QPIC_PAD_NAND_CS_N QPIC_PAD_CLE_LB_N QPIC_PAD_ALE_LB_N QPIC_PAD_WE_N QPIC_PAD_OE_N QPIC_PAD_BUSY_N QPIC_PAD_DATA[7:0]
Single-ended
< 5 in. Ensure continuous and unbroken return path without voids Length match 200 mils within group, 400 mils across groups Spacing requirements 2 W spacing to other signals GND shielding Not required Vias/layer transitions Vias are acceptable Voltage 3.3 V Follow best design practices and provide decoupling close to the NAND device. Allocate one 0201 decap per pin and locate close to the pin Decoupling and power layout A bulk capacitor in the order of 1 uF or more is advised for the device Share the 3.3 V power plane Other Some NAND controller output lines are used at power-up to sense boot configuration straps. Take care to minimize stubs in the path. A 10K pull-up is recommended on the NAND_CS signal at flash device 20 LCD DESIGN GUIDELINES:
Category Guidelines/Remarks Signal/group Route type Return path Length Voltage Voltage QPIC_PAD_LCD_CS_N QPIC_PAD_CLE_LB_N QPIC_PAD_LCD_RS_N QPIC_PAD_ALE_LB_N QPIC_PAD_WE_N QPIC_PAD_OE_N QPIC_PAD_BUSY_N QPIC_PAD_DATA[8:0]
< 5 in. 3.3 V 3.3 V Single-ended 50 Ohm impedance Ensure continuous and unbroken return path without voids Spacing requirements 2 W spacing to other signals GND shielding Not required Vias/layer transitions Vias are acceptable Decoupling and power layout Allocate one 0201 decap per pin and locate close to the pin A bulk capacitor in the order of 1 uF or more is advised for the device Follow best design practices and provide decoupling close to the NAND device. Share the 3.3 V power plane 8.4. I2C I2C DESIGN GUIDELINES:
Category Guidelines/Remarks Signal/group I2C_SDA, I2C_SCL Spacing Loading Voltage As open drain signaling is used by the interface, these signals are susceptible to crosstalk from strongly driven aggressors. A spacing of 2 W is recommended at the minimum from other signals Run the traces short to the devices and reduce capacitive load The IPQ4029 chip operates this interface at 1.8 V and the input will not withstand higher voltage. Level converters are recommended to work with I2C devices at higher voltage 21 8.5. SD/eMMC SDIO DESIGN GUIDELINES:
Category Guidelines/Remarks Configurable function Pin name Signal/group SDIO_CD SDIO_CLK SDIO_DAT[0]
SDIO_DAT[1]
SDIO_DAT[2]
SDIO_DAT[3]
SDIO_DAT[4]
SDIO_DAT[5]
SDIO_DAT[6]
SDIO_DAT[7]
GPIO22 GPIO27 GPIO23 GPIO24 GPIO25 GPIO26 GPIO29 GPIO30 GPIO31 GPIO32 Route type Return path Length Single-ended 50 Ohm impedance Ensure continuous and unbroken return path without voids
< 4.5 in. Length match 10 mils within group Spacing requirements 2 W spacing to other signals GND shielding Now required Vias/layer transitions Vias are acceptable 1.8 V / 3.3 V auto change according to SD card If configured as eMMC interface, it is fixed 1.8 V Voltage Other Decoupling and power layout Allocate one 0201 decap per pin and locate it close to the pin A bulk capacitor in the order of 1 MF or more is advised for the device Follow best design practices and provide decoupling close to the SDIO device. Pay attention to SDIO_CLK, add 22 Ohm damping resistor and 5 pF paralleled cap to GND 22 8.6. PCIe PCIE DESIGN GUIDELINES FOR DATA SIGNALS:
Category Guidelines/Remarks Signal/group/group PCIE_TXP, PCIE_TXN PCIE_RXP, PCIE_RXN Route type Return path Length Length match within pair
+- 5mils
< 5 in. Differential pair 100 Ohm impedance Ensure continuous and unbroken return path without voids Length match across pairs There is no requirement to length match the Tx and Rx pairs Spacing requirements 3 W spacing between pairs and other signals after the breakout from module GND shielding Provide GND shield at 3 W spacing away from the signal pairs. The GND shape must be stitched to the main GND in inner layers with vias at regular intervals of 100 mils Vias/layer transitions Avoid layer transitions AC coupling Voltage Other There are already 0.1 uF capacitors on each signal line of the Tx pair on the module; No addi-
tional coupling is needed The voltage rails for the PCIe interface are implemented with filters for the PLL
(AVDDPLL_PCIE) and the I/O (AVDD) rails Clear the GND pour under the paired signal pads of the connector where SMD connectors are used PCIE DESIGN GUIDELINES FOR REFCLK:
Category Guidelines/Remarks Signal/group PCIE_CLKOUTN, PCIE_CLKOUTTP Route type Return path Length Length match within pair
+- 5 mils
< 5 in. Differential pair 100 Ohm impedance Ensure continuous and unbroken return path without voids Length match across pairs There is no specific requirements to match lengths across different REFCLK pairs Spacing requirements 3 W spacing between pairs and to other signals after the breakout from the module GND shielding Provide GND shield at 3 W spacing away from the signal pairs. The GND shape must be stitched to the main GND in inner layers with vias at regular intervals of 100 mils Vias/layer transitions Minimize layer transitions. Where necessary, limit to 2 vias per signal trace. Provide return vias interconnecting the GNDs in the immediate vicinity of the signal vias. These vias should form a symmetric GSSG pattern and recommend clearing an oblong void at this transition point through layers AC coupling Should not be used. The REFCLK must be DC connected to the loads 23 8.7. JTAG Category Signal/group Mechanical Spacing Routing JTAG DEBUG INTERFACE DESIGN GUIDELINES:
Guidelines/Remarks JTAG_TRST_N, JTAG_TDI, JTAG_TDO, JTAG_TMS, JTAG_TCK, JTAG_RST_N(SRST) Ensure sufficient clearance for placement of debug headers 2 W spacing is desirable Route short (< 5 in.) and direct traces with impedance control Length match No critical requirement; recommend keeping the signals matched within 500 mils Voltage Operates at 3.3 V; the PowerTrace debugger can be connected directly 9. Thermal considerations Thermal flow equals GND current flow Heat flows where current flows in copper Greater copper cross section Vertical copper cross section Move the heat to other layers Internal layers conduct heat horizontally Horizontal copper cross section More heat flow, more current flow through Via and GND structure Avoid fence of non-GND vias (reduce horizontal copper) Internal layers cannot get rid of heat Heat can be trapped on inner layers Opening the solder mask in top and bottom layers beneath the heat parts is the better way of radiating heat Also to have maximum GND copper possible with vertical copper (vias) to move heat from inner layers 24 10. Development board 10.1 DVK dimensions 140.0 0
. 5 9 6
. 0 2
0 1 0
. 3 25 10.2 DVK interfaces 15 9 9 2 3 15 8 14 7 6 9 9 1 4 4 4 4 4 11 12 13 1. Power 12V-24V 2. SD card socket 3. eMMC connector 4. Ethernet port 5. Buttons (Reset, GPIO8) 6. USB 3.0 (5V 1A) 7. USB 2.0 (5V 1A) 8. LEDs 9. Heatsink screws 10. Habanero module 11. FPC connector 12. PCIe connector 13. Heatsink 14. External NAND place 15. Dual-band antennas 26 10.3 LEDs 1 2 3 4 5 3 1 0 1 2 3 4 5 0 1 0 1 10.4 BOOTSTRAP switch 1 2 GPIO0~GPIO5 are used as JTAG interface. GPIO0~GPIO5 are normal GPIOs. Force boot from USB Normal boot GPIO14 AND GPIO51 CONFIGURATION GPIO51 GPIO14 ON OFF 0 0 1 1 LED number Description GPIO48 GPIO46 GPIO40 GPIO37 Power 4 1 0 5
Function description Boot interface is SPI Boot interface is eMMC Boot interface is QPIC Boot from USB 27 JTAG_EN USB_BOOT GPIO14 GPIO51 Not connected 10.5 DVK header pinout J13 Header pin GPIO Header pin GPIO Header pin GPIO 1 3 5 7 9 11 13 15 17 19 21 23 25 1 3 5 7 9 11 13 15 17 19 J17 Header pin GPIO Header pin GPIO 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 3.3V GPIO2 GPIO0 GPIO1 GPIO5 GPIO3 GPIO7 GPIO54 GPIO46 GPIO30 GPIO29 GPIO23 GPIO27 GPIO26 GPIO28 1 2 3 4 5 6 7 GPIO8 GND GPIO11 UART_RXD GPIO10 UART_TXD GPIO09 10 11 12 13 14 15 16 17 18 7 8 9 10 11
8 9 10 11 12 13 14 GPIO61 GPIO51 GPIO52 GPIO50 GPIO47 GPIO48 GPIO49 GPIO43 GPIO44 GPIO25 GPIO24 GPIO32 GPIO31 GPIO22
3.3V GPIO18 GPIO20 GPIO21 GPIO33 GND GPIO35 19 20 21 22 23 24 25 26
15 16 17 18 19 20
2 4 6 8 10 12 14 16 18 20 22 24 26 11 10 9 8 7 6 5 4 3 2 1 2 4 6 8 10 12 14 16 18 20 J18 Header pin GPIO Header pin GPIO Header pin GPIO GPIO45 GPIO41 GPIO42 GPIO39 GPIO40 GPIO37 GPIO36 GND
CHIP_RST_ OUT GPIO34 5V 3.3V GND 3.3V
28 10.6 DVK heatsink 140.0 102.6 77.6 53.4 38.5 3.5 0
. 5 9 5
. 8 6 6
. 9 4 7
. 5 2 4
. 5 2 5
. 2 1 5
. 3 0 3
. 3.5 4x M3 Threaded 5
. 3 5
. 3 5
. 3 8x M2.5 Threaded 3.5 3.5 29 11. Habanero packaging and ordering info Habanero modules are packed into trays. Each tray fits 15 modules. Every 5 trays are vacuum sealed and one standard packaging box contains 225 modules. FIGURE 12-1. HABANERO TRAY DIMENSIONS 280.0 53.4 3
. 9 5 0
. 0 0 2 A 0 0
. 5 1 0 8 2 2
. 0 6
. 0 5 5
. 4 4 B 1
. 0 5
. 1 1 1
. 0 0
. 0 1 B All Draft Angles 10 41.6 46.6 0.2 DETAIL A SCALE 2 : 3 SECTION B-B SCALE 1 : 1 FIGURE 12-2. STANDARD PACKAGING BOX DIMENSIONS 0 8 2 220 0 0 3 220 300 TABLE 12-3. ORDERING PART NUMBERS Habanero Habanero-I Habanero module, commercial temperature range 0C to 65C, IPQ 4019 SoC Habanero module, industrial temperature range -40C to 85C, IPQ 4029 SoC Habanero-DVK Development kit, based on Habanero module, IPQ 4019 SoC 30 12. Document Revision History Revision Revision Date 1.0 1.1 1.2 1.3 2019.08.05 2019.08.14 2019.09.06 2020.02.06 Description Initial release. Updated mechanical and added product packaging and ordering info. Updated J18 header pin 6 description on page 28. Updated table 3-2 (page 6) and table 3-9 (page 12). Pin ID B17 to B16. 31 Antenna info:
1. Type: Whip antenna Gain:2.4G :4.0 dBi 5G: Band 1: 4.5dBi, Band 4: 5dBi 2. Type: Planare WLAN antenna Gain:2.4G :-3.6 dBi 5G: -5.5 dBi 3. Type: Ceramic Antenna Gain:BT/BLE/2.4G :2.09dBi 5G: 4.32 dBi FCC Statement This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including Any Changes or modifications not expressly approved by the party responsible for compliance could void the interference that may cause undesired operation. user's authority to operate the equipment. Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. FCC Radiation Exposure Statement This modular complies with FCC RF radiation exposure limits set forth for an uncontrolled environment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. If the FCC identification number is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: Z9W-HAB Or Contains FCC ID: Z9W-HAB statements;
When the module is installed inside another device, the user manual of the host must contain below warning 1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference.
(2) This device must accept any interference received, including interference that may cause undesired operation. Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 2. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. The devices must be installed and used in strict accordance with the manufacturer's instructions as described in the user documentation that comes with the product. Any company of the host device which install this modular with limit modular approval should perform the test of radiated & conducted emission and spurious emission,etc. according to FCC part 15C : 15.249 and 15.209 &
15.207 ,15B Class B requirement, Only if the test result comply with FCC part 15C : 15.249 and 15.209 &
15.207 ,15B Class B requirementthen the host can be sold legally. IC STATEMENT device Sciences transmitter into This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canadas licence-exempt RSS(s). Operation is subject to the following two conditions:
(1) This device may not cause interference.
(2) This device must accept any interference, including interference that may cause undesired operation of the Cet appareil contient des metteurs / rcepteurs exempts de licence conformes aux RSS (RSS) d'Innovation, et Dveloppement conomique Canada. Le fonctionnement est soumis aux deux conditions suivantes :
(1) Cet appareil ne doit pas causer d'interfrences.
(2) Cet appareil doit accepter toutes les interfrences, y compris celles susceptibles de provoquer un fonctionnement indsirable de l'appareil. IC Radiation Exposure Statement This modular complies with IC RF radiation exposure limits set forth for an uncontrolled environment. This must not be co-located or operating in conjunction with any other antenna or transmitter. If the IC number is not visible when the module is installed inside another device, then the outside of the device which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains IC: 11468A-HAB when the module is installed inside another device, the user manual of this device must contain below warning statements;
Economic device. 1. This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Development Canadas licence-exempt RSS(s). Operation is subject to the following two conditions:
(1) This device may not cause interference.
(2) This device must accept any interference, including interference that may cause undesired operation of the 2. Cet appareil contient des metteurs / rcepteurs exempts de licence conformes aux RSS (RSS) d'Innovation, Sciences et Dveloppement conomique Canada. Le fonctionnement est soumis aux deux conditions suivantes :
(1) Cet appareil ne doit pas causer d'interfrences.
(2) Cet appareil doit accepter toutes les interfrences, y compris celles susceptibles de provoquer un fonctionnement indsirable de l'appareil. the user documentation that comes with the product. The devices must be installed and used in strict accordance with the manufacturer's instructions as described in