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User Manual | Users Manual | 490.76 KiB | ||||
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Internal Photos | Internal Photos | 2.43 MiB | ||||
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External Photos | External Photos | 218.80 KiB | ||||
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Label Artwork and Location | ID Label/Location Info | 129.88 KiB | ||||
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Block Diagram | Block Diagram | 338.38 KiB | ||||
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Circuit Diagram | Schematics | 158.51 KiB | ||||
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Letter of Agency | Cover Letter(s) | 282.38 KiB | ||||
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Technical Description | Operational Description | 1.94 MiB | ||||
1 | Test Report |
1 | User Manual | Users Manual | 490.76 KiB |
SUBWOOFER SBT1739-SWE USER ManUal SaFETY InSTRUCTIOnS On PlaCEMEnT Do not use the unit in places that are extremely hot, cold, dusty, or humid. The ventilation should not be impeded by covering the ventilation openings with items such as newspaper, table-cloths, curtains, etc. On SaFETY When connecting or disconnecting the AC power cord, grip the plug and not the cord itself. Pulling the cord may damage it and create a hazard. When you are not going to use the unit for a long period of time, disconnect the AC power cord. No naked flame sources such as lighted candles should be placed on the AC power cord and the unit. Leave a minimum of 10 cm around the apparatus for ventilation. Attention should be drawn to the environmental aspects of battery disposal. Use of apparatus in moderate climates. On COndEnSaTIOn When left in a heated room where it is warm and damp, water droplets or condensation may form inside the unit. When there is condensation inside the unit, the unit may not function normally. Let the unit stand for 1 to 2 hours before turning the power on, or gradually heat the room and let the unit dry before use. RaTIng PlaTE lOCaTIOn The rating plate is located at the rear of unit. WARNING:
Should any trouble occur, disconnect the AC power cord and refer servicing to a qualified technician. Mains plug is used as the disconnect device, it shall remain readily operable and should not be obstructed during intended use. To be completely disconnected the apparatus from supply mains, the mains plug of the apparatus shall be disconnected from the mains socket outlet completely. FCC InFORMaTIOn NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. COnnECT THE WIRElESS SUBWOOFER In order to use the subwoofer, you must pair it with the Soundbar RTS739BWS. 1. Connect the power cord to a wall outlet. 2. Turn on the Soundbar. 3. Turn the POWER switch on the back of the subwoofer to ON position. 4. The Soundbar and the subwoofer will automatically pair up. The wireless link pairing indicator will turn red when the wirelss link is activated. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Warning: Changes or modifications to this unit not expressly approved by the party responsible for compliance could void the users authority to operate the equipment. IMPORTanT SaFETY InSTRUCTIOnS 1. Read these instructions. 2. Keep these instructions. 3. Heed all warnings. 4. Follow all instructions. 5. Do not use this apparatus near water. 6. Clean only with a dry cloth. 7. Do not block any ventilation openings. Install in accordance with the manufacturers instructions. 8. Do not install near any heat sources such as radiators, heat registers, stoves, or other apparatus (including amplifiers) that produce heat. 9. Do not defeat the safety purpose of the polarized or grounding-type. A polarized power plug has two blades with one wider than the other. A grounding type power plug has two blades and a third grounding prong. The wide blade or the third prong is provided for your safety. When the provided power cord does not fit into your AC power outlet, consult an electrician for replacement of the obsolete outlet. 10. Protect the AC power cord from being walked on or pinched particularly at the power plug, convenience receptacles, and the point where they exit from the apparatus. 11. Only use attachments/accessories specified by the manufacturer. 12. Use only with the cart, stand, tripod, bracket, or table specified by the manufacturer, or sold with the apparatus. When a cart is used, use caution when moving the cart/apparatus combination to avoid injury from tip-over. 13. Unplug this apparatus during lightning storms or when unused for long periods of time. 14. Refer all servicing to qualified service personnel. Servicing is required when the apparatus has been damaged in any way, such as the AC power cord is damaged, liquid has spilled or objects have fallen into the apparatus, the apparatus has been exposed to rain or moisture, does not operate normally, or has been dropped. PlaCEMEnT POSITIOnIng SPEaKERS SUBWOOFER A subwoofer is designed to reproduce powerful low bass effects (explosions, the rumble of spaceships, etc.). It is not recommended to place the subwoofer near the TV set. Place the subwoofer at least 12 away from the TV. REaR SPEaKERS (SURROUnd SPEaKERS) Place Surround speakers to either side of the listening area, not behind it and if space permits, intall Surround speakers 2-3 feet above viewers. This help to minimize localization effects. The lightning flash with an arrowhead symbol, within the equilateral triangle, is intended to alert the user to the presence of uninsulated dangerous voltage within the products enclosure that may be of sufficient magnitude to cause an electric shock. The exclamation point within the equilateral triangle is intended to alert the user to the presence of important operating and maintenance
(servicing) instructions in this user manual. WARNING: THE APPARATUS SHALL NOT BE EXPOSED TO DRIPPING OR SPLASHING AND THAT NO OBJECTS FILLED WITH LIQUIDS, SUCH AS VASES, SHALL BE PLACED ON APPARATUS. WARNING: TO REDUCE THE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT EXPOSE THE APPLIANCE TO RAIN OR MOISTURE. CAUTION: USE OF CONTROLS OR ADJUSTMENTS OR PERFORMANCE OF PROCEDURES OTHER THAN THOSE SPECIFIED MAY RESULT IN HAZARDOUS RADIATION EXPOSURE. CAUTION: DANGER OF EXPLOSION IF BATTERY IS INCORRECTLY REPLACED. REPLACE ONLY WITH THE SAME OR EQUIVALENT TYPE. CAUTION: TO REDUCE THE RISK OF FIRE, DO NOT PLACE ANY HEATING OR COOKING APPARATUS BENEATH THIS UNIT. CAUTION: TO PREVENT ELECTRIC SHOCK, MATCH WIDE BLADE OF PLUG TO WIDE SLOT OF POWER OUTLET, THEN FULLY INSERT. It is important to read this instruction book prior to using your new product for the first time. The symbol for Class II (Double Insulation) COnnECTIOnS COnnECT THE lEFT/RIgHT REaR SPEaKERS Connect the speaker wire from the back of each speaker to the corresponding terminal at the back of the Wireless Subwoofer. Press down the tab to open the terminal and insert the wire. Release the tab to lock wire in the terminal. Note:
When connecting the speakers, make sure speaker wires connect to correct terminals as shown below. If the cords are reversed, the sound will be distorted. lOCaTIOn OF COnTROlS 1. Rear speakers terminal 2. Wireless link button/
Wireless link pairing indicator 3. Power switch 4. Power cord to wall outlet
1 | Label Artwork and Location | ID Label/Location Info | 129.88 KiB |
REAR OF SUBWOOFER MM = production month SL SR WIRELESS LINK AVC Multimedia MM/2015 CARB 93120 Compliant for Formaldehyde Model : SBT1739-SWE Power Source : 120V 60 Hz Power Consumption : 48W AVC Multimedia Markham, Ontario L3R 1E3 Made in China/Fabriqu en Chine/
Fabricado en China This device complies with Part 15 of the FCC Rules. Operation is subject two conditions: (1) This device may not cause harmful interference, and
(2) This device must accept any including interference received, interference that may cause undesired operation. CAN ICES-3 (B) / NMB-3 (B) FCC ID: A2HSBT1739-SWE following the to SUBWOOFER SUBWOOFER Model : SBT1739-SWE Power Source : 120V 60 Hz Power Consumption : 48W Venturer Electronics Inc. Markham, Ontario L3R 1B8 Made in China/Fabriqu en Chine/
Fabricado en China This device complies with Part 15 of the FCC Rules. Operation is subject two conditions: (1) This device may not cause harmful interference, and
(2) This device must accept any including interference received, interference that may cause undesired operation. CAN ICES-3 (B) / NMB-3 (B) FCC ID: A2HSBT1739-SWE following the to Letter size 2mm WARNING: SHOCK HAZARD - DO NOT OPEN AVERTISSEMENT: RISQUE DE CHOC LECTRIQUE - NE PAS OUVRIR DO NOT EXPOSE THIS UNIT TO RAIN OR MOISTURE NE PAS EXPOSER CET APPAREIL DE LA PLUIE OU DE LHUMIDIT
1 | Letter of Agency | Cover Letter(s) | 282.38 KiB |
Electronics Limited A member of the ALCO group 11/F Zung Fu Industrial Building,1067 Kings Road, Quarry Bay, Hong Kong Tel: (852) 2562 6121, Fax: (852) 2597 5201 , (852) 2811 1056 Letter of Agency
"I, an officer of Alco Electronics Ltd., do hereby authorize Intertek Testing Services
(Mr. Terry Chan / Koo Wai Ip / Kenneth Wong) to act on our behalf in front of the Federal Communications Commission with respect to all matters relating to certification of equipment under Part 15 and Part 18 of the FCC Rules until further notice."
I further certify that no party (as defined in 1.2002(b) of CFR 47, 2004) to this application, including myself, is subject to a denial of federal benefits, that includes FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C.,862. Dated this 2nd day of March, 2015 By _____________ ____ Signature _ Peggy Suen_____ _ ____ Printed Name _ Secretary, Engineering Dept.__ Title data base. Remark: The person who signs this authorization letter must be the grantee contact of record in the Grantee Code
1 | Technical Description | Operational Description | 1.94 MiB |
Technical Description The Equipment Under Test (EUT) is the wirless Subwoofer Unit (with two separate surround speakers) of Home Theatre Sound Bar. The audio signal can be sent via the 2.4GHz Digital wireless modules, which are incorporated in both soundbar unit and subwoofer unit. The EUT is powered by 120VAC mains. 2.4GHz Wireless Module:
Modulation Type: GFSK Antenna Type: Integral, Internal (PCB Trace) Frequency Range: 2404MHz - 2479MHz, 5MHz channel spacing, 16 channels Antenna Gain: 0dBi Nominal rated field strength: 92.0dBV/m at 3m Maximum allowed field strength of production tolerance: +/- 3dB The functions of main ICs are mentioned below. 1) XL9618 (U1) acts as I2S audio interface with DSP. 2) The 16MHz crystal (Y1) provides system clock for U1. 3) A7125 (U6) is 2.4GHz FSK transceiver. 4) L2 is antenna matching network. 5) AU1 (2110) is surround speaker amplifiers. 6) AU3 (2110) is subwoofer amplifier. 7) U8 (CE2711) is DAC for surround channels. 8) SIC303 (CE2766) is DAC for subwoofer channel. 2.4GHz wirless module (channel table) Channel Frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2.404GHz 2.409GHz 2.414GHz 2.419GHz 2.424GHz 2.429GHz 2.434GHz 2.439GHz 2.444GHz 2.449GHz 2.454GHz 2.459GHz 2.464GHz 2.469GHz 2.494GHz 2.479GHz GWK5NO_SW_TX Datasheet GWK5NO_SW 2.4GHz Wireless Subwoofer Module 1. General Description GWK5NO_SW is the optimized module dedicated for the wireless subwoofer application, it balance well between the cost and performance by utilizing the fact of subwoofer limited frequency response bandwidth. The narrow bandwidth enables GWK5NO_SW to transmit enough redundant data to combat with the 2.4GHz interference thus maintain the good co-existence performance in the 2.4GHz ISM band. Inheriting from its GWK5 family, GWK5NO_SW features both good wireless performance and audio performance. GWK5NO_SW has good RF co-existence and robust link quality, can combat the most interference from the crowded 2.4G ISM band. GWK5NO_SW uses non-compression PCM signal and 24bit high precision thus delivering very low THD audio. By adopting advance forward error correction and error concealment algorithm, GWK5NO_SW can reach <20ms latency, this makes it ideal for the Video synchronization, Home Theater applications. GWK5NO_SW is ideal for the subwoofer application not only by its competitive cost, but also by its flexibility for customized functions. The SW crossover frequency can be adjusted easily by the digital filter, and the general purpose I2C can be used to control customer peripheral unit to eliminate an extra microcontroller. 2. Applications
5.1 Subwoofer Speaker
2.1 Subwoofer Speaker
Soundbar Subwoofer
DVD 3. Features
2.4GHz AFH Solution
24bit high precision digital audioSNR>115dB
Optimized for subwoofer application, 20~250Hz bandwidth
Co-existence: small foot-print(2MHz bandwidth) enabling better 2.4GHz co-existence
Low Power: TX: 36mA/3.3V @ -3dBm RF Output
RF Range: 15m+ indoor
Pairing function to support multi TX/RX operating simultaneously
Optional I2S digital audio interface support most audio ADCs and DACs
Power management function and control for green power policy
General purpose I2C for digital amplifier control
Flexible design, custom functions supported 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 1 of 13 4. Electrical Specification Description Min/Typical/Max GWK5NO_SW_TX Datasheet Supply voltage TX:3.3V General Supply current TX: 36mA Operation temperature
-10 ~ +60 RF Frequency 2400 ~ 2483MHZ Modulation Data rate TX Power RX Sensitivity RF Channels RF Range RF GFSK 2M bps
-3dBm
-90dBm 16 15m+ indoor Output/input gain 1:1 Frequency response 20Hz ~ 600Hz (-3dB) Latency S/N ratio THD 20ms 115dB
< 0.01% @ 100Hz Dynamic range 90dB Table [1]: Electrical Specification 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 2 of 13 5. GWK5NO_SW Pin Assignment GWK5NO_SW_TX Datasheet Pin
1 GND 2 3.3V 3 MFB Pin name Type Description Ground
+3.3V Power Input I/O Power or pairing key input, press long than 3s to turn on or off the module, press long than 10s to enter pairing mode. 4 LED I/O Status LED output 5 MCLK I2S Master Clock Output, NC when I2S is in slave mode 6 7 8 9 I2SMOSI I2SMISO SCLK LRCK I2S Data Master Output / Slave Input I2S Data Master Input / Slave Output I2S Bit Clock Input / Output I2S Left and Right Clock Input / Output 10 SDA I2C Data or Standby Control, firmware configurable. For
/STANDBY Standby mode, A high level will be asserted when no TX signal >5s. When used as I2C, External 4.7K pull-up resister required. 11 SCL I/O I2C Clock or MUTE Control, firmware configurable.
/MUTE When used as I2C, External 4.7K pull-up resister required. 12 GND 13 NC 14 GP5 15 GP4 16 GP3 17 GP2 18 GP8 19 TXD 20 RXD Ground Not Connected General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO UART TX UART RX P P O I/O I/O I/O I/O I/O P NA P I/O I/O I/O I/O I/O I/O 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 3 of 13 GWK5NO_SW_TX Datasheet 21 RST 22 KEY 23 LR2 24 NC I I/O NA NA Reset input, active low Built-in ADC for KEY Not Connected Not Connected Table [2]. GWK5NO_SW Pin Description 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 4 of 13 GWK5NO_SW_TX Datasheet I2S Digital Audio Interface 6. GWK5NO_SW supports 3 digital audio interface modes: Left justify mode, I2S mode and Right justify mode. Figure [1]. Left Justify Mode Figure [2]. Default I2S Mode Figure [3]. Right Justify Mode 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 5 of 13 GWK5NO_SW_TX Datasheet GWK5NO_SW I2S interface can work as master or slave mode, the IO pin function is described below. The default configuration is GWK5NO_SW Tx in I2S slave mode, and GWK5NO_SW RX in left justify master mode. Other configurations are available upon customer request. Master Mode Slave Mode MCLK Output, Driving the external DSP or Non function, can be left open Codec Codec Codec BCLK Output, Driving the external DSP or Input, Driven by the external DSP or LRCK Output, Driving the external DSP or Input, Driven by the external DSP or MISO MOSI PCM Data Input PCM Data Output Table [3]: GWK5NO_SW I2S Interface Codec Codec PCM Data Output PCM Data Input 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 6 of 13 7. Application Schematic GWK5NO_SW_TX Datasheet GWK5NO_SW
+3.3V GND 3.3VIN KEY MSB LED MCLK MOSI MISO SCLK LRCK SDA SCL R1 2K KEY1 LED L C S A D S K C R L K L C S N I D S I2C Control To DSP I2S Output Figure [4]: GWK5NO_SW Interfacing with DSP (I2S Slave Input Mode) 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 7 of 13 2 0 0 8
2 0 1 3 G g a w i i t l E e c t r o n c s i L d t
. V e r s o n 1 i
. 0 1 P a g e 8 o f 1 3 i F g u r e
5
G W K 5 N O _ S W I n t e r f a c n g w i i t h A D C J5
+5V 1 2 3 4 5
D-
D+
C1 220uF/16V USB J4 C5 0.1uF/X7R D2 1 2
+5V BAT 1N5819 R1 0R 3.3VIN VCC33 U2 1 2 3 Vin GND ON/OFF Vout NC 5 4 RT9193 C6 0.1uF/X7R C2 0.1uF/X7R C4 10uF/10V/X7R J3 J2 1 2 3 2 1 Shunt for ISP TXD RXD R11 4.7K
NC GPIO5 GPIO4 GPIO3 GPIO2 GPIO8 TXD RXD RSTN ADCKEY NC NC J1 12 13 14 11 15 10 16 9 17 8 18 7 19 6 20 5 21 4 22 3 23 2 24 1 GWK5NO SCL SDA I2SLRCK I2SSCLK I2SSDIN I2SMOSI I2SMCLK BLED MFB 3.3VIN SW1 MFB R10 1K D1 BLUE
+5V R3 5R1 VA I2SMCLK I2SLRCK C10 10uF/10V/X7R 14 13 12 11 10 9 8 U3 DGND MLCK LRCK NOHP AGND AVDD LIN WM8738 DVDD SDATO BCLK FMT CAP VREF RIN 1 2 3 4 5 6 7 VCC33 C7 0.1uF/X7R I2SSDIN I2SSCLK C13 10uF/10V/X7R C14 10uF/10V/X7R 10uF/10V/X7R C8 C11 10uF/10V/X7R R4 10K R6 10K C9 1nF/NPO R2 470 R5 470 C12 1nF/NPO RCH J6 LCH Line In G W K 5 N O _ S W _ T X D a t a s h e e t GWK5NO_SW_TX Datasheet ISP Firmware Updating 8. GWK5NO_SW support ISP firmware updating through UART, When TXD pin connected with a 4.7K resistor to the GND, GWK5NO_SW will enter the ISP mode. Figure [6]: Gigawit ISP tool GWK5 Module USB to UART RXD TXD GND TXD RXD GND J1 Short for ISP R1 4.7K Figure [7]: Gigawit ISP Connection 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 9 of 13 GWK5NO_SW_TX Datasheet 9. Pairing GWK5NO_SW support ID matching to enable multi TX/RX operating in a same area. The RX will only receive the paired TX audio signals. To pair the TX and RX module, follow the below steps. 1) Power on the TX and RX Module. The TX/RX LED will keep solid for 5 seconds, and then turn into Idle Mode and flash slowly. 2) Press the TX key long than 10 seconds Until the LED change into flashing fast. Release After this, The TX Module will stay into Pairing Mode for 30 seconds until it find the RX
(the RX must be in Pairing Mode in 30 seconds, see Step 3).If the TX found the RX in 30 seconds and paired, the LED will turn to solid and quit the Pairing Mode, or it will be time out after 30 seconds and turn the Pairing Mode into the Idle Mode. 3) Press the RX key long than 10 seconds Until the LED change into flashing fast. Release the key. the key. After this, The RX Module will stay into Pairing Mode for 30 seconds until it find the TX
(the TX must be in Pairing Mode, see Step 2) If the RX found the RX in 30 seconds and paired, the LED will turn to solid and quit the Pairing Mode, or it will be time out after 30 seconds and turn the Pairing Mode into the Idle Mode. 4) When the TX and the RX are paired, The TX/RX LED will stay in solid .the RX can receive the TX signal. Figure [8]: Key and LED Timing at pairing mode In some application, a simple pairing method can be implemented by using a slider switch with 4 positions. See the following schematic, 4 IDs can be set using the switch. To be paired, the TX/RX switch S2 should be in the same position. The module will be rebooted when the switch id changed to let the ID be effective. The whole pairing ID is a combination of above KEY/LED pairing ID (stored in EEPROM) and the switch ID(see table [5]) 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 10 of 13 10. Physical Dimension GWK5NO_SW_TX Datasheet Figure [9]. GWK5NO_SW Module outline 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 11 of 13 11. Naming Rule GWK5NO_SW_TX Datasheet
12. Tx LabelIntro 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 12 of 13 13. Ordering Information GWK5NO_SW_TX Datasheet Gigawit ID. Description GWK5NO_SW1 GWK5NO_SW TX I2S slave mode RX I2S master mode GWK5NO_SW2 GWK5NO_SW TX I2S master mode RX I2S master mode 14. Contact
Gigawit Electronics Limited 512 Building R2-A, Virtual University ,Science Park, Nanshan District, 518057 Shenzhen, China Tel:+86-755-86329300, Fax:+86-755-86329882 http://www.gigawit.com 15. Revision History 2011-06-01 Version 1.0, Original version 2013-01-05 Version 1.01, Add LabelIntro 2008-2013 Gigawit Electronics Ltd. Version 1.01 Page 13 of 13 2.4GHz FSK Transceiver A7125 A7125 Data Sheet, 2.4GHz FSK Transceiver with 2M / 1Mbps data rate Document Title Revision History Rev. No. History Initial issue. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 Logo change. Modify PIN Configuration and Description, Block Diagram, Electrical Specifications, Diagram of State Machine. Add Control Register and Function Description. Add Power Saving FIFO Mode. Rename GPIO1 and GPIO2 into GIO1 and GIO2. IFAT Register (36h): IGFI [2:0] = [111], IGFQ [2:0] = [111]
Modify register recommended value IGFI [2:0] = [000]
Modify register recommended value IGFQ [2:0] = [000]
Delete TWWS function Modify register recommended value Delay Register I (17h): PDL= [000]
Delay Register II (18h): WSEL= [011]
Battery Detect Register (2Ch): QDS = [1]
Crystal Test Register (32h): XCP= [00]
Modify PLL to WPLL settling time when PDL=[000]
If LO is changed, from 20 us to 30 us If LO is fixed, from 20 us to 10 us Delete Ext Voltage Measurement function Add EOPD output to GIO2 Add PASW output to GIO2 Add EOPDS Register Add section 16.5 Modify register recommended value ADC Control (1Fh): CDM= [0]
Modify recommended timing of PASW Issue Date Aug. 31, 2007 Oct. 18, 2007 July 31, 2008 Remark Preliminary Preliminary Preliminary August 31, 2008 Preliminary October 06, 2008 Preliminary June 11, 2009 Preliminary 1.1 Add Note 8 (regulator settling time) in chapter 8. Nov., 2010 Feb., 2010 Full Production Full Production Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such applications is understood to be fully at the risk of the customer. Nov., 2010, v1.1 1 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Table of Contents 1. Typical Application ..................................................................................................................................................... 5 2. General Description ................................................................................................................................................... 5 3. Feature ..................................................................................................................................................................... 5 4. PIN Configuration ...................................................................................................................................................... 6 5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital)........................................................... 7 6. Block Diagram ........................................................................................................................................................... 8 7. Absolution Maximum Rating ....................................................................................................................................... 9 8. Electrical Specifications............................................................................................................................................ 10 General ................................................................................................................................................................ 10 Phase Locked Loop .............................................................................................................................................. 10 Transmitter ........................................................................................................................................................... 10 Receiver............................................................................................................................................................... 10 Regulator ............................................................................................................................................................. 10 Digital IO DC characteristics...................................................................................................................................11 9. Control Register....................................................................................................................................................... 12 9.1 Control Register Table..................................................................................................................................... 12 9.2 Control Register Description............................................................................................................................ 15 9.2.1 Mode Register (Address: 00h) ............................................................................................................... 15 9.2.2 Mode Control Register (Address: 01h) ................................................................................................... 15 9.2.3 Calibration Control Register (Address: 02h)............................................................................................ 16 9.2.4 FIFO Register I (Address: 03h) .............................................................................................................. 16 9.2.5 FIFO Register II (Address: 04h) ............................................................................................................. 16 9.2.6 FIFO DATA Register (Address: 05h)....................................................................................................... 16 9.2.7 ID DATA Register (Address: 06h) ........................................................................................................... 16 9.2.8 RC OSC Register I (Address: 07h)......................................................................................................... 17 9.2.9 RC OSC Register II (Address: 08h)........................................................................................................ 17 9.2.10 RC OSC Register III (Address: 09h)..................................................................................................... 17 9.2.11 CKO Pin Control Register (Address: 0Ah)............................................................................................. 17 9.2.12 GIO1 Pin Control Register (Address: 0Bh)............................................................................................ 17 9.2.13 GIO2 Pin Control Register (Address: 0Ch) ........................................................................................... 18 9.2.14 Data Rate Clock Register (Address: 0Dh)............................................................................................. 19 9.2.15 PLL Register I (Address: 0Eh).............................................................................................................. 21 9.2.16 PLL Register II (Address: 0Fh)............................................................................................................. 21 9.2.17 PLL Register III (Address: 10h) ............................................................................................................ 21 9.2.18 PLL Register IV (Address: 11h) ............................................................................................................ 21 9.2.19 PLL Register V (Address: 12h)............................................................................................................. 21 9.2.20 Channel Group Register I (Address: 13h) ............................................................................................. 21 9.2.21 Channel Group Register II (Address: 14h) ............................................................................................ 22 9.2.22 TX Register I (Address: 15h)................................................................................................................ 22 9.2.23 TX Register II (Address: 16h)............................................................................................................... 22 9.2.24 Delay Register I (Address: 17h) ........................................................................................................... 23 9.2.25 Delay Register II (Address: 18h) .......................................................................................................... 23 9.2.26 RX Register (Address: 19h) ................................................................................................................. 24 9.2.27 RX Gain Register I (Address: 1Ah)....................................................................................................... 24 9.2.28 RX Gain Register II (Address: 1Bh)...................................................................................................... 24 9.2.29 RX Gain Register III (Address: 1Ch)..................................................................................................... 25 9.2.30 RX Gain Register IV (Address: 1Dh) .................................................................................................... 25 9.2.31 RSSI Threshold Register (Address: 1Eh).............................................................................................. 25 9.2.32 ADC Control Register (Address: 1Fh)................................................................................................... 25 9.2.33 Code Register I (Address: 20h) ............................................................................................................ 26 9.2.34 Code Register II (Address: 21h)........................................................................................................... 26 9.2.35 Code Register III (Address: 22h) .......................................................................................................... 26 9.2.36 IF Calibration Register I (Address: 23h)................................................................................................ 26 9.2.37 IF Calibration Register II (Address: 24h)............................................................................................... 27 9.2.38 VCO Current Calibration Register (Address: 25h) ................................................................................. 27 9.2.39 VCO Bank Calibration Register I (Address: 26h)................................................................................... 27 9.2.40 VCO Bank Calibration Register II (Address: 27h).................................................................................. 28 9.2.41 VCO Deviation Calibration Register I (Address: 28h) ............................................................................ 28 9.2.42 VCO Deviation Calibration Register II (Address: 29h) ........................................................................... 28 9.2.43 VCO Deviation Calibration Register III (Address: 2Ah) .......................................................................... 28 9.2.44 VCO Modulation Delay Register (Address: 2Bh)................................................................................... 29 9.2.45 Battery Detect Register (Address: 2Ch)................................................................................................ 29 Nov., 2010, v1.1 2 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 9.2.46 TX test Register (Address: 2Dh)........................................................................................................... 29 9.2.47 RX DEM test Register I (Address: 2Eh)................................................................................................ 29 9.2.48 RX DEM test Register II (Address: 2Fh) ............................................................................................... 30 9.2.49 Charge Pump Current Register I (Address: 30h)................................................................................... 30 9.2.50 Charge Pump Current Register II (Address: 31h).................................................................................. 30 9.2.51 Crystal test Register (Address: 32h) ..................................................................................................... 30 9.2.52 PLL test Register (Address: 33h).......................................................................................................... 30 9.2.53 VCO test Register (Address: 34h) ........................................................................................................ 31 9.2.54 RF Analog test Register (Address: 35h)................................................................................................ 31 9.2.55 IFAT Register (Address: 36h) ............................................................................................................... 31 9.2.56 Channel Select Register (Address: 37h)............................................................................................... 32 9.2.57 VRB Register (Address: 38h) ............................................................................................................... 32 10. SPI........................................................................................................................................................................ 33 10.1 SPI Format ................................................................................................................................................... 34 10.2 SPI Timing Characteristic .............................................................................................................................. 34 10.3 SPI Timing Chart........................................................................................................................................... 34 10.3.1 Timing Chart of 3-wire SPI ................................................................................................................... 34 10.3.2 Timing Chart of 4-wire SPI ................................................................................................................... 35 10.4 Strobe Commands ........................................................................................................................................ 35 10.4.1 Strobe Command - Sleep Mode ........................................................................................................... 36 10.4.2 Strobe Command - ldle Mode............................................................................................................... 36 10.4.3 Strobe Command - Standby Mode........................................................................................................ 37 10.4.4 Strobe Command - PLL Mode.............................................................................................................. 37 10.4.5 Strobe Command - RX Mode ............................................................................................................... 38 10.4.6 Strobe Command - TX Mode................................................................................................................ 38 10.4.7 Strobe Command FIFO Write Pointer Reset ...................................................................................... 38 10.4.8 Strobe Command FIFO Read Pointer Reset ...................................................................................... 39 10.5 Reset Command........................................................................................................................................... 39 10.6 ID Accessing Command ................................................................................................................................ 39 10.6.1 ID Write Command.............................................................................................................................. 40 10.6.2 ID Read Command.............................................................................................................................. 40 10.7 FIFO Accessing Command............................................................................................................................ 40 10.7.1 TX FIFO Write Command .................................................................................................................... 40 10.7.2 Rx FIFO Read Command .................................................................................................................... 41 11. State machine........................................................................................................................................................ 42 11.1 Key states ..................................................................................................................................................... 42 11.1.1 Standby mode ..................................................................................................................................... 42 11.1.2 Sleep mode ......................................................................................................................................... 43 11.1.3 ldle mode ............................................................................................................................................ 43 11.1.4 PLL mode............................................................................................................................................ 43 11.1.5 TX mode ............................................................................................................................................. 43 11.1.6 RX mode............................................................................................................................................. 43 11.1.7 CAL mode ........................................................................................................................................... 44 11.2 Normal FIFO Mode........................................................................................................................................ 45 11.3 Quick FIFO Mode.......................................................................................................................................... 47 11.4 Power Saving FIFO Mode.............................................................................................................................. 48 11.5 Quick Direct Mode......................................................................................................................................... 51 12 Crystal Oscillator Circuit.......................................................................................................................................... 54 12.1 Use External Crystal...................................................................................................................................... 54 12.2 Use External Clock........................................................................................................................................ 54 13. System Clock ........................................................................................................................................................ 55 13.1 Derive System Clock ..................................................................................................................................... 55 13.2 Data Rate ..................................................................................................................................................... 56 14. Transceiver Frequency........................................................................................................................................... 57 14.1 LO Frequency Setting ................................................................................................................................... 58 14.2 IF Side Band Select ...................................................................................................................................... 61 14.2.1 Auto IF Exchange................................................................................................................................ 62 14.2.2 Fast Exchange .................................................................................................................................... 62 14.3 Band Edge Frequency Setting ....................................................................................................................... 63 14.4 Frequency Compensation.............................................................................................................................. 65 15. Calibration............................................................................................................................................................. 67 15.1 Calibration Procedure.................................................................................................................................... 67 15.2 IF Filter Bank Calibration ............................................................................................................................... 67 15.3 RSSI Calibration ........................................................................................................................................... 67 15.4 VCO Current Calibration................................................................................................................................ 68 15.5 VCO Bank Calibration ................................................................................................................................... 68 Nov., 2010, v1.1 3 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 15.6 VCO Deviation Calibration............................................................................................................................. 68 15.7 Channel Group Function ............................................................................................................................... 68 16. FIFO (First In First Out).......................................................................................................................................... 70 16.1 Packet Format of FIFO mode ........................................................................................................................ 70 16.2 Bit Stream Process........................................................................................................................................ 71 16.3 Transmission Time ........................................................................................................................................ 71 16.4 Usage of TX and RX FIFO............................................................................................................................. 72 16.4.1 Easy FIFO........................................................................................................................................... 72 16.4.2 Segment FIFO..................................................................................................................................... 73 16.4.3 FIFO Extension ................................................................................................................................... 76 16.5 Optimize Throughput..................................................................................................................................... 80 17. ADC (Analog to Digital Converter) .......................................................................................................................... 82 17.1 Temperature Measurement............................................................................................................................ 82 17.2 RSSI Measurement....................................................................................................................................... 82 17.3 Carrier Detect ............................................................................................................................................... 84 18. Battery Detect........................................................................................................................................................ 85 19. Application Circuit Example .................................................................................................................................... 86 20. Abbreviations......................................................................................................................................................... 87 20. Abbreviations......................................................................................................................................................... 88 21. Ordering Information .............................................................................................................................................. 88 22. Package Information .............................................................................................................................................. 89 23. Top Marking Information......................................................................................................................................... 90 24. Reflow Profile ........................................................................................................................................................ 91 25. Tape Reel Information............................................................................................................................................ 92 26. Product Status ....................................................................................................................................................... 94 Nov., 2010, v1.1 4 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 1. Typical Application 2. General Description 2.4GHz ISM band Communication System 2.4GHz Remote Control n n n Wireless Keyboard and Mouse Wireless Intelligent sports Wireless Toy and Gaming Wireless Audio/Video Streaming A7125 is a high performance and low cost 2.4GHz ISM band wireless transceiver. It integrates high sensitivity receiver
(-90dBm @2Mbps), high efficiency power amplifier (up to 3dBm), frequency synthesizer and base-band modem. In typical system, A7125 is used together with MCU (microcontroller) with very few external passive components. A7125 supports both FIFO mode and direct mode that contains clock recovery circuit CKO pin to MCU. A7125 supports very fast settling time (90 us) for frequency hopping system. For packet handling, A7125 has built-in separated 64-bytes TX/RX FIFO (could be extended to 256 bytes) for data buffering and burst transmission, CRC for error detection, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, data whitening for data encryption/decryption, thermal sensor for monitoring relative temperature. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. A7125s data rate is up to 2Mbps and can be easily programmed to 1Mbps or 2 Mbps via 3-wire or 4-wire SPI bus. For power saving, A7125 supports sleep mode, idle mode, standby mode. For easy-to-use, A7125 has an unique SPI command set called Strobe command that are used to control A7125s state machine. Based on Strobe commands, from power saving, TX delivery, RX receiving, channel monitoring, frequency hopping to auto calibrations, MCU only needs to define A7125s control registers and send Strobe commands via SPI bus. In addition, A7125 supports two general purpose I/O pins, GIO1 and GIO2, to inform MCU its status so that MCU could use either polling or interrupt scheme to do radio control. Therefore, it is very easy to monitor transmission between MCU and A7125 because of its digital interface. 3. Feature n n n n n n n n n n n n n n n n n Support 3-wire or 4-wire SPI. Small size (QFN 4X4, 20 pins). Support 2400 ~ 2483.5 MHz ISM band. FSK modulation. Programmable data rate to 1Mbps or 2Mbps. Low current consumption: RX 17mA, TX 15.7mA (at 0dBm output power). Low sleep current (1.5uA). Programmable RF output power -20dBm ~ 3dBm. Very High sensitivity (-90dBm@2Mbps, -92dBm@1Mbps). On chip regulator, supports input voltage 2.0 ~ 3.6V. Easy to use u u Unique Strobe command via SPI. u Change frequency channel by ONE register setting. u u u u u u u u Data Whitening for encryption and decryption. u u u u Support low cost crystal (6 / 8 /12 / 16MHz). Support low accuracy crystal within 50ppm. Support Auto Frequency Compensation. Support crystal sharing, (1 / 2 / 4 / 8MHz) to MCU. Fast settling time synthesizer for frequency hopping system. Built-in thermal sensor for monitoring relative temperature. Built-in Battery Detector. 8-bits Digital RSSI for clear channel indication. Fast exchange mode during TRX role switching. Auto RSSI measurement. Auto Calibrations. Auto IF function. Auto CRC Check. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 256 bytes). Support direct mode with recovery clock output to MCU. Support direct mode with frame sync signal to MCU. Nov., 2010, v1.1 5 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 4. PIN Configuration Figure 4.1 A7125 QFN 4x4 Package Top View Nov., 2010, v1.1 6 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 5. PIN Description (I: Input, O: Output, I/O: Input or Output, G: Ground, D: Digital) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol BP_RSSI BP_BG VDD_VCO VDD_PLL RFI RFO RFC CP XI XO SCS SCK VDD_D SDIO GND GIO1 GIO2 CKO REGI VDD_A Back side plate I/O O O I O I I O O I O DI DI O DI/O G DI/O DI/O DO I O G Function Description O: RSSI bypass. Connect to bypass capacitor. Band-gap bypass. Connect to bypass capacitor. RF input. Connect to matching circuit. RF output. Connect to matching circuit. RF choke input. Connect to matching circuit. VCO supply voltage input. Charge-pump output. Connect to loop filter. PLL supply voltage input. Crystal oscillator input. Connect to tank capacitor. Crystal oscillator output. Connect to tank capacitor. SPI chip select input. SPI clock input. Digital supply voltage output. Connect to bypass capacitor. SPI data IO. Ground. Multi-function IO 1 / SPI data output. Multi-function IO 2 / SPI data output. Multi-function clock output. Regulator input. Connect to VDD supply. Analog supply voltage output. Connect to bypass capacitor. Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. Nov., 2010, v1.1 7 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 6. Block Diagram A _ D D V 20 I G E R 19 O K C 18 2 O G I 17 1 O G I 16 I O F F X R I O F F X T 10 O X BP_RSSI 1 ADC Regulator/
Thermal sensor Radio Control 15 GND RFI LNA PA VCO PLL BP_BG 2 3 4 RFO RFC 5 14 SDIO 13 VDD_D 12 SCK M E D O M l r e d n a H t e k c a P P S B I P S XOSC 11 SCS 6 O C V _ D D V 7 P C 8 L L P _ D D V 9 I X Figure 6.1 A7125 Block Diagram Nov., 2010, v1.1 8 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 7. Absolution Maximum Rating Parameter With respect to Supply voltage range (VDD) Digital I/O pins range Voltage on the analog pins range Input RF level Storage Temperature range ESD Rating GND GND GND HBM MM
-0.3 ~ VDD+0.3 Rating
-0.3 ~ 3.6
-0.3 ~ 2.1 14
-55 ~ 125 2K 100 Unit V dBm V V C V V
*Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A.
*Device is Moisture Sensitivity Level III (MSL 3). Nov., 2010, v1.1 9 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 8. Electrical Specifications
(Ta=25, VDD=3.3V, data rate= 2Mbps, FXTAL =16MHz, with Matching Network and low pass filter, On Chip Regulator =
1.8V, unless otherwise noted.) Parameter Description Minimum Typical Maximum Unit General Operating Temperature Supply Voltage (VDD) Current Consumption
-40 2.0 85 3.6 3.3 1.5(1*) 300(1*) Regulator supply input Sleep Mode Idle Mode (Regulator on) Standby Mode (XOSC on, Clock generator on) PLL Mode RX Mode (2Mbps) RX Mode (1 Mbps) TX Mode (@3dBm output) TX Mode (@0dBm output) TX Mode (@-10dBm output) TX Mode (@-20dBm output)
@Loop BW = 200 KHz 30MHz~1GHz 1GHz~12.75GHz 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz
@Loop BW =200 KHz 2Mbps 1Mbps Co-Channel (C/I0) 1st Adjacent Channel (C/I1) 2nd Adjacent Channel (C/I2) 3rd Adjacent Channel (C/I3) Image (C/IIM)
@RF input (BER=0.1%) 30MHz~1GHz 1GHz~12.75GHz
@RF input
@Loop BW = 200 KHz 1
-100 6(3*), 8, 12, 16 2400 2483.5 C V uA uA mA mA mA mA mA mA mA mA us MHz MHz ms dBm dBm Mbps KHz ms dBm dBm MHz dB dB dB dB dB dBm dBm dBm ms ms V V 2.9 9.8 17.0 16.2 21 15.7 13.7 13.3 300 30 0 2 500 40
-90
-92 2 11 2
-18
-28
-12 40 500 1.23 1.8
-36
-30
-47
-47 2 3
-57
-47
-50 Phase Locked Loop XTAL Start-up Time (2*) XTAL Frequency (FXTAL) VCO Operation Frequency PLL Settling Time (4*) Transmitter TX Power Control Range Out Band Spurious Emission (5*) Data rate Frequency Deviation TX Settling Time (6*) Receiver Sensitivity @BER=0.001 Sensitivity @BER=0.001 IF Frequency (FIF) Interference (7*) Maximum Operating Input Power Spurious Emission (5*) RSSI Range RX Settling Time Regulator Regulator settling time (8*) Band-gap reference voltage Regulator output voltage Nov., 2010, v1.1 10 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver Digital IO DC characteristics High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL)
@IOH= -0.5mA
@IOL= 0.5mA 0.8*VDD VDD-0.4 0 0 VDD 0.2*VDD VDD 0.4 V V V V Note 1: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall be pulled high only); otherwise, more leakage current will be induced in all operation modes. Note 2: Refer to Delay Register II (18h) to set up crystal settling delay. Note 3: If 6MHz external crystal is selected, A7125 only supports 1Mbps data rate. Note 4: Refer to Delay Register I (17h) to set up PDL (PLL settling delay). Note 5: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz
~12.75GHz. Note 6: Refer to Delay Register I (17h) to set up TDL delay. Note 7: The power level of wanted signal is set at sensitivity +3dB. The modulation data for wanted signal and interferer are PN9 and PN15, respectively. Channel spacing is 2MHz. Note 8: When VDD < 2.1V and temperature < -30 degree C, the regulator settling time will arise up to 20ms. Nov., 2010, v1.1 11 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 9. Control Register A7125 has totally built-in 57 control registers that cover all radio control. MCU can access those control registers via 3-wire or 4-wire SPI (Support max. SPI data rate up to 10 Mbps). User can refer to chapter 10 for details of SPI bus. A7125 is simply controlled by registers and outputs its status to MCU by GIO1 and GIO2 pins. 9.1 Control Register Table Address /
R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode control DDPC DDPC RESETN RESETN RESETN RESETN RESETN RESETN RESETN FECF ARSSI ARSSI
CRCF AIF AIF
CER DFCD CD VCC XER WWSE WWSE VBC RESETN PLLER FMT FMT VDC TRSR FMS FMS FBC TRER ADCM ADCM RSSC
SDR1 SDR1 DBL DBL BIP7 IP7 BFP15
-FP15 BFP7 Name 00h Mode 01h 02h Calc 03h FIFO I 04h FIFO II 05h FIFO Data 06h ID Data RC OSC I 07h 08h 09h 0Ah 0Bh 0Ch 0Dh RC OSC II RC OSC III CKO Pin GIO1 Pin I GIO2 Pin II 0Eh PLL I 0Fh PLL II 10h PLL III 11h PLL IV 12h PLL V 13h 14h 15h TX I 16h TX II 17h Delay I 18h Delay II 19h RX 1Ah RX Gain I W R W R W W R/W W W W W W R W R W R W R W R W W W W W Data Rate Clock R/W CHN7 FEP7 FEP6 FEP5 FEP4 FEP3 FEP2 FEP1 FEP0 FPM1 FPM0 PSA5 PSA4 PSA3 PSA2 PSA1 PSA0 R/W FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 R/W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0 R RCOC0 RCOC5 RCOC3 RCOC2 RCOC1 RCOC4
W WWS_SL9 WWS_SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0 BBCKS1 BBCKS0
RCOSC_E TSEL TWWS_E ECKOE CKOS3 CKOS2 CKOS1 CKOS0 CKOI CKOE SCKI
SDR0 SDR0 CHN6 RRC1 RRC1 BIP6 IP6 BFP14 GIO1S3 GIOS2 GIO1S1 GIO1S0 GIO1I GIO1OE GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE GRC3 GRC3 CHN5 RRC0 RRC0 BIP5 IP5 BFP13 GRC1 GRC2 CHN4 CHR3 CHR3 BIP4 IP4 BFP12 GRC1 GRC1 CHN3 CHR2 CHR2 BIP3 IP3 BFP11 GRC0 GRC0 CHN2 CHR1 CHR1 BIP2 IP2 BFP10 CGS
CHN1 CHR0 CHR0 BIP1 IP1 BFP9 XS
CHN0 IP8 BIP8 BIP0 IP0 BFP8 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 AC9-FP9 AC8-FP8 BFP6 BFP5 BFP4 BFP3 BFP2 BFP1 BFP0 AC7-FP7 AC6-FP6 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 AC1-FP1 AC0-FP0 R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 R/W CHGH7 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 Channel Group I Channel Group II SDMS TMDE TXDI TME
FDP2 FDP1 FDP0 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 EOPDS DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0
RXSM1 RXSM0 FC RXDI DMG RAW ULS R/W MVGS MRHL IGS MGS1 MGS0 LGS2 LGS1 LGS0 Nov., 2010, v1.1 12 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 RX Gain II RX Gain III RX Gain IV 1Bh 1Ch 1Dh 1Eh 1Fh ADC Control RSSI Threshold 20h Code I 21h Code II 22h Code III IF Calibration I IF Calibration II 23h 24h 25h 26h 27h 28h 29h VCO current Calibration VCO band Calibration I VCO band Calibration II VCO deviation Calibration I VCO deviation Calibration II 2Ah VCO deviation Calibration III 2Bh Delay 2Ch 2Dh TX test 2Eh Battery detect Rx DEM test I Rx DEM test II 2Fh 30h Charge Pump Current I 31h Charge Pump Current II Crystal test 32h 33h 34h 35h PLL test VCO test RF Analog test W W W W R W W W W W R R W R W R W R W R W R W W W R W W W W W W W W W RH7 RL7 RH6 RL6 RH5 RL5 RH4 RL4 RH3 RL3 AVSEL1 AVSEL0 MVSEL1 MVSEL0 MHC RTH7 ADC7 RTH6 ADC6 RTH5 ADC5 RTH4 ADC4 RTH3 ADC3 RSM1 RSM0 RADC1 RADC0 FSARS XADS RH2 RL2 LHC1 RTH2 ADC2 WS2 MFB2 FB2 FCD2 VCB2 MVB2 VB2 RH1 RL1 LHC0 RTH1 ADC1 RSS WS1 MFB1 FB1 FCD1 VCB1 MVB1 VB1 RH0 RL0 AGCE RTH0 ADC0 CDM WS0 MFB0 FB0 FCD0 VCB0 MVB0 VB0 WHTS FECS CRCS IDL PML1 PML0 DCL2 DCL1 DCL0 ETH1 ETH0 PMD1 PMD0 WS6 WS5 WS4 MFBS FBCF FCD4 VCCF
WS3 MFB3 FB3 FCD3 VCB3 MVBS VBCF VCCS MVCS VCOC3 VCOC2 VCOC1 VCOC0 DDC1 DDC0 MDAGS MDAG7 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 ADAG7 ADAG6 ADAG5 ADAG4 ADAG3 ADAG2 ADAG1 ADAG0 DEVS3 DEVS2 DEVS1 DEVS0 DAMR_M VMTE_M VMS_M MSEL DEVA7 DEVA6 DEVA5 DEVA4 DEVA3 DEVA2 DEVA1 DEVA0 MVDS MDEV6 MDEV5 MDEV4 MDEV3 MDEV2 MDEV1 MDEV0 ADEV7 ADEV6 ADEV5 ADEV4 ADEV3 ADEV2 ADEV1 ADEV0 VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 RGS RGV1 RGV0 QDS BDF BVT2
PAC0 BVT1
TBG2 BVT0
TBG1 BD_E
TBG0 TXCS PAC1 DMT DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 CPM3 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0
DBD XCC XCP1 XCP0 CPS PRRC1 PRRC0 PRIC1 PRIC0 SDPW NSDO TLB1 TLB0 RLB1 RLB0 VCBS OLM VTBS CPH CPCS
RFT2 RFT1 RFT0
VCO modulation DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 Nov., 2010, v1.1 13 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 36h IFAT 37h 38h VRB Channel Select W W W Legend: - = unimplemented IGFI2 IGFI1 IGFI0 IGFQ2 IGFQ1 IGFQ0 IFBC LIMC CHI3 CHI2 CHI1 CHI0 CHD3 CHD2 CHD1 CHD0 VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 Nov., 2010, v1.1 14 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 9.2 Control Register Description 9.2.1 Mode Register (Address: 00h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset R W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN PLLER CRCF TRSR TRER FECF CER XER
RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear FECF: FEC flag. (FECF is read only, it is updated for each valid packet.)
[0]: FEC pass. [1]: FEC error. CRCF: CRC flag. (CRCF is read only, it is updated for each valid packet.)
[0]: CRC pass. [1]: CRC error. CER: RF chip enable status.
[0]: RF chip is disabled. [1]: RF chip is enabled. XER: Internal crystal oscillator enable status.
[0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. PLLE: PLL enable status.
[0]: PLL is disabled. [1]: PLL is enabled. TRER: TRX state enable status.
[0]: TRX is disabled. [1]: TRX is enabled. TRSR: TRX Status Register.
[0]: RX state. [1]: TX state. Serviceable if TRER=1 (TRX is enable). 9.2.2 Mode Control Register (Address: 01h) Bit Name Reset R/W Bit 7 R W DDPC DDPC 0 Bit 6 ARSSI ARSSI 0 Bit 5 AIF AIF 0 Bit 4 CD DFCD 0 Bit 3 WWSE WWSE 0 Bit 2 FMT FMT 0 Bit 1 FMS FMS 0 Bit 0 ADCM ADCM 0 DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin when this register is enabled.
[0]: Disable. [1]: Enable. ARSSI: Auto RSSI measurement while entering RX mode.
[0]: Disable. [1]: Enable. AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode.
[0]: Disable. [1]: Enable. CD / DFCD:
DFCD (Data Filter by CD): The received packet will be filtered out if Carrier Detector signal is inactive.
[0]: Disable. [1]: Enable. CD (Read): Carrier detector signal.
[0]: Input power below threshold. [1]: Input power above threshold. WWSE: Reserved for internal usage only. Shall be set to [0]. FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select.
[0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement enable (Auto clear when done).
[0]: Disable measurement or measurement finished. [1]: Enable measurement. ADCM
[0]
[1]
Disable ADC Measure temperature A7125 @ Standby mode A7125 @ RX mode Disable ADC Measure RSSI, carrier detect Nov., 2010, v1.1 15 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Refer to chapter 17 for details. 9.2.3 Calibration Control Register (Address: 02h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 R/W
Bit 4 VCC 0 Bit 3 VBC 0 Bit 2 VDC 0 Bit 1 FBC 0 Bit 0 RSSC 0 VCC: VCO Current calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. VBC: VCO Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. FBC: IF Filter Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. RSSC: RSSI calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. 9.2.4 FIFO Register I (Address: 03h) FEP [7:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Refer to chapter 16 for details. 9.2.5 FIFO Register II (Address: 04h) FPM [1:0]: FIFO Pointer Margin PSA [5:0]: Used for Segment FIFO. Refer to chapter 16 for details. 9.2.6 FIFO DATA Register (Address: 05h) Bit Name Reset R/W W Bit 7 FEP7 0 Bit 6 FEP6 0 Bit 5 FEP5 1 Bit 4 FEP4 1 Bit 3 FEP3 1 Bit 2 FEP2 1 Bit 1 FEP1 1 Bit 0 FEP0 1 Bit Name Reset R/W W Bit 7 FPM1 0 Bit 6 FPM0 1 Bit 5 PSA5 0 Bit 4 PSA4 0 Bit 3 PSA3 0 Bit 2 PSA2 0 Bit 1 PSA1 0 Bit 0 PSA0 0 Bit Name Reset R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 0 0 0 0 0 0 0 0 FIFO [7:0]: FIFO data. TX FIFO (Write only) and RX FIFO (Read only). TX FIFO and RX FIFO share the same address (05h). Refer to chapter 16 for details. 9.2.7 ID DATA Register (Address: 06h) Bit Name Reset R/W Bit 7 R/W ID7 0 Bit 6 ID6 0 Bit 5 ID5 0 Bit 4 ID4 0 Bit 3 ID3 0 Bit 2 ID2 0 Bit 1 ID1 0 Bit 0 ID0 0 Once this address is accessed, ID Data is input/output in sequence corresponding to Write or Read. ID [7:0]: ID data. Refer to section 10.6 for details. Nov., 2010, v1.1 16 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 9.2.8 RC OSC Register I (Address: 07h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W WWS_SL7 WWS_SL6 WWS_SL5 WWS_SL4 WWS_SL3 WWS_SL2 WWS_SL1 WWS_SL0 RCOC2 RCOC1 RCOC0 RCOC4 RCOC5 RCOC3 0 0 0 0 0 0 0 0 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W WWS_SL9 WWS_SL8 WWS_AC5 WWS_AC4 WWS_AC3 WWS_AC2 WWS_AC1 WWS_AC0 0 0 0 0 0 0 0 1 Name Reset Bit Name Reset RCOC [5:0]: Reserved for internal usage only. 9.2.9 RC OSC Register II (Address: 08h) WWS_AC [5:0]: Reserved for internal usage only. WWS_SL [9:0]: Reserved for internal usage only. 9.2.10 RC OSC Register III (Address: 09h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 W BBCKS1 BBCKS0 0 0
RCOSC_E 1 Bit 1 TSEL 0 Bit 0 TWWS_E 1 Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 W ECKOE CKOS3 CKOS2 CKOS1 CKOS0 1 0 1 1 1 Bit 2 CKOI 0 Bit 1 CKOE 1 Bit 0 SCKI 0 BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00].
[00]: FSYCK / 8. [01]: FSYCK / 16. [10]: FSYCK / 32. [11]: FSYCK / 64. FSYCK is A7125s System clock = 64MHz. RCOSC_E: Reserved for internal usage only. TSEL: Reserved for internal usage only. TWWS_E: Reserved for internal usage only. 9.2.11 CKO Pin Control Register (Address: 0Ah) ECKOE: External Clock Output Enable for CKOS [3:0]= [0100] ~ [0111].
[0]: Disable. [1]: Enable. CKOS [3:0]: CKO pin output select.
[0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0010]: FPF (FIFO pointer flag).
[0011]: EOVBC, EOFBC, EOADC, EOVCC, OKADC (Internal usage only).
[0100]: External clock output= FSYCK / 8.
[0101]: External clock output / 2= FSYCK / 16.
[0110]: External clock output / 4= FSYCK / 32.
[0111]: External clock output / 8= FSYCK / 64.
[1xxx]: Reserved. CKOI: CKO pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. CKOE: CKO pin Output Enable.
[0]: High Z. [1]: Enable. SCKI: SPI clock input invert.
[0]: Non-inverted input. [1]: Inverted input. 9.2.12 GIO1 Pin Control Register (Address: 0Bh) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nov., 2010, v1.1 17 AMIC Communication Corporation 2.4GHz FSK Transceiver Name Reset W
GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE 0 0 0 0 0 1 A7125 9.2.13 GIO2 Pin Control Register (Address: 0Ch) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W
GIO2S3 GIO2S2 GIO2S1 GIO2S0 GIO2I GIO2OE 0 1 0 0 0 1 GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0]
TX state WTR (Wait until TX or RX finished) RX state
(Reserved.) TMEO(TX modulation enable) FSYNC(frame sync) CD(carrier detect) Preamble Detect Output (PMDO)
(Reserved.) In phase demodulator input(DMII) SDO ( 4 wires SPI data out) TRXD In/Out ( Direct mode ) RXD ( Direct mode ) TXD ( Direct mode ) In phase demodulator external input(EXDI0) External FSYNC input in RX direct mode EOP (End Of Packet) Inhibited
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]~[1111]
GIO1I: GIO1 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. GIO1OE: GIO1pin output enable.
[0]: High Z. [1]: Enable. GIO2S [3:0]: GIO2 pin function select. GIO2S
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
TX state RX state WTR (Wait until TX or RX finished) PASW (Output Signal to switch off external PA ) *
FSYNC(frame sync) TMEO(TX modulation enable) CD(carrier detect) Preamble Detect Output (PMDO)
(Reserved.) Quadrature phase demodulator input(DMIQ) SDO ( 4 wires SPI data out ) TRXD In/Out ( Direct mode ) RXD ( Direct mode ) TXD ( Direct mode ) Quadrature phase demodulator external input(EXDI1) External FSYNC input in RX direct mode EOPD (End Of Packet Delay) *
[1101]~[1111]
* Refer to Section 14.3 for details. Inhibited GIO2I: GIO2 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. GIO2OE: GIO2 pin Output Enable.
[0]: High Z. [1]: Enable. In TX Mode. Timing diagram among WTR, EOP and EOPD are illustrated below when EOPDS = 1. However, if EOPDS = 0, T2~T4 is around 1 us only. Nov., 2010, v1.1 18 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 SPI
(SCS,SCK,SDIO) TX-Strobe PLL Mode PDL+TDL No Command Required
(dummy bits) Next Instruction Auto Back PLL Mode Preamble + ID Code + Payload
+ CRC T0 T1
< 1us Preamble 4 bytes (default) ID 4 bytes (recommend) CRC Enable 4 bytes (default) 4 bytes (recommend) Disable W 20 us T2 T3 T4 Payload (Byte) 64 32 16 64 32 16 W (us) 3.5 11.5 15.5 11.5 19.5 3.5 In RX Mode. WTR goes low when last bit is recieved. Compared to TX mode, there are no dummy bits in RX mode. Hence, user can monitor the falling edge of WTR (if EOPDS=1) to turn on RX mode ahead of tunning on counterpart to TX mode for stable transmission timeslot. SPI
(SCS,SCK,SDIO) TX-Strobe PLL Mode PDL+TDL No Command Required Next Instruction Preamble + ID Code + Payload
+ CRC Auto Back PLL Mode RF Port GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - EOP
(GIO1S[3:0]=1100) GIO2 Pin - EOPD
(GIO2S = 1100) RF Port GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - EOP
(GIO1S[3:0]=1100) GIO2 Pin - EOPD
(GIO2S = 1100) T0 T1
< 1us T2 9.2.14 Data Rate Clock Register (Address: 0Dh) Bit R/W Bit 7 Name Reset R W SDR1 SDR1 0 Bit 6 SDR0 SDR0 0 Bit 5 GRC3 GRC3 0 Bit 4 GRC2 GRC2 1 Bit 3 GRC1 GRC1 1 Bit 2 GRC0 GRC0 1 Bit 1 Bit 0 CGS
1
XS 1 SDR [1:0]: Data rate setting. Nov., 2010, v1.1 19 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 SDR [1:0]
(Internal system clock)
[00]
[01]
[10]
[11]
FSYCK 64 MHz 64 MHz 64 MHz 64 MHz Data Rate 2 Mbps 1 Mbps Reserved Reserved Refer to chapter 13 for details. GRC [3:0]: Generator Reference Counter Due to A7125 supports different external crystals, GRC is used to get 2 MHz Clock Generator Reference (FCGR) for internal usage. External Crystal (FXREF) 16 MHz 12 MHz 8 MHz 6 MHz Clock Generation Reference (CGR) GRC [3:0]
Must be 2 MHz Must be 2 MHz Must be 2 MHz Must be 2 MHz
[0111]
[0101]
[0011]
[0010]
Refer to chapter 13 for details. CGS: Clock generator enable. Shall be set to [1].
[0]: Disable. [1]: Enable. XS: Crystal oscillator select. Recommend XS = [1]
[0]: Use external clock. [1]: Use external crystal. Nov., 2010, v1.1 20 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 9.2.15 PLL Register I (Address: 0Eh) Bit Name Reset R/W Bit 7 R/W CHN7 0 Bit 6 CHN6 0 Bit 5 CHN5 0 Bit 4 CHN4 0 Bit 3 CHN3 0 Bit 2 CHN2 0 Bit 1 CHN1 0 Bit 0 CHN0 0 CHN [7:0]: RF LO channel number. Change CHN to do frequency hopping. Refer to chapter 14 for details. 9.2.16 PLL Register II (Address: 0Fh) Bit R/W Bit 7 Name Reset R W DBL DBL 0 Bit 6 RRC1 RRC1 0 Bit 5 RRC0 RRC0 1 Bit 4 CHR3 CHR3 0 Bit 3 CHR2 CHR2 1 Bit 2 CHR1 CHR1 1 Bit 1 CHR0 CHR0 1 Bit 0 IP8 BIP8 0 DBL: Crystal frequency doubler enable.
[0]: Disable. FXREF = FXTAL.
[1]: Enable. FXREF =2 * FXTAL. RRC [1:0]: RF PLL reference counter setting. CHR [3:0]: PLL channel step setting. Refer to chapter 14 for details. 9.2.17 PLL Register III (Address: 10h) BIP [8:0]: LO base frequency integer part setting. BIP [8:0] are from address (0Fh) and (10h), IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0Fh) and (10h), Refer to chapter 14 for details. 9.2.18 PLL Register IV (Address: 11h) Bit R/W Bit 7 Name Reset R W IP7 BIP7 1 Bit 6 IP6 BIP6 0 Bit 5 IP5 BIP5 0 Bit 4 IP4 BIP4 1 Bit 3 IP3 BIP3 0 Bit 2 IP2 BIP2 1 Bit 1 IP1 BIP1 1 Bit 0 IP0 BIP0 0 Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
--/FP15 BFP15 0 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 0 0 0 0 0 0 BFP8 0 9.2.19 PLL Register V (Address: 12h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 BFP7 0 BFP6 0 BFP5 0 BFP4 0 BFP3 0 BFP2 1 BFP1 0 BFP0 0 Name Reset Name Reset R W R W BFP [15:0]: LO base frequency fractional part setting. BFP [15:0] are from address (11h) and (12h), AC [14:0] (Read): Frequency compensation value if AFC (19h) =1. FP [15:0] (Read): LO frequency fractional part setting. Refer to chapter 14 for details. 9.2.20 Channel Group Register I (Address: 13h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nov., 2010, v1.1 21 AMIC Communication Corporation 2.4GHz FSK Transceiver Name Reset R/W CHGL7 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 0 0 1 1 1 1 0 0 A7125 Bit Name Reset R/W Bit 7 R/W CHGH7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 0 1 1 1 1 0 0 0 CHGL [7:0]: PLL channel group low boundary setting. Refer to chapter 15 for details. 9.2.21 Channel Group Register II (Address: 14h) CHGH [7:0]: PLL channel group high boundary setting. Refer to chapter 15 for details. PLL frequency is divided into 3 groups:
Group1 Group2 Group3 Channel 0 ~ CHGL-1 CHGL ~ CHGH-1 CHGH ~ 255 9.2.22 TX Register I (Address: 15h) Bit Name Reset R/W Bit 7 W SDMS 1 Bit 6 TMDE 1 Bit 5 TXDI 0 Bit 4 TME 1 Bit 3
Bit 2 FDP2 1 Bit 1 FDP1 1 Bit 0 FDP0 0 SDMS: Reserved for internal usage only. Shall be set to [1]. TMDE: TX data VCO modulation enable.
[0]: Disable. [1]: Enable. TXDI: TX data invert. Recommend TXDI = [0].
[0]: Non-invert. [1]: Invert. TME: TX modulation enable.
[0]: Disable. [1]: Enable. FDP [2:0]: Frequency deviation power setting. Refer to control register (16h). 9.2.23 TX Register II (Address: 16h) Bit Name Reset R/W Bit 7 W FD7 1 Bit 6 FD6 1 Bit 5 FD5 0 Bit 4 FD4 0 Bit 3 FD3 0 Bit 2 FD2 0 Bit 1 FD1 0 Bit 0 FD0 0 FD [7:0]: Frequency deviation setting. Frequency deviation:
FDEV= FPFD * 127 * (FD [7:0] + 1) * 2 Recommend FDEV = 500 KHz.
(FDP [2:0] + 1) 26
/ 2 Nov., 2010, v1.1 22 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 9.2.24 Delay Register I (Address: 17h) Bit Name Reset R/W Bit 7 W EOPDS 0 Bit 6 DPR1 0 Bit 5 DPR0 0 Bit 4 TDL1 1 Bit 3 TDL0 0 Bit 2 PDL2 0 Bit 1 PDL1 1 Bit 0 PDL0 0 EOPDS: End Of Packet Delay Select.
[0]: 1us. Recommend EOPDS = [0] in external PA free requirement. Recommend EOPDS = [1] in external PA application. See below timing diagram.
[1]: 20 us. G IO 1 P in
(W T R ) G IO 2 P in
(E O P D ) T X S tro b e C m d E O P D S = 1
(2 0 u s ) T im e Z o n e to ind ic a te M C U to sw itch o ff e xt P A DPR [1:0]: Delay scale. Recommend DPR = [00]. TDL [1:0]: Delay for TRX settling from WPLL to TX/RX. Delay= 20 * (TDL [1:0] + 1) * (DPR [1:0] + 1) us. DPR [1:0]
00 00 00 00 WPLL to TX 20 us 40 us 60 us 80 us TDL [1:0]
00 01 10 11 PDL [2:0]: Delay for TX settling from PLL to WPLL. Delay= 10+20 * (PDL [2:0] + 1) * (DPR [1:0] + 1) us. DPR [1:0]
PDL [2:0]
Note Recommend 00 00 00 00 000 001 010 011 PLL to WPLL
(LO freq. fixed) 10 us 10 us 10 us 10 us PLL to WPLL
(LO freq changed) 30 us 50 us 70 us 90 us Note Recommend P L L M o d e T X M o d e G IO 1 P in
(W T R ) R F O P in T X S tro be P D L T D L P a ck e t 9.2.25 Delay Register II (Address: 18h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 0 1 0 0 0 0 0 1 WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [011].
[000]: 200us. [001]: 400us. [010]: 800us, [011]: 600us.
[100]: 1ms.
[101]: 1.5ms.
[111]: 2.5ms.
[110]: 2ms. Nov., 2010, v1.1 23 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Id le m o d e 3 0 0 u s W S E L T X o r R X m od e C ry s ta l O sc illa to r G IO 1 P in
(W T R ) R F O P in P D L T D L P a ck e t ( P r e a m b le + ID + P a ylo a d ) RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00].
[00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [001].
[000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us.
[100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us. 9.2.26 RX Register (Address: 19h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 W
RXSM1 RXSM0 1 0 FC 0 Bit 3 RXDI 0 Bit 2 DMG 0 Bit 1 RAW 1 Bit 0 ULS 0 RXSM0: Reserved for internal usage only. Shall be set to [1]. RXSM1: Reserved for internal usage only. Shall be set to [1]. AFC: Auto Frequency compensation.
[0]: Disable. [1]: Enable. Refer to section 14.4 for details. RXDI: RX data output invert. Recommend RXDI = [0].
[0]: Non-inverted output. [1]: Inverted output. DMG: Reserved for internal usage only. Shall be set to [0]. RAW: Reserved for internal usage only. Shall be set to [1]. ULS: RX Up/Low side band select.
[0]: Up side band, [1]: Low side band. Refer to section 14.2 for details. 9.2.27 RX Gain Register I (Address: 1Ah) MVGS: Manual VGA setting.
[0]: Auto. [1]: Manual. MRHL: Manual RH, RL setting.
[0]: Auto. [1]: Manual. IGS: Reserved for internal usage only. Shall be set to [1]. MGS [1:0]: Mixer gain attenuation select. Recommend MGS = [00].
[00]: 0dB. [01]: -6dB. [10]: -12dB. [11]: -18dB. LGS [2:0]: LNA gain attenuation select. Recommend LGS = [000].
[000]: 0dB. [001]: -6dB. [010]: -12dB. [011]: -18dB. [1XX]: -24dB. 9.2.28 RX Gain Register II (Address: 1Bh) Bit Name Reset R/W Bit 7 R/W MVGS 0 Bit 6 MRHL 0 Bit 5 IGS 0 Bit 4 MGS1 0 Bit 3 MGS0 0 Bit 2 LGS2 0 Bit 1 LGS1 0 Bit 0 LGS0 0 Bit Name Reset R/W Bit 7 R/W RH7 1 Bit 6 RH 6 0 Bit 5 RH5 0 Bit 4 RH4 0 Bit 3 RH3 0 Bit 2 RH2 0 Bit 1 RH1 0 Bit 0 RH0 0 Nov., 2010, v1.1 24 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 RH [7:0]: AGC calibration high threshold. 9.2.29 RX Gain Register III (Address: 1Ch) RL [7:0]: AGC calibration low threshold. 9.2.30 RX Gain Register IV (Address: 1Dh) Bit Name Reset R/W Bit 7 R/W RL7 1 Bit 6 RL6 0 Bit 5 RL5 0 Bit 4 RL4 0 Bit 3 RL3 0 Bit 2 RL2 0 Bit 1 RL1 0 Bit 0 RL0 0 Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 W AVSEL1 AVSEL0 MVSEL1 MVSEL0 0 1 0 0 Bit 3 MHC 1 Bit 2 LHC1 1 Bit 1 LHC0 1 Bit 0 AGCE 0 AVSEL [1:0]: ADC average times (AGC mode). Recommend AVSEL = [11].
[00]: No average. [01]: Average 2 times. [10]: Average 4 times. [11]: Average 8 times. MVSEL [1:0]: ADC average times (VCO calibration and RSSI measurement mode). Recommend MVSEL = [01].
[00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times. MHC: Reserved for internal usage only. Shall be set to [0]. LHC: Reserved for internal usage only. Shall be set to [01]. AGCE: AGC active enable.
[0]: End AGC. [1]: AGC active. 9.2.31 RSSI Threshold Register (Address: 1Eh) RTH [7:0]: Carrier detect threshold. Refer to chapter 17 for details. ADC [7:0]: ADC output value of temperature, RSSI . ADC input voltage= 0.3 + 1.2 * ADC [7:0] / 256 V. Refer to chapter 17 for details. 9.2.32 ADC Control Register (Address: 1Fh) Bit R/W Bit 7 Name Reset R W ADC7 RTH7 1 Bit 6 ADC6 RTH6 0 Bit 5 ADC5 RTH5 0 Bit 4 ADC4 RTH4 1 Bit 3 ADC3 RTH3 0 Bit 2 ADC2 RTH2 0 Bit 1 ADC1 RTH1 0 Bit 0 ADC0 RTH0 1 Bit Name Reset R/W Bit 7 W RSM1 0 Bit 6 RSM0 1 Bit 5 Bit 4 Bit 3 RADC1 RADC0 FSARS 0 0 1 Bit 2 XADS 0 Bit 1 RSS 1 Bit 0 CDM 1 RSM [1:0]: RSSI margin = RTH RTL. Recommend RSM = [11].
[00]: 5. [01]: 10. [10]: 15. [11]: 20. Refer to chapter 17 for details. RADC: ADC read out average mode.
[00]: No average.
[01]: 1, 2, 4, 8 average mode. The average number is according to the setting of AVSEL (in RX Gain Register IV).
[10]: 8, 16, 32, 64 average mode. The average number is according to the setting of MVSEL (in RX Gain Register IV).
[11]: Reserved. FSARS: ADC clock select.
[0]: 4MHz. [1]: 8MHz. XADS: ADC input signal select.
[0]: Convert RSS signal. [1]: Reserved for internal usage. Nov., 2010, v1.1 25 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Bit Name Reset R/W Bit 7 Bit 6 W
Bit 5 WHTS 0 Bit 4 FECS 0 Bit 3 CRCS 0 Bit 2 IDL 1 Bit 1 PML1 1 Bit 0 PML0 1 RSS: Temperature / RSSI measurement select.
[0]: Temperature. [1]: RSSI or carrier-detect measurement. CDM: RSSI measurement mode. Recommend CDM = [0].
[0]: Single mode. [1]: Continuous mode. 9.2.33 Code Register I (Address: 20h) WHTS: Data whitening (Data Encryption) select.
[0]: Disable. [1]: Enable. FECS: FEC select.
[0]: Disable. [1]: Enable. CRCS: CRC select.
[0]: Disable. [1]: Enable. IDL: ID code length select. Recommend IDL= [1].
[0]: 2 bytes. [1]: 4 bytes. PML [1:0]: Preamble length select. Recommend PML= [11].
[00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes. Refer to chapter 16 for details. 9.2.34 Code Register II (Address: 21h) Bit Name Reset R/W Bit 7 W
Bit 6 DCL2 1 Bit 5 DCL1 1 Bit 4 DCL0 1 Bit 3 ETH1 0 Bit 2 ETH0 1 Bit 1 PMD1 1 Bit 0 PMD0 1 DCL [2:0]: Demodulator DC estimation average mode. Refer to DCM (2Eh) for details. DCL2: For payload average mode. Recommend DCL2 = [1].
[0]: 128 bits average. [1]: 256 bits average. DCL1: For average and hold mode. Recommend DCL1 = [0].
[0]: 32 bits average. [1]: 64 bits average. DCL0: Preamble detect delay. Count from preamble detected signal. Recommend DCL0 = [1].
[0]: 4 bits for DCL1=0, 8 bits for DCL1=1. [1]: 8 bits for DCL1=0, 16 bits for DCL1=1. ETH [1:0]: ID code error tolerance. Recommend ETH = [01].
[00]: 0 bit, [01]: 1 bit. [10]: 2 bit. [11]: 3 bit. PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10].
[00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits. Refer to chapter 16 for details. 9.2.35 Code Register III (Address: 22h) Bit Name Reset R/W Bit 7 W
Bit 6 WS6 0 Bit 5 WS5 1 Bit 4 WS4 0 Bit 3 WS3 1 Bit 2 WS2 0 Bit 1 WS1 1 Bit 0 WS0 0 WS [6:0]: Data Whitening seed setting (data encryption key). Refer to chapter 16 for details. 9.2.36 IF Calibration Register I (Address: 23h) Bit Name R/W Bit 7 R
Bit 6
Bit 5
Bit 4 FBCF Bit 3 FB3 Bit 2 FB2 Bit 1 FB1 Bit 0 FB0 Nov., 2010, v1.1 26 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Reset W
MFBS MFB3 MFB2 MFB1 MFB0 0 0 1 1 0 MFBS: IF filter calibration value select. Recommend MFBS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. Bit 4 FCD4
Bit 3 FCD3
Bit 2 FCD2
Bit 1 FCD1
Bit 0 FCD0
Bit R/W Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 VCCS
1 Bit 4 VCCF MVCS 0 VCB3 VCOC3 VCB2 VCOC2 VCB1 VCOC1 VCB0 VCOC0 1 1 0 0 MFB [3:0]: IF filter manual calibration value. FBCF: IF filter auto calibration flag.
[0]: Pass. [1]: Fail. FB [3:0]: IF filter calibration value. MFBS= 0: Auto calibration value (AFB), MFBS= 1: Manual calibration value (MFB). Refer to chapter 15 for details. 9.2.37 IF Calibration Register II (Address: 24h) R/W Bit 7 Bit 6 Bit 5 FCD [4:0]: IF filter auto calibration deviation. 9.2.38 VCO Current Calibration Register (Address: 25h) Bit Name Reset Name Reset R R W
VCCS: Reserved for internal usage only. Shall be set [0]. MVCS: VCO current calibration value select. Recommend MVCS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. VCOC [3:0]: VCO current manual calibration value. FVCC: VCO current auto calibration flag.
[0]: Pass. [1]: Fail. VCB [3:0]: VCO current calibration value. MVCS= 0: Auto calibration value (AVCB). MVCS= 1: Manual calibration value (VCOC). Refer to chapter 15 for details.
1 DDC [1:0]: VCO deviation calibration delay. Recommend DDC = [01]. Delay time = PLL delay time ( DDC + 1 ). MDAGS: DAG calibration value select. Recommend MDAGS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. MVBS: VCO bank calibration value select. Recommend MVBS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. MVB [2:0]: VCO band manual calibration value. VBCF: VCO band auto calibration flag.
[0]: Pass. [1]: Fail. 9.2.39 VCO Bank Calibration Register I (Address: 26h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Name Reset R W
1 DDC1 DDC0 MDAGS
0
Bit 3 VBCF MVBS 0 Bit 2 VB2 MVB2 1 Bit 1 VB1 MVB1 0 Bit 0 VB0 MVB0 0 Nov., 2010, v1.1 27 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 VB [2:0]: VCO bank calibration value. MVBS= 0: Auto calibration value (AVB). MVBS= 1: Manual calibration value (MVB). Refer to chapter 15 for details. 9.2.40 VCO Bank Calibration Register II (Address: 27h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset ADAG7 ADAG0 R W MDAG7 MDAG6 MDAG5 MDAG4 MDAG3 MDAG2 MDAG1 MDAG0 ADAG3 ADAG6 ADAG4 ADAG5 ADAG1 ADAG2 1 0 0 0 0 0 0 0 MDAG [7:0]: DAG manual calibration value. Recommend MDAG = [0x80]. ADAG [7:0]: DAG auto calibration value. 9.2.41 VCO Deviation Calibration Register I (Address: 28h) Bit R/W Bit 7 Name Reset DEVA7 R W DEVS3 0 Bit 6 DEVA6 DEVS2 1 Bit 5 DEVA5 DEVS1 1 Bit 4 Bit 3 Bit 2 Bit 1 DEVA1 DEVA4 DEVS0 DAMR_M VMTE_M VMS_M DEVA3 DEVA2 1 0 0 0 Bit 0 DEVA0 MSEL 0 DEVS [3:0]: Deviation output scaling. Recommend DEVS = [0011]. DAMR_M: DAMR manual enable. Recommend DAMR_M = [0].
[0]: Disable. [1]: Enable. VMTE_M: VMT manual enable. Recommend VMTE_M = [0].
[0]: Disable. [1]: Enable. VMS_M: VM manual enable. Recommend VMS_M = [0].
[0]: Disable. [1]: Enable. MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0].
[0]: Auto control. [1]: Manual control. DEVA [7:0]: Deviation output value. MVDS= 0: Auto calibration value ((ADEV / 8) (DEVS + 1)), MVDS= 1: Manual calibration value (MDEV). 9.2.42 VCO Deviation Calibration Register II (Address: 29h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset ADEV7 R W MVDS ADEV6 MDEV6 ADEV5 ADEV4 MDEV5 MDEV4 ADEV3 ADEV2 MDEV3 MDEV2 ADEV1 ADEV0 MDEV1 MDEV0 0 0 1 0 1 0 0 0 MVDS: VCO deviation calibration value select. Recommend MVDS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. MDEV [6:0]: VCO deviation manual calibration value. ADEV [7:0]: VCO deviation auto calibration value. Refer to chapter 15 for details. 9.2.43 VCO Deviation Calibration Register III (Address: 2Ah) Bit Name Reset R/W Bit 7 W VMG7 1 Bit 6 VMG6 0 Bit 5 VMG5 0 Bit 4 VMG4 0 Bit 3 VMG3 0 Bit 2 VMG2 0 Bit 1 VMG1 0 Bit 0 VMG0 0 VMG [7:0]: Reserved for internal usage only. Shall be set to [0x80]. Nov., 2010, v1.1 28 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 0 0 0 0 0 0 9.2.44 VCO Modulation Delay Register (Address: 2Bh) DEVFD [2:0]: Reserved for internal usage only. Shall be set to [000]. DEVD [2:0]: Reserved for internal usage only. Shall be set to [000]. 9.2.45 Battery Detect Register (Address: 2Ch) Bit Name Reset Name Reset W R W
0
1 Bit R/W Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 RGS RGV1 RGV0 BVT2 BVT1 BVT0 BD_E
0
1
1
0 Bit 4 BDF QDS 0
0 RGS: VDD_D voltage setting in Sleep mode.
[0]: 3/5 * REGI. [1]: 3/4 * REGI. RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep mode. Recommend RGV = [11].
[00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V. Bit Name Reset R/W Bit 7 Bit 6 W
Bit 5 TXCS 0 Bit 4 PAC1 1 Bit 3 PAC0 0 Bit 2 TBG2 1 Bit 1 TBG1 1 Bit 0 TBG0 1 QDS: Reserved for internal usage only. Shall be set [1]. BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. BD_E: Battery detect enable.
[0]: Disable. [1]: Enable. It will be clear after battery detection done. BDF: Battery detect flag.
[0]: Battery voltage less than threshold. [1]: Battery voltage greater than threshold. Refer to chapter 19 for details. 9.2.46 TX test Register (Address: 2Dh) TXCS: TX Current Setting. PAC [1:0]: PA Current Setting. TBG [2:0]: TX Buffer Setting. Typical Recommend setting Typical Output Power (dBm) TXCS TBG PAC TX current (mA) 3 0
-10 1 1 1 7 7 4 2 0 0 21 15.7 13.7
-20 13.3 Also, refer to App. Note for more setting of TX power level. 0 0 1 9.2.47 RX DEM test Register I (Address: 2Eh) Bit Name Reset R/W Bit 7 W DMT 0 Bit 6 DCM1 1 Bit 5 DCM0 1 Bit 4 MLP1 0 Bit 3 MLP0 0 Bit 2 SLF2 1 Bit 1 SLF1 0 Bit 0 SLF0 0 Nov., 2010, v1.1 29 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 DMT: Reserved for internal usage only. Shall be set to [0]. DCM [1:0]: Demodulator DC estimation mode.
[00]: Fix mode (For 10ppm crystal accuracy only). DC level is set by DCV [7:0].
[01]: Preamble hold mode. DC level is preamble average value at PMDO.
[10]: Average and hold mode. DC level is the average value at PMDO with DCL0 delay.
[11]: Payload average mode (For internal usage). DC level is payload data average. MLP [1:0]: Reserved for internal usage only. Shall be set to [00]. SLF [2:0]: Reserved for internal usage only. Shall be set to [111]. 9.2.48 RX DEM test Register II (Address: 2Fh) R/W Bit 7 W DCV7 Bit 6 DCV6 1 Bit 5 DCV5 0 Bit 4 DCV4 0 Bit 3 DCV3 0 Bit 2 DCV2 0 Bit 1 DCV1 0 Bit 0 DCV0 0 DCV [7:0]: Demodulator fix mode DC value. Recommend DCV = [0x80]. 9.2.49 Charge Pump Current Register I (Address: 30h) R/W Bit 7 W CPM3 Bit 6 CPM2 1 Bit 5 CPM1 1 Bit 4 CPM0 1 Bit 3 CPT3 1 Bit 2 CPT2 1 Bit 1 CPT1 1 Bit 0 CPT0 1 CPM [3:0]: Charge pump current setting for VM loop. Recommend CPM = [1111]. Charge pump current = (CPM + 1) / 16 mA. CPT [3:0]: Charge pump current setting for VT loop. Recommend CPT = [0001]. Charge pump current = (CPT + 1) / 16 mA. 9.2.50 Charge Pump Current Register II (Address: 31h) Bit Name Reset R/W Bit 7 W CPTX3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 1 1 1 1 0 0 1 1 CPTX [3:0]: Charge pump current setting for TX mode. Recommend CPTX = [0001]. Charge pump current = (CPTX + 1) / 16 mA. CPRX [3:0]: Charge pump current setting for RX mode. Recommend CPRX = [0001]. Charge pump current = (CPRX + 1) / 16 mA. 9.2.51 Crystal test Register (Address: 32h) R/W Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 DBD 0 Bit 2 XCC 1 Bit 1 XCP1 0 Bit 0 XCP0 0 W W DBD: Reserved for internal usage only. Shall be set to [0]. XCC: Reserved for internal usage only. Shall be set to [1]. XCP [1:0]: Reserved for internal usage only. Shall be set to [00]. 9.2.52 PLL test Register (Address: 33h) CPS: Reserved for internal usage only. Shall be set to [1]. PRRC [1:0]: Reserved for internal usage only. Shall be set to [00]. PRIC [1:0]: Reserved for internal usage only. Shall be set to [01]. R/W Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 CPS 1 PRRC1 PRRC0 PRIC1 PRIC0 SDPW NSDO 0 1 0 0 0 1 Bit Name Reset Bit Name Reset Bit Name Reset Bit Name Reset 0 1
Nov., 2010, v1.1 30 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Bit Name Reset R/W Bit 7 Bit 6 Bit 5 W
Bit 4 TLB1 1 Bit 3 TLB0 1 Bit 2 RLB1 0 Bit 1 RLB0 0 Bit 0 VCBS 0 SDPW: Reserved for internal usage only. Shall be set to [0]. NSDO: Reserved for internal usage only. Shall be set to [1]. 9.2.53 VCO test Register (Address: 34h) TLB [1:0]: Reserved for internal usage only. Shall be set to [11]. RLB [1:0]: Reserved for internal usage only. Shall be set to [00]. VCBS: Reserved for internal usage only. Shall be set to [0]. 9.2.54 RF Analog test Register (Address: 35h) OLM: Reserved for internal usage only. Shall be set to [0]. VTBS: Reserved for internal usage only. Shall be set to [0]. CPH: Reserved for internal usage only. Shall be set to [0]. CPCS: Reserved for internal usage only. Shall be set to [1]. RFT [2:0]: RF analog pin configuration. Recommend RFT= [000].
{XADS, RFT[2:0]}
Bit Name Reset R/W Bit 7 W OLM 0 Bit 6 VTBS 0 Bit 5 CPH 0 Bit 4 CPCS 0 Bit 3
Bit 2 RFT2 0 Bit 1 RFT1 0 Bit 0 RFT0 0 BPF positive quadrature phase output BPF negative quadrature phase output BPF negative in phase output
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
BP_BG Band-gap voltage Analog temperature voltage Band-gap voltage Analog temperature voltage BPF positive in phase output No connection No connection Band-gap voltage Analog temperature voltage Band-gap voltage Analog temperature voltage No connection No connection No connection No connection BP_RSSI RSSI voltage RSSI voltage No connection No connection No connection No connection External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source External ADC input source 9.2.55 IFAT Register (Address: 36h) Bit Name Reset R/W Bit 7 W IGFI2 1 Bit 6 IGFI1 0 Bit 5 IGFI0 0 Bit 4 Bit 3 Bit 2 IGFQ2 IGFQ1 IGFQ0 1 0 0 Bit 1 IFBC 1 Bit 0 LIMC 1 IGFI [2:0]: Reserved for internal usage only. Shall be set to [111]. IGFQ [2:0]: Reserved for internal usage only. Shall be set to [111]. IFBC: Reserved for internal usage only. Shall be set to [1]. LIMC: Reserved for internal usage only. Shall be set to [1]. Nov., 2010, v1.1 31 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 9.2.56 Channel Select Register (Address: 37h) Bit Name Reset R/W Bit 7 W CHI3 0 Bit 6 CHI2 1 Bit 5 CHI1 0 Bit 4 CHI0 0 Bit 3 CHD3 0 Bit 2 CHD2 1 Bit 1 CHD1 0 Bit 0 CHD0 0 CHI [3:0]: Auto IF offset channel number setting. FCHSP * (CHI + 1) = 2MHz Refer to chapter 14 for FCHSP setting. CHD [3:0]: The channel frequency offset for deviation calibration. If FCHSP = 500KHz, recommend CHD = [0111]. Offset channel number = +/- (CHD + 1). 9.2.57 VRB Register (Address: 38h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W VTRB3 VTRB2 VTRB1 VTRB0 VMRB3 VMRB2 VMRB1 VMRB0 0 0 0 0 0 0 0 0 VTRB [3:0]: Reserved for internal usage only. Shall be set to [1111]. VMRB [3:0]: Reserved for internal usage only. Shall be set to [1111]. Nov., 2010, v1.1 32 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 10. SPI A7125 only supports one SPI bus with maximum data rate 10Mbps. MCU should assert SCS pin low (SPI chip select) to active accessing of A7125. Via SPI bus, user can access control registers and issue Strobe command. Figure 10.1 gives an overview of SPI access manners. 3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire SPI, SDIO pin is configured as bi-direction to be data input and output. For 4-wire SPI, SDIO pin is data input and GIO1 (or GIO2) pin is data output. In such case, GIO1S (0bh) or GIO2S (0ch) should be set to [0110]. For SPI write operation, SDIO pin is latched into A7125 at the rising edge of SCK. For SPI read operation, if input address is latched by A7125, data output is aligned at falling edge of SCK. Therefore, MCU can latch data output at the rising edge of SCK. To control A7125s internal state machine, it is very easy to send Strobe command via SPI bus. The Strobe command is a unique command set with total 8 commands. See section 10.3, 10.4 and 10.5 for details. SPI chip select Data In Data Out 3-Wire SPI SCS pin = 0 SDIO pin SDIO pin 4-Wire SPI SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) /
GIO2 (GIO2S=0110) Read/Write register ADDRreg DataByte ADDRreg DataByte ADDRreg DataByte ADDRFIFO DataByte0 DataByte1 DataByte2 DataByte3 DataByten ADDRID DataByte0 DataByte1 DataByte2 DataByte3 SCS Read/Write RF FIFO Read/Write ID register Sleep Mode Idle Mode STBY Mode PLL Mode RX Mode TX Mode Strobe CommandSleep Mode Strobe CommandIdle Mode Strobe CommandSTBY Mode Strobe CommandPLL Mode Strobe CommandRX Mode Strobe CommandTX Mode FIFO Write Reset FIFO Read Reset Strobe CommandFIFO Write Reset Strobe CommandFIFO Read Reset Figure 10.1 SPI Access Manners Nov., 2010, v1.1 33 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 10.1 SPI Format The first bit (A7) is critical to indicate A7125 the following instruction is Strobe command or control register. See Table 10.1 for SPI format. Based on Table 10.1, if A7=0, A7125 is informed for control register accessing. So, A6 bit is used to indicate read (A6=1) or write operation (A6=0). See Figure 10.2 and Figure 10.3 for details. Address Byte (8 bits) CMD R/W A7 A6 A5 A4 Address A2 A3 A1 A0 7 6 5 4 2 1 0 Data Byte (8 bits) Data 3 Table 10.1 SPI Format Address byte:
Bit 7: Command bit
[0]: Control register command.
[1]: Strobe command. Bit 6: R/W bit
[0]: Write data to control register.
[1]: Read data from control register. Bit [5:0]: Address of control register Data Byte:
Bit [7:0]: SPI input or output data, see Figure 10.2 and Figure 10.3 for details. 10.2 SPI Timing Characteristic No matter 3-wire or 4-wire SPI bus is configured, the maximum SPI data rate is 10 Mbps. To active SPI bus, SCS pin must be set to low. For correct data latching, user has to take care hold time and setup time between SCK and SDIO. See Table 10.2 for details. Parameter FC TSE THE TSW THW TDR Description FIFO clock frequency. Enable setup time. Enable hold time. TX Data setup time. TX Data hold time. RX Data delay time. Min. 50 50 50 50 0 Max. 10 50 Unit MHz ns ns ns ns ns Table 10.2 SPI Timing Characteristic 10.3 SPI Timing Chart In this section, 3-wire and 4-wire SPI bus read / write timing are described. 10.3.1 Timing Chart of 3-wire SPI Nov., 2010, v1.1 34 AMIC Communication Corporation SCS SCK SDIO SCS SCK SDIO SCS SCK SDIO SCS SCK SDI GIOx 2.4GHz FSK Transceiver A7125 A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at the rising edge of SCK 3-Wire serial interface - Write operation A7 A6 A5 A4 A3 A2 A1 A0 DR7 DR6 DR5 DR1 DR0 RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at rising edge of SCK 3-Wire serial interface - Read operation Figure 10.2 Read/Write Timing Chart of 3-Wire SPI 10.3.2 Timing Chart of 4-wire SPI A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at rising edge of SCK 4-Wire serial interface - Write operation A7 A6 A5 A4 A3 A2 A1 A0 x x DR7 DR6 DR5 DR2 DR1 DR0 RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at the rising edge of SCK 4-Wire serial interface - Read operation Figure 10.3 Read/Write Timing Chart of 4-Wire SPI 10.4 Strobe Commands A7125 supports 8 Strobe commands to control internal state machine for chips operations. Table 10.3 is the summary of Strobe commands. Nov., 2010, v1.1 35 AMIC Communication Corporation 2.4GHz FSK Transceiver Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected, A3 ~ A0 are dont care conditions. In such case, SCS pin can be remaining low for asserting next commands. A7125 Strobe Command Strobe Command A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 A3 x x x x x x x x A2 x x x x x x x x A1 x x x x x x x x Description Idle mode A0 x Sleep mode x x Standby mode x PLL mode x RX mode x TX mode x FIFO write pointer reset x FIFO read pointer reset Table 10.3 Strobe Commands by SPI bus 10.4.1 Strobe Command - Sleep Mode Refer to Table 10.3, user can issue 4 bits (1000) Strobe command directly to set A7125 into Sleep mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 Description A0 0 Sleep mode Figure 10.4 Sleep mode Command Timing Chart 10.4.2 Strobe Command - ldle Mode Refer to Table 10.3, user can issue 4 bits (1001) Strobe command directly to set A7125 into Idle mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 0 A5 0 A4 1 A3 x A2 x A1 x A0 x Idle mode Description Nov., 2010, v1.1 36 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 SCS SCK SCS SCK SDIO A7 A6 A5 A4 SDIO A7 A6 A5 A4 A3 A2 A1 A0 Idle mode Idle mode Figure 10.5 Idle mode Command Timing Chart 10.4.3 Strobe Command - Standby Mode Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7125 into Standby mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 0 A5 1 A4 0 A3 x A2 x A1 x Description A0 x Standby mode Figure 10.6 Standby mode Command Timing Chart 10.4.4 Strobe Command - PLL Mode Refer to Table 10.3, user can issue 4 bits (1011) Strobe command directly to set A7125 into PLL mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 0 A5 1 A4 1 A3 x A2 x A1 x Description A0 x PLL mode Figure 10.7 PLL mode Command Timing Chart Nov., 2010, v1.1 37 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 10.4.5 Strobe Command - RX Mode Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7125 into RX mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 0 A4 0 A3 x A2 x A1 x A0 x RX mode Description Figure 10.8 RX mode Command Timing Chart 10.4.6 Strobe Command - TX Mode Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7125 into TX mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 0 A4 1 A3 x A2 x A1 x A0 x TX mode Description Figure 10.9 TX mode Command Timing Chart 10.4.7 Strobe Command FIFO Write Pointer Reset Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7125 FIFO write pointer. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 1 A4 0 A3 x A2 x A1 x A0 x FIFO write pointer reset Description Nov., 2010, v1.1 38 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 10.10 FIFO write pointer reset Command Timing Chart 10.4.8 Strobe Command FIFO Read Pointer Reset Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7125 FIFO read pointer. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 1 A4 1 A3 x A2 x A1 x A0 x FIFO read pointer reset Description Figure 10.11 FIFO read pointer reset Command Timing Chart 10.5 Reset Command In addition to power on reset (POR), MCU could issue software reset to A7125 by setting Mode Register (00h) through SPI bus as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7125 is informed to generate internal signal RESETN to initial itself. After reset command, A7125 is in standby mode. SCS SCK SDIO RESETN A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 Figure 10.12 Reset Command Timing Chart Reset RF chip 10.6 ID Accessing Command A7125 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI bus. ID length is recommended to be 32 bits by setting IDL (20h). Figure 10.13 and 10.14 are timing charts of 32-bits ID accessing via 3-wire SPI. Nov., 2010, v1.1 39 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 10.6.1 ID Write Command User can refer to Figure 10.2 for SPI write timing chart. Below is the procedure of ID write command. Step1: Deliver A7~A0 = 00000110 (A7=0 for control register, A6=0 for write operation, ID addr = 06h). Step2: Via SDIO pin, 32-bits ID are written in sequence by Data Byte 0, 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Figure 10.13 ID Write Command Timing Chart 10.6.2 ID Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command. Step1: Deliver A7~A0 = 01000110 (A7=0 for control register, A6=1 for read operation, ID addr = 06h). Step2: Via SDIO pin, 32-bits ID are read in sequence by Data Byte 0, 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Figure 10.14 ID Read Command Timing Chart 10.7 FIFO Accessing Command A7125 has separated TX / RX FIFO, user just needs to set FMS (01h) =1 to enable FIFO mode. In FIFO mode, before packet is delivered, write wanted data into TX FIFO and issue TX strobe command. Similarly, user can read RX FIFO once packet is received. User can choose polling or interrupt scheme for FIFO accessing. FIFO status is output via GIO1 (or GIO2) pin by setting GIO1 (0Bh) or GIO2 (0Ch). See Figure 10.15 and 10.16 for timing charts of FIFO accessing via 3-wire SPI. 10.7.1 TX FIFO Write Command User can refer to Figure 10.2 for SPI write timing chart. Below is the procedure of TX FIFO write command. Step1: Deliver A7~A0 = 00000101 (A7=0 for control register, A6=0 for write operation, FIFO addr = 05h). Step2: Via SDIO pin, write (n+1) bytes TX data into TX FIFO in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when step2 is completed. Step4: Send TX Strobe command for packet transmitting. Refer to Figure 10.9. Nov., 2010, v1.1 40 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 10.15 TX FIFO Write Command Timing Chart 10.7.2 Rx FIFO Read Command User can refer to Figure 10.2 for SPI read timing chart. Below is the procedure of RX FIFO read command. Step1: Deliver A7~A0 = 01000101 (A7=0 for control register, A6=1 for read operation, FIFO addr = 05h). Step2: Via SDIO pin, RX FIFO is read in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when RX FIFO is read completely. Figure 10.16 RX FIFO Read Command Timing Chart Nov., 2010, v1.1 41 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 11. State machine In chapter 9 and chapter 10, user can learn both accessing A7125s control registers as well as issuing Strobe commands. From section 10.2 ~ 10.6, it is clear to know configurations of 3-wire SPI and 4-wire SPI, Strobe command, software reset, and how to access ID Registers and TX/RX FIFO. In section 11.1, built-in state machine is introduced. Then, combined with Strobe command, software reset and A7125s control registers, section 11.2 , 11.3 and 11.4 demonstrate 3 state diagrams to explain how transitions of A7125s operation. From accessing data point of view, if FMS=1 (01h), FIFO mode is enabled, otherwise, A7125 is in direct mode. If FMS=1 and FIFO Read/Write at standby mode, we call it is Normal FIFO mode. Otherwise, If FMS=1 and FIFO Read/Write at PLL mode, we called it is Quick FIFO mode due to the reduction of PLL settling time. If FMS=1 and FIFO Read/Write at IDLE mode, we called it is Power Saving FIFO mode due to the reduction of average current. SPI chip select Data In Data Out Operation Mode 3-Wire SPI SCS pin = 0 SDIO pin SDIO pin 4-Wire SPI SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) /
GIO2 (GIO2S=0110) FIFO (FMS=1) Direct(FMS=0) FIFO (FMS=1) Direct(FMS=0) Clock Recovery for Direct Mode CKO pin
(CKOS = 0001) CKO pin
(CKOS = 0001)
(1) Normal FIFO Mode
(2) Quick FIFO Mode
(3) Power Saving FIFO Mode
(4) Quick Direct Mode
(FMS=1 and FIFO R/W @ Standby mode)
(FMS=1 and FIFO R/W @ PLL mode)
(FMS=1 and FIFO R/W @ IDLE mode)
(FMS=0 and FIFO ignored, write packet @ TX mode, read packet @ RX mode) 11.1 Key states A7125 supports 7 key operation states. Those are,
(1) Standby mode
(2) Sleep mode
(3) Idle mode
(4) PLL mode
(5) TX mode
(6) RX mode
(7) CAL mode After power on reset or software reset, A7125 is automatically into standby mode. Then, user has to do calibration process because all control registers are in initial values. The calibration process of A7125 is very easy, user only needs to issue Strobe commands and enable calibration registers. If so, the calibrations are automatically completed by A7125s internal state machine. See 11.2, 11.3, 11.4 and chapter 15 for details. After calibration, A7125 is ready to do TX and RX operation. User can start wireless transmission. 11.1.1 Standby mode When Standby Strobe is issued, A7125 enters standby mode automatically. Internal power management is listed below. Be noted that A7125 is in standby mode after power on reset or software reset. Standby mode On Chip Regulator Crystal Oscillator ON ON VCO OFF PLL OFF RX Circuitry TX Circuitry OFF OFF Strobe Command
(1010xxxx)b See Figure 10.6 Nov., 2010, v1.1 42 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 11.1.2 Sleep mode When Sleep Strobe is issued, A7125 enters sleep mode automatically. In sleep mode, A7125 still can accept other strobe commands via SPI bus. But, A7125 can not support Read/Write FIFO in sleep mode. Internal power management is listed below. Sleep mode On Chip Regulator Crystal Oscillator OFF OFF VCO OFF PLL OFF RX Circuitry TX Circuitry OFF OFF Strobe Command
(1000xxxx)b See Figure 10.4 When Idle Strobe is issued, A7125 enters idle mode automatically. In idle mode, A7125 can accept other strobe commands as well as supporting Read/Write FIFO. Internal power management is listed below. ldle mode On Chip Regulator Crystal Oscillator ON OFF VCO OFF PLL OFF RX Circuitry TX Circuitry OFF OFF Strobe Command
(1001xxxx)b See Figure 10.5 When PLL Strobe is issued, A7125 enters PLL mode automatically. In PLL mode, internal PLL and VCO are both turned on to generate LO (local oscillator) frequency before TX and RX operation. Internal power management is listed below. According to PLL Register I, II, III, IV and V, PLL circuitry is easy to control by users definition. PLL mode On Chip Regulator Crystal Oscillator ON ON VCO ON PLL ON RX Circuitry TX Circuitry OFF OFF Strobe Command
(1011xxxx)b See Figure 10.7 When TX Strobe is issued, A7125 enters TX mode automatically for data delivery. Internal power management is listed below. Be notice,
(1) If A7125 is in FIFO mode, TX data packet (Preamble + ID + Payload) is delivered through TX circuitry. Then, A7125 supports auto-back function to previous state for the next packet.
(2) If A7125 is in direct mode, TX data packet is also delivered through TX circuitry. Then, A7125 stays in TX mode. User has to issue Strobe command to back to previous state. TX mode On Chip Regulator Crystal Oscillator ON ON VCO ON PLL ON RX Circuitry OFF Circuitry TX ON Strobe Command
(1101xxxx)b See Figure 10.9 When RX Strobe is issued, A7125 enters RX mode automatically for data receiving. Internal power management is listed below. 43 AMIC Communication Corporation 11.1.3 ldle mode 11.1.4 PLL mode 11.1.5 TX mode 11.1.6 RX mode Be notice, Nov., 2010, v1.1 A7125 2.4GHz FSK Transceiver
(1) If A7125 is in FIFO mode, RX data packet is caught through RX circuitry. Then, A7125 supports auto-back function to previous state for next receiving packet.
(2) If A7125 is in direct mode, RX data packet is also caught through RX circuitry. Then, A7125 stays in RX mode. User has to issue Strobe command to back to previous state. RX mode On Chip Regulator Crystal Oscillator ON ON VCO ON PLL ON RX Circuitry TX Circuitry ON OFF Strobe Command
(1101xxxx)b See Figure 10.9 11.1.7 CAL mode Calibration process shall be done after power on reset or software reset. Calibration items include VCO, IF Filter and RSSI. It is easy to implement calibration process by Strobe command and enable CALC (02h) control register. See chapter 15 for details. Be noted that VCO Calibration is executed in PLL mode only. However, IF Filter and RSSI Calibration can be executed in Standby or PLL mode. Nov., 2010, v1.1 44 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 11.2 Normal FIFO Mode This mode is suitable for requirement of general purpose applications. After calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transceiving, only one Strobe command is needed. Once transmission is done, A7125 is auto back to standby mode. If all packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in sleep mode. Figure 11.1 is the state diagram of Normal FIFO mode. CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI CALC.1=1, IF Filter CALC.2=1, VCO Deviation CALC.3=1, VCO Bank CALC.4=1, VCO Current 15.3 15.2 15.6 15.5 15.4 Strobe CMD Value Note Section ST1 ST2 ST3 ST4 ST5-TX ST5-RX 1011b 1010b 1000b 1001b 1101b 1100b Enter to PLL Enter to Standby Enter to SLEEP Enter to IDLE Enter to TX Enter to RX 10.4.4 10.4.3 10.4.1 10.4.2 10.4.6 10.4.5 RST-CMD 00000000b Software Reset 10.5 l Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty. Figure 11.1 State diagram of Normal FIFO Mode From Figure 11.1, when ST5 command is issued for TX operation, see Figure 11.2 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Nov., 2010, v1.1 45 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Strobe CMD
(SCS,SCK,SDIO) ST5 Next Instruction 90 us (auto delay) Preamble + ID Code + Payload RFO Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) T0 T1 T0-T1: Auto Delay by Register setting (PDL + TDL) Transmitting Time Auto Back Standby Mode T2 LO Freq. Standby to WPLL WPLL to TX TX Ready Time Changed No Changed
(PDL) 30 us 30 us
(TDL) 60 us 60 us 90 us 90 us Figure 11.2 Transmitting Timing Chart of Normal FIFO Mode From Figure 11.1, when ST5 command is issued for RX operation, see Figure 11.3 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Strobe CMD
(SCS,SCK,SDIO) ST5 90 us Wait Packet RFI Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) Preamble + ID Code + Payload Receiving Time Next Instruction Auto Back T3 Standby Mode T0 T1 T2 T0-T1: RX Settling. T1-T2: RX is ready, Wait for valid packet LO Freq. Standby to WPLL WPLL to RX RX Ready Time Changed No Changed 30 us 30 us 60 us 60 us 90 us 90 us Figure 11.3 Receiving Timing Chart of Normal FIFO Mode Nov., 2010, v1.1 46 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 11.3 Quick FIFO Mode This mode is suitable for requirement of fast transceiving. After calibration flow, user can issue Strobe command to enter PLL mode where write TX FIFO or read RX FIFO. From PLL mode to packet data transceiving, only one Strobe command is needed. Once transmission is done, A7125 is auto back to PLL mode. When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in sleep mode. Figure 11.4 is the state diagram of Quick FIFO mode. 15.3 15.2 15.6 15.5 15.4 Section 10.4.4 CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI CALC.1=1, IF Filter CALC.2=1, VCO Deviation CALC.3=1, VCO Bank CALC.4=1, VCO Current Strobe CMD Value Note ST 1 ST 2 ST 3 ST 4 ST 5-TX ST 5-R X 1011b 1010b 1000b 1001b 1101b 1100b Enter to PLL Enter to Standby 10.4.3 Enter to SLEEP Enter to ID LE Enter to TX Enter to R X 10.4.1 10.4.2 10.4.6 10.4.5 RST-CMD 00000000b Software Reset 10.5 l Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty. l Be notice, ST5 delay time is either 70 us (LO frequency changed) or 10 us (LO frequency NOT changed) Figure 11.4 State diagram of Quick FIFO Mode From Figure 11.4, when ST5 command is issued for TX operation, see Figure 11.5 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Nov., 2010, v1.1 47 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Strobe CMD
(SCS,SCK,SDIO) ST5 Next Instruction 90 us / 70 us (auto delay) Preamble + ID Code + Payload RF In/Out Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) T0 T1 T0-T1: Auto Delay by Register setting(PDL+TDL) Transmitting Time Auto Back PLL Mode T2 LO Freq. PLL to WPLL WPLL to TX TX Ready Time Changed No Changed
(PDL) 30 us 10 us
(TDL) 60 us 60 us 90 us 70 us Figure 11.5 Transmitting Timing Chart of Quick FIFO Mode From Figure 11.4, when ST5 command is issued for RX operation, see Figure 11.6 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Strobe CMD
(SCS,SCK,SDIO) ST5 90 us / 70 us Wait Packet RF In/Out Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) Preamble + ID Code + Payload Receiving Time Next Instruction Auto Back PLL Mode T3 T0 T1 T2 T0-T1: RX Settling by register setting (PDL+TDL). T1-T2: RX is ready, Wait for valid packet LO Freq. Standby to WPLL WPLL to RX RX Ready Time Changed No Changed
(PDL) 30 us 10 us
(TDL) 60 us 60 us 90 us 70 us Figure 11.6 Receiving Timing Chart of Quick FIFO Mode 11.4 Power Saving FIFO Mode This mode is suitable for requirement of low power consumption. After calibration flow, user can issue Strobe command to enter idle mode where write TX FIFO or read RX FIFO. From idle mode to packet data transceiving, only one Strobe command is needed. Once transmission is done, A7125 is auto back to idle mode. When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in sleep mode. Figure 11.7 is the state diagram of Power Saving FIFO mode. Nov., 2010, v1.1 48 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 15.3 15.2 15.6 15.5 15.4 Section 10.4.4 CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI CALC.1=1, CALC.2=1, IF Filter VCO Deviation CALC.3=1, VCO Bank CALC.4=1, VCO Current Strobe CMD Value Note ST 1 ST 2 ST 3 ST 4 ST 5-TX ST 5-RX 1011b 1010b 1000b 1001b 1101b 1100b Enter to PLL Enter to Standby 10.4.3 Enter to SLEEP Enter to IDLE Enter to TX Enter to RX 10.4.1 10.4.2 10.4.6 10.4.5 RST-CMD 00000000b Software Reset 10.5 l Be notice, refer to chapter 16 for definition of RX FIFO Full and TX FIFO Empty. Figure 11.7 State diagram of Power Saving FIFO Mode From Figure 11.7, when ST5 command is issued for TX operation, see Figure 11.8 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Nov., 2010, v1.1 49 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Strobe CMD
(SCS,SCK,SDIO) ST5 Next Instruction RF In/Out Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) 990 us (auto delay) Crystal Ready
(900 us) Preamble + ID Code + Payload Transmitting Time T0 T1 T0-T1: Auto Delay by Register setting (WSEL+PDL+TDL) Auto Back IDLE Mode T2 LO Freq. IDLE to PLL PLL to WPLL WPLL to TX TX Ready Time
(WSEL, Crystal Ready) Changed No Changed 300+600 us 300+600 us
(PDL) 30 us 30 us
(TDL) 60 us 60 us 990 us 990 us Figure 11.8 Transmitting Timing Chart of Power Saving FIFO Mode From Figure 11.7, when ST5 command is issued for RX operation, see Figure 11.9 for detailed timing. A7125 status can be represented to GIO1 or GIO2 pin to MCU for timing control. Strobe CMD
(SCS,SCK,SDIO) ST5 Next Instruction RF In/Out Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) 990 us Wait Packet Crystal ready
(900 us) Preamble + ID Code + Payload Receiving Time T0 T1 T2 Auto Back IDLE Mode T3 T0-T1: Crystal Ready + RX settling by register setting (WSEL+PDL+TDL) T1-T2: RX is ready, Wait for valid packet LO Freq. Changed No Changed IDLE to PLL
(WSEL) 300+600 us 300+600 us WPLL to RX WPLL to RX RX Ready Time
(TDL) 30 us 30 us
(TDL) 60 us 60 us 990 us 990 us Figure 11.9 Receiving Timing Chart of Power Saving FIFO Mode Nov., 2010, v1.1 50 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 11.5 Quick Direct Mode This mode is suitable for fast transceiving. After calibration flow, for every state transition, user has to issue Strobe command to A7125.This mode is also suitable for the requirement of versatile packet format. Noted that user needs to take care the transition time by MCUs timer. When packets are finished and deeper power saving is necessary, user can issue Strobe command to ask A7125 staying in idle mode (or sleep mode). Figure 11.3 is the state diagram of Quick Direct mode. 15.3 15.2 15.6 15.5 15.4 Section 10.4.4 CAL CMD CMD Value Calibration Section AK CALC.0=1, RSSI CALC.1=1, IF Filter CALC.2=1, VCO Deviation CALC.3=1, VCO Bank CALC.4=1, VCO Current Strobe CMD Value Note ST 1 ST 2 ST 3 ST 4 ST 5-TX ST 5-RX 1011b 1010b 1000b 1001b 1101b 1100b Enter to PLL Enter to Standby 10.4.3 Enter to SLEEP Enter to ID LE Enter to TX Enter to RX 10.4.1 10.4.2 10.4.6 10.4.5 RST-CMD 00000000b Software Reset 10.5 l Be notice, Dummy stands for dummy preamble. l Be notice, ST5 delay time is either 70 us (LO frequency changed) or 10 us (LO frequency NOT changed) Figure 11.10 State diagram of Quick Direct Mode Nov., 2010, v1.1 51 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 From Figure 11.10, when PLL mode transits to WPLL mode, LO (local oscillator) frequency changed or not will induce different PLL setting time by either 70us or 10 us. Therefore, MCU total delay time is different. See Table 11.1 for details. LO Freq. Changed No Changed PLL to WPLL WPLL to TX TX Ready Time 30 us 10 us 50 us 50 us 80 us 60 us Table 11.1 MCU total delay time from PLL to TX mode. From Figure 11.10, when A7125 enters TX mode, MCU should immediately deliver dummy preamble and defined packet to A7125s GIO1 or GIO2 pin. Dummy preamble is used to stabilize TX circuitry. See Table 11.2 for details. A7125 Data Rate Dummy Preamble Packet Note Preamble ID Max Payload 1 Mbps 2 Mbps 10 bits 20 bits 32 bits 32 bits 32 bits 32 bits 512 bytes 512 bytes Total Preamble = 42 bits Total Preamble = 52 bits Table 11.2 Format of dummy preamble and packet. From Figure 11.10, Table 11.1 and 11.2, MCU total delay time and dummy preamble are important for quick direct mode. When ST5 command is issued for TX operation, see Figure 11.4 for detailed timing. A7125 status can be represented to GIO1 and GIO2 pin to MCU for timing control. Strobe CMD
(SCS,SCK,SDIO) ST5 80 us / 60 us 10 us ST1 Dummy Preamble + Preamble + ID + Payload Dummy Preamble Transmitting Output GIO1 Pin - TRXD
(GPIO1S[3:0]=0111) GIO2 Pin - WTR
(GPIO2S[3:0]=0000) GIO2 Pin - TMEO
(GPIO2S[3:0]=0010) CKO Pin - DCK
(CKOS[3:0]=0000) T0 T1 T2 T3 T0-T1: MCU Total Delay Time, Refer to Table 11.1 T1-T2: Dummy Preamble, Refer to Table 11.2 T2: TMEO (TX Modulation Enable) is auto triggered T2-T3: Transmitting Time Figure 11.11 Transmitting Timing Chart of Quick Direct Mode From Figure 11.3, Table 11.1 and 11.2, RX settling time is important for quick direct mode. When ST5 command is issued for RX operation, after RX settling and preamble detect, A7125 offers ID sync function (if 32 bits ID is stored in ID Register) to generate FSYNC signal to inform MCU. Figure 11.5 is the detailed timing. A7125 status can be represented to GIO1 and GIO2 pin to MCU for timing control. Nov., 2010, v1.1 52 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 ST5 90 us / 70 us Wait Packet ST1 Preamble + ID + Payload Preamble Detect ID Sync. Payload Output Strobe CMD
(SCS,SCK,SDIO) GIO1 Pin - TRXD
(GPIO1S[3:0]=0111) GIO2 Pin - PMDO
(GPIO2S[3:0]=0011) GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001) CKO Pin - RCK
(CKOS[3:0]=0001) T0 T1 T2 T3 T4 T5 T0-T1: RX Ready Time T1-T2: RX is ready, wait for valid packet T2-T3: Preamble Detect T3-T4: ID Sync T4-T5: Payload Output LO Freq. PLL to WPLL WPLL to RX RX Ready Time Changed No Changed 30 us 10 us 60 us 60 us 90 us 70 us Figure 11.12 Receiving Timing Chart of Quick Direct Mode Nov., 2010, v1.1 53 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 A7125 needs external crystal or external clock that is either 6 or 8/12/16 MHz, to generate internal wanted clock. Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate. 12 Crystal Oscillator Circuit Relative Control Register Data Rate Clock Register (Address: 0Dh) Bit R/W Bit 7 Name Reset R W SDR1 SDR1 0 Bit 6 SDR0 SDR0 0 Bit 5 GRC3 GRC3 0 Bit 4 GRC2 GRC2 1 Bit 3 GRC1 GRC1 1 Bit 2 GRC0 GRC0 1 Bit 1 Bit 0 CGS
1
XS 1 12.1 Use External Crystal To use external crystal, user just sets XS= 1 (0Dh) to enable crystal oscillator. Figure 12.1 shows the connection of crystal network between XI and XO pins. C1 and C2 capacitance are used to adjust different crystal loading. A7125 support low cost crystal within 50ppmaccuracy. Be noted that crystal accuracy requirement includes initial tolerance, temperature drift, aging and crystal loading. i.e., Crystal = 16MHz (Cload =20pF), C1=C2=33pF. Figure12.1 Crystal network connection for using external crystal 12.2 Use External Clock A7125 has built-in AC couple capacitor to support external clock input. Figure 11.2 shows how to connect. In such case, XI pin is left opened. To use external clock from MCU instead of external crystal, user just sets XS= 0 (0Dh) to active AC couple capacitor. Be notice, the frequency accuracy of external clock shall be controlled within 50ppm and the clock swing (peak-to-peak) shall be larger than 1.5V.
(External clock is controlled within 50ppm and > 1.5Vpp.) Figure 12.2 Connect to external clock source Nov., 2010, v1.1 54 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 13. System Clock System clock (64MHz) is generated from crystal oscillator for internal digital circuitry. User can set Data Rate Clock Register (0Dh) to adapt different wanted crystal frequency (6/8/12/16MHz). Based on this, two important internal clocks FCGR and FSYCK are generated.
(1) FCGR: Clock Generation Reference = 2MHz (Ref. clock of internal 64MHz PLL)
(2) FSYCK: System Clock = 64 MHz
(Main clock for internal digital circuit) Relative Control Register Data Rate Clock Register (Address: 0Dh) Bit R/W Bit 7 Name Reset Name Reset R W R W SDR1 SDR1 0 DBL DBL 0 Bit 6 SDR0 SDR0 0 Bit 6 RRC1 RRC1 0 Bit 5 GRC3 GRC3 0 Bit 5 RRC0 RRC0 1 Bit 4 GRC2 GRC2 1 Bit 4 CHR3 CHR3 0 Bit 3 GRC1 GRC1 1 Bit 3 CHR2 CHR2 1 Bit 2 GRC0 GRC0 1 Bit 2 CHR1 CHR1 1 Bit 1 Bit 0 CGS
1 Bit 1 CHR0 CHR0 1
XS 1 Bit 0 IP8 BIP8 0 PLL Register II (Address: 0Fh) Bit R/W Bit 7 Because A7125 supports different external crystals, GRC [3:0] (0Dh) are used to get 2 MHz Clock Generation Reference
(FCGR) for internal usage. 13.1 Derive System Clock F CGR
F
)1]0:3[
GRC XREF
. Below is block diagram of system clock. FXTAL is the crystal frequency. User can set registers to get FSYCK = 64MHz. FXREF is the reference clock of Clock Generator to generate FCGR = 2MHz and FSPLL = 64MHz. After delay circuitry, System clock is derived, FSYCK = 64MHz. ADC clock (FADC = 4MHz or 8MHz) is from FSYCK = 64MHz after frequency divider. XI XO FXTAL GRC CGS CE XS CE CE FXREF
(GRC+1) PLL 64MHz DBL X 2 0 1 FCGR= 2MHz Delay Clock Generator FSPLL= 64MHz 1 0 System clock FSYCK= 64MHz
/ 8 4MHz
/ 2 0 1 8MHz ADC clock
(FADC) FSARS Figure 13.1 System Clock Block Diagram Recommend to set DBL (0Fh) = [0], then, FXREF = FXTAL Crystal Frequency
(FXTAL) 16 MHz Internal Crystal Clock Generation Reference
(FXREF) 16 MHz Reference
(FCGR) GRC [3:0]
Must be 2 MHz
[0111]
CGS 1 Nov., 2010, v1.1 55 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 12 MHz 8 MHz 6 MHz 12 MHz 8 MHz 6 MHz Must be 2 MHz Must be 2 MHz Must be 2 MHz
[0101]
[0011]
[0010]
1 1 1 Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate. 13.2 Data Rate A7125 supports programmable data rate by setting SDR [1:0] (0Dh). Data rate = (FIFCK / (SDR [1:0] +1)). The data rate clock is from IF clock (FIFCK) and FIFCK = FSYCK / 32 = 2 MHz Figure 13.2 Data Rate Block Diagram A7125 Data Rate =
1 32 F SYCK 0]:
SDR[1
1 FSYCK
(system clock) 64 MHz 64 MHz 64 MHz 64 MHz FIFCK
(IF clock) 2 MHz 2 MHz 2 MHz 2 MHz SDR [1:0]
(0Dh)
[00]
[01]
[10]
[11]
Data Rate 2 Mbps 1 Mbps Reserved Reserved Nov., 2010, v1.1 56 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 14. Transceiver Frequency A7125 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up LO (Local Oscillator) frequency for two-way radio transmission. To target full range of 2.4GHz ISM band (2400 MHz to 2483.5 MHz), A7125 applies offset concept by LO frequency FLO =
FLO_BASE + FOFFSET. Therefore, A7125 is easy to implement frequency hopping and multi-channels by ONE register setting, PLL Register I (CHN [7:0], 0Eh). In general, user can plan the wanted channels by a CHN Look-Up-Table to implement hopping table for two-way radio between master and slave. Below is the LO frequency block diagram. F XTAL X (DBL+1)
/ (RRC[1:0]+1) PFD VCO F LO FPFD AFC 1 0 F LO
AC[14:0]/ 2 16 0 F LO_BASE
F OFFSET Divider Figure 14.1 Block Diagram of Local Oscillator BIP[8:0] +
BFP[15:0]/ 2 16 CHN / [4*(CHR+1)]
Relative Control Register PLL Register I (Address: 0Eh) Bit Name Reset R/W Bit 7 R/W CHN7 0 PLL Register II (Address: 0Fh) Bit R/W Bit 7 PLL Register III (Address: 10h) Bit R/W Bit 7 PLL Register IV (Address: 11h) Name Reset Name Reset Name Reset Name Reset R W R W R W R W Bit 6 CHN6 0 Bit 6 RRC1 RRC1 0 Bit 6 IP6 BIP6 0 Bit 5 CHN5 0 Bit 5 RRC0 RRC0 1 Bit 5 IP5 BIP5 0 Bit 4 CHN4 0 Bit 4 CHR3 CHR3 0 Bit 4 IP4 BIP4 1 Bit 3 CHN3 0 Bit 3 CHR2 CHR2 1 Bit 3 IP3 BIP3 0 Bit 2 CHN2 0 Bit 2 CHR1 CHR1 1 Bit 2 IP2 BIP2 1 Bit 1 CHN1 0 Bit 1 CHR0 CHR0 1 Bit 1 IP1 BIP1 1 Bit 0 CHN0 0 Bit 0 IP8 BIP8 0 Bit 0 IP0 BIP0 0 DBL DBL 0 IP7 BIP7 1 Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
--/FP15 BFP15 0 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 0 0 0 0 0 0 BFP8 0 PLL Register V (Address: 12h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 BFP7 0 BFP6 0 BFP5 0 BFP4 0 BFP3 0 BFP2 1 BFP1 0 BFP0 0 Nov., 2010, v1.1 57 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver RX Register (Address: 19h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 4 W
RXSM1 RXSM0 1 0 FC 0 Bit 3 RXDI 0 Bit 2 DMG 0 Bit 1 RAW 1 Bit 0 ULS 0 14.1 LO Frequency Setting From Figure 14.1, FLO is not only for TX radio frequency but also to be RX LO frequency. To set up FLO, it is easy to implement by below 8 steps. Set the base frequency (FLO_BASE) by PLL Register II, III, IV and V (0Fh, 10h, 11h and 12h). Recommend to set FLO_BASE ~ 2400.001MHz. Set the channel step (FCHSP) by PLL Register II (0Fh). A7125 supports different channel steps by 2M / 1M / 500K / 250K. (500K is recommended.) 1. 2. 3. 4. Set CHN [7:0] to get offset frequency by PLL Register I (0Eh). FOFFSET = CHN [7:0] * FCHSP LO frequency is equal to base frequency plus offset frequency. FLO = FLO_BASE + FOFFSET FLO_BASE FLO F LO_BASE
F PFD
BIP
]0:8[
DBL
)1
BIP
]0:8[
F XTAL RRC 1]0:1[
BFP
]0:15[
16 2
) FOFFSET BFP
]0:15[
16 2 Base on the above formula, for example, if FXTAL = 16 MHz and step FCHSP = 500 KHz, To get FLO_BASE and FLO ,see Table 14.1, 14.2, 14.3 and Figure 14.2 for details. How to set FLO_BASE ~ 2400.001 MHz STEP 1 2 3 4 5 6 1 2 3 4 5 6 ITEMS FXTAL DBL RRC BIP BFP FLO_BASE ITEMS FLO_BASE CHR FCHSP CHN FOFFSET FLO How to set FLO = FLO_BASE + FOFFSET ~ 2405.001 MHz STEP VALUE 16 MHz 0 0 0x96 0x0004 NOTE Crystal Frequency Disable double function If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency
~2400.001 MHz Table 14.1 How to set FLO_BASE VALUE
~2400.001 MHz 7 500 KHz 0x0A 5 MHz
~2405.001 MHz Table 14.2 How to set FLO NOTE After set up BIP and BFP To get FCHSP= 500 KHz Channel step = 500KHz Set channel number = 10 FOFFSET= 500 KHz * (CHN) = 5MHz Get FLO= FLO_BASE + FOFFSET Nov., 2010, v1.1 58 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 14.2 show FLO ~ 2405.001 MHz and its registers setting. F XT AL=16M F PFD=16M X (DBL+1) DBL = 0
/ (RRC[1:0]+1) RRC = 0 PFD VCO FL O=
2405.001M AC[14:0]/ 2 16 AFC 1 0 0 Divider BIP[8:0] +
BFP[15:0]/ 2 16
(BIP = 0x96)
(BFP = 0x0004) F LO_BASE=2400.001M CHN / [4*(CHR+1)]
(CH N=0x0A)
(CHR = 7) FO FFSET= 5M
FLO=2405.001M
Figure 14.2 Block Diagram of FLO ~ 2405.001 MHz For different crystal frequency, 16MHz / 12MHz / 8 MHz / 6MHz, below are calculation details for
(1) How to set FLO_BASE ~ 2400.001 MHz
(2) How to set FLO ~ 2405.005 MHz Be notice if 6MHz external crystal (clock) is selected, A7125 only supports 1Mbps data rate. F PFD
DBL RRC f
)1
XTAL 1]0:1[
Recommend DBL = 0 FXTAL (MHz) DBL 16 12 8 6 16 12 8 6 0 0 0 0 BIP 0x096 0x0C8 0x12C 0x190 F LO _ BASE
F PFD
BIP
]0:8[
]0:15[
BFP 16 2
) FPFD (MHz)
(integer part)
(floating part) PRC 0 0 0 0 BFP 0x0004 0x0005 0x0008 0x000A F CHSP
PFD F
CHR 4
0:3
)1 F LO
F LO _ BASE
CHN
]0:7[
F CHSP
) FPFD (MHz) 16 12 8 6 FLO_BASE (MHz)
~2400.001
~2400.001
~2400.001
~2400.001 Nov., 2010, v1.1 59 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 FXTAL = 16 MHz, How to set FCHSP FPFD (MHz) CHR [3:0]
FCHSP (KHz) FXTAL = 12 MHz, How to set FCHSP FPFD (MHz) CHR [3:0]
FCHSP (KHz) FXTAL = 8 MHz, How to set FCHSP FPFD (MHz) CHR [3:0]
FCHSP (KHz) FXTAL = 6 MHz, How to set FCHSP FPFD (MHz) CHR [3:0]
FCHSP (KHz) 2000 1000 500 250 1000 500 250 2000 1000 500 250 500 250 1 3 7 15 2 5 11 0 1 3 7 2 5 16 16 16 16 12 12 12 8 8 8 8 6 6 CHN [7:0]
0x00 ~ 0x2A 0x00 ~ 0x54 0x00 ~ 0xA8 0x00 ~ 0xFF FOFFSET (MHz) 0 ~ 84 0 ~ 84 0 ~ 84 FLO (MHz) 2400 ~ 2484 2400 ~ 2484 2400 ~ 2484 0 ~ 63.75 Depends on FLO_BASE CHN [7:0]
0x00 ~ 0x54 0x00 ~ 0xA8 0x00 ~ 0xFF FOFFSET (MHz) 0 ~ 84 0 ~ 84 FLO (MHz) 2400 ~ 2484 2400 ~ 2484 0 ~ 63.75 Depends on FLO_BASE CHN [7:0]
0x00 ~ 0x2A 0x00 ~ 0x54 0x00 ~ 0xA8 0x00 ~ 0xFF FOFFSET (MHz) 0 ~ 84 0 ~ 84 0 ~ 84 FLO (MHz) 2400 ~ 2484 2400 ~ 2484 2400 ~ 2484 0 ~ 63.75 Depends on FLO_BASE CHN [7:0]
0x00 ~ 0xA8 0x00 ~ 0xFF FOFFSET (MHz) 0 ~ 84 0 ~ 63.75 FLO (MHz) 2400 ~ 2484 Depends on FLO_BASE Be notice if 6MHz external crystal (clock) is selected and DBL=0, A7125 only supports 1Mbps data rate. Nov., 2010, v1.1 60 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 In two ways radio, both master and slave have two roles, TX and RX. In general, slave usually has to reply an ACK-packet or status update. In such case, A7125 offers two methods to set up FLO while TRX exchanging. 14.2 IF Side Band Select
(1) Auto IF exchange
(2) Fast exchange Relative Control Register Mode Control Register (Address: 01h) Bit R/W Bit 7 RX Register (Address: 19h) Name Reset Bit Name Reset R W W DDPC DDPC 0 Bit 6 ARSSI ARSSI 0 Bit 5 AIF AIF 0 Bit 4 CD DFCD 0 Bit 3 WWSE WWSE 0 R/W Bit 7 Bit 6 Bit 5 Bit 4
RXSM1 RXSM0 1 0 FC 0 Bit 3 RXDI 0 Bit 2 FMT FMT 0 Bit 2 DMG 0 Bit 1 FMS FMS 0 Bit 1 RAW 1 Bit 0 ADCM ADCM 0 Bit 0 ULS 0 Register Setting AIF Function ULS=0 ULS=1 ULS=0 ULS=1 Disable
(AIF=0) Enable
(AIF=1) FRXLO Formula FRXLO = FLO FRXLO = FLO FRXLO = FLO 2MHz FRXLO = FLO 2MHz Table 14.3 FRXLO Formula Nov., 2010, v1.1 61 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 14.2.1 Auto IF Exchange A7125 supports Auto IF offset function (AIF, 01h). If AIF is enabled, only one On-air frequency (Fcarrier) is occupied. In this case, user has no need to change FRXLO while TRX exchanging because FRXLO is auto shifted FIF. See below Figures and Table 14.4 for details.
<Master>
AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXLO for 2MHz (FIF). FTXLO = FLO = FCarrier FLO_BASE FRXLO FOFFSET =5MHz
<Slave>
AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXLO for 2MHz (FIF). FIF 2MHz FIF 2MHz FTXLO = FLO = FCarrier FLO_BASE FRXLO FOFFSET =5MHz Item Role AIF ULS CHN[7:0]
TX RX TX RX 1 1 1 1 0 0 0 0 10 10 10 10 FCHSP
(KHz) 500 500 500 500 FTXLO
(KHz) FRXLO
(MHz) 2405.001 NOTE 2405.001
2403.001 Up side band FRXLO is auto shifted 2403.001 Up side band FRXLO is auto shifted
Master Slave Role Exchanging Switching Time Above setting is the same to Master and Slave. Refer to Figure 11.4, If A7125 delivers one packet and receives one packet, FLO is changed from 2405.001 to 2403.001, longer switching time. Total Switching time = TX ready time + RX ready time
=( 30 us + 60 us) + ( 30 us + 60 us)
= 180 us On air frequency Master FTXLO = 2405.001 MHz Slave FTXLO = 2405.001 MHz
(ONE occupied frequency only.) Table 14.4 AIF function while TRX exchanging 14.2.2 Fast Exchange To reduce PLL settling time, user can disable AIF function. If AIF is disabled, two On-air frequency (FCarrier (master), FCarrier
(slave)) are occupied. In this case, user has to control ULS =0 (Master side) and ULS = 1 (Slave side) for fast exchange in two-way radio. See below Figures and Table 14.5 for details. Nov., 2010, v1.1 62 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125
<Master>
AIF=0 and ULS=0, Master is set Up side band. FTXLO = FLO = FCarrier (Master) FLO_BASE FRXLO FOFFSET =5MHz
<Slave>
AIF=0 and ULS=1, Slave is set Low side band. FIF 2M FLO_BASE FOFFSET =7MHz FTXLO= FLO = FCarrier (Slave) FRXLO Item Role AIF ULS CHN[7:0]
TX RX TX RX 0 0 0 0 0 0 1 1 10 10 14 14 FCHSP
(KHz) 500 500 500 500 FTXLO
(KHz) FRXLO
(MHz) 2405.001 NOTE 2405.001 Up side band
2407.001
2407.001 Low side band Master Slave Role Exchanging Switching Time ULS and CHN setting are different in Master and Slave site. Refer to Figure 11.4, If A7125 delivers one packet and receives one packet, Masters FLO is fixed at 2405.001MHz, shorter settling time. Total Settling time = TX ready time + RX ready time
= 140 us
= ( 10 us + 60 us) + ( 10 us + 60 us) On air frequency Master FTXLO = 2405.001 MHz Slave FTXLO = 2407.001 MHz
(TWO occupied on-air frequency.) Table 14.5 Fast exchange function while TRX exchanging 14.3 Band Edge Frequency Setting For 2.4GHz ISM band, it is free licensed from 2400 MHz to 2483.5 MHz. Due to regulation criteria, in general, most of applications are avoided to use band edge of 2400MHz and 2483.5MHz. Therefore, in such cases, user can define specific band edges and set different FLO_BASE. Combined with different channel step FCHSP, user can gain different on air channel numbers. See table 14.1 for reference. User Defined
(Low Band Edge) User Defined
(High Band Edge) Cover Range
(MHz) FCHSP
(KHz) On air Channel NOTE FLO_BASE
(MHz)
(recommended) Nov., 2010, v1.1 63 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 2400 MHz 2483.5 MHz 83.5 MHz
~2400.001 2405 MHz 2477.0 MHz 72.0 MHz
~2405.001 2405 MHz 2467.0 MHz 62.0 MHz
~2405.001 2410 MHz 2463.0 MHz 52.0 MHz
~2410.001 2000 1000 500 2000 1000 500 2000 1000 500 2000 1000 500 FCHSP
(KHz) 250 250 Numbers 42 37 32 27 37 31 On air Channel Numbers 2.0 MHz / on air channel step 2.0 MHz / on air channel step 2.0 MHz / on air channel step 2.0 MHz / on air channel step NOTE 1.75 MHz / on air channel step 1.75 MHz / on air channel step User Defined
(Low Band Edge) User Defined
(High Band Edge) Cover Range
(MHz) FLO_BASE
(MHz) 2405 MHz 2468.0 MHz 63.0 MHz
~2405.001 2410 MHz 2462.5 MHz 52.5 MHz
~2405.001 Be notice, if FCHSP = 250 KHz, due to limitation of CHN [7:0], max cover range of FLO is 63.75MHz. Table 14.6 Band edge frequency setting vs. on air channel number In long distance applications, user usually adds external PA (Ext-PA) to extend TX power level up 10dBm ~ 20 dBm. To gain the most available hopping channels under FCC / ETSI regulations, user has to switch off Ext-PA before A7125s PA (Em-PA) to minimize spurious emission. In the other words, band edge becomes critical so that A7125 supports two methods (EOPD and PASW) to let user switch Ext-PA easily.
(1) EOPD (End Of Packet Delay) Set GIO2S = [1100] and EOPDS=1, then EOPD outputs 20 us pulse to GIO2 pin. Nov., 2010, v1.1 64 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125
(2) PASW (Ext-PA Switch) Set GIO2S = [0001] and EOPDS=1, then PASW outputs to GIO2 pin. However, GIO2S[3:0] shall be set different in TX mode [ 0001] and RX mode [0100] to avoid FSYNC conflict in RX mode. Therefore, before issue TX Strobe command, write GIO2S = [0001]. Before issue RX Strobe command, write GIO2S = [0100]. Then, PASW is only active in TX mode. In such case, user just needs to connect GIO2 pin to control external PA as shown below. Generally, this procedure could support sufficient band edge control. In more rigorous condition, it is recommended to switch GIO2S from [0100] to [0001]
after delaying 30us counting from TX strobe command. 14.4 Frequency Compensation AFC (Auto Frequency Compensation) function supports low accuracy crystal without sensitivity degradation. If AFC=1
(19h), bit error rate is optimized because AFC circuitry adjusts RX LO frequency (FRXLO) to compensate crystal drift automatically. F XTAL FPFD F LO X (DBL+1)
/ (RRC[1:0]+1) PFD VCO BIP[8:0] +
BFP[15:0]/ 2 16 CHN / [4*(CHR+1)]
AC[14:0]/ 2 16 1 0 0 F LO_BASE AFC
F OFFSET F LO
Divider Figure 14.3 Block Diagram of enabling FC function Nov., 2010, v1.1 65 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Relative Control Register RX Register (Address: 19h) PLL Register IV (Address: 11h) Bit Name Reset Name Reset Name Reset W R W R W PLL Register V (Address: 12h) R/W Bit 7 Bit 6 Bit 5 RXSM1 RXSM0
Bit 4 AFC 0 Bit 3 RXDI 0 Bit 2 DMG 0 Bit 1 RAW 1 Bit 0 ULS 0 Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
--/FP15 BFP15 0 AC14/FP14 AC13/FP13 AC12/P12 AC11/ FP11 AC10/FP10 AC9/FP9 AC8/FP8 BFP14 BFP13 BFP12 BFP11 BFP10 BFP9 0 0 0 0 BFP8 0 1 0 0 0 Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7/FP7 AC6/FP6 AC5/FP5 AC4/FP4 AC3/FP3 AC2/FP2 AC1/FP1 AC0/FP0 BFP7 0 BFP6 0 BFP5 0 BFP4 0 BFP3 0 BFP2 1 BFP1 0 BFP0 0 Nov., 2010, v1.1 66 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 15. Calibration A7125 needs calibration process during initialization by below 5 items, they are, VCO Current, VCO Bank, VCO Deviation, IF Filter Bank and RSSI Calibration. 1. 2. 3. 4. 5. VCO Current Calibration is to find adequate VCO current. VCO Bank Calibration is to select best VCO frequency bank for the calibrated frequency. VCO Deviation Calibration is to calibrate 500 KHz deviation of VCO. IF Filter Bank Calibration is to calibrate IF filter bandwidth and center frequency. RSSI Calibration is to find the RSSI value corresponding to -70dBm RF input and RSSI curve. Be notice that VCO Current, Bank and Deviation is calibrated in PLL mode by sequence. IF Filter Bank and RSSI can be calibrated either in standby or PLL mode. User can set A7125 in PLL mode and enable 5 control registers together, then, all calibration procedures are automatically executed and its results are stored in calibration flags. Relative Control Register Calibration Control Register (Address: 02h) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 R/W
Bit 4 VCC 0 Bit 3 VBC 0 Bit 2 VDC 0 Bit 1 FBC 0 Bit 0 RSSC 0 15.1 Calibration Procedure 1. 2. 3. 4. 5. 6. Initialize all control registers (refer to A7125 reference code). Select auto value mode (set MFBS, MVCS, MVBS, MVDS= 0). Set A7125 in PLL mode. Enable IF Filter Bank and RSSI Calibration (set FBC, RSSC= 1) and Enable VCO Current, Bank and Deviation Calibration (VCC, VBC, VDC= 1). After calibration done, FBC, RSSC, VCC, VBC and VDC are auto clear. Check pass or fail by calibration flag
(FBCF) and (VCCF, VBCF). 15.2 IF Filter Bank Calibration IF Calibration Register I (Address: 23h) Bit R/W Bit 7 Bit 6 Bit 5 Name Reset R W
Bit 4 FBCF MFBS 0 Bit 3 FB3 MFB3 0 Bit 2 FB2 MFB2 1 Bit 1 FB1 MFB1 1 Bit 0 FB0 MFB0 0 1. 2. 3. 4. 5. 6. 7. 8. Initialize all control registers (refer A7125 reference code). Set MFBS= 0 for auto calibration. Set A7125 in PLL mode. Set FBC= 1 (02h). The maximum calibration time for this calibration is about 64us. FBC is auto clear after calibration done. User can read calibration flay (FBCF, 23h) to check pass or fail. User also can read FB [3:0] (23h) to get the auto calibration value. 15.3 RSSI Calibration 1. 2. 3. Initialize all control registers (refer A7125 reference code). Set A7125 in PLL mode. Set RSSC= 1 (02h). RSSC is auto clear after calibration done. Nov., 2010, v1.1 67 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 4. No need to check calibration flag. 15.4 VCO Current Calibration VCO Current Calibration Register (Address: 25h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset R W
VCCS
1 VCB3 VCOC3 VCB2 VCOC2 VCB1 VCOC1 VCB0 VCOC0 1 1 0 0 Bit 4 VCCF MVCS 0 1. 2. 3. 4. 5. 6. 7. Initialize all control registers (refer A7125 reference code). Set MVCS= 0 for auto calibration. Set A7125 in PLL mode. Set VCC= 1 (02h). VCC is auto clear after calibration done. User can read calibration flag (VCCF, 25h) to check pass or fail. User can read VCB [3:0] (25h) to get the auto calibration value. 15.5 VCO Bank Calibration VCO Bank Calibration Register I (Address: 26h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Name Reset R W
1
1 DDC1 DDC0 DAGS
0
Bit 3 VBCF MVBS 0 Bit 2 VB2 MVB2 1 Bit 1 VB1 MVB1 0 Bit 0 VB0 MVB0 0 1. 2. 3. 4. 5. 6. 7. 8. Initialize all control registers (refer A7125 reference code). Set MVBS= 0 for auto calibration. Set A7125 in PLL mode. Set VBC= 1 (02h). The maximum calibration time for VCO Bank Calibration is about 240 us (4 * PLL settling time). VBC is auto clear after calibration done. User can read calibration flag (VBCF, 26h) to check pass or fail. User can read VB [2:0] (26h) to get the auto calibration value. 15.6 VCO Deviation Calibration VCO Deviation Calibration Register II (Address: 29h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset ADEV7 R W MVDS 0 ADEV6 MDEV6 0 ADEV5 ADEV4 MDEV5 MDEV4 ADEV3 ADEV2 MDEV3 MDEV2 ADEV1 ADEV0 MDEV1 MDEV0 1 0 1 0 0 0 1. 2. 3. 4. 5. 6. 7. Initialize all control registers (refer A7125 reference code). Set MVDS= 0 for auto calibration. Set A7125 in PLL mode. Set VDC= 1 (02h). VDC is auto clear after calibration done. User can read ADEV [7:0] (29h) to get the auto calibration value. No need to check calibration flag. 15.7 Channel Group Function Channel group function is used for VCO calibration that supports to increase the accuracy of VCO Current, Bank and Deviation. By this function, user can easily set Channel Group Register I and II (13h, 14h) to get 2.4G ISM band into 3 groups as shown below. Then, choose middle frequency (2415MHz / 2445MHz / 2475MHz) of 3 groups to do the VCO Nov., 2010, v1.1 68 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Current, Bank and Deviation Calibration. Below is an example of channel group distribution. 2 4 1 5 M H z 2 4 4 5 M H z 2 4 7 5 M H z IS M b a n d 2 4 0 0 M H z 2 4 3 0 M H z
(C H G L ) 2 4 6 0 M H z
(C H G H ) 2 4 8 3 .5 M H z Channel Group Register I (Address: 13h) Figure 15.1 Channel Group setting of VCO calibration Channel Group Register II (Address: 14h) R/W Bit 7 R/W CHGL7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL1 CHGL0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 R/W Bit 7 R/W CHGH7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGH0 See below table for setting CHGL and CHGH to get 2430MHz and 2460MHz respectively. FPFD (MHz)
(integer part)
(floating part) FLO_BASE (MHz) FCHSP (KHz) CHGL[7:0]
CHGH[7:0]
BIP 0x096 0x0C8 0x12C 0x190 BFP 0x0004 0x0005 0x0008 0x000A
~2400.001
~2400.001
~2400.001
~2400.001 0x3C 0x3C 0x3C 0x3C 0x78 0x78 0x78 0x78 Bit Name Reset Bit Name Reset 16 12 8 6 1 1 500 500 500 500 Nov., 2010, v1.1 69 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 16. FIFO (First In First Out) A7125 supports separated 64-bytes TX and RX FIFO by enabling FMS =1 (01h). For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, once RX circuitry synchronizes ID Code, received payload is stored into RX FIFO. In chapter 10 and 11, user can also find below FIFO information.
(1) Figure 10.15 and 10.16 for FIFO accessing via 3-wire SPI.
(2) Section 10.4.7 and 10.4.8 for FIFO pointer reset command.
(3) Figure 11.2 and Figure 11.3 for Normal/Quick FIFO mode. 16.1 Packet Format of FIFO mode D a ta w h ite n in g (o p tio n a l) F E C e n co d e d /d e c o de d (o p tio n a l) C R C -1 6 c a lcu la tio n (o p tio n a l) P re a m b le ID c o d e P a y lo a d 4 b yte s 4 b yte s M a x . 2 5 6 b y te s
(C R C ) 2 b yte s Figure 16.1 Packet Format of FIFO mode ID code ID Byte 0 ID Byte 1 ID Byte 2 ID Byte 3 Figure 16.2 ID Code Format Preamble:
The packet is led by preamble which is composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be 01010101. In the contrast, if the first bit of ID code is 1, preamble shall be 10101010. Preamble length is recommended to set 4 bytes by PML [1:0] (20h). ID code:
ID code is recommended to set 4 bytes by IDL=1 (20h) and ID Code is sequenced by ID Byte 0, 1, 2 and 3. If RX circuitry check ID code is correct, payload will be written into RX FIFO. In special case, ID code could be set error tolerance (0~ 3bit error) by ETH [1:0] (21h) for ID synchronization check. Payload:
Payload length is programmable by FEP [7:0] (03h). The physical FIFO depth is 64 bytes. A7125 also supports logical FIFO extension up to 256 bytes. See section 16.5 for details. CRC (option):
In FIFO mode, if CRC is enabled (CRCS=1, 20h), 2-bytes of CRC value is transmitted automatically after payload. In the same way, RX circuitry will check CRC value and show the result to CRC Flag (00h).CRC Flag is updated by each received packet. Relative Control Register Mode Register (Address: 00h) Bit R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reset R W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN PLLER CRCF TRSR TRER FECF CER XER
Nov., 2010, v1.1 70 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 FIFO Register I (Address: 03h) Bit Name Reset R/W W Bit 7 FEP7 0 Bit 6 FEP6 0 Bit 5 FEP5 1 Bit 4 FEP4 1 Bit 3 FEP3 1 Bit 2 FEP2 1 Bit 1 FEP1 1 Bit 0 FEP0 1 Code Register I (Address: 20h) R/W Bit 7 Bit 6 Bit Name Reset Bit Name Reset Bit Name Reset Code Register II (Address: 21h) R/W Bit 7 Code Register III (Address: 22h) R/W Bit 7 W W W
Bit 6 DCL2 1 Bit 6 WS6 0 Bit 5 WHTS 0 Bit 4 FECS 0 Bit 3 CRCS 0 Bit 5 DCL1 1 Bit 5 WS5 1 Bit 4 DCL0 1 Bit 4 WS4 0 Bit 3 ETH1 0 Bit 3 WS3 1 Bit 2 IDL 1 Bit 2 ETH0 1 Bit 2 WS2 0 Bit 1 PML1 1 Bit 0 PML0 1 Bit 1 PMD1 1 Bit 0 PMD0 1 Bit 1 WS1 1 Bit 0 WS0 0 16.2 Bit Stream Process A7125 supports 3 optional bit stream process for payload, they are,
(1) CCITT-16 CRC
(2) (7, 4) Hamming FEC
(3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence). CRC (Cyclic Redundancy Check):
1. CRC is enabled by CRCS= 1 (20h). TX circuitry calculates the CRC value of payload (preamble, ID code excluded) and transmits 2-bytes CRC value after payload. RX circuitry checks CRC value and shows the result to CRC Flag (00h). If CRCF=0, received payload is correct, else error occurred. (CRCF is read only, it is updated by each valid packet.) FEC (Forward Error Correction):
1. 2. FEC is enabled by FECS= 1 (20h). Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code. Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically.
(ex. 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.) RX circuitry decodes received code words automatically. FEC supports 1-bit error correction each code word. Once 1-bit error occurred, FEC flag=1 (00h). (FECF is read only, it is updated by each valid packet.) Data Whitening:
1. Data whitening is enabled by WHTS= 1 (20h). Payload and CRC value (if CRCS=1) or their encoded code words (if FECS=1) are encrypted by bit XOR operation with PN7. The initial seed of PN7 is set by WS [6:0] (22h). RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Be notice, user shall set the same WS [6:0] (22h) to TX and RX. 2. 3. 2. 16.3 Transmission Time Based on CRC and FEC options, the transmission time are different. See table 16.1 for details. Data Rate = 2 Mbps Data Rate Preamble ID Code Payload
(Mbps)
(bits)
(bits) 2 2 2 2 32 32 32 32 32 32 32 32
(bits) 512 512 512 512 CRC
(bits) Disable 16 bits Disable 16 * 7 / 4 FEC Disable Disable Transmission Time / Packet 576 bit * 0.5 us = 288 us 592 bit * 0.5 us = 296 us 960 bit * 0.5 us = 480 us 988 bit * 0.5 us = 494 us 512 * 7 / 4 512 * 7 / 4 Table 16.1 Transmission time of 2 Mbps data rate Nov., 2010, v1.1 71 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Data Rate = 1 Mbps Data Rate Preamble ID Code Payload
(Mbps)
(bits)
(bits) 1 1 1 1 32 32 32 32 32 32 32 32
(bits) 512 512 512 512 CRC
(bits) Disable 16 bits Disable 16 * 7 / 4 FEC Disable Disable Transmission Time / Packet 576 bit * 1.0 us = 576 us 592 bit * 1.0 us = 592 us 960 bit * 1.0 us = 960 us 988 bit * 1.0 us = 988 us 512 * 7 / 4 512 * 7 / 4 Table 16.2 Transmission time of 1 Mbps data rate 16.4 Usage of TX and RX FIFO In application points of view, A7125 supports 3 options of FIFO arrangement.
(1) Easy FIFO
(2) Segment FIFO
(3) FIFO Extension For FIFO operation, A7125 supports Strobe command to reset TX and RX FIFO pointer as shown below. User can refer to section 10.5 for FIFO write pointer reset and FIFO read pointer reset. Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 Description 1 1 1 1 1 1 0 1 x x x x X X x FIFO write pointer reset (for TX FIFO) x FIFO read pointer reset (for RX FIFO) FIFO Register I (Address: 03h) Bit Name Reset R/W W Bit 7 FEP7 0 Bit 6 FEP6 0 Bit 5 FEP5 1 Bit 4 FEP4 1 Bit 3 FEP3 1 Bit 2 FEP2 1 Bit 1 FEP1 1 Bit 0 FEP0 1 Bit 7 FPM1 0 Bit 6 FPM0 1 Bit 5 PSA5 0 Bit 4 PSA4 0 Bit 3 PSA3 0 Bit 2 PSA2 0 Bit 1 PSA1 0 Bit 0 PSA0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO7 FIFO6 FIFO5 FIFO4 FIFO3 FIFO2 FIFO1 FIFO0 0 0 0 0 0 0 0 0 FIFO Register II (Address: 04h) FIFO DATA Register (Address: 05h) Bit Name Reset Bit Name Reset R/W W R/W R/W 16.4.1 Easy FIFO Register setting TX FIFO Length
(byte) 1 RX FIFO Length
(byte) 1 In Easy FIFO, max FIFO length is 64 bytes. FIFO length is equal to (FEP [7:0] +1). User just needs to control FEP [7:0]
(03h) and disable PSA and FPM as shown below. Control Registers FEP[7:0]
(03h) 0x00 FPM[1:0]
(04h) 0 PSA[5:0]
(04h) 0 72 Nov., 2010, v1.1 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 8 16 32 64 8 16 32 64 0x07 0x0F 0x1F 0x3F 0 0 0 0 0 0 0 0 Table 16.3 Control registers of Easy FIFO Initialize all control registers (refer A7125 reference code). Set FEP [7:0] = 0x3F for 64-bytes FIFO. Refer to Figure 11.2 and Figure 11.3 Send Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Transmitting 1. 2. 3. 4. 5. MCU writes 64-bytes data to TX FIFO. 6. 7. Send TX Strobe Command. Done. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading. 2. 3. MCU read 64-bytes from RX FIFO. 4. Send Strobe command RX FIFO read pointer reset. Done. Figure 16.3 Easy FIFO 16.4.2 Segment FIFO In Segment FIFO, TX FIFO length is equal to (FEP [7:0] PSA [5:0]1). FPM [1:0] should be zero. This function is very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [7:0]) and issues TX strobe command. If TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length are 8 bytes TX Control Registers Segment PSA FEP FIFO Length PSA[5:0]
FEP[7:0]
(04h)
(03h) FPM[1:0]
(04h) Nov., 2010, v1.1 73 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 1 2 3 4 5 6 7 8 PSA1 PSA2 PSA3 PSA4 PSA5 PSA6 PSA7 PSA8 FEP1 FEP2 FEP3 FEP4 FEP5 FEP6 FEP7 FEP8
(byte) 8 8 8 8 8 8 8 8 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x07 0x0F 0x17 0x1F 0x27 0x2F 0x37 0x3F 0 0 0 0 0 0 0 0 RX FIFO Length
(byte) 8 Control Registers PSA[5:0]
FEP[7:0]
(04h) 0
(03h) 0x07 FPM[1:0]
(04h) 0 Table 16.4 Segment FIFO is arranged into 8 segments Initialize all control registers (refer A7125 reference code). Refer to Figure 11.2 and Figure 11.3 (in chapter 11). Send Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Transmitting 1. 2. 3. 4. MCU writes fixed code into corresponding segment FIFO once and for all. 5. To consign Segment 1, set PSA = 0x00 and FEP= 0x07 To consign Segment 2, set PSA = 0x08 and FEP= 0x0F To consign Segment 3, set PSA = 0x10 and FEP= 0x17 To consign Segment 4, set PSA = 0x18 and FEP= 0x1F To consign Segment 5, set PSA = 0x20 and FEP= 0x27 To consign Segment 6, set PSA = 0x28 and FEP= 0x2F To consign Segment 7, set PSA = 0x30 and FEP= 0x37 To consign Segment 8, set PSA = 0x38 and FEP= 0x3F Send TX Strobe Command. Done. 6. 7. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading. 2. 3. MCU read 8-bytes from RX FIFO. 4. Send Strobe command RX FIFO read pointer reset. Done. Nov., 2010, v1.1 74 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 16.4 Segment FIFO Mode Nov., 2010, v1.1 75 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 16.4.3 FIFO Extension In FIFO Extension, FIFO length is equal to (FEP [7:0] +1). PSA [5:0] shall be zero, and FPM [1:0] is used to set FIFO Pointer Flag (FPF) to MCU. FIFO extension could be set up to 256 bytes by FEP [7:0] with different FPF trigger conditions. Be notice, setting of SPI data rate is important to prevent error operation of FIFO extension. The min. SPI data rate shall be equal or greater than (A125 data rate + 500Kbps) and refer Table 16.4 and 16.5 for max. SPI Data Rate. If A7125 data rate = 2Mbps and FIFO extension = 256 bytes. FIFO Length
(byte) 256 FIFO Length
(byte) 256 TX FPF Trigger Condition Delta = 04 Delta = 08 Delta = 12 Delta = 16 TX FPF Trigger Condition Delta = 04 Delta = 08 Delta = 12 Delta = 16 Control Registers FEP[7:0]
FPM[1:0] PSA[5:0]
FIFO Length
(byte) 256 Max. SPI Data Rate 10 Mbps 10 Mbps 10 Mbps 8 Mbps Max. SPI Data Rate 10 Mbps 10 Mbps 10 Mbps 8 Mbps 0xFF Table 16.5 How to set FIFO extension when A7125 is at 2Mbps data rate FIFO Length
(byte) 256 Max SPI Data Rate 10 Mbps 8 Mbps 5 Mbps 4 Mbps Control Registers Max SPI Data FEP[7:0]
FPM[1:0] PSA[5:0]
Rate 10 Mbps 8 Mbps 5 Mbps 4 Mbps 0xFF 00 01 10 11 00 01 10 11 0 0 0 0 0 0 0 0 RX FPF Trigger Condition Delta = 60 Delta = 56 Delta = 52 Delta = 48 RX FPF Trigger Condition Delta = 60 Delta = 56 Delta = 52 Delta = 48 If A7125 data rate = 1Mbps and FIFO extension = 256 bytes. Table 16.6 How to set FIFO extension when A7125 is at 1Mbps data rate Please refer to AMICCOMs reference code (FIFO extension) for details. Send TX Strobe command. Initialize all control registers (refer A7125 reference code). Set FEP [7:0] = 0xFF for 256-bytes FIFO extension. Set FPM [1:0] = 11 for FPF trigger condition. Set CKO Register = 0x12 Send Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Extension 1. 2. 3. 4. 5. 6. MCU writes 1st 64-bytes TX FIFO. 7. 8. MCU monitors FPF from A7125s CKO pin. 9. 10. Monitor FPF. 11. FPF triggers MCU to write 3rd 48-bytes TX FIFO. 12. Monitor FPF. 13. FPF triggers MCU to write 4th 48-bytes TX FIFO. 14. Monitor FPF. 15. FPF triggers MCU to write 5th 48-bytes TX FIFO. 16. Done. FPF triggers MCU to write 2nd 48-bytes TX FIFO. Nov., 2010, v1.1 76 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 16.5 TX FIFO Extension Nov., 2010, v1.1 77 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 FPF triggers MCU to read 1st 48-bytes RX FIFO. Initialize all control registers (refer A7125 reference code). Set FEP [7:0] = 0xFF for 256-bytes FIFO extension. Set FPM [1:0] = 11b for FPF trigger condition. Set CKO Register = 0x12 Send Strobe command RX FIFO read pointer reset. Send RX Strobe command. Procedures of RX FIFO Reading 1. 2. 3. 4. 5. 6. 7. MCU monitors FPF from A7125s CKO pin. 8. 9. Monitor FPF. 10. FPF triggers MCU to read 2nd 48-bytes RX FIFO. 11. Monitor FPF. 12. FPF triggers MCU to read 3rd 48-bytes RX FIFO. 13. Monitor FPF. 14. FPF triggers MCU to read 4th 48-bytes RX FIFO. 15. Monitor FPF. 16. FPF triggers MCU to read 5th 48-bytes RX FIFO. 17. Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO 18. Done. Nov., 2010, v1.1 78 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Figure 16.6 RX FIFO Extension Mode Nov., 2010, v1.1 79 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 16.5 Optimize Throughput To get the best throughput during two-way radio transmission, user can use FIFO Extension mode, section 16.4.3, to reduce overhead of preamble, ID, settling time delay of PDL and TDL. The disadvantage of FIFO Extension is more MCU loading and overhead of retransmission time if packet lost. In another way, by Easy FIFO mode, If MCUs SPI bus 2.5Mbps, user can use WTR signal to Read / Write FIFO during PDL+TDL settling time to gain more throughput. See below illustrations with pre-conditions. A7125s data rate = 2Mbps. Pre-Conditions:
1. 2. Min. requirement of CPU SPI bus = 2.5 Mbps > A7125s data rate. 3. If MCU SPI bus = 8Mbps and ignore guard time of SPI. i. ii. Write TX-FIFO = (addr+data) * 0.125 us = (1+64) * 8 * 0.125 = 65 us. Read RX-FIFO = (addr+data) * 0.125 us = (1+64) * 8 * 0.125 = 65 us. CRC is enabled. Use Easy FIFO mode (64 bytes). 4. 5. 6. One packet = Preamble + ID + Payload + CRC = (4+4+64+2) * 8 = 592 bit. 7. One packet transmission time = 592 bits * 0.5 = 296 us. 8. W=1 us if EOPDS = 0; W=23.5 us if EOPDS = 1 9. One frequency channel for n-packets. 10. MCU monitors WTR. However, If MCUs SPI bus < 2.5Mbps and EOPD =1 for band edge optimization in adding Ext-PA application, user can use EOP signal to Write FIFO to gain a few throughput. See below illustrations with pre-conditions. Nov., 2010, v1.1 80 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Pre-Conditions:
1. 2. A7125s data rate = 2Mbps. If MPU SPI bus = 1Mbps and ignore guard time of SPI, CRCF Check and MCUs ISR. i. ii. Write TX-FIFO = (addr+data) * 1 us = (1+64) * 8 * 1 = 520 us. Read RX-FIFO = (addr+data) * 1 us = (1+64) * 8 * 1 = 520 us. CRC is enabled. Use Easy FIFO mode (64 bytes). 3. 4. 5. One packet = Preamble + ID + Payload + CRC = (4+4+64+2) * 8 = 592 bit. 6. One packet transmission time = 592 bits * 0.5 = 296 us. 7. 8. One frequency channel for n-packets. 9. MCU monitors EOP. EOPDS = 1. TX-
Strobe Cmd TX-
Strobe Cmd TX-
Strobe Cmd GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - EOP
(GIO1S[3:0]=1100) GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - EOP
(GIO1S[3:0]=1100) Packet 1 90us
(PDL+TDL) 296 us Packet 2 70us
(PDL+TDL) 296 us Packet n 70us
(PDL+TDL) 296 us 23.5 us 23.5 us 23.5 us 520 us 520 us Write TX-FIFO
(64 bytes) Write TX-FIFO
(64 bytes) Total Transmitting Time (Master Site in TX Mode) RX-
Strobe Cmd RX-
Strobe Cmd RX-
Strobe Cmd Packet 1 90us
(PDL+TDL) 296 us Packet 2 70us
(PDL+TDL) 296 us Packet n 70us
(PDL+TDL) 296 us 23.5 us 23.5 us 520 us 520 us Read RX-FIFO
(64 bytes) Read RX-FIFO
(64 bytes) Total Receiving Time (Slave Site in RX Mode) 23.5 us 520 us Read RX-FIFO
(64 bytes) Nov., 2010, v1.1 81 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver 17. ADC (Analog to Digital Converter) A7125 has built-in 8-bits ADC that supports multi-functions to do temperature measurement, RSSI, carrier detection. User can set FSARS (1Fh) to select 4MHz or 8MHz ADC clock (FADC). The converting time is 20 times of ADC clock periods. Bit XADS RSS 0 0 1 0 1 X Description Standby mode Temperature None Reserved RX mode None RSSI / Carrier detect None Table 17.1 ADC Function List. Relative Control Register Mode Control Register (Address: 01h) R/W Bit 7 R W DDPC DDPC 0 Bit 6 ARSSI ARSSI 0 Bit 5 AIF AIF 0 Bit 4 CD DFCD 0 Bit 3 WWSE WWSE 0 RX Gain Register IV (Address: 1Dh) R/W Bit 7 Bit 6 Bit 5 Bit 4 W AVSEL1 AVSEL0 MVSEL1 MVSEL0 0 1 0 0 RSSI Threshold Register (Address: 1Eh) Bit R/W Bit 7 R W ADC7 RTH7 1 Bit 6 ADC6 RTH6 0 Bit 5 ADC5 RTH5 0 Bit 4 ADC4 RTH4 1 ADC Control Register (Address: 1Fh) Bit Name Reset Bit Name Reset Name Reset Bit Name Reset R/W Bit 7 W RSM1 0 Bit 6 RSM0 1 Bit 5 Bit 4 Bit 3 RADC1 RADC0 FSARS 0 0 1 Bit 2 XADS 0 Bit 2 FMT FMT 0 Bit 2 LHC1 1 Bit 2 ADC2 RTH2 0 Bit 3 MHC 1 Bit 3 ADC3 RTH3 0 Bit 1 FMS FMS 0 Bit 1 LHC0 1 Bit 1 ADC1 RTH1 0 Bit 1 RSS 1 Bit 0 ADCM ADCM 0 Bit 0 AGCE 0 Bit 0 ADC0 RTH0 1 Bit 0 CDM 1 17.1 Temperature Measurement A7125 has built-in thermal sensor. Combined with 8-bits ADC, it can be used to monitor the relative environment temperature. Below is the measurement procedure:
1. 2. 3. 4. 5. Set RSS= 0 (1Fh), FSARS= 0 (1Fh). Enter Standby mode. Set ADCM= 1 (01h). A7125 will enable relative temperature measurement automatically. After measurement done, ADCM is auto clear. User can read digital temperature value from ADC [7:0] (1Eh). 17.2 RSSI Measurement A7125 has built-in 8-bits digital RSSI to detect RF signal strength. After measurement done, RSSI is stored in ADC [7:0]
(1Eh). The more signal power, the larger RSSI value. Below is the measurement procedure:
Nov., 2010, v1.1 82 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Set wanted FRXLO (Refer to chapter 14). Set ADCM=1 (01h), RSS= 1 (1Fh), FSARS= 1 (1Fh, 8MHz ADC clock). Enable MVSEL = [00] (1Dh) and RADC = [10] (1Fh) to do 8-times average RSSI measurement. Set ARSSI= 1 (01h). Send RX Strobe command. Auto RSSI measurement for TX Power:
1. 2. 3. 4. 5. 6. Once entering into RX mode, A7125 executes 8-times average measurement repeatedly. 7. Once A7125 leaves RX mode, user can read digital RSSI value from ADC [7:0] (1Eh) for TX power. Be notice, in step 7, if A7125 is set in direct mode, once the received packet is completed, MCU shall ask A7125 to leave RX mode within 40 us to prevent RSSI inaccuracy. Strobe CMD
(SCS,SCK,SDIO) RX-Strobe RFI Pin GIO1 Pin - WTR
(GPIO1S[3:0]=0000) GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001) MCU Read ADC[7:0] (1Eh) Read 8-bits RSSI value Received Packet T0 T1 T2 T3 T4 T5 T0-T1: Settling Time from PLL to RX mode T2-T3: Receiving Packet T3: A7125 leaves RX mode T4-T5: MCU read RSSI value @ ADC [7:0](1Eh) Figure 17.1 Timing chart of Auto RSSI measurement for TX Power:
Set wanted FRXLO (Refer to chapter 14). Set ADCM=1 (01h), RSS= 1 (1Fh), FSARS= 1 (1Fh, 8MHz ADC clock). Enable MVSEL = [00] (1Dh) and RADC = [10] (1Fh) to do 8-times average RSSI measurement. Set ARSSI= 1 (01h). Send RX Strobe command. Auto RSSI measurement for Background Power:
1. 2. 3. 4. 5. 6. MCU delays min. 140us. 7. 8. Read digital RSSI value from ADC [7:0] (1Eh) to get background power. Send Strobe command to ask A7125 to leave RX mode. Nov., 2010, v1.1 83 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 Strobe CMD
(SCS,SCK,SDIO) RX-Strobe RFI Pin GIO1 Pin - WTR
(GPIO1S[3:0]=0000) GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001) Min. 140 us MCU Read ADC[7:0] (1Eh) No Packet MCU can read 8-bits RSSI value that Is re-calculated every 20 us T0 T1 T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment T1 : Auto RSSI Measurment is done by 8-times average. MCU can read RSSI value from ADC [7:0](1Eh) RSSI measurement Iis re-calculated every 20 us. Figure 17.2 Timing chart of Auto RSSI measurement for Background Power:
17.3 Carrier Detect Base on RSSI measurement, user can extend its application to do carrier detect (CD). If CD is triggered, its output can be set to GIO1 or GIO2 pin to inform MCU the occupied channel. Below is the detection procedure:
Set RTH (1Eh) for RSSI higher threshold by users definition (see below Table 17.2). Set RTL (RTL = RTH RSM) by RSM = [11] (1Fh) (recommended). Set GIO1S = [0010] (0Bh) for GIO1 pin to output CD signal. Follow procedure of auto RSSI measurement. 1. 2. 3. 4. 5. MCU checks GIO1 pin for carrier detect (CD) signal. In step 1, MCU can read RH and RL to calculate and store the RTH value corresponding to desired CD trigger level below. RSSI Range RH [7:0] RL [7:0]
Trigger Level
(dBm) RTH
(Recommended) CD
-58
-64
-70
-76
-82
(3RH - RL) / 2 RH RL
(3RL - RH) / 2
(RH + RL) / 2 Note Formula of digital RSSI values is just approximate for reference. Max (-50 dBm) Min (-100 dBm) Address Address 1Bh 1Ch In step 5, CD=1 if measured RSSI RTH. That means this channel is occupied. CD=0 if measured RSSI RTL. That means this channel is clear. Table 17.2 RTH Recommended Setting Nov., 2010, v1.1 84 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 A7125 has built-in battery detector to check supply voltage (REGI pin). The detect range is 2.0V ~ 2.7V in 8 levels. 18. Battery Detect Relative Control Register Battery Detect Register (Address: 2Ch) Bit Name Reset R/W Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 R W
0
1
0
0
1
1
0 RGS RGV1 RGV0 BVT2 BVT1 BVT0 BD_E Bit 4 BDF QDS 0 BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. Below is the procedure of battery detect for low voltage detection (ex., below 2.1V):
Set A7125 in standby or PLL mode. Set BVT (2Ch) = [001] and enable BD_E (2Ch) = 1. After 5 us, BD_E is auto clear. 1. 2. 3. 4. MCU check BDF (2Ch). If REGI pin > 2.1V, BDF = 1. Else, BDF = 0. Nov., 2010, v1.1 85 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 19. Application Circuit Example Below are AMICCOMs ref. design module, MD7125-A04, circuit example and its PCB layout. GND SCK GIO1 J1 1 3 5 7 REGI SCS SDIO GIO2 2 4 6 8 HEADER 4X2A/2.54 ANT C13 1pF L1 2.7nH C15 1pF L5 2.2nH C8 1pF C1 NC C11 3.9pF C12 3.9pF VDD_A C5 100pF C2 1nF C3 100pF C6 0.1uF C9 2.2uF C4 4.7uF A _ D D V I G E R O K C 2 O G I 1 O G I 0 2 9 1 8 1 7 1 6 1 I G E R O K C 2 O G I 1 O G I 1 2 3 4 5 BP_RSSI BP_BG RFI RFO RFC A _ D D V O C V _ D D V A7125PKG L L P _ D D V U1 GND SDIO VDD_D SCK SCS 15 14 13 12 11 C10 2.2uF SDIO SCK SCS R1 2.7k C16 180pF C14 2.2nF VDD_A C7 0.1uF C19 100pF 1 2 C17 33pF Y1 16MHz C18 27pF L4 1.2nH R2 NC L3 1.5nH P C I X O X A7125PKG 6 7 8 9 0 1 1. 2. A7125 schematic for RF layouts with single ended 50 RF output. C17 and C18 must be matched to the crystals load capacitance, Cload. Please see application note for detail. Nov., 2010, v1.1 86 AMIC Communication Corporation A7125 2.4GHz FSK Transceiver MD7125-A04 which size is 13mm x 20mm with PCB antenna is suitable for small form factor application. MD7125-A04 is based on a design by a double-sided FR-4 board of 0.8mm thickness. All passive components are 0402 size. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. Keep sufficient via holes to connect the top layer ground areas to the bottom layer ground plane. Be notice, IC back side plate shall be well-solder to ground; otherwise, it will impact RF performance. To get a good RF performance, the well designed PCB is necessary. A poor layout can lead to loss of RF performance especially on matching networks as well as VDD bypass capacitors. PCB layout of critical traces shall follow AMICCOMs recommended values and layout placement. Long power supply lines on the PCB should be avoided. Keep GND via holes as close as possible to A7125s GND pad and IC back side plate (GND). Be Notice, 1. IC Back side plate shall be well-solder to ground (U1 area) for good RF performance. Need at least 9 GND via holes at U1 area 2. Nov., 2010, v1.1 87 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 20. Abbreviations ADC AIF FC AGC BER BW CD CHSP CRC DC FEC FIFO FSK ID IF ISM LO MCU PFD PLL POR RX RXLO RSSI SPI SYCK TX TXLO VCO XOSC XREF XTAL Analog to Digital Converter Auto IF Frequency Compensation Automatic Gain Control Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Transmitter Transmitter Radio Frequency Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal 21. Ordering Information Part No. Package Units Per Reel / Tray A71X25AQFI/Q QFN20L, Pb Free, Tape & Reel, -4085 A71X25AQFI A71X25AH QFN20L, Pb Free, Tray, -4085 Die form, -4085 3K 490EA 250EA Nov., 2010, v1.1 88 AMIC Communication Corporation 2.4GHz FSK Transceiver 22. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions unit: inches/mm A7125 TOP VIEW BOTTOM VIEW D 0.25 C D2 15 11 11 15 10 6 2 E e 10 6 L 16 20 1 5 5 e 1 b 0.10 M C A B 16 20 E C 5 2
. 0 1 A
0.10 C A 3 A y C Seating Plane C Symbol Dimensions in inches Dimensions in mm 0.008 REF 0.203 REF Max 0.032 0.002 0.012 0.161 0.083 0.161 0.083 Min 0.70 0.00 0.18 3.90 1.90 3.90 1.90 Min 0.028 0.000 0.007 0.154 0.075 0.154 0.075 0.012 Nom 0.030 0.001 0.010 0.158 0.079 0.158 0.079 0.016 0.003 A A1 A3 B D D2 E E2 e L Y Max 0.80 0.05 0.30 4.10 2.10 4.10 2.10 0.50 Nom 0.75 0.02 0.25 4.00 2.00 4.00 2.00 0.40 0.08 0.020 BSC 0.50 BSC 0.020 0.30 Nov., 2010, v1.1 89 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 23. Top Marking Information A71X25AQFI
: A71X25AQFI Part No. Pin Count : 20 Package Type : QFN Dimension : 4*4 mm Mark Method : Laser Mark Character Type : Arial Nov., 2010, v1.1 90 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 24. Reflow Profile Nov., 2010, v1.1 91 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 25. Tape Reel Information Cover / Carrier Tape Dimension D0 P1 P0 E D1 B0 F W NO COMPONENT TRAILER LENGTH 40mil. 11 EA IC TYPE 20 QFN 4X4 24 QFN 4X4 32 QFN 5X5 48 QFN 7X7 DFN-10 20 SSOP 24 SSOP 28 SSOP (150mil) A0 P NO COMPONENT LEADER LENGTH 500min P 8 8 8 12 4 12 12 8 A0 4.35 4.4 5.25 7.25 3.2 8.2 8.2 6 B0 4.35 4.4 5.25 7.25 3.2 7.5 8.8 10 TYPE 20 QFN (4X4) 24 QFN (4X4) 32 QFN (5X5) 48 QFN (7X7) DFN-10 20 SSOP 24 SSOP 28 SSOP (150mil) 60cm4cm P0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 K0 1.1 1.4 1.1 1.1 0.75 2.5 2.1 2.5 P1 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 K1
D0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 t 0.3 0.3 0.3 0.3 0.25 0.3 0.3 0.3 D1 1.5 1.5 1.5 1.5
1.5 1.5 1.5 E 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 COVER TAPE WIDTH F 5.5 5.5 5.5 7.5 1.9 7.5 7.5 7.5 9.2 9.2 9.2 13.3 8 13.3 13.3 12.5 W 12 12 12 16 8 16 16 16 Unit : mm Nov., 2010, v1.1 92 AMIC Communication Corporation REEL DIMENSIONS UNIT IN mm 20 QFN(4X4) 24 QFN(4X4) 32 QFN(5X5) DFN-10 48 QFN(7X7) 2.4GHz FSK Transceiver A7125 TYPE G N T M D K L R 12.8+0.6/-0.4 18.2(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 16.8+0.6/-0.4 22.2(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 28 SSOP (150mil) 20.4+0.6/-0.4 25(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 20 SSOP 24 SSOP 16.4+2.0/-0.0 22.4(MAX) 1.750.25 13.0+0.2/-0.2 1.90.4 100 REF 100 REF 100 REF 100 REF 330 0.00/-1.0 20.2 330 0.00/-1.0 20.2 330 0.00/-1.0 20.2 330 0.00/-1.0 20.2 L R D N K M T G Nov., 2010, v1.1 93 AMIC Communication Corporation 2.4GHz FSK Transceiver A7125 26. Product Status Data Sheet Identification Objective Product Status Planned or Under Development Preliminary Engineering Samples and First Production No Identification Noted Full Production Obsolete Not In Production Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves to make changes at any time without notice in order to improve design and supply the best possible product. the right This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. RF ICs AMICCOM Headquarter A3, 1F, No.1, Li-Hsin 1st Rd., Hsinchu Science Park, Hsinchu, Taiwan 30078 Tel: 886-3-5785818 Taipei Office 8F, No.106, Zhouzi St., NeiHu Dist., Taipei, Taiwan 11493 Tel: 886-2-26275818 Web Site http://www.amiccom.com.tw Nov., 2010, v1.1 94 AMIC Communication Corporation
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2015-08-24 | 2404 ~ 2479 | DXX - Part 15 Low Power Communication Device Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2015-08-24
|
||||
1 | Applicant's complete, legal business name |
Alco Electronics Ltd
|
||||
1 | FCC Registration Number (FRN) |
0021262878
|
||||
1 | Physical Address |
11/F, Metropole Square, 2 On Yiu Street, Sha Tin, New Territories
|
||||
1 |
11/F, Metropole Square
|
|||||
1 |
Hong Kong
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
T******@intertek.com
|
||||
1 | TCB Scope |
A2: Low Power Transmitters (except Spread Spectrum) and radar detectors operating above 1 GHz
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
A2H
|
||||
1 | Equipment Product Code |
SBT1739-SWE
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
P****** S********
|
||||
1 | Title |
Secretary, Engineering Dept.
|
||||
1 | Telephone Number |
852 2********
|
||||
1 | Fax Number |
852 2********
|
||||
1 |
p******@alco.com.hk
|
|||||
app s | Technical Contact | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
T****** C******
|
||||
1 | Physical Address |
2/F., Garment Centre
|
||||
1 |
Kowloon
|
|||||
1 |
Hong Kong
|
|||||
1 | Telephone Number |
(852)********
|
||||
1 | Fax Number |
(852)********
|
||||
1 |
t******@intertek.com
|
|||||
app s | Non Technical Contact | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
T******** C****
|
||||
1 | Physical Address |
2/F., Garment Centre
|
||||
1 |
Kowloon
|
|||||
1 |
Hong Kong
|
|||||
1 | Telephone Number |
(852)********
|
||||
1 | Fax Number |
(852)********
|
||||
1 |
t******@intertek.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DXX - Part 15 Low Power Communication Device Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Subwoofer | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Does not apply | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
J******** H****
|
||||
1 | Telephone Number |
85221********
|
||||
1 | Fax Number |
85278********
|
||||
1 |
j******@intertek.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2404.00000000 | 2479.00000000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC