UNIVERSAL ISM BAND FSK TRANSCEIVER MODULE VZ38915AZ VZ38915AZ General Introduction VZ38915AZ is a low costing ISM band transceiver module implemented with unique PLL. The SPI interface is used to communicate with microcontroller for parameter setting. Features:
Low costing, high performance and price ratio Tuning free during production PLL and zero IF technology Fast PLL lock time Automatic antenna tuning Analog and digital signal strength indicator (ARSSI/DRSSI) Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX synchron pattern recognition SPI compatible serial control interface Clock and reset signal output for external MCU use 16 bit RX Data FIFO Two 8 bit TX data registers Standard 10 MHz crystal reference Wakeup timer 3.3V power supply Low power consumption Standby current less than 0.3uA This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible the user's authority to operate the equipment. for compliance could void Pin Definition SMD definition nINT/VDI VDD SDI SCK nSEL SDO nIRQ FSK/DATA/nFFS DI/DO/DI Type DI/ DO S DI DI DI DO DO Function Interrupt input (active low)/Valid data indicator Positive power supply SPI data input SPI clock input Chip select (active low) Serial data output with bus hold Interrupts request outputactive low Transmit FSK data input/ Received data output (FIFO not used)/ FIFO select DCLK/CFIL/FFIT DO/AIO/DO Clock output (no FIFO )/ external filter capacitor(analog mode)/ FIFO CLK nRES GND DO DIO S interrupts(active high)when FIFO level set to 1, FIFO empty interruption can be achieved Clock output for external microcontroller Reset outputactive low Power ground Electrical Parameter Maximumnot at working mode symbol Vdd Vin Iin ESD Tst Tld parameter Positive power supply All pin input level Input current except power Human body model Storage temperature Soldering temperature(10s) minimum
-0.5
-0.5
-25
-55 maximum 6.0 Vdd+0.5 25 1000 125 260 Unit V V mA V Recommended working range symbol Vdd Top parameter Positive power supply Working temperature minimum 3.3*0.9
-40 maximum 3.3*1.1 85 Unit V DC characteristic symbol parameter Idd_TX_0 Supply current
(TX mode, Pout = 0dBm) Idd_TX_PMAX Supply current Idd_RX
(TX mode, Pout = Pmax) Supply current
(RX mode) Idle current Sleep mode current Low level input High level input Leakage current Leakage current Low level output High level output Ix Ipd Vil Vih Iil Iih Vol Voh AC characteristic symbol fref BW parameter PLL frequency Receiver bandwidth tlock PLL lock time tst, P BR BRA Pmin PLL startup time Data rate Data rate sensitivity AFCrange AFC working range RSA RSR CARSSI RSSI accuracy RSSI range ARSSI filter minimum typical maximum Unit mA 19 17 Remark 915MHz band 915MHz band Crystal oscillator on All blocks off Vil=0V Vih=Vdd, Vdd=5.4V Iol=2mA Ioh=-2mA 24 13 0.62 0.3 0.7*Vdd
-1
-1 Vdd-0.4 26 15 1.2 0.3*Vdd 1 1 0.4 remark mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 After 10MHz step hopping, frequency error <10 kHz With a running crystal oscillator With internal digital demodulator With external RC filter BER 10-3, BW=134KHz,BR=1.2kbps dfFSK : FSK deviation in the received signal min 9 60 120 180 240 300 360 0.6 typical max 11 10 75 67 150 134 225 200 300 270 350 375 400 450 30 300 115.2 256
-96 200
-102 0.8*
dfFSK 5 46 1 mA mA mA uA V V uA uA V V Unit MHz KHz us us kbps kbps dBm dB dB nF RSSTEP RSSI programmable step RSRESP DRSSI response time RSSI output high after valid , CARRSI=5nF 6 500 dB us AC characteristic(Transmitter) symbol parameter Pmax_50 Max. output power delivered to remark 915MHZ band min typical max Unit 5 dbm 50Ohm load over a suitable matching network Pmax_ant Max. EIRP with suitable selected PCB antenna. Typical output power Pout Co Qo Lout Output capacitance
(set by the automatic antenna tuning circuit) Quality factor of the output capacitance Output phase noise BRTX FSK bit rate BRATX FSK bit rate dffsk FSK frequency deviation 915 MHz bands Selectable in 3 dB steps In low bands In high bands 7 Pmax-21 2 2.1 2.6 2.7 In low bands In high bands 100 kHz from carrier 1 MHz from carrier Via internal TX data register TX data connected to the FSK input Programmable in 15 kHz steps 13 8 15 15 10 dbm Pmax dbm pf 3.2 3.3 17 12
-80
-103 172 dbc/HZ kbps 256 kbps 240 kHZ AC characteristic(Turn-on/Turnaround timings) symbol Tst remark Crystal ESR < 100 parameter Crystal oscillator startup time Transmitter time Receiver turn-on time turn-on Ttx_XTAL_ON Trx_XTAL_ON Ttx_rx_SYNT_ON Transmitter Receiver turnover time Trx_tx_SYNT_ON Receiver Transmitter turnover time Cxl Crystal load capacitance off, off, and Synthesizer crystal oscillator on with 10 MHz step Synthesizer crystal oscillator on with 10 MHz step Synthesizer crystal oscillator on during TX/RX Synthesizer oscillator on during RX/TX Programmable in 0.5 pF steps, tolerance+/- 10%
crystal and min typical max Unit 1 ms 5 250 250 150 150 us us us us 8.5 16 pf tPOR tPBt Cin, D tr, f Internal POR timeout Wake-up timer clock period Digital input apacitance Digital output rise/fall time After Vdd has reached 90% of final value Calibrated every 30 seconds 15pF pure capacitive load 100 ms 0.96 1.05 ms 2 10 pf ns CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-
bit command). Bits having no influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
The TX register is ready to receive the next byte (RGIT) The FIFO has received the preprogrammed amount of bits (FFIT) Power-on reset (POR) FIFO overflow (FFOV) / TX register underrun (RGUR) Wake-up timer timeout (WKUP) Negative pulse on the interrupt input pin nINT (EXT) Supply voltage below the preprogrammed value is detected (LBD) FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out. Timing Specification Symbol tC tC tS tS tS tD tD tO Parameter Clock high time Clock low time Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time Timing Diagram Minimum value [ns]
25 25 10 10 25 5 5 10 tSS tCH tCL tDS tDH tOD tSHI tSH BIT 15 BIT 14 BIT 13 BIT 8 BIT 7 BIT 1 BIT 0 nSEL SCK SDI SDO FFIT FFOV CRL AT S OFFS(0) FIFO OUT Control Commands h ld mode clock output enable Receiver Control Command FIFO and Reset Mode Command Control Command Configuration Setting Command Power Management Command 1 2 Related Parameters/Functions Frequency band, crystal oscillator load capacitance, RX FIFO and TX register enable Receiver/Transmitter change, synthesizer, crystal oscillator, PA, wake-up timer, Frequency of the local oscillator/carrier signal Bit rate Function of pin 16, Valid Data Indicator, baseband bandwidth, LNA gain, digital RSSI th Data filter type, clock recovery parameters Data FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable, POR sensitivity Synchron pattern RX FIFO read AFC parameters 3 Frequency Setting Command 4 Data Rate Command 5 6 Data Filter Command 7 8 Synchron Pattern Command 9 Receiver FIFO Read Command 10 AFC Command 11 TX Configuration Control Command Modulation parameters, output power 12 13 Transmitter Register Write 14 Wake-Up Timer Command 15 Low Duty-Cycle Command Low Battery Detector and Microcontroller Clock Divider Command CLK out buffer speed, low power mode of the crystal oscillator, dithering, PLL bandwidth TX data register write Wake-up time period Enable and set low duty-cycle mode LBD voltage and microcontroller clock division ratio Status bit readout 17 Status Read Command PLL Setting Command 16 Related control bits el, ef, b1 to b0, x3 to x0 er, ebb, et, es, ex, eb, ew, dc f11 to f0 cs, r6 to r0 p16, d1 to d0, i2 to i0, g1 to g0, r2 al, ml, s, f2 to f0 f3 to f0, sp, ff, al, dr b7 to b0 a1 to a0, rl1 to rl0, st, fi, oe, en mp, m3 to m0, p2 to p0 ob1 to ob0, ddit, ddy, bw0 t7 to t0 r4 to r0, m7 to m0 d6 to d0, en d2 to d0, v3 to v0 In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on. Description of the Control Commands 1. Configuration Setting Command Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 el 6 ef 5 b1 4 b0 3 x3 2 x2 1 x1 0 x0 POR 8008h Bit el enables the internal data register. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. b1 b0 0 0 1 0 1 0 1 1 Reserved 433 868 915 Frequency Band [MHz]
Crystal Load Capacitance [pF]
8.5 9.0 9.5 10.0 x3 0 0 0 0 x2 0 0 0 0 x1 0 0 1 1 x0 0 1 0 1 1 1 1 1 1 1 0 1 15.5 16.0 2. Power Management Command IA4421 Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 er 6 ebb 5 et 4 es 3 ex 2 eb 1 ew 0 dc POR 8208h Bit er ebb et es ex eb ew dc Related blocks RF front end, baseband, synthesizer, oscillator Function of the control bit Enables the whole receiver chain The receiver baseband circuit can be separately switched Baseband Switches on the PLL, the power amplifier, and starts the transmission (If TX register is enabled) Turns on the synthesizer Turns on the crystal oscillator Enables the low battery detector Enables the wake-up timer Disables the clock output (pin 8) Power amplifier, synthesizer, oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time. Logic connections between power control bits:
enable power amplifier start TX Edge detector clear TX latch
(If TX latch is used) enable RF synthesizer
(osc.must be on) enable RF front end enable baseband circuits
(synt. must be on) enable oscillator et es er ebb ex Note:
If both et and er bits are set the chip goes to receive mode. FSK / nFFSEL input are equipped with internal pull-up resistor. To achieve minimum current consumption do not pull this input to logic low in sleep mode. 3. Frequency Setting Command Bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR A680h The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept. The synthesizer center frequency f be calculated as:
f = 10 * C1 * (C2 + F/4000) [MHz]
can 0 0 The constants C1 and C2 are determined by the selected band as:
Band [MHz]
433 868 915 C1 1 2 3 C2 43 43 30 4. Data Rate Command Bit 14 1 13 0 15 1 12 0 11 0 10 1 9 1 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C623h The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
In the receiver set R according to the next function:
R= (10000 / 29 / (1+cs*7) / BR) 1, where BR is the expected bit rate in kbps. 5. Receiver Control Command Bit 15 1 14 13 12 11 0 0 0 1 9 10 8 p16 d1 d0 7 i2 6 i1 5 i0 4 g1 3 g0 2 r2 1 r1 0 r0 POR 9080h Bit 10 (p16): pin16 function select p16 0 1 Function of pin 16 Interrupt VDI Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
d1 d0 0 0 1 0 1 0 1 1 Response Fas Medium Slo Always on CR_LOCK DRSSI DQD DRSSI DQD CR_LOCK VDI MUX SEL0 SEL1 IN0 IN1 IN2 IN3 CLR Y d0 d1 FAST MEDIUM SLOW LOGIC HIGH er *
DQD SET Q R/S FF CLR Note:
* For details see the Power Management Command Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 i0 0 1 0 1 0 1 0 1 BW [kHz]
reserved 400 340 270 200 134 67 reserved Bits 4-3 (g1 to g0): LNA gain select:
g1 g0 0 0 1 0 0 1 1 1 relative to maximum [dB]
0
-6
-14
-20 Bits 2-0 (r2 to r0): RSSI detector threshold:
r2 0 0 0 0 1 1 1 1 r1 0 0 1 1 0 0 1 1 r0 0 1 0 1 0 1 0 1 RSSIsetth [dBm]
-103
-97
-91
-85
-79
-73 Reserved Reserved The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSIth=RSSIsetth+GLNA 6. Data Filter Command Bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 al 6 ml 5 1 4 s 3 1 2 f2 1 f1 0 f0 POR C22Ch Bit 7 (al): Clock recovery (CR) auto lock control, if set. CR will start in fast mode, then after locking it will automatically switch to slow mode. Bit 6 (ml): Clock recovery lock control 1: fast mode, fast attack and fast release (4 to 8 bit preamble (1010...) is recommended) 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended) Using the slow mode requires more accurate bit timing (see Data Rate Command). Bits 4 (s): Select the type of the data filter:
s 0 1 Filter Type Digital filter Analog RC filter Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Note: Bit rate can not exceed 115 kpbs in this mode. Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. The table shows the optimal filter capacitor values for different data rates 1.2 kbps 12 nF 2.4 kbps 8.2 nF 4.8 kbps 6.8 nF 9.6 kbps 3.3 nF 19.2 kbps 1.5 nF 38.4 kbps 680 pF 57.6 kbps 115.2 kbps 256 kbps 270 pF 100 pF 150 pF Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used. Bits 2-0 (f2 to f0): DQD threshold parameter. Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where the bitrate is close to the deviation. At higher deviation/bitrate settings, a higher threshold parameter can report "good signal quality" as well. 7. FIFO and Reset Mode Command Bit 13 0 14 1 15 1 POR CA80h Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level. Bit 3 (sp): Select the length of the synchron pattern:
12 0 11 1 10 0 0 dr 3 sp 9 1 7 f3 6 f2 5 f1 4 f0 2 al 1 ff 8 0 sp 0 1 Byte1 2Dh Not used Byte0 (POR) D4h D4h Synchron Pattern (Byte1+Byte0) 2DD4h D4h Note: Byte0 can be programmed by the Synchron Pattern Command. Bit 2 (al): Set the input of the FIFO fill start condition:
al 0 1 Synchron pattern Always fill Latch nRES al*
FIFO_OVERFL FIFO_Logic
(simplified) FIFO_WRITE _EN nFIFO_RESET FIFO_IT
. FIFO_OVERFL Note:
For details see the
* Output and FIFO mode Command,
** Configuration Setting Command,
*** Power Management Command Synchron Pattern Detector EN PIN 6 I/O port DIRECTION CR_LOCK DQD ff*
ef**
er***
ef**
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the highly sensitive RESET mode. Reset mode Sensitive reset dr=0 dr=1 Non-sensitive reset Reset triggered when Vdd below 1.5V Vdd glitch greater than 500mV Vdd below 0.25V Note: To restart the synchron pattern recognition, bit 1 should be cleared and set. 8. Synchron Pattern Command Bit 15 1 14 1 13 0 12 0 11 1 10 1 9 1 8 0 7 b7 6 b6 5 b5 4 b4 3 b3 2 b2 1 b1 0 b0 POR CED4h The Byte0 used for synchron pattern detection can be reprogrammed by B <b7:b0>. 9. Receiver FIFO Read Command Bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POR B000h With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command. Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/fref . 10. AFC Command Bit 15 1 14 1 13 0 12 0 11 0 10 1 9 0 8 0 7 a1 6 a0 5 rl1 4 rl0 3 st 2 fi 1 oe 0 en POR C4F7h Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1 0 0 1 1 a0 0 1 0 1 Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving (VDI=high) Keep the foffset value independently from the state of the VDI signal Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
rl1 0 0 1 1 rl0 0 1 0 1 Max deviation No restriction
+15 fres to -16 fres
+7 fres to -8 fres
+3 fres to -4 fres fres:
433 MHz bands: 2.5 kHz 868 MHz band: 5 kHz 915 MHz band: 7.5 kHz Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block. Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice as long, but the measurement uncertainty is about half. Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit. There are three operation modes, examples from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX maximum distance can be achieved. Possible application:
In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an interferer. 2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern easier to receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the corrected frequency settings. 2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility of reducing it. In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies. 3, (a1=1, a0=1) Its the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. 11. TX Configuration Control Command Bit 15 1 14 0 13 0 12 1 11 1 10 0 9 0 7 8 4 mp m3 m2 m1 m0 6 5 3 0 2 p2 1 p1 0 p0 POR 9800h Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
The resulting output frequency can be calculated as:
Pout where:
fout = f0 + (-
1) SIG N
* (M + 1) * (15 kHz) f0 is the channel center frequency (see the Frequency Setting Command) M is the four bit binary number <m3 :
m0>
SIGN = (mp) XOR FSK Bits 2-0 (p2 to p0): Output power:
df fsk mp=0 and FSK=0 or df fsk f 0 f out mp=0 and FSK=1 or p2 p1 p0 0 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 0 0 1 1 0 0 1 1 Relative Output Power [dB]
0
-2.5
-5
-7.5
-10
-12.5
-15
-17.5 mp=1 and FSK=1 mp=1 and FSK=0 Note:
FSK represents the value of the actual data bit. The output power given in the table is relative to the maximum available power, which depends on impedance.
(See: Antenna Application Note: IA ISM-AN1) the actual antenna 12. PLL Setting Command Bit 15 1 14 1 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 ob1 5 ob0 4 1 3 ddy 2 ddit 1 1 0 bw0 POR CC67h Note: POR default setting of the register carefully selected to cover almost all typical applications. Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control. ob1 0 0 1 ob0 0 1 X Selected uC CLK frequency 5 or 10 MHz (recommended) 3.3 MHz 2.5 MHz or less Bit 3 (ddy):
Bit 2 (ddit):
Bit 0 (bw0):
bw0 0 1 Switches on the delay in the phase detector when this bit is set. When set, disables the dithering in the PLL loop. PLL bandwidth can be set for optimal TX RF performance. Max bit rate [kbps]
86.2 256 Phase noise at 1MHz offset [dBc/Hz]
-107
-102 13. Transmitter Register Write Command Bit 15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 0 7 t7 6 t6 5 t5 4 t4 3 t3 2 t2 1 t1 0 t0 POR B8AAh With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting Command. Multiple Byte Write with Transmit Register Write Command:
Note: Alternately the transmit register can be directly accessed by nFFSEL (pin6). 14. Wake-Up Timer Command Bit 15 1 14 1 13 1 12 r4 11 r3 10 r2 9 r1 7 8 0 r0 m7 m6 m5 m4 m3 m2 m1 m0 6 5 4 3 2 1 The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
= 1.03 * M * 2R + 0.5 [ms]
T Note:
For continual operation the ew bit should be cleared and set at the end of every cycle. For future compatibility, use R in a range of 0 and 29. wake-up POR E196h 15. Low Duty-Cycle Command Bit 15 1 14 1 13 0 12 0 11 1 10 0 9 0 8 0 7 d6 6 d5 5 d4 4 d3 3 d2 2 d1 1 d0 0 en POR C80Eh With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode. The time cycle is determined by the Wake-Up Timer Command. The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.) Duty-Cycle= (D * 2 +1) / M *100%
The on-cycle is automatically extended while DQD indicates good received signal condition (FSK transmission is detected in the frequency range determined by Frequency Setting Command plus and minus the baseband filter bandwidth determined by the Receiver Control Command). Application Proposal For LPDM (Low Power Duty-Cycle Mode) Receivers:
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt is not generated in this mode. Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command. 16. Low Battery Detector and Microcontroller Clock Divider Command Bit 15 1 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 d2 6 d1 5 d0 4 0 3 v3 2 v2 1 v1 0 v0 POR C000h The 4 bit parameter (v3 to v0) represents the value V, which defines the threshold voltage V V = 2.25 + V * 0.1 [V]
Clock divider configuration:
lb of the detector:
lb d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [MHz]
1 1.25 1.66 2 2.5 3.33 5 10 The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command. 17. Status Read Command The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits will be clocked out on the SDO pin as follows:
Status Register Read Sequence with FIFO Read Example:
RGIT FFIT POR RGUR FFOV WKUP EXT LBD FFEM ATS RSSI DQD CRL ATGL OFFS(6) OFFS(3) -OFFS(0) TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command) The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the FIFO read methods) Power-on reset (Cleared after Status Read Command) TX register under run, register over write (Cleared after Status Read Command) RX FIFO overflow (Cleared after Status Read Command) Wake-up timer overflow (Cleared after Status Read Command) Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command) Low battery detect, the power supply voltage is below the pre-programmed limit FIFO is empty Antenna tuning circuit detected strong enough RF signal The strength of the incoming signal is above the pre-programmed limit Data quality detector output Clock recovery locked Toggling in each AFC cycle MSB of the measured frequency offset (sign of the offset value) Offset value to be added to the value of the frequency control parameter (Four LSB bits) Note: In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command
(bit 0). TX REGISTER BUFFERED DATA TRANSMISSION In this operating mode (enabled by bit el, in the Configuration Control Command) the TX data is clocked into one of the two 8-
bit data registers. The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. TX register simplified block diagram (before transmit) TX register simplified block diagram (during transmit) Typical TX register usage Note: The content of the data registers are initialized by clearing bit et. RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. Interrupt Controlled Mode:
The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. Polling Mode:
When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available to read out the content of the FIFO. FIFO Read Example with FFIT Polling nSEL SCK nFFS SDO FFIT 0 1 2 3 4 FIFO read out FIFO OUT FO+1 FO+2 FO+3 FO+4 Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50 % the shorter period of the clock pulse should be at least 2/fref .