FCC ID: WAP829I10 AIROC Bluetooth LE Module

CYW20829B0-P4TAI100, CYW20829B0-P4EPI100, CYW20829B0S-P4TAI100, CYW20829B0S-P4EPI100 A I R O C B l u etooth L E m o d u l e General description The CYW20829B0-P4xxI100 is a fully integrated Bluetooth LE wireless module. The CYW20829B0-P4xxI100 includes an onboard crystal oscillator, passive components, flash memory, and the CYW20829 silicon device. Refer to the CYW20829 datasheet for additional details on the capabilities of the silicon device used in this module. The CYW20829B0-P4xxI100 supports high-performance analog-to-digital conversion audio input, I2S/PCM, CAN, LIN for automotive use cases and other standard communication and timing peripherals. The CYW20829B0-P4xxI100 includes a royalty-free Bluetooth stack compatible with Bluetooth 5.4 core spec in a 14.5 19 1.95 mm package. The CYW20829B0-P4xxI100 includes 1 MB of onboard serial flash memory and is designed for standalone operation. The CYW20829B0-P4xxI100 uses an integrated power amplifier to achieve Class I or Class II output power capability. The CYW20829B0-P4xxI100 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost-optimized Bluetooth wireless connectivity. The CYW20829B0-P4xxI100 is offered in two certified versions CYW20829B0-P4TAI100, and CYW20829B0-P4EPI100. The CYW20829B0-P4TAI100 includes an integrated trace antenna. The CYW20829B0-P4EPI100 supports an external antenna through a RF solder pad output. Module descri pti on Module size: 14.5 19 1.95 mm Bluetooth 5.4 core spec qualified module

- QDID: TBD

- Declaration ID: TBD Certified to FCC, ISED, MIC, and CE regulations Castelated solder pad connections for ease-of-use 1-MB on-module serial flash memory Up to 26 GPIOs Temperature range: 30C to +85C 96-MHz Arm Cortex-M33 CPU with single-cycle multiply and memory protection unit (MPU) Maximum TX output power

- Programmable TX power: up to 11 dBm Bluetooth LE connection range of up to 500 meters at 10 dBm[1]

RX sensitivity:

- LE-1 Mbps: 98 dBm

- LE-2 Mbps: 95 dBm

- Coded PHY 500 kbps (LE-LR): 101 dBm

- Coded PHY 125 kbps (LE-LR): 106 dBm Note 1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +10.0 dBm. Actual range will vary based on end product design, environment, receive sensitivity, and transmit output power of the central device. Datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document page 1 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Power consumption Powe r consumpt ion Bluetooth LE current consumption

- RX current: 5.6 mA @ LE 1 Mbps

- TX current: 5.2 mA @ 0 dBm

- Deep Sleep mode current with 64 KB SRAM retention: 4.5 A

- HIDOFF (Deep Sleep): 0.5 A Functio nal capabilities Flexible clocking options

- 8-MHz internal main oscillator (IMO) with 2% accuracy

- Ultra-low-power 32-kHz internal low-speed oscillator (ILO)

- Two oscillators: High-frequency (24-MHz) for radio PLL and low-frequency (32-kHz watch crystal) for LPO

- 48-MHz low power IHO (internal oscillator)

- Frequency-locked loop (FLL) for multiplying IMO frequency

- Integer and fractional peripheral clock dividers Quad SPI (QSPI)/serial memory interface (SMIF)

- eXecute-In-Place (XIP) from external quad SPI flash

- On-the-fly encryption and decryption

- Support for DDR

- Supports single, dual, and quad interfaces with throughput up to 384-Mbps Serial Communication

- Three run-time configurable Serial Communication Blocks (SCBs) First SCB: Configurable as SPI or I2C Second SCB: Configurable as SPI or UART Third SCB: Configurable as I2C or UART Audio subsystem

- Two pulse density modulation (PDM) channels and one I2 S channel with time division multiplexed (TDM) mode Timing and pulse-width modulation

- Seven 16-bit and two 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks, for MCU. Multiple PWMs needed for color LEDs.

- PWM supports center-aligned, edge, and pseudo-random modes ADC and MIC

- Sigma-delta switched cap ADC for audio and DC measurements Up to 32 programmable GPIOs

- One I/O port (8 I/Os) enables Boolean operations on GPIO pins; available during system Deep Sleep

- Programmable drive modes, strengths, and slew rates

- Two overvoltage-tolerant (OVT) pins

- Up to six, used for SMIF Datasheet 2 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Benefits Security built into platform architecture

- ROM-based root of trust via uninterruptible Secure Boot

- Step-wise authentication of execution images

- Secure execution of code in execute-only mode for protected routines

- All debug and test ingress paths can be disabled

- Up to four protection contexts (One available for customer code)

- Secure debug support via authenticated debug token

- Encrypted image support for external SMIF memory Cryptography hardware

- Hardware Acceleration for symmetric cryptographic methods and hash functions

- True Random Number Generation (TRNG) function Benefits CYW20829B0-P4xxI100 provides all necessary components required to operate Bluetooth LE communication standards. Proven ready-to-use hardware design Cost optimized for applications without space constraints Nonvolatile memory for self-sufficient operation and over-the-air updates Bluetooth SIG listed with QDID and declaration ID Fully certified module eliminates the time needed for design, development, and certification processes ModusToolbox provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application Datasheet 3 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module More information More information Infineon provides a wealth of data at www.infineon.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References Overview: AIROC Bluetooth LE & Bluetooth portfolio, Module portfolio CYW20829 Bluetooth silicon datasheet Development kits:

- CYW920829B0M2P4TAI100-EVK, CYW20829B0-P4TAI100 evaluation board

- CYW920829B0M2P4EPI100-EVK, CYW20829B0-P4EPI100 evaluation board Test and debug tools:

- CYSmart, Bluetooth LE test and debug tool (Windows)

- CYSmart Mobile, Bluetooth LE test and debug tool (Android/iOS Mobile App) Knowledge base article

- KBA97095 - EZ-Bluetooth LE module placement

- KBA213976 - FAQ for Bluetooth LE and regulatory certifications with EZ-BLE modules

- KBA210802 - Queries on Bluetooth LE qualification and declaration processes

- KBA218122 - 3D Model Files for EZ-BLE/EZ-BT modules Developmen t envi ronments ModusToolbox software is a modern, extensible development environment supporting a wide range of Infineon microcontroller devices. It provides a flexible set of tools and a diverse, high-quality collection of application-focused software. These include configuration tools, low-level drivers, libraries, and operating system support, most of which are compatible with Linux, macOS, and Windows-hosted environments. ModusToolbox software does not include proprietary tools or custom build environments. This means you choose your compiler, your IDE, your RTOS, and your ecosystem without compromising usability or access to our industry leading CAPSENSE, AIROC, Bluetooth, Wi-Fi, security, and low-power features. Technical support Infineon community: Whether you are a customer, partner, or a developer interested in the latest innovations, the developer community offers you a place to learn, share, and engage with both Infineon experts and other embedded engineers around the world. Visit our support page and contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Datasheet 4 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Table of contents Table of contents General description ...........................................................................................................................1 Module description............................................................................................................................1 Power consumption...........................................................................................................................2 Functional capabilities.......................................................................................................................2 Benefits............................................................................................................................................3 More information ..............................................................................................................................4 References........................................................................................................................................4 Development environments ...............................................................................................................4 Technical support..............................................................................................................................4 Table of contents ...............................................................................................................................5 1 Overview .......................................................................................................................................7 1.1 Functional block diagram.......................................................................................................................................7 1.2 Module description .................................................................................................................................................7 1.2.1 Module dimensions and drawing........................................................................................................................7 2 Pad connection interface.................................................................................................................9 3 Recommended host PCB layout......................................................................................................11 4 Module connections ......................................................................................................................12 5 Connections and optional external components..............................................................................14 5.1 Power connections (VBAT) ...................................................................................................................................14 5.1.1 Considerations and optional components for Brown Out (BO) conditions....................................................14 5.2 External reset (XRES) ............................................................................................................................................15 5.3 Critical components list........................................................................................................................................17 5.4 Antenna design .....................................................................................................................................................17 6 Functional description ..................................................................................................................18 6.1 CPU and memory subsystem ...............................................................................................................................18 6.1.1 CPU .....................................................................................................................................................................19 6.1.2 Interrupts............................................................................................................................................................19 6.1.3 Datawire .............................................................................................................................................................19 6.1.4 Cryptography accelerator (Cryptolite)..............................................................................................................20 6.1.5 Protection units .................................................................................................................................................20 6.1.6 AES-128...............................................................................................................................................................20 6.1.7 Vector unit (VU) ..................................................................................................................................................20 6.1.8 Controller area network flexible data-rate (CAN FD) .......................................................................................20 6.1.9 Local interconnect network (LIN) .....................................................................................................................21 6.1.10 Real time clock (RTC) .......................................................................................................................................21 6.1.11 Memory.............................................................................................................................................................21 6.1.12 Boot code .........................................................................................................................................................21 6.1.13 Memory map ....................................................................................................................................................22 7 System resources..........................................................................................................................23 7.1 Power system........................................................................................................................................................23 7.1.1 Power modes .....................................................................................................................................................23 7.1.2 CYW20829 clock system.....................................................................................................................................24 7.1.3 Internal main oscillator (IMO) ...........................................................................................................................25 7.1.4 Internal low-speed oscillator (ILO) ...................................................................................................................25 7.1.5 External crystal oscillators (ECO) ......................................................................................................................26 7.1.6 Watchdog timers (WDT, MCWDT) ......................................................................................................................26 7.1.7 Clock dividers.....................................................................................................................................................26 7.1.8 Trigger routing ...................................................................................................................................................26 7.1.9 Reset ...................................................................................................................................................................27 7.2 Bluetooth LE radio and subsystem ....................................................................................................................28 7.3 Programmable analog-to-digital converter (ADC) ..............................................................................................28 Datasheet 5 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Table of contents 7.3.1 Sigma delta ADC.................................................................................................................................................28 7.4 Programmable digital...........................................................................................................................................28 7.5 Fixed-function digital............................................................................................................................................29 7.5.1 Timer/counter/pulse-width modulator (TCPWM) block..................................................................................29 7.5.2 Serial communication blocks (SCB)..................................................................................................................30 7.5.3 QSPI interface serial memory interface (SMIF).................................................................................................30 7.6 GPIO.......................................................................................................................................................................31 7.7 Special-function peripherals................................................................................................................................32 7.7.1 Audio subsystem................................................................................................................................................32 8 Pinouts ........................................................................................................................................33 9 Power management unit ...............................................................................................................38 9.1 RF power management ........................................................................................................................................38 9.2 Host controller power management ...................................................................................................................38 9.3 BBC power management......................................................................................................................................38 10 Electrical characteristics .............................................................................................................39 11 Chipset RF specifications .............................................................................................................40 12 Timing and AC characteristics ......................................................................................................42 12.1 UART timing ........................................................................................................................................................42 12.2 SPI timing ............................................................................................................................................................43 12.3 I2C interface timing.............................................................................................................................................45 13 Environmental specifications.......................................................................................................48 13.1 Environmental compliance ................................................................................................................................48 13.2 RF certification ....................................................................................................................................................48 13.3 Safety certification..............................................................................................................................................48 13.4 Environmental conditions..................................................................................................................................48 13.5 ESD and EMI protection ......................................................................................................................................48 14 Regulatory information ...............................................................................................................49 14.1 FCC.......................................................................................................................................................................49 14.2 ISED......................................................................................................................................................................50 14.3 European declaration of conformity..................................................................................................................51 14.4 MIC Japan............................................................................................................................................................52 15 Packaging ..................................................................................................................................53 16 Ordering information ..................................................................................................................55 17 Acronyms ...................................................................................................................................56 18 Document conventions................................................................................................................60 18.1 Units of measure .................................................................................................................................................60 Revision history ..............................................................................................................................61 Datasheet 6 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Overview 1 Overview 1.1 Figure 1 illustrates the CYW20829B0-P4xxI100 functional block diagram. Functional block diagram XRES Up to 2 SCBs

(I2C, SPI, UART) SCB Deep Sleep

(I2C, SPI) CAN-FD ADC UP to 9 TCPWMs Up to 26 GPIOs CYW20829 Silicon Device Passive Components

(RES, CAP, IND) 1 MB SERIAL FLASH 24 MHz XTAL Figure 1 Functional block diagram (GPIOs) Module description 1.2 The CYW20829B0-P4xxI100 module is a complete module designed to be soldered to the applications main board. Module dimensions and drawing 1.2.1 Infineon reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm). Table 1 Module design dimensions Dimension item Module dimensions Antenna connection location dimensions PCB thickness Shield height Maximum component height Total module thickness (bottom of module to highest component) Specification Length (X) 14.5 0.15 mm Width (Y) 19 0.15 mm Length (X) 14.5 mm Width (Y) 4.62 mm Height (H) 0.50 0.05 mm Height (H) 1.45-mm typical Height (H) 1.45-mm typical Height (H) 1.95-mm typical Datasheet 7 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Overview See Figure 2 for the mechanical reference drawing for CYW20829B0-P4xxI100. Figure 2 Module mechanical drawing Notes 2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Recommended host PCB layout on page 11. 3. The CYW20829B0-P4TAI100, CYW20829B0-P4EPI100 includes castellated pad connections, denoted as the circular openings at the pad location above. Datasheet 8 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Pad connection interface 2 Pad connection interface As shown in the bottom view of Figure 2, the CYW20829B0-P4xxI100 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYW20829B0-P4xxI100 module. Table 2 Connection description Part number Name Connections Connection type CYW20829B0-P4TAI100 SP CYW20829B0-P4EPI100 SP 41 41 Solder pads Solder pads Pad length dimension Pad width dimension 1.02 mm 1.02 mm 0.61 mm 0.61 mm Pad pitch 0.90 mm 0.90 mm Figure 3 Solder pad dimensions (seen from bottom) To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the module (see Figure 2) must not contain ground or signal traces. This keepout area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Bluetooth module is in a corner of the host board with the PCB trace antenna located at the far corner. This placement minimizes the additional recommended keepout area stated in item 2. Refer to AN96841 for module placement best practices. Datasheet 9 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Pad connection interface Figure 4 Recommended host PCB keepout area around the CYW20829B0-P4xxI100 antenna Datasheet 10 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Recommended host PCB layout 3 Recommended host PCB layout Figure 5 provides details that can be used for the recommended host PCB layout pattern for the CYW20829B0-P4xxI100. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.64 mm from center of the pad on either side) shown in Figure 4 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5 CYW20829B0-P4xxI100 host layout (dimensioned) Datasheet 11 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Module connections 4 Module connections Table 3 details the solder pad connection definitions and available functions for the pad connections for the CYW20829B0-P4xxI100 module. Table 3 lists the solder pads on the CYW20829B0-P4xxI100 module, the silicon device pin, and denotes what functions are available for each solder pad. Table 3 Pin assignments Module pad name Pin number Silicon pin name Pin number I/O Power domain Description Microphone Microphone MIC_P MIC_N MIC_BIAS GND_A MIC_P MIC_N MIC_BIAS 24 25 23 22, 26 Power supply VBAT 15 2.75 V~3.6 V 54 55 53 I O Microphone positive input VDDA Microphone negative input Microphone bias supply Analog ground for microphone Ground pins GND Radio I/O RFIO 1, 2, 14, 21, 33, 39, 41 40 I/O External antenna port (only for CYW20829B0-P4EPI100) Datasheet 12 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Module connections Table 4 GPIO pin descriptions Module pad name Pad number Silicon pin name Silicon pin number Direction Default POR state Power domain Description P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 6 7 8 9 10 11 4 5 12 13 18 19 20 27 28 29 30 16 17 31 32 37 38 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 32 33 34 35 36 37 38 39 40 41 43 44 45 1 2 3 4 5 6 8 9 13 14 P5.0/

WCO_OUT 34 WCO_OUT P5.1/

WCO_IN P5.2 XRES 35 36 3 P5.0/

WCO_OUT 10 WCO_OUT P5.1/

WCO_IN P5.2 XRES 11 12 23 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO Floating VDDO Floating VDDO Floating Floating VDDO VDDO General input and output port. See Table 13 for alternate functions. Notes 4. The CYW20829B0-P4xxI100 contains a single SPI (SPI1) peripheral supporting both master or slave configu-

rations. SPI2 is used for on-module serial memory interface. 5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in Table 23. Datasheet 13 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Connections and optional external components 5 Connections and optional external components Power connections (VBAT) 5.1 The CYW20829B0-P4xxI100 contains one power supply connection, VBAT, which accepts a supply input range of 2.75 V to 3.6 V for CYW20829B0-P4xxI100. Table 15 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 15. It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330 , 100 MHz. 5.1.1 Considerations and optional components for Brown Out (BO) conditions Power supply design must be completed to ensure that the CYW20829B0-P4xxI100 module does not encounter a Brown Out condition, which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the following range:

VILVDDIN VIH Refer to Table 16 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to Figure 6 for the recommended circuit design when using an external voltage detection IC. Figure 6 Reference circuit block diagram for external voltage detection IC In the event that the module does encounter a Brown Out condition, and is operating erratically or is not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. Datasheet 14 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Connections and optional external components External reset (XRES) 5.2 The CYW20829B0-P4xxI100 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYW20829B0-P4xxI100 module (solder pad 3). The CYW20829B0-P4xxI100 module does not require an external pull-up resistor on the XRES input During power-on operation, the XRES connection to the CYW20829B0-P4xxI100 is required to be held low 50 ms after the VBAT power supply input to the module is stable. This can be accomplished in the following ways:

The host device should connect a GPIO to the XRES of the CYW20829B0-P4xxI100 module and pull XRES low until VBAT is stable. XRES is recommended to be released 50 ms after VBAT is stable. If the XRES connection of the CYW20829B0-P4xxI100 module is not used in the application, a 10-F capacitor may be connected to the XRES solder pad of the CYW20829B0-P4xxI100 to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VBAT power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms after VBAT stability. The XRES release timing may be controlled by an external voltage detection IC. XRES should be released 50 ms after VBAT is stable. Datasheet 15 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Connections and optional external components Figure 7 illustrates the CYW20829B0-P4xxI100 schematic. Figure 7 CYW20829B0-P4xxI100 schematic diagram Datasheet 16 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Connections and optional external components 5.3 Table 5 details the critical components used in the CYW20829B0-P4xxI100 module. Critical components list Table 5 Critical component list Component Reference designator Description Silicon Silicon Crystal U1 U2 Y1 56-pin QFN Bluetooth LE silicon device - CYW20829 8-pin TDF8N, 1 MB Serial Flash 24 MHz, 8 pF 5.4 Table 6 details trace antenna used in the CYW20829B0-P4TAI100 module. For more information, see Table 6. Antenna design Table 6 Item Trace antenna specifications Description Frequency range 2400 MHz2500 MHz Peak gain Return loss 0.5-dBi typical 10-dB minimum Table below details the qualified dipole antenna used in the CYW20829B0-P4EPI100 module. Any antenna of equivalent or less gain can be used without additional application and testing for FCC regulations. For more information, see Table below. Table Dipole antenna specifications Item Manufacture Part number Frequency range Peak gain Description Pulse W1010 2400 MHz2500 MHz 2.0-dBi typical Datasheet 17 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Functional description 6 Functional description The following sections provide an overview of the features, capabilities and operation of each functional block identified in the block diagram in Figure 1. For more detailed information, refer to the following documentation:

Board Support Package (BSP) documentation BSPs are available on GitHub. They are aligned with Infineon kits and provide files for basic device functionality such as hardware configuration files, startup code, and linker files. The BSP also includes other libraries that are required to support a kit. Each BSP has its own documentation, but typically includes an API reference such as the example here. This search link finds all currently available BSPs on the Infineon GitHub site. Hardware Abstraction Layer (HAL) API reference manual The Infineon HAL provides a high-level interface to configure and use hardware blocks on Infineon MCUs. It is a generic interface that can be used across multiple product families. You can leverage the HALs simpler and more generic interface for most of an application, even if one portion requires finer-grained control. The HAL API Reference provides complete details. Example applications that use the HAL download it automatically from the GitHub repository. CPU and memory subsystem 6.1 AIROC CYW20829 has multiple bus masters, as Figure 1 shows. They are: CPU, datawire, QSPI, and a Crypto block. Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer Arm AMBA high-performance bus (AHB) arbitration. An interprocessor communication block (IPC) provides communication between the CPU and the Bluetooth LE sub-system. Datasheet 18 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Functional description CPU 6.1.1 The Cortex-M33 has single-cycle multiply and a memory protection unit (MPU). It can run at up to 96 MHz in LP mode and 48 MHz in ULP mode. This is the main CPU, designed for a short interrupt response time, high code density, and high throughput. Cortex-M33 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the Armv8-M architecture reference manual). The main MCU also implements device-level security, safety, and protection features. Cortex-M33 provides a secure, interruptible boot function. This guarantees that post boot, system integrity is checked and memory and peripheral access privileges are enforced. The CPU has the following power draw, at VDDD = 3.0 V and using the internal buck regulator. Table 7 Active current slope at VDDD = 3.0 V using the internal buck regulator System power mode CPU ULP 22 A/MHz LP 40 A/MHz The CPU can be selectively placed in Sleep and Deep Sleep power modes as defined by Arm. The CPU also implements a Deep Sleep RAM (DS-RAM) mode in which almost all the circuits except RAM are powered OFF. Data in RAM is retained to maintain state. Upon exit, the CPU goes through a reset but can use the data in RAM to skip software initialization. The CPU also has nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, and wakeup interrupt controllers (WIC) for CPU wakeup from Deep Sleep power mode. CYW20829 has a debug access port (DAP) that acts as the interface for device programming and debug. An external programmer or debugger (the host) communicates with the DAP through the device serial wire debug

(SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to device security restrictions), the host can access the device memory and peripherals as well as the registers in the CPU. CPU debug and trace features are as follows:

Six hardware breakpoints and four watchpoints, serial wire viewer (SWV), and printf()-style debugging through the single wire output (SWO) pin. Interrupts 6.1.2 The CPU has interrupt request lines (IRQ), with the interrupt source n directly connected to IRQn. Each interrupt supports eight configurable priority levels. One system interrupt can be mapped to the CPU non-maskable interrupts (NMI). Multiple interrupt sources are capable of waking the device from Deep Sleep power mode using the WIC. Datawire 6.1.3 Datawire is a light weight DMA controller with 16 channels, which support CPU-independent accesses to memory and peripherals. The descriptors for the channels are in SRAM and the number of descriptors is limited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and destination. Datasheet 19 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Functional description Cryptography accelerator (Cryptolite) 6.1.4 A combination of HW and SW is able to support several cryptographic functions. Specifically it supports the following functions:

Encryption/decryption

- AES-128 hardware accelerator with following supported modes:

Electronic Code Book (ECB) Cipher Block Chaining (CBC) Cipher Feedback (CFB) Output Feedback (OFB) Counter (CTR) Hashing

- Secure Hash Algorithm (SHA-256) hardware accelerator Message Authentication Functions (MAC)

- Hashed Message Authentication Code (HMAC) acceleration using SHA-256 hardware True Random Number Generator (TRNG) Vector unit hardware accelerator

- Digital Signature Verification using RSA

- Digital Signature Verification using ECDSA Protection units 6.1.5 CYW20829 has multiple types of protection to control erroneous or unauthorized access to memory and peripheral registers. Protection units support memory and peripheral access attributes including address range, read/write, code/data, privilege level, secure/non-secure, and protection context. Protection units are configured at Secure Boot to control access privileges and rights for bus masters and peripherals. Up to eight protection contexts (Secure Boot is in protection context 0) allow access privileges for memory and system resources to be set by the Secure Boot process per protection context by bus master and code privilege level. Multiple protection contexts are available. AES-128 6.1.6 AES-128 component to accelerate block cipher functionality. This functionality supports forward encryption of a single 128 bit block with a 128 bit key. SHA-256 component to accelerate hash functionality. This component supports message schedule calculation for a 512-bit message chunk and processing of a 512-bit message chunk. Vector unit (VU) 6.1.7 VU component to accelerate asymmetric key cryptography (for example, RSA and ECC). This component supports large integer multiplication, addition, and so on. TRNG component based on a set of ring oscillators. The TRNG includes a HW health monitor. Controller area network flexible data-rate (CAN FD) 6.1.8 CYW20829 supports the CAN FD controller that supports one CAN FD channel. All CAN FD controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in hardware. All functions concerning the handling of messages are implemented by the RX and TX handlers. The RX handler manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and provides receive-message status. The TX handler is responsible for the transfer of transmit messages from the message RAM to the CAN core, and provides transmit-message status. Datasheet 20 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Functional description Local interconnect network (LIN) 6.1.9 CYW20829 contains a LIN channel. Each channel supports transmission/reception of data following the LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin interface (including an enable function) and supports master and slave functionality. Each block also supports classic and enhanced checksum, along with break detection during message reception and wake-up signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware. 6.1.10 Real time clock (RTC) Year/Month/Date, Day-of-week, Hour:Minute:Second fields 12- and 24-hour formats Automatic leap-year correction 6.1.11 CYW20829 contains the SRAM, ROM, and eFuse memory blocks. Memory SRAM: CYW20829 has 256-KB of SRAM. Power control and retention granularity is 64-KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode. ROM: The 64-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system functions. The ROM contains, primarily device initialization and security. ROM code is executed, in protection context 0. eFuse: A one-time programmable (OTP) eFuse array consists of 1024 bits, which are reserved for system use such as Die ID, Device ID, initial trim settings, device life cycle, and security settings. Some of the bits are available for storing security key information and hash values and can be programmed by the user for device security. Each fuse is individually programmed; once programmed (or blown), its state cannot be changed. Blowing a fuse transitions it from the default state of 0 to 1. To program an eFuse, VDDIO1 must be at 2.5 V 5%. Because blowing an eFuse is an irreversible process, programming is recommended only in mass production under controlled factory conditions by Infineon provided provisioning tools. 6.1.12 On a device reset, the boot code in ROM is the first code to execute. This code performs the following:

Boot code Device trim setting (calibration) Setting the device protection units Setting device access restrictions for secure life cycle states Configures the Debug Access Port In secure life cycle supports secure debug via authenticated debug token Configures the SMIF for external flash access In secure life cycle validates first user code in external flash by checking its digital signature. Supports OTF decryption of encrypted images in external flash Copies the application bootstrap from the external flash to SRAM and jumps to the ROM. It cannot be changed and acts as the Root of Trust in a secure system. It should also be noted that the ROM code sets the system clock to 48 MHz IHO source. Datasheet 21 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Functional description Memory map 6.1.13 The 32-bit (4 GB) address space is divided into the regions shown in Table 9. Note that code can be executed from the Code, and Internal RAM or External flash. Table 8 Address map Address range Name Use 0x0000 0000 to 0x1FFF FFFF Code Program code region. It includes the exception vector table, which starts at address 0. 0x2000 0000 to 0x3FFF FFFF SRAM Data region 0x4000 0000 to 0x5FFF FFFF Peripheral 0x6000 0000 to 0x8FFF FFFF External NVM All peripheral registers. Code cannot be executed from this region. Bit-band in this region is not supported. SMIF/Quad SPI, (see the QSPI interface serial memory interface (SMIF) on page 30 section). Code can be executed from this region. 0xA000 0000 to 0xDFFF FFFF External Device Not used 0xE000 0000 to 0xE00F FFFF Private Peripheral Bus Provides access to peripheral registers within the CPU core. 0xE010 0A000 to 0xFFFF FFFF Device Device-specific system registers The device memory map is shown in Table 9. Table 9 Internal memory address map Address range Memory type 0x0000 0000 to 0x0001 0000 0x2000 0000 to 0x 2004 0000 ROM SRAM Size 64 KB Up to 256 KB Datasheet 22 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7 System resources Power system 7.1 The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the reset occurring. There are no voltage sequencing requirements. The VDDD supply (1.7 V to 3.6 V) powers an on-chip buck regulator which offers a selectable (1.0 V or 1.16 V) core operating voltage (VCCD). The selection lets users choose between two system power modes:

System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device configuration. System Ultra Low Power (ULP) operates VCCD at 1.0 V for exceptional low power, but imposes limitations on clock speeds. The Bluetooth radio requires 1.1 V for operation. Bluetooth system may override user core voltage selection when the radio is turned on. System voltage will return to the user selected value automatically once Bluetooth radio activity is completed. Refer to Power management unit on page 38 for more details. Power modes 7.1.1 CYW20829 can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the relevant application note. Power modes supported by CYW20829, in the order of decreasing power consumption, are:

System Low Power (LP) - All peripherals and CPU power modes are available at maximum speed System Ultra Low Power (ULP) - All peripherals and CPU power modes are available, but with limited speed CPU Active - CPU is executing code in system LP or ULP mode CPU Sleep - CPU code execution is halted in system LP or ULP mode CPU Deep Sleep - CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode System Deep Sleep - Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode System Hibernate - Device and I/O states are frozen and the device resets on wakeup Deep Sleep RAM - only RAM and IO states are retained. All system activity except for select low power peripherals ceases until system exits from this state. The CPU resets upon exit but can skip software initialization since RAM is retained. CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep, Deep Sleep RAM and Hibernate modes are additional low-power modes supported by the CYW20829. Datasheet 23 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources CYW20829 clock system 7.1.2 CYW20829 clock system consists of a combination of oscillators, external clock, and frequency-locked loop. Specifically, the following:

Internal main oscillator (IMO) Internal low-speed oscillator (ILO) Watch crystal oscillator (WCO) System 24-MHz crystal oscillator External clock input One frequency-locked loop (FLL) Internal high-speed oscillator (IHO) Clocks may be buffered and brought out to a pin on a smart I/O port. Table 10 shows the mapping of port and associated clock group mapped to peripherals. Table 10 Mapping of clock groups to peripherals PCLK group Root clock

(clk_hf) Peripherals Frequency LP

(1.1 V Typ) ULP

(1.0 V Typ) Description 0 1 2 3 4 5 6 clk_hf0 CPU Trace 24 MHz 24 MHz SCB TCPWM clk_hf1 LIN 96 MHz 48 MHz CANFD SMARTIO SMIF BTSS clk_hf0 96 MHz 48 MHz CRYPTO PDM TDM clk_hf1 96 MHz 48 MHz Async peripherals: Strobe signals are driven through dividers; Interface clock is generated inside the peripheral with the main group clock. Direct connection pass through from clk_hf. This clock is not used for interface clock, rather it is used for the MMIO clocks of SMIF, BTSS and CRYPTO. BTSS uses this clock for Master and Slave AHB/MMIO transactions, and SMIF also uses this clock for FAST/SLOW clocks. Uses PERI ACLK with default div by 2 option, required interface frequencies are obtained by further division inside the peripheral. clk_hf2 BTSS 48 MHz 48 MHz RPU clock for BTSS clk_hf3 ADCMIC 24 MHz 24 MHz clk_hf1 SMIF 96 MHz 48 MHz Direct connection for ADCMIC, main source of clk_hf3 is clk_althf which is the BTSS ECO clock. Direct connection for SMIF and SMARTIO peripherals. This clock is an interface clocks for these peripherals. Datasheet 24 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources Internal main oscillator (IMO) 7.1.3 The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz and tolerance is 2%. Internal low-speed oscillator (ILO) 7.1.4 The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against a higher accuracy clock for better accuracy. Primary mux Path mux

(FLL/PLL) Root mux FLL

(optional) clk_path0 clk_path<P+1>

... (D+P)

... (D) clk_path<P+D>

clk_ref_hf Predivider

(1/2/4/8) Predivider

(1/2/4/8)

... (R) Predivider

(1/2/4/8) CSV_HF0

(optional) clk_hf0 dsi_in0 io_clk_hf_out[0]

CSV_HF1

(optional) clk_hf1 dsi_in1 io_clk_hf_out[1]

CSV_HF<R-1>

(optional) clk_hf<R-1>

dsi_in<R-1>

io_clk_hf_out[R-1]

clk_ext clk_althf

(optional) IHO Active domain DeepSleep domain IMO clk_imo MF Prescaler clk_mf

(see ver note) clk_lf LEGEND Active DeepSleep Hibernate/HV clk_ilo0_hv clk_bak_hv DeepSleep domain Backup/Hibernate/

HV domain LS LS 0 ILO0 WCO

(optional) PILO

(optional) clk_wco_hv clk_pilo Yellow muxes are glitch safe, white ones are combinational. Intermediate clock signals (inputs to muxes) are are provided for asynchronous use in other peripherals. Use muxed output clocks for general logic. D = # of direct select paths (>0) P = # of PLLs (>=0) R = # of clock roots (>0) By default, all clocks are off except the IMO path through clk_path0 to clk_hf0. The predivider is bypassed. It is assumed that P<=R, since it does not make sense to have more PLLs than clock roots During XRES:SAFE* modes, clk_hf0 is bypassed to clk_ext (not shown in pic). Figure 8 CYW20829 clocking diagram with corresponding oscillators Note: Using PILO as the ILO clock source will result in longer boot time. Datasheet 25 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources External crystal oscillators (ECO) 7.1.5 Figure 9 shows all of the external crystal oscillator circuits for CYW20829. The component values shown are typical; check the ECO specifications for the crystal values, and the crystal datasheet for the load capacitor values. The ECO and WCO require balanced external load capacitors. For more information, see the HW design guidelines. Note that its performance is affected by GPIO switching noise. CYW20829 BT_XTALI BT_XTALO P5.1/WCO_IN P5.0/WCO_OUT 24 MHz XTAL 32.768 kHz XTAL CL / 2 CL / 2 CL / 2 CL / 2 Figure 9 External oscillator Watchdog timers (WDT, MCWDT) 7.1.6 CYW20829 has one WDT and two multi-counter WDTs (MCWDTs). The WDT has a 16-bit free-running counter. Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event. The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup generation in system LP/ULP and Deep Sleep power modes. 7.1.7 Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are one or more:

Clock dividers 8-bit clock dividers 16-bit integer clock dividers 16.5-bit fractional clock dividers 24.5-bit fractional clock divider Trigger routing 7.1.8 CYW20829 contains a trigger multiplexer block. This is a collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between GPIOs and peripheral blocks. There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination. There are also hardwired switches called one-to-one triggers, which connect a specific source to a destination. The user can enable or disable the route. Datasheet 26 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7.1.9 CYW20829 can be reset from a variety of sources:

Reset Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to function properly. POR activates automatically at power-up. Brown-out detect (BOD) reset to monitor the digital voltage supply VDDD and generate a reset if VDDD falls below the minimum required logic operating voltage. External reset dedicated pin (XRES) to reset the device using an external source. The XRES pin is active LOW. It can be connected either to a pull-up resistor to VDDD, or to an active drive circuit, as Figure 10 shows. If a pull-up resistor is used, select its value to minimize current draw when the pin is pulled LOW; 10 k is typical. 1.7 to 3.6 V CYW20829 VDDD 10 k typ. XRES drive XRES Figure 10 XRES connection diagram Watchdog Timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout period. Software-initiated reset to reset the device on demand using firmware. Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur;

for example, reaching a debug breakpoint while executing privileged code. Hibernate wakeup reset to bring the device out of the system Hibernate low-power mode. Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to determine the cause of the reset. Datasheet 27 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources Bluetooth LE radio and subsystem 7.2 CYW20829 incorporates a Bluetooth 5.4 LE subsystem (BLESS) that contains the physical layer (PHY) and link layer (LL) engines with an embedded security engine. The Bluetooth LE SS supports all Bluetooth LE 5.4 features including LE 2 Mbps, LE Long Range, LE Advertising Extensions, LE Isochronous Channels, Periodic Advertising with Responses (PAwR), Encrypted Advertising Data, LE GATT Security Levels Characteristic and Advertising Coding Selection. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian frequency shift keying (GFSK) packets at 1 or 2 Mbps over a 2.4 GHz ISM band, The device also supports Bluetooth LE long range, both 500 and 125 kbps speeds. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50 antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it through the antenna. 7.3 Programmable analog-to-digital converter (ADC) Sigma delta ADC 7.3.1 The ADC block is a single switched-cap - ADC core for audio and DC measurement. It operates at the 12-MHz clock rate and has 32 DC input channels, including eight GPIO inputs. The internal bandgap reference has 5%

accuracy without calibration. Different calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC. One of three internal references may be used for the ADC reference voltage: VDDA, VDDA/2, and an analog reference

(AREF). AREF is nominally 1.2 V, trimmed to 1%. 7.4 Programmable digital System Deep Sleep operation Asynchronous or synchronous (clocked) operation Can be synchronous or asynchronous Datasheet 28 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7.5 7.5.1 Fixed-function digital Timer/counter/pulse-width modulator (TCPWM) block The TCPWM supports the following operational modes:

- Timer-counter with compare

- Timer-counter with capture

- Quadrature decoding

- Pulse width modulation (PWM)

- Pseudo-random PWM

- PWM with dead time Up, down, and up/down counting modes Clock pre-scaling (division by 1, 2, 4, ... 64, 128) Double buffering of compare/capture and period values Underflow, overflow, and capture/compare output signals Supports interrupt on:

- Terminal count - Depends on the mode; typically occurs on overflow or underflow

- Capture/compare - The count is captured to the capture register or the counter value equals the value in the compare register Complementary output for PWMs Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state. In this device there are:

Two 32-bit TCPWMs Seven 16-bit TCPWMs Datasheet 29 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7.5.2 Serial communication blocks (SCB) This product line has three SCBs:

- First SCB: Configurable as SPI or I2C

- Second SCB: Configurable as SPI or UART

- Third SCB: Configurable as I2C or UART One SCB (SCB #0) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I2C slave. I2C mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I2C communication to reading from and writing to an array in the memory. The SCB supports a 256-byte FIFO for receive and transmit. The I2C peripheral is compatible with I2C standard-mode, Fast Mode, and Fast Mode Plus devices. The I2C bus I/O is implemented with GPIO in open-drain modes. UART mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface

(LIN), infrared interface (IrDA), and SmartCard (ISO 7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated. SPI mode: The SPI mode supports full SPI, Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 4-MHz clock. QSPI interface serial memory interface (SMIF) 7.5.3 A serial memory interface is provided, running at up to 48 MHz. It supports single, dual and quad SPI configurations, and supports up to four external memory devices. It supports two modes of operation:

Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and FIFOs Execute-in-Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers. In XIP mode, the external memory is mapped into the CYW20829 internal address space, enabling code execution directly from the external memory. To improve performance, a 32 KB cache is included. XIP mode also supports AES-128 based on-the-fly encryption and decryption, enabling secure storage and access of code and data in the external memory. Datasheet 30 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7.6 CYW20829 has up to 32 GPIOs, which implement:

GPIO Eight drive strength modes:

- Analog input mode (input and output buffers disabled) on some IOs

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

- Hold mode for latching previous state (used for retaining the I/O state in system Hibernate and deep sleep mode)

- Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are up to eight pins in width. Data output and pin state registers store, respectively, the values to be driven on the pins and the input states of the pins. Every pin can generate an interrupt if enabled; each port has an interrupt request (IRQ) associated with it. The port 4 pins are capable of overvoltage-tolerant (OVT) operation, where the input voltage may be higher than VDDD. OVT pins are commonly used with I2C, to allow powering the chip OFF while maintaining a physical connection to an operating I2C bus without affecting its functionality. GPIO pins can be ganged to source or sink higher values of current. GPIO pins, including OVT pins, may not be pulled up higher than the absolute maximum; see Electrical characteristics on page 39. During power-on and reset, the pins are forced to the analog input drive mode, with input and output buffers disabled, so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as the high-speed I/O matrix (HSIOM) is used to multiplex between various peripheral and analog signals that may connect to an I/O pin. In order to get the best performance, the following frequency and drive mode constraints may be applied. The DRIVE_SEL values (refer to Table 11) represent drive strengths. Table 11 DRIVE_SEL values Ports Maximum frequency Ports 0, 1 8 MHz Drive strength for VDDD 2.7 V DRIVE_SEL 2 Drive strength for VDDD > 2.7 V DRIVE_SEL 3 Ports 2 to 5 16 MHz; 24 MHz for SPI DRIVE_SEL 2 DRIVE_SEL 3 Datasheet 31 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module System resources 7.7 Special-function peripherals Audio subsystem 7.7.1 This subsystem consists of the following hardware blocks:

One inter-IC sound (I2S) interface Two pulse-density modulation (PDM) to pulse-code modulation (PCM) decoder channels The I2S interface implements two independent hardware FIFO buffers - TX and RX, which can operate in master or slave mode. The following features are supported:

Multiple data formats - I2S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B Programmable channel/word lengths - 8/16/18/20/24/32 bits Internal/external clock operation. Up to 192 ksps Interrupt mask events - trigger, not empty, full, overflow, underflow, watchdog Configurable FIFO trigger level with datawire support The I2S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to PCM data output. The following features are supported:

Programmable data output word length - 16/18/20/24 bits Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz Droop correction and configurable decimation rate for sampling; up to 48 ksps Programmable high-pass filter gain Interrupt mask events - not empty, overflow, trigger, underflow Configurable FIFO trigger level with DMA support The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM data line. Datasheet 32 002-39262 Rev. **

2023-12-20 i P n o u t s A I R O C B l u e t o o t h L E m o d u l e D a t a s h e e t 3 6 0 0 2

3 9 2 6 2 R e v

2 0 2 3

1 2

2 0 Each port pin has multiple alternate functions. These are defined in Table 13. Table 13 Multiple alternate functions[6]

Port/Pin Analog ACT #0 ACT #1 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15 DS #2 DS #3 DS #5 DS #6 DS #7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P2.0 P2.1 P2.2 P2.3 Note 6. tdm.tdm_ tx_ mck[0]:0 tdm.tdm_ rx_ mck[0]:0 tdm.tdm_ tx_sck[0]:0 tdm.tdm_ tx_ fsync[0]:0 tdm.tdm_ tx_sd[0]:0 tdm.tdm_ rx_sck[0]:0 tdm.tdm_ rx_ fsync[0]:0 tdm.tdm_ rx_sd[0]:0 pdm. pdm_ clk[1]:0 pdm. pdm_ data[1]:0 peri.tr_io_ input[4]:0 peri.tr_io_ input[0]:0 peri.tr_io_ input[1]:0 scb[1].spi_ select3:0 scb[1].spi_ select2:0 scb[1].spi_ select1:0 scb[1].spi_ select0:0 scb[1].spi_ clk:0 scb[1]. uart_cts:0 scb[1]. uart_rts:0 scb[1]. uart_rx:0 scb[2].i2c_ scl:1 scb[1].spi_ mosi:0 scb[1]. uart_tx:0 scb[2].i2c_ sda:1 scb[1].spi_ miso:0 peri.tr_io_ input[2]:0 peri.tr_io_ input[3]:0 tcpwm[0]. line_ compl[0]:3 tcpwm[0]. line_ compl[262]:0 tcpwm[0]. line[1]:3 tcpwm[0]. line[256]:1 tcpwm[0]. line_ compl[1]:3 tcpwm[0]. line_ compl[256]:1 tcpwm[0]. line[0]:4 tcpwm[0]. line[257]:1 tcpwm[0]. line_ compl[0]:4 tcpwm[0]. line_ compl[257]:1 srss.ext_ clk:0 tcpwm[0]. line[1]:4 tcpwm[0]. line[258]:1 tcpwm[0]. line_ compl[1]:4 tcpwm[0]. line_ compl[258]:1 tcpwm[0]. line[0]:5 tcpwm[0].l ine[259]:1 tcpwm[0]. line_ compl[0]:5 tcpwm[0]. line_ compl[259]:1 tcpwm[0]. line[1]:5 tcpwm[0]. line[260]:1 tcpwm[0]. line_ compl[1]:5 tcpwm[0]. line_ compl[260]:1 tcpwm[0]. line[0]:6 tcpwm[0]. line[261]:1 tcpwm[0]. line_ compl[0]:6 tcpwm[0]. line_ compl[261]:1 cpuss. trace_ data[3]:1 cpuss. trace_ data[2]:1 cpuss. trace_ data[1]:1 cpuss. trace_ data[0]:1 cpuss. trace_ clock:1 peri.tr_ io_ output[0]:0 peri.tr_ io_ output[1]:0 lin[0].lin_ en[1]:0 lin[0].lin_ rx[1]:0 lin[0].lin_ tx[1]:0 scb[0]. spi_ select1:0 scb[0]. spi_ select2:0 scb[0]. spi_ mosi:0 scb[0]. spi_ miso:0 scb[0]. spi_clk:0 scb[0]. spi_ select0:0 keyscan. ks_ col[2]

keyscan. ks_ col[3]

keyscan. ks_ col[11]

keyscan. ks_ col[12]

keyscan. ks_ row[0]

keyscan. ks_ row[1]

keyscan. ks_ row[2]

keyscan. ks_ row[3]

keyscan. ks_ row[4]

keyscan. ks_ row[5]

keyscan. ks_ col[4]

keyscan. ks_ col[5]

keyscan. ks_ col[6]

scb[0]. i2c_scl:0 scb[0]. i2c_sda:0 srss.cal_ wave cpuss. swj_ swo_ tdo cpuss. swj_ swdoe_ tdi cpuss. swj_ swdio_ tms cpuss.clk_ swj_ swclk_tclk smif. spihb_ select1 smif. spihb_ select0 smif. spihb_ data3 smif. spihb_ data2 smif. spihb_ data1 The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. i P n o u t s A I R O C B l u e t o o t h L E m o d u l e D a t a s h e e t 3 7 Table 13 Multiple alternate functions[6] (continued) Port/Pin Analog ACT #0 ACT #1 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15 DS #2 DS #3 DS #5 DS #6 DS #7 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P5.0/

WCO_OUT P5.1/

WCO_IN scb[2]. uart_cts:0 scb[2]. uart_rts:0 scb[1].spi_ select0:1 scb[1].spi_ clk:1 lin[0].lin_ en[0]:0 scb[2]. uart_rx:0 scb[2].i2c_ scl:0 scb[1].spi_ mosi:1 scb[2]. uart_tx:0 scb[2].i2c_ sda:0 scb[1].spi_ miso:1 pdm. pdm_ clk[0]:0 pdm. pdm_ data[0]:0 peri.tr_io_ input[6]:0 lin[0].lin_ rx[0]:0 canfd[0]. ttcan_rx[0]

adcmic. clk_pdm:0 peri.tr_io_ input[7]:0 lin[0].lin_ tx[0]:0 canfd[0]. ttcan_tx[0]

adcmic. pdm_ data:0 scb[1].spi_ select3:1 scb[1].spi_ select2:1 scb[1].spi_ select1:1 cpuss. trace_ data[3]:0 cpuss. trace_ data[2]:0 cpuss. trace_ data[1]:0 cpuss. trace_ data[0]:0 cpuss. trace_ clock:0 adcmic. gpio_ adc_in[0]

tcpwm[0]. line[0]:0 tcpwm[0]. line[256]:0 adcmic. gpio_ adc_in[1]

tcpwm[0]. line_ compl[0]:0 tcpwm[0]. line_ ompl[256]:0 adcmic. gpio_ adc_in[2]

tcpwm[0]. line[1]:0 tcpwm[0]. line[257]:0 adcmic. gpio_ adc_in[3]

tcpwm[0]. line_ compl[1]:0 tcpwm[0]. line_ ompl[257]:0 adcmic. gpio_ adc_in[4]

tcpwm[0]. line[0]:1 tcpwm[0]. line[258]:0 adcmic. gpio_ adc_in[5]

tcpwm[0]. line_ compl[0]:1 tcpwm[0]. line_ ompl[258]:0 adcmic. gpio_ adc_in[6]

tcpwm[0]. line[1]:1 tcpwm[0]. line[259]:0 adcmic. gpio_ adc_in[7]

tcpwm[0]. line_ compl[1]:1 tcpwm[0]. line_ ompl[259]:0 tcpwm[0]. line_ compl[1]:2 tcpwm[0]. line_ ompl[261]:0 tcpwm[0]. line[0]:3 tcpwm[0]. line[262]:0 cpuss.rst_ swj_trstn smif. spihb_ data0 smif. spihb_ clk btss. uart_ cts:0 btss. uart_ rts:0 btss. uart_ rxd:0 btss. uart_ txd:0 keyscan. ks_col[13]

keyscan. ks_col[14]

keyscan. ks_col[15]

keyscan. ks_col[16]

keyscan. ks_col[7]

keyscan. ks_col[8]

keyscan. ks_col[9]

keyscan. ks_col[10]

keyscan. ks_row[6]

scb[0]. i2c_scl:1 keyscan. ks_row[7]

scb[0]. i2c_sda:1 scb[0]. spi_ mosi:1 scb[0]. spi_ miso:1 tcpwm[0]. line[0]:2 tcpwm[0]. line[260]:0 srss.ext_ clk:1 scb[2]. uart_cts:1 scb[1].spi_ select0:2 tcpwm[0]. line_compl

[0]:2 tcpwm[0]. line_ ompl[260]:0 tcpwm[0]. line[1]:2 tcpwm[0]. line[261]:0 pdm. pdm_ clk[0]:1 pdm. pdm_ data[0]:1 adcmic. clk_pdm:1 btss. uart_ cts:1 adcmic. pdm_ data:1 keyscan. ks_col[17]

keyscan. ks_col[0]

keyscan. ks_col[1]

The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. P5.2 Note 6. 0 0 2

3 9 2 6 2 R e v

2 0 2 3

1 2

2 0 AIROC Bluetooth LE module Power management unit 9 Power management unit The Power management unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. RF power management 9.1 The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4-GHz transceiver, which then processes the power-down functions accordingly. Host controller power management 9.2 Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in Deep Sleep (HIDOFF) mode. 9.3 There are several low-power operations for the BBC:

BBC power management Physical layer packet handling turns RF on and off dynamically within packet TX and RX. Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20829B0-P4xxI100 runs on the low power oscillator and wakes up after a predefined time period. The CYW20829B0-P4xxI100 automatically adjusts its power dissipation based on user activity. The following power modes are supported:

Active mode Idle mode Sleep mode HIDOFF (Deep Sleep) mode The CYW20829B0-P4xxI100 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. In HIDOFF (Deep Sleep) mode, the CYW20829B0-P4xxI100 baseband and core are powered off by disabling power to VDDC_OUT and PAVDD. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. Datasheet 38 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Electrical characteristics 10 Electrical characteristics Table 14 shows the maximum electrical ratings for voltages referenced to VDDIN pad. Table 14 Maximum electrical ratings Rating VDDIN Voltage on input or output pin Operating ambient temperature range Storage temperature range Symbol Value Topr Tstg 3.795 VSS 0.3 to VDD + 0.3 30 to +85 40 to +85 Unit V C Table 15 shows the power supply characteristics for the range TJ = 0C to 125C. Table 15 Power supply Description Parameter VDDIN VDDIN_RIPPLE Maximum power supply ripple for VDDIN input voltage Power supply input (CYW20829B0-P4xxI100) Min[7]

2.75 Typ Max[7]

3.6 100 Unit V mV Table 16 shows the specifications for the digital voltage levels. Table 16 Digital voltage levels Characteristics Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance (VDDMEM domain) Table 17 shows the current consumption measurements. Symbol VIL VIH VOL VOH CIN Min 2.0 VDDIN 0.4 Typ Max Unit 0.8 0.4 0.4 V pF Note 7. Overall performance degrades beyond minimum and maximum supply voltages.The voltage range specified is determined by the minimum and maximum operating voltage of the SPI Serial Flash included on the module. Datasheet 39 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Chipset RF specifications 11 Chipset RF specifications All specifications in Table 18 are for industrial temperatures and are single-ended. Unused inputs are left open. Table 18 Receiver RF specifications Conditions Min Typ[8]

Max Unit Parameter General Frequency range RX sensitivity[9]

Maximum input GFSK, 1 Mbps Interference performance TBD Out-of-band blocking performance (CW)[10]

30MHz2000MHz 0.1% BER 2000MHz2399MHz 2498MHz3000MHz 0.1% BER 0.1% BER 0.1% BER 3000MHz12.75 GHz Intermodulation performance[11]

BT, Df=4MHz Spurious Emissions[12]

30MHz1 GHz 1 GHz12.75 GHz 65 MHz108 MHz 746MHz764MHz 851MHz894MHz 925MHz960MHz 1805MHz1880MHz 1930MHz1990MHz 2110MHz2170MHz FM RX CDMA CDMA EDGE/GSM EDGE/GSM PCS WCDMA 2402 39.0 98 2480 20 MHz dBm 10.0 27 27 10.0 147 147 147 147 147 147 147 62 47 dBm dBm dBm dBm/Hz Notes 8. Typical operating conditions are 1.22-V operating voltage and 25C ambient temperature. 9. The receiver sensitivity is measured at BER of 0.1% on the device interface. 10.Meets this specification using front-end band pass filter. 11.f0=64 dBm Bluetooth-modulated signal, f1=39 dBm sine wave, f2=39 dBm Bluetooth-modulated signal, f0=2f1f2, and |f2 f1|=n 1MHz, where n is 3, 4, or 5. For the typical case, n = 4. 12.Includes baseband radiated emissions. Datasheet 40 002-39262 Rev. **

2023-12-20 Conditions Min Typ Max Unit AIROC Bluetooth LE module Chipset RF specifications Table 19 Transmitter RF specifications Parameter General Frequency range Class 1: GFSK TX power Power control step Out-of-Band spurious emissions 30MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz Table 20 Bluetooth LE RF specifications Parameter Frequency range RX sense[15]

TX power Mod Char: Delta F1 average Mod Char: Delta F2 max[16]

Mod Char: Ratio Conditions N/A GFSK, 0.1% BER, 1 Mbps N/A N/A N/A N/A 2402 2 Min 2402 225 99.9 0.8 10 4 Typ 98 10 255 0.95 2480 8 36.0[13]

30.0[14]

47.0 47.0 Max 2480 275 MHz dBm dB dBm Unit MHz dBm kHz

Notes 13.Maximum value is the value required for Bluetooth qualification. 14.Meets this spec using a front-end band-pass filter. 15.Dirty TX is OFF. 16.At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Datasheet 41 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics 12 Timing and AC characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. 12.1 UART timing Table 21 UART timing specifications Reference Characteristics 1 2 3 Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min Max 1.50 0.67 1.33 Unit Baud periods Figure 12 UART timing Datasheet 42 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics SPI timing 12.2 The SPI interface supports clock speeds up to 12 MHz. Table 22 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively. Table 22 SPI mode 0 and 2 Reference Characteristics Min Max Unit 1 2 3 4 5 6 7 8 Time from slave assert SPI_INT to master assert SPI_CSN

(DirectRead) Time from master assert SPI_CSN to slave assert SPI_INT

(DirectWrite) Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN 0 0 20 8 8 0 0 SCK SCK 100 ns Idle time between subsequent SPI transactions 1 SCK SPI_CSN SPI_INT

(DirectWrite) SPI_INT

(DirectRead) SPI_CLK

(Mode 0) SPI_CLK

(Mode 2) 1 2 5 3 4 SPI_MOSI First Bit Second Bit Last bit SPI_MISO Not Driven First Bit Second Bit Last bit Not Driven Figure 13 SPI timing mode 0 and 2 Datasheet 43 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics Table 23 and Figure 14 show the timing requirements when operating in SPI Mode 1 and 3. Table 23 SPI mode 1 and 3 Reference Characteristics 1 2 3 4 5 Time from master assert SPI_CSN to first clock edge Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions Min 45 12 0 0 1 SCK Max SCK 100 Unit ns SPI_CSN SPI_INT

(DirectWrite) SPI_INT

(DirectRead) SPI_CLK

(Mode 1) SPI_CLK

(Mode 3) 1 2 5 3 4 SPI_MOSI Invalid bit First bit Last bit SPI_MISO Not Driven Invalid bit First bit Last bit Not Driven Figure 14 SPI timing mode 1 and 3 Datasheet 44 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics 12.3 I2C interface timing Table 24 Reference I2C interface timing specifications Characteristics 1 2 3 4 5 6 7 8 9 10 Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time[17]

Data input setup time STOP condition setup time Output valid from clock Bus free time[18]

Unit kHz ns Min 650 280 650 280 0 100 280 650 Max 100 400 800 1000 400 Figure 15 I2C Interface timing diagram Notes 17.As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 18.Time that the bus must be free before a new transaction can start. Datasheet 45 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics Table 25 Timing for I2S transmitters and receivers Transmitter Lower limit Receiver Upper limit Lower limit Upper limit Notes Clock Period T Min Ttr Max Min Max Min Tr Max Min Max 0.35 Ttr 0.35 Ttr Master mode: Clock generated by transmitter or receiver HIGH tHC LOWtLC Slave mode: Clock accepted by transmitter or receiver HIGH tHC LOW tLC Rise time tRC Transmitter Delay tdtr Hold time thtr Receiver Setup time tsr Hold time thr 0.35 Ttr 0.35 Ttr 0.15 Ttr 0.8 T 0 0.35 Ttr 0.35 Ttr 0.35 Ttr 0.35 Ttr 0.2 Tr 0 19 20 20 21 21 22 23 22 24 23 Note: The time periods specified in Figure 16 and Figure 17 are defined by the transmitter speed. The receiver specifications must match transmitter performance. Notes 19.The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 20.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. 21.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35 Tr, any clock that meets the requirements can be used. 22.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15 Ttr. 23.To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 24.The data setup and hold time must not be less than the specified receiver setup and hold time. Datasheet 46 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Timing and AC characteristics Figure 16 I2S transmitter timing Figure 17 I2S receiver timing Datasheet 47 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Environmental specifications 13 Environmental specifications Environmental compliance 13.1 This CYW20829B0-P4xxI100 Bluetooth LE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Infineon module and components used to produce this module are RoHS and HF compliant. RF certification 13.2 The CYW20829B0-P4xxI100 module will be certified under the following RF certification standards at production release. FCC: TBD CE IC: TBD MIC: TBD 13.3 The CYW20829B0-P4xxI100 module complies with the following safety regulations:

Safety certification Underwriters Laboratories, Inc. (UL): Filing E331901 CSA TUV 13.4 Table 26 describes the operating and storage conditions for the Bluetooth LE module. Environmental conditions Table 26 Environmental conditions for CYW20829B0-P4xxI100 Description Operating temperature Minimum specification Maximum specification 30C Operating humidity (relative, non-condensation) 5%

Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into end system components[25]

40C 85C 85%

3C/minute 85C 85C at 85%

15 kV Air 2.0 kV Contact ESD and EMI protection 13.5 Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 25.This does not apply to the RF pins (ANT). Datasheet 48 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Regulatory information 14 Regulatory information FCC 14.1 FCC NOTICE:

The device CYW20829B0-P4xxI100 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Infineon may void the users authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help This module is only FCC authorized for the specific rule FCC 15.247 listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification, final host product requires Part 15 Subpart B compliance testing with the modular transmitter installed. LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Infineon FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP829I10. In any case the end product must be labeled exterior with Contains FCC ID: WAP829I10. ANTENNA WARNING:

This device is tested with a standard SMA connector and with the antenna listed in Table 6. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. Datasheet 49 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Regulatory information RF EXPOSURE:

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 6, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYW20829B0-P4xxI100 with the trace antenna is far below the FCC radio frequency exposure limits. Nevertheless, use CYW20829B0-P4xxI100 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 13 mm between the radiator and your body. ISED 14.2 Innovation, Science and Economic Development Canada (ISED) Certification CYW20829B0-P4xxI100 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada (ISED), License: IC: 7922A-829I10 Manufacturers of mobile, fixed, or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian infor-

mation on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 6, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE:

The device CYW20829B0-P4xxI100 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYW20829B0-P4xxI100, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences d'approbation de l'metteur modulaire tel que dcrit dans RSS-GEN. L'opration est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interfrences nuisibles, et (2) Cet appareil doit accepter toute interfrence reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and

(2) this device must accept any interference, including interference that may cause undesired operation of the device. Datasheet 50 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Regulatory information Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 16 mm between the radiator and your body. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. Cet quipement doit tre install et utilis avec un minimum de 16 mm de distance entre la source de rayonnement et votre corps. LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that ISED labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Infineon IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-829I10. In any case, the end product must be labeled in its exterior with Contains IC: 7922A-829I10 European declaration of conformity 14.3 Hereby, Infineon declares that the Bluetooth module CYW20829B0-P4xxI100 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:

All versions of the CYW20829B0-P4xxI100 in the specified reference design can be used in the following countries:

Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Datasheet 51 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Regulatory information MIC Japan 14.4 CYW20829B0-P4xxI100 is certified as a module with certification number TBD. End products that integrate CYW20829B0-P4xxI100 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. TBD Figure 18 MIC label Datasheet 52 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Packaging 15 Packaging Table 27 Solder Reflow peak temperature Module part number Package Maximum peak temperature Maximum time at peak temperature No. of cycles CYW20829B0-P4TAI040 CYW20829B0-P4EPI040 41-pad SMT 41-pad SMT 260C 260C 30 seconds 30 seconds 2 2 Table 28 Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module part number CYW20829B0-P4TAI040 CYW20829B0-P4EPI040 Package 41-pad SMT 41-pad SMT MSL MSL 3 MSL 3 The CYW20829B0-P4xxI100 is offered in tape and reel packaging. Figure 19 details the tape dimensions used for the CYW20829B0-P4xxI100. Figure 19 CYW20829B0-P4xxI100 tape dimensions Figure 20 details the orientation of the CYW20829B0-P4xxI100 in the tape as well as the direction for unreeling. Figure 20 Component orientation in tape and unreeling direction Datasheet 53 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Packaging Figure 21 details reel dimensions used for the CYW20829B0-P4xxI100. Figure 21 Reel dimensions Datasheet 54 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Ordering information 16 Ordering information Table 29 lists the CYW20829B0-P4xxI100 part number and features. Table 30 lists the reel shipment quantities for the CYW20829B0-P4xxI100. Table 29 Ordering information Part number CPU speed

(MHz) Flash size

(KB) RAM size

(KB) UART I2C

(BSC) CYW20829B0-P4TAI040 96 1024 256 Yes Yes CYW20829B0-P4EPI040 96 1024 256 Yes Yes PWM Antenna Package Packaging 9 9 Trace 41-SMT Pad 41-SMT Tape and reel Tape and reel Table 30 Tape and reel package quantity and minimum order amount Minimum reel quantity Maximum reel quantity Comments Description Reel quantity Minimum order quantity (MOQ) 500 500 Order increment (OI) 500 500 Ships in 500 unit reel quantities. The CYW20829B0-P4xxI100 is offered in tape and reel packaging. The CYW20829B0-P4xxI100 ships in a reel size of 500. For additional information and a complete list of Infineon Wireless products, contact your local Infineon sales representative. To locate the nearest Infineon office, visit our website. U.S. headquarters address U.S. headquarter contact info Website address 198 Champion Court, San Jose, CA 95134

(408) 943-2600 https://www.infineon.com Datasheet 55 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Acronyms 17 Acronyms Table 31 Acronyms used in this document Acronym Description ADC ADV ALU analog-to-digital converter advertising arithmetic logic unit AMUXBUS analog multiplexer bus API Arm BLE application programming interface advanced RISC machine, a CPU architecture Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group BW CAN CE CMRR CPU CRC CSA ECC ECO bandwidth Controller Area Network, a communications protocol European Conformity common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol Canadian Standards Association error correcting code external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI EMIF EOC EOF ESD FCC FET FIR FPB FS GPIO HCI HVI I/O electromagnetic interference external memory interface end of conversion end of frame electrostatic discharge Federal Communications Commission field-effect transistor finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin host controller interface high-voltage interrupt, see also LVI, LVD input/output, see also GPIO, DIO, SIO, USBIO I2C, or IIC Inter-Integrated Circuit, a communications protocol IC IC IDAC IDE integrated circuit Industry Canada current DAC, see also DAC, VDAC integrated development environment Datasheet 56 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Acronyms Table 31 Acronyms used in this document (continued) Acronym Description IIR ILO IMO INL IPOR IPSR IRQ ITM KC LCD LIN LNA LR LUT LVD LVI LVTTL MAC MCU MIC MISO NC NMI NRZ NVIC NVL infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell Korea Certification liquid crystal display Local Interconnect Network, a communications protocol. low noise amplifier link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit Ministry of Internal Affairs and Communications (Japan) master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL Opamp operational amplifier PA PAL PC PCB PGA PHUB PHY PICU PLA PLD PLL PMDD POR power amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset Datasheet 57 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Acronyms Table 31 Acronyms used in this document (continued) Acronym Description PRES PRS PS PSoC PSRR PWM QDID RAM RISC RMS RTC RTL RTR RX S/H SAR SC/CT SCL SDA SINAD SIO SMT SOC SOF SPI SR SRAM SRES STN SWD SWV TD THD TIA TN TRM TTL TUV TX precise power-on reset pseudo random sequence port read data register Programmable System-on-Chip power supply rejection ratio pulse-width modulator qualification design ID random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive sample and hold successive approximation register switched capacitor/continuous time I2C serial clock I2C serial data signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs start of conversion start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset super twisted nematic serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier twisted nematic technical reference manual transistor-transistor logic Germany: Technischer Uberwachungs-Verein (Technical Inspection Association) transmit Datasheet 58 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Acronyms Table 31 Acronyms used in this document (continued) Acronym Description UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Datasheet 59 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Document conventions Document conventions Units of measure Units of measure Unit of measure degrees Celsius decibel decibel-milliwatts femtofarads hertz 1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt 18 18.1 Table 32 Symbol C dB dBm fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V Datasheet 60 002-39262 Rev. **

2023-12-20 AIROC Bluetooth LE module Revision history Revision histor y Document version

Date of release Description of changes 2023-12-20 Initial release. Datasheet 61 002-39262 Rev. **

2023-12-20 Please read the Important Notice and Warnings at the end of this document Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-12-20 Published by Infineon Technologies AG 81726 Munich, Germany 2023 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document?

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erratum@infineon.com Document reference 001-08694 Rev. AO IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (Beschaffenheitsgarantie). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. representatives of With respect to any examples, hints or any typical information values stated herein and/or any regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customers compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customers products and any use of the product of Infineon Technologies in customers applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customers technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.

Remark:Its hard to put FCC statement on the product due to devices irregular appearance. FCC state ment will be placed in the user manual which the device is marketed. Remark:Its hard to put FCC statement on the product due to devices irregular appearance. FCC state ment will be placed in the user manual which the device is marketed. Remark:Its hard to put FCC statement on the product due to devices irregular appearance. FCC state ment will be placed in the user manual which the device is marketed. Remark:Its hard to put FCC statement on the product due to devices irregular appearance. FCC state ment will be placed in the user manual which the device is marketed.

Cypress Semiconductor TO:

Federal Communication Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MID 21046 Regarding: FCC ID: WAP829I10 To whom it may concern:

Date: 2023/12/15 We, the undersigned, hereby authorize Parlam Zhan to act on our behalf in all manners relating to application for equipment authorization with respect to the FCC ID above, including signing of all documents relating to these matters. Any and all acts carried out by the agent on our behalf shall have the same effect as acts of our own. We, the undersigned, hereby certify that we are not subject to a denial of federal benefits, that includes FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 853(a). Where our agent signs the application for certification on our behalf, I acknowledge that all responsibility for complying with the terms and conditions for Certification, as specified by SGS North America, Inc., still resides with Cypress Semiconductor. This authorization is valid until further written notice from the applicant. Name (Printed): Juan Martinez Title: Senior System Engineer Signature:

On behalf of Company: Cypress Semiconductor Telephone: 8317446217

Cypress Semiconductor To:

SGS North America Inc. 620 Old Peachtree Road SUITE 100 Suwanee, Georgia United States From: Company Name: Cypress Semiconductor Address: 198 Champion Court, San Jose, California 95134, United States Regarding:

Confidentiality Request regarding application for FCC ID: WAP829I10 LONG TERM CONFIDENTIALITY Pursuant to 47 CFR Section 0.459 and 0.457 of the commissions rules, the applicant hereby request confidential treatment of the documents listed below, associated with the certification application referenced above. Schematic(s) Block Diagrams Operational Descriptions The documents above contain proprietary information not released to the public. Public disclosure of this information may prove harmful to the business of the applicant. Sincerely, Signature:

Printed Name (on file with the FCC associated with the Grantee Code): Juan Martinez Title: Senior System Engineer Company Name: Cypress Semiconductor

UNITED STATES DESIGNATED AGENT LETTER Date: 2023/12/15 TO:

Federal Communication Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MID 21046 Applicant Company Name: Cypress Semiconductor Grantee Code: WAP Contact Name:

Address:

City/Province/Zip

Telephone:

Fax:

Email:

Juan Martinez 198 Champion Court, San Jose, California 95134, United States 8317446217 408-544-1694 juan.martinez2@infineon.co m Applicable Equipment: FCC ID: WAP829I10 ATTN: Director of Certification:

U.S. designated agent Company Name: Cypress Semiconductor FRN:

Contact Name:

Address:

City/Province/Zip

0017759150 Juan Martinez 198 Champion Court, San Jose, California 95134, United States 8317446217 408-544-1694 juan.martinez2@infineon.co m Telephone:

Fax:

Email:

We, Cypress Semiconductor and Cypress Semiconductor understand and acknowledge the applicants consent and the designated agents obligation to accept service of process in the United States for matters related to the applicable equipment, and at the physical U.S. address and e-mail of the designated agent listed above. We, Cypress Semiconductor and Cypress Semiconductor acknowledge the applicants acceptance of its obligation to maintain an agent for service of process in the United States for no less than one year after either the grantee has permanently terminated all marketing and importation of the applicable equipment within the U.S., or the conclusion of any Commission-related administrative or judicial proceeding involving the equipment, whichever is later. Applicant U.S. designated agent Name (Printed): Juan Martinez Name (Printed): Juan Martinez Title: Senior System Engineer Title: Senior System Engineer Signature:

Signature:

Cypress Semiconductor FCC ID: WAP829I10 Gentlemen:

Cover Letter-Modular Approval Date: 2023-12-15 Theres a radar Module that would like to have your authorization as a modular approval. The specific product as below, radar Module with its designed features and specified description, meets special requirements for Full modular approval on FCC KDB996369 by cross-reference list below. Company Model Name Model Number FCC ID Cypress Semiconductor AIROC Bluetooth LE Module CYW20829B0-P4TAI100, CYW20829B0-P4EPI100, CYW20829B0S-P4TAI100, CYW20829B0S-P4EPI100 WAP829I10 Requirement of FCC KDB996369 1. The modular transmitter must have its own RF shielding. 2. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with Part 15 requirements under conditions of excessive data rates or over-modulation. 3. The modular transmitter must have its own power supply regulation. 4. The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section. 5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. 6. The modular transmitter must be labeled with its own FCC ID number, and, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: N82-KOHLER053 or Contains FCC ID: N82-KOHLER053 Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application ComplyY/N Y The EUT has its own RF shielding. Please refer to EUT Photos. Y The EUT uses the chip: CYW20829B0 as an embedded processor to buffer the data. Please refer to Schematics. Y The EUT has its own power supply regulation, The power supply of this module is 2.75V~3.6V. Please refer to User Manual. Y The EUT meets the FCC antenna requirements; The photo of antenna is shown in the test report. Y The EUT was tested with a test cable, see test report and setup photo Y Please see exhibition label sample for the FCC ID of this module. And also in the exhibition Users manual, there are instructions to the OEM on how to label the end product. Y The EUT is compliant with all applicable FCC rules. Details instructions for maintaining compliance are given in the User Manual. Y The EUT complies with RF exposure requirement. Cypress Semiconductor for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization. 7. The modular transmitter must comply with any specific rule or operating requirements applicable to the transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. 8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance in accordance with Section 15.247(b)(4). Thank you. Sincerely, Print Name: Juan Martinez Title: Senior System Engineer Signature:

On behalf of Company: Cypress Semiconductor Telephone: 8317446217

Cypress Semiconductor Current Date: 2023-12-15 To:

SGS-CSTC Standards Technical Services (Shanghai) Co., Ltd. No. 588 West Jindu Road, Songjiang District, Shanghai, China. 201612 Dear Sir/Madam, Subject: Declaration Letter about Identity of Products

*WE (Cypress Semiconductor) HEREBY DECLARED THAT Product Description AIROC Bluetooth LE Module Model No. CYW20829B0S-P4TAI100, CYW20829B0S-P4EPI100 Manufacturers Name Cypress Semiconductor Manufacturers Address 198 Champion Ct, San Jose, California 95134, United States

*Except that CYW20829B0-P4TAI100 and CYW20829B0S-P4TAI100, support PCB antennas. CYW20829B0-P4EPI100 and CYW20829B0S-P4EPI100 support Dipole antennas. Their other electrical performance is the same. The modules part number has -S, means the device sup ports encrypted secure mode to improve the security with the same hardware deviation, are identical with the original product as follows:

Note: The definition of identical should be electrically identical. A device will be considered to be electrically identical if no changes are made to the devices schematics, board layouts, component layouts, chip sets, resistors and all other electrical aspects of the device are identical. with the model(s) below which samples we chose to be tested by SGS Model No.:

CYW20829B0-P4TAI100, CYW20829B0-P4EPI100 Manufacturers Name:

Cypress Semiconductor Manufacturers Address:

198 Champion Ct, San Jose, California 95134, United States Sincerely, Signature ():

Printed Name ():

Juan Martinez Position/Title ():

Senior System Engineer Contact Number ():

8317446217

SGS North America Inc. 620 Old Peachtree Road SUITE 100 Suwanee, Georgia 30024 United States Applicant Legal Business Name Cypress Semiconductor Applicant Declaration Address Grantee Code FCC ID Authorized Contact Name Contact Email Contact Phone 198 Champion Court, San Jose, California 95134, United States WAP WAP829I10 Juan Martinez juan.martinez2@infineon.com 8317446217 I, the undersigned, certify that I am an authorized signatory for the Applicant and therefore declare;

a) b) in accordance with 47CFR2.911(d), all of the statements herein and the exhibits attached hereto are true and correct to the best of my knowledge and belief. in accepting a Grant of Equipment Authorization issued by a TCB, under the authority of the FCC, as a result of the representations made in this application, the Applicant is responsible for:

labeling the equipment with the exact FCC ID as specified in this application,

(1)

(2) compliance statement labeling pursuant to the applicable rules,

(3) compliance of the equipment with the applicable technical rules, c) d) e) if the Applicant is not the actual manufacturer of the equipment, appropriate arrangements have been made with the manufacturer to ensure that production units of this equipment will continue to comply with the FCCs technical requirements. in accordance with 47 CFR 2.909 and KDB394321, the Applicant has read, understood and agrees to accept that they are the responsible party and agree to abide by their responsibilities as specified under 47 CFR 2.909 and KDB394321. in accordance with ISO 17065, FCC KDB641163, FCC KDB610077, KDB394321 and RSP-100, the Applicant has read, understood, accepts and agrees to abide by the post market surveillance requirements.

(1)

(2)

(3) the Applicant understands, accepts and agrees that a sample may be requested for surveillance testing. the Applicant shall make provisions to always have a production sample available upon request by SGS, FCC and/or ISED. the Applicant shall, upon request by SGS, at the Applicants expense, provide a production sample of the requested product to SGS, FCC and/or ISED as instructed. The sample shall include all support devices, cables, software, accessories or other hardware or software required for evaluation, review, certification and audit surveillance of products certified by SGS. f) g) neither the Applicant nor any party to the application is subject to a denial of Federal benefits, that includes FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 862 because of a conviction for possession or distribution of a controlled substance. See 47CFR 1.2002(b) for the definition of a party for these purposes. the Applicant has read, understood, accepts and agrees to abide by the SGS North America, Inc.(TCB) terms and conditions. Link to CFRs: https://www.fcc.gov/wireless/bureau-divisions/technologies-systems-and-innovation-division/rules-regulations-title-47 Link to KDBs: https://apps.fcc.gov/oetcf/kdb/index.cfm Link to RSP-100: https://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf01130.html Link to the Covered List: Covered List

[Cypress Semiconductor] (the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules.

[Cypress Semiconductor] (the applicant) certifies that, as of the date of the filing of the application, the applicant [is not] identified on the Covered list, established pursuant to 1.50002, as an entity producing covered equipment. Applicant Signature:

Date: 2023/12/15 Print Name:

Juan Martinez Title:

Senior System Engineer

*NOTE: This declaration cannot be signed by an Agent, it shall be signed by an authorized person listed in the FCC database QSF27-14-04 Rev 1.0 Rev. Feb 6, 2023 Page 1 of 1 Original Issue: Jan. 4, 2021