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PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. n Overview: EZ-BLE Module Portfolio, Module Roadmap n EZ-BLE PRoC Product Overview n PRoC BLE Silicon Datasheet n Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are:
p AN96841 - Getting Started with EZ-BLE Module p AN94020 - Getting Started with PRoC BLE p AN97060 - PSoC 4 BLE and PRoC BLE - Over-The-Air p AN91445 - Antenna Design and RF Layout Guidelines p PRoC BLE Technical Reference Manual p KBA97095 - EZ-BLE Module Placement n Technical Reference Manual (TRM):
n Knowledge Base Articles p CYBLE-212006-EVAL, CYBLE-212006-01 Evaluation Board p CYBLE-202007-EVAL, CYBLE-202007-01 Evaluation Board p CYBLE-202013-EVAL, CYBLE-202013-11 Evaluation Board p CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer p CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit
(OTA) Device Firmware Upgrade (DFU) Guide n Development Kits:
Kit p AN91162 - Creating a BLE Custom Profile p AN91184 - PSoC 4 BLE - Designing BLE Applications p AN92584 - Designing for Low Power and Estimating Battery p AN85951 - PSoC 4 CapSense Design Guide p AN95089 - PSoC 4/PRoC BLE Crystal Oscillator Selec-
Life for BLE Applications tion and Tuning Techniques n Test and Debug Tools:
p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App) PSoC Creator Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC Components. PSoC Components are analog and digital virtual chips, represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. Bluetooth Low Energy Component The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. Technical Support n Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. n Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums. n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-15631 Rev.PRELIMINARY Page 2 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Contents Overview............................................................................ 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Power Supply Connections and Recommended External Components.................................................................... 10 Connection Options................................................... 10 External Component Recommendation .................... 10 Critical Components List ........................................... 13 Antenna Design......................................................... 13 Qualified Antenna for CYBLE-202007-01 and CY ......... BLE-202013-11 ................................................................ 13 Power Amplifier (PA) and Low Noise Amplifier (LNA) 13 Electrical Specification .................................................. 14 GPIO ......................................................................... 16 XRES......................................................................... 17 Digital Peripherals ..................................................... 20 Serial Communication ............................................... 22 Memory ..................................................................... 23 System Resources .................................................... 23 Environmental Specifications ....................................... 29 Environmental Compliance ....................................... 29 RF Certification.......................................................... 29 Safety Certification .................................................... 29 Environmental Conditions ......................................... 29 ESD and EMI Protection ........................................... 29 Regulatory Information.................................................. 30 FCC........................................................................... 30 Industry Canada (IC) Certification............................. 31 European R&TTE Declaration of Conformity ............ 31 MIC Japan................................................................. 32 KC Korea................................................................... 32 Packaging........................................................................ 33 Ordering Information...................................................... 35 Part Numbering Convention...................................... 35 Acronyms........................................................................ 36 Document Conventions ................................................. 36 Units of Measure ....................................................... 36 Document History Page................................................. 37 Sales, Solutions, and Legal Information ...................... 38 Worldwide Sales and Design Support....................... 38 Products .................................................................... 38 PSoC Solutions ...................................................... 38 Cypress Developer Community................................. 38 Technical Support ..................................................... 38 Document Number: 002-15631 Rev.PRELIMINARY Page 3 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Overview Module Description The CYBLE-2X20XX-X1 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Module dimensions Antenna location dimensions PCB thickness Shield height Maximum component height Length (X) Width (Y) Length (X) Width (Y) Height (H) Height (H) Height (H) Total module thickness (bottom of module to highest component) Height (H) Specification 15.00 0.15 mm 23.00 0.15 mm 15.00 0.15 mm 4.65 0.15 mm 0.80 0.10 mm 1.20 0.10 mm 1.20 mm typical (shield) - CYBLE-212006-01 1.25 mm typical (connector) - CYBLE-202007-01 0.75mm typical (crystal) - CYBLE-202013-11 2.00 mm typical - CYBLE-212006-01 2.05 mm typical - CYBLE-202007-01 1.55 mm typical - CYBLE-202013-11 See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2X20XX-X1. Document Number: 002-15631 Rev.PRELIMINARY Page 4 of 38 CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 PRELIMINARY Figure 1. Module Mechanical Drawing Top View (View from Top) Side View Bottom View (Seen from Bottom) Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3. Document Number: 002-15631 Rev.PRELIMINARY Page 5 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Pad Connection Interface As shown in the bottom view of Figure 1 on page 5, the CYBLE-2X20XX-X1 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2X20XX-X1 module. Table 2. Solder Pad Connection Description Name Connections Connection Type SP Solder Pads 30 Pad Length Dimension Pad Width Dimension 1.02 mm 0.71 mm Pad Pitch 1.27 mm Figure 2. Solder Pad Dimensions (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-2X20XX-X1 Antenna Document Number: 002-15631 Rev.PRELIMINARY Page 6 of 38 Host PCB Keep Out Area Around Trace Antenna PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Recommended Host PCB Layout Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-212006-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-2X20XX-X1 Figure 5. Module Pad Location from Origin Top View (On Host PCB) Top View (On Host PCB) Document Number: 002-15631 Rev.PRELIMINARY Page 7 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 3 provides the center location for each solder pad on the CYBLE-2X20XX-X1. All dimensions reference the to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location Solder Pad
(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Location (X,Y) from Orign (mm)
(0.38, 10.54)
(0.38, 11.81)
(0.38, 13.08)
(0.38, 14.35)
(0.38, 15.62)
(0.38, 16.89)
(0.38, 18.16)
(0.38, 19.43)
(0.38, 20.70)
(0.38, 21.97)
(2.32, 22.62)
(3.59, 22.62)
(4.86, 22.62)
(6.13, 22.62)
(7.40, 22.62)
(8.67, 22.62)
(9.94, 22.62)
(11.21, 22.62)
(12.48, 22.62)
(13.75, 22.62)
(14.62, 20.70)
(14.62, 19.43)
(14.62, 18.16)
(14.62, 16.89)
(14.62, 15.62)
(14.62, 14.35)
(14.62, 13.08)
(14.62, 11.81) See Figure 2 See Figure 2 Dimension from Orign (mils)
(14.96, 414.96)
(14.96, 464.96)
(14.96, 514.96)
(14.96, 564.96)
(14.96, 614.96)
(14.96, 664.96)
(14.96, 714.96)
(14.96, 764.96)
(14.96, 814.96)
(14.96, 864.96)
(91.34, 890.55)
(141.34, 890.55)
(191.34, 890.55)
(241.34, 890.55)
(291.34, 890.55)
(341.34, 890.55)
(391.34,8 90.55)
(441.34, 890.55)
(491.34, 890.55)
(541.34, 890.55
(575.59, 814.96)
(575.59, 764.96)
(575.59, 714.96)
(575.59, 664.96)
(575.59, 614.96)
(575.59, 564.96)
(575.59, 514.96)
(575.59, 464.96) See Figure 2 See Figure 2 Document Number: 002-15631 Rev.PRELIMINARY Page 8 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-2X20XX-X1, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3. Table 4. Solder Pad Connection Definitions Solder Pad UART SPI I2C TCPWM[2]
SWD GPIO Cap-
Sense WCO Out ECO Out LCD Number Device Port Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Ground Connection Reference Voltage Input (Optional) External Reset Hardware Connection Input 3(TCPWM0_P) 3(CMOD) 3(TCPWM3_N) 3(Sensor) 3 3(TCPWM3_P) 3(Sensor) 3(SCB1_SCL) 3(TCPWM2_N) 3(Sensor) 3(SCB1_SDA) 3(TCPWM2_P) 3(Sensor) GND XRES P4.0[3] 3(SCB1_RTS) 3(SCB1_MOSI) P3.7 3(SCB1_CTS) P3.6 3(SCB1_RTS) P3.5 3(SCB1_TX) P3.4 3(SCB1_RX) VREF 3(Sensor) P2.6 3(Sensor) P2.4 3(Sensor) 3 P2.3 3(Sensor) 3(SCB0_SS3) P2.2 3(Sensor) 3(SCB0_SS1) P2.0 3(TCPWM3_N) 3(Sensor) P1.7 3(SCB0_CTS) 3(SCB0_SCLK P1.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM3_P) 3(Sensor) P1.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2_N) 3(Sensor) P1.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2_P) 3(Sensor) 3(TCPWM2_N) 3(Sensor) P0.7 3(SCB0_CTS) 3(SCB0_SCLK 3(TCPWM0_P) 3(Sensor) P1.0 P0.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1_P) 3(Sensor) P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1_N) 3(Sensor) Digital Power Supply Input (1.8 to 5.5V) VDD P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2_P) 3(Sensor) GND[4]
Ground Connection Ground Connection GND Ground Connection GND GND Ground Connection VDDR ANT GND Radio Power Supply (2V to 3.6V) RF Pin to External Antenna Ground Connection 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3(SWDCLK) 3 3 3 3 3 3 3 3 3 3(SWDIO) 3 Notes 2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions. 3. When using the capacitive sensing functionality, Pad 3 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this 4. The main board needs to connect all GND connections (Pad 24/25/26/27) on the module to the common ground of the system. 5. capacitor is 2.2 nF and should be placed as close to the module as possible. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator. Document Number: 002-15631 Rev.PRELIMINARY Page 9 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Power Supply Connections and Recommended External Components Power Connections The CYBLE-2X20XX-X1 contains two power supply connec-
tions, VDD and VDDR. The VDD connection supplies power for both digital and analog device operation. The VDDR connection supplies power for the device radio. VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 2.0V to 3.6V. These specifications can be found in Table 12. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 10. The power supply ramp rate of VDD must be equal to or greater than that of VDDR. Connection Options Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply. 2. Independent supply: Power VDD and VDDR separately. External Component Recommendation In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-2X20XX-X1. Figure 8 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Figure 7. Recommended Host Schematic Options for a Single Supply Option Single Ferrite Bead Option Two Ferrite Bead Option Document Number: 002-15631 Rev.PRELIMINARY Page 10 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Figure 8. Recommended Host Schematic for an Independent Supply Option Document Number: 002-15631 Rev.PRELIMINARY Page 11 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 The CYBLE-2X20XX-X1 schematic is shown in Figure 9. Figure 9. CYBLE-2X20XX-X1 Schematic Diagram Document Number: 002-15631 Rev.PRELIMINARY Page 12 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Electrical Specification Table 10 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 10. CYBLE-2X20XX-X1 Absolute Maximum Ratings Typ Max Units Details/Conditions Parameter VDDD_ABS VCCD_ABS VDD_RIPPLE VGPIO_ABS IGPIO_ABS IGPIO_injection LU Description Analog, digital, or radio supply relative to VSS
(VSSD = VSSA) Direct digital core voltage input relative to VSSD Maximum power supply ripple for VDD and VDDR input voltage GPIO voltage Maximum current per GPIO GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS Pin current for latch up Min 0.5 0.5 0.5 25 0.5 200 Table 11 details the RF characteristics for the Cypress BLE module. Table 11. CYBLE-2X20XX-X1 RF Performance Characteristics Parameter Description Min Typ RFO RXS FR GP RL RF output power on ANT RF receive sensitivity on ANT Module frequency range Peak gain Return loss 1 2402 93 0.5 10 6 1.95 100 VDD +0.5 25 0.5 200 Max 7.5 2480 V Absolute maximum V mV Absolute maximum 3.0V supply Ripple frequency of 100 kHz to 750 kHz V Absolute maximum mA Absolute maximum mA Absolute maximum current mA injected per pin settings (CYBLE-212006-01) Units Details/Conditions dBm Configurable via register dBm Measured value MHz dBi dB
(CYBLE-212006-01) Table 12 through Table 51 list the module level electrical characteristics for the CYBLE-2X20XX-X1. All specifications are valid for 40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 12. CYBLE-2X20XX-X1 DC Specifications Power supply input voltage unregulated Parameter Description Power supply input voltage Radio supply voltage (radio on) Radio supply voltage (radio off) VDD1 VDD2 VDDR1 VDDR2 Active Mode, VDD = 1.71 V to 5.5 V IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 Execute from flash; CPU at 3 MHz Execute from flash; CPU at 3 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 12 MHz Execute from flash; CPU at 12 MHz Min 1.8 1.71 2.0 2.0 Typ 1.8 1.7 2.5 4 Max 5.5 1.89 3.6 3.6 Units Details/Conditions V With regulator enabled Internally unregulated supply V V V Restricted by RFX2401C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C Document Number: 002-15631 Rev.PRELIMINARY Page 14 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 12. CYBLE-2X20XX-X1 DC Specifications (continued) Parameter Description IMO on ECO on WDT with WCO on WDT with WCO on Execute from flash; CPU at 48 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 48 MHz IDD9 IDD10 IDD11 IDD12 Sleep Mode, VDD = 1.8 to 5.5 V IDD13 Sleep Mode, VDD and VDDR = 1.9 to 5.5 V IDD14 Deep-Sleep Mode, VDD = 1.8 to 3.6 V IDD15 IDD16 IDD17 IDD18 Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) IDD19 WDT with WCO on IDD20 WDT with WCO on Hibernate Mode, VDD = 1.8 to 3.6 V IDD27 GPIO and reset active IDD28 GPIO and reset active Hibernate Mode, VDD = 3.6 to 5.5 V IDD29 GPIO and reset active IDD30 Stop Mode, VDD = 1.8 to 3.6 V IDD33 Stop-mode current (VDD) GPIO and reset active WDT with WCO on WDT with WCO on Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) IDD34 IDD35 IDD36 Stop Mode, VDD = 3.6 to 5.5 V IDD37 Stop-mode current (VDD) IDD38 IDD39 IDD40 Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) Min Typ 7.1 13.4 1.5 150 20 40 Max
-
Details/Conditions Units mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz A T = 25 C, VDD = 3.3 V A T = 40 C to 85 C A T = 25 C, VDD = 5 V A T = 40 C to 85 C A T = 25 C A T = 40 C to 85 C nA T = 25 C, VDD = 3.3 V nA T = 40 C to 85 C nA T = 25 C, VDD = 5 V nA T = 40 C to 85 C nA T = 25 C, VDD = 3.3 V nA T = 25 C, nA T = 40 C to 85 C nA T = 40 C to 85 C, VDDR = 1.9 V to 3.6 V VDDR = 3.3 V nA T = 25 C, VDD = 5 V nA T = 25 C, VDDR = 5 V nA T = 40 C to 85 C nA T = 40 C to 85 C Document Number: 002-15631 Rev.PRELIMINARY Page 15 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 13. AC Specifications Parameter Description CPU frequency Wakeup from Sleep mode FCPU TSLEEP TDEEPSLEEP THIBERNATE TSTOP GPIO Table 14. GPIO DC Specifications Wakeup from Deep-Sleep mode Wakeup from Hibernate mode Wakeup from Stop mode Min DC Parameter Description Min
[6]
VIH VIL VOH VOL RPULLUP RPULLDOWN IIL IIL_CTBM CIN VHYSTTL VHYSCMOS IDIODE ITOT_GPIO Input voltage HIGH threshold LVTTL input, VDD < 2.7 V LVTTL input, VDD 2.7 V Input voltage LOW threshold LVTTL input, VDD < 2.7 V LVTTL input, VDD 2.7 V Output voltage HIGH level Output voltage HIGH level Output voltage LOW level Output voltage LOW level Output voltage LOW level Pull-up resistor Pull-down resistor Input leakage current (absolute value) Input leakage on CTBm input pins Input capacitance Input hysteresis LVTTL Input hysteresis CMOS Current through protection diode to VDD/VSS Maximum total source or sink chip current 0.7 VDD 0.7 VDD 2.0 VDD 0.6 VDD 0.5 3.5 3.5 25 0.05 VDD Typ 0 Typ 5.6 5.6 40 Max 48 25 2 2 Max 0.3 VDD 0.3 VDD 0.8 0.6 0.6 0.4 8.5 8.5 2 4 7 100 200 Units MHz s s ms ms Details/Conditions 1.71 V VDD 5.5 V Guaranteed by characterization 24-MHz IMO. Guaranteed by characterization Guaranteed by characterization XRES wakeup Units Details/Conditions V V V V V V V V V V V k k nA nA pF mV 1 A mA CMOS input CMOS input IOH = 4 mA at 3.3-V VDD IOH = 1 mA at 1.8-V VDD IOL = 8 mA at 3.3-V VDD IOL = 4 mA at 1.8-V VDD IOL = 3 mA at 3.3-V VDD 25 C, VDD = 3.3 V VDD > 2.7 V Note 6. VIH must not exceed VDD + 0.2 V. Document Number: 002-15631 Rev.PRELIMINARY Page 16 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 15. GPIO AC Specifications Parameter Description TRISEF TFALLF TRISES TFALLS FGPIOUT1 FGPIOUT2 FGPIOUT3 FGPIOUT4 FGPIOIN Rise time in Fast-Strong mode Fall time in Fast-Strong mode Rise time in Slow-Strong mode Fall time in Slow-Strong mode GPIO Fout; 3.3 V VDD 5.5 V Fast-Strong mode GPIO Fout; 1.7 V VDD 3.3 V Fast-Strong mode GPIO Fout; 3.3 V VDD 5.5 V Slow-Strong mode GPIO Fout; 1.7 V VDD 3.3 V Slow-Strong mode GPIO input operating frequency 1.71 V VDD 5.5 V Min 2 2 10 10 Typ Max 12 12 60 60 33 16.7 7 3.5 48 Units ns ns ns ns MHz MHz MHz MHz MHz Details/Conditions 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10% VIO Table 16. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Parameter Description Min Typ Max IIL VOL Input leakage (absolute value). VIH > VDD Output voltage LOW level Table 17. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Parameter TRISE_OVFS TFALL_OVFS TRISESS Description Output rise time in Fast-Strong mode Output fall time in Fast-Strong mode Output rise time in Slow-Strong mode TFALLSS FGPIOUT1 FGPIOUT2 Output fall time in Slow-Strong mode GPIO FOUT; 3.3 V VDD 5.5 V Fast-Strong mode GPIO FOUT; 1.71 V VDD 3.3 V Fast-Strong mode Min 1.5 1.5 10 10 Typ 10 0.4 Max 12 12 60 60 24 16 Units A V Details/Conditions 25C, VDD = 0 V, VIH = 3.0 V IOL = 20 mA, VDD > 2.9 V Units ns ns ns ns MHz MHz Details/Conditions 25-pF load, 10%90%, VDD = 3.3 V 25-pF load, 10%90%, VDD = 3.3 V 25 pF load, 10%-90%, VDD = 3.3 V 25 pF load, 10%-90%, VDD = 3.3 V 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle XRES Table 18. XRES DC Specifications Parameter Description Min VIH VIL RPULLUP CIN VHYSXRES IDIODE Input voltage HIGH threshold Input voltage LOW threshold Pull-up resistor Input capacitance Input voltage hysteresis Current through protection diode to VDD/VSS 0.7 VDDD 3.5 Typ 5.6 3 100 Max 0.3 VDDD 8.5 100 Units Details/Conditions CMOS input CMOS input V V k pF mV A Document Number: 002-15631 Rev.PRELIMINARY Page 17 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 19. XRES AC Specifications Parameter Description TRESETWIDTH Reset pulse width Temperature Sensor Table 20. Temperature Sensor Specifications Parameter TSENSACC Description Temperature-sensor accuracy SAR ADC Table 21. SAR ADC DC Specifications Parameter A_RES A_CHNIS_S Description Resolution Number of channels - single-ended A-CHNKS_D Number of channels - differential A-MONO Monotonicity A_GAINERR Gain error A_OFFSET Input offset voltage A_ISAR A_VINS A_VIND A_INRES A_INCAP Current consumption Input voltage range - single-ended Input voltage range - differential Input resistance Input capacitance VREFSAR Trimmed internal reference to SAR Min 1 Typ Max Units s Details/Conditions Min 5 Typ 1 Max 5 Units C Details/Conditions 40 C to +85 C Min VSS VSS 1 Typ Max 12 8 4 0.1 2 1 VDDA VDDA 2.2 10 1 Details/Conditions Units bits 8 full-speed Diff inputs use neighboring I/O Yes With external reference Measured with 1-V VREF Percentage of Vbg
(1.024 V)
%
mV mA V V k pF
%
Table 22. SAR ADC AC Specifications Parameter Description Min Typ Max Units Details/Conditions A_PSRR A_CMRR A_SAMP Fsarintref A_SNR A_BW A_INL A_INL A_INL A_dnl Power-supply rejection ratio Common-mode rejection ratio Sample rate SAR operating speed without external ref. bypass Signal-to-noise ratio (SNR) Input bandwidth without aliasing Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps 70 66 65 1.7 1.5 1.5 1 1 100 A_SAMP/2 2 1.7 1.7 2.2 dB dB Msps Ksps dB kHz LSB LSB LSB LSB Measured at 1-V reference 12-bit resolution FIN = 10 kHz VREF = 1 V to VDD VREF = 1.71 V to VDD VREF = 1 V to VDD VREF = 1 V to VDD Document Number: 002-15631 Rev.PRELIMINARY Page 18 of 38 PRELIMINARY Table 22. SAR ADC AC Specifications (continued) Parameter Description Min Typ A_DNL A_DNL A_THD Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps Total harmonic distortion CSD CSD Block Specifications Parameter VCSD IDAC1 IDAC1 IDAC2 IDAC2 SNR IDAC1_CRT1 IDAC1_CRT2 IDAC2_CRT1 IDAC2_CRT2 Description Voltage range of operation DNL for 8-bit resolution INL for 8-bit resolution DNL for 7-bit resolution INL for 7-bit resolution Ratio of counts of finger to noise Output current of IDAC1 (8 bits) in High range Output current of IDAC1 (8 bits) in Low range Output current of IDAC2 (7 bits) in High range Output current of IDAC2 (7 bits) in Low range 1 1 Min 1.71 1 3 1 3 5 Typ 612 306 305 153 Max 2 2.2 65 Max 5.5 1 3 1 3 CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Units LSB LSB dB Details/Conditions VREF = 1.71 V to VDD VREF = 1 V to VDD FIN = 10 kHz Units Details/Conditions V LSB LSB LSB LSB Ratio A A A A Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan Document Number: 002-15631 Rev.PRELIMINARY Page 19 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Digital Peripherals Timer Table 23. Timer DC Specifications Parameter Description ITIM1 ITIM2 ITIM3 Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Table 24. Timer AC Specifications Parameter TTIMFREQ TCAPWINT TCAPWEXT TTIMRES TTENWIDINT TTENWIDEXT TTIMRESWINT TTIMRESEXT Description Operating frequency Capture pulse width (internal) Capture pulse width (external) Timer resolution Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) Counter Table 25. Counter DC Specifications Parameter Description ICTR1 ICTR2 ICTR3 Table 26. Counter AC Specifications Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Parameter Description TCTRFREQ Operating frequency TCTRPWINT Capture pulse width (internal) TCTRPWEXT Capture pulse width (external) TCTRES Counter Resolution TCENWIDINT Enable pulse width (internal) TCENWIDEXT Enable pulse width (external) TCTRRESWINT Reset pulse width (internal) TCTRRESWEXT Reset pulse width (external) Min Min FCLK 2 TCLK 2 TCLK TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Min Min FCLK 2 TCLK 2 TCLK TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Typ Typ Typ Typ Max 42 130 535 Max 48 Max 42 130 535 Max 48 Units A A A Units MHz ns ns ns ns ns ns ns Units A A A Units MHz ns ns ns ns ns ns ns Details/Conditions 16-bit timer 16-bit timer 16-bit timer Details/Conditions Details/Conditions 16-bit counter 16-bit counter 16-bit counter Details/Conditions Document Number: 002-15631 Rev.PRELIMINARY Page 20 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Pulse Width Modulation (PWM) Table 27. PWM DC Specifications Parameter Description IPWM1 IPWM2 IPWM3 Table 28. PWM AC Specifications Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Parameter TPWMFREQ TPWMPWINT TPWMEXT TPWMKILLINT TPWMKILLEXT TPWMEINT TPWMENEXT TPWMRESWINT TPWMRESWEXT Description Operating frequency Pulse width (internal) Pulse width (external) Kill pulse width (internal) Kill pulse width (external) Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) LCD Direct Drive Table 29. LCD Direct Drive DC Specifications Description Parameter ILCDLOW CLCDCAP LCDOFFSET ILCDOP1 Operating current in low-power mode LCD capacitance per segment/common driver Long-term segment offset LCD system operating current, VBIAS = 5 V LCD system operating current, VBIAS = 3.3 V ILCDOP2 Table 30. LCD Direct Drive AC Specifications Description Parameter FLCD LCD frame rate Min Min FCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Min Typ Typ Typ 17.5 500 20 2 2 Max 42 130 535 Max 48 Max 5000 Units A A A Units MHz ns ns ns ns ns ns ns ns Details/Conditions 16-bit PWM 16-bit PWM 16-bit PWM Details/Conditions Units A Details/Conditions 16 4 small segment display at 50 Hz pF mV mA mA 32 4 segments. 50 Hz at 25 C 32 4 segments 50 Hz at 25 C Min 10 Typ 50 Max 150 Units Hz Details/Conditions Document Number: 002-15631 Rev.PRELIMINARY Page 21 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Serial Communication Table 31. Fixed I2C DC Specifications Parameter Description Block current consumption at 100 kHz Block current consumption at 400 kHz Block current consumption at 1 Mbps I2C enabled in Deep-Sleep mode II2C1 II2C2 II2C3 II2C4 Table 32. Fixed I2C AC Specifications Parameter FI2C1 Bit rate Description Table 33. Fixed UART DC Specifications Description Parameter IUART1 IUART2 Block current consumption at 100 kbps Block current consumption at 1000 kbps Table 34. Fixed UART AC Specifications Description Parameter FUART Bit rate Table 35. Fixed SPI DC Specifications Parameter ISPI1 ISPI2 ISPI3 Description Block current consumption at 1 Mbps Block current consumption at 4 Mbps Block current consumption at 8 Mbps Min Min Min Min Min Typ Typ Typ Typ Typ Max 50 155 390 1.4 Units A A A A Max 400 Units kHz Max 55 312 Units A A Details/Conditions Details/Conditions Details/Conditions Max 1 Units Mbps Details/Conditions Max 360 560 600 Units A A A Details/Conditions Table 36. Fixed SPI AC Specifications Parameter FSPI Description SPI operating frequency (master; 6x over sampling) Min Typ Max 8 Units MHz Details/Conditions Table 37. Fixed SPI Master Mode AC Specifications Parameter Description TDMO TDSI THMO MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge Full clock, late MISO sampling used Previous MOSI data hold time Min 20 0 Table 38. Fixed SPI Slave Mode AC Specifications Parameter Description TDMI TDSO TDSO_ext THSO TSSELSCK MOSI valid before SCLK capturing edge MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V Previous MISO data hold time SSEL valid to first SCK valid edge Typ Max Units 18 ns Details/Conditions ns ns Full clock, late MISO sampling Referred to Slave capturing edge Min 40 0 100 Typ Max 42 + 3 TCPU 50 Units ns ns ns ns ns Document Number: 002-15631 Rev.PRELIMINARY Page 22 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Memory Table 39. Flash DC Specifications Parameter Description VPE TWS48 TWS32 TWS16 Erase and program voltage Number of Wait states at 3248 MHz Number of Wait states at 1632 MHz Number of Wait states for 016 MHz Table 40. Flash AC Specifications Parameter
[7]
TROWWRITE
[7]
TROWERASE TROWPROGRAM
[7]
TBULKERASE
[7]
TDEVPROG FEND FRET FRET2 Description Row (block) write time (erase and program) Row erase time
[7] Row program time after erase Bulk erase time (256 KB) Total device program time Flash endurance Flash retention. TA 55 C, 100 K P/E cycles Flash retention. TA 85 C, 10 K P/E cycles System Resources Power-on-Reset (POR) Table 41. POR DC Specifications Parameter VRISEIPOR VFALLIPOR VIPORHYST Description Rising trip voltage Falling trip voltage Hysteresis Table 42. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 43. Brown-Out Detect Parameter VFALLPPOR VFALLDPSLP Description BOD trip voltage in Active and Sleep modes BOD trip voltage in Deep Sleep Table 44. Hibernate Reset Min 1.71 2 1 0 Min 100 K 20 10 Min 0.80 0.75 15 Min Min 1.64 1.4 Typ Typ Typ Typ Typ Max 5.5 Max 20 13 7 35 25 Max 1.45 1.40 200 Max 1 Max Units V Details/Conditions CPU execution from flash CPU execution from flash CPU execution from flash Units ms ms ms ms seconds cycles years years Details/Conditions Row (block) = 256 bytes Units Details/Conditions V V mV Units s Details/Conditions Units Details/Conditions V V Parameter VHBRTRIP Description BOD trip voltage in Hibernate Min 1.1 Typ Max Units V Details/Conditions Note 7. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-15631 Rev.PRELIMINARY Page 23 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Min 1.71 1.76 1.85 1.95 2.05 2.15 2.24 2.34 2.44 2.54 2.63 2.73 2.83 2.93 3.12 4.39 Min Min 0.25 T 0.25 T 1 Typ 1.75 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.20 4.50 Typ Typ Max 1.79 1.85 1.95 2.05 2.15 2.26 2.36 2.46 2.56 2.67 2.77 2.87 2.97 3.08 3.28 4.61 100 Units Details/Conditions V V V V V V V V V V V V V V V V A Max 1 Units s Details/Conditions Max 14 7 0.5 T Units MHz MHz ns ns ns ns Details/Conditions SWDCLK 1/3 CPU clock frequency SWDCLK 1/3 CPU clock frequency Voltage Monitors (LVD) Table 45. Voltage Monitor DC Specifications Parameter Description VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 VLVI10 VLVI11 VLVI12 VLVI13 VLVI14 VLVI15 VLVI16 LVI_IDD LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b Block current Table 46. Voltage Monitor AC Specifications Parameter TMONTRIP Description Voltage monitor trip time SWD Interface Table 47. SWD Interface Specifications Description 3.3 V VDD 5.5 V 1.71 V VDD 3.3 V Parameter F_SWDCLK1 F_SWDCLK2 T_SWDI_SETUP T = 1/f SWDCLK T_SWDI_HOLD T = 1/f SWDCLK T_SWDO_VALID T = 1/f SWDCLK T_SWDO_HOLD T = 1/f SWDCLK Document Number: 002-15631 Rev.PRELIMINARY Page 24 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Internal Main Oscillator Table 48. IMO DC Specifications Parameter Description IIMO1 IIMO2 IIMO3 IIMO4 IIMO5 IMO operating current at 48 MHz IMO operating current at 24 MHz IMO operating current at 12 MHz IMO operating current at 6 MHz IMO operating current at 3 MHz Table 49. IMO AC Specifications Parameter FIMOTOL3 FIMOTOL3 Description Frequency variation from 3 to 48 MHz IMO startup time Internal Low-Speed Oscillator Table 50. ILO DC Specifications Parameter IILO2 Description ILO operating current at 32 kHz Table 51. ILO AC Specifications Parameter TSTARTILO1 FILOTRIM1 Description ILO startup time 32-kHz trimmed frequency Table 52. ECO Trim Value Specification Description Parameter ECOTRIM 24-MHz trim value
(firmware configuration) BLE Subsystem Table 53. BLE Subsystem Min Min Min Min 15 Typ Typ 12 Typ 0.3 Typ 32 Max 1000 325 225 180 150 Max 2 Units A A A A A Units
%
s Details/Conditions Details/Conditions With API-called calibration Max 1.05 Units A Details/Conditions Max 2 50 Units ms kHz Details/Conditions Value Details/Conditions 0x00007FDC Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Parameter Description Min Typ Max Units Details/Conditions RF Receiver Specification RXS, IDLE RX sensitivity with idle transmitter RX sensitivity with idle transmitter excluding Balun loss RXS, DIRTY RX sensitivity with dirty transmitter RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter PRXMAX Maximum input power CI1 Cochannel interference, Wanted signal at 67 dBm and Interferer at FRX 10 89 91 87 91 1 9 70 21 dBm dBm dBm dBm dBm dB Guaranteed by design simulation RF-PHY Specification
(RCV-LE/CA/01/C) RF-PHY Specification
(RCV-LE/CA/06/C) RF-PHY Specification
(RCV-LE/CA/03/C) Document Number: 002-15631 Rev.PRELIMINARY Page 25 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 53. BLE Subsystem (continued) Parameter Description Min Typ Max Units Details/Conditions 3 15 CI2 CI3 CI4 CI5 CI3 OBB1 OBB2 OBB3 OBB4 IMD RXSE1 RXSE2 Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 1 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 2 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 3 MHz Adjacent channel interference Wanted Signal at 67 dBm and Interferer at Image frequency (FIMAGE) Adjacent channel interference Wanted signal at 67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 302000 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 20032399 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 24842997 MHz Out-of-band blocking, Wanted signal a 67 dBm and Interferer at F = 300012750 MHz Inter modulation performance Wanted signal at 64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel Receiver spurious emission 30 MHz to 1.0 GHz Receiver spurious emission 1.0 GHz to 12.75 GHz RF Transmitter Specifications TXP, ACC TXP, RANGE TXP, 0dBm RF power accuracy RF power control range Output power, 0-dB Gain setting (PA7) Output power, maximum power setting
(PA10) Output power, minimum power setting
(PA1) Average frequency deviation for 10101010 pattern Average frequency deviation for 11110000 pattern TXP, MAX TXP, MIN F2AVG F1AVG Document Number: 002-15631 Rev.PRELIMINARY 50 185 225 30 27 35 27 35 27 30 27 29 39 20 30 1 20 0 3 18 57 47 250 275 dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dB dB dBm dBm dBm kHz kHz RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/05/C) 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/05/C) Page 26 of 38 PRELIMINARY Table 53. BLE Subsystem (continued) Parameter Description EO Eye opening = F2AVG/F1AVG FTX, ACC Frequency accuracy FTX, MAXDR Maximum frequency drift FTX, INITDR Initial frequency drift FTX, DR Maximum drift rate IBSE1 IBSE2 TXSE1 TXSE2 In-band spurious emission at 2-MHz offset In-band spurious emission at 3-MHz offset Transmitter spurious emissions
(average), <1.0 GHz Transmitter spurious emissions
(average), >1.0 GHz RF Current Specifications IRX IRX_RF IRX, HIGHGAIN ITX, 3dBm ITX, 0dBm ITX_RF, 0dBm ITX_RF, 0dBm ITX,-3dBm ITX,-6dBm ITX,-12dBm ITX,-18dBm Receive current in normal mode Radio receive current in normal mode Receive current in high-gain mode TX current at 3-dBm setting (PA10) TX current at 0-dBm setting (PA7) Radio TX current at 0 dBm setting (PA7) Radio TX current at 0 dBm excluding Balun loss TX current at 3-dBm setting (PA4) TX current at 6-dBm setting (PA3) TX current at 12-dBm setting (PA2) TX current at 18-dBm setting (PA1) Iavg_1sec, 0dBm Average current at 1-second BLE connection interval Iavg_4sec, 0dBm Average current at 4-second BLE connection interval General RF Specifications FREQ CHBW DR RF operating frequency Channel spacing On-air data rate Min 0.8 150 50 20 20 Typ 18.7 16.4 21.5 20 16.5 15.6 14.2 15.5 14.5 13.2 12.5 17.1 6.1 Max 150 50 20 20 20
-30
-55.5
-41.5 CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Units kHz kHz kHz kHz/
50 s dBm dBm Details/Conditions RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/03/C) RF-PHY Specification
(TRM-LE/CA/03/C) dBm FCC-15.247 dBm FCC-15.247 mA mA mA mA mA mA mA mA mA mA mA A A Measured at VDDR Measured at VDDR Guaranteed by design simulation TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange 2400 2 1000 2482 MHz MHz kbps Document Number: 002-15631 Rev.PRELIMINARY Page 27 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Table 53. BLE Subsystem (continued) Parameter IDLE2TX IDLE2RX RSSI Specifications RSSI, ACC RSSI, RES RSSI, PER Description BLE.IDLE to BLE. TX transition time BLE.IDLE to BLE. RX transition time RSSI accuracy RSSI resolution RSSI sample period Min Typ 120 75 5 1 6 Max 140 120 Units s s dB dB s Details/Conditions Document Number: 002-15631 Rev.PRELIMINARY Page 28 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-212006-01 and CYBLE-202007-01 modules will be certified under the following RF certification standards at production release. n FCC: WAP2006 n CE n IC: 7922A-2006 n MIC: TBD n KC: TBD Safety Certification The CYBLE-212006-01 and CYBLE-202007-01 modules comply with the following regulations:
n Underwriters Laboratories, Inc. (UL) - Filing E331901 n CSA n TUV Environmental Conditions Table 54 describes the operating and storage conditions for the Cypress BLE module. Table 54. Environmental Conditions for CYBLE-2X20XX-X1 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[8]
40 C 5%
40 C 85 C 85%
3 C/minute 85 C 85 C at 85%
15 kV Air 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 8. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-15631 Rev.PRELIMINARY Page 29 of 38 RF Exposure distance of the device is 15mm. RF Exposure distance of the device is 15mm. la distance d'exposition RF de l'appareil est de 15mm. PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 MIC Japan CYBLE-212006-01 and CYBLE-202007-01 are certified as a module with type certification number TBD. End products that integrate CYBLE-212006-01 and CYBLE-202007-01 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-212006-01 and CYBLE-202007-01 are certified for use in Korea with certificate number TBD. Document Number: 002-15631 Rev.PRELIMINARY Page 32 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Packaging Table 55. Solder Reflow Peak Temperature Module Part Number CYBLE-2X20XX-X1 Package 30-pad SMT Maximum Peak Temperature 260 C Maximum Time at Peak Temperature 30 seconds No. of Cycles 2 Table 56. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBLE-2X20XX-X1 Package 30-pad SMT MSL MSL 3 The CYBLE-2X20XX-X1 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-2X20XX-X1. Figure 10. CYBLE-2X20XX-X1 Tape Dimensions Figure 11 details the orientation of the CYBLE-2X20XX-X1 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction (Illustration Only) - TBD Document Number: 002-15631 Rev.PRELIMINARY Page 33 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Figure 12 details reel dimensions used for the CYBLE-2X20XX-X1. Figure 12. Reel Dimensions The CYBLE-2X20XX-X1 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-2X20XX-X1 is detailed in Figure 13. Figure 13. CYBLE-2X20XX-X1 Center of Mass (Seen from Top) - TBD Document Number: 002-15631 Rev.PRELIMINARY Page 34 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Ordering Information Table 57 lists the CYBLE-2X20XX-X1 part numbers and features. Table 57. Ordering Information Part Number CPU Speed
(MHz) CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 48 48 48 Flash Size
(KB) 256 256 256 CapSense SCB TCPWM Yes Yes Yes 2 2 2 4 4 4 12-Bit SAR ADC 1 Msps Yes Yes 1 Msps Yes Yes 1 Msps Yes Yes I2S LCD Package Packing Certified 30-SMT Tape and Reel 30-SMT Tape and Reel 30-SMT Tape and Reel Yes Yes No Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-15631 Rev.PRELIMINARY Page 35 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Document Conventions Units of Measure Table 59. Units of Measure Symbol C kV mA mm mV A m MHz GHz V Unit of Measure degree Celsius kilovolt milliamperes millimeters millivolt microamperes micrometers megahertz gigahertz volt Description Bluetooth Low Energy Bluetooth Special Interest Group Acronyms Table 58. Acronyms Used in this Document Acronym BLE Bluetooth SIG CE CSA EMI ESD FCC GPIO IC IDE KC European Conformity Canadian Standards Association electromagnetic interference electrostatic discharge Federal Communications Commission general-purpose input/output Industry Canada integrated design environment Korea Certification Ministry of Internal Affairs and Communications
(Japan) printed circuit board receive qualification design ID surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs MIC PCB RX QDID SMT TCPWM timer, counter, pulse width modulator (PWM) TUV TX Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit Document Number: 002-15631 Rev.PRELIMINARY Page 36 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Document History Page Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE PRoC 4.2 XR Module Document Number: 002-09764 Orig. of Revision Change Description of Change Submission Date ECN
**
PRELIM-
INARY MINS PRELIM-
INARY Preliminary datasheet for CYBLE-212006-01, CYBLE-202007-01 and CYBLE-202013-11module. Document Number: 002-15631 Rev.PRELIMINARY Page 37 of 38 PRELIMINARY CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/powerpsoc cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-15631 Rev.PRELIMINARY Revised July 28, 2016 Page 38 of 38
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2016-08-29 | 2402 ~ 2480 | DTS - Digital Transmission System | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2016-08-29
|
||||
1 | Applicant's complete, legal business name |
Cypress Semiconductor
|
||||
1 | FCC Registration Number (FRN) |
0017759150
|
||||
1 | Physical Address |
198 Champion Court
|
||||
1 |
San Jose, California 95134
|
|||||
1 |
United States
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
V******@tuvam.com
|
||||
1 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
WAP
|
||||
1 | Equipment Product Code |
2006
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
D**** S********
|
||||
1 | Title |
Sr. Business Unit Director
|
||||
1 | Telephone Number |
408-5********
|
||||
1 | Fax Number |
408-5********
|
||||
1 |
d******@cypress.com
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DTS - Digital Transmission System | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Bluetooth Module | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Single Modular Approval | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Modular Approval. Output power is peak conducted. | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
DEKRA Testing and Certification (Suzhou) Co., Ltd.
|
||||
1 | Name |
J******** P********
|
||||
1 | Telephone Number |
86-51******** Extension:
|
||||
1 | Fax Number |
86-51********
|
||||
1 |
j******@quietek.com.cn
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0069000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC