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User Manual | Users Manual | 4.35 MiB | June 09 2016 | |||
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User Manual II | Users Manual | 1.24 MiB | November 12 2015 | |||
| 1 2 | Cover Letter(s) | June 09 2016 | ||||||
| 1 2 | Cover Letter(s) | November 09 2016 / June 09 2016 | ||||||
| 1 2 | External Photos | June 09 2016 | ||||||
| 1 2 | Internal Photos | June 09 2016 | ||||||
| 1 2 | ID Label/Location Info | June 09 2016 | ||||||
| 1 2 | RF Exposure Info | June 09 2016 | ||||||
| 1 2 | Test Report | June 09 2016 | ||||||
| 1 2 | Test Setup Photos | June 09 2016 | ||||||
| 1 2 | Cover Letter(s) | November 12 2015 | ||||||
| 1 2 | Cover Letter(s) | November 12 2015 | ||||||
| 1 2 | Cover Letter(s) | November 12 2015 |
| 1 2 | User Manual | Users Manual | 4.35 MiB | June 09 2016 |
PRELIMINARY CYBLE-214015-01 EZ-BLE PSoC Module General Description The Cypress CYBLE-214015-01 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-214015-01 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC 4 BLE. Refer to the PSoC 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module. The EZ-BLE PSoC module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-214015-01 also includes digital programmable high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The CYBLE-214015-01 includes a royalty-free BLE stack compatible with Bluetooth 4.2 and provides up to 25 GPIOs in a small 11 11 1.80 mm package. The CYBLE-214015-01 is drop-in the CYBLE-014008-00 and CYBLE-214009-00 EZ-BLE Modules. The CYBLE-214015-01 is a complete solution and an ideal fit for applications seeking a highly integrated BLE wireless solution. Module Description n Module size: 11.0 mm 11.0 mm 1.80 mm (with shield) n Drop-in compatible with CYBLE-014008-00 and compatible with logic, CYBLE-214009-00 n 256-KB flash memory, 32-KB SRAM memory n Up to 25 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output n Bluetooth 4.2 qualified single-mode module p QDID: 79480 p Declaration ID: D029646 n Certified to FCC, CE, MIC, KC, and IC regulations n Industrial temperature range: 40 C to +85 C n 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz n Watchdog timer with dedicated internal low-speed oscillator
(ILO) n Two-pin SWD for programming Power Consumption n TX output power: 18 dbm to +3 dbm n Received signal strength indicator (RSSI) with 1-dB resolution n TX current consumption of 15.6 mA (radio only, 0 dbm) n RX current consumption of 16.4 mA (radio only) n Low power mode support p Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on p Hibernate: 150 nA with SRAM retention p Stop: 60 nA with XRES wakeup Programmable Analog n Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode n 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging n Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin n One low-power comparator that operate in Deep-Sleep mode Programmable Digital n Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and datapath n Cypress-provided peripheral Component library, user-defined state machines, and Verilog input Capacitive Sensing n Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance n Cypress-supplied software component makes capacitive-sensing design easy n Automatic hardware-tuning algorithm (SmartSense) Segment LCD Drive n LCD drive supported on all GPIOs (common or segment) n Operates in Deep-Sleep mode with four bits per pin memory Serial Communication n Two independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionality Timing and Pulse-Width Modulation n Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks n Center-aligned, Edge, and Pseudo-random modes n Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 25 Programmable GPIOs n Any GPIO pin can be CapSense, LCD, analog, or digital Cypress Semiconductor Corporation Document Number: 002-15923 Rev. **
198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised August 18, 2016 PRELIMINARY CYBLE-214015-01 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. n Overview: EZ-BLE Module Portfolio, Module Roadmap n EZ-BLE PSoC Product Overview n PSoC 4 BLE Silicon Datasheet n Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are:
p AN96841 - Getting Started with EZ-BLE Module p AN94020 - Getting Started with PSoC 4 BLE p AN97060 - PSoC 4 BLE and PRoC BLE - Over-The-Air p PSoC 4 BLE Technical Reference Manual p PSOC(R) 4 BLE Registers Technical Reference Manual p KBA97095 - EZ-BLE Module Placement p KBA213976 - FAQ for BLE and Regulatory Certifications with p KBA210802 - Queries on BLE Qualification and Declaration n Technical Reference Manual (TRM):
n Knowledge Base Articles EZ-BLE modules Processes
(OTA) Device Firmware Upgrade (DFU) Guide p AN91162 - Creating a BLE Custom Profile p AN91184 - PSoC 4 BLE - Designing BLE Applications p AN92584 - Designing for Low Power and Estimating Battery p AN85951 - PSoC 4 CapSense Design Guide p AN95089 - PSoC 4/PRoC BLE Crystal Oscillator Life for BLE Applications Selection and Tuning Techniques p AN91445 - Antenna Design and RF Layout Guidelines
(TRM) n Development Kits:
p CYBLE-214015-EVAL, CYBLE-214015-01 Evaluation Board p CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer p CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit Kit n Test and Debug Tools:
p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App) PSoC Creator Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC Components. PSoC Components are analog and digital virtual chips, represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. Bluetooth Low Energy Component The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. Technical Support n Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. n Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums. n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-15923 Rev. **
Page 2 of 42 PRELIMINARY CYBLE-214015-01 Contents Overview ............................................................................4 Module Description ......................................................4 Pad Connection Interface ................................................6 Recommended Host PCB Layout ...................................7 Power Supply Connections and Recommended External Components ....................................................11 Connection Options ...................................................11 External Component Recommendation ....................11 Critical Components List ...........................................14 Antenna Design .........................................................14 Electrical Specification ..................................................15 GPIO .........................................................................17 XRES .........................................................................18 Analog Peripherals ....................................................18 Digital Peripherals .....................................................22 Serial Communication ...............................................24 Memory .....................................................................25 System Resources ....................................................25 Environmental Specifications .......................................31 Environmental Compliance .......................................31 RF Certification .......................................................... 31 Environmental Conditions ......................................... 31 ESD and EMI Protection ........................................... 31 Regulatory Information .................................................. 32 FCC ........................................................................... 32 Industry Canada (IC) Certification ............................. 33 European R&TTE Declaration of Conformity ............ 33 MIC Japan ................................................................. 34 KC Korea ................................................................... 34 Packaging ........................................................................ 35 Ordering Information ...................................................... 37 Part Numbering Convention ...................................... 37 Acronyms ........................................................................ 38 Document Conventions ................................................. 40 Units of Measure ....................................................... 40 Document History Page ................................................. 41 Sales, Solutions, and Legal Information ...................... 42 Worldwide Sales and Design Support ....................... 42 Products .................................................................... 42 PSoC Solutions ...................................................... 42 Cypress Developer Community ................................. 42 Technical Support ..................................................... 42 Document Number: 002-15923 Rev. **
Page 3 of 42 PRELIMINARY CYBLE-214015-01 Overview Module Description The CYBLE-214015-01 module is a complete module designed to be soldered to the main host board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna location dimensions Length (X) Width (Y) Length (X) Width (Y) Height (H) PCB thickness Height (H) Shield height Maximum component height Height (H) Total module thickness (bottom of module to highest component) Height (H) 11.00 0.15 mm 11.00 0.15 mm 11.00 0.15 mm 4.62 0.15 mm 0.80 0.10 mm 1.00 0.10 mm 1.00 mm typical (shield) 1.80 mm typical See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-214015-01. Document Number: 002-15923 Rev. **
Page 4 of 42 PRELIMINARY CYBLE-214015-01 Figure 1. Module Mechanical Drawing Top View Side View Bottom View Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 on page 6, Figure 4 and Figure 5 on page 7, and Figure 6 and Table 3 on page 8. Document Number: 002-15923 Rev. **
Page 5 of 42 PRELIMINARY CYBLE-214015-01 Pad Connection Interface As shown in the bottom view of Figure 1 on page 5, the CYBLE-214015-01 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-214015-01 module. Table 2. Solder Pad Connection Description Name Connections Connection Type SP 32 Solder Pads Pad Length Dimension Pad9/Pad24: 0.74 mm All Others: 0.79 mm Pad Width Dimension 0.41 mm Pad Pitch 0.66 mm Figure 2. Solder Pad Dimensions (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. Please refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-214015-01 Trace Antenna Document Number: 002-15923 Rev. **
Page 6 of 42 Host PCB Keep-Out Area Around Trace Antenna PRELIMINARY CYBLE-214015-01 Recommended Host PCB Layout Figure 4 through Figure 6 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-214015-01. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-214015-01 Figure 5. Module Pad Location from Origin Document Number: 002-15923 Rev. **
Page 7 of 42 PRELIMINARY CYBLE-214015-01 Table 3 provides the center location for each solder pad on the CYBLE-214015-01. All dimensions reference the to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location Solder Pad
(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Location (X,Y) from Orign (mm)
(0.30, 4.83)
(0.30, 5.49)
(0.30, 6.15)
(0.30, 6.81)
(0.30, 7.47)
(0.30, 8.13)
(0.30, 8.79)
(0.30, 9.45)
(0.27, 10.11)
(1.21, 10.70)
(1.87, 10.70)
(2.53, 10.70)
(3.19, 10.70)
(3.85, 10.70)
(4.51, 10.70)
(5.17, 10.70)
(5.84, 10.70)
(6.50, 10.70)
(7.16, 10.70)
(7.82, 10.70)
(8.48, 10.70)
(9.14, 10.70)
(9.80, 10.70)
(10.73, 10.11)
(10.70, 9.45)
(10.70, 8.79)
(10.70, 8.13)
(10.70, 7.47)
(10.70, 6.81)
(10.70, 6.15)
(10.70, 5.49)
(10.70, 4.83) Dimension from Orign (mils)
(11.81, 190.16)
(11.81, 216.14)
(11.81, 242.13)
(11.81, 268.11)
(11.81, 294.09)
(11.81, 320.08)
(11.81, 346.06)
(11.81, 372.05)
(10.63, 398.03)
(47.64, 421.26)
(73.62, 421.26)
(99.61, 421.26)
(125.59, 421.26)
(151.57, 421.26)
(177.56, 421.26)
(203.54, 421.26)
(229.92, 421.26)
(255.91, 421.26)
(281.89, 421.26)
(307.87, 421.26)
(333.86, 421.26)
(359.84, 421.26)
(385.83, 421.26)
(422.44, 398.03)
(421.26, 372.05)
(421.26, 346.06)
(421.26, 320.08)
(421.26, 294.09)
(421.26, 268.11)
(421.26, 242.13)
(421.26, 216.14)
(421.26, 190.16) Document Number: 002-15923 Rev. **
Page 8 of 42 PRELIMINARY CYBLE-214015-01 Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-214015-01, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3. Table 4. Digital Peripheral Capabilities I2C SPI UART Device Port Pin GND[3]
Ground Connection 3(TCPWM0_N) 3 P1.1 3(TCPWM0_P) 3 P1.0 P1.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2_N) 3 P0.1 3(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0_N) 3 P0.7 3(SCB0_CTS) 3(SCB0_SCLK) 3(TCPWM2_N) 3 3(SCB1_SS1) TCPWM[2]
Cap Sense 3 3 3 3 3 WCO Out ECO OUT LCD SWD GPIO VDD P1.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2_P) 3 P0.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1_P) 3 P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1_N) 3 P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2_P) 3 Digital Power Supply Input (1.71 to 5.5V) 3 3 3 3 3 P1.2 VDDR P2.6 P1.3 P3.0 3(SCB0_RX) P2.1 P2.2 P2.3 VDDA P3.4 3(SCB1_RX) P3.1 3(SCB0_TX) P3.7 3(SCB1_CTS) P3.5 3(SCB1_TX) P3.3 3(SCB0_CTS) VREF P3.2 3(SCB0_RTS) P3.6 3(SCB1_RTS) XRES P2.4 P2.5 GND[3]
3(SCB1_SS2) 3(SCB1_SS3) 3(SCB0_SS2) 3(SCB0_SS3) 3(TCPWM1_P) 3 Radio Power Supply (1.9V to 5.5V) 3 3(TCPWM1_N) 3 3(SCB0_SDA) 3(TCPWM0_P) 3 3 3 3 Analog Power Supply Input (1.71 to 5.5V) 3(SCB1_SDA) 3(TCPWM2_P) 3 3(SCB0_SCL) 3(TCPWM0_N) 3 3(TCPWM3_N) 3 3(SCB1_SCL) 3(TCPWM2_N) 3 3(TCPWM1_N) 3 3 3 Reference Voltage Input 3(TCPWM1_P) 3 3(TCPWM3_P) 3 External Reset Hardware Connection Input 3 3 Ground Connection 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
(SWDCLK) 3
(SWDIO) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system. Document Number: 002-15923 Rev. **
Page 9 of 42 PRELIMINARY CYBLE-214015-01 Table 5. Analog Peripheral Capabilities Pad Number Device Port Pin SARMUX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND[3]
P1.1 P1.0 P1.5 P0.1 P0.7 VDD P1.4 P0.4 P0.5 P0.6 P1.2 VDDR P2.6 P1.3 P3.0 P2.1 P2.2 P2.3 VDDA P3.4 P3.1 P3.7 P3.5 P3.3 VREF P3.2 P3.6 XRES P2.4 P2.5 GND OPAMP Ground Connection 3(CTBm1_OA0_INN) 3(CTBm1_OA0_INP) 3(CTBm1_OA1_INP) LPCOMP Digital Power Supply Input (1.71 to 5.5V) 3(CTBm1_OA1_INN) 3(COMP1_INP) 3(COMP1_INN) 3 3 3 3 3 3 3 3 3(CTBm1_OA0_OUT) Radio Power Supply (1.9V to 5.5V) 3(CTBm1_OA0_INP) 3(CTBm1_OA1_OUT) 3(CTBm1_OA0_INN) 3(CTBm1_OA0_OUT) 3(CTBm1_OA1_OUT) Analog Power Supply Input (1.71 to 5.5V) Reference Voltage Input (Optional) External Reset Hardware Connection Input 3(CTBm1_OA1_INN) 3(CTBm1_OA1_INP) Ground Connection Document Number: 002-15923 Rev. **
Page 10 of 42 PRELIMINARY CYBLE-214015-01 Power Supply Connections and Recommended External Components Power Connections The CYBLE-214015-01 contains three power supply connec-
tions, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respec-
tively. VDDR supplies power for the device radio. VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 10. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 8. The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used. Connection Options Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same External Component Recommendation In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-214015-01. Figure 8 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz (Murata BLM21PG331SN1D). supply. 2. Independent supply: Power VDD, VDDA, and VDDR separately. Figure 7. Recommended Host Schematic Options for Single Supply Option Single Ferrite Bead Option Three Ferrite Bead Option Document Number: 002-15923 Rev. **
Page 11 of 42 PRELIMINARY CYBLE-214015-01 Figure 8. Recommended Host Schematic for Independent Supply Option Document Number: 002-15923 Rev. **
Page 12 of 42 PRELIMINARY CYBLE-214015-01 The CYBLE-214015-01 schematic is shown in Figure 9. Figure 9. CYBLE-214015-01 Schematic Diagram Document Number: 002-15923 Rev. **
Page 13 of 42 PRELIMINARY CYBLE-214015-01 Critical Components List Table 6 details the critical components used in the CYBLE-214015-01 module. Table 6. Critical Component List Component Reference Designator Description U1 Y1 Y2 Silicon Crystal Crystal Antenna Design Table 7 details antenna used on the CYBLE-214015-01 module. The Cypress module performance improves many of these characteristics. For more information, see Table 9 on page 15. Table 7. Trace Antenna Specifications 76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE 24.000 MHz, 10PF 32.768 kHz, 12.5PF Item Description Frequency Range Peak Gain Average Gain Return Loss 2400 2500 MHz
-0.5 dBi typical
-0.5 dBi typical 10 dB minimum Document Number: 002-15923 Rev. **
Page 14 of 42 PRELIMINARY CYBLE-214015-01 Electrical Specification Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 8. CYBLE-214015-01 Absolute Maximum Ratings Parameter VDDD_ABS VCCD_ABS VDDD_RIPPLE VGPIO_ABS IGPIO_ABS IGPIO_injection LU Description VDD, VDDA or VDDR supply relative to VSS
(VSSD = VSSA) Direct digital core voltage input relative to VSSD Maximum power supply ripple for VDD, VDDA and VDDR input voltage GPIO voltage Maximum current per GPIO GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS Pin current for latch up Table 9 details the RF characteristics for the Cypress BLE module. Table 9. CYBLE-214015-01 RF Performance Characteristics Parameter Description RFO RXS FR GP GAvg RL RF output power on ANT RF receive sensitivity on ANT Module frequency range Peak gain Average gain Return loss Min 0.5 0.5 0.5 25 0.5 200 Min 18 2400 Typ Max Unit Details/Conditions Typ 0 87
-0.5 0.5 10 6 1.95 100 VDD +0.5 25 0.5 200 Max 3 2480 V Absolute maximum V mV Absolute maximum 3.0V supply Ripple frequency of 100 kHz to 750 kHz V Absolute maximum mA Absolute maximum mA Absolute maximum current mA injected per pin settings simulation Unit Details/Conditions dBm Configurable via register dBm Guaranteed by design MHz dBi dBi dB Table 10 through Table 51 list the module level electrical characteristics for the CYBLE-214015-01. All specifications are valid for 40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. Table 10. CYBLE-214015-01 DC Specifications Parameter Description Power supply input voltage (VDD = VDDA = VDDR) Power supply input voltage unregulated (VDD =
VDDA = VDDR) Radio supply voltage (radio on) Radio supply voltage (radio off) VDD1 VDD2 VDDR1 VDDR2 Active Mode, VDD = 1.71V to 5.5V IDD3 IDD4 IDD5 IDD6 IDD7 Execute from flash; CPU at 3 MHz Execute from flash; CPU at 3 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 12 MHz Min 1.71 1.71 1.9 1.71 Typ 1.8 1.7 2.5 4 Max 5.5 1.89 5.5 5.5 Unit Details/Conditions V With regulator enabled Internally unregulated supply V V V mA T = 25 C, VDD = 3.3V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3V Document Number: 002-15923 Rev. **
Page 15 of 42 PRELIMINARY CYBLE-214015-01 Table 10. CYBLE-214015-01 DC Specifications (continued) Parameter Description IMO on ECO on WDT with WCO on Execute from flash; CPU at 48 MHz Execute from flash; CPU at 12 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 48 MHz IDD8 IDD9 IDD10 IDD11 IDD12 Sleep Mode, VDD = 1.71 to 5.5V IDD13 Sleep Mode, VDD and VDDR = 1.9 to 5.5V IDD14 Deep-Sleep Mode, VDD = 1.71 to 3.6V IDD15 IDD16 IDD17 IDD18 Deep-Sleep Mode, VDD = 1.71 to 1.89V (Regulator Bypassed) IDD19 IDD20 Hibernate Mode, VDD = 1.71 to 3.6V GPIO and reset active IDD27 IDD28 Hibernate Mode, VDD = 3.6 to 5.5V IDD29 IDD30 Stop Mode, VDD = 1.71 to 3.6V IDD33 WDT with WCO on WDT with WCO on Stop-mode current (VDD) GPIO and reset active GPIO and reset active GPIO and reset active WDT with WCO on WDT with WCO on WDT with WCO on Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) IDD34 IDD35 IDD36 Stop Mode, VDD = 3.6 to 5.5V IDD37 Stop-mode current (VDD) IDD38 IDD39 IDD40 Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) Min Typ 7.1 13.4 1.3 150 20 40 Max
-
Details/Conditions Unit mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3V, SYSCLK = 3 MHz mA T = 25 C, VDD = 3.3V, SYSCLK = 3 MHz A T = 25 C, VDD = 3.3V A T = 40 C to 85 C A T = 25 C, VDD = 5V A T = 40 C to 85 C A T = 25 C A T = 40 C to 85 C nA T = 25 C, VDD = 3.3V nA T = 40 C to 85 C nA T = 25 C, VDD = 5V nA T = 40 C to 85 C nA T = 25 C, VDD = 3.3V nA T = 25 C, VDDR = 3.3V nA T = 40 C to 85 C nA T = 40 C to 85 C, VDDR = 1.9 V to 3.6V nA T = 25 C, VDD = 5V nA T = 25 C, VDDR = 5V nA T = 40 C to 85 C nA T = 40 C to 85 C Document Number: 002-15923 Rev. **
Page 16 of 42 PRELIMINARY CYBLE-214015-01 Table 11. AC Specifications Parameter Description CPU frequency Wakeup from Sleep mode FCPU TSLEEP TDEEPSLEEP THIBERNATE TSTOP GPIO Table 12. GPIO DC Specifications Wakeup from Deep-Sleep mode Wakeup from Hibernate mode Wakeup from Stop mode Min DC Parameter Description Min
[4]
VIH VIL VOH VOL RPULLUP RPULLDOWN IIL IIL_CTBM CIN VHYSTTL VHYSCMOS IDIODE ITOT_GPIO Input voltage HIGH threshold LVTTL input, VDD < 2.7V LVTTL input, VDD 2.7V Input voltage LOW threshold LVTTL input, VDD < 2.7V LVTTL input, VDD 2.7V Output voltage HIGH level Output voltage HIGH level Output voltage LOW level Output voltage LOW level Output voltage LOW level Pull-up resistor Pull-down resistor Input leakage current (absolute value) Input leakage on CTBm input pins Input capacitance Input hysteresis LVTTL Input hysteresis CMOS Current through protection diode to VDD/VSS Maximum total source or sink chip current 0.7 VDD 0.7 VDD 2.0 VDD 0.6 VDD 0.5 3.5 3.5 25 0.05 VDD Typ 0 Typ 5.6 5.6 40 Max 48 25 800 2 Max 0.3 VDD 0.3 VDD 0.8 0.6 0.6 0.4 8.5 8.5 2 4 7 100 200 Unit MHz s s s ms Unit V V V V V V V V V V V k k nA nA pF mV 1 A mA Details/Conditions 1.71V VDD 5.5V Guaranteed by characterization 24-MHz IMO. Guaranteed by characterization Guaranteed by characterization XRES wakeup Details/Conditions CMOS input CMOS input IOH = 4 mA at 3.3-V VDD IOH = 1 mA at 1.8-V VDD IOL = 8 mA at 3.3-V VDD IOL = 4 mA at 1.8-V VDD IOL = 3 mA at 3.3-V VDD 25 C, VDD = 3.3V VDD > 2.7V Note 4. VIH must not exceed VDD + 0.2 V. Document Number: 002-15923 Rev. **
Page 17 of 42 PRELIMINARY CYBLE-214015-01 Table 13. GPIO AC Specifications Parameter Description TRISEF TFALLF TRISES TFALLS FGPIOUT1 FGPIOUT2 FGPIOUT3 FGPIOUT4 FGPIOIN Rise time in Fast-Strong mode Fall time in Fast-Strong mode Rise time in Slow-Strong mode Fall time in Slow-Strong mode GPIO Fout; 3.3V VDD 5.5V Fast-Strong mode GPIO Fout; 1.7V VDD 3.3V Fast-Strong mode GPIO Fout; 3.3V VDD 5.5V Slow-Strong mode GPIO Fout; 1.7V VDD 3.3V Slow-Strong mode GPIO input operating frequency 1.71V VDD 5.5V Min 2 2 10 10 Typ Max 12 12 60 60 33 16.7 7 3.5 48 Unit ns ns ns ns MHz MHz MHz MHz MHz Details/Conditions 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10% VIO XRES Table 14. XRES DC Specifications Parameter Description Min VIH VIL RPULLUP CIN VHYSXRES IDIODE Input voltage HIGH threshold Input voltage LOW threshold Pull-up resistor Input capacitance Input voltage hysteresis Current through protection diode to VDD/VSS Table 15. XRES AC Specifications Parameter Description TRESETWIDTH Reset pulse width Analog Peripherals Opamp Table 16. Opamp Specifications 0.7 VDDD 3.5 Min 1 Typ 5.6 3 100 Typ Max 0.3 VDDD 8.5 100 Unit V V k pF mV A Details/Conditions CMOS input CMOS input Max Unit s Details/Conditions Parameter Description Min Typ Power = high Power = medium Power = low IDD (Opamp Block Current. VDD = 1.8V. No Load) IDD_HI IDD_MED IDD_LOW GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7V) GBW_HI GBW_MED GBW_LO IOUT_MAX (VDDA 2.7V, 500 mV from Rail) IOUT_MAX_HI Power = high Power = medium Power = low Power = high 6 4 10 1000 500 250 1 Max 1300 350 Unit Details/Conditions A A A MHz MHz MHz mA Document Number: 002-15923 Rev. **
Page 18 of 42 PRELIMINARY CYBLE-214015-01 Table 16. Opamp Specifications (continued) Description Power = medium Power = low Power = high Power = medium Power = low Charge pump on, VDDA 2.7V Charge pump on, VDDA 2.7V Parameter IOUT_MAX_MID IOUT_MAX_LO IOUT (VDDA = 1.71V, 500 mV from Rail) IOUT_MAX_HI IOUT_MAX_MID IOUT_MAX_LO VIN VCM VOUT (VDDA 2.7V) VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOS_TR VOS_TR VOS_TR VOS_DR_TR VOS_DR_TR VOS_DR_TR CMRR Power = high, ILOAD = 10 mA Power = high, ILOAD = 1 mA Power = medium, ILOAD = 1 mA Power = low, ILOAD = 0.1 mA Offset voltage, trimmed Offset voltage, trimmed Offset voltage, trimmed Offset voltage drift, trimmed Offset voltage drift, trimmed Offset voltage drift, trimmed DC PSRR Noise VN1 VN2 VN3 VN4 CLOAD Slew_rate T_op_wake At 1 kHz, 100-mV ripple Input referred, 1 Hz1 GHz, power = high Input referred, 1 kHz, power = high Input referred, 10 kHz, power = high Input referred, 100 kHz, power = high Stable up to maximum load. Performance specs at 50 pF Cload = 50 pF, Power = High, VDDA 2.7V From disable to enable, no external RC dominating Min 10 4 4 0.05 0.05 0.5 0.2 0.2 0.2 1 10 65 70 6 Typ 5 2 0.5 1 2 3 10 10 70 85 94 72 28 15 300 Response time; power = high Response time; power = medium Response time; power = low Hysteresis Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.) TPD1 TPD2 TPD3 Vhyst_op Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5V) GBW_DS IDD_DS Vos_DS Vos_dr_DS Vout_DS Gain bandwidth product Current Offset voltage Offset voltage drift Output voltage 150 400 2000 10 0.2 50 15 5 20 VDD0.2 Max VDDA 0.2 VDDA 0.2 Unit mA mA mA mA mA V V Details/Conditions VDDA 0.5 VDDA 0.2 VDDA 0.2 VDDA 0.2 1 10 High mode Medium mode Low mode High mode V V V V mV mV mV V/C V/C Medium mode V/C Low mode VDDD = 3.6V, High-power mode VDDD = 3.6V 125 dB dB Vrms nV/rtHz nV/rtHz nV/rtHz pF V/sec sec ns ns ns mV kHz A mV V/C V Document Number: 002-15923 Rev. **
Page 19 of 42 PRELIMINARY CYBLE-214015-01 Table 16. Opamp Specifications (continued) Description Parameter Vcm_DS Common mode voltage Table 17. Comparator DC Specifications Parameter Description VOFFSET1 VOFFSET2 VOFFSET3 VHYST VICM1 VICM2 VICM3 CMRR CMRR ICMP1 ICMP2 ICMP3 ZCMP Input offset voltage, Factory trim Input offset voltage, Custom trim Input offset voltage, ultra-low-power mode Hysteresis when enabled Input common mode voltage in normal mode Input common mode voltage in low-power mode Input common mode voltage in ultra low-power mode Common mode rejection ratio Common mode rejection ratio Block current, normal mode Block current, low-power mode Block current in ultra-low-power mode DC input impedance of comparator Table 18. Comparator AC Specifications Parameter Description TRESP1 TRESP2 TRESP3 Response time, normal mode, 50-mV overdrive Response time, low-power mode, 50-mV overdrive Response time, ultra-low-power mode, 50-mV overdrive Min 0.2 Min 0 0 0 50 42 35 Min Typ Max VDD 1.8 Unit V Details/Conditions Typ 12 10 6 Typ 38 70 2.3 Max 10 6 35 VDDD 0.1 VDDD VDDD 1.15 400 100 Unit mV mV mV mV V V V dB dB A A A M Details/Conditions Modes 1 and 2 VDDD 2.7V VDDD 2.7V Max Unit Details/Conditions ns ns s 50-mV overdrive 50-mV overdrive 200-mV overdrive Temperature Sensor Table 19. Temperature Sensor Specifications Parameter TSENSACC Description Temperature-sensor accuracy SAR ADC Table 20. SAR ADC DC Specifications Parameter A_RES A_CHNIS_S Description Resolution Number of channels - single-ended A-CHNKS_D Number of channels - differential A-MONO Monotonicity A_GAINERR Gain error Min 5 Typ 1 Max 5 Unit C Details/Conditions 40 to +85 C Min Typ Max 12 8 4 0.1 Unit bits
%
Details/Conditions 8 full-speed Diff inputs use neighboring I/O Yes With external reference Document Number: 002-15923 Rev. **
Page 20 of 42 PRELIMINARY CYBLE-214015-01 Table 20. SAR ADC DC Specifications (continued) Parameter Description A_OFFSET Input offset voltage A_ISAR A_VINS A_VIND A_INRES A_INCAP Current consumption Input voltage range - single-ended Input voltage range - differential Input resistance Input capacitance VREFSAR Trimmed internal reference to SAR Min VSS VSS 1 Typ Max Unit 2 1 VDDA VDDA 2.2 10 1 Table 21. SAR ADC AC Specifications Parameter Description Min Typ Max A_PSRR A_CMRR A_SAMP Fsarintref A_SNR A_BW A_INL A_INL A_INL A_dnl A_DNL A_DNL A_THD Power-supply rejection ratio Common-mode rejection ratio Sample rate SAR operating speed without external ref. bypass Signal-to-noise ratio (SNR) Input bandwidth without aliasing Integral nonlinearity. VDD = 1.71V to 5.5V, 1 Msps Integral nonlinearity. VDDD = 1.71V to 3.6V, 1 Msps Integral nonlinearity. VDD = 1.71V to 5.5V, 500 Ksps Differential nonlinearity. VDD = 1.71V to 5.5V, 1 Msps Differential nonlinearity. VDD = 1.71V to 3.6 V, 1 Msps Differential nonlinearity. VDD = 1.71V to 5.5V, 500 Ksps Total harmonic distortion CSD Table 22. CSD Block Specifications Parameter VCSD IDAC1 IDAC1 IDAC2 IDAC2 Description Voltage range of operation DNL for 8-bit resolution INL for 8-bit resolution DNL for 7-bit resolution INL for 7-bit resolution 70 66 65 1.7 1.5 1.5 1 1 1 Min 1.71 1 3 1 3 Typ 1 100 A_SAMP/2 2 1.7 1.7 2.2 2 2.2 65 Max 5.5 1 3 1 3 Details/Conditions Measured with 1-V VREF Percentage of Vbg
(1.024 V) Details/Conditions Measured at 1-V reference 12-bit resolution FIN = 10 kHz VREF = 1V to VDD VREF = 1.71V to VDD VREF = 1V to VDD VREF = 1V to VDD VREF = 1.71V to VDD VREF = 1V to VDD FIN = 10 kHz Details/Conditions mV mA V V k pF
%
Unit dB dB Msps Ksps dB kHz LSB LSB LSB LSB LSB LSB dB Unit V LSB LSB LSB LSB Document Number: 002-15923 Rev. **
Page 21 of 42 PRELIMINARY CYBLE-214015-01 Table 22. CSD Block Specifications (continued) Parameter Description Min Typ Max Unit SNR Ratio of counts of finger to noise IDAC1_CRT1 IDAC1_CRT2 IDAC2_CRT1 IDAC2_CRT2 Output current of IDAC1 (8 bits) in High range Output current of IDAC1 (8 bits) in Low range Output current of IDAC2 (7 bits) in High range Output current of IDAC2 (7 bits) in Low range Digital Peripherals Timer Table 23. Timer DC Specifications Parameter ITIM1 ITIM2 ITIM3 Description Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz 5 Min Table 24. Timer AC Specifications Parameter TTIMFREQ TCAPWINT TCAPWEXT TTIMRES TTENWIDINT TTENWIDEXT TTIMRESWINT TTIMRESEXT Description Operating frequency Capture pulse width (internal) Capture pulse width (external) Timer resolution Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) Counter Table 25. Counter DC Specifications Parameter ICTR1 ICTR2 ICTR3 Description Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Table 26. Counter AC Specifications Parameter TCTRFREQ TCTRPWINT TCTRPWEXT Description Operating frequency Capture pulse width (internal) Capture pulse width (external) Document Number: 002-15923 Rev. **
612 306 305 153 Typ Typ Min FCLK 2 TCLK 2 TCLK TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Min Min FCLK 2 TCLK 2 TCLK Typ Typ Details/Conditions Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan Details/Conditions 16-bit timer 16-bit timer 16-bit timer Details/Conditions Details/Conditions 16-bit counter 16-bit counter 16-bit counter Max 42 130 535 Max 48 Max 42 130 535 Ratio A A A A Unit A A A Unit MHz ns ns ns ns ns ns ns Unit A A A Max 48 Unit MHz ns ns Details/Conditions Page 22 of 42 Table 26. Counter AC Specifications (continued) PRELIMINARY CYBLE-214015-01 Parameter Description Counter Resolution TCTRES TCENWIDINT Enable pulse width (internal) TCENWIDEXT Enable pulse width (external) TCTRRESWINT Reset pulse width (internal) TCTRRESWEXT Reset pulse width (external) Pulse Width Modulation (PWM) Table 27. PWM DC Specifications Parameter Description IPWM1 IPWM2 IPWM3 Table 28. PWM AC Specifications Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Parameter TPWMFREQ TPWMPWINT TPWMEXT TPWMKILLINT TPWMKILLEXT TPWMEINT TPWMENEXT TPWMRESWINT TPWMRESWEXT Description Operating frequency Pulse width (internal) Pulse width (external) Kill pulse width (internal) Kill pulse width (external) Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) Min TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Min Min FCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Typ Typ Typ Max Max 42 130 535 Max 48 Unit ns ns ns ns ns Unit A A A Unit MHz ns ns ns ns ns ns ns ns Details/Conditions Details/Conditions 16-bit PWM 16-bit PWM 16-bit PWM Details/Conditions LCD Direct Drive Table 29. LCD Direct Drive DC Specifications Spec ID Parameter Description SID228 SID229 SID230 SID231 SID232 ILCDLOW CLCDCAP LCDOFFSET ILCDOP1 ILCDOP2 Operating current in low-power mode LCD capacitance per segment/common driver Long-term segment offset LCD system operating current VBIAS = 5 V LCD system operating current VBIAS = 3.3 V Table 30. LCD Direct Drive AC Specifications Spec ID SID233 Parameter FLCD Description LCD frame rate Min Typ 17.5 500 20 2 2 Max 5000 Unit A Details/Conditions 16 4 small segment display at 50 Hz pF mV mA 32 4 segments. 50 Hz at 25 C mA 32 4 segments 50 Hz at 25 C Min 10 Typ 50 Max 150 Unit Hz Details/Conditions Document Number: 002-15923 Rev. **
Page 23 of 42 PRELIMINARY CYBLE-214015-01 Serial Communication Table 31. Fixed I2C DC Specifications Parameter Description Block current consumption at 100 kHz Block current consumption at 400 kHz Block current consumption at 1 Mbps I2C enabled in Deep-Sleep mode II2C1 II2C2 II2C3 II2C4 Table 32. Fixed I2C AC Specifications Parameter FI2C1 Bit rate Description Table 33. Fixed UART DC Specifications Description Parameter IUART1 IUART2 Block current consumption at 100 kbps Block current consumption at 1000 kbps Table 34. Fixed UART AC Specifications Description Parameter FUART Bit rate Table 35. Fixed SPI DC Specifications Parameter ISPI1 ISPI2 ISPI3 Description Block current consumption at 1 Mbps Block current consumption at 4 Mbps Block current consumption at 8 Mbps Min Min Min Min Min Typ Typ Typ Typ Typ Max 50 155 390 1.4 Max 400 Max 55 312 Unit A A A A Unit kHz Unit A A Details/Conditions Details/Conditions Details/Conditions Max 1 Unit Mbps Details/Conditions Max 360 560 600 Unit A A A Details/Conditions Table 36. Fixed SPI AC Specifications Parameter FSPI Description SPI operating frequency (master; 6x over sampling) Min Typ Max 8 Unit MHz Details/Conditions Table 37. Fixed SPI Master Mode AC Specifications Parameter Description TDMO TDSI THMO MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge Full clock, late MISO sampling used Previous MOSI data hold time Table 38. Fixed SPI Slave Mode AC Specifications Parameter Description TDMI TDSO TDSO_ext THSO TSSELSCK MOSI valid before SCLK capturing edge MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0V Previous MISO data hold time SSEL valid to first SCK valid edge Min 20 0 Typ Max 18 Unit ns ns ns Details/Conditions Full clock, late MISO sampling Referred to Slave capturing edge Min 40 0 100 Typ Max 42 + 3 TCPU 50 Unit ns ns ns ns ns Document Number: 002-15923 Rev. **
Page 24 of 42 PRELIMINARY CYBLE-214015-01 Memory Table 39. Flash DC Specifications Parameter Description VPE TWS48 TWS32 TWS16 Table 40. Flash AC Specifications Erase and program voltage Number of Wait states at 3248 MHz Number of Wait states at 1632 MHz Number of Wait states for 016 MHz Parameter
[5]
TROWWRITE
[5]
TROWERASE TROWPROGRAM
[5]
TBULKERASE
[5]
TDEVPROG FEND FRET FRET2 Description Row (block) write time (erase and program) Row erase time
[5] Row program time after erase Bulk erase time (256 KB) Total device program time Flash endurance Flash retention. TA 55 C, 100 K P/E cycles. Flash retention. TA 85 C, 10 K P/E cycles. System Resources Power-on-Reset (POR) Table 41. POR DC Specifications Parameter VRISEIPOR VFALLIPOR VIPORHYST Description Rising trip voltage Falling trip voltage Hysteresis Table 42. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 43. Brown-Out Detect Parameter VFALLPPOR VFALLDPSLP Description BOD trip voltage in Active and Sleep modes BOD trip voltage in Deep Sleep Min 1.71 2 1 0 Min 100 K 20 10 Min 0.80 0.75 15 Min Min 1.64 1.4 Typ Typ Typ Typ Typ Max 5.5 Max 20 13 7 35 25 Max 1.45 1.40 200 Max 1 Max Unit V Unit ms ms ms ms seconds cycles years years Unit V V mV Unit s Unit V V Details/Conditions CPU execution from flash CPU execution from flash CPU execution from flash Details/Conditions Row (block) = 256 bytes Details/Conditions Details/Conditions Details/Conditions Table 44. Hibernate Reset Parameter VHBRTRIP Description BOD trip voltage in Hibernate Min 1.1 Typ Max Unit V Details/Conditions Note 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-15923 Rev. **
Page 25 of 42 Voltage Monitors (LVD) Table 45. Voltage Monitor DC Specifications Parameter Description VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 VLVI10 VLVI11 VLVI12 VLVI13 VLVI14 VLVI15 VLVI16 LVI_IDD LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b Block current Table 46. Voltage Monitor AC Specifications Parameter TMONTRIP Description Voltage monitor trip time SWD Interface Table 47. SWD Interface Specifications Description 3.3 V VDD 5.5 V 1.71 V VDD 3.3 V Parameter F_SWDCLK1 F_SWDCLK2 T_SWDI_SETUP T = 1/f SWDCLK T_SWDI_HOLD T = 1/f SWDCLK T_SWDO_VALID T = 1/f SWDCLK T_SWDO_HOLD T = 1/f SWDCLK PRELIMINARY CYBLE-214015-01 Min 1.71 1.76 1.85 1.95 2.05 2.15 2.24 2.34 2.44 2.54 2.63 2.73 2.83 2.93 3.12 4.39 Min Min 0.25 T 0.25 T 1 Typ 1.75 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.20 4.50 Typ Typ Max 1.79 1.85 1.95 2.05 2.15 2.26 2.36 2.46 2.56 2.67 2.77 2.87 2.97 3.08 3.28 4.61 100 Max 1 Unit V V V V V V V V V V V V V V V V A Unit s Max 14 7 0.5 T Unit MHz MHz ns ns ns ns Details/Conditions Details/Conditions Details/Conditions SWDCLK 1/3 CPU clock frequency SWDCLK 1/3 CPU clock frequency Document Number: 002-15923 Rev. **
Page 26 of 42 PRELIMINARY CYBLE-214015-01 Internal Main Oscillator Table 48. IMO DC Specifications Parameter Description IIMO1 IIMO2 IIMO3 IIMO4 IIMO5 IMO operating current at 48 MHz IMO operating current at 24 MHz IMO operating current at 12 MHz IMO operating current at 6 MHz IMO operating current at 3 MHz Table 49. IMO AC Specifications Parameter FIMOTOL3 FIMOTOL3 Description Frequency variation from 3 to 48 MHz IMO startup time Internal Low-Speed Oscillator Table 50. ILO DC Specifications Parameter IILO2 Description ILO operating current at 32 kHz Table 51. ILO AC Specifications Parameter TSTARTILO1 FILOTRIM1 Description ILO startup time 32-kHz trimmed frequency Table 52. ECO Trim Value Specification Description Parameter ECOTRIM 24-MHz trim value
(firmware configuration) Table 53. UDB AC Specifications Min Min Min Min 15 Typ Typ 12 Typ 0.3 Typ 32 Max 1000 325 225 180 150 Max 2 Max 1.05 Max 2 50 Unit A A A A A Unit
%
s Unit A Unit ms kHz Details/Conditions Details/Conditions With API-called calibration Details/Conditions Details/Conditions Value Details/Conditions 0x00002D6A Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Parameter Description Min Typ Max Unit Details/Conditions Data Path performance FMAX-TIMER FMAX-ADDER FMAX_CRC PLD Performance in UDB Max frequency of 16-bit timer in a UDB pair Max frequency of 16-bit adder in a UDB pair Max frequency of 16-bit CRC/PRS in a UDB pair FMAX_PLD Clock to Output Performance Max frequency of 2-pass PLD function in a UDB pair TCLK_OUT_UDB1 TCLK_OUT_UDB2 Prop. delay for clock in to data out at 25 C, Typical Prop. delay for clock in to data out, Worst case 15 25 48 48 48 48 MHz MHz MHz MHz ns ns Document Number: 002-15923 Rev. **
Page 27 of 42 PRELIMINARY CYBLE-214015-01 Table 54. BLE Subsystem Parameter Description Min Typ Max RF Receiver Specification RXS, IDLE RX sensitivity with idle transmitter RX sensitivity with idle transmitter excluding Balun loss RX sensitivity with dirty transmitter RXS, DIRTY RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter PRXMAX Maximum input power CI1 CI2 CI3 CI4 CI5 CI3 OBB1 OBB2 OBB3 OBB4 IMD RXSE1 RXSE2 Cochannel interference, Wanted signal at 67 dBm and Interferer at FRX Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 1 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 2 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 3 MHz Adjacent channel interference Wanted Signal at 67 dBm and Interferer at Image frequency (FIMAGE) Adjacent channel interference Wanted signal at 67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 302000 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 20032399 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 24842997 MHz Out-of-band blocking, Wanted signal a 67 dBm and Interferer at F = 300012750 MHz Intermodulation performance Wanted signal at 64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel Receiver spurious emission 30 MHz to 1.0 GHz Receiver spurious emission 1.0 GHz to 12.75 GHz Document Number: 002-15923 Rev. **
10 89 91 87 91 1 9 3 29 39 20 30 30 27 35 27 35 27 30 27 50 70 21 15 57 47 Unit dBm dBm dBm dBm dBm dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm Details/Conditions Guaranteed by design simulation RF-PHY Specification
(RCV-LE/CA/01/C) RF-PHY Specification
(RCV-LE/CA/06/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/05/C) 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 Page 28 of 42 PRELIMINARY CYBLE-214015-01 Table 54. BLE Subsystem (continued) Parameter Description Min Typ Max Unit Details/Conditions RF Transmitter Specifications TXP, ACC TXP, RANGE TXP, 0dBm RF power accuracy RF power control range Output power, 0-dB Gain setting (PA7) Output power, maximum power setting
(PA10) Output power, minimum power setting
(PA1) Average frequency deviation for 10101010 pattern Average frequency deviation for 11110000 pattern Eye opening = F2AVG/F1AVG TXP, MAX TXP, MIN F2AVG F1AVG EO FTX, ACC Frequency accuracy FTX, MAXDR Maximum frequency drift FTX, INITDR Initial frequency drift FTX, DR IBSE1 IBSE2 TXSE1 TXSE2 Maximum drift rate In-band spurious emission at 2-MHz offset In-band spurious emission at 3-MHz offset Transmitter spurious emissions
(average), <1.0 GHz Transmitter spurious emissions
(average), >1.0 GHz RF Current Specifications IRX IRX_RF IRX, HIGHGAIN ITX, 3dBm ITX, 0dBm ITX_RF, 0dBm ITX_RF, 0dBm ITX,-3dBm ITX,-6dBm ITX,-12dBm ITX,-18dBm Receive current in normal mode Radio receive current in normal mode Receive current in high-gain mode TX current at 3-dBm setting (PA10) TX current at 0-dBm setting (PA7) Radio TX current at 0 dBm setting (PA7) Radio TX current at 0 dBm excluding Balun loss TX current at 3-dBm setting (PA4) TX current at 6-dBm setting (PA3) TX current at 12-dBm setting (PA2) TX current at 18-dBm setting (PA1) 185 225 0.8 150 50 20 20 1 20 0 3 18 250 18.7 16.4 21.5 20 16.5 15.6 14.2 15.5 14.5 13.2 12.5 275 150 50 20 20 20 30 55.5 41.5 dB dB dBm dBm dBm kHz kHz kHz kHz kHz kHz/
50 s dBm dBm dBm dBm mA mA mA mA mA mA mA mA mA mA mA RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/03/C) RF-PHY Specification
(TRM-LE/CA/03/C) FCC-15.247 FCC-15.247 Measured at VDDR Measured at VDDR Guaranteed by design simulation Document Number: 002-15923 Rev. **
Page 29 of 42 PRELIMINARY CYBLE-214015-01 Table 54. BLE Subsystem (continued) Parameter Description Min Typ Max Unit Iavg_1sec, 0dBm Average current at 1-second BLE connection interval Iavg_4sec, 0dBm Average current at 4-second BLE connection interval RF operating frequency Channel spacing On-air data rate BLE.IDLE to BLE. TX transition time BLE.IDLE to BLE. RX transition time General RF Specifications FREQ CHBW DR IDLE2TX IDLE2RX RSSI Specifications RSSI, ACC RSSI, RES RSSI, PER RSSI accuracy RSSI resolution RSSI sample period 2400 17.1 6.1 2 1000 120 75 5 1 6 2482 140 120 A A MHz MHz kbps s s dB dB s Details/Conditions TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange. TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange. Document Number: 002-15923 Rev. **
Page 30 of 42 PRELIMINARY CYBLE-214015-01 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-214015-01 module is certified under the following RF certification standards:
n FCC ID: WAP4008 n CE n IC: 7922A-4008 n MIC: 203-JN0505 n KC: MSIP-CRM-Cyp-4008 Environmental Conditions Table 55 describes the operating and storage conditions for the Cypress BLE module. Table 55. Environmental Conditions for CYBLE-214015-01 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[6]
40 C 5%
40 C 85 C 85%
3 C/minute 85 C 85 C at 85%
15 kV Air 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-15923 Rev. **
Page 31 of 42 PRELIMINARY CYBLE-214015-01 Regulatory Information FCC FCC NOTICE:
The device CYBLE-214015-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
n Reorient or relocate the receiving antenna. n Increase the separation between the equipment and receiver. n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. n Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008. In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 14. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-214015-01 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-214015-01 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-15923 Rev. **
Page 32 of 42 PRELIMINARY CYBLE-214015-01 Industry Canada (IC) Certification CYBLE-214015-01 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-4008 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of -0.5 dBi. Anten-
nas not included in this list or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required an-
tenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. IC NOTICE:
The device CYBLE-214015-01 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. IC RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-4008". European R&TTE Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-214015-01 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-214015-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-
bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-15923 Rev. **
Page 33 of 42 PRELIMINARY CYBLE-214015-01 MIC Japan CYBLE-214015-01 is certified as a module with type certification number 203-JN0505. End products that integrate CYBLE-214015-01 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-214015-01 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008. Document Number: 002-15923 Rev. **
Page 34 of 42 PRELIMINARY CYBLE-214015-01 Packaging Table 56. Solder Reflow Peak Temperature Module Part Number CYBLE-214015-01 Package 32-pad SMT Maximum Peak Temperature Maximum Time at PeakTemperature No. of Cycles 260 C 30 seconds 2 Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBLE-214015-01 Package 32-pad SMT MSL MSL 3 The CYBLE-214015-01 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-214015-01. Figure 10. CYBLE-214015-01 Tape Dimensions Figure 11 details the orientation of the CYBLE-214015-01 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction Document Number: 002-15923 Rev. **
Page 35 of 42 PRELIMINARY CYBLE-214015-01 Figure 12 details reel dimensions used for the CYBLE-214015-01. Figure 12. Reel Dimensions The CYBLE-214015-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-214015-01 is detailed in Figure 13. Figure 13. CYBLE-214015-01 Center of Mass Document Number: 002-15923 Rev. **
Page 36 of 42 PRELIMINARY CYBLE-214015-01 Ordering Information Table 58 lists the CYBLE-214015-01 part number and features. Table 59 lists the reel shipment quantities for the CYBLE-214015-01. Table 58. Ordering Information
) z H M MPN
(
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(
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p m a p O Features e s n e S p a C e v i r D D C L t c e r i D C D A R A S t i b
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2 1 s r o t a r a p m o C P L l s k c o B M W P C T l s k c o B B C S
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i S 2 I CYBLE-214015-01 48 256 32 4 4 3 3 1 Msps 1 4 2 4 3 25 32-SMT Table 59. Tape and Reel Package Quantity and Minimum Order Amount Description Minimum Reel Quantity Maximum Reel Quantity Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) 500 500 500 2,000 Comments Reel quantity ships in increments of 500 units up to a maximum of 2,000 depending on line item order quantity. The CYBLE-214015-01 is offered in tape and reel packaging. The CYBLE-214015-01 ships with a maximum of 2,000 units/reel. If a 500 unit reel is desired, an order should be placed with a single line item of 500 units. Order line items larger than 500 units will be shipped in multiples of either 1,000, 1,500, or 2,000 units per reel based on the order line item quantity. Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-15923 Rev. **
Page 37 of 42 PRELIMINARY CYBLE-214015-01 Acronyms Table 60. Acronyms Used in this Document Acronym Description ABUS ADC AG AHB ALU AMUXBUS API APSR ARM ATM BLE Bluetooth SIG BW CAN CE CSA CMRR CPU CRC DAC DFB DIO DMIPS DMA DNL DNU DR DSI DWT ECC ECO EEPROM EMI analog local bus analog-to-digital converter analog global AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode Bluetooth Low Energy Bluetooth Special Interest Group bandwidth Controller Area Network, a communications protocol European Conformity Canadian Standards Association common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO. Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference Table 60. Acronyms Used in this Document (continued) Acronym Description EMIF EOC EOF EPSR ESD ETM FCC FET FIR FPB FS GPIO HCI HVI IC IDAC IDE I2C, or IIC IC IIR ILO IMO INL I/O IPOR IPSR IRQ ITM KC LCD LIN LR LUT LVD LVI LVTTL external memory interface end of conversion end of frame execution program status register electrostatic discharge embedded trace macrocell Federal Communications Commission field-effect transistor finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin host controller interface high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment Inter-Integrated Circuit, a communications protocol Industry Canada infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell Korea Certification liquid crystal display Local Interconnect Network, a communications protocol. link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic Document Number: 002-15923 Rev. **
Page 38 of 42 PRELIMINARY CYBLE-214015-01 Table 60. Acronyms Used in this Document (continued) Table 60. Acronyms Used in this Document (continued) Acronym Description Acronym Description MAC MCU MIC MISO NC NMI NRZ NVIC NVL Opamp PAL PC PCB PGA PHUB PHY PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC PSRR PWM QDID RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL multiply-accumulate microcontroller unit Ministry of Internal Affairs and Communications
(Japan) master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-Chip power supply rejection ratio pulse-width modulator qualification design ID random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I2C serial clock SDA S/H SINAD SIO SMT SOC SOF SPI SR SRAM SRES STN SWD SWV TD THD TIA TN TRM TTL TUV TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL I2C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs start of conversion start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset super twisted nematic serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier twisted nematic technical reference manual transistor-transistor logic Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Document Number: 002-15923 Rev. **
Page 39 of 42 PRELIMINARY CYBLE-214015-01 Document Conventions Units of Measure Table 61. Units of Measure Symbol Unit of Measure C dB dBm fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V degrees Celsius decibel decibel-milliwatts femtofarads hertz 1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt Document Number: 002-15923 Rev. **
Page 40 of 42 PRELIMINARY CYBLE-214015-01 Document History Page Document Title: CYBLE-214015-01, EZ-BLE PSoC Bluetooth 4.2 Module Document Number: 002-15923 Orig. of Revision Change Submission Date ECN
**
DSO Description of Change 08/17/2016 Preliminary datasheet for CYBLE-214015-01 module. Document Number: 002-15923 Rev. **
Page 41 of 42 PRELIMINARY CYBLE-214015-01 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF PSoC Solutions cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/powerpsoc cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-15923 Rev. **
Revised August 18, 2016 Page 42 of 42
| 1 2 | User Manual II | Users Manual | 1.24 MiB | November 12 2015 |
PRELIMINARY CYBLE-214009-00 EZ-BLETM PSoC Module logic, General Description The Cypress CYBLE-214009-00 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-214009-00 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC 4 BLE. Refer to the PSoC 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module. The EZ-BLETM PSoC module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-214009-00 also includes digital programmable high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The CYBLE-214009-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a small 11 11 1.80 mm package. The CYBLE-214009-00 is a complete solution and an ideal fit for applications seeking a highly integrated BLE wireless solution. CYBLE-214009-00 is drop-in compatible CYBLE-014008-00. Module Description n Module size: 11.0 mm 11.0 mm 1.80 mm (with shield) n Bluetooth 4.1 single-mode module n Industrial temperature range: 40 C to +85 C n 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz n 256-KB flash memory, 32-KB SRAM memory n Watchdog timer with dedicated internal low-speed oscillator
(ILO) n Two-pin SWD for programming n Up to 25 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output n Certified to FCC, CE, MIC, KC, and IC regulations n Bluetooth SIG 4.1 qualified Power Consumption n TX output power: 18 dbm to +3 dbm n Received signal strength indicator (RSSI) with 1-dB resolution n TX current consumption of 15.6 mA (radio only, 0 dbm) n RX current consumption of 16.4 mA (radio only) n Low power mode support p Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on p Hibernate: 150 nA with SRAM retention p Stop: 60 nA with XRES wakeup Programmable Analog n Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode. n 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging n Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin n One low-power comparator that operate in Deep-Sleep mode Programmable Digital n Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and datapath n Cypress-provided peripheral Component library, user-defined state machines, and Verilog input Capacitive Sensing n Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance n Cypress-supplied software component makes capacitive-sensing design easy n Automatic hardware-tuning algorithm (SmartSense) Segment LCD Drive n LCD drive supported on all GPIOs (common or segment) n Operates in Deep-Sleep mode with four bits per pin memory Serial Communication n Two independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionality Timing and Pulse-Width Modulation n Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks n Center-aligned, Edge, and Pseudo-random modes n Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 25 Programmable GPIOs n Any GPIO pin can be CapSense, LCD, analog, or digital n Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable Cypress Semiconductor Corporation Document Number: 002-09714 Rev. **
198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised October 29, 2015 PRELIMINARY CYBLE-214009-00 Contents Overview............................................................................ 3 Module Description...................................................... 3 Pad Connection Interface ................................................ 5 Recommended Host PCB Layout ................................... 6 Power Supply Connections and Recommended External Components.................................................................... 10 Connection Options................................................... 10 External Component Recommendation .................... 10 Critical Components List ........................................... 13 Antenna Design......................................................... 13 Electrical Specification .................................................. 14 GPIO ......................................................................... 16 XRES......................................................................... 17 Analog Peripherals .................................................... 17 Digital Peripherals ..................................................... 21 Serial Communication ............................................... 23 Memory ..................................................................... 24 System Resources .................................................... 24 Environmental Specifications ....................................... 30 Environmental Compliance ....................................... 30 RF Certification.......................................................... 30 Environmental Conditions ......................................... 30 ESD and EMI Protection ........................................... 30 Regulatory Information.................................................. 31 FCC........................................................................... 31 Industry Canada (IC) Certification............................. 32 European R&TTE Declaration of Conformity ............ 32 MIC Japan................................................................. 33 KC Korea................................................................... 33 Ordering Information...................................................... 34 Part Numbering Convention...................................... 34 Acronyms........................................................................ 35 Document Conventions ................................................. 37 Units of Measure ....................................................... 37 Errata ............................................................................... 38 Document History Page................................................. 39 Sales, Solutions, and Legal Information ...................... 40 Worldwide Sales and Design Support....................... 40 Products .................................................................... 40 PSoC Solutions ...................................................... 40 Cypress Developer Community................................. 40 Technical Support ..................................................... 40 Document Number: 002-09714 Rev. **
Page 2 of 40 PRELIMINARY CYBLE-214009-00 Overview Module Description The CYBLE-214009-00 module is a complete module designed to be soldered to the main host board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna location dimensions Length (X) Width (Y) Length (X) Width (Y) Height (H) PCB thickness Height (H) Shield height Maximum component height Height (H) Total module thickness (bottom of module to highest component) Height (H) 11.00 0.15 mm 11.00 0.15 mm 11.00 0.15 mm 4.62 0.15 mm 0.80 0.10 mm 1.00 0.10 mm 1.00 mm typical (shield) 1.80 mm typical See Figure 1 on page 4 for the mechanical reference drawing for CYBLE-214009-00. Document Number: 002-09714 Rev. **
Page 3 of 40 PRELIMINARY CYBLE-214009-00 Figure 1. Module Mechanical Drawing Side View Top View Bottom View Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 and Figure 4 on page 6. Document Number: 002-09714 Rev. **
Page 4 of 40 PRELIMINARY CYBLE-214009-00 Pad Connection Interface As shown in the bottom view of Figure 1 on page 4, the CYBLE-214009-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-214009-00 module. Table 2. Solder Pad Connection Description Name Connections Connection Type SP 32 Solder Pads Pad Length Dimension Pad9/Pad24: 0.74 mm All Others: 0.79 mm Pad Width Dimension 0.41 mm Pad Pitch 0.66 mm Figure 2. Solder Pad Dimensions Document Number: 002-09714 Rev. **
Page 5 of 40 PRELIMINARY CYBLE-214009-00 Recommended Host PCB Layout Figure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm. Figure 3. Recommended PCB Layout Pattern for CYBLE-214009-00 Top View (On Host PCB) To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. 2. It is recommended that the area around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm). Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-214009-00 Trace Antenna Host PCB Keep-Out Area Around Trace Antenna Document Number: 002-09714 Rev. **
Page 6 of 40 PRELIMINARY CYBLE-214009-00 Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections. Table 3. Module Solder Pad Connection Dimensions Pad X Bottom Right Corner 1 2 3 4 5 6 7 8 Top Right Corner 10 11 12 13 14 15 16 17 18 19 20 21 22 Top Left Corner 24 25 26 27 28 29 30 31 32 Pad Y Pad Pitch (Pad X - Pad Y) Comments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bottom Left Corner 4.83 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 1.21 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.89 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 0.66 mm 4.83 mm Distance from bottom right corner to Pad 1 center Distance from Pad 1 center to Pad 2 center Distance from Pad 2 center to Pad 3 center Distance from Pad 3 center to Pad 4 center Distance from Pad 4 center to Pad 5 center Distance from Pad 5 center to Pad 6 center Distance from Pad 6 center to Pad 7 center Distance from Pad 7 center to Pad 8 center Distance from Pad 8 center to Pad 9 center Distance from Pad 9 center to Pad 10 center Distance from Pad 10 center to Pad 11 center Distance from Pad 11 center to Pad 12 center Distance from Pad 12 center to Pad 13 center Distance from Pad 13 center to Pad 14 center Distance from Pad 14 center to Pad 15 center Distance from Pad 15 center to Pad 16 center Distance from Pad 16 center to Pad 17 center Distance from Pad 17 center to Pad 18 center Distance from Pad 18 center to Pad 19 center Distance from Pad 19 center to Pad 20 center Distance from Pad 20 center to Pad 21 center Distance from Pad 21 center to Pad 22 center Distance from Pad 22 center to Pad 23 center Distance from Top Left Corner to Pad 24 center Distance from Pad 24 center to Pad 25 center Distance from Pad 25 center to Pad 26 center Distance from Pad 26 center to Pad 27 center Distance from Pad 27 center to Pad 28 center Distance from Pad 28 center to Pad 29 center Distance from Pad 29 center to Pad 30 center Distance from Pad 30 center to Pad 31 center Distance from Pad 31 center to Pad 32 center Distance from Pad 32 center to Bottom Left Corner Document Number: 002-09714 Rev. **
Page 7 of 40 PRELIMINARY CYBLE-214009-00 Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-214009-00, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3. Table 4. Digital Peripheral Capabilities Cap-
Sense WCO Out ECO OUT LCD SWD GPIO Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 3 3 3 3 3 3 3 3 3 I2C SPI UART TCPWM[2]
Device Port Pin GND[3]
Ground Connection 3(TCPWM0) P1.1 3(TCPWM0) P1.0 P1.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2) P0.1 3(SCB1_TX) 3(SCB1_MISO) 3(SCB1_SCL) 3(TCPWM0) P0.7 3(SCB0_CTS) 3(SCB0_SCLK) 3(TCPWM2) 3(SCB1_SS1) VDD P1.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2) P0.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1) P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1) P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2) Digital Power Supply Input (1.71 to 5.5V) P1.2 VDDR P2.6 P1.3 P3.0 3(SCB0_RX) P2.1 P2.2 P2.3 VDDA P3.4 3(SCB1_RX) P3.1 3(SCB0_TX) P3.7 3(SCB1_CTS) P3.5 3(SCB1_TX) P3.3 3(SCB0_CTS) VREF P3.2 3(SCB0_RTS) P3.6 3(SCB1_RTS) XRES P2.4 P2.5 GND 3(SCB1_SS2) 3(TCPWM1) Radio Power Supply (1.9V to 5.5V) 3(TCPWM1) 3(SCB0_SDA) 3(TCPWM0) 3(SCB1_SS3) 3(SCB0_SS2) 3(SCB0_SS3) 3 3 3 3 3 3 Analog Power Supply Input (1.71 to 5.5V) 3(SCB1_SDA) 3(TCPWM2) 3(SCB0_SCL) 3(TCPWM0) 3(TCPWM3) 3(SCB1_SCL) 3(TCPWM2) 3(TCPWM1) 3 3 3 3 3 3 3 Reference Voltage Input 3(TCPWM1) 3(TCPWM3) 3 3 External Reset Hardware Connection Input 3 3 Ground Connection 3 3 3 3 3 3 3 3 3 3 3
(SWDCLK) 3
(SWDIO) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system. Document Number: 002-09714 Rev. **
Page 8 of 40 PRELIMINARY CYBLE-214009-00
. Table 5. Analog Peripheral Capabilities Pad Number Device Port Pin SARMUX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND[3]
P1.1 P1.0 P1.5 P0.1 P0.7 VDD P1.4 P0.4 P0.5 P0.6 P1.2 VDDR P2.6 P1.3 P3.0 P2.1 P2.2 P2.3 VDDA P3.4 P3.1 P3.7 P3.5 P3.3 VREF P3.2 P3.6 XRES P2.4 P2.5 GND 3 3 3 3 3 3 3 3 LPCOMP 3(COMP0_INN) 3(COMP1_INP) 3(COMP1_INN) OPAMP Ground Connection 3(CTBm1_OA0_INN) 3(CTBm1_OA0_INP) 3(CTBm1_OA1_INP) Digital Power Supply Input (1.71 to 5.5V) 3(CTBm1_OA1_INN) 3(CTBm1_OA0_OUT) Radio Power Supply (1.9V to 5.5V) 3(CTBm1_OA0_INP) 3(CTBm1_OA1_OUT) 3(CTBm1_OA0_INN) 3(CTBm1_OA0_OUT) 3(CTBm1_OA1_OUT) Analog Power Supply Input (1.71 to 5.5V) Reference Voltage Input (Optional) External Reset Hardware Connection Input 3(CTBm1_OA1_INN) 3(CTBm1_OA1_INP) Ground Connection Document Number: 002-09714 Rev. **
Page 9 of 40 PRELIMINARY CYBLE-214009-00 Power Supply Connections and Recommended External Components Power Connections The CYBLE-214009-00 contains three power supply connec-
tions, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respec-
tively. VDDR supplies power for the device radio. VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 10. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 8. The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used. Connection Options Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same External Component Recommendation In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. Figure 5 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-214009-00. Figure 6 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). supply. 2. Independent supply: Power VDD, VDDA, and VDDR separately. Figure 5. Recommended Host Schematic Options for a Single Supply Option Three Ferrite Bead Option Single Ferrite Bead Option Document Number: 002-09714 Rev. **
Page 10 of 40 PRELIMINARY CYBLE-214009-00 Figure 6. Recommended Host Schematic for an Independent Supply Option Document Number: 002-09714 Rev. **
Page 11 of 40 PRELIMINARY CYBLE-214009-00 The CYBLE-214009-00 schematic is shown in Figure 7. Figure 7. CYBLE-214009-00 Schematic Diagram Document Number: 002-09714 Rev. **
Page 12 of 40 PRELIMINARY CYBLE-214009-00 Critical Components List Table 6 details the critical components used in the CYBLE-214009-00 module. Table 6. Critical Component List Component Reference Designator Description U1 Y1 Y2 Silicon Crystal Crystal Antenna Design Table 7 details antenna used on the CYBLE-214009-00 module. The Cypress module performance improves many of these charac-
teristics. For more information, see Table 9. Table 7. Trace Antenna Specifications 76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE 24.000 MHz, 10PF 32.768 kHz, 12.5PF Item Frequency Range Peak Gain Average Gain Return Loss 2400 2500 MHz 0.5 dBi typical
-0.5 dBi typical 10 dB minimum Description Document Number: 002-09714 Rev. **
Page 13 of 40 PRELIMINARY CYBLE-214009-00 Electrical Specification Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 8. CYBLE-214009-00 Absolute Maximum Ratings Parameter VDDD_ABS VCCD_ABS VDDD_RIPPLE VGPIO_ABS IGPIO_ABS IGPIO_injection LU Description VDD, VDDA or VDDR supply relative to VSS (VSSD
= VSSA) Direct digital core voltage input relative to VSSD Maximum power supply ripple for VDD, VDDA and VDDR input voltage GPIO voltage Maximum current per GPIO GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS Pin current for latch up Table 9 details the RF characteristics for the Cypress BLE module. Table 9. CYBLE-214009-00 RF Performance Characteristics Parameter Description RFO RXS FR GP GAvg RL RF output power on ANT RF receive sensitivity on ANT Module frequency range Peak gain Average gain Return loss Min 0.5 0.5 0.5 25 0.5 200 Min 18 2400 Typ Max Units Details/Conditions Typ 0 91 0.5 0.5 10 6 1.95 100 VDD +0.5 25 0.5 200 Max 3 2480 V Absolute maximum V mV Absolute maximum 3.0V supply Ripple frequency of 100 kHz to 750 kHz V Absolute maximum mA Absolute maximum mA Absolute maximum current mA injected per pin simulation; High Gain Mode settings Units Details/Conditions dBm Configurable via register dBm Guaranteed by design MHz dBi dBi dB Table 10 through Table 50 list the module level electrical characteristics for the CYBLE-214009-00. All specifications are valid for 40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 10. CYBLE-214009-00 DC Specifications Parameter Description Power supply input voltage (VDD = VDDA = VDDR) Power supply input voltage unregulated (VDD =
VDDA = VDDR) Radio supply voltage (radio on) Radio supply voltage (radio off) VDD1 VDD2 VDDR1 VDDR2 Active Mode, VDD = 1.71 V to 5.5 V IDD3 IDD4 IDD5 IDD6 IDD7 Execute from flash; CPU at 3 MHz Execute from flash; CPU at 3 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 6 MHz Execute from flash; CPU at 12 MHz Min 1.71 1.71 1.9 1.71 Typ 1.8 1.7 2.5 4 Max 5.5 1.89 5.5 5.5 Units Details/Conditions V With regulator enabled Internally unregulated supply V V V mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V Document Number: 002-09714 Rev. **
Page 14 of 40 PRELIMINARY CYBLE-214009-00 Table 10. CYBLE-214009-00 DC Specifications (continued) Parameter Description IMO on ECO on WDT with WCO on Execute from flash; CPU at 48 MHz Execute from flash; CPU at 12 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 24 MHz Execute from flash; CPU at 48 MHz IDD8 IDD9 IDD10 IDD11 IDD12 Sleep Mode, VDD = 1.71 to 5.5 V IDD13 Sleep Mode, VDD and VDDR = 1.9 to 5.5 V IDD14 Deep-Sleep Mode, VDD = 1.71 to 3.6 V IDD15 IDD16 IDD17 IDD18 Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) IDD19 IDD20 Hibernate Mode, VDD = 1.71 to 3.6 V GPIO and reset active IDD27 IDD28 GPIO and reset active Hibernate Mode, VDD = 3.6 to 5.5 V IDD29 GPIO and reset active IDD30 Stop Mode, VDD = 1.71 to 3.6 V IDD33 WDT with WCO on WDT with WCO on Stop-mode current (VDD) GPIO and reset active WDT with WCO on WDT with WCO on WDT with WCO on Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) IDD34 IDD35 IDD36 Stop Mode, VDD = 3.6 to 5.5 V IDD37 Stop-mode current (VDD) IDD38 IDD39 IDD40 Stop-mode current (VDDR) Stop-mode current (VDD) Stop-mode current (VDDR) Min Typ 7.1 13.4 1.3 150 20 40 Max
-
Details/Conditions Units mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V mA T = 40 C to 85 C mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz A T = 25 C, VDD = 3.3 V A T = 40 C to 85 C A T = 25 C, VDD = 5 V A T = 40 C to 85 C A T = 25 C A T = 40 C to 85 C nA T = 25 C, VDD = 3.3 V nA T = 40 C to 85 C nA T = 25 C, VDD = 5 V nA T = 40 C to 85 C nA T = 25 C, VDD = 3.3 V nA T = 25 C, nA T = 40 C to 85 C nA T = 40 C to 85 C, VDDR = 1.9 V to 3.6 V VDDR = 3.3 V nA T = 25 C, VDD = 5 V nA T = 25 C, VDDR = 5 V nA T = 40 C to 85 C nA T = 40 C to 85 C Document Number: 002-09714 Rev. **
Page 15 of 40 PRELIMINARY CYBLE-214009-00 Table 11. AC Specifications Parameter Description CPU frequency Wakeup from Sleep mode FCPU TSLEEP TDEEPSLEEP THIBERNATE TSTOP GPIO Table 12. GPIO DC Specifications Wakeup from Deep-Sleep mode Wakeup from Hibernate mode Wakeup from Stop mode Min DC Parameter Description Min
[4]
VIH VIL VOH VOL RPULLUP RPULLDOWN IIL IIL_CTBM CIN VHYSTTL VHYSCMOS IDIODE ITOT_GPIO Input voltage HIGH threshold LVTTL input, VDD < 2.7 V LVTTL input, VDD 2.7 V Input voltage LOW threshold LVTTL input, VDD < 2.7 V LVTTL input, VDD 2.7 V Output voltage HIGH level Output voltage HIGH level Output voltage LOW level Output voltage LOW level Output voltage LOW level Pull-up resistor Pull-down resistor Input leakage current (absolute value) Input leakage on CTBm input pins Input capacitance Input hysteresis LVTTL Input hysteresis CMOS Current through protection diode to VDD/VSS Maximum total source or sink chip current 0.7 VDD 0.7 VDD 2.0 VDD 0.6 VDD 0.5 3.5 3.5 25 0.05 VDD Typ 0 Typ 5.6 5.6 40 Max 48 25 800 2 Max 0.3 VDD 0.3 VDD 0.8 0.6 0.6 0.4 8.5 8.5 2 4 7 100 200 Units MHz s s s ms Details/Conditions 1.71 V VDD 5.5 V Guaranteed by characterization 24-MHz IMO. Guaranteed by characterization Guaranteed by characterization XRES wakeup Units Details/Conditions V V V V V V V V V V V k k nA nA pF mV 1 A mA CMOS input CMOS input IOH = 4 mA at 3.3-V VDD IOH = 1 mA at 1.8-V VDD IOL = 8 mA at 3.3-V VDD IOL = 4 mA at 1.8-V VDD IOL = 3 mA at 3.3-V VDD 25 C, VDD = 3.3 V VDD > 2.7 V Note 4. VIH must not exceed VDD + 0.2 V. Document Number: 002-09714 Rev. **
Page 16 of 40 PRELIMINARY CYBLE-214009-00 Table 13. GPIO AC Specifications Parameter Description TRISEF TFALLF TRISES TFALLS FGPIOUT1 FGPIOUT2 FGPIOUT3 FGPIOUT4 FGPIOIN Rise time in Fast-Strong mode Fall time in Fast-Strong mode Rise time in Slow-Strong mode Fall time in Slow-Strong mode GPIO Fout; 3.3 V VDD 5.5 V Fast-Strong mode GPIO Fout; 1.7 V VDD 3.3 V Fast-Strong mode GPIO Fout; 3.3 V VDD 5.5 V Slow-Strong mode GPIO Fout; 1.7 V VDD 3.3 V Slow-Strong mode GPIO input operating frequency 1.71 V VDD 5.5 V Min 2 2 10 10 Typ Max 12 12 60 60 33 16.7 7 3.5 48 Units ns ns ns ns MHz MHz MHz MHz MHz Details/Conditions 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 3.3-V VDDD, CLOAD = 25 pF 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10%, 25 pF load, 60/40 duty cycle 90/10% VIO XRES Table 14. XRES DC Specifications Parameter Description Min VIH VIL RPULLUP CIN VHYSXRES IDIODE Input voltage HIGH threshold Input voltage LOW threshold Pull-up resistor Input capacitance Input voltage hysteresis Current through protection diode to VDD/VSS Table 15. XRES AC Specifications Parameter Description TRESETWIDTH Reset pulse width Analog Peripherals Opamp Table 16. Opamp Specifications 0.7 VDDD 3.5 Min 1 Typ 5.6 3 100 Typ Max 0.3 VDDD 8.5 100 Units Details/Conditions CMOS input CMOS input V V k pF mV A Max Units s Details/Conditions Parameter Description Min Typ Max Units Details/
Conditions Power = high Power = medium Power = low IDD (Opamp Block Current. VDD = 1.8 V. No Load) IDD_HI IDD_MED IDD_LOW GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V) GBW_HI GBW_MED GBW_LO IOUT_MAX (VDDA 2.7 V, 500 mV from Rail) Power = high Power = medium Power = low 6 4 1000 500 250 1 1300 350 A A A MHz MHz MHz Document Number: 002-09714 Rev. **
Page 17 of 40 PRELIMINARY CYBLE-214009-00 Table 16. Opamp Specifications (continued) Parameter Description Power = high Power = medium Power = low Power = high Power = medium Power = low Charge pump on, VDDA 2.7 V Charge pump on, VDDA 2.7 V IOUT_MAX_HI IOUT_MAX_MID IOUT_MAX_LO IOUT (VDDA = 1.71 V, 500 mV from Rail) IOUT_MAX_HI IOUT_MAX_MID IOUT_MAX_LO VIN VCM VOUT (VDDA 2.7 V) VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOS_TR VOS_TR VOS_TR VOS_DR_TR VOS_DR_TR VOS_DR_TR CMRR Power = high, ILOAD=10 mA Power = high, ILOAD=1 mA Power = medium, ILOAD=1 mA Power = low, ILOAD=0.1 mA Offset voltage, trimmed Offset voltage, trimmed Offset voltage, trimmed Offset voltage drift, trimmed Offset voltage drift, trimmed Offset voltage drift, trimmed DC PSRR Noise VN1 VN2 VN3 VN4 CLOAD Slew_rate T_op_wake At 1 kHz, 100-mV ripple Input referred, 1 Hz1 GHz, power = high Input referred, 1 kHz, power = high Input referred, 10 kHz, power = high Input referred, 100 kHz, power = high Stable up to maximum load. Performance specs at 50 pF Cload = 50 pF, Power = High, VDDA 2.7 V From disable to enable, no external RC dominating Min 10 10 4 4 0.05 0.05 0.5 0.2 0.2 0.2 1 10 65 70 6 Typ 5 2 0.5 1 2 3 10 10 70 85 94 72 28 15 300 Response time; power = high Response time; power = medium Response time; power = low Hysteresis Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.) TPD1 TPD2 TPD3 Vhyst_op Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V) GBW_DS IDD_DS Vos_DS Gain bandwidth product Current Offset voltage 150 400 2000 10 50 15 5 Max VDDA 0.2 VDDA 0.2 VDDA 0.5 VDDA 0.2 VDDA 0.2 VDDA 0.2 1 10 125 Details/
Conditions High mode Medium mode Low mode High mode Medium mode Low mode VDDD = 3.6 V, High-power mode VDDD = 3.6 V Units mA mA mA mA mA mA V V V V V V mV mV mV V/C V/C V/C dB dB Vrms nV/rtHz nV/rtHz nV/rtHz pF V/sec sec nsec nsec nsec mV kHz A mV Document Number: 002-09714 Rev. **
Page 18 of 40 PRELIMINARY CYBLE-214009-00 Table 16. Opamp Specifications (continued) Parameter Description Vos_dr_DS Vout_DS Vcm_DS Offset voltage drift Output voltage Common mode voltage Table 17. Comparator DC Specifications Parameter Description VOFFSET1 VOFFSET2 VOFFSET3 VHYST VICM1 VICM2 VICM3 CMRR CMRR ICMP1 ICMP2 ICMP3 ZCMP Input offset voltage, Factory trim Input offset voltage, Custom trim Input offset voltage, ultra-low-power mode Hysteresis when enabled Input common mode voltage in normal mode Input common mode voltage in low-power mode Input common mode voltage in ultra low-power mode Common mode rejection ratio Common mode rejection ratio Block current, normal mode Block current, low-power mode Block current in ultra-low-power mode DC input impedance of comparator Table 18. Comparator AC Specifications Parameter Description TRESP1 TRESP2 TRESP3 Response time, normal mode, 50-mV overdrive Response time, low-power mode, 50-mV overdrive Response time, ultra-low-power mode, 50-mV overdrive Temperature Sensor Table 19. Temperature Sensor Specifications Parameter TSENSACC Description Temperature-sensor accuracy SAR ADC Table 20. SAR ADC DC Specifications Parameter Description A_RES Resolution Min 0.2 0.2 Min 0 0 0 50 42 35 Min Details/
Conditions Typ 20 Max VDD0.2 VDD1.8 Units V/C V V Typ 12 10 6 Typ 38 70 2.3 Max 10 6 35 VDDD 0.1 VDDD VDDD 1.15 400 100 Units Details/
Conditions mV mV mV mV V V V dB dB A A A M Modes 1 and 2 VDDD 2.7 V VDDD 2.7 V Max Units ns ns s Details/
Conditions 50-mV overdrive 50-mV overdrive 200-mV overdrive Min 5 Typ 1 Max 5 Units C Details/Conditions 40 to +85 C Min Typ Max 12 Units bits Details/Conditions Document Number: 002-09714 Rev. **
Page 19 of 40 PRELIMINARY CYBLE-214009-00 Table 20. SAR ADC DC Specifications A_CHNIS_S A-CHNKS_D Number of channels - single-ended Number of channels - differential A-MONO A_GAINERR Monotonicity Gain error A_OFFSET Input offset voltage A_ISAR A_VINS A_VIND A_INRES A_INCAP VREFSAR Current consumption Input voltage range - single-ended Input voltage range - differential Input resistance Input capacitance Trimmed internal reference to SAR VSS VSS 1 8 4 0.1 2 1 VDDA VDDA 2.2 10 1 Table 21. SAR ADC AC Specifications Parameter Description Min Typ Max A_PSRR A_CMRR A_SAMP Fsarintref A_SNR A_BW A_INL A_INL A_INL A_dnl A_DNL A_DNL A_THD Power-supply rejection ratio Common-mode rejection ratio Sample rate SAR operating speed without external ref. bypass Signal-to-noise ratio (SNR) Input bandwidth without aliasing Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps Total harmonic distortion 70 66 65 1.7 1.5 1.5 1 1 1 1 100 A_SAMP/2 2 1.7 1.7 2.2 2 2.2 65 8 full-speed Diff inputs use neighboring I/O Yes With external reference Measured with 1-V VREF Percentage of Vbg
(1.024 V) Details/
Conditions Measured at 1-V reference 806 Ksps for More Part Numbers devices 12-bit resolution FIN = 10 kHz VREF = 1 V to VDD VREF = 1.71 V to VDD VREF = 1 V to VDD VREF = 1 V to VDD VREF = 1.71 V to VDD VREF = 1 V to VDD
%
mV mA V V k pF
%
Units dB dB Msps Ksps dB kHz LSB LSB LSB LSB LSB LSB dB FIN = 10 kHz CSD CSD Block Specifications Parameter Description VCSD Voltage range of operation Min 1.71 Typ Max 5.5 Units V Details/
Conditions Document Number: 002-09714 Rev. **
Page 20 of 40 PRELIMINARY CYBLE-214009-00 CSD Block Specifications (continued) Parameter Description Min Typ Max Units Details/
Conditions IDAC1 IDAC1 IDAC2 IDAC2 SNR IDAC1_CRT1 IDAC1_CRT2 IDAC2_CRT1 IDAC2_CRT2 DNL for 8-bit resolution INL for 8-bit resolution DNL for 7-bit resolution INL for 7-bit resolution Ratio of counts of finger to noise Output current of IDAC1 (8 bits) in High range Output current of IDAC1 (8 bits) in Low range Output current of IDAC2 (7 bits) in High range Output current of IDAC2 (7 bits) in Low range Digital Peripherals Timer Table 22. Timer DC Specifications Parameter ITIM1 ITIM2 ITIM3 Description Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Table 23. Timer AC Specifications Parameter TTIMFREQ TCAPWINT TCAPWEXT TTIMRES TTENWIDINT TTENWIDEXT TTIMRESWINT TTIMRESEXT Description Operating frequency Capture pulse width (internal) Capture pulse width (external) Timer resolution Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) 1 3 1 3 5 Min Min FCLK 2 TCLK 2 TCLK TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Counter Table 24. Counter DC Specifications Parameter ICTR1 ICTR2 ICTR3 Description Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Min 612 306 305 153 Typ Typ Typ 1 3 1 3 Max 42 130 535 Max 48 Max 42 130 535 LSB LSB LSB LSB Ratio Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan A A A A Units A A A Units MHz ns ns ns ns ns ns ns Units A A A Details/Conditions 16-bit timer 16-bit timer 16-bit timer Details/Conditions Details/Conditions 16-bit counter 16-bit counter 16-bit counter Document Number: 002-09714 Rev. **
Page 21 of 40 PRELIMINARY CYBLE-214009-00 Table 25. Counter AC Specifications Parameter Description TCTRFREQ Operating frequency TCTRPWINT Capture pulse width (internal) TCTRPWEXT Capture pulse width (external) TCTRES Counter Resolution TCENWIDINT Enable pulse width (internal) TCENWIDEXT Enable pulse width (external) TCTRRESWINT Reset pulse width (internal) TCTRRESWEXT Reset pulse width (external) Min FCLK 2 TCLK 2 TCLK TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Pulse Width Modulation (PWM) Table 26. PWM DC Specifications Parameter Description IPWM1 IPWM2 IPWM3 Table 27. PWM AC Specifications Block current consumption at 3 MHz Block current consumption at 12 MHz Block current consumption at 48 MHz Parameter TPWMFREQ TPWMPWINT TPWMEXT TPWMKILLINT TPWMKILLEXT TPWMEINT TPWMENEXT TPWMRESWINT TPWMRESWEXT Description Operating frequency Pulse width (internal) Pulse width (external) Kill pulse width (internal) Kill pulse width (external) Enable pulse width (internal) Enable pulse width (external) Reset pulse width (internal) Reset pulse width (external) LCD Direct Drive Table 28. LCD Direct Drive DC Specifications Min Min FCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK 2 TCLK Details/Conditions Details/Conditions 16-bit PWM 16-bit PWM 16-bit PWM Details/Conditions Typ Typ Typ Max 48 Max 42 130 535 Max 48 Units MHz ns ns ns ns ns ns ns Units A A A Units MHz ns ns ns ns ns ns ns ns Spec ID SID228 SID229 SID230 SID231 SID232 Parameter Description ILCDLOW CLCDCAP LCDOFFSET ILCDOP1 ILCDOP2 Operating current in low-power mode LCD capacitance per segment/common driver Long-term segment offset LCD system operating current VBIAS = 5 V LCD system operating current VBIAS = 3.3 V Min Typ 17.5 500 20 2 2 Max Units Details/Conditions 16 4 small segment A display at 50 Hz 5000 pF mV mA 32 4 segments. 50 Hz at 25 C mA 32 4 segments 50 Hz at 25 C Table 29. LCD Direct Drive AC Specifications Spec ID SID233 Parameter FLCD Description LCD frame rate Min 10 Typ 50 Max 150 Units Hz Details/Conditions Document Number: 002-09714 Rev. **
Page 22 of 40 PRELIMINARY CYBLE-214009-00 Serial Communication Table 30. Fixed I2C DC Specifications Parameter Description Block current consumption at 100 kHz Block current consumption at 400 kHz Block current consumption at 1 Mbps I2C enabled in Deep-Sleep mode II2C1 II2C2 II2C3 II2C4 Table 31. Fixed I2C AC Specifications Parameter FI2C1 Bit rate Description Table 32. Fixed UART DC Specifications Description Parameter IUART1 IUART2 Block current consumption at 100 kbps Block current consumption at 1000 kbps Table 33. Fixed UART AC Specifications Description Parameter FUART Bit rate Table 34. Fixed SPI DC Specifications Parameter ISPI1 ISPI2 ISPI3 Description Block current consumption at 1 Mbps Block current consumption at 4 Mbps Block current consumption at 8 Mbps Min Min Min Min Min Typ Typ Typ Typ Typ Max 50 155 390 1.4 Units A A A A Max 400 Units kHz Max 55 312 Units A A Details/Conditions Details/Conditions Details/Conditions Max 1 Units Mbps Details/Conditions Max 360 560 600 Units A A A Details/Conditions Table 35. Fixed SPI AC Specifications Parameter FSPI Description SPI operating frequency (master; 6x over sampling) Min Typ Max 8 Units MHz Details/Conditions Table 36. Fixed SPI Master Mode AC Specifications Parameter Description TDMO TDSI THMO MOSI valid after SCLK driving edge MISO valid before SCLK capturing edge Full clock, late MISO sampling used Previous MOSI data hold time Min 20 0 Table 37. Fixed SPI Slave Mode AC Specifications Parameter Description TDMI TDSO TDSO_ext THSO TSSELSCK MOSI valid before SCLK capturing edge MISO valid after SCLK driving edge MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V Previous MISO data hold time SSEL valid to first SCK valid edge Typ Max Units 18 ns Details/Conditions ns ns Full clock, late MISO sampling Referred to Slave capturing edge Min 40 0 100 Typ Max 42 + 3 TCPU 50 Units ns ns ns ns ns Document Number: 002-09714 Rev. **
Page 23 of 40 PRELIMINARY CYBLE-214009-00 Memory Table 38. Flash DC Specifications Parameter Description VPE TWS48 TWS32 TWS16 Table 39. Flash AC Specifications Erase and program voltage Number of Wait states at 3248 MHz Number of Wait states at 1632 MHz Number of Wait states for 016 MHz Parameter
[5]
TROWWRITE
[5]
TROWERASE TROWPROGRAM
[5]
TBULKERASE
[5]
TDEVPROG FEND FRET FRET2 Description Row (block) write time (erase and program) Row erase time
[5] Row program time after erase Bulk erase time (256 KB) Total device program time Flash endurance Flash retention. TA 55 C, 100 K P/E cycles Flash retention. TA 85 C, 10 K P/E cycles System Resources Power-on-Reset (POR) Table 40. POR DC Specifications Parameter VRISEIPOR VFALLIPOR VIPORHYST Description Rising trip voltage Falling trip voltage Hysteresis Table 41. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 42. Brown-Out Detect Parameter VFALLPPOR VFALLDPSLP Description BOD trip voltage in Active and Sleep modes BOD trip voltage in Deep Sleep Min 1.71 2 1 0 Min 100 K 20 10 Min 0.80 0.75 15 Min Min 1.64 1.4 Typ Typ Typ Typ Typ Max 5.5 Max 20 13 7 35 25 Max 1.45 1.40 200 Units V Details/Conditions CPU execution from flash CPU execution from flash CPU execution from flash Units ms ms ms ms seconds cycles years years Details/Conditions Row (block) = 256 bytes Units Details/Conditions V V mV Max Units Details/Conditions 1 s Max Units Details/Conditions V V Table 43. Hibernate Reset Parameter VHBRTRIP Description BOD trip voltage in Hibernate Min 1.1 Typ Max Units V Details/Conditions Note 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-09714 Rev. **
Page 24 of 40 Voltage Monitors (LVD) Table 44. Voltage Monitor DC Specifications Parameter Description VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 VLVI10 VLVI11 VLVI12 VLVI13 VLVI14 VLVI15 VLVI16 LVI_IDD LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b Block current Table 45. Voltage Monitor AC Specifications Parameter TMONTRIP Description Voltage monitor trip time SWD Interface Table 46. SWD Interface Specifications Description 3.3 V VDD 5.5 V 1.71 V VDD 3.3 V Parameter F_SWDCLK1 F_SWDCLK2 T_SWDI_SETUP T = 1/f SWDCLK T_SWDI_HOLD T = 1/f SWDCLK T_SWDO_VALID T = 1/f SWDCLK T_SWDO_HOLD T = 1/f SWDCLK PRELIMINARY CYBLE-214009-00 Min 1.71 1.76 1.85 1.95 2.05 2.15 2.24 2.34 2.44 2.54 2.63 2.73 2.83 2.93 3.12 4.39 Min Min 0.25 T 0.25 T 1 Typ 1.75 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.20 4.50 Typ Typ Max 1.79 1.85 1.95 2.05 2.15 2.26 2.36 2.46 2.56 2.67 2.77 2.87 2.97 3.08 3.28 4.61 100 Units Details/Conditions V V V V V V V V V V V V V V V V A Max 1 Units s Details/Conditions Max 14 7 0.5 T Units MHz MHz ns ns ns ns Details/Conditions SWDCLK 1/3 CPU clock frequency SWDCLK 1/3 CPU clock frequency Document Number: 002-09714 Rev. **
Page 25 of 40 PRELIMINARY CYBLE-214009-00 Internal Main Oscillator Table 47. IMO DC Specifications Parameter Description IIMO1 IIMO2 IIMO3 IIMO4 IIMO5 IMO operating current at 48 MHz IMO operating current at 24 MHz IMO operating current at 12 MHz IMO operating current at 6 MHz IMO operating current at 3 MHz Table 48. IMO AC Specifications Parameter FIMOTOL3 FIMOTOL3 Description Frequency variation from 3 to 48 MHz IMO startup time Internal Low-Speed Oscillator Table 49. ILO DC Specifications Parameter IILO2 Description ILO operating current at 32 kHz Table 50. ILO AC Specifications Parameter TSTARTILO1 FILOTRIM1 Description ILO startup time 32-kHz trimmed frequency Table 51. ECO Trim Value Specification Description Parameter ECOTRIM 24-MHz trim value
(firmware configuration) Table 52. UDB AC Specifications Min Min Min Min 15 Typ Typ 12 Typ 0.3 Typ 32 Max 1000 325 225 180 150 Max 2 Units A A A A A Units
%
s Details/Conditions Details/Conditions With API-called calibration Max 1.05 Units A Details/Conditions Max 2 50 Units ms kHz Details/Conditions Value Details/Conditions 0x00003FFA Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Parameter Description Min Typ Max Units Details/Conditions Data Path performance FMAX-TIMER FMAX-ADDER FMAX_CRC Max frequency of 16-bit timer in a UDB pair Max frequency of 16-bit adder in a UDB pair Max frequency of 16-bit CRC/PRS in a UDB pair PLD Performance in UDB FMAX_PLD Max frequency of 2-pass PLD function in a UDB pair Clock to Output Performance TCLK_OUT_UDB1 TCLK_OUT_UDB2 Prop. delay for clock in to data out at 25 C, Typical Prop. delay for clock in to data out, Worst case 15 25 48 48 48 48 MHz MHz MHz MHz ns ns Document Number: 002-09714 Rev. **
Page 26 of 40 PRELIMINARY CYBLE-214009-00 Table 53. BLE Subsystem Parameter Description Min Typ Max Units RF Receiver Specification RXS, IDLE RX sensitivity with idle transmitter RX sensitivity with idle transmitter excluding Balun loss RX sensitivity with dirty transmitter RX sensitivity in high-gain mode with idle transmitter Maximum input power Cochannel interference, Wanted signal at 67 dBm and Interferer at FRX Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 1 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 2 MHz Adjacent channel interference Wanted signal at 67 dBm and Interferer at FRX 3 MHz Adjacent channel interference Wanted Signal at 67 dBm and Interferer at Image frequency (FIMAGE) Adjacent channel interference Wanted signal at 67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 302000 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 20032399 MHz Out-of-band blocking, Wanted signal at 67 dBm and Interferer at F = 24842997 MHz Out-of-band blocking, Wanted signal a 67 dBm and Interferer at F = 300012750 MHz Intermodulation performance Wanted signal at 64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel Receiver spurious emission 30 MHz to 1.0 GHz 10 89 91 87 91 1 9 3 29 39 20 30 30 27 35 27 35 27 30 27 50 RXS, DIRTY RXS, HIGHGAIN PRXMAX CI1 CI2 CI3 CI4 CI5 CI3 OBB1 OBB2 OBB3 OBB4 IMD RXSE1 Details/
Conditions Guaranteed by design simulation RF-PHY Specification
(RCV-LE/CA/01/C) RF-PHY Specification
(RCV-LE/CA/06/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/03/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/04/C) RF-PHY Specification
(RCV-LE/CA/05/C) 70 21 15 dBm dBm dBm dBm dBm dB dB dB dB dB dB dBm dBm dBm dBm dBm 57 dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 Document Number: 002-09714 Rev. **
Page 27 of 40 PRELIMINARY CYBLE-214009-00 Table 53. BLE Subsystem (continued) Parameter Description Min Typ RXSE2 Receiver spurious emission 1.0 GHz to 12.75 GHz RF Transmitter Specifications TXP, ACC TXP, RANGE TXP, 0dBm TXP, MAX RF power accuracy RF power control range Output power, 0-dB Gain setting (PA7) Output power, maximum power setting
(PA10) Output power, minimum power setting
(PA1) Average frequency deviation for 10101010 pattern Average frequency deviation for 11110000 pattern Eye opening = F2AVG/F1AVG TXP, MIN F2AVG F1AVG EO FTX, ACC Frequency accuracy FTX, MAXDR Maximum frequency drift FTX, INITDR Initial frequency drift FTX, DR Maximum drift rate IBSE1 IBSE2 TXSE1 TXSE2 In-band spurious emission at 2-MHz offset In-band spurious emission at 3-MHz offset Transmitter spurious emissions
(average), <1.0 GHz Transmitter spurious emissions
(average), >1.0 GHz RF Current Specifications IRX IRX_RF IRX, HIGHGAIN ITX, 3dBm ITX, 0dBm ITX_RF, 0dBm ITX_RF, 0dBm Receive current in normal mode Radio receive current in normal mode Receive current in high-gain mode TX current at 3-dBm setting (PA10) TX current at 0-dBm setting (PA7) Radio TX current at 0 dBm setting (PA7) Radio TX current at 0 dBm excluding Balun loss TX current at 3-dBm setting (PA4) TX current at 6-dBm setting (PA3) ITX,-3dBm ITX,-6dBm Max 47 Units dBm Details/
Conditions 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 275 150 50 20 20 20
-30
-55.5
-41.5 dB dB dBm dBm dBm kHz kHz kHz kHz kHz kHz/
50 s dBm dBm dBm dBm mA mA mA mA mA mA mA mA mA RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/05/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/06/C) RF-PHY Specification
(TRM-LE/CA/03/C) RF-PHY Specification
(TRM-LE/CA/03/C) FCC-15.247 FCC-15.247 Measured at VDDR Measured at VDDR Guaranteed by design simulation 185 225 0.8 150 50 20 20 1 20 0 3 18 250 18.7 16.4 21.5 20 16.5 15.6 14.2 15.5 14.5 Document Number: 002-09714 Rev. **
Page 28 of 40 PRELIMINARY CYBLE-214009-00 Table 53. BLE Subsystem (continued) Parameter Description Min ITX,-12dBm ITX,-18dBm Iavg_1sec, 0dBm TX current at 12-dBm setting (PA2) TX current at 18-dBm setting (PA1) Average current at 1-second BLE connection interval Iavg_4sec, 0dBm Average current at 4-second BLE connection interval RF operating frequency Channel spacing On-air data rate BLE.IDLE to BLE. TX transition time BLE.IDLE to BLE. RX transition time General RF Specifications FREQ CHBW DR IDLE2TX IDLE2RX RSSI Specifications RSSI, ACC RSSI, RES RSSI, PER RSSI accuracy RSSI resolution RSSI sample period 2400 Typ 13.2 12.5 17.1 6.1 2 1000 120 75 5 1 6 Max Units Details/
Conditions TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange 2482 140 120 mA mA A A MHz MHz kbps s s dB dB s Document Number: 002-09714 Rev. **
Page 29 of 40 PRELIMINARY CYBLE-214009-00 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-214009-00 module is certified under the following RF certification standards:
n FCC ID: WAP4008 n CE n IC: 7922A-4008 n MIC (Japan) n KC: MSIP-CRM-Cyp-4008 Environmental Conditions Table 54 describes the operating and storage conditions for the Cypress BLE module. Table 54. Environmental Conditions for CYBLE-214009-00 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[6]
-40 C 5%
40 C 85 C 85%
3 C/minute 85 C 85 C at 85%
15 kV Air 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-09714 Rev. **
Page 30 of 40 PRELIMINARY CYBLE-214009-00 Regulatory Information FCC FCC NOTICE:
The device CYBLE-214009-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
n Reorient or relocate the receiving antenna. n Increase the separation between the equipment and receiver. n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. n Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008. In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 13. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-214009-00 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-214009-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-09714 Rev. **
Page 31 of 40 PRELIMINARY CYBLE-214009-00 Industry Canada (IC) Certification CYBLE-214009-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-4008 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 13, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. IC NOTICE:
The device CYBLE-214009-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. IC RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC:
7922A-4008". European R&TTE Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-214009-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-214009-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-
bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-09714 Rev. **
Page 32 of 40 PRELIMINARY CYBLE-214009-00 MIC Japan CYBLE-214009-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-214009-00 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-214009-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008 Document Number: 002-09714 Rev. **
Page 33 of 40 PRELIMINARY CYBLE-214009-00 Ordering Information The CYBLE-214009-00 part number and features are listed in the following table. Features MPN
) z H M
(
d e e p S U P C x a M
) B K
(
h s a F l
) B K
(
M A R S B D U
) m B T C
(
p m a p O e s n e S p a C e v i r D D C L t c e r i D C D A R A S t i b
-
2 1 s r o t a r a p m o C P L l s k c o B M W P C T l s k c o B B C S
) s B D U g n s u
(
i s M W P
) B D U g n s u
(
i S 2 I e g a k c a P I O P G 48 CYBLE-214009-00 256 Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. 3 3 1 Msps 32 4 1 4 4 2 4 3 25 32-SMT For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-09714 Rev. **
Page 34 of 40 PRELIMINARY CYBLE-214009-00 Acronyms Table 55. Acronyms Used in this Document Acronym Description ABUS ADC AG AHB ALU AMUXBUS API APSR ARM ATM BLE Bluetooth SIG BW CAN CE CSA CMRR CPU CRC DAC DFB DIO DMIPS DMA DNL DNU DR DSI DWT ECC ECO EEPROM EMI analog local bus analog-to-digital converter analog global AMBA (advanced microcontroller bus archi-
tecture) high-performance bus, an ARM data transfer bus arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode Bluetooth Low Energy Bluetooth Special Interest Group bandwidth Controller Area Network, a communications protocol European Conformity Canadian Standards Association common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO. Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference Table 55. Acronyms Used in this Document (continued) Acronym Description EMIF EOC EOF EPSR ESD ETM FCC FET FIR FPB FS GPIO HCI HVI IC IDAC IDE I2C, or IIC IC IIR ILO IMO INL I/O IPOR IPSR IRQ ITM KC LCD LIN LR LUT LVD LVI LVTTL external memory interface end of conversion end of frame execution program status register electrostatic discharge embedded trace macrocell Federal Communications Commission field-effect transistor finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin host controller interface high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment Inter-Integrated Circuit, a communications protocol Industry Canada infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell Korea Certification liquid crystal display Local Interconnect Network, a communications protocol. link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic Document Number: 002-09714 Rev. **
Page 35 of 40 PRELIMINARY CYBLE-214009-00 Table 55. Acronyms Used in this Document (continued) Table 55. Acronyms Used in this Document (continued) Acronym Description Acronym Description MAC MCU MIC MISO NC NMI NRZ NVIC NVL Opamp PAL PC PCB PGA PHUB PHY PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC PSRR PWM QDID RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL multiply-accumulate microcontroller unit Ministry of Internal Affairs and Communications
(Japan) master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-Chip power supply rejection ratio pulse-width modulator qualification design ID random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I2C serial clock SDA S/H SINAD SIO SMT SOC SOF SPI SR SRAM SRES STN SWD SWV TD THD TIA TN TRM TTL TUV TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL I2C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. surface-mount technology; a method for producing electronic circuitry in which the compo-
nents are placed directly onto the surface of PCBs start of conversion start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset super twisted nematic serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier twisted nematic technical reference manual transistor-transistor logic Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Document Number: 002-09714 Rev. **
Page 36 of 40 PRELIMINARY CYBLE-214009-00 Document Conventions Units of Measure Table 56. Units of Measure Symbol Unit of Measure C dB dBm fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V degrees Celsius decibel decibel-milliwatts femtofarads hertz 1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt Document Number: 002-09714 Rev. **
Page 37 of 40 PRELIMINARY CYBLE-214009-00 Errata This section describes the errata for the CYBLE-214009-00 module. Details include errata trigger conditions, scope of impact, and available workarounds. Contact your local Cypress Sales Representative if you have questions. Errata Summary 1. CapSense is not enabled in PSoC Creator. n PROBLEM DEFINITION CapSense Support for CYBLE-214009-00 is not enabled in PSoC Creator 3.3. n PARAMETERS AFFECTED None n TRIGGER CONDITIONS Applicatoins that need CapSense functionality will not be able to enable it with PSoC Creator 3.3. n SCOPE OF IMPACT None n WORKAROUND No work aruond with PSoC Creator 3.3. n FIX STATUS This issue will be fixed in November, 2015 on a future PSoC Creator release. n CHANGES None Document Number: 002-09714 Rev. **
Page 38 of 40 PRELIMINARY CYBLE-214009-00 Document History Page Document Title: CYBLE-214009-00 EZ-BLETM PSoC Module Document Number: 002-09714 Orig. of Revision Change Submission Date ECN
**
DSO Description of Change 10/29/2015 Preliminary datasheet for CYBLE-214009-00 module. Document Number: 002-09714 Rev. **
Page 39 of 40 PRELIMINARY CYBLE-214009-00 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 002-09714 Rev. **
Revised October 29, 2015 Page 40 of 40 All products and company names mentioned in this document may be the trademarks of their respective holders.
| frequency | equipment class | purpose | ||
|---|---|---|---|---|
| 1 | 2016-09-06 | 2402 ~ 2480 | DTS - Digital Transmission System | Class II permissive change or modification of presently authorized equipment |
| 2 | 2015-12-11 | 2402 ~ 2480 | DTS - Digital Transmission System | Original Equipment |
| app s | Applicant Information | |||||
|---|---|---|---|---|---|---|
| 1 2 | Effective |
2016-09-06
|
||||
| 1 2 |
2015-12-11
|
|||||
| 1 2 | Applicant's complete, legal business name |
Cypress Semiconductor
|
||||
| 1 2 | FCC Registration Number (FRN) |
0017759150
|
||||
| 1 2 | Physical Address |
198 Champion Court
|
||||
| 1 2 |
San Jose, California 95134
|
|||||
| 1 2 |
United States
|
|||||
| app s | TCB Information | |||||
| 1 2 | TCB Application Email Address |
V******@tuvam.com
|
||||
| 1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
| app s | FCC ID | |||||
| 1 2 | Grantee Code |
WAP
|
||||
| 1 2 | Equipment Product Code |
4008
|
||||
| app s | Person at the applicant's address to receive grant or for contact | |||||
| 1 2 | Name |
D****** S******
|
||||
| 1 2 | Title |
Sr. Business Unit Director
|
||||
| 1 2 | Telephone Number |
408-5********
|
||||
| 1 2 | Fax Number |
408-5********
|
||||
| 1 2 |
d******@cypress.com
|
|||||
| app s | Technical Contact | |||||
| n/a | ||||||
| app s | Non Technical Contact | |||||
| n/a | ||||||
| app s | Confidentiality (long or short term) | |||||
| 1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
| 1 2 | Yes | |||||
| 1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
| if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
| app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
| 1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
| 1 2 | Equipment Class | DTS - Digital Transmission System | ||||
| 1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Bluetooth Module | ||||
| 1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
| 1 2 | Modular Equipment Type | Single Modular Approval | ||||
| 1 2 | Purpose / Application is for | Class II permissive change or modification of presently authorized equipment | ||||
| 1 2 | Original Equipment | |||||
| 1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
| 1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
| 1 2 | Grant Comments | C2PC as described in this filing. Modular Approval. Output power is peak conducted. | ||||
| 1 2 | Modular Approval. Output power is peak conducted. The antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons. End-users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. | |||||
| 1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
| 1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
| app s | Test Firm Name and Contact Information | |||||
| 1 2 | Firm Name |
DEKRA Testing and Certification (Suzhou) Co., Ltd.
|
||||
| 1 2 | Name |
J**** P******
|
||||
| 1 2 | Telephone Number |
86-51******** Extension:
|
||||
| 1 2 | Fax Number |
86-51********
|
||||
| 1 2 |
j******@quietek.com.cn
|
|||||
| Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
| 1 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0013600 | ||||||||||||||||||||||||||||||||||||
| Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
| 2 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0013600 | ||||||||||||||||||||||||||||||||||||
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC