FCC ID: WAP6045 AIROC Bluetooth LE module

 

PRELIMINARY CYBLE-416045-02 EZ-BLE Creator Module General Description The Cypress CYBLE-416045-02 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-416045-02 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC 63 BLE silicon device. Refer to the PSoC 63 BLE datasheet for additional details on the capabilities of the PSoC 63 BLE device used on this module. The EZ-BLE Creator module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic includes digital routing. The CYBLE-416045-02 also programmable high-performance analog-to-digital conversion (ADC), low-power comparators, and standard communication and timing peripherals. The CYBLE-416045-02 includes a royalty-free BLE stack compatible with Bluetooth 5.0 and provides up to 36 GPIOs in a 14 18.5 2.00 mm package. The CYBLE-416045-02 is a complete solution and an ideal fit for applications seeking a high performance BLE wireless solution. Module Description n Module size: 14.0 mm 18.5 mm 2.00 mm (with shield) n 1 MB Application Flash with 32-KB EEPROM area and 32-KB logic, Secure Flash n 288-KB SRAM with Selectable Retention Granularity n Up to 36 GPIOs with programmable drive modes, strengths, and slew rates n Bluetooth 5.0 qualified single-mode module p QDID: TBD p Declaration ID:TBD n Certified to FCC, CE, MIC, and ISED regulations n Industrial temperature range: 40 C to +85 C n 150-MHz Arm Cortex-M4F CPU with single-cycle multiply

(Floating Point and Memory Protection Unit) n 100-MHz Cortex M0+ CPU with single-cycle multiply and MPU. n One-Time-Programmable (OTP) E-Fuse memory for validation and security Power Consumption n TX output power: 20 dbm to +4 dbm n Received signal strength indicator (RSSI) with 4-dB resolution n TX current consumption of 5.7 mA (radio only, 0 dbm) n RX current consumption of 6.7 mA (radio only) Low power 1.7-V to 3.6-V Operation n Active, Low-power Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes for fine-grained power management n Deep Sleep mode current with 64K SRAM retention is 7 A with 3.3-V external supply and internal buck n On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter,

<1 A quiescent current n Backup domain with 64 bytes of memory and Real-Time-Clock-

Programmable Analog Serial Communication n Nine independent run-time reconfigurable serial communi-

cation blocks (SCBs), each is software configurable as I2C, SPI, or UART Timing and Pulse-Width Modulation n Thirty-two Timer/Counter Pulse-Width Modulator (TCPWM) blocks n Center-aligned, Edge, and Pseudo-random modes n Comparator-based triggering of Kill signals Capacitive Sensing n Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance n Cypress-supplied software component makes capacitive-sensing design easy n Automatic hardware-tuning algorithm (SmartSense) Serial Communication n Two independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionality Timing and Pulse-Width Modulation n Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks n Center-aligned, Edge, and Pseudo-random modes n Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIOs n Any GPIO pin can be CapSense, analog, or digital Cypress Semiconductor Corporation Document Number: 002-24085 Rev. **

198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised May 30, 2018 PRELIMINARY CYBLE-416045-02 Audio Subsystem n I2S Interface; up to 192 kilosamples (ksps) Word Clock n Two PDM channels for stereo digital microphones Programmable Analog n 12-bit 1 Msps SAR ADC with differential and single-ended modes and Sequencer with signal averaging n One 12-bit voltage mode DAC with < 5 s settling time n Two opamps with low-power operation modes n Two low-power comparators that operate in Deep Sleep and Hibernate modes. n Built-in temp sensor connected to ADC Programmable Digital n 12 programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) n Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog programmable blocks n Cypress-provided peripheral component library using UDBs to implement functions such as Communication peripherals (for example, LIN, UART, SPI, I2C, S/PDIF and other protocols), Waveform Generators, Pseudo-Random Sequence (PRS) generation, and many other functions. n Smart I/O (Programmable I/O) blocks enable Boolean operations on signals coming from, and going to, GPIO pins n Two ports with Smart_IO blocks, capability are provided; these are available during Deep Sleep Energy Profiler n Block that provides history of time spent in different power modes n Allows software energy profiling to observe and optimize energy consumption Security Built into Platform Architecture n Multi-faceted secure architecture based on ROM-based root of trust n Secure Boot uninterruptible until system protection attributes are established n Authentication during boot using hardware hashing n Step-wise authentication of execution images n Secure execution of code in execute-only mode for protected routines n All Debug and Test ingress paths can be disabled Cryptography Accelerators n Hardware acceleration for Symmetric and Asymmetric cryptographic methods (AES, 3DES, RSA, and ECC) and Hash functions (SHA-512, SHA-256) n True Random Number Generator (TRNG) function Capacitive Sensing n Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing n Mutual Capacitance sensing (Cypress CSX) with dynamic usage of both Self and Mutual sensing n Wake on Touch with very low current n Cypress-supplied software component makes capacitive sensing design fast and easy n Automatic hardware tuning (SmartSense) Document Number: 002-24085 Rev. **

Page 2 of 60 PRELIMINARY CYBLE-416045-02 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. n Overview: Module Roadmap n PSoC 63 BLE Silicon Datasheet n Application Notes:

p KBA97095 - EZ-BLE Module Placement p KBA213976 - FAQ for BLE and Regulatory Certifications with n Knowledge Base Articles p AN96841 - Getting Started with EZ-BLE Module p AN210781 - Getting Started with PSoC 6 MCU BLE p AN215656 - PSoC 6 MCU Dual-CPU System Design p AN91162 - Creating a BLE Custom Profile p AN217666 - PSoC 6 MCU Interrupts p AN91445 - Antenna Design and RF Layout Guidelines p AN213924 - PSoC 6 MCU Bootloader Guide p AN219528 - PSoC 6 MCU Power Reduction Techniques n Technical Reference Manual (TRM):

p PSoC 63 with BLE Architecture Technical Reference Manual p PSoC 63 with BLE Registers Technical Reference Manual p KBA210802 - Queries on BLE Qualification and Declaration EZ-BLE modules Processes n Development Kits:

p CYBLE-416045-EVAL, CYBLE-416045-02 Evaluation Board p CY8CKIT-062-BLE, PSoC 63 BLE Pioneer Kit n Test and Debug Tools:

p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool

(Android/iOS Mobile App) PSoC Creator Integrated Design Environment (IDE) PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can:

1. Explore the library of 200+ Components in PSoC Creator 2. Drag and drop Component icons to complete your hardware 4. Co-design your application firmware and hardware in the PSoC Creator IDE or build project for 3rd party IDE system design in the main design workspace 3. Configure Components using the Component Configuration Tools and the Component datasheets 5. Prototype your solution with the PSoC 6 Pioneer Kits.If a design change is needed, PSoC Creator and Components enable you to make changes on the fly without the need for hardware revisions. Figure 1. PSoC Creator Schematic Entry and Components Document Number: 002-24085 Rev. **

Page 3 of 60 PRELIMINARY CYBLE-416045-02 Contents Functional Definition........................................................ 5 CPU and Memory Subsystem ..................................... 5 System Resources ...................................................... 5 BLE Radio and Subsystem ......................................... 6 Analog Blocks.............................................................. 6 Programmable Digital.................................................. 7 Fixed-Function Digital.................................................. 7 GPIO ........................................................................... 8 Special-Function Peripherals ...................................... 8 Module Overview.............................................................. 9 Module Description...................................................... 9 Pad Connection Interface .............................................. 11 Recommended Host PCB Layout ................................. 12 Digital and Analog Capablities and Connections........ 14 Power............................................................................... 17 Critical Components List ........................................... 19 Antenna Design......................................................... 19 Electrical Specification .................................................. 20 Device-Level Specifications ...................................... 20 Analog Peripherals .................................................... 28 Digital Peripherals ..................................................... 36 Memory ..................................................................... 38 System Resources .................................................... 39 Environmental Specifications ....................................... 49 Environmental Compliance ....................................... 49 RF Certification.......................................................... 49 Environmental Conditions ......................................... 49 ESD and EMI Protection ........................................... 49 Regulatory Information.................................................. 50 FCC........................................................................... 50 ISED.......................................................................... 51 European Declaration of Conformity ......................... 52 MIC Japan................................................................. 52 Packaging........................................................................ 53 Ordering Information...................................................... 55 Part Numbering Convention...................................... 55 Acronyms........................................................................ 56 Document Conventions ................................................. 58 Units of Measure ....................................................... 58 Document History Page................................................. 59 Sales, Solutions, and Legal Information ...................... 60 Worldwide Sales and Design Support....................... 60 Products .................................................................... 60 PSoC Solutions ...................................................... 60 Cypress Developer Community................................. 60 Technical Support ..................................................... 60 Document Number: 002-24085 Rev. **

Page 4 of 60 PRELIMINARY CYBLE-416045-02 includes Functional Definition CPU and Memory Subsystem CPU The CPU subsystem in the More Part Numbers consists of two Arm Cortex cores and their associated busses and memories:

M4 with Floating-point unit and Memory Protection Units (FPU and MPU) and an M0+ with an MPU. The Cortex M4 and M0+

have 8-KB Instruction Caches (I-Cache) with 4-way set associa-

tivity. This subsystem also independent DMA controllers with 32 channels each, a Cryptographic accelerator block, 1 MB of on-chip Flash, 288 KB of SRAM, and 128 KB of ROM. The Cortex M0+ provides a secure, un-interruptible Boot function. This guarantees that post-Boot, system integrity is checked and privileges enforced. Shared resources can be accessed through the normal Arm multi-layer bus arbitration and exclusive accesses are supported by an Inter-Processor Communication (IPC) scheme, which implements hardware semaphores and protection. Active power consumption for the Cortex M4 is 22 A/MHz and 15 A/MHz for the Cortex M0+, both at 3.3 V chip supply voltage with the internal buck enabled and at 0.9 V internal supply. Note that at Cortex M4 speeds above 100 MHz, the M0+ and Peripheral subsystem are limited to half the M4 speed. If the M4 is running at 150 Mhz, the M0+and peripheral subsystem is limited to 75 MHz. DMA Controllers There are two DMA controllers with 16 channels each. They support independent accesses to peripherals using the AHB Multi-layer bus. Flash CYBLE-416045-02 has 1-MB of flash with additional 32K of Flash that can be used for EEPROM emulation for longer retention and a separate 32-KB block of Flash that can be securely locked and is only accessible via a key lock that cannot be changed (One Time Programmable). SRAM with 32-KB Retention Granularity There is 288 KB of SRAM memory, which can be fully retained or retained in increments of user-designated 32-KB blocks. SROM There is a supervisory 128-KB ROM that contains boot and configuration routines. This ROM will guarantee Secure Boot if authentication of User Flash is required. One-Time-Programmable (OTP) eFuse The 1024-bit OTP memory can provide a unique and unalterable Identifier on a per-chip basis. This unalterable key can be used to access Secured Flash. System Resources Power System The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) when the power supply drops below specified levels. The design will guaranteed safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the Reset occurring. There are no voltage sequencing requirements. The VDD core logic supply

(1.7 to 3.6 V) will feed an on-chip buck, which will produce the core logic supply of either 1.1 V or 0.9 V selectable. Depending on the frequency of operation, the buck converter will have a quiescent current of <1 A. A separate power domain called Backup is provided; note this is not a power mode. This domain is powered from the VBACKUP domain and includes the 32-kHz WCO, RTC, and backup registers. It is connected to VDD when not used as a backup domain. Port 0 is powered from this supply. Pin 5 of Port 0 (P0.5) can be assigned as a PMIC wakeup output

(timed by the RTC); P0.5 is driven to the resistive pull-up mode by default. Clock System The Part Number clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for the CYBLE-416045-02 consists of the Internal Main Oscillator (IMO) and the Internal Low-speed Oscil-

lator (ILO), crystal oscillators (ECO and WCO), PLL, FLL, and provision for an external clock. An FLL will provide fast wake-up at high clock speeds without waiting for a PLL lock event (which can take up to 50 s). Clocks may be buffered and brought out to a pin on a Smart I/O port. The 32-kHz oscillator is trimmable to within 2 ppm using a higher accuracy clock. The ECO will deliver 20-ppm accuracy and will use an external crystal. IMO Clock Source The IMO is the primary source of internal clocking in More Part Numbers. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz. IMO tolerance is 2% and its current consumption is less than 10 A. ILO Clock Source The ILO is a very low power oscillator, nominally 32 kHz, which may be used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Document Number: 002-24085 Rev. **

Page 5 of 60 PRELIMINARY CYBLE-416045-02 for external reset Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows watchdog operation during Deep Sleep and Hibernate modes, and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. Clock Dividers Integer and Fractional clock dividers are provided for peripheral use and timing purposes. There are eight 8-bit integer and sixteen 16-bit integer clock dividers. There is also one 24.5-bit fractional and four 16.5-bit fractional clock dividers. Reset The More Part Numbers can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the Reset. An XRES pin is reserved to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. BLE Radio and Subsystem Part Number incorporates a Bluetooth Smart subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 2 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 5.0. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50- antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna. Key features of BLESS are as follows:

n Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols n API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP n L2CAP connection-oriented channel (Bluetooth 4.1 feature) n GAP features p Broadcaster, Observer, Peripheral, and Central roles p Security mode 1: Level 1, 2, and 3 p User-defined advertising data p Multiple bond support n GATT features p GATT client and server p Supports GATT sub-procedures p 32-bit universally unique identifier (UUID) (Bluetooth 4.1 feature) n Security Manager (SM) p Pairing methods: Just works, Passkey Entry, and Out of Band p LE Secure Connection Pairing model p Authenticated man-in-the-middle (MITM) protection and data signing n Link Layer (LL) p Master and Slave roles p 128-bit AES engine p Low-duty cycle advertising p LE Ping n Supports all SIG-adopted BLE profiles n Power levels for Adv (1.28s, 31 bytes, 0 dBm) and Con

(300 ms, 0 byte, 0 dBm) are 42 W and 70 W respectively Analog Blocks 12-bit SAR ADC The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. The block functionality is augmented for the user by adding a reference buffer to it (trimmable to 1%) and by providing the choice of three internal voltage references, VDD, VDD/2, and VREF (nominally 1.024 V), as well as an external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is programmable; it allows the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used and system noise levels permit it. To improve the perfor-

mance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A feature provided by the sequencer is the buffering of each channel to reduce CPU interrupt-service requirements. To accommodate signals with varying source impedances and frequencies, it is possible to have different sample times programmable for each channel. Also, the signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. There are 16 channels of which any 13 can be sampled in a single scan. Document Number: 002-24085 Rev. **

Page 6 of 60 PRELIMINARY CYBLE-416045-02 for calibration and other The SAR is able to digitize the output of the on-chip temperature sensor temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 V to 3.6 V. Temperature Sensor Part Number has an on-chip temperature sensor. This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temper-

ature value by using a Cypress-supplied software that includes calibration and linearization. 12-bit Digital-Analog Converter There is a 12-bit voltage mode DAC on the chip, which can settle in less than 5 s. The DAC may be driven by the DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output. Continuous Time Block (CTBm) with Two Opamps This block consists of two opamps, which have their inputs and outputs connected to fixed pins and have three power modes and a comparator mode. The outputs of these opamps can be used as buffers for the SAR inputs. The non-inverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware. The opamps can be set to one of the four power levels; the lowest level allowing operation in Deep Sleep mode in order to preserve lower perfor-

mance Continuous-Time functionality in Deep Sleep mode. The DAC output can be buffered through an opamp. Low-Power Comparators CYBLE-416045-02 has a pair of low-power comparators, which can also operate in Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during Deep Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator-switch event. Programmable Digital Smart I/O There are two Smart I/O blocks, which allow Boolean operations on signals going to the GPIO pins from the subsystems of the chip or on signals coming into the chip. Operation can be synchronous or asynchronous and the blocks operate in low-power modes, such as Deep Sleep and Hibernate.This allows, for example, detection of logic conditions that can indicate that the CPU should wake up instead of waking up on general I/O interrupts, which consume more power and can generate spurious wake-ups. Universal Digital Blocks (UDBs) and Port Interfaces The CYBLE-416045-02 has 12 UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. I2C block implements a Fixed-Function Digital Timer/Counter/PWM Block The timer/counter/PWM block consists of 32 counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. There are eight 32-bit counters and 24 16-bit counters. Serial Communication Blocks (SCB) Part Number has nine SCBs, which can each implement an I2C, UART, or SPI interface. One SCB will operate in Deep Sleep with an external clock, this SCB will only operate in Slave mode

(requires external clock). I2C Mode: The hardware full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C that creates a mailbox address range in the memory of Part Number and effectively reduces the I2C commu-

nication to reading from and writing to an array in the memory. In addition, the block supports a 256 byte-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with I2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. UART Mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256 byte-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface will operate with a 25-MHz SPI Clock. Document Number: 002-24085 Rev. **

Page 7 of 60 PRELIMINARY CYBLE-416045-02 analog multiplexed bus. Any GPIO pin can be connected to this AMUX bus through an analog switch. CapSense function can thus be provided on any pin or a group of pins in a system under software control. Cypress provides a software component for the CapSense block for ease-of-use. Shield voltage can be driven on another mux bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented. The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise. The CapSense block has two 7-bit IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). A (slow) 10-bit Slope ADC may be realized by using one of the IDACs. The block can implement Swipe, Tap, Wake-up on Touch

(< 3 A at 1.8 V), mutual capacitance, and other types of sensing functions. Audio Subsystem This subsystem consists of an I2S block and two PDM channels. The PDM channels interface to a PDM microphone's bit-stream output. The PDM processing channel provides droop correction and can operate with clock speeds ranging from 384 kHz to 3.072 MHz and produce word lengths of 16 to 24 bits at audio sample rates of up to 48 ksps. The I2S interface supports both Master and Slave modes with Word Clock rates of up to 192 ksps (8-bit to 32-bit words). GPIO CYBLE-416045-02 has up to 36 GPIOs. The GPIO block imple-

ments the following:

n Eight drive strength modes:

p Analog input mode (input and output buffers disabled) p Input only p Weak pull-up with strong pull-down p Strong pull-up with weak pull-down p Open drain with strong pull-down p Open drain with strong pull-up p Strong pull-up with strong pull-down p Weak pull-up with weak pull-down n Input threshold select (CMOS or LVTTL) n Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) n Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it. Six GPIO pins are capable of overvoltage tolerant (OVT) operation where the input voltage may be higher than VDD (these may be used for I2C functionality to allow powering the chip off while maintaining physical connection to an operating I2C bus without affecting its function-

ality). GPIO pins can be ganged to sink 16 mA or higher values of sink current. GPIO pins, including OVT pins, may not be pulled up higher than 3.6 V. Special-Function Peripherals CapSense CapSense is supported on all pins in the Part Number through a CapSense Sigma-Delta (CSD) block that can be connected to an Document Number: 002-24085 Rev. **

Page 8 of 60 PRELIMINARY CYBLE-416045-02 Module Overview Module Description The CYBLE-416045-02 module is a complete module designed to be soldered to the main host board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna location dimensions Length (X) Width (Y) Length (X) Width (Y) Height (H) PCB thickness Height (H) Shield height Maximum component height Height (H) Total module thickness (bottom of module to highest component) Height (H) 14.00 0.15 mm 18.50 0.15 mm 14.00 0.15 mm 4.62 0.15 mm 0.80 0.10 mm 1.20 0.10 mm 1.20 mm typical (shield) 2.00 mm typical See Figure 2 on page 10 for the mechanical reference drawing for CYBLE-416045-02. Document Number: 002-24085 Rev. **

Page 9 of 60 PRELIMINARY CYBLE-416045-02 Figure 2. Module Mechanical Drawing Top View Side View Bottom View (Seen from Bottom) Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 4 on page 11, Figure 5 and Figure 6 on page 12, and Figure 7 and Table 3 on page 13. Document Number: 002-24085 Rev. **

Page 10 of 60 PRELIMINARY CYBLE-416045-02 Pad Connection Interface As shown in the bottom view of Figure 2 on page 10, the CYBLE-416045-02 connects to the host board via solder pads on the back of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBLE-416045-02 module. Table 2. Solder Pad Connection Description Name Connections Connection Type SP Solder Pads 43 Pad Length Dimension Pad Width Dimension 1.02 mm 0.61 mm Pad Pitch 0.90 mm Figure 3. Solder Pad Dimensions (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. Please refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm). Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-416045-02 Trace Antenna Host PCB Keep-Out Area Around Trace Antenna Document Number: 002-24085 Rev. **

Page 11 of 60 PRELIMINARY CYBLE-416045-02 Recommended Host PCB Layout Figure 5 through Figure 7 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-416045-02. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. Host Layout Pattern for CYBLE-416045-02 Figure 6. Module Pad Location from Origin Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-24085 Rev. **

Page 12 of 60 PRELIMINARY CYBLE-416045-02 Table 3 provides the center location for each solder pad on the CYBLE-416045-02. All dimensions reference the to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location 41 42 43

(13.62, 6.73)

(13.62, 5.83)

(13.62, 4.93)

(536.22, 264.96)

(536.22, 229.53)

(536.22, 194.09) Figure 7. Solder Pad Reference Location Top View (Seen on Host PCB) Solder Pad

(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Location (X,Y) from Orign (mm)

(0.38, 4.93)

(0.38, 5.83)

(0.38, 6.73)

(0.38, 7.63)

(0.38, 8.54)

(0.38, 9.44)

(0.38, 10.34)

(0.38, 11.24)

(0.38, 12.14)

(0.38, 13.04)

(0.38, 13.95)

(0.38, 14.85)

(0.38, 15.75)

(0.38, 16.65)

(0.69, 18.12)

(1.59, 18.12)

(2.49, 18.12)

(3.39, 18.12)

(4.29, 18.12)

(5.20, 18.12)

(6.10, 18.12)

(7.00, 18.12)

(7.90, 18.12)

(8.80, 18.12)

(9.70, 18.12)

(10.61, 18.12)

(11.51, 18.12)

(12.41, 18.12)

(13.31, 18.12)

(13.62, 16.65)

(13.62, 15.75)

(13.62, 14.85)

(13.62, 13.95)

(13.62, 13.04)

(13.62, 12.14)

(13.62, 11.24)

(13.62, 10.34)

(13.62, 9.44)

(13.62, 8.54)

(13.62, 7.63) Dimension from Orign (mils)

(14.96, 194.09)

(14.96, 229.53)

(14.96, 264.96)

(14.96, 300.39)

(14.96, 336.22)

(14.96, 371.65)

(14.96, 407.09)

(14.96, 442.52)

(14.96, 477.95)

(14.96, 513.38)

(14.96, 549.21)

(14.96, 584.64)

(14.96, 620.08)

(14.96, 655.51)

(27.17, 713.38)

(62.60, 713.38)

(98.03, 713.38)

(133.46, 713.38)

(168.90, 713.38)

(204.72, 713.38)

(240.16, 713.38)

(275.59, 713.38)

(311.02, 713.38)

(346.46, 713.38)

(381.89, 713.38)

(417.72, 713.38)

(453.15, 713.38)

(488.58, 713.38)

(524.01, 713.38)

(536.22, 655.51)

(536.22, 620.08)

(536.22, 584.64)

(536.22, 549.21)

(536.22, 513.38)

(536.22, 477.95)

(536.22, 442.52)

(536.22, 407.09)

(536.22, 371.65)

(536.22, 336.22)

(536.22, 300.39) Document Number: 002-24085 Rev. **

Page 13 of 60 PRELIMINARY CYBLE-416045-02 Digital and Analog Capablities and Connections Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-416045-02, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3. Table 4. Digital Peripheral Capabilities UART SPI I2C TCPWM[2,3]

Cap Sense EXT_CLK _IN AUDIO CMP Dig-

ital Out SWD/JTAG GPIO Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Device Port Pin GND[4]

P0.5 VBACKUP VDD P0.0 P0.1 3(scb0_CTS) 3(scb0_SS0) 3(scb0_SS1) 3(scb0_SS2) P10.3 3(scb1_CTS) 3(scb1_SS0) P10.4 3(scb1_SS1) P9.3 3(scb2_CTS) 3(scb2_SS0) P10.6 P10.5 3(scb1_SS3) 3(scb1_SS2) P10.1 3(scb1_TX) 3(scb1_MISO) 3(scb1_SDA) P10.0 3(scb1_RX) 3(scb1_MOSI) 3(scb1_SCL) P9.4 GND VREF P9.0 P9.1 P9.5 P9.6 P9.2 P7.2 P7.1 P6.4 P5.4 P6.7 P6.6 P6.2 P6.5 3(scb2_SS1) 3(scb2_RX) 3(scb2_MOSI) 3(scb2_SCL) 3(scb2_TX) 3(scb2_MISO) 3(scb2_SDA) 3(scb2_SS2) 3(scb2_SS3) 3(scb2_RTS) 3(scb2_SCLK) 3(scb4_RTS) 3(scb4_SCLK) 3(scb4_TX) 3(scb4_MISO) 3(scb4_SDA) 3(SCB6_RX) 3(scb6_MOSI)

(scb8_MOSI) 3(scb5_SS1) 3(scb8_SCL)

(scb6_SCL) 3(scb6_CTS) 3(scb6_SS0)

(scb8_SS0) 3(scb6_RTS) 3(scb6_SCLK)

(scb8_SCLK) 3(scb3_RTS) 3(scb3_SCLK)

(scb8_SCLK) 3(scb6_TX) 3(scb6_MISO)

(scb8_MISO) Ground Connection tcpwm[0].line_compl[2]

tcpwm[1].line_compl[2]

3 3 Battery Backup Domain Input Voltage (1.71 V to 3.6 V) Power Supply Input Voltage (1.71 V to 3.6 V) 3 3(JTAG RST) 3PDM_CLK ctb_cmp1 3PDM_DATA tcpwm[0].line[0]

tcpwm[1].line[0]

tcpwm[0].line_compl[0]

tcpwm[1].line_compl[0]

tcpwm[0].line_compl[7]

tcpwm[1].line_compl[23]

tcpwm[0].line[0]

tcpwm[1].line[0]

tcpwm[0].line_compl[5]

tcpwm[1].line_compl[21]

tcpwm[0].line[1]

tcpwm[1].line[2]

tcpwm[0].line_compl[0]

tcpwm[1].line_compl[0]

tcpwm[0].line_compl[6]

tcpwm[1].line_compl[22]

tcpwm[0].line[6]

tcpwm[1].line[22]

tcpwm[0].line[7]

tcpwm[1].line[0]

3 3 3 3 3 3 3 3 3 3 Ground Connection Voltage Reference Input (Optional) tcpwm[0].line[4]

tcpwm[1].line[20]

tcpwm[0].line_compl[4]

tcpwm[1].line_compl[20]

tcpwm[0].line_compl[7]

tcpwm[1].line_compl[0]

tcpwm[0].line[0]

tcpwm[1].line[1]

tcpwm[0].line[5]

tcpwm[1].line[21]

tcpwm[0].line[5]

tcpwm[1].line[13]

tcpwm[0].line_compl[4]

tcpwm[1].line_compl[12]

tcpwm[0].line[2]

tcpwm[1].line[10]

tcpwm[0].line[6]

tcpwm[1].line[6]

tcpwm[0].line_compl[3]

tcpwm[1].line_compl[11 tcpwm[0].line[3]

tcpwm[1].line[11]

tcpwm[0].line[1]

tcpwm[1].line[9]

3 3 3 3 3 3 3 3 3 3 3 3 3 ctb_cmp0 3I2S_SCK_RX 3(JTAG TDO) 3(SWDCLK)

(JTAG TCLK) 3(SWDIO)

(JTAG TMS) 3(JTAG TDI) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3(scb8_SDA) 3(scb6_SDA) tcpwm[0].line_compl[2]

tcpwm[1].line_compl[10]

Document Number: 002-24085 Rev. **

Page 14 of 60 PRELIMINARY CYBLE-416045-02 Table 4. Digital Peripheral Capabilities 3(scb3_CTS) 3(scb3_SS0)

(scb8_SS0) 3(scb3_SS1) P6.3 P7.7 31 30 32 33 34 35 36 37 38 39 40 41 42 43 P5.6 3(scb5_SS3) P10.2 3(scb1_RTS) 3(scb1_SCLK) 3(scb6_SS3) 3(scb5_SS2) 3(scb5_CTS) 3(scb5_SS0) 3(scb5_RTS) 3(scb5_SCLK) 3(scb5_RX) 3(scb5_MOSI) 3(scb5_SCL) 3(scb5_TX) 3(scb5_MISO) 3(scb5_SDA) 3(scb0_RTS) 3(scb0_SCLK) P12.6 P12.7 P5.5 P5.3 P5.2 P5.0 P5.1 P0.4 XRES GND[4]

tcpwm[0].line_compl[1]

tcpwm[1].line_compl[9]

tcpwm[0].line_compl[7]

tcpwm[1].line_compl[15]

tcpwm[0].line[7]

tcpwm[1].line[7]

tcpwm[0].line[7]

tcpwm[1].line[23]

tcpwm[0].line[7]

tcpwm[1].line[7]

tcpwm[0].line_compl[7]

tcpwm[1].line_compl[7]

tcpwm[0].line_compl[6]

tcpwm[1].line_compl[6]

cpwm[0].line_compl[5]

tcpwm[1].line_compl[5]

tcpwm[0].line[5]

tcpwm[1].line[5]

tcpwm[0].line[4]

tcpwm[1].line[4]

tcpwm[0].line_compl[4]

tcpwm[1].line_compl[4]

tcpwm[0].line[2]

tcpwm[1].line[2]

3 3 3 3 3 3 3 3 3 3 3 3 External Reset (Active Low) Ground Connection 3I2S_SDI_RX 3I2S_WS_RX 3I2S_SDO_TX 3I2S_WS_TX 3I2S_EXT_CLK 3I2S_CLK_TX 3 3 3 3 3 3 3 3 3 3 3 3 Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive or negative polarity. 4. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system. Document Number: 002-24085 Rev. **

Page 15 of 60 PRELIMINARY CYBLE-416045-02 Table 5. Additional Analog and Digital Functional Capabilities Pad Number Device Port Pin Analog Functionality Digital HV Universal Digital Block (UDB) SMARTIO wco_in wco_out sarmux[3]

sarmux[4]

ctb_oa1_out sarmux[6]

sarmux[5]

sarmux[1]

sarmux[0]

ctb_oa1-

ctb_oa0+

ctb_oa0-

ctb_oa1+

ctb_oa0+

ctb_oa0_out csd.csh_tankpadd csd.csh_tankpads csd.cmodpadd csd.cmodpads lpcomp.inp_comp1 lpcomp.inn_comp1 csd.cshieldpads lpcomp.inp_comp0 sarmux[2]

ECO_IN ECO_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GND P0.5 VBACKUP VDD P0.0 P0.1 P10.3 P10.4 P9.3 P10.6 P10.5 P10.1 P10.0 P9.4 GND VREF P9.0 P9.1 P9.5 P9.6 P9.2 P7.2 P7.1 P6.4 P5.4 P6.7 P6.6 P6.2 P6.5 P6.3 P7.7 P5.6 P10.2 P12.6 P12.7 P5.5 P5.3 P5.2 P5.0 P5.1 P0.4 XRES GND Ground Connection 3(pmic_wakeup_out) 3(UDB0[5]) Battery Backup Domain Input Voltage (1.71 V to 3.6 V) Power Supply Input Voltage (1.71 V to 3.6 V) SMARTIO10[3]

SMARTIO9[4]

SMARTIO9[0]

SMARTIO9[1]

SMARTIO9[5]

SMARTIO9[6]

SMARTIO9[2]

3(UDB0[0]) 3(UDB0[1]) 3(UDB9[3]) 3(UDB9[4]) 3(UDB10[3]) 3(UDB9[6]) 3(UDB9[5]) 3(UDB9[1]) 3(UDB9[0]) 3(UDB10[4]) 3(UDB10[0]) 3(UDB10[1]) 3(UDB10[5]) 3(UDB10[6]) 3(UDB10[2]) 3(UDB5[2]) 3(UDB5[1]) 3(UDB4[4]) 3(UDB3[5]) 3(UDB4[7]) 3(UDB4[6]) 3(UDB4[2]) 3(UDB4[5]) 3(UDB4[3]) 3(UDB5[7]) 3(UDB3[6]) 3(UDB9[2]) 3(UDB7[6]) 3(UDB7[7]) 3(UDB3[5]) 3(UDB3[3]) 3(UDB3[2]) 3(UDB3[0]) 3(UDB3[1]) 3(UDB0[4]) Ground Connection Reference Voltage Input (Optional) swd_clk swd_data pmic_wakeup_in hibernate_wakeup[1]

External Reset (Active Low) Ground Connection Document Number: 002-24085 Rev. **

Page 16 of 60 PRELIMINARY CYBLE-416045-02 Power The power connection diagram (see Figure 8) shows the general requirements for power pins on the CYBLE-416045-02. The CYBLE-416045-02 contains a single power supply connection (VDD) and a backup voltage input (VBACKUP). Description of the power pins is as follows:

1. VBACKUP is the supply to the backup domain. The backup domain includes the 32 kHz WCO, RTC, and backup registers. It can generate a wake-up interrupt to the chip via the RTC timers or an external input. It can also generate an output to wakeup external circuitry. It is connected to VDD when not used as a separate battery backup domain. VBACKUP provides the supply for Port 0. 2. VDD is the main power supply input (1.7 to 3.6V). It provides the power input to the digital, analog and radio domains. Isolation required for these domains is integrated on-module, therefore no additional isloation is required for the CYBLE-416045-02. The supply voltage range is 1.71 to 3.6 V with all functions and circuits operating over that range. All ground connections specified must be connected to system ground. VDD and VBACKUP may be shorted together externally. They are not required to be seperate inputs voltages. Figure 8. CYBLE-416045-02 Power Connections Document Number: 002-24085 Rev. **

Page 17 of 60 PRELIMINARY CYBLE-416045-02 The CYBLE-416045-02 schematic is shown in Figure 9. Figure 9. CYBLE-416045-02 Schematic Diagram Document Number: 002-24085 Rev. **

Page 18 of 60 PRELIMINARY CYBLE-416045-02 Critical Components List Table 6 details the critical components used in the CYBLE-416045-02 module. Table 6. Critical Component List Component Reference Designator Description Silicon Crystal U1 Y1 116-pin BGA Programmable System-on-Chip (PSoC6) with BLE 32.000 MHz, 10PF Antenna Design Table 7 details the PCB trace antenna used on the CYBLE-416045-02 module. The Cypress module performance improves many of these characteristics. For more information, see Table 10 on page 26. Table 7. Trace Antenna Specifications Item Description Frequency Range Peak Gain Return Loss 2400 2500 MHz

-0.5 dBi typical 10 dB minimum Document Number: 002-24085 Rev. **

Page 19 of 60 PRELIMINARY CYBLE-416045-02 Electrical Specification Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 8. CYBLE-416045-02 Absolute Maximum Ratings[5]

Parameter VDDD_ABS VCCD_ABS VDDD_RIPPLE Description VDD, VDDA and VDDR supply relative to VSS

(VSSD = VSSA) Direct digital core voltage input relative to VSSD Maximum power supply ripple for VDD, VDDA and VDDR input voltage GPIO voltage Maximum current per GPIO VGPIO_ABS IGPIO_ABS IGPIO_injection GPIO injection current per pin LU Pin current for latch up Min 0.5 0.5 0.5 25 0.5 100 Typ Max Unit Details/Conditions 4 1.2 100 VDD +0.5 25 0.5 100 V Absolute maximum V mV Absolute maximum 3.0V supply Ripple frequency of 100 kHz to 750 kHz V Absolute maximum mA Absolute maximum mA Absolute maximum current mA Absolute maximum injected per pin Device-Level Specifications All specifications are valid for 40 C TA 85 C and for 1.71 V to 3.6 V except where noted. Table 9. Power Supply Range, CPU Current, and Transition Time Specifications Parameter Description Min Typ Max Units Details / Conditions DC Specifications VDDD VDDA VDDIO1 VDDIO0 VDDIO0 VDDIOR VDDIOA VDDUSB VBACKUP VCCD1 VCCD2 CEFC CEXC Internal regulator and Port 1 GPIO supply Analog power supply voltage. Shorted to VDDIOA on PCB. GPIO Supply for Ports 5 to 8 when present GPIO Supply for Ports 11 to 13 when present Supply for E-Fuse Programming GPIO supply for Ports 2 to 4 on BGA 124 only GPIO Supply for Ports 9 to 10. Shorted to VDDA on PCB. Supply for Port 14 (USB or GPIO) when present Backup Power and GPIO Port 0 supply when present Output voltage (for core logic bypass) Output voltage (for core logic bypass) External regulator voltage (VCCD) bypass Power supply decoupling capacitor 1.7 1.7 1.7 1.7 2.38 1.7 1.7 1.7 1.7 3.8 2.5 1.1 0.9 4.7 10 3.6 3.6 3.6 3.6 2.62 3.6 3.6 3.6 3.6 5.6 Internally unregulated Supply VDDIO_1 must be to VDDA. E-Fuse Programming Voltage V V V V V V V V Min supply is 2.85 V for USB V Min. is 1.4 V in Backup mode V High-speed mode ULP mode. Valid for 20 to 85 C F X5R ceramic or better F X5R ceramic or better Note 5. Usage above the absolute maximum conditions listed in Table 8 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 002-24085 Rev. **

Page 20 of 60 PRELIMINARY CYBLE-416045-02 Table 9. Power Supply Range, CPU Current, and Transition Time Specifications Parameter Description Min Typ Max Units Details / Conditions LP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO) Cortex M4. Active Mode Execute with Cache Disabled (Flash) IDD1 IDD2 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz.With IMO. While(1) Execute with Cache Enabled IDD3 IDD4 IDD5 IDD6 Execute from Cache;CM4 Active150 MHz, CM0+ Sleep 75 MHz. IMO & FLL. Dhrystone. Execute from Cache;CM4 Active100 MHz, CM0+ Sleep 100MHz. IMO & FLL. Dhrystone. Execute from Cache;CM4 Active 50 MHz, CM0+ Sleep 25MHz. IMO & FLL. Dhrystone Execute from Cache;CM4 Active 8 MHz, CM0+ Sleep 8 MHz. IMO. Dhrystone Cortex M0+. Active Mode Execute with Cache Disabled (Flash) IDD7 IDD8 Execute from Flash;CM4 Off, CM0+ Active 50 MHz. With IMO & FLL. While (1). Execute from Flash;CM4 Off, CM0+ Active 8 MHz. With IMO. While (1) Execute with Cache Enabled IDD9 IDD10 Execute from Cache;CM4 Off, CM0+

Active 100 MHz. With IMO & FLL. Dhrystone. Execute from Cache;CM4 Off, CM0+

Active 8 MHz. With IMO. Dhrystone Cortex M4. Sleep Mode IDD11 IDD12 CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL 2.3 3.1 4.2 0.9 1.2 1.6 6.3 9.7 13.2 4.8 7.4 10.1 2.4 3.7 5.1 0.90 1.27 1.8 2.4 3.2 4.1 0.8 1.1 1.45 3.8 5.9 7.7 0.80 1.2 1.41 1.5 2.2 2.9 1.20 1.70 2.20 3.2 3.6 5.1 1.5 1.6 2.4 7 11.2 13.7 5.8 8.4 10.7 3.4 4.1 5.8 1.5 1.75 2.6 3.3 3.7 4.8 1.5 1.6 1.9 4.5 6.5 8.2 1.3 1.7 2 2.2 2.7 3.5 1.9 2.2 2.8 mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD=3.3 V, Buck ON, Max at 60 C VDDD = 1.8V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C Document Number: 002-24085 Rev. **

Page 21 of 60 PRELIMINARY CYBLE-416045-02 Table 9. Power Supply Range, CPU Current, and Transition Time Specifications Parameter Description Min Typ Max Units Details / Conditions IDD13 CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. 0.7 0.96 1.22 1.3 1.5 2 mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C Document Number: 002-24085 Rev. **

Page 22 of 60 Table 9. Power Supply Range, CPU Current, and Transition Time Specifications Table 9. Power Supply Range, CPU Current, and Transition Time Spec PRELIMINARY CYBLE-416045-02 Parameter Description Min Typ Parameter Max Units Description Details / Conditions Min Typ M Cortex M0+. Sleep Mode Cortex M0+. Low Power Sleep (LPS) Mode IDD14 IDD15 CM4 Off, CM0+ Sleep 50 MHz. With IMO

& FLL. CM4 Off, CM0+ Sleep 8 MHz. With IMO. Cortex M4. Low Power Active (LPA) Mode IDD16 IDD17 Execute from Flash; CM4 LPA 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1). Execute from Cache; CM4 LPA 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. Cortex M0+. Low Power Active (LPA) Mode IDD18 IDD19 Execute from Flash; CM4 Off, CM0+ LPA 8 MHz. With IMO. While (1) Execute from Cache; CM4 Off, CM0+ LPA 8 MHz. With IMO. Dhrystone. Cortex M4. Low Power Sleep (LPS) Mode IDD20 CM4 LPS 8 MHz, CM0+ LPS 8 MHz. With IMO. 1.3 1.94 2.57 0.7 0.95 1.25 0.85 1.18 1.63 0.90 1.27 1.77 0.8 1.14 1.6 0.8 1.15 1.62 0.65 0.95 1.31 2 2.4 3.2 1.3 1.5 2 1.5 1.65 2.4 1.5 1.75 2.5 1.4 1.6 2.4 1.4 1.65 2.4 1.1 1.5 2.1 mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C mA VDDD=3.3 V, Buck ON, Max at 60 C VDDD=1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C Document Number: 002-24085 Rev. **

Page 23 of 60 Table 9. Power Supply Range, CPU Current, and Transition Time Specifications Table 9. Power Supply Range, CPU Current, and Transition Time Spec PRELIMINARY CYBLE-416045-02 Parameter Description IDD22 CM4 Off, CM0+ LPS 8 MHz. With IMO. Min Typ Parameter Max Units Description Details / Conditions Min Typ M Cortex M4. Sleep Mode 0.64 0.93 1.29 1.1 1.45 2 mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C VDDD = 1.8 to 3.3 V, LDO, max at 60 C ULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from -20 to +85 C. Cortex M4. Active Mode Execute with Cache Disabled (Flash) IDD3 IDD10 IDD16 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1) IDD4 Execute with Cache Enabled Execute from Cache; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. Dhrystone. Execute from Cache; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. IDD11 Cortex M0+. Active Mode Execute with Cache Disabled (Flash) Execute from Flash; CM4 Off, CM0+

Active 25 MHz. With IMO & FLL. Write(1). Execute from Flash; CM4 Off, CM0+

Active 8 MHz. With IMO. While(1) IDD17 Execute with Cache Enabled IDD18 IDD19 Execute from Cache; CM4 Off, CM0+

Active 25 MHz. With IMO & FLL. Dhrystone. Execute from Cache; CM4 Off, CM0+

Active 8 MHz. With IMO. Dhrystone. 1.7 2.1 0.56 0.75 1.6 2.4 0.65 0.8 1.00 1.34 0.54 0.73 0.91 1.34 0.51 0.73 2.2 2.4 0.8 1 2.2 2.7 0.8 1.1 1.4 1.6 0.75 1 1.25 1.6 0.72 0.95 mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C Document Number: 002-24085 Rev. **

Page 24 of 60 Table 9. Power Supply Range, CPU Current, and Transition Time Specifications PRELIMINARY CYBLE-416045-02 Parameter Description Min Typ IDD21 CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO IDD22 Cortex M0+. Sleep Mode IDD23 CM4 Off, CM0+ Sleep 25 MHz. With IMO

& FLL. IDD25 CM4 Off, CM0+ Sleep 8 MHz. With IMO. IDD24 Cortex M4. Ultra Low Power Active (ULPA) Mode Execute from Flash. CM4 ULPA 8 MHz, CM0+ ULPS 8 MHz. With IMO. While(1). Execute from Cache. CM4 ULPA 8 MHz, IDD26 CM0+ ULPS 8 MHz. With IMO. Dhrystone. Cortex M0+. Ultra Low Power Active (ULPA) Mode Execute from Flash. CM4 Off, CM0+ ULPA 8 MHz. With IMO. While (1). Execute from Cache. CM4 Off, CM0+

ULPA 8 MHz. With IMO. Dhrystone. IDD28 Cortex M4. Ultra Low Power Sleep (ULPS) Mode CM4 ULPS 8 MHz, CM0 ULPS 8 MHz. With IMO. IDD29 Cortex M0+. Ultra Low Power Sleep (ULPS) Mode IDD27 CM4 Off, CM0+ ULPS 8 MHz. With IMO. IDD31 Deep Sleep Mode IDD33A IDD33A_B IDD33B With internal Buck enabled and 64K SRAM retention With internal Buck enabled and 64K SRAM retention With internal Buck enabled and 256K SRAM retention With internal Buck enabled and 256K SRAM retention VDDD = 1.8 V VDDD = 3.3 V IDD33B_B Hibernate Mode IDD34 IDD34A Power Mode Transition Times TLPACT_ACT Low Power Active to Active transition time TDS_LPACT Deep Sleep to LP Active transition time TDS_ACT THIB_ACT Deep Sleep to Active transition time Hibernate to Active transition time 0.76 1.1 0.42 0.59 0.62 0.88 0.41 0.58 0.52 0.76 0.54 0.78 0.51 0.75 0.48 0.7 0.4 0.57 0.39 0.56 7 7 9 9 300 800 500 Max 1.1 1.4 0.65 0.8 0.9 1.1 0.6 0.8 0.75 1 0.76 1 0.75 1 0.7 0.95 0.6 0.8 0.6 0.8 35 25 25 Units Details / Conditions mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C mA VDDD = 3.3 V, Buck ON, Max at 60 C VDDD = 1.8 V, Buck ON, Max at 60 C A Max value is at 85 C A Max value is at 60 C A Max value is at 85 C A Max value is at 60 C nA No clocks running nA No clocks running s Including PLL lock time s Guaranteed by design s Guaranteed by design s Including PLL lock time Table 10 details the RF characteristics for the Cypress BLE module. Document Number: 002-24085 Rev. **

Page 25 of 60 PRELIMINARY CYBLE-416045-02 Table 10. CYBLE-416045-02 RF Performance Characteristics Parameter Description RFO RXS FR GP GAvg RL RF output power on ANT RF receive sensitivity on ANT Module frequency range Peak gain Average gain Return loss Min 20 2400 Typ 0 87 0.5 0.5 10 Max 4 2480 settings simulation Details/Conditions Unit dBm Configurable via register dBm Guaranteed by design MHz dBi dBi dB XRES Table 11. XRES Parameter Description Min Typ Max Units Details / Conditions POR or XRES release to Active transition time XRES Pulse width XRES (Active Low) Specifications XRES AC Specifications TXRES_ACT TXRES_PW XRES DC Specifications TXRES_IDD TXRES_IDD_1 VIH IDD when XRES asserted IDD when XRES asserted Input Voltage high threshold VIL CIN VHYSXRES IDIODE Input Voltage low threshold Input Capacitance Input voltage hysteresis Current through protection diode to VDD/VSS 5 0.7*

VDD 750 300 800 3 100 0.3*

VDD 100 s s nA nA V Normal mode, 50 MHz M0+. VDDD = 1.8 V VDDD = 3.3 V CMOS Input V CMOS Input pF mV A Notes 6. Cypress-supplied software wakeup routines take approximately 100 CPU clock cycles after hardware wakeup (the 25 s) before transition to Application code. With an 8-MHz CPU clock (LP Active), the time before user code executes is 25 + 12.5 = 37.5 s. 7. Cypress-supplied software wakeup routines take approximately 100 CPU clock cycles after hardware wakeup (the 25 s) before transition to Application code. With a 25-MHz CPU clock (FLL), the time before user code executes is 25 + 4 = 29 s. With a 100-MHz CPU clock, the time is 25 + 1 = 26 s. Document Number: 002-24085 Rev. **

Page 26 of 60 PRELIMINARY CYBLE-416045-02 GPIO Table 12. GPIO Specifications Parameter Description Min Typ Max Units Details / Conditions GPIO DC Specifications VIH IIHS VIL VIH VIL VIH VIL VOH VOL RPULLUP RPULLDOWN IIL IIL_CTBM CIN VHYSTTL VHYSCMOS IDIODE ITOT_GPIO GPIO AC Specifications TRISEF Input voltage high threshold Input current when Pad > VDDIO for OVT inputs Input voltage low threshold LVTTL input, VDD < 2.7 V LVTTL input, VDD < 2.7 V LVTTL input, VDD 2.7 V LVTTL input, VDD 2.7 V Output voltage high level Output voltage low level Pull-up resistor Pull-down resistor Input leakage current (absolute value) Input leakage on CTBm input pins Input Capacitance Input hysteresis LVTTL VDD > 2.7 V Input hysteresis CMOS Current through protection diode to VDD/VSS Maximum Total Source or Sink Chip Current Rise time in Fast Strong Mode. 10% to 90% of VDD Fall time in Fast Strong Mode. 10% to 90% of VDD Rise time in Slow Strong Mode. 10% to 90% of VDD Rise time in Slow Strong Mode. 10% to 90% of VDD Fall time in Slow Strong Mode. 10% to 90% of VDD Fall time in Slow Strong Mode. 10% to 90% of VDD 0.7*VDD 0.7*VDD 2.0 VDD-0.5 3.5 3.5 100 0.05*VDD 52 48 44 42 Fall time (30% to 70% of VDD) in Slow Strong mode GPIO Fout. Fast Strong mode. 20*VDDIO/

5.5 GPIO Fout; Slow Strong mode. GPIO Fout; Fast Strong mode. GPIO Fout; Slow Strong mode. TFALLF TRISES_1 TRISES_2 TFALLS_1 TFALLS_2 TFALL_I2C FGPIOUT1 FGPIOUT2 FGPIOUT3 FGPIOUT4 Document Number: 002-24085 Rev. **

5.6 5.6 0 10 0.3*VDD 0.3*VDD 0.8 0.4 8.5 8.5 2 4 5

-

-

100 200 2.5 2.5 142 102 211 93 250 100 16.7 7 3.5 V A V V V V V V V k k nA nA pF mV mV A mA ns ns ns ns ns ns ns MHz MHz MHz MHz CMOS Input Per I2C Spec CMOS Input IOH = 8 mA IOL = 8 mA 25 C, VDD = 3.0 V Cload = 15 pF, 8 mA drive strength Cload = 15 pF, 8 mA drive strength Cload = 15 pF, 8 mA drive strength, VDD 2.7 V Cload = 15 pF, 8 mA drive strength, 2.7 V < VDD 3.6 V Cload = 15 pF, 8 mA drive strength, VDD 2.7 V Cload = 15 pF, 8 mA drive strength, 2.7 V < VDD 3.6 V Cload = 10 pF to 400 pF, 8-mA drive strength 90/10%, 15-pF load, 60/40 duty cycle 90/10%, 15-pF load, 60/40 duty cycle 90/10%, 25-pF load, 60/40 duty cycle 90/10%, 25-pF load, 60/40 duty cycle Page 27 of 60 PRELIMINARY CYBLE-416045-02 Table 12. GPIO Specifications (continued) Parameter Description FGPIOIN GPIO input operating frequency;1.71 V VDD 3.6 V Analog Peripherals Opamp Table 13. Opamp Specifications Min Typ Max 100 Units Details / Conditions MHz 90/10% VIO Units Details/Conditions Parameter Description IDD IDD_HI IDD_MED IDD_LOW GBW GBW_HI GBW_MED GBW_LO IOUT_MAX IOUT_MAX_HI IOUT_MAX_MID IOUT_MAX_LO IOUT IOUT_MAX_HI IOUT_MAX_MID IOUT_MAX_LO VIN VCM VOUT VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOS_UNTR VOS_TR VOS_TR VOS_TR VOS_DR_UNTR VOS_DR_TR VOS_DR_TR VOS_DR_TR CMRR PSRR Opamp Block current. No load. Power = Hi Power = Med Power = Lo Load = 20 pF, 0.1 mA. VDDA = 2.7 V Power = Hi Power = Med Power = Lo VDDA 2.7 V, 500 mV from rail Power = Hi Power = Mid Power = Lo VDDA = 1.71 V, 500 mV from rail Power = Hi Power = Mid Power = Lo Input voltage range Input common mode voltage VDDA 2.7V Power = hi, Iload = 10 mA Power = hi, Iload = 1 mA Power = med, Iload = 1 mA Power = lo, Iload = 0.1 mA Offset voltage, untrimmed Offset voltage, trimmed Offset voltage, trimmed Offset voltage, trimmed Offset voltage drift, untrimmed Offset voltage drift, trimmed Offset voltage drift, trimmed Offset voltage drift, trimmed DC Common mode rejection ratio Power supply rejection ratio at 1 kHz, 10-mV ripple Min 6 4 10 4 4 0 0 0.5 0.2 0.2 0.2 10 67 70 Typ 1300 450 250 Max 1500 600 350 1 5 2 VDDA-0.2 VDDA-0.2 VDDA-0.5 VDDA-0.2 VDDA-0.2 VDDA-0.2 0.5 1 2 3 10 10 80 85 10 A A A MHz MHz MHz mA mA mA mA mA mA V V V V V V mV mV High mode, 0.2 to VDDA - 0.2 Medium mode Low mode mV mV V/C V/C High mode, 0.2 to VDDA-0.2 V/C Medium mode V/C Low mode dB VDDD = 3.3 V VDDD = 3.3 V dB Document Number: 002-24085 Rev. **

Page 28 of 60 PRELIMINARY CYBLE-416045-02 Table 13. Opamp Specifications (continued) Description Parameter Noise VN1 VN2 VN3 VN4 CLOAD Input-referred, 1 Hz - 1 GHz, power = Hi Input-referred, 1 kHz, power = Hi Input-referred, 10 kHz, power = Hi Input-referred, 100kHz, power = Hi Stable up to max. load. Performance specs at 50 pF. SLEW_RATE Output slew rate T_OP_WAKE From disable to enable, no external RC dominating Comparator mode; 50-mV overdrive, Trise = Tfall (approx.) Response time; power = hi Response time; power = med Response time; power = lo Hysteresis COMP_MODE TPD1 TPD2 TPD3 VHYST_OP Deep Sleep Mode Mode 2 is lowest current range. Mode 1 has higher GBW. Mode 1, High current Mode 1, Medium current Mode 1, Low current Mode 2, High current Mode 2, Medium current Mode 2, Low current Mode 1, High current IDD_HI_M1 IDD_MED_M1 IDD_LOW_M1 IDD_HI_M2 IDD_MED_M2 IDD_LOW_M2 GBW_HI_M1 GBW_MED_M1 Mode 1, Medium current GBW_LOW_M1 Mode 1, Low current GBW_HI_M2 Mode 2, High current GBW_MED_M2 Mode 2, Medium current GBW_LOW_M2 Mode 2, Low current VOS_HI_M1 VOS_MED_M1 VOS_LOW_M1 VOS_HI_M2 Mode 1, High current Mode 1, Medium current Mode 1, Low current Mode 2, High current Min 6 Typ 100 180 70 38 25 150 400 2000 10 1300 460 230 120 60 15 4 2 0.5 0.5 0.2 0.1 5 5 5 5 Max 125 1500 600 350 Units Vrms nV/rtHz nV/rtHz nV/rtHz pF V/s s ns ns ns mV A A A A A A MHz MHz MHz MHz MHz Details/Conditions Cload = 50 pF, Power = High, VDDA 2.7 V Deep Sleep mode operation:

VDDA 2.7 V. VIN is 0.2 to VDDA -1.5 Typ at 25 C Typ at 25 C Typ at 25 C 25 C 25 C 25 C 25 C 25 C 25 C 20-pF load, no DC load 0.2 V to VDDA-1.5 V 20-pF load, no DC load 0.2 V to VDDA-1.5 V 20-pF load, no DC load 0.2 V to VDDA-1.5 V VDDA-1.5 V MHz mV With trim 25 C, 0.2 V to mV With trim 25 C, 0.2 V to mV With trim 25 C, 0.2 V to mV With trim 25 C, 0.2 V to VDDA-1.5 V VDDA-1.5 V VDDA-1.5 V Document Number: 002-24085 Rev. **

Page 29 of 60 PRELIMINARY CYBLE-416045-02 Table 13. Opamp Specifications (continued) Description Parameter Min Typ Max VOS_MED_M2 VOS_LOW_M2 IOUT_HI_M1 IOUT_MED_M1 IOUT_LOW_M1 IOUT_HI_M2 IOUT_MED_M2 IOUT_LOW_M2 Mode 2, Medium current Mode 2, Low current Mode 1, High current Mode 1, Medium current Mode 1, Low current Mode 2, High current Mode 2, Medium current Mode 2, Low current 5 5 10 10 4 1 1 0.5 VDDA-1.5 V Units Details/Conditions mV With trim 25 C, 0.2 V to mV With trim 25 C, 0.2 V to mA mA mA mA mA mA VDDA-1.5 V Output is 0.5 V to VDDA-0.5 V Output is 0.5 V to VDDA-0.5 V Output is 0.5 V to VDDA-0.5 V Output is 0.5 V to VDDA-0.5 V Output is 0.5 V to VDDA-0.5 V Output is 0.5 V to VDDA-0.5 V Table 14. Low-Power (LP) Comparator Specifications Parameter Description Min Typ Max Units Details/Conditions LP Comparator DC Specifications VOFFSET1 VOFFSET2 VOFFSET3 VHYST1 VHYST2 VICM1 VICM2 Input offset voltage for COMP1. Normal power mode. Input offset voltage. Low-power mode. Input offset voltage. Ultra low-power mode. Hysteresis when enabled in Normal mode Hysteresis when enabled in Low-power mode Input common mode voltage in Normal mode Input common mode voltage in Low power mode Input common mode voltage in Ultra low power mode Common mode rejection ratio in Normal power mode Block Current, Normal mode Block Current, Low power mode Block Current in Ultra low-power mode DC Input impedance of comparator ICMP1 ICMP2 ICMP3 ZCMP LP Comparator AC Specifications TRESP1 VICM3 CMRR Response time, Normal mode, 100 mV overdrive Response time, Low power mode, 100 mV overdrive Response time, Ultra-low power mode, 100 mV overdrive TRESP2 TRESP3 T_CMP_EN1 Time from Enabling to operation T_CMP_EN2 Time from Enabling to operation 10 25 25 0 0 0 50 35 12 12 0.3 10 25 25 60 80 VDDIO1-0.1 VDDIO1-0.1 VDDIO1-0.1 150 10 0.85 100 1000 20 10 50 mV COMP0 offset is 25 mV mV mV mV mV V V V dB A A A M ns ns s s Normal and Low-power s Ultra low-power mode modes Document Number: 002-24085 Rev. **

Page 30 of 60 PRELIMINARY CYBLE-416045-02 Min Typ 1 Max 5 Units C Details/Conditions 40 to +85 C Min 1.188 Typ 1.2 Max 1.212 Units V Details/Conditions Min Typ Vss Vss Max 12 16 8

-

0.2 2 1 1.25 VDDA VDDA 2.2 10 Units bits Details/Conditions 8 full speed. Diff inputs use neighboring I/O Yes

% With external reference. mV Measured with 1-V reference mA At 1 Msps. External Bypass Cap. mA V V K pF At 1 Msps. External Bypass Cap. Table 15. Temperature Sensor Specifications Parameter TSENSACC Description Temperature sensor accuracy Table 16. Internal Reference Specification Parameter Description VREFBG SAR ADC Table 17. 12-bit SAR ADC DC Specifications Parameter Description A_RES A_CHNLS_S A-CHNKS_D A-MONO A_GAINERR A_OFFSET A_ISAR_1 A_ISAR_2 A_VINS A_VIND A_INRES A_INCAP SAR ADC Resolution Number of channels - single ended Number of channels - differential Monotonicity Gain error Input offset voltage Current consumption at 1 Msps Current consumption at 1 Msps. Reference = VDD Input voltage range - single-ended Input voltage range - differential Input resistance Input capacitance Table 18. 12-bit SAR ADC AC Specifications Parameter Description Min Typ Max Units Details / Conditions 12-bit SAR ADC AC Specifications A_PSRR A_CMRR One Megasample per second mode:

A_SAMP_1 Power supply rejection ratio Common mode rejection ratio A_SAMP_2 A_SAMP_3 A_SINAD A_INL Sample rate with external reference bypass cap. Sample rate with no bypass cap;

Reference = VDD Sample rate with no bypass cap. Internal reference. Signal-to-noise and Distortion ratio

(SINAD). VDDA = 2.7 to 3.6 V, 1 Msps. Integral Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps 70 66 64 2 1 250 100 2 dB dB Measured at 1 V Msps Ksps Ksps dB Fin = 10 kHz LSB Measured with internal VREF =1.2 V and bypass cap. Document Number: 002-24085 Rev. **

Page 31 of 60 PRELIMINARY CYBLE-416045-02 Table 18. 12-bit SAR ADC AC Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions A_INL A_DNL A_DNL A_THD Integral Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps Differential Non Linearity. VDDA =

2.7 to 3.6 V, 1 Msps Differential Non Linearity. VDDA =

2.7 to 3.6 V, 1 Msps Total harmonic distortion. VDDA =

2.7 to 3.6 V, 1 Msps. 4 1 1 Table 19. 12-bit DAC Specifications 4 1.4 1.7 LSB Measured with external VREF 1 V and VIN common mode < 2*Vref LSB Measured with internal VREF = 1.2 V and bypass cap. LSB Measured with external VREF 1 V and VIN 65 dB common mode < 2*Vref Fin = 10 kHz Parameter Description Min Typ Max Units Details / Conditions DAC resolution Integral Non-Linearity Differential Non Linearity Output Voltage zero offset error 12-bit DAC DC Specifications DAC_RES DAC_INL DAC_DNL DAC_OFFSET DAC_OUT_RES DAC Output Resistance DAC_IDD DAC_QIDD 12-bit DAC AC Specifications DAC_CONV DAC_Wakeup DAC Current DAC Current when DAC stopped DAC Settling time Time from Enabling to ready for conversion 4 2 10 15 12 4 2 10 125 1 2 10 bits LSB LSB Monotonic to 11 bits. mV k A A For 000 (hex) Driving through CTBm buffer; 25 pF load s s Document Number: 002-24085 Rev. **

Page 32 of 60 PRELIMINARY CYBLE-416045-02 CSD Table 20. CapSense Sigma-Delta (CSD) Specifications Parameter Description Min Typ Max Units Details / Conditions CSD V2 Specifications VDD_RIPPLE Max allowed ripple on power supply, DC to 10 MHz VDD_RIPPLE_1.8 Max allowed ripple on power supply, DC to 10 MHz ICSD VREF VREF_EXT IDAC1IDD IDAC2IDD VCSD VCOMPIDAC IDAC1DNL IDAC1INL Maximum block current Voltage reference for CSD and Comparator External Voltage reference for CSD and Comparator IDAC1 (7-bits) block current IDAC2 (7-bits) block current Voltage range of operation Voltage compliance range of IDAC DNL INL 0.6 0.6 1.7 0.6 1 3 1.2 50 25 4500 VDDA -

0.6 VDDA -

0.6 1900 1900 3.6 VDDA 0.6 1 3 mV mV A V V A A V V LSB LSB VDDA > 2 V (with ripple), 25 C TA, Sensitivity = 0.1 pF VDDA > 1.75 V (with ripple), 25 C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity 0.4 pF VDDA VREF 0.6 V VDDA VREF 0.6 V 1.71 to 3.6 V VDDA VREF 0.6 V If VDDA < 2 V then for LSB of 2.4 A or less IDAC2DNL IDAC2INL DNL INL If VDDA < 2 V then for LSB of 2.4 A or less SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization SNRC_1 9.5-pF max. capacitance Ratio 5 1 3 1 3 LSB LSB SNRC_2 SNRC_3 SNRC_4 SNRC_5 SNRC_6 SNRC_7 SNRC_8 SNRC_9 IDAC1CRT1 IDAC1CRT2 SRSS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity SRSS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity SRSS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity PASS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity PASS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity PASS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity PASS Reference. IMO + PLL Clock Source. 0.1-pF sensitivity PASS Reference. IMO + PLL Clock Source. 0.3-pF sensitivity PASS Reference. IMO + PLL Clock Source. 0.6-pF sensitivity Output current of IDAC1 (7 bits) in low range Output current of IDAC1(7 bits) in medium range 5 5 5 5 5 5 5 5 Ratio 31-pF max. capacitance Ratio 61-pF max. capacitance Ratio 12-pF max. capacitance Ratio 47-pF max. capacitance Ratio 86-pF max. capacitance Ratio 27-pF max. capacitance Ratio 86-pF max. capacitance Ratio 168-pF Max. capacitance 4.2 33.7 5.7 45.6 A A LSB = 37.5-nA typ LSB = 300 nA typ. Document Number: 002-24085 Rev. **

Page 33 of 60 Table 20. CapSense Sigma-Delta (CSD) Specifications (continued) PRELIMINARY CYBLE-416045-02 Parameter Description IDAC1CRT3 IDAC1CRT12 IDAC1CRT22 IDAC1CRT32 IDAC2CRT1 IDAC2CRT2 IDAC2CRT3 IDAC2CRT12 IDAC2CRT22 IDAC2CRT32 IDAC3CRT13 IDAC3CRT23 IDAC3CRT33 Output current of IDAC1(7 bits) in high range Output current of IDAC1 (7 bits) in low range, 2X mode Output current of IDAC1(7 bits) in medium range, 2X mode Output current of IDAC1(7 bits) in high range, 2X mode. VDDA > 2 V Output current of IDAC2 (7 bits) in low range Output current of IDAC2 (7 bits) in medium range Output current of IDAC2 (7 bits) in high range Output current of IDAC2 (7 bits) in low range, 2X mode Output current of IDAC2(7 bits) in medium range, 2X mode Output current of IDAC2(7 bits) in high range, 2X mode. VDDA > 2V Output current of IDAC in 8-bit mode in low range Output current of IDAC in 8-bit mode in medium range Output current of IDAC in 8-bit mode in high range. VDDA > 2V All zeroes input Full-scale error less offset IDACOFFSET IDACGAIN IDACMISMATCH1 Mismatch between IDAC1 and IDAC2 in Low mode IDACMISMATCH2 Mismatch between IDAC1 and IDAC2 in Medium mode IDACMISMATCH3 Mismatch between IDAC1 and IDAC2 IDACSET8 IDACSET7 CMOD in High mode Settling time to 0.5 LSB for 8-bit IDAC Settling time to 0.5 LSB for 7-bit IDAC External modulator capacitor. Min 270 8 67 540 4.2 33.7 270 8 67 540 8 67 540 Typ 2.2 Max 365 11.4 91 730 5.7 45.6 365 11.4 91 730 11.4 91 730 1 15 9.2 6 5.8 10 10 Units Details / Conditions A A A A A A A A A A A A A LSB = 2.4 uA typ. LSB = 37.5nA typ. 2X output stage LSB = 300 nA typ. 2X output stage LSB = 2.4 uA typ. 2X output stage LSB = 37.5nA typ. LSB = 300 nA typ. LSB = 2.4 uA typ. LSB = 37.5 nA typ. 2X output stage LSB = 300 nA typ. 2X output stage LSB = 2.4 uA typ. 2X output stage LSB = 37.5nA typ. LSB = 300 nA typ. LSB = 2.4 A typ. LSB

%

LSB Polarity set by Source or Sink LSB = 2.4 A typ. LSB = 37.5-nA typ. LSB LSB = 300-nA typ. LSB LSB = 2.4 A typ. s s nF Full-scale transition. No external load. Full-scale transition. No external load. 5-V rating, X7R or NP0 cap. Table 21. CSD ADC Specifications Parameter Description Min Typ Max Units Details / Conditions CSDv2 ADC Specifications A_RES A_CHNLS_S A-MONO Resolution Number of channels - single ended Monotonicity 10 Yes bits Auto-zeroing is required every millisecond 16 VREF mode Document Number: 002-24085 Rev. **

Page 34 of 60 PRELIMINARY CYBLE-416045-02 Table 21. CSD ADC Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions A_GAINERR_VREF Gain error A_GAINERR_VDDA Gain error A_OFFSET_VREF Input offset voltage A_OFFSET_VDDA Input offset voltage A_ISAR_VREF A_ISAR_VDDA A_VINS_VREF Current consumption Current consumption Input voltage range - single ended VSSA 0.6 0.2 0.5 0.5 0.3 0.3 VREF A_VINS_VDDA Input voltage range - single ended VSSA VDDA V

% Reference Source: SRSS

(VREF = 1.20 V, VDDA < 2.2 V),

(VREF = 1.6 V, 2.2 V < VDDA<2.7 V), (VREF = 2.13 V, VDDA>2.7 V)

% Reference Source: SRSS

(VREF=1.20 V, VDDA< 2.2V),

(VREF=1.6 V, 2.2 V < VDDA < 2.7 V),

(VREF = 2.13 V, VDDA > 2.7 V) lsb After ADC calibration, Ref. Src = SRSS, (VREF =

1.20 V, VDDA < 2.2 V), (VREF=1.6 V, 2.2 V<VDDA <

2.7 V),

(VREF = 2.13 V, VDDA > 2.7 V) lsb After ADC calibration, Ref. Src = SRSS, (VREF =

1.20 V, VDDA < 2.2 V), (VREF=1.6 V, 2.2 V<VDDA <

2.7 V),

(VREF = 2.13 V, VDDA > 2.7 V) mA CSD ADC Block current mA CSD ADC Block current V

(VREF = 1.20 V, VDDA < 2.2 V), (VREF=1.6 V, 2.2 V<VDDA < 2.7 V),

(VREF = 2.13 V, VDDA > 2.7 V)

(VREF = 1.20 V, VDDA < 2.2 V), (VREF=1.6 V, 2.2 V<VDDA < 2.7 V),

(VREF = 2.13 V, VDDA > 2.7 V) k pF dB A_INRES A_INCAP A_PSRR A_TACQ A_CONV8 A_CONV10 A_SND_VRE A_SND_VDDA A_INL_VREF A_INL_VDDA A_DNL_VREF Input charging resistance Input capacitance Power supply rejection ratio

(DC) Sample acquisition time Conversion time for 8-bit resolution at conversion rate

= Fhclk/(2"(N+2)). Clock frequency = 50 MHz. Conversion time for 10-bit resolution at conversion rate

= Fhclk/(2"(N+2)). Clock frequency = 50 MHz. Signal-to-noise and Distortion ratio (SINAD) Signal-to-noise and Distortion ratio (SINAD) Integral Non Linearity. 11.6 ksps Integral Non Linearity. 11.6 ksps Differential Non Linearity. 11.6 ksps 15 41 60 10 25 60 57 52 2 2 1 s Measured with 50 source impedance. 10 s is default software driver acquisition time setting. Settling to within 0.05%. s Does not include acquisition time. s Does not include acquisition time. dB Measured with 50 source impedance dB Measured with 50 source impedance LSB Measured with 50 source impedance LSB Measured with 50 source impedance LSB Measured with 50 source impedance Document Number: 002-24085 Rev. **

Page 35 of 60 PRELIMINARY CYBLE-416045-02 Table 21. CSD ADC Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions A_DNL_VDDA Differential Non Linearity. 11.6 ksps Digital Peripherals 1 LSB Measured with 50 source impedance Table 22. Timer/Counter/PWM (TCPWM) Specifications Parameter ITCPWM1 ITCPWM2 ITCPWM3 ITCPWM4 Description Block current consumption at 8 MHz Block current consumption at 24 MHz Block current consumption at 50 MHz Block current consumption at 100 MHz TCPWMFREQ Operating frequency Min Typ Max Units 70 180 270 A All modes (TCPWM) A All modes (TCPWM) A All modes (TCPWM) Details/Conditions A All modes (TCPWM) 540 100 MHz Fc max = Fcpu TPWMENEXT Input Trigger Pulse Width for all Trigger Events 2/Fc TPWMEXT Output Trigger Pulse widths TCRES Resolution of Counter PWMRES PWM Resolution QRES Quadrature inputs resolution 1.5/F c 1/Fc 1/Fc 2/Fc Maximum = 100 MHz Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) trigger outputs ns ns ns Minimum time between successive counts ns Minimum pulse width of PWM Output ns Minimum pulse width between Quadrature phase inputs. Delays from pins should be similar. Table 23. Serial Communication Block (SCB) Specifications Parameter Description Min Typ Max Units Details / Conditions Block current consumption at 100 kHz Block current consumption at 400 kHz Block current consumption at 1 Mbps I2C enabled in Deep Sleep mode Block current consumption at 100 Kbps Block current consumption at 1000 Kbps Bit Rate Fixed I2C DC Specifications II2C1 II2C2 II2C3 II2C4 Fixed I2C AC Specifications FI2C1 Fixed UART DC Specifications IUART1 IUART2 Fixed UART AC Specifications FUART1 FUART2 Fixed SPI DC Specifications ISPI1 ISPI2 Bit Rate Block current consumption at 1Mbps Block current consumption at 4 Mbps 30 80 180 1.7 A A A A At 60 C 1 Mbps 30 180 A A 3 8 Mbps ULP Mode LP Mode 220 340 A A Document Number: 002-24085 Rev. **

Page 36 of 60 PRELIMINARY CYBLE-416045-02 Table 23. Serial Communication Block (SCB) Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions Block current consumption at 8 Mbps Block current consumption at 25 Mbps ISPI3 ISP14 Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise FSPI SPI Operating frequency Master and Externally Clocked Slave SPI Slave Internally Clocked 360 800 A A 25 MHz 14-MHz max for ULP (0.9 V) mode FSPI_IC Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise ns TDMO 20ns max for ULP (0.9 V) mode ns Full clock, late MISO sampling TDSI THMO ns Referred to Slave capturing edge Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise ns TDMI TDSO_EXT ns MOSI Valid after SClock driving edge MISO Valid before SClock capturing edge MOSI data hold time 15 MHz 5 MHz max for ULP (0.9 V) mode 35ns max. for ULP (0.9 V) mode 12 20 5 0 5 MOSI Valid before Sclock Capturing edge MISO Valid after Sclock driving edge in Ext. Clk. mode MISO Valid after Sclock driving edge in Internally Clk. Mode MISO Valid after Sclock driving edge in Internally Clk. Mode with Median filter enabled. TDSO TDSO THSO TSSELSCK1 TSSELSCK2 Previous MISO data hold time SSEL Valid to first SCK Valid edge SSEL Hold after Last SCK Valid edge 5 65 65 TDSO_ EXT +

3*Tscb TDSO_ EXT +

4*Tscb ns Tscb is Serial Comm Block clock period. ns Tscb is Serial Comm Block clock period. ns ns ns Document Number: 002-24085 Rev. **

Page 37 of 60 PRELIMINARY CYBLE-416045-02 LCD Specifications Table 24. LCD Direct Drive DC Specifications Parameter Description ILCDLOW CLCDCAP LCDOFFSET ILCDOP1 ILCDOP2 Operating current in low-power mode LCD capacitance per segment/common driver Long-term segment offset PWM Mode current. 3.3-V bias. 8-MHz IMO. 25 C. PWM Mode current. 3.3-V bias. 8-MHz IMO. 25 C. Table 25. LCD Direct Drive AC Specifications Parameter FLCD Description LCD frame rate Memory Table 26. Flash Specifications Min Typ 5 500 20 0.6 0.5 Max 5000 Units A Details/Conditions 16 x 4 small segment display at 50 Hz pF mV mA 32 4 segments 50 Hz mA 32 4 segments 50 Hz Min 10 Typ 50 Max 150 Units Hz Details/Conditions Parameter Description Min Typ Max Units Details / Conditions Erase and program voltage Row (Block) write time (erase & program) Row erase time Flash DC Specifications VPE Flash AC Specifications TROWWRITE TROWERASE TROWPROGRAM Row program time after erase TBULKERASE Bulk erase time (1024K bytes) TSECTORERASE Sector erase time (256K bytes) TSSERIAE TSSWRITE TSWRITE TDEVPROG FEND FRET1 FRET2 FRET3 TWS100 TWS50 Sub-sector erase time Sub-sector write time; 1 erase plus 8 program times Sector write time; 1 erase plus 512 program times Total device program time Flash Endurance Flash Retention. Ta 25 C, 100K P/E cycles Flash Retention. Ta 85 C, 10K P/E cycles Flash Retention. Ta 55 C, 20K P/E cycles Number of Wait states at 100 MHz Number of Wait states at 50 MHz Row (Block) = 512 bytes 512 rows per sector 8 rows per sub-sector 1.71 100K 10 10 20 3 2 V ms ms ms ms ms ms ms seconds seconds cycles years years years 3.6 16 11 5 11 11 11 51 2.6 15 Note 8. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-24085 Rev. **

Page 38 of 60 PRELIMINARY CYBLE-416045-02 System Resources Table 27. CYBLE-416045-02 System Resources Parameter Description Min Typ Max Units Details/Conditions Power-On-Reset with Brown-out DC Specifications Precise POR(PPOR) VFALLPPOR VFALLDPSLP VDDRAMP POR with Brown-out AC Specification BOD trip voltage in Active and Sleep modes. VDDD BOD trip voltage in Deep Sleep. VDDD Maximum power supply ramp rate (any supply) Maximum power supply ramp rate (any supply) in Deep Sleep VDDRAMP_DS Voltage Monitors DC Specifications VHVD0 VHVDI1 VHVDI2 VHVDI3 VHVDI4 VHVDI5 VHVDI6 VHVDI7 VHVDI8 VHVDI9 VHVDI10 VHVDI11 VHVDI12 VHVDI13 VHVDI14 VHVDI15 LVI_IDD Voltage Monitors AC Specification TMONTRIP Block current Voltage monitor trip time 1.54 1.54 V V BOD Reset guaranteed for levels below 1.54 V 100 mV/s Active Mode 10 mV/s BOD operation guaranteed 1.18 1.23 1.27 1.38 1.43 1.47 1.57 1.63 1.68 1.76 1.83 1.89 2.1 1.95 2.03 2.05 2.13 2.2 2.15 2.23 2.3 2.24 2.33 2.41 2.34 2.43 2.51 2.44 2.53 2.61 2.53 2.63 2.72 2.63 2.73 2.82 2.73 2.83 2.92 2.82 2.93 3.03 2.92 3.03 3.13 3.02 3.13 3.23 15 5 170 V V V V V V V V V V V V V V V V A ns Document Number: 002-24085 Rev. **

Page 39 of 60 PRELIMINARY CYBLE-416045-02 SWD Interface Table 28. SWD and Trace Specifications Parameter Description Min Typ Max Units Details / Conditions SWD and Trace Interface 1.7 V VDDD 3.6 V 1.7 V VDDD 3.6 V F_SWDCLK2 F_SWDCLK2L T_SWDI_SETUP T = 1/f SWDCLK T_SWDI_HOLD T = 1/f SWDCLK T_SWDO_VALID T = 1/f SWDCLK T_SWDO_HOLD T = 1/f SWDCLK F_TRCLK_LP1 With Trace Data setup/hold times of 2/1 ns respectively F_TRCLK_LP2 With Trace Data setup/hold times of 3/2 ns respectively F_TRCLK_ULP With Trace Data setup/hold times of 3/2 ns respectively Internal Main Oscillator Table 29. IMO DC Specifications 0.25*T 0.25*T 1 25 12 0.5*T 75 70 25 LP Mode; VCCD = 1.1 V MHz MHz ULP Mode. VCCD = 0.9 V. ns ns ns ns MHz LP Mode. VDD = 1.1 V MHz LP Mode. VDD = 1.1 V MHz ULP Mode. VDD = 0.9 V Parameter Description IIMO1 IMO operating current at 8 MHz Min Typ 9 Max 15 Units A Details/Conditions Table 30. IMO AC Specifications Parameter FIMOTOL1 TJITR Description Frequency variation centered on 8 MHz Cycle-to-Cycle and Period jitter Min Typ 250 Max 2 Units Details/Conditions

%

ps Internal Low-Speed Oscillator Table 31. ILO DC Specification Parameter Description IILO2 ILO operating current at 32 kHz Table 32. ILO AC Specifications Parameter Description TSTARTILO1 TLIODUTY FILOTRIM1 ILO startup time ILO Duty cycle 32-kHz trimmed frequency External Clock Specifications Table 33. External Clock Specifications Parameter EXTCLKFREQ EXTCLKDUTY Description External Clock input Frequency Duty cycle; Measured at VDD/2 Min Min 45 28.8 Typ 0.3 Typ 50 32 Max 0.7 Units A Details/Conditions Max 7 55 35.2 Units s

%

kHz Details/Conditions Startup time to 95% of final frequency 10% variation Min 0 45 Typ Max 100 55 Units MHz

%

Details/Conditions Document Number: 002-24085 Rev. **

Page 40 of 60 PRELIMINARY CYBLE-416045-02 Table 34. PLL Specifications Parameter PLL_LOCK PLL_OUT PLL_IDD PLL_JTR Description Time to achieve PLL Lock Output frequency from PLL Block PLL Current Period Jitter Table 35. Clock Source Switching Time Min Typ 16 0.55 Max 35 150 1.1 150 Units s MHz mA ps Details/Conditions Typ at 100 MHz out. 100 MHz output frequency Parameter TCLKSWITCH Description Min Typ Clock switching from clk1 to clk2 in clock periods Max Units 4 clk1 +

3 clk2 periods Details/Conditions Table 36. Frequency Locked Loop (FLL) Specifications Parameter Description Min Typ Max Units Details / Conditions Frequency Locked Loop (FLL) Specifications FLL_RANGE Input frequency range. FLL_OUT_DIV2 FLL_OUT_DIV2 Output frequency range. VCCD = 1.1 V Output frequency range. VCCD = 0.9 V FLL_DUTY_DIV2 Divided-by-2 output; High or Low FLL_WAKEUP Time from stable input clock to 1% of final value on deep sleep wakeup FLL_JITTER FLL_CURRENT Period jitter (1 sigma at 100 MHz) CCO + Logic current 0.001 24.00 24.00 47.00 100 MHz Lower limit allows lock to USB SOF signal (1 kHz). Upper limit is for External input. 100.00 50.00 53.00 7.50 35.00 5.50 MHz Output range of FLL divided-by-2 output MHz Output range of FLL divided-by-2 output

%

us ps A/MHz With IMO input, less than 10 C change in temperature while in Deep Sleep, and Fout 50 MHz. 50 ps at 48 MHz, 35 ps at 100 MHz Table 37. UDB AC Specifications Parameter Data Path Performance Description Min Typ Max Units Details/Conditions FMAX-TIMER FMAX-ADDER Max frequency of 16-bit timer in a UDB pair Max frequency of 16-bit adder in a UDB pair FMAX_CRC PLD Performance in UDB Max frequency of 16-bit CRC/PRS in a UDB pair FMAX_PLD Clock to Output Performance Max frequency of 2-pass PLD function in a UDB pair TCLK_OUT_UDB1 Prop. delay for clock in to data out 5 100 100 100 MHz MHz MHz 100 MHz ns Document Number: 002-24085 Rev. **

Page 41 of 60 PRELIMINARY CYBLE-416045-02 Table 37. UDB AC Specifications (continued) UDB Port Adaptor Specifications Conditions: 10-pF load, 3-V VDDIO and VDDD TLCLKDO TDINLCLK TDINLCLKHLD TLCLKHIZ TFLCLK TLCLKDUTY LCLK to Output delay Input setup time to LCLCK rising edge Input hold time from LCLK rising edge LCLK to Output tristated LCLK frequency LCLK duty cycle (percentage high) Table 38. Audio Subsystem Specifications 5 40%

11 7 28 33 60%

ns ns ns ns MHz

%

Parameter Description Min Typ Max Units Details / Conditions Audio Subsystem specifications PDM Specifications 175 600 PDM_IDD1 PDM_IDD2 PDM Active current, Stereo operation, 1-MHz clock PDM Active current, Stereo operation, 3-MHz clock RMS Jitter in PDM clock PDM Clock speed PDM_JITTER PDM_CLK PDM_BLK_CLK PDM Block input clock PDM_SETUP PDM_HOLD PDM_OUT PDM_WL Data input set-up time to PDM_CLK edge Data input hold time to PDM_CLK edge Audio sample rate Word Length PDM_SNR Signal-to-Noise Ratio (A-weighted0 PDM_DR Dynamic Range (A-weighted) PDM_FR Frequency Response 200 0.384 1.024 10 10 8 16 0.2 100 100 Stop Band Stop Band Attenuation Adjustable Gain Startup time PDM_SB PDM_SBA PDM_GAIN PDM_ST I2S Specifications. The same for LP and ULP modes unless stated otherwise. I2S_WORD Length of I2S Word 12 60 48 0.566 8 I2S_WS Word Clock frequency in LP mode I2S_WS_U Word Clock frequency in ULP mode I2S_WS_TDM Word Clock frequency in TDM mode for LP I2S_WS_TDM_U Word Clock frequency in TDM mode for ULP I2S Slave Mode TS_WS WS Setup Time to the Following Rising Edge of SCK for LP Mode 5 200 3.072 49.152 48 24 0.2 10.5 32 192 48 48 12 16-bit audio at 16 ksps 24-bit audio at 48 ksps PDM input, 20 Hz to 20 kHz BW 20 Hz to 20 kHz BW, -60 dB FS DC to 0.45. DC Blocking filter off. PDM to PCM, 1.5 dB/step WS (Word Select) cycles 12.288-MHz bit clock with 32-bit word 3.072-MHz bit clock with 32-bit word 8 32-bit channels 8 32-bit channels A A ps MHz MHz ns ns ksps bits dB dB dB f dB dB bits kHz kHz kHz kHz ns Document Number: 002-24085 Rev. **

Page 42 of 60 PRELIMINARY CYBLE-416045-02 Table 38. Audio Subsystem Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions TS_WS TH_WS WS Setup Time to the Following Rising Edge of SCK for ULP Mode WS Hold Time to the Following Edge of SCK TMCLK_S 11 OC+5 TD_SDO Delay Time of TX_SDO Transition from Edge of TX_SCK for LP mode

-(TMCLK_ SOC+25) TD_SDO TS_SDI TS_SDI TH_SDI Delay Time of TX_SDO Transition from Edge of TX_SCK for ULP mode

-(TMCLK_ SOC+70) RX_SDI Setup Time to the Following Edge of RX_SCK in Lp Mode RX_SDI Setup Time to the Following Edge of RX_SCK in ULP mode 5 11 RX_SDI Hold Time to the Rising Edge of RX_SCK TMCLK_S OC+5 TSCKCY I2S Master Mode TX/RX_SCK Bit Clock Duty Cycle TD_WS TD_WS_U TD_SDO TD_SDO TS_SDI WS Transition Delay from Falling Edge of SCK in LP mode WS Transition Delay from Falling Edge of SCK in ULP mode SDO Transition Delay from Falling Edge of SCK in LP mode SDO Transition Delay from Falling Edge of SCK in ULP mode SDI Setup Time to the Associated Edge of SCK 45 10 10 10 10 5 TH_SDI SDI Hold Time to the Associated Edge of SCK TMCLK_S OC+5 TSCKCY FMCLK_SOC SCK Bit Clock Duty Cycle MCLK_SOC Frequency in LP mode FMCLK_SOC_U MCLK_SOC Frequency in ULP mode TMCLKCY TJITTER MCLK_SOC Duty Cycle MCLK_SOC Input Jitter 45 1.024 1.024 45 100 TMCLK_ SOC+25 TMCLK_ SOC+70 55 20 40 20 40 ns ns ns ns ns ns ns

%

ns ns ns ns ns ns 55 98.304 24.576 55 100

%

MHz MHz

%

ps Associated clock edge depends on selected polarity Associated clock edge depends on selected polarity Associated clock edge depends on selected polarity T is TX/RX_SCK Bit Clock period. Associated clock edge depends on selected polarity. FMCLK_SOC = 8*Bit-clock FMCLK_SOC_U =

8*Bit-clock Document Number: 002-24085 Rev. **

Page 43 of 60 PRELIMINARY CYBLE-416045-02 Table 39. Smart I/O Specifications Parameter SMIO_BYP SMIO_LUT Description Smart I/O Bypass delay Smart I/O LUT prop delay Min Typ TBD Max 2 Units ns ns Details/Conditions Document Number: 002-24085 Rev. **

Page 44 of 60 PRELIMINARY CYBLE-416045-02 Table 40. BLE Subsystem Specifications Parameter Description Min Typ Max Units Details / Conditions BLE Subsystem specifications RF Receiver Specifications (1 Mbps) RXS,IDLE RXS,IDLE RXS,DIRTY PRXMAX CI1 CI2 CI3 CI4 CI5 CI6 RXS,IDLE RXS,DIRTY PRXMAX CI1 CI2 CI3 CI4 RX Sensitivity with Ideal Trans-

mitter RX Sensitivity with Ideal Trans-

mitter RX Sensitivity with Dirty Transmitter Maximum received signal strength at < 0.1% PER Co-channel interference, Wanted Signal at -67dBm and Inter-

ferer at FRX Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 1 MHz Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 2 MHz Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 3 MHz Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at Image frequency (FIMAGE) Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at Image frequency (FIMAGE 1 MHz ) RX Sensitivity with Ideal Trans-

mitter RX Sensitivity with Ideal Trans-

mitter RX Sensitivity with Dirty Transmitter Maximum received signal strength at < 0.1% PER Co-channel interference, Wanted Signal at -67dBm and Inter-

ferer at FRX Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 2 MHz Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 4 MHz Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at FRX 6 MHz 95 93 92 0 9 3 21 15 Frequency Range dBm Across RF Operating Frequency Range dBm 255-byte packet length, across dBm RF-PHY Specification dBm RF-PHY Specification

(RCV-LE/CA/01/C)

(RCV-LE/CA/06/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) 26 17 dB RF-PHY Specification

(RCV-LE/CA/03/C) 33 27 dB RF-PHY Specification

(RCV-LE/CA/03/C) 20 9 dB RF-PHY Specification

(RCV-LE/CA/03/C) 28 15 dB RF-PHY Specification

(RCV-LE/CA/03/C) 92 90 89 0 9 3

-26 33 21 15

-17

-27 Frequency Range dBm Across RF Operating Frequency Range dBm 255-byte packet length, across dBm RF-PHY Specification dBm RF-PHY Specification

(RCV-LE/CA/01/C)

(RCV-LE/CA/06/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) dB RF-PHY Specification

(RCV-LE/CA/03/C) RF Receiver Specifications (2 Mbps) RXS,IDLE Document Number: 002-24085 Rev. **

Page 45 of 60 PRELIMINARY CYBLE-416045-02 Table 40. BLE Subsystem Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions CI5 CI6 Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at Image frequency (FIMAGE) Adjacent channel interference Wanted Signal at -67dBm and Inter-

ferer at Image frequency (FIMAGE 2MHz) 20 9 dB RF-PHY Specification

(RCV-LE/CA/03/C) 28 15 dB RF-PHY Specification

(RCV-LE/CA/03/C) OBB2 OBB1 OBB3 RF Receiver Specification (1 & 2 Mbps) Out of Band Blocking Wanted Signal at -67dBm and Inter-

ferer at F = 30 -2000 MHz Out of Band Blocking Wanted Signal at -67dBm and Inter-

ferer at F = 2003 -2399 MHz Out of Band Blocking, Wanted Signal at -67dBm and Inter-

ferer at F= 2484-2997MHz Out of Band Blocking Wanted Signal at -67dBm and Inter-

ferer at F= 3000-12750 MHz Intermodulation Performance Wanted Signal at -64dBm amd 1 Mbps BLE, 3rd, 4th and 5th offset channel Receiver Spurious emission 30 MHz to 1.0 GHz Receiver Spurious emission 1.0 GHz to 12.75 GHz RXSE1 OBB4 IMD RXSE2 RF Transmitter Specifications TXP,ACC TXP,RANGE TXP,0dBm TXP,MAX RF Power Accuracy Frequency Accuracy Output Power, 0 dB Gain setting Output Power, Maximum Power Setting Output Power, Minimum Power Setting Average Frequency deviation for 10101010 pattern Average Frequency deviation for 10101010 pattern for 2Mbps Average Frequency deviation for 11110000 pattern Average Frequency deviation for 11110000 pattern for 2Mbps Eye opening = F2AVG/F1AVG TXP,MIN F2AVG F2AVG_2M F1AVG F1AVG_2M EO FTX,ACC Frequency Accuracy FTX,MAXDR Maximum Frequency Drift 30 27 35 27 35 27 30 27 50 185 370 225 450 0.8 150 50 24 0 4 20 250 500 57 53 1 275 550 150 50 dBm RF-PHY Specification

(RCV-LE/CA/04/C) dBm RF-PHY Specification

(RCV-LE/CA/04/C) dBm RF-PHY Specification

(RCV-LE/CA/04/C) dBm RF-PHY Specification

(RCV-LE/CA/04/C) dBm RF-PHY Specification

(RCV-LE/CA/05/C) ETSI EN300 328 V2.1.1 ETSI EN300 328 V2.1.1 dBm 100 kHz measurement bandwidth dBm 1 MHz measurement bandwidth dB dB dBm dBm

-20dBm to +4dBm

(TRM-LE/CA/05/C)

(TRM-LE/CA/05/C)

(TRM-LE/CA/05/C) dBm kHz RF-PHY Specification kHz RF-PHY Specification kHz RF-PHY Specification kHz RF-PHY Specification

(TRM-LE/CA/05/C) RF-PHY Specification

(TRM-LE/CA/05/C) kHz RF-PHY Specification kHz RF-PHY Specification

(TRM-LE/CA/06/C)

(TRM-LE/CA/06/C) Document Number: 002-24085 Rev. **

Page 46 of 60 PRELIMINARY CYBLE-416045-02 Table 40. BLE Subsystem Specifications (continued) Parameter Description FTX,INITDR Initial Frequency drift FTX,DR IBSE1 IBSE2 TXSE1 Maximum Drift Rate In Band Spurious Emission at 2 MHz offset (1 Mbps) In Band Spurious Emission at 4 MHz offset (2 Mbps) In Band Spurious Emission at 3 MHz offset (1 Mbps) In Band Spurious Emission at 6 MHz offset (2 Mbps) Transmitter Spurious Emissions

(Averaging), < 1.0 GHz Transmitter Spurious Emissions

(Averaging), > 1.0 GHz TXSE2 RF Current Specification IRX1_wb Receive Current (1 Mbps) ITX1_wb_0dBm TX Current at 0 dBm setting IRX1_nb ITX1_nb_0dBm TX Current at 0-dBm setting ITX1_nb_4dBm TX Current at 4-dBm setting ITX1_wb_4dBm TX Current at 4-dBm setting ITX1_nb_20dBm TX Current at -20-dBm setting

(1 Mbps) Receive Current (1 Mbps)

(1 Mbps)

(1Mbps)

(1Mbps)

(1Mbps) Receive Current (2 Mbps)

(2Mbps)

(2Mbps)

(2Mbps) Receive Current (2Mbps) IRX2_wb ITX2_wb_0dBm TX Current at 0 dBm setting IRX2_nb ITX2_nb_0dBm TX Current at 0 dBm setting ITX2_nb_4dBm TX Current at 4 dBm setting ITX2_wb_4dBm TX Current at 4 dBm setting ITX2_nb_20dBm TX Current at -20 dBm setting General RF Specification FREQ CHBW DR1 DR2 TXSUP RXSUP RF operating frequency Channel spacing On-air Data Rate (1Mbps) On-air Data Rate (2Mbps) Transmitter Startup time Receiver Startup time

(2Mbps)

(2Mbps) Min 20 20 2400 Typ Max Units Details / Conditions 6.7 5.7 11 10 13 8.5 7 7 5.7 11.3 10 13 8.5 7 2 1000 2000 80 80 20 20

-20

-30 kHz RF-PHY Specification

(TRM-LE/CA/06/C) RF-PHY Specification kHz/

50 s

(TRM-LE/CA/06/C) dBm RF-PHY Specification

(TRM-LE/CA/03/C) dBm RF-PHY Specification

(TRM-LE/CA/03/C)

-55.5 dBm FCC-15.247

-41.5 dBm FCC-15.247 buck mA VDD_NS = VDDD = 3.3 V current with mA VDD_NS = VDDD = 3.3 V current with mA VDDD current without buck mA VDDD current without buck buck mA VDDD current without buck mA VDD_NS = VDDD = 3.3 V current with buck buck mA VDDD current without buck mA VDD_NS = VDDD = 3.3 V current with mA VDD_NS = VDDD = 3.3 V current with mA VDDD current without buck mA VDDD current without buck buck mA VDDD current without buck mA VDD_NS = VDDD = 3.3 V current with buck mA VDDD current without buck 2482 82 82 MHz MHz Kbps Kbps s s Document Number: 002-24085 Rev. **

Page 47 of 60 PRELIMINARY CYBLE-416045-02 Table 40. BLE Subsystem Specifications (continued) Parameter Description Min Typ Max Units Details / Conditions RSSI Accuracy RSSI Resolution RSSI Sample Period RSSI Specification RSSI,ACC RSSI,RES RSSI,PER System-Level BLE Specifications Adv_Pwr Conn_Pwr_300 Conn_Pwr_1S Conn_Pwr_4S Table 41. Precision ILO (PILO) Specifications 1.28s, 32 bytes, 0 dBm 300 ms, 0 byte, 0 dBm 1000 ms, 0 byte, 0 dBm 4000 ms, 0 byte, 0 dBm Parameter Description 4 1 6 42 70 30 4 4

-95 dBm to -20 dBm measurement range dB dB s W 3.3 V, Buck, w/o Deep Sleep current W 3.3 V, Buck, w/o Deep Sleep current W 3.3 V, Buck, w/o Deep Sleep current W 3.3 V, Buck, w/o Deep Sleep current IPILO F_PILO ACC_PILO Operating current PILO nominal frequency PILO accuracy with periodic calibration 500 Min Typ 1.2 32768 Max Units A 4 Hz 500 ppm Details/Conditions T = 25 C with 20-ppm crystal Document Number: 002-24085 Rev. **

Page 48 of 60 PRELIMINARY CYBLE-416045-02 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances directives. The Cypress module RF Certification The CYBLE-416045-02 module is certified under the following RF certification standards:

and components used to produce this module are RoHS and HF compliant.

(RoHS) and Halogen Free (HF) FCC ID: WAP6045 CE IC: 7922A-6045 MIC: TBD n n n n Environmental Conditions Table Table 42. Environmental Conditions for CYBLE-416045-02 describes the operating and storage conditions for the Cypress 42 BLE module. Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[9]

40 C 5%

40 C 85 C 85%

3 C/minute 85 C 85 C at 85%

15 kV Air 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 9. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-24085 Rev. **

Page 49 of 60 PRELIMINARY CYBLE-416045-02 Regulatory Information FCC FCC NOTICE:

The device CYBLE-416045-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. notified that any changes or modifications made to this device the user's authority to operate CAUTION:

The FCC requires the user to be Cypress Semiconductor may void This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause installation. harmful interference to radio communications. However, there is If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of that are not expressly approved no guarantee that interference will not occur in a particular the following measures:

the equipment. by Reorient or relocate the receiving antenna. Increase the separation between Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help the equipment and receiver. n n n n LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that FCC label on the outside as the FCC Notice above. The FCC In any case the end product must identifier is FCC ID: WAP6045. of the OEM enclosure be labeled exterior with "Contains FCC ID: WAP6045"

specifying the appropriate Cypress Semiconductor FCC identifier for this product as labelling requirements are met. This includes a clearly visible well ANTENNA WARNING:

This device is tested with a standard SMA connector and with the antennas listed in on page 19. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. Table 7 Table 7 RF EXPOSURE:

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-416045-02 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-416045-02 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions on page 19, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal in manuals, for products operating with the approved antennas for satisfying RF exposure compliance. Document Number: 002-24085 Rev. **

Page 50 of 60 PRELIMINARY CYBLE-416045-02 is to the meet licensed regulatory ISED Innovation, Science and Economic Development (ISED) Canada Certification CYBLE-416045-02 Canada. License: IC: 7922A-6045 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance from www.ic.gc.ca. on page 19, having a maximum gain of -0.5 dBi. Antennas This device has been designed to operate with the antennas listed in not included in prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. on page 19 or having a gain greater than -0.5 dBi are strictly Development requirements compliance information Innovation, Economic Canadian exposure exposure Science Table 7 Table 7 and/or

(ISED) Users limits. obtain SAR and can and RF RF for on of ISED NOTICE:

The device CYBLE-416045-02 including the built-in trace antenna requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to device may not cause harmful interference, and (2) This device may cause undesired operation. complies with Canada RSS-GEN Rules. The device meets the the following two conditions: (1) This must accept any interference received, including interference that L'appareil CYBLE-416045-02, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux conditions exigences suivantes: (1) Cet appareil ne doit pas causer d'interfrences reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. doit accepter toute interfrence nuisibles, et (2) Cet appareil d'approbation L'opration RSS-GEN. modulaire l'metteur soumise dans deux dcrit que aux de tel est ISED INTERFERENCE STATEMENT FOR CANADA This and Operation is subject to the following two conditions: (1) this interference, including interference that may cause undesired operation of the device. Development Innovation, Economic complies Science device with standard(s). device may not cause interference, and (2) this device must accept any licence-exempt Canada

(ISED) RSS Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonction-

nement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that ISED label on the outside of the OEM the ISED Notices above. The IC identifier is 7922A-6045. In any case, IC: 7922A-6045". labelling requirements are met. This includes a clearly visible enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the end product must be labeled in its exterior with "Contains Le fabricant d'quipement d'origine (OEM) doit s'assurer que les exigences d'tiquetage ISED sont respectes. Cela comprend une tiquette clairement visible l'extrieur de l'enceinte OEM spcifiant l'identifiant Cypress Semiconductor IC appropri pour ce produit ainsi que l'avis ISED ci-dessus. extrieur avec "Contient IC: 7922A-6045". L'identificateur IC est 7922A-6045. En tout cas, le produit final doit tre tiquet dans son Document Number: 002-24085 Rev. **

Page 51 of 60 PRELIMINARY CYBLE-416045-02 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-416045-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:

All versions of the CYBLE-416045-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-

bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBLE-416045-02 is certified as a module with type certification number TBD. End products that integrate CYBLE-416045-02 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. Document Number: 002-24085 Rev. **

Page 52 of 60 PRELIMINARY CYBLE-416045-02 Packaging Table 43. Solder Reflow Peak Temperature Module Part Number CYBLE-416045-02 Package 43-pad SMT Maximum Peak Temperature Maximum Time at PeakTemperature No. of Cycles 260 C 30 seconds 2 Table 44. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBLE-416045-02 Package 43-pad SMT MSL MSL 3 The CYBLE-416045-02 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-416045-02. Figure 10. CYBLE-416045-02 Tape Dimensions (TBD) Figure 11 details the orientation of the CYBLE-416045-02 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction (TBD) Document Number: 002-24085 Rev. **

Page 53 of 60 PRELIMINARY CYBLE-416045-02 Figure 12 details reel dimensions used for the CYBLE-416045-02. Figure 12. Reel Dimensions The CYBLE-416045-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-416045-02 is detailed in Figure 13. Figure 13. CYBLE-416045-02 Center of Mass (TBD) Document Number: 002-24085 Rev. **

Page 54 of 60 PRELIMINARY CYBLE-416045-02 Ordering Information Table 45 lists the CYBLE-416045-02 part number and features. Table 46 lists the reel shipment quantities for the CYBLE-416045-02. Table 45. Ordering Information MPN

) 4 M

(

d e e p S U P C CYBLE-416045-02 150/50

)

+

0 M

(

d e e p S U P C 100/25 Features B D U e s n e S p a C e v i r D D C L t c e r i D C D A R A S t i b

-

2 1

) B K

(

h s a F l

) B K

(

M A R S 1024 288 12 3 3 1 Msps s r o t a r a p m o C P L 2 l s k c o B B C S M D P S 2

/

I I O P G e g a k c a P 2 3 36 43-SMT Table 46. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) 500 500 500 500 Minimum Reel Quantity Maximum Reel Quantity Comments Ships in 500 unit reel quantities. The CYBLE-416045-02 is offered in tape and reel packaging. The CYBLE-416045-02 ships with a maximum of 500 units/reel. Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com

(408) 943-2600 Document Number: 002-24085 Rev. **

Page 55 of 60 PRELIMINARY CYBLE-416045-02 Acronyms Table 47. Acronyms Used in this Document Acronym Description abus ADC AG AHB ALU AMUXBUS API APSR Arm ATM BW CAN CMRR CPU CRC DAC DFB DIO DMIPS DMA DNL DNU DR DSI DWT ECC ECO EEPROM EMI EMIF EOC EOF EPSR ESD analog local bus analog-to-digital converter analog global AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode bandwidth Controller Area Network, a communications protocol common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO. Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge Table 47. Acronyms Used in this Document (continued) Acronym Description ETM FIR FPB FS GPIO HVI IC IDAC IDE I2C, or IIC IIR ILO IMO INL I/O IPOR IPSR IRQ ITM LCD LIN LR LUT LVD LVI LVTTL MAC MCU MISO NC NMI NRZ NVIC NVL opamp PAL PC embedded trace macrocell finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display Local Interconnect Network, a communications protocol. link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter Document Number: 002-24085 Rev. **

Page 56 of 60 PRELIMINARY CYBLE-416045-02 Table 47. Acronyms Used in this Document (continued) Table 47. Acronyms Used in this Document (continued) Acronym Description Acronym Description TD THD TIA TRM TTL TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal PCB PGA PHUB PHY PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC PSRR PWM RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL SDA S/H SINAD SIO SOC SOF SPI SR SRAM SRES SWD SWV printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-Chip power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I2C serial clock I2C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. start of conversion start of frame Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol single-wire viewer Document Number: 002-24085 Rev. **

Page 57 of 60 PRELIMINARY CYBLE-416045-02 Document Conventions Units of Measure Table 48. Units of Measure Symbol Unit of Measure C dB dBm fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V degrees Celsius decibel decibel-milliwatts femtofarads hertz 1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt Document Number: 002-24085 Rev. **

Page 58 of 60 PRELIMINARY CYBLE-416045-02 Document History Page Document Title: CYBLE-416045-02 EZ-BLE Creator Module Document Number: 002-24085 Orig. of Revision Change Submission Date ECN PRELIM PRELIM DSO Description of Change 05/29/2018 Preliminary datasheet for CYBLE-416045-02 module. Document Number: 002-24085 Rev. **

Page 59 of 60 PRELIMINARY CYBLE-416045-02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs |

Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-24085 Rev. **

Revised May 30, 2018 Page 60 of 60