FCC ID: WAP-0737 This product is a Bluetooth wireless EZ-BT WICED SIP Module

by: Cypress Semiconductor latest update: 2018-05-14 model: 0737

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1	User Manual CYW20732S - 0514	Users Manual	pdf	1.76 MiB
1	User Manual CYW20736S - 0514	Users Manual	pdf	1.62 MiB
1	User Manual CYW20737S - 0514	Users Manual	pdf	1.44 MiB
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User Manual CYW20732S - 0514

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CYW20732S Bluetooth Low Energy SiP Module Doc. # 002-15222 Rev. *G Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): +1.408.943.2600 www.cypress.com Copyrights Copyrights Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or refer-

enced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as spe-

cifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organi-

zation, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR-

POSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without fur-

ther notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weap-

ons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-

RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respec-

tive owners. CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 2 Preface This document provides descriptions of the interfaces, pin assignments, and specifications of Cypress CYW20732S Bluetooth Low Energy (BLE) System-in-Package (SiP) module. It is intended for designers who are responsible for adding the CYW20732S module to wireless input devices including heart-rate monitors, blood pressure monitors, proximity sensors, temperature sensors, and battery monitors. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this con-

version, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 2-1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM20732 BCM20732S CYW20732 CYW20732S Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary. Document Conventions The following conventions may be used in this document:

Convention Bold Monospace

< >

[ ]

Description User input and actions: for example, type exit, click OK, press Alt+C Code: #include <iostream>

HTML: <td rowspan = 3>

Command line commands and parameters: wl [-l] <command>

Placeholders for required elements: enter your <username> or wl <command>

Indicates optional command-line parameters: wl [-l]

Indicates bit and byte ranges (inclusive): [0:3] or [7:0]

Technical Support Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout informa-

tion, and software updates. Customers can acquire technical documentation and software from the Cypress Support Commu-

nity website (http://community.cypress.com/). 3 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Preface CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 4 Contents 1. 1.2 1.3 1.4 1.5 1.6 7 Introduction 1.1 Overview...................................................................................................................................7 1.1.1 Features........................................................................................................................7 1.1.2 Application Profiles........................................................................................................7 1.1.3 Block Diagram...............................................................................................................8 1.1.4 External Reset...............................................................................................................8 1.1.5 32.768 kHz Oscillator....................................................................................................9 Pin Map and Signal Descriptions............................................................................................10 Electrical Specifications ..........................................................................................................14 RF Specifications....................................................................................................................15 ADC Specifications .................................................................................................................16 Timing and AC Characteristics ...............................................................................................17 1.6.1 SPI Timing...................................................................................................................17 1.6.2 BSC Interface Timing ..................................................................................................18 1.6.3 UART Timing...............................................................................................................19 PCB Design and Manufacturing Recommendations ..............................................................20 1.7.1 Pad and Solder Mask Opening Dimensions ...............................................................20 1.7.2 PCB Layout Recommendations for Configuration A ...................................................20 1.7.3 PCB Layout Recommendations for Configuration B...................................................23 1.7.4 Common Guidelines for CYW20732S.........................................................................24 1.7.5 PCB Stencil.................................................................................................................25 1.7.6 Solder Reflow..............................................................................................................26 1.8 Packaging and Storage Information .......................................................................................27 1.9 Mechanical Information...........................................................................................................29 1.10 Ordering Information...............................................................................................................31 33 1.7 Revision History 5 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Contents CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 6 1. Introduction Overview 1.1 The CYW20732S is a compact, highly-integrated Bluetooth low-energy (BLE) system-in-package (SiP) module. The CYW20732S SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of exter-

nal components is needed to create a standalone BLE device. The CYW20732S is designed to accelerate time-to-market. The Bluetooth stack and several application profiles are built into the module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20732S includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load cycle. All this, coupled with an ultra-small form factor and support for a wide voltage range, makes the CYW20732S well suited for virtually any Bluetooth Smart application. Features 1.1.1 ARM Cortex-M3 microcontroller unit (MCU) Embedded 512 Kb EEPROM Broadcom Serial Control (BSC), SPI, and UART interfaces FCC and CE compliant RoHS compliant, certified lead- and halogen-free Moisture Sensitivity Level (MSL) 3 compliant 6.5 mm 6.5 mm 1.2 mm Land Grid Array (LGA) 48-pin package Application Profiles 1.1.2 The following profiles are supported in CYW20732S ROM:

Battery status Blood pressure monitor Find me Heart rate monitor Proximity Thermometer Weight scale Time Blood glucose monitor Additional profiles that can be supported in CYW20732S RAM include:

Blood glucose monitor Temperature alarm Location Other custom profiles 7 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 1.1.3 A block diagram of the CYW20732S BLE SiP is shown in Figure 1-1. Block Diagram Figure 1-1. CYW20732S BLE SiP Block Diagram Introduction VBAT/VDDIO CYW20732S Antenna Bandpass Filter CYW20732 Bluetooth Low Energy System-on-Chip with ARM Cortex M3-based Microprocessor Core 24 MHz XTAL UART SPI/I2C Infrared ADC GPIOs PWM EEPROM 512 Kb I2C 32.768 kHz Oscillator

(optional) 1.1.4 External reset timing for the CYW20732S is illustrated in Figure 1-2. External Reset Figure 1-2. External Reset Timing Pulsewidth

>20s Crystal warmup delay:

~5ms RESET_N BasebandReset CrystalEnable StartreadingEEPROMand firmwareboot CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 8 Introduction 32.768 kHz Oscillator 1.1.5 The CYW20732S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the out-

put to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold

(~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 1-1. Table 1-1. 32 kHz Crystal Oscillator Characteristics Parameter Symbol Conditions Min. Output frequency Frequency tolerance Start-up time Crystal drive level Crystal series resistance Crystal shunt capacitance Foscout Ftol Tstartup Pdrv Rseries Cshunt Crystal-dependent For crystal selection For crystal selection For crystal selection 0.5 Typ. 32.768 100 Max. 500 70 1.3 Unit kHz ppm s W k pF 9 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Pin Map and Signal Descriptions 1.2 The CYW20732S pin map is shown in Figure 1-3. Figure 1-3. CYW20732S (TOP View) Introduction The signal name, type, and description of each pin in the CYW20732S is listed in Table 1-2. The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU =

weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Table 1-2. Pin Descriptions Pin Name GPIO: P27 PWM1 I/O Type I GND VBAT GND GND GND GND GND GND I GND GND GND GND GND 1 2 3 4 5 6 7 8 Description Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: MOSI (master and slave) for SPI_2 GND Battery supply input. GND GND GND GND GND CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 10 Introduction Table 1-2. Pin Descriptions (continued) Pin Name I/O Type Description 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GND Reserved GND GND GND GND GND GND GND UART_RX UART_TX GND SCL SDA GND GND GPIO: P1 TMC RESET_N GPIO: P0 GND GPIO: P3 GPIO: P2 GND GND GND GND GND GND GND GND I O, PU GND I/O, PU I/O, PU GND GND I I I/O PU I GND I I GND Leave floating GND GND GND GND GND GND GND UART_RX. This pin is pulled low through an internal 10 k resistor. UART_TX GND SCL I/O, PU clock signal for an external I2C device SDA I/O, PU data signal for an external I2C device GND GND Default direction: Input. After POR state: Input floating. This pin is tied to the WP pin of the embedded EEPROM. Requires an external 10K pull-up Test mode control. Pull this pin high to invoke test mode; leave it floating if not used. This pin is connected to GND through an internal 10 k resistor. Active-low system reset with open-drain output Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input Peripheral UART TX (PUART_TX) MOSI (master and slave) for SPI_2 IR_RX 60Hz_main GND Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART CTS (PUART_CTS) SPI_CLK (master and slave) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART RX (PUART_RX) SPI_CS (slave only) for SPI_2 SPI_MOSI (master only) for SPI_2 11 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Table 1-2. Pin Descriptions (continued) Introduction Pin 32 Name GPIO: P4 33 34 GPIO: P8 GPIO: P33 35 GPIO: P32 36 37 38 39 40 GPIO: P25 GPIO: P24 N/C GPIO: P13 PWM3 GPIO: P28 PWM2 GPIO: P14 PWM2 GPIO: P38 I/O Type Description I I I I I I N/C I I I I Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART RX (PUART_RX) MOSI (master and slave) for SPI_2. IR_TX Default direction: Input. After POR state: Input floating. Alternate functions: A/D converter input Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input MOSI (slave only) for SPI_2 Auxiliary clock output (ACLK1) Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input SPI_CS (slave only) for SPI_2. Auxiliary clock output (ACLK0) Peripheral UART TX (PUART_TX) Default direction: Input. After POR state: Input floating. Alternate functions:

MISO (master and slave) for SPI_2 Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions:

SPI_CLK (master and slave) for SPI_2 Peripheral UART TX (PUART_TX) N/C Default Direction: Input After POR State: Input Floating Drain current: 16 mA Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate functions:

A/D converter input LED1 IR_TX Default direction: Input. After POR state: Input floating. Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input MOSI (master and slave) for SPI_2 IR_TX CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 12 Introduction Table 1-2. Pin Descriptions (continued) Pin 41 Name GPIO: P15 42 43a GPIO: P26 PWM0 GPIO: P12 XTALO32K 44b GPIO: P11 XTALI32K GND GND GND GND 45 46 47 48 I/O Type Description I I I O I I GND GND GND GND Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input IR_RX 60 Hz_main Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: SPI_CS (slave only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALO32K Low-power oscillator (LPO) output. Alternate functions:

P12 P26 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALI32K Low-power oscillator (LPO) input. Alternate functions:

P11 P27 GND GND GND GND a. When pin 43 (XTALO32K) is used, ADC/GPIO:P12 is unavailable. P26 may still be available. b. When pin 44 (XTALI32K) is used, ADC/GPIO:P11 is unavailable. P27 may still be available. 13 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Electrical Specifications 1.3 Absolute maximum ratings are defined in Table 1-3. Table 1-3. Absolute Maximum Ratings Parameter Min. Max. Supply power Storage temperature Voltage ripple Power supply (VBAT absolute maximum rating) NA 40 0 1.62 3.63 125 2 3.63 Introduction Unit V C

V Power for the CYW20732S module is provided by the host through the power pins. Table 1-4. Voltage Symbol VBAT Battery voltage Parameter Min. 1.62 Typ. Max. 3.63 Unit V Table 1-5. Current Consumption Operating Mode Receive Transmit Sleep Deep Sleep Condition Receiver and baseband are both operating, 100%

Transmitter and baseband are both operating, 100%

Wake in < 5 ms Wake on interrupt Note: All measurements taken at 25C Nominal 24.0 Maximum 28.0 24.0 55.0 2.0 28.0 60.0 2.5 Unit mA mA A A Based on the current measurements in Table 1-5 , CYW20732S peak power values are:

RX: 101.6 mW TX: 101.6 mW Sleep mode: 217.8 W Deep Sleep mode: 9.1 W CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 14 Introduction RF Specifications 1.4 CYW20732S receiver specifications are defined in Table 1-6. Table 1-6. Receiver Specifications Parameter Frequency range Mode and Conditions RX sensitivity (standard) Maximum input Packets: 200 Payload: PRBS 9 Length: 37 Bytes Dirty Transmitter: off. PER: 30.8%

Note: All measurements taken at 3.0V (default voltage) RF transmitter specifications are defined in Table 1-7. Table 1-7. Transmitter Specifications Min. 2402 Typ. 94 10 Max. 2480 Unit MHz dBm dBm Parameter Min. Typ. Max. Unit Transmitter Frequency rangea Output power adjustment range Output power Output power variation LO Performance Initial carrier frequency tolerance Frequency Drift Frequency drift Drift rate Frequency Deviation Average deviation in payload

(sequence: 00001111) Average deviation in payload

(sequence: 10101010) Channel spacing a. This parameter is taken from the Bluetooth 4.0 specification. 2402 20 225 185 2 2.5 2 2480 4 MHz dBm dBm dB 150 kHz 50 20 275 kHz kHz/50 s kHz kHz MHz 15 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Introduction ADC Specifications 1.5 CYW20732S ADC specifications are defined in Table 1-8. Table 1-8. ADC Specifications Parameter Number of input channels Channel switching rate Input signal range Reference settling time Input resistance Input capacitance Conversion rate Conversion time Resolution Absolute voltage measurement error Current Power Leakage Current Power-up time Integral nonlinearity Differential nonlinearity a. LSBs are expressed at the 10-bit level. Symbol fch Vinp Rinp Cinp Fc Tc R I P Ileakage Tpowerup INL DNL Conditions Charging refsel Effective, single-ended Using onchip ADC firmware driver Iavdd1p2 + Iavdd3p3 T = 25C In the guaranteed performance range In the guaranteed performance range Min. 0 7.5 5.859 5.35 1 1 Typ. 9 500 16 2 1.5 Max. 133.33 3.63 5 187 170.7 1 100 200 1 1 Unit

Kch/s V s k pF kHz s Bits

mA mW nA s LSBa LSB<S upersc ript>a CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 16 Introduction 1.6 Timing and AC Characteristics 1.6.1 SPI interface timing is illustrated in Figure 1-4 and Figure 1-5 and are defined in Table 1-9 . SPI Timing Figure 1-4. SPI TimingModes 0 and 2 SPI_CSN SPI_CLK

(Mode0) SPI_CLK

(Mode2) SPI_MOSI 1 FirstBit 2 3 SecondBit 6 Lastbit 4 5 SPI_MISO NotDriven FirstBit SecondBit Lastbit NotDriven Figure 1-5. SPI TimingModes 1 and 3 SPI_CSN SPI_CLK

(Mode1) SPI_CLK

(Mode3) SPI_MOSI 1 2 3 Invalidbit Firstbit SPI_MISO NotDriven Invalidbit Firstbit 6 4 5 Lastbit Lastbit NotDriven 17 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Introduction Min. 1 SCK 1/2SCK 1/2 SCK SCK Typ. 100 1/2SCK

1/2 SCK 10 SCK Max. 100 Table 1-9. SPI Interface Timing Specifications Reference Characteristics 1 2 3 4 5 6 Time from CSN asserted to first clock edge Master setup time Master hold time Slave setup time Slave hold time Time from last clock edge to CSN deasserted 1.6.2 BSC interface timing is illustrated in Figure 1-6 and is defined in Table 1-10. BSC Interface Timing Figure 1-6. BSC Interface Timing Table 1-10. BSC Interface Timing Specifications Reference 1 2 3 4 5 6 7 8 9 10 Characteristics Min. Max. Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time 650 280 650 280 0 100 280 650 100, 400, 800, 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 18 Introduction 1.6.3 UART timing is illustrated in Figure 1-7 and defined in Table 1-11. UART Timing Figure 1-7. UART Timing Table 1-11. UART Timing Specifications Reference 1 2 3 Characteristics Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min. Max. 24 10 2 Unit Baudout cycles ns Baudout cycles 19 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Introduction 1.7 PCB Design and Manufacturing Recommendations 1.7.1 CYW20732S pad and solder mask opening dimensions are defined in Table 1-12. Pad and Solder Mask Opening Dimensions Table 1-12. Pad and Solder Mask Dimensions Pad Type Pad Dimensions Solder Mask Opening Dimensions Type A Type B Type C 0.6 0.25 0.55 0.3 0.4 0.4 0.7 0.35 0.65 0.4 0.5 0.5 Unit mm PCB Layout Recommendations for Configuration A 1.7.2 The following layout recommendations are referenced to Figure 1-8:

Connect to system ground from side B of the module (pins 1322). An L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer. Antenna efficiency of 3141% can be achieved based on the layout in Figure 1-8 and the dimensions listed below. Follow-

ing these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommenda-

lowing these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommen-

dations may reduce the range of the antenna. D: 4.5 mm (typical) G, H, S: 3 mm (typical) L: 3 mm (minimum) W: 0.4 mm (typical) Route signal traces out of the module from side C (between pins 27 and 30) or side B (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area. Do not route traces from side A or sideD. Figure 1-11. PCB Layout Example, Configuration B Notes:

Side A indicates the side of Pin #1 - Pin #12 of the CYW20732S. Side B indicates the side of Pin #13 - Pin #22 of the CYW20732S. Side C indicates the side of Pin #23 - Pin #34 of the CYW20732S. Side D indicates the side of Pin #35 - Pin #44 of the CYW20732S. 23 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 1.7.4 It is recommended to have a 0.4 mm gap between the chip's upper surface and the plastic housing (Figure 1-12). Common Guidelines for CYW20732S Figure 1-12. Gap Between Chips Upper Surface and Plastic Housing Introduction Arrange the GND plane under the module and connect the GND pins of the module to the GND plane as shown in Figure 1-14. Figure 1-13. Example of Ground Plane Under the Module Note: Do not route the GND plane under the RF pin. If you are unable to reserve such a large GND plane, then use the minimal required area as shown in Figure 1-14. CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 24 Introduction Figure 1-14. Minimum Required Ground Plane PCB Stencil 1.7.5 The recommended PCB stencil is shown in Figure 1-15 (all measurements in mm). Use an unsolder mask to set the module footprint. Figure 1-15. CYW20732S Stencil (Bottom View) 25 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 1.7.6 The recommended solder reflow profile for the CYW20732S is defined in Figure 1-16. Solder Reflow Figure 1-16. Solder Reflow Profile Introduction 245C 217C 200C 150C e r u t a r e p m e T PreHeating:90~120sec. Soldering:60~90sec. Time CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 26 Introduction Packaging and Storage Information 1.8 The CYW20732S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 1-17. The storage temperature range is 40C to +125C. Figure 1-17. CYW20732S ESD/Moisture Packaging The moisture sensitivity label on the CYW20732S shipping bag is shown in Figure 1-18. Figure 1-18. CYW20732S Moisture Sensitivity Label Figure 1-19 shows the location of pin 1 on the CYW20732S relative to its orientation on the tape packaging. 27 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Figure 1-19. CYW20732S Tape and Reel Pin 1 Location Introduction CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 28 Introduction Mechanical Information 1.9 Package dimensions for the CYW20732S are shown in Figure 1-20. Figure 1-20. CYW20732S Package Dimensions Additional CYW20732Spackage dimensions are shown in Figure 1-21. 29 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G Figure 1-21. CYW20732S Pin Dimensions (Bottom View) Introduction CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G 30 Introduction 1.10 Ordering Information Table 1-13. Ordering Information Part Number Package Operating Temperature Humidity CYW20732S 48-pin LGA 40C to +85C 95% max., noncondensing 31 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G PRELIMINARY

The device complies with part 15 of

n n n n

WAP-0737 WAP-0737

the device with the PCB

WAP-0737 the device

PRELIMINARY

7922A-0737 ISED The device

-1.5dBi, ante than -1.5

(3) No SAR evaluation is required since maximum transmitter Pout is below IC threshold

(3) Aucune valuation SAR n'est requise tant donn que la puissance maximale de l'metteur est infrieure au seuil IC.

7922A-0737

device in the specified Revision History Document Revision History Document Title: CYW20732S Bluetooth Low Energy SiP Module Document Number: 002-15222 Revision ECN#

Issue Date Origin of Change Description of Change

10/02/2013 01/15/2014 03/04/2014 05/13/2014 08/22/2014 09/11/2014 03/24/2016

5560143 01/27/2017 UTSV MMP20732S-TRM100-R:

Initial Release MMP20732S-TRM101-R Update document template MMP20732S-TRM102-R Updated:

Table 2: Pin Descriptions. Technical Support (added link to the WICED support community). Section: Electrical Specifications, Table 4: Voltage MMP20732S-TRM103-R Added:

Footnotes for pins 43 and 44 of Table 2: Pin Descriptions PCB Layout Recommendations for Configuration A PCB Layout Recommendations for Configuration B Common Guidelines for CYW20732S MMP20732S-TRM104-R Updated:

Table 2: Pin Descriptions, (pins 33 and 38). MMP20732S-TRM105-R Updated:

Table 2: Pin Descriptions, pin 37 alternate functions. PCB Layout Recommendations for Configuration A. PCB Layout Recommendations for Configuration B. Removed:

Appendix A: Acronyms and Abbreviations. MMP20732S-TRM106-R Updated:

Table 5, Current Consumption Updated to Cypress Template. 33 CYW20732S Bluetooth Low Energy SiP Module, Doc. # 002-15222 Rev. *G

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User Manual CYW20736S - 0514

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1.62 MiB

CYW20736S Bluetooth Low Energy System-in-Package

(SiP) Module Doc. # 002-15315 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): +1.408.943.2600 www.cypress.com Copyrights Copyrights Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or refer-

POSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without fur-

tive owners. CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 2 Preface This document provides descriptions of the interfaces, pin assignments, and specifications of CYW20736S Bluetooth Low Energy (BLE) System-in-Package (SiP) module. It is intended for designers who are responsible for adding the CYW20736S module to wireless input devices including heart-rate monitors, blood pressure monitors, proximity sensors, temperature sensors, and battery monitors.. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this con-

version, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 2-1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM20736 BCM20736S CYW20736 CYW20736S Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary. Document Conventions The following conventions may be used in this document:

Convention Bold Monospace

< >

[ ]

Description User input and actions: for example, type exit, click OK, press Alt+C Code: #include <iostream>

HTML: <td rowspan = 3>

Command line commands and parameters: wl [-l] <command>

Placeholders for required elements: enter your <username> or wl <command>

Indicates optional command-line parameters: wl [-l]

Indicates bit and byte ranges (inclusive): [0:3] or [7:0]

tion, and software updates. Customers can acquire technical documentation and software from the Cypress Support Commu-

nity website (http://community.cypress.com/). 3 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Preface CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 4 Contents 1. 1.2 1.3 1.4 1.5 1.6 7 Introduction 1.1 Overview...................................................................................................................................7 1.1.1 Features........................................................................................................................7 1.1.2 Application Profiles........................................................................................................7 1.1.3 Block Diagram...............................................................................................................8 1.1.4 External Reset...............................................................................................................8 1.1.5 32.768 kHz Oscillator....................................................................................................9 Pin Map and Signal Descriptions............................................................................................10 Electrical Specifications ..........................................................................................................14 RF Specifications....................................................................................................................15 ADC Specifications .................................................................................................................16 Timing and AC Characteristics ...............................................................................................17 1.6.1 SPI Timing...................................................................................................................17 1.6.2 BSC Interface Timing ..................................................................................................18 1.6.3 UART Timing...............................................................................................................19 PCB Design and Manufacturing Recommendations ..............................................................20 1.7.1 Pad and Solder Mask Opening Dimensions ...............................................................20 1.7.2 PCB Layout Recommendations..................................................................................20 1.7.3 PCB Stencil.................................................................................................................21 1.7.4 Solder Reflow..............................................................................................................22 1.8 Packaging and Storage Information .......................................................................................23 1.9 Mechanical Information...........................................................................................................25 1.10 Ordering Information...............................................................................................................26 27 1.7 Revision History 5 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Contents CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 6 1. Introduction Overview 1.1 The CYW20736S is a compact, highly integrated Bluetooth low energy (BLE) system-in-package (SiP) module. The CYW20736S SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of exter-

nal components is needed to create a standalone BLE device. The CYW20736S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into the module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20736S includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load cycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20736S well suited for virtually any Bluetooth Smart application. Features 1.1.1 ARM Cortex-M3 microcontroller unit (MCU) Embedded 512 Kb EEPROM Broadcom Serial Control (BSC), SPI, and UART interfaces FCC and CE compliant RoHS compliant, certified lead- and halogen-free Moisture Sensitivity Level (MSL) 3 compliant 6.5 mm 6.5 mm 1.2 mm Land Grid Array (LGA) 48-pin package Application Profiles 1.1.2 The following profiles are supported in CYW20736S ROM:

Battery status Blood pressure monitor Find me Heart rate monitor Proximity Thermometer Weight scale Time Blood glucose monitor Additional profiles that can be supported in CYW20736S RAM include:

Blood glucose monitor Temperature alarm Location Other custom profiles 7 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 1.1.3 A block diagram of the CYW20736S BLE SiP is shown in Figure 1-1. Block Diagram Figure 1-1. CYW20736S BLE SiP Block Diagram Introduction VBAT/VDDIO CYW20736S Antenna Bandpass Filter CYW20736 Bluetooth Low Energy System-on-Chip with ARM Cortex M3-based Microprocessor Core 24 MHz XTAL UART SPI/I2C Infrared ADC GPIOs PWM EEPROM 512 Kb I2C 32.768 kHz Oscillator

(optional) 1.1.4 External reset timing for the CYW20736S is illustrated in Figure 1-2. External Reset Figure 1-2. External Reset Timing Pulsewidth

>20s Crystal warmup delay:

~5ms RESET_N BasebandReset CrystalEnable StartreadingEEPROMand firmwareboot CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 8 Introduction 32.768 kHz Oscillator 1.1.5 The CYW20736S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the out-

put to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold

(~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 1-1. Table 1-1. 32 kHz Crystal Oscillator Characteristics Parameter Symbol Conditions Min. Output frequency Frequency tolerance Start-up time Crystal drive level Crystal series resistance Crystal shunt capacitance Foscout Ftol Tstartup Pdrv Rseries Cshunt Crystal-dependent For crystal selection For crystal selection For crystal selection 0.5 Typ. 32.768 100 Max. 500 70 1.3 Unit kHz ppm s W k pF 9 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Pin Map and Signal Descriptions 1.2 The CYW20736S pin map is shown in Figure 1-3. Figure 1-3. CYW20736S (TOP View) Introduction The signal name, type, and description of each pin in the CYW20736S is listed in Table 1-2 . The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU =

weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 10 Introduction Table 1-2. Pin Descriptions Pin Name I/O Type Description GPIO: P27 PWM1 I GND VBAT GND GND GND GND GND GND GND I GND GND GND GND GND GND Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: MOSI (master and slave) for SPI_2 GND Battery supply input. GND GND GND GND GND GND Reserved Leave floating GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND UART_RX I UART_RX. This pin is pulled low through an internal 10 k resistor. UART_TX GND SCL SDA GND GND O, PU GND I/O, PU I/O, PU GND GND GPIO: P1 TMC I I RESET_N I/O PU UART_TX GND SCL I/O, PU clock signal for an external I2C device SDA I/O, PU data signal for an external I2C device GND GND Default direction: Input. After POR state: Input floating. This pin is tied to the WP pin of the embedded EEPROM. Requires an external 10K pull-up Test mode control. Pull this pin high to invoke test mode; leave it floating if not used. This pin is connected to GND through an internal 10 k resistor. Active-low system reset with open-drain output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 11 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Table 1-2. Pin Descriptions (Cont.) Pin 28 Name GPIO: P0 I/O Type I 29 30 31 GND GND GPIO: P3 GPIO: P2 I I I I I I I I 32 GPIO: P4 33 34 GPIO: P8 GPIO: P33 35 GPIO: P32 36 37 GPIO: P25 GPIO: P24 Introduction Description Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input Peripheral UART TX (PUART_TX) MOSI (master and slave) for SPI_2 IR_RX 60Hz_main GND Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART CTS (PUART_CTS) SPI_CLK (master and slave) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART RX (PUART_RX) SPI_CS (slave only) for SPI_2 SPI_MOSI (master only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART RX (PUART_RX) MOSI (master and slave) for SPI_2. IR_TX Default direction: Input. After POR state: Input floating. Alternate functions: A/D converter input. Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input MOSI (slave only) for SPI_2 Auxiliary clock output (ACLK1) Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input SPI_CS (slave only) for SPI_2. Auxiliary clock output (ACLK0) Peripheral UART TX (PUART_TX) Default direction: Input. After POR state: Input floating. Alternate functions:

MISO (master and slave) for SPI_2 Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions:

SPI_CLK (master and slave) for SPI_2 Peripheral UART TX (PUART_TX) CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 12 Introduction Table 1-2. Pin Descriptions (Cont.) 38 39 40 Pin Name NC GPIO: P13 PWM3 GPIO: P28 PWM2 GPIO: P14 PWM2 GPIO: P38 41 GPIO: P15 42 43 GPIO: P26 PWM0 GPIO: P12 I I I I I I I XTALO32K O 44 GPIO: P11 XTALI32K GND GND GND GND 45 46 47 48 I I GND GND GND GND I/O Type NC No Connection (N/C). Description Default Direction: Input After POR State: Input Floating Drain current: 16 mA Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate functions:

A/D converter input MOSI (master and slave) for SPI_2 IR_TX Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALO32K Low-power oscillator (LPO) output. Alternate functions:

P12 P26 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALI32K Low-power oscillator (LPO) input. Alternate functions:

P11 P27 GND GND GND GND 13 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Electrical Specifications 1.3 Absolute maximum ratings are defined in Table 1-3. Table 1-3. Absolute Maximum Ratings Parameter Min. Max. Supply power Storage temperature Voltage ripple Power supply (VBAT absolute maximum rating) NA 40 0 1.62 3.63 125 2 3.63 Introduction Unit V C

V Power for the CYW20736S module is provided by the host through the power pins. Table 1-4. Voltage Symbol VBAT Battery voltage Parameter Min. 1.62 Typ. Max. 3.63 Unit V Note: With an optional DC-DC (90% efficient) converter at 3V, the current between the battery terminals (shown in Table 1-5) are about 50% lower than their nominal values at the default operating voltage (1.62V). Table 1-5. Current Consumption Operating Mode Receive Transmit Sleep Deep Sleep Condition Receiver and baseband are both operating, 100%

Transmitter and baseband are both operating, 100%

Wake in < 5 ms Wake on interrupt Note: All measurements taken at 25C Nominal 9.8 Maximum 10.0 9.1 12.0 0.65 9.3 19.2 Unit mA mA A A Based on the current measurements in Table 1-5 , CYW20736S peak power values are:

RX: 39.6 mW TX: 37.8 mW Sleep mode: 36 W Deep Sleep mode: 2.4 W CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 14 Introduction RF Specifications 1.4 CYW20736S receiver specifications are defined in Table 1-6. Table 1-6. Receiver Specifications Parameter Frequency range Mode and Conditions RX sensitivity (standard) Maximum input Packets: 200 Payload: PRBS 9 Length: 37 Bytes Dirty Transmitter: off. PER: 30.8%

(sequence: 00001111) Average deviation in payload

(sequence: 10101010) Channel spacing a. This parameter is taken from the Bluetooth 4.0 specification. 2402 20 225 185 2 2.5 2 2480 4 MHz dBm dBm dB 150 kHz 50 20 275 kHz kHz/50 s kHz kHz MHz 15 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Introduction ADC Specifications 1.5 CYW20736S ADC specifications are defined in Table 1-8. Table 1-8. ADC Specifications Parameter Number of input channels Channel switching rate Input signal range Reference settling time Input resistance Input capacitance Conversion rate Conversion time Resolution Absolute voltage measurement error Current Power Leakage Current Power-up time Integral nonlinearity Differential nonlinearity a. LSBs are expressed at the 10-bit level. Symbol fch Vinp Rinp Cinp Fc Tc R I P Ileakage Tpowerup INL DNL Conditions Charging refsel Effective, single-ended Using onchip ADC firmware driver Iavdd1p2 + Iavdd3p3 T = 25C In the guaranteed performance range In the guaranteed performance range Min. 0 7.5 5.859 5.35 1 1 Typ. 9 500 16 2 1.5 Max. 133.33 3.63 5 187 170.7 1 100 200 1 1 Unit

Kch/s V s k pF kHz s Bits

mA mW nA s LSBa LSBa CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 16 Introduction 1.6 Timing and AC Characteristics 1.6.1 SPI interface timing is illustrated in Figure 1-4 and Figure 1-5 and defined in Table 1-9 . SPI Timing Figure 1-4. SPI TimingModes 0 and 2 SPI_CSN SPI_CLK

(Mode0) SPI_CLK

(Mode2) SPI_MOSI 1 FirstBit 2 3 SecondBit 6 Lastbit 4 5 SPI_MISO NotDriven FirstBit SecondBit Lastbit NotDriven Figure 1-5. SPI TimingModes 1 and 3 SPI_CSN SPI_CLK

(Mode1) SPI_CLK

(Mode3) SPI_MOSI 1 2 3 Invalidbit Firstbit SPI_MISO NotDriven Invalidbit Firstbit 6 4 5 Lastbit Lastbit NotDriven 17 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Introduction Min. 1 SCK 1/2SCK 1/2 SCK SCK Typ. 100 1/2SCK

1/2 SCK 10 SCK Max. 100 Table 1-9. SPI Interface Timing Specifications Reference Characteristics 1 2 3 4 5 6 Time from CSN asserted to first clock edge Master setup time Master hold time Slave setup time Slave hold time Time from last clock edge to CSN deasserted 1.6.2 BSC interface timing is illustrated in Figure 1-6 and is defined in Table 1-10. BSC Interface Timing Figure 1-6. BSC Interface Timing Table 1-10. BSC Interface Timing Specifications Reference 1 2 3 4 5 6 7 8 9 10 Characteristics Min. Max. Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time 650 280 650 280 0 100 280 650 100, 400, 800, 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 18 Introduction 1.6.3 UART timing is illustrated in Figure 1-7 and defined in Table 1-11. UART Timing Figure 1-7. UART Timing Table 1-11. UART Timing Specifications Reference 1 2 3 Characteristics Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min. Max. 24 10 2 Unit Baudout cycles ns Baudout cycles 19 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Introduction 1.7 PCB Design and Manufacturing Recommendations 1.7.1 CYW20736S pad and solder mask opening dimensions are defined in Table 1-12. Pad and Solder Mask Opening Dimensions Table 1-12. Pad and Solder Mask Dimensions Pad Type Pad Dimensions Solder Mask Opening Dimensions Type A Type B Type C 0.6 0.25 0.55 0.3 0.4 0.4 0.7 0.35 0.65 0.4 0.5 0.5 Unit mm PCB Layout Recommendations 1.7.2 The following layout recommendations are referenced to Figure 1-8. Connect to system ground from side D of the module (pins 1322). The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes. An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer. Antenna efficiency of 3141% can be achieved based on the layout in Figure 1-8 and the dimensions listed below. Follow-

ing these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommenda-

tions may reduce the range of the antenna. D: 4.5 mm (typical) G, H, S: 3 mm (typical) L: 3 mm (minimum) W: 0.4 mm (typical) Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area. Do not route traces from side A or side B. CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 20 Introduction Figure 1-8. PCB Layout Example PCB Stencil 1.7.3 The recommended PCB stencil is shown in Figure 1-9 (all measurements in mm). Use an unsolder mask to set the module footprint. Figure 1-9. CYW20736S Stencil (Bottom View) 21 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 1.7.4 The recommended solder reflow profile for the CYW20736S is defined in Figure 1-10. Solder Reflow Figure 1-10. Solder Reflow Profile Introduction 245C 217C 200C 150C e r u t a r e p m e T PreHeating:90~120sec. Soldering:60~90sec. Time CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 22 Introduction Packaging and Storage Information 1.8 The CYW20736S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 1-11. The storage temperature range is 40C to +125C. Figure 1-11. CYW20736S ESD/Moisture Packaging The moisture sensitivity label on the CYW20736S shipping bag is shown in Figure 1-12. Figure 1-12. CYW20736S Moisture Sensitivity Label 23 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Figure 1-13 shows the location of pin 1 on the CYW20736S relative to its orientation on the tape packaging. Figure 1-13. CYW20736S Tape and Reel Pin 1 Location Introduction CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 24 Introduction Mechanical Information 1.9 Package dimensions for the CYW20736S are shown in Figure 1-14. Figure 1-14. CYW20736S Package Dimensions Additional CYW20736S package dimensions are shown in Figure 1-15. 25 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C Figure 1-15. CYW20736S Pin Dimensions (Bottom View) Introduction 1.10 Ordering Information Table 1-13. Ordering Information Part Number Package Operating Temperature Humidity CYW20736S 48-pin LGA 40C to +85C 95% max., noncondensing CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C 26 PRELIMINARY

The device complies with part 15 of

n n n n

WAP-0737 WAP-0737

the device with the PCB

WAP-0737 the device

PRELIMINARY

7922A-0737 ISED The device

-1.5dBi, ante than -1.5

(3) No SAR evaluation is required since maximum transmitter Pout is below IC threshold

(3) Aucune valuation SAR n'est requise tant donn que la puissance maximale de l'metteur est infrieure au seuil IC.

7922A-0737

device in the specified Revision History Document Revision History Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module Document Number: 002-15315 Revision ECN#

Issue Date Origin of Change

04/18/2014 07/15/2014 09/11/2014

5560317 01/27/2017 UTSV Description of Change 20736S-TRM100-R:

Initial Release 20736S-TRM101-R Updated:

Pin 33 and pin 38 descriptions; see Table 2: Pin Descriptions. 20736S-TRM102-R Updated:

Removed:

Appendix A: Acronyms and Abbreviations. Updated to Cypress Template. Table 2, Pin Descriptions: Pin 37. 27 CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module, Doc. # 002-15315 Rev. *C

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CYW20737S Bluetooth Low Energy System-in-Package (SiP) Module The CYW20737S is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The CYW20737S SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of external components is needed to create a standalone BLE device. The CYW20737S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into the module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20737S includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load cycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20737S well suited for virtually any Bluetooth Smart application. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number CYW20737S BCM20737S Features ARM Cortex-M3 microcontroller unit (MCU) Embedded 512 Kb EEPROM Broadcom Serial Control (BSC), SPI, and UART interfaces FCC and CE compliant RoHS compliant, certified lead- and halogen-free Moisture Sensitivity Level (MSL) 3 compliant 6.5 mm 6.5 mm 1.2 mm Land Grid Array (LGA) 48-pin package Applications Profiles supported in ROM:

Battery status Blood pressure monitor Find me Heart rate monitor Proximity Thermometer Weight scale Time Blood glucose monitor Support for RSA security library Support for LE Audio Support for pairing using NFC tags Additional profiles supported in RAM:

Blood glucose monitor Temperature alarm Location Other custom profiles Cypress Semiconductor Corporation Document Number: 002-14888 Rev. *C 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised April 21, 2017 CYW20737S Figure 1. CYW20737S BLE SiP Block Diagram VBAT/VDDIO BCM20737S CYW20737S BCM20737S CYW20737S Bluetooth Low Energy System-on-Chip with ARM Cortex M3-based Microprocessor Core Antenna Bandpass Filter 24 MHz XTAL UART SPI/I2C Infrared ADC GPIOs PWM EEPROM 512 Kb I2C 32.768 kHz Oscillator

(optional) IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/). Document Number: 002-14888 Rev. *C Page 2 of 24 CYW20737S Contents 1. Functional Description .................................................4 1.1 External Reset .......................................................4 1.2 32.768 kHz Oscillator ............................................4 2. Pin Map and Signal Descriptions ................................5 3. Electrical Specifications ............................................10 4. RF Specifications .......................................................11 5. ADC Specifications ....................................................12 6. Timing and AC Characteristics .................................13 6.1 SPI Timing ...........................................................13 6.2 BSC Interface Timing ..........................................14 6.3 UART Timing ....................................................... 15 7. PCB Design and Manufacturing Recommendations 16 7.1 Pad and Solder Mask Opening Dimensions ........ 16 7.2 PCB Layout Recommendations .......................... 16 7.3 PCB Stencil ............................................................... 17 7.4 Solder Reflow ...................................................... 17 8. Packaging and Storage Information ......................... 18 9. Mechanical Information ............................................. 20 10. Ordering Information ................................................ 22 Document History .......................................................... 23 Document Number: 002-14888 Rev. *C Page 3 of 24 CYW20737S 1. Functional Description 1.1 External Reset External reset timing for the CYW20737S is illustrated in Figure 2. Figure 2. External Reset Timing Pulsewidth

>20s Crystal warmup delay:

~5ms RESET_N BasebandReset CrystalEnable StartreadingEEPROMand firmwareboot 1.2 32.768 kHz Oscillator The CYW20737S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 2. Table 2. 32 kHz Crystal Oscillator Characteristics Parameter Output frequency Frequency tolerance Start-up time Crystal drive level Crystal series resistance Crystal shunt capacitance Symbol Foscout Ftol Tstartup Pdrv Rseries Cshunt Conditions Crystal-dependent For crystal selection For crystal selection For crystal selection Min. 0.5 Typ. 32.768 100 Max. 500 70 1.3 Unit kHz ppm s W k pF Document Number: 002-14888 Rev. *C Page 4 of 24 2. Pin Map and Signal Descriptions The CYW20737S pin map is shown in Figure 3. Figure 3. CYW20737S (TOP View) CYW20737S The signal name, type, and description of each pin in the CYW20737S is listed in Table 3 on page 6. The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Document Number: 002-14888 Rev. *C Page 5 of 24 CYW20737S Table 3. Pin Descriptions Pin Name I/O Type Description GPIO: P27 PWM1 GND VBAT GND GND GND GND GND GND Reserved GND GND GND GND GND GND GND UART_RX UART_TX GND SCL SDA GND GND GPIO: P1 TMC I GND I GND GND GND GND GND GND GND GND GND GND GND GND GND I O, PU GND I/O, PU I/O, PU GND GND I I RESET_N I/O PU Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: MOSI (master and slave) for SPI_2 GND Battery supply input. GND GND GND GND GND GND Leave floating GND GND GND GND GND GND GND UART_RX. This pin is pulled low through an internal 10 k resistor. UART_TX GND SCL I/O, PU clock signal for an external I2C device SDA I/O, PU data signal for an external I2C device GND GND Default direction: Input. After POR state: Input floating. This pin is tied to the WP pin of the embedded EEPROM. Requires an external 10K pull-up Test mode control. Pull this pin high to invoke test mode; leave it floating if not used. This pin is connected to GND through an internal 10 k resistor. Active-low system reset with open-drain output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Document Number: 002-14888 Rev. *C Page 6 of 24 CYW20737S Table 3. Pin Descriptions (Cont.) Pin Name I/O Type Description 28 GPIO: P0 I Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input Peripheral UART TX (PUART_TX) MOSI (master and slave) for SPI_2 IR_RX 60Hz_main GND GND GND 29 30 GPIO: P3 I I I I I Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART CTS (PUART_CTS) SPI_CLK (master and slave) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

Peripheral UART RX (PUART_RX) SPI_CS (slave only) for SPI_2 SPI_MOSI (master only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input MOSI (slave only) for SPI_2 Auxiliary clock output (ACLK1) Peripheral UART RX (PUART_RX) 31 GPIO: P2 32 GPIO: P4 33 GPIO: P8 34 GPIO: P33 Document Number: 002-14888 Rev. *C Page 7 of 24 Table 3. Pin Descriptions (Cont.) Pin Name I/O Type Description CYW20737S NC NC 35 GPIO: P32 36 GPIO: P25 37 38 39 40 GPIO: P24 GPIO: P13 PWM3 GPIO: P28 PWM2 GPIO: P14 PWM2 GPIO: P38 41 GPIO: P15 I I I I I I I I Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input SPI_CS (slave only) for SPI_2. Auxiliary clock output (ACLK0) Peripheral UART TX (PUART_TX) Default direction: Input. After POR state: Input floating. Alternate functions:

MISO (master and slave) for SPI_2 Peripheral UART RX (PUART_RX) Default direction: Input. After POR state: Input floating. Alternate functions:

SPI_CLK (master and slave) for SPI_2 Peripheral UART TX (PUART_TX) No Connection (N/C). Default Direction: Input After POR State: Input Floating Drain current: 16 mA Alternate function: A/D converter input Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate functions:

A/D converter input MOSI (master and slave) for SPI_2 IR_TX Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input IR_RX 60 Hz_main Document Number: 002-14888 Rev. *C Page 8 of 24 CYW20737S Table 3. Pin Descriptions (Cont.) Pin 42 43 44 45 46 47 48 Name I/O Type Description GPIO: P26 PWM0 GPIO: P12 I I XTALO32K O GPIO: P11 XTALI32K GND GND GND GND I I GND GND GND GND Default direction: Input. After POR state: Input floating. Drain current: 16 mA Alternate function: SPI_CS (slave only) for SPI_2 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALO32K Low-power oscillator (LPO) output. Alternate functions:

P12 P26 Default direction: Input. After POR state: Input floating. Alternate functions:

A/D converter input XTALI32K Low-power oscillator (LPO) input. Alternate functions:

P11 P27 GND GND GND GND Document Number: 002-14888 Rev. *C Page 9 of 24 3. Electrical Specifications Absolute maximum ratings are defined in Table 4. Table 4. Absolute Maximum Ratings Parameter Supply power Storage temperature Voltage ripple Power supply (VBAT absolute maximum rating) CYW20737S Min. NA 40 0 1.62 Max. 3.63 125 2 3.63 Unit V C

V Power for the CYW20737S module is provided by the host through the power pins. Table 5. Voltage Symbol VBAT Battery voltage Table 6. Current Consumption Parameter Min. 1.62 Typ. Max. 3.63 Unit V Operating Mode Condition Nominal Maximum Receive Transmit Sleep Receiver and baseband are both operating, 100%

Transmitter and baseband are both operating, 100%

Wake in < 5 ms Deep Sleep Wake on interrupt Note: All measurements taken at 25C 24.0 24.0 55.0 2.0 28.0 28.0 60.0 2.5 Unit mA mA A A Based on the current measurements in Table 6 on page 10, CYW20737S peak power values are:

RX: 101.6 mW TX: 101.6 mW Sleep mode: 217.8 W Deep Sleep mode: 9.1 W Document Number: 002-14888 Rev. *C Page 10 of 24 4. RF Specifications CYW20737S receiver specifications are defined in Table 7. Table 7. Receiver Specifications Parameter Frequency range RX sensitivity (standard) Mode and Conditions Packets: 200 Payload: PRBS 9 Length: 37 Bytes Dirty Transmitter: off. PER: 30.8%

Maximum input Note: All measurements taken at 3.0V (default voltage) RF transmitter specifications are defined in Table 8. Table 8. Transmitter Specifications Parameter Transmitter LO Performance Frequency Drift Frequency Deviation Frequency rangea Output power adjustment range Output power Output power variation Initial carrier frequency tolerance Frequency drift Drift rate Average deviation in payload

(sequence: 00001111) Average deviation in payload

(sequence: 10101010) Channel spacing a. This parameter is taken from the Bluetooth 4.0 specification. CYW20737S Min. 2402 Typ. 94 10 Max. 2480 Unit MHz dBm dBm Min. 2402 20 225 185 Typ. 2 2.5 2 Max. 2480 4 150 50 20 275 Unit MHz dBm dBm dB kHz kHz kHz/50 s kHz kHz MHz Document Number: 002-14888 Rev. *C Page 11 of 24 5. ADC Specifications CYW20737S ADC specifications are defined in Table 9. Table 9. ADC Specifications Parameter Symbol Conditions Min. Typ. Number of input channels Channel switching rate Input signal range Reference settling time Input resistance Input capacitance Conversion rate Conversion time Resolution Absolute voltage measurement error Current Power Leakage Current Power-up time Integral nonlinearity Differential nonlinearity a. LSBs are expressed at the 10-bit level. fch Vinp Rinp Cinp Fc Tc R I P Ileakage Tpowerup INL DNL Charging refsel Effective, single-ended Using onchip ADC firmware driver Iavdd1p2 + Iavdd3p3 T = 25C In the guaranteed performance range In the guaranteed performance range 0 7.5 5.859 5.35 1 1 9 500 16 2 1.5 CYW20737S Max. 133.33 3.63 5 187 170.7 1 100 200 1 1 Unit

Kch/s V s k pF kHz s Bits

mA mW nA s LSBa LSBa Document Number: 002-14888 Rev. *C Page 12 of 24 6. Timing and AC Characteristics 6.1 SPI Timing SPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14. Figure 4. SPI TimingModes 0 and 2 CYW20737S 6 SPI_CSN SPI_CLK

(Mode0) SPI_CLK

(Mode2) SPI_MOSI 1 FirstBit 2 3 SecondBit Lastbit 4 5 SPI_MISO NotDriven FirstBit SecondBit Lastbit NotDriven Figure 5. SPI TimingModes 1 and 3 SPI_CSN SPI_CLK

(Mode1) SPI_CLK

(Mode3) SPI_MOSI 1 2 3 Invalidbit Firstbit SPI_MISO NotDriven Invalidbit Firstbit 6 4 5 Lastbit Lastbit NotDriven Document Number: 002-14888 Rev. *C Page 13 of 24 Table 10. SPI Interface Timing Specifications Reference Characteristics 1 2 3 4 5 6 Time from CSN asserted to first clock edge Master setup time Master hold time Slave setup time Slave hold time Time from last clock edge to CSN deasserted 6.2 BSC Interface Timing BSC interface timing is illustrated in Figure 6 and is defined in Table 11. Figure 6. BSC Interface Timing CYW20737S Min. 1 SCK 1/2SCK 1/2 SCK SCK Typ. 100 1/2SCK

1/2 SCK 10 SCK Max. 100 Table 11. BSC Interface Timing Specifications Reference Characteristics 1 2 3 4 5 6 7 8 9 10 Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Min. 650 280 650 280 0 100 280 650 Max. 100, 400, 800, 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns Document Number: 002-14888 Rev. *C Page 14 of 24 6.3 UART Timing UART timing is illustrated in Figure 7 and defined in Table 12. Figure 7. UART Timing CYW20737S Table 12. UART Timing Specifications Reference Characteristics 1 2 3 Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min. Max. 24 10 2 Unit Baudout cycles ns Baudout cycles Document Number: 002-14888 Rev. *C Page 15 of 24 CYW20737S 7. PCB Design and Manufacturing Recommendations 7.1 Pad and Solder Mask Opening Dimensions CYW20737S pad and solder mask opening dimensions are defined in Table 13. Table 13. Pad and Solder Mask Dimensions Pad Type Type A Type B Type C Pad Dimensions Solder Mask Opening Dimensions 0.6 0.25 0.55 0.3 0.4 0.4 0.7 0.35 0.65 0.4 0.5 0.5 Unit mm 7.2 PCB Layout Recommendations The following layout recommendations are referenced to Figure 8 on page 16. Connect to system ground from side D of the module (pins 1322). The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes. An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer. Antenna efficiency of 3141% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below. Following these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations may reduce the range of the antenna. D: 4.5 mm (typical) G, H, S: 3 mm (typical) L: 3 mm (minimum) W: 0.4 mm (typical) Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area. Do not route traces from side A or side B. Figure 8. PCB Layout Example Document Number: 002-14888 Rev. *C Page 16 of 24 7.3 PCB Stencil The recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint. Figure 9. CYW20737S Stencil (Bottom View) CYW20737S 7.4 Solder Reflow The recommended solder reflow profile for the CYW20737S is defined in Figure 10. Figure 10. Solder Reflow Profile 245C 217C 200C 150C e r u t a r e p m e T PreHeating:90~120sec. Soldering:60~90sec. Ti Document Number: 002-14888 Rev. *C Page 17 of 24 8. Packaging and Storage Information The CYW20737S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 11. The storage temperature range is 40C to +125C. Figure 11. CYW20737S ESD/Moisture Packaging CYW20737S The moisture sensitivity label on the CYW20737S shipping bag is shown in Figure 12 on page 19. Document Number: 002-14888 Rev. *C Page 18 of 24 Figure 12. CYW20737S Moisture Sensitivity Label CYW20737S Figure 13 shows the location of pin 1 on the CYW20737S relative to its orientation on the tape packaging. Figure 13. CYW20737S Tape and Reel Pin 1 Location Document Number: 002-14888 Rev. *C Page 19 of 24 9. Mechanical Information Package dimensions for the CYW20737S are shown in Figure 14. Figure 14. CYW20737S Package Dimensions CYW20737S Additional CYW20737S package dimensions are shown in Figure 15 on page 21. Document Number: 002-14888 Rev. *C Page 20 of 24 Figure 15. CYW20737S Pin Dimensions (Bottom View) CYW20737S Document Number: 002-14888 Rev. *C Page 21 of 24 10. Ordering Information Table 14. Ordering Information Part Number CYW20737S Package 48-pin LGA Operating Temperature Humidity 40C to +85C 95% max., noncondensing CYW20737S Document Number: 002-14888 Rev. *C Page 22 of 24 PRELIMINARY

The device complies with part 15 of

n n n n

WAP-0737 WAP-0737

the device with the PCB

WAP-0737 the device

PRELIMINARY

7922A-0737 ISED The device

-1.5dBi, ante than -1.5

(3) No SAR evaluation is required since maximum transmitter Pout is below IC threshold

(3) Aucune valuation SAR n'est requise tant donn que la puissance maximale de l'metteur est infrieure au seuil IC.

7922A-0737

device in the specified CYW20737S Document History Document Title: CYW20737S Bluetooth Low Energy System-in-Package (SiP) Module Document Number: 002-14888 Revision Submission ECN Orig. of Change Date Description of Change

*C 09/26/2014 UTSV 11/06/2015 5444054 5688156 UTSV 09/23/2016 AESATMP7 04/21/2017 20737S-DS100-R:

Initial release 20737S-DS101-R:

Updated Updated to Cypress Template Updated Cypress Logo and Copyright. Table 5 on page 14 Document Number: 002-14888 Rev. *C Page 23 of 24 CYW20737S Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoCSolutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IoT Forums | Projects | Video | Blogs |

Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless 24 Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (Cypress). This document, including any software or firmware included or referenced in this document (Software), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (Unintended Uses). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-14888 Rev. *C Revised April 21, 2017 Page 24 of 24

		frequency	equipment class	purpose
1	2018-05-14	2402 ~ 2480	DTS - Digital Transmission System	Original Equipment

Application Forms

app s	Applicant Information
1	Effective	2018-05-14
1	Applicant's complete, legal business name	Cypress Semiconductor
1	FCC Registration Number (FRN)	0017759150
1	Physical Address	198 Champion Court
1		San Jose, California 95134
1		United States

app s	TCB Information
1	TCB Application Email Address	a******@dekra.com
1	TCB Scope	A4: UNII devices & low power transmitters using spread spectrum techniques

app s	FCC ID
1	Grantee Code	WAP
1	Equipment Product Code	0737

app s	Person at the applicant's address to receive grant or for contact
1	Name	D**** S****
1	Title	Sr. Business Unit Director
1	Telephone Number	408-5********
1	Fax Number	408-5********
1	E-mail	d******@cypress.com

app s	Technical Contact
		n/a

app s	Non Technical Contact
		n/a

app s	Confidentiality (long or short term)
1	Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?:	Yes
1	Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?:	No
	if no date is supplied, the release date will be set to 45 calendar days past the date of grant.

app s	Cognitive Radio & Software Defined Radio, Class, etc
1	Is this application for software defined/cognitive radio authorization?	No
1	Equipment Class	DTS - Digital Transmission System
1	Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant)	This product is a Bluetooth wireless EZ-BT WICED SIP Module
1	Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application?	No
1	Modular Equipment Type	Limited Single Modular Approval
1	Purpose / Application is for	Original Equipment
1	Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization?	No
1	Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization?	No
1	Grant Comments	Ouput power is conducted. Single Limited Modular approval limited to the hosts: CYW20732S, CYW20736S and CYW20737S This device is approved for mobile use with respect to RF exposure compliance. Multi-transmitter, supporting simultaneous transmission configurations, have not been evaluated and shall be evaluated according to KDB Publication 447498 and §2.947(f), §15.31(h) and §15.31(k) composite system and §2.1 end product terms and concepts. Compliance of this device in all final product configurations is the responsibility of the Grantee. Installation of this device into specific final products may require the submission of a Class II permissive change application containing data pertinent to RF Exposure, emissions and host/module authentication, or new application if appropriate.
1	Is there an equipment authorization waiver associated with this application?	No
1	If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded?	No

app s	Test Firm Name and Contact Information
1	Firm Name	DEKRA Testing and Certification (Suzhou) Co., Ltd.
1	Name	J****** X****
1	Telephone Number	86 51********
1	E-mail	j******@dekra.com

Equipment Specifications
	Line	Rule Parts	Grant Notes	Lower Frequency	Upper Frequency	Power Output	Tolerance	Emission Designator	Microprocessor Number
1	1	15C		2402.00000000	2480.00000000	0.0022000

some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details

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