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User Guide | Users Manual | 1.16 MiB | March 12 2018 | |||
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User Manual | Users Manual | 1.90 MiB | December 07 2017 | |||
1 2 3 4 | Block diagram | Block Diagram | December 03 2018 | confidential | ||||
1 2 3 4 | External Photos | March 12 2018 | ||||||
1 2 3 4 | Cover Letter(s) | March 12 2018 | ||||||
1 2 3 4 | Cover Letter(s) | March 12 2018 | ||||||
1 2 3 4 | Internal Photos | March 12 2018 | ||||||
1 2 3 4 | Cover Letter(s) | March 12 2018 | ||||||
1 2 3 4 | Operation Description | Operational Description | December 03 2018 | confidential | ||||
1 2 3 4 | Schematic | Schematics | December 03 2018 | confidential | ||||
1 2 3 4 | Test Setup Photos | March 12 2018 | ||||||
1 2 3 4 | Cover Letter(s) | December 07 2017 | ||||||
1 2 3 4 | External Photos | December 07 2017 | ||||||
1 2 3 4 | Cover Letter(s) | December 07 2017 | ||||||
1 2 3 4 | Cover Letter(s) | December 07 2017 | ||||||
1 2 3 4 | ID Label/Location Info | December 07 2017 | ||||||
1 2 3 4 | RF Exposure Info | December 07 2017 | ||||||
1 2 3 4 | Test Report | December 07 2017 | ||||||
1 2 3 4 | Test Setup Photos | December 07 2017 |
1 2 3 4 | User Guide | Users Manual | 1.16 MiB | March 12 2018 |
CYBT-343151-02 EZ-BT WICED XT/XR Module Power Consumption n Enhanced Data Rate (EDR) at 8 dBm p Peak TX current: 52.5 mA p Peak RX current consumption: 26.4 mA n Bluetooth Low Energy (BLE) at 0 dBm p 1-second interval BLE ADV average current consumption:
315 uA n Low power mode support p Deep Sleep: 2.69 uA Functional Capabilities n - ADC for audio (12 bits) and DC measurement (10 bits) n Serial Communications interface compatible with I2C slaves n Serial Peripheral Interface (SPI) support for both master and slave modes n HCI interface through UART n PCM/I2S Audio interface n Two-wire Global Coexistence Interface (GCI) n Integrated peripherals such as PWM, ADC n Programmable output power control n Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets Benefits CYBT-343151-02 provides all necessary components required to operate BLE and/or BR/EDR communication standards. n Proven hardware design ready to use n Dual-mode operation eliminates the need for multiple modules n Cost optimized for applications without space constraints n Nonvolatile memory for self-sufficient operation and Over-the-air updates n Bluetooth SIG Listed with QDID and Declaration ID n Fully certified module eliminates the time needed for design, development and certification processes n WICED STUDIO provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application General Description The CYBT-343151-02 is a fully integrated Bluetooth Smart Ready wireless module. The CYBT-343151-02 includes an onboard crystal oscillator, passive components, flash memory, and the Cypress CYW20706 silicon device. Refer to the CYW20706 datasheet for additional details on the capabilities of the silicon device used in this module. The CYBT-343151-02 provides extended industrial temperature operation (XT). The CYBT-343151-02 supports peripheral functions (ADC and PWM), UART, I2C, and SPI communication, and a PCM/I2S audio interface. The CYBT-343151-02 includes a royalty-free Bluetooth stack compatible with Bluetooth 5.0 in a 12.0 15.5 1.95 mm package. The CYBT-343151-02 includes 512 KB of onboard serial flash memory and is designed for standalone operation. The CYBT-343151-02 uses an integrated power amplifier to achieve Class I or Class II output power capability. The CYBT-343151-02 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost optimized Bluetooth wireless connectivity. Module Description n Module size: 12.00 mm 15.50 mm 1.95 mm p Drop-in compatible with CYBT-343026-01 n Bluetooth 5.0 Qualified Smart Ready module p QDID:TBD p Declaration ID:TBD n Certified to FCC, ISED, MIC, and CE regulations n Castelated solder pad connections for ease-of-use n 512-KB on-module serial flash memory n Up to 11 GPIOs n Temperature range: 30 C to +85 C n Cortex-M3 32-bit processor n Maximum TX output power p +12 dbm for Bluetooth Classic p +9 dBm for Bluetooth Low Energy BLE connection range of up to 250 meters at 9 dBm[1]
n RX Receive Sensitivity:
p Bluetooth Classic:
93.5 dBm at 1 Mbps, GFSK 95.5 dBm at 2 Mbps, /4-DQPSK 89.5 dBm at 3 Mbps, 8-DPSK p 96.5 dBm for Bluetooth Low Energy Note 1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +9.0 dBm. Actual range will vary based on end product design, environment, receive sensitity and transmit output power of the central deivce. Cypress Semiconductor Corporation Document Number: 002-24961 Rev. **
198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised November 26, 2018 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References CYBT-343151-02 n Overview: EZ-BLE/BT Module Portfolio, Module Roadmap n CYW20706 BT Silicon Datasheet n Development Kits:
p CYBT-343026-EVAL, CYBT-343026-01 Evaluation Board n Test and Debug Tools:
p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App) n Knowledge Base Article p KBA97095 - EZ-BLE Module Placement p KBA213260- RF Regulatory Certifications for CYBT-343026-01 EZ-BT WICED Modules p KBA213976 - FAQ for BLE and Regulatory Certifications with p KBA210802 - Queries on BLE Qualification and Declaration EZ-BLE modules Processes p KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules p KBA221025 - Platform Files for CYBT-343026-EVAL p KBA223428 - Programming an EZ-BT WICED Module Development Environments Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK) Cypress' WICED (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth connectivity in system design. WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. Technical Support n Cypress Community: Whether youre a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world. n Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System. n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-24961 Rev. **
Page 2 of 52 CYBT-343151-02 Electrical Characteristics............................................... 25 Chipset RF Specifications ............................................. 27 Timing and AC Characteristics ..................................... 30 UART Timing............................................................. 30 SPI Timing................................................................. 31 I2C Interface Timing.................................................. 33 PCM Interface Timing................................................ 34 I2S Interface Timing .................................................. 38 Environmental Specifications ....................................... 41 Environmental Compliance ....................................... 41 RF Certification.......................................................... 41 Safety Certification .................................................... 41 Environmental Conditions ......................................... 41 ESD and EMI Protection ........................................... 41 Regulatory Information.................................................. 42 FCC........................................................................... 42 ISED.......................................................................... 43 European Declaration of Conformity ......................... 44 MIC Japan................................................................. 44 Packaging........................................................................ 45 Ordering Information...................................................... 47 Acronyms........................................................................ 48 Document Conventions ................................................. 50 Units of Measure ....................................................... 50 Document History Page................................................. 51 Sales, Solutions, and Legal Information ...................... 52 Worldwide Sales and Design Support....................... 52 Products .................................................................... 52 PSoC Solutions ...................................................... 52 Cypress Developer Community................................. 52 Technical Support ..................................................... 52 Contents Overview............................................................................ 4 Functional Block Diagram ........................................... 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Module Connections ........................................................ 9 Connections and Optional External Components....... 10 Power Connections (VDDIN)..................................... 10 External Reset (XRES).............................................. 10 Multiple-Bonded GPIO Connections ......................... 11 Critical Components List ........................................... 13 Antenna Design......................................................... 13 Functional Description................................................... 14 Bluetooth Baseband Core ......................................... 14 Microcontroller Unit ................................................... 16 External Reset (XRES).............................................. 17 Integrated Radio Transceiver ........................................ 18 Transmitter Path........................................................ 18 Receiver Path............................................................ 18 Local Oscillator Generation ....................................... 18 Calibration ................................................................. 18 Internal LDO.............................................................. 19 Collaborative Coexistence............................................. 19 Global Coexistence Interface ........................................ 19 SECI I/O .................................................................... 19 Peripheral and Communication Interfaces .................. 20 I2C Communication Interface.................................... 20 HCI UART Interface .................................................. 20 Peripheral UART Interface ........................................ 21 Serial Peripheral Interface......................................... 21 PCM Interface ........................................................... 21 Clock Frequencies.......................................................... 21 GPIO Port ........................................................................ 22 PWM................................................................................. 22 Power Management Unit................................................ 24 RF Power Management ............................................ 24 Host Controller Power Management ......................... 24 BBC Power Management.......................................... 24 Document Number: 002-24961 Rev. **
Page 3 of 52 Overview Functional Block Diagram Figure 1 illustrates the CYBT-343151-02 functional block diagram. Figure 1. Functional Block Diagram (GPIOs) CYBT-343151-02 Module Description The CYBT-343151-02 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna connection location dimensions Length (X) Width (Y) Length (X) Width (Y) Height (H) PCB thickness Height (H) Shield height Height (H) Maximum component height Total module thickness (bottom of module to highest component) Height (H) 12.00 0.15 mm 15.50 0.15 mm 12.0 mm 4.62 mm 0.50 0.05 mm 1.45 mm typical 1.45 mm typical 1.95 mm typical See Figure 2 for the mechanical reference drawing for CYBT-343151-02. Document Number: 002-24961 Rev. **
Page 4 of 52 Figure 2. Module Mechanical Drawing CYBT-343151-02 Top View (Seen from Top) Side View Bottom View Notes 2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Recommended Host PCB Layout on page 7. 3. The CYBT-343151-02 includes castellated pad connections, denoted as the circular openings at the pad location above. Document Number: 002-24961 Rev. **
Page 5 of 52 CYBT-343151-02 Pad Connection Interface As shown in the bottom view of Figure 2 on page 5, the CYBT-343151-02 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-343151-02 module. Table 2. Connection Description Name Connections SP 24 Connection Type Pad Length Dimension Pad Width Dimension Solder Pads 1.02 mm 0.71 mm Pad Pitch 1.22 mm Figure 3. Solder Pad Dimensions (Seen from Bottom To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement best practices. Figure 4. Recommended Host PCB Keep Out Area Around the CYBT-343151-02 Antenna Document Number: 002-24961 Rev. **
Page 6 of 52 Recommended Host PCB Layout Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-343151-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-343151-02 Host Layout (Dimensioned) Figure 6. CYBT-343151-02 Host Layout (Relative to Origin) CYBT-343151-02 Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-24961 Rev. **
Page 7 of 52 Table 3 provides the center location for each solder pad on the CYBT-343151-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location CYBT-343151-02 Solder Pad
(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Location (X,Y) from Orign (mm)
(0.38, 5.04)
(0.38, 6.26)
(0.38, 7.48)
(0.38, 8.70)
(0.38, 9.92)
(0.38, 11.14)
(0.38, 12.35)
(0.38, 13.57)
(1.73, 15.11)
(2.95, 15.11)
(4.17, 15.11)
(5.39, 15.11)
(6.61, 15.11)
(7.83, 15.11)
(9.05, 15.11)
(10.27, 15.11)
(11.62, 13.57)
(11.62, 12.35)
(11.62, 11.14)
(11.62, 9.92)
(11.62, 8.70)
(11.62, 7.48)
(11.62, 6.26)
(11.62, 5.04) Dimension from Orign (mils)
(14.96, 198.42)
(14.96, 246.46)
(14.96, 294.49)
(14.96, 342.52)
(14.96, 390.55)
(14.96, 438.58)
(14.96, 486.22)
(14.96, 534.25)
(68.11, 594.88)
(116.14, 594.88)
(164.17, 594.88)
(212.20, 594.88)
(260.24, 594.88)
(308.27, 594.88)
(356.30, 594.88)
(404.33, 594.88)
(457.48, 534.25)
(457.48, 486.22)
(457.48, 438.58)
(457.48, 390.55)
(457.48, 342.52)
(457.48, 294.49)
(457.48, 246.46)
(457.48, 198.42) Top View (Seen on Host PCB) Document Number: 002-24961 Rev. **
Page 8 of 52 CYBT-343151-02 Module Connections Table 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-343151-02 module. Table 4 lists the solder pads on the CYBT-343151-02 module, the silicon device pin, and denotes what functions are available for each solder pad. Table 4. CYBT-343151-02 Solder Pad Connection Definitions Pad Pad Name Silicon Pin Name Silicon Port-Pin Name UART SPI[4,5]
I2C ADC COEX CLK/
XTAL GPIO Other PCM_Sync/
I2S_WS/P0/P34 PUART_TX/P0 PUART_RX/P34 SPI1_MOSI/P0
(master/slave) PUART_CTS/
P3 or P35 SPI1_CLK/P3
(master/slave) IN29/P0 IN5/P34 IN4/P35 IN10/29 SCL SDA/
P35 3 3
(P3/P29
/P35) PCM_Sync I2S_WS I2S_DO PCM_Out PWM3 (P29) 1 2 3 4 P0/P34 I2C_SCL C8 A8 XRES RESET _N I2C_SDA C7 5 P2/P37/P28 B7 GND 6 SPI2_CS_N 7 8 SPI2_MISO 9 SPI2_MOSI 10 SPI2_CLK 11 GPIO_0 12 13 14 15 GPIO_1 GND GPIO_4 P4/P24 16 UART_TXD 17 UART_CTS 18 UART_RTS 19 GPIO_7 20 UART_RXD 21 VDDIN 22 GPIO_3 D7 GND D8 E8 E7 F8 F7 GND D6 G8 F4 G4 F3 C6 F5 G1 C5 23 GPIO_6 B6 PCM_Out/P3/
I2S_DO/
P29/P35 RESET_N PCM_IN/
I2S_DI/P12 PCM_CLK/
I2S_CLK/P2/
P28/P37 N/A GND N/A N/A N/A BT_GPIO_0/
P36/P38 External Reset (Active Low) PUART_RX/P2 SPI1_CS(slave)/P2 SPI1_MOSI(master)/P2 SPI1_MISO(slave)/P37 SDA IN23/P12 SCL/
P37 IN11/P28 IN2/P37 3
(P12) 3 PCM_IN I2S_DI PWM2 (P28) I2S_CLK PCM_CLK ACLK1
/P37 No Connect (Used for on-module memory SPI interface for CYBT-343151-02) Ground No Connect (Used for on-module memory SPI interface for CYBT-343151-02) No Connect (Used for on-module memory SPI interface for CYBT-343151-02) No Connect (Used for on-module memory SPI interface for CYBT-343151-02) ACLK0
/P36 ACLK0
/P32 IN3/P36 IN1/P38 IN7/P32 Ground IN8/P31 SPI1_CLK/P36 SPI1_MOSI/P38
(master/slave) SPI1_MISO/P25
(master/slave) SPI1_CS/P32
(slave) SPI1_CS/P6
(slave) SPI1_MOSI/P4
(master/slave) SPI1_CLK/P24
(master/slave) HCI UART Transmit Data HCI UART Clear To Send Input HCI UART Request To Send Output IN9/P30 3
(GCI_SE CI_OUT) HCI UART Receive Data VDDIN (2.3V ~ 3.6V)
(DevWa 3 ke)
(HostWa 3 ke) Ext LPO In 3 3
(CLK_R EQ) 3 3 3 PWM1 (P27) PWM0 (P26) PUART_RX/P33 SPI1_MOSI/P27
(master/slave) SPI1_MOSI/P33
(slave) SPI1_CS/P26
(slave) IN6/P33 ACLK1
/P33 IN24/P11 3
(GCI_SE CI_IN) BT_GPIO_1/
P25/P32 PUART_RX/P25 PUART_TX/P32 GND BT_GPIO_4/P6/
P31/LPO_IN PUART_RTS/P6 PUART_TX/P31 BT_CLK_REQ/
P4/P24 PUART_RX/P4 PUART_TX/P24 BT_UART_TXD BT_UART_CTS BT_UART_RTS BT_GPIO_7/
P30 PUART_RTS/
P30 BT_UART_RXD VDDIN BT_GPIO_3/
P27/P33 BT_GPIO_6/
P11/P26 GND GND 24 Note 4. The CYBT-343026-01 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface. 5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in the table above. Ground GND Document Number: 002-24961 Rev. **
Page 9 of 52 CYBT-343151-02 Connections and Optional External Components Power Connections (VDDIN) The CYBT-343151-02 contains one power supply connection, VDDIN. VDDIN accepts a supply input range of 2.3 V to 3.6 V for CYBT-343151-02. Table 11 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 11. It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330 , 100 MHz. Considerations and Optional Components for Brown Out (BO) Conditions Power supply design must be completed to ensure that the CYBT-343151-02 module does not encounter a Brown Out condition, which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the following range:
VIL VDDIN VIH Refer to Table 12 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to Figure 8 for the recommended circuit design when using an external voltage detection IC. Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. External Reset (XRES) The CYBT-343151-02 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-343151-02 module (solder pad 3). The CYBT-343151-02 module does not require an external pull-up resistor on the XRES input During power-on operation, the XRES connection to the CYBT-343151-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:
n The host device should connect a GPIO to the XRES of the Cypress CYBT-343151-02 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDDIN is stable. n If the XRES connection of the CYBT-343151-02 module is not used in the application, a 10-F capacitor may be connected to the XRES solder pad of the CYBT-343151-02 in order to delay the XRES release. The capacitor value for this recommended imple-
mentation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms after VDDIN stability. n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. Refer to Figure 11 on page 17 for XRES operating and timing requirements during power-on events. Document Number: 002-24961 Rev. **
Page 10 of 52 CYBT-343151-02 Multiple-Bonded GPIO Connections The CYBT-343151-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used, only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio SDK. For details on the features and functions that each of these multiple-bonded GPIOs provide, refer to Table 4. The list below details the multiple-bonded GPIOs available on the CYBT-343151-02 module:
n PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available) n PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available) n PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available) n PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available) n PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available) n PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available) n PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available) n PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available) n PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available) n PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available) n PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available) Document Number: 002-24961 Rev. **
Page 11 of 52 Figure 9 illustrates the CYBT-343151-02 schematic. Figure 9. CYBT-343151-02 Schematic Diagram CYBT-343151-02 Document Number: 002-24961 Rev. **
Page 12 of 52 CYBT-343151-02 Critical Components List Table 5 details the critical components used in the CYBT-343151-02 module. Table 5. Critical Component List Component Reference Designator Description Silicon Silicon Crystal U1 U2 Y1 49-pin FBGA BT/BLE Silicon Device - CYW20706 8-pin TDF8N, 512K Serial Flash 24.000 MHz, 12PF Antenna Design Table 6 details trace antenna used in the CYBT-343151-02 module. For more information, see Table 6. Table 6. Trace Antenna Specifications Item Frequency Range Peak Gain Return Loss 24002500 MHz 0.5 dBi typical 10 dB minimum Description Document Number: 002-24961 Rev. **
Page 13 of 52 CYBT-343151-02 Functional Description Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:
n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. Table 7. Bluetooth Features Bluetooth 1.0 Basic Rate SCO Paging and Inquiry Page and Inquiry Scan Sniff Bluetooth 2.1 Secure Simple Pairing Enhanced Inquiry Response Sniff Subrating Bluetooth 4.1 Low Duty Cycle Advertising Dual Mode LE Link Layer Topology Bluetooth 1.2 Interlaced Scans Adaptive Frequency Hopping eSCO Bluetooth 3.0 Unicast Connectionless Data Enhanced Power Control eSCO Bluetooth 4.2 Data Packet Length Extension LE Secure Connection Link Layer Privacy Bluetooth 2.0 EDR 2 Mbps and 3 Mbp Bluetooth 4.0 Bluetooth Low Energy Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth Link Controller. n States:
p Standby p Connection p Page p Page Scan p Inquiry p Inquiry Scan p Sniff p Advertising p Scanning Document Number: 002-24961 Rev. **
Page 14 of 52 CYBT-343151-02 Test Mode Support The CYBT-343151-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYBT-343151-02 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:
n Fixed frequency carrier wave (unmodulated) transmission p Simplifies some type-approval measurements (Japan) p Aids in transmitter performance analysis n Fixed frequency constant receiver mode p Receiver output directed to I/O pin p Allows for direct BER measurements using standard RF test equipment p Facilitates spurious emissions testing for receive mode n Fixed frequency constant transmission p 8-bit fixed pattern or PRBS-9 p Enables modulated signal measurements with standard RF test equipment. Frequency Hopping Generator The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth clock, and device address. Document Number: 002-24961 Rev. **
Page 15 of 52 CYBT-343151-02 Microcontroller Unit The microprocessor unit in CYBT-343151-02 runs software from the link control (LC) layer up to the host controller interface (HCI). The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code. The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the internal ROM. External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an external serial flash memory. NVRAM Configuration Data and Storage NVRAM contains configuration information about the customer application, including the following:
n Fractional-N information n BD_ADDR n UART baud rate n SDP service record n File system information used for code, code patches, or data. The CYBT-343151-02 uses SPI Serial Flash for NVRAM storage. One-Time Programmable Memory The microprocessor unit in CYBT-343151-02 includes 2 KB of one-time programmable (OTP) memory allow manufacturing custom-
ization and to avoid the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after the CYBT-343151-02 boots and is ready for host transport communication. The OTP contents are limited to:
n Parameters required prior to downloading the user configuration to RAM. n Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key). n VDDIN for the module must be kept to 3.0 V to 3.6 V power supply range if OTP is used in the application. Document Number: 002-24961 Rev. **
Page 16 of 52 External Reset (XRES) The CYBT-343151-02 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external active low reset signal, XRES, can be used to put the CYBT-343151-02 in the reset state. The XRES pin has an internal pull-up resistor and, in most applications, it does not require anything to be connected to it. Figure 10. External Reset Internal Timing CYBT-343151-02 External Reset (XRES) Recommended External Components and Proper Operation During a power-on event, the XRES line of the CYBT-343151-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. Refer to Figure 11 for the Power-On XRES timing operation. This power-on operation can be accomplished in the following ways:
n A host device should connect a GPIO to the XRES of the Cypress CYBT-343151-02 module and pull XRES low until VDD is stable. XRES can be released after VDD is stable. n If the XRES connection of the CYBT-343151-02 module is not used in the application, a 10-F capacitor may be connected to the XRES solder pad of the CYBT-343151-02. n The XRES release timing can also be controlled via an external voltage detection circuit. Figure 11. Power-On External Reset (XRES) Operation Document Number: 002-24961 Rev. **
Page 17 of 52 CYBT-343151-02 Integrated Radio Transceiver The CYBT-343151-02 has an integrated radio transceiver that has been optimized for use in 2.4-GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4-GHz unlicensed ISM band. The CYBT-343151-02 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR) specification and meets or exceeds the requirements to provide the highest communication link quality of service. Transmitter Path The CYBT-343151-02 a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4-GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the BLE specification. The transmitter PA bias can also be adjusted to provide Bluetooth class 1 or class 2 operation. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK, 4-DQPSK, and 8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Power Amplifier The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. Receiver Path The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation, enables the CYBT-343151-02 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYBT-343151-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator Generation The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation sub-block employs an architecture for high immunity to LO pulling during PA operation. The CYBT-343151-02 uses an internal loop filter. Calibration The CYBT-343151-02 radio transceiver features an automated calibration scheme that is fully self-contained in the radio. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the perfor-
mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops, and calibrates for temperature variations as the device cools and heats during normal operation in its environment. Document Number: 002-24961 Rev. **
Page 18 of 52 CYBT-343151-02 Internal LDO The microprocessor in CYBT-343151-02 uses two LDOs one for 1.2 V and the other for 2.5 V. The 1.2-V LDO provides power to the baseband and radio and the 2.5-V LDO powers the PA. Collaborative Coexistence The CYBT-343151-02 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions. Global Coexistence Interface The CYBT-343151-02 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a 2-wire interface. The following key features are associated with the interface:
n Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input
(GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function. n It supports generic UART communication between WLAN and Bluetooth devices. n To conserve power, it is disabled when inactive. n It supports automatic resynchronization upon waking from sleep mode. n It supports a baud rate of up to 4 Mbps. SECI I/O The microprocessor in CYBT-343151-02 has dedicated GCI_SECI_IN (PAD 23/GPIO_6) and GCI_SECI_OUT (PAD19/GPIO_7) pins. Refer to Table 4, which detail the module solder pad number used for SECI I/O. Document Number: 002-24961 Rev. **
Page 19 of 52 CYBT-343151-02 Peripheral and Communication Interfaces I2C Communication Interface The CYBT-343151-02 provides a 2-pin master I2C interface, which can be used to retrieve configuration information from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. This interface is compatible with I2C slave devices. I2C does not support multimaster capability or flexible wait-state insertion by either master or slave devices. The following transfer clock rates are supported by the I2C:
n 100 kHz n 400 kHz n 800 kHz (not a standard I2C-compatible speed.) n 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.) The following transfer types are supported by the I2C:
n Read (Up to 127 bytes can be read) n Write (Up to 127 bytes can be written) n Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written) n Write-then-Read (Up to127 bytes can be written and up to 127 bytes can be read) Hardware controls the transfers, requiring minimal firmware setup and supervision. The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the CYBT-343151-02, are required on both the SCL and SDA pad for proper operation. HCI UART Interface The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 4 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYBT-343151-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 4 Mbps. The baud rate of the CYBT-343151-02UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. Table 8 contains example values to generate common baud rates with a 24 MHz UART clock. Table 8. Common Baud Rate Examples, 24 MHz Clock Baud Rate (bps) Baud Rate Adjustment High Nibble Low Nibble 4M 3M 2M 1M 921600 460800 230400 115200 57600 38400 0xFF 0xFF 0XFF 0X44 0x05 0x02 0x04 0x00 0x00 0x01 0xF4 0xF8 0XF4 0XFF 0x05 0x02 0x04 0x00 0x00 0x00 Mode High rate High rate High rate Normal Normal Normal Normal Normal Normal Normal Error (%) 0.00 0.00 0.00 0.00 0.16 0.16 0.16 0.16 0.16 0.00 Document Number: 002-24961 Rev. **
Page 20 of 52 CYBT-343151-02 Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYBT-343151-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within 2%. Peripheral UART Interface The CYBT-343151-02 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each signal as shown in Table 9 Table 9. CYBT-343151-02 Peripheral UART Signal Name PUART_TX PUART_RX PUART_CTS_N PUART_RTS_N PUART Port Configuration #1 PUART Port Configuration #2 P0 P31 P2 P33 P3 P35 P6 P30 Serial Peripheral Interface The CYBT-343151-02 has two independent SPI interfaces. One is a master-only interface (SPI2) and the other (SPI1) can be either a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-343151-02 has optional I/O ports that can be configured individually and separately for each functional pin. The CYBT-343151-02 acts as an SPI master device that supports 3.3 V SPI slaves. In master mode, refer to Table 4 to identify the solder pads avialable for SPI1_MISO, SPI1_MOSI, and SPI1_CLK connections. NOTE: In master mode, any available GPIO can be assigned as SPI1_CS. The CYBT-343151-02 can also act as an SPI slave device that supports a 3.3 V SPI master. For SPI1 slave mode, refer to Table 4 to identify the solder pads available for SPI1 slave mode connections. SPI voltage depends on VDDIN; therefore, VDDIN should be set to 3.3 V for SPI communication. PCM Interface The CYBT-343151-02 includes a PCM interface that shares pins with the I2S interface. The PCM Interface on the CYBT-343151-02 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-343151-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-343151-02. Slot Mapping The CYBT-343151-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYBT-343151-02 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The CYBT-343151-02 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYBT-343151-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first. Clock Frequencies The CYBT-343151-02 has an integrated 24 MHz crystal on the module. There is no need to add an additional crystal oscillator. Document Number: 002-24961 Rev. **
Page 21 of 52 CYBT-343151-02 GPIO Port The CYBT-343151-02 has nine GPIOs besides two I2C pads. All GPIOs support programmable pull-ups and are capable of driving up to 8 mA at 3.3 V or 4 mA at 1.8 V, except chips P26, P27, P28, and P29, which are capable of driving up to 16 mA at 3.3 V. The following GPIOs are available on the module pads:
n PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available) n PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available) n PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available) n PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available) n PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available) n PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available) n PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available) n PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available) n PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available) n PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available) n PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available) Refer to Table 4 to determine what GPIOs can be configured as ADC Inputs. NOTE: Any available GPIO can be used for SPI1_CS when in master mode. Port 26Port 29 in PAD 23/PAD 22/PAD 5/PAD 2 P[26:29] in PAD 23/PAD 22/PAD 5/PAD 2 consists of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have PWM functionality, which can be used for LED dimming. For a description of the capabilities of all GPIOs, see Table 4. PWM The CYBT-343151-02 has four PWMs. The PWM module consists of the following:
n PWM0-3 n The following GPIOs can be mapped as PWMs, module pad shown in [ ]:
p PWM0: P26 on P11/P26 [Pad 23]
p PWM1: P27 on P33/P27 [Pad 22]
p PWM2: P28 on P2/P37/P28 [Pad 5]
p PWM3: P29 on P3/P35/P29/I2C_SCL [Pad 2]
n PWM1-4: Each of the four PWM channels contains the following registers:
p 10-bit initial value register (read/write) p 10-bit toggle register (read/write) p 10-bit PWM counter value register (read) n PWM configuration register shared among PWM1-4 (read/write). This 12-bit register is used:
p To configure each PWM channel p To select the clock of each PWM channel p To change the phase of each PWM channel Figure 12 shows the structure of one PWM. Document Number: 002-24961 Rev. **
Page 22 of 52 Figure 12. PWM Block Diagram CYBT-343151-02 Document Number: 002-24961 Rev. **
Page 23 of 52 CYBT-343151-02 Power Management Unit The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4-GHz trans-
ceiver, which then processes the power-down functions accordingly. Host Controller Power Management Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep sleep (HIDOFF) mode. BBC Power Management There are several low-power operations for the BBC:
n Physical layer packet handling turns RF on and off dynamically within packet TX and RX. n Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBT-343151-02 runs on the Low Power Oscillator and wakes up after a predefined time period. The CYBT-343151-02 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
n Active mode n Idle mode n Sleep mode n HIDOFF (Deep Sleep) mode The CYBT-343151-02 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. In HIDOFF (Deep Sleep) mode, the CYBT-343151-02 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. Document Number: 002-24961 Rev. **
Page 24 of 52 CYBT-343151-02 Electrical Characteristics Table 10 shows the maximum electrical rating for voltages referenced to VDDIN pad. Table 10. Maximum Electrical Rating Rating VDDIN Voltage on input or output pin Operating ambient temperature range Storage temperature range Table 11 shows the power supply characteristics for the range TJ = 0 to 125 C. Table 11. Power Supply Symbol Topr Tstg Value 3.795 VSS 0.3 to VDD + 0.3 30 to +85 40 to +85 Description Minimum[6]
Typical Maximum[6]
Parameter VDDIN VDDIN_RIPPLE Power Supply Input (CYBT-343151-02) Maximum Power Supply Ripple for VDDIN input voltage 2.3 Table 12 shows the specifications for the digital voltage levels. Table 12. Digital Voltage Levels Characteristics Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance (VDDMEM domain) Table 13 shows the current consumption measurements Table 13. Bluetooth, BLE, BR and EDR Current Consumption Parameter Description Typ Symbol VIL VIH VOL VOH CIN Min 2.0 VDDIN 0.4 Silicon or Module Parameter Output Power Level/Class 3DM5/3DH5 DM1/DH1 DM3/DH3 DM5/DH5 RX1M_BR TX1M_BR RX23M_EDR TX23M_EDR Deep Sleep Bluetooth Classic (BR, EDR) HCI control mode HCI control mode HCI control mode HCI control mode Peak receive (1 Mbps) current level when receiving a basic rate packet (radio only) Peak transmit (1 Mbps) current level when trans-
mitting a basic rate packet (radio only) Peak receive (EDR) current level when receiving a 2 or 3 Mbps rate packet (radio only) Peak transmit (EDR) current level when trans-
mitting a 2 or 3 Mbps rate packet (radio only) Deep Sleep (HIDOFF) current Silicon Silicon Silicon Silicon Silicon Class 1 Class 1 Class 1 Class 1 Class 1 Silicon 10 dBm Silicon Class 1 Silicon Module 8 dBm All Unit V V C C Unit V mV Unit V V V V pF Unit mA mA mA mA mA mA mA mA uA 3.6 100 Max 0.8 0.4 0.4 Typ 37.1 32.2 38.2 38.5 26.4 60.3 26.4 52.5 2.69 Note 6. Overall performance degrades beyond minimum and maximum supply voltages.The voltage range specified is determined by the minimum and maximum operating Page 25 of 52 Document Number: 002-24961 Rev. **
voltage of the SPI Serial Flash included on the module. CYBT-343151-02 Table 13. Bluetooth, BLE, BR and EDR Current Consumption Parameter Description Silicon or Module Parameter Output Power Level/Class Bluetooth Classic (BR, EDR) Connected + IScan + PScan Connected with no data transfer + Inquiry IDLE IScan PScan IScan+PScan Connected Connected + PScan Connected + SNIFF Connected + SNIFF+ IScan
+ PScan TX_BR TX+SNIFF_BR RXPeak TXPeak Deep Sleep Connection_1s Connection_4s Adv_640 Adv_30 Adv_1s Module Module Module Module Module Module is idle, non-discoverable and non-connectable Inquiry Scan (1.28 seconds) Page scan (1.28 seconds) Inquiry scan + Page Scan (1.28 seconds) Connected with no data transfer Connected with no data transfer + Page Scan (1.28 seconds) Scan(1.28 seconds) + Page Scan (1.28 seconds) Module Connected with no data transfer + SNIFF (500 ms) Module Connected with no data transfer + SNIFF (500 ms)
+ Inquiry Scan and Page Scan 1.28 seconds Data transfer @ 115200 baud rate Module Data transfer @ 115200 baud rate + Sniff (500 ms) Module Module Module Bluetooth Low Energy (BLE) Peak RX current Peak TX Current Deep Sleep (HIDOFF) current Connection - 1-second interval Connection - 4-second interval Module Module Module Module Module Advertisement (low duty cycle) - 640 ms Module Advertisement (high duty cycle) - 30 ms Module 1-second non-connectable advertisement
(Beacon) Module Class 1 Class 1 Class 1 Class 1 Class 1 Class 1 Class 1 Class 1 Class 1 Class 1 Class 1
-2.5dBm
+6.5 dBm
+9.0 dBm
-2.5dBm
+6.5 dBm
+9.0 dBm All
-2.5dBm
+6.5 dBm
+9.0 dBm
-2.5dBm
+6.5 dBm
+9.0 dBm
-2.5dBm
+6.5 dBm
+9.0 dBm
-2.5dBm
+6.5 dBm
+9.0 dBm
-2.5dBm
+6.5 dBm
+9.0 dBm Unit mA mA mA mA mA mA mA mA mA mA mA mA mA uA uA uA mA mA uA Typ 0.11 0.65 0.65 1.2 2.6 3.3 3.6 0.95 1.9 22 5.5 42 54 56 28 28 28 2.69 970 980 1000 900 945 950 0.4 0.5 0.5 3.8 4.2 4.3 315 350 350 Document Number: 002-24961 Rev. **
Page 26 of 52 Chipset RF Specifications All specifications in Table 14 are for industrial temperatures and are single-ended. Unused inputs are left open. Table 14. Chipset Receiver RF Specifications Parameter Conditions Minimum Typical[7]
Maximum Unit CYBT-343151-02 Frequency range RX sensitivity[8]
Maximum input Maximum input C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I Image channel C/I 1 MHz adjacent to image channel General 2402 GFSK, 0.1% BER, 1 Mbps LE GFSK, 0.1% BER, 1 Mbps
/4-DQPSK, 0.01% BER, 2 Mbps 8-DPSK, 0.01% BER, 3 Mbps GFSK, 1 Mbps
/4-DQPSK, 8-DPSK, 2/3 Mbps Interference Performance GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER 8-DPSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 93.5 96.5 95.5 89.5 9.5 5 40 49 27 37 11 8 40 50 27 40 17 5 40 47 20 35 30 MHz2000 MHz 20002399 MHz 0.1% BER 0.1% BER 10.0 27 Out-of-Band Blocking Performance (CW)[9]
2480 20 20 11 0 30.0 40.0 9.0 20.0 13 0 30.0 40.0 7.0 20.0 21 5 25.0 33.0 0 13.0 MHz dBm dBm dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm Notes 7. Typical operating conditions are 1.22-V operating voltage and 25C ambient temperature. 8. The receiver sensitivity is measured at BER of 0.1% on the device interface. 9. Meets this specification using front-end band pass filter. Document Number: 002-24961 Rev. **
Page 27 of 52 Table 14. Chipset Receiver RF Specifications (continued) Conditions Parameter 24983000 MHz 3000 MHz12.75 GHz 0.1% BER 0.1% BER Minimum Typical[7]
Maximum 27 10.0 Out-of-Band Blocking Performance, Modulated Interferer 776764 MHz 824849 MHz 18501910 MHz 824849 MHz 880915 MHz 17101785 MHz 18501910 MHz 18501910 MHz 19201980 MHz BT, Df = 5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 65 MHz to 108 MHz 746 MHz to 764 MHz 851894 MHz 925960 MHz 18051880 MHz 19301990 MHz 21102170 MHz CDMA CDMA CDMA EDGE/GSM EDGE/GSM EDGE/GSM EDGE/GSM WCDMA WCDMA Intermodulation Performance[11]
39.0 Spurious Emissions[12]
FM Rx CDMA CDMA EDGE/GSM EDGE/GSM PCS WCDMA 10[10]
10[10]
23[10]
10[10]
10[10]
23[10]
23[10]
23[10]
23[10]
147 147 147 147 147 147 147 CYBT-343151-02 Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz 62 47 Notes 10. Numbers are referred to the pin output with an external BPF filter. 11. f0 = -64 dBm Bluetooth-modulated signal, f1 = 39 dBm sine wave, f2 = 39 dBm Bluetooth-modulated signal, f0 = 2f1 f2, and |f2 f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. 12. Includes baseband radiated emissions. Document Number: 002-24961 Rev. **
Page 28 of 52 CYBT-343151-02 Table 15. Chipset Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range Class1: GFSK Tx power[13]
Class1: EDR Tx power[14]
Class 2: GFSK Tx power Power control step
/4-DQPSK Frequency Stability
/4-DQPSK RMS DEVM
/4-QPSK Peak DEVM
/4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM 8-DPSK 99% DEVM 1.0 MHz < |M N| < 1.5 MHz 1.5 MHz < |M N| < 2.5 MHz
|M N| > 2.5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz General 2402 2 Modulation Accuracy 10 10 In-Band Spurious Emissions Out-of-Band Spurious Emissions 12 9 2 4 Table 16. Chipset BLE RF Specifications Parameter Frequency range Rx sense[17]
Tx power[18]
Mod Char: Delta F1 average Mod Char: Delta F2 max[19]
Mod Char: Ratio Conditions N/A GFSK, 0.1% BER, 1 Mbps N/A N/A N/A N/A Minimum 2402 225 99.9 0.8 Typical 96.5 255 0.95 2480 8 10 20 35 30 10 13 25 20 26 20 40 36.0[15]
30.0[15, 16]
47.0 47.0 Maximum 2480 9 275 MHz dBm dBm dBm dB kHz
%
%
%
kHz
%
%
%
dBc dBm dBm dBm dBm dBm dBm Unit MHz dBm dBm kHz
%
%
13. TBD dBm output for GFSK measured with PAVDD = 2.5 V. 14. TBD dBm output for EDR measured with PAVDD = 2.5 V. 15. Maximum value is the value required for Bluetooth qualification. 16. Meets this spec using a front-end band-pass filter. 17. Dirty Tx is Off. 18. The BLE Tx power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE Tx power at the antenna port cannot exceed the 10 dBm EIRP specification limit. 19. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Document Number: 002-24961 Rev. **
Page 29 of 52 CYBT-343151-02 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 17. UART Timing Specifications Reference Characteristics 1 2 3 Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min Max 24 10 2 Unit Baud out cycles ns Baud out cycles Figure 13. UART Timing Document Number: 002-24961 Rev. **
Page 30 of 52 CYBT-343151-02 SPI Timing The SPI interface supports clock speeds up to 12 MHz Table 18 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively. Table 18. SPI Mode 0 and 2 Reference Characteristics Minimum Maximum Unit 1 2 3 4 5 6 7 8 Time from slave assert SPI_INT to master assert SPI_CSN (Direc-
tRead) Time from master assert SPI_CSN to slave assert SPI_INT (Direct-
Write) Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions 0 0 20 8 8 0 0 1 SCK SCK SCK 100 ns ns ns ns ns ns ns ns Figure 14. SPI Timing Mode 0 and 2 Table 19 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3. Document Number: 002-24961 Rev. **
Page 31 of 52 CYBT-343151-02 Table 19. SPI Mode 1 and 3 Reference Characteristics Minimum Maximum Unit 1 2 3 4 5 6 7 8 Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead) Time from master assert SPI_CSN to slave assert SPI_INT (DirectWrite) Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions 0 0 20 8 8 0 0 1 SCK SCK SCK 100 ns ns ns ns ns ns ns ns Figure 15. SPI Timing Mode 1 and 3 Document Number: 002-24961 Rev. **
Page 32 of 52 I2C Interface Timing Table 20. I2C Interface Timing Specifications 1 2 3 4 5 6 7 8 9 10 Reference Characteristics Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time[20]
Data input setup time STOP condition setup time Output valid from clock Bus free time[21]
Figure 16. I2C Interface Timing Diagram CYBT-343151-02 Min 650 280 650 280 0 100 280 650 Max 100 400 800 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns Notes 20. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 21. Time that the cbus must be free before a new transaction can start. Document Number: 002-24961 Rev. **
Page 33 of 52 PCM Interface Timing Short Frame Sync, Master Mode Figure 17. PCM Timing Diagram (Short Frame Sync, Master Mode) CYBT-343151-02 Table 21. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Reference Characteristics Minimum Typical Maximum 1 2 3 4 5 6 7 8 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 41.0 41.0 0 0 8.0 8.0 0 12 25.0 25.0 25.0 Unit MHz ns ns ns ns ns ns ns Document Number: 002-24961 Rev. **
Page 34 of 52 Short Frame Sync, Slave Mode Figure 18. PCM Timing Diagram (Short Frame Sync, Slave Mode) CYBT-343151-02 Table 22. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Minimum Characteristics Reference Typical Maximum 1 2 3 4 5 6 7 8 9 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 41.0 41.0 8.0 8.0 0 8.0 8.0 0 12.0 25.0 25.0 Unit MHz ns ns ns ns ns ns ns ns Document Number: 002-24961 Rev. **
Page 35 of 52 Long Frame Sync, Master Mode Figure 19. PCM Timing Diagram (Long Frame Sync, Master Mode) CYBT-343151-02 Table 23. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Reference Characteristics Minimum 1 2 3 4 5 6 7 8 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 41.0 41.0 0 0 8.0 8.0 0 Typical Maximum 12 25.0 25.0 25.0 Unit MHz ns ns ns ns ns ns ns Document Number: 002-24961 Rev. **
Page 36 of 52 Long Frame Sync, Slave Mode Figure 20. PCM Timing Diagram (Long Frame Sync, Slave Mode) CYBT-343151-02 Table 24. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Reference Characteristics Minimum 1 2 3 4 5 6 7 8 9 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 41.0 41.0 8.0 8.0 0 8.0 8.0 0 Typical Maximum 12 25.0 25.0 Unit MHz ns ns ns ns ns ns ns ns Document Number: 002-24961 Rev. **
Page 37 of 52 CYBT-343151-02 I2S Interface Timing The I2S interface supports both master and slave modes. The I2S signals are:
n I2S clock: I2S SCK n I2S Word Select: I2S WS n I2S Data Out: I2S SDO n I2S Data In: I2S SDI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYBT-343151-02 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. The clock rate in master mode is either of the following:
n 48 kHz x 32 bits per frame = 1.536 MHz n 48 kHz x 50 bits per frame = 2.400 MHz Document Number: 002-24961 Rev. **
Page 38 of 52 The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. Timing values specified in Table 25 are relative to high and low threshold levels. Table 25. Timing for I2S Transmitters and Receivers Transmitter Receiver CYBT-343151-02 Clock Period T HIGH tHC LOWtLC HIGH tHC LOW tLC Rise time tRC Delay tdtr Hold time thtr Setup time tsr Hold time thr Lower LImit Min Max Ttr Master Mode: Clock generated by transmitter or receiver Lower Limit Min Max Tr Upper Limit Min Max 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr Slave Mode: Clock accepted by transmitter or receiver 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.15Ttr Transmitter 0.8T Receiver 0 0.2Tr 0 Upper Limit Min Max Notes Note 22 Note 23 Note 23 Note 24 Note 24 Note 25 Note 26 Note 26 Note 27 Note 27 Note: The time periods specified in Figure 21 and Figure 22 are defined by the transmitter speed. The receiver specifications must match transmitter performance. Notes 22. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 23. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with 24. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 25. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. 26. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient respect to T. setup time. 27. The data setup and hold time must not be less than the specified receiver setup and hold time. Document Number: 002-24961 Rev. **
Page 39 of 52 Figure 21. I2S Transmitter Timing CYBT-343151-02 Figure 22. I2S Receiver Timing Document Number: 002-24961 Rev. **
Page 40 of 52 CYBT-343151-02 Environmental Specifications Environmental Compliance This CYBT-343151-02 BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBT-343151-02 module will be certified under the following RF certification standards at production release. n FCC: WAP3026 n CE n IC: 7922A-3026 n MIC: 203-JN0721 Safety Certification The CYBT-343151-02 module complies with the following safety regulations:
n Underwriters Laboratories, Inc. (UL): Filing E331901 n CSA n TUV Environmental Conditions Table 26 describes the operating and storage conditions for the Cypress BLE module. Table 26. Environmental Conditions for CYBT-343151-02 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into end system Components[28]
30 C 5%
40 C 105 C 85%
3 C/minute 105 C 85 C at 85%
15 kV Air 2.0 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 28. This does not apply to the RF pins (ANT). Document Number: 002-24961 Rev. **
Page 41 of 52 CYBT-343151-02 Regulatory Information FCC FCC NOTICE:
The device CYBT-343151-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
n Reorient or relocate the receiving antenna. n Increase the separation between the equipment and receiver. n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. n Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3026. In any case the end product must be labeled exterior with "Contains FCC ID: WAP3026"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 6 on page 13. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 6 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBT-343151-02 with the trace antenna is far below the FCC radio frequency exposure limits. Never-
theless, use CYBT-343151-02 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-24961 Rev. **
Page 42 of 52 CYBT-343151-02 ISED Innovation, Science and Economic Development Canada (ISED) Certification CYBT-343151-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada (ISED), License: IC: 7922A-3026 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 6 on page 13, having a maximum gain of -0.5 dBi. Antennas not included in this list or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE:
The device CYBT-343151-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYBT-343151-02, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences d'approbation de l'metteur modulaire tel que dcrit dans RSS-GEN. L'opration est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interfrences nuisibles, et (2) Cet appareil doit accepter toute interfrence reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonction-
nement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 10 mm between the radiator and your body. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. Cet quipement doit tre install et utilis avec un minimum de 10 mm de distance entre la source de rayonnement et votre corps. LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3026. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3026"
Document Number: 002-24961 Rev. **
Page 43 of 52 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-343151-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
CYBT-343151-02 All versions of the CYBT-343151-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBT-343151-02 is certified as a module with certification number 203-JN0721. End products that integrate CYBT-343151-02 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. Figure 23. MIC Label Document Number: 002-24961 Rev. **
Page 44 of 52 CYBT-343151-02 Packaging Table 27. Solder Reflow Peak Temperature Module Part Number Package 24-pad SMT CYBT-343151-02 Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles 260 C 30 seconds 2 Table 28. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBT-343151-02 Package 24-pad SMT MSL MSL 3 The CYBT-343151-02 is offered in tape and reel packaging. Figure 24 details the tape dimensions used for the CYBT-343151-02. Figure 24. CYBT-343151-02 Tape Dimensions Figure 25 details the orientation of the CYBT-343151-02 in the tape as well as the direction for unreeling. Figure 25. Component Orientation in Tape and Unreeling Direction Document Number: 002-24961 Rev. **
Page 45 of 52 Figure 26 details reel dimensions used for the CYBT-343151-02. Figure 26. Reel Dimensions CYBT-343151-02 The CYBT-343151-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-343151-02 is detailed in Figure 27. Figure 27. CYBT-343151-02 Center of Mass Document Number: 002-24961 Rev. **
Page 46 of 52 CYBT-343151-02 Ordering Information Table 29 lists the CYBT-343151-02 part number and features. Table 30 lists the reel shipment quantities for the CYBT-343151-02. Table 29. Ordering Information CPU Speed
(MHz) Flash Size (KB) Part Number I2C
(BSC) Packaging Package RAM PWM CYBT-343151-02 24 512 Yes 4 24-SMT Tape and Reel Size (KB) UART Yes 352 Table 30. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) 500 500 500 500 Minimum Reel Quantity Maximum Reel Quantity Comments Ships in 500 unit reel quantities. The CYBT-343151-02 is offered in tape and reel packaging. The CYBT-343151-02 ships in a reel size of 500. For additional information and a complete list of Cypress Semiconductor Wireless products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-24961 Rev. **
Page 47 of 52 Acronyms Table 31. Acronyms Used in this Document Acronym ADC ALU AMUXBUS API ARM BLE Bluetooth SIG BW CAN CE CSA CMRR CPU CRC ECC ECO EEPROM EMI EMIF EOC EOF ESD FCC FET FIR FPB FS GPIO HCI HVI IC IDAC Description analog-to-digital converter arithmetic logic unit Acronym IDE I2C, or IIC analog multiplexer bus application programming interface advanced RISC machine, a CPU architecture Bluetooth Low Energy Bluetooth Special Interest Group bandwidth Controller Area Network, a communications protocol European Conformity Canadian Standards Association common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame electrostatic discharge Federal Communications Commission field-effect transistor finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin host controller interface high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC IC IIR ILO IMO INL I/O IPOR IPSR IRQ ITM KC LCD LIN LNA LR LUT LVD LVI LVTTL MAC MCU MIC MISO NC NMI NRZ NVIC NVL Opamp PA CYBT-343151-02 Description integrated development environment Inter-Integrated Circuit, a communications protocol Industry Canada infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell Korea Certification liquid crystal display Local Interconnect Network, a communica-
tions protocol. low noise amplifier link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit Ministry of Internal Affairs and Communica-
tions (Japan) master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier power amplifier Document Number: 002-24961 Rev. **
Page 48 of 52 Table 31. Acronyms Used in this Document (continued) Acronym Description Acronym Description CYBT-343151-02 PAL PC PCB PGA programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier PHUB peripheral hub PHY physical layer PICU PLA PLD PLL PMDD POR PRES PRS PS PSoC PSRR PWM QDID RAM RISC RMS RTC RTL RTR RX SAR SC/CT SCL SDA SOC port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset precise power-on reset pseudo random sequence port read data register Programmable System-on-Chip power supply rejection ratio pulse-width modulator qualification design ID random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time I2C serial clock I2C serial data start of conversion SOF S/H SINAD SIO SMT SPI SR SRAM SRES STN SWD SWV TD THD TIA TN TRM TTL TUV TX UART UDB USB USBIO VDAC WDT WOL WRES XRES XTAL start of frame sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO. surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset super twisted nematic serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier twisted nematic technical reference manual transistor-transistor logic Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block Universal Serial Bus USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal Document Number: 002-24961 Rev. **
Page 49 of 52 CYBT-343151-02 Document Conventions Units of Measure Table 32. Units of Measure Symbol Unit of Measure C dB dBm fF Hz KB kbps Khr kHz k ksps LSB Mbps MHz M Msps A F H s V W mA ms mV nA ns nV pF ppm ps s sps sqrtHz V degrees Celsius decibel decibel-milliwatts femtofarads hertz 1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt Document Number: 002-24961 Rev. **
Page 50 of 52 Document History Page Document Title: CYBT-343151-02 EZ-BTTM WICED Module Document Number: 002-24961 Orig. of Revision Change SHNG Submission ECN TBD
**
Date Description of Change 11/23/2018 Preliminary datasheet for CYBT-343151-02 module. CYBT-343151-02 Document Number: 002-24961 Rev. **
Page 51 of 52 CYBT-343151-02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-24961 Rev. **
Revised November 26, 2018 Page 52 of 52
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PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 EZ-BT WICED Module General Description The CYBT-X430XX-01 is a fully integrated Bluetooth Smart Ready wireless module. The CYBT-X430XX-01 includes an onboard crystal oscillator, passive components, flash memory, and the Cypress CYW20706 silicon device. Refer to the CYW20706 datasheet for additional details on the capabilities of the silicon device used in this module. The CYBT-X430XX-01 supports peripheral functions (ADC and PWM), UART and USB communication, and a Bluetooth audio interface. The CYBT-X430XX-01 includes a royalty-free BLE stack compatible with Bluetooth 4.2 in a 12.0 15.5 1.95 mm package. The CYBT-343026-01 includes 512KB of onboard serial flash memory and is designed for stand-alone opperation. The CYBT-343029-01 has the CYBT-343026-01, but also include an on-board Apple Authentication co-processor for use with Apple products such as Homekit. The CYBT-143038-01 does not contain onboard flash, requiring hosted control or application RAM upload operating modes. The CYBT-143038-01 can also interface to external flash on the host board. The CYBT-X430XX-01 utilizes an integrated power amplifer to achieve Class I or Class II output power capability. The CYBT-X430XX-01 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost optimized BLE wireless connectivity. Module Description n Module size: 12.00 mm 15.50 mm 1.95 mm n Bluetooth LE 4.2 Smart Ready module the same characterisitcs as p QDID: WAP3026 p Declaration ID: 7922A-3026 n Certified to FCC, IC, MIC, and CE regulations n Castelated solder pad connections for ease-of-use n 512-KB on-module serial flash memory ( CYBT-34302X-01) n Up to 10 GPIOs n Temperature range: 30 C to +85 C n Cortex-M3 32-bit processor n Maximum TX output power:
p +12 dbm for Bluetooth EDR p +9 dBm for Bluetooth Low Energy n RX Receive Sensitivity:
p 93.5 dBm for Bluetooth Classic p 96.5 dBm for Bluetooth Low Energy Power Consumption[1]
n TX average current consumption: 12.5 mA (EDR) Class-II n RX average current consumption: 20.0 mA (EDR) n Low power mode support p Sleep: 120 uA Functional Capabilities n 10-bit auxiliary ADC with nine analog channels n Serial Communications interface compatible with I2C slaves n Serial Peripheral Interface (SPI) support for both master and slave modes n HCI interface through USB or UART n PCM/I2S Auido interface n 2-wire Global Coexistence Interface (GCI) n Bluetooth wideband speech support n Integrated peripherals such as PWM, ADC, Triac control n Programmable output power control n Maximum of 100 LE Connections n Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets Benefits CYBT-X430XX-01 provides all necessary components required to operate BLE and/or EDR/BR communication standards. n Proven hardware design ready to use n Dual-mode operatoin eliminates the need for multiple modules n Cost optimized for applications without space constraints n Non-volatile memory for self-sufficient operation and Over-the-air updates ( CYBT-34302X-01 only) n Bluetooth SIG Listed with QDID and Declaration ID n Fully certified module eliminates the time needed for design, development and certification processes n WICED STUDIO 4.0 provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application n Pre-programmed EZ-Serial firmware platform to allow for easy-to-use out of the box Bluetooth connectivity Notes 1. The values in this section were calculated for a 90% efficient DC-DC at 3V in HCI mode, and based on a Class I configurationbench-marked at Class II. Lower values are expected for a class II configuration using an external LPO and corresponding PAconfiguration Cypress Semiconductor Corporation Document Number: 002-19525 Rev. **
198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised May 31, 2017 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References n Overview: EZ-BLE/BT Module Portfolio, Module Roadmap n EZ-BT WICED Product Overview n CYW20706 BT Silicon Datasheet n Knowledge Base Article p KBA97095 - EZ-BLE Module Placement p KBA213260 - RF Regulatory Certifications for CYBT-343026-01 and CYBT-143038-01 EZ-BT WICED Modules p KBA213976 - FAQ for BLE and Regulatory Certifications with p KBA210802 - Queries on BLE Qualification and Declaration EZ-BLE modules Processes n Development Kits:
p CYBT-343026-EVAL, CYBT-343026-01 Evaluation Board n Test and Debug Tools:
p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App) Development Environments Two Easy-To-Use Design Environments to Get You Started Quickly Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK) Cypress's WICED (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits
(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth connectivity in system design. WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. EZ-Serial BT Firmware Platform Cypresss EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in Bluetooth applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the modules GPIOs, making it easy to add BLE and/or EDR/BR functionality quickly to existing designs. Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. EZ-BT modules with non-volatile memory are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you can download each EZ-BT modules firmware images on the EZ-Serial webpage. Technical Support n Cypress Community: Whether youre a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world. n Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-19525 Rev. **
Page 2 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Contents Overview............................................................................ 4 Functional Block Diagram ........................................... 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Module Connections ........................................................ 9 Connections and Optional External Components....... 11 Power Connections (VDDIN)..................................... 11 External Reset (XRES).............................................. 11 Multiple-Bonded GPIO Connections ......................... 11 Using CYBT-143038-01 with External Flash............. 11 Critical Components List ........................................... 13 Antenna Design......................................................... 13 Bluetooth Baseband Core ............................................. 14 Link Control Layer ..................................................... 14 Test Mode Support.................................................... 15 Frequency Hopping Generator.................................. 15 Microprocessor Unit....................................................... 16 NVRAM Configuration Data and Storage.................. 16 One-Time Programmable Memory............................ 16 External Reset (XRES).............................................. 17 Integrated Radio Transceiver ........................................ 18 Transmitter Path........................................................ 18 Digital Modulator ....................................................... 18 Digital Demodulator and Bit Synchronizer................. 18 Power Amplifier ......................................................... 18 Receiver Path............................................................ 18 Digital Demodulator and Bit Synchronizer................. 18 Receiver Signal Strength Indicator............................ 18 Local Oscillator Generation ....................................... 18 Calibration ................................................................. 18 Internal LDO.............................................................. 19 Collaborative Coexistence............................................. 19 Global Coexistence Interface ........................................ 19 SECI I/O .................................................................... 19 Peripheral Transport Unit .............................................. 19 Cypress Serial Communications Interface ................ 19 UART Interface.......................................................... 20 Peripheral UART Interface ........................................ 21 PCM Interface.................................................................. 21 Slot Mapping ............................................................. 21 Frame Synchronization ............................................. 21 Data Formatting......................................................... 21 Burst PCM Mode ....................................................... 21 Clock Frequencies.......................................................... 21 GPIO Port ........................................................................ 22 PWM................................................................................. 22 Triac Control/PWM ......................................................... 23 Serial Peripheral Interface ............................................. 23 Power Management Unit................................................ 23 RF Power Management ............................................ 23 Host Controller Power Management ......................... 24 BBC Power Management.......................................... 24 Electrical Characteristics............................................... 25 RF Specifications ........................................................... 27 Timing and AC Characteristics ..................................... 30 UART Timing............................................................. 30 SPI Timing................................................................. 31 BSC Interface Timing ................................................ 33 PCM Interface Timing................................................ 34 I2S Interface Timing .................................................. 38 Environmental Specifications ....................................... 39 Environmental Compliance ....................................... 39 RF Certification.......................................................... 39 Safety Certification .................................................... 39 Environmental Conditions ......................................... 39 ESD and EMI Protection ........................................... 39 Regulatory Information.................................................. 40 FCC........................................................................... 40 ISED.......................................................................... 41 European Declaration of Conformity ......................... 42 MIC Japan................................................................. 42 Packaging........................................................................ 43 Ordering Information...................................................... 45 Acronyms........................................................................ 46 Document Conventions ................................................. 47 Units of Measure ....................................................... 47 Document History Page................................................. 48 Sales, Solutions, and Legal Information ...................... 49 Worldwide Sales and Design Support....................... 49 Products .................................................................... 49 PSoC Solutions ...................................................... 49 Cypress Developer Community................................. 49 Technical Support ..................................................... 49 Document Number: 002-19525 Rev. **
Page 3 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Overview Functional Block Diagram Figure 1 illustrates the CYBT-343026-01 functional block diagram. Figure 1. Functional Block Diagram Module Description The CYBT-X430XX-01 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna connection location dimensions Length (X) Width (Y) Length (X) Width (Y) Height (H) PCB thickness Height (H) Shield height Maximum component height Height (H) Total module thickness (bottom of module to highest component) Height (H) 12.00 0.15 mm 15.50 0.15 mm 12.0 mm 4.62 mm 0.50 0.05 mm 1.45 mm typical 1.45 mm typical 1.95 mm typical See Figure 2 for the mechanical reference drawing for CYBT-X430XX-01. Document Number: 002-19525 Rev. **
Page 4 of 49 PRELIMINARY Figure 2. Module Mechanical Drawing CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Side View Top View (See Bottom View (Seen from Bottom) Notes 2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Recommended Host PCB Layout on page 7. 3. The CYBT-343026-01 includes castellated pad connections, denoted as the circular openings at the pad location above. Document Number: 002-19525 Rev. **
Page 5 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Pad Connection Interface As shown in the bottom view of Figure 2 on page 5, the CYBT-X430XX-01 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-X430XX-01 module. Table 2. Connection Description Name Connections SP 24 Connection Type Pad Length Dimension Pad Width Dimension Solder Pads 1.02 mm 0.71 mm Pad Pitch 1.27 mm Figure 3. Solder Pad Dimensions (Seen from Bottom To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module placement best practices. Figure 4. Recommended Host PCB Keep Out Area Around the CYBT-X430XX-01 Antenna Document Number: 002-19525 Rev. **
Page 6 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Recommended Host PCB Layout Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-X430XX-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-X430XX-01 Host Layout (Dimensioned) Figure 6. CYBT-X430XX-01 Host Layout (Relative to Origin) Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-19525 Rev. **
Page 7 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 3 provides the center location for each solder pad on the CYBT-X430XX-01. All dimensions reference the to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location Solder Pad
(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Location (X,Y) from Orign (mm)
(0.38, 5.04)
(0.38, 6.26)
(0.38, 7.48)
(0.38, 8.70)
(0.38, 9.92)
(0.38, 11.14)
(0.38, 12.35)
(0.38, 13.57)
(1.73, 15.11)
(2.95, 15.11)
(4.17, 15.11)
(5.39, 15.11)
(6.61, 15.11)
(7.83, 15.11)
(9.05, 15.11)
(10.27, 15.11)
(11.62, 13.57)
(11.62, 12.35)
(11.62, 11.14)
(11.62, 9.92)
(11.62, 8.70)
(11.62, 7.48)
(11.62, 6.26)
(11.62, 5.04) Dimension from Orign (mils)
(14.96, 198.42)
(14.96, 246.46)
(14.96, 294.49)
(14.96, 342.52)
(14.96, 390.55)
(14.96, 438.58)
(14.96, 486.22)
(14.96, 534.25)
(68.11, 594.88)
(116.14, 594.88)
(164.17, 594.88)
(212.20, 594.88)
(260.24, 594.88)
(308.27, 594.88)
(356.30, 594.88)
(404.33, 594.88)
(457.48, 534.25)
(457.48, 486.22)
(457.48, 438.58)
(457.48, 390.55)
(457.48, 342.52)
(457.48, 294.49)
(457.48, 246.46)
(457.48, 198.42) Top View (Seen on Host PCB) Document Number: 002-19525 Rev. **
Page 8 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Module Connections Table 4 and Table 5 detail the solder pad connection definitions and available functions for the pad connections for the CYBT-34302X-01 and CYBT-143038-01 respectively. Table 4 and Table 5 lists the solder pads on the CYBT-X430XX-01 modules, the silicon device pin, and denotes what functions are available for each solder pad. The CYBT-343026-01 and CYBT-343029-01 share a common footprint. Table 4. CYBT-343026-01 and CYBT-343029-01 Solder Pad Connection Definitions Pad Pad Name UART SPI1 I2C QD2 CLK/XTAL GPIO PUART_TX/P0 PUART_RX/P34 SPI1_MOSI/P0
(master/slave) P0/P34 I2C_SCL XRES I2C_SDA P2/P37/P28 PUART_RX/P2 ADC IN29/P0 IN5/P34 DY0/P34 SCL External Reset (Active Low) SDA SPI1_CS(slave)/P2 SPI1_MOSI(master)/P2 SPI1_MISO(slave)/P37 No Connect (Used for on-module memory SPI interface for CYBT-343026-01) ACK1/P37 SCL/P37 IN11/P28 IN2/P37 DX0/P2 OC2/P28 DZ1/P37 Ground No Connect (Used for on-module memory SPI interface for CYBT-343026-01) No Connect (Used for on-module memory SPI interface for CYBT-343026-01) No Connect (Used for on-module memory SPI interface for CYBT-343026-01) 3 3 Other PCM_Sync I2S_WS
~TX_PD/P36 SPI1_CLK/P36 SPI1_MOSI/P38
(master/slave) SPI1_MISO/P25
(master/slave) SPI1_CS/P32
(slave) SPI1_CS/P6
(slave) SPI1_MOSI/P6
(master/slave) SPI1_CLK/P24
(master/slave) PUART_RX/P25 PUART_TX/P32 PUART_RTS/P6 PUART_TX/P31 PUART_RX/P4 PUART_TX/P24 IN3/P36 IN1/P38 DZ0/P36 ACLK0/P36 IN7/P32 DX0/P32 ACLK0/P32 Ground IN8/P31 DZ0/P6 DY0/P4 UART Transmit Data UART Clear To Send Input UART Request To Send Output IN9/P30 UART Receive Data VDDIN (3.0V ~ 3.6V)
(DevWake 3
)
(HostWak 3 e) 3
(GCI) Ext LPO In
(CLK_RE 3 Q) 3
(GCI) GPIO_7 PUART_RTS/P30 UART_RXD VDDIN GPIO_3 UART_RX/P33 GPIO_6 GND SPI1_MOSI/P27
(master/slave) SPI1_MOSI/P33
(slave) SPI1_CS/P26
(slave) IN6/P33 OC1/P27 DX1/P33 ACLK1/P33 3 PWM2/P27 IN24/P11 OC0/P26 Ground 3
(GCI) PWM1/P26 1. The CYBT-343026-01 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface. 2. Quadrature Decoder Document Number: 002-19525 Rev. **
Page 9 of 49 SPI2_CS_N GND SPI2_MISO SPI2_MOSI SPI2_CLK GPIO_0 GPIO_1 GND GPIO_4 P4/P24 UART_TXD UART_CTS UART_RTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 SPI1_CS(slave)/P2 SPI1_MOSI(master)/
SPI1_MISO(slave)/P3 P2 7 SPI2 active-low chip select SPI2_MISO
(master) SPI2_MOSI
(master) SPI2_CLK
(master) SPI1_CLK/P36 SPI1_MOSI/P38
(master/slave) SPI1_MISO/P25
(master/slave) SPI1_CS/P32
(slave) SPI1_CS/P6
(slave) SPI1_MOSI/P6
(master/slave) SPI1_CLK/P24
(master/slave) ADC IN29/P0 IN5/P34 QD2 CLK/XTAL DY0/P34 GPIO 3 Other PCM_Sync I2S_WS External reset I2C SCL SDA SCL/P37 IN11/P28 IN2/P37 DX0/P2 OC2/P28 DZ1/P37 ACK1/P37 3 Ground SCL SDA IN3/P36 IN1/P38 DZ0/P36 ACLK0/P36 3
(DevWake)
~TX_PD/P36 IN7/P32 DX0/P32 ACLK0/P32 3
(Host Wake) Ground IN8/P31 DZ0/P6 DY0/P4 UART transmit data UART clear to send input UART request to send output IN9/P30 UART receive data VDDIN (3.0V ~ 3.6V) 3
(GCI) Ext LPO In 3
(CLK_REQ) 3
(GCI) Table 5. CYBT-143038-01 Solder Pad Pad Pad Name UART SPI1 PUART_TX/P0 PUART_RX/P34 SPI1_MOSI/P0
(master/slave) P0/P34 I2C_SCL XRES I2C_SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P2/P37/P28 PUART_RX/P2 SPI2_CS_N GND SPI2_MISO SPI2_MOSI SPI2_CLK GPIO_0 GPIO_1 GND GPIO_4 P4/P24 UART_TXD UART_CTS UART_RTS PUART_RX/P25 PUART_TX/P32 PUART_RTS/P6 PUART_TX/P31 PUART_RX/P4 PUART_TX/P24 GPIO_7 PUART_RTS/P30 UART_RXD VDDIN GPIO_3 UART_RX/P33 GPIO_6 GND SPI1_MOSI/P27
(master/slave) SPI1_MOSI/P33
(slave) SPI1_CS/P26
(slave) IN6/P33 OC1/P27 DX1/P33 ACLK1/P33 3 PWM2/P27 IN24/P11 OC0/P26 Ground 3
(GCI) PWM1/P26 1. The CYBT-143038-01 contains two SPI peripherals, SPI1 and SPI2. SPI1 supports only master or slave modes, whereas SPI2 supports master only mode. The con-
nections shown in Table 5 above detail the SPI function for the given mode shown in parenthesis. If external memory is used with the CYBT-143038-01, then SPI2 should be used as the interface. 2. Quadrature Decoder Document Number: 002-19525 Rev. **
Page 10 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Connections and Optional External Components Power Connections (VDDIN) The CYBT-X430XX-01 contains one power supply connection, VDDIN. VDDIN accepts a supply input range of 2.3 V to 3.6 V for CYBT-34302X-01 and 1.62 V to 3.6 V for the CYBT-143038-01. Table 12 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 12. It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330, 100 MHz. External Reset (XRES) The CYBT-X430XX-01 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-X430XX-01 module (solder pad 3). The CYBT-X430XX-01 module does not require an external pull-up resistor on the XRES input During power on operation, the XRES connection to the CYBT-X430XX-01 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:
n The host device should connect a GPIO to the XRES of Cypress CYBT-X430XX-01 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDDIN is stable. n The XRES release timing may be controlled by a external voltage detection circuit. XRES should be released 50 ms after VDD is stable. Refer to Figure 10 on page 17 for XRES operating and timing requirements during power on events. Multiple-Bonded GPIO Connections The CYBT-X430XX-01 contains GPIO which are multiple-bonded at the silicon level. If any of these dual-bonded GPIO are used, only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio SDK. For details on the features and functions that each of these multiple-bonded GPIO provide, please refer to Table 4 and Table 5. Using CYBT-143038-01 with External Flash The CYBT-143038-01 does not contain any on-module non-volatile memory. If desired, the CYBT-143038-01 can be used with an external memory device (SFLASH). If EEPROM is used as an external memory device with I2C interface, module solder pads 4 (SDA) and 2 (SCL) must be used as the I2C interface. If using external SFLASH as the memory interface, SPI2 (master) must be used as the interface to the SFLASH device. The specific GPIO required and the applicable SPI signal is shown below. These are the same signals used for SFLASH interface on the CYBT-343026-01. 1. SPI signal MOSI: Module Solder Pad 9, silicon connection SPI2_MOSI_I2C_SDA 2. SPI signal MISO: Module Solder Pad 8, silicon connection SPI2_MISO_I2C_SCL 3. SPI Signal CLK: Module Solder Pad 10 silicon connection SPI2_CLK 4. SPI Signal CS: Module Solder Pad 6, silicon connection SPI2_CSN Document Number: 002-19525 Rev. **
Page 11 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Figure 8 illustrates the CYBT-343026-01 schematic. Figure 8. CYBT-343026-01 Schematic Diagram Document Number: 002-19525 Rev. **
Page 12 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Critical Components List Table 6 details the critical components used in the CYBT-X430XX-01 module. Table 6. Critical Component List Component Reference Designator Description Silicon Silicon Crystal U1 U2 Y1 49-pin FBGA BT/BLE Silicon Device - CYW20706 8-pin TDF8N, 512KSerial Flash ( CYBT-34302X-01) 24.000 MHz, 12PF Antenna Design Table 7 details trace antenna used in the CYBT-X430XX-01 module. For more information, see Table 7. Table 7. Trace Antenna Specifications Item Frequency Range Peak Gain Return Loss 2400 2500 MHz 0.5 dBi typical 10 dB minimum Description Document Number: 002-19525 Rev. **
Page 13 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:
n Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. n Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. Bluetooth 4.2 Features CYBT-X430XX-01 supports all Bluetooth 4.2 and legacy features, with the following benefits n Dual-mode Bluetooth (BT and BLE operation) n Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode. n Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment. n Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. n Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required. n Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link timeout supervision. n Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements. n Secure connections (BR/EDR) n Fast advertising interval n Piconet clock adjust n Connectionless broadcast n LE privacy v1.1 n Low duty cycle directed advertising n LE dual mode topology Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth Link Controller. n States:
p Standby p Connection p Page p Page Scan p Inquiry p Inquiry Scan p Sniff p Advertising p Scanning Document Number: 002-19525 Rev. **
Page 14 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Test Mode Support The CYBT-X430XX-01 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYBT-X430XX-01also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:
n Fixed frequency carrier wave (unmodulated) transmission p Simplifies some type-approval measurements (Japan) p Aids in transmitter performance analysis n Fixed frequency constant receiver mode p Receiver output directed to I/O pin p Allows for direct BER measurements using standard RF test equipment p Facilitates spurious emissions testing for receive mode n Fixed frequency constant transmission p 8-bit fixed pattern or PRBS-9 p Enables modulated signal measurements with standard RF test equipment. Frequency Hopping Generator The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth clock, and device address. Document Number: 002-19525 Rev. **
Page 15 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Microprocessor Unit The microprocessor unit in CYBT-X430XX-01 runs software from the link control (LC) layer up to the host controller interface (HCI). The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code. The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the internal ROM. External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an external serial flash memory. NVRAM Configuration Data and Storage NVRAM contains configuration information about the customer application, including the following:
n Fractional-N information n BD_ADDR n UART baud rate n SDP service record n File system information used for code, code patches, or data. The CYBT-X430XX-01 can use SPI Flash or I2C EEPROM/serial flash for NVRAM storage.. One-Time Programmable Memory The microprocessor unit in CYBT-X430XX-01 includes 2 Kbytes of one-time programmable (OTP) memory allow manufacturing customization and to avoid the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after the CYBT-X430XX-01 boots and is ready for host transport communication. The OTP contents are limited to:
n Parameters required prior to downloading the user configuration to RAM. n Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key). Document Number: 002-19525 Rev. **
Page 16 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 External Reset (XRES) The CYBT-X430XX-01 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external active low reset signal, XRES, can be used to put the CYBT-X430XX-01 in the reset state. The XRES pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it. Figure 9. External Reset Internal Timing External Reset (XRES) Recommended External Components and Proper Operation During a power on event, the XRES line of the CYBT-X430XX-01 is required to be held low 50 ms after the VDD power supply input to the module is stable. Refer to Figure 10 for the Power On XRES timing operation. This power on operation can be accomplished in the following ways:
n A host device should connect a GPIO to the XRES of Cypress CYBT-X430XX-01 module and pull XRES low until VDD is stable. XRES can be released after VDD is stable. n If the XRES connection of the CYBT-X430XX-01 module is not used in the application, a 0.47uF capacitor may be connected to the XRES solder pad of the CYBT-X430XX-01. n The XRES release timing can also be controlled via a external voltage detection circuit. Figure 10. Power On External Reset (XRES) Operation Document Number: 002-19525 Rev. **
Page 17 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Integrated Radio Transceiver The CYBT-X430XX-01 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. The CYBT-X430XX-01 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR) specification and meets or exceeds the requirements to provide the highest communication link quality of service. Transmitter Path The CYBT-X430XX-01 a fully integrated z6ro-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the BLE specification. The transmitter PA bias can also be adjusted to provide Bluetooth class 1 or class 2 operation. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and 8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bitsyn-
chronization algorithm. Power Amplifier The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset appli-
cations in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. Receiver Path The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation, enables the CYBT-X430XX-01 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYBT-X430XX-01 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator Generation The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYBT-X430XX-01 uses an internal loop filter. Calibration The CYBT-X430XX-01 radio transceiver features an auotmated calibration scheme that is fully self-contained in the radio. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the perfor-
mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops, and calibrates for temperature variations as the device cools and heats during normal operation in its environment.. Document Number: 002-19525 Rev. **
Page 18 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Internal LDO The microprocessor in CYBT-X430XX-01 uses two LDOs - one for 1.2V and the other for 2.5V. The 1.2V LDO provides power to the baseband and radio and the 2.5V LDO powers the PA. Collaborative Coexistence The CYBT-X430XX-01 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions. Global Coexistence Interface The CYBT-X430XX-01 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a 2-wire interface. The following key features are associated with the interface:
n Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input
(GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function. n It supports generic UART communication between WLAN and Bluetooth devices. n To conserve power, it is disabled when inactive. n It supports automatic resynchronization upon waking from sleep mode. n It supports a baud rate of up to 4 Mbps. SECI I/O The microprocessor in CYBT-X430XX-01 have dedicated GCI_SECI_IN and GCI_SECI_OUT pins. The two pin functions can be mapped to the folloiwng connections on the Cypress module:
n GCI_SECI_IN: Module pad Cypress Global Coexistence Interface (GCI) GPIO (Pad 4/5/6/7) . Pin function mapping is controlled by the configuration file that is stored in either NVRAM or downloaded directly into on-chip RAM from the host. Peripheral Transport Unit Cypress Serial Communications Interface The CYBT-X430XX-01 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible wait-state insertion by either master or slave devices. The following transfer clock rates are supported by the BSC:
n 100 kHz n 400 kHz n 800 kHz (not a standard I2C-compatible speed.) n 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.) n The following transfer types are supported by the BSC:
n Read (Up to 127 bytes can be read.) n Write (Up to 127 bytes can be written.) n Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written.) n Write-then-Read (Up to127 bytes can be written and up to 127 bytes can be read.) Hardware controls the transfers, requiring minimal firmware setup and supervision. The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors external to the CYBT-X430XX-01 are required on both the SCL and SDA pad for proper operation. Document Number: 002-19525 Rev. **
Page 19 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 UART Interface The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYBT-X430XX-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate of the CYBT-X430XX-01UART is controlled by two values. The first is aU ART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. Table 8 contains example values to generate common baud rates with a 24 MHz UART clock. Table 8. Common Baud Rate Examples, 24 MHz Clock Baud Rate (bps) Baud Rate Adjustment High Nibble Low Nibble 3M 2M 1M 921600 460800 230400 115200 57600 38400 0xFF 0XFF 0X44 0x05 0x02 0x04 0x00 0x00 0x01 0xF8 0XF4 0XFF 0x05 0x02 0x04 0x00 0x00 0x00 Mode High rate High rate Normal Normal Normal Normal Normal Normal Normal Table 9 contains example values to generate common baud rates with a 48 MHz UART clock. Table 9. Common Baud Rate Examples, 48 MHz Clock Baud Rate (bps) High Rate Low Rate 6M 4M 3M 2M 1.5M 1M 921600 230400 115200 57600 38400 0xFF 0xFF 0x0 0x44 0x0 0x0 0x22 0x0 0x1 0x1 0x11 0xF8 0xF4 0xFF 0xFF 0xFE 0xFD 0xFD 0xF3 0xE6 0xCC 0xB2 Mode High rate High rate Normal Normal Normal Normal Normal Normal Normal Normal Normal Error (%) 0.00 0.00 0.00 0.16 0.16 0.16 0.16 0.16 0.00 Error (%) 0 0 0 0 0 0 0.16 0.16 0.08 0.04 0 Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYBT-X430XX-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within 2%
Document Number: 002-19525 Rev. **
Page 20 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Peripheral UART Interface The CYBT-X430XX-01 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 5 and Table 6. Table 10. CYBT-X430XX-01 Peripheral UART Pin Name pUART_TX pUART_RX pUART_CTS_N pUART_RTS_N Configured pin name P0 (
P31 P2 P33 P3 P6 P30 PCM Interface The CYBT-X430XX-01 includes a PCM interface that shares pins with the I2S interface. The PCM Interface on the CYBT-013033-01 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-013033-01 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-X430XX-01. Slot Mapping The CYBT-X430XX-01 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYBT-X430XX-01 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The CYBT-X430XX-01 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYBT-X430XX-01 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first. Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Clock Frequencies The CYBT-X430XX-01 has an integrated 24 MHz crystal on the module. There is no need to add an additional crystal oscillator. Document Number: 002-19525 Rev. **
Page 21 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 GPIO Port The CYBT-X430XX-01 has 24 general-purpose I/Os (GPIOs). All GPIOs support programmable pull-ups and are capable of driving up to 8 mA at 3.3V or 4 mA at 1.8V, except chip P26, P27, P28, and P29, which are capable of driving up to 16 mA at 3.3V or 8 mA at 1.8V. The Following GPIOs on the module pads are available:
n PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available) n PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available) n PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available) n PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available) n PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available) n PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available) n PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available) n PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available) n PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available) n PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available) n PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only on All of these pins can be programmed as ADC inputs. Port 26Port 29 in PAD 23/PAD 22/PAD 5/PAD 2 P[26:29] in PAD 23/PAD 22/PAD 5/PAD 2 consists of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have PWM functionality, which can be used for LED dimming. For a description of the capabilities of all GPIOs, see Table 4 and Table 5 . PWM The CYBT-X430XX-01 has four PWMs. The PWM module consists of the following:
n PWM0-3 n The following GPIOs can be mapped as PWMs, module pad shown in [ ]:
p P26 on P12/P26 [Pad 5]
p P27 on P11/P27 [Pad 4]
p P14 on P14/P38 [Pad 7]
p P13 on P13/P28 [Pad 8]
n PWM1-4: Each of the four PWM channels contains the following registers:
p 10-bit initial value register (read/write) p 10-bit toggle register (read/write) p 10-bit PWM counter value register (read) n PWM configuration register shared among PWM1-4 (read/write). This 12-bit register is used:
p To configure each PWM channel p To select the clock of each PWM channel p To change the phase of each PWM channel Figure 11 shows the structure of one PWM. Document Number: 002-19525 Rev. **
Page 22 of 49 PRELIMINARY Figure 11. PWM Block Diagram CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Triac Control/PWM The CYBT-X430XX-01 includes hardware support for zero-crossing detection and trigger control for up to two triacs (PAD 22/23). The CYBT-X430XX-01 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero crossing. This allows the CYBT-X430XX-01 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an input event. The zero-crossing hardware includes an option to suppress glitches. Serial Peripheral Interface The CYBT-X430XX-01 has two independent SPI interfaces. One is a master-only interface (SPI2) and the other (SPI1) can be either a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-X430XX-01 has optional I/O ports that can be configured individually and separately for each functional pin. The CYBT-X430XX-01 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYBT-X430XX-01 can also act as an SPI slave device that supports a 1.8V or 3.3V SPI master. SPI voltage depends on VDD; therefore, it defines the type of devices that can be supported. Power Management Unit The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver, which then processes the power-down functions accordingly. Document Number: 002-19525 Rev. **
Page 23 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Host Controller Power Management Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep sleep (HIDOFF) mode. BBC Power Management There are several low-power operations for the BBC:
n Physical layer packet handling turns RF on and off dynamically within packet TX and RX. n Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBT-X430XX-01 runs on the Low Power Oscillator and wakes up after a predefined time period. The CYBT-X430XX-01 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
n Active mode n Idle mode n Sleep mode n HIDOFF (Deep Sleep) mode The CYBT-X430XX-01 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. In HIDOFF (Deep Sleep) mode, the CYBT-X430XX-01 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. Document Number: 002-19525 Rev. **
Page 24 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Electrical Characteristics Table 11 shows the maximum electrical rating for voltages referenced to VDD pin. Table 11. Maximum Electrical Rating Rating VDDIN Voltage on input or output pin Operating ambient temperature range Storage temperature range Symbol Topr Tstg Value 3.795 VSS 0.3 to VDD + 0.3 30 to +85 40 to +125 Table 12 shows the power supply characteristics for the range TJ = 0 to 125 C. Table 12. Power Supply Parameter VDDIN VDDIN Description Power Supply Input for CYBT-34302X-01 Power Supply Input for CYBT-143038-01 Minimum1 Typical Maximum1 2.30 1.62 3.6 3.6 1. Overall performance degrades beyond minimum and maximum supply voltages. Table 13 shows the specifications for the digital voltage levels. Table 13. Digital Levels Characteristics Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance (VDDMEM domain) Symbol VIL VIH VOL VOH CIN Min 2.0 VDD 0.4 Typ Table 9 shows the current consumption measurements Table 14. Bluetooth, BLE, BR and EDR Current Consumption, Class 1 Remarks BLE Connected 600 ms interval Unconnectable 1.00 sec No devices present. A 1.28 second interval with a scan window of 11.25 ms Mode 3DH5/3DH5 n BLE n BLE ADV n BLE Scan n DM1/DH1 n DM3/DH3 n DM5/DH5 HIDOFF Page scan Deep sleep Periodic scan rate is 1.28 sec DMx/DHx Receive Max 0.8 0.4 0.4 Typ. 37.10 211 176 355 32.15 38.14 38.46 2.69 0.486 n 1 Mbps n EDR Peak current level during reception of a basic-rate packet. Peak current level during the reception of a 2 or 3 Mbps rate packet. 26.373 26.373 Unit V V C C Unit V V Unit V V V V pF Unit mA A
?A
?A mA mA mA
?A mA mA mA Document Number: 002-19525 Rev. **
Page 25 of 49 PRELIMINARY Table 14. Bluetooth, BLE, BR and EDR Current Consumption, Class 1 CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 n 11.25 ms n 22.5 ms n 495.00 ms n 1 Mbps n EDR Sniff Slave Based on one attempt and no timeout. Transmit 4.95 2.6 254 Peak current level during the transmission of a basic-rate packet: GFSK output power = 10 dBm. Peak current level during the transmission of a 2 or 3 Mbps rate packet. EDR output power = 8 dBm. 60.289 52.485 Table 15. Bluetooth and BLE Current Consumption, Class 2 (0 dBm) Mode 3DH5/3DH5 n BLE ADV n BLE Scan n DM1/DH1 n DM3/DH3 n DM5/DH5 Remarks BLE Unconnectable 1.00 sec No devices present. A 1.28 second interval with a scan window of 11.25 ms DMx/DHx Typ. 31.57 174 368 27.5 31.34 32.36 mA mA
?A mA mA Unit mA
?A
?A mA mA mA Document Number: 002-19525 Rev. **
Page 26 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 RF Specifications All specifications in Table 16 are for industrial temperatures and are single-ended. Unused inputs are left open. Table 16. Receiver RF Specifications Parameter Conditions Minimum Typical 1 Maximum Unit Frequency range RX sensitivity 2 Maximum input Maximum input C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I image channel C/I 1 MHz adjacent to image channel C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I > 3 MHz adjacent channel C/I Image channel C/I 1 MHz adjacent to image channel General 2402 GFSK, 0.1% BER, 1 Mbps LE GFSK, 0.1% BER, 1 Mbps
/4-DQPSK, 0.01% BER, 2 Mbps 8-DPSK, 0.01% BER, 3 Mbps GFSK, 1 Mbps
/4-DQPSK, 8-DPSK, 2/3 Mbps Interference Performance GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER GFSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER 8-DPSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER 8-DPSK, 0.1% BER Out-of-Band Blocking Performance (CW)3 30 MHz2000 MHz 20002399 MHz 24983000 MHz 3000 MHz12.75 GHz 0.1% BER 0.1% BER 0.1% BER 0.1% BER 93.5 96.5 95.5 89.5 9.5 5 40 49 27 37 11 8 40 50 27 40 17 5 40 47 20 35 10.0 27 27 10.0 2480 20 20 11 0 30.0 40.0 9.0 20.0 13 0 30.0 40.0 7.0 20.0 21 5 25.0 33.0 0 13.0 MHz dBm dBm dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm dBm dBm Document Number: 002-19525 Rev. **
Page 27 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 16. Receiver RF Specifications (continued) Parameter Conditions Minimum Typical 1 Maximum Unit Out-of-Band Blocking Performance, Modulated Interferer 776764 MHz 824849 MHz 18501910 MHz 824849 MHz 880915 MHz 17101785 MHz 18501910 MHz 18501910 MHz 19201980 MHz BT, Df = 5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 65 MHz to 108 MHz 746 MHz to 764 MHz 851894 MHz 925960 MHz 18051880 MHz 19301990 MHz 21102170 MHz CDMA CDMA CDMA EDGE/GSM EDGE/GSM EDGE/GSM EDGE/GSM WCDMA WCDMA FM Rx CDMA CDMA EDGE/GSM EDGE/GSM PCS WCDMA Intermodulation Performance5 Spurious Emissions6 39.0 104 10<Super-
script>4 23<Super-
script>4 10<Super-
script>4 10<Super-
script>4 23<Super-
script>4 23<Super-
script>4 23<Super-
script>4 23<Super-
script>4 147 147 147 147 147 147 147 62 47 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz 1. Typical operating conditions are 1.22V operating voltage and 25C ambient temperature. 2. The receiver sensitivity is measured at BER of 0.1% on the device interface. 3. Meets this specification using front-end band pass filter. 4. Numbers are referred to the pin output with an external BPF filter. 5. f0 = -64 dBm Bluetooth-modulated signal, f1 = 39 dBm sine wave, f2 = 39 dBm Bluetooth-modulated signal, f0 = 2f1 f2, and |f2 f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. Includes baseband radiated emissions. 6. Document Number: 002-19525 Rev. **
Page 28 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 17. Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit General 2402 2 Modulation Accuracy 10 10 In-Band Spurious Emissions Out-of-Band Spurious Emissions Frequency range Class1: GFSK Tx power1 Class1: EDR Tx power2 Class 2: GFSK Tx power Power control step
/4-DQPSK Frequency Stability
/4-DQPSK RMS DEVM
/4-QPSK Peak DEVM
/4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM 8-DPSK 99% DEVM 1.0 MHz < |M N| < 1.5 MHz 1.5 MHz < |M N| < 2.5 MHz
|M N| > 2.5 MHz 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz 1. TBD dBm output for GFSK measured with PAVDD = 2.5V. 2. TBD dBm output for EDR measured with PAVDD = 2.5V. 3. Maximum value is the value required for Bluetooth qualification. 4. Meets this spec using a front-end band-pass filter. Table 18. BLE RF Specifications 12 9 2 4 2480 8 10 20 35 30 10 13 25 20 26 20 40 36.03 30.0<Super-
script>3, 4 47.0 47.0 MHz dBm dBm dBm dB kHz
%
%
%
kHz
%
%
%
dBc dBm dBm dBm dBm dBm dBm Parameter Conditions Minimum Typical Maximum N/A GFSK, 0.1% BER, 1 Mbps Frequency range Rx sense1 Tx power2 Mod Char: Delta F1 average Mod Char: Delta F2 max3 Mod Char: Ratio 1. Dirty Tx is Off. 2. The BLE Tx power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE Tx power 225 99.9 0.8 275 N/A N/A N/A N/A 9 255 96.5 2402 2480 0.95 at the antenna port cannot exceed the 10 dBm EIRP specification limit. 3. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Unit MHz dBm dBm kHz
%
%
Document Number: 002-19525 Rev. **
Page 29 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 19. UART Timing Specifications Reference Characteristics 1 2 3 Delay time, UART_CTS_N low to UART_TXD valid Setup time, UART_CTS_N high before midpoint of stop bit Delay time, midpoint of stop bit to UART_RTS_N high Min Max 24 10 2 Unit Baud out cycles ns Baud out cycles Figure 12. UART Timing Document Number: 002-19525 Rev. **
Page 30 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 SPI Timing The SPI interface supports clock speeds up to 12 MHz Table 20 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively. Table 20. SPI Mode 0 and 2 Reference Characteristics Minimum Maximum Unit 1 2 3 4 5 6 7 8 Time from slave assert SPI_INT to master assert SPI_CSN (Direc-
tRead) Time from master assert SPI_CSN to slave assert SPI_INT (Direct-
Write) Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions 0 0 20 8 8 0 0 1 SCK
?
?
?
<FmNumerator
>1/<FmDeno minator>2 SCK
<FmNumerator
>1/<FmDeno minator>2 SCK 100
?
?
ns ns ns ns ns ns ns ns Figure 13. SPI Timing Mode 0 and 2 Table 21 and Figure 14 show the timing requirements when operating in SPI Mode 1 and 3. Document Number: 002-19525 Rev. **
Page 31 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 21. SPI Mode 1 and 3 Reference Characteristics Minimum Maximum Unit 1 2 3 4 5 6 7 8 Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead) Time from master assert SPI_CSN to slave assert SPI_INT (DirectWrite) Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions Figure 14. SPI Timing Mode 1 and 3 0 0 20 8 8 0 0 1 SCK
?
?
?
<FmNumerator>1
/<FmDenomi-
nator>2 SCK
<FmNumerator>1
/<FmDenomi-
nator>2 SCK 100
?
?
ns ns ns ns ns ns ns ns Document Number: 002-19525 Rev. **
Page 32 of 49 PRELIMINARY BSC Interface Timing Table 22. BSC Interface Timing Specifications Reference Characteristics Clock frequency START condition setup time START condition hold time Clock low time Clock high time Data input hold time1 Data input setup time STOP condition setup time Output valid from clock Bus free time2 1 2 3 4 5 6 7 8 9 10 CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Min 650 280 650 280 0 100 280 650 Max 100 400 800 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns 1. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2. Time that the cbus must be free before a new transaction can start. Figure 15. BSC Interface Timing Diagram Document Number: 002-19525 Rev. **
Page 33 of 49 PRELIMINARY PCM Interface Timing Short Frame Sync, Master Mode Figure 16. PCM Timing Diagram (Short Frame Sync, Master Mode) CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 23. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Reference Characteristics Minimum Typical Maximum 1 2 3 4 5 6 7 8 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 20.0 20.0 0 0.4 16.9 25.0 0.4 20.0 5.7 5.6 5.6 Unit MHz ns ns ns ns ns ns ns Document Number: 002-19525 Rev. **
Page 34 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Short Frame Sync, Slave Mode Figure 17. PCM Timing Diagram (Short Frame Sync, Slave Mode) Table 24. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Minimum Characteristics Reference 1 2 3 4 5 6 7 8 9 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance TBD TBD TBD TBD TBD TBD TBD TBD Typical Maximum TBD TBD TBD Unit MHz ns ns ns ns ns ns ns ns Document Number: 002-19525 Rev. **
Page 35 of 49 PRELIMINARY Figure 18. PCM Timing Diagram (Long Frame Sync, Master Mode) CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Table 25. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Reference Characteristics Minimum 1 2 3 4 5 6 7 8 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC delay PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance TBD TBD TBD TBD TBD TBD TBD Typical Maximum TBD TBD TBD TBD Unit MHz ns ns ns ns ns ns ns Document Number: 002-19525 Rev. **
Page 36 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Long Frame Sync, Slave Mode Figure 19. PCM Timing Diagram (Long Frame Sync, Slave Mode) Table 26. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Reference Characteristics Minimum 1 2 3 4 5 6 7 8 9 PCM bit clock frequency PCM bit clock LOW PCM bit clock HIGH PCM_SYNC setup PCM_SYNC hold PCM_OUT delay PCM_IN setup PCM_IN hold Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance TBD TBD TBD TBD TBD TBD TBD TBD Typical Maximum TBD TBD TBD Unit MHz ns ns ns ns ns ns ns ns Document Number: 002-19525 Rev. **
Page 37 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 I2S Interface Timing The I2S interface supports both master and slave modes. The I2S signals are:
n I2S clock: I2S SCK n I2S Word Select: I2S WS n I2S Data Out: I2S SDO n I2S Data In: I2S SDI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYBT-013033-01 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. The clock rate in master mode is either of the following:
n 48 kHz x 32 bits per frame = 1.536 MHz n 48 kHz x 50 bits per frame = 2.400 MHz The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. Timing values specified in Table 27 are relative to high and low threshold levels. Table 27. Timing for I2S Transmitters and Receivers Transmitter Receiver Clock Period T HIGH tHC LOWtLC HIGH tHC LOW tLC Rise time tRC Delay tdtr Hold time thtr Lower LImit Min Max Ttr Master Mode: Clock generated by transmitter or receiver Lower Limit Min Max Tr Upper Limit Min Max 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr Slave Mode: Clock accepted by transmitter or receiver 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.15Ttr 0 Upper Limit Min Max Notes 1 2 2 3 3 4 5 5 Transmitter 0.8T Receiver Setup time tsr Hold time thr 1. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum 3. periods are greater than 0.35Tr, any clock that meets the requirements can be used. exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. setup time. 4. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not 5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient 0 6 0.2Tr 6 6. The data setup and hold time must not be less than the specified receiver setup and hold time. Document Number: 002-19525 Rev. **
Page 38 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Environmental Specifications Environmental Compliance This CYBT-X430XX-01 BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBT-X430XX-01 module will be certified under the following RF certification standards at production release. n FCC: WAP3026 n CE n IC: 7922A-3026 n MIC: TBD Safety Certification The CYBT-X430XX-01 module complies with the following safety regulations:
n Underwriters Laboratories, Inc. (UL): Filing E331901 n CSA n TUV Environmental Conditions Table 28 describes the operating and storage conditions for the Cypress BLE module. Table 28. Environmental Conditions for CYBT-X430XX-01 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[4]
30 C 5%
40 C 85 C 85%
3 C/minute 85 C 85 C at 85%
15 kV Air 2.0 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 4. This does not apply to the RF pins (ANT). Document Number: 002-19525 Rev. **
Page 39 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Regulatory Information FCC FCC NOTICE:
The device CYBT-X430XX-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
n Reorient or relocate the receiving antenna. n Increase the separation between the equipment and receiver. n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. n Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3026. In any case the end product must be labeled exterior with "Contains FCC ID: WAP3026"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 13. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBT-X430XX-01 with the trace antenna is far below the FCC radio frequency exposure limits. Never-
theless, use CYBT-X430XX-01 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-19525 Rev. **
Page 40 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 ISED Innovation, Science and Economic Development Canada (ISED) Certification CYBT-X430XX-01 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada (ISED), License: ISED: 7922A-3026 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 13, having a maximum gain of -0.5 dBi. Antennas not included in this list or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE:
The device CYBT-X430XX-01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYBT-X430XX-01, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences d'approbation de l'metteur modulaire tel que dcrit dans RSS-GEN. L'opration est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interfrences nuisibles, et (2) Cet appareil doit accepter toute interfrence reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonction-
nement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3026. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3026"
Document Number: 002-19525 Rev. **
Page 41 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-X430XX-01 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
All versions of the CYBT-X430XX-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBT-X430XX-01 is certified as a module with certification number TBD. End products that integrate CYBT-X430XX-01 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. Document Number: 002-19525 Rev. **
Page 42 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Packaging Table 29. Solder Reflow Peak Temperature Module Part Number Package 24-pad SMT CYBT-X430XX-01 Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles 260 C 30 seconds 2 Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBT-X430XX-01 Package 24-pad SMT MSL MSL 3 The CYBT-X430XX-01 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-X430XX-01. Figure 20. CYBT-X430XX-01 Tape Dimensions (TBD) Figure 21 details the orientation of the CYBT-X430XX-01 in the tape as well as the direction for unreeling. Figure 21. Component Orientation in Tape and Unreeling Direction (TBD) Document Number: 002-19525 Rev. **
Page 43 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Figure 22 details reel dimensions used for the CYBT-X430XX-01. Figure 22. Reel Dimensions The CYBT-X430XX-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-X430XX-01 is detailed in Figure 23. Figure 23. CYBT-X430XX-01 Center of Mass (TBD) Document Number: 002-19525 Rev. **
Page 44 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Ordering Information Table 31 lists the CYBT-X430XX-01 part number and features. Table 32 lists the reel shipment quantities for the CYBT-X430XX-01. Table 31. Ordering Information Part Number CPU Speed
(MHz) Flash Size (KB) CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 24 24 24 512 512 RAM Size (KB) UART Yes Yes Yes 352 352 352 BSC
(I2C) Yes Yes Yes Apple Homekit PWM 4 4 4 No Yes No Package Packaging 24-SMT 24-SMT 24-SMT Tape and Reel Tape and Reel Tape and Reel Table 32. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) TBD TBD TBD TBD Minimum Reel Quantity Maximum Reel Quantity Comments Ships in TBD unit reel quantities. The CYBT-X430XX-01 is offered in tape and reel packaging. The CYBT-X430XX-01 ships in a reel size of TBD. For additional information and a complete list of Cypress Semiconductor Wireless products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-19525 Rev. **
Page 45 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Acronyms Table 33. Acronyms Used in this Document Description Acronym Bluetooth Low Energy BLE Bluetooth SIG Bluetooth Special Interest Group CE CSA EMI ESD FCC GPIO IC IDE KC European Conformity Canadian Standards Association electromagnetic interference electrostatic discharge Federal Communications Commission general-purpose input/output Industry Canada integrated design environment Korea Certification Ministry of Internal Affairs and Communications
(Japan) printed circuit board receive qualification design ID surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs timer, counter, pulse width modulator (PWM) Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit MIC PCB RX QDID SMT TCPWM TUV TX Document Number: 002-19525 Rev. **
Page 46 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Document Conventions Units of Measure Table 34. Units of Measure Symbol C kV mA mm mV A m MHz GHz V Unit of Measure degree Celsius kilovolt milliamperes millimeters millivolt microamperes micrometers megahertz gigahertz volt Document Number: 002-19525 Rev. **
Page 47 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Document History Page Document Title: CYBT-X430XX-01 EZ-BT WICED Module Document Number: 002-19525 Orig. of Revision Change Submission Date ECN
**
PRELIM-
INARY DSO Description of Change Preliminary datasheet for CYBT-X430XX-01 module. Document Number: 002-19525 Rev. **
Page 48 of 49 PRELIMINARY CYBT-343026-01 CYBT-343029-01 CYBT-143038-01 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-19525 Rev. **
Revised May 31, 2017 Page 49 of 49
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2018-12-03 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Class II permissive change or modification of presently authorized equipment |
2 | 2402 ~ 2480 | DTS - Digital Transmission System | ||
3 | 2017-07-12 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Original Equipment |
4 | 2402 ~ 2480 | DTS - Digital Transmission System |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 3 4 | Effective |
2018-12-03
|
||||
1 2 3 4 |
2017-07-12
|
|||||
1 2 3 4 | Applicant's complete, legal business name |
Cypress Semiconductor
|
||||
1 2 3 4 | FCC Registration Number (FRN) |
0017759150
|
||||
1 2 3 4 | Physical Address |
198 Champion Court
|
||||
1 2 3 4 |
San Jose, California 95134
|
|||||
1 2 3 4 |
United States
|
|||||
app s | TCB Information | |||||
1 2 3 4 | TCB Application Email Address |
a******@dekra.com
|
||||
1 2 3 4 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 3 4 | Grantee Code |
WAP
|
||||
1 2 3 4 | Equipment Product Code |
3026
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 3 4 | Name |
D**** S********
|
||||
1 2 3 4 | Title |
Sr. Business Unit Director
|
||||
1 2 3 4 | Telephone Number |
408-5********
|
||||
1 2 3 4 | Fax Number |
408-5********
|
||||
1 2 3 4 |
d******@cypress.com
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 3 4 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 3 4 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
1 2 3 4 | If so, specify the short-term confidentiality release date (MM/DD/YYYY format) | 01/17/2019 | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 3 4 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 3 4 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
1 2 3 4 | DTS - Digital Transmission System | |||||
1 2 3 4 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | This product is a Bluetooth wireless EZ-BT Module | ||||
1 2 3 4 | Bluetooth wireless EZ-BT Module | |||||
1 2 3 4 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 3 4 | Modular Equipment Type | Single Modular Approval | ||||
1 2 3 4 | Purpose / Application is for | Class II permissive change or modification of presently authorized equipment | ||||
1 2 3 4 | Original Equipment | |||||
1 2 3 4 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
1 2 3 4 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 3 4 | Grant Comments | Single modular Approval. Output power is conducted. This device is approved for portable use with respect to RF exposure compliance. Multi-transmitter, supporting simultaneous transmission configurations, have not been evaluated and shall be evaluated according to KDB Publication 447498 and §15.31(h) and §15.31(k) composite system. | ||||
1 2 3 4 | Single modular Approval. Output power is conducted. This device is approved for portable use with respect to RF exposure compliance. Multi-transmitter, supporting simultaneous transmission configurations, have not been evaluated and shall be evaluated according to KDB Publication 447498 and §15.31(h) and §15.31(k) composite system. | |||||
1 2 3 4 | Single modular approval. Output power is conducted. This device is approved for portable use with respect to RF exposure compliance. Multi-transmitter, supporting simultaneous transmission configurations, have not been evaluated and shall be evaluated according to KDB Publication 447498 and §15.31(h) and §15.31(k) composite system. | |||||
1 2 3 4 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 3 4 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 3 4 | Firm Name |
DEKRA Testing and Certification (Suzhou) Co., Ltd.
|
||||
1 2 3 4 | Name |
J**** X******
|
||||
1 2 3 4 |
J******** P********
|
|||||
1 2 3 4 | Telephone Number |
86 51********
|
||||
1 2 3 4 |
86-51******** Extension:
|
|||||
1 2 3 4 | Fax Number |
86-51********
|
||||
1 2 3 4 |
j******@dekra.com
|
|||||
1 2 3 4 |
j******@quietek.com.cn
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | CC | 2402 | 2480 | 0.0061 | |||||||||||||||||||||||||||||||||||
1 | 2 | 15C | CC | 2402 | 2480 | 0.0042 | |||||||||||||||||||||||||||||||||||
1 | 3 | 15C | CC | 2402 | 2480 | 0.0048 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0034000 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
3 | 1 | 15C | CC | 2402 | 2480 | 0.0065 | |||||||||||||||||||||||||||||||||||
3 | 2 | 15C | CC | 2402 | 2480 | 0.0045 | |||||||||||||||||||||||||||||||||||
3 | 3 | 15C | CC | 2402 | 2480 | 0.0051 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
4 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0042000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC