FCC ID: WAP3039 This product is a Bluetooth wireless EZ-BT WICED XR Module with Mesh

PRELIMINARY CYBT-483039-02 EZ-BT XR WICED Module

(BLE) wireless module General Description The CYBT-483039-02 is a dual-mode Bluetooth BR/EDR and Low Energy solution. The CYBT-483039-02 includes onboard crystal oscillators, passive components, PA/LNA, and the Cypress CYW20719 silicon device. The CYBT-483039-02 supports a number of peripheral functions

(ADC, PWM), as well as multiple serial communication protocols

(UART, SPI, I2C, I2S/PCM). The CYBT-483039-02 includes a royalty-free stack compatible with Bluetooth 5.0 in a 12.75 18.59 1.80 mm module form-factor. The CYBT-483039-02 includes an integrated chip antenna, on-board external power/low noise amplifier, qulaified by Bluetooth SIG, and includes regulatory certification approval for FCC, ISED, MIC, and CE. Module Description n Module size: 12.75 mm 18.59 mm 1.80 mm n Complies with Bluetooth Core Specification version 5.0 supporting BR, EDR 2/3 Mbps, eSCO, BLE, and LE 2 Mbps . p QDID: TBD p Declaration ID: TBD n True Extended Range:

p Up to 1 kilometer bidirectional communication[1, 2]

n Certified to FCC, ISED, MIC, and CE standards n Up to 15 GPIOs n 1024-KB flash memory, 512-KB SRAM memory n Industrial temperature range: 30 C to +85 C n Integrated ARM Cortex-M4 microprocessor core with floating point unit (FPU) RF Characteristics n Maximum TX output power(EIRP): +20.0 dBm n Conducted output power:

p +17.6dBm for BT3.0, +16.8dBm for BT4.0 n Antenna peak gain: 2.3 dBi n BLE RX Receive Sensitivity: 95.0 dbm n Received signal strength indicator (RSSI) with 1-dB resolution Power Consumption n TX current consumption p BLE silicon: 5.6 mA (MCU + radio only, 0 dbm) p RFX2401C: 100 mA peak (PA/LNA only, +17.5 dBm Pout) p RFX2401C: 27 mA peak (PA/LNA only, +7.5 dBm Pout) n RX current consumption p Bluetooth silicon: 5.9 mA (MCU + radio only) p RFX2401C: 8.0 mA (PA/LNA only) n Cypress CYW20719 silicon low power mode support p PDS: 61 A with 512 KB SRAM retention p SDS: 1.6 uA p HIDOFF (External Interrupt): 400 nA Functional Capabilities n 1x ADC with (12-bit ENoB for DC measurement and 13-bit ENoB for Audio measurement) with 10 channels. n 1x HCI UART for programming and HCI n 1x peripheral UART (PUART) n 2x SPI (master or slave) blocks (SPI, Quad SPI, MIPI DBI-C) n 1x I2C master/slave and 1x I2C master only n I2S/PCM audio interfaces n Up to 6 16-bit PWMs n Watchdog Timer n Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR) Support n BLE protocol stack supporting generic access profile (GAP) Central, Peripheral, or Broadcaster roles n Hardware Security Engine Benefits CYBT-483039-02 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth communication standards. n Proven hardware design ready to use n Ultra-flexible supermux I/O designs allows maximum flexibility for GPIO function assignment n Large non-volatile memory for complex application devel-

opment n Over-the-air update capable for development or field updates n Bluetooth SIG qualified with QDID and Declaration ID n WICED Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test your Bluetooth application Notes 1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +18 dBm POUT. 2. Specified as EZ-BT XT module to module range. Mobile phone connection will decrease based on the PA/LNA performance of the mobile phone used. Cypress Semiconductor Corporation Document Number: 002-23993 Rev. **

198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised May 22, 2018 PRELIMINARY CYBT-483039-02 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References n Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap n Development Kits:

p CYBT-483039-EVAL, CYBT-483039-02 Evaluation Board p CYW920719Q40EVB-01, Evaluation Kit for CYW20719 silicon device n Test and Debug Tools:

p CYSmart, Bluetooth LE Test and Debug Tool (Windows) p CYSmart Mobile, Bluetooth LE Test and Debug Tool

(Android/iOS Mobile App) n Knowledge Base Article p KBA97095 - EZ-BLE Module Placement p KBA213976 - FAQ for BLE and Regulatory Certifications with p KBA210802 - Queries on BLE Qualification and Declaration EZ-BLE modules Processes p KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules p KBA223428- Programming an EZ-BT WICED Module Development Environments Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK) Cypress' WICED (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits

(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth connectivity in system design. WICED Studio is the only SDK for the Internet of Things (ioT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. Technical Support n Cypress Community: Whether youre a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world. n Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System. n Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-23993 Rev. **

Page 2 of 49 PRELIMINARY CYBT-483039-02 Contents Overview............................................................................ 4 Functional Block Diagram ........................................... 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 8 Module Connections ...................................................... 10 Connections and Optional External Components ..... 12 Power Connections (VDD and VDDPA).................... 12 External Reset (XRES).............................................. 13 HCI UART Connections ............................................ 13 External Component Recommendation .................... 13 Critical Components List ........................................... 15 Antenna Design......................................................... 15 Power Amplifier (PA) and Low Noise Amplifier (LNA) 15 Bluetooth Baseband Core ............................................. 16 BQB and Regulatory Testing Support ....................... 16 Power Management Unit................................................ 17 Integrated Radio Transceiver ........................................ 18 Transmitter Path........................................................ 18 Receiver Path............................................................ 18 Local Oscillator.......................................................... 18 Microcontroller Unit ....................................................... 19 External Reset........................................................... 19 Peripheral and Communication Interfaces .................. 20 I2C............................................................................. 20 HCI UART Interface .................................................. 20 Peripheral UART Interface ........................................ 20 Serial Peripheral Interface......................................... 20 32 kHz Crystal Oscillator ........................................... 20 ADC Port ................................................................... 22 GPIO Ports ................................................................ 22 PWM.......................................................................... 23 PDM Microphone....................................................... 24 I2S Interface .............................................................. 24 PCM Interface ........................................................... 24 Security Engine ......................................................... 25 Power Modes .................................................................. 26 Firmware.......................................................................... 26 Electrical Characteristics............................................... 27 Core Buck Regulator................................................. 27 Digital LDO................................................................ 29 Digital I/O Characteristics.......................................... 29 ADC Electrical Characteristics .................................. 29 Bluetooth Silicon Current Consumption .................... 30 Chipset RF Specifications ............................................. 31 Timing and AC Characteristics ..................................... 34 UART Timing............................................................. 34 SPI Timing................................................................. 35 I2C Compatible Interface Timing............................... 37 I2S Interface Timing .................................................. 38 Environmental Specifications ....................................... 40 Environmental Compliance ....................................... 40 RF Certification.......................................................... 40 Safety Certification .................................................... 40 Environmental Conditions ......................................... 40 ESD and EMI Protection ........................................... 40 Regulatory Information.................................................. 41 FCC........................................................................... 41 ISED.......................................................................... 42 European Declaration of Conformity ......................... 43 MIC Japan................................................................. 43 Packaging........................................................................ 44 Ordering Information...................................................... 46 Acronyms........................................................................ 47 Document Conventions ................................................. 47 Units of Measure ....................................................... 47 Document History Page................................................. 48 Sales, Solutions, and Legal Information ...................... 49 Worldwide Sales and Design Support....................... 49 Products .................................................................... 49 PSoC Solutions ...................................................... 49 Cypress Developer Community................................. 49 Technical Support ..................................................... 49 Document Number: 002-23993 Rev. **

Page 3 of 49 PRELIMINARY CYBT-483039-02 Overview Functional Block Diagram Figure 1 illustrates the CYBT-483039-02 functional block diagram. Figure 1. Functional Block Diagram Note: General Purpose Input/Output pins shown in Figure 1 are configuratble to any specified input or output function in the SuperMux table detailed in Table 5 in the Module Connections section. Note: Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYBT-483039-02 is 15. Module Description The CYBT-483039-02 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for the CYBT-483039-02 will not be made until approval is provided by the end customer for this product. The CYBT-483039-02 will be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Module dimensions Antenna location dimensions PCB thickness Shield height Maximum component height Total module thickness (bottom of module to top of shield) Specification Length (X) Width (Y) Length (X) Width (Y) Height (H) Height (H) Height (H) Height (H) 12.75 0.15 mm 18.59 0.15 mm 12.75 mm 4.82 mm 0.50 0.10 mm 1.20 mm 1.30 mm typical (Chip Antenna) 1.80 mm typical See Figure 2 for the mechanical reference drawing for CYBT-483039-02. Document Number: 002-23993 Rev. **

Page 4 of 49 PRELIMINARY CYBT-483039-02 Figure 2. Module Mechanical Drawing Top View (Seen from Top) Side View Bottom View (Seen from Bottom) Notes 3. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Recommended Host PCB Layout on page 8. Document Number: 002-23993 Rev. **

Page 5 of 49 PRELIMINARY CYBT-483039-02 Pad Connection Interface As shown in the bottom view of Figure 2 on page 5, the CYBT-483039-02 has 34 connections to a host board via solder pads (SP). Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-483039-02 module. Table 2. Connection Description Name Connections SP 34 Connection Type Pad Length Dimension Pad Width Dimension Solder Pad 1.02 mm 0.71 mm Pad Pitch 1.02 mm Figure 3. Solder Pad Dimensions (Seen from Bottom) Solder Pad Connections

(Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Please refer to AN96841 for module placement best practices. 3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). Document Number: 002-23993 Rev. **

Page 6 of 49 PRELIMINARY CYBT-483039-02 Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-483039-02 Chip Antenna Document Number: 002-23993 Rev. **

Page 7 of 49 PRELIMINARY CYBT-483039-02 Recommended Host PCB Layout Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-483039-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-483039-02 Host Layout (Dimensioned) Figure 6. CYBT-483039-02 Host Layout (Relative to Origin) Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-23993 Rev. **

Page 8 of 49 PRELIMINARY CYBT-483039-02 Table 3 provides the center location for each solder pad on the CYBT-483039-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location Solder Pad

(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Location (X,Y) from Orign (mm)

(0.38, 5.92)

(0.38, 6.93)

(0.38, 7.95)

(0.38, 8.97)

(0.38, 9.98)

(0.38, 11.00)

(0.38, 12.01)

(0.38, 13.03)

(0.38, 14.05)

(0.38, 15.06)

(0.38, 16.08)

(0.38, 17.09)

(1.80, 18.21)

(2.82, 18.21)

(3.84, 18.21)

(4.85, 18.21)

(5.87, 18.21)

(6.88, 18.21)

(7.90, 18.21)

(8.92, 18.21)

(9.93, 18.21)

(10.95, 18.21)

(12.37, 17.09)

(12.37, 16.08)

(12.37, 15.06)

(12.37, 14.05)

(12.37, 13.03)

(12.37, 12.01)

(12.37, 11.00)

(12.37, 9.98)

(12.37, 8.97)

(12.37, 7.95)

(12.37, 6.93)

(12.37, 5.92) Dimension from Orign (mils)

(14.96, 233.07)

(14.96, 272.83)

(14.96, 312.99)

(14.96, 353.15)

(14.96, 392.91)

(14.96, 433.07)

(14.96, 472.83)

(14.96, 512.99)

(14.96, 553.15)

(14.96, 592.91)

(14.96, 633.07)

(14.96, 672.83)

(70.87, 716.93)

(111.02, 716.93)

(151.18, 716.93)

(190.94, 716.93)

(231.10, 716.93)

(270.87, 716.93)

(311.02, 716.93)

(351.18, 716.93)

(390.94, 716.93)

(431.10, 716.93)

(487.01, 672.83)

(487.01, 633.07)

(487.01, 592.91)

(487.01, 553.15)

(487.01, 512.99)

(487.01, 472.83)

(487.01, 433.07)

(487.01, 392.91)

(487.01, 353.15)

(487.01, 312.99)

(487.01, 272.83)

(487.01, 233.07) Top View (Seen on Host PCB) Document Number: 002-23993 Rev. **

Page 9 of 49 PRELIMINARY CYBT-483039-02 Module Connections Table 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available on the CYBT-483039-02 can be configured to any of the input or output funcitons listed in Table 5. Table 4 specifies any function that is required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux. Table 4. CYBT-483039-02 Solder Pad Connection Definitions Pad SuperMux Capable[4]

Silicon Pin Name Pad Name XTALI/O GPIO ADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDD GND XRES P33 P25 P26 P38 P34/P35/P36 P1 P0 P29 P13/P23/P28 GND P10/P11 P17 P7 P6 P4 VDDIO GND RST_N P33 P25 P26 P38 P34 P35 P36 P1 P0 P29 P13 P23 P28 GND P10 P11 P17 P7 P6 P4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

XTALO_32K XTALO_32K External Oscillator Output (32KHz) XTALI_32K/

P15[5]

XTALI_32K P15 External Oscillator Input

(32KHz) Silicon Power Supply Input (2.0V ~ 3.6V) Ground External Reset (Active Low) IN6

-

-

IN1 IN5 (P34) IN4 (P35) IN3 (P36) IN28 IN29 IN10 IN22 (P13) IN12 (P23) IN11 (P28) IN25 (P10) IN24 (P11) IN18

-

-

-

-

3 3 3 3 3 see Table 5 3 see Table 5 3 see Table 5 3 see Table 5 3 (P34/P35/P36) 3 see Table 5 3 3 3 3 see Table 5 3 see Table 5 3 see Table 5 3(P13/P23/P28) 3 see Table 5 Ground 3 (P10/P11) 3 3 3 3

-

3 see Table 5 3 see Table 5

-

3 see Table 5

-

-

IN20 (P15) 3(P15) 3(P15), see Table 5 UART_CTS_N BT_UART_CTS_N UART_RTS_N BT_UART_RTS_N UART_TXD BT_UART_TXD BT_UART_RXD UART_RXD BT_HOST_WAKE A signal from the CYBT-483039-02 module to the host indicating that the Bluetooth device requires UART (HCI UART) Transmit Data Only UART (HCI UART) Receive Data Only UART (HCI UART) Request To Send Output Only UART (HCI UART) Clear To Send Input Only HOST_WAKE GND GND GND GND GND GND VDDPA GND GND 26 27 28 29 30 31 32 33 34 Note 4. The CYBT-483039-02 can configure GPIO connections to any Input/Output function described in Table 5. 5. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 GND GND GND GND GND GND N/A GND GND PA/LNA Power Supply Voltage (2.0 ~ 3.6V) Ground Ground until the device comes out of reset. attention. Ground Ground Ground Ground Ground Ground Document Number: 002-23993 Rev. **

Page 10 of 49 PRELIMINARY CYBT-483039-02 Table 5 details the available Input and Ouput functions that are configurable to any sodler pad in Table 4 that are marked as SuperMux capable. Table 5. GPIO SuperMux Input and Output Functions Function Input or Output Function Type GPIOs Required SWD SPI 1 Input Input/Output Serial Communication and Debug 2 Input/Output Serial Communication

(Master or Slave) 4 ~ 8 Function Connection Description SWDCK, Serial Wire Debugger Clock SWDIO, Serial Wire Debugger I/O SPI 1 Clock SPI 1 Chip Select SPI 1 MOSI SPI 1 MISO SPI 1 I/O 2 (Quad SPI) SPI 1 I/O 3 (Quad SPI) SPI 1 Interrupt Output SPI 1 DCX (DBI-C DCX 8-bit mode) SPI 2 Input/Output Serial Communication

(Master or Slave) 4 ~ 8 Output Input Serial Communication Input Output Serial Communication Output Input/Output Input/Output Serial Communication

(Master or Slave) Serial Communication

(Master or Slave) PUART I2C I2C 2 PCM In Input Audio Input Communication PCM Out Output Audio Output Communication I2S In I2S Out PDM Input Audio Input Communication Ouput Audio Output Communication Input Microphone 1 ~ 2 4 2 2 3 3 3 3 SPI 2 Clock SPI 2 Chip Select SPI 2 MOSI SPI 2 MISO SPI 2 I/O 2 (Quad SPI) SPI 2 I/O 3 (Quad SPI) SPI 2 Interrupt SPI 2 DCX (DBI-C DCX 8-bit mode) Periperal UART RX Peripheral UART CTS Peripheral UART TX Peripheral UART RTS I2C Clock I2C Data I2C 2 Clock I2C 2 Data PCM Input PCM Clock PCM Sync PCM Output PCM Clock PCM Sync I2S DI, Data Input I2S WS, Word Select I2S Clock I2S DO, Data Output I2S WS, Word Select I2S Clock PDM Input Channel 1 PDM Input Channel 2 Document Number: 002-23993 Rev. **

Page 11 of 49 PRELIMINARY CYBT-483039-02 Function Input or Output Function Type GPIOs Required Function Connection Description PWM Output Pulse Width Modulator 1 ~ 6 ACLK HIDOFF Output Output Auxiliary Clock HID-OFF Indicator 1 ~ 2 1 PWM Channel 0 PWM Channel 1 PWM Channel 2 PWM Channel 3 PWM Channel 4 PWM Channel 5 Auxiliary Clock 0 (ACLK0) Auxiliary Clock 1 (ACLK1) HID-OFF Indicator to host Connections and Optional External Components Power Connections (VDD and VDDPA) The CYBT-483039-02 contains two power supply connections, VDD and VDDPA. VDD is the power supply connection for the Cypress CYW20719 silicon device. VDD accepts a supply input of 1.76 V to 3.63 V. Table 14 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 14. VDDPA is the power supply connection for the on-module power amplifier/low-noise amplifier. VDDPA accepts a supply input of 2.00 V to 3.60 V. Table 14 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 14. Considerations and Optional Components for Brown Out (BO) Conditions Power supply design must be completed to ensure that the CYBT-483039-02 module does not encounter a Brown Out condition, which can lead to unexpected funcitonality, or module lock up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the range shown below:

VIL VDD VIH Refer to Table 18 for the VIL and VIH specifications. System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occuring during power removal. Please refer to Figure 8 for the recommended circuit design when using an external voltage detection IC. Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. Document Number: 002-23993 Rev. **

Page 12 of 49 PRELIMINARY CYBT-483039-02 External Reset (XRES) The CYBT-483039-02 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-483039-02 module (solder pad 3). The CYBT-483039-02 module does not require an external pull-up resistor on the XRES input During power on operation, the XRES connection to the CYBT-483039-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:

n The host device can connect a GPIO to the XRES of Cypress CYBT-483039-02 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDD is stable. n If the XRES connection of the CYBT-483039-02 module is not used in the application, a 0.33 uF capacitor may be connected to the XRES solder pad of the CYBT-483039-02 in order to delay the XRES release. The capacitor value for this recommended imple-

mentation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitor value should result in an XRES release timing of at least 50 ms after VDD stability. n The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. Refer to Figure 11 on page 19 for XRES operating and timing requirements during power on events. HCI UART Connections The recommendations in this section apply to the HCI UART (Solder Pads 21, 22, 23, and 24). For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:

n UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. n UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the module. External Component Recommendation Power Supply Input Options and Circuitry Two connection options are available for the VDD and VDDPA power supplies:

1. Single supply: Connect VDD and VDDPAto the same supply. 2. Independent supply: Power VDD and VDDPA separately. In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pad connection. The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Document Number: 002-23993 Rev. **

Page 13 of 49 PRELIMINARY CYBT-483039-02 Figure 9 illustrates the CYBT-483039-02 schematic. Figure 9. CYBT-483039-02 Schematic Diagram Document Number: 002-23993 Rev. **

Page 14 of 49 PRELIMINARY CYBT-483039-02 Critical Components List Table 6 details the critical components used in the CYBT-483039-02 module. Table 6. Critical Component List Component Reference Designator Description Silicon Chip Antenna PA/LNA Crystal U2 A1 U2 Y1 N Bluetooth Silicon Device - CYW20719 40-pin QF Antenna, 2.4 GHz, ALA321C3-C PA/LNA, RFX2401C 24.000 MHz, 12PF Antenna Design Table 7 details the chip antenna used in the CYBT-483039-02 module. Table 7. Chip Antenna Specifications Item Frequency Range Peak Gain Return Loss 2400 2500 MHz 2.3 dBi typical 10.0 dB typical Description Power Amplifier (PA) and Low Noise Amplifier (LNA) Table 8 details the PA/LNA that is used on the CYBT-483039-02 module. For more information, see Table 8. Table 8. Power Amplifier/Low Noise Amplifier Details Item Description PA/LNA Manufacturer PA/LNA Part Number Power Supply R ange Skyworks Inc. RFX2401C 2.0V to 3.6V Table 9 details the power consumption of the integrated PA/LNA used on the More Part Numbers module. Table 9 only details the current consumption of the RFX2401C PA/LNA. VDD= 3.3 V, TA = +25C, measured on the RFX2401C evaluation board, unless otherwise noted. Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications Typical Parameter Max Min Tx High Power Current Tx Quiescent Current Rx Quiescent Current Test Condition Pout = +18dBm No RF applied No RF applied 100 17 8 Unit mA mA mA Document Number: 002-23993 Rev. **

Page 15 of 49 PRELIMINARY CYBT-483039-02 Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening. Table 10. Bluetooth Features Bluetooth 1.0 Basic Rate SCO Paging and Inquiry Page and Inquiry Scan Sniff Bluetooth 2.1 Secure Simple Pairing Enhanced Inquiry Response Sniff Subrating Bluetooth 4.1 Bluetooth 1.2 Interlaced Scans Adaptive Frequency Hopping eSCO Bluetooth 3.0 Unicast Connectionless Data Enhanced Power Control eSCO Bluetooth 4.2 Bluetooth 2.0 EDR 2 Mbps and 3 Mbp Bluetooth 4.0 Bluetooth Low Energy Bluetooth 5.0 Data Packet Length Extension LE Secure Connection Link Layer Privacy Low Duty Cycle Advertising Dual Mode LE Link Layer Topology BQB and Regulatory Testing Support The CYBT-483039-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYBT-483039-02 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:

n Fixed frequency carrier wave (unmodulated) transmission LE 2 Mbps Slot Availability Mask High Duty Cycle Advertising p Simplifies some type-approval measurements (Japan) p Aids in transmitter performance analysis n Fixed frequency constant receiver mode p Receiver output directed to I/O pin p Allows for direct BER measurements using standard RF test equipment p Facilitates spurious emissions testing for receive mode n Fixed frequency constant transmission p 8-bit fixed pattern or PRBS-9 p Enables modulated signal measurements with standard RF test equipment Document Number: 002-23993 Rev. **

Page 16 of 49 PRELIMINARY CYBT-483039-02 Power Management Unit Figure 10 shows the CYW20719 power management unit (PMU) block diagram. The CYW20719 includes an integrated buck regulator, a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls below 2.1V. The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions. Figure 10. Default Usage Mode Document Number: 002-23993 Rev. **

Page 17 of 49 PRELIMINARY CYBT-483039-02 Integrated Radio Transceiver The CYBT-483039-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the require-

ments to provide the highest communication link quality of service. Transmitter Path CYBT-483039-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. Power Amplifier The CYBT-483039-02 has an integrated power amplifier (PA) on the silicon device as well as a high power external power amplifier

(PA) integrated on the module. The total output power that this module is designed to achieve is +18 dBm. Receiver Path The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-483039-02 to be used in most applications without off-chip filtering. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYBT-483039-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The CYBT-483039-02 uses an internal loop filter. Document Number: 002-23993 Rev. **

Page 18 of 49 PRELIMINARY CYBT-483039-02 Microcontroller Unit The CYBT-483039-02 includes a Cortex M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip flash. The CM4 has a maximum speed of 96 MHz. CYBT-483039-02 supports execution from on-chip flash (OCF). The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU). The CM4 runs all the BT layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack layers freeing up the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support. External Reset An external active-low reset signal, XRES, can be used to put the CYBT-483039-02 in the reset state. An external voltage detector reset IC with 50 ms delay is recommended on the XRES connection. The XRES must only be released after the VDDO supply volt-

age level has been stabilized for 50 ms. Figure 11. Reset Timing Document Number: 002-23993 Rev. **

Page 19 of 49 PRELIMINARY CYBT-483039-02 Peripheral and Communication Interfaces I2C The CYBT-483039-02 provides a 2-pin I2C compatible master interface to communicate with I2C compatible peripherals. The following transfer clock rates are supported are:

n 100 kHz n 400 kHz n 800 kHz (Not a standard I2C-compatible speed) n 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed) SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I2C block does not support multi master capability by either master or slave devices. I2C1 is Master Only; I2C2 is Master/Slave. The Slave support is subject to driver support in WICED Studio. HCI UART Interface The CYBT-483039-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYBT-483039-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within 5%. The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. The CYBT-483039-02 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal (solder pad 2). signal allows the CYBT-483039-02 to optimize system power consumption by allowing a host device to remain in low power modes as long as possible. The HOST_WAKE signal can be enabled via a vendor specific command. Peripheral UART Interface The CYBT-483039-02 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin. The CYBT-483039-02 can map the peripheral UART to any GPIO. The Peripheral UART functionality is the same as the HCI UART, but with a 256-byte transmit and receive FIFO. Serial Peripheral Interface The CYBT-483039-02 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well as MIPI DBI-C Interface.Either of the interface can be a master or a slave. SPI2 can support only 1 slave. SPI1 has a 1024 byte transmit and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To support more flexibility for user applications, the CYBT-483039-02 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO. MIPI interface There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYBT-483039-02 plays the role of host, and only the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins are used. In the 8-bit mode, an additional pin (DCX) is required. The DCX pin indicates if the current outgoing bit stream is a command or data byte. 32 kHz Crystal Oscillator The CYBT-483039-02 utlizes the built-in Local Oscillator (LO) on the CYW20719 silicon device for 32kHz timing. The accuracy of the LO is +/- 500 ppm. The use of an external XTAL oscillator is optional. CYBT-483039-02 includes external XTAL oscilator connections for applications requiring higher timing accuracy. Figure 12 shows an external 32 kHz XTAL oscillator with external components and Table 11 lists the the recommended external oscillators characteristics. This oscillator input can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M and C1 =

C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator. Document Number: 002-23993 Rev. **

Page 20 of 49 PRELIMINARY CYBT-483039-02 Figure 12. 32 kHz Oscillator Block Diagram Table 11. XTAL Oscillator Characteristics Symbol Parameter Conditions Minimum Typical Maximum Output frequency Frequency tolerance Start-up time XTAL drive level XTAL series resistance XTAL shunt capacitance External AC Input Amplitude Foscout Crystal-dependent Tstartup Pdrv Rseries Cshunt VIN (AC) For crystal selection For crystal selection For crystal selection Ccouple = 100 pF;

Rbias= 10 Mohm 400 32.768 100 500 0.5 70 2.2 Unit kHz ppm ms W k pF mVpp Document Number: 002-23993 Rev. **

Page 21 of 49 PRELIMINARY CYBT-483039-02 ADC Port The ADC is a - ADC core designed for audio (13 bits) and DC (12 bits) measurement. It operates at 12 MHz and has 10 solder pad connections that can act as input channels. The internal bandgap reference has 5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode. The following CYBT-483039-02 module solder pads can be used as ADC inputs:

n Pad 4: P33, ADC Input Channel 6 n Pad 7: P38, ADC Input Channel 1 n Pad 8: P34/P35/P36, ADC Input Channels 5/4/3 respectively; NOTE: only one ADC input on this solder pad can be active at a given time. n Pad 9: P1, ADC Input Channel 28 n Pad 10: P0, ADC Input Channel 29 n Pad 11: P29, ADC Input Channel 10 n Pad 12: P13/P23/28, ADC Input Channels 22/12/11 respectively; NOTE: only one ADC input on this solder pad can be active at a given time. n Pad 14: P10/P11, ADC Input Channels 25/24 respectively; NOTE: only one ADC input on this solder pad can be active at a given time. n Pad 15: P17, ADC Input Channel 18 n Pad 20: P15, ADC Input Channel 20. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset. GPIO Ports The CYBT-483039-02 has a maximum of 15 general-purpose I/Os (GPIOs). All GPIOs support the following:

n Programmable pull-up/down of approximately 45 KOhms. n Input disable, allowing pins to be left floating or analog signals connected without risk of leakage. n Source/sink 8 mA at 3.3V and 4 mA at 1.8V. n P15 is Bonded to the same pin as XTALI_32K (Pad 20). If an External 32.768KHz crystal is not used, then this pin can be used as GPIO P15. n P26/P28/P29 can sink/source 16 mA at 3.3V and 8 mA at 1.8V. Most peripheral functions can be assigned to any GPIO. For details, refer to Table 5. For more details on Supermux configuration and control, refer to "Supermux Wizard for CYW20719" user guide. The list below details the GPIOs that are available on the CYBT-483039-02 module:

p P0-P1, P4, P6, P7, P17, P25, P26, P29, P33, and P38 p P10/P11 (Double bonded connection on the CYBT-483039-02 module, only one of two is available) p P13/P23/P28 (Triple bonded connection on the CYBT-483039-02 module, only one of three is available) p P15/XTALI_32K (Double bonded pin on the CYBT-483039-02 module, only one of two is available) p P34/P35/P36 (Triple bonded pin on the CYBT-483039-02 module, only one of three is available) p P19, P20 and P39 are reserved for system use. Please do not use those 3 GPIOs. For GPIOs highlighted as double or triple bonded connections, only one of the connections can be used at a given time. When a certain GPIO is selected, the other GPIOs bonded to the same connection must be configured to input with output disable. Document Number: 002-23993 Rev. **

Page 22 of 49 PRELIMINARY CYBT-483039-02 PWM The CYBT-483039-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:

n Each of the six PWM channels contains the following registers:

p 16-bit initial value register (read/write) p 16-bit toggle register (read/write) p 16-bit PWM counter value register (read) n PWM configuration register shared among PWM05 (read/write). This 18-bit register is used:

p To configure each PWM channel p To select the clock of each PWM channel p To change the phase of each PWM channel The application can access the PWM module through the FW driver. Figure 13 shows the structure of one PWM channel. Figure 13. PWM Block Diagram Document Number: 002-23993 Rev. **

Page 23 of 49 PRELIMINARY CYBT-483039-02 PDM Microphone The CYBT-483039-02 accepts a -based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:

n 8 kHz n 16 kHz The external digital microphone takes in a 2.4 MHz clock generated by the CYBT-483039-02 and outputs a PDM signal which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible. Note: Subject to the driver support in WICED Studio. I2S Interface The CYBT-483039-02 supports a single I2S digital audio port with both master and slave modes. The I2S signals are:

n I2S Clock: I2S SCK n I2S Word Select: I2S WS n I2S Data Out: I2S DO n I2S Data In: I2S DI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYBT-483039-02 are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK. Note: The PCM interface shares HW with the I2S interface and only one can be used at a given time. PCM Interface The CYBT-483039-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-483039-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-483039-02.The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Note: The PCM interface shares HW with the I2S interface and only one can be used at a given time. Slot Mapping The CYBT-483039-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYBT-483039-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchro-

nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The CYBT-483039-02 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYBT-483039-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first. Document Number: 002-23993 Rev. **

Page 24 of 49 PRELIMINARY CYBT-483039-02 Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Security Engine The CYBT-483039-02 includes a hardware security accelerator which greatly decreases the time required to perform typical security operations. Access to the hardware block is provided via a firmware interface (see firmware documentation for details).Thie security engine includes:

n Public key acceleration (PKA) cryptography n AES-CTR/CBC-MAC/CCM acceleration n SHA2 message hash and HMAC acceleration n RSA encryption and decryption of modulus sizes up to 2048 bits n Elliptic curve Diffie-Hellman in prime field GF(p) Note: Security Engine is used only by the Bluetooth stack to reduce CPU overhead. It is not available for application use. Random Number Generator This hardware block is used for key generation for Bluetooth. Note: Availability for use by the application is subject to the support in WICED Studio. Note: The Random Number Generator block must be warmed up prior to use. A delay of 500 ms from cold boot is necessary prior to using the Random Number Generator. Document Number: 002-23993 Rev. **

Page 25 of 49 PRELIMINARY CYBT-483039-02 Power Modes The CYBT-483039-02 support the following HW power modes are supported:

n Active mode - Normal operating mode in which all peripherals are available and the CPU is active. n Idle mode - In this mode, the CPU is in Wait for Interrupt (WFI) and the HCLK, which is the high frequency clock derived from the main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained. n Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained. n PDS mode - This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused. n Shut Down Sleep (SDS) - Everything is turned off except the IO Power Domain, RTC, and LPO. The device can come out of this mode either due to BT activity or by an external interrupt. Before going into this mode, the application can store some bytes of data into Always On RAM (AON). When the device comes out of this mode, the data from AON is restored. After waking from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In the SDS mode, a single BT task with no data activity, such as an ACL connection, BLE connection, or BLE advertisement can be performed. n HIDOFF (Timed-Wake) mode - The device can enter this mode asynchronously, that is, the application can force the device into this mode at any time. IO Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake the device up after a predetermined fixed time. n HIDOFF (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-off mode even the LPO and RTC are turned off. So, the only wakeup source is an external interrupt. Transition between power modes is handled by the on-chip firmware with host/application involvement. Please see Firmware Section for details. Firmware The CYBT-483039-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes. The CYBT-483039-02 is fully supported by the Cypress WICED Studio platform. WICED releases provide latest ROM patches, drivers, and sample applications allowing customized applications using the CYBT-483039-02 to be built quickly and efficiently. Please refer to WICED Technical Brief and CYBT-483039-02 Product Guide for details on the firmware architecture, driver documen-

tation, power modes and how to write applications/profiles using the CYBT-483039-02. Document Number: 002-23993 Rev. **

Page 26 of 49 PRELIMINARY CYBT-483039-02 Electrical Characteristics The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 12. Silicon Absolute Maximum Ratings Requirement Parameter Maximum Junction Temperature VDD IO VDD RF VDDBAT3V DIGLDO_VDDIN1P5 RFLDO_VDDIN1P5 PALDO_VDDIN_5V MIC_AVDD Table 13. ESD/Latchup Requirement Parameter ESD Tolerance HBM (Silicon) ESD Tolerance CDM (Silicon) Latch-up Min. 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Min. 2000 500 Specification Nom. Specification Nom. 200 Max. 125 3.795 1.38 3.795 1.65 1.65 3.795 3.795 Max. 2000 500 Table 14. Power Supply Specifications Parameter Conditions VDD input VDDPA input VDD Ripple VBAT Input PMU turn-on time Module Chipset Input Module PA/LNA Input Module Input Ripple (VDDPA, VDD) Internal to Module (not accessible) VBAT is ready. Min. 2.0 2.0 1.90 Typical 3.0 3.0 3.0 Max. 3.60 3.60 100 3.6 300 Unit C V V V V V V V Unit V V mA Unit V V mV V s The CYBT-483039-02 uses an onboard low voltage detector to shut down the part when supply voltage (VDD) drops below operating range. Table 15. Power Supply Shut Down Specifications Min. 1.625 Max. 1.76 Parameter Unit V Typical 1.7 VSHUT Core Buck Regulator Table 16. Silicon Core Buck Regulator Parameter Input supply voltage DC, VBAT CBUCK output current Conditions DC voltage range inclusive of disturbances LPOM only Min. 1.90 Typ. 3.0 Max. 3.63 65 Unit V mA Document Number: 002-23993 Rev. **

Page 27 of 49 PRELIMINARY CYBT-483039-02 Table 16. Silicon Core Buck Regulator (continued) Parameter Output voltage range Output voltage DC accuracy LPOM efficiency (high load) LPOM efficiency (low load) Input supply voltage ramp-up time Conditions Programmable, 30mV/step default = 1.2V (bits=0000) Includes load and line regulation 0 to 3.3V Min. 1.2 Typ. 1.26 Max. 1.5 Unit V 4 40 85 80

+4

%

%

%

s n Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging. n Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any. Document Number: 002-23993 Rev. **

Page 28 of 49 PRELIMINARY CYBT-483039-02 Conditions Minimum Vin=Vo+0.12V requirement must be met under maximum load. Internal default setting At maximum load Min. 1.2 Typ. 1.2 1.1 Max. 1.6 120 Unit V V mV Digital LDO Table 17. Digital LDO Parameter Input supply voltage, Vin Nominal output voltage,Vo Dropout voltage Digital I/O Characteristics Table 18. Digital I/O Characteristics Characteristics Symbol Minimum Typical Maximum Input low voltage (VDD = 3V) Input high voltage (VDD = 3V) Input low voltage (VDD = 1.8V) Input high voltage (VDD = 1.8V) Output low voltage Output high voltage Input low current Input high current Output low current (VDD = 3V, VOL = 0.5V) Output low current (VDD = 1.8V, VOL = 0.5V) Output high current (VDD = 3V, VOH = 2.55V) Output high current (VDD = 1.8V, VOH = 1.35V) Input capacitance UART_TXD VOL (0.5mA) UART_TXD VOH (0.5mA) ADC Electrical Characteristics Table 19. Electrical Characteristics VIL VIH VIL VIH VOL VOH IIL IIH IOL IOL IOH IOH CIN UART_TXD VOL UART_TXD VOH 2.4 1.4 VDDO 0.45V TBD Parameter Current consumption Power down current ADC Core Specification ADC reference voltage ADC sampling clock Absolute error ENOB ADC input full scale Conversion rate Symbol ITOT VREF FS Conditions/Comments At room temperature From BG with 3% accuracy Includes gain error, offset and distortion. Without factory calibration. Includes gain error, offset and distortion. After factory calibration. For audio application For static measurement For audio application For static measurement For audio application For static measurement Min. 12 10 1.8 8 50 Typ. 2 1 0.85 12 13 1.6 16 100 0.8 0.4 0.45 1.0 1.0 8.0 4.0 8.0 4.0 0.4 TBD Max. 3 5 2 3.6 Unit V V V V V V A A mA mA mA mA pF mA mA Unit mA A V MHz

%

%

Bit kHz Document Number: 002-23993 Rev. **

Page 29 of 49 PRELIMINARY CYBT-483039-02 Table 19. Electrical Characteristics (continued) Parameter Symbol Conditions/Comments Signal bandwidth Input impedance Startup time MIC PGA Specifications MIC PGA gain range MIC PGA gain step MIC PGA gain error PGA input referred noise Passband gain flatness MIC Bias Specifications MIC bias output voltage MIC bias loading current MIC bias noise MIC bias PSRR ADC SNR ADC THD + N GPIO input voltage GPIO source impedance1 RIN For audio application For static measurement For audio application For static measurement For audio application For static measurement Includes part-to-part gain variation At 42 dB PGA gain A-weighted PGA and ADC, 100 Hz4 kHz At 2.5V supply Refers to PGA input 20 Hz to 8 kHz, A-weighted at 1 kHz A-weighted 0 dB PGA gain 3 dBFS input 0 dB PGA gain Always lower than avddBAT Resistance Capacitance Min. 20 10 500 0 1 0.5 40 78 74 Typ. DC 10 20 1 2.1 Max. 8K 42 1 4 0.5 3 3 3.6 1 10 1. Conditional requirement for the measurement time of 10 s. Relaxed with longer measurement time for each GPIO input channel. Bluetooth Silicon Current Consumption In Table 20, current consumption measurements are taken at module input VDD = 3.0V. Table 20. SIlicon Current Consumption BT/LE Operational Mode HCI RX TX PDS HID-Off (SDS) Advertising LE Connection - SDS Page Scan - PDS Sniff - PDS Conditions Typical 48 MHz with Pause 48 MHz Without Pause Continuous RX Continuous TX - 0 dBm 32 KHz xtal and 16 KB Retention RAM on Unconnectable - 1 sec Connectable Undirected - 1 sec Master - 1 sec Slave - 1 sec Interlaced - R1 500 ms Sniff, 1 attempt, 0 timeout - Master 500 ms Sniff, 1 attempt, 0 timeout - Slave 1.1 2.2 5.9 5.6 61 1.6 14 17 TBD TBD 122 132 138 Unit Hz KW ms s dB dB dB V dB V mA V dB dB dB V k pF Unit mA mA mA mA A A A A A A A A A Document Number: 002-23993 Rev. **

Page 30 of 49 PRELIMINARY CYBT-483039-02 Table 20. SIlicon Current Consumption BT/LE Operational Mode Bi-Directional Data Exchange Conditions Continuous DM5 or DH5 packets - Mas ter or Slave Typical 6.9 Unit mA Table 21. Power Amplifier/Low Noise Amplifier Current Consumption Specifications Typical Parameter Min Tx High Power Current Tx Quiescent Current Rx Quiescent Current Test Condition Pout = +18dBm No RF applied No RF applied 100 17 8 Max Unit mA mA mA Chipset RF Specifications Table 22 and Table 23 apply to single-ended industrial temperatures. Unused inputs are left open. Table 22. Chipset Receiver RF Specifications Parameter Mode and Conditions Frequency range RX sensitivity1 GFSK, 0.1% BER, 1 Mbps

/4-DQPSK, 0.01% BER, 2 Mbps 8-DPSK, 0.01% BER All data rates

, 3 Mbps 3 MHz adjacent channel 3 GFSK, 0.1% BER 4 GFSK, 0.1% BER 3 GFSK, 0.1% BER 5 GFSK, 0.1% BER 3 GFSK, 0.1% BER 3 GFSK, 0.1% BER Maximum input GFSK Modulation C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I C/I image channel C/I 1 MHz adjacent to image channel QPSK Modulation

/4-DQPSK, 0.1% BER3 C/I cochannel

/4-DQPSK, 0.1% BER4 C/I 1 MHz adjacent channel

/4-DQPSK, 0.1% BER3 C/I 2 MHz adjacent channel

/4-DQPSK, 0.1% BER5 C/I 3 MHz adjacent channel

/4-DQPSK, 0.1% BER3 C/I image channel C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER3 8PSK Modulation C/I cochannel C/I 1 MHz adjacent channel C/I 2 MHz adjacent channel C/I C/I image channel C/I 1 MHz adjacen Out-of-Band Blocking Performance (CW)4 30 MHz to 2000 MHz 3 8-DPSK, 0.1% BER 3 8-DPSK, 0.1% BER 3 8-DPSK, 0.1% BER 5 8-DPSK, 0.1% BER 3 8-DPSK, 0.1% BER 3 8-DPSK, 0.1% BER 3 MHz adjacent channel BDR GFSK 0.1% BER t to image channel Min 2402 Typ 92.0 94.0 88.0 2 2 2 10.0 Max 2480 20 11.0 0 30.0 40.0 9.0 20.0 13.0 0 30.0 40.0 9.0 20.0 21.0 5.0 25.0 33.0 0 13 Unit MHz dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm Document Number: 002-23993 Rev. **

Page 31 of 49 PRELIMINARY CYBT-483039-02 Table 22. Chipset Receiver RF Specifications (continued) Parameter 2000 MHz to 2399 MHz 2498 MHz to 3000 MHz 3000 MHz to 12.75 GHz Inter-modulation Performance6 BT, interferer signal level Spurious Emissions 30 MHz to 1 GHz 1 GHz to 12.75 GHz Mode and Conditions BDR GFSK 0.1% BER BDR GFSK 0.1% BER BDR GFSK 0.1% BER BDR GFSK 0.1% BER Min Typ 27.0 27.0 10.0 Max 39.0 57.0 55.0 Unit dBm dBm dBm dBm dBm dBm 1. Dirty TX is off 2. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations 3. The receiver sensitivity is measured at BER of 0.1% on the device interface. 4. Desired signal is 10 dB above the reference sensitivity level (defined as 70 dBm). 5. Desired signal is 3 dB above the reference sensitivity level (defined as 70 dBm). 6. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is 39 dBm sine wave at frequency f1, interferer 2 is 39 dBm Bluetooth modulated signal at frequency f2, f0 = 2*f1 f2, and |f2 f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. Table 23. Chipset Transmitter RF Specifications Parameter Transmitter Section Frequency range Class 2: GFSK Tx power Class 2: EDR Tx Power 20 dB bandwidth Adjacent Channel Power

|M N| = 2

|M N| 3 Out-of-Band Spurious Emission 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz LO Performance Initial carrier frequency tolerance Frequency Drift DH1 packet DH3 packet DH5 packet Drift rate Frequency Deviation Average deviation in payload

(sequence used is 00001111) Maximum deviation in payload

(sequence used is 10101010) Channel spacing Modulation Accuracy Document Number: 002-23993 Rev. **

Min 2402 75 25 40 40 20 140 115 Typ 4.0 0 930 1 Max 2480 1000 20 40 36.0 30.0 47.0 47.0

+75

+25

+40

+40 20 175 Unit MHz dBm dBm kHz dBm dBm dBm dBm dBm dBm kHz kHz kHz kHz kHz/50 s kHz kHz MHz Page 32 of 49 PRELIMINARY CYBT-483039-02 Table 23. Chipset Transmitter RF Specifications (continued) Parameter

/4-DQPSK Frequency Stability

/4-DQPSK RMS DEVM

/4-QPSK Peak DEVM

/4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM 8-DPSK 99% DEVM In-Band Spurious Emissions 1.5 MHz 1.0 MHz < |M N| <

1.5 MHz < |M N| <

2.5 MHz

|M N| > 2.5 MHz Min 10 10 Typ Max 10 20 35 30 10 13 25 20 26 20 40 Table 24. BLE RF Specifications Parameter Conditions Minimum Typical Maximum Frequency range Rx sensitivity (QFN)1 Tx power Tx power Mod Char: Delta F1 average Mod Char: Delta F2 max3 Mod Char: Ratio N/A LE GFSK, 0.1% BER, 1 Mbps BLE Silicon Device CYW20719 Only Module total output power N/A N/A N/A 2402 225 99.9 0.8 2 95.0 4.0 255 0.95 2480 18 275 1. Dirty Tx is Off 2. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations 3. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Unit kHz

%

%

%

kHz

%

%

%

dBc dBm dBm Unit MHz dBm dBm dBm kHz

%

%

Table 25. CYBT-483039-02 GPS and GLONASS Band Spurious Emission Parameter 1570-1580 MHz 1592-1610 MHz GPS GLONASS Condition Min. Typ. 160 159 Max. Unit dBm/Hz dBm/Hz Document Number: 002-23993 Rev. **

Page 33 of 49 PRELIMINARY CYBT-483039-02 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 26. UART Timing Specifications Reference 1 2 3 Characteristics Delay time, UART_CTS_N low to UART_TXD valid. Setup time, UART_CTS_N high before midpoint of stop bit. Delay time, midpoint of stop bit to UART_RTS_N high. Min. Typ. Max. 1.50 0.67 1.33 Unit Bit periods Bit periods Bit periods Figure 14. UART Timing Document Number: 002-23993 Rev. **

Page 34 of 49 PRELIMINARY CYBT-483039-02 SPI Timing The SPI interface can be clocked up to 24 MHz. Table 27 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2. Table 27. SPI Mode 0 and 2 Reference 1 2 3 4 5 Characteristics Time from master assert SPI_CSN to first clock edge Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions Figure 15. SPI Timing, Mode 0 and 2 Min. 45 12 0 0 1 SCK Max. SCK 100 Unit ns ns ns ns ns Document Number: 002-23993 Rev. **

Page 35 of 49 PRELIMINARY CYBT-483039-02 Table 28 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3. Table 28. SPI Mode 1 and 3 Reference 1 2 3 4 5 Characteristics Time from master assert SPI_CSN to first clock edge Hold time for MOSI data lines Time from last sample on MOSI/MISO to slave deassert SPI_INT Time from slave deassert SPI_INT to master deassert SPI_CSN Idle time between subsequent SPI transactions Min. 45 12 0 0 1 SCK Max. SCK 100 Unit ns ns ns ns ns Figure 16. SPI Timing, Mode 1 and 3 Document Number: 002-23993 Rev. **

Page 36 of 49 PRELIMINARY CYBT-483039-02 I2C Compatible Interface Timing The specifications in Table 29 references Figure 17. Table 29. I2C Compatible Interface Timing Specifications (up to 1 MHz) Reference Characteristics 1 Clock frequency 2 3 4 5 6 7 8 9 10 START condition setup time START condition hold time Clock low time Clock high time Data input hold time1 Data input setup time STOP condition setup time Output valid from clock Bus free time2 Minimum Maximum 650 280 650 280 0 100 280 650 100 400 800 1000 400 Unit kHz ns ns ns ns ns ns ns ns ns 1. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2. Time that the CBUS must be free before a new transaction can start. Figure 17. I2C Interface Timing Diagram Document Number: 002-23993 Rev. **

Page 37 of 49 PRELIMINARY CYBT-483039-02 I2S Interface Timing I2S timing is shown below in Table 30, Figure 18, and Figure 19. Table 30. Timing for I2S Transmitters and Receivers Clock Period T HIGH tHC LOWtLC HIGH tHC LOW tLC Rise time tRC Delay tdtr Hold time thtr Transmitter Receiver Lower LImit Min Max Ttr Upper Limit Min Max Lower Limit Min Max Tr Upper Limit Min Max Master Mode: Clock generated by transmitter or receiver 0.35Ttr 0.35Ttr Slave Mode: Clock accepted by transmitter or receiver 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.15Ttr 0 Transmitter Receiver 0.8T Notes 1 2 2 3 3 4 5 4 Setup time tsr Hold time thr 1. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer 0.2Ttr 0.2Ttr 6 6 2.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and rate. tLC are specified with respect to T. 3.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 4.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. 5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 6. The data setup and hold time must not be less than the specified receiver setup and hold time. Document Number: 002-23993 Rev. **

Page 38 of 49 PRELIMINARY CYBT-483039-02 Figure 18. I2S Transmitter Timing Figure 19. I2S Receiver Timing Document Number: 002-23993 Rev. **

Page 39 of 49 PRELIMINARY CYBT-483039-02 Environmental Specifications Environmental Compliance This Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBT-483039-02 module is certified under the following RF certification standards:

n FCC: WAP3039 n IC: 7922A-3039 n MIC: TBD n CE Safety Certification The CYBT-483039-02 module complies with the following safety regulations:

n Underwriters Laboratories, Inc. (UL): Filing E331901 n CSA n TUV Environmental Conditions Table 31 describes the operating and storage conditions for the Cypress BLE module. Table 31. Environmental Conditions for CYBT-483039-02 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[6]

30 C 5%

40 C 85 C 85%

10 C/minute 85 C 85 C at 85%

15 kV Air 2.0 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 6. This does not apply to the RF pins (ANT). Document Number: 002-23993 Rev. **

Page 40 of 49 PRELIMINARY CYBT-483039-02 Regulatory Information FCC FCC NOTICE:

The device CYBT-483039-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter device approval as detailed in FCC public Notice DA00-1407.transmitter may not cause harmful interference, and (2) This device must accept any interference received, cause undesired operation. Operation is subject to the following two conditions: (1) This including interference that may CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved Cypress Semiconductor may void This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment cause generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may harmful interference to radio communications. However, there is installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to no guarantee that interference will not occur in a particular correct the interference by one or more of the user's authority to operate the following measures:

the equipment. by Reorient or relocate the receiving antenna. Increase the separation between Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help the equipment and receiver. n n n n LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that FCC label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as as the FCC Notice above. The FCC In any case the end product must be labeled exterior with Contains FCC ID: WAP3039. labelling requirements are met. This includes a clearly visible well identifier is FCC ID: WAP3039. ANTENNA WARNING:

This device is tested with a standard SMA connector and with the antenna listed in product, this fixed antenna requires installation preventing end-users from replacing them with not in emissions. on page 15 must be tested to comply with FCC Section 15.203 for unique antenna connectors Table 7 Table 7 on page 15. When integrated in the OEMs non-approved antennas. Any antenna and Section 15.247 for RF EXPOSURE:

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in instructions about the integrated radio module is not allowed. SAR is not required for this module as long as the distance is higher than 33mm away from user. End and transmitter operating conditions in manuals, for products operating with the approved antennas notification to the end user of installation or removal with for satisfying RF exposure compliance. on page 15, to alert users on FCC RF Exposure compliance. Any instructions. integrators installation provided provided module Table 7 users users OEM must may end with the not be be Document Number: 002-23993 Rev. **

Page 41 of 49 PRELIMINARY CYBT-483039-02 ISED Innovation, Science and Economic Development (ISED) Canada Certification CYBT-483039-02 is licensed to meet the regulatory requirements License: IC: 7922A-3039 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance from www.ic.gc.ca. on page 15, having a maximum gain of 2.3 dBi. Antennas This device has been designed to operate with the antennas listed in not included in prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. of Innovation, Science and Economic Development (ISED) Canada. on page 15 or having a gain greater than 2.3 dBi are strictly compliance information Canadian exposure exposure Table 7 Table 7 and/or Users limits. obtain SAR and can RF RF for on device ISED NOTICE:

The requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to device may not cause harmful interference, and (2) This device may cause undesired operation. CYBT-483039-02 including complies antenna built-in trace with the the following two conditions: (1) This must accept any interference received, including interference that RSS-GEN Canada device Rules. meets The the L'appareil CYBT-483039-02, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences conditions suivantes: (1) Cet appareil ne doit pas causer d'interfrences reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. doit accepter toute interfrence nuisibles, et (2) Cet appareil d'approbation L'opration RSS-GEN. modulaire l'metteur soumise dans deux dcrit que aux de tel est ISED INTERFERENCE STATEMENT FOR CANADA This and Operation is subject to the following two conditions: (1) this interference, including interference that may cause undesired operation of the device. Development Innovation, Economic complies Science device with standard(s). device may not cause interference, and (2) this device must accept any licence-exempt Canada

(ISED) RSS Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonction-

nement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA The antenna of this transmitter must provide a separation distance of at least 35 mm from all persons. Installers and end-users must be provided with antenna installation instructions and transmitter operating conditions and instructions for satisfying RF exposure compliance. Compliance of this device in all final product configurations is the responsibility of the Grantee. Installation of this device into specific final products may require the submission of a Class II permissive change application, containing data pertinent to RF Exposure, emissions and host/module authentication, or new application if appropriate. The final product operating with this transmitter must include operating instructions and antenna installation instructions, for end-users and installers to satisfy RF exposure compliance requirements. L'antenne de cet metteur doit fournir une distance de sparation d'au moins 35 mm par rapport toutes les personnes. Les installateurs et les utilisateurs finaux doivent recevoir les instructions d'installation de l'antenne ainsi que les conditions d'utilisation de l'metteur et les instructions pour satisfaire la conformit l'exposition aux radiofrquences. La conformit de cet appareil dans toutes les configurations de produit final est la responsabilit du bnficiaire. L'installation de cet appareil dans des produits finaux spcifiques peut ncessiter la soumission d'une demande de modification permissive de classe II, contenant des donnes pertinentes sur l'exposition RF, les missions et l'authentification hte / module, ou une nouvelle application, le cas chant. Le produit final fonctionnant avec cet metteur doit inclure des instructions d'utilisation et des instructions d'installation de l'antenne, pour les utilisateurs finaux et les installateurs afin de satisfaire aux exigences de conformit en matire d'exposition aux RF. Document Number: 002-23993 Rev. **

Page 42 of 49 PRELIMINARY CYBT-483039-02 LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3039. In any case, the end product must be labeled in its exterior with "Contains IC:7922A-3039". Le fabricant d'quipement d'origine (OEM) doit s'assurer que les exigences d'tiquetage ISED sont respectes. Cela comprend une tiquette clairement visible l'extrieur de l'enceinte OEM spcifiant l'identifiant Cypress Semiconductor IC appropri pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3039. En tout cas, le produit final doit tre tiquet dans son extrieur avec

"Contient IC: 7922A-3039". European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-483039-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:

All versions of the CYBT-483039-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan More Part Numbers is certified as a module with certification number TBD. End products that integrate More Part Numbers do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. Document Number: 002-23993 Rev. **

Page 43 of 49 PRELIMINARY CYBT-483039-02 Packaging Table 32. Solder Reflow Peak Temperature Module Part Number Package 34-pad SMT CYBT-483039-02 Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles 260 C 30 seconds 2 Table 33. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBT-483039-02 Package 34-pad SMT MSL MSL 3 The CYBT-483039-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-483039-02. Figure 20. CYBT-483039-02 Tape Dimensions Figure 21 details the orientation of the CYBT-483039-02 in the tape as well as the direction for unreeling. Figure 21. Component Orientation in Tape and Unreeling Direction (TBD) Document Number: 002-23993 Rev. **

Page 44 of 49 PRELIMINARY CYBT-483039-02 Figure 22 details reel dimensions used for the CYBT-483039-02. Figure 22. Reel Dimensions The CYBT-483039-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-483039-02 is detailed in Figure 23. Figure 23. CYBT-483039-02 Center of Mass (TBD) Document Number: 002-23993 Rev. **

Page 45 of 49 PRELIMINARY CYBT-483039-02 Ordering Information Table 34 lists the CYBT-483039-02 part number and features. Table 34 also lists the target program for the respective module ordering codes. Table 35 lists the reel shipment quantities for the CYBT-483039-02. Table 34. Ordering Information Ordering Part Number Max CPU Speed

(MHz) CYBT-483039-02 96 Flash Size

(KB) 1024 RAM Size

(KB) 512 UART I2C SPI I2S PCM PWM ADC Yes Yes Yes Yes Yes 6 Inputs GPIOs Package Packaging 34-SMT Tape and Reel 10 15 Table 35. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) 500 500 500 500 Minimum Reel Quantity Maximum Reel Quantity Comments Ships in 500 unit reel quantities. The CYBT-483039-02 is offered in tape and reel packaging. The CYBT-483039-02 ships in a reel size of 500 units. For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com

(408) 943-2600 Document Number: 002-23993 Rev. **

Page 46 of 49 PRELIMINARY CYBT-483039-02 Document Conventions Units of Measure Table 37. Units of Measure Symbol C kV mA mm mV A m MHz GHz V Unit of Measure degree Celsius kilovolt milliamperes millimeters millivolt microamperes micrometers megahertz gigahertz volt Acronyms Table 36. Acronyms Used in this Document Description Acronym Bluetooth Low Energy BLE Bluetooth SIG Bluetooth Special Interest Group CE CSA EMI ESD FCC GPIO European Conformity Canadian Standards Association electromagnetic interference electrostatic discharge Federal Communications Commission general-purpose input/output Innovation, Science and Economic Devel-

opment (Canada) integrated design environment Korea Certification Ministry of Internal Affairs and Communications

(Japan) printed circuit board receive qualification design ID surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs timer, counter, pulse width modulator (PWM) Germany: Technischer berwachungs-Verein

(Technical Inspection Association) transmit ISED IDE KC MIC PCB RX QDID SMT TCPWM TUV TX Document Number: 002-23993 Rev. **

Page 47 of 49 PRELIMINARY CYBT-483039-02 Document History Page Document Title: CYBT-483039-02 EZ-BT XR WICED Module Document Number: 002-23993 Orig. of Revision Change Submission Date ECN

**

DSO Description of Change 05/17/2018 Preliminary datasheet for CYBT-483039-02 module. Document Number: 002-23993 Rev. **

Page 48 of 49 PRELIMINARY CYBT-483039-02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs |

Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-23993 Rev. **

Revised May 22, 2018 Page 49 of 49