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CYBT-213043-02 User Manual | Users Manual | 1.30 MiB | March 19 2019 | |||
| 1 2 | Test Report | March 19 2019 | ||||||
| 1 2 | Test Report | March 19 2019 | ||||||
| 1 2 | Block diagram | Block Diagram | March 19 2019 | confidential | ||||
| 1 2 | ID Label/Location Info | March 19 2019 | ||||||
| 1 2 | External Photos | March 19 2019 | ||||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | Test Setup Photos | March 19 2019 | ||||||
| 1 2 | Internal Photos | March 19 2019 | ||||||
| 1 2 | Operational description | Operational Description | March 19 2019 | confidential | ||||
| 1 2 | Schematic | Schematics | March 19 2019 | confidential | ||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | Cover Letter(s) | March 19 2019 | ||||||
| 1 2 | External Photos | March 19 2019 |
| 1 2 | CYBT-213043-02 User Manual | Users Manual | 1.30 MiB | March 19 2019 |
PRELIMINARY CYBT-213043-02 EZ-BT Module Functional Capabilities Up to 22 GPIOs I2C, I2S, UART, and PCM interfaces Two Quad-SPI interfaces Auxiliary ADC with up to 15 analog channels Programmable key scan 20 8 matrix General-purpose timers and PWM Real-time clock (RTC) and watchdog timers (WDT) Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR) Support BLE protocol stack supporting generic access profile (GAP) Central, Peripheral, or Broadcaster roles Hardware Security Engine Benefits CYBT-213043-02 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth communication standards. Proven hardware design ready to use Ultra-flexible supermux I/O design allows maximum flexibility for GPIO function assignment Over-the-air update capable for development or field updates Bluetooth SIG qualified. ModusToolbox provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test your Bluetooth application
(BLE) wireless module General Description The CYBT-213043-02 is a dual-mode Bluetooth BR/EDR and Low Energy solution. The CYBT-213043-02 includes an onboard crystal oscillator, passive components, and the Cypress CYW20819 silicon device. The CYBT-213043-02 supports a number of peripheral functions
(ADC, PWM), as well as multiple serial communication protocols
(UART, SPI, I2C, I2S/PCM). The CYBT-213043-02 includes a royalty-free stack compatible with Bluetooth 5.0 in a 12.0 16.61 1.70 mm module form-factor. The CYBT-213043-02 trace antenna, is qualified by Bluetooth SIG, and includes regulatory certification approval for FCC, ISED, MIC, and CE. Module Description Module size: 12.00 mm 16.61 mm 1.70 mm Complies with Bluetooth Core Specification version 5.0 and includes support for BR, EDR 2/3 Mbps, eSCO, BLE, LE 2 Mbps, as well as Bluetooth Mesh. QDID: TBD Declaration ID: TBD integrated PCB includes an Certified to FCC, ISED, MIC, and CE standards 256-KB on-chip Flash, 176-KB on-chip RAM Industrial temperature range: 30 C to +85 C Integrated Arm Cortex-M4 microprocessor core with floating point unit (FPU) RF Characteristics Maximum TX output power: +4.0 dBm BLE RX Receive Sensitivity: 95.0 dBm Power Consumption TX current consumption BLE silicon: 5.8 mA (radio only, 4 dBm) RX current consumption Bluetooth silicon: 5.9 mA (radio only) Cypress CYW20819 silicon low power mode support PDS: 16.5 A with 176 KB RAM retention ePDS: 8.7 A HIDOFF (External Interrupt): 1.75 A Cypress Semiconductor Corporation Document Number: 002-26540 Rev. **
198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised February 21, 2019 PRELIMINARY CYBT-213043-02 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. References Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap Development Kits:
CYBT-213043-EVAL, CYBT-213043-02 Evaluation Board CYBT-213043-MESH, Mesh Evaluation Kit CYW920819Q40EVB-01, Evaluation Kit for CYW20819 silicon device Test and Debug Tools:
CYSmart, Bluetooth LE Test and Debug Tool (Windows) CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App) Knowledge Base Article KBA97095 - EZ-BLE Module Placement RF Regulatory Certifications for CYBT-213034-02 EZ-BT WICED Modules (TBD) KBA213976 - FAQ for BLE and Regulatory Certifications with KBA210802 - Queries on BLE Qualification and Declaration EZ-BLE modules Processes KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules KBA223428 - Programming an EZ-BT WICED Module KBA225450 - Putting 2073x, 2070x, and 20719 Based De-
vices or Modules in HCI Mode Development Environments ModusToolbox Integrated Development Environment (IDE) ModusToolbox simplifies development for IoT designers. It delivers easy-to-use tools and a familiar microcontroller (MCU) integrated development environment (IDE) for Windows, macOS, and Linux. It provides a sophisticated environment for system setup, wireless connectivity libraries, power analysis, application-specific configurators for Bluetooth Low Energy (BLE), CapSense, as well as other peripherals. In addition, code examples, documentation, technical support and community forums are available to help your IoT development process along. These tools and features enable an IoT designer to develop innovative IoT applications efficiently and with ease. Technical Support Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share, and engage with both Cypress experts and other embedded engineers around the world. Frequently Asked Questions (FAQs): Learn more about our Bluetooth ecosystem. Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-26540 Rev. **
Page 2 of 45 PRELIMINARY CYBT-213043-02 Contents Overview............................................................................ 4 Functional Block Diagram ........................................... 4 Module Description...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Module Connections ........................................................ 9 Connections and Optional External Components ..... 11 Power Connections (VDD) ........................................ 11 External Reset (XRES).............................................. 11 HCI UART Connections ............................................ 11 External Component Recommendation .................... 11 Critical Components List ...........................................13 Antenna Design......................................................... 13 Bluetooth Baseband Core ............................................. 14 BQB and Regulatory Testing Support ....................... 14 Power Management Unit................................................ 15 Integrated Radio Transceiver ........................................ 16 Transmitter Path........................................................ 16 Receiver Path............................................................ 16 Local Oscillator.......................................................... 16 Microcontroller Unit ....................................................... 17 External Reset........................................................... 17 32-kHz Crystal Oscillator........................................... 17 Power Modes ............................................................ 18 Firmware ................................................................... 18 Peripherals and Communication Interfaces ................ 19 I2C............................................................................. 19 HCI UART Interface .................................................. 19 Peripheral UART Interface ........................................ 19 Serial Peripheral Interface......................................... 19 ADC Port ................................................................... 20 GPIO Port.................................................................. 20 PWM.......................................................................... 21 PDM Microphone....................................................... 21 I2S Interface ..............................................................22 PCM Interface ........................................................... 22 Electrical Characteristics............................................... 23 Current Consumption ................................................ 24 Silicon Core Buck Regulator ..................................... 24 Digital LDO................................................................ 25 RF LDO ..................................................................... 25 Digital I/O Characteristics.......................................... 26 ADC Characteristics.................................................. 26 Chipset RF Specifications ............................................. 28 Timing and AC Characteristics ..................................... 30 UART Timing............................................................. 30 SPI Timing................................................................. 31 I2C Compatible Interface Timing............................... 33 I2S Interface Timing .................................................. 34 Environmental Specifications ....................................... 36 Environmental Compliance ....................................... 36 RF Certification.......................................................... 36 Safety Certification .................................................... 36 Environmental Conditions ......................................... 36 ESD and EMI Protection ........................................... 36 Regulatory Information.................................................. 37 FCC........................................................................... 37 ISED.......................................................................... 38 European Declaration of Conformity ......................... 39 MIC Japan................................................................. 39 Packaging........................................................................ 40 Ordering Information...................................................... 42 Acronyms........................................................................ 43 Document Conventions ................................................. 43 Units of Measure ....................................................... 43 Document History Page................................................. 44 Sales, Solutions, and Legal Information ...................... 45 Worldwide Sales and Design Support....................... 45 Products .................................................................... 45 PSoC Solutions ...................................................... 45 Cypress Developer Community................................. 45 Technical Support ..................................................... 45 Document Number: 002-26540 Rev. **
Page 3 of 45 PRELIMINARY CYBT-213043-02 Overview Functional Block Diagram Figure 1 illustrates the CYBT-213043-02 functional block diagram. Figure 1. Functional Block Diagram Note: General Purpose Input/Output pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Table 5 in the Module Connections section. Note: Connections shown in Figure 1 are maximum number of connections per function. The total number of GPIOs available on the CYBT-213043-02 is 22. Module Description The CYBT-213043-02 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. The CYBT-213043-02 will be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Module dimensions Antenna location dimensions PCB thickness Shield height Maximum component height Total module thickness (bottom of module to top of shield) Length (X) Width (Y) Length (X) Width (Y) Height (H) Height (H) Height (H) Height (H) 12.00 0.15 mm 16.61 0.15 mm 12.00 mm 4.55 mm 0.50 0.10 mm 1.20 mm typical 0.80 mm typical 1.70 mm typical See Figure 2 for the mechanical reference drawing for CYBT-213043-02. Document Number: 002-26540 Rev. **
Page 4 of 45 PRELIMINARY CYBT-213043-02 Figure 2. Module Mechanical Drawing Top View (Seen from Top) Side View Bottom View (Seen from Bottom) Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on the recommended host PCB layout, see Recommended Host PCB Layout on page 7. Document Number: 002-26540 Rev. **
Page 5 of 45 PRELIMINARY CYBT-213043-02 Pad Connection Interface As shown in the bottom view of Figure 2 on page 5, the CYBT-213043-02 has 28 connections to a host board via solder pads (SP). Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-213043-02 module. Table 2. Connection Description Name Connections SP 35 Connection Type Pad Length Dimension Pad Width Dimension Solder Pad 1.02 mm 0.61 mm Pad Pitch 0.90 mm Figure 3. Solder Pad Dimensions (Seen from Bottom) Solder Pad Connections
(Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to AN96841 for module placement best practices. 3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module PCB antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-213043-02 PCB Antenna Document Number: 002-26540 Rev. **
Optional Host PCB Keep Out Area Around PCB An-
tenna
(Seen from Bottom) Page 6 of 45 PRELIMINARY CYBT-213043-02 Recommended Host PCB Layout Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-213043-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.633 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 5. CYBT-213043-02 Host Layout (Dimensioned) Figure 6. CYBT-213043-02 Host Layout (Relative to Origin) Top View (Seen on Host PCB) Top View (Seen on Host PCB) Document Number: 002-26540 Rev. **
Page 7 of 45 PRELIMINARY CYBT-213043-02 Table 3 provides the center location for each solder pad on the CYBT-213043-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 7. Solder Pad Reference Location Solder Pad
(Center of Pad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Location (X,Y) from Orign (mm)
(0.38, 4.85)
(0.38, 5.75)
(0.38, 6.65)
(0.38, 7.56)
(0.38, 8.46)
(0.38, 9.36)
(0.38, 10.26)
(0.38, 11.16)
(0.38, 12.07)
(0.38, 12.97)
(0.38, 13.87)
(0,38, 14.77)
(1.49, 16.23)
(2.39, 16.23)
(3.30, 16.23)
(4.20, 16.23)
(5.10, 16.23)
(6.00, 16.23)
(6.90, 16.23)
(7.80, 16.23)
(8.71, 16.23)
(9.61, 16.23)
(10.51, 16.23)
(11.62, 14.47)
(11.62, 13.87)
(11.62, 12.97)
(11.62, 12.07)
(11.62, 11.16)
(11.62, 10.26)
(11.62, 9.36)
(11.62, 8.46)
(11.62, 7.56)
(11.62, 6.65)
(11.62, 5.75)
(11.62, 4.85) Dimension from Orign (mils)
(14.96, 190.94)
(14.96, 226.38)
(14.96, 261.81)
(14.96, 297.64)
(14.96, 333.07)
(14.96, 368.50)
(14.96, 403.94)
(14.96, 439.37)
(14.96, 475.20)
(14.96, 510.63)
(14.96, 546.06)
(14.96, 581.49)
(58.66, 638.98)
(94.09, 638.98)
(129.92, 638.98)
(165.35, 638.98)
(200.79, 638.98)
(236.22, 638.98)
(271.65, 638.98)
(307.09, 638.98)
(342.91, 638.98)
(378.35, 638.98)
(413.78, 638.98)
(457.48, 581.49)
(457.48, 546.06)
(457.48, 510.63)
(457.48, 475.20)
(457.48, 439.37)
(457.48, 403.94)
(457.48, 368.50)
(457.48, 333.07)
(457.48, 297.64)
(457.48, 261.81)
(457.48, 226.38)
(457.48, 190.94) Top View (Seen on Host PCB) Document Number: 002-26540 Rev. **
Page 8 of 45 PRELIMINARY CYBT-213043-02 Module Connections Table 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available on the CYBT-213043-02 can be configured to any of the input or output functions listed in Table 5. Table 4 specifies any function that is required to be used on a specific solder pad, and also identifies SuperMux capable GPIOs that can be configured using the ModusToolbox device configurator. Table 4. CYBT-213043-02 Solder Pad Connection Definitions Pad SuperMux Capable[2]
Silicon Pin Name Pad Name XTALI/O GPIO ADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDD XRES P29 P32 P27 P37 P28 P0 P1 P10 P13 GND P12 P11 P9 P14 P17 P5 P6 P4 P2 P3 GND VDDIO RST_N P29 P32 P27 P37 P28 P0 P1 P10 P13 GND P12 P11 P9 P14 P17 P5 P6 P4 P2 P3 XTALI_32K XTALI_32K XTALO_32K XTALO_32K P15 P8 P15 P8 UART_CTS_N UART_RTS_N UART_TXD UART_RXD UART_CTS_N UART_RTS_N UART_TXD UART_RXD HOST_WAKE HOST_WAKE Ground Power Supply Input (1.71V ~ 3.63V) External Reset (Active Low) IN10 IN7
-
IN2 IN11 IN29 IN28 IN25 IN22 IN23 IN24 IN26 IN21 IN18
-
-
-
-
-
-
-
IN20 IN27 Ground
-
-
see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5
, see Table 5 see Table 5 see Table 5 see Table 5 see Table 5 see Table 5
-
-
see Table 5 see Table 5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
External Oscillator Input
(32KHz) External Oscillator Output (32KHz)
-
-
UART (HCI UART) Clear To Send Input Only UART (HCI UART) Request To Send Output Only UART (HCI UART) Transmit Data Only UART (HCI UART) Receive Data Only A signal from the CYBT-213043-02 module to the host indicating that the Bluetooth device requires attention. DEV_WAKE DEV_WAKE 33 34 35 Note 2. The CYBT-213043-02 can configure GPIO connections to any Input/Output function described in Table 5 using the ModusToolbox Device Configurator. A signal from the host to the CYBT-213043-02 module indicating that the host requires attention. see Table 5 P26 GND P26 GND Ground
-
-
Document Number: 002-26540 Rev. **
Page 9 of 45 PRELIMINARY CYBT-213043-02 Table 5 details the available Input and Output functions that are configurable to any solder pad in Table 4 that are marked as SuperMux capable. Table 5. GPIO SuperMux Input and Output Functions Function Input or Output Function Type GPIOs Required Function Connection Description SPI 1 Input/Output Serial Communication
(Master or Slave) 4 ~ 7 SPI 2 Input/Output Serial Communication
(Master or Slave) 4 ~ 7 PUART Input Serial Communication Input Output Serial Communication Output I2C Input/Output Serial Communication
(Master or Slave) PCM In Input Audio Input Communication PCM Out Output Audio Output Communication I2S In I2S Out PDM Input Audio Input Communication Output Audio Output Communication Input Microphone 1 ~ 2 PWM Output Pulse Width Modulator 1 ~ 6 4 2 3 3 3 3 SPI 1 Clock SPI 1 Chip Select SPI 1 MOSI SPI 1 MISO SPI 1 I/O 2 (Quad SPI) SPI 1 I/O 3 (Quad SPI) SPI 1 Interrupt SPI 2 Clock SPI 2 Chip Select SPI 2 MOSI SPI 2 MISO SPI 2 I/O 2 (Quad SPI) SPI 2 I/O 3 (Quad SPI) SPI 2 Interrupt Peripheral UART RX Peripheral UART CTS Peripheral UART TX Peripheral UART RTS I2C Clock I2C Data PCM Input PCM Clock PCM Sync PCM Output PCM Clock PCM Sync I2S DI, Data Input I2S WS, Word Select I2S Clock I2S DO, Data Output I2S WS, Word Select I2S Clock PDM Input Channel 1 PDM Input Channel 2 PWM Channel 0 PWM Channel 1 PWM Channel 2 PWM Channel 3 PWM Channel 4 PWM Channel 5 Document Number: 002-26540 Rev. **
Page 10 of 45 PRELIMINARY CYBT-213043-02 Connections and Optional External Components Power Connections (VDD) The CYBT-213043-02 contains one power supply connection, VDD. VDD accepts a supply input of 1.71 V to 3.63 V. Table 12 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 12. External Reset (XRES) The CYBT-213043-02 has an integrated power-on reset circuit which completely resets all circuits to a known power-on state. This action can also be invoked by an external reset signal, forcing it into a power-on reset state. XRES is an active-low input signal on the CYBT-213043-02 module (solder pad 3). The CYBT-213043-02 does not require external pull-up resistors on the XRES input Refer to Figure 10 on page 17 for Power On and XRES operation and timing requirements during power on events. HCI UART Connections The recommendations in this section apply to the HCI UART (Solder Pads 28, 29, 30, and 31). For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:
UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on. UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the module. External Component Recommendation Power Supply Circuitry It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included. The ferrite bead should be positioned as close as possible to the module pad connection. If used, the recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). Document Number: 002-26540 Rev. **
Page 11 of 45 PRELIMINARY CYBT-213043-02 Figure 8 illustrates the CYBT-213043-02 schematic. Figure 8. CYBT-213043-02 Schematic Diagram Document Number: 002-26540 Rev. **
Page 12 of 45 PRELIMINARY CYBT-213043-02 Critical Components List Table 6 details the critical components used in the CYBT-213043-02 module. Table 6. Critical Component List Component Reference Designator Description Silicon Crystal U1 Y1 62-pin QFN Bluetooth Silicon Device - CYW20819 24.000 MHz, 8PF Antenna Design Table 7 details the PCB trace antenna used in the CYBT-213043-02 module. Table 7. PCB Antenna Specifications Item Frequency Range Peak Gain Return Loss 24002500 MHz 0.5 dBi typical 10 dB minimum Description Document Number: 002-26540 Rev. **
Page 13 of 45 PRELIMINARY CYBT-213043-02 Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening. Table 8. Bluetooth Features Bluetooth 1.0 Basic Rate SCO Paging and Inquiry Page and Inquiry Scan Sniff Bluetooth 2.1 Secure Simple Pairing Enhanced Inquiry Response Sniff Subrating Bluetooth 4.1 Bluetooth 1.2 Interlaced Scans Adaptive Frequency Hopping eSCO Bluetooth 3.0 Unicast Connectionless Data Enhanced Power Control eSCO Bluetooth 4.2 Bluetooth 2.0 EDR 2 Mbps and 3 Mbps Bluetooth 4.0 Bluetooth Low Energy Bluetooth 5.0 Data Packet Length Extension LE Secure Connection Link Layer Privacy Low Duty Cycle Advertising Dual Mode LE Link Layer Topology BQB and Regulatory Testing Support The CYBT-213043-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the CYBT-213043-02 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:
Fixed frequency carrier wave (unmodulated) transmission LE 2 Mbps Slot Availability Mask High Duty Cycle Advertising Simplifies some type-approval measurements (Japan) Aids in transmitter performance analysis Fixed frequency constant receiver mode Receiver output directed to I/O pin Allows for direct BER measurements using standard RF test equipment Facilitates spurious emissions testing for receive mode Fixed frequency constant transmission 8-bit fixed pattern or PRBS-9 Enables modulated signal measurements with standard RF test equipment Document Number: 002-26540 Rev. **
Page 14 of 45 PRELIMINARY CYBT-213043-02 Power Management Unit Figure 9 shows the CYW20819 power management unit (PMU) block diagram. The CYW20819 includes an integrated buck regulator, a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls below 2.1 V. The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions. Figure 9. Default Usage Mode Document Number: 002-26540 Rev. **
Page 15 of 45 PRELIMINARY CYBT-213043-02 Integrated Radio Transceiver The CYBT-213043-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the require-
ments to provide the highest communication link quality of service. Transmitter Path CYBT-213043-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. Power Amplifier The CYBT-213043-02 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation. Receiver Path The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-213043-02 to be used in most applications without off-chip filtering. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the CYBT-213043-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the band. The CYBT-213043-02 uses an internal loop filter. Document Number: 002-26540 Rev. **
Page 16 of 45 PRELIMINARY CYBT-213043-02 Microcontroller Unit The CYBT-213043-02 includes a Cortex-M4 processor with 1 MB of program ROM, 160 KB of data RAM, 16 KB of patch RAM, and 256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code execution from flash at near maximum speed and low power consumption. The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support. External Reset Figure 10 shows power on and reset timing of the CYBT-213043-02. After VBAT is applied and reset is inactive, the internal buck turns on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows the digital core to come out of reset. As shown in the figure, external reset can be applied at any time subsequent to power up. Figure 10. Reset Timing 32-kHz Crystal Oscillator The CYBT-213043-02 includes connections for an external 32-kHz oscillator to provide accurate timing during low power operations. Figure 11 shows the 32-kHz XTAL oscillator with external components and Table 9 lists the oscillator characteristics. This oscillator can be operated with a 32 kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must have an accuracy of 250 ppm or better per the BT spec over temperature and including aging. The default component values are:
R1 = 10 MO and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator. Figure 11. 32 kHz Oscillator Block Diagram Document Number: 002-26540 Rev. **
Page 17 of 45 PRELIMINARY CYBT-213043-02 Unit kHz ppm W k pF pF Table 9. XTAL Oscillator Characteristics Symbol Parameter Conditions Minimum Typical Maximum 32.768 Foscout Pdrv Rseries Cshunt Cl Over temperature and aging For crystal selection For crystal selection For crystal selection For crystal selection Output frequency Frequency tolerance XTAL drive level XTAL series resistance XTAL shunt capacitance Load capacitance Power Modes The CYBT-213043-02 support the following HW power modes are supported:
Active mode - Normal operating mode in which all peripherals are available and the CPU is active. Idle mode - CPU is paused. Sleep mode - All systems clocks idle except for LPO. The device can wake up either after a programmed period of time has expired or if an external event is received via one of the GPIOs. In Sleep mode, the CPU is in WFI (wait for interrupt) and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. The state of the device is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained. 250 0.5 70 2.2
-
6 PDS (Power Down Sleep) mode - radio powered down and digital core mostly powered down except for RAM, registers, and some core logic. CYBT-213043-02 can wake up either after a programmed period of time has expired or if an external event is received via one of the GPIO. ePDS (extended PDS) - This power mode is an extension of PDS Mode. In this mode, only the main RAM and ePDS control circuitry retains power. As in other modes, the CYBT-213043-02 can wake up either after a programmed period or upon receiving an external event. HIDOFF (Deep Sleep) mode - Core, radio, and regulators powered down. Only the LHL IO domain is powered. In this mode, the CYBT-213043-02 can be woken up either by an event on one of the GPIOs or after a certain amount of time has expired. After wakeup, the part will go through full FW initialization although it will retain enough information to determine that it came out of HID-Off and the event the caused the wake up. The LPO and RTC are turned off in the HIDOFF power mode. Transition between power modes is handled by the on-chip firmware with host/application involvement. Refer to Firmware Section for details. Firmware The CYBT-213043-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes. The ROM also supports OTA firmware update. The CYBT-213043-02 is fully supported by the Cypress ModusToolbox IDE. ModusToolbox releases provide latest ROM patches, drivers, and sample applications allowing customized applications using the CYBT-213043-02 to be built quickly and efficiently. Watchdog CYBT-213043-02 includes an onboard watchdog with a period of approximately 4 seconds. The watchdog generates an interrupt to the Firmware after 2 seconds of inactivity and resets the device after 4 seconds. Lockout Functionality The CYBT-213043-02 powers up with JTAG and SWD access to flash and RAM is disabled. After reset, FW checks OCF for the presence of a security lockout field. If present, FW leaves JTAG and SWD Flash and RAM access disabled and also blocks any HCI commands from reading the raw contents of the RAM or Flash. This provides an effective way of protection against tampering, dumping, probing, or reverse engineering of the user application stored in the on-chip flash. The only firmware upgrade path in this scenario is secure over-the-air (OTA) update. The security field can be programmed in the factory after all programming and testing has been done. True Random Number Generator The CYBT-213043-02 includes a hardware TRNG (True Random Number Generator). Applications can access the random number generator via the firmware driver. Document Number: 002-26540 Rev. **
Page 18 of 45 PRELIMINARY CYBT-213043-02 Peripherals and Communication Interfaces I2C The CYBT-213043-02 provides a 2-pin I2C master/slave interface to communicate with I2C compatible peripherals. The following transfer clock rates are supported:
100 kHz 400 kHz 800 kHz (Not a standard I2C-compatible speed) 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed) The I2C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where read/write can be up to 64 bytes. SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 4), allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. BSC does not support multimaster capability or flexible wait-state insertion by either master or slave devices. HCI UART Interface CYBT-213043-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYBT-213043-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within 5%. The UART interface CYBT-213043-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-213043-02 or allow the CYBT-213043-02 to sleep when radio activities permit. The CYBT-213043-02 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. Combined, the two signals allow the host and the CYBT-213043-02 to optimize system power consumption by allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific command. The FW UART driver allows applications to select different baud rates. Peripheral UART Interface The CYBT-213043-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the same as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be configured individually and separately for each functional pin. The CYBT-213043-02 can map the peripheral UART to any LHL GPIO. Serial Peripheral Interface The CYBT-213043-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI operations. Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-213043-02 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO/VDDM. Document Number: 002-26540 Rev. **
Page 19 of 45 PRELIMINARY CYBT-213043-02 ADC Port The CYBT-213043-02 includes a - ADC designed for audio and DC measurements. The ADC can measure the voltage on 15 GPIOs (P0, P1, P8-P15, P17, P28, P29, P32, P37). When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap reference has 5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in Direct Current (DC) Mode. The application can access the ADC through the ADC driver included in the firmware. The following CYBT-213043-02 module solder pads can be used as ADC inputs:
Pad 4: P29, ADC Input Channel 10 Pad 5: P32, ADC Input Channel 7 Pad 7: P37, ADC Input Channel 2 Pad 8: P28, ADC Input Channel 11 Pad 9: P0, ADC Input Channel 29 Pad 10: P13, ADC Input Channels 28 Pad 11: P10, ADC Input Channel 25 Pad 12: P13, ADC Input Channel 22 Pad 14: P12, ADC Input Channel 23 Pad 15: P11, ADC Input Channels 24 Pad 16: P9, ADC Input Channels 26 Pad 17: P14, ADC Input Channels 21 Pad 18: P17, ADC Input Channels 18 Pad 26: P15, ADC Input Channels 20 Pad 27: P8, ADC Input Channels 27 GPIO Port The CYBT-213043-02 has a maximum of 22 GPIOs. All GPIOs support the following:
Programmable pull-up/down of approximately 45 KW. Input disable, allowing pins to be left floating or analog signals connected without risk of leakage. Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V. P26/P27/P28/P29 can sink/source 16 mA at 3.3 V and 8 mA at 1.8 V. Most peripheral functions can be assigned to any GPIO using the ModusToolbox Device Configurator. For details on the functions that are assignable via the ModusToolbox Device Configurator, refer to Table 5. The following list details the GPIOs that are available on the CYBT-213043-02 module:
P0-P6, P8-P15, P17, P26-P29, P32, and P37 Document Number: 002-26540 Rev. **
Page 20 of 45 PRELIMINARY CYBT-213043-02 PWM The CYBT-213043-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:
Each of the six PWM channels contains the following registers:
16-bit initial value register (read/write) 16-bit toggle register (read/write) 16-bit PWM counter value register (read) PWM configuration register shared among PWM05 (read/write). This 18-bit register is used:
To configure each PWM channel To select the clock of each PWM channel To change the phase of each PWM channel The application can access the PWM module through the FW driver. Figure 12 shows the structure of one PWM channel. Figure 12. PWM Block Diagram PDM Microphone The CYBT-213043-02 accepts a -based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:
8 kHz 16 kHz The external digital microphone takes in a 2.4-MHz clock generated by the CYBT-213043-02 and outputs a PDM signal, which is registered by the PDM interface with either the rising or falling edge of the 2.4-MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible. Document Number: 002-26540 Rev. **
Page 21 of 45 PRELIMINARY CYBT-213043-02 I2S Interface The CYBT-213043-02 supports a single I2S digital audio port. with both master and slave modes. The I2S signals are:
I2S Clock: I2S SCK I2S Word Select: I2S WS I2S Data Out: I2S DO I2S Data In: I2S DI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYBT-213043-02 are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK. The clock rate in master mode is either one of the following:
32 kHz 32 bits per frame = 1024 kHz 32 kHz 50 bits per frame = 1600 kHz The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz. Note: The PCM interface shares HW with the I2S interface and only one can be used at a given time. PCM Interface The CYBT-213043-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-213043-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-213043-02.The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Note: The PCM interface shares HW with the I2S interface and only one can be used at a given time. Note: Only audio source (other than SCO) use cases are supported on 20819 at this time. Slot Mapping The CYBT-213043-02 supports up to three simultaneous full-duplex channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The CYBT-213043-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The CYBT-213043-02 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYBT-213043-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2s complement data, left justified, and clocked MSB first. Document Number: 002-26540 Rev. **
Page 22 of 45 PRELIMINARY CYBT-213043-02 Electrical Characteristics The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 10. Silicon Absolute Maximum Ratings Requirement Parameter Maximum Junction Temperature VDDO1/VDDO2 IFVDD/PLLVDD/VCOVDD/VDDC PMUAVDD/SR_PVDD DIGLDO_VDDIN RFLDO_VDDIN MIC_AVDD Table 11. ESD/Latch-up Requirement Parameter ESD Tolerance HBM (Silicon) ESD Tolerance CDM (Silicon) Latch-up Table 12. Power Supply Specifications Min. 0.5 0.5 0.5 0.5 0.5 0.5 Min. 2000 500 Specification Nom. Specification Nom. 200 Parameter Conditions VDD input VDD Ripple VBAT Input PMU turn-on time Module Input Module Input Ripple (VDD) Internal to Module (not accessible) VBAT is ready. Min. 1.76 1.90 Typical 3.0 3.0 Table 13. Shutdown Voltage (Brown Out) Parameter VSHUT Min. 1.54 Specification Typ. 1.62 Max. TBD 3.795 1.38 3.795 1.65 1.65 3.795 Max. 2000 500 Max. 3.63 100 3.6 300 Max. 1.7 Unit C V V V V V V Unit V V mA Unit V mV V s Unit V The CYBT-213043-02 uses an onboard low voltage detector to shut down the device when supply voltage (VDDBAT3V) drops below the operating range. Document Number: 002-26540 Rev. **
Page 23 of 45 PRELIMINARY CYBT-213043-02 Current Consumption Table 14 provides the current consumption measurements taken at the input of LDOIN and VDDIO combined (LDOIN = VDDIO =
3.0 V). Table 14. Current Consumption Operational Mode Conditions HCI RX TX PDS ePDS HID-Off (SDS) 48 MHz with Pause 48 MHz without Pause Continuous RX Continuous TX - 4 dBm All RAM retained 32 kHz XTAL on Silicon Core Buck Regulator Table 15. Core Buck Regulator Parameter Input Supply, VBAT Output Current Output Voltage Output Voltage Accuracy Ripple Voltage Output Inductor, L Output Capacitor, COUT Input Capacitor, CIN Input Supply Voltage Ramp Time Conditions DC Range Active Mode PDS Mode Active Mode PDS Mode, 40 mV min regulation window. Active Mode, includes line and load regulation. Before trim:
After trim:
Active Mode 2.2 H 25% inductor, DCR = 114 m 20%
4.7 F 10% capacitor, Total ESR < 20 m PDS Mode Components are included on module. 0 to 3.3 V Typical 1.3 2.55 5.9 5.8 16.5 8.7 1.75 Unit mA A Min. 1.62 1.1 0.76 4 2 40 1.6[3]
3.0[3]
4.0[3]
40 Typ. 3.0
< 60
< 60 1.26 0.94 Avg
(0.92-0.96) 3 40 2.2 4.7 10 Max. 3.63 100 70 1.4 1.4
+4
+2 Unit V mA V
%
%
mV H F s Note 3. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects. Document Number: 002-26540 Rev. **
Page 24 of 45 Digital LDO Table 16. Digital LDO Parameter Input Supply, DIGLDO_VDDIN Output Voltage, DIGLDO_VDDOUT Dropout Voltage Output Current Quiescent Current Output Load Capacitor, COUT Line Regulation Load Regulation Load Step Error Leakage Current In-rush Current LDO Turn On Time PSRR RF LDO Table 17. RF LDO Parameter Input Supply, RFLDO_VDDIN Output Voltage, RFLDO_VDDOUT Dropout Voltage Output Current Quiescent Current Output Load Capacitor, COUT Line Regulation Load Regulation Load Step Error Leakage Current PRELIMINARY CYBT-213043-02 Condition Min Min must be met for correct operation Range Step Accuracy after trimming At max load current DC Load At T 85 C, VIN = 1.4 V Total trace + cap ESR must be < 80 m 1.235 V VIN 1.4 V VOUT = 1.2 V, VIN = 1.26 V, 1 mA IOUT 25 mA IOUT step 1 mA 20 mA @ 1 s rise/fall, COUT = 2.2 F, VIN = 1.235 V, VOUT = 1.2 V Power down Mode, VIN = 1.4 V, Temp = 25 C Power down Mode, VIN = 1.4 V, Temp = 125 C COUT = 2.2 F, VIN = 1.4 V, VOUT = 1.2 V COUT = 2.2 F, VIN = 1.4 V, VOUT = 1.2 V, IOUT = 20 mA COUT = 2.2 F, 1.235V VIN 1.4 V, VOUT = 1.2 V, IOUT = 20 mA f = 1 kHz f = 100 kHz Typ Max 1.4 1.275 Unit V 0.9 2 VOUT + 20 mV 1.26 1.2 25 40 2.2 5 1.55[4]
0.075 mV
%
+2 mV 20 mA 60 A 40 F 10 mV/V 0.44 mV/mA 24 25 13
+24 50 2 100 120 Typ. Max. 1.4 1.275 Conditions Min. Min must be met for correct operation Range Step Accuracy after trimming At max load current DC Load At T 85 C, VIN = 1.4 V Total trace + cap ESR must be < 80 m 1.235 V VIN 1.4 V VOUT = 1.2 V, VIN = 1.26 V, 1 mA IOUT 25 mA IOUT step 1 mA 20 mA @ 1 s rise/fall, COUT = 2.2 F, VIN = 1.235 V, VOUT = 1.2 V Power down Mode, VIN = 1.4 V, Temp = 25 C Power down Mode, VIN = 1.4 V, Temp = 125 C COUT = 2.2 F, VIN = 1.4 V, VOUT = 1.2 V COUT = 2.2 F, VIN = 1.4 V, VOUT = 1.2 V, IOUT = 20 mA 1.1 2 VOUT + 20 mV 1.26 1.2 25 20 2.2 5 1.55[4]
0.075 24 mV nA A mA s dB dB Unit V mV
%
+2 mV 20 mA 60 A 40 F 10 mV/V 0.44 mV/mA
+24 50 2 100 120 mV nA A mA s Page 25 of 45 In-rush Current LDO Turn On Time Note 4. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects. Document Number: 002-26540 Rev. **
PRELIMINARY CYBT-213043-02 Table 17. RF LDO (continued) Parameter PSRR Noise Conditions Min. Typ. Max. Unit COUT = 2.2 F, 1.235 V VIN 1.4 V, VOUT = 1.2 V, IOUT = 20 mA f = 1 kHz f = 100 kHz COUT = 2.2 F, VIN = 1.235 V, VOUT = 1.2 V, IOUT =
20 mA f = 30 kHz f = 100 kHz 25 13 dB dB 80 70 nVHz nVHz Digital I/O Characteristics Table 18. Digital I/O Characteristics Characteristics Symbol Minimum Typical Maximum Input low voltage (VDD = 3 V) Input high voltage (VDD = 3 V) Input low voltage (VDD = 1.8 V) Input high voltage (VDD = 1.8 V) Output low voltage Output high voltage Input low current Input high current Output low current (VDD = 3 V, VOL = 0.4 V) Output low current (VDD = 3 V, VOL = 1.8 V) Output high current (VDD = 3 V, VOH = 2.6 V) Output high current (VDD = 1.8 V, VOH = 1.4 V) Input capacitance ADC Characteristics Table 19. Electrical Characteristics VIL VIH VIL VIH VOL VOH IIL IIH IOL IOL IOH IOH CIN 2.4 1.4 VDDO 0.4 V 0.8 0.4 0.4 1.0 1.0 4.0 2.0 8.0 4.0 0.4 Parameter Current consumption Power down current ADC Core Specification ADC reference voltage ADC sampling clock Absolute error ENOB ADC input full scale Symbol ITOT VREF FS Conditions/Comments At room temperature From BG with 3% accuracy Includes gain error, offset and distortion. Without factory calibration. Includes gain error, offset and distortion. After factory calibration. For audio application For static measurement For audio application For static measurement Min. 12 10 1.8 Typ. 2 1 0.85 12 13 1.6 Max. 3 5 2 3.6 Unit V V V V V V A A mA mA mA mA pF Unit mA A V MHz
%
%
Bit Document Number: 002-26540 Rev. **
Page 26 of 45 PRELIMINARY CYBT-213043-02 Table 19. Electrical Characteristics (continued) Parameter Symbol Conditions/Comments Conversion rate Signal bandwidth Input impedance Startup time MIC PGA Specifications MIC PGA gain range MIC PGA gain step MIC PGA gain error PGA input referred noise Passband gain flatness MIC Bias Specifications MIC bias output voltage MIC bias loading current MIC bias noise MIC bias PSRR ADC SNR ADC THD + N GPIO input voltage GPIO source impedance[5]
RIN For audio application For static measurement For audio application For static measurement For audio application For static measurement For audio application For static measurement Includes part-to-part gain variation At 42 dB PGA gain A-weighted PGA and ADC, 100 Hz4 kHz At 2.5-V supply Refers to PGA input 20 Hz to 8 kHz, A-weighted at 1 kHz A-weighted 0 dB PGA gain 3 dBFS input 0 dB PGA gain Always lower than avddBAT Resistance Capacitance Min. 8 50 20 10 500 0 1 0.5 40 78 74 Typ. 16 100 DC 10 20 1 2.1 Max. 8K 42 1 4 0.5 3 3 3.6 1 10 Unit kHz Hz KW ms s dB dB dB V dB V mA V dB dB dB V k pF Note 5. Conditional requirement for the measurement time of 10 s. Relaxed with longer measurement time for each GPIO input channel. Document Number: 002-26540 Rev. **
Page 27 of 45 PRELIMINARY CYBT-213043-02 Chipset RF Specifications Table 20, Table 21, Table 22, and Table 23 apply to single-ended industrial temperatures. Unused inputs are left open. Table 20. BR/EDR - Receiver RF Specifications Parameter Mode and Conditions Receiver Section Frequency range RX sensitivity GFSK, BDR GFSK 0.1% BER, 1 Mbps EDR 2M EDR 3M Maximum input Interference Performance GFSK, BDR GFSK 0.1% BER[]
C/I cochannel GFSK, BDR GFSK 0.1% BER[]
C/I 1 MHz adjacent channel GFSK, BDR GFSK 0.1% BER[]
C/I 2 MHz adjacent channel GFSK, BDR GFSK 0.1% BER[]
C/I 3 MHz adjacent channel GFSK, BDR GFSK 0.1% BER[]
C/I image channel C/I 1 MHz adjacent to image channel GFSK, BDR GFSK 0.1% BER[]
Out-of-Band Blocking Performance (CW)[]
30 MHz to 2000 MHz 2000 MHz to 2399 MHz 2498 MHz to 3000 MHz 3000 MHz to 12.75 GHz Intermodulation Performance[]
BT, interferer signal level Spurious Emissions 30 MHz to 1 GHz 1 GHz to 12.75 GHz BDR GFSK 0.1% BER BDR GFSK 0.1% BER BDR GFSK 0.1% BER BDR GFSK 0.1% BER BDR GFSK 0.1% BER Min 2402 20 Typ 92[]
93.5 87 10.0 27 27 10.0 Max 2480 11.0 0.0 30.0 40.0 9.0 20.0 39.0 57.0 55.0 Unit MHz dBm dB dBm dB dBm dBm dBm
. Notes 6. The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off. 7. Desired signal is 10 dB above the reference sensitivity level (defined as 70 dBm). 8. Desired signal is 3 dB above the reference sensitivity level (defined as 70 dBm). 9. Desired signal is 64 dBm Bluetooth-modulated signal, interferer 1 is 39 dBm sine wave at frequency f1, interferer 2 is 39 dBm Bluetooth-modulated signal at frequency f2, f0 = 2 * f1 f2, and |f2 f1| = n * 1 MHz, where n = 3, 4, or 5. For the typical case, n = 4. Document Number: 002-26540 Rev. **
Page 28 of 45 PRELIMINARY CYBT-213043-02 Table 21. BR/EDR - Transmitter RF Specifications Parameter Transmitter Section Frequency range Class 2: BR TX power Class 2: EDR 2M and 3M TX power 20 dB bandwidth Adjacent Channel Power
|M N| = 2
|M N| 3 [10]
Out-of-Band Spurious Emission 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz LO Performance Initial carrier frequency tolerance Frequency Drift DH1 packet DH3 packet DH5 packet Drift rate Frequency Deviation Average deviation in payload (sequence used is 00001111) Maximum deviation in payload (sequence used is 10101010) Channel spacing Note 10. Meet SIG Specification. Table 22. BLE RF Specifications Min 2402 75 25 40 40 20 140 115 Typ 4.0 0 930 1 Max 2480 1000 20 40 36.0 30.0 47.0 47.0
+75
+25
+40
+40 20 175 Parameter Conditions Minimum Typical Maximum 2402 N/A Frequency range GFSK, BDR GFSK 0.1% BER 0.1% BER, RX sensitivity[11]
1 Mbps N/A TX power Mod Char: Delta F1 average N/A Mod Char: Delta F2 max[12]
N/A Mod Char: Ratio N/A Notes 11. Dirty TX is Off. 12. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. 225 99.9 0.8 95 4.0 255 2480 275 Unit MHz dBm kHz dBm dBm kHz kHz kHz/50 s kHz MHz Unit MHz dBm kHz
%
%
Document Number: 002-26540 Rev. **
Page 29 of 45 PRELIMINARY CYBT-213043-02 Table 23. BLE2 RF Specifications Parameter RX sensitivity[13]
TX power Note 13. 255 packet. Conditions Minimum Typical Maximum 89 4.0 Unit dBm Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. UART Timing Table 24. UART Timing Specifications Reference 1 2 3 Characteristics Delay time, UART_CTS_N low to UART_TXD valid. Setup time, UART_CTS_N high before midpoint of stop bit. Delay time, midpoint of stop bit to UART_RTS_N high. Min. Typ. Max. 1.50 0.67 1.33 Unit Bit periods Bit periods Bit periods Figure 13. UART Timing Document Number: 002-26540 Rev. **
Page 30 of 45 PRELIMINARY CYBT-213043-02 SPI Timing The SPI interface can be clocked up to 24 MHz. Table 25 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2. Table 25. SPI Mode 0 and 2 Reference 1 2 3 Characteristics Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Idle time between subsequent SPI transactions Min. 45 6 1 SCK Max. SCK Unit ns Figure 14. SPI Timing, Mode 0 and 2 Document Number: 002-26540 Rev. **
Page 31 of 45 PRELIMINARY CYBT-213043-02 Table 26 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3. Table 26. SPI Mode 1 and 3 Reference 1 2 3 Characteristics Time from master assert SPI_CSN to first clock edge Setup time for MOSI data lines Idle time between subsequent SPI transactions Min. 45 6 1 SCK Max. SCK Unit ns Figure 15. SPI Timing, Mode 1 and 3 Document Number: 002-26540 Rev. **
Page 32 of 45 PRELIMINARY CYBT-213043-02 I2C Compatible Interface Timing The specifications in Table 26 references Figure . Table 27. I2C Interface Timing Specifications (up to 1 MHz) Characteristics Reference 1 Clock frequency Minimum Maximum Unit 100 400 800 1000 kHz START condition setup time START condition hold time Clock low time Clock high time Data input hold time[14]
Data input setup time STOP condition setup time Output valid from clock Bus free time[15]
2 3 4 5 6 7 8 9 10 Notes 14. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 15. Time that the CBUS must be free before a new transaction can start. 650 280 650 280 0 100 280 650 400 ns Figure 16. I2C Interface Timing Diagram Document Number: 002-26540 Rev. **
Page 33 of 45 PRELIMINARY CYBT-213043-02 I2S Interface Timing I2S timing is shown below in Table 28, Figure 17, and Figure 18. Table 28. Timing for I2S Transmitters and Receivers Clock Period T HIGH tHC LOWtLC HIGH tHC LOW tLC Rise time tRC Delay tdtr Hold time thtr Transmitter Receiver Lower LImit Min Max Ttr Upper Limit Min Max Lower Limit Min Max Tr Upper Limit Min Max Master Mode: Clock generated by transmitter or receiver 0.35Ttr 0.35Ttr Slave Mode: Clock accepted by transmitter or receiver 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.35Ttr 0.15Ttr 0 Transmitter Receiver 0.8T Notes
[16]
[17]
[17]
[16]
[16]
[17]
[18]
[17]
Setup time tsr Hold time thr Notes 16. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 17. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with 18. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 19. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. 20. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 0.2Ttr 0.2Ttr
[19]
[19]
respect to T. 21. The data setup and hold time must not be less than the specified receiver setup and hold time. Document Number: 002-26540 Rev. **
Page 34 of 45 PRELIMINARY CYBT-213043-02 Figure 17. I2S Transmitter Timing Figure 18. I2S Receiver Timing Document Number: 002-26540 Rev. **
Page 35 of 45 PRELIMINARY CYBT-213043-02 Environmental Specifications Environmental Compliance This Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBT-213043-02 module is certified under the following RF certification standards:
FCC: WAP3034 ISED: 7922A-3034 MIC: TBD CE Safety Certification The CYBT-213043-02 module complies with the following safety regulations:
Underwriters Laboratories, Inc. (UL): Filing E331901 CSA TUV Environmental Conditions Table 29 describes the operating and storage conditions for the Cypress Bluetooth module. Table 29. Environmental Conditions for CYBT-213043-02 Description Minimum Specification Maximum Specification Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity ESD: Module integrated into system Components[22]
30 C 5%
40 C 85 C 85%
10 C/minute 85 C 85 C at 85%
15 kV Air 2.0 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 22. This does not apply to the RF pins (ANT). Document Number: 002-26540 Rev. **
Page 36 of 45 PRELIMINARY CYBT-213043-02 Regulatory Information FCC FCC NOTICE:
The device CYBT-213043-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3034. In any case the end product must be labeled exterior with Contains FCC ID: WAP3034. ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 13. When integrated in the OEMs product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna not in Table 7 on page 13 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 7 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBT-213043-02 with the integrated PCB trace antenna (FCC ID: WAP3034) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-213043-02 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-26540 Rev. **
Page 37 of 45 PRELIMINARY CYBT-213043-02 ISED Innovation, Science and Economic Development (ISED) Canada Certification CYBT-213043-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-3034 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antenna listed in Table 7 on page 13, having a maximum gain of -0.5 dBi. Antennas not included in Table 7 on page 13 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. ISED NOTICE:
The device CYBT-213043-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. L'appareil CYBT-213043-02, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences d'approbation de l'metteur modulaire tel que dcrit dans RSS-GEN. L'opration est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interfrences nuisibles, et (2) Cet appareil doit accepter toute interfrence reue, y compris les interfrences pouvant entraner un fonctionnement indsirable. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3034. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3034". Le fabricant d'quipement d'origine (OEM) doit s'assurer que les exigences d'tiquetage ISED sont respectes. Cela comprend une tiquette clairement visible l'extrieur de l'enceinte OEM spcifiant l'identifiant Cypress Semiconductor IC appropri pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3034. En tout cas, le produit final doit tre tiquet dans son extrieur avec "Contient IC: 7922A-3034". Document Number: 002-26540 Rev. **
Page 38 of 45 PRELIMINARY CYBT-213043-02 European Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-213043-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
All versions of the CYBT-213043-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. MIC Japan CYBT-213043-02 is certified as a module with certification number TBD. End products that integrate CYBT-213043-02 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. TBD Document Number: 002-26540 Rev. **
Page 39 of 45 PRELIMINARY CYBT-213043-02 Packaging Table 30. Solder Reflow Peak Temperature Module Part Number Package 35-pad SMT CYBT-213043-02 Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles 260 C 30 seconds 2 Table 31. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number CYBT-213043-02 Package 35-pad SMT MSL MSL 3 The CYBT-213043-02 is offered in tape and reel packaging. Figure 19 details the tape dimensions used for the CYBT-213043-02. Figure 19. CYBT-213043-02 Tape Dimensions Figure 20 details the orientation of the CYBT-213043-02 in the tape as well as the direction for unreeling. Figure 20. Component Orientation in Tape and Unreeling Direction Document Number: 002-26540 Rev. **
Page 40 of 45 PRELIMINARY CYBT-213043-02 Figure 21 details reel dimensions used for the CYBT-213043-02. Figure 21. Reel Dimensions The CYBT-213043-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-213043-02 is detailed in Figure 22. Figure 22. CYBT-213043-02 Center of Mass Document Number: 002-26540 Rev. **
Page 41 of 45 Top View (Seen from Top) PRELIMINARY CYBT-213043-02 Ordering Information Table 32 lists the CYBT-213043-02 part number and features. Table 32 also lists the target program for the respective module ordering codes. Table 33 lists the reel shipment quantities for the CYBT-213043-02. Table 32. Ordering Information Ordering Part Number Max CPU Speed
(MHz) CYBT-213043-02 96 Flash Size
(KB) 256 RAM Size
(KB) 176 UART I2C SPI I2S PCM PWM ADC Yes Yes Yes Yes Yes 6 Inputs GPIOs Package Packaging 35-SMT Tape and Reel 15 22 Table 33. Tape and Reel Package Quantity and Minimum Order Amount Description Reel Quantity Minimum Order Quantity (MOQ) Order Increment (OI) 500 500 500 500 Minimum Reel Quantity Maximum Reel Quantity Comments Ships in 500 unit reel quantities. The CYBT-213043-02 is offered in tape and reel packaging. The CYBT-213043-02 ships in a reel size of 500 units. For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address 198 Champion Court, San Jose, CA 95134 http://www.cypress.com
(408) 943-2600 Document Number: 002-26540 Rev. **
Page 42 of 45 PRELIMINARY CYBT-213043-02 Acronyms Table 34. Acronyms Used in this Document Description Acronym Document Conventions Units of Measure Table 35. Units of Measure Symbol C dB dBi dBm kV mA mm mV A m MHz GHz V Unit of Measure degree Celsius decibel decibels relative to isotropic decibel-milliwatts kilovolt milliamperes millimeters millivolt microamperes micrometers megahertz gigahertz volt Bluetooth Low Energy BLE Bluetooth SIG Bluetooth Special Interest Group CE CSA EMI ESD FCC GPIO European Conformity Canadian Standards Association electromagnetic interference electrostatic discharge Federal Communications Commission general-purpose input/output Innovation, Science and Economic Devel-
opment (Canada) integrated design environment Korea Certification Ministry of Internal Affairs and Communications
(Japan) printed circuit board receive qualification design ID surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs timer, counter, pulse width modulator (PWM) Germany: Technischer berwachungs-Verein
(Technical Inspection Association) transmit ISED IDE KC MIC PCB RX QDID SMT TCPWM TUV TX Document Number: 002-26540 Rev. **
Page 43 of 45 PRELIMINARY CYBT-213043-02 Document History Page Document Title: CYBT-213043-02 EZ-BT Module Document Number: 002-26540 Orig. of Revision Change Submission Date ECN
**
6487647 DSO Description of Change 02/21/2019 Preliminary datasheet for CYBT-213043-02 module. Document Number: 002-26540 Rev. **
Page 44 of 45 PRELIMINARY CYBT-213043-02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Arm Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory Microcontrollers PSoC Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless Cypress Semiconductor Corporation, 2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-26540 Rev. **
Revised February 21, 2019 Page 45 of 45
| frequency | equipment class | purpose | ||
|---|---|---|---|---|
| 1 | 2019-03-19 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Original Equipment |
| 2 | 2402 ~ 2480 | DTS - Digital Transmission System |
| app s | Applicant Information | |||||
|---|---|---|---|---|---|---|
| 1 2 | Effective |
2019-03-19
|
||||
| 1 2 | Applicant's complete, legal business name |
Cypress Semiconductor
|
||||
| 1 2 | FCC Registration Number (FRN) |
0017759150
|
||||
| 1 2 | Physical Address |
198 Champion Court
|
||||
| 1 2 |
San Jose, California 95134
|
|||||
| 1 2 |
United States
|
|||||
| app s | TCB Information | |||||
| 1 2 | TCB Application Email Address |
a******@dekra.com
|
||||
| 1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
| app s | FCC ID | |||||
| 1 2 | Grantee Code |
WAP
|
||||
| 1 2 | Equipment Product Code |
3043
|
||||
| app s | Person at the applicant's address to receive grant or for contact | |||||
| 1 2 | Name |
D******** S******
|
||||
| 1 2 | Title |
Sr. Business Unit Director
|
||||
| 1 2 | Telephone Number |
408-5********
|
||||
| 1 2 | Fax Number |
408-5********
|
||||
| 1 2 |
d******@cypress.com
|
|||||
| app s | Technical Contact | |||||
| n/a | ||||||
| app s | Non Technical Contact | |||||
| n/a | ||||||
| app s | Confidentiality (long or short term) | |||||
| 1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
| 1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
| if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
| app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
| 1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
| 1 2 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
| 1 2 | DTS - Digital Transmission System | |||||
| 1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | This product is a Bluetooth wireless EZ-BT WICED Module | ||||
| 1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
| 1 2 | Modular Equipment Type | Single Modular Approval | ||||
| 1 2 | Purpose / Application is for | Original Equipment | ||||
| 1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
| 1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
| 1 2 | Grant Comments | Output power is conducted Single Modular Approval. Compliance of this device in all final product configurations is the responsibility of the Grantee. Installation of this device into specific final products may require the submission of a Class II permissive change application containing data pertinent to RF Exposure, emissions and host/module authentication, or new application if appropriate. This device meets the SAR Test Exclusion threshold specified in KDB447498 and it has also been evaluated with respect to RF Exposure compliance since then, it is authorized for portable and mobile operation. Multi-transmitter, supporting simultaneous transmission, configurations have not been evaluated and shall be evaluated according to KDB Publication 447498 and §15.31(h) and §15.31(k) composite system. | ||||
| 1 2 | Output power is conducted. Single Modular Approval. Compliance of this device in all final product configurations is the responsibility of the Grantee. Installation of this device into specific final products may require the submission of a Class II permissive change application containing data pertinent to RF Exposure, emissions and host/module authentication, or new application if appropriate. This device meets the SAR Test Exclusion threshold specified in KDB447498 and it has also been evaluated with respect to RF Exposure compliance since then, it is authorized for portable and mobile operation. Multi-transmitter, supporting simultaneous transmission, configurations have not been evaluated and shall be evaluated according to KDB Publication 447498 and §15.31(h) and §15.31(k) composite system. | |||||
| 1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
| 1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
| app s | Test Firm Name and Contact Information | |||||
| 1 2 | Firm Name |
DEKRA Testing and Certification (Suzhou) Co., Ltd.
|
||||
| 1 2 | Name |
J****** X****
|
||||
| 1 2 | Telephone Number |
86 51********
|
||||
| 1 2 |
j******@dekra.com
|
|||||
| Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
| 1 | 1 | 15C | CC | 2402 | 2480 | 0.0024 | |||||||||||||||||||||||||||||||||||
| 1 | 2 | 15C | CC | 2402 | 2480 | 0.0016 | |||||||||||||||||||||||||||||||||||
| 1 | 3 | 15C | CC | 2402 | 2480 | 0.0017 | |||||||||||||||||||||||||||||||||||
| Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
| 2 | 1 | 15C | CC | 2402 | 2480 | 0.0028 | |||||||||||||||||||||||||||||||||||
| 2 | 2 | 15C | CC | 2402 | 2480 | 0.0025 | |||||||||||||||||||||||||||||||||||
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC