FCC ID: WAP-CYSBSYS-RP01 Wifi 802.11b/g/n/ac + BT/BLE

Please note that Cypress is an Infineon Technologies Company.The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.Continuity of document contentThe fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page.Continuity of ordering part numbersInfineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering.www.infineon.com PRELIMINARY CYSBSYS-RP01Rapid IoT ConnectGeneral DescriptionThe SubSystems CYSBSYS-RP01 Rapid IoT Connect module is the easiest way to provide a secure, scalable, and reliable connection from your device to your cloud. CYSBSYS-RP01 is apre-certified 802.11ac-friendly dual-band (2.4 and 5.0 GHz)Wi-Fi and Bluetooth 5.0-compliant combo radio module. The module includes a PSoC 6 MCU with an Arm Cortex-M4F CPU, a single-chip radio, on-board crystals, oscillators, chip antenna, and passive components.CYSBSYS-RP01 provides up to 51 I/Os in a 26.6 x 14.0 x 2.9 mm castellated surface-mount PCB for easy manufacturing. When combined with Cypress SubSystems connectivity services, CYSBSYS-RP01 is the fastest way to deploy a secure and reliable network of IoT devices.100-MHz Arm Cortex-M4F CPU with single-cycle multiply(Floating Point and Memory Protection Unit)512-KB application flash with 16-KB EEPROM area 512-KB SRAMBackup domain with 64 bytes of memory and Real-Time-Clock(RTC)Up to 51 programmable GPIOCertified to FCC, ISED, and CE regulations Industrial temperature range: -20 C to +70 C Key Features Size: 26.59 mm 14 mm x 2.5 mm (L x W x H) Weight: 15 gm Dual-band 2.4-GHz/5-GHz radio On-board chip antenna or external antenna variant Full IEEE 802.11a/b/g/n compatibility with enhanced perfor- mance 802.11ac-friendly[1], MCS8 (256-QAM) for 20-MHz channels Ordering Information NoteBluetooth 5.0-compliant with LE 2-Mbps data rate for BluetoothLow EnergySupports all optional Bluetooth 4.2 features - LE SecureConnections, LE Privacy 1.2, and LE Data Packet LengthExtensionsSupports BDR (1 Mbps), EDR (2 Mbps/3 Mbps), BLE(1 Mbps/2 Mbps)Adaptive frequency hopping (AFH) for reducing radiofrequency interferencePackage73-pin castellated solder pads0.8-mm pitch castellated solder padsBenefitsProven, qualified, certified, and ready to use hardware designSmall host footprint (27.79 15.20 mm 2.5 mm), perfect forspace-constrained applicationsCastellated solder pad connections for ease-of-useFully certified module eliminates the time needed for design,development, and certification processesFlexible and programmable MCU architecture, with program-mable digital and analog resourcesLarge non-volatile memory for complex application devel-opmentOver-the-air (OTA) update-capable for development or fieldupdatesPb-free, Halogen-free and RoHS-compliant.1. IEEE 802.11ac full-compliance requires support for 40-MHz and 80-MHz channel bandwidths. The radio on CYSBSYS-RP01 is 802.11ac-friendly. It only supports20-MHz channel bandwidth; however, it supports 802.11ac's 256-QAM for 20-MHz channels in the 5-GHz band, enabling it to offer higher throughput and lower energyper bit than 802.11n-only products. San Jose, CA 95134-1709 408-943-2600Cypress Semiconductor Corporation 198 Champion Court Document Number: 002-29368 Rev. *C Revised June 19, 2020CYSBSYS-RP01, Rapid IoT ConnectPart NumberDescriptionAvailabilityCYSBSYS-RP01Rapid IoT Connect with on board chip antennaRestricted samplingCYSBSYSKIT-01Rapid IoT Connect Platform RP01 Feather KitRestricted sampling PRELIMINARYCYSBSYS-RP01Contents Overview............................................................................ 3 Functional Block Diagram ...............................................3 PSoC 6 MCU...................................................................... 4 Dual-band 802.11ac-friendly Radio with BT 5.0............. 4Crystal and Oscillators ....................................................4 Chip Antenna for Wi-Fi / BT and u.FL Connector (CYSBSYS-RP01) ..............................................................4 CapSense External Modulation and Integration Capacitors .........................................................................4 Mechanical Dimensions ...................................................5 Castellated Pads Layout ..................................................6 Recommended Host PCB Layout ....................................7System Connections........................................................ 8 Castellated Pads Pin Description ...................................9External Reset (XRES) ...................................................13 Electrical Specifications ................................................13 Absolute Maximum Ratings .......................................13Recommended Operating Conditions ..........................14 DC Specifications ......................................................14 GPIO DC Specifications ............................................14External ECO Specification ...........................................14 Environmental Conditions............................................ 15 ESD and EMI Protection ................................................ 15 Regulatory Information ................................................. 15 FCC........................................................................... 15 ISED.......................................................................... 16 Document Conventions ................................................. 21 Sales, Solutions, and Legal Information ..................... 22 Document Number: 002-29368 Rev. *C Page 2 of 22 Ordering Information ..................................................... 20 Part Numbering Convention......................................... 20 Acronyms ....................................................................... 21 European Declaration of Conformity ......................... 17 Packaging........................................................................ 18 Worldwide Sales and Design Support....................... 22 Products .................................................................... 22 PSoC Solutions ...................................................... 22 Cypress Developer Community ................................. 22 CINT PRELIMINARYCYSBSYS-RP01OverviewFunctional Block DiagramFigure 1. Functional Block DiagramPSoC 6 MCUCMODCINT32 kHzOscillatorDualBandRadio2G TX2G RXBT5G TX5G RX2G SP3T5G SP3T2G5GDiplexerRFMatchingNetworkANTVDDUSBVDDA, VDDIO1 VDDIO0VDD_NS, VDDD, VDDIO2,VBACKUP1.83.3V1.8V/ 2.5V1.8V54 I/OsXRESPower andPSoC IOs(0.8mmcastellated pads)SDIO, UART, ControlVDDIOVBATUMCConnectorCYSBSYS-RP01 provides GPIO of PSoC 6 MCU via castellated solder pads. It has onboard connection between PSoC 6 MCU and single-chip, ultra-low-power, IEEE 802.11n-compliant, IEEE 802.11ac-friendly Wi-Fi with integrated Bluetooth 5.0 radio.CYSBSYS-RP01 has an onboard dual-band chip antenna Wi-Fi / BT and u.FL connector (CYSBSYS-RP01-UFL) for external antenna connection. CYSBSYS-RP01 has an onboard 32-kHz oscillator for the WCO of PSoC 6 MCU and the radio Wi-Fi sleep clock. It has the modulation and integration capacitors required for capacitive sensing. Furthermore, it has the diplexer and RF switches required for RF functionality.CYSBSYS-RP01 is a complete hardware solution designed to be soldered to the applications main board. It provides a certified system for customers to design their end solutions.Figure 2. Key ComponentsChip AntennaAntenna Matching NetworkDiplexerSP3T 5GSP3T 5GDualband802.11ac friendlywith BT 5.0Radio Crystal 37.4 MHzCMODUMC Connector (No Load)CINTSoldering PADs for RF ShieldPSoC 6 MCU0.8-mm Castellated PadsLPO 32 kHzDocument Number: 002-29368 Rev. *C Page 3 of 22 SDIO (6 I/Os) / UART (4 I/Os) /Control (6 I/Os)1.83.3V1.8V3.6V PRELIMINARYCYSBSYS-RP01There are five major subsystems:PSoC 6 MCUSingle-chip, ultra-low-power, IEEE 802.11n-compliant, IEEE 802.11ac-friendly Wi-Fi with Integrated Bluetooth 5.0 radio Crystal and oscillatorsChip antenna for Wi-Fi / BT and u.FL connectorCapSense external modulation and integration capacitors and other passives like bypass capacitors and limiting resistors.PSoC 6 MCUThe PSoC 6 MCU product family, based on an ultra-low-power 40-nm platform, is a combination of a microcontroller with low-power flash technology and digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, and standard communication and timing peripherals.Dual-band 802.11ac-friendly Radio with BT 5.0This radio is purpose-built for IoT applications. This radio is a 28-nm, ultra-low-power device that integrates a single-stream, dual-band IEEE 802.11n-compliant, IEEE 802.11ac-friendly Wi-Fi sub-system, a Bluetooth 5.0-compliant BT sub-system, and an advancedcoexistence engine for maximum combined performance. The 28-nm architecture enables dual-band 802.11ac-friendly with BT 5.0radio to offer best-in-class power consumption in active and power saving modes. 802.11ac-friendliness enables the radio toguarantee superior performance in terms of throughput and power consumption compared to 802.11n products when operating in802.11ac networks.Crystal and OscillatorsThe CYSBSYS-RP01 system has an onboard 32.768-kHz oscillator shared between PSoC 6 MCU and the radio. The 32.768-kHz oscillator is used by PSoC 6 MCU for the WCO block for deep sleep operation for low-power-mode timing.Chip Antenna for Wi-Fi / BT and u.FL ConnectorThe system has an ultra-miniature chip antenna that supports 5-GHz and 2.4-GHz bands. The selected antenna has an efficiency of up to 51% at 2.4 GHz at 48% for 5 GHz. See Recommended Host PCB Layout on page 7 for optimal placement of the CYSBSYS-RP01 board, and antenna efficiency details for different host board layouts.An additional footprint for a u.FL connector is also provided on board; this is used to connect an external antenna. See Ordering Information on page 22 for CYSBSYS-RP01 board variants with u.FL connector.CapSense External Modulation and Integration CapacitorsTo enable CapSense use cases on end applications, PSoC 6 MCU requires an external CMOD capacitor (modulator capacitor) forself-capacitance sensing, and CINTA and CINTB (integration capacitors) for mutual capacitance sensing. These external capacitorsare connected between a dedicated GPIO pin and ground.Document Number: 002-29368 Rev. *C Page 4 of 22 0 0 4 1

. 0 6 0

. 0 6 0

. 6 0 0 6 0 5 6 3 0 1 R E V 0 3 C Y S U B R P 0 1 0 0 8

. A E R A A N N E T N A 0 0 4 1

. 0 0 1

. PRELIMINARYMechanical DimensionsPhysical dimensions of CYSBSYS-RP01 system is as shown in Figure 3 and Table 1.Figure 3. Board Dimensions: Top Side and Bottom Views26.59CYSBSYS-RP011.01.50U3U4 A1Y1Y2U2U5U1J1Top View (View from Top) Side ViewANTENNAAREA1.93 0.80 5.060.500.401.93 #123.53Bottom View (View from Top)3.06#1Pad dimensionTable 1. Board DimensionsMark Dimension UnitL (typical) 26.59 mmW (typical) 14 mmPCB thickness 1.0 mmRF Shield height 1.5 mmT (Total System thickness, max) 2.5 mmDocument Number: 002-29368 Rev. *C Page 5 of 22 1 A 3 U 5 U 5 L 1 J 1 U 2 U L1 1 Y 2 Y 4 _ 8 P 0 _ 8 P 3 _ 8 P 2 _ 8 P 1 _ 8 P 3 _ 7 P 4 _ 0 P 5 _ 0 P D N G 3 _ 6 P 2 _ 6 P 0 _ 1 1 P 0 _ 0 1 P 1 _ 0 1 P 2 _ 0 1 P 3 _ 0 1 P 4 _ 0 1 P PRELIMINARYCYSBSYS-RP01Castellated Pads LayoutFigure 4. Board Pad Layout (Top view)GNDGNDGNDGNDGNDGNDP11_7P11_3P11_5P11_4P11_6P11_2P11_1GNDP5_5P6_0P6_1P5_4P5_1P5_0P5_2VBAT_WLVBAT_WLGNDVDDIO2P5_7P5_3P5_6GNDP7_0P6_6P6_5P6_7P6_4VDDIO1P9_1VDDAP9_3P9_0P9_4P9_7P9_2GNDP12_6P12_7VBACKUPVDDIO0VDDUSBUSBDMUSBDPGNDVDDDXRES_LP10_6P10_5P10_7Table 2. Board Pad LayoutPad Number Pad Name Pad Number Pad Name Pad Number Pad Name1GND 26 P5_7 51 GND2GND 27 P5_3 52 USBDP3GND 28 P5_6 53 USBDM4GND 29 P8_4 54 VDDUSB5GND 30 P8_0 55 VDDIO06GND 31 P8_3 56 VBACKUP7P11_7 32 P8_2 57 P12_78P11_3 33 P8_1 58 P12_69P11_5 34 P7_3 59 GND10P11_4 35 P0_4 60 P9_211P11_6 36 P0_5 61 P9_712P11_2 37 GND 62 P9_413P11_1 38 P6_3 63 P9_014GND 39 P6_2 64 P9_315P5_5 40 P11_0 65 VDDA16P6_0 41 P10_0 66 P9_117P6_1 42 P10_1 67 VDDIO118P5_4 43 P10_2 68 P6_419P5_1 44 P10_3 69 P6_720P5_0 45 P10_4 70 P6_521P5_2 46 P10_7 71 P6_622VBAT_WL 47 P10_5 72 P7_023VBAT_WL 48 P10_6 73 GND24 GND 49 XRES_L25 VDDIO_WL 50 VDDDDocument Number: 002-29368 Rev. *C Page 6 of 22 6 0 0 6 0 5 6 3 0 1 R E V 0 3 C Y S U B R P 0 1 0 0 8

. A E R A A N N E T N A 1 8 1 3 1

. 8 3 4 1

. 0 3 1

. 0 2 1

. 0 2 5 1

. 0 2 1

. 0 8 2 1

. 0 2 1

. PRELIMINARYCYSBSYS-RP01Recommended Host PCB LayoutFigure 5 provides details that can be used for the recommended host PCB layout pattern for CYSBSYS-RP01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.02 mm as shown in Figure 5 is the minimum recommended host pad length. All dimensions are referenced to the center of the solder pad.To maximize performance, the host layout should follow these recommendations:1.The ideal placement of the CYSBSYS-RP01 board is in a corner of the host board with the antenna located outside the edge of the host board. This placement minimizes the additional recommended keep out area stated in item 3.2.To maximize RF performance, the area immediately around the system antenna should contain a keep out area, where no grounding or signal traces are contained. This keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 5.3.If fanout of traces are done under the board, care should be taken to fill the used area under the board with copper plane to avoid any unbalanced surface that may lead to an assembly issue.4.No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area.Figure 5. Board Land Pattern on Host PCB (Top View Seen on Host PCB)27.79U3U4 A1Dont put any metal objects or batteries (if applicable) above or below the yellow region.Keep away any other metals from clearance area,including ground planeY1Y2U2U5U1J15.06ANTENNAAREAFlush the antenna side PCB edge to host PCB edge for optimal performanceRecommended Host PCB Keep Out Area2.5320.800.801.530.600.500.40Solder PasteLand PatternSolder Mask1.532.5324.133.66Host Land Pattern (View from Top) Pad dimensionsDocument Number: 002-29368 Rev. *C Page 7 of 22 PRELIMINARYCYSBSYS-RP01System ConnectionsPower Supply Connections and Recommended External ComponentsFigure 6 shows the general requirements for power pins on CYSBSYS-RP01. See the DC Specifications table for details on the entire range of supported voltage for each power pins.Figure 6. Board Power Pad Connections1.8VC2310uF10V1.8V~3.3V50U1AVDDDVBAT_WL1VBAT_WL222233.6V~4.2VGND1.8V *C3810uF10V1.8V65VDDAVDDIO_WL25C14.7uF25VGND 1.8VVBACKUPC24.7uFGNDC401uF25V1.8V~3.3VC391uF25V5567VDDIO0VDDIO1GND1GND2GND3GND4GND5GND6GND7GND81234561424GND25VNotes:VDDIO1 should be to VDDA.VDDUSB should be minimum2.85 V for USB1.8V~3.3VGND54GND10GND11VDDUSB GND12515973C31uF25VCYSBSYS-RP01GNDGNDBypass capacitors must be used from VBAT_WL, VDDD, and VDDA to ground and wherever indicated in the diagram. Typical practice for systems in this frequency range is to use a capacitor in the 10-F range. A parallel smaller capacitor for each domain is provided on the CYSBSYS-RP01 board. Note that these are rules of thumb: for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. All capacitors should be 20%, X5R ceramic or better.Power supplies and ports correspond as follows:P0: VBACKUPP5, P6, P7, P8: VDDIO1P9, P10: VDDIO, VDDAP11, P12, P13: VDDIO0Document Number: 002-29368 Rev. *C Page 8 of 22 GND56GND937 PRELIMINARYCYSBSYS-RP01Castellated Pads Pin DescriptionFigure 7. Castellated Pads Pinout35362019212718152826161768707169726366606462615857U1BP0_4P0_5P5_0P5_1P5_2P5_3P5_4P5_5P5_6P5_7P6_0P6_1P6_4P6_5P6_6P6_7P7_0P9_0P9_1P9_2P9_3P9_4P9_7P12_6P12_7XRES_LP10_0P10_1P10_2P10_3P10_4P10_5P10_6P10_7P6_3P6_2P11_0P11_1P11_2P11_3P11_4P11_5P11_6P11_7P7_3P8_0P8_1P8_2P8_3P8_4USBDMUSBDP494142434445474846383940131281091173430333231295352CYSBSYS-RP01Document Number: 002-29368 Rev. *C Page 9 of 22 PRELIMINARYCYSBSYS-RP01Each port pin has multiple alternate functions. These are defined in the table below. The columns ACT #x and DS #y denote active (System LP/ULP) and deep sleep mode signals respectively.Port.PinAct #0Act #1Act #2Act #3DS #2DS #3Act #4Act #5Act #6Act #7Act #8Act #9Act #10Act #12Act #13Act #14Act #15DS #5DS #6P0.4tcpwm[0].line[2]:0tcpwm[1].line[2]:0csd.csd_tx:4csd.csd_tx_n:4scb[0].uart_rts:0scb[0].spi_clk:0peri.tr_io_output[0]:2P0.5tcpwm[0].line_compl[2]:0tcpwm[1].line_compl[2]:0csd.csd_tx:5csd.csd_tx_n:5srss.ext_clk:1scb[0].uart_cts:0scb[0].spi_select0:0peri.tr_io_output[1]:2P5.0tcpwm[0].line[4]:0tcpwm[1].line[4]:0csd.csd_tx:30csd.csd_tx_n:30scb[5].uart_rx:0scb[5].i2c_scl:0scb[5].spi_mosi:0audioss[0].clk_i2s_if:0peri.tr_io_input[10]:0P5.1tcpwm[0].line_compl[4]:0tcpwm[1].line_compl[4]:0csd.csd_tx:31csd.csd_tx_n:31scb[5].uart_tx:0scb[5].i2c_sda:0scb[5].spi_miso:0audioss[0].tx_sck:0peri.tr_io_input[11]:0P5.2tcpwm[0].line[5]:0tcpwm[1].line[5]:0csd.csd_tx:32csd.csd_tx_n:32scb[5].uart_rts:0scb[5].spi_clk:0audioss[0].tx_ws:0P5.3tcpwm[0].line_compl[5]:0tcpwm[1].line_compl[5]:0csd.csd_tx:33csd.csd_tx_n:33scb[5].uart_cts:0scb[5].spi_select0:0audioss[0].tx_sdo:0P5.4tcpwm[0].line[6]:0tcpwm[1].line[6]:0csd.csd_tx:34csd.csd_tx_n:34scb[10].uart_rx:0scb[10].i2c_scl:0scb[5].spi_select1:0audioss[0].rx_sck:0P5.5tcpwm[0].line_compl[6]:0tcpwm[1].line_compl[6]:0csd.csd_tx:35csd.csd_tx_n:35scb[10].uart_tx:0scb[10].i2c_sda:0scb[5].spi_select2:0audioss[0].rx_ws:0P5.6tcpwm[0].line[7]:0tcpwm[1].line[7]:0csd.csd_tx:36csd.csd_tx_n:36scb[10].uart_rts:0scb[5].spi_select3:0audioss[0].rx_sdi:0P5.7tcpwm[0].line_compl[7]:0tcpwm[1].line_compl[7]:0csd.csd_tx:37csd.csd_tx_n:37scb[10].uart_cts:0scb[3].spi_select3:0P6.0tcpwm[0].line[0]:1tcpwm[1].line[8]:0csd.csd_tx:38csd.csd_tx_n:38scb[8].i2c_scl:0scb[3].uart_rx:0scb[3].i2c_scl:0scb[3].spi_mosi:0cpuss.fault_out[0]scb[8].spi_mosi:0P6.1tcpwm[0].line_compl[0]:1tcpwm[1].line_compl[8]:0csd.csd_tx:39csd.csd_tx_n:39scb[8].i2c_sda:0scb[3].uart_tx:0scb[3].i2c_sda:0scb[3].spi_miso:0cpuss.fault_out[1]scb[8].spi_miso:0P6.2tcpwm[0].line[1]:1tcpwm[1].line[9]:0csd.csd_tx:40csd.csd_tx_n:40scb[3].uart_rts:0scb[3].spi_clk:0scb[8].spi_clk:0P6.3tcpwm[0].line_compl[1]:1tcpwm[1].line_compl[9]:0csd.csd_tx:41csd.csd_tx_n:41scb[3].uart_cts:0scb[3].spi_select0:0scb[8].spi_select0:0P6.4tcpwm[0].line[2]:1tcpwm[1].line[10]:0csd.csd_tx:42csd.csd_tx_n:42scb[8].i2c_scl:1scb[6].uart_rx:2scb[6].i2c_scl:2scb[6].spi_mosi:2peri.tr_io_input[12]:0peri.tr_io_output[0]:1cpuss.swj_swo_tdoscb[8].spi_mosi:1P6.5tcpwm[0].line_compl[2]:1tcpwm[1].line_compl[10]:0csd.csd_tx:43csd.csd_tx_n:43scb[8].i2c_sda:1scb[6].uart_tx:2scb[6].i2c_sda:2scb[6].spi_miso:2peri.tr_io_input[13]:0peri.tr_io_output[1]:1cpuss.swj_swdoe_tdiscb[8].spi_miso:1P6.6tcpwm[0].line[3]:1tcpwm[1].line[11]:0csd.csd_tx:44csd.csd_tx_n:44scb[6].uart_rts:2scb[6].spi_clk:2cpuss.swj_swdio_tmsscb[8].spi_clk:1P6.7tcpwm[0].line_compl[3]:1tcpwm[1].line_compl[11]:0csd.csd_tx:45csd.csd_tx_n:45scb[6].uart_cts:2scb[6].spi_select0:2cpuss.swj_swclk_tclkscb[8].spi_select0:1P7.0tcpwm[0].line[4]:1tcpwm[1].line[12]:0csd.csd_tx:46csd.csd_tx_n:46scb[4].uart_rx:1scb[4].i2c_scl:1scb[4].spi_mosi:1peri.tr_io_input[14]:0cpuss.trace_clockP7.3tcpwm[0].line_compl[5]:1tcpwm[1].line_compl[13]:0csd.csd_tx:49csd.csd_tx_n:49scb[4].uart_cts:1scb[4].spi_select0:1Document Number: 002-29368 Rev. *C Page 10 of 22 PRELIMINARYCYSBSYS-RP01Port.PinAct #0Act #1Act #2Act #3DS #2DS #3Act #4Act #5Act #6Act #7Act #8Act #9Act #10Act #12Act #13Act #14Act #15DS #5DS #6P8.0tcpwm[0].line[0]:2tcpwm[1].line[16]:0csd.csd_tx:54csd.csd_tx_n:54scb[4].uart_rx:0scb[4].i2c_scl:0scb[4].spi_mosi:0peri.tr_io_input[16]:0P8.1tcpwm[0].line_compl[0]:2tcpwm[1].line_compl[16]:0csd.csd_tx:55csd.csd_tx_n:55scb[4].uart_tx:0scb[4].i2c_sda:0scb[4].spi_miso:0peri.tr_io_input[17]:0P8.2tcpwm[0].line[1]:2tcpwm[1].line[17]:0csd.csd_tx:56csd.csd_tx_n:56lpcomp.dsi_comp0:0scb[4].uart_rts:0scb[4].spi_clk:0P8.3tcpwm[0].line_compl[1]:2tcpwm[1].line_compl[17]:0csd.csd_tx:57csd.csd_tx_n:57lpcomp.dsi_comp1:0scb[4].uart_cts:0scb[4].spi_select0:0P8.4tcpwm[0].line[2]:2tcpwm[1].line[18]:0csd.csd_tx:58csd.csd_tx_n:58scb[11].uart_rx:0scb[11].i2c_scl:0scb[4].spi_select1:0P9.0tcpwm[0].line[4]:2tcpwm[1].line[20]:0csd.csd_tx:62csd.csd_tx_n:62scb[2].uart_rx:0scb[2].i2c_scl:0scb[2].spi_mosi:0audioss[0].clk_i2s_if:1peri.tr_io_input[18]:0cpuss.trace_data[3]:0P9.1tcpwm[0].line_compl[4]:2tcpwm[1].line_compl[20]:0csd.csd_tx:63csd.csd_tx_n:63scb[2].uart_tx:0scb[2].i2c_sda:0scb[2].spi_miso:0audioss[0].tx_sck:1peri.tr_io_input[19]:0cpuss.trace_data[2]:0P9.2tcpwm[0].line[5]:2tcpwm[1].line[21]:0csd.csd_tx:64csd.csd_tx_n:64scb[2].uart_rts:0scb[2].spi_clk:0audioss[0].tx_ws:1cpuss.trace_data[1]:0P9.3tcpwm[0].line_compl[5]:2tcpwm[1].line_compl[21]:0csd.csd_tx:65csd.csd_tx_n:65scb[2].uart_cts:0scb[2].spi_select0:0audioss[0].tx_sdo:1cpuss.trace_data[0]:0P9.4tcpwm[0].line[7]:5tcpwm[1].line[0]:2csd.csd_tx:66csd.csd_tx_n:66scb[2].spi_select1:0audioss[0].rx_sck:1P9.7tcpwm[0].line_compl[0]:6tcpwm[1].line_compl[1]:2csd.csd_tx:69csd.csd_tx_n:69P10.0tcpwm[0].line[6]:2tcpwm[1].line[22]:0csd.csd_tx:70csd.csd_tx_n:70scb[1].uart_rx:1scb[1].i2c_scl:1scb[1].spi_mosi:1peri.tr_io_input[20]:0cpuss.trace_data[3]:1P10.1tcpwm[0].line_compl[6]:2tcpwm[1].line_compl[22]:0csd.csd_tx:71csd.csd_tx_n:71scb[1].uart_tx:1scb[1].i2c_sda:1scb[1].spi_miso:1peri.tr_io_input[21]:0cpuss.trace_data[2]:1P10.2tcpwm[0].line[7]:2tcpwm[1].line[23]:0csd.csd_tx:72csd.csd_tx_n:72scb[1].uart_rts:1scb[1].spi_clk:1cpuss.trace_data[1]:1P10.3tcpwm[0].line_compl[7]:2tcpwm[1].line_compl[23]:0csd.csd_tx:73csd.csd_tx_n:73scb[1].uart_cts:1scb[1].spi_select0:1cpuss.trace_data[0]:1P10.4tcpwm[0].line[0]:3tcpwm[1].line[0]:1csd.csd_tx:74csd.csd_tx_n:74scb[1].spi_select1:1audioss[0].pdm_clk:0P10.5tcpwm[0].line_compl[0]:3tcpwm[1].line_compl[0]:1csd.csd_tx:75csd.csd_tx_n:75scb[1].spi_select2:1audioss[0].pdm_data:0P10.6tcpwm[0].line[1]:6tcpwm[1].line[2]:2csd.csd_tx:76csd.csd_tx_n:76scb[1].spi_select3:1P10.7tcpwm[0].line_compl[1]:6tcpwm[1].line_compl[2]:2csd.csd_tx:77csd.csd_tx_n:77P11.0tcpwm[0].line[1]:3tcpwm[1].line[1]:1csd.csd_tx:78csd.csd_tx_n:78smif.spi_se-lect2scb[5].uart_rx:1scb[5].i2c_scl:1scb[5].spi_mosi:1audioss[1].clk_i2s_if:1peri.tr_io_input[22]:0P11.1tcpwm[0].line_compl[1]:3tcpwm[1].line_compl[1]:1csd.csd_tx:79csd.csd_tx_n:79smif.spi_se-lect1scb[5].uart_tx:1scb[5].i2c_sda:1scb[5].spi_miso:1audioss[1].tx_sck:1peri.tr_io_input[23]:0P11.2tcpwm[0].line[2]:3tcpwm[1].line[2]:1csd.csd_tx:80csd.csd_tx_n:80smif.spi_se-lect0scb[5].uart_rts:1scb[5].spi_clk:1audioss[1].tx_ws:1Document Number: 002-29368 Rev. *C Page 11 of 22 PRELIMINARYCYSBSYS-RP01Port.PinAct #0Act #1Act #2Act #3DS #2DS #3Act #4Act #5Act #6Act #7Act #8Act #9Act #10Act #12Act #13Act #14Act #15DS #5DS #6P11.3tcpwm[0].line_compl[2]:3tcpwm[1].line_compl[2]:1csd.csd_tx:81csd.csd_tx_n:81smif.spi_data3scb[5].uart_cts:1scb[5].spi_select0:1audioss[1].tx_sdo:1peri.tr_io_output[0]:0P11.4tcpwm[0].line[3]:3tcpwm[1].line[3]:1csd.csd_tx:82csd.csd_tx_n:82smif.spi_data2scb[5].spi_select1:1audioss[1].rx_sck:1peri.tr_io_output[1]:0P11.5tcpwm[0].line_compl[3]:3tcpwm[1].line_compl[3]:1csd.csd_tx:83csd.csd_tx_n:83smif.spi_data1scb[5].spi_select2:1audioss[1].rx_ws:1P11.6csd.csd_tx:84csd.csd_tx_n:84smif.spi_data0scb[5].spi_select3:1audioss[1].rx_sdi:1P11.7smif.spi_clkP12.6tcpwm[0].line[7]:3tcpwm[1].line[7]:1csd.csd_tx:91csd.csd_tx_n:91scb[6].spi_select3:0sdhc[1].card_if_pwr_enP12.7tcpwm[0].line_compl[7]:3tcpwm[1].line_compl[7]:1csd.csd_tx:92csd.csd_tx_n:92sdhc[1].io_volt_selP14.1P14.0Document Number: 002-29368 Rev. *C Page 12 of 22 PRELIMINARYCYSBSYS-RP01External Reset (XRES)CYSBSYS-RP01 has an integrated power-on reset circuit, which completely resets all circuits to a known power on state. This actioncan also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active LOW signal, whichis an input to the CYSBSYS-RP01 (ad 49). The CYSBSYS-RP01 module does not require an external pull-up resistor on the XRESinput.Electrical SpecificationsAbsolute Maximum RatingsTable 3. Absolute Maximum RatingsParameterDescriptionMinMaxUnitsVABT_WLDC supply voltage for dual-band 802.11ac-friendly radio with BT 5.0, VBAT and PA driver supply-0.5+5.0VVDDIO_WLDC supply voltage for digital I/O-0.5+2.20VVDDD, VBACKUP, VDDIO0Internal regulator and Port 1 GPIO supply for PSoC 6 MCUBackup power and GPIO Port 0 supply when presentGPIO supply for Ports 11 to 13 when present /Supply for eFuse Programming*-0.5-0.5+2.20+2.62VVVDDA, VDDIO1, VDDUSBAnalog power supply voltage for PSoC 6 MCUGPIO supply for Ports 5 to 8 when presentSupply for Port 14 (USB or GPIO) when present-0.5+4VESD_HBMHuman body model contact discharge per JEDEC EID/JESD22-A1142200-VESD_CDMCharged device model contact discharge per JEDEC EIA/JESD22-C101500-VUsage above the absolute maximum conditions listed in above table may cause permanent damage to the device. Exposure toabsolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 Cin compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditionsbut above normal operating conditions, the device may not operate to specification.Document Number: 002-29368 Rev. *C Page 13 of 22 PRELIMINARYCYSBSYS-RP01Recommended Operating ConditionsDC SpecificationsTable 4. DC SpecificationsParameterDescriptionMinTypMaxUnitsDetails / ConditionsVABT_WLDC supply voltage for dual-band 802.11ac-friendly radio with BT 5.0, VBAT and PA driver supply3.63.64.2VVDDIO_WLDC supply voltage for digital I/O1.621.81.98VVDDD,VBACKUP,VDDIO0Internal regulator and Port 1 GPIO supply for PSoC 6 MCUBackup power and GPIO Port 0 supply whenpresentGPIO supply for Ports 11 to 13 when present /supply for eFuse Programming* 1.622.381.82.51.982.62VVVDDD and VDDIO0 must be to VDDIO_WL.Min. VBACKUP is 1.4 V inBackup Mode.VDDA,VDDIO1,Analog power supply voltage for PSoC 6 MCU GPIO supply for ports 5 to 8 when present1.83.33.3VVDDIO_1 must be to VDDA.VDDUSBSupply for Port 14 (USB or GPIO) when present1.83.33.3VMin supply is 2.85 V for USBGPIO DC SpecificationsTable 5. GPIO DC SpecificationsParameterDescriptionMinMaxUnitsDetails / ConditionsVIHInput voltage HIGH threshold0.7 * VDD-VCMOS InputVILInput voltage LOW threshold0.3 * VDDVCMOS InputVOHOutput voltage HIGH levelVDD 0.5VIOH = 8 mAVOLOutput voltage LOW level0.4VIOL = 8 mAITOT_GPIOMaximum total source or sink chip current200mAExternal ECO SpecificationTable 6. External PSoC 6 MCU ECO SpecificationsParameterDescriptionMinTypMaxUnitsF_MHzCrystal frequency range for PSoC 6 MCU43333MHzLoad capacitanceCrystal parallel load capacitance--18pFDrive Level--100WAccuracy (ppm)Frequency stability-20+20ppmESREquivalent series resistance50200Document Number: 002-29368 Rev. *C Page 14 of 22 PRELIMINARYCYSBSYS-RP01Environmental ConditionsThis section describes the operating and storage conditions for CYSBSYS-RP01.Table 13. Environmental Conditions for CYSBSYS-RP01Description Minimum SpecificationMaximum SpecificationOperating temperature-20 C 70 C Operating humidity (relative, non-condensation)5 % 85 % Thermal ramp rate1 C/s 3 C/s Storage temperature-40 C 85 C ESD4kV 8kV ESD and EMI ProtectionExposed components require special attention to ESD and EMI.Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Regulatory InformationFCCFCC NOTICE:The device CYSBSYS-RP01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.CAUTION:The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instruction may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:Reorient or relocate the receiving antenna.Increase the separation between the equipment and receiver.Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.Consult the dealer or an experienced radio/TV technician for helpLABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP-CYSBSYS-RP01. In any case the end product must be labeled exterior with Contains FCC ID: WAP-CYSBSYS-RP01. ANTENNA WARNING: This device is tested with a standard SMA connector and with the on-board chip antenna. When integrated in the OEMs product, no rework or replacement is permitted to the on-board chip antenna with higher gain, nor mounting any other external antenna. Document Number: 002-29368 Rev. *C Page 15 of 22 PRELIMINARYCYSBSYS-RP01RF EXPOSURE: To comply with FCC RF Exposure requirements, the OEM must use the module with on-board chip antenna as-is. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved on-board chip antenna, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYSBSYS-RP01 module is far below the FCC radio frequency exposure limits. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Nevertheless, the module is to be used in such a manner that the potential for human contact during normal operation is minimized. This can be accomplished by installing the module as per manufacturer instructions. The module has been evaluated for and shown compliant with the FCC RF Exposure limits under mobile exposure conditions (antennas are greater than 20cm from a persons body). This device has also been evaluated for and shown compliant with the FCC RF exposure limits under portable exposure conditions (antennas are within 20 cm of a person's body) when installed in certain specific configurations. ISED Innovation, Science and Economic Development (ISED) Canada Certification CYSBSYS-RP01 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-CYSBSYSRP01. Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the on board chip antenna, having a maximum gain of 1 dBi. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antennaor transmitter. ISED NOTICE: The device CYSBSYS-RP01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation of the device. Operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems. L'appareil CYSBSYS-RP01, y compris l'antenne intgre, est conforme aux Rgles RSS-GEN de Canada. L'appareil rpond aux exigences d'approbation de l'metteur modulaire tel que dcrit dans RSS-GEN. L'opration est soumise aux deux conditionssuivantes: (1) Cet appareil ne doit pas causer d'interfrences nuisibles, et (2) Cet appareil doit accepter toute interfrence reue, ycompris les interfrences pouvant entraner un fonctionnement indsirable. La bande 51505250 MHz est reservee uniquement pour une utilisation a linterieur afin de reduire les risques de brouillage prejudiciable aux systemes de satellites mobiles utilisant les memes canaux. ISED INTERFERENCE STATEMENT FOR CANADA This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil est conforme la norme sur l'innovation, la science et le dveloppement conomique (ISED) norme RSS exempte de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. ISED RADIATION EXPOSURE STATEMENT FOR CANADA This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum of 7.9 '' (20 cm) distance between the radiation source and your body. Cet quipement est conforme aux limites d'exposition aux radiations ISED prvues pour un environnement incontrl. Cet quipement doit tre install et utilis avec un minimum de 7,9 po (20 cm) de distance entre la source de rayonnement et votre corps. Document Number: 002-29368 Rev. *C Page 16 of 22 PRELIMINARYCYSBSYS-RP01LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-CYSBSYSRP01. In any case, the end product must be labeled in its exterior with Contains IC: 7922A-CYSBSYSRP01. Le fabricant d'quipement d'origine (OEM) doit s'assurer que les exigences d'tiquetage ISED sont respectes. Cela comprend unetiquette clairement visible l'extrieur de l'enceinte OEM spcifiant l'identifiant Cypress Semiconductor IC appropri pour ce produitainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-CYSBSYSRP01. En tout cas, le produit final doit tre tiquet dans son extrieuravec Contient IC: 7922A-CYSBSYSRP01. European Declaration of Conformity Hereby, Cypress Semiconductor declares that the IoT module CYSBSYS-RP01 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows: All versions of the CYSBSYS-RP01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-29368 Rev. *C Page 17 of 22 Packaging Table 14. Solder Reflow Peak Temperature Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles CYSBSYS-RP01 73-pin castellated solder pads 260 C 30 seconds 2 n e r s i o a r y V P r e li m i n PRELIMINARYCYSBSYS-RP01Table 15. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2Part Number PackageMSLCYSBSYS-RP0173-pin castellated solder pads3CYSBSYS-RP01 is offered in tape and reel packaging. Figure 8 details the tape dimensions used for CYSBSYS-RP01.Figure 8. Tape DimensionsDocument Number: 002-29368 Rev. *C Page 18 of 22 PRELIMINARYCYSBSYS-RP01Figure 9 details the orientation of CYSBSYS-RP01 in the tape as well as the direction for unreeling.Figure 9. Tape DimensionsFigure 10 details reel dimensions used for CYSBSYS-RP01.Figure 10. Tape DimensionsDocument Number: 002-29368 Rev. *C Page 19 of 22 Preliminary Version Preliminary Version 1. Center-of-Mass for CYSB D D B B T T TBD PRELIMINARYCYSBSYS-RP01CYSBSYS-RP01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. Figure 11 shows thecenter-of-mass for CYSBSYS-RP01.Figure 1 SYS-RP01Preliminary VersionTBDOrdering InformationTable 16. Ordering InformationPart Number PackageCYSBSYS-RP01 73-pin castellated solder pads Chip AntennaTable 17. Tape and Reel Package Quantity and Minimum Order AmountFeatures AntennaDescriptionMinimum ReelQuantityMaximum ReelQuantityCommentsReel Quantity 400 400 Ships in 400-unit reel quantities Minimum Order Quantity (MOQ) 400 -Order Increment (OI) 400 -Part Numbering ConventionThe part numbers are of the form CYSBSYS-RP01 where the fields are defined as follows.CYSBSYS-RP01Radio type : 01 - Dual-band 2.4 GHz/5 GHz radio, 02 - Single-band 2.4 GHz radio Marketing code : RP - Rapid IoT ConnectMarketing code : SBSYS - Subsystem Product FamilyCompany ID : CY- CypressFor additional information and a complete list of Cypress Semiconductor Rapid IoT Connect products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website www.cypress.com.Document Number: 002-29368 Rev. *C Page 20 of 22 PRELIMINARYCYSBSYS-RP01Acronyms Document ConventionsTable 18. Acronyms Used in this Document Table 19. Unit of MeasureAcronym Description ADCanalog-to-digital converterCM4Cortex-M4, an Arm CPUCMOScomplementary metal-oxide-semiconductor, a process technology for IC fabricationCSDCapSense Sigma-DeltaCSXCypress mutual capacitance sensing methodECOexternal crystal oscillatorEEPROMelectrically erasable programmable read-only memoryEMIelectromagnetic interferenceESDelectrostatic dischargeGPIOgeneral-purpose input/output, applies to a PSoC pinGNDGroundIoTInternet of ThingsMCUmicrocontroller unitRAMrandom-access memoryROMread-only memoryRTCreal-time clockWCOwatch crystal oscillatorDocument Number: 002-29368 Rev. *C Page 21 of 22 SymbolUnit of MeasureCdegrees CelsiusdBdecibeldBmdecibel-milliwattsHzhertzKB1024 byteskbpskilobits per secondkHzkilohertzMbpsmegabits per secondMHzmegahertzMmega-ohmFmicrofaradWmicrowattmAmilliamperenAnanoampereohmpFpicofaradppmparts per millionssecondVvolt PRELIMINARYCYSBSYS-RP01Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the officeclosest to you, visit us at Cypress Locations.ProductsArm Cortex Microcontrollers cypress.com/armAutomotive cypress.com/automotiveClocks & Buffers cypress.com/clocksInterface cypress.com/interfaceInternet of Things cypress.com/iotMemory cypress.com/memoryMicrocontrollers cypress.com/mcuPSoC cypress.com/psocPower Management ICs cypress.com/pmicTouch Sensing cypress.com/touchUSB Controllers cypress.com/usbWireless Connectivity cypress.com/wirelessPSoC SolutionsPSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCUCypress Developer CommunityCommunity | Projects | Video | Blogs | Training | ComponentsTechnical Supportcypress.com/supportNotice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-C Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third-party software tools, including sample code, to modify the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS Cypress Semiconductor Corporation, 2019-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (Cypress). This document, including any software or firmware included or referenced in this document (Software), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you apersonal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproducethe Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computingdevice can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, suchas unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, Security Breach). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extentpermitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of anyproduct or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. High-Risk Devicemeans any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and othermedical devices. Critical Component means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization touse the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.Document Number: 002-29368 Rev. *C Revised June 19, 2020 Page 22 of 22

Cypress Semiconductor 198 Champion Court, San Jose, CA, United States, 95134 Tel: 408-468-3617 ; Fax: 408-544-1694 Date: March 10, 2021 Federal Communications Commission Office of Engineering and Technology Laboratory Division 7435 Oakland Mills Rd Columbia MD 21046-1609 Subject: Request for Confidentiality FCC ID: WAP-CYSBSYS-RP01 To Whom It May Concern, Pursuant to the provisions of Sections 0.457 and 0.459 of Commissions rules (47CFR0.457, 0.459), we are requesting the Commission to withhold the following attachment(s) as confidential document from public disclosure indefinitely. Operational Description Tune-up Procedure Schematic Diagram Block Diagram Part List Above mentioned document contains detailed system and equipment description are considered as proprietary information in operation of the equipment. The public disclosure of above documents might be harmful to our company and would give competitor an unfair advantage in the market. In additional to above mentioned documents, pursuant to Public Notice DA 04-1705 of the Commission s policy, in order to comply with the marketing regulations in 47 CFT 2.803 and the importation rules in 47 CFR 2.1204, while ensuring that business sensitive information remains confidential until the actual marketing of newly authorized devices. We are requesting the commission to grant short-term confidentiality request on the following attachment(s) for 180 days after the grant as outlined in Public Notice DA 04-1705. External Photos Internal Photos Test Setup Photos User Manual It is our understanding that all measurement test reports, FCC ID label format and correspondent during certification review process cannot be granted as confidential documents and those information will be available for public review once the grant of equipment authorization is issued. Best Regards, ______________________ Kalyan Dharanipragada Kal.Dharanipragada@infineon.com

Cypress Semiconductor 198 Champion Court, San Jose, CA, United States, 95134 Tel: 408-468-3617 ; Fax: 408-544-1694 Request for Modular Approval for FCC ID: WAP-CYSBSYS-RP01 EUT The module is equipped with its own shielding case. Date: March 10, 2021 Item Requirements 1. The radio elements must have the radio frequency circuitry shielded. Physical components and tuning capacitor(s) may be located external to the shield, but must be on the module assembly modulation/data inputs to ensure that the device will comply with Part 15 requirements with any type of input signal 2. The module must have buffered The module has buffer modulation / data inputs. 3. The module must contain power supply The module has its own power supply regulation. regulation on the module 4. The module must contain a permanently attached antenna, or contain a unique antenna connector, and be marketed and operated only with specific antenna(s), per 15.203, 15.204(b), 15.204(c), 15.212(a), 2.929(b) 5. The module must demonstrate compliance in a stand-alone configuration The module has a permanently attached antenna, with the antenna gain:

2.4G = 0.8dBi 5G = 1dBi The module was tested on evaluation board, and its not inside of another device during testing 6. The module must be labeled with its The module transmitter will be labeled with its own permanently affixed FCC ID label, or use an electronic display FCC ID, and for OEM integration the integration manual contains labeling instructions for the host device per Part 15.212 (vi) 7. The module must comply with all specific rules applicable to the transmitter, including The module approved transmitter complies with all applicable rules and the integration manual all the conditions provided in the integration instructions by the grantee contains any specific requirements addressed to the integrator and/or to the end-user of the final 8. The module must comply with RF exposure requirements end-product. The module complies with the FCC RF exposure requirements for fixed and mobile applications. RF exposure is addressed in the RF exposure exhibit. ______________________ Kalyan Dharanipragada Kal.Dharanipragada@infineon.com

Cypress Semiconductor 198 Champion Court, San Jose, CA, United States, 95134 Tel: 408-468-3617 ; Fax: 408-544-1694 Date: March 10, 2021 To whom it may concern, Please be notified that I, Kalyan Dharanipragada, have designated Jones Tsai in Sporton International Inc. as the person being responsible for this project and to sign the form 731 and other documentation. Any and all acts carried out by Jones Tsai in Sporton International Inc. on the matters of relating to all processes required in the FCC approval and any communication needed with the national authority, shall have the same legal authority as acts on our own behalf. We further certify that neither the applicant nor any party to this application, as defined in 47 CFR Ch. 1.2002 (b), is subject to a denial to Federal benefits, that include FCC benefits, pursuant to section 5301 of the Anti-Drug Abuse Act of 1998, 21 U.S.C. 862. This authorization is limited to the product of as following:

FCC ID: WAP-CYSBSYS-RP01 If you have any acknowledgement and response, please send it to Sporton International Inc. directly. Sincerely yours, Kalyan Dharanipragada Kal.Dharanipragada@infineon.com