FCC ID: H79DFZM-E7210 ZigBee Module

DFZM-E72xx Data sheet DFZM-E72xx An IEEE 802.15.4 SystemOn-Chip ZigBee module Data Sheet Sheet 1 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx Contents 1. Features ............................................................................................................................................... 4 2. ZigBee Model No. Definition ............................................................................................................. 6 3. Architecture ......................................................................................................................................... 7 3-1.Block Diagram .............................................................................................................................. 7 3-2.Block Diagram Description .......................................................................................................... 8 3-2-1.Overview ........................................................................................................................... 8 3-2-2.CPU and Memory .............................................................................................................. 8 3-2-3.Clocks and Power Management ...................................................................................... 10 3-2-4.Peripherals ....................................................................................................................... 12 4. Pin-out and Signal Description ......................................................................................................... 15 4-1.Device Pin-out Diagram (Module top view) .............................................................................. 15 4-2.Module Pins Description ............................................................................................................ 16 5. Electrical Characteristics .................................................................................................................. 23 5-1.Absolute Maximum Rating......................................................................................................... 23 5-2.Recommended Operating Conditions ......................................................................................... 23 5-3.Power Consumption.................................................................................................................... 23 5-4.Digital I/O and nRESET Pin Specifications ............................................................................... 25 5-5.Wake-up and Timing ................................................................................................................... 26 5-6.Radio Parameters ........................................................................................................................ 27 5-7.ADC Parameters ......................................................................................................................... 28 6. Package and Layout Guidelines ........................................................................................................ 29 6-1.Recommended PCB Footprint and Dimensions ......................................................................... 29 6-2.Layout Guidelines ....................................................................................................................... 31 6-2-1.Surface Mount Assembly ................................................................................................ 32 6-3.Recommended Stencil Aperture ................................................................................................. 34 7. Ordering Information ........................................................................................................................ 35 8. Package ............................................................................................................................................. 35 8-1.Information of carrier tape direction&packaging dimension ..................................................... 35 8-2.Reel dimension ........................................................................................................................... 37 8-3.Total Package .............................................................................................................................. 38 Data Sheet Sheet 2 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change Revision History DFZM-E72xx Version Date 0.1 2013/9/5 0.2 2013/9/16 Reason of change Initial release 1. Change the DFZM-E722x module size, and modify all mechine drawing 2. Add package information 1. Add RF exposure warning statement including FCC 0.3 2014/2/15 statement. 2. Modify 5.6 Radio Parameter for DFZM-E721x . Maker Fred Fred Monch Data Sheet Sheet 3 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx DFZM-E72xx IEEE802.15.4 System-On-Chip ZigBee Module T HIS DOCUMENT describes the DFZM-E72xx ZigBee module hardware specification. The EM357 based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity for embedded devices for a variety of applications, such as wireless sensors and energy monitoring. It combines 32-bit ARM Cortex-M3 processor, in-system programable flash memory, 12-KB RAM, 192KB flash memory and off module certified antenna options, and various RF front end options for end customer range needs in order to provide a ZigBee and regulatory certified. The module has various operating modes, making it highly suit for system where ultralow power consumption is required. Short transition times between operating modes further ensure low energy consumption. 1. Features Family of modules with different antenna and output power options:

DFZM-E72xx 27 mm by 16 mm by 3.3 mm (Length * Width * Height) 28-pin Dual Flat pack PCB Surface Mount Package. DFZM-E7220, DFZM-E7221, DFZM-E7210, and DFZM-E7211 are all pin to pin compatible (see section 7 Ordering Information), and the user has to account only for power consumption for various end applications. Simple API for embedded markets covering large areas of applications. Compliant with IEEE 802.15.4 and regulatory domains:

RoHS compliant. Microcontroller:

Industry-leading ARM Cortex-M3 processor. 192KB Flash with optional read protection. 12KB RAM memory. Flexible nested vectored interrupt controller. Data Sheet Sheet 4 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change Interfaces:

DFZM-E72xx Internal antenna or external antenna options. Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers. Up to 22 configurable general purpose I/Os. Single voltage operation: 2.1~3.6V Embedded RTC (Real Time Clock) can run directly from battery. Data Sheet Sheet 5 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx

- DT 0 R D F Z M - E 7 2 2 0 2. ZigBee Model No. Definition Free-lead Serial no. Customer code Antenna Version Power Version Frequency Chip Type Chip Vendor Product-type Property Substrate Company E=Pb free R=RoHS N=NG L=Process with Lead 0~9 then A~Z DT= Delta Define 0= External Antenna 1= Onboard Chip Antenna 1= High Power 2= Low Power 2= 2.4GHz 7=EM357 E=Ember(Silicon Labs) M= Module Z= ZigBee F= FR4 D= DELTA Data Sheet Sheet 6 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 3. Architecture 3-1.Block Diagram ANT 24M Xtal Balun Figure 3-1: DFZM-E722x Block Diagram ANT 24M Xtal SE2432L Figure 3-2: DFZM-E721x Block Diagram Digital I/O VCC Digital I/O VCC Sep 16, 2013 Data Sheet Sheet 7 of 40 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 3-2.Block Diagram Description 3-2-1.Overview DFZM-E72xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:

The module includes Silicon Labs EM357 SoC, which contains CPU- and memory-related, peripherals-related, clocks and power management-related in a single package. The module features an IEEE802.15.4-compliant radio transceiver with onboard 24 MHz crystal circuitries, RF, and certified antenna or external antenna options. o The low power module option has a capability of +8dBm output power at the antenna (see Figure 3-1). o The high power module option has a capability of +18.5dBm output power at the antenna (see Figure 3-2). Variety of interfaces are available such as UART, SPI, TIMER, ADC, Operational amperifier and GPIO. DFZM-E72xx contains single power supply (VCC). 3-2-2.CPU and Memory The EM357 integrates the ARM Cortex-M3 microprocessor. The ARM Cortex-M3 is an advanced 32-bit modified Harvard architecture processor that has separate internal program and data buses, but presents a unified program and data address space to software. The word width is 32 bits for both the program and data sides. The ARM Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-packed data structures. The ARM Cortex-M3 clock speed is configurable to 6 , 12 , or 24 MHz. For normal operation 24 MHz is preferred over 12 MHz due to improved performance for all applications and improved duty cycling for applications using sleep modes. The 6 MHz operation can only be used when radio operations are not required since the radio requires an accurate 12 MHz clock. The ARM Cortex-M3 in the EM357 has also been enhanced to support two separate memory protection levels. Basic protection is available without using the MPU, but normal operation uses the MPU. The MPU allows for protecting unimplemented areas of the memory map to prevent common software bugs from interfering with software operation. The architecture could also allow for separation of the networking stack from the application code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the Data Sheet Sheet 8 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx developer to assist in tracking down and fixing issues. Figure 3.3 shows the EM357 ARM Cortex-M3 memory map. Figure 3-3: DFZM-E72xx memory map Data Sheet Sheet 9 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 3-2-3.Clocks and Power Management The DFZM-E72xx integrates four oscillators:

12 MHz RC oscillator 24 MHz crystal oscillator 10 kHz RC oscillator Figure 3-4 shows a block diagram of the clocks in the DFZM-E72xx. This simplified view shows all the clock sources and the general areas of the chip to which they are routed Figure 3-4: DFZM-E72xx block diagram of the clocks Data Sheet Sheet 10 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx The DFZM-E72xxs power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E72xx has four main sleep modes:

Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All power domains remain fully powered and nothing is reset. Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and the sleep timer is active. Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this mode the sleep timer cannot wake up the DFZM-E72xx. Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering down the core domain. Instead, the core domain remains powered and all peripherals except the system debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow DFZM-E72xx software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints. The power management state diagram in Figure 3-5 shows the basic operation of the power management controller. Figure 3-5: DFZM-E72xx power management state diagram Data Sheet Sheet 11 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 3-2-4.Peripherals The DFZM-E72xx has 22 multipurpose GPIO pins, which may be individually configured as:

General purpose output General purpose open-drain output Alternate output controlled by a peripheral device Alternate open-drain output controlled by a peripheral device Analog General purpose input General purpose input with pull-up or pull-down resistor The GPIO signal assignments are shown in Table 3-1. GPIO Analog PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 Alternate Output TIM2C11, SC2MOSI TIM2C31, SC2MISO, SC2SDA TIM2C41, SC2SCLK, SC2SCL TIM2C21, TRACECLK ADC4 PTI_EN, TRACEDATA2 ADC5 PTI_DATA, TRACEDATA3 TIM1C3 TIM1C4, REG_EN3 VREF TRACECLK Input TIM2C11, SC2MOSI TIM2C31, SC2MISO, SC2SDA TIM2C41, SC2SCLK TIM2C21, SC2nSSEL nBOOTMODE2 TIM1C3 TIM1C4 TIM1CLK, TIM2MSK, IRQA TIM2C14, SC1TXD, SC1MOSI, SC1MISO, SC1SDA TIM2C14, SC1SDA PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 TIM2C24, SC1SCLK TIM2C34, SC1SCLK TIM2C44, SC1nRTS ADC0 ADC1 TIM1C1 ADC2 TIM1C2 TRACEDATA1 TIM2C24, SC1MISO, SC1MOSI, SC1SCL, SC1RXD TIM2C34, SC1SCLK, SC1nCTS TIM2C44, SC1nSSEL TIM2CLK, TIM1MSK TIM1C1, IRQB TIM1C2 JRST5 Output Current Drive Standard Standard Standard Standard Standard Standard High High Standard Standard Standard Standard Standard Standard High High High Data Sheet Sheet 12 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx ADC3 TRACEDATA0, SWO JTDO6, SWO SWDIO7 TX_ACTIVE PC1 PC2 PC3 PC4 PC5 Notes:

JTDI5 SWDIO7, JTMS7 Standard Standard Standard Standard Standard 1.Default signal assignment (not remapped). 2. Overrides during reset as an input with pull up. 3. Overrides after reset as an open-drain output. 4. Alternate signal assignment (remapped). 5. Overrides in JTAG mode as a input with pull up. 6. Overrides in JTAG mode as a push-pull output. 7. Overrides in Serial Wire mode as either a push-pull output, or a floating input, controlled by the debugger. Table 3-1: DFZM-E72xx GPIO signal assignments The DFZM-E72xx has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications. SPI (Serial Peripheral Interface), master or slave TWI (Two Wire serial Interface), master only UART (Universal Asynchronous Receiver/Transmitter), SC1 only Receive and transmit FIFOs and DMA channels, SPI and UART modes Before using a serial controller, configure and initialize it as follows:

1. Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.). 2. Configure the GPIO pins used by the serial controller as shown in Tables 3-2 and 3-3. 3. If using DMA, set up the DMA and buffers. 4. If using interrupts, select edge- or level-triggered interrupts with the SCx_INTMODE register, enable the desired second-level interrupt sources in the INT_SCxCFG register, and finally enable the top-level SCx interrupt in the NVIC. 5. Write the serial interface operating mode (SPI, TWI, or UART) to the SCx_MODE register Data Sheet Sheet 13 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx PB1 PB2 PB3 PB4 SPI-Master SPI-Slave TWI-Master UART SC1MOSI Alternate Output (push-pull) SC1MISO Alternate Output (push-pull) SC1SDA Alternate Output (open-drain) TXD Alternate Output

(push-pull) SC1MISO Input SC1SCLK Alternate Output (push-pull)

(not used) SC1MOSI Input SC1SCLK Input SC1nSSEL Input SC1SCL Alternate Output (open-drain)

(not used)

(not used) RXD Input nCTS Input1 nRTS Alternate Output

(push-pull)*

*Note: used if RTS/CTS hardware flow control is enabled. Table 3-2: DFZM-E72xx SC1 GPIO Usage and Configuration PA0 PA1 PA2 PA3 SPI-Master SC2MOSI Alternate Output (push-pull) SPI-Slave SC2MOSI Input TWI-Master

(not used) SC2MISO Input SC2MISO Alternate Output (push-pull) SC2SDA Alternate Output (open-drain) SC2SCLK Alternate Output (push-pull)

(not used) SC2SCLK Input SC2nSSEL Input SC2SCL Alternate Output (open-drain)

(not used) Table 3-3: DFZM-E72xx SC2 GPIO Usage and Configuration Data Sheet Sheet 14 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 4. Pin-out and Signal Description 4-1.Device Pin-out Diagram (Module top view) Figure 4-1: DFZM-E72xx Device Pin-out Diagram (Module top view) Data Sheet Sheet 15 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 4-2.Module Pins Description Pins Pin Type Name DFZM-E72xx Description 1 2 3 4 5 GND PC5 nRESET PA7 TIM1C4 TIM1C4 REG_EN PB3 TIM2C3 TIM2C3 SC1nCTS SC1SCLK SC1SCLK PB4 TIM2C4 6 TIM2C4 SC1nRTS Data Sheet Ground Ground Digital I/O(Not available for DFZM-E721X-DT0R) Active low chip reset(internal pull-up) I/O I I/O Digital I/O, High current, Disable REG_EN with GPIO_DBGCFG[4]

Timer 1 Channel 4 output, Enable timer output with TIM1_CCER Select alternate output function with GPIO_PACFGH[15:12]

Disable REG_EN with GPIO_DBGCFG[4]

Timer 1 Channel 4 input, Cannot be remapped External regulator open drain output, Enabled after reset Digital I/O Timer 2 channel 3 output, Enable remap with TIM2_OR[6]

Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGL[15:12]

Timer 2 channel 3 input, Enable remap with TIM2_OR[6]

UART CTS handshake of Serial Controller 1 Enable with SC1_UARTCFG[5], Select UART with SC1_MODE SPI master clock of Serial Controller 1 Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[6]

Enable master with SC1_SPICFG[4], Select SPI with SC1_MODE Select alternate output function with GPIO_PBCFGL[15:12]

SPI slave clock of Serial Controller 1 Enable slave with SC1_SPICFG[4], Select SPI with SC1_MODE Digital I/O Timer 2 channel 4 output, Enable remap with TIM2_OR[7]

Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGH[3:0]

Timer 2 channel 4 input, Enable remap with TIM2_OR[7]

UART RTS handshake of Serial Controller 1 O I O I/O O I I O I I/O O I O Sheet 16 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx Either disable timer output in TIM2_CCER,or disable remap with TIM2_OR[7]

Enable with SC1_UARTCFG[5], Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGH[3:0]

SPI slave select of Serial Controller 1 Enable slave with SC1_SPICFG[4], Select SPI with SC1_MODE Digital I/O Timer 2 channel 1 output, Disable remap with TIM2_OR[4]

Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[3:0]

Timer 2 channel 1 input, Disable remap with TIM2_OR[4]

SPI master data out of Serial Controller 2 Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[4]

Enable master with SC2_SPICFG[4], Select SPI with SC2_MODE Select alternate output function with GPIO_PACFGL[3:0]

SPI slave data in of Serial Controller 2 Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE Digital I/O Timer 2 channel 3 output, Disable remap with TIM2_OR[6]

Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[7:4]

Timer 2 channel 3 input, Disable remap with TIM2_OR[6]

TWI data of Serial Controller 2, Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[6], Select TWI with SC2_MODE Select alternate open-drain output function with GPIO_PACFGL[7:4]

SPI slave data out of Serial Controller 2, Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[6], Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE, Select alternate output function with GPIO_PACFGL[7:4]

SPI master data in of Serial Controller 2 Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE Digital I/O Timer 2 channel 4 output I I/O O I O I I/O O I I/O O I I/O O 7 SC1nSSEL PA0 TIM2C1 TIM2C1 SC2MOSI SC2MOSI PA1 TIM2C3 TIM2C3 8 SC2SDA SC2MISO SC2MISO 9 PA2 TIM2C4 Data Sheet Sheet 17 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change TIM2C4 SC2SCL I I/O SC2SCLK O SC2SCLK PA3 SC2nSSEL TRACECLK 10 TIM2C2 TIM2C2 PA4 ADC4 I I/O I O O I I/O DFZM-E72xx Disable remap with TIM2_OR[7], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[11:8]

Timer 2 channel 4 input, Disable remap with TIM2_OR[7]

TWI clock of Serial Controller 2, Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[7], Select TWI with SC2_MODE Select alternate open-drain output function with GPIO_PACFGL[11:8]

SPI master clock of Serial Controller 2 Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[7]

Enable master with SC2_SPICFG[4], Select SPI with SC2_MODE Select alternate output function with GPIO_PACFGL[11:8]

SPI slave clock of Serial Controller 2 Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE Digital I/O SPI slave select of Serial Controller 2 Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE Synchronous CPU trace clock, Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[5], Enable trace interface in ARM core Select alternate output function with GPIO_PACFGL[15:12]

Timer 2 channel 2 output Disable remap with TIM2_OR[5], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[15:12]

Timer 2 channel 2 input, Disable remap with TIM2_OR[5]

Digital I/O Analog ADC Input 4, Select analog function with GPIO_PACFGH[3:0]

PTI_EN O 11 TRACEDATA2 O Frame signal of Packet Trace Interface (PTI) Disable trace interface in ARM core, Enable PTI in Ember software Select alternate output function with GPIO_PACFGH[3:0]

Synchronous CPU trace data bit 2 Select 4-wire synchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GPIO_PACFGH[3:0]

Data Sheet Sheet 18 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change PA5 ADC5 PTI_DATA 12 nBOOTMODE TRACEDATA3 O I/O Digital I/O DFZM-E72xx Analog ADC Input 5, Select analog function with GPIO_PACFGH[7:4]

Data signal of Packet Trace Interface (PTI) Disable trace interface in ARM core, Enable PTI in Ember software Select alternate output function with GPIO_PACFGH[7:4]

Activate FIB monitor instead of main program or bootloader when coming out of reset. Signal is active during and immediately after a reset on nRESET. Synchronous CPU trace data bit 3 Select 4-wire synchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GPIO_PACFGH[7:4]

PA6 I/O Digital I/O, High current O I Timer 1 channel 3 output, Enable timer output in TIM1_CCER Select alternate output function with GPIO_PACFGH[11:8]

Timer 1 channel 3 input, Cannot be remapped 13 TIM1C3 TIM1C3 14 GND 15 VCC PB1 SC1MISO 16 SC1MOSI SC1SDA SC1TXD Data Sheet Ground Ground Power I/O Power Supply Input Digital I/O SPI slave data out of Serial Controller 1 Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]

Select SPI with SC1_MODE, Select slave with SC1_SPICR Select alternate output function with GPIO_PBCFGL[7:4]

SPI master data out of Serial Controller 1 Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]

Select SPI with SC1_MODE, Select master with SC1_SPICR Select alternate output function with GPIO_PBCFGL[7:4]

TWI data of Serial Controller 1, Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4], Select TWI with SC1_MODE Select alternate open-drain output function with GPIO_PBCFGL[7:4]

UART transmit data of Serial Controller 1 Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]

Sheet 19 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change O I O O I/O O DFZM-E72xx Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGL[7:4]

Timer 2 channel 1 output Enable remap with TIM2_OR[4], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[7:4]

Timer 2 channel 1 input, Disable remap with TIM2_OR[4]

Digital I/O SPI master data in of Serial Controller 1 Select SPI with SC1_MODE, Select master with SC1_SPICR SPI slave data in of Serial Controller 1 Select SPI with SC1_MODE, Select slave with SC1_SPICR TWI clock of Serial Controller 1, Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[5], Select TWI with SC1_MODE Select alternate open-drain output function with GPIO_PBCFGL[11:8]

UART receive data of Serial Controller 1, Select UART with SC1_MODE Timer 2 channel 2 output Enable remap with TIM2_OR[5], Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGL[11:8]

Timer 2 channel 2 input, Enable remap with TIM2_OR[5]

Serial Wire clock input/output with debugger Selected when in Serial Wire mode (see JTMS description, Pin 21) JTAG clock input from debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 21) Internal pull-down is enabled Digital I/O, Enable with GPIO_DBGCFG[5]

JTAG data out to debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 21) Serial Wire Output asynchronous trace output to debugger Select asynchronous trace interface in ARM core, Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL[11:8]

Enable Serial Wire mode (see JTMS description, Pin 21), Internal pull-up is enabled TIM2C1 TIM2C1 PB2 SC1MISO SC1MOSI O I I/O I I 17 SC1SCL I/O I O I I/O I I/O O O SC1RXD TIM2C2 TIM2C2 SWCLK 18 19 JTCK PC2 JTDO SWO Data Sheet Sheet 20 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 20 21 PC3 JTDI PC4 JTMS SWDIO PB0 VREF VREF 22 IRQA TRACECLK TIM1CLK TIM2MSK PC1 ADC3 DFZM-E72xx I/O I I/O I I/O I/O Digital I/O, Either Enable with GPIO_DBGCFG[5]

or enable Serial Wire mode (see JTMS description) JTAG data in from debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 21) Internal pull-up is enabled Digital I/O, Enable with GPIO_DBGCFG[5]

JTAG mode select from debugger, Selected when in JTAG mode (default mode) JTAG mode is enabled after power-up or by forcing nRESET low Select Serial Wire mode using the ARM-defined protocol through a debugger Internal pull-up is enabled Serial Wire bidirectional data to/from debugger Enable Serial Wire mode (see JTMS description) Select Serial Wire mode using the ARM-defined protocol through a debugger Internal pull-up is enabled Digital I/O(Not available for DFZM-E721X-DT0R) I Analog I Analog O ADC reference output, Enable analog function with GPIO_PBCFGL[3:0]

ADC reference input, Enable analog function with GPIO_PBCFGL[3:0]

Enable reference output with an Ember system function External interrupt source A Synchronous CPU trace clock, Enable trace interface in ARM core Select alternate output function with GPIO_PBCFGL[3:0]

Timer 1 external clock input Timer 2 external clock mask input Digital I/O I I I/O O Analog ADC Input 3, Enable analog function with GPIO_PCCFGL[7:4]

SWO 23 O TRACEDATA0 O Serial Wire Output asynchronous trace output to debugger Select asynchronous trace interface in ARM core, Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL[7:4]

Synchronous CPU trace data bit 0 Select 1-, 2- or 4-wire synchronous trace interface in ARM core Enable trace interface in ARM core Data Sheet Sheet 21 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change PC0 JRST 24 IRQD I/O I I TRACEDATA1 O DFZM-E72xx Select alternate output function with GPIO_PCCFGL[7:4]

Digital I/O, High current, Either enable with GPIO_DBGCFG[5]

or enable Serial Wire mode (see JTMS description, Pin 21) and disable TRACEDATA1 JTAG reset input from debugger Selected when in JTAG mode (default mode, see JTMS description) and TRACEDATA1 is disabled, Internal pull-up is enabled Default external interrupt source D Synchronous CPU trace data bit 1 Select 2- or 4-wire synchronous trace interface in ARM core Enable trace interface in ARM core, Select alternate output function with GPIO_PCCFGL[3:0]

Digital I/O, High current I/O Analog ADC Input 2, Enable analog function with GPIO_PBCFGH[15:12]

I O I I/O Default external interrupt source C Timer 1 channel 2 output, Enable timer output in TIM1_CCER Select alternate output function with GPIO_PBCFGH[15:12]

Timer 1 channel 2 input, Cannot be remapped Digital I/O, High current Analog ADC Input 1, Enable analog function with GPIO_PBCFGH[11:8]

I O I I/O External interrupt source B Timer 1 channel 1 output, Enable timer output in TIM1_CCER Select alternate output function with GPIO_PBCFGH[11:8]

Timer 1 channel 1 input, Cannot be remapped Digital I/O(Not available for DFZM-E721X-DT0R) Analog ADC Input 0, Enable analog function with GPIO_PBCFGH[7:4]

I I Timer 2 external clock input Timer 1 external clock mask input Ground Ground PB7 ADC2 IRQC TIM1C2 TIM1C2 PB6 ADC1 IRQB TIM1C1 TIM1C1 PB5 ADC0 TIM2CLK TIM1MSK 25 26 27 28 GND Data Sheet Sheet 22 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 5. Electrical Characteristics 5-1.Absolute Maximum Rating Conditions beyond those cited in Table 5-1 may cause permanent damage to the DFZM-E72xx, and must be avoided. Parameter Minimum Maximum Supply voltage(VCC) Storage temperature range Voltage on any digitai I/O

-0.3

-40

-0.3 3.6 125 VCC+0.3 Unit V C V Table 5-1: Absolute Maximum Ratings 5-2.Recommended Operating Conditions Parameter Operating supply voltage(VCC) Operating ambient temperature range(TA) Minimum Maximum 2.1

-40 3.6

+110 Unit V C Table 5-2: Recommended Operating Conditions 5-3.Power Consumption Test Conditions: TA=25 C, VCC=3.0V Parameter Test conditions Mim Typ Max Unit Deep Sleep Current Quiescent current, internal RC oscillator disabled Quiescent current, including internal RC Data Sheet 0.4 0.7 uA uA Sep 16, 2013 Sheet 23 of 40 Proprietary Information and Specifications are Subject to Change oscillator DFZM-E72xx Simulated deep sleep (debug mode) current With no debugger activity Reset Current Quiescent current, nRESET asserted Processor and Peripheral Currents ARM Cortex-M3, RAM, and flash memory ARM Cortex-M3 running at 24 MHz from crystal oscillator Radio and all peripherals off ARM Cortex-M3, RAM, and flash memory sleep current ARM Cortex-M3 sleeping, CPU clock set to 12 MHz from the crystal oscillator Radio and all peripherals off Serial controller current For each controller at maximum data rate General purpose timer current For each timer at maximum clock rate General purpose ADC current At maximum sample rate, DMA enabled RX Current Radio receiver, MAC, and baseband Total RX current ( = IRadio receiver, MAC and baseband, CPU + IRAM, and Flash memory ) Boost mode total RX current ( = IRadio receiver, MAC and baseband, CPU+

IRAM, and flash memory ) TX current Radio transmitter, MAC, and baseband Total TX current ( = IRadio transmitter, MAC and baseband, CPU + IRAM, and flash memory) ARM Cortex-M3 sleeping, CPU clock set to 12 MHz ARM Cortex-M3 running at 24 MHz ARM Cortex-M3 running at 24 MHz max. power out (+3 dBm typical) ARM Cortex-M3 sleeping, CPU clock set to 12 MHz maximum power setting (+8 dBm); ARM Cortex-M3 running at 24 MHz maximum power setting (+18.5 dBm); ARM Cortex-M3 running at 24 MHz Table 5-3: Poewr Consumption 300 uA 1.2 2.0 mA 7.5 9.5 mA 3.0 0.2 0.25 1.1 22 mA mA mA mA mA 26.5 31 mA 28.5 26.0 43.5 110 mA mA mA mA Data Sheet Sheet 24 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 5-4.Digital I/O and nRESET Pin Specifications Test Conditions: TA=25 C, VCC=3.0V DFZM-E72xx Parameter Test conditions Low Schmitt switching threshold High Schmitt switching threshold Input current for logic 0 Input current for logic 1 Input pull-up resistor value Input pull-down resistor value Output voltage for logic 0 VSWIL, Schmitt input threshold going from high to low VSWIH, Schmitt input threshold going from low to high IIL IIH RIPU RIPD VOL(IOL = 4 mA for standard pads, 8 mA for high current pads)

>85 C VOL(IOL = 2 mA for standard pads, 4 mA for high current pads) Min 0.42 x VCC 0.62 x VCC 24 24 0 0 VOH(IOH = 4 mA for standard pads, 8 mA for high current pads)

>85 C VOH(IOH = 2 mA for standard pads, 4 mA for high current pads) 0.82 x VCC 0.82 x VCC Output voltage for logic 1 Output source current

(standard current pad) Output sink current

(standard current pad) Output source current high current pad:

PA6, PA7, PB6, PB7, PC0 Output sink current high current pad:

PA6, PA7, PB6, PB7, PC0 IOHS

>85 C IOHS IOLS

>85 C IOLS IOHH

>85 C IOHH IOLH

>85 C IOLH Total output current (for I/O Pads) IOH + IOL Typ 29 29 Max Unit 0.5 x VCC V 0.80 x VCC

-1.0

+1.0 34 34 0.18 x VCC 0.18 x VCC VCC VCC 4 2 4 2 8 4 8 4 2 V uA uA k k V V V V mA mA mA mA mA mA mA mA mA Data Sheet Sheet 25 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change Table 5-4: Digital I/O Specifications DFZM-E72xx Parameter Test conditions Low Schmitt switching threshold High Schmitt switching threshold VSWIL, Schmitt input threshold going from high to low VSWIH, Schmitt input threshold going from low to high Input current for logic 0 Input current for logic 1 IIL IIH Input pull-up resistor value RIPU, Pull-up value while the chip is not reset Input pull-down resistor value RIPURESET, Pull-up value while the chip is reset Table 5-5: nRESET pin Specifications Min 0.42 x VCC 0.62 x VCC 24 12 Typ 29 14.5 Max Unit 0.5 x VCC V 0.80 x VCC

-1.0

+1.0 34 17 V uA uA k k 5-5.Wake-up and Timing Test Conditions: TA=25 C, VCC=3.0V Parameter Test conditions Min Typ Max Unit System wake time from deep sleep From wakeup event to first ARM Cortex-M3 instruction running from 6 MHz internal RC clock Includes supply ramp time and oscillator startup time Shutdown time going into deep sleep From last ARM Cortex-M3 instruction to deep sleep mode 110 5 us us Table 5-6: Wake-up and Timing Data Sheet Sheet 26 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 5-6.Radio Parameters Test Conditions: TA=25 C, VCC=3.0V DFZM-E72xx Parameter RF Frequency range TX/RX specification for DFZM-E722x Output power(boost mode) Output power Error vector magnitude (EVM) Frequency error tolerance Receiver sensitivity(boost mode) Receiver sensitivity Saturation(Maximum input level) TX/RX specification for DFZM-E721x Output power Error vector magnitude (EVM) Frequency error tolerance Receiver sensitivity Saturation(Maximum input level) Min 2400 1

-3

-30 0

-30

-102 6 Typ 8 5 5 0

-102

-100 18.5 5 0

-100 Max 2500 15 30

-87

-85 15 30

-94 Unit MHz dBm dBm

ppm dBm dBm dBm dBm

ppm dBm dBm Table 5-7: Radio Parameters Notes PER = 1%

PER = 1%

PER = 1%, PER = 1%, PER = 1%, Data Sheet Sheet 27 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 5-7.ADC Parameters Test Conditions: TA=25 C, VCC=3.0V Parameter VREF VREF output current VREF load capacitance External VREF voltage range External VREF input impedance Minimum input voltage Maximum input vlotage Single-ended signal range Differential signal range Common mode range Input referred ADC offset Min 1.17 1.1 1 0 0

-VREF 0

-10 Typ 1.2 1.2 Max 1.23 1 10 1.3 VREF VREF

+VREF VREF 10 Unit V mA nF V M V V V V V mV M Input Impedence 1MHz sample clock 6MHz sample clock Not sample 1 0.5 10

*Note: The signal-ended ADC measurements are limited in their range and only guaranteed for accuracy within the limits shown in this table. The ADC's internal design allows for measurements outside of this range (200 mV), but the accuracy of such measurements is not guaranteed. The maximum input voltage is of more interest to the differential sampling where a differential measurement might be small, but a common mode can push the actual input voltage on one of the signals towards the upper voltage limit. Table 5-8: ADC Parameters Data Sheet Sheet 28 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 6. Package and Layout Guidelines 6-1.Recommended PCB Footprint and Dimensions Figure 6-1: DFZM-E72xx Module Recommended PCB Footprint (in mm) Data Sheet Sheet 29 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx Figure 6-2: DFZM-E72xx Module Dimensions (in mm) Data Sheet Sheet 30 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 6-2.Layout Guidelines DFZM-E72xx Keep out area for onboard antenna. All layers on the PCB must be clear.

(i.e. No GND, Power trace/plane, traces.) Note: If guidelines are not followed, DFZM-E72xx range with onboard antenna will be compromised. Figure 6-3: DFZM-E72xx module onboard antenna keep-out layout guidelines (in mm) Notes:

1. All Dimensions are in mm. Tolerances shall be 0.10 mm. 2. Absolutely no metal trace or ground layer underneath this area. 3. It is recommended not to run circuit traces underneath the module. 4. In performing SMT or manual soldering of the module to the base board, please align the two row of pins. In addition to the guidelines in Figure 6-3, note the following suggestions:

DFZM-E72xx External Bypass capacitors for all module supplies should be as close as possible to the module pins. Never place the antenna very close to metallic objects. The external dipole antennas need a reasonable ground plane area for antenna efficiency. DFZM-E7221; DFZM-E7211 onboard antenna specific The onboard antenna keep out area, as shown in Figure 6-3, must be adhered to. In addition it is recommended to have clearance above and below the PCB trace antenna (Figure 6-4) for optimal range performance. Data Sheet Sheet 31 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx Do not use a metallic or metalized plastic for the end product enclosure. Recommendation is to keep plastic enclosure clearance of 1cm from top and bottom of the DFZM-E72xx onboard antenna keep-out area, if possible. 5-mm (0.2 in) clearance shall be the minimum as shown in Figure 6-4. Figure 6-4 Recommended clearance above and below the PCB trace antenna 6-2-1.Surface Mount Assembly The reflow profile is shown in Figure 6-5.

(C ) 245 217 200 150 Room temp. Peak temp 250c max 10 sec max 245c5c for 10 ~30 sec 50 sec max 60-180 sec 60-150 sec Data Sheet Figure 6-5: Reflow temperature profile Sheet 32 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change Time DFZM-E72xx 1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the conditions of the parts and boards, and the specifications of the reflow furnace. 2. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the solder paste. 3. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time. 4. If the temperature is too low, non-melting tends to be caused in the area with large heat capacity after reflow. 5. Be careful about sudden rise in temperature as it may worsen the slump of solder paste. 6. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining strength at times. Note:

Data Sheet Sheet 33 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 6-3.Recommended Stencil Aperture Note: The thickness of the stencil should be 0.15mm over this area. Data Sheet Figure 6-6: DFZM-E72xx recommended stencil aperture Sheet 34 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 7. Ordering Information DFZM-E72xx DEVICE DESCRIPTION ORDERING NUMBER Extended range module using external antenna Extended range module using onboard antenna Low power module using external antenna Low power module using onboard antenna DFZM-E7210-DT0R DFZM-E7211-DT0R DFZM-E7220-DT0R DFZM-E7221-DT0R 8. Package 8-1.Information of carrier tape direction&packaging dimension Data Sheet Sheet 35 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 2 6 3 Z L

2 0 0 6 2 0 0 0 3 6 0 5

. 7 R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F N N N N N W W Y Y 1 RoHS Compliant Pb Accepted CUSTOMER:

MODEL:

Q'TY:

DATE:

FQC:

Unreeling direction R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F N N N N N W W Y Y R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F N N N N N W W Y Y R 0 T D

0 1 0 1 2 S T

M Z F D 9 7 H N N N N N W W Y Y R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F N N N N N W W Y Y R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F N N N N N W W Y Y R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F Trailer 20PCS(min) Reel 4 Carrier tape Components Quantity:750pcs R 0 T D

0 1 2 S T

M Z F D 0 1 2 S T

M Z F D 9 7 H

D I C C F Protective Tape

(width=56mm,Thickness=0.5mm) 8 7 6 5 4 3 2 1 PS 6 Z L

2 0 0 6 2 0 0 0 3 6 0 5

. 7 Adhesive Tape RoHS Compliant Pb Accepted CUSTOMER:

MODEL:

Q'TY:

DATE:

FQC:

5 Leader 20PCS min Cover tape N N N N N W W Y Y N N N N N W W Y Y Sep 16, 2013 Data Sheet Sheet 36 of 40 Proprietary Information and Specifications are Subject to Change DFZM-E72xx W1 W0 13" 100*44mm RUR-26-3-XL W0 45.00.5 W1 50.01.0

* B , C L W 8-2.Reel dimension ZL:200620003605.7 Data Sheet Sheet 37 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx 8-3.Total Package Data Sheet Sheet 38 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change 8-4. RF exposure warning statement FCC Label Statement DFZM-E72xx This device complies with part 15 of the FCC rules. Operation is subject to the following two conditions:

1. This device may not cause harmful interference, and 2. This device must accept any interference received, including interference that may cause undesired operation. Federal Communications Commission (FCC) Statement 15.21 You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the users authority to operate the equipment. 15.105(b) This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

-Reorient or relocate the receiving antenna.

-Increase the separation between the equipment and receiver.

-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

-Consult the dealer or an experienced radio/TV technician for help. FCC RF Radiation Exposure Statement:

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter must not Data Sheet Sheet 39 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change DFZM-E72xx be co-located or operating in conjunction with any other antenna or transmitter. Data Sheet Sheet 40 of 40 Sep 16, 2013 Proprietary Information and Specifications are Subject to Change