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DFZM-TT2xx Data sheet DFZM-TT2xx An IEEE 802.15.4 SystemOn-Chip ZigBee module Data Sheet Sheet 1 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Contents 1. Features ............................................................................................................................................... 4 2. Zigbee Model No. Definition.............................................................................................................. 6 3. Architecture......................................................................................................................................... 7 3-1.Block Diagram.............................................................................................................................. 7 3-2.Block Diagram Description .......................................................................................................... 8 3-2-1.Overview........................................................................................................................... 8 3-2-2.CPU and Memory............................................................................................................ 8 3-2-3.AES Engine with 128, 192 256 Bit Key Support........................................................... 9 3-2-4.Peripherals ..................................................................................................................... 10 3-3.Power Management .................................................................................................................... 14 4. Pin-out and Signal Description ......................................................................................................... 17 4-1.Device Pin-out Diagram (Module top view) .............................................................................. 17 4-2.Module Pins Description ............................................................................................................ 18 5. Electrical Characteristics .................................................................................................................. 20 5-1.Absolute Maximum Rating......................................................................................................... 20 5-2.Recommended Operating Conditions......................................................................................... 20 5-3.Power Consumption.................................................................................................................... 20 5-4.DC Characteristics ...................................................................................................................... 22 5-5.Wake-up and Timing................................................................................................................... 22 5-6.Radio Parameters ........................................................................................................................ 23 5-7.ADC Parameters ......................................................................................................................... 24 5-8.Control Input AC Characteristics................................................................................................ 26 5-9.USB Interface DC Characteristics .............................................................................................. 26 6. Package and Layout Guidelines........................................................................................................ 27 6-1.Recommended PCB Footprint and Dimensions................................................................... 27 6-2.Layout Guidelines....................................................................................................................... 29 6-2-1.Surface Mount Assembly ................................................................................................ 30 6-3.Recommended Stencil Aperture ................................................................................................. 32 7. Reference Design Schematic ............................................................................................................ 33 8. DUT Setup ........................................................................................................................................ 33 Data Sheet Sheet 2 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 9. Federal Communications Commission (FCC) Statement................................................................. 38 Data Sheet Sheet 3 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change T DFZM-TT2xx DFZM-TT2xx IEEE802.15.4 System-On-Chip ZigBee Module HIS DOCUMENT describes the DFZM-TT2xx Zigbee module hardware specification. The CC2538 based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity for embedded devices for a variety of applications, such as wireless sensors and energy monitoring. It combines ARM Cotex-M3 based processors, in-system programable flash memory, 32-KB RAM, 512KB flash memory and off module certified antenna options, and various RF front end options for end customer range needs in order to provide a Zigbee and regulatory certified. The module has various operating modes, making it highly suit for system where ultralow power consumption is required. Short transition times between operating modes further ensure low energy consumption. 1. Features Family of modules with different antenna and output power options:
DFZM-TT2xx 29.3 mm by 19.8 mm by 3.3mm (Length * Width * Height) 42-pin Dual Flat pack PCB Surface Mount Package. DFZM-TT220, DFZM-TT221, DFZM-TT210, and DFZM-TT211 are all pin to pin compatible (see section 7 Ordering Information), and the user has to account only for power consumption. Simple API for embedded markets covering large areas of applications. Compliant with IEEE 802.15.4 and regulatory domains:
RoHS compliant. Microcontroller:
Powerful ARM Cortex M3 with code prefetch. 512KB In-Syctem-Programmable Flash. Up to 32KB RAM (16-kB With Retention in All Power Modes). Supports On-Chip Over-the-Air Upgrade(OTA). Data Sheet Sheet 4 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Hardware debug support. Interfaces:
On board antenna or external antenna options. DMA. 4 General-Purpose Timers (Each 32-Bit or 2 16-Bit). USB 2.0 Full-Speed Device (12 Mbps). 2 SPI. Two universal asynchronous receiver/transmitters (UARTs) with IrDA, 9-bit (one UART with modem flow control). I2C. Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and synchronization. Up to 28 configurable general purpose I/Os. Single 3.3V supply option:
o Wide supply voltage range 2.0 ~ 3.6V. One 12-bit ADC with 8 Channels and Configurable Resolution. Embedded RTC (Real Time Clock) can run directly from battery. Low-power mode operations. Power mode 0,1, 2, 3. Data Sheet Sheet 5 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx
- DT 0 R D F Z M - T T 2 2 0 2. Zigbee Model No. Definition Free-lead Serial no. Customer code Antenna Version Power Version Frequency Chip Type Chip Vendor Product-type Property Substrate Company E=Pb free R=RoHS N=NG L=Process with Lead 0~9 then A~Z DT= Delta Define 0= External Antenna 1= Onboard Antenna 1= High Power 2= Low Power 2= 2.4GHz T=CC2538 T=TI M= Module Z= Zigbee F= FR4 D= DELTA Data Sheet Sheet 6 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 3. Architecture 3-1.Block Diagram ANT Balun ANT CC2591 Data Sheet DFZM-TT2xx Digital I/O VCC Digital I/O VCC 32K Xtal 32M Xtal Figure 3-1: DFZM-TT22x Block Diagram 32K Xtal 32M Xtal Figure 3-2: DFZM-TT21x Block Diagram Sheet 7 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 3-2.Block Diagram Description 3-2-1.Overview DFZM-TT2xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:
The module includes TI CC2538 SoC, which contains CPU- and memory-related, peripherals-related, clocks and power management-related in a single package. The module features an IEEE802.15.4-compliant radio transceiver with onboard 32 KHz & 32 MHz crystal circuitries, RF, and certified on board antenna or external antenna options. o The low power module option has a capability of +7dBm output power at the antenna (see Figure 3-1). o The high power module option has a capability of +18.5dBm output power at the antenna (see Figure 3-2). Variety of interfaces are available such as two USART and SPI, four TIMER, one 12 bit ADC, Operational amperifier and GPIO. DFZM-TT2xx contains single power supply (VCC). 3-2-2.CPU and Memory The CC2538 is designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications. Outstanding processing performance combined with fast interrupt handling. Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications. Single-cycle multiply instruction and hardware divide. Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control. Unaligned data access, enabling data to be efficiently packed into memory. Fast code execution permits slower processor clock or increases sleep mode time. Data Sheet Sheet 8 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Harvard architecture characterized by separate buses for instruction and data. Efficient processor core, system and memories. Hardware division and fast multiplier. Deterministic, high-performance interrupt handling for time-critical applications. Memory protection unit (MPU) provides a privileged mode for protected operating system functionality. Enhanced system debug with extensive breakpoint capabilities and debugging through power modes. cJTAG reduces the number of pins required for debugging. Ultra-low power consumption with integrated sleep modes. 32-MHz operation. The CC2538 provides a 16KB block of single-cycle on-chip SRAM with full retention in all power modes. In addition, some variants offer an additional 16KB of single-cycle on-chip SRAM without retention in the lowest power modes. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from the SRAM using the micro DMA (DMA) controller. The flash block provides in-circuit programmable nonvolatile program memory for the device. The flash memory is organized as a set of 2KB pages that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In addition to holding program code and constants, the nonvolatile memory allows the application to save data that must be preserved such that it is available after restarting the device. Using this feature one can, for example, use saved network-specific data to avoid the need for a full start-up and network find-and-join process. The ROM is preprogrammed with a serial boot loader (SPI or UART). For applications that require in-field programmability, the royalty-free CC2538 boot loader can act as an application loader and support in-field firmware updates. 3-2-3.AES Engine with 128, 192 256 Bit Key Support CCM, GCM, CTR, CBC-MAC, ECB modes of operation SHA-256 hash function. Data Sheet Sheet 9 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Secure key storage memory. High throughput, low latency. Public key accelerator. Elliptic Curve Cryptography (ECC) and RSA-2048. Support for RSA-2048 makes it ideal for ESIs. Keeps the key exchange algorithms out of the CPU cycle budget and reduces energy consumption. 3-2-4.Peripherals The CC2538 device supports both asynchronous and synchronous serial communications with:
USB 2.0 FS device. Two UARTs with 9-bit. I2C module. Two SSI. The following sections provide more detail on each of these communications functions. Universal serial bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface. The CC2538 device supports the USB 2.0 FS configuration in device mode and has the following features:
Complies with USB-IF certification standards. USB 2.0 full speed (12 Mbps) operation with integrated PHY. 4 transfer types: control, interrupt, bulk, and isochronous. Five IN and five OUT configurable endpoints. Support for packet sizes between 8 to 256 bytes and remote wake-up. 1KB of dedicated endpoint memory flexibly assigned to the different endpoints. Efficient transfers using the DMA controller. A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter
(parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The CC2538 microcontroller includes two fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the receive (RX), transmit (TX), modem flow control, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. Data Sheet Sheet 10 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx The two UARTs have the following features:
Programmable baud-rate generator allowing speeds up to 2 Mbps for regular speed (divide by 16) and 4 Mbps for high speed (divide by 8). Separate 16x8 TX and RX FIFOs to reduce CPU interrupt service loading. Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface. FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8. Standard asynchronous communication bits for start, stop, and parity. Line-break generation and detection. Fully programmable serial interface characteristics:
5, 6, 7, or 8 data bits. Even, odd, stick, or no-parity bit generation and detection. 1 or 2 stop-bit generation. Full modem handshake support (on UART1). Modem flow control (on UART1). LIN protocol support. EIA-485 9-bit support. Standard FIFO-level and end-of-transmission (EoT) interrupts. Efficient transfers using the DMA controller:
Separate channels for TX and RX. Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level. Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level. The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacturing. Each device on the I2C bus can be designated as a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The CC2538 microcontroller includes an I2C module with the following features:
Devices on the I2C bus can be designated as either a master or a slave:
Data Sheet Sheet 11 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Supports both transmitting and receiving data as either a master or a slave. Supports simultaneous master and slave operation. Four I2C modes:
Master transmit. Master receive. Slave transmit. Slave receive. Two transmission speeds: Standard (100 Kbps) and fast (400 Kbps). Clock low time-out interrupt. Dual slave address capability. Master and slave interrupt generation:
Master generates interrupts when a TX or RX operation completes (or aborts due to an error). Slave generates interrupts when data is transferred or requested by a master or when a START or STOP condition is detected. Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode. An SSI module is a 4-wire bidirectional communications interface that converts data between parallel and serial. The SSI performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI can be configured as either a master or slave device. As a slave device, the SSI can also be configured to disable its output, which allows coupling of a master device with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the SSI. Bit rates are generated based on the input clock, and the maximum bit rate is determined by the connected peripheral. The CC2538 includes two SSI modules with the following features:
Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces. Master or slave operation. Programmable clock bit rate and prescaler. Separate TX and RX FIFOs, each 16 bits wide and 8 locations deep. Programmable data frame size from 4 to 16 bits. Internal loopback test mode for diagnostic and debug testing. Standard FIFO-based interrupts and EoT interrupt. Data Sheet Sheet 12 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change Efficient transfers using the DMA controller:
DFZM-TT2xx Separate channels for TX and RX. Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains four entries. Transmit single request asserted when there is space in the FIFO; burst request asserted when FIFO contains four entries. GPIO pins offer flexibility for a variety of connections. The CC2538 GPIO module is comprised of four GPIO blocks, each corresponding to an individual GPIO port. The GPIO module supports CC2538 programmable I/O pins. The number of GPIOs available depends on the peripherals being used. Up to 28 GPIOs, depending on configuration. 4 pins with 20-mA drive strength, 28 pins with 4-mA drive strength. Fully flexible digital pin muxing allows use as GPIO or any of several peripheral functions. Programmable control for GPIO interrupts:
Interrupt generation masking per pin. Edge-triggered on rising or falling. Bit masking in read and write operations through address lines. Can be used to initiate a DMA transfer. Pin state can be retained during all sleep modes. Pins configured as digital inputs are Schmitt-triggered. Programmable control for GPIO pad configuration:
Weak pull up or pull down resistors. Digital input enables. An ADC is a peripheral that converts a continuous analog voltage to a discrete digital number. The ADC module features 12-bit conversion resolution and supports eight input channels plus an internal division of the battery voltage and a temperature sensor. Eight shared analog input channels. 12-bit precision ADC with up to 11.5 ENOB. Single-ended and differential-input configurations. On-chip internal temperature sensor. Periodic sampling or conversion over a sequence of channels. Data Sheet Sheet 13 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Converter uses an internal regulated reference, AVDD or an external reference. Efficient transfers using the DMA controller. Dedicated channel for each sample sequencer. An analog comparator is a peripheral that compares two analog voltages, two external pin inputs, and provides a logical output that signals the comparison result. The CC2538 microcontroller provides an independent integrated and low-power analog comparator that can be active in all power modes. The comparator output is mapped into the digital I/O port, and the MCU can treat the comparator output as a regular digital input. The random number generator (RNG) uses a 16-bit LFSR to generate pseudorandom numbers, which can be read by the CPU or used directly by the command strobe processor. The RNG can be seeded with random data from noise in the radio ADC. The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The compact JTAG (cJTAG) interface has the following features:
IEEE 1149.1-1990-compatible TAP controller. IEEE 1149.7 cJTAG interface. ICEPick JTAG router. Four-bit IR chain for storing JTAG instructions. IEEE standard instructions: BYPASS, IDCODE, SAMPLE and PRELOAD, EXTEST and INTEST. ARM additional instructions: APACC, DPACC, and ABORT. 3-3.Power Management Different operating modes, or power modes, are used to allow low-power operation. Ultralow-power operation is obtained by turning off the power supply to modules to avoid static (leakage) power consumption and also by using clock gating and turning off oscillators to reduce dynamic power consumption. Data Sheet Sheet 14 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx The six various operating modes (power modes) are called active mode, Sleep mode, PM0, PM1, PM2, and PM3. Active mode is the normal operating mode, whereas PM3 has the lowest power consumption. The impact of the different power modes on system operation is shown in Table 3-1, together with voltage regulator and oscillator options. Operational Mode Power Consumption Sequencing time Functional limitations Active Sleep PM0 PM1 PM2 PM2 Clock gating with RCGC None None Clock gating with SCGC Enter: immediate CPU in sleep Clock gating with DCGC Enter: immediate CPU in Deep sleep Power down of:
System clock source Power down of:
System Clock source Digital Power supply Power down of:
System Clock source Digital Power supply 32 kHz Clock source Enter: 0.5 us Exit: 4 us CPU in Deep sleep All peripherals inactive Enter: 136 us CPU in Deep sleep (inactive) Exit: 136 us All peripherals inactive Enter: 136 us CPU in Deep sleep (inactive) Exit: 136 us All peripherals inactive Sleep Mode Timer inactive Table 3-1: DFZM-TT2xx Power Management Note: The RCGCXX register controls clocks in Active mode (Run mode). The SCGCXX register controls clocks in Sleep mode. The DCGSXX register controls clocks in PM0 (Deep Sleep mode). When using power management in CC2538 it is important to understand the sequence of events and timing involved in the process. A simple flow diagram for power management is shown in Figure 3-3. As can be seen from the figure PM1, 2 and 3 are always entered from a state where the CPU is running on 16 MHz RCOSC. Data Sheet Sheet 15 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Figure 3-3: DFZM-TT2xx Simple Flow Diagram for Power Management Data Sheet Sheet 16 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 4. Pin-out and Signal Description 4-1.Device Pin-out Diagram (Module top view) Data Sheet Figure 4-1: DFZM-TT2xx Device Pin-out Diagram (Module top view) Sheet 17 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 4-2.Module Pins Description DFZM-TT2xx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pins Name GND VCC Pin Type Ground Power Description Ground Power Supply Input JTAG_TMS Digital I/O JTAG TMS JTAG_TCK Digital I/O PB7 PB6 PB5 PB4 PB3 PB2 PB1 USB_P USB_N GND Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O USB I/O USB I/O Ground JTAG TCK GPIO port B pin 7JTAG TDO GPIO port B pin 6JTAG TDI GPIO port B pin 5 GPIO port B pin 4 GPIO port B pin 3 GPIO port B pin 2 GPIO port B pin 1 USB differential data plus (D+) USB differential data plus (D-) Ground DVDD_USB Power (USB pads) 3.3V USB power supply connection PB0 PC7 PC6 PC5 PC4 PC3 Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O 22 PC2 Digital I/O 23 24 PC1 PC0 Digital I/O Digital I/O GPIO port B pin 0. ROM bootloader UART CTS GPIO port C pin 7 GPIO port C pin 6 GPIO port C pin 5 GPIO port C pin 4 GPIO port C pin 3, 20 mA output capability, no pull-up or pull-down. Not available for DFZM-TT21X-DT0R GPIO port C pin 2, 20 mA output capability, no pull-up or pull-down. Not available for DFZM-TT21X-DT0R GPIO port C pin 1, 20 mA output capability, no pull-up or pull-down GPIO port C pin 0, 20 mA output capability, no pull-up or Data Sheet Sheet 18 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx GND PA0 PA1 PA2 GND PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 Ground Digital I/O Digital I/O Digital I/O Ground Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O pull-down Ground GPIO port A pin 0. ROM bootloader UART RXD GPIO port A pin 1. ROM bootloader UART TXD GPIO port A pin 2. ROM bootloader SSI CLK Ground GPIO port A pin 3. ROM bootloader SSI SEL GPIO port A pin 4. ROM bootloader SSI RXD GPIO port A pin 5. ROM bootloader SSI TXD GPIO port A pin 6 GPIO port A pin 7 GPIO port D pin 0 GPIO port D pin 1 GPIO port D pin 2. Not available for DFZM-TT21X-DT0R RESET_N Digital input Reset, active low PD3 PD4 PD5 GND Digital I/O Digital I/O Digital I/O Ground GPIO port D pin 3. ROM bootloader UART RTS GPIO port D pin 4 GPIO port D pin 5 Ground 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Data Sheet Sheet 19 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 5. Electrical Characteristics 5-1.Absolute Maximum Rating Conditions beyond those cited in Table 5-1 may cause permanent damage to the DFZM-TT2xx, and must be avoided. Parameter Supply voltage(VCC) Storage temperature range Voltage on any digitai I/O Minimum Maximum
-0.3
-40
-0.3 3.9 125 VCC+0.3, 3.9 Unit V C V Table 5-1: Absolute Maximum Ratings 5-2.Recommended Operating Conditions Parameter Minimum Maximum Unit Operating supply voltage(VCC) Operating ambient temperature range(TA) 2
-40 3.6 110 V C Table 5-2: Recommended Operating Conditions 5-3.Power Consumption Test Conditions: TA=25 C, VCC=3.0V Parameter Test conditions Mim Typ Max Unit Icore Core current consumption Digital regulator on. 16MHz RCOSC running. No radio, crystals, or peripherals active. CPU running at 16-MHz with flash access 32MHz XOSC running. No radio or peripherals active. CPU 74 mA 13 mA Data Sheet Sheet 20 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx running at 32-MHz with flash access,. 32MHz XOSC running, radio in RX mode, 50dBm input power, no peripherals active, CPU idle@DFZM-TT22x 32MHz XOSC running, radio in RX mode, 50dBm input power, no peripherals active, CPU idle@DFZM-TT21x 32MHz XOSC running, radio in RX mode at -100dBm input power
(waiting for signal), no peripherals active, CPU idle@DFZM-TT22x 32MHz XOSC running, radio in RX mode at -100dBm input power (waiting for signal), no peripherals active, CPU idle@DFZM-TT21x 32MHz XOSC running, radio in TX mode, 7dBm output power, no peripherals active, CPU idle@DFZM-TT22x 32MHz XOSC running, radio in TX mode, 18.5dBm output power, no peripherals active, CPU idle@DFZM-TT21x Power mode 1. Digital regulator on; 16MHz RCOSC and 32MHz crystal oscillator off; 32.768kHz XOSC, POR, BOD and sleep timer active; RAM and register retention Power mode 2. Digital regulator off; 16MHz RCOSC and 32MHz crystal oscillator off; 32.768kHz XOSC, POR, and sleep timer active;
RAM and register retention Power mode 3. Digital regulator off; no clocks; POR active; RAM and Iperi Peripheral current consumption
(Adds to core current Icore for each peripheral unit activated) register retention General-
purpose Timer running, 32-MHz XOSC used timer SPI I2C UART Sleep timer Including 32.753-kHz RCOSC 20 24 mA mA 24 27 mA 27 34 150 0.6 mA mA mA uA 1.3 2 uA 0.4 1 uA 120 300 0.1 0.7 0.9 uA uA mA mA uA Data Sheet Sheet 21 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 48-MHz clock running, USB enabled When converting Erase Burst write peak current USB ADC Flash Table 5-3: Poewr Consumption DFZM-TT2xx 3.8 1.2 12 8 mA mA mA mA 5-4.DC Characteristics Test Conditions: TA=25 C, VCC=3.0V Parameter Test conditions Min Typ Max Unit Logic-0 input voltage Logic-1 input voltage Logic-0 input current Logic-1 input current Input equals 0 V Input equals VDD I/O-pin pullup and pulldown resistors Logic-0 output voltage, 4-mA pins Output load 4 mA Logic-1 output voltage, 4-mA pins Output load 4 mA Logic-0 output voltage, 20-mA pins Output load 20 mA Logic-1 output voltage, 20-mA pins Output load 20 mA Table 5-4: DC Characteristics 5-5.Wake-up and Timing Test Conditions: TA=25 C, VCC=3.0V 2.5
-300
-300 2.4 2.4 20 0.5 300 300 0.5 0.5 V V nA nA k V V V V Parameter Test conditions Min Typ Max Unit Power mode 1 active Digital regulator on, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of 16-MHz RCOSC Power mode 2 or 3 active Digital regulator off, 16-MHz RCOSC and 32-MHz crystal 4 136 us us Data Sheet Sheet 22 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Parameter Test conditions Min Typ Max Unit Active TX or RX oscillator off. Start-up of regulator and 16-MHz RCOSC Initially running on 16-MHz RCOSC, with 32-MHz XOSC OFF With 32-MHz XOSC initially on RX/TX and TX/RX turnaround USB PLL start-up time With 32-MHz XOSC initially on Table 5-5: Wake-up and Timing 0.5 192 192 32 ms us us us 5-6.Radio Parameters Test Conditions: TA=25 C, VCC=3.0V Parameter RF Frequency range Radio baud rate Radio chip rate Flash erase cycles Flash page size TX/RX specification for DFZM-TT22x Output power Error vector magnitude (EVM) Min 2394 Frequency error tolerance
-30 Receiver sensitivity Saturation(Maximum input level) TX/RX specification for DFZM-TT21x Output power Error vector magnitude (EVM) Frequency error tolerance Receiver sensitivity
-30 Typ 250 2 2 7 3 0
-97 10 18.5 3 0
-99 Max 2507 Unit MHz Kbps Mchip/s 20 K cycles 30
-92 30
-92 KB dBm
%
ppm dBm dBm dBm
%
ppm dBm Notes PER = 1%, PER = 1%, PER = 1%, Data Sheet Sheet 23 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change Parameter Saturation(Maximum input level) Min Typ 10 DFZM-TT2xx Max Unit dBm Notes PER = 1%, Table 5-6: Radio Parameters Test Condiction Min Typ Max Unit 5-7.ADC Parameters Test Conditions: TA=25 C, VCC=3.0V Parameter Input voltage External reference voltage External reference voltage differential Input resistance, signal Using 4-MHz clock speed Full-scale signal(1) Peak-to-peak, defines 0 dBFS ENOB(1) Effective number of bits Single-ended input, 7-bit setting Single-ended input, 9-bit setting Single-ended input, 10-bit setting Single-ended input, 12-bit setting Differential input, 7-bit setting Differential input, 9-bit setting Differential input, 10-bit setting Differential input, 12-bit setting Useful power bandwidth 7-bit setting, both single and differential 0 20 THD(1) Single-ended input, 12-bit setting, 6 dBFS Total harmonic distortion Differential input, 12-bit setting, 6 dBFS Single-ended input, 12-bit setting Differential input, 12-bit setting Single-ended input, 12-bit setting, 6 dBFS Differential input, 12-bit setting, 6 dBFS Signal to nonharmonic ratio(1) Data Sheet Sheet 24 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 0 0 0 197 2.97 5.7 7.5 9.3 10.8 6.5 8.3 10.0 11.5 VCC VCC VCC
-75.2
-86.6 70.2 79.3 78.8 88.9 V V V k V bits KHz dB dB DFZM-TT2xx CMRR Differential input, 12-bit setting, 1-kHz sine Common-mode rejection ratio
(0 dBFS), limited by ADC resolution Crosstalk Offset Gain error DNL(1) Differential nonlinearity INL(1) Integral nonlinearity SINAD(1) (THD+N) Signal-to-noise-and-distortion Conversion time Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution Midscale 12-bit setting, mean 12-bit setting, maximum 12-bit setting, mean 12-bit setting, maximum Single-ended input, 7-bit setting Single-ended input, 9-bit setting Single-ended input, 10-bit setting Single-ended input, 12-bit setting Differential input, 7-bit setting Differential input, 9-bit setting Differential input, 10-bit setting Differential input, 12-bit setting 7-bit setting 9-bit setting 10-bit setting 12-bit setting Internal reference voltage Internal reference VCC coefficient Internal reference temperature coefficient Table 5-7: ADC Parameters
(1) Measured with 300-Hz sine-wave input and VCC as reference. Data Sheet Sheet 25 of 39 84 84
-3 0.68 0.05 0.9 4.6 13.3 35.4 46.8 57.5 66.6 40.7 51.6 61.8 70.8 20 36 68 132 1.19 2 0.4 dB dB mV
%
LSB LSB dB us V mV/V mV/10C Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 5-8.Control Input AC Characteristics Test Conditions: TA= -40~110 C, VCC= 2.0~3.6V DFZM-TT2xx Parameter Test conditions Mim Typ Max Unit System clock, fSYSCLK TSYSCLK = 1/fSYSCLK The undivided system clock is 32 MHz when crystal oscillator is used. The undivided system clock is 16 MHz when calibrated 16 16-MHz RC oscillator is used. RESET_N low duration See item 1, Figure 5-1. This is the shortest pulse that is recognized as a complete reset pin request. Note that shorter pulses may be recognized but might not lead to complete reset of all modules within the chip. Interrupt pulse duration See item 2, Figure 5-1.This is the shortest pulse that is recognized as an interrupt request. 1 20 32 MHz us ns Table 5-8: Control Input AC Characteristics Figure 5-1: SPI Master AC Characteristics 5-9.USB Interface DC Characteristics Test Conditions: TA= 25 C, VCC= 3.0~3.6V Parameter Test conditions Mim Typ Max Unit USB pad voltage output, high VCC 3.6 V, 4-mA load USB pad voltage output, low VCC 3.6 V, 4-mA load 3.4 0.2 V V Data Sheet Sheet 26 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 6. Package and Layout Guidelines 6-1.Recommended PCB Footprint and Dimensions Figure 6-1: DFZM-TT2xx Module Recommended PCB Footprint (in mm) Data Sheet Sheet 27 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Figure 6-2: DFZM-TT2xx Module Dimensions (in mm) Data Sheet Sheet 28 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change 6-2.Layout Guidelines DFZM-TT2xx Keep out area for onboard antenna. All layers on the PCB must be clear.
(i.e. No GND, Power trace/plane, traces.) Note: If guidelines are not followed, DFZM-TT2xx range with onboard chip antenna will be compromised. Figure 6-3: DFZM-TT2xx module onboard antenna keep-out layout guidelines (in mm) Notes:
1. All Dimensions are in mm. Tolerances shall be 0.10 mm. 2. Absolutely no metal trace or ground layer underneath this area. 3. It is recommended not to run circuit traces underneath the module. 4. In performing SMT or manual soldering of the module to the base board, please align the two row of pins. In addition to the guidelines in Figure 6-3, note the following suggestions:
DFZM-TT2xx External Bypass capacitors for all module supplies should be as close as possible to the module pins. Never place the antenna very close to metallic objects. The external dipole antennas need a reasonable ground plane area for antenna efficiency. DFZM-TT221; DFZM-TT211 onboard antenna specific The onboard antenna keep out area, as shown in Figure 6-3, must be adhered to. In addition it is recommended to have clearance above and below the PCB trace antenna (Figure 6-4) for optimal range performance. Data Sheet Sheet 29 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Do not use a metallic or metalized plastic for the end product enclosure. Recommendation is to keep plastic enclosure clearance of 1cm from top and bottom of the DFZM-TT2xx onboard antenna keep-out area, if possible. 5-mm (0.2 in) clearance shall be the minimum as shown in Figure 6-4. Figure 6-4 Recommended clearance above and below the PCB trace antenna 6-2-1.Surface Mount Assembly The reflow profile is shown in Figure 6-8. Peak temp 250c max 10 sec max 245c5c for 10 ~30 sec
(C ) 245 217 200 150 Room temp. 50 sec max 60-180 sec 60-150 sec Data Sheet Figure 6-5: Reflow temperature profile Sheet 30 of 39 Proprietary Information and Specifications are Subject to Change Time Feb. 3, 2016 DFZM-TT2xx 1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the conditions of the parts and boards, and the specifications of the reflow furnace. 2. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the solder paste. 3. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time. 4. If the temperature is too low, non-melting tends to be caused in the area with large heat capacity after reflow. 5. Be careful about sudden rise in temperature as it may worsen the slump of solder paste. 6. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining strength at times. Note:
Data Sheet Sheet 31 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 6-3.Recommended Stencil Aperture Note: The thickness of the stencil should be 0.15mm over this area. Figure 6-9: DFZM-TT2xx recommended stencil aperture Data Sheet Sheet 32 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 7. Reference Design Schematic 8. DUT Setup DUT DUT PIN 3V3 500mA Data Sheet Feb. 3, 2016 Sheet 33 of 39 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx
:
RF Studio 7 :
Data Sheet Sheet 34 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx DUT FIND DEVICE LIST double click list double click list CC2538 OK control panel Data Sheet Sheet 35 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Ranger extender CC2591 Frequency selection on left-top, TX power choose 19.5 dBm Data Sheet Sheet 36 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx Data Sheet Sheet 37 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx 9. Federal Communications Commission (FCC) Statement 15.21 You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the users authority to operate the equipment. 15.105(b) This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
-Reorient or relocate the receiving antenna.
-Increase the separation between the equipment and receiver.
-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-Consult the dealer or an experienced radio/TV technician for help. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1) this device may not cause harmful interference, and 2) this device must accept any interference received, including interference that may cause Data Sheet Sheet 38 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change DFZM-TT2xx undesired operation of the device. FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. For modular approval, the following information needs to be in user manual:
Information for the OEMs and Integrators The following statement must be included with all versions of this document supplied to an OEM or integrator, but should not be distributed to the end user. This device is intended for OEM integrators only. Please See the full Grant of Equipment document for other restrictions. Information To Be Supplied to the End User by the OEM or Integrator:
The following regulatory and safety notices must be published in documentation supplied to the end user of the product or system incorporating an adapter in compliance with local regulations. Host system must be labeled with "Contains FCCID:H79DFZM-TT211, FCC ID displayed on label. Data Sheet Sheet 39 of 39 Feb. 3, 2016 Proprietary Information and Specifications are Subject to Change
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2016-04-29 | 2405 ~ 2480 | DTS - Digital Transmission System | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2016-04-29
|
||||
1 | Applicant's complete, legal business name |
Delta Electronics Incorporated
|
||||
1 | FCC Registration Number (FRN) |
0023665490
|
||||
1 | Physical Address |
3 Tungyuan Road
|
||||
1 |
Taoyuan County, N/A 32063
|
|||||
1 |
Taiwan
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
c******@telefication.com
|
||||
1 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
H79
|
||||
1 | Equipment Product Code |
DFZM-TT211
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
R**** C******
|
||||
1 | Title |
Manager
|
||||
1 | Telephone Number |
886 3******** Extension:
|
||||
1 | Fax Number |
886 3********
|
||||
1 |
r******@delta.com.tw
|
|||||
app s | Technical Contact | |||||
1 | Firm Name |
SGS Taiwan Ltd.
|
||||
1 | Name |
W**** C******
|
||||
1 | Physical Address |
134, Wu Kung Rd.
|
||||
1 |
Taiwan
|
|||||
1 | Telephone Number |
88622********
|
||||
1 | Fax Number |
88622********
|
||||
1 |
w******@sgs.com
|
|||||
app s | Non Technical Contact | |||||
1 | Firm Name |
SGS Taiwan Ltd.
|
||||
1 | Name |
W****** C****
|
||||
1 | Physical Address |
134, Wu Kung Rd.
|
||||
1 |
Taiwan
|
|||||
1 | Telephone Number |
88622********
|
||||
1 | Fax Number |
88622********
|
||||
1 |
w******@sgs.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | If so, specify the short-term confidentiality release date (MM/DD/YYYY format) | 10/16/2016 | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DTS - Digital Transmission System | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | zigBee module | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Single Modular Approval | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Output power listed is conducted. This grant is valid only when the module is sold to OEM integrators and must be installed by the OEM or OEM integrators. The antenna's as listed in this application must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. End-users may not be provided with the module installation instructions. OEM integrators and end-users must be provided with transmitter operating conditions for satisfying RF exposure compliance. | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
SGS Taiwan Ltd.
|
||||
1 | Name |
R****** W****
|
||||
1 | Telephone Number |
+886-******** Extension:
|
||||
1 | Fax Number |
+886-********
|
||||
1 |
R******@sgs.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2405.00000000 | 2480.00000000 | 0.0950000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC