WARNING:pdfminer.pdfpage:The PDF <_io.BufferedReader name='/Volumes/Scratch/Incoming/eg-scratch/5861937.pdf'> contains a metadata field indicating that it should not allow text extraction. Ignoring this field and proceeding. Use the check_extractable if you want to raise an error in this case Everestek Inc. Everestek 5GHz Module (MD) Data Sheet Everestek Inc. Version: 0.1 Subject to change without further notice. 2022/05/06 www.everestek.biz Page 1 INDEX 1. Features .................................................................................................................................................... 3 2. Application .............................................................................................................................................. 3 3. Electrical Specifications .......................................................................................................................... 4 I2S Format ............................................................................................................................................... 5 4. 5. I2C Timing ............................................................................................................................................... 6 6. Module Pin Definition ............................................................................................................................. 7 7. Federal Communication Commission Interference Statement ................................................................ 9 8. Revision History .................................................................................................................................... 10 Everestek Inc. www.everestek.biz Page 2 1. Features Everestek Inc. The MD is a module based on dual Everestek ETK52, providing uncompressed or compressed audio applications operating in the 5.8/5.2 GHz bands. The wireless audio link support lots of application, like subwoofer, stereo, headphone, headset, microphone, and comes with additional features such as data encryption, pairing functionality, bi-directional data messages, enhanced RF interference detection, and automatic frequency allocation. Brief features include:
Radio Frequency: 5.8/5.2 GHz unlicensed bands Link Distance: up to 10 ~ 40 meters depends on application Advanced RF Selection Algorithm Small RF Foot Print Best Coexistence with Wi-Fi/Bluetooth Highly Integrated SoC: RF/PA/CPU/Flash Embedded Wide-Band Antenna on Module Short RBOM List RF Modulation: FSK Digital I2S (master or slave) Audio Interface, 16/24bit , 32/44.1/48/96KHz Sampling Rate Low Power Consumption Supply Voltage: 2.7~3.6V Support I2C master/slave mode and UART Compliant with EMC Regulations (FCC/CE) 2. Application Wireless HIFI Mono Wireless HIFI Stereo Wireless 2.1CH with Advanced Audio Quality www.everestek.biz Page 3 Everestek Inc. 3. Electrical Specifications Item RF Carrier Frequency
-20dB bandwidth Output Power RF Sensitivity Item VDD Operating Temperature Min 5725 5135 Min 2.7
-5 RF Specification Typ 2 7
-81 Max 5850 5260 Unit MHz MHz dBm dBm Note For 5.8G For 5.2G Operation Condition Typ 3.3 25 Max 3.6 60 Unit Note V C Power Supply Voltage Ambient temperature Item Min Transmitter current Receiver current RF idle with ARM
@33MHz sleep mode Electrical Specification (MCU+RF) Max Unit Typ Note 160 80 120 60 40 24 8 mA mA mA mA mA mA mA Output power 7dBm, two chip in operation Output power 7dBm, one chip in operation Output power 7dBm, two chip in operation Output power 7dBm, one chip in operation RF idle, two chip in operation RF idle, one chip in operation Crystal enable, timer or interrupt wake up system Note: power consumption is different depends on application. Item VIH VIL VOH VOL Digital interface Min Typ Max Unit Note 0.7VDD VSS VDD-0.3 0 VDD+0.2 0.3VDD VDD 0.3 V V V V Input High Threshold Input Low Threshold Output High Threshold Output Low Threshold www.everestek.biz Page 4 Everestek Inc. 4. I2S Format ETK52 I2S data in and data out share the same LRCK and BCK pins. ETK52 can work in master mode and slave mode. The audio sampling rate can be 32/44.1/48K. In master mode, ETK52 will generate I2S_MCLK/LRCK/BCK for external audio codec. In slave mode, ETK52 will receive external LRCK/BCK signal. ETK52 has a digital controlled PLL, so the clock jitter noise will not be a problem in Rx. During operate in slave mode, ETK52 will tracking external audio clock to make Tx and Rx work in the same frequency. Mono channel data can feed through left channel (Lch) or right channel (Rch). If 2(stereo) or 1(mono) channel application, Tx I2S signal connection as followed, Note: if module is operated in I2S slave mode, module dont need MCLK signal. Only need BCK, LRCK, DIN signals. ETK52 work in 64 Fs mode. This means total 64 BCK pulse in one LRCK cycle. The I2S signal as the chart followed, I2S master mode (Tx and Rx site) switching characteristics Symbol Min Typ Max Unit MCLK BCK Duty (MCLK, BCK) 256fs 64fs 50 Hz Hz
Symbol Min Typ Max Unit Note tBKLR tBKDO (Rx only)
-1
-1
+1
+1 ns ns BCK falling edge to DOUT transient www.everestek.biz Page 5 LRCKBCKDIN(stereo)P1.2P1.3P1.1TxMCLKMCLK(256Fs)01231516171819232526312401231516171819232526242322218976510LRCKBCK2322218976510DATA Note: DIN setup time and hold time timing in master mode is same as slave mode. Everestek Inc. I2S slave mode (Tx site) switching characteristics Symbol Min Typ Max Unit BCK 64fs Hz Symbol Min Typ Max Unit Note tBKLR tLRBK tDSU tDHO 10 10 20 20 ns ns ns ns BCK rising to LRCK edge LRCK edge to BCK rising DIN setup time DIN hold time Second I2S data input please refer to manual 2.1_Second_I2S_AppNote v1.0 for client.pdf. 5. I2C Timing www.everestek.biz Page 6 LRCKBCKDOUTtBKLR50% dutytBKDOLRCKBCKDINtBKLRtLRBKtDSUtDHO Everestek Inc. Parameter Symbol Min SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time:
Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition FSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO TBUF 4 2.2 2.2 4 0 100 4 10 Max 200 unit KHz us us us us us ns ns ns us us 500 300 Please also refer to Everestek_I2C_200KHz_and_USB_HID_desciption.pdf for detail. 6. Module Pin Definition Note:
XXXX-A: means this GPIO is connect to A-chip. XXXX-B: means this GPIO is connect to B-chip. XXXX-dual: means this GPIO is connect to both A-chip and B-chip. Pin Name VDD 1 DGND 2 MCLK-A 3 DGND 4 D-_A 5 DGND 6 D+_A 7 DGND 8 I/O P P O P A P A P Function Definition VDD (2.7V~3.6V) System ground For audio codec system clock(12.288MHz or 11.2896MHz) System ground USB D-
System ground USB D+
System ground www.everestek.biz Page 7 9 10 11 12 13 14 15 P0.7_CS-A P2.0_DOUT1-A P2.7-A P1.5_I2S_DataIn2-A P0.6_SCK-A P1.5-B P0.5_MISO-A I/O, C I/O I/O I/O I/O, C I/O I/O, C 16 FLASH_PROG C P0.4_MOSI-A I/O, C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 P0.0_SCL- dual P0.1_SDA- dual P2.0_DOUT1-B P1.6-A P1.2_I2S_LRCK-dual P2.7_PWM-B P1.3_I2S_BCK-dual P1.1_I2S_DIN-A P1.0_I2S_DOUT-A P1.1_I2S_DIN-B P1.0_I2S_DOUT-B P3.2-A P3.2-B P0.6_SCK-B 32 P0.7_CS-B 33 P0.4_MOSI-B 34 P0.5_MISO-B Everestek Inc. GPIO and SPI SCK for SPI in programming internal flash mode I2S Data out (spare) or GPIO GPIO GPIO or 2nd I2S data input for subwoofer General I/O and SPI SCK for SPI in programming internal flash mode GPIO General I/O and SPI MISO for SPI in programming internal flash mode Program mode select, active high, default pull low For programming internal flash memory Please leave this pin float for normal operation. General I/O and SPI MOSI for SPI in programming internal flash mode General I/O, I2C clock General I/O, I2C data I2S Data out (spare) or GPIO GPIO I2S LRCK(input for I2S slave, output for I2S master) GPIO or PWM I2S BCK(input for I2S slave, output for I2S master) I2S Data in(from audio codec, or from ADC I2S DATA out) I2S Data out(to audio codec, or to DAC I2S DATA in) I2S Data in(from audio codec, or from ADC I2S DATA out) I2S Data out(to audio codec, or to DAC I2S DATA in) General I/O General I/O General I/O and SPI SCK for programming internal flash mode General I/O and SPI chip select for programming internal flash mode General I/O and SPI MOSI for programming internal flash mode General I/O and SPI MISO for programming internal flash mode I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, C I/O, C I/O, C I/O, C www.everestek.biz Page 8 Everestek Inc. 7. Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate this equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This device is restricted for indoor use. FCC Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. IMPORTANT NOTE:
This module is intended for OEM integrator. This module is only FCC authorized for the specific rule parts listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. The final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. Additional testing and certification may be necessary when multiple modules are used. USERS MANUAL OF THE END PRODUCT:
In the users manual of the end product, the end user has to be informed to keep at least 20cm separation with the antenna while this end product is installed and operated. The end user has to be informed that the FCC radio-frequency exposure guidelines for an uncontrolled environment can be satisfied. The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment. This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation. www.everestek.biz Page 9 LABEL OF THE END PRODUCT:
The final end product must be labeled in a visible area with the following " Contains TX FCC ID: 2AWBQ-EWMD ". Everestek Inc. This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation. Antenna Information Ant. Antenna Type Gain (dBi) 1 2 PCB PCB 2 2 8. Revision History Revision 0.1 Descriptions Draft Date 2022/05/06 www.everestek.biz Page 10