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V110 USER MANUAL Rugged Mobile Computing Solutions February 2018 TRADEMARKS All brand and product names are trademarks or registered trademarks of their respective companies. NOTE The information in this manual is subject to change without notice. For the latest version of the manual, please visit the Getac website at www.getac.com. Table of Contents Chapter 1 Chapter 2 Getting Started.................................................................................................................. 1 Getting the Computer Running ........................................... 2 Unpacking .................................................................. 2 Connecting to AC Power ............................................... 3 Opening and Closing the Cover ...................................... 4 Operating in Tablet Mode .............................................. 5 Turning On and Off the Computer .................................. 7 Taking a Look at the Computer ......................................... 9 Front Components ........................................................ 9 Rear Components ....................................................... 10 Right-Side Components ................................................ 11 Left-Side Components .................................................. 12 Top-open Components ................................................. 13 Bottom Components ..................................................... 15 Installing the Accessories ................................................. 17 Attaching the Carrying Strap ......................................... 17 Using the Tether ........................................................ 18 Attaching the Handgrip Strap (Optional) ......................... 19 Operating Your Computer ......................................................................................... 20 Using the Internal Keyboard ............................................. 21 Typewriter Keys .......................................................... 21 Cursor-Control Keys .................................................... 21 Numeric Keypad ........................................................ 22 Function Keys ........................................................... 23 Fn Key .................................................................... 23 i Chapter 3 Chapter 4 Hot Keys ................................................................. 23 Windows Keys ........................................................... 24 Using the Touchpad ....................................................... 26 Touch Gestures for Windows 10 ................................... 27 Configuring the Touchpad ............................................ 27 Navigating on the Screen................................................ 29 Using the Touchscreen ................................................ 29 Using the Dual Mode Display (Optional) ....................... 32 Using Network and Wireless Connections ........................... 33 Using the LAN .......................................................... 33 Using the WLAN ....................................................... 33 Using the BT Feature ................................................. 34 Using the WWAN Feature (Optional) ........................... 35 Managing Power ........................................................................................................... 40 AC Adapter ................................................................... 41 Battery Pack ................................................................ 42 Charging the Battery Pack ........................................... 42 Initializing the Battery Pack .......................................... 43 Checking the Battery Level .......................................... 43 Battery Low Signals and Actions ................................... 44 Replacing the Battery Pack .......................................... 44 Power-Saving Tips ........................................................ 47 Expanding Your Computer ........................................................................................ 48 Connecting Peripheral Devices .......................................... 49 Connecting a Display Monitor ....................................... 49 Connecting a USB Device ........................................... 49 Connecting a Device for USB Charging .......................... 50 Connecting a Serial Device ........................................... 51 Connecting an Audio Device ......................................... 51 Using Various Card Readers............................................ 53 Using Smart Cards .................................................... 53 Using ExpressCards .................................................... 54 Using the NFC/RFID Reader (Optional) ....................... 55 Using the Fingerprint Scanner (Optional) .......................... 38 ii Chapter 5 Chapter 6 Chapter 7 Chapter 8 Enrolling a Fingerprint ................................................. 38 Fingerprint Login ........................................................ 39 Changing or Replacing ................................................... 56 Replacing the Hard Disk Drive ..................................... 56 System Memory Upgrade ............................................. 57 Using BIOS Setup .......................................................................................................... 60 When and How to Use ................................................... 61 Menu Descriptions ......................................................... 62 Information Menu ....................................................... 62 Main Menu ............................................................... 62 Advanced Menu ......................................................... 63 Security Menu ........................................................... 65 Boot Menu ............................................................... 66 Exit Menu ................................................................ 66 Using Getac Software ..................................................................................................67 OSD Control Panel ........................................................ 68 G-Manager .................................................................. 69 G-Camera .................................................................... 71 Care and Maintenance ................................................................................................ 72 Protecting the Computer .................................................. 73 Using an Anti-Virus Strategy ....................................... 73 Using the Cable Lock ................................................. 73 Taking Care of the Computer .......................................... 74 Location Guidelines ..................................................... 74 General Guidelines ..................................................... 74 Cleaning Guidelines .................................................... 75 Battery Pack Guidelines .............................................. 75 Touchscreen Guidelines ............................................... 77 When Traveling ............................................................. 78 Troubleshooting ............................................................................................................79 Preliminary Checklist ....................................................... 80 Solving Common Problems ............................................... 81 Battery Problems ......................................................... 81 BT Problems .............................................................. 81 iii Display Problems ....................................................... 82 Hardware Device Problems .......................................... 82 Keyboard and Touchpad Problems ................................. 83 LAN Problems ........................................................... 83 Power Management Problems ....................................... 84 Sensor Problems ........................................................ 84 Software Problems ..................................................... 85 Sound Problems ........................................................ 85 Startup Problems ....................................................... 86 WLAN Problems ........................................................ 86 Other Problems ......................................................... 88 Resetting the Computer .................................................. 89 System Recovery ........................................................... 90 Using Windows RE .................................................... 90 Using Recovery Partition ............................................... 91 Using the Driver Disc (Optional) ..................................... 93 Appendix A Specifications ................................................................................................................ 94 Appendix B Regulatory Information ............................................................................................. 96 On the Use of the System ............................................. 97 Class B Regulations ................................................... 97 ANSI Warning ........................................................... 98 Safety Notices ........................................................... 99 On the Use of the RF Device ....................................... 103 USA and Canada Safety Requirements and Notices......... 103 European Union CE Marking and Compliance Notices ...... 105 User Notification of Take-back Service ............................. 107 ENERGY STAR 6.1 ...................................................... 108 Battery Recycling .......................................................... 110 iv Chapter 1 Chapter 1 Getting Started This chapter first tells you step by step how to get the computer up and running. Then, you will find a section briefly introducing the external components of the computer. 1 Getting the Computer Running Unpacking After unpacking the shipping carton, you should find these standard items:
V110 notebook computer AC adapter AC power cord Battery pack x 2 Screen cleaning cloth Stylus Carrying strap Tether Document(s) Driver disc (optional) Inspect all the items. If any item is damage or missing, notify your dealer immediately. 2 Connecting to AC Power CAUTION: Use only the AC adapter included with your computer. Using other AC adapters may damage the computer. NOTE:
The battery pack is shipped to you in power saving mode that protects it from charging/discharging. It will get out of the mode to be ready for use when you install the battery pack and connect AC power to the computer for the very first time. When the AC adapter is connected, it also charges the battery pack. For information on using battery power, see Chapter 3. You must use AC power when starting up the computer for the very first time. 1. Plug the DC cord of the AC adapter to the power connector of the computer
(). 2. Plug the female end of the AC power cord to the AC adapter and the male end to an electrical outlet (). 3. Power is being supplied from the electrical outlet to the AC adapter and onto your computer. Now, you are ready to turn on the computer. 3 Opening and Closing the Cover To open the top cover:
1. Pull loose the cover latch () and release the clamp (). 2. Lift up the cover (). You can tilt the cover forward or backward for optimal viewing clarity. To close the top cover:
1. Close the display. 2. Lift the cover latch and engage the clamp on the display. Then, push in the cover latch to click it into place. CAUTION: Before engaging the clamp, make sure the two guide pins are correctly seated in place. 4 Correct: guide pin correctly seated Wrong: guide pin not seated Correct: guide pin correctly seated Wrong: guide pin not seated Operating in Tablet Mode In addition to being used as a regular notebook computer (Laptop mode), your computer can also be operated in Tablet mode. In Tablet mode, you operate the computer with a stylus or digitizer pen, or a fingertip, instead of a keyboard or mouse. 1. Open the top cover so that it is almost perpendicular with the keyboard of the computer. 2. Turn the display counter-clockwise by 180o. CAUTION: Do not rotate the display more than 180o, or attempt to rotate the display clockwise. 5 3. Close the computer with the display facing up. 4. Lift the cover latch and engage the clamp on the display. Then, push in the cover latch to click it into place. CAUTION: Before engaging the clamp, make sure the two guide pins are correctly seated in place. 6 Correct: guide pin correctly seated Wrong: guide pin not seated Correct: guide pin correctly seated Wrong: guide pin not seated Turning On and Off the Computer Turning On Press the power button (
). The Windows operating system should start. NOTE: Tapping the screen during startup may invoke a pre-boot menu (unless the default settings have been changed). If the menu appears, simply select Continue. Turning Off When you finish a working session, you can stop the system by turning off the power or leaving it in Sleep or Hibernation mode:
To... Do this... Power off (Shutdown) Click Sleep Power Shut down. Use one of these methods:
Press the power button.*
Close the top cover.*
Press Fn + F12.*
Click By default, this option is not shown in the Start menu. Power Sleep. Hibernate 7 To... Do this... If you want to use the feature, set up accordingly in Windows settings.
* Sleep is the default result of the action. You can change what the action does through Windows settings. 8 Taking a Look at the Computer NOTE: Depending on the model you purchased, the appearance of your computer may not be exactly the same as those shown in this manual. CAUTION: You need to open the protective covers to access the connectors. When not using a connector, make sure to close the cover completely for water- , dust-, and fire-proof integrity.
(Engage the locking mechanism if existing.) Front Components Description Two buckles hold the carrying strap. Sends out sound and voice from your computer. Turns the power on or off. (The default off state is Sleep mode.) Increases the sound volume. Decreases the sound volume. Locks the top cover. Receives sound and voice to record voice. Opens or closes the OSD Control Panel. Starts the G-Camera application. When pressed longer:
Serves as the Ctrl+Alt+Del keyboard keys. Ref Component Strap holder Stereo speaker Power button Down button Up button Top cover latch Microphone P2 button P1 button 9 NOTE: The hardware buttons (except the power button) can be re-defined using G-Manager. Rear Components To access a connector, open its protective cover by lifting up the tab of the cover. When closing the cover, push the tab downward until the cover clicks into place. Ref Component Description Power connector Connects the AC adapter. HDMI connector USB 3.0 port Connects a HDMI monitor or TV set. Connects a USB device, such as a flash disk, printer, digital camera, joystick, and more. Connects the LAN cable. Connects a serial device. Locks the computer to a stationary object for security. RJ-45 connector Serial port Kensington lock 10 Right-Side Components To access a connector, open its protective cover by lifting up the tab of the cover. When closing the cover, push the tab downward until the cover clicks into place. To access a device bay, slide the cover latch toward the unlocked position ( ) and then lift up the tab to release the cover. When closing the cover, push the tab downward until the cover clicks into place and then slide the latch toward the locked position ( ). Ref Component Description USB port PowerShare Battery pack Inside is the battery pack (Battery 2) that supplies power to your computer when external power is not connected. Provides either of the below two functions depending on your setting. Charges a connected mobile device.
- or -
Functions as a standard USB 3.0 port (default setting). Connects a set of headphones or external speakers with amplifier Supports a headset microphone with 4-pole TRRS 3.5mm jack. Accepts a smart card for additional security feature. Combo audio connector Smart card 11 slot Ref Component ExpressCard slot Description Accepts an ExpressCard for additional functions. Left-Side Components To access a device bay, slide the cover latch toward the unlocked position ( ) and then lift up the tab to release the cover. When closing the cover, push the tab downward until the cover clicks into place and then slide the latch toward the locked position ( ). Description Inside is the hard disk drive. Inside is the battery pack (Battery 1) that supplies power to your computer when external power is not connected. Ref Component Hard disk drive Battery pack 12 Top-open Components Description Reads data from NFC/RFID tags. Displays and receives information for the computer. Allows you to use your computers camera function. When the camera lens is in use, the LED beside it lights up. Serves as the fingerprint verification, preventing unauthorized access to your computer. Ref Component RFID antenna
(optional) Touchscreen Camera lens Fingerprint scanner
(optional) 13 Ref Component Light sensor Windows logo button Indicators Power Battery charge Hard disk drive in-use Description Detects the surrounding lighting condition for automatic adjustment of the LCD brightness. Opens or closes the Start menu. Show the current status of the computers devices. Lights green when the computer is turned on. Blinks green when the computer is in Sleep mode. Lights amber when the battery is being charged. Lights green when battery charging is completed. Blinks green to indicate the batterys built-in high temperature protection mechanism is activated. CAUTION: Do not remove the battery during this period. Blinks red when the batterys capacity is below 10%. Blinks amber when the battery charging is in an abnormal state. Replace the battery in case this happens. Lights green when the computer is accessing the hard disk drive. Caps Lock Lights green when Caps Lock is on. RF (Radio Lights green when the RF radio of any RF feature
(WLAN/BT/WWAN) is on. Serves as the data input device. Serves as the pointing device. Frequency) Keyboard Touchpad 14 Bottom Components Ref Component Camera indicator
(optional) Flash (optional) Camera lens
(optional) Memory slots SIM card slot
(optional) Description Lights up when the camera lens beside it is in use. Provides extra light when taking pictures. Allows you to use the camera function. Inside are the memory slots for expanding the memory size of your computer. Inside is the SIM card slot. Antenna pass-
through (optional) Connects to the docking station for using external WWAN/WLAN/GPS antenna. WWAN WLAN GPS 15 Ref Component Docking connector Description Inside is the docking connector for connecting an office dock or vehicle dock (purchased separately). 16 Installing the Accessories Attaching the Carrying Strap Insert one end of the strap into one strap holder () on your computer and feed it through the slider buckle (). Use the fastener () to fix the strap end in place. Secure the other end of the strap to the computer in the same way. The strap provides a slot for storing the stylus (). 17 Using the Tether A tether is available for attaching the stylus to your computer. 1. Insert one of the tethers loop ends through the hole of the stylus (as indicated by below). Then, insert the other end through the first loop (as indicated by below) and pull it tight. 2. Insert the other loop end to the strap holder on computer (as indicated by below). Then, insert the stylus end through the loop (as indicated by below) and pull it tight. 18 Attaching the Handgrip Strap (Optional) 1. Insert a hook to each of the computers four bottom corners. Secure each hook with a screw. 2. Attach the four loops of the handgrip strap to the four hooks. Make sure the loops are securely hooked. When you need to operate and hold your computer at the same time, insert your hand through the strap for a firm grip. 19 Chapter 2 Chapter 2 Operating Your Computer This chapter provides information about the use of the computer. If you are new to computers, reading this chapter will help you learn the operating basics. If you are already a computer user, you may choose to read only the parts containing information unique to your computer. CAUTION:
Do not expose your skin to the computer when operating it in a very hot or cold environment. The computer can get uncomfortably warm when you use it in high temperatures. As a safety precaution in such a circumstance, do not place the computer on your lap or touch it with your bare hands for extended periods of time. Prolonged body contact can cause discomfort and potentially a burn. 20 Using the Internal Keyboard Your keyboard has all the standard functions of a full-sized computer keyboard plus an Fn key added for specific functions. The standard functions of the keyboard can be further divided into four major categories:
Typewriter keys Cursor-control keys Numeric keys Function keys Typewriter Keys Typewriter keys are similar to the keys on a typewriter. Several keys are added such as the Ctrl, Alt, Esc, and lock keys for special purposes. The Control (Ctrl) / Alternate (Alt) key is normally used in combination with other keys for program-specific functions. The Escape (Esc) key is usually used for stopping a process. Examples are exiting a program and canceling a command. The function depends on the program you are using. Cursor-Control Keys Cursor-control keys are generally used for moving and editing purposes. NOTE: The word cursor refers to the indicator on the screen that lets you know exactly where on your screen anything you type will appear. It can take the form of a vertical or horizontal line, a block, or one of many other shapes. 21 Numeric Keypad A 15-key numeric keypad is embedded in the typewriter keys as shown next:
Numeric keys facilitate entering of numbers and calculations. When Num Lock is on, the numeric keys are activated; meaning you can use these keys to enter numerals. NOTE:
When the numeric keypad is activated and you need to type the English letter in the keypad area, you can turn Num Lock off or you can press Fn and then the letter without turning Num Lock off. Some software may not be able to use the numeric keypad on the computer. If so, use the numeric keypad on an external keyboard instead. The Num Lock key can be disabled. (See Main Menu in Chapter 5.) 22 Function Keys On the top row of the keys are the function keys: F1 to F12. Function keys are multi-purpose keys that perform functions defined by individual programs. Fn Key The Fn key, at the lower left corner of the keyboard, is used with another key to perform the alternative function of a key. To perform a desired function, first press and hold Fn, then press the other key. Hot Keys Hot keys refer to a combination of keys that can be pressed any time to activate special functions of the computer. Most hot keys operate in a cyclic way. Each time a hot key combination is pressed, it shifts the corresponding function to the other or next choice. You can easily identify the hot keys with the icons imprinted on the keytop. The hot keys are described next. Key Description Switches the keyboard backlight on and off (option). Switches the RF (radio frequency) radio on and off. When off, all wireless modules (such as WLAN, BT, and WWAN) cannot be used. When on, individual settings of the module work. Decreases the sound volume. Increases the sound volume. 23 Key Description Switches the display output to the next choice if an external display is connected. Choices are:
LCD only LCD + External display (Duplicate) LCD + External display (Extend) External display only The hot keys are equivalent to Windows logo key + P. Decreases the LCD brightness. Increases the LCD brightness. Switches the touchscreen on or off. Switches the touchpad off or on. Switches the system sound output off (mute) or on. Switches the display on or off. Serves as the sleep button that you can define with Windows Power Options. Windows Keys The keyboard has two keys that perform Windows-specific functions:
Logo key and Application key. Windows 24 Windows Logo key opens the Start menu and performs software-
The specific functions when used in combination with other keys. The key usually has the same effect as a right mouse click. Application 25 Using the Touchpad CAUTION: Do not use a sharp object such as a pen on the touchpad. Doing so may damage the touchpad surface. NOTE:
Press Fn+F9 to toggle the touchpad on or off. For optimal performance of the touchpad, keep your fingers and the pads clean and dry. When tapping on the pad, tap lightly. Do not use excessive force. The touchpad is a pointing device that allows you to communicate with the computer by controlling the location of the pointer on the screen and making selection with the buttons. The touchpad consists of a rectangular pad (work surface) and a left and right buttons. To use the touchpad, place your forefinger or thumb on the pad. The rectangular pad acts like a miniature duplicate of your display. As you slide your fingertip across the pad, the pointer (also called cursor) on the screen moves accordingly. When your finger reaches the edge of the pad, simply relocate yourself by lifting the finger and placing it on the other side of the pad. Here are some common terms that you should know when using the touchpad:
26 Term Point Click Double-click Action Move your finger on the pad until the cursor points to the selection on the screen. Press and release the left button. or Tap gently anywhere on the pad. Press and release the left button twice in quick succession. or Tap twice on the pad rapidly. Drag and drop Press and hold the left button, then move your finger until you reach your destination (drag). Finally, release the button
(drop) when you finish dragging your selection to the destination. The object will drop into the new location. or Gently tap twice on the pad and on the second tap, keep your finger in contact with the pad. Then, move your finger across the pad to drag the selected object to your destination. When you lift your finger from the pad, the selected object will drop into place. Touch Gestures for Windows 10 The touchpad supports touch gestures for Windows 10 such as one-finger scrolling, two-finger scrolling, pinch zoom, rotating, and others. For detailed information, go to Settings Devices Mouse & touchpad Additional mouse options Device Settings Settings. Configuring the Touchpad You may want to configure the touchpad to suit your needs. For example, if you are a left-handed user, you can swap the two buttons so that you can use the right button as the left button and vice versa. You can also change the size of the on-screen pointer, the speed of the pointer, and so on. 27 To configure the touchpad, go to Settings Devices Mouse & touchpad. 28 Navigating on the Screen The screen of your computer is touch-sensitive. You can operate the computer by touching the screen with your finger or the stylus. CAUTION: Do not use a sharp object such as a ballpoint pen or pencil on the touchscreen. Doing so may damage the touchscreen surface. NOTE: An optical film has been attached to the screen before shipment. The film is a consumable, which will be worn out by possible scratches. You can purchase a new one when replacement is required. Using the Touchscreen Your computer has a capacitive touchscreen. This type of touchscreen responds to objects that have conductive properties, such as fingertips and a capacitive-tipped stylus. You can change the touchscreen sensitivity settings to suit your scenario. Double-tap the Touch Screen Mode shortcut on Windows desktop to open the settings menu and select one of the options (as shown below). Select this if you prefer using fingertips. Also, select this when raindrops are falling on the screen and should be rejected as input. Select this if you are using the stylus. (You must use the one supplied with your model.) Select this if you are wearing gloves (referring to warm gloves or work gloves, not referring to touchscreen-capable gloves). NOTE: If liquid is spilled on the touchscreen causing a wet area, the area will stop responding to any inputs. For the area to function again, you must dry it. 29 The following table shows how you use the touchscreen to obtain equivalent mouse functions. Term/Action Equivalent Mouse Function Tap: Touch the screen once. Double-tap: Touch the screen twice rapidly. Tap and hold: Tap and hold until a popup menu appears. Drag: Hold the stylus (or finger) on the screen and drag across the screen until reaching your destination. Click/Point Double-click Right-click Drag Using Multi-touch Gestures You can interact with your computer by placing two fingers on the screen. The movement of the fingers across the screen creates gestures, which send commands to the computer. Here are the multi-touch gestures that you can use:
Gestures Pan
(Scroll) Actions
( = finger down; = finger up) Descriptions Use panning to see another part of a page that has scroll bars. or Drag 1 or 2 fingers up or down. 30 Gestures Zoom
(Pinch) Rotate Press and Tap Two-
finger Tap Actions
( = finger down; = finger up) Descriptions Use zooming to make an item (a photo for example) on the screen larger or smaller. The gesture works in applications that support mouse wheel zooming. Use rotating to move a picture or other item on the screen in a circular direction (clockwise or counter-
clockwise). The gesture works in applications that support the specific gesture. Use press and tap to access the shortcut menu. The function is defined by applications that support the specific gesture. Move two fingers apart/toward each other. or Move two fingers in opposing directions.
-or-
Use one finger to pivot around another. Press on target and tap using a second finger. Tap two fingers at the same time (where the target is in the midpoint between the fingers). 31 Gestures Flicks Actions
( = finger down; = finger up) Descriptions Make quick drag gestures in the desired direction. Flick left or right to navigate back and forward in a browser and other applications. The gesture works in most applications that support back and forward. Using the Dual Mode Display (Optional) Dual mode display (if your model has the feature) incorporates both touchscreen and digitizer functions. The display is set to Touchscreen mode by default. Touchscreen mode provides all the functionalities that an ordinary touchscreen has. When the Computer receives signals from the digitizer pen, the display automatically switches to Digitizer mode. You can move the cursor by bringing the digitizer pen close to the screen, without actually touching the screens surface. 32 Using Network and Wireless Connections Using the LAN To connect the network cable to the LAN module, connect one end of the LAN cable to the RJ-45 connector on the computer and the other end to the network hub. Using the WLAN The WLAN (Wireless Local Area Network) module of your computer supports IEEE 802.11a/b/g/n/ac. Turning On/Off the WLAN Radio To turn on the WLAN radio:
Click On position. Settings Network & Internet Wi-Fi. Slide the Wi-Fi switch to the To turn off the WLAN radio:
You can turn off the WLAN radio the same way you turn it on. If you want to quickly turn off all wireless radio, simply switch on Airplane mode. You can control the Airplane mode using one of the below methods. Press Fn+F1. Use the Airplane Mode button in the OSD Control Panel. 33 Click Settings Network & Internet Airplane mode. Connecting to a WLAN Network 1. Make sure that the WLAN function is enabled (as described above). 2. Click the network icon 3. Select the device you want to connect from the search results. in the lower right of the task bar. 4. Some networks require a network security key or passphrase. To connect to one of those networks, ask your network administrator or Internet service provider
(ISP) for the security key or passphrase. For more information on setting a wireless network connection, refer to Windows online help. Using the BT Feature The BT technology allows short-range wireless communications between devices without requiring a cable connection. Data can be transmitted through walls, pockets and briefcases as long as two devices are within range. Turning On/Off the BT Radio To turn on the BT radio:
Click Settings Devices BT. Slide the BT switch to the On position. To turn off the BT radio:
You can turn off the BT radio the same way you turn it on. If you want to quickly turn off all wireless radio, simply switch on Airplane mode. You can control the Airplane mode using one of the below methods. Press Fn+F1. Use the Airplane Mode button in the OSD Control Panel. Click Settings Network & Internet Airplane mode. 34 Connecting to another BT Device 1. Make sure that the BT function is enabled (as described above). 2. Make sure that the target BT device is turned on, discoverable and within close range. (See the documentation that came with the BT device.) 3. Click Settings Devices BT. 4. Select the device you want to connect from the search results. 5. Depending on the type of BT device that you want to connect to, you will need to enter the pertinent information. For detailed information on using the BT feature, see Windows online Help. Using the WWAN Feature (Optional) A WWAN (Wireless Wide Area Network) uses mobile telecommunication cellular network technologies to transfer data. The WWAN module of your computer supports 3G and 4G LTE. NOTE: Your model only supports data transmission. Voice transmission is not supported. Installing a SIM Card 1. Turn off the computer and disconnect the AC adapter. 2. Carefully place the computer upside down. 3. Remove the 8 screws to open the compartment cover. 35 4. Locate the SIM card holder. Slide the SIM card holder tray toward the OPEN direction to unlock. Lift up the tray and, noting the orientation, insert the SIM card into the tray. Close the holder tray and slide it back to the locked position. 5. Close the compartment cover and secure with 8 screws. Turning On/Off the WWAN Radio To turn on the WWAN radio:
Click switch to the On position. Settings Network & Internet Airplane mode. Slide the Cellular 36 To turn off the WWAN radio:
You can turn off the WWAN radio the same way you turn it on. If you want to quickly turn off all wireless radio, simply switch on Airplane mode. You can control the Airplane mode using one of the below methods. Press Fn+F1. Use the Airplane Mode button in the OSD Control Panel. Click Settings Network & Internet Airplane mode. Setting up a WWAN Connection Settings Network & Internet Cellular. (For detailed information on Tap cellular settings in Windows 10, see Microsoft Support website.) 37 Using the Fingerprint Scanner
(Optional) CAUTION:
For optimal performance, both the scanning surface and the finger should be clean and dry. Clean the scanning surface when needed. You can use adhesive tape to remove dirt and oil from the scanner surface. It is not recommended that you use the fingerprint scanner in a below-
freezing temperature. The moisture on your finger can freeze to the scanners metal surface when you touch it, resulting in a failed operation. Besides, touching freezing metal with your finger can cause frostbite. The fingerprint scanner (if your model has the feature) provides a strong authentication mechanism based on fingerprint recognition. You can log on to Windows and dismiss the lock screen with an enrolled fingerprint instead of a password. Fingerprint scanner Enrolling a Fingerprint NOTE: You can enroll a fingerprint only after creating a password for the Windows user account. 1. Click Settings Accounts Sign-in options. 2. On the right side under Fingerprint, click Set up. 38 3. Follow the onscreen instructions to complete. Fingerprint Login NOTE: The fingerprint login process can take a while. This is because the system has to check hardware devices and security configuration before initiating the fingerprint scanner. With an enrolled fingerprint, the user can log on by tapping the Fingerprint option in Windows login screen and then placing the finger on the scanner. The user can also dismiss the lock screen with the fingerprint. The fingerprint scanner has 360-degree readability. You can place your finger in any orientation for the scanner to recognize an enrolled fingerprint. If fingerprint login attempts fail three times, you will be switched to password login. 39 Chapter 3 Chapter 3 Managing Power Your computer operates either on external AC power or on internal battery power. This chapter tells you how you can effectively manage power. To maintain optimal battery performance, it is important that you use the battery in the proper way. 40 AC Adapter CAUTION:
The AC adapter is designed for use with your Computer only. Connecting the AC adapter to another device can damage the adapter. The AC power cord supplied with your Computer is for use in the country where you purchased your Computer. If you plan to go overseas with the Computer, consult your dealer for the appropriate power cord. When you disconnect the AC adapter, disconnect from the electrical outlet first and then from the Computer. A reverse procedure may damage the AC adapter or Computer. When unplugging the connector, always hold the plug head. Never pull on the cord. The AC adapter serves as a converter from AC (Alternating Current) to DC (Direct Current) power because your Computer runs on DC power, but an electrical outlet usually provides AC power. It also charges the battery pack when connected to AC power. The adapter operates on any voltage in the range of 100~240 V AC. 41 Battery Pack Your computer has two battery packs. The battery pack is the internal power source for the computer. It is rechargeable using the AC adapter. NOTE: Care and maintenance information for the battery is provided in the Battery Pack Guidelines section in Chapter 7. Charging the Battery Pack NOTE:
Charging will not start if the batterys temperature is outside the allowed range, which is between 0 C (32 F) and 50 C (122 F). Once the temperature meets the requirements, charging automatically resumes. During charging, do not disconnect the AC adapter before the battery has been fully charged; otherwise you will get a prematurely charged battery. The battery has a high temperature protection mechanism which limits the maximum charge of the battery to 80% of its total capacity in the event of high temperature conditions. In such conditions, the battery will be regarded as fully charged at 80% capacity. The battery level may automatically lessen due to the self-discharge process (0.21% per day), even when the battery pack is fully charged (100%). This happens no matter if the battery pack is installed in the computer. To charge the battery pack, connect the AC adapter to the computer and an electrical outlet. The Battery Charge Indicator ( ) on the computer glows amber to indicate that charging is in progress. You are advised to keep the computer power off while the battery is being charged. When the battery is fully charged, the Battery Charge Indicator glows green. The two battery packs are charged in parallel. It takes approximately 5 hours to fully charge the two battery packs when the power is off and approximately 6 hours when the power is on (may need a longer charging time at lower temperatures). 42 CAUTION: After the computer has been fully recharged, do not immediately disconnect and reconnect the AC adapter to charge it again. Doing so may damage the battery. Initializing the Battery Pack You need to initialize a new battery pack before using it for the first time or when the actual operating time of a battery pack is much less than expected. Initializing is the process of fully charging, discharging, and then charging. It can take several hours. A software tool called Gauge Reset is provided for the purpose. Use the G-Manager program and select the Battery tab to find the tool. Checking the Battery Level NOTE: Any battery level indication is an estimated result. The actual operating time can be different from the estimated time, depending on how you are using the computer. The operating time of a fully charged battery pack depends on how you are using the computer. When your applications often access peripherals, you will experience a shorter operating time. The two battery packs are discharged in parallel. By Operating System You can check the approximate battery level using the battery meter function of the operating system. To read the battery level in Windows, click the battery icon on the taskbar. By Gas Gauge On the exterior side of the battery pack is a gas gauge for displaying the estimated battery charge. When the battery pack is not installed in the computer and you want to know the battery charge, you can press the push-button to see the number of LEDs that light up. Each LED represents 20% charge. 43 Push-button Battery Low Signals and Actions The battery icon changes appearance to display the current state of the battery. Battery Icon Battery Level Description Discharging The icon shows the charge remaining in 10-percent Low Critically low increments until the charge reaches the low-battery level. The battery charge has reached the low-battery level. The battery charge has reached the critical battery level. By default, Windows will display a notification and put your computer into Hibernation. When the battery is low, the computers Battery Charge Indicator ( ) also blinks red to alert you to take actions. Always respond to low-battery by connecting the AC adapter, placing your computer in Hibernation mode, or turning off the computer. Replacing the Battery Pack CAUTION:
There is danger of explosion if the battery is incorrectly replaced. Replace the battery only with the computer manufacturers battery packs. Discard used batteries according to the dealers instructions. Do not attempt to disassemble the battery pack. NOTE: You can hot swap one battery pack while the other one is supplying the power. 44 To replace the battery pack, follow these steps:
1. Depending on which battery pack ( on the left side or on the right side) you want to replace, open the respective cover. Slide the cover latch toward the unlocked position ( ) () and then lift up the tab () to release the cover.
(Battery 1 as the example) 2. Hold the battery latch and slide it toward the right to unlock.
(Battery 1 as the example) CAUTION: To unlock or lock, always hold the battery latch itself to move it. Never use the ribbon strip to pull the battery latch. The wrong method can cause a broken strip or an incorrect battery pack installation. 3. Remove the battery pack out of the slot by pulling the ribbon strip. 4. Noting the orientation, insert the new battery pack all the way into the slot. 5. Hold the battery latch and slide it toward the left to the locked position. 45
(Battery 1 as the example) 6. When closing the cover, push the tab downward until the cover clicks into place and then slide the latch toward the locked position ( ). CAUTION: Make sure the latch is correctly locked, not revealing the underneath red part. Correct Incorrect (revealing red part) 46 Power-Saving Tips Aside from enabling your computers power saving mode, you can do your part to maximize the batterys operating time by following these suggestions. Do not disable Power Management. Decrease the LCD brightness to the lowest comfortable level. Shorten the length of time before Windows turn off the display. When not using a connected device, disconnect it. Turn off the wireless radio if you are not using the wireless module (such as WLAN, BT, or WWAN). Turn off the computer when you are not using it. 47 Chapter 4 Chapter 4 Expanding Your Computer You can expand the capabilities of your computer by connecting other peripheral devices. When using a device, be sure to read the instructions accompanying the device together with the relevant section in this chapter. 48 Connecting Peripheral Devices Connecting a Display Monitor If you want the benefits of a larger display screen with higher resolution, you can connect an external display monitor to your computer. Your computer supports an HDMI connector. HDMI (High-Definition Multimedia Interface) is an audio/video interface that transmits uncompressed digital data and therefore delivers true HD quality. You can switch the display output by using Fn+F5, Windows Control Panel, or OSD Control Panel. Connecting a USB Device Your computer has two USB 3.0 ports for connecting USB devices, such as a digital camera, scanner, printer, modem, and mouse. NOTE: You computer has a PowerShare USB port. This port can be set to function as a standard USB 3.0 port. (See Connecting a Device for USB Charging later for information.) 49 Connecting a Device for USB Charging You computer has a PowerShare USB port (
). You can use this port to charge mobile devices even when the computer is in power-off, sleep, or hibernation state. A connected device is charged by either external power (if the AC adapter is connected) or by the computers battery (if the AC adapter is not connected). In the latter case, charging will stop when the battery level gets low (20% capacity). Notes and Cautions on USB Charging To use the USB charging feature, you must first enable the feature by running the BIOS Setup program or the G-Manager program. (See Advanced Menu in Chapter 5 or G-Manager in Chapter 6.) Otherwise the PowerShare USB port functions as a standard USB 3.0 port. Before connecting a device for charging, make sure the device works with the USB charging feature. Connect a device directly to this port. Do not connect via a USB hub. After resuming from sleep or hibernation, the computer may not detect the connected device. If this happens, try disconnecting and reconnecting the cable. USB charging will stop in the following situations. You shut down the computer by pressing the power button for more than 5 seconds All power (AC adapter and battery pack) is disconnected and then reconnected during power-off state. 50 For USB devices which do not require charging, connect them to other USB ports on your computer. Connecting a Serial Device Your computer has a serial port for connecting a serial device such as a serial mouse or serial communication device. Connecting an Audio Device For higher audio quality, you can send sound through an external audio device. The combo connector is the 4-pole TRRS 3.5mm type (Apple iPhone Recessed) so you can connect a compatible headset microphone. SAFETY WARNING:
To prevent possible hearing damage, do not listen at high volume levels for long periods. 51 52 Using Various Card Readers Using Smart Cards With an embedded microcontroller, smart cards have the unique ability to store large amounts of data, carry out their own on-card functions (e.g., encryption and mutual authentication), and interact intelligently with a smart card reader. To insert a smart card:
1. Locate the smart card reader. Open its protective cover by lifting up the tab of the cover. 2. Slide the smart card, with its label and embedded computer chip facing up into the slot (the lower one). Chip 3. When closing the cover, push the tab downward until the cover clicks into place. NOTE: An ExpressCard in the upper slot hinders the removal of the smart card. In this case, first remove the ExpressCard so that you can remove the smart card. To remove a smart card:
1. Make sure that the software is not accessing the smart card. 2. Open the cover. 3. Slightly push the card to release and then pull it out of the slot. 4. Close the cover. 53 Using ExpressCards The ExpressCard slot can accommodate a 54 mm (ExpressCard/54) or 34 mm
(ExpressCard/34) wide ExpressCard. Typical ExpressCards support a very extensive range of applications including memory, wired and wireless communication cards, and security devices. To insert an ExpressCard:
1. Locate the ExpressCard slot. Open its protective cover by lifting up the tab of the cover. 2. Slide the ExpressCard, with its label facing up, all the way into the slot (the upper one) until the rear connectors click into place. 3. When a new card is seated, the computer will detect it and try to install the appropriate driver. Follow the on-screen instructions to complete the process. 4. When closing the cover, push the tab downward until the cover clicks into place. To remove an ExpressCard:
1. Double-click on the Safely Remove Hardware icon found on the Windows taskbar and the Safely Remove Hardware window appears on screen. 2. Select (highlight) the ExpressCard from the list to disable the card. 3. Open the cover. 4. Pull the card out of the slot. 5. Close the cover. 54 Using the NFC/RFID Reader (Optional) If your model has the NFC/RFID reader module, you can read data from NFC (Near Field Communication) and RFID (Radio Frequency Identification) tags. RFID antenna NOTE:
For optimal results when reading an NFC/RFID tag, have the tag face the antenna in the same orientation as indicated by the icon on the exterior of the computer. For your model, the icon shows a horizontal position. When not using an NFC/RFID card, do not leave it within or near the antenna area. For enhanced applications and customization of the module, contact your authorized Getac dealer. The NFC reader requires specialized applications. For further information, ask your system administrator. 55 Changing or Replacing Replacing the Hard Disk Drive 1. Turn off the computer and disconnect the AC adapter. 2. Slide the cover latch toward the unlocked position ( ) () and then lift up the tab () to release the cover. 3. Using the ribbon strip, first pull the small latch toward the right to unlock () and then pull the hard disk drive out of the device bay (). 4. Noting the orientation, insert the new hard disk drive all the way into the slot until the small latch clicks into place. 5. When closing the cover, push the tab downward until the cover clicks into place and then slide the latch toward the locked position ( ). CAUTION: Make sure the latch is correctly locked, not revealing the underneath red part. Correct Incorrect (revealing red part) 56 System Memory Upgrade You can upgrade your computer by expanding system memory. CAUTION:
It is not recommended that you buy and install RAM modules by yourself. If you want to expand system memory, please ask Getac service center to install DRAM modules for you so that full compatibility can be guaranteed. RAM modules are extremely sensitive to static electricity. There are cases where static electricity generated by the human body has adversely affected such modules. When inserting or removing a RAM module, do not touch the terminals or internal components, insert objects other than the module, or allow foreign particles to enter. Doing so has been known to cause damage, fire, or electrical shock. To install the RAM module:
1. Disconnect the AC adapter and remove the battery packs. 2. Carefully place the computer upside down. 3. Remove the 8 screws to open the compartment cover. 57 4. Remove the plastic bar by unfastening two screws. 5. To install the RAM module, match the module's notched part with the socket's projected part and firmly insert the module into the socket at a 20-degree angle
(). Then push down until the retaining clips lock the module into position
(). CAUTION: If the RAM module is difficult to insert or difficult to push down, do not force it. Check once more to ensure that the module is positioned correctly. 6. Replace the plastic bar and secure with two screws. 7. Close the compartment cover and secure with 8 screws. 8. Replace the battery packs. 58 59 Chapter 5 Chapter 5 Using BIOS Setup BIOS Setup Utility is a program for configuring the BIOS (Basic Input/ Output System) settings of the computer. BIOS is a layer of software, called firmware, that translates instructions from other layers of software into instructions that the computer hardware can understand. The BIOS settings are needed by your computer to identify the types of installed devices and establish special features. This chapter tells you how to use the BIOS Setup Utility. 60 When and How to Use NOTE:
The actual setting items on your model may differ from those described in this chapter. The availability of some setting items depends on the Windows version your computer is running. You need to run BIOS Setup Utility when:
You see an error message on the screen requesting you to run BIOS Setup Utility. You want to restore the factory default BIOS settings. You want to modify some specific settings according to the hardware. You want to modify specific settings to optimize the system performance. To run BIOS Setup Utility:
Method 1: During system startup when the logo screen appears, click the screen or press the Windows Logo button on your Computer. In the pre-boot menu that appears, select Setup Utility. NOTE:
If you dont want any accidental tapping to invoke the pre-boot menu, you can disable this method by setting the Screen Tapping for Boot Options item in the BIOS Setup Utility. For Windows 10 models, the time period in which you can use the above method is extremely short. You can use the other method as described below. Method 2: Click Settings Update & security Recovery. Under Advanced startup, click Restart now. In the boot options menu, click Troubleshoot Advanced options UEFI Firmware Settings. Click Restart. In the pre-boot menu that appears, select Setup Utility. 61 Menu Descriptions Information Menu The Information menu contains the basic configuration information of the system. There are no user-definable items in this menu. NOTE: The Asset Tag information appears when you have entered the asset number for this computer using the asset management program. The program is provided in the Asset tag folder of the Driver disc. Main Menu The Main menu contains the various system settings. System Date sets the system date. System Time sets the system time. OS Select specifies which version of Windows your computer is running. Boot Priority determines the first device that the system boots from. Select Legacy First or UEFI First according to your needs. Legacy USB Support enables or disables the systems support for Legacy USB. CSM Support enables or disables CSM (Compatibility Support Mode). You can set this item to Yes for backward compatibility with legacy BIOS services. PXE Boot sets the PXE boot to UEFI or Legacy. PXE (Preboot eXecution Environment) is an environment to boot computers using a network interface independently of data storage devices or installed operating systems. Internal Numlock sets if the Num Lock function of the built-in keyboard can work. When set to Enabled, you can press Fn + Num Lock to activate the numeric keypad, which is embedded in the typewriter keys. When set to Disabled, Num Lock does not work. In this case, you can still press Fn + a letter key to enter a number. 62 Advanced Menu The Advanced menu contains the advanced settings. Wake Up Capability Any-key Wake Up From S3 state allows any key to wake up the system from S3
(Sleep) state. USB Wake-Up From S3 allows a USB device activity to wake up the system from S3 (Sleep) state. System Policy allows you to choose between Performance and Balance. If battery life is your first priority, select Balance. If you need system performance more than battery life, select Performance. AC Initiation sets if connecting AC power will automatically start or resume the system. Screen Tapping for Boot Options sets if tapping the screen during startup will invoke the boot options menu which provides access to some pre-boot operations. If disabled, tapping the screen during startup has no effect to the systems booting process. USB Power-off Charging (PowerShare USB) enables or disables the USB charging feature of the PowerShare USB port. When disabled, the PowerShare USB port functions as a standard USB 3.0 port. For detailed information on the PowerShare USB port, see Connecting a Device for USB Charging in Chapter 4. MAC Address Pass Through allows the system specific MAC address to pass through a connected dock, meaning the dock specific MAC address will be overridden by the system specific MAC address. This feature only works for UEFI PXE boot. Active Management Technology Support (This item appears only on models supporting vPro.) Intel AMT Support enables or disables Intel Active Management Technology BIOS extension execution. AMT allows the system administrator to access an AMT featured computer remotely. Intel AMT Setup Prompt determines whether the prompt for entering Intel AMT Setup appears or not during POST. 63 Virtualization Technology Setup Intel(R) Virtualization Technology enables or disables Intel VT (Intel Virtualization Technology) feature which provides hardware support for processor virtualization. When enabled, a VMM (Virtual Machine Monitor) can utilize the additional hardware virtualization capabilities provided by this technology. Intel(R) VT for Directed I/O (VT-d) enables or disables VT-d (Intel Virtualization Technology for Directed I/O). When enabled, VT-d helps enhance Intel platforms for efficient virtualization of I/O devices. Graphics Setup DVMT Pre-Allocated sets the amount of pre-allocated (fixed) graphics memory for use by the internal graphics device. Device Configuration enables or disables several hardware components. The items available for setting depend on your model. Recovery Partition allows you to restore your Windows 10 system to the factory default state by using the recovery partition feature. Recovery partition is a portion of your hard disk drive that is set aside by the manufacturer to hold the original image of your system. WARNING:
Using this feature will reinstall Windows to your system and configure it to the systems factory default settings. All data on the hard disk drive will be lost. Make sure that power is not interrupted during the recovery process. An unsuccessful recovery may result in Windows startup problems. Windows RE launches Windows Recovery Environment. Windows RE (Windows Recovery Environment) is a recovery environment that provides recovery, repair, and troubleshooting tools in Windows 10. 64 Security Menu The Security menu contains the security settings, which safeguard your system against unauthorized use. NOTE:
You can set the user password only when the supervisor password has been set. If both the supervisor and user passwords are set, you can enter any of them for starting up the system and/or entering BIOS Setup. However, the user password only allows you to view/change the settings of certain items. A password setting is applied right after it is confirmed. To cancel a password, leave the password empty by pressing the Enter key. Set Supervisor/User Password sets the supervisor/user password. You can set the supervisor/user password to be required for starting up the system and/or entering BIOS Setup. Password on Boot allows you to enable or disable the entering of password for booting up your system. Set HDD 0 User Password sets the password for locking the Primary Master hard disk drive. After setting a password, the hard disk drive can only be unlocked by the password no matter where it is installed. TPM Setup Menu TPM Support enables or disables TPM (Trusted Platform Module) support. TPM
(Trusted Platform Module) is a component on your computers mainboard that is specifically designed to enhance platform security by providing a protected space for key operations and other security critical tasks. Change TPM Status allows you to select between No Change and Clear. Intel Trusted Execution Technology enables utilization of additional hardware capabilities provided by Intel Trusted Execution Technology. 65 Boot Menu The Boot menu sets the sequence of the devices to be searched for the operating system. Boot Type Order determines the boot order. You can rearrange the order by dragging the boot device name up or down in the list. Each boot device can be individually set to On or Off. If you want to exclude a boot device from the boot order, set the device to Off. Exit Menu The Exit menu displays ways of exiting BIOS Setup Utility. After finishing with your settings, you must save and exit so that the changes can take effect. Exit Saving Changes saves the changes you have made and exits BIOS Setup Utility. Exit Discarding Changes exits BIOS Setup Utility without saving the changes you have made. Load Setup Defaults loads the factory default values for all the items. Discard Changes restores the previous values for all the items. Saves Changes saves the changes you have made. 66 Chapter 6 Chapter 6 Using Getac Software Getac software includes application programs for specific computer components and utility programs for overall management. This chapter briefly introduces the programs. 67 OSD Control Panel The OSD (On Screen Display) Control Panel provides a user-friendly interface for you to quickly activate or operate certain functions on your computer with a simple click of the screen. To open the OSD Control Panel, start the program named OSDC. The following screen appears. Help For detailed information on the program, see the programs online help. 68 G-Manager G-Manager is a unified user interface utility that allows you to view, manage, or configure your computer features. With G-Manager, you can perform all or some of the tasks listed below. View system information. Check the battery status and configure the battery. Configure ECO modes (or called power profiles). Set the touchscreen sensitivity mode. Enable PowerShare USB feature. Set if a warning message will appear when a connected docking station is removed unexpectedly. Enable the use of external GPS/WWAN/WLAN antenna signal. Change the function of the hardware button. Configure how your system works with the vehicle ignition. Monitor the system. View GPS information. Right-click the Getac Utility icon G-Manager to start the program. The G-Manager window appears, containing several tabs. located on Windows taskbar and select NOTE: Depending on your model, the actual items and information appearing on the screen may differ from those shown in this manual. 69 Help For detailed information on the program, see the programs online help. 70 G-Camera G-Camera is a geo-tagging camera application. Geographical information can be embedded into JPEG files as EXIF 2.2 metadata. NOTE: G-Camera uses the standard location service of Windows. To start the G-Camera application, select All apps G-Camera. In the middle is the preview window with status display. At the two sides are various buttons. For detailed information on the program, see the programs online help. Click Help. 71 Chapter 7 Chapter 7 Care and Maintenance Taking good care of your computer will ensure a trouble-free operation and reduce the risk of damage to your computer. This chapter gives you guidelines covering areas such as protecting, storing, cleaning, and traveling. 72 Protecting the Computer To safeguard the integrity of your computer data as well as the computer itself, you can protect the computer in several ways as described in this section. Using an Anti-Virus Strategy You can install a virus-detecting program to monitor potential viruses that could damage your files. Using the Cable Lock You can use a Kensington-type cable lock to protect your computer against theft. The cable lock is available in computer stores. To use the lock, loop the lock cable around a stationary object such as a table. Insert the lock to the Kensington lock hole and turn the key to secure the lock. Store the key in a safe place. 73 Taking Care of the Computer Location Guidelines For optimal performance, use the computer where the recommended temperature is between 0 C (32 F) and 55 C (131 F). (Actual operating temperature depends on product specifications.) Avoid placing the computer in a location subject to high humidity, extreme temperatures, mechanical vibration, direct sunlight, or heavy dust. Using in extreme environments for long periods can result in product deterioration and a shortened product life. Operating in an environment with metallic dust is not allowed. Place the computer on a flat and steady surface. Do not stand the computer on its side or store it in an upside-down position. A strong impact by dropping or hitting may damage the computer. Do not cover or block any ventilation openings on the computer. For example, do not place the computer on a bed, sofa, rug, or other similar surface. Otherwise, overheating may occur that results in damage to the computer. As the computer can become very hot during operation, keep it away from objects that are vulnerable to heat. Keep the computer at least 13 cm (5 inches) away from electrical appliances that can generate a strong magnetic field such as a TV, refrigerator, motor, or a large audio speaker. Avoid moving the computer abruptly from a cold to a warm place. A temperature difference of more than 10 C (18 F) may cause condensation inside the unit, which may damage the storage media. General Guidelines Do not place heavy objects on top of the computer as this may damage the display. 74 Do not move the computer simply by grasping the display screen. To avoid damaging the screen, do not touch it with any sharp object. LCD image sticking occurs when a fixed pattern is displayed on the screen for a prolonged period of time. You can avoid the problem by limiting the amount of static content on the display. It is recommended that you use a screen saver or turn off the display when it is not in use. To maximize the life of the backlight in the display, allow the backlight to automatically turn off as a result of power management. Cleaning Guidelines Never clean the computer with its power on. Use a soft cloth moistened with water or a non-alkaline detergent to wipe the exterior of the computer. Gently wipe the display with a soft, lint-free cloth. Dust or grease on the touchpad can affect its sensitivity. Clean the pad by using adhesive tape to remove the dust and grease on its surface. If water or liquid is split onto the computer, wipe it dry and clean when possible. Though your computer is water-proof, do not leave the computer wet when you can dry it. If the computer gets wet where the temperature is 0C (32F) or below, freeze damage may occur. Make sure to dry the wet computer. Battery Pack Guidelines Recharge the battery pack when it is nearly discharged. When recharging, make sure that the battery pack is fully charged. Doing so may avoid harm to the battery pack. The battery pack is a consumable product and the following conditions will shorten its life:
75 when frequently charging the battery pack when using, charging, or storing the battery in high temperature condition To avoid hastening the deterioration of the battery pack thereby prolonging its useful life, minimize the number of times you charge it so as not to frequently increase its internal temperature. Charge the battery pack between 10 C ~ 30 C (50 F ~ 86 F) temperature range. A higher environment temperature will cause the battery packs temperature to rise. Avoid charging the battery pack inside a closed vehicle and in hot weather condition. Also, charging will not start if the battery pack is not within the allowed temperature range. It is recommended that you do not charge the battery pack more than once a day. It is recommended that you charge the battery pack with the computers power off. To maintain the battery packs operating efficiency, store it in a cool dark place removed from the computer and with 30 % ~ 40 % charge remaining. Important guidelines when using the battery pack. When installing or removing the battery pack take note of the following:
avoid installing or removing the battery pack when the computer is in Sleep mode. Abruptly removing the battery pack may cause loss of data or the computer may become unstable. avoid touching the battery pack terminals or damage may occur, thereby causing improper operation to it or the computer. The computers input voltage and surrounding temperature will directly affect the battery packs charge and discharge time:
charging time will be prolonged when the computer is turned on. To shorten the charging time, it is recommended that you place the computer in Sleep or hibernation mode. a low temperature will prolong the charging time as well as hasten the discharge time. 76 When using battery power in an extremely low temperature environment, you may experience shortened operating time and incorrect battery level reading. This phenomenon comes from the chemical characteristics of batteries. The appropriate operating temperature for the battery is -10 C ~ 50 C (14 F ~ 122 F). Do not leave the battery pack in storage for more than six months without recharging it. Touchscreen Guidelines Use your finger or the stylus (if purchased) on the display. Using a sharp or metallic object other than your finger or stylus may cause scratches and damage the display, thereby causing errors. Use a soft cloth to remove dirt on the display. The touchscreen surface has a special protective coating that prevents dirt from sticking to it. Not using a soft cloth may cause damage to the special protective coating on the touchscreen surface. Turn off the computer power when cleaning the display. Cleaning the display with the power on may cause improper operation. Do not use excessive force on the display. Avoid placing objects on top of the display as this may cause the glass to break thereby damaging the display. Using the touchscreen during low temperature (below 5 oC / 41 F) may cause a slower response time, this is normal. A normal response time may be restored upon returning to room temperature. When there is noticeable discrepancy in the operation of the touchscreen function
(wrong location on intended operation or improper display resolution), refer to the Windows online Help for instructions on recalibrating the touchscreen display. 77 When Traveling Before traveling with your computer, make a backup of your hard disk data into flash disks or other storage devices. As an added precaution, bring along an extra copy of your important data. Make sure that the battery pack is fully charged. Make sure that the computer is turned off and the top cover is securely closed. Make sure that all the connector covers are closed completely to ensure the waterproof integrity. Do not leave objects in between the keyboard and closed display. Disconnect the AC adapter from the computer and take it with you. Use the AC adapter as the power source and as a battery-charger. Hand-carry the computer. Do not check it in as luggage. If you need to leave the computer in the car, put it in the trunk of the car to avoid exposing the computer to excessive heat. When going through airport security, it is recommended that you send the computer and flash disks through the X-ray machine (the device you set your bags on). Avoid the magnetic detector (the device you walk through) or the magnetic wand (the handheld device used by security personnel). If you plan to travel abroad with your computer, consult your dealer for the appropriate AC power cord for use in your country of destination. 78 Chapter 8 Chapter 8 Troubleshooting Computer problems can be caused by hardware, software, or both. When you encounter any problem, it might be a typical problem that can easily be solved. This chapter tells you what actions to take when solving common computer problems. 79 Preliminary Checklist Here are helpful hints to follow before you take further actions when you encounter any problem:
Try to isolate which part of the computer is causing the problem. Make sure that you turn on all peripheral devices before turning on the computer. If an external device has a problem, make sure that the cable connections are correct and secure. Make sure that the configuration information is properly set in the BIOS Setup program. Make sure that all the device drivers are correctly installed. Make notes of your observations. Are there any messages on the screen? Do any indicators light? Do you hear any beeps? Detailed descriptions are useful to the service personnel when you need to consult one for assistance. If any problem persists after you follow the instructions in this chapter, contact an authorized dealer for help. 80 Solving Common Problems Battery Problems The battery does not charge (Battery Charge indicator does not light amber). Make sure that the AC adapter is properly connected. Make sure that the battery is not too hot or cold. Allow time for the battery pack to return to room temperature. If the battery doesn't charge after it has been stored in very low temperatures, try disconnecting and reconnecting the AC adapter to solve the problem. Make sure that the battery pack is installed correctly. Make sure that the battery terminals are clean. The operating time of a fully charged battery becomes shorter. If you often partially recharge and discharge, the battery might not be charged to its full potential. Initialize the battery to solve the problem. The battery operating time indicated by the battery meter does not match the actual operating time. The actual operating time can be different from the estimated time, depending on how you are using the computer. If the actual operating time is much less than the estimated time, initialize the battery. BT Problems I cannot connect to another device with BT wireless technology. Make sure that both devices have activated BT feature. Make sure that the distance between the two devices is within the limit and that there are no walls or other obstructions between the devices. Make sure that the other device is not in Hidden mode. 81 Make sure that both devices are compatible. Display Problems Nothing appears on the screen. During operation, the screen may automatically turn off as a result of power management. Press any key to see if the screen comes back. The brightness level might be too low. Increase the brightness. The display output might be set to an external device. To switch the display back to the LCD, press the Fn+F5 hot key or change the display through the Display Settings Properties. The characters on the screen are dim. Adjust the brightness and/or contrast. The display brightness cannot be increased. As a protection, the display brightness will be fixed at a low level when the surrounding temperature is too high or too low. It is not a malfunction in this situation. Bad dots appear on the display at all times. A small number of missing, discolored, or bright dots on the screen are an intrinsic characteristic of TFT LCD technology. It is not regarded as a LCD defect. Clouding (or called mura) happens on the screen when you exert forces on the left or right side of the LCD frame. This is a normal phenomenon, not a defect. Hardware Device Problems The computer does not recognize a newly installed device. The device may not be correctly configured in the BIOS Setup program. Run the BIOS Setup program to identify the new type. 82 Make sure if any device driver needs to be installed. (Refer to the documentation that came with the device.) Make sure if the device needs any jumper or switch settings. (Refer to the documentation that came with the device.) Check the cables or power cords for correct connections. For an external device that has its own power switch, make sure that the power is turned on. Keyboard and Touchpad Problems The keyboard does not respond. Try connecting an external keyboard. If it works, contact an authorized dealer, as the internal keyboard cable might be loose. Water or liquid is spilt into the keyboard. Immediately turn off the computer and unplug the AC adapter. Then turn the keyboard upside down to drain the liquid out of the keyboard. Make sure to clean up any part of the spill you can get to. Though the keyboard of your computer is spill-proof, liquid will remain in the keyboard enclosure if you dont remove it. Wait for the keyboard to air dry before using the computer again. The touchpad does not work, or the pointer is difficult to control with the touchpad. Make sure that the touchpad is clean. LAN Problems I cannot access the network. Make sure that the LAN cable is properly connected to the RJ-45 connector and the network hub. Make sure that the network configuration is appropriate. Make sure that the user name or password is correct. 83 Power Management Problems The computer does not enter Sleep or Hibernation mode automatically. If you have a connection to another computer, the computer does not enter Sleep or Hibernation mode if the connection is actively in use. Make sure that the Sleep or Hibernation time-out is enabled. The computer does not enter Sleep or Hibernation mode immediately. If the computer is performing an operation, it normally waits for the operation to finish. The computer does not resume from Sleep or Hibernation mode. The computer automatically enters Sleep or Hibernation mode when the battery pack is empty. Do any one of the following:
Connect the AC adapter to the computer. Replace the empty battery pack with a fully charged one. Sensor Problems The built-in digital compass doesnt seem to be accurate. Rotating the display can affect the accuracy of the digital compass. This is normal, not a malfunction. The sensors for the compass require periodic recalibration. Follow this method to recalibrate the sensors:
1. Make sure you are far away from any large metal objects or magnetic fields. 2. Start an application that utilizes the digital compass. 3. Hold the computer level with the horizon, with the LCD side facing up. 4. Rotate the computer 360 at least three times around each axis (X, Y, and Z) as shown below. 84 Software Problems An application program does not work correctly. Make sure that the software is correctly installed. If an error message appears on the screen, consult the software programs documentation for further information. If you are sure the operation has stop, reset the computer. Sound Problems No sound is produced. Make sure that the volume control is not set too low. Increase the volume. 85 Make sure that the sound is not muted. Make sure that the computer is not in Sleep mode. If using an external speaker, make sure that the speaker is properly connected. Distorted sound is produced. Make sure that the volume control is not set too high or too low. In most cases, a high setting can cause the audio electronics to distort the sound. Startup Problems When you turn on the computer, it does not respond and the Power Indicator does not light green. If you are using an external AC power, make sure that the AC adapter is correctly and securely connected. If so, make sure that the electrical outlet works properly. If you are using the battery power, make sure that the battery is not discharged. When the ambient temperature is below -20 C (-4 F), the computer will start up only if both battery packs are installed. When you turn on the computer, it stops after POST. Reset your computer. WLAN Problems I cannot use the WLAN feature. Make sure that the WLAN feature is turned on. Transmission quality is poor. Your computer may be in an out-of-range situation. Move your computer closer to the Access Point or another WLAN device it is associated with. Check if there is high interference around the environment and solve the problem as described next. 86 Radio interference exists. Move your computer away from the device causing the radio interference such as microwave oven and large metal objects. Plug your computer into an outlet on a different branch circuit from that used by the affecting device. Consult your dealer or an experienced radio technician for help. I cannot connect to another WLAN device. Make sure that the WLAN feature is turned on. Make sure that the SSID setting is the same for every WLAN device in the network. Your computer is not recognizing changes. Restart the computer. Make sure that the IP address or subnet mask setting is correct. I cannot communicate with the computer in the network when Infrastructure mode is configured. Make sure that the Access Point your computer is associated with is powered on and all the LEDs are working properly. If the operating radio channel is in poor quality, change the Access Point and all the wireless station(s) within the BSSID to another radio channel. Your computer may be in an out-of-range situation. Move your computer closer to the Access Point it is associated with. Make sure that your computer is configured with the same security option
(encryption) to the Access Point. Use the Web Manager/Telnet of the Access Point to check whether it is connected to the network. Reconfigure and reset the Access Point. 87 I cannot access the network. Make sure that the network configuration is appropriate. Make sure that the user name or password is correct. You have moved out of range of the network. Turn off power management. Other Problems The date/time is incorrect. Correct the date and time via the operating system or BIOS Setup program. After you have performed everything as described above and still have the incorrect date and time every time you turn on the computer, the RTC
(Real-Time Clock) battery is at the end of its life. Call an authorized dealer to replace the RTC battery. 88 Resetting the Computer You may have to reset (reboot) your computer on some occasions when an error occurs and the program you are using hangs up. If you are sure the operation has stopped and you cannot use the restart function of the operating system, reset the computer. Reset the computer by any one of these methods:
Press Ctrl+Alt+Del on the keyboard. This opens the Ctrl-Alt-Del screen where you can select actions including Restart. Press and hold the P1 button for more than 2 seconds. This opens the Ctrl-Alt-Del screen where you can select actions including Restart. If the above action does not work, press and hold the power button for more than 5 seconds to force the system to turn off. Then turn on the power again. 89 System Recovery Using Windows RE Windows 10 has a recovery environment (Windows RE) that provides recovery, repair, and troubleshooting tools. The tools are referred to as Advanced Startup Options. You can access these options by selecting security. There are several choices:
Settings Update &
System Restore This option allows you to restore Windows to an earlier point in time if you have created a restore point. Recover from a drive If you have created a recovery drive on Windows 10, you can use the recovery drive to reinstall Windows. Reset this PC This option allows you to reinstall Windows with or without keeping your files. See Microsoft website for more information. NOTE:
If you are in a situation where your computer wont boot into Windows, you can access the Advanced Startup Options by running the BIOS Setup Utility and selecting Advanced Windows RE. System recovery for Windows 10 typically will take several hours to complete. 90 Using Recovery Partition When necessary, you can restore your Windows 10 system to the factory default state by using the recovery partition feature. Recovery partition is a portion of your hard disk drive that is set aside by the manufacturer to hold the original image of your system. WARNING:
Using this feature will reinstall Windows to your system and configure it to the systems factory default settings. All data on the hard disk drive will be lost. Make sure that power is not interrupted during the recovery process. An unsuccessful recovery may result in Windows startup problems. To restore your system to the factory default state:
1. Connect the AC adapter. 2. Run BIOS Setup Utility. Select Advanced Recovery Partition. (See Chapter 5 for more information.) 3. Follow the onscreen instructions to complete the process. 91 92 Using the Driver Disc (Optional) NOTE: You can download the latest drivers and utilities from Getac website at http://www.getac.com Support. The Driver disc contains drivers and utilities required for specific hardware in your computer. Since your computer comes with drivers and utilities pre-installed, you normally do not need to use the Driver disc. In case you want to manually install Windows, you will have to install the drivers and utilities one by one after installing Windows. To manually install drivers and utilities:
1. Start up the computer. 2. Prepare an external CD/DVD drive (with USB connection). Connect the drive to your computer. Wait for the computer to recognize the drive. 3. Insert the Driver disc. Make sure you use the disc that matches the Windows version of your computer. 4. The autorun program should automatically start. You will see the installation menu. Click NEXT to go to the next page if there is more than one. 5. To install a driver or utility, just click the particular button and follow the onscreen instructions to complete the installation. 93 Appendix A Specifications NOTE: Specifications are subject to change without any prior notice. Parts Specifications CPU BIOS Kabylake Platform
- Intel Core i7-7500U Processor, 2.7GHz, up to 3.5GHz, 4M cache
- Intel Core i5-7200U Processor, 2.5GHz, up to 3.1GHz, 3M cache
- Option: Intel Core i5-7300U vPro Processor, 2.6GHz, up to 3.5GHz, 3M cache
- Option: Intel Core i7-7600U vPro Processor, 2.8GHz, up to 3.9GHz, 4M cache Insyde, Flash EEPROM, 16MB, supporting ACPI, TPM, vPro, NIST, Computrace, and HDD Security Erasure 4GB/8GB/16GB DDR4 2133MHz, SO-DIMM slot x 2 UMA - Intel HD Graphics 620 11.6-inch (16:9) TFT LCD, HD 1366x768, dimmer mode, blackout mode, sunlight readable, 800 Nits maximum brightness Capacitive multi-touch screen - 10 point Touchscreen Azalia, High Definition audio Audio Features Speaker 1.5W x 2 Microphone Integrated RAM Video Controller Display Panel Keyboard Standard keys with numeric pad keys, 12 function keys, special Fn
(Function) key and Windows keys, with water-proof membrane or backlight (option) 94 Parts Pointing device Hard disk drive Card slots I/O ports LAN Specifications Glide touchpad with multi-touch feature, capacitive type 128GB/256GB/512GB/1TB SSD (Solid-State Disk) ExpressCard/54 Smart Card USB 3.0 x 2, PowerShare USB 3.0, RS232, HDMI, combo audio
(4-pole TRRS 3.5mm type), RJ-45, Docking Intel i219-LM Gigabit Network Connection, 10/100/1000 Mbps Ethernet Wireless LAN + BT Intel 8265NGW 2x2 802.11 AC + BT combo, GPS (option) WWAN (option) Camera RFID Reader
(option) Security BT 4.2 class2+ EDR Internal UART Sierra EM7355/EM7305, 3G/4G LTE Front: FHD 2MP Rear (option): 8M pixel, autofocus, LED, video capture Contactless, combo NFC & RFID, supporting ISO14443A/B, MIFARE, ISO 15693, and ISO 18000-3 Kensington lock TPM 2.0 Fingerprint scanner (option) Power AC adapter Universal 65 W; input: 100240 V, 50/60 Hz; output: 19V Battery pack x 2 Lithium-ion Prismatic type, 3-cell Dimension (LxWD) 299 x 223 x 34mm (11.77 8.78 1.34 inch) Weight 1.98 kg (4.36 lb) 95 Appendix B Regulatory Information This appendix provides regulatory statements and safety notices on your computer. NOTE: Marking labels located on the exterior of your computer indicate the regulations that your model complies with. Please check the marking labels and refer to the corresponding statements in this appendix. Some notices apply to specific models only. 96 On the Use of the System Class B Regulations USA Federal Communications Commission Radio Frequency Interference Statement NOTE:
This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. Please note:
The use of a non-shielded interface cable with this equipment is prohibited. 97 Canada Canadian Department of Communications Radio Interference Regulations Class B Compliance Notice This Class B digital apparatus meets all requirements of the Canada Interference-Causing equipment regulations. Cet appareil numrique de Classe B respecte toutes les exigences du Rglement Canadien sur le matriel brouileur. This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications. Le prsent appareil numrique nmet pas de bruits radiolectriques dpassant les limites applicables aux appareils numriques de la classe B prescrites dans le Rglement sur le brouillage radiolectrique dict par le ministre des Communications du Canada. ANSI Warning Equipment approved for ANSI/ISA 12.12.01, Nonincendive Electrical Equipment for use in Class 1, Division 2, Group A, B, C, and D. Maximum ambient temperature: 40C WARNING: To prevent ignition of a hazardous atmosphere, batteries must only be changed or charged in an area known to be non-hazardous. EXPLOSION HARZARD WARNING: External connections/hubs through the connectors as mentioned (USB connector, Ethernet connector, phone connector, video port, serial port, power supply connector, microphone jack, headphones jack, and buttons/switches) and super multi DVD/combo drive are not to be used in a hazardous location. Power adapter shall not be used in hazardous locations. 98 Safety Notices About the Battery If the battery is mishandled, it may cause fire, smoke or an explosion and the batterys functionality will be seriously damaged. The safety instructions listed below must be followed. Danger Do not immerse the battery with liquid such as water, sea water or soda. Do not charge/discharge or place the battery in high-temperature (more than 80 C / 176 F) locations, such as near a fire, heater, in a car in direct sunlight, etc. Do not use unauthorized chargers. Do not force a reverse-charge or a reverse-connection. Do not connect the battery with AC plug (outlet) or car plugs. Do not adapt the battery to unspecified applications. Do not short circuit the battery. Do not drop or subject the battery to impacts. Do not penetrate with a nail or strike with a hammer. Do not directly solder the battery. Do not disassemble the battery. Warning Keep the battery away from infants. Stop using the battery if there are noticeable abnormalities such as abnormal smell, heat, deformities, or discoloration. Stop charging if the charging process cannot be finished. 99 In case of a leaking battery, keep the battery away from flames and do not touch it. Pack the battery tightly during transport. Caution Do not use the battery where static electricity (more than 100V) exists that might damage the protection circuit of the battery. When children are using the system, parents or adults must ensure that they are using the system and battery correctly. Keep the battery away from flammable materials during charging and discharging. In case lead wires or metal objects come out from the battery, you must seal and insulate them completely. Caution Texts Concerning Lithium Batteries DANISH ADVARSEL! Lithiumbatteri Eksplosionsfare ved fejlagtig hndtering. Udskiftning m kun ske med batteri af samme fabrikat og type. Levr det brugte batteri tilbage til leverandren. NORWEGIAN ADVARSEL: Eksplosjonsfare ved feilaktig skifte av batteri. Benytt samme batteritype eller en tilsvarende type anbefalt av apparatfabrikanten. Brukte batterier kasseres i henhold til fabrikantens instruksjoner. SWEDISH VARNING: Explosionsfara vid felaktigt batteribyte. Anvnd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren. Kassera anvnt batteri enligt fabrikantens instruktion. FINNISH VAROITUS: Paristo voi rjht, jos se on virheellisesti asennettu. Vaihda paristo ainoastaan valmistajan suosittelemaan tyyppiin. Hvit kytetty paristo valmistajan ohjeiden mukaisesti. 100 ENGLISH CAUTION: Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the equipment manufacturer. Discard used batteries according to manufacturers instructions. DEUTSCH VORSICHT: Explosionsgefahr bei unsachgemem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Hersteller empfohlenen gleich-wertigen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers. FRENCH ATTENTION: II y a danger dexplosion sil y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du mme type ou dun type quivalent recommand par le constructeur. Mettre au rebut les batteries usages conformment aux instructions du fabricant. Attention (for USA Users) The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste officials for details in your area for recycling options or proper disposal. About the AC Adapter Use only the AC adapter supplied with your computer. Use of another type of AC adapter will result in malfunction and/or danger. Do not use the adapter in a high moisture environment. Never touch the adapter when your hands or feet are wet. Allow adequate ventilation around the adapter when using it to operate the device or charge the battery. Do not cover the AC adapter with paper or other objects that will reduce cooling. Do not use the AC adapter while it is inside a carrying case. Connect the adapter to a proper power source. The voltage requirements are found on the product case and/or packaging. 101 Do not use the adapter if the cord becomes damaged. Do not attempt to service the unit. There are no serviceable parts inside. Replace the unit if it is damaged or exposed to excess moisture. 102 On the Use of the RF Device USA and Canada Safety Requirements and Notices IMPORTANT NOTE: To comply with FCC RF exposure compliance requirements, the antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Radio Frequency Interference Requirements and SAR This device meets the governments requirements for exposure to radio waves. This device is designed and manufactured not to exceed the emission limits for exposure to radio frequency (RF) energy set by the Federal Communications Commission of the U.S. Government. This device complies with FCC radiation exposure limits set forth for an uncontrolled environment. EMC Requirements This device uses, generates and radiates radio frequency energy. The radio frequency energy produced by this device is well below the maximum exposure allowed by the Federal Communications Commission (FCC). This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference.
(2) This device must accept any interference received, including interference that may cause undesired operation. The FCC limits are designed to provide reasonable protection against harmful interference when the equipment is installed and used in accordance with the instruction manual and operated in a commercial environment. However, there is no guarantee that interference will not occur in a particular commercial installation, or if operated in a residential area. 103 If harmful interference with radio or television reception occurs when the device is turned on, the user must correct the situation at the users own expense. The user is encouraged to try one or more of the following corrective measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. CAUTION: The Part 15 radio device operates on a non-interference basis with other devices operating at this frequency. Any changes or modification to said product not expressly approved by the manufacturer could void the users authority to operate this device. Canada Radio Frequency Interference Requirements To prevent radio interference to the licensed service, this device is intended to be operated indoors and away from windows to provide maximum shielding. Equipment
(or its transmit antenna) that is installed outdoors is subject to licensing. Pour empcher que cet appareil cause du brouillage au service faisant l'objet d'une licence, il doit tre utilis l'intrieur et devrait tre plac loin des fentres afin de fournir un cran de blindage maximal. Si le matriel (ou son antenne d'mission) est install l'extrieur, il doit faire l'objet d'une licence. 104 European Union CE Marking and Compliance Notices Statements of Compliance English This product follows the provisions of the European Directive 2014/53/EU. Danish Dette produkt er i overensstemmelse med det europ iske direktiv 2014/53/EU. Dutch Dit product is in navolging van de bepalingen van Europees Directief 2014/53/EU. Finnish Tm tuote noudattaa EU-direktiivin 2014/53/EU mryksi. French Ce produit est conforme aux exigences de la Directive Europenne 2014/53/EU. German Dieses Produkt entspricht den Bestimmungen der Europischen Richtlinie 2014/53/EU. Greek To 2014/53/EU. Icelandic essi vara stenst regluger Evrpska Efnahags Bandalagsins nmer 2014/53/EU. Italian Questo prodotto conforme alla Direttiva Europea 2014/53/EU. Norwegian Dette produktet er i henhold til bestemmelsene i det europeiske direktivet 2014/53/EU. Portuguese Este produto cumpre com as normas da Diretiva Europia 2014/53/EU. 105 Spanish Este producto cumple con las normas del Directivo Europeo 2014/53/EU. Swedish Denna produkt har tillverkats i enlighet med EG-direktiv 2014/53/EU. Notices The device is restricted to indoor use only when operating in the 5150 to 5350 MHz frequency range. AT EE IT PT BE FI LV RO BG FR LT SK HR DE LU SI CY EL MT ES CZ HU NL SE DK IE PL UK Waste Electrical and Electronic Equipment (WEEE) This symbol means that according to local laws and regulations your product and/or its battery shall be disposed of separately from household waste. When this product reaches its end of life, take it to a collection point designated by local authorities. Proper recycling of your product will protect human health and the environment. 106 User Notification of Take-back Service To Institutional (B2B) Users in United States:
Getac believes in providing our institutional customers with easy-to-use solutions to recycle your Getac-brand products for free. Getac understands the institutional customers will likely be recycling multiple items at once and as such. Getac wants to make the recycling process for these larger shipments as streamlined as possible. Getac works with recycling vendors with the highest standards for protecting our environment, ensuring worker safety, and complying with global environmental laws. Our commitment to recycling our old equipment grows out of our work to protect the environment in many ways. Please see the product type below for information on Getac product, battery and packaging recycling in USA. For Product Recycling:
Your portable Getac products contain hazardous materials. While they pose no risk to you during normal use, they should never be disposed with other wastes. Getac provides a free take-back service for recycling your Getac products. Our electronics recycler will provide competitive bids for recycling non-Getac products as well. For Battery Recycling:
The batteries used to power your portable Getac products contain hazardous materials. While they pose no risk to you during normal use, they should never be disposed with other wastes. Getac provides a free take-back service for recycling your batteries from Getac products. For Packaging Recycling:
Getac has chosen the packaging materials used to transport our products carefully, to balance the requirements of shipping the product to you safely while minimizing the amount of material used. The materials used in our packaging are designed to be recycled locally. If you have the above for recycling, please contact our recycler, All Green Electronics Recycling, LLC. For more information on recycling, visit the website http://www.allgreenrecycling.com. 107 ENERGY STAR 6.1 ENERGY STAR is a government program that offers businesses and consumers energy-efficient solutions, making it easy to save money while protecting the environment for future generations. Please reference ENERGY STAR related information from http://www.energystar.gov. As an ENERGY STAR Partner, Getac Technology Corporation has determined that this product meets the ENERGY STAR guidelines for energy efficiency. An ENERGY STAR qualified computer uses 70 % less electricity than computers without enabled power management features. Earning the ENERGY STAR When every home office is powered by equipment that has earned the ENERGY STAR, the change will keep over 289 billion pounds of greenhouse gases out of the air. If left inactive, ENERGY STAR qualified computers enter a low-power mode and may use 15 watts or less. New chip technologies make power management features more reliable, dependable, and user-friendly than even just a few years ago. Spending a large portion of time in low-power mode not only saves energy, but helps equipment run cooler and last longer. 108 Businesses that use ENERGY STAR enabled office equipment may realize additional savings on air conditioning and maintenance. Over its lifetime, ENERGY STAR qualified equipment in a single home office
(e.g., computer, monitor, printer, and fax) can save enough electricity to light an entire home for more than 4 years. Power management (sleep settings) on computers and monitors can result in much savings annually. Remember, saving energy prevents pollution Because most computer equipment is left on 24 hours a day, power management features are important for saving energy and are an easy way to reduce air pollution. By using less energy, these products help lower consumers utility bills, and prevent greenhouse gas emissions. Getac Product Compliance All Getac products with ENERGY STAR logo comply with the ENERGY STAR standard, and the power management feature is enabled by default. As recommended by the ENERGY STAR program for optimal energy savings, the computer is automatically set to sleep after 15 minutes (in battery mode) and 30 minutes (in AC mode) of user inactivity. To wake up the computer, press the power button. If you want to configure power management settings such as inactivity time and ways to initiate/end Sleep mode, go to Power Options by right-clicking the battery icon on the Windows taskbar and then selecting Power Options in the pop-up menu. Please visit http://www.energystar.gov/powermanagement for detail information on power management and its benefits to the environment. 109 Battery Recycling For the U.S. and Canada only:
To recycle the battery, please go to the RBRC Call2Recycle website or use the Call2Recycle Helpline at 800-822-8837. Call2Recycle is a product stewardship program providing no-cost battery and cellphone recycling solutions across the U.S. and Canada. Operated by Call2Recycle, Inc., a 501(c)4 nonprofit public service organization, the program is funded by battery and product manufacturers committed to responsible recycling. See more at:
http://www.call2recycle.org 110
1 | User Manual Module | Users Manual | 2.95 MiB |
PIC32MX1XX/2XX 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog Operating Conditions 2.3V to 3.6V, -40C to +105C, DC to 40 MHz Core: 40 MHz MIPS32 M4K MIPS16e mode for up to 40% smaller code size 1.56 DMIPS/MHz (Dhrystone 2.1) performance Code-efficient (C and Assembly) architecture Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Clock Management 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Fast wake-up and start-up Power Management Low-power management modes (Sleep, Idle) 0.5 mA/MHz dynamic current (typical) 20 A IPD current (typical) Audio Interface Features Data communication: I2S, LJ, RJ, DSP modes Control interface: SPI and I2C Master clock:
Integrated Power-on Reset and Brown-out Reset Independent Watchdog Timer
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time Advanced Analog Features ADC Module:
- 10-bit 1.1 Msps rate with one S&H
- Up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices Flexible and independent ADC trigger sources Charge Time Measurement Unit (CTMU):
- Supports mTouch capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement capability Comparators:
- Up to three Analog Comparator modules
- Programmable references with 32 voltage points Timers/Output Compare/Input Capture Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters Five Output Compare (OC) modules Five Input Capture (IC) modules Peripheral Pin Select (PPS) to allow function remap Real-Time Clock and Calendar (RTCC) module Communication Interfaces USB 2.0-compliant Full-speed OTG controller Two UART modules (10 Mbps)
- Supports LIN 2.0 protocols and IrDA support Two 4-wire SPI modules (20 Mbps) Two I2C modules (up to 1 Mbaud) with SMBus support Peripheral Pin Select (PPS) to allow function remap Parallel Master Port (PMP) Direct Memory Access (DMA) Four channels of hardware DMA with automatic data size detection Two additional channels dedicated for USB Programmable Cyclic Redundancy Check (CRC) Input/Output 15 mA source/sink on all I/O pins 5V-tolerant pins Selectable open drain, pull-ups, and pull-downs External interrupts on all I/O pins Qualification and Class B Support AEC-Q100 REVG (Grade 2 -40C to +105C) planned Class B Safety Library, IEC 60730 Debugger Development Support In-circuit and in-application programming 4-wire MIPS Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Type Pin Count I/O Pins (up to) Contact/Lead Pitch SOIC 28 21 1.27 SSOP 28 21 0.65 SPDIP 28 21 0.100''
QFN VTLA 28 21 0.65 44 34 0.65 36 25 0.50 44 34 0.50 TQFP 44 34 0.80 Dimensions 17.90x7.50x2.65 10.2x5.3x2 1.365x.285x.135''
6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1 Note: All dimensions are in millimeters (mm) unless specified. 2011 Microchip Technology Inc. Preliminary DS61168C-page 1 PIC32MX1XX/2XX TABLE 1:
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) 2
(
s r e m T i PIC32MX110F016B 28 16+3 PIC32MX110F016C 36 16+3 PIC32MX110F016D 44 16+3 PIC32MX120F032B 28 32+3 PIC32MX120F032C 36 32+3 PIC32MX120F032D 44 32+3 4 4 4 8 8 8 20 5/5/5 24 5/5/5 32 5/5/5 20 5/5/5 24 5/5/5 32 5/5/5 PIC32MX130F064B 28 64+3 16 20 5/5/5 PIC32MX130F064C 36 64+3 16 24 5/5/5 PIC32MX130F064D 44 64+3 16 32 5/5/5 PIC32MX150F128B 28 128+3 32 20 5/5/5 PIC32MX150F128C 36 128+3 32 24 5/5/5 PIC32MX150F128D 44 128+3 32 32 5/5/5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Note 1:
2:
3:
This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. s r o t a r a p m o C g o a n A l 3 3 3 3 3 3 3 3 3 3 3 3
) G T O
(
o G
-
e h T
-
n O B S U N N N N N N N N N N N N C 2 I P M P 2 2 2 2 2 2 2 2 2 2 2 2 Y Y Y Y Y Y Y Y Y Y Y Y
) 3
(
s t p u r r e t n I l a n r e t x E 5 5 5 5 5 5 5 5 5 5 5 5 i
/
l
) d e t a c d e D e b a m m a r g o r P l s e n n a h C A M D
(
4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 l
) s e n n a h C
(
U M T C Y Y Y Y Y Y Y Y Y Y Y Y C D A s p s M 1 t i b
-
0 1 10 12 13 10 12 13 10 12 13 10 12 13 C C T R Y Y Y Y Y Y Y Y Y Y Y Y i s n P O
/
I 21 25 34 21 25 34 21 25 34 21 25 34 G A T J s e g a k c a P Y Y Y Y Y Y Y Y Y Y Y Y SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN DS61168C-page 2 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 2:
PIC32MX2XX USB FAMILY FEATURES Remappable Peripherals e c i v e D s n P i
) 1
(
) B K
(
y r o m e M m a r g o r P
) B K
(
y r o m e M a t a D i l s n P e b a p p a m e R T R A U S 2 I
/
I P S
) 3
(
s t p u r r e t n I l a n r e t x E s r o t a r a p m o C g o a n A l
) G T O
(
o G
-
e h T
-
n O B S U C 2 I P M P e r a p m o C e r u t p a C
/
/
) 2
(
s r e m T i s l e n n a h C A M D i
/
l
) d e t a c d e D e b a m m a r g o r P
(
PIC32MX210F016B 28 16+3 PIC32MX210F016C 36 16+3 PIC32MX210F016D 44 16+3 PIC32MX220F032B 28 32+3 PIC32MX220F032C 36 32+3 PIC32MX220F032D 44 32+3 4 4 4 8 8 8 19 5/5/5 23 5/5/5 31 5/5/5 19 5/5/5 23 5/5/5 31 5/5/5 PIC32MX230F064B 28 64+3 16 19 5/5/5 PIC32MX230F064C 36 64+3 16 PIC32MX230F064D 44 64+3 16 23 31 5/5/5 5/5/5 PIC32MX250F128B 28 128+3 32 19 5/5/5 PIC32MX250F128C 36 128+3 32 PIC32MX250F128D 44 128+3 32 23 31 5/5/5 5/5/5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 5 5 5 5 5 5 5 5 5 5 5 3 3 3 3 3 3 3 3 3 3 3 3 Y Y Y Y Y Y Y Y Y Y Y Y 2 2 2 2 2 2 2 2 2 2 2 2 Y Y Y Y Y Y Y Y Y Y Y Y 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 Note 1:
2:
3:
This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. l
) s e n n a h C
(
C D A s p s M 1 t i b
-
0 1 9 12 13 9 12 13 9 12 13 9 12 13 U M T C Y Y Y Y Y Y Y Y Y Y Y Y C C T R Y Y Y Y Y Y Y Y Y Y Y Y i s n P O
/
I 19 23 33 19 23 33 19 23 33 19 23 33 G A T J s e g a k c a P Y Y Y Y Y Y Y Y Y Y Y Y SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN 2011 Microchip Technology Inc. Preliminary DS61168C-page 3 PIC32MX1XX/2XX Pin Diagrams 28-Pin SOIC, SPDIP, SSOP(1,2) MCLR MCLR MCLR MCLR VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 VSS VSS VSS VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD VDD VDD VDD PGED3/RPB5/PMD7/RB5 MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD TMS/RPB5/USBID/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
= Pins are up to 5V tolerant AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN11/RPB13/CTPLS/PMRD/RB13 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VCAP VSS VSS VSS VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AN11/RPB13/CTPLS/PMRD/RB13 VUSB PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 VBUS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I I I I P C 3 2 M X 1 5 0 F 1 2 8 B P C 3 2 M X 1 3 0 F 0 6 4 B P C 3 2 M X 1 2 0 F 0 1 6 B P C 3 2 M X 1 2 0 F 0 3 2 B I I I I P C 3 2 M X 2 5 0 F 1 2 8 B P C 3 2 M X 2 3 0 F 0 6 4 B P C 3 2 M X 2 2 0 F 0 1 6 B P C 3 2 M X 2 2 0 F 0 3 2 B Note 1:
2:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. DS61168C-page 4 Preliminary 2011 Microchip Technology Inc. Pin Diagrams (Continued) 28-Pin QFN(1,2,3) PIC32MX1XX/2XX
= Pins are up to 5V tolerant
/
/
/
/
4 1 B R R W M P 5 D E T C 1 K C S 4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
I
/
/
/
/
5 1 B R 1 S C M P 6 D E T C 2 K C S 5 1 B P R A N I 3 C
/
9 N A
/
/
R L C M D D V A S S V A
/
/
/
I 0 A R 1 D E T C 0 A P R C N 3 C 0 N A
+
F E R V C
+
F E R V
/
/
/
/
1 A R 2 D E T C 1 A P R 1 N A
/
/
/
-
F E R V C
/
-
F E R V PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 1 2 3 4 5 6 7 8 2 7 2 6 2 5 2 4 2 3 2 2 2 PIC32MX120F032B PIC32MX120F016B PIC32MX130F064B PIC32MX150F128B 0 8 9 1 1 1 2 1 3 1 4 1 21 20 19 18 17 16 15 AN11/RPB13/CTPLS/PMRD/RB13 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 4 B R
/
4 B P R
/
I C S O S D D V 5 B R
/
7 D M P
/
5 B P R
/
3 D E G P 6 B R
/
6 D M P
/
6 B P R
/
3 C E G P 7 B R
/
0 T N I
/
5 D M P
/
3 D E T C
/
7 B P R
/
I D T 8 B R
/
4 D M P
/
0 1 D E T C
/
1 L C S
/
8 B P R K C T
/
/
4 A R
/
1 A M P
/
9 D E T C K C 1 T
/
4 A P R O C S O S
/
Note 1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2011 Microchip Technology Inc. Preliminary DS61168C-page 5 PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3)
= Pins are up to 5V tolerant
/
/
/
/
I 0 A R 7 D M P 1 D E T C 0 A P R C N 3 C 0 N A
+
F E R V C
+
F E R V
/
3 D E G P
/
/
/
/
/
/
4 1 B R 5 D E T C 1 K C S N O S U B V 4 1 B P R B N I 3 C
/
0 1 N A
/
F E R V C
/
/
/
/
/
5 1 B R 1 S C M P 6 D E T C 2 K C S
/
5 1 B P R A N I 3 C
/
9 N A
/
R L C M D D V A S S V A
/
/
1 A R 6 D M P 2 D E T C 1 A P R 1 N A
/
/
/
-
F E R V C
/
-
F E R V
/
3 C E G P PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 1 2 3 4 5 6 7 8 2 7 2 6 2 5 2 4 2 3 2 2 2 PIC32MX220F032B PIC32MX220F016B PIC32MX230F064B PIC32MX250F128B 0 8 9 1 1 1 2 1 3 1 4 1 21 20 19 18 17 16 15 AN11/RPB13/CTPLS/PMRD/RB13 VUSB PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 4 B R
/
4 B P R
/
I C S O S D D V
/
I 5 B R D B S U
/
5 B P R S M T
/
S U B V 7 B R
/
0 T N I
/
5 D M P
/
3 D E T C 7 B P R
/
/
I D T 8 B R
/
4 D M P
/
0 1 D E T C
/
1 L C S 8 B P R K C T
/
/
/
4 A R
/
1 A M P
/
9 D E T C K C 1 T 4 A P R O C S O S
/
/
Note 1:
2:
3:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61168C-page 6 Preliminary 2011 Microchip Technology Inc. Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) PIC32MX1XX/2XX
= Pins are up to 5V tolerant
/
/
/
I 0 A R 1 D E T C 0 A P R C N 3 C 0 N A
+
F E R V C
+
F E R V
/
/
/
/
1 A R 2 D E T C 1 A P R 1 N A
/
/
/
-
F E R V C
/
-
F E R V
/
/
/
5 1 B R 1 S C M P 6 D E T C 2 K C S 5 1 B P R A N 3 C
/
9 N A I
/
/
R L C M D D V A S S V A
/
/
/
/
4 1 B R R W M P 5 D E T C 1 K C S 4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
I
/
/
/
3 1 B R D R M P S L P T C 3 1 B P R
/
1 1 N A
/
/
/
I
/
I 0 B R 0 B P R D N 3 C B N 2 C D N 1 C 2 N A 1 D E G P
/
/
I
/
/
/
/
1 B R 2 1 D E T C 1 B P R A N 2 C C N 1 C 3 N A 1 C E G P
/
/
I
/
I 36 35 34 33 32 31 30 29 28 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 PGED(4)/AN6/RPC0/RC0 PGEC(4)/AN7/RPC1/RC1 VDD VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 1 2 3 4 5 6 7 8 9 PIC32MX120F032C PIC32MX120F016C PIC32MX130F064C PIC32MX150F128C 10 11 12 13 14 15 16 17 27 26 25 24 23 22 21 20 19 18 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VDD VCAP VSS RPC9/CTED7/RC9 TDO/RPB9/SDA1/CTED4/PMD3/RB9 S S V D D V D D V 3 C R
/
3 C P R 5 B R
/
7 D M P
/
5 B P R
/
3 D E G P 6 B R
/
6 D M P
/
6 B P R
/
3 C E G P 7 B R
/
0 T N I
/
5 D M P
/
3 D E T C 7 B P R
/
/
I D T 8 B R
/
4 D M P
/
0 1 D E T C
/
1 L C S 8 B P R K C T
/
/
/
4 A R
/
1 A M P
/
9 D E T C K C 1 T 4 A P R O C S O S
/
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064C and PIC32MX150F128C devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 7 PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
/
/
/
/
I 0 A R 7 D M P 1 D E T C 0 A P R C N 3 C 0 N A
+
F E R V C
+
F E R V
/
3 D E G P
/
/
/
/
/
1 A R 6 D M P 2 D E T C 1 A P R 1 N A
/
/
/
-
F E R V C
/
-
F E R V
/
3 C E G P
/
/
/
4 1 B R 5 D E T C 1 K C S N O S U B V 4 1 B P R B N 3 C 0 1 N A
/
F E R V C I
/
/
/
/
/
3 1 B R D R M P S L P T C
/
3 1 B P R
/
1 1 N A
/
/
/
5 1 B R 1 S C M P 6 D E T C 2 K C S 5 1 B P R A N I 3 C
/
9 N A
/
/
R L C M D D V A S S V A
/
/
/
I
/
0 B R 0 D M P 0 B P R D N 3 C B N 2 C D N 1 C
/
2 N A
/
1 D E G P I
/
I
/
/
/
/
1 B R 1 D M P 2 1 D E T C 1 B P R A N 2 C C N 1 C 3 N A
/
1 C E G P I
/
I
/
36 35 34 33 32 31 30 29 28 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 PGED4(4)/AN6/RPC0/RC0 PGEC4(4)/AN7/RPC1/RC1 VDD VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 1 2 3 4 5 6 7 8 9 PIC32MX220F032C PIC32MX220F016C PIC32MX230F064C PIC32MX250F128C 10 11 12 13 14 15 16 17 27 26 25 24 23 22 21 20 19 18 VUSB PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VDD VCAP VSS RPC9/CTED7/RC9 TDO/RPB9/SDA1/CTED4/PMD3/RB9 S S V D D V D D V 3 C R
/
3 C P R
/
2 1 N A
/
I 5 B R D B S U
/
5 B P R S M T
/
S U B V 7 B R
/
0 T N
/
I
/
5 D M P 3 D E T C 7 B P R
/
/
I D T 8 B R
/
4 D M P
/
0 1 D E T C 1 L C S 8 B P R K C T
/
/
/
/
4 A R
/
1 A M P
/
9 D E T C K C 1 T 4 A P R O C S O S
/
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064C and PIC32MX250F128C devices only. DS61168C-page 8 Preliminary 2011 Microchip Technology Inc. Pin Diagrams (Continued) 44-Pin QFN(1,2,3) PIC32MX1XX/2XX
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
/
/
6 B R 6 D M P 6 B P R 3 C E G P
/
/
/
5 B R 7 D M P 5 B P R 3 D E G P
/
/
5 C R 3 A M P 5 C P R
/
D D V S S V
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R
/
9 A R 9 A M P 9 A P R
/
/
I D T
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 PIC32MX120F032D PIC32MX120F016D PIC32MX130F064D PIC32MX150F128D 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 33 32 31 30 29 28 27 26 25 24 23 SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 5 1 B R
/
1 S C M P
/
6 D E T C
/
2 K C S
/
5 1 B P R A N 3 C 9 N A
/
I
/
S S V A D D V A R L C M 1 A R
/
2 D E T C
/
1 A P R
/
1 N A
/
-
F E R V C
/
-
F E R V
/
0 A R
/
1 D E T C
/
0 A P R C N I 3 C
/
0 N A
+
F E R V C
+
F E R V
/
/
/
/
0 B R
/
0 B P R D N I 3 C B N I 2 C D N I 1 C
/
2 N A 1 D E G P
/
/
/
1 B R
/
2 1 D E T C
/
1 B P R A N I 2 C C N I 1 C 3 N A 1 C E G P
/
/
/
0 1 A R
/
0 1 A M P S M T
/
/
) 4
(
4 D E G P 7 A R
/
7 A M P
/
8 D E T C K C T
/
/
) 4
(
C E G P
/
4 1 B R R W M P
/
5 D E T C
/
1 K C S
/
4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
I
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 9 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3)
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
S U B V
/
I 5 B R D B S U 5 B P R
/
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
/
5 C R 3 A M P 5 C P R
/
D D V S S V
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R 2 1 N A
/
/
9 A R 9 A M P 9 A P R
/
/
I D T RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 PIC32MX220F032D PIC32MX220F016D PIC32MX230F064D PIC32MX250F128D 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 33 32 31 30 29 28 27 26 25 24 23 SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 0 1 A R
/
0 1 A M P S M T
/
/
) 4
(
D E G P 7 A R
/
7 A M P
/
8 D E T C K C T
/
/
) 4
(
C E G P
/
4 1 B R
/
5 D E T C
/
1 K C S N O S U B V
/
4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
/
I S S V A D D V A R L C M 5 1 B R
/
1 S C M P
/
6 D E T C
/
2 K C S
/
5 1 B P R A N I 3 C 9 N A
/
/
1 A R
/
6 D M P
/
2 D E T C
/
1 A P R
/
1 N A
/
-
F E R V C
/
/
-
F E R V 3 C E G P
/
/
0 B R
/
0 D M P
/
0 B P R D N I 3 C B N I 2 C D N I 1 C
/
2 N A 1 D E G P
/
/
/
0 A R
/
7 D M P
/
1 D E T C
/
0 A P R C N I 3 C
/
0 N A
+
F E R V C
+
F E R V 3 D E G P
/
/
/
/
1 B R
/
1 D M P
/
2 1 D E T C
/
1 B P R A N I 2 C C N I 1 C 3 N A 1 C E G P
/
/
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. DS61168C-page 10 Preliminary 2011 Microchip Technology Inc. Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) PIC32MX1XX/2XX
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
/
/
6 B R 6 D M P 6 B P R 3 C E G P
/
/
/
5 B R 7 D M P 5 B P R 3 D E G P
/
/
5 C R 3 A M P 5 C P R
/
D D V S S V
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R
/
9 A R 9 A M P 9 A P R
/
/
I D T
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 PIC32MX120F032D PIC32MX120F016D PIC32MX130F064D PIC32MX150F128D 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 33 32 31 30 29 28 27 26 25 24 23 SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 0 1 A R
/
0 1 A M P S M T
/
/
) 4
(
D E G P 7 A R
/
7 A M P
/
8 D E T C K C T
/
/
) 4
(
C E G P 5 1 B R
/
1 S C M P
/
6 D E T C
/
2 K C S
/
5 1 B P R A N 3 C 9 N A
/
I
/
S S V A D D V A R L C M
/
/
0 B R
/
0 B P R D N I 3 C B N I 2 C D N I 1 C
/
2 N A 1 D E G P
/
/
1 A R
/
2 D E T C
/
1 A P R
/
1 N A
/
-
F E R V C
/
-
F E R V
/
0 A R
/
1 D E T C
/
0 A P R C N I 3 C
/
0 N A
+
F E R V C
+
F E R V
/
/
/
1 B R
/
2 1 D E T C
/
1 B P R A N I 2 C C N I 1 C 3 N A 1 C E G P
/
/
/
/
4 1 B R R W M P
/
5 D E T C
/
1 K C S
/
4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
I
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 11 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
/
/
6 B R 6 D M P 6 B P R 3 C E G P
/
/
/
5 B R 7 D M P 5 B P R 3 D E G P
/
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
/
5 C R 3 A M P 5 C P R
/
D D V S S V
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R
/
9 A R 9 A M P 9 A P R
/
/
I D T 44 43 42 41 40 39 38 37 36 35 34 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 1 2 3 4 5 6 7 8 9 10 11 PIC32MX120F032D PIC32MX120F016D PIC32MX130F064D PIC32MX150F128D 12 13 14 15 16 17 18 19 20 21
/
4 B R 4 B P R
/
I C S O S 33 32 31 30 29 28 27 26 25 24 23 22 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 5 1 B R
/
1 S C M P
/
6 D E T C
/
2 K C S
/
5 1 B P R A N 3 C 9 N A
/
I
/
S S V A D D V A R L C M 1 A R
/
2 D E T C
/
1 A P R
/
1 N A
/
-
F E R V C
/
-
F E R V
/
0 A R
/
1 D E T C
/
0 A P R C N I 3 C
/
0 N A
+
F E R V C
+
F E R V
/
/
/
/
0 B R
/
0 B P R D N I 3 C B N I 2 C D N I 1 C 2 N A 1 D E G P
/
/
/
/
1 B R
/
2 1 D E T C
/
1 B P R A N I 2 C C N 1 C 3 N A 1 C E G P
/
/
/
I
/
/
3 1 B R D R M P S L P T C
/
3 1 B P R
/
1 1 N A 0 1 A R
/
0 1 A M P S M T
/
/
) 4
(
D E G P 7 A R
/
7 A M P
/
8 D E T C K C T
/
/
) 4
(
C E G P
/
4 1 B R R W M P
/
5 D E T C
/
1 K C S
/
4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
I
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. DS61168C-page 12 Preliminary 2011 Microchip Technology Inc. Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) PIC32MX1XX/2XX
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
S U B V
/
I 5 B R D B S U 5 B P R
/
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
/
5 C R 3 A M P 5 C P R
/
D D V S S V
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R 2 1 N A
/
/
9 A R 9 A M P 9 A P R
/
/
I D T RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 PIC32MX220F032D PIC32MX220F016D PIC32MX230F064D PIC32MX250F128D 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 33 32 31 30 29 28 27 26 25 24 23 SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 0 1 A R
/
0 1 A M P S M T
/
/
) 4
(
D E G P 7 A R
/
7 A M P
/
8 D E T C K C T
/
/
) 4
(
C E G P
/
4 1 B R
/
5 D E T C
/
1 K C S N O S U B V
/
4 1 B P R B N 3 C 0 1 N A
/
F E R V C
/
/
I S S V A D D V A R L C M 5 1 B R
/
1 S C M P
/
6 D E T C
/
2 K C S
/
5 1 B P R A N I 3 C 9 N A
/
/
1 A R
/
6 D M P
/
2 D E T C
/
1 A P R
/
1 N A
/
-
F E R V C
/
/
-
F E R V 3 C E G P
/
/
0 B R
/
0 D M P
/
0 B P R D N I 3 C B N I 2 C D N I 1 C
/
2 N A 1 D E G P
/
/
/
0 A R
/
7 D M P
/
1 D E T C
/
0 A P R C N I 3 C
/
0 N A
+
F E R V C
+
F E R V 3 D E G P
/
/
/
/
1 B R
/
1 D M P
/
2 1 D E T C
/
1 B P R A N I 2 C C N I 1 C 3 N A 1 C E G P
/
/
/
Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 13 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3)
= Pins are up to 5V tolerant
/
/
8 B R 4 D M P 0 1 D E T C 1 L C S 8 B P R
/
/
7 B R 0 T N
/
I
/
/
5 D M P 3 D E T C 7 B P R
/
/
/
4 A R 9 D E T C K C 1 T 4 A P R O C S O S
/
/
/
4 B R 4 B P R
/
I C S O S
/
9 A R 9 A M P 9 A P R
/
/
I D T
/
I 5 B R D B S U 5 B P R
/
S U B V D D V S S V
/
5 C R 3 A M P 5 C P R
/
/
4 C R 4 A M P 4 C P R
/
/
3 C R 3 C P R 2 1 N A
/
44 43 42 41 40 39 38 37 36 35 34 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB 1 2 3 4 5 6 7 8 9 10 11 PIC32MX220F032D PIC32MX220F016D PIC32MX230F064D PIC32MX250F128D 12 13 14 15 16 17 18 19 20 21 33 32 31 30 29 28 27 26 25 24 23 22 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2
/
0 1 A R 0 1 A M P S M T
/
/
) 4
(
D E G P
/
/
3 1 B R D R M P S L P T C 3 1 B P R 1 1 N A
/
/
/
/
7 A R 7 A M P 8 D E T C K C T
/
/
) 4
(
C E G P S S V A D D V A R L C M
/
/
/
5 1 B R 1 S C M P 6 D E T C 2 K C S 5 1 B P R A N 3 C
/
9 N A I
/
/
/
/
/
4 1 B R 5 D E T C 1 K C S N O S U B V 4 1 B P R B N I 3 C
/
0 1 N A
/
F E R V C
/
/
/
/
/
/
I 0 A R 7 D M P 1 D E T C 0 A P R C N 3 C 0 N A
+
F E R V C
+
F E R V
/
3 D E G P
/
/
/
/
/
1 A R 6 D M P 2 D E T C 1 A P R 1 N A
/
/
/
-
F E R V C
/
-
F E R V
/
3 C E G P
/
/
/
I
/
0 B R 0 D M P 0 B P R D N 3 C B N 2 C D N 1 C 2 N A
/
1 D E G P
/
I
/
I
/
/
/
/
1 B R 1 D M P 2 1 D E T C 1 B P R A N 2 C C N 1 C
/
3 N A
/
1 C E G P I
/
I Note 1:
2:
3:
4:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 Peripheral Pin Select for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 I/O Ports for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. DS61168C-page 14 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 19 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 27 3.0 CPU............................................................................................................................................................................................ 33 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Flash Program Memory.............................................................................................................................................................. 79 6.0 Resets ........................................................................................................................................................................................ 83 7.0 Interrupt Controller ..................................................................................................................................................................... 87 8.0 Oscillator Configuration.............................................................................................................................................................. 95 9.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 105 10.0 USB On-The-Go (OTG)............................................................................................................................................................ 121 11.0 I/O Ports ................................................................................................................................................................................... 143 12.0 Timer1 ...................................................................................................................................................................................... 151 13.0 Timer2/3, Timer4/5................................................................................................................................................................... 155 14.0 Input Capture............................................................................................................................................................................ 159 15.0 Output Compare....................................................................................................................................................................... 163 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 165 17.0 Inter-Integrated Circuit (I2C).............................................................................................................................................. 173 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 179 19.0 Parallel Master Port (PMP)....................................................................................................................................................... 185 20.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 193 21.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 203 22.0 Comparator .............................................................................................................................................................................. 211 23.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 215 24.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 217 25.0 Power-Saving Features ........................................................................................................................................................... 221 26.0 Special Features ...................................................................................................................................................................... 225 27.0 Instruction Set .......................................................................................................................................................................... 239 28.0 Development Support............................................................................................................................................................... 241 29.0 Electrical Characteristics.......................................................................................................................................................... 245 30.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 285 31.0 Packaging Information.............................................................................................................................................................. 289 The Microchip Web Site..................................................................................................................................................................... 315 Customer Change Notification Service .............................................................................................................................................. 315 Customer Support.............................................................................................................................................................................. 315 Reader Response .............................................................................................................................................................................. 316 Product Identification System ............................................................................................................................................................ 317 2011 Microchip Technology Inc. Preliminary DS61168C-page 15 PIC32MX1XX/2XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS61168C-page 16 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Referenced Sources This device data sheet is based on the following individual chapters of the PIC32 Family Reference Manual. These documents should be considered as the general reference for the operation of a particular module or device feature. Note:
To access the documents listed below, browse to the documentation section of the site
(www.microchip.com). Microchip web Section 1. Introduction (DS61127) Section 2. CPU (DS61113) Section 3. Memory Organization (DS61115) Section 5. Flash Program Memory (DS61121) Section 6. Oscillator Configuration (DS61112) Section 7. Resets (DS61118) Section 8. Interrupt Controller (DS61108) Section 9. Watchdog Timer and Power-up Timer (DS61114) Section 10. Power-Saving Features (DS61130) Section 12. I/O Ports (DS61120) Section 13. Parallel Master Port (PMP) (DS61128) Section 14. Timers (DS61105) Section 15. Input Capture (DS61122) Section 16. Output Compare (DS61111) Section 17. 10-bit Analog-to-Digital Converter (ADC) (DS61104) Section 19. Comparator (DS61110) Section 20. Comparator Voltage Reference (CVREF) (DS61109) Section 21. Universal Asynchronous Receiver Transmitter (UART) (DS61107) Section 23. Serial Peripheral Interface (SPI) (DS61106) Section 24. Inter-Integrated Circuit (I2C) (DS61116) Section 27. USB On-The-Go (OTG) (DS61126) Section 29. Real-Time Clock and Calendar (RTCC) (DS61125) Section 31. Direct Memory Access (DMA) Controller (DS61117) Section 32. Configuration (DS61124) Section 33. Programming and Diagnostics (DS61129) Section 37. Charge Time Measurement Unit (CTMU) (DS61167) 2011 Microchip Technology Inc. Preliminary DS61168C-page 17 PIC32MX1XX/2XX NOTES:
DS61168C-page 18 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX This document contains device-specific information for PIC32MX1XX/2XX devices. Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX1XX/2XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 1.0 DEVICE OVERVIEW the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. FIGURE 1-1:
BLOCK DIAGRAM(1) PORTA PORTB PORTC Remappable Pins OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators PLL Dividers PLL-USB Timing Generation VCAP Voltage Regulator Precision Band Gap Reference USBCLK SYSCLK PBCLK Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Peripheral Bus Clocked by SYSCLK K L C B P y b d e k c o C s u B l l a r e h p i r e P JTAG BSCAN Priority Interrupt Controller EJTAG INT MIPS32 M4K CPU Core IS 32 DS 32 32 B S U C A M D D C I 32 32 32 32 Bus Matrix 32 128 32 32 Data RAM Peripheral Bridge r e h s a F l l l o r t n o C 128-bit Wide Program Flash Memory VDD, VSS MCLR CTMU Timer1-5 PWM OC1-5 IC1-5 SPI1-2 I2C1-2 PMP 10-bit ADC UART1-2 RTCC Comparators 1-3 Note 1: Some features are not available on all device variants. 2011 Microchip Technology Inc. Preliminary DS61168C-page 19 PIC32MX1XX/2XX TABLE 1-1:
PINOUT I/O DESCRIPTIONS Pin Name 28-pin QFN Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 36-pin VTLA Pin Type Buffer Type 44-pin QFN Description Analog Analog input channels. Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when ST/CMOS 32.768 kHz low-power oscillator crystal configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. Reference Input Clock Reference Output Clock Capture Inputs 1-5 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 CLKI CLKO OSC1 OSC2 SOSCI SOSCO 27 28 1 2 3 4 23 22 21 20(2) 6 7 6 7 8 9 2 3 4 5 6 7 26 25 24 23(2) 9 10 9 10 11 12 33 34 35 36 1 2 3 4 29 28 27 26(2) 11(3) 7 8 7 8 9 10 19 20 21 22 23 24 25 26 27 15 14 11 10(2) 36(3) 30 31 30 31 33 34 PPS REFCLKI PPS REFCLKO PPS IC1 PPS IC2 PPS IC3 PPS IC4 IC5 PPS Legend: CMOS = CMOS compatible input or output PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer I I I I I I I I I I I I I I O I I O I O I I I I I I/O ST ST ST ST ST ST Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168C-page 20 Preliminary 2011 Microchip Technology Inc. TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) PIC32MX1XX/2XX Pin Type Buffer Type 44-pin QFN Description 36-pin VTLA Pin Name 28-pin QFN Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC PPS PPS PPS PPS PPS PPS PPS 16 PPS PPS PPS PPS OC1 OC2 OC3 OC4 OC5 OCFA OCFB INT0 INT1 INT2 INT3 INT4 RA0 RA1 RA2 RA3 RA4 RA7 RA8 RA9 RA10 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 Legend: CMOS = CMOS compatible input or output PPS PPS PPS PPS PPS PPS PPS 13 PPS PPS PPS PPS 27 28 6 7 9 1 2 3 4 8 11 12(2) 13 14 15 18 19 20(2) 21 22 23 PPS PPS PPS PPS PPS PPS PPS 17 PPS PPS PPS PPS 33 34 7 8 10 35 36 1 2 9 15 16(2) 17 18 19 24 25 26(2) 27 28 29 PPS PPS PPS PPS PPS PPS PPS 43 PPS PPS PPS PPS 19 20 30 31 34 13 32 35 12 21 22 23 24 33 41 42(2) 43 44 1 8 9 10(2) 11 14 15 2 3 9 10 12 4 5 6 7 11 14 15(2) 16 17 18 21 22 23(2) 24 25 26 Output Compare Output 1 Output Compare Output 2 Output Compare Output 3 Output Compare Output 4 Output Compare Output 5 Output Compare Fault A Input Output Compare Fault B Input External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port O O O O O I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 21 PIC32MX1XX/2XX TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name 28-pin QFN Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 36-pin VTLA Pin Type Buffer Type 44-pin QFN Description RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 9 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 22 PPS PPS PPS 23 PPS PPS PPS 28 12 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 25 PPS PPS PPS 26 PPS PPS PPS 3 3 4 11 20 10 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 28 PPS PPS PPS 29 PPS PPS PPS 34 25 26 27 36 37 38 2 3 4 5 34 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 14 PPS PPS PPS 15 PPS PPS PPS 20 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I O I O I O I O I/O I O I/O I/O I O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port Timer1 external clock input Timer2 external clock input Timer3 external clock input Timer4 external clock input Timer5 external clock input UART1 clear to send UART1 ready to send UART1 receive UART1 transmit UART2 clear to send UART2 ready to send UART2 receive UART2 transmit Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 slave synchronization or frame pulse I/O Synchronous serial clock input/output for I2C1 Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168C-page 22 Preliminary 2011 Microchip Technology Inc. TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) PIC32MX1XX/2XX Pin Type Buffer Type 44-pin QFN Description Pin Name 28-pin QFN 27 12(2) 11(2) SDA1 SCL2 SDA2 TMS Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 36-pin VTLA 2 15(2) 14(2) 33 16(2) 15(2) 19 42(2) 41(2) 12 19(2) 11(3) 14 13 15 4 28 27 22 4 3 2 1 2 1 4 3 23 22 27 1 22(2) 14(3) 17 16 18 7 3 2 25 7 6 5 4 5 4 7 6 26 25 2 4 13 TCK 35 TDI 32 TDO 24 RTCC 20 CVREF-
19 CVREF+
14 CVREFOUT 24 C1INA 23 C1INB 22 C1INC 21 C1IND 22 C2INA 21 C2INB 24 C2INC 23 C2IND 15 C3INA 14 C3INB 19 C3INC 21 C3IND PPS C1OUT PPS C2OUT C3OUT PPS Legend: CMOS = CMOS compatible input or output PPS PPS PPS PPS PPS PPS 25(2) 15(3) 18 17 19 2 34 33 28 2 1 36 35 36 35 2 1 29 28 33 35 PPS PPS PPS ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer I/O I/O I/O I I O O I I I O I I I I I I I I I I I I O O O ST ST ST ST ST ST Synchronous serial data input/output for I2C1 Synchronous serial clock input/output for I2C2 Synchronous serial data input/output for I2C2 JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Real-Time Clock alarm output Analog Comparator Voltage Reference (low) Analog Comparator Voltage Reference (high) Analog Comparator Voltage Reference output Analog Comparator Inputs Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Comparator Outputs Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 23 PIC32MX1XX/2XX TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name 28-pin QFN PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMCS1 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR VBUS VUSB 7 9 23 20(2) 1(3) 19(2) 2(3) 18(2) 3(3) 15 14 13 12(2) 28(3) 11(2) 27(3) 21 22(2) 4(3) 12 20 Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 10 8 36-pin VTLA 12 10 26 23(2) 4(3) 22(2) 5(3) 21(2) 6(3) 18 17 16 15(2) 3(3) 14(2) 2(3) 24 25(2) 7(3) 15 23 29 26(2) 35(3) 25(2) 36(3) 24(2) 1(3) 19 18 17 16(2) 34(3) 15(2) 33(3) 27 28(2) 2(3) 16 26 3 2 27 38 37 4 5 13 32 35 12 15 10(2) 21(3) 9(2) 22(3) 8(2) 23(3) 1 44 43 42(2) 20(3) 41(2) 19(3) 11 14(2) 24(3) 42 10 TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST I/O I/O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O I P O I/O I/O Pin Type Buffer Type 44-pin QFN Description TTL/ST Parallel Master Port Address bit 0 input
(Buffered Slave modes) and output
(Master modes) TTL/ST Parallel Master Port Address bit 1 input
(Buffered Slave modes) and output
(Master modes) Parallel Master Port address
(Demultiplexed Master modes) Parallel Master Port Chip Select 1 strobe Parallel Master Port data (Demultiplexed Master mode) or address/data
(Multiplexed Master modes) Parallel Master Port read strobe Parallel Master Port write strobe Analog USB bus power monitor USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. USB Host and OTG bus power control output VBUSON 22 25 28 14 D+
D-
Legend: CMOS = CMOS compatible input or output 18 19 21 22 24 25 8 9 ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Analog USB D+
Analog USB D-
Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168C-page 24 Preliminary 2011 Microchip Technology Inc. TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) PIC32MX1XX/2XX Pin Type Buffer Type 44-pin QFN Description USB OTG ID detect CTMU External Edge Input Pin Name 28-pin QFN USBID CTED1 CTED2 CTED3 CTED4 CTED5 CTED6 CTED7 CTED8 CTED9 CTED10 CTED11 CTED12 CTED13 CTPLS PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 PGED4 PGEC4 11 27 28 13 15 22 23 9 14 18 2 3 21 1 2 18 19 11(2) 27(3) 12(2) 28(3) 36-pin VTLA Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 14 2 3 16 18 25 26 12 17 21 5 6 24 4 15 33 34 17 19 28 29 20 10 18 24 36 1 27 35 5 21 22 14(2) 2(3) 15(2) 3(3) 36 24 25 15(2) 33(3) 16(2) 34(3) 3 4 41 19 20 43 1 14 15 5 13 34 44 8 22 23 11 21 22 8 9 41(2) 19(3) 42(2) 20(3) 12 13 I I I I I I I I I I I I I I O I/O I I/O I I/O I I/O I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST CTMU Pulse Output Data I/O pin for Programming/Debugging Communication Channel 1 Clock input pin for Programming/Debugging Communication Channel 1 Data I/O pin for Programming/Debugging Communication Channel 2 Clock input pin for Programming/Debugging Communication Channel 2 Data I/O pin for Programming/Debugging Communication Channel 3 Clock input pin for Programming/
Debugging Communication Channel 3 Data I/O pin for Programming/Debugging Communication Channel 4 Clock input pin for Programming/
Debugging Communication Channel 4 P = Power I = Input
= N/A Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Analog = Analog input O = Output PPS = Peripheral Pin Select Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 25 PIC32MX1XX/2XX TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name 28-pin QFN Pin Number(1) 28-pin SSOP/
SPDIP/
SOIC 36-pin VTLA Pin Type Buffer Type 44-pin QFN Description P P P P P I I MCLR AVDD AVSS VDD VCAP VSS 26 25 24 10 1 28 27 13 17 5, 16 20 8, 19 32 31 30 18 17 16 5, 13, 14, 23 22 28, 40 7 6, 12, 21 6, 29, 39 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules Positive supply for peripheral logic and I/O pins CPU logic filter capacitor connection Ground reference for logic and I/O pins. This pin must be connected at all times. VREF+
VREF-
Legend: CMOS = CMOS compatible input or output 27 28 19 20 33 34 2 3 ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Analog Analog voltage reference (high) input Analog Analog voltage reference (low) input Analog = Analog input P = Power I = Input O = Output PPS = Peripheral Pin Select
= N/A Note 1: Pin numbers are provided for reference only. See the Pin Diagrams section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168C-page 26 Preliminary 2011 Microchip Technology Inc. 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. Basic Connection Requirements 2.1 Getting started with the PIC32MX1XX/2XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceed-
ing with development. The following is a list of pin names, which must always be connected:
All VDD and VSS pins
(see Section 2.2 Decoupling Capacitors) All AVDD and AVSS pins, even if the ADC module is not used
(see Section 2.2 Decoupling Capacitors) VCAP pin
(see Section 2.3 Capacitor on Voltage Regulator (VCAP)) Internal MCLR pin
(see Section 2.4 Master Clear (MCLR) Pin) PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSP) and debugging purposes
(see Section 2.5 ICSP Pins) OSC1 and OSC2 pins, when external oscillator source is used
(see Section 2.7 External Oscillator Pins) The following pin may be required, as well:
VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note:
The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source. Decoupling Capacitors 2.2 The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. PIC32MX1XX/2XX Consider the following criteria when using decoupling capacitors:
Value and type of capacitor: A value of 0.1 F
(100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-
ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch
(6 mm) in length. Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in par-
allel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implement-
ing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decou-
pling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. FIGURE 2-1:
RECOMMENDED MINIMUM CONNECTION VDD R R1 C 0.1 F Ceramic CBP 0.1 F Ceramic CBP CEFC P A C V MCLR D D V S S V PIC32 VUSB(1) VDD VSS D D V A S S V A D D V S S V 0.1 F Ceramic CBP 0.1 F Ceramic CBP 0.1 F Ceramic CBP VSS VDD 10 Note 1:
If the USB module is not used, this pin must be connected to VDD. 2011 Microchip Technology Inc. Preliminary DS61168C-page 27 PIC32MX1XX/2XX BULK CAPACITORS 2.2.1 The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. 2.3 Capacitor on Internal Voltage Regulator (VCAP) INTERNAL REGULATOR MODE 2.3.1 A low-ESR (1 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regu-
lator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 29.0 Electrical Characteristics for additional information on CEFC specifications. Master Clear (MCLR) Pin 2.4 The MCLR pin provides for two specific device functions:
Device Reset Device programming and debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. in Figure 2-2, illustrated it FIGURE 2-2:
EXAMPLE OF MCLR PIN CONNECTIONS(1,2,3) VDD R JP C R1 MCLR PIC32 Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 3: The capacitor can be sized to prevent uninten-
tional Resets from brief glitches or to extend the device Reset period during POR. DS61168C-page 28 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX JTAG 2.6 The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete compo-
nents are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC character-
istics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. ICSP Pins 2.5 The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging pur-
poses. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements. Ensure that the Communication Channel Select (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB ICD 3 or MPLAB REAL ICE. For more information on ICD 3 and REAL ICE connection following documents that are available on the Microchip web site. Using MPLAB ICD 3 (poster) DS51765 MPLAB ICD 3 Design Advisory DS51764 MPLAB REAL ICE In-Circuit Debugger requirements, refer the to Users Guide DS51616 Using MPLAB REAL ICE Emulator (poster) DS51749 2011 Microchip Technology Inc. Preliminary DS61168C-page 29 PIC32MX1XX/2XX External Oscillator Pins 2.7 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 Oscillator Configuration for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator cir-
cuit close to the respective oscillator pins, not exceed-
ing one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3:
SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the analog-to-
digital input pins (ANx) as digital pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the analog-
to-digital pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must cor-
rectly configure the ADPCFG register. Automatic initial-
ization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic 0, which may affect user application functionality. Unused I/Os 2.9 Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. DS61168C-page 30 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 and Figure 2-5. FIGURE 2-4:
CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION PIC32MX120F032D Current Source CTMU ADC Read the Touch Sensors Microchip mTouch Library Process Samples User Application Display Data Microchip Graphics Library To AN6 To AN7 To AN8 To AN9 To AN11 To AN0 AN0 AN1 To AN1 AN9 AN11 To AN5 R1 C1 R2 C1 R3 C1 R1 C2 R2 C2 R3 C2 R1 C3 R2 C3 R3 C3 R1 C4 R2 C4 R3 C4 R1 C5 R2 C5 R3 C5 Parallel Master Port PMPD<7:0>
PMPWR LCD Controller Frame Buffer Display Controller LCD Panel FIGURE 2-5:
AUDIO PLAYBACK APPLICATION USB Host USB PMP PMPD<7:0>
PMPWR PIC32MX220F032D I2S SPI 3 3 3 SDI Display Audio Codec MMC SD Stereo Headphones Speaker 2011 Microchip Technology Inc. Preliminary DS61168C-page 31 PIC32MX1XX/2XX NOTES:
DS61168C-page 32 Preliminary 2011 Microchip Technology Inc. 3.0 CPU the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 2. CPU sheet,
(DS61113) PIC32 Family Reference Manual, which is available from web site
(www.microchip.com/PIC32). Resources for the MIPS32 M4K Processor Core are available at http://www.mips.com. Microchip refer the the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The the MIPS32 M4K Processor Core is the heart of the PIC32MX1XX/2XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. Features 3.1 5-stage pipeline 32-bit address and data paths MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts PIC32MX1XX/2XX
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency for interrupt handlers
- Bit field manipulation instructions MIPS16e code compression
- 16-bit encoding of 32-bit instructions to improve code density
- Special PC-relative instructions for efficient loading of addresses and constants
- SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines Improved support for handling 8 and 16-bit data types
-
Simple Fixed Mapping Translation (FMT) mechanism Simple dual bus interface Independent 32-bit address and data busses
-
- Transactions can be aborted to improve interrupt latency Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
- Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints FIGURE 3-1:
MIPS32 M4K PROCESSOR CORE BLOCK DIAGRAM CPU MDU Execution Core
(RF/ALU/Shift) EJTAG TAP Off-Chip Debug I/F FMT Bus Interface Dual Bus I/F x i r t a M s u B System Coprocessor Power Management 2011 Microchip Technology Inc. Preliminary DS61168C-page 33 PIC32MX1XX/2XX Architecture Overview 3.2 The MIPS32 M4K processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core:
Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller EXECUTION UNIT 3.2.1 The MIPS32 M4K processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception process-
ing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes:
32-bit adder used for calculating the data address Address unit for calculating the next instruction Logic for branch determination and branch target address address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results the CLZ and CLO instructions Leading Zero/One detect unit for implementing Arithmetic Logic Unit (ALU) for performing bitwise logical operations Shifter and store aligner MULTIPLY/DIVIDE UNIT (MDU) 3.2.2 The MIPS32 M4K processor core includes a Multi-
ply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline oper-
ates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown
(32 of 32x16) represents the rs operand. The second number (16 of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) oper-
and to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a sub-
sequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. TABLE 3-1:
MIPS32 M4K PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits 1 2 2 3 12 19 26 33 1 2 1 2 11 18 25 32 DS61168C-page 34 Preliminary 2011 Microchip Technology Inc. The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive operations is increased. instructions, Multiply-Add (MADD) and Two other Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. TABLE 3-2:
Register Number COPROCESSOR 0 REGISTERS Register Name PIC32MX1XX/2XX 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processors diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2. Function 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Reserved in the PIC32MX1XX/2XX family core. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved in the PIC32MX1XX/2XX family core. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved in the PIC32MX1XX/2XX family core. Debug control and exception status. Program counter at last debug exception. Reserved in the PIC32MX1XX/2XX family core. Program counter at last error. Debug handler scratchpad register. Note 1: Registers used in exception processing. 2: Registers used during debug. 2011 Microchip Technology Inc. Preliminary DS61168C-page 35 PIC32MX1XX/2XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3:
Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL MIPS32 M4K PROCESSOR CORE EXCEPTION TYPES Description Assertion MCLR or a Power-on Reset (POR). EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. Power Management 3.3 The MIPS M4K processor core offers a number of power management low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. including features, 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 25.0 Power-Saving Features. EJTAG Debug Support 3.4 The MIPS M4K processor core provides for an Enhanced JTAG (EJTAG) interface for use in the soft-
ware debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the M4K core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for trans-
ferring test data in and out of the core. In addition to the standard JTAG instructions defined in the EJTAG specification define which registers are selected and how they are used. instructions, special DS61168C-page 36 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 4.1 PIC32MX1XX/2XX Memory Layout PIC32MX1XX/2XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX1XX/2XX devices are illustrated in Figure 4-1 and Figure 4-2. 4.0 MEMORY ORGANIZATION Note:
the PIC32MX1XX/2XX This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive source.For detailed information, refer to Section 3. Memory Organization (DS61115) in the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32). reference PIC32MX1XX/2XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX1XX/2XX devices to execute from data memory. Key features include:
32-bit native data width Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space Flexible program Flash memory partitioning Flexible data RAM partitioning for data and program space Separate boot Flash memory for protected code Robust bus exception handling to intercept runaway code Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable (KSEG0) and non-cacheable (KSEG1) address regions 2011 Microchip Technology Inc. Preliminary DS61168C-page 37 PIC32MX1XX/2XX FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX11X/21X DEVICES(1) Virtual Memory Map Reserved Physical Memory Map 0xFFFFFFFF Device Configuration Registers Boot Flash Reserved SFRs Reserved 1 G E S K Program Flash(2) Reserved RAM(2) Reserved Device Configuration Registers Boot Flash Reserved Program Flash(2) 0 G E S K Reserved RAM(2) Reserved Reserved Device Configuration Registers Boot Flash Reserved SFRs Reserved Program Flash(2) Reserved RAM(2) 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D004000 0x1D003FFF 0x1D000000 0x00001000 0x00000FFF 0x00000000 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD004000 0xBD003FFF 0xBD000000 0xA0001000 0xA0000FFF 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF 0x9FC00000 0x9D004000 0x9D003FFF 0x9D000000 0x80001000 0x80000FFF 0x80000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization
(DS61115) in the PIC32 Family Reference Manual) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61168C-page 38 Preliminary 2011 Microchip Technology Inc. FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX12X/22X DEVICES(1) PIC32MX1XX/2XX Virtual Memory Map Reserved Physical Memory Map 0xFFFFFFFF Device Configuration Registers Boot Flash Reserved SFRs Reserved 1 G E S K Program Flash(2) Reserved RAM(2) Reserved Device Configuration Registers Boot Flash Reserved Program Flash(2) 0 G E S K Reserved RAM(2) Reserved Reserved Device Configuration Registers Boot Flash Reserved SFRs Reserved Program Flash(2) Reserved RAM(2) 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D008000 0x1D007FFF 0x1D000000 0x00002000 0x00001FFF 0x00000000 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD008000 0xBD007FFF 0xBD000000 0xA0002000 0xA0001FFF 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF 0x9FC00000 0x9D008000 0x9D007FFF 0x9D000000 0x80002000 0x80001FFF 0x80000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization
(DS61115) in the PIC32 Family Reference Manual) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2011 Microchip Technology Inc. Preliminary DS61168C-page 39 PIC32MX1XX/2XX FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX13X/23X DEVICES(1) Virtual Memory Map Reserved Physical Memory Map 0xFFFFFFFF Device Configuration Registers Boot Flash Reserved SFRs Reserved 1 G E S K Program Flash(2) Reserved RAM(2) Reserved Device Configuration Registers Boot Flash Reserved Program Flash(2) 0 G E S K Reserved RAM(2) Reserved Reserved Device Configuration Registers Boot Flash Reserved SFRs Reserved Program Flash(2) Reserved RAM(2) 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D010000 0x1D00FFFF 0x1D000000 0x00004000 0x00003FFF 0x00000000 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF 0xBD000000 0xA0004000 0xA0003FFF 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF 0x9FC00000 0x9D010000 0x9D00FFFF 0x9D000000 0x80004000 0x80003FFF 0x80000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization
(DS61115) in the PIC32 Family Reference Manual) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61168C-page 40 Preliminary 2011 Microchip Technology Inc. FIGURE 4-4:
MEMORY MAP ON RESET FOR PIC32MX15X/25X DEVICES(1) PIC32MX1XX/2XX Virtual Memory Map Reserved Physical Memory Map 0xFFFFFFFF Device Configuration Registers Boot Flash Reserved SFRs Reserved 1 G E S K Program Flash(2) Reserved RAM(2) Reserved Device Configuration Registers Boot Flash Reserved Program Flash(2) 0 G E S K Reserved RAM(2) Reserved Reserved Device Configuration Registers Boot Flash Reserved SFRs Reserved Program Flash(2) Reserved RAM(2) 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D020000 0x1D01FFFF 0x1D000000 0x00008000 0x00007FFF 0x00000000 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF 0xBD000000 0xA0008000 0xA0007FFF 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF 0x9FC00000 0x9D020000 0x9D01FFFF 0x9D000000 0x80008000 0x80007FFF 0x80000000 0x00000000 Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. Memory Organization
(DS61115) in the PIC32 Family Reference Manual) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). 2011 Microchip Technology Inc. Preliminary DS61168C-page 41 I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 4 2 4.1.1 Table 4-1 through Table 4-27 contain the peripheral address maps for the PIC32MX1XX/2XX devices. PERIPHERAL REGISTERS LOCATIONS TABLE 4-1:
BUS MATRIX REGISTER MAP s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits l l A s t e s e R 2000 BMXCON(1) 31:16 2010 BMXDKPBA(1) 31:16 15:0 15:0 2020 BMXDUDBA(1) 31:16 15:0 2030 BMXDUPBA(1) 31:16 2040 BMXDRMSZ 2050 BMXPUPBA(1) 31:16 2060 BMXPFMSZ 2070 BMXBOOTSZ 15:0 31:16 15:0 15:0 31:16 15:0 31:16 15:0 BMXWSDRM BMXDKPBA<15:0>
BMXDUDBA<15:0>
BMXDUPBA<15:0>
BMXDRMSZ<31:0>
BMXPUPBA<15:0>
BMXPFMSZ<31:0>
BMXBOOTSZ<31:0>
BMXARB<2:0>
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F 0041 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 3000 BMXPUPBA<19:16>
P r e l i i m n a r y Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-2:
INTERRUPT REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits l l A s t e s e R i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 4 3 T3IF T3IE IFS1 IFS0 1070 1000 1090 1060 IEC1 IEC0 1040 1030 1020 IPTMR CNCIE INTCON FCEIF IC3EIF CNCIF FCEIE IC3EIE 31:16 15:0 1010 INTSTAT(3) 31:16 15:0 31:16 15:0 RTCCIF FSCMIF 31:16 INT2IF 15:0 31:16 DMA3IF DMA2IF DMA1IF CNBIF CNAIF 15:0 RTCCIE FSCMIE 31:16 15:0 INT2IE 31:16 DMA3IE DMA2IE DMA1IE CNAIE 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 CNBIE IPC0 IPC7 IPC1 IPC2 IPC5 IPC6 IPC3 IPC4 1100 10F0 10A0 10B0 10E0 10C0 10D0 Legend:
Note 1:
2:
3:
MVEC AD1IF OC2IF DMA0IF I2C1MIF AD1IE OC2IE DMA0IE I2C1MIE TPC<2:0>
SRIPL<2:0>
IPTMR<31:0>
OC5IF IC2IF CTMUIF I2C1SIF OC5IE IC2IE CTMUIE I2C1SIE IC5IF IC2EIF I2C2MIF I2C1BIF IC5IE IC2EIE I2C2MIE I2C1BIE IC5EIF T2IF I2C2SIF U1TXIF IC5EIE T2IE I2C2SIE U1TXIE T5IF INT1IF I2C2BIF U1RXIF T5IE INT1IE I2C2BIE U1RXIE INT4IF OC1IF U2TXIF U1EIF INT4IE OC1IE U2TXIE U1EIE SS0 INT4EP VEC<5:0>
T4IF INT0IF IC4EIF T1IF T4IE INT0IE IC4IF IC1EIF U2EIF IC4IE IC1EIE U2EIE INT3IF OC3IF CS1IF CS0IF INT3IE OC3IE CS1IE CS0IE IC3IE CTIE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE 0000 INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000 0000 0000 OC4IF IC3IF 0000 IC1IF CTIF 0000 U2RXIF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF SPI1EIF USBIF(2) CMP3IF CMP2IF CMP1IF 0000 SPI1TXIF SPI1RXIF 0000 OC4IE IC4EIE 0000 IC1IE T1IE 0000 U2RXIE SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP3IE CMP2IE CMP1IE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
OC4IP<2:0>
T4IP<2:0>
OC5IP<2:0>
T5IP<2:0>
FCEIP<2:0>
FSCMIP<2:0>
USBIP<2:0>(2) CMP2IP<2:0>
INT0IS<1:0>
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
INT4IS<1:0>
IC4IS<1:0>
AD1IS<1:0>
IC5IS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
SPI1IS<1:0>
CMP3IS<1:0>
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. These bits are not available on PIC32MX1XX devices. This register does not have associated CLR, SET, INV registers. CS1IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
OC4IS<1:0>
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
FCEIS<1:0>
FSCMIS<1:0>
USBIS<1:0>(2) CMP2IS<1:0>
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT4IP<2:0>
IC4IP<2:0>
AD1IP<2:0>
IC5IP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
SPI1IP<2:0>
CMP3IP<2:0>
I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-2:
INTERRUPT REGISTER MAP(1) (CONTINUED) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits l l A s t e s e R s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
1110 IPC8 1120 IPC9 IPC10 1130 Legend:
Note 1:
2:
3:
31:16 15:0 31:16 15:0 31:16 15:0 PMPIP<2:0>
I2C1IP<2:0>
CTMUIP<2:0>
U2IP<2:0>
PMPIS<1:0>
I2C1IS<1:0>
CTMUIS<1:0>
U2IS<1:0>
CNIP<2:0>
U1IP<2:0>
I2C2IP<2:0>
SPI2IP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
CNIS<1:0>
U1IS<1:0>
I2C2IS<1:0>
SPI2IS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
0000 0000 0000 0000 0000 0000 DMA3IS<1:0>
DMA1IS<1:0>
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. These bits are not available on PIC32MX1XX devices. This register does not have associated CLR, SET, INV registers. DMA3IP<2:0>
DMA1IP<2:0>
I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 4 4 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-3:
TIMER1-TIMER5 REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
0600 T1CON 0610 TMR1 0620 PR1 0800 T2CON 0810 TMR2 0820 PR2 0A00 T3CON 0A10 TMR3 0A20 PR3 0C00 T4CON 0C10 TMR4 0C20 PR4 0E00 T5CON 0E10 TMR5 0E20 PR5 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ON ON ON ON ON SIDL SIDL SIDL SIDL SIDL TWDIS TWIP TGATE TGATE TGATE TMR1<15:0>
PR1<15:0>
TMR2<15:0>
PR2<15:0>
TMR3<15:0>
PR3<15:0>
TMR4<15:0>
PR4<15:0>
TMR5<15:0>
PR5<15:0>
TGATE TGATE TCKPS<1:0>
TCKPS<2:0>
TCKPS<2:0>
TCKPS<2:0>
TCKPS<2:0>
T32 T32 TSYNC TCS TCS TCS TCS TCS 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. Legend:
Note 1:
D S 6 1 1 6 8 C
-
p a g e 4 5 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 4 6 P r e l i i m n a r y TABLE 4-4:
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B IC2BUF IC1BUF 2000 IC1CON(1) 31:16 15:0 31:16 2010 15:0 2200 IC2CON(1) 31:16 15:0 31:16 2210 15:0 2400 IC3CON(1) 31:16 15:0 31:16 2410 15:0 2600 IC4CON(1) 31:16 15:0 31:16 2610 15:0 2800 IC5CON(1) 31:16 15:0 31:16 15:0 IC3BUF IC4BUF IC5BUF 2810 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ON ON ON ON ON SIDL SIDL SIDL SIDL SIDL FEDGE C32 ICTMR IC1BUF<31:0>
FEDGE C32 ICTMR IC2BUF<31:0>
FEDGE C32 ICTMR IC3BUF<31:0>
FEDGE C32 ICTMR IC4BUF<31:0>
FEDGE C32 ICTMR IC5BUF<31:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICOV ICBNE ICOV ICBNE ICOV ICBNE ICOV ICBNE ICOV ICBNE ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
s t e s e R l l A 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. Legend:
Note 1:
i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-5:
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1) Bits r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A ON ON ON ON ON SIDL SIDL SIDL SIDL SIDL OC32 OCFLT OCTSEL OCM<2:0>
OC32 OCFLT OCTSEL OCM<2:0>
OC32 OCFLT OCTSEL OCM<2:0>
OC32 OCFLT OCTSEL OCM<2:0>
OC32 OCFLT OCTSEL OCM<2:0>
OC1R<31:0>
OC1RS<31:0>
OC2R<31:0>
OC2RS<31:0>
OC3R<31:0>
OC3RS<31:0>
OC4R<31:0>
OC4RS<31:0>
OC5R<31:0>
OC5RS<31:0>
0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
3410 OC3R 3210 OC2R 3010 OC1R 3220 OC2RS 3020 OC1RS 3000 OC1CON 3400 OC3CON 3200 OC2CON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 3420 OC3RS 31:16 15:0 31:16 15:0 31:16 15:0 3620 OC4RS 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 3600 OC4CON 3800 OC5CON 3820 OC5RS 3610 OC4R 3810 OC5R Legend:
Note 1:
D S 6 1 1 6 8 C
-
p a g e 4 7 I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-6:
I2C1 AND I2C2 REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 5000 I2C1CON 5010 I2C1STAT 5020 I2C1ADD 5030 I2C1MSK 5040 I2C1BRG 5050 I2C1TRN 5060 I2C1RCV 5100 I2C2CON 5110 I2C2STAT 5120 I2C2ADD 5130 I2C2MSK 5140 I2C2BRG 5150 I2C2TRN 5160 I2C2RCV ON ON 31:16 15:0 31:16 15:0 ACKSTAT TRSTAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ACKSTAT TRSTAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SIDL SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN GCSTAT ADD10 IWCOL I2COV BCL BCL Baud Rate Generator Register Transmit Register Receive Register D/A P Address Register Address Mask Register D/A P Address Register Address Mask Register S S Baud Rate Generator Register Transmit Register Receive Register SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN GCSTAT ADD10 IWCOL I2COV PEN R/W PEN R/W RSEN RBF RSEN RBF SEN TBF SEN TBF 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 4 8 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-7:
UART1 AND UART2 REGISTER MAP s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits ON UTXISEL<1:0>
ON UTXISEL<1:0>
6020 U1TXREG 6000 U1MODE(1) 31:16 15:0 6010 U1STA(1) 31:16 15:0 31:16 15:0 31:16 6030 U1RXREG 15:0 6040 U1BRG(1) 31:16 15:0 6200 U2MODE(1) 31:16 15:0 6210 U2STA(1) 31:16 15:0 31:16 15:0 31:16 6230 U2RXREG 15:0 6240 U2BRG(1) 31:16 15:0 Legend:
Note 1:
6220 U2TXREG UTXINV URXEN UTXBRK UTXEN UTXBF URXISEL<1:0>
ADDEN RIDLE SIDL IREN RTSMD SIDL IREN RTSMD UTXINV URXEN UTXBRK UTXEN UTXBF UEN<1:0>
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0>
ADM_EN TRMT TX8 RX8 Baud Rate Generator Prescaler ADM_EN TRMT TX8 RX8 URXISEL<1:0>
Baud Rate Generator Prescaler ADDR<7:0>
PERR Transmit Register Receive Register ADDR<7:0>
PERR Transmit Register Receive Register FERR OERR PDSEL<1:0>
FERR OERR ADDEN RIDLE UEN<1:0>
WAKE LPBACK ABAUD RXINV BRGH 0000 STSEL 0000 0000 URXDA 0110 0000 0000 0000 0000 0000 0000 0000 STSEL 0000 0000 URXDA 0110 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. D S 6 1 1 6 8 C
-
p a g e 4 9 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 5 0 TABLE 4-8:
SPI2 AND SPI2 REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
DISSDO MODE32 MODE16 FRMCNT<2:0>
MCLKSEL SMP CKE SSEN RXBUFELM<4:0>
MSTEN DISSDI STXISEL<1:0>
SPIFE SRXISEL<1:0>
TXBUFELM<4:0>
5800 SPI1CON 5810 SPI1STAT 5820 SPI1BUF 5830 SPI1BRG 5840 SPI1CON2 15:0 ON SIDL 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 FRMERR SPIBUSY FRM ERREN SPI ROVEN SGNEXT SPI ON SIDL 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 FRMERR SPIBUSY SPI 15:0 SGNEXT P r e l i i m n a r y 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5A40 SPI2CON2 SPITUR SRMT SPIROV SPIRBE DATA<31:0>
SPI TUREN IGNROV IGNTUR AUDEN MCLKSEL FRMCNT<2:0>
CKP CKP DISSDO MODE32 MODE16 RXBUFELM<4:0>
SMP CKE SSEN MSTEN DISSDI TXBUFELM<4:0>
SPITUR SRMT SPIROV SPIRBE DATA<31:0>
FRM ERREN SPI ROVEN SPI TUREN IGNROV IGNTUR AUDEN ENHBUF 0000 0000 0000 SPIRBF 0008 0000 0000 0000 0000 0000 0000 ENHBUF 0000 0000 0000 SPIRBF 0008 0000 0000 0000 0000 0000 0000 SPITBF SPITBF AUDMOD<1:0>
SPIFE SRXISEL<1:0>
AUDMOD<1:0>
BRG<8:0>
SPITBE AUD-
MONO STXISEL<1:0>
SPITBE BRG<8:0>
AUD MONO x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. Legend:
Note 1:
i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-9:
ADC REGISTER MAP Register Name e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
CSCNA OFFCAL ON VCFG<2:0>
SIDL 90B0 ADC1BUF4 90A0 ADC1BUF3 9090 ADC1BUF2 9080 ADC1BUF1 9070 ADC1BUF0 9000 AD1CON1(1) 31:16 15:0 9010 AD1CON2(1) 31:16 15:0 9020 AD1CON3(1) 31:16 15:0 ADRC 9040 AD1CHS(1) 31:16 CH0NB 15:0 9050 AD1CSSL(1) 31:16 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 9130 ADC1BUFC 9120 ADC1BUFB 9100 ADC1BUF9 9110 ADC1BUFA 90F0 ADC1BUF8 90E0 ADC1BUF7 90C0 ADC1BUF5 90D0 ADC1BUF6 9140 ADC1BUFD Legend:
Note 1:
FORM<2:0>
SAMC<4:0>
CH0SB<3:0>
BUFS CH0NA SSRC<2:0>
CLRASAM SMPI<3:0>
ADCS<7:0>
ASAM SAMP BUFM CH0SA<3:0>
CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ALTS 0000 DONE 0000 0000 0000 0000 0000 0000 0000 0000 CSSL0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for details. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 5 1 I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-9:
ADC REGISTER MAP (CONTINUED) Register Name e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for details. ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
31:16 15:0 31:16 15:0 9150 ADC1BUFE 9160 ADC1BUFF Legend:
Note 1:
0000 0000 0000 0000 I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 5 2 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-10: DMA GLOBAL REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 3000 DMACON 3010 DMASTAT 3020 DMAADDR 31:16 15:0 31:16 15:0 31:16 15:0 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ON SUSPEND DMABUSY RDWR DMACH<2:0>(2) DMAADDR<31:0>
Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. TABLE 4-11: DMA CRC REGISTER MAP(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 BYTO<1:0>
WBO BITO PLEN<4:0>
CRCEN CRCAPP CRCTYP CRCCH<2:0>
DCRCDATA<31:0>
DCRCXOR<31:0>
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. s t e s e R l l A 0000 0000 0000 0000 0000 0000 s t e s e R l l A 0000 0000 0000 0000 0000 0000 s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR 31:16 15:0 31:16 15:0 31:16 15:0 Legend:
Note 1:
D S 6 1 1 6 8 C
-
p a g e 5 3 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 3060 DCH0CON 3070 DCH0ECON 3080 DCH0INT 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 3130 DCH1ECON 3140 DCH1INT 3150 DCH1SSA 3160 DCH1DSA 31:16 15:0 CHBUSY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 CHBUSY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 CHSIRQ<7:0>
CHSIRQ<7:0>
CHCHNS CHSSA<31:0>
CHDSA<31:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHSPTR<15:0>
CHDPTR<15:0>
CHCSIZ<15:0>
CHCPTR<15:0>
CHEN PATEN CHAED CHAEN CHCHN CHEDET SIRQEN AIRQEN CHPRI<1:0>
CHAIRQ<7:0>
0000 0000 00FF FF00 CFORCE CABORT CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 CFORCE CABORT CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 0000 0000 0000 CHPDAT<7:0>
CHAIRQ<7:0>
CHPRI<1:0>
SIRQEN AIRQEN CHEDET CHCHN CHAEN CHAED PATEN CHEN CHSSA<31:0>
CHDSA<31:0>
CHCHNS Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. D S 6 1 1 6 8 C
-
p a g e 5 4 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 3170 DCH1SSIZ 3180 DCH1DSIZ n c
. 3190 DCH1SPTR 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 CHBUSY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT 3210 DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ CHSIRQ<7:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHSPTR<15:0>
CHDPTR<15:0>
CHCSIZ<15:0>
CHCPTR<15:0>
CHEN CHAED CHCHN CHPDAT<7:0>
CHAIRQ<7:0>
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 CFORCE CABORT CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHPRI<1:0>
SIRQEN AIRQEN CHEDET CHAEN PATEN CHSSA<31:0>
CHDSA<31:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHSPTR<15:0>
CHDPTR<15:0>
CHCSIZ<15:0>
CHCHNS Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 5 5 I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-12: DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 3280 DCH2CPTR 3290 DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT 31:16 15:0 31:16 15:0 31:16 15:0 CHBUSY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 CHSIRQ<7:0>
CHCHNS CHSSA<31:0>
CHCPTR<15:0>
CHEN PATEN CHAED CHAEN CHCHN CHEDET SIRQEN AIRQEN CHPRI<1:0>
CHPDAT<7:0>
CHAIRQ<7:0>
0000 0000 0000 0000 0000 0000 00FF FF00 CFORCE CABORT CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHPDAT<7:0>
CHDSA<31:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHSPTR<15:0>
CHDPTR<15:0>
CHCSIZ<15:0>
CHCPTR<15:0>
Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 5 6 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-13: COMPARATOR REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
A000 CM1CON A010 CM2CON A020 CM3CON A060 CMSTAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ON ON ON COE COE COE CPOL CPOL CPOL SIDL EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
CREF CREF CREF CCH<1:0>
CCH<1:0>
CCH<1:0>
0000 00C3 0000 00C3 0000 00C3 0000 C1OUT 0000 C3OUT C2OUT Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. COUT COUT COUT TABLE 4-14: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
9800 CVRCON 31:16 15:0 ON CVROE CVRR CVRSS CVR<3:0>
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. 0000 0000 Legend:
Note 1:
D S 6 1 1 6 8 C
-
p a g e 5 7 I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-15:
FLASH CONTROLLER REGISTER MAP s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B F400 NVMCON(1) 31:16 15:0 31:16 F410 NVMKEY 15:0 F420 NVMADDR(1) 31:16 15:0 31:16 15:0 31:16 15:0 F430 NVMDATA F440 NVMSRC ADDR Legend:
Note 1:
Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 WR WREN WRERR LVDERR LVDSTAT NVMOP<3:0>
NVMKEY<31:0>
NVMADDR<31:0>
NVMDATA<31:0>
NVMSRCADDR<31:0>
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. I P C 3 2 M X 1 X X 2 X X
/
s t e s e R l l A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 D S 6 1 1 6 8 C
-
p a g e 5 8 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-16:
SYSTEM CONTROL REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
PLLODIV<2:0>
COSC<2:0>
FRCDIV<2:0>
NOSC<2:0>
SOSCRDY PBDIVRDY CLKLOCK ULOCK(4) SLOCK ON ON SIDL OE IOLOCK PMDLOCK RODIV<14:0>
RSLP DIVSWEN ACTIVE ROTRIM<8:0>
CMR SYSKEY<31:0>
VREGS EXTR SWR SLPEN PBDIV<1:0>
CF TUN<5:0>
SWDTPS<4:0>
WDTO SLEEP JTAGEN OC5MD OC4MD IC4MD IC5MD T5MD T4MD PLLMULT<2:0>
BOR IDLE ROSEL<3:0>
x1xx(2) UFRCEN(4) SOSCEN OSWEN xxxx(2) 0000 0000 0000 0000 0000 0000 0000 WDTWINEN WDTCLR 0000 0000 POR xxxx(2) 0000 0000 0000 TDOEN 000B 0000 0000 0000 AD1MD 0000 0000 CMP3MD CMP2MD CMP1MD 0000 OC1MD 0000 OC3MD 0000 IC1MD IC3MD 0000 0000 T1MD I2C1MD 0000 0000 U1MD PMPMD 0000 REFOMD RTCCMD 0000 T2MD I2C1MD U2MD OC2MD IC2MD SWRST T3MD CVRMD CTMUMD x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. USB1MD SPI2MD SPI1MD CLR, SET and INV Registers for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. This register does not have associated CLR, SET, INV registers. This bit is available on PIC32MX2XX devices only. 2:
3:
4:
1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 5 9 F600 RCON F010 OSCTUN F610 RSWRST 0000 WDTCON F000 OSCCON F020 REFOCON F030 REFOTRIM 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 F200 CFGCON 15:0 F230 SYSKEY(3) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 F240 F250 F260 F270 F280 F290 Legend:
Note I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 6 0 P r e l i i m n a r y TABLE 4-17: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits s s e r d d A l a u t r i V
)
#
_ 0 C F B
(
2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 31:16 FVBUSONID FUSBIDIO IOL1WAY PMDL1WAY 15:0 31:16 15:0 UPLLEN(1) 31:16 15:0 31:16 15:0 FPBDIV<1:0>
CP PWP<5:0>
FCKSM<1:0>
UPLLIDIV<2:0>(1) OSCIOFNC POSCMOD<1:0>
BWP USERID<15:0>
Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. This bit is available on PIC32MX2XX devices only. FPLLMUL<2:0>
FPLLODIV<2:0>
FPLLIDIV<2:0>
FWDTWINSZ<1:0> FWDTEN WINDIS WDTPS<4:0>
IESO FSOSCEN ICESEL<1:0>
FNOSC<2:0>
JTAGEN DEBUG<1:0>
TABLE 4-18: DEVICE AND REVISION ID SUMMARY(1) s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B F220 DEVID 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 VER<3:0>
DEVID<27:16>
Bits x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. DEVID<15:0>
I P C 3 2 M X 1 X X 2 X X
/
s t e s e R l l A xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx s t e s e R l l A xxxx xxxx Legend:
Note 1:
i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-19:
PORTA REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
6000 ANSELA 6010 TRISA 6020 PORTA 6030 LATA 6040 ODCA 6050 CNPUA 6060 CNPDA 6070 CNCONA 6080 CNENA 6090 CNSTATA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ON 31:16 15:0 31:16 15:0 SIDL RA8(2) RA9(2) RA7(2) RA10(2) LATA8(2) LATA9(2) LATA7(2) LATA10(2) TRISA7(2) TRISA8(2) TRISA9(2) ODCA10(2) TRISA10(2) CNSTATA10(2) CNSTATA9(2) CNSTATA8(2) CNSTATA7(2) CNPUA10(2) CNPUA9(2) CNPUA8(2) CNPUA7(2) CNPDA10(2) CNPDA9(2) CNPDA8(2) CNPDA7(2) CNIEA10(2) CNIEA7(2) CNIEA9(2) CNIEA8(2) ODCA9(2) ODCA8(2) ODCA7(2) LATA4 LATA2 LATA3 LATA1 ANSA1 TRISA2 TRISA1 TRISA4 TRISA3 RA0 RA2 RA4 RA3 RA1 0000 ANSA0 0003 0000 TRISA0 079F 0000 xxxx 0000 xxxx 0000 0000 0000 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 0000 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 0000 0000 0000 CNIEA0 0000 0000 CNSTATA4 CNSTATA3 CNSTATA2 CNSTATA1 CNSTATA0 0000 CNIEA4 CNIEA3 CNIEA2 CNIEA1 LATA0 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. This bit is available on 44-pin devices only. Legend:
Note 1:
2:
D S 6 1 1 6 8 C
-
p a g e 6 1 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 6 2 P r e l i i m n a r y TABLE 4-20:
PORTB REGISTER MAP r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
6100 ANSELB 6110 TRISB 6120 PORTB 6130 LATB 6140 ODCB 6150 CNPUB 6160 CNPDB 6170 CNCONB 6180 CNENB 6190 CNSTATB RB11 RB10 RC13 RC14 RC15 LATB9 ANSB1 ANSB0 ANSB2 ANSB3 LATB11 RC6(2) TRISB5 TRISB7 TRISB1 TRISB2 TRISB3 TRISB9 TRISB8 TRISB4 LATB13 LATB14 LATB15 LATB10 ANSB13 ANSB14 TRISB14 RC12(2) TRISB6(2) LATB12(2) ANSB12(2) RB8 RB7 RB9 RB5 TRISB13 TRISB12(2) TRISB11 TRISB10 0000 31:16 E00F 15:0 ANSB15 0000 31:16 TRISB0 FFFF 15:0 TRISB15 0000 31:16 xxxx 15:0 0000 31:16 xxxx 15:0 0000 31:16 0000 15:0 0000 31:16 15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 0000 31:16 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 0000 31:16 0000 15:0 0000 31:16 15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB11(2) CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6(2) CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000 0000 31:16 STATB0 0000 STATB8 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF. ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB5 ODCB4 SIDL STATB12(2) STATB6(2) ON LATB6(2) STATB13 STATB15 STATB14 STATB10 RB1 RB3 RB4 RB0 RB2 STATB11 STATB2 STATB1 STATB5 STATB4 STATB3 STATB9 STATB7 ODCB6 CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN LATB0 LATB5 LATB1 LATB3 LATB8 LATB7 LATB4 LATB2 15:0 Legend:
Note 1:
2:
i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-21:
PORTC REGISTER MAP(1,2) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
6200 ANSELC 6210 TRISC 6220 PORTC 6230 LATC 6240 ODCC 6250 CNPUC 6260 CNPDC 6270 CNCONC 6280 CNENC 6290 CNSTATC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ON 31:16 15:0 31:16 15:0 SIDL LATC9 ANSC1 ANSC3 ANSC0 RC6(3) RC4(3) RC5(3) RC7(3) RC8(3) ODCC9 TRISC1 TRISC3 TRISC9 TRISC0 LATC7(3) LATC6(3) LATC8(3) ANSC2(3) TRISC5(3) TRISC2(3) TRISC7(3) TRISC4(3) TRISC8(3) TRISC6(3) RC9 0000 000F 0000 03FF 0000 xxxx 0000 xxxx 0000 0000 0000 CNPUC8(3) CNPUC7(3) CNPUC6(3) CNPUC5(3) CNPUC4(3) CNPUC3 CNPUC2(3) CNPUC1 CNPUC0 0000 0000 CNPDC8(3) CNPDC7(3) CNPDC6(3) CNPDC5(3) CNPDC4(3) CNPDC3 CNPDC2(3) CNPDC1 CNPDC0 0000 0000 0000 0000 0000 0000 CNSTATC9 CNSTATC8(3) CNSTATC7(3) CNSTATC6(3) CNSTATC5(3) CNSTATC4(3) CNSTATC3 CNSTATC2(3) CNSTATC1 CNSTATC0 0000 CNIEC8(3) CNIEC2(3) CNIEC5(3) CNIEC4(3) CNIEC7(3) CNIEC6(3) ODCC5(3) ODCC8(3) ODCC7(3) ODCC6(3) ODCC4(3) LATC5(3) LATC2(3) LATC4(3) RC3 RC1 RC0 CNPUC9 CNPDC9 CNIEC1 CNIEC9 CNIEC0 CNIEC3 RC2(3) LATC0 LATC3 LATC1 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. PORTC is not available on 28-pin devices. This bit is available on 44-pin devices only. Legend:
Note 1:
2:
3:
D S 6 1 1 6 8 C
-
p a g e 6 3 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-22:
PERIPHERAL PIN SELECT INPUT REGISTER MAP s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N FA04 INT1R FA08 INT2R FA0C INT3R FA10 INT4R FA18 T2CKR FA1C T3CKR FA20 T4CKR FA24 T5CKR FA28 IC1R FA2C IC2R FA30 IC3R FA34 IC4R FA38 IC5R FA48 OCFAR FA4C OCFBR FA50 U1RXR Bits e g n a R t i B 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 INT1R<3:0>
INT2R<3:0>
INT3R<3:0>
INT4R<3:0>
T2CKR<3:0>
T3CKR<3:0>
T4CKR<3:0>
T5CKR<3:0>
IC1R<3:0>
IC2R<3:0>
IC3R<3:0>
IC4R<3:0>
IC5R<3:0>
OCFAR<3:0>
OCFBR<3:0>
U1RXR<3:0>
s t e s e R l l A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 D S 6 1 1 6 8 C
-
p a g e 6 4 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-22:
PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N FA54 U1CTSR FA58 U2RXR FA5C U2CTSR FA84 SDI1R FA88 SS1R FA90 SDI2R FA94 SS2R FAB8 REFCLKIR Bits e g n a R t i B 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 U1CTSR<3:0>
U2RXR<3:0>
U2CTSR<3:0>
SDI1R<3:0>
SS1R<3:0>
SDI2R<3:0>
SS2R<3:0>
REFCLKIR<3:0>
s t e s e R l l A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 D S 6 1 1 6 8 C
-
p a g e 6 5 I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 6 6 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-23:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
FB2C FB0C FB00 FB10 FB08 FB04 RPA4R RPA2R RPA1R RPA0R RPA3R RPB0R FB24 RPA9R(1) FB20 RPA8R(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 FB40 15:0 FB44 RPB6R(2) 31:16 15:0 31:16 15:0 31:16 15:0 RPB4R RPB8R RPB1R RPB2R RPB3R RPB5R RPB7R FB30 FB34 FB38 FB48 FB3C FB4C RPA0<3:0>
RPA1<3:0>
RPA2<3:0>
RPA3<3:0>
RPA4<3:0>
RPA8<3:0>
RPA9<3:0>
RPB0<3:0>
RPB1<3:0>
RPB2<3:0>
RPB3<3:0>
RPB4<3:0>
RPB5<3:0>
RPB6<3:0>
RPB7<3:0>
RPB8<3:0>
I P C 3 2 M X 1 X X 2 X X
/
s t e s e R l l A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Note 1:
2:
3:
This register is only available on 44-pin devices. This register is only available on PIC32MX1XX devices. This register is only available on 36-pin and 44-pin devices. TABLE 4-23:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
FB50 RPB9R FB58 RPB11R FB64 RPB14R FB60 RPB13R FB54 RPB10R 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 FB68 RPB15R 15:0 FB6C RPC0R(3) 31:16 15:0 FB70 RPC1R(3) 31:16 15:0 FB74 RPC2R(1) 31:16 15:0 FB78 RPC3R(3) 31:16 15:0 FB7C RPC4R(1) 31:16 15:0 FB80 RPC5R(1) 31:16 15:0 FB84 RPC6R(1) 31:16 15:0 FB88 RPC7R(1) 31:16 15:0 FB8C RPC8R(1) 31:16 15:0 FB90 RPC9R(3) 31:16 15:0 Note RPB9<3:0>
RPB10<3:0>
RPB11<3:0>
RPB13<3:0>
RPB14<3:0>
RPB15<3:0>
RPC0<3:0>
RPC1<3:0>
RPC2<3:0>
RPC3<3:0>
RPC4<3:0>
RPC5<3:0>
RPC6<3:0>
RPC7<3:0>
RPC8<3:0>
RPC9<3:0>
1:
2:
3:
This register is only available on 44-pin devices. This register is only available on PIC32MX1XX devices. This register is only available on 36-pin and 44-pin devices. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 6 7 s t e s e R l l A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-24:
PARALLEL MASTER PORT REGISTER MAP(1) r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
7000 PMCON 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN 7060 PMSTAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ON BUSY SIDL IRQM<1:0>
CS1 ADRMUX<1:0>
INCM<1:0>
IBF PTEN14 IBOV IB3F PMPTTL PTWREN PTRDEN MODE<1:0>
CSF<1:0>
WAITB<1:0>
ALP CS1P WAITM<3:0>
DATAOUT<31:0>
DATAIN<31:0>
IB2F IB1F IB0F OBE ADDR<10:0>
PTEN<10:0>
OBUF WRSP RDSP WAITE<1:0>
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 008F OB3E OB2E OB1E OB0E Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 6 8 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y TABLE 4-25: RTCC REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 0200 RTCCON 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE ON 31:16 15:0 31:16 15:0 ALRMEN CHIME 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SIDL PIV HR10<3:0>
SEC10<3:0>
YEAR10<3:0>
DAY10<3:0>
HR10<3:0>
SEC10<3:0>
DAY10<3:0>
ALRMSYNC AMASK<3:0>
HR01<3:0>
SEC01<3:0>
YEAR01<3:0>
DAY01<3:0>
HR01<3:0>
SEC01<3:0>
DAY01<3:0>
CAL<9:0>
RTSECSEL RTCCLKON MIN10<3:0>
MONTH10<3:0>
MIN10<3:0>
MONTH10<3:0>
0000 RTCWREN RTCSYNC HALFSEC RTCOE 0000 0000 0000 ARPT<7:0>
xxxx xx00 xxxx xx00 xxxx xx00 00xx xx0x MIN01<3:0>
MONTH01<3:0>
WDAY01<3:0>
MIN01<3:0>
MONTH01<3:0>
WDAY01<3:0>
Legend:
Note 1:
x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. TABLE 4-26: CTMU REGISTER MAP(1) i r e t s g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits s s e r d d A l a u t r i V
)
#
_ 0 8 F B
(
A200 CTMUCON 31:16 EDG1MOD EDG1POL 15:0 ON EDG1SEL<3:0>
TGEN EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0>
EDGEN EDGSEQEN IDISSEN CTTRIG x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for more information. ITRIM<5:0>
CTMUSIDL IRNG<1:0>
0000 0000 Legend:
Note 1:
D S 6 1 1 6 8 C
-
p a g e 6 9 I P C 3 2 M X 1 X X 2 X X
/
I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-27: USB REGISTER MAP(1) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits U1OTGIE 5040 U1OTGIR(2) 31:16 15:0 31:16 5050 15:0 5060 U1OTGSTAT(3) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 5070 U1OTGCON U1PWRC 5080 5200 U1IR(2) 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 5210 U1IE 5220 U1EIR(2) 5230 U1EIE 5240 U1STAT(3) 5250 U1CON 5260 U1ADDR 5270 U1BDTP1 Legend:
Note IDIF IDIE ID UACTPND(4) SOFIF TRNIF IDLEIF ACTVIF ACTVIE LSTATE STALLIF SESVD SESEND SESVDIF SESENDIF SESVDIE SESENDIE T1MSECIF LSTATEIF T1MSECIE LSTATEIE USLPGRD USBBUSY ATTACHIF RESUMEIF STALLIE ATTACHIE RESUMEIE 0000 VBUSVDIF 0000 0000 VBUSVDIE 0000 0000 VBUSVD 0000 0000 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000 0000 USUSPEND USBPWR 0000 0000 0000 URSTIF DETACHIF 0000 0000 0000 URSTIE DETACHIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ENDPT<3:0>
PKTDIS TOKBUSY DFN8EE CRC16EE HOSTEN RESUME DFN8EF CRC16EF CRC5EE EOFEE CRC5EF EOFEF PPBI DEVADDR<6:0>
USBEN SOFEN BDTPTRL<7:1>
DIR USBRST PPBRST LSPDEN UERRIE UERRIF JSTATE DMAEE DMAEF BMXEE BMXEF BTOEE BTOEF BTSEE BTSEF IDLEIE SOFIE PIDEE TRNIE PIDEF SE0 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 CLR, SET and INV Registers for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. 2:
3:
4:
D S 6 1 1 6 8 C
-
p a g e 7 0 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. TABLE 4-27: USB REGISTER MAP(1) (CONTINUED) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 UTEYE UOEMON LSPD RETRYDIS PID<3:0>
FRML<7:0>
CNT<7:0>
BDTPTRH<7:0>
BDTPTRU<7:0>
USBSIDL FRMH<2:0>
EP<3:0>
EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 UASUSPND 0001 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 CLR, SET and INV Registers for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. 2:
3:
4:
i 2 0 1 1 M c r o c h p T e c h n o o g y I i l P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 7 1 5280 U1FRML(3) 5290 U1FRMH(3) n c
. 52A0 U1TOK 52B0 U1SOF 52C0 U1BDTP2 52D0 U1BDTP3 52E0 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 5380 U1EP8 Legend:
Note I P C 3 2 M X 1 X X 2 X X
/
TABLE 4-27: USB REGISTER MAP(1) (CONTINUED) s s e r d d A l a u t r i V
)
#
_ 8 8 F B
(
r e t s i g e R e m a N e g n a R t i B 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 s t e s e R l l A Bits 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 5390 U1EP9 53A0 U1EP10 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 53E0 U1EP14 53F0 U1EP15 Legend:
Note EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal. 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 CLR, SET and INV Registers for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. 2:
3:
4:
I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 7 2 P r e l i i m n a r y i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. PIC32MX1XX/2XX Control Registers 4.2 Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code. REGISTER 4-1:
Bit Bit Range BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-1 BMX WSDRM U-0 U-0 U-0 U-0 U-0 R/W-1 BMX ERRIXI U-0 U-0 U-0 R/W-1 BMX ERRICD U-0 U-0 U-0 R/W-1 BMX ERRDMA U-0 R/W-0 U-0 R/W-1 BMX ERRDS U-0 R/W-0 U-0 R/W-1 BMX ERRIS U-0 R/W-1 BMXARB<2:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared bit 31-21 Unimplemented: Read as 0 bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access bit 15-7 Unimplemented: Read as 0 bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup Unimplemented: Read as 0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111 = Reserved (using these Configuration modes will produce undefined behavior) 011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 bit 19 bit 18 bit 17 bit 16 bit 5-3 bit 2-0 2011 Microchip Technology Inc. Preliminary DS61168C-page 73 PIC32MX1XX/2XX REGISTER 4-2:
Bit Bit Range 31/23/15/7 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 R-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 BMXDKPBA<15:8>
R-0 BMXDKPBA<7:0>
R-0 U-0 U-0 R/W-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-11 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 10-0 BMXDKPBA<9:0>: Read-Only bits Value is always 0, which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ. DS61168C-page 74 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 REGISTER 4-3:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 R-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 BMXDUDBA<15:8>
R-0 BMXDUDBA<7:0>
R-0 U-0 U-0 R/W-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-11 BMXDUDBA<15:10>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 10-0 BMXDUDBA<9:0>: Read-Only bits Value is always 0, which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ. 2011 Microchip Technology Inc. Preliminary DS61168C-page 75 PIC32MX1XX/2XX REGISTER 4-4:
Bit Bit Range BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER(1,2) Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 R-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 BMXDUPBA<15:8>
R-0 BMXDUPBA<7:0>
R-0 U-0 U-0 R/W-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-11 BMXDUPBA<15:10>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 10-0 BMXDUPBA<9:0>: Read-Only bits Value is always 0, which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXDRMSZ. DS61168C-page 76 Preliminary 2011 Microchip Technology Inc. REGISTER 4-5:
Bit Bit Range BMXDRMSZ: DATA RAM SIZE REGISTER Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 PIC32MX1XX/2XX Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R R R R Legend:
R = Readable bit
-n = Value at POR R R R R R R R R R R BMXDRMSZ<31:24>
R R BMXDRMSZ<23:16>
R R BMXDRMSZ<15:8>
R BMXDRMSZ<7:0>
R R R R R R R R R R R R R W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes:
0x00001000 = device has 4 KB RAM 0x00002000 = device has 8 KB RAM 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM REGISTER 4-6:
BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER(1,2) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 BMXPUPBA<15:8>
R-0 BMXPUPBA<7:0>
R/W-0 R-0 U-0 U-0 R/W-0 R/W-0 BMXPUPBA<19:16>
R-0 R-0 R-0 R-0 U-0 R/W-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as 0 bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA<10:0>: Read-Only bits Value is always 0, which forces 2 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. 2: The value in this register must be less than or equal to BMXPFMSZ. 2011 Microchip Technology Inc. Preliminary DS61168C-page 77 PIC32MX1XX/2XX REGISTER 4-7:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 R R R R Legend:
R = Readable bit
-n = Value at POR BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R BMXPFMSZ<31:24>
R R BMXPFMSZ<23:16>
R R BMXPFMSZ<15:8>
R BMXPFMSZ<7:0>
R R R R R R R R R R R R R W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes:
0x00004000 = device has 16 KB Flash 0x00008000 = device has 32 KB Flash 0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R R R R R R R R R R BMXBOOTSZ<31:24>
R R BMXBOOTSZ<23:16>
R R BMXBOOTSZ<15:8>
R R BMXBOOTSZ<7:0>
R R R R Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R REGISTER 4-8:
Bit Bit Range 31:24 23:16 15:8 7:0 R R R R Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes:
0x00000C00 = device has 3 KB boot Flash DS61168C-page 78 Preliminary 2011 Microchip Technology Inc. 5.0 FLASH PROGRAM MEMORY the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 5. Flash sheet, Program Memory (DS61121) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). refer 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX In-Circuit Serial Programming (ICSP) PIC32MX1XX/2XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory:
1. Run-Time Self-Programming (RTSP) 2. EJTAG Programming 3. RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. Flash Program Memory (DS61121) in the PIC32 Family Reference Manual. EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the PIC32 Flash Programming Specification (DS61145), which can be downloaded from the Microchip web site. 2011 Microchip Technology Inc. Preliminary DS61168C-page 79 PIC32MX1XX/2XX REGISTER 5-1:
Bit Bit Range 31/23/15/7 NVMCON: PROGRAMMING CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 WREN U-0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 WR U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R-0 U-0 U-0 R-0 U-0 U-0 R-0 WRERR(1) LVDERR(1) LVDSTAT(1) U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 NVMOP<3:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 bit 14 bit 13 bit 12 bit 11 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation complete or inactive WREN: Write Enable bit 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit This is the only bit in this register reset by a device Reset. WRERR: Write Error bit(1) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set, and cleared, by hardware. 1 = Low-voltage event active 0 = Low-voltage event NOT active bit 10-4 Unimplemented: Read as 0 bit 3-0 NVMOP<3:0>: NVM Operation bits These bits are writable when WREN = 0. 1111 = Reserved 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR). DS61168C-page 80 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX NVMKEY: PROGRAMMING UNLOCK REGISTER(1) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24>
W-0 NVMKEY<23:16>
W-0 W-0 NVMKEY<15:8>
W-0 W-0 NVMKEY<7:0>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 5-2:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 W-0 W-0 W-0 W-0 Legend:
R = Readable bit
-n = Value at POR bit 31-0 NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as 0 on any read Note 1: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. REGISTER 5-3:
Bit Bit Range NVMADDR: FLASH ADDRESS REGISTER Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<31:24>
R/W-0 NVMADDR<23:16>
R/W-0 NVMADDR<15:8>
R/W-0 R/W-0 NVMADDR<7:0>
R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored. Page Erase: Address identifies the page to erase. Row Program: Address identifies the row to program. Word Program: Address identifies the word to program. 2011 Microchip Technology Inc. Preliminary DS61168C-page 81 PIC32MX1XX/2XX REGISTER 5-4:
Bit Bit Range NVMDATA: FLASH PROGRAM DATA REGISTER(1) Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24>
R/W-0 NVMDATA<23:16>
R/W-0 R/W-0 NVMDATA<15:8>
R/W-0 R/W-0 NVMDATA<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 NVMDATA<31:0>: Flash Programming Data bits Note 1: The bits in this register are only reset by a Power-on Reset (POR). REGISTER 5-5:
Bit Bit Range 31/23/15/7 NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<15:8>
R/W-0 NVMSRCADDR<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming. DS61168C-page 82 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources:
POR: Power-on Reset MCLR: Master Clear Reset pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is illustrated in Figure 6-1. 6.0 RESETS the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. Resets
(DS61118) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM Glitch Filter WDT Time-out VDD Rise Detect Power-up Timer Brown-out Reset MCLR Sleep or Idle Voltage Regulator Enabled VDD Configuration Mismatch Reset Software Reset MCLR WDTR POR BOR CMR SWR SYSRST 2011 Microchip Technology Inc. Preliminary DS61168C-page 83 PIC32MX1XX/2XX REGISTER 6-1:
Bit Bit Range 31/23/15/7 RCON: RESET CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS EXTR R/W-0, HS SWR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE U-0 U-0 R/W-0, HS CMR R/W-1, HS BOR(1) U-0 U-0 R/W-0 VREGS R/W-1, HS POR(1) Legend:
R = Readable bit
-n = Value at POR HS = Set by hardware W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-10 Unimplemented: Read as 0 bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is disabled and is off during Sleep mode EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed Unimplemented: Read as 0 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: User software must clear this bit to view next detection. DS61168C-page 84 Preliminary 2011 Microchip Technology Inc. REGISTER 6-2:
Bit Bit Range RSWRST: SOFTWARE RESET REGISTER Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 PIC32MX1XX/2XX Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC SWRST(1) HC = Cleared by hardware W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-1 Unimplemented: Read as 0 bit 0 SWRST: Software Reset Trigger bit(1) 1 = Enable software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2011 Microchip Technology Inc. Preliminary DS61168C-page 85 PIC32MX1XX/2XX NOTES:
DS61168C-page 86 Preliminary 2011 Microchip Technology Inc. 7.0 INTERRUPT CONTROLLER the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. Interrupt Controller (DS61108) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes interrupt events before the presenting them to the CPU. PIC32MX1XX/2XX The PIC32MX1XX/2XX interrupt module includes the following features:
Up to 64 interrupt sources Up to 44 interrupt vectors Single and multi-vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set for all priority levels(1) Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing Note 1: On PIC32MX1XX/2XX devices, the dedicated shadow set is associated with all priority levels. FIGURE 7-1:
INTERRUPT CONTROLLER MODULE s t s e u q e R Vector Number t p u r r e n t I Interrupt Controller Priority Level CPU Core Shadow Set Number 2011 Microchip Technology Inc. Preliminary DS61168C-page 87 PIC32MX1XX/2XX TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ
#
Vector
#
Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0 1 2 3 4 5 5 6 7 8 9 9 10 11 12 13 13 14 15 16 17 17 18 19 20 21 21 22 23 24 25 Highest Natural Order Priority IEC0<0>
IEC0<1>
IEC0<2>
IEC0<3>
IEC0<4>
IEC0<5>
IEC0<6>
IEC0<7>
IEC0<8>
IEC0<9>
IPC0<1:0>
IPC0<9:8>
IPC0<17:16>
IPC0<25:24>
IPC1<1:0>
IPC1<9:8>
IPC1<9:8>
IPC1<17:16>
IPC1<25:24>
IPC2<1:0>
IPC2<9:8>
IPC2<9:8>
IPC2<17:16>
IPC2<25:24>
IPC3<1:0>
IPC3<9:8>
IPC3<9:8>
IPC3<17:16>
IPC3<25:24>
IPC4<1:0>
IPC4<9:8>
IPC4<9:8>
IPC4<17:16>
IPC4<25:24>
IPC5<1:0>
IPC5<9:8>
IPC5<9:8>
IPC5<17:16>
IPC5<25:24>
IPC6<1:0>
IPC6<9:8>
IPC0<4:2>
IFS0<0>
IPC0<12:10>
IFS0<1>
IPC0<20:18>
IFS0<2>
IPC0<28:26>
IFS0<3>
IPC1<4:2>
IFS0<4>
IPC1<12:10>
IFS0<5>
IPC1<12:10>
IFS0<6>
IPC1<20:18>
IFS0<7>
IPC1<28:26>
IFS0<8>
IFS0<9>
IPC2<4:2>
IFS0<10> IEC0<10> IPC2<12:10>
IFS0<11> IEC0<11> IPC2<12:10>
IFS0<12> IEC0<12> IPC2<20:18>
IFS0<13> IEC0<13> IPC2<28:26>
IFS0<14> IEC0<14>
IPC3<4:2>
IFS0<15> IEC0<15> IPC3<12:10>
IFS0<16> IEC0<16> IPC3<12:10>
IFS0<17> IEC0<17> IPC3<20:18>
IFS0<18> IEC0<18> IPC3<28:26>
IFS0<19> IEC0<19>
IPC4<4:2>
IFS0<20> IEC0<20> IPC4<12:10>
IFS0<21> IEC0<21> IPC4<12:10>
IFS0<22> IEC0<22> IPC4<20:18>
IFS0<23> IEC0<23> IPC4<28:26>
IFS0<24> IEC0<24>
IPC5<4:2>
IFS0<25> IEC0<25> IPC5<12:10>
IFS0<26> IEC0<26> IPC5<12:10>
IFS0<27> IEC0<27> IPC5<20:18>
IFS0<28> IEC0<28> IPC5<28:26>
IFS0<29> IEC0<29>
IPC6<4:2>
IFS0<30> IEC0<30> IPC6<12:10>
CT Core Timer Interrupt CS0 Core Software Interrupt 0 CS1 Core Software Interrupt 1 INT0 External Interrupt T1 Timer1 IC1E Input Capture 1 Error IC1 Input Capture 1 OC1 Output Compare 1 INT1 External Interrupt 1 T2 Timer2 IC2E Input Capture 2 IC2 Input Capture 2 OC2 Output Compare 2 INT2 External Interrupt 2 T3 Timer3 IC3E Input Capture 3 IC3 Input Capture 3 OC3 Output Compare 3 INT3 External Interrupt 3 T4 Timer4 IC4E Input Capture 4 Error IC4 Input Capture 4 OC4 Output Compare 4 INT4 External Interrupt 4 T5 Timer5 IC5E Input Capture 5 Error IC5 Input Capture 5 OC5 Output Compare 5 AD1 ADC1 Convert done FSCM Fail-Safe Clock Monitor RTCC Real-Time Clock and Calendar No FCE Flash Control Event No CMP1 Comparator Interrupt No CMP2 Comparator Interrupt No CMP3 Comparator Interrupt Yes USB USB Interrupts Yes SPI1E SPI1 Fault Yes SPI1RX SPI1 Receive Done SPI1TX SPI1 Transfer Done Yes Note 1: Not all interrupt sources are available on all devices. See TABLE 1: PIC32MX1XX General Purpose IFS0<31> IEC0<31> IPC6<20:18>
IPC6<28:26>
IFS1<0>
IFS1<1>
IPC7<4:2>
IPC7<12:10>
IFS1<2>
IPC7<20:18>
IFS1<3>
IFS1<4>
IPC7<28:26>
IPC7<28:26>
IFS1<5>
IFS1<6>
IPC7<28:26>
No No No No No Yes Yes No No No Yes Yes No No No Yes Yes No No No Yes Yes No No No Yes Yes No Yes No No IPC6<17:16>
IPC6<25:24>
IPC7<1:0>
IPC7<9:8>
IPC7<17:16>
IPC7<25:24>
IPC7<25:24>
IPC7<25:24>
IEC1<0>
IEC1<1>
IEC1<2>
IEC1<3>
IEC1<4>
IEC1<5>
IEC1<6>
31 32 33 34 35 36 37 38 26 27 28 29 30 31 31 31 Family Features and TABLE 2: PIC32MX2XX USB Family Features for the lists of available peripherals. DS61168C-page 88 Preliminary 2011 Microchip Technology Inc. TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) PIC32MX1XX/2XX Interrupt Source(1) IRQ
#
Vector
#
U1E UART1 Fault U1RX UART1 Receive Done U1TX UART1 Transfer Done I2C1B I2C1 Bus Collision Event I2C1S I2C1 Slave Event I2C1M I2C1 Master Event CNA PORTA Input Change Interrupt CNB PORTB Input Change Interrupt CNC PORTC Input Change Interrupt PMP Parallel Master Port PMPE Parallel Master Port Error SPI2E SPI2 Fault SPI2RX SPI2 Receive Done SPI2TX SPI2 Transfer Done U2E UART2 Error U2RX UART2 Receiver U2TX UART2 Transmitter I2C2B I2C2 Bus Collision Event I2C2S I2C2 Slave Event I2C2M I2C2 Master Event CTMU CTMU Event DMA0 DMA Channel 0 DMA1 DMA Channel 1 DMA2 DMA Channel 2 DMA3 DMA Channel 3 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Interrupt Bit Location Flag Enable IEC1<7>
IEC1<8>
IEC1<9>
Priority IPC8<4:2>
IFS1<7>
IPC8<4:2>
IFS1<8>
IFS1<9>
IPC8<4:2>
IFS1<10> IEC1<10> IPC8<12:10>
IFS1<11> IEC1<11> IPC8<12:10>
IFS1<12> IEC1<12> IPC8<12:10>
IFS1<13> IEC1<13> IPC8<20:18>
Sub-priority IPC8<1:0>
IPC8<1:0>
IPC8<1:0>
IPC8<9:8>
IPC8<9:8>
IPC8<9:8>
IPC8<17:16>
IFS1<14> IEC1<14> IPC8<20:18>
IPC8<17:16>
IFS1<15> IEC1<15> IPC8<20:18>
IPC8<17:16>
32 32 32 33 33 33 34 34 34 IFS1<16> IEC1<16> IPC8<28:26>
IPC8<25:24>
IFS1<17> IEC1<17> IPC8<28:26>
IPC8<25:24>
IFS1<18> IEC1<18>
IPC9<4:2>
IPC9<1:0>
IPC9<4:2>
IFS1<19> IEC1<19>
IPC9<1:0>
IFS1<20> IEC1<20>
IPC9<4:2>
IPC9<1:0>
IFS1<21> IEC1<21> IPC9<12:10>
IPC9<9:8>
IFS1<22> IEC1<22> IPC9<12:10>
IPC9<9:8>
IFS1<23> IEC1<23> IPC9<12:10>
IPC9<9:8>
IFS1<24> IEC1<24> IPC9<20:18>
IPC9<17:16>
IFS1<25> IEC1<25> IPC9<20:18>
IPC9<17:16>
IFS1<26> IEC1<26> IPC9<20:18>
IPC9<17:16>
IFS1<27> IEC1<27> IPC9<28:26>
IPC9<25:24>
IFS1<28> IEC1<28>
IPC10<4:2>
IPC10<1:0>
IFS1<29> IEC1<29> IPC10<12:10>
IPC10<9:8>
IFS1<30> IEC1<30> IPC10<20:18> IPC10<17:16>
IFS1<31> IEC1<31> IPC10<28:26> IPC10<25:24>
35 35 36 36 36 37 37 37 38 38 38 39 40 41 42 43 Lowest Natural Order Priority Persistent Interrupt Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Note 1: Not all interrupt sources are available on all devices. See TABLE 1: PIC32MX1XX General Purpose Family Features and TABLE 2: PIC32MX2XX USB Family Features for the lists of available peripherals. 2011 Microchip Technology Inc. Preliminary DS61168C-page 89 PIC32MX1XX/2XX REGISTER 7-1:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR INTCON: INTERRUPT CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 MVEC R/W-0 INT4EP U-0 U-0 U-0 R/W-0 INT3EP U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 INT2EP TPC<2:0>
R/W-0 INT1EP U-0 R/W-0 SS0 R/W-0 R/W-0 INT0EP W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Read as 0 bit 16 SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set bit 15-13 Unimplemented: Read as 0 bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode Unimplemented: Read as 0 bit 11 bit 10-8 TPC<2:0>: Temporal Proximity Control bits 111 = Interrupts of group priority 7 or lower start the TP timer 010 = Interrupts of group priority 2 or lower start the TP timer 001 = Interrupts of group priority 1 start the IP timer 000 = Disables proximity timer Unimplemented: Read as 0 INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168C-page 90 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX INTSTAT: INTERRUPT STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 RIPL<2:0>(1) R/W-0 U-0 U-0 R/W-0 R/W-0 VEC<5:0>(1) W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 7-2:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR bit 31-11 Unimplemented: Read as 0 bit 10-8 RIPL<2:0>: Requested Priority Level bits(1) bit 7-6 bit 5-0 000-111 = The priority level of the latest interrupt presented to the CPU Unimplemented: Read as 0 VEC<5:0>: Interrupt Vector bits(1) 00000-11111 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 7-3:
Bit Bit Range TPTMR: TEMPORAL PROXIMITY TIMER REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<31:24>
R/W-0 TPTMR<23:16>
R/W-0 TPTMR<15:8>
R/W-0 TPTMR<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 TPTMR<31:0>: Temporal Proximity Timer Reload bits Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by an interrupt event. 2011 Microchip Technology Inc. Preliminary DS61168C-page 91 PIC32MX1XX/2XX REGISTER 7-4:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 R/W-0 IFS31 R/W-0 IFS23 R/W-0 IFS15 R/W-0 IFS07 Legend:
R = Readable bit
-n = Value at POR IFSx: INTERRUPT FLAG STATUS REGISTER(1) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 IFS30 R/W-0 IFS22 R/W-0 IFS14 R/W-0 IFS06 R/W-0 IFS29 R/W-0 IFS21 R/W-0 IFS13 R/W-0 IFS05 R/W-0 IFS28 R/W-0 IFS20 R/W-0 IFS12 R/W-0 IFS04 R/W-0 IFS27 R/W-0 IFS19 R/W-0 IFS11 R/W-0 IFS03 R/W-0 IFS26 R/W-0 IFS18 R/W-0 IFS10 R/W-0 IFS02 R/W-0 IFS25 R/W-0 IFS17 R/W-0 IFS09 R/W-0 IFS01 R/W-0 IFS24 R/W-0 IFS16 R/W-0 IFS08 R/W-0 IFS00 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 IFS31-IFS00: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred Note 1: This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit definitions. IECx: INTERRUPT ENABLE CONTROL REGISTER(1) Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 IEC30 R/W-0 IEC22 R/W-0 IEC14 R/W-0 IEC06 R/W-0 IEC29 R/W-0 IEC21 R/W-0 IEC13 R/W-0 IEC05 R/W-0 IEC28 R/W-0 IEC20 R/W-0 IEC12 R/W-0 IEC04 R/W-0 IEC27 R/W-0 IEC19 R/W-0 IEC11 R/W-0 IEC03 R/W-0 IEC26 R/W-0 IEC18 R/W-0 IEC10 R/W-0 IEC02 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 IEC25 R/W-0 IEC17 R/W-0 IEC09 R/W-0 IEC01 R/W-0 IEC24 R/W-0 IEC16 R/W-0 IEC08 R/W-0 IEC00 REGISTER 7-5:
Bit Bit Range 31:24 23:16 15:8 7:0 R/W-0 IEC31 R/W-0 IEC23 R/W-0 IEC15 R/W-0 IEC07 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 IEC31-IEC00: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit definitions. DS61168C-page 92 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX IPCx: INTERRUPT PRIORITY CONTROL REGISTER(1) Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IP03<2:0>
R/W-0 IP02<2:0>
R/W-0 IP01<2:0>
R/W-0 IP00<2:0>
R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 IS03<1:0>
R/W-0 R/W-0 IS02<1:0>
R/W-0 R/W-0 IS01<1:0>
R/W-0 R/W-0 IS00<1:0>
REGISTER 7-6:
Bit Bit Range 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as 0 bit 28-26 IP03<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS03<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpiority is 0 bit 23-21 Unimplemented: Read as 0 bit 20-18 IP02<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS02<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as 0 bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. 2011 Microchip Technology Inc. Preliminary DS61168C-page 93 PIC32MX1XX/2XX REGISTER 7-6:
bit 9-8 IPCx: INTERRUPT PRIORITY CONTROL REGISTER(1) (CONTINUED) bit 7-5 bit 4-2 bit 1-0 IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as 0 IP00<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS00<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. DS61168C-page 94 Preliminary 2011 Microchip Technology Inc. 8.0 OSCILLATOR CONFIGURATION PIC32MX1XX/2XX the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. Oscillator Configuration the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32).
(DS61112) in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The PIC32MX1XX/2XX oscillator system has the following modules and features:
A Total of four external and internal oscillator options as clock sources On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources On-Chip user-selectable divisor postscaler on select oscillator sources Software-controllable switching between various clock sources A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown Dedicated On-Chip PLL for USB peripheral A block diagram of the oscillator system is provided in Figure 8-1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 95 PIC32MX1XX/2XX FIGURE 8-1:
PIC32MX1XX/2XX FAMILY CLOCK DIAGRAM USB PLL(5) USB Clock (48 MHz) UFIN div x PLL x24 div 2 UFIN = 4 MHz UPLLIDIV<2:0>
UFRCEN UPLLEN REFCLKI System USB PLL 4 MHz FIN 5 MHz FIN PLL div x POSC FRC LPRC SOSC PBCLK SYSCLK FPLLIDIV<2:0>
COSC<2:0>
PLLMULT<2:0>
div y XTPLL, HSPLL, ECPLL, FRCPLL OE div N REFCLKO RODIV<14:0>
To SPI ROSEL<3:0>
Primary Oscillator
(POSC) OSC1 C1(3) XTAL RS(1) OSC2(4) C2(3) RF(2) To Internal Logic Enable div 2 To ADC PLLODIV<2:0>
div 16 FRC Oscillator 8 MHz typical TUN<5:0>
LPRC Oscillator Postscaler FRCDIV<2:0>
31.25 kHz typical Secondary Oscillator (SOSC) 32.768 kHz SOSCEN and FSOSCEN SOSCO SOSCI POSC (XT, HS, EC) Postscaler div x Peripherals PBCLK (TPB) PBDIV<1:0>
CPU and Select Peripherals SYSCLK FRC FRC/16 FRCDIV LPRC SOSC FSCM INT FSCM Event Clock Control Logic Fail-Safe Clock Monitor NOSC<2:0>
COSC<2:0>
FSCMEN<1:0>
OSWEN WDT, PWRT Timer1, RTCC Notes: 1. A series resistor, RS, may be required for AT strip cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 M. 2. 3. Refer to Section 6. Oscillator Configuration (DS61112) in the PIC32 Family Reference Manual for help in determining the best oscillator components. 4. PBCLK out is available on the OSC2 pin in certain clock modes. 5. USB PLL is available on PIC32MX2XX devices only. DS61168C-page 96 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-1:
Bit Bit Range 31/23/15/7 OSCCON: OSCILLATOR CONTROL REGISTER(1) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 U-0 R-0 R/W-y R/W-y R/W-y PLLODIV<2:0>
R-1 R/W-y R/W-y SOSCRDY PBDIVRDY R-0 R-0 COSC<2:0>
PBDIV<1:0>
R-0 U-0 R/W-0 CF CLKLOCK ULOCK(2) R-0 R-0 SLOCK R/W-0 SLPEN R/W-0 UFRCEN(2) R/W-y SOSCEN R/W-0 OSWEN Bit 25/17/9/1 R/W-0 FRCDIV<2:0>
R/W-y PLLMULT<2:0>
R/W-y NOSC<2:0>
Bit 24/16/8/0 R/W-1 R/W-y R/W-y R/W-0 R/W-y R/W-y Legend:
R = Readable bit
-n = Value at POR y = Value set from Configuration bits on POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as 0 bit 29-27 PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 Unimplemented: Read as 0 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary Oscillator is still warming up or is turned off PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV<1:0> bits can be written 0 = PBDIV<1:0> bits cannot be written bit 23 bit 22 bit 21 bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note 1: Writes to this register require an unlock sequence. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2: This bit is available on PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 97 PIC32MX1XX/2XX REGISTER 8-1:
bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits OSCCON: OSCILLATOR CONTROL REGISTER(1) 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 Unimplemented: Read as 0 bit 15 bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator Unimplemented: Read as 0 bit 11 bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):
1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):
Clock and PLL selections are never locked and may be modified. ULOCK: USB PLL Lock Status bit(2) 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: Writes to this register require an unlock sequence. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2: This bit is available on PIC32MX2XX devices only. DS61168C-page 98 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-1:
bit 2 OSCCON: OSCILLATOR CONTROL REGISTER(1) UFRCEN: USB FRC Clock Enable bit(2) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete bit 1 bit 0 Note 1: Writes to this register require an unlock sequence. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2: This bit is available on PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 99 PIC32MX1XX/2XX REGISTER 8-2:
Bit Bit Range 31/23/15/7 OSCTUN: FRC TUNING REGISTER(1) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 R-0 R-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 TUN<5:0>(2) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 y = Value set from Configuration bits on POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-6 Unimplemented: Read as 0 bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2) 100000 = Center frequency -12.5%
100001 =
111111 =
000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz) 000001 =
011110 =
011111 = Center frequency +12.5%
Note 1: Writes to this register require an unlock sequence. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested. DS61168C-page 100 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 SIDL U-0 RODIV<14:8>(3) R/W-0 R/W-0 RODIV<7:0>(3) R/W-0 R/W-0 OE RSLP(2) U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HC DIVSWEN R-0, HS, HC ACTIVE R/W-0 R/W-0 ROSEL<3:0>(1) HC = Hardware Clearable HS = Hardware Settable W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 8-3:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 R/W-0 R/W-0 ON U-0 Legend:
R = Readable bit
-n = Value at POR Unimplemented: Read as 0 bit 31 bit 30-16 RODIV<14:0> Reference Clock Divider bits(1) 111111111111111 = Output clock is source clock frequency divided by 65,534 111111111111110 = Output clock is source clock frequency divided by 65,532 000000000000010 = Output clock is source clock frequency divided by 4 000000000000001 = Output clock is source clock frequency divided by 2 000000000000000 = Output clock is same frequency as source clock (no divider) ON: Output Enable bit 1 = Reference Oscillator Module enabled 0 = Reference Oscillator Module disabled Unimplemented: Read as 0 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFCLKO pin 0 = Reference clock is not driven out on REFCLKO pin RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference Oscillator Module output continues to run in Sleep 0 = Reference Oscillator Module output is disabled in Sleep Unimplemented: Read as 0 DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete ACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active 0 = Reference clock request is not active bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is 1, as undefined behavior may result. 2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. 3: While the ON bit is set to 1, writes to these bits do not take effect until the DIVSWEN bit is also set to1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 101 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER PIC32MX1XX/2XX REGISTER 8-3:
bit 7-4 bit 3-0 Unimplemented: Read as 0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is 1, as undefined behavior may result. 2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. 3: While the ON bit is set to 1, writes to these bits do not take effect until the DIVSWEN bit is also set to1. DS61168C-page 102 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER(1,2) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 REGISTER 8-4:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 ROTRIM<0>
U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ROTRIM<8:1>
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR y = Value set from Configuration bits on POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to RODIV value 111111110 = 510/512 divisor added to RODIV value 100000000 = 256/512 divisor added to RODIV value 000000010 = 2/512 divisor added to RODIV value 000000001 = 1/512 divisor added to RODIV value 000000000 = 0/512 divisor added to RODIV value bit 22-0 Unimplemented: Read as 0 Note 1: While the ON bit (REFOCON<15>) is 1, writes to this register do not take effect until the DIVSWEN bit is also set to 1. 2: This register is not available on all devices. Refer to the specific device data sheet for availability. 2011 Microchip Technology Inc. Preliminary DS61168C-page 103 PIC32MX1XX/2XX NOTES:
DS61168C-page 104 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and destination Fixed priority channel arbitration Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining Flexible DMA requests:
- A DMA request can be selected from any of the peripheral interrupt sources
- Each channel can select any (appropriate) observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any of the peripheral interrupt sources
- Pattern (data) match transfer termination Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event Invalid DMA address generated
-
DMA debug support features:
- Most recent address accessed by a DMA channel
- Most recent DMA channel to transfer data CRC Generation module:
- CRC module can be assigned to any of the available channels
- CRC module is highly configurable 9.0 DIRECT MEMORY ACCESS
(DMA) CONTROLLER the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. Direct Memory Access (DMA) Controller
(DS61117) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The PIC32 Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32 (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, etc.) or memory itself. Following are some of the key features of the DMA controller module:
Four identical channels, each featuring:
- Auto-increment source and destination address registers
- Source and destination pointers
- Memory to memory and memory to peripheral transfers FIGURE 9-1:
DMA BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus Address Decoder Channel 0 Control SEL I0 Channel 1 Control Global Control
(DMACON) Channel n Control I1 I2 In Y Bus Interface Device Bus + Bus Arbitration L E S Channel Priority Arbitration 2011 Microchip Technology Inc. Preliminary DS61168C-page 105 PIC32MX1XX/2XX DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 SUSPEND DMABUSY U-0 U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 REGISTER 9-1:
Bit Bit Range 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) U-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as 0 SUSPEND: DMA Suspend bit bit 12 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally DMABUSY: DMA Module Busy bit(4) 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 11 bit 10-0 Unimplemented: Read as 0 Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 106 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX DMASTAT: DMA STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 RDWR DMACH<2:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 9-2:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR bit 31-4 Unimplemented: Read as 0 RDWR: Read/Write Status bit bit 3 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH<2:0>: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 9-3:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 R-0 R-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR DMAADDR: DMA ADDRESS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<31:24>
R-0 DMAADDR<23:16>
R-0 DMAADDR<15:8>
R-0 DMAADDR<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR<31:0>: DMA Module Address bits These bits contain the address of the most recent DMA access. 2011 Microchip Technology Inc. Preliminary DS61168C-page 107 PIC32MX1XX/2XX REGISTER 9-4:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 CRCEN Legend:
R = Readable bit
-n = Value at POR DCRCCON: DMA CRC CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 BYTO<1:0>
U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 WBO(1) U-0 R/W-0 U-0 U-0 U-0 R/W-0 PLEN<4:0>
U-0 U-0 R/W-0 R/W-0 BITO U-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCCH<2:0>
CRCAPP(1) CRCTYP W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as 0 bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits half-word) per half-word) 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered bit 27 bit 26-25 Unimplemented: Read as 0 bit 24 BITO: CRC Bit Order Selection bit(4) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as 0 bit 12-8 PLEN<4:0>: Polynomial Length bits(1) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused. bit 7 When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial 1. CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS61168C-page 108 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-4:
bit 6 DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the completes the DMA writes the calculated CRC value to the location given by CHxDSA destination bit 5 bit 4-3 bit 2-0 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC Unimplemented: Read as 0 CRCCH<2:0>: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. 2011 Microchip Technology Inc. Preliminary DS61168C-page 109 PIC32MX1XX/2XX REGISTER 9-5:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR DCRCDATA: DMA CRC DATA REGISTER Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24>
R/W-0 DCRCDATA<23:16>
R/W-0 DCRCDATA<15:8>
R/W-0 R/W-0 DCRCDATA<7:0>
R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA<31:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return 0 on any read. When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always 0. Data written to this register is converted and read back in 1s complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return 0 on any read. REGISTER 9-6:
Bit Bit Range 31/23/15/7 DCRCXOR: DMA CRCXOR ENABLE REGISTER(1,2,3) Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<31:24>
R/W-0 DCRCXOR<23:16>
R/W-0 R/W-0 DCRCXOR<15:8>
R/W-0 R/W-0 DCRCXOR<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register DS61168C-page 110 Preliminary 2011 Microchip Technology Inc. REGISTER 9-7:
Bit Bit Range DCHxCON: DMA CHANNEL x CONTROL REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 CHBUSY R/W-0 CHEN(2) U-0 U-0 U-0 R/W-0 CHAED U-0 U-0 U-0 R/W-0 CHCHN U-0 U-0 U-0 R/W-0 CHAEN U-0 U-0 U-0 U-0 PIC32MX1XX/2XX Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 CHCHNS(1) R/W-0 U-0 U-0 U-0 R-0 CHEDET CHPRI<1:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 CHBUSY: Channel Busy bit bit 15 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as 0 bit 8 bit 7 bit 6 bit bit 4 bit 3 bit 2 bit 1-0 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete Unimplemented: Read as 0 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). 2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. 2011 Microchip Technology Inc. Preliminary DS61168C-page 111 PIC32MX1XX/2XX REGISTER 9-8:
Bit Bit Range 31/23/15/7 DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 R/W-1 R/W-1 S-0 U-0 R/W-1 R/W-1 S-0 CFORCE CABORT U-0 R/W-1 R/W-1 R/W-0 PATEN U-0 U-0 R/W-1 R/W-1 CHAIRQ<7:0>(1) R/W-1 R/W-1 CHSIRQ<7:0>(1) R/W-0 R/W-0 SIRQEN AIRQEN U-0 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 U-0 Legend:
R = Readable bit
-n = Value at POR S = Settable bit W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as 0 bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a 1 0 = This bit always reads 0 CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a 1 0 = This bit always reads 0 PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 Note 1: See Table 7-1: Interrupt IRQ, Vector and Bit Location for the list of available interrupt IRQ sources. DS61168C-page 112 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 REGISTER 9-9:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF U-0 R/W-0 CHTAIE U-0 R/W-0 CHTAIF U-0 R/W-0 CHERIE U-0 R/W-0 CHERIF Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as 0 bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 6 bit 5 bit 15-8 Unimplemented: Read as 0 bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending 2011 Microchip Technology Inc. Preliminary DS61168C-page 113 PIC32MX1XX/2XX REGISTER 9-9:
bit 4 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED) pattern match event occurs CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a 0 = No interrupt is pending CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected 0 = No interrupt is pending Either the source or the destination address is invalid. bit 3 bit 2 bit 1 bit 0 DS61168C-page 114 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24>
R/W-0 CHSSA<23:16>
R/W-0 CHSSA<15:8>
R/W-0 CHSSA<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 9-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-0 R/W-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<31:24>
R/W-0 CHDSA<23:16>
R/W-0 CHDSA<15:8>
R/W-0 CHDSA<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. 2011 Microchip Technology Inc. Preliminary DS61168C-page 115 PIC32MX1XX/2XX REGISTER 9-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 CHSSIZ<15:8>
R/W-0 CHSSIZ<7:0>
R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHSSIZ<15:0>: Channel Source Size bits 1111111111111111 = 65,535 byte source size 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 9-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 CHDSIZ<15:8>
R/W-0 CHDSIZ<7:0>
R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS61168C-page 116 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER(1) Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Range U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 R-0 R-0 CHSPTR<15:8>
R-0 R-0 CHSPTR<7:0>
U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 Bit 24/16/8/0 U-0 U-0 R-0 R-0 31:24 23:16 15:8 7:0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source Note 1: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 9-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 R-0 R-0 CHDPTR<15:8>
R-0 R-0 CHDPTR<7:0>
U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination 2011 Microchip Technology Inc. Preliminary DS61168C-page 117 PIC32MX1XX/2XX REGISTER 9-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit Range U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 CHCSIZ<15:8>
R/W-0 CHCSIZ<7:0>
R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 9-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R-0 R-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 R-0 R-0 CHCPTR<15:8>
R-0 R-0 CHCPTR<7:0>
U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 U-0 U-0 R-0 R-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note 1: When in Pattern Detect mode, this register is reset on a pattern detect. DS61168C-page 118 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 CHPDAT<7:0>
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-0 CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match. All other modes:
Unused. 2011 Microchip Technology Inc. Preliminary DS61168C-page 119 PIC32MX1XX/2XX NOTES:
DS61168C-page 120 Preliminary 2011 Microchip Technology Inc. 10.0 USB ON-THE-GO (OTG) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. USB On-
The-Go (OTG) (DS61126) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA control-
ler, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 10-1. PIC32MX1XX/2XX The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communi-
cation. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the need for external signaling components. The register the CPU interface allows to configure and communicate with the module. The PIC32 USB module features:
USB Full-speed support for host and device Low-speed host support USB OTG support Integrated signaling resistors Integrated analog comparators for VBUS includes following the monitoring Note:
Integrated USB transceiver Transaction handshaking performed by hardware Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully and responsible satisfying licensing obligations. investigating applicable any for 2011 Microchip Technology Inc. Preliminary DS61168C-page 121 PIC32MX1XX/2XX FIGURE 10-1:
PIC32MX1XX/2XX FAMILY USB INTERFACE DIAGRAM FRC Oscillator 8 MHz Typical TUN<5:0>(3) Primary Oscillator
(POSC) UFIN(4) Div x PLL Div 2 UPLLIDIV(5) UFRCEN(2) UPLLEN(5) USB Module SRP Charge SRP Discharge USB Voltage Comparators 48 MHz USB Clock(6) Full Speed Pull-up Host Pull-down Low Speed Pull-up Transceiver SIE Registers and Control Interface Host Pull-down ID Pull-up DMA System RAM OSC1 OSC2 Bus D+(1) D-(1) ID(7) VBUSON(7) VUSB Transceiver Power 3.3V Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. Note 1:
2:
3:
4: USB PLL UFIN requirements: 4 MHz. 5:
6:
7:
This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS61168C-page 122 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit Range 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WC-0, HS IDIF R/WC-0, HS T1MSECIF R/WC-0, HS LSTATEIF R/WC-0, HS ACTVIF R/WC-0, HS SESVDIF R/WC-0, HS SESENDIF Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WC-0, HS VBUSVDIF Legend:
R = Readable bit
-n = Value at POR WC = Write 1 to clear W = Writable bit 1 = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No change in ID state detected T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected Unimplemented: Read as 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input detected 0 = No change on the session valid input detected bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 123 PIC32MX1XX/2XX REGISTER 10-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit Range U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 VBUSVDIE 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 IDIE Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt enabled 0 = ID interrupt disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt enabled 0 = Line state interrupt disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = ACTIVITY interrupt enabled 0 = ACTIVITY interrupt disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt enabled 0 = Session valid interrupt disabled SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt enabled 0 = B-session end interrupt disabled Unimplemented: Read as 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt enabled 0 = A-VBUS valid interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168C-page 124 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-3: U1OTGSTAT: USB OTG STATUS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-0 ID Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 LSTATE U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 SESVD SESEND U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 VBUSVD W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 6 bit 5 bit 31-8 Unimplemented: Read as 0 ID: ID Pin State Indicator bit bit 7 1 = No cable is attached or a type B cable has been plugged into the USB receptacle 0 = A type A OTG cable has been plugged into the USB receptacle Unimplemented: Read as 0 LSTATE: Line State Stable Indicator bit 1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms 0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms Unimplemented: Read as 0 SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device SESEND: B-Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device Unimplemented: Read as 0 VBUSVD: A-VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device bit 1 bit 0 bit 2 2011 Microchip Technology Inc. Preliminary DS61168C-page 125 PIC32MX1XX/2XX REGISTER 10-4: U1OTGCON: USB OTG CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168C-page 126 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-5: U1PWRC: USB POWER CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-0 UACTPND Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 USLPGRD USBBUSY U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 USUSPEND USBPWR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as 0 bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as 0 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode 0 = USB module operates normally USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) 2011 Microchip Technology Inc. Preliminary DS61168C-page 127 PIC32MX1XX/2XX REGISTER 10-6: U1IR: USB INTERRUPT REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 U-0 U-0 R-0 STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) U-0 U-0 U-0 R/WC-0, HS URSTIF(5) DETACHIF(6) Legend:
R = Readable bit
-n = Value at POR WC = Write 1 to clear W = Writable bit 1 = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode a STALL handshake was received during the handshake phase of the transaction In Device mode a STALL handshake was transmitted during the handshake phase of the transaction 0 = STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 s 0 = K-State is not observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for 2.5 s, and the current bus state is not SE0. 2: When not in Suspend mode, this interrupt should be disabled. 3: Clearing this bit will cause the STAT FIFO to advance. 4: Only error conditions enabled through the U1EIE register will set this bit. 5: Device mode. 6: Host mode. DS61168C-page 128 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-6: U1IR: USB INTERRUPT REGISTER (CONTINUED) bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected Note 1: This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for 2.5 s, and the current bus state is not SE0. 2: When not in Suspend mode, this interrupt should be disabled. 3: Clearing this bit will cause the STAT FIFO to advance. 4: Only error conditions enabled through the U1EIE register will set this bit. 5: Device mode. 6: Host mode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 129 PIC32MX1XX/2XX REGISTER 10-7: U1IE: USB INTERRUPT ENABLE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) U-0 U-0 U-0 R/W-0 URSTIE(2) DETACHIE(3) Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt enabled 0 = ATTACH interrupt disabled RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt enabled 0 = RESUME interrupt disabled IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt enabled 0 = Idle interrupt disabled TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt enabled 0 = TRNIF interrupt disabled SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt enabled 0 = SOFIF interrupt disabled UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt enabled 0 = USB Error interrupt disabled URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt enabled 0 = URSTIF interrupt disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt enabled 0 = DATTCHIF interrupt disabled Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. 2: Device mode. 3: Host mode. DS61168C-page 130 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit Range U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF R/WC-0, HS CRC5EF(3,4) EOFEF(5) R/WC-0, HS PIDEF 31:24 23:16 15:8 7:0 Legend:
R = Readable bit
-n = Value at POR WC = Write 1 to clear W = Writable bit 1 = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 5 bit 6 bit 31-8 Unimplemented: Read as 0 BTSEF: Bit Stuff Error Flag bit bit 7 1 = Packet rejected due to bit stuff error 0 = Packet accepted BMXEF: Bus Matrix Error Flag bit 1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid. 0 = No address error DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted bit 4 bit 3 bit 2 Note 1: This type of error occurs when the modules request for the DMA bus is not granted in time to service the modules demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. 2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. 3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. 4: Device mode. 5: Host mode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 131 PIC32MX1XX/2XX REGISTER 10-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(3,4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(5) 1 = EOF error condition detected 0 = No EOF error condition PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed bit 0 Note 1: This type of error occurs when the modules request for the DMA bus is not granted in time to service the modules demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. 2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. 3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. 4: Device mode. 5: Host mode. DS61168C-page 132 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE U-0 U-0 U-0 R/W-0 CRC5EE(2) EOFEE(3) U-0 U-0 U-0 R/W-0 PIDEE Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt enabled 0 = BTSEF interrupt disabled BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt enabled 0 = BMXEF interrupt disabled DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt enabled 0 = DMAEF interrupt disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt enabled 0 = BTOEF interrupt disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt enabled 0 = DFN8EF interrupt disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt enabled 0 = CRC16EF interrupt disabled CRC5EE: CRC5 Host Error Interrupt Enable bit(2) 1 = CRC5EF interrupt enabled 0 = CRC5EF interrupt disabled EOFEE: EOF Error Interrupt Enable bit(3) 1 = EOF interrupt enabled 0 = EOF interrupt disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt enabled 0 = PIDEF interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. 2: Device mode. 3: Host mode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 133 PIC32MX1XX/2XX REGISTER 10-10: U1STAT: USB STATUS REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-x Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x ENDPT<3:0>
U-0 U-0 U-0 R-x U-0 U-0 U-0 R-x DIR U-0 U-0 U-0 R-x PPBI U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) PPBI: Ping-Pong BD Pointer Indicator bit 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank bit 3 bit 2 bit 1-0 Unimplemented: Read as 0 Note 1: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is invalid when U1IR<TRNIF> = 0. DS61168C-page 134 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-x U-0 U-0 U-0 R-x U-0 U-0 U-0 R/W-0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 USBRST HOSTEN(2) RESUME(3) PPBRST U-0 U-0 U-0 R/W-0 USBEN(4) SOFEN(5) Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE detected on the USB 0 = No JSTATE detected SE0: Live Single-Ended Zero flag bit 1 = Single Ended Zero detected on the USB 0 = No Single Ended Zero detected PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token being executed by the USB module 0 = No token being executed USBRST: Module Reset bit(5) 1 = USB reset generated 0 = USB reset terminated HOSTEN: Host Mode Enable bit(2) 1 = USB host capability enabled 0 = USB host capability disabled RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling activated 0 = RESUME signaling disabled bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). 2: All host control logic is reset any time that the value of this bit is toggled. 3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. 4: Device mode. 5: Host mode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 135 PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 bit 0 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). 2: All host control logic is reset any time that the value of this bit is toggled. 3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. 4: Device mode. 5: Host mode. DS61168C-page 136 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 LSPDEN Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 DEVADDR<6:0>
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 LSPDEN: Low Speed Enable Indicator bit 1 = Next token command to be executed at Low Speed 0 = Next token command to be executed at Full Speed DEVADDR<6:0>: 7-bit USB Device Address bits bit 6-0 REGISTER 10-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 FRML<7:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. 2011 Microchip Technology Inc. Preliminary DS61168C-page 137 PIC32MX1XX/2XX REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 FRMH<2:0>
U-0 U-0 U-0 R-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as 0 bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 10-15: U1TOK: USB TOKEN REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 PID<3:0>(1) EP<3:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-4 PID<3:0>: Token Type Indicator bits(1) 0001 = OUT (TX) token type transaction 1001 = IN (RX) token type transaction 1101 = SETUP (TX) token type transaction Note: All other values are reserved and must not be used. EP<3:0>: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. bit 3-0 Note 1: All other values are reserved and must not be used. DS61168C-page 138 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 CNT<7:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-0 CNT<7:0>: SOF Threshold Value bits Typical values of the threshold are:
01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet REGISTER 10-17: U1BDTP1: USB BDT PAGE 1 REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 BDTPTRL<15:9>
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-1 BDTPTRL<15:9>: BDT Base Address bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. Unimplemented: Read as 0 bit 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 139 PIC32MX1XX/2XX REGISTER 10-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 BDTPTRH<23:16>
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-0 BDTPTRH<23:16>: BDT Base Address bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. REGISTER 10-19: U1BDTP3: USB BDT PAGE 3 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 BDTPTRU<31:24>
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7-0 BDTPTRU<31:24>: BDT Base Address bits This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS61168C-page 140 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 UTEYE U-0 U-0 U-0 R/W-0 UOEMON U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 USBSIDL U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 UASUSPND Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 bit 6 bit 5 bit 4 bit 3-1 bit 0 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test enabled 0 = Eye-Pattern Test disabled UOEMON: USB OE Monitor Enable bit 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive Unimplemented: Read as 0 USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
(U1PWRC<1>) in Register 10-5. USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock 2011 Microchip Technology Inc. Preliminary DS61168C-page 141 PIC32MX1XX/2XX REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 LSPD U-0 U-0 U-0 R/W-0 RETRYDIS U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as 0 bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled; hub required with PRE_PID RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NAKd transactions disabled 0 = Retry NAKd transactions enabled; retry done in hardware Unimplemented: Read as 0 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed Otherwise, this bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake enabled 0 = Endpoint Handshake disabled (typically used for isochronous endpoints) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168C-page 142 Preliminary 2011 Microchip Technology Inc. 11.0 I/O PORTS the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. I/O Ports
(DS61120) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX General purpose I/O pins are the simplest of peripher-
als. They allow the PIC MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module:
Individual output pin open-drain enable/disable Individual input pin weak pull-up and pull-down Monitor selective inputs and generate interrupt when change in pin state is detected Operation during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Figure 11-1 illustrates a block diagram of a typical multiplexed I/O port. FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data Q D CK EN Q ODC Q D CK EN Q TRIS Q D CK EN Q LAT I/O Cell 0 1 1 0 1 0 Output Multiplexers I/O Pin 1 0 Q Q D CK Q Q D CK Synchronization PIO Module RD ODC Data Bus SYSCLK WR ODC RD TRIS WR TRIS WR LAT WR PORT RD LAT RD PORT Sleep SYSCLK Peripheral Input Peripheral Input Buffer R Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. 2011 Microchip Technology Inc. Preliminary DS61168C-page 143 PIC32MX1XX/2XX Parallel I/O (PIO) Ports 11.1 All port pins have ten registers directly associated with their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an output. If the data direction bit is a 1, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. OPEN-DRAIN CONFIGURATION 11.1.1 In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of out-
puts higher than VDD (e.g., 5V) on any desired 5V-tol-
erant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the Pin Diagrams section for the available pins and their functionality. 11.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are analog (not digital) by default. If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module. When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. I/O PORT WRITE/READ TIMING 11.1.3 One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP. INPUT CHANGE NOTIFICATION 11.1.4 The input change notification function of the I/O ports allows the PIC32MX1XX/2XX devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state. Five control registers are associated with the CN func-
tionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. Note:
Pull-ups and pull-downs on change notifi-
cation pins should always be disabled when the port pin is configured as a digital output. An additional control register (CNCONx) is shown in Register 11-3. 11.2 CLR, SET and INV Registers Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as 1 are modified. Bits specified as 0 are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. DS61168C-page 144 Preliminary 2011 Microchip Technology Inc. Peripheral Pin Select 11.3 A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The chal-
lenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. Peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature oper-
ates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most dig-
ital peripherals to these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. AVAILABLE PINS 11.3.1 The number of available pins is dependent on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation RPn full pin designation, where RP designates a remappable peripheral and n is the remappable port number. their in AVAILABLE PERIPHERALS 11.3.2 The peripherals managed by the peripheral pin select are all digital-only peripherals. These include general serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs. In comparison, some digital-only peripheral modules are never included in the peripheral pin select feature. This is because the peripherals function requires spe-
cial I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all mod-
ules with analog inputs, such as the Analog-to-Digital Converter (ADC). A key difference between remappable and non-remap-
pable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. PIC32MX1XX/2XX When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 11.3.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately con-
trolled, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-select-
able pin is handled in two different ways, depending on whether an input or output is being mapped. INPUT MAPPING 11.3.4 The inputs of the peripheral pin select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 11-1, are used to configure peripheral input mapping (see Register 11-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 11-1. For example, Figure 11-2 illustrates the remappable pin selection for the U1RX input. FIGURE 11-2:
REMAPPABLE INPUT EXAMPLE FOR U1RX U1RXR<3:0>
RPA2 RPB6 RPA4 RPn Note:
0 1 2 n U1RX input to peripheral For input only, peripheral pin select functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to 1). 2011 Microchip Technology Inc. Preliminary DS61168C-page 145 PIC32MX1XX/2XX TABLE 11-1:
INPUT PIN SELECTION Peripheral Pin
[pin name]R SFR
[pin name]R bits
[pin name]R Value to RPn Pin Selection INT4 T2CK IC4 SS1 INT4R T2CKR IC4R SS1R INT4R<3:0>
T2CKR<3:0>
IC4R<3:0>
SS1R<3:0>
REFCLKI REFCLKIR REFCLKIR<3:0>
INT3 T3CK IC3 U1CTS U2RX SDI1 INT2 T4CK IC1 IC5 U1RX U2CTS SDI2 OCFB INT1 T5CK IC2 SS2 OCFA INT3R T3CKR IC3R U1CTSR U2RXR SDI1R INT2R T4CKR IC1R IC5R U1RXR U2CTSR SDI2R OCFBR INT1R T5CKR IC2R SS2R OCFAR INT3R<3:0>
T3CKR<3:0>
IC3R<3:0>
U1CTSR<3:0>
U2RXR<3:0>
SDI1R<3:0>
INT2R<3:0>
T4CKR<3:0>
IC1R<3:0>
IC5R<3:0>
U1RXR<3:0>
U2CTSR<3:0>
SDI2R<3:0>
OCFBR<3:0>
INT1R<3:0>
T5CKR<3:0>
IC2R<3:0>
SS2R<3:0>
OCFAR<3:0>
0000 = RPA0 0001 = RPB3 0010 = RPB4 0011 = RPB15 0100 = RPB7 0101 = RPC7 0110 = RPC0 0111 = RPC5 1000 = Reserved 1111 = Reserved 0000 = RPA1 0001 = RPB5 0010 = RPB1 0011 = RPB11 0100 = RPB8 0101 = RPA8 0110 = RPC8 0111 = RPA9 1000 = Reserved 1111 = Reserved 0000 = RPA2 0001 = RPB6 0010 = RPA4 0011 = RPB13 0100 = RPB2 0101 = RPC6 0110 = RPC1 0111 = RPC3 1000 = Reserved 1111 = Reserved 0000 = RPA3 0001 = RPB14 0010 = RPB0 0011 = RPB10 0100 = RPB9 0101 = RPC9 0110 = RPC2 0111 = RPC4 1000 = Reserved 1111 = Reserved DS61168C-page 146 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Control Register Lock 11.3.6.1 Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these regis-
ters, they must be unlocked in hardware. The regis-
ter lock is controlled by the IOLOCK Configuration bit
(CFGCON<13>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 6. Oscillator
(DS61112) in the PIC32 Family Reference Manual for details. Configuration Bit Select Lock 11.3.6.2 As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3<29>) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. OUTPUT MAPPING 11.3.5 In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 11-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripherals output is mapped to the pin (see Table 11-2 and Figure 11-3). A null output is associated with the output register reset value of 0. This is done to ensure that remappable outputs remain disconnected from all output pins by default. FIGURE 11-3:
EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPA0 RPA0R<3:0>
Default U1TX Output U1RTS Output 0 1 2 14 15 Output Data RPA0 11.3.6 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to the peripheral map:
Control register lock sequence Configuration bit select lock 2011 Microchip Technology Inc. Preliminary DS61168C-page 147 PIC32MX1XX/2XX TABLE 11-2: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPnR bits RPnR Value to Peripheral Selection RPA0 RPB3 RPB4 RPB15 RPB7 RPC7 RPC0 RPC5 RPA1 RPB5 RPB1 RPB11 RPB8 RPA8 RPC8 RPA9 RPA2 RPB6 RPA4 RPB13 RPB2 RPC6 RPC1 RPC3 RPA3 RPB14 RPB0 RPB10 RPB9 RPC9 RPC2 RPC4 RPA0R RPB3R RPB4R RPB15R RPB7R RPC7R RPC0R RPC5R RPA1R RPB5R RPB1R RPB11R RPB8R RPA8R RPC8R RPA9R RPA2R RPB6R RPA4R RPB13R RPB2R RPC6R RPC1R RPC3R RPA3R RPB14R RPB0R RPB10R RPB9R RPC9R RPC2R RPC4R RPA0R<3:0>
RPB3R<3:0>
RPB4R<3:0>
RPB15R<3:0>
RPB7R<3:0>
RPC7R<3:0>
RPC0R<3:0>
RPC5R<3:0>
RPA1R<3:0>
RPB5R<3:0>
RPB1R<3:0>
RPB11R<3:0>
RPB8R<3:0>
RPA8R<3:0>
RPC8R<3:0>
RPA9R<3:0>
RPA2R<3:0>
RPB6R<3:0>
RPA4R<3:0>
RPB13R<3:0>
RPB2R<3:0>
RPC6R<3:0>
RPC1R<3:0>
RPC3R<3:0>
RPA3R<3:0>
RPB14R<3:0>
RPB0R<3:0>
RPB10R<3:0>
RPB9R<3:0>
RPC9R<3:0>
RPC2R<3:0>
RPC4R<3:0>
0000 = No Connect 0001 = U1TX 0010 = U2RTS 0011 = SS1 0100 = Reserved 0101 = OC1 0110 = Reserved 0111 = C2OUT 1000 = Reserved 1111 = Reserved 0000 = No Connect 0001 = Reserved 0010 = Reserved 0011 = SDO1 0100 = SDO2 0101 = OC2 0110 = Reserved 1111 = Reserved 0000 = No Connect 0001 = Reserved 0010 = Reserved 0011 = SDO1 0100 = SDO2 0101 = OC4 0110 = OC5 0111 = REFCLKO 1000 = Reserved 1111 = Reserved 0000 = No Connect 0001 = U1RTS 0010 = U2TX 0011 = Reserved 0100 = SS2 0101 = OC3 0110 = Reserved 0111 = C1OUT 1000 = Reserved 1111 = Reserved DS61168C-page 148 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX
[pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER(1) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
[pin name]R<3:0>
U-0 U-0 U-0 R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 11-1:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR bit 31-4 Unimplemented: Read as 0 bit 3-0
[pin name]R<3:0>: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 11-1 for input pin selection values. Note 1: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0. REGISTER 11-2: RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 RPnR<3:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as 0 bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits See Table 11-2 for output pin selection values. Note 1: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 149 PIC32MX1XX/2XX REGISTER 11-3: CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A, B, C) Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Bit Range 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 SIDL U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Control bit 1 = CPU Idle Mode halts CN operation 0 = CPU Idle does not affect CN operation bit 14 bit 13 bit 12-0 Unimplemented: Read as 0 DS61168C-page 150 Preliminary 2011 Microchip Technology Inc. 12.0 TIMER1 the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. Timers
(DS61105) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. FIGURE 12-1:
TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-bit Comparator Reset TMR1 T1IF Event Flag 0 1 TGATE SOSCO/T1CK SOSCI SOSCEN D Q Q Gate Sync PBCLK PIC32MX1XX/2XX family of PIC32 devices This features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applica-
tions and counting external events. This timer can also be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications. The following modes are supported:
Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer 12.1 Additional Supported Features Selectable clock prescaler Timer operation during CPU Idle and Sleep mode Fast bit manipulation using CLR, SET and INV registers Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) Sync TSYNC 1 0 TGATE TCS ON x 1 1 0 0 0 Prescaler 1, 8, 64, 256 2 TCKPS<1:0>
Note 1: The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 151 PIC32MX1XX/2XX REGISTER 12-1:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 TGATE Legend:
R = Readable bit
-n = Value at POR T1CON: TYPE A TIMER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 SIDL R/W-0 U-0 U-0 R/W-0 TWDIS R/W-0 TCKPS<1:0>
U-0 U-0 R-0 TWIP U-0 U-0 U-0 U-0 R/W-0 TSYNC U-0 U-0 U-0 R/W-0 TCS U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode:
This bit is read as 0. bit 10-8 Unimplemented: Read as 0 bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1:
This bit is ignored. When TCS = 0:
1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled Unimplemented: Read as 0 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 14 bit 13 bit 12 bit 11 bit 6 bit 5-4 Note 1: When using 1:1 PBCmLK divisor, the users software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 152 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) REGISTER 12-1:
bit 3 bit 2 Unimplemented: Read as 0 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1:
1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0:
This bit is ignored. TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock Unimplemented: Read as 0 bit 1 bit 0 Note 1: When using 1:1 PBCmLK divisor, the users software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2011 Microchip Technology Inc. Preliminary DS61168C-page 153 PIC32MX1XX/2XX NOTES:
DS61168C-page 154 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes:
Synchronous internal 32-bit timer Synchronous internal 32-bit gated timer Synchronous external 32-bit timer Note:
In this chapter, references to registers, TxCON, TMRx and PRx, use x to repre-
sent Timer2 through 5 in 16-bit modes. In 32-bit modes, x represents Timer2 or 4;
y represents Timer3 or 5. 13.1 Additional Supported Features Selectable clock prescaler Timers operational during CPU idle Time base for Input Capture and Output Compare modules (Timer2 and Timer3 only) ADC event trigger (Timer3 only) Fast bit manipulation using CLR, SET and INV registers 13.0 TIMER2/3, TIMER4/5 the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. Timers
(DS61105) of PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. This family of PIC32 devices features four synchronous 16-bit timers (default) that can operate as a free-
running interval timer for various timing applications and counting external events. The following modes are supported:
Synchronous internal 16-bit timer Synchronous internal 16-bit gated timer Synchronous external 16-bit timer FIGURE 13-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) TMRx Sync ADC Event Trigger(1) TxIF Event Flag 0 1 TGATE TxCK Comparator x 16 PRx Equal Reset D Q Q Gate Sync PBCLK TGATE TCS ON Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS x 1 1 0 0 0 Note 1:
ADC event trigger is available on Timer3 only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 155 PIC32MX1XX/2XX FIGURE 13-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) Reset TMRy TMRx MS Half Word LS Half Word Equal 32-bit Comparator ADC Event Trigger(2) Sync TyIF Event Flag 0 1 TGATE TxCK PRy PRx D Q Q Gate Sync PBCLK x 1 1 0 0 0 TGATE TCS ON Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1:
In this diagram, the use of x in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of y in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. 2: ADC event trigger is available only on the Timer2/3 pair. DS61168C-page 156 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TXCON: TYPE B TIMER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 REGISTER 13-1:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1,3) R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 SIDL(4) R/W-0 U-0 U-0 U-0 R/W-0 TGATE(3) TCKPS<2:0>(3) U-0 U-0 U-0 R/W-0 T32(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TCS(3) U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 bit 14 bit 13 bit 12-8 bit 7 bit 6-4 ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit(4) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode Unimplemented: Read as 0 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1:
This bit is ignored and is read as 0. When TCS = 0:
1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS<2:0>: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit is available only on even numbered timers (Timer2 and Timer4). 3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. 4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 157 PIC32MX1XX/2XX REGISTER 13-1:
bit 3 TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer Unimplemented: Read as 0 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock Unimplemented: Read as 0 bit 2 bit 1 bit 0 Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit is available only on even numbered timers (Timer2 and Timer4). 3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. 4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. DS61168C-page 158 Preliminary 2011 Microchip Technology Inc. 14.0 INPUT CAPTURE the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 15. Input sheet, refer Capture (DS61122) of the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events:
PIC32MX1XX/2XX 1. Simple capture event modes
- Capture timer value on every falling edge of input at ICx pin
- Capture timer value on every rising edge of input at ICx pin 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler capture event modes
- Capture timer value on every 4th rising edge of input at ICx pin
- Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include:
Device wake-up from capture pin during CPU Sleep and Idle modes Interrupt on input capture event 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled Input capture can also be used to provide additional sources of external interrupts FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM FEDGE ICM<2:0>
ICx pin 110 101 100 011 010 001 Specified/Every Edge Mode Prescaler Mode
(16th Rising Edge) Prescaler Mode
(4th Rising Edge) Rising Edge Mode Falling Edge Mode Edge Detection Mode Sleep/Idle Wake-up Mode TMR2 TMR3 C32/ICTMR CaptureEvent FIFO CONTROL To CPU ICxBUF FIFO ICI<1:0>
ICM<2:0>
/N Set Flag ICxIF
(In IFSx Register) 001 111 Note: An x in a signal, register or bit name denotes the number of the capture channel. 2011 Microchip Technology Inc. Preliminary DS61168C-page 159 PIC32MX1XX/2XX REGISTER 14-1:
ICXCON: INPUT CAPTURE X CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 ICTMR U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 SIDL R/W-0 ICI<1:0>
U-0 U-0 U-0 R-0 ICOV U-0 U-0 U-0 R-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 FEDGE R/W-0 U-0 U-0 R/W-0 C32 R/W-0 ICBNE ICM<2:0>
Legend:
R = Readable bit
-n = Bit Value at POR: (0, 1, x = unknown) W = Writable bit U = Unimplemented bit P = Programmable bit r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 bit 4 bit 3 Unimplemented: Read as 0 ON: Input Capture Module Enable bit(1) 1 = Module enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications Unimplemented: Read as 0 SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode Unimplemented: Read as 0 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110) 1 = Capture rising edge first 0 = Capture falling edge first C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is 1) 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture ICI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 160 Preliminary 2011 Microchip Technology Inc. REGISTER 14-1:
bit 2-0 PIC32MX1XX/2XX ICXCON: INPUT CAPTURE X CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode every sixteenth rising edge 100 = Prescaled Capture Event mode every fourth rising edge 011 = Simple Capture Event mode every rising edge 010 = Simple Capture Event mode every falling edge 001 = Edge Detect mode every edge (rising and falling) 000 = Input Capture module is disabled Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2011 Microchip Technology Inc. Preliminary DS61168C-page 161 PIC32MX1XX/2XX NOTES:
DS61168C-page 162 Preliminary 2011 Microchip Technology Inc. 15.0 OUTPUT COMPARE the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. Output Compare (DS61111) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX The Output Compare module (OCMP) is used to gen-
erate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. The following are some of the key features:
Multiple Output Compare Modules in a device Programmable interrupt generation on compare event Single and Dual Compare modes Single and continuous output pulse generation Pulse-Width Modulation (PWM) mode Hardware-based PWM Fault detection and automatic output disable Programmable selection of 16-bit or 32-bit time bases Can operate from either of two available 16-bit time bases or a single 32-bit time base FIGURE 15-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Comparator Output Logic 3 OCM<2:0>
Mode Select QS R OCx(1) Output Enable Output Enable Logic OCFA or OCFB(2) 0 1 OCTSEL 0 1 16 16 Timer2 Timer3 Timer2 Rollover Timer3 Rollover Note 1: Where x is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 2011 Microchip Technology Inc. Preliminary DS61168C-page 163 PIC32MX1XX/2XX REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 SIDL R/W-0 OC32 U-0 U-0 U-0 R-0 OCFLT(2) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 OCTSEL OCM<2:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 4 bit 3 bit 2-0 bit 31-16 Unimplemented: Read as 0 bit 15 ON: Output Compare Peripheral On bit(1) 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode bit 12-6 Unimplemented: Read as 0 bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this OCMP module 0 = Timer2 is the clock source for this OCMP module OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit is only used when OCM<2:0> = 111. It is read as 0 in all other modes. DS61168C-page 164 Preliminary 2011 Microchip Technology Inc. 16.0 SERIAL PERIPHERAL INTERFACE (SPI) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 23. Serial sheet, refer Peripheral Interface (SPI) (DS61106) in the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola SPI and SIOP interfaces. Some of the key features of the SPI module are:
Master and Slave modes support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer Operation during CPU Sleep and Idle mode Audio Codec Support:
I2S protocol
-
- Left-justified
- Right-justified
- PCM FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM Internal Data Bus FIFOs Share Address SPIxBUF SPIxBUF Read Write SPIxRXB FIFO SPIxTXB FIFO Transmit Receive SPIxSR bit 0 Slave Select and Frame Sync Control Shift Control Clock Control Edge Select MCLKSEL Baud Rate Generator MSTEN REFCLK PBCLK SDIx SDOx SSx/FSYNC SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. 2011 Microchip Technology Inc. Preliminary DS61168C-page 165 PIC32MX1XX/2XX REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 31:24 23:16 15:8 7:0 R/W-0 FRMEN R/W-0 R/W-0 FRMSYNC FRMPOL R/W-0 MSSEN R/W-0 MCLKSEL(2) R/W-0 ON(1) R/W-0 SSEN U-0 U-0 R/W-0 CKP U-0 R/W-0 SIDL R/W-0 MSTEN U-0 R/W-0 DISSDO R/W-0 DISSDI Bit 27/19/11/3 R/W-0 FRMSYPW U-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FRMCNT<2:0>
R/W-0 ENHBUF(2) R/W-0 SPIFE R/W-0 SMP R/W-0 R/W-0 CKE(3) R/W-0 SRXISEL<1:0>
MODE32 MODE16 R/W-0 R/W-0 STXISEL<1:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in 0 = Slave select SPI support is disabled. FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide Master mode. Polarity is determined by the FRMPOL bit. bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode. 111 = Reserved; do not use 110 = Reserved; do not use 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character MCLKSEL: Master Clock Enable bit(2) 1 = REFCLK is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as 0 bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 31 bit 30 bit 29 bit 28 bit 27 bit 23 Note 1: When using the 1:1 PBCLK divisor, the users software should not read or write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to 0 for the Framed SPI mode (FRMEN = 1). DS61168C-page 166 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 15 bit 14 bit 13 bit 12 bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits When AUDEN = 1:
MODE32 MODE16 When AUDEN = 0:
MODE32 MODE16 1 1 0 0 1 0 0 1 0 1 0 x 1 0 Communication 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame Communication 32-bit 16-bit 8-bit bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module Note 1: When using the 1:1 PBCLK divisor, the users software should not read or write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to 0 for the Framed SPI mode (FRMEN = 1). 2011 Microchip Technology Inc. Preliminary DS61168C-page 167 PIC32MX1XX/2XX REGISTER 16-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) Note 1: When using the 1:1 PBCLK divisor, the users software should not read or write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: This bit can only be written when the ON bit = 0. 3: This bit is not used in the Framed SPI mode. The user should program this bit to 0 for the Framed SPI mode (FRMEN = 1). DS61168C-page 168 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-2: SPIxCON2: SPI CONTROL REGISTER 2 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 SPISGNEXT R/W-0 AUDEN(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR U-0 R/W-0 AUDMONO(1,2) U-0 R/W-0 R/W-0 AUDMOD<1:0>(1,2) Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extened bit 14-13 Unimplemented: Read as 0 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 3 bit 2 bit 1-0 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun Generates Error Events 0 = Transmit Underrun Does Not Generates Error Events IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data 0 = A ROV is a critical error which stop SPI operation IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stop SPI operation AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol enabled 0 = Audio protocol disabled Unimplemented: Read as 0 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo Unimplemented: Read as 0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: This bit can only be written when the ON bit = 0. 2: This bit is only valid for AUDEN = 1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 169 PIC32MX1XX/2XX REGISTER 16-3: SPIxSTAT: SPI STATUS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R-0 SRMT SPIROV SPIRBE R-0 R-0 R/C-0, HS FRMERR U-0 R-0 RXBUFELM<4:0>
R-0 TXBUFELM<4:0>
R-0 R-0 R-0 SPIBUSY R-1 SPITBE U-0 U-0 R-0 R-0 U-0 R-0 R-0 R-0 R-0 SPITUR R-0 SPITBF SPIRBF Legend:
R = Readable bit
-n = Value at POR C = Clearable bit W = Writable bit 1 = Bit is set HS = Set in hardware U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as 0 bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as 0 bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as 0 bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error detected 0 = No Frame error detected This bit is only valid when FRMEN = 1. SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as 0 bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module. SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software. SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) Unimplemented: Read as 0 the SPIxBUF register. bit 11 bit 7 bit 6 bit 5 bit 4 DS61168C-page 170 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-3: SPIxSTAT: SPI STATUS REGISTER bit 3 bit 2 bit 1 bit 0 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. Unimplemented: Read as 0 SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise 2011 Microchip Technology Inc. Preliminary DS61168C-page 171 PIC32MX1XX/2XX NOTES:
DS61168C-page 172 Preliminary 2011 Microchip Technology Inc. 17.0 INTER-INTEGRATED CIRCUIT (I2C) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 24. Inter-
sheet, refer Integrated Circuit (I2C) (DS61116) in the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 17-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features:
I2C interface supporting both master and slave I2C Slave mode supports 7-bit and 10-bit addressing I2C Master mode supports 7-bit and 10-bit operation addressing I2C port allows bidirectional transfers between master and slaves Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) I2C supports multi-master operation; detects bus collision and arbitrates accordingly Provides support for address bit masking 2011 Microchip Technology Inc. Preliminary DS61168C-page 173 PIC32MX1XX/2XX FIGURE 17-1:
I2C BLOCK DIAGRAM SCLx SDAx Shift Clock I2CxRCV I2CxRSR LSB Internal Data Bus Read Match Detect Address Match Write I2CxMSK Write Read i c g o L l o r t n o C I2CxSTAT I2CxCON I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN Reload Control LSB Shift Clock BRG Down Counter I2CxBRG PBCLK Read Write Read Write Read Write Read Write Read DS61168C-page 174 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX I2CXCON: I2C CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 STREN U-0 U-0 R/W-0 SIDL R/W-0 ACKDT U-0 U-0 R/W-1, HC SCLREL R/W-0, HC ACKEN U-0 U-0 R/W-0 STRICT R/W-0, HC RCEN U-0 U-0 R/W-0 A10M R/W-0, HC PEN U-0 U-0 R/W-0 DISSLW R/W-0, HC RSEN U-0 U-0 R/W-0 SMEN R/W-0, HC SEN HC = Cleared in Hardware W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown REGISTER 17-1:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 GCEN Legend:
R = Readable bit
-n = Value at POR bit 31-16 Unimplemented: Read as 0 bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1:
Bit is R/W (i.e., software can write 0 to initiate stretch and write 1 to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0:
Bit is R/S (i.e., software can only write 1 to release clock). Hardware clear at beginning of slave transmission. STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate 0 = Strict I2C Reserved Address Rule not enabled A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds addresses in reserved address space. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2011 Microchip Technology Inc. Preliminary DS61168C-page 175 PIC32MX1XX/2XX REGISTER 17-1:
bit 7 I2CXCON: I2C CONTROL REGISTER (CONTINUED)
(module is enabled for reception) GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress Hardware clear at end of master Acknowledge sequence. master Repeated Start sequence. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 176 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX I2CXSTAT: I2C STATUS REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 REGISTER 17-2:
Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 R-0, HSC ACKSTAT R/C-0, HS IWCOL R-0, HSC TRSTAT R/C-0, HS I2COV U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC D_A R/C-0, HSC R/C-0, HSC P S U-0 U-0 U-0 U-0 U-0 U-0 R/C-0, HS BCL R-0, HSC R_W R-0, HSC GCSTAT R-0, HSC RBF R-0, HSC ADD10 R-0, HSC TBF Legend:
R = Readable bit
-n = Value at POR HS = Set in hardware W = Writable bit 1 = Bit is set HSC = Hardware set/cleared U = Unimplemented bit, read as 0 0 = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as 0 bit 15 ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as 0 bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 14 bit 9 bit 8 bit 7 bit 6 bit 5 2011 Microchip Technology Inc. Preliminary DS61168C-page 177 PIC32MX1XX/2XX REGISTER 17-2:
bit 4 I2CXSTAT: I2C STATUS REGISTER (CONTINUED) P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read indicates data transfer is output from slave 0 = Write indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. bit 3 bit 2 bit 1 bit 0 DS61168C-page 178 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX The primary features of the UART module are:
Full-duplex, 8-bit or 9-bit data transmission Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 38 bps to 10 Mbps at 40 MHz 8-level deep First-In-First-Out (FIFO) transmit data buffer 8-level deep FIFO receive data buffer Parity, framing and buffer overrun error detection Support for interrupt-only on address detect
(9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support LIN Protocol support IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 18-1 illustrates a simplified block diagram of the UART. 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
(UART) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. Universal Asynchronous Receiver Transmitter
(UART) (DS61107) in the PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The UART module is one of the serial I/O modules available in PIC32MX1XX/2XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN and IrDA. The module also sup-
ports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter UxRTS/BCLKx UxCTS UxRX UxTX Note:
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information. 2011 Microchip Technology Inc. Preliminary DS61168C-page 179 PIC32MX1XX/2XX REGISTER 18-1: UxMODE: UARTx MODE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 WAKE U-0 U-0 U-0 R/W-0 LPBACK U-0 U-0 R/W-0 SIDL R/W-0 ABAUD U-0 U-0 R/W-0 IREN R/W-0 RXINV U-0 U-0 R/W-0 RTSMD R/W-0 BRGH U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 UEN<1:0>
R/W-0 PDSEL<1:0>
R/W-0 STSEL Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx control bits registers; UARTx power consumption is minimal Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode Unimplemented: Read as 0 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by in the PORTx register in the PORTx register corresponding bits in the PORTx register bit 7 bit 6 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up enabled 0 = Wake-up disabled LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 180 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 cleared by hardware upon completion ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character requires reception of Sync character (0x55);
0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is 0 0 = UxRX Idle state is 1 BRGH: High Baud Rate Enable bit 1 = High-Speed mode 4x baud clock enabled 0 = Standard Speed mode 16x baud clock enabled PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit bit 4 bit 3 bit 2-1 bit 0 Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2011 Microchip Technology Inc. Preliminary DS61168C-page 181 PIC32MX1XX/2XX REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 31:24 23:16 15:8 7:0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UTXISEL<1:0>
R/W-0 R/W-0 URXISEL<1:0>
U-0 R/W-0 R/W-0 UTXINV R/W-0 ADDEN U-0 R/W-0 U-0 R/W-0 ADDR<7:0>
R/W-0 URXEN R-1 RIDLE R/W-0 UTXBRK R-0 PERR U-0 R/W-0 R/W-0 UTXEN R-0 FERR U-0 R/W-0 R-0 UTXBF R/W-0 OERR Bit 24/16/8/0 R/W-0 ADM_EN R/W-0 R-1 TRMT R-0 URXDA Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as 0 bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR<7:0>: Automatic Address Mask bits When the ADM_EN bit is 1, this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is 0):
1 = UxTX Idle state is 0 0 = UxTX Idle state is 1 If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is 1):
1 = IrDA encoded UxTX Idle state is 1 0 = IrDA encoded UxTX Idle state is 0 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port. UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve 0 bits, followed by Stop bit; cleared by 0 = Break transmission is disabled or completed UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is con-
hardware upon completion trolled by port. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 DS61168C-page 182 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 183 PIC32MX1XX/2XX Figure 18-2 and Figure 18-3 illustrate typical receive and transmit timing for the UART module. FIGURE 18-2:
UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13 Cleared by Software Cleared by Software Cleared by Software Read to UxRXREG UxRX RIDLE OERR UxRXIF URXISEL = 00 UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 18-3:
TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF TSR Pull from Buffer Start Bit 0 Bit 1 Stop Start Bit 1 Write to UxTXREG BCLK/16
(Shift Clock) UxTX UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS61168C-page 184 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Key features of the PMP module include:
Fully multiplexed address/data mode Demultiplexed or partially multiplexed address/
data mode
- up to 11 address lines with single chip select
- up to 12 address lines without chip select One Chip Select Line Programmable Strobe Options
-
Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe Address Auto-Increment/Auto-Decrement Programmable Address/Data Multiplexing Programmable Polarity on Control Signals Legacy Parallel Slave Port Support Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer Programmable Wait States Selectable Input Voltage Levels 19.0 PARALLEL MASTER PORT
(PMP) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. Parallel Master Port (PMP) (DS61128) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The PMP is a parallel 8-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. FIGURE 19-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PIC32MX1XX/2XX Parallel Master Port Address Bus Data Bus Control Lines Up to 12-bit Address Flash EEPROM SRAM Microcontroller LCD FIFO Buffer 8-bit Data (with or without multiplexed addressing) PMA<0>
PMALL PMA<1>
PMALH PMA<10:2>
PMA<14>
PMCS1 PMRD PMRD/PMWR PMWR PMENB PMD<7:0>
2011 Microchip Technology Inc. Preliminary DS61168C-page 185 PIC32MX1XX/2XX REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 U-0 U-0 U-0 R/W-0 CSF<1:0>(2) U-0 U-0 R/W-0 SIDL R/W-0 ALP(2) U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 ADRMUX<1:0>
U-0 R/W-0 CS1P(2) PMPTTL PTWREN PTRDEN U-0 R/W-0 WRSP R/W-0 RDSP Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 10 bit 9 bit 8 bit 7-6 bit 5 bit 31-16 Unimplemented: Read as 0 bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits PMA<14>
11 = Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and 00 = Address and data appear on separate pins PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled CSF<1:0>: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 function as Chip Select 01 = PMCS1 functions as address bit 14 00 = PMCS1 function as address bit 14 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS61168C-page 186 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as 0 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) Unimplemented: Read as 0 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11):
1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11):
1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. 2011 Microchip Technology Inc. Preliminary DS61168C-page 187 PIC32MX1XX/2XX REGISTER 19-2: PMMODE: PARALLEL PORT MODE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 BUSY R/W-0 R/W-0 WAITB<1:0>(1) IRQM<1:0>
R/W-0 INCM<1:0>
R/W-0 R/W-0 WAITM<3:0>(1) U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 MODE<1:0>
R/W-0 R/W-0 WAITE<1:0>(1) Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only) bit 12-11 INCM<1:0>: Increment Mode bits bit 10 bit 9-8 11 = Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00 only) 10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2) 00 = No increment or decrement of address Unimplemented: Read as 0 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. DS61168C-page 188 Preliminary 2011 Microchip Technology Inc. REGISTER 19-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) PIC32MX1XX/2XX 1111 = Wait of 16 TPB 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) For Read operations:
11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. 2011 Microchip Technology Inc. Preliminary DS61168C-page 189 PIC32MX1XX/2XX REGISTER 19-3: PMADDR: PARALLEL PORT ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R/W-0 CS1 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 ADDR<10:8>
R/W-0 R/W-0 R/W-0 ADDR<7:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as 0 bit 14 CS1: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (pin functions as PMA<14>) bit 13-11 Unimplemented: Read as 0 bit 10-0 ADDR<10:0>: Destination Address bits DS61168C-page 190 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 19-4: PMAEN: PARALLEL PORT PIN ENABLE REGISTER(1,2) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 PTEN14 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 PTEN<10:8>
R/W-0 R/W-0 R/W-0 PTEN<7:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as 0 bit 15-14 PTEN14: PMCS1 Strobe Enable bits 1 = PMA14 functions as either PMA14 or PMCS1(1) 0 = PMA14 functions as port I/O bit 13-11 Unimplemented: Read as 0 bit 10-2 PTEN<10:2>: PMP Address Port Enable bits bit 1-0 1 = PMA<10:2> function as PMP address lines 0 = PMA<10:2> function as port I/O PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads functions as port I/O Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register. 2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register. 2011 Microchip Technology Inc. Preliminary DS61168C-page 191 PIC32MX1XX/2XX REGISTER 19-5: PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R-0 IBF R-1 OBE U-0 U-0 R/W-0, HSC IBOV R/W-0, HSC OBUF U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 IB3F R-1 U-0 U-0 R-0 IB2F R-1 U-0 U-0 R-0 IB1F R-1 U-0 U-0 R-0 IB0F R-1 OB3E OB2E OB1E OB0E Legend:
R = Readable bit
-n = Value at POR HSC = Set by Hardware; Cleared by Software W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 IBF: Input Buffer Full Status bit bit 15 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred bit 14 bit 13-12 Unimplemented: Read as 0 bit 11-8 IBxF: Input Buffer x Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as 0 OBxE: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted bit 7 bit 6 bit 5-4 bit 3-0 DS61168C-page 192 Preliminary 2011 Microchip Technology Inc. 20.0 REAL-TIME CLOCK AND CALENDAR (RTCC) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. Real-Time
(RTCC) Clock
(DS61125) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). Calendar the the Microchip and in web 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The PIC32 RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. FIGURE 20-1:
RTCC BLOCK DIAGRAM 32.768 kHz Input from Secondary Oscillator (SOSC) CAL<9:0>
RTCC Prescalers 0.5s RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter PIC32MX1XX/2XX Following are some of the key features of this module:
Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: 0.66 seconds error per month Calibrates up to 260 ppm of crystal error Requirements: External 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin RTCVAL ALRMVAL RTCTIME HR, MIN, SEC RTCDATE YEAR, MONTH, DAY, WDAY ALRMTIME HR, MIN, SEC ALRMDATE MONTH, DAY, WDAY RTCC Interrupt Logic Set RTCC Flag 0 1 Alarm Pulse Seconds Pulse RTCC RTSECSEL RTCOE 2011 Microchip Technology Inc. Preliminary DS61168C-page 193 PIC32MX1XX/2XX REGISTER 20-1: RTCCON: RTC CONTROL REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 R/W-0 U-0 R/W-0 R/W-0 ON(2,3) R/W-0 U-0 R-0 RTSECSEL(4) RTCCLKON U-0 R/W-0 R/W-0 SIDL U-0 U-0 R/W-0 U-0 R/W-0 CAL<7:0>
U-0 R/W-0 R/W-0 R/W-0 CAL<9:8>
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 RTCWREN(5) RTCSYNC HALFSEC(6) RTCOE U-0 R-0 U-0 R-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as 0 bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute 1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute ON: RTCC On bit(2,3) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode bit 12-8 Unimplemented: Read as 0 bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit(4) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Unimplemented: Read as 0 bit 15 bit 14 bit 13 bit 6 bit 5-4 Note 1: This register is reset only on a Power-on Reset (POR). 2: The ON bit is only writable when RTCWREN = 1. 3: When using the 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 4: Requires RTCOE = 1 (RTCCON<0>) for the output to be active. 5: The RTCWREN bit can be set only when the write sequence is enabled. 6: This bit is read-only. It is cleared to 0 on a write to the seconds bit fields (RTCTIME<14:8>). DS61168C-page 194 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-1: RTCCON: RTC CONTROL REGISTER(1) (CONTINUED) bit 3 If the register is read twice and results in the same data, the data can be assumed to be valid RTCWREN: RTC Value Registers Write Enable bit(5) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read 0 = RTC Value registers can be read without concern about a rollover ripple HALFSEC: Half-Second Status bit(6) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled clock presented onto an I/O 0 = RTCC clock output disabled bit 2 bit 1 bit 0 Note 1: This register is reset only on a Power-on Reset (POR). 2: The ON bit is only writable when RTCWREN = 1. 3: When using the 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 4: Requires RTCOE = 1 (RTCCON<0>) for the output to be active. 5: The RTCWREN bit can be set only when the write sequence is enabled. 6: This bit is read-only. It is cleared to 0 on a write to the seconds bit fields (RTCTIME<14:8>). 2011 Microchip Technology Inc. Preliminary DS61168C-page 195 PIC32MX1XX/2XX REGISTER 20-2: RTCALRM: RTC ALARM CONTROL REGISTER(1) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 ALRMEN(2,3) CHIME(3) R/W-0 R/W-0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 PIV(3) R/W-0 U-0 U-0 R-0 ALRMSYNC(4) U-0 U-0 R/W-0 R/W-0 ARPT<7:0>(3) R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AMASK<3:0>(3) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 14 bit 31-16 Unimplemented: Read as 0 ALRMEN: Alarm Enable bit(2,3) bit 15 1 = Alarm is enabled 0 = Alarm is disabled CHIME: Chime Enable bit(3) 1 = Chime is enabled ARPT<7:0> is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled ARPT<7:0> stops once it reaches 0x00 PIV: Alarm Pulse Initial Value bit(3) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. ALRMSYNC: Alarm Sync bit(4) 1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. bit 13 bit 12 The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved; do not use 1011 = Reserved; do not use 11xx = Reserved; do not use Note 1: This register is reset only on a Power-on Reset (POR). 2: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. 3: This field should not be written when the RTCC ON bit = 1 (RTCCON<15>) and ALRMSYNC = 1. 4: This assumes a CPU read will execute in less than 32 PBCLKs. DS61168C-page 196 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-2: RTCALRM: RTC ALARM CONTROL REGISTER(1) (CONTINUED) bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(3) 11111111 = Alarm will trigger 256 times 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: This register is reset only on a Power-on Reset (POR). 2: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. 3: This field should not be written when the RTCC ON bit = 1 (RTCCON<15>) and ALRMSYNC = 1. 4: This assumes a CPU read will execute in less than 32 PBCLKs. 2011 Microchip Technology Inc. Preliminary DS61168C-page 197 PIC32MX1XX/2XX REGISTER 20-3: RTCTIME: RTC TIME VALUE REGISTER(1) Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-x R/W-x R/W-x U-0 Legend:
R = Readable bit
-n = Value at POR R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0>
HR01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MIN10<3:0>
MIN01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEC10<3:0>
U-0 U-0 SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as 0 Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>). DS61168C-page 198 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-4: RTCDATE: RTC DATE VALUE REGISTER(1) Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-x R/W-x R/W-x U-0 Legend:
R = Readable bit
-n = Value at POR R/W-x R/W-x YEAR10<3:0>
R/W-x R/W-x MONTH10<3:0>
R/W-x R/W-x DAY10<3:0>
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR01<3:0>
R/W-x R/W-x MONTH01<3:0>
R/W-x R/W-x DAY01<3:0>
R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x WDAY01<3:0>
W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9 bit 7-4 bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6 Unimplemented: Read as 0 Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>). 2011 Microchip Technology Inc. Preliminary DS61168C-page 199 PIC32MX1XX/2XX REGISTER 20-5: ALRMTIME: ALARM TIME VALUE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-x R/W-x R/W-x U-0 Legend:
R = Readable bit
-n = Value at POR R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0>
HR01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MIN10<3:0>
MIN01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEC10<3:0>
U-0 U-0 SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as 0 DS61168C-page 200 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-6: ALRMDATE: ALARM DATE VALUE REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 R/W-x R/W-x U-0 Legend:
R = Readable bit
-n = Value at POR U-0 R/W-x U-0 R/W-x MONTH10<3:0>
R/W-x DAY10<1:0>
U-0 U-0 R/W-x U-0 R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x MONTH01<3:0>
R/W-x R/W-x DAY01<3:0>
R/W-x R/W-x WDAY01<3:0>
U-0 R/W-x R/W-x R/W-x W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as 0 bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6 Unimplemented: Read as 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 201 PIC32MX1XX/2XX NOTES:
DS61168C-page 202 Preliminary 2011 Microchip Technology Inc. 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data to Section 17. 10-bit sheet, refer Analog-to-Digital Converter
(ADC)
(DS61104) PIC32 Family Reference Manual, which is available from site
(www.microchip.com/PIC32). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX The PIC32MX1XX/2XX 10-bit Analog-to-Digital Converter (ADC) includes the following features:
Successive Approximation Register (SAR) conversion Up to 1 Msps conversion speed Up to 13 analog input pins External voltage reference input pins One unipolar, differential Sample and Hold Amplifier (SHA) Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable buffer fill modes Eight conversion result format options Operation during CPU Sleep and Idle modes A block diagram of the 10-bit ADC is illustrated in Figure 21-1. The 10-bit ADC has up to 13 analog input pins, designated AN0-AN12. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. FIGURE 21-1:
ADC1 MODULE BLOCK DIAGRAM CTMUI(3) VREF+(1) AVDD VREF-(1) AVSS AN0 AN12(2) CTMUT(3) IVREF(4) Open(5) VCFG<2:0>
Channel Scan CH0SA<4:0>
CH0SB<4:0>
+
-
S&H VREFH VREFL SAR ADC CSCNA AN1 VREFL CH0NA CH0NB Alternate Input Selection ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUFE ADC1BUFF Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2: AN8 is only available on 44-pin devices. AN6 and AN7 are not available on 28-pin devices. 3: Connected to the CTMU module. See Section 24.0 Charge Time Measurement Unit (CTMU) for more information. 4: See Section 23.0 Comparator Voltage Reference (CVREF) for more information. 5: This selection is only used with CTMU capacitive and time measurement. 2011 Microchip Technology Inc. Preliminary DS61168C-page 203 PIC32MX1XX/2XX FIGURE 21-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM FRC(1) Div 2 TPB(2) ADCS<7:0>
8 ADC Conversion Clock Multiplier 2, 4,..., 512 ADRC 1 0 TAD Note 1: See Section 29.0 Electrical Characteristics for the exact FRC clock value. 2: Refer to Figure 8-1 in Section 8.0 Oscillator Configuration for more information. DS61168C-page 204 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-1: AD1CON1: ADC CONTROL REGISTER 1 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 SIDL R/W-0 U-0 U-0 U-0 R/W-0 SSRC<2:0>
CLRASAM U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ASAM U-0 U-0 R/W-0 U-0 U-0 R/W-0 FORM<2:0>
R/W-0, HSC SAMP(2) R/C-0, HSC DONE(3) W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 ON: ADC Operating Mode bit(1) bit 15 1 = ADC module is operating 0 = ADC module is not operating Unimplemented: Read as 0 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 14 bit 13 bit 12-11 Unimplemented: Read as 0 bit 10-8 FORM<2:0>: Data Output Format bits bit 7-5 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the 2:
SYSCLK cycle immediately following the instruction that clears the modules ON bit. If ASAM = 0, software can write a 1 to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a 0 to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. 3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a 0 to clear this bit (a write of 1 is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. 2011 Microchip Technology Inc. Preliminary DS61168C-page 205 PIC32MX1XX/2XX REGISTER 21-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 4 bit 3 bit 2 bit 1 bit 0 ADC interrupt is generated. CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence Unimplemented: Read as 0 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit(2) 1 = The ADC sample and hold amplifier is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing 1 to this bit starts sampling. When SSRC = 000, writing 0 to this bit will end sampling and start conversion. DONE: Analog-to-Digital Conversion Status bit(3) 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the 2:
SYSCLK cycle immediately following the instruction that clears the modules ON bit. If ASAM = 0, software can write a 1 to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a 0 to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. 3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a 0 to clear this bit (a write of 1 is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. DS61168C-page 206 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-2: AD1CON2: ADC CONTROL REGISTER 2 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 R-0 BUFS U-0 U-0 R/W-0 VCFG<2:0>
U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 OFFCAL R/W-0 U-0 U-0 U-0 R/W-0 SMPI<3:0>
U-0 U-0 R/W-0 CSCNA R/W-0 U-0 U-0 U-0 R/W-0 BUFM U-0 U-0 U-0 R/W-0 ALTS Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits 000 001 010 011 1xx VREFH AVDD External VREF+ pin AVDD External VREF+ pin AVDD VREFL AVss AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 bit 1 bit 0 OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode 0 = Disable Offset Calibration mode Positive and negative inputs of the sample and hold amplifier are connected to VREFL The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL Unimplemented: Read as 0 CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as 0 BUFS: Buffer Fill Status bit Only valid when BUFM = 1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as 0 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and 0 = Always use Sample A input multiplexer settings Sample A input multiplexer settings for all subsequent samples 2011 Microchip Technology Inc. Preliminary DS61168C-page 207 PIC32MX1XX/2XX REGISTER 21-3: AD1CON3: ADC CONTROL REGISTER 3 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ADRC R/W-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 ADCS<7:0>(2) R/W-0 U-0 U-0 R/W-0 SAMC<4:0>(1) U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W R/W-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) bit 14-13 Unimplemented: Read as 0 bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) bit 7-0 11111 = 31 TAD 00001 =1 TAD 00000 =0 TAD (Not allowed) ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 =TPB 2 (ADCS<7:0> + 1) = 512 TPB = TAD 00000001 =TPB 2 (ADCS<7:0> + 1) = 4 TPB = TAD 00000000 =TPB 2 (ADCS<7:0> + 1) = 2 TPB = TAD Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111. 2: This bit is not used if the ADRC bit (AD1CON3<15>) = 1. DS61168C-page 208 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-4: AD1CHS: ADC INPUT SELECT REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/W-0 CH0NB R/W-0 CH0NA U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<3:0>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CH0SA<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31 CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 30-28 Unimplemented: Read as 0 bit 27-24 CH0SB<3:0>: Positive Input Select bits for Sample B 1111 = Channel 0 positive input is Open(1) 1110 = Channel 0 positive input is IVREF(2) 1101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(2) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 22-20 Unimplemented: Read as 0 bit 19-16 CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting 1111 = Channel 0 positive input is Open(1) 1110 = Channel 0 positive input is IVREF(2) 1101 = Channel 0 positive input is CTMU temperature (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 Unimplemented: Read as 0 bit 23 bit 15-0 Note 1: This selection is only used with CTMU capacitive and time measurement. 2: See Section 23.0 Comparator Voltage Reference (CVREF) for more information. 3: See Section 24.0 Charge Time Measurement Unit (CTMU) for more information. 4: AN12 is only available on 44-pin devices. AN6-AN8 are not available on 28-pin devices. 2011 Microchip Technology Inc. Preliminary DS61168C-page 209 PIC32MX1XX/2XX REGISTER 21-5: AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 CSSL15 R/W-0 CSSL7 CSSL14 R/W-0 CSSL6 CSSL13 R/W-0 CSSL5 CSSL12 R/W-0 CSSL4 CSSL11 R/W-0 CSSL3 CSSL10 R/W-0 CSSL2 U-0 U-0 R/W-0 CSSL9 R/W-0 CSSL1 U-0 U-0 R/W-0 CSSL8 R/W-0 CSSL0 Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits(1,2) 1 = Select ANx for input scan 0 = Skip ANx for input scan Note 1: CSSL = ANx, where x = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan;
CSSL15 selects VSS for scan. 2: On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to VREFL. DS61168C-page 210 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX The PIC32MX1XX/2XX Analog Comparator module contains three comparators that can be configured in a variety of ways. Following are some of the key features of this module:
Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(IVREF)
- Comparator voltage reference (CVREF) Outputs can be Inverted Selectable interrupt generation A block diagram of the comparator module is provided in Figure 22-1. 22.0 COMPARATOR the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features family of of devices. It is not intended to be a comprehensive reference source. To complement the information in this to Section 19. data sheet, refer Comparator (DS61110) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. FIGURE 22-1:
COMPARATOR BLOCK DIAGRAM C1INB C1INC C1IND C1INA C2INB C2INC C2IND C2INA C3INB C3INC C3IND C3INA CCH<1:0>
CREF CCH<1:0>
CREF CCH<1:0>
CREF CMP1 CPOL CMP2 CPOL CMP3 CPOL COE COE COE C1OUT CMSTAT<C1OUT>
CM1CON<COUT>
To CTMU module
(Pulse Generator) C2OUT CMSTAT<C2OUT>
CM2CON<COUT>
C3OUT CMSTAT<C3OUT>
CM3CON<COUT>
CVREF(1) IVREF (1.2V) Note 1:
Internally connected. See Section 23.0 Comparator Voltage Reference
(CVREF) for more information. 2011 Microchip Technology Inc. Preliminary DS61168C-page 211 PIC32MX1XX/2XX REGISTER 22-1: CMXCON: COMPARATOR CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) R/W-1 U-0 U-0 R/W-0 COE R/W-1 EVPOL<1:0>
U-0 U-0 R/W-0 CPOL(2) U-0 U-0 U-0 U-0 R/W-0 CREF U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 U-0 U-0 R-0 COUT R/W-1 CCH<1:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: Comparator ON bit(1) 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register bit 14 bit 13 COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted bit 7-6 bit 12-9 Unimplemented: Read as 0 COUT: Comparator Output bit bit 8 1 = Output of the Comparator is a 1 0 = Output of the Comparator is a 0 EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled Unimplemented: Read as 0 CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXINA pin Unimplemented: Read as 0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the CxIND pin 01 = Comparator inverting input is connected to the CxINC pin 00 = Comparator inverting input is connected to the CxINB pin bit 3-2 bit 1-0 bit 5 bit 4 Note 1: When using the 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. 2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. DS61168C-page 212 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 22-2: CMSTAT: COMPARATOR STATUS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 SIDL U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0 R-0 C3OUT C2OUT C1OUT W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as 0 SIDL: Stop in IDLE Control bit bit 13 1 = All Comparator modules are disabled in IDLE mode 0 = All Comparator modules continue to operate in the IDLE mode bit 1 bit 12-3 Unimplemented: Read as 0 C3OUT: Comparator Output bit bit 2 1 = Output of Comparator 3 is a 1 0 = Output of Comparator 3 is a 0 C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a 1 0 = Output of Comparator 2 is a 0 C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a 1 0 = Output of Comparator 1 is a 0 bit 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 213 PIC32MX1XX/2XX NOTES:
DS61168C-page 214 Preliminary 2011 Microchip Technology Inc. 23.0 COMPARATOR VOLTAGE REFERENCE (CVREF) the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. Comparator Voltage Reference (CVREF) (DS61109) in the PIC32 Family Reference Manual, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. A block diagram of the module is illustrated in Figure 23-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The modules supply refer-
ence can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is avail-
able for the comparators and typically available for pin output. The comparator voltage reference has the following features:
High and low range selection Sixteen output levels available for each range Internally connected to comparators to conserve device pins FIGURE 23-1:
Output can be connected to a pin COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+
AVDD CVREN CVRSS = 1 CVRSRC CVRSS = 0 8R CVR<3:0>
CVREF 16 Steps R R R R R R R X U M 1
-
o t
-
6 1 CVREFOUT CVRCON<CVROE>
CVRR VREF-
AVSS 8R CVRSS = 1 CVRSS = 0 2011 Microchip Technology Inc. Preliminary DS61168C-page 215 PIC32MX1XX/2XX REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1) U-0 U-0 U-0 U-0 R/W-0 CVROE U-0 U-0 U-0 R/W-0 CVRR U-0 U-0 U-0 R/W-0 CVRSS U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 CVR<3:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: Comparator Voltage Reference On bit(1) 1 = Module is enabled 0 = Module is disabled and does not consume current. Setting this bit does not affect other bits in the register. Clearing this bit does not affect the other bits in the register. bit 5 bit 14-7 Unimplemented: Read as 0 CVROE: CVREFOUT Enable bit bit 6 1 = Voltage level is output on CVREFOUT pin 0 = Voltage level is disconnected from CVREFOUT pin CVRR: CVREF Range Selection bit 1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD AVSS CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC) When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) bit 3-0 bit 4 Note 1: When using 1:1 PBCLK divisor, the users software should not read/write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 216 Preliminary 2011 Microchip Technology Inc. 24.0 CHARGE TIME MEASUREMENT UNIT (CTMU) Note 1: This data sheet summarizes the fea-
tures of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. Charge
(CTMU) Time Measurement Unit
(DS61167) PIC32 Family Reference Manual, which is available from site
(www.microchip.com). the Microchip web the in 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. The Charge Time Measurement Unit (CTMU) is a flex-
ible analog module that has a configurable current source with a digital configuration circuit built around it. The CTMU can be used for differential time measure-
ment between pulse sources and can be used for gen-
erating an asynchronous pulse. By working with other FIGURE 24-1:
CTMU BLOCK DIAGRAM PIC32MX1XX/2XX on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capaci-
tance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes the following key features:
Up to 13 channels available for capacitive or time measurement input On-chip precision current source 16-edge input trigger sources Selection of edge or level-sensitive inputs Polarity control for each edge source Control of edge sequence Control of response to edges High precision time measurement Time delay of external or internal signal asynchro-
nous to system clock Integrated temperature sensing diode Control of current source during auto-sampling Four current source ranges Time measurement resolution of one nanosecond A block diagram of the CTMU is shown in Figure 24-1. CTED1 CTED13 Timer1 OC1 IC1-IC3 CMP1-CMP3 PBCLK CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0>
IRNG<1:0>
Current Source Edge Control Logic EDG1STAT EDG2STAT TGEN CTMU Control Logic Current Control CTMUP Pulse Generator ADC Trigger CTPLS CTMUT
(To ADC) Temperature Sensor
(To ADC S&H capacitor) CTMUI C2INB CDelay External capacitor for pulse generation Comparator 2 Current Control Selection CTMUT CTMUI CTMUP No Connect TGEN 0 0 1 1 EDG1STAT, EDG2STAT EDG1STAT = EDG2STAT EDG1STAT EDG2STAT EDG1STAT EDG2STAT EDG1STAT = EDG2STAT 2011 Microchip Technology Inc. Preliminary DS61168C-page 217 PIC32MX1XX/2XX REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range 31:24 23:16 15:8 7:0 R/W-0 R/W-0 EDG1MOD EDG1POL R/W-0 R/W-0 EDG2MOD EDG2POL R/W-0 R/W-0 R/W-0 ON R/W-0 U-0 R/W-0 R/W-0 CTMUSIDL R/W-0 R/W-0 R/W-0 R/W-0 EDG1SEL<3:0>
R/W-0 EDG2SEL<3:0>
R/W-0 EDGEN R/W-0 R/W-0 TGEN(1) R/W-0 Bit 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 EDG2STAT EDG1STAT U-0 R/W-0 R/W-0 EDGSEQEN IDISSEN(2) R/W-0 R/W-0 U-0 R/W-0 CTTRIG R/W-0 ITRIM<5:0>
IRNG<1:0>
Legend:
R = Readable bit
-n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31 bit 30 EDG1MOD: Edge1 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive EDG1POL: Edge 1 Polarity Select bit 1 = Edge1 programmed for a positive edge response 0 = Edge1 programmed for a negative edge response bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = IC3 Capture Event is selected 1011 = IC2 Capture Event is selected 1010 = IC1 Capture Event is selected 1001 = CTED8 pin is selected 1000 = CTED7 pin is selected 0111 = CTED6 pin is selected 0110 = CTED5 pin is selected 0101 = CTED4 pin is selected 0100 = CTED3 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected EDG2STAT: Edge2 Status bit Indicates the status of Edge2 and can be written to control edge source 1 = Edge2 has occurred 0 = Edge2 has not occurred bit 25 Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to 1110 to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to 1, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 Electrical Characteristics for current values. 4: This bit setting is not available for the CTMU temperature diode. DS61168C-page 218 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge1 Status bit Indicates the status of Edge1 and can be written to control edge source 1 = Edge1 has occurred 0 = Edge1 has not occurred EDG2MOD: Edge2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive EDG2POL: Edge 2 Polarity Select bit 1 = Edge2 programmed for a positive edge response 0 = Edge2 programmed for a negative edge response bit 23 bit 22 bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = PBCLK clock is selected 1011 = IC3 Capture Event is selected 1010 = IC2 Capture Event is selected 1001 = IC1 Capture Event is selected 1000 = CTED13 pin is selected 0111 = CTED12 pin is selected 0110 = CTED11 pin is selected 0101 = CTED10 pin is selected 0100 = CTED9 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 17-16 Unimplemented: Read as 0 bit 15 bit 14 bit 13 bit 12 bit 11 ON: ON Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as 0 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to 1110 to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to 1, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 Electrical Characteristics for current values. 4: This bit setting is not available for the CTMU temperature diode. 2011 Microchip Technology Inc. Preliminary DS61168C-page 219 PIC32MX1XX/2XX REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 10 bit 9 bit 8 bit 7-2 bit 1-0 EDGSEQEN: Edge Sequence Enable bit 1 = Edge1 must occur before Edge2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Range Select bits(3) 11 = 100 times base current 10 = 10 times base current 01 = Base current level 00 = 1000 times base current(4) Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to 1110 to select C2OUT. 2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to 1, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. 3: Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 Electrical Characteristics for current values. 4: This bit setting is not available for the CTMU temperature diode. DS61168C-page 220 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. SLEEP MODE 25.3 Power-Saving Operation Peripherals and the CPU can be Halted or disabled to further reduce power consumption. 25.3.1 Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are Halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics:
The CPU is Halted. The system clock source is typically shutdown. See Section 25.3.3 Peripheral Bus Scaling Method for specific information. There can be a wake-up delay based on the oscillator selection. The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. The BOR circuit remains operative during Sleep mode. The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. The USB module can override the disabling of the Posc or FRC. Refer to the USB section for specific details. Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. 25.0 POWER-SAVING FEATURES the PIC32MX1XX/2XX Note 1: This data sheet summarizes the features of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. Power-
Saving Features (DS61130) in the PIC32 Family Reference Manual, which is available from the Microchip web site
(www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 Memory Organization in this data sheet for device-specific register and bit information. This section describes power-saving features for the PIC32MX1XX/2XX. The PIC32 devices offer a total of nine methods and modes, organized two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-
saving is controlled by software. into Power Saving with CPU Running 25.1 When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules. These methods are grouped the following categories:
FRC Run mode: the CPU is clocked from the FRC into clock source with or without postscalers. LPRC Run mode: the CPU is clocked from the LPRC clock source. SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK). 25.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below:
POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. 2011 Microchip Technology Inc. Preliminary DS61168C-page 221 PIC32MX1XX/2XX The processor will exit, or wake-up, from Sleep on one of the following events:
On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. On any form of device Reset. On a WDT time-out. If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. IDLE MODE 25.3.2 In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripher-
als to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. Note 1: Changing the PBCLK divider ratio requires recalculation of peripheral tim-
ing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing cal-
culation required for a peripheral should be performed with the new PB clock fre-
quency instead of scaling the previous value based on a change in the PB divisor ratio. 2: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-
up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events:
On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. On any form of device Reset On a WDT time-out interrupt 25.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, interrupt controller, DMA, bus matrix and prefetch cache are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects:
The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. The power consumption of the peripherals. Power consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock require-
ments, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. DS61168C-page 222 Preliminary 2011 Microchip Technology Inc. Peripheral Module Disable 25.4 The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. PIC32MX1XX/2XX To disable a peripheral, the associated PMDx bit must be set to 1. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 25-1 for more information. Note:
Disabling a peripheral module while its ON bit is set, may result in undefined behavior. The ON bit for the associated peripheral module must be cleared prior to disable a module via the PMDx bits. TABLE 25-1:
PERIPHERAL MODULE DISABLE BITS AND LOCATIONS(1) Peripheral PMDx bit Name Register Name and Bit Location ADC1 CTMU Comparator Voltage Reference Comparator 1 Comparator 2 Comparator 3 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Timer1 Timer2 Timer3 Timer4 Timer5 UART1 UART2 SPI1 SPI2 I2C1 I2C2 USB(2) RTCC Reference Clock Output PMP Note 1: Not all modules and associated PMDx bits are available on all devices. See TABLE 1: PIC32MX1XX PMD1<0>
PMD1<8>
PMD1<12>
PMD2<0>
PMD2<1>
PMD2<2>
PMD3<0>
PMD3<1>
PMD3<2>
PMD3<3>
PMD3<4>
PMD3<16>
PMD3<17>
PMD3<18>
PMD3<19>
PMD3<20>
PMD4<0>
PMD4<1>
PMD4<2>
PMD4<3>
PMD4<4>
PMD5<0>
PMD5<1>
PMD5<8>
PMD5<9>
PMD5<16>
PMD5<17>
PMD5<24>
PMD6<0>
PMD6<1>
PMD6<16>
AD1MD CTMUMD CVRMD CMP1MD CMP2MD CMP3MD IC1MD IC2MD IC3MD IC4MD IC5MD OC1MD OC2MD OC3MD OC4MD OC5MD T1MD T2MD T3MD T4MD T5MD U1MD U2MD SPI1MD SPI2MD I2C1MD I2C2MD USBMD RTCCMD REFOMD PMPMD General Purpose Family Features and TABLE 2: PIC32MX2XX USB Family Features for the lists of available peripherals. 2: Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit. 2011 Microchip Technology Inc. Preliminary DS61168C-page 223 PIC32MX1XX/2XX 25.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals:
Control register lock sequence Configuration bit select lock Control Register Lock 25.4.1.1 Under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the PMDLOCK Configuration bit (CFGCON<12>). Set-
ting PMDLOCK prevents writes to the control registers;
clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must to Section 6. Oscillator be executed. Refer
(DS61112) in the PIC32 Family Reference Manual for details. Configuration Bit Select Lock 25.4.1.2 As an additional level of safety, the device can be configured to prevent more than one write session to the PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3<28>) blocks the PMDLOCK bit from being cleared after it has been set once. If PMDLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable PMD functionality is to perform a device Reset. DS61168C-page 224 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX to select registers 26.1 Configuration Bits The Configuration bits can be programmed using the following various device configurations. DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 CFGCON: Configuration Control Register In addition, provides device and revision information.
(Register 26-6) the DEVID register 26.0 SPECIAL FEATURES Note:
the PIC32MX1XX/2XX This data sheet summarizes the features of family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. Watchdog Timer and Power-up Timer (DS61114), Section 32. Configuration (DS61124) and Section 33. Programming and Diagnostics (DS61129) in the PIC32 Family Reference Manual (DS61132), which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX1XX/2XX devices include several features intended to maximize application flexibility and reliabil-
ity and minimize cost through elimination of external components. These are:
Flexible device configuration Watchdog Timer (WDT) Joint Test Action Group (JTAG) interface In-Circuit Serial Programming (ICSP) 2011 Microchip Technology Inc. Preliminary DS61168C-page 225 PIC32MX1XX/2XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 r-0 r-1 R/P r-1 r-1 r-1 R/P r-1 r-1 r-1 R/P R/P CP r-1 R/P r-1 r-1 R/P r-1 r-1 R/P PWP<5:0>
r-1 R/P R/P ICESEL<1:0>(2) R/P JTAGEN(1) R/P r-1 BWP r-1 r-1 r-1 r-1 R/P R/P DEBUG<1:0>
Legend:
R = Readable bit
-n = Value at POR r = Reserved bit W = Writable bit 1 = Bit is set P = Programmable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown Reserved: Write 0 bit 31 bit 30-29 Reserved: Write 1 CP: Code-Protect bit bit 28 Prevents boot and program Flash memory from being read or modified by an external pro-
gramming device. 1 = Protection is disabled 0 = Protection is enabled bit 27-25 Reserved: Write 1 bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-16 Reserved: Write 1 Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the Pin Diagrams section for availability. DS61168C-page 226 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 15-10 PWP<5:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. 111111 = Disabled 111110 = Memory below 0x0400 address is write-protected 111101 = Memory below 0x0800 address is write-protected 111100 = Memory below 0x0C00 address is write-protected 111011 = Memory below 0x1000 address is write-protected 111010 = Memory below 0x1400 address is write-protected 111001 = Memory below 0x1800 address is write-protected 111000 = Memory below 0x1C00 address is write-protected 110111 = Memory below 0x2000 address is write-protected 110110 = Memory below 0x2400 address is write-protected 110101 = Memory below 0x2800 address is write-protected 110100 = Memory below 0x2C00 address is write-protected 110011 = Memory below 0x3000 address is write-protected 110010 = Memory below 0x3400 address is write-protected 110001 = Memory below 0x3800 address is write-protected 110000 = Memory below 0x3C00 address is write-protected 101111 = Memory below 0x4000 address is write-protected 101110 = Memory below 0x4400 address is write-protected 101101 = Memory below 0x4800 address is write-protected 101100 = Memory below 0x4C00 address is write-protected 101011 = Memory below 0x5000 address is write-protected 101010 = Memory below 0x5400 address is write-protected 101001 = Memory below 0x5800 address is write-protected 101000 = Memory below 0x5C00 address is write-protected 100111 = Memory below 0x6000 address is write-protected 100110 = Memory below 0x6400 address is write-protected 100101 = Memory below 0x6800 address is write-protected 100100 = Memory below 0x6C00 address is write-protected 100011 = Memory below 0x7000 address is write-protected 100010 = Memory below 0x7400 address is write-protected 100001 = Memory below 0x7800 address is write-protected 100000 = Memory below 0x7C00 address is write-protected 011111 = Memory below 0x8000 address is write-protected Reserved: Write 1 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = PGEC4/PGED4 pair is used(2) JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled DEBUG<1:0>: Background Debugger Enable bits (forced to 11 if code-protect is enabled) 1x = Debugger is disabled 0x = Debugger is enabled bit 9-5 bit 4-3 bit 2 bit 1-0 Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the Pin Diagrams section for availability. 2011 Microchip Technology Inc. Preliminary DS61168C-page 227 PIC32MX1XX/2XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 r-1 R/P r-1 R/P FWDTEN WINDIS R/P R/P FCKSM<1:0>
r-1 R/P IESO r-1 R/P r-1 r-1 R/P R/P FPBDIV<1:0>
r-1 R/P FSOSCEN r-1 R/P r-1 r-1 r-1 R/P R/P R/P FWDTWINSZ<1:0>
R/P R/P WDTPS<4:0>
R/P OSCIOFNC R/P R/P R/P POSCMOD<1:0>
R/P R/P FNOSC<2:0>
Legend:
R = Readable bit
-n = Value at POR r = Reserved bit W = Writable bit 1 = Bit is set P = Programmable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-26 Reserved: Write 1 bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits bit 23 bit 22 11 = Window size is 25%
10 = Window size is 37.5%
01 = Window size is 50%
00 = Window size is 75%
FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled and cannot be disabled by software 0 = Watchdog Timer is not enabled; it can be enabled in software WINDIS: Watchdog Timer Window Enable bit 1 = Watchdog Timer is in non-Window mode 0 = Watchdog Timer is in Window mode Reserved: Write 1 bit 21 bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS61168C-page 228 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Reserved: Write 1 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00) bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) Reserved: Write 1 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Write 1 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. 2011 Microchip Technology Inc. Preliminary DS61168C-page 229 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 R/P R/P R/P r-1 R/P FPLLODIV<2:0>
R/P UPLLIDIV<2:0>(1) R/P FPLLIDIV<2:0>
r-1 R/P R/P R/P r-1 r-1 r-1 r-1 P = Programmable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown PIC32MX1XX/2XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 Bit Range 31:24 23:16 15:8 7:0 r-1 r-1 R/P UPLLEN(1) r-1 Legend:
R = Readable bit
-n = Value at POR r-1 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P r-1 r-1 r-1 R/P-1 FPLLMUL<2:0>
r = Reserved bit W = Writable bit 1 = Bit is set bit 31-19 Reserved: Write 1 bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 UPLLEN: USB PLL Enable bit(1) 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write 1 bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits(1) bit 15 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Reserved: Write 1 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier Reserved: Write 1 bit 7 bit 6-4 bit 3 Note 1: This bit is available on PIC32MX2XX devices only. DS61168C-page 230 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is available on PIC32MX2XX devices only. 2011 Microchip Technology Inc. Preliminary DS61168C-page 231 PIC32MX1XX/2XX REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R/P R/P R/P R/P FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY r-1 R/P R/P r-1 R/P R/P r-1 R/P R/P r-1 r-1 R/P r-1 R/P USERID<15:8>
R/P USERID<7:0>
R/P r-1 r-1 R/P R/P r-1 r-1 R/P R/P r-1 r-1 R/P R/P Legend:
R = Readable bit
-n = Value at POR r = Reserved bit W = Writable bit 1 = Bit is set P = Programmable bit U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31 bit 30 bit 29 bit 28 FVBUSONIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations PMDl1WAY: Peripheral Module Disable Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 27-16 Reserved: Write 1 bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP and JTAG DS61168C-page 232 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-5: CFGCON: CONFIGURATION CONTROL REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 U-0 U-0 U-0 U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 R/W-0 U-0 U-0 R/W-0 IOLOCK(1) PMDLOCK(1) U-0 U-0 U-0 U-0 U-0 R/W-1 JTAGEN U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-1 U-0 U-0 U-0 R/W-1 TDOEN W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as 0 bit 13 IOLOCK: Peripheral Pin Select Lock bit(1) 1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed. 0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed. PMDLOCK: Peripheral Module Disable bit(1) 1 = Peripheral module is locked. Writes to PMD registers is not allowed. 0 = Peripheral module is not locked. Writes to PMD registers is allowed. bit 12 bit 11-4 Unimplemented: Read as 0 JTAGEN: JTAG Port Enable bit bit 3 1 = Enable the JTAG port 0 = Disable the JTAG port Unimplemented: Read as 1 TDOEN: TDO Enable for 2-Wire JTAG 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO bit 2-1 bit 0 Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. Oscillator (DS61112) in the PIC32 Family Reference Manual for details. 2011 Microchip Technology Inc. Preliminary DS61168C-page 233 PIC32MX1XX/2XX REGISTER 26-6: DEVID: DEVICE AND REVISION ID REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 R R R R Legend:
R = Readable bit
-n = Value at POR R VER<3:0>(1) R R R R R R R R R R R DEVID<23:16>(1) R R DEVID<15:8>(1) R R DEVID<7:0>(1) R R DEVID<27:24>(1) R R R R R R R R R R W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Note 1: See the PIC32MX Flash Programming Specification (DS61145) for a list of Revision and Device ID values. DS61168C-page 234 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX The following are some of the key features of the WDT module:
Configuration or software controlled User-configurable time-out period Can wake the device from Sleep or Idle 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX1XX/2XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. FIGURE 26-1:
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Oscillator WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 1:64 Output 1 25-bit Counter 25 Clock WDT Counter Reset PWRT Enable LPRC Control PWRT 0 1 Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0> (DEVCFG1<20:16>) 2011 Microchip Technology Inc. Preliminary DS61168C-page 235 PIC32MX1XX/2XX REGISTER 26-7: WDTCON: WATCHDOG TIMER CONTROL REGISTER(1,2,3) Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31:24 23:16 15:8 7:0 U-0 U-0 R/W-0 ON(1,2) U-0 Legend:
R = Readable bit
-n = Value at POR U-0 U-0 U-0 R-y U-0 U-0 U-0 R-y U-0 U-0 U-0 R-y U-0 U-0 U-0 R-y U-0 U-0 U-0 R-y U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 SWDTPS<4:0>
WDTWINEN WDTCLR y = Values set from Configuration bits on POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as 0 bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software bit 14-7 Unimplemented: Read as 0 bit 6-2 bit 1 bit 0 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits. WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer WDTCLR: Watchdog Timer Reset bit 1 = Writing a 1 will clear the WDT 0 = Software cannot force this bit to a 0 Note 1: A read of this bit results in a 1 if the Watchdog Timer is enabled by the device configuration or software. 2: When using the 1:1 PBCLK divisor, the users software should not read or write the peripherals SFRs in the SYSCLK cycle immediately following the instruction that clears the modules ON bit. DS61168C-page 236 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 26.4 Programming and Diagnostics PIC32MX1XX/2XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include:
Simplified field programmability using two-wire In-Circuit Serial Programming (ICSP) interfaces Debugging using ICSP Programming and debugging capabilities using the EJTAG extension of JTAG JTAG boundary scan testing for device and board diagnostics PIC32 devices incorporate two programming and diag-
nostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 26-3:
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 PGEC4 PGED4 TDI TDO TCK TMS ICSP Controller Core ICESEL JTAG Controller JTAGEN DEBUG<1:0>
devices designs, most 26.3 On-Chip Voltage Regulator All PIC32MX1XX/2XX devices core and digital logic are designed to operate at a nominal 1.8V. To simplify system the PIC32MX1XX/2XX family incorporate an on-chip regu-
lator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 29.1 DC Characteristics. in Note:
It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. ON-CHIP REGULATOR AND POR 26.3.1 It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. ON-CHIP REGULATOR AND BOR 26.3.2 PIC32MX1XX/2XX devices also have a simple brown-
out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 29.1 DC Characteristics. FIGURE 26-2:
CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V(1) CEFC(2,3)
(10 F typ) PIC32 VDD VCAP VSS Note 1:
2:
3:
These are typical operating voltages. Refer to Section 29.1 DC Characteristics for the full operating ranges of VDD. It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. The typical voltage on the VCAP pin is 1.8V. 2011 Microchip Technology Inc. Preliminary DS61168C-page 237 PIC32MX1XX/2XX NOTES:
DS61168C-page 238 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 27.0 INSTRUCTION SET The PIC32MX1XX/2XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32 device family does not support the following features:
Core extend instructions Coprocessor 1 instructions Coprocessor 2 instructions Note:
to MIPS32 Architecture Refer for Programmers Volume II: The MIPS32 Instruction Set at www.mips.com for more information. 2011 Microchip Technology Inc. Preliminary DS61168C-page 239 PIC32MX1XX/2XX NOTES:
DS61168C-page 240 Preliminary 2011 Microchip Technology Inc. 28.0 DEVELOPMENT SUPPORT The PIC microcontrollers and dsPIC digital signal controllers are supported with a full range of software and hardware development tools:
Integrated Development Environment
- MPLAB IDE Software Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for Various Device Families Simulators
- MPLAB SIM Software Simulator Emulators
- MPLAB REAL ICE In-Circuit Emulator In-Circuit Debuggers
- MPLAB ICD 3
- PICkit 3 Debug Express Device Programmers
- PICkit 2 Programmer
- MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits PIC32MX1XX/2XX 28.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows operating system-based application that contains:
A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
-
-
In-Circuit Emulator (sold separately) In-Circuit Debugger (sold separately) A full-featured editor with color-coded context A multiple project manager Customizable data windows with direct edit of contents High-level source code debugging Mouse over variable inspection Drag and drop variables from source to watch windows Extensive on-line help Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to:
Edit your source files (either C or assembly) One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011 Microchip Technology Inc. Preliminary DS61168C-page 241 PIC32MX1XX/2XX 28.2 MPLAB C Compilers for Various Device Families 28.5 MPLINK Object Linker/
MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchips PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 28.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchips PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple platforms. 28.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include:
Integration into MPLAB IDE projects User-defined macros to streamline assembly code Conditional assembly for multi-purpose source files Directives that allow complete control over the assembly process The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include:
Efficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include:
Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS61168C-page 242 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 28.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC Flash microcon-
trollers and dsPIC DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.10 PICkit 3 In-Circuit Debugger/
Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with users guide, lessons, tutorial, compiler and MPLAB IDE software. 28.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software development tool. 28.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchips next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash MCUs and dsPIC Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineers PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. full-speed emulation, low-cost, 2011 Microchip Technology Inc. Preliminary DS61168C-page 243 PIC32MX1XX/2XX 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express full PIC12F5xx, The PICkit 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter-
face for programming and debugging Microchips Flash families of microcontrollers. The featured Windows programming interface supports baseline
(PIC10F, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchips powerful MPLAB Integrated Development Environment (IDE) the PICkit 2 enables in-circuit debugging on most PIC microcon-
trollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a break-
point, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with users guide, lessons, tutorial, compiler and MPLAB IDE software. 28.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM and dsPICDEM demon-
stration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ security ICs, CAN, IrDA, PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. flow DS61168C-page 244 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX electrical characteristics. Additional information will be pro-
vided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX1XX/2XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40C to +105C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB ............................................................................... -0.3V to (VUSB + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin ....................................................................................................15 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2). 3: See the Pin Diagrams section for the 5V tolerant pins. 2011 Microchip Technology Inc. Preliminary DS61168C-page 245 PIC32MX1XX/2XX 29.1 DC Characteristics TABLE 29-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 DC5b VDD Range
(in Volts) 2.3-3.6V 2.3-3.6V Temp. Range
(in C)
-40C to +85C
-40C to +105C TABLE 29-2:
THERMAL OPERATING CONDITIONS Max. Frequency PIC32MX1XX/2XX 40 MHz 40 MHz Rating Symbol Min. Typical Max. Unit Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range V-temp Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD S IOH) I/O Pin Power Dissipation:
I/O = S (({VDD VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TJ TA TJ TA PD
-40
-40
-40
-40
+125
+85
+140
+105 PINT + PI/O PDMAX
(TJ TA)/JA TABLE 29-3:
THERMAL PACKAGING CHARACTERISTICS Characteristics Package Thermal Resistance, 28-pin SSOP Package Thermal Resistance, 28-pin SOIC Package Thermal Resistance, 28-pin SPDIP Package Thermal Resistance, 28-pin QFN Package Thermal Resistance, 36-pin VTLA Package Thermal Resistance, 44-pin QFN Package Thermal Resistance, 44-pin TQFP Package Thermal Resistance, 44-pin VTLA Note 1:
1 1 1 1 1 1 1 1 Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. Symbol Typical Max. Unit C/W C/W C/W C/W C/W C/W C/W C/W JA JA JA JA JA JA JA JA 71 50 42 35 31 32 45 30 C C C C W W Notes DS61168C-page 246 Preliminary 2011 Microchip Technology Inc. DC CHARACTERISTICS Param. No. Symbol Operating Voltage DC10 DC12 VDD VDR DC16 VPOR DC17 SVDD TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS PIC32MX1XX/2XX Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Characteristics Min. Typical Max. Units Conditions Supply Voltage RAM Data Retention Voltage
(Note 1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal 2.3 1.75 1.75 0.00005 3.6 2.1 V V V 0.115 V/s Note 1: This is the limit to which VDD can be lowered without losing RAM data. TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Parameter No. Typical(3) Max. Units Conditions 2 5 10 15 20 100 Operating Current (IDD)(1,2) DC20 DC21 DC22 DC23 DC24 LPRC (32 kHz) (Note 4) DC25 Note 1: A devices IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. 20 MHz (Note 4) 30 MHz (Note 4) 25 30 40 45 55 150 mA mA mA mA mA A 4 MHz (Note 4)
+25C, 3.3V 10 MHz 40 MHz 2: The test conditions for IDD measurements are as follows: Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail. CPU, Program Flash and SRAM data memory are operational. All peripheral modules are disabled (ON bit = 0) but the associated PMD bit is cleared. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. 3: Data in Typical column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. 2011 Microchip Technology Inc. Preliminary DS61168C-page 247 PIC32MX1XX/2XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) DC30a DC31a DC32a DC33a DC34a DC37a DC37b DC37c Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and 2 4.5 8.5 12 14.5 30 55 230 20 MHz (Note 3) 30 MHz (Note 3) mA mA mA mA mA A A A 15 20 25 28 30
-40C
+25C
+85C 4 MHz (Note 3)
(Note 3) 10 MHz 40 MHz 3.3V LPRC (31 kHz) PBCLK divisor = 1:1. CPU in Idle mode (CPU core Halted). All peripheral modules are disabled
(ON bit = 0), but the associated PMD bit is cleared. WDT and FSCM are disabled. All I/O pins are config-
ured as inputs and pulled to VSS. MCLR = VDD. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: This parameter is characterized, but not tested in manufacturing. DS61168C-page 248 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Typical(2) Max. Units Conditions 10 44 168 335 Power-Down Current (IPD) (Note 1) 20 A DC40k 50 A DC40l 400 DC40n A DC40m A 700 Module Differential Current DC41e DC42e DC43d Note 1: Base IPD is measured with all peripheral modules and clocks shut down (ON = 0, PMDx = 1), CPU clock is Watchdog Timer Current: IWDT (Note 3) RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) ADC: IADC (Notes 3,4)
-40C
+25C
+85C
+105C Base Power-Down Current 5 23 1000 20 50 1100 3.6V 3.6V 3.6V A A A disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. 2: Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. added to the base IPD current. 3: The current is the additional current consumed when the module is enabled. This current should be 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 2011 Microchip Technology Inc. Preliminary DS61168C-page 249 PIC32MX1XX/2XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics Min. Typical(1) Max. Units Conditions Param. No. DI10 DI18 DI19 DI20 DI28 DI29 VIL VIH Input Low Voltage I/O Pins with PMP I/O Pins SDAx, SCLx SDAx, SCLx VSS VSS VSS VSS Input High Voltage I/O Pins not 5V-tolerant(5) I/O Pins 5V-tolerant with PMP(5) I/O Pins 5V-tolerant(5) SDAx, SCLx 0.65 VDD 0.25 VDD + 0.8V 0.65 VDD 0.65 VDD SDAx, SCLx Change Notification Pull-up Current Change Notification Pull-down Current(4) Input Leakage Current
(Note 3) I/O Ports Analog Input Pins MCLR(2) OSC1 2.1 50 DI30 ICNPU DI31 ICNPD IIL DI50 DI51 DI55 DI56 250 50 0.15 VDD 0.2 VDD 0.3 VDD 0.8 VDD 5.5 5.5 5.5 5.5 400
+1
+1
+1
+1 V V V V V V V V V SMBus disabled
(Note 4) SMBus enabled
(Note 4)
(Note 4)
(Note 4) SMBus disabled
(Note 4) SMBus enabled, 2.3V VPIN 5.5
(Note 4) A VDD = 3.3V, VPIN = VSS A VDD = 3.3V, VPIN = VDD A VSS VPIN VDD, Pin at high-impedance A VSS VPIN VDD, Pin at high-impedance A VSS VPIN VDD A VSS VPIN VDD, XT and HS modes Note 1: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the Pin Diagrams section for the 5V-tolerant pins. DS61168C-page 250 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. Symbol Characteristic Min. Typ. Max. Units Conditions DO10 VOL Output Low Voltage I/O Pins Output High Voltage DO20 VOH I/O Pins 1.5(1) 2.0(1) 2.4 3.0(1) 0.4 V V IOL 10 mA, VDD = 3.3V IOH -14 mA, VDD = 3.3V IOH -12 mA, VDD = 3.3V IOH -10 mA, VDD = 3.3V IOH -7 mA, VDD = 3.3V Note 1: Parameters are characterized, but not tested. TABLE 29-10: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. BO10 Symbol Characteristics Min.(1) Typical Max. Units Conditions VBOR BOR Event on VDD transition high-to-low 2.0 2.3 V Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2011 Microchip Technology Inc. Preliminary DS61168C-page 251 PIC32MX1XX/2XX TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Symbol Characteristics Min. Typical(1) Max. Units Conditions D130 D131 D132 D134 EP VPR VPEW TRETD D135 IDDP D136 D137 TWW TRW TPE TCE Program Flash Memory Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time
(Note 2)
(128 words per row) Page Erase Cycle Time Chip Erase Cycle Time 20,000 2.3 2.3 20 20 3 20 80 10 4.5 3.6 3.6 40 E/W V V Year Provided no other specifications are violated mA s ms ms ms Note 1: Data in Typical column is at 3.3V, 25C unless otherwise stated. 2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to the PIC32 Flash Programming Specification (DS61145) for operating conditions during programming and erase cycles. DS61168C-page 252 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-12: COMPARATOR SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics Min. Typical Max. Units Comments Param. No. D300 VIOFF Input Offset Voltage D301 VICM Input Common Mode Voltage D302 CMRR Common Mode Rejection Ratio D303 TRESP Response Time D304 ON2OV Comparator Enabled to Output Valid 0 55 7.5 25 VDD 150 400 10 mV V AVDD = VDD, AVSS = VSS AVDD = VDD, AVSS = VSS
(Note 2) dB Max VICM = (VDD - 1)V
(Note 2) AVDD = VDD, AVSS = VSS
(Notes 1,2) Comparator module is configured before setting the comparator ON bit
(Note 2) BGSEL<1:0> = 00 ns s V s D305 D312 IVREF TSET Internal Voltage Reference Internal Voltage Reference Setting time (Note 3) 1.14 1.2 1.26 10 Note 1: Response time measured with one comparator input at (VDD 1.5)/2, while the other input transitions from VSS to VDD. 2: These parameters are characterized but not tested. 3: Settling time measured while CVRR = 1 and CVR<3:0> transitions from 0000 to 1111. This parameter is characterized, but not tested in manufacturing. TABLE 29-13:
INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. D321 Symbol Characteristics Min. Typical Max. Units Comments CEFC External Filter Capacitor Value 8 10 F Capacitor must be low series resistance (1 ohm). Typical voltage on the VCAP pin is 1.8V. 2011 Microchip Technology Inc. Preliminary DS61168C-page 253 PIC32MX1XX/2XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX AC characteristics and timing parameters. FIGURE 29-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 for all pins except OSC2 Load Condition 2 for OSC2 VDD/2 RL CL VSS Pin Pin CL VSS RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) TABLE 29-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. Symbol Characteristics Min. Typical(1) Max. Units No. DO56 DO58 Note 1: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only All I/O pins and OSC2 SCLx, SDAx pF EC mode pF In I2C mode 50 400 CIO CB Conditions and are not tested. FIGURE 29-2:
EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31 DS61168C-page 254 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-15: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. OS10 OS11 OS12 OS13 OS14 OS15 OS20 OS30 OS31 OS40 Symbol Characteristics FOSC External CLKI Frequency
(External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency TOSC TOSC = 1/FOSC = TCY (Note 2) Min. DC 4 3 4 10 10 32 TOSL, TOSH TOSR, TOSF TOST External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time Oscillator Start-up Timer Period
(Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) Primary Clock Fail Safe Time-out Period External Oscillator Transconductance 0.45 x TOSC OS41 TFSCM OS42 GM Typical(1) Max. Units Conditions 32.768 1024 2 12 40 40 10 10 25 25 100 MHz MHz EC (Note 4) ECPLL (Note 3) MHz XT (Note 4) MHz XTPLL
(Notes 3,4) MHz HS (Note 5) MHz HSPLL
(Notes 3,4) kHz SOSC (Note 4) See parameter OS10 for FOSC value EC (Note 4) ns 0.05 x TOSC ns EC (Note 4) TOSC (Note 4) ms
(Note 4) mA/V VDD = 3.3V, TA = +25C
(Note 4) Note 1: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not 2:
tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at min. values with an external clock applied to the OSC1/CLKI pin. 3: PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. 4: This parameter is characterized, but not tested in manufacturing. 2011 Microchip Technology Inc. Preliminary DS61168C-page 255 PIC32MX1XX/2XX TABLE 29-16: PLL CLOCK TIMING SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. OS50 FPLLI OS51 FSYS OS52 OS53 TLOCK DCLK Symbol Characteristics(1) PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability(2)
(Period Jitter or Cumulative) Min. 3.92 60
-0.25 Typical Max. Units Conditions 5 MHz ECPLL, HSPLL, XTPLL, FRCPLL modes 120 MHz 2
+0.25 ms
% Measured over 100 ms period Note 1: These parameters are characterized, but not tested in manufacturing. 2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula:
EffectiveJitter
=
DCLK SYSCLK
--------------------------------------------------------------
----------------------------------------------------------
CommunicationClock For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
EffectiveJitter
=
=
DCLK
--------------
1.41 DCLK
--------------
40
------
20 TABLE 29-17:
INTERNAL FRC ACCURACY AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Characteristics Min. Typical Max. Units Conditions Internal FRC Accuracy @ 8.00 MHz(1) F20b Note 1: Frequency calibrated at 25C and 3.3V. The TUN bits can be used to compensate for temperature drift. FRC
+0.9
-0.9
%
TABLE 29-18:
INTERNAL LPRC ACCURACY AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Characteristics Min. Typical Max. Units Conditions LPRC @ 31.25 kHz(1) F21 Note 1: Change of LPRC frequency as VDD changes. LPRC
-15
+15
%
DS61168C-page 256 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-3:
I/O TIMING CHARACTERISTICS I/O Pin
(Input) I/O Pin
(Output) DI35 DI40 Note: Refer to Figure 29-1 for load conditions. DO31 DO32 TABLE 29-19:
I/O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(2) Min. Typical(1) Max. Units Conditions Param. No. DO31 TIOR Port Output Rise Time DO32 TIOF Port Output Fall Time 10 2 5 5 5 5 15 10 15 10 ns ns ns ns ns TSYSCLK VDD < 2.5V VDD > 2.5V VDD < 2.5V VDD > 2.5V TINP TRBP DI35 DI40 Note 1: Data in Typical column is at 3.3V, 25C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing. INTx Pin High or Low Time CNx High or Low Time (input) 2011 Microchip Technology Inc. Preliminary DS61168C-page 257 PIC32MX1XX/2XX FIGURE 29-4:
POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR
(TSYSDLY) SY02 Power-up Sequence
(Note 2) CPU Starts Fetching Code SY00
(TPU)
(Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD
(TSYSDLY) SY02 VPOR Power-up Sequence
(Note 2) SY00
(TPU)
(Note 1) SY10
(TOST) CPU Starts Fetching Code Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN). Includes interval voltage regulator stabilization delay. 2:
DS61168C-page 258 Preliminary 2011 Microchip Technology Inc. FIGURE 29-5:
EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) PIC32MX1XX/2XX MCLR BOR Reset Sequence TMCLR
(SY20) TBOR
(SY30)
(TSYSDLY) SY02 CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY) SY02 Reset Sequence TABLE 29-20: RESETS TIMING AC CHARACTERISTICS TOST
(SY10) CPU Starts Fetching Code Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions TPU Power-up Period Internal Voltage Regulator Enabled TSYSDLY System Delay Period:
Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. MCLR Pulse Width (low) BOR Pulse Width (low) 400 1 s +
8 SYSCLK cycles 600 s s s TMCLR TBOR SY20 SY30 Note 1: These parameters are characterized, but not tested in manufacturing. 2 1 2: Data in Typ column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. Param. No. SY00 SY02 2011 Microchip Technology Inc. Preliminary DS61168C-page 259 PIC32MX1XX/2XX FIGURE 29-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRx Tx10 Tx11 Tx15 OS60 Tx20 Note: Refer to Figure 29-1 for load conditions. TABLE 29-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(2) Min. Typical Max. Units Conditions Param. No. TA10 TTXH TxCK High Time TA11 TTXL TxCK Low Time TA15 TTXP TxCK Input Period OS60 FT1 SOSC1/T1CK Oscillator Input Frequency Range
(oscillator enabled by setting TCS bit (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: Timer1 is a Type A. Synchronous, with prescaler Asynchronous, with prescaler Synchronous, with prescaler Asynchronous, with prescaler Synchronous, with prescaler Asynchronous, with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns 10
[(12.5 ns or 1 TPB)/N]
+ 25 ns 10
[(Greater of 25 ns or 2 TPB)/N] + 30 ns
[(Greater of 25 ns or 2 TPB)/N] + 50 ns 20 50 32 ns Must also meet parameter TA15 ns ns Must also meet parameter TA15 ns ns ns ns ns VDD > 2.7V VDD < 2.7V VDD > 2.7V
(Note 3) VDD < 2.7V
(Note 3) 100 kHz 1 TPB 2: This parameter is characterized, but not tested in manufacturing. 3: N = Prescale Value (1, 8, 64, 256). DS61168C-page 260 Preliminary 2011 Microchip Technology Inc. Param. No. TB10 PIC32MX1XX/2XX TABLE 29-22: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature AC CHARACTERISTICS
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Max. Units Conditions TTXH TxCK High Time Synchronous, with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns TB11 TTXL TxCK Low Time Synchronous, with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns TB15 TTXP TxCK Input Period Synchronous, with prescaler
[(Greater of [(25 ns or 2 TPB)/N] + 30 ns
[(Greater of [(25 ns or 2 TPB)/N] + 50 ns N = prescale value
(1, 2, 4, 8, 16, 32, 64, 256) 1 ns Must also meet parameter TB15 ns Must also meet parameter TB15 ns VDD > 2.7V ns VDD < 2.7V TPB TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 29-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx Note: Refer to Figure 29-1 for load conditions. IC10 IC11 IC15 TABLE 29-23:
INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Max. Units Conditions Param. No. IC10 TCCL ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns IC11 TCCH ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns N = prescale value (1, 4, 16) ns Must also meet parameter IC15. ns Must also meet parameter IC15. IC15 TCCP ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns ns Note 1: These parameters are characterized, but not tested in manufacturing. 2011 Microchip Technology Inc. Preliminary DS61168C-page 261 PIC32MX1XX/2XX FIGURE 29-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx
(Output Compare or PWM mode) OC11 OC10 Note: Refer to Figure 29-1 for load conditions. TABLE 29-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. Symbol Characteristics(1) No. OC10 OC11 Note 1: These parameters are characterized, but not tested in manufacturing. OCx Output Fall Time OCx Output Rise Time TCCF TCCR Min. Typical(2) Max. Units Conditions ns ns See parameter DO32 See parameter DO31 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-9:
OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OC15 OCFA/OCFB OCx Note: Refer to Figure 29-1 for load conditions. OCx is tri-stated TABLE 29-25: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param Symbol Characteristics(1) Min Typical(2) No. OC15 OC20 Note 1: These parameters are characterized, but not tested in manufacturing. Fault Input to PWM I/O Change Fault Input Pulse Width TFD TFLT 50 Max Units Conditions 50 ns ns 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. DS61168C-page 262 Preliminary 2011 Microchip Technology Inc. FIGURE 29-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS PIC32MX1XX/2XX SCKx
(CKP = 0) SCKx
(CKP = 1) SDOx SDIx SP11 SP10 SP21 SP20 SP20 SP21 MSb Bit 14 - - - - - -1 LSb SP30 Bit 14 - - - -1 LSb In SP35 SP31 MSb In SP40 SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-26: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions Param. No. SP10 TSCL SP11 TSCH SP20 TSCF SP21 TSCR SP30 TDOF SP31 TDOR SP35 SP40 SP41 TSCH2DOV, TSCL2DOV TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL SCKx Output Low Time
(Note 3) SCKx Output High Time
(Note 3) SCKx Output Fall Time
(Note 4) SCKx Output Rise Time
(Note 4) SDOx Data Output Fall Time
(Note 4) SDOx Data Output Rise Time
(Note 4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge TSCK/2 TSCK/2 10 10 15 20 ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. 2011 Microchip Technology Inc. Preliminary DS61168C-page 263 PIC32MX1XX/2XX FIGURE 29-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX
(CKP = 0) SCKX
(CKP = 1) SDOX SDIX SP11 SP10 SP21 SP20 SP35 SP20 SP21 MSb Bit 14 - - - - - -1 LSb SP30,SP31 MSb In SP41 SP40 Bit 14 - - - -1 LSb In Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions AC CHARACTERISTICS Param. No. SP10 SP11 SP20 SP21 SP30 TSCL TSCH TSCF TSCR TDOF SP31 TDOR SP35 SP36 SP40 SP41 TSCH2DOV, TSCL2DOV TDOV2SC, TDOV2SCL TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL SCKx Output Low Time (Note 3) TSCK/2 SCKx Output High Time (Note 3) TSCK/2 SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time
(Note 4) SDOx Data Output Rise Time
(Note 4) SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge 15 15 20 15 20 15 20 ns ns ns ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V VDD > 2.7V VDD < 2.7V VDD > 2.7V VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS61168C-page 264 Preliminary 2011 Microchip Technology Inc. FIGURE 29-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS PIC32MX1XX/2XX SSX SCKX
(CKP = 0) SCKX
(CKP = 1) SDOX SDIX SP50 SP52 SP71 SP70 SP73 SP72 SP35 SP72 SP73 MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 Bit 14 - - - -1 LSb In SP40 MSb In SP41 Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature -40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, TSCL2DOV TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL TSSL2SCH, TSSL2SCL TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3) SSx after SCKx Edge TSCH2SSH TSCL2SSH TSCK/2 TSCK/2 10 10 175 5 TSCK + 20 15 20 25 ns ns ns ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. 2011 Microchip Technology Inc. Preliminary DS61168C-page 265 PIC32MX1XX/2XX FIGURE 29-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SCKx
(CKP = 0) SCKx
(CKP = 1) SDOx SDI SDIx SP50 SP52 SP71 SP70 SP73 SP72 SP35 SP72 SP73 MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SP40 MSb In SP41 Bit 14 - - - -1 LSb In Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature -40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions AC CHARACTERISTICS Param. No. SP70 SP71 SP72 SP73 SP30 TSCL TSCH TSCF TSCR TDOF SP31 TDOR SP35 SP40 SP41 SP50 TSCH2DOV, TSCL2DOV TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL TSSL2SCH, TSSL2SCL SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time
(Note 4) SDOx Data Output Rise Time
(Note 4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input TSCK/2 TSCK/2 10 10 175 5 5 10 10 20 30 ns ns ns ns ns ns ns ns ns ns ns See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. DS61168C-page 266 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature -40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. SP51 SP52 SP60 Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions TSSH2DOZ SSx to SDOX Output High-Impedance
(Note 4) SSx after SCKx Edge TSCH2SSH TSCL2SSH TSSL2DOV SDOx Data Output Valid after SSx Edge 5 TSCK +
20 25 25 ns ns ns Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. 2011 Microchip Technology Inc. Preliminary DS61168C-page 267 PIC32MX1XX/2XX FIGURE 29-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx SDAx IM31 IM30 Start Condition Note: Refer to Figure 29-1 for load conditions. IM34 IM33 Stop Condition FIGURE 29-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM40 IM11 IM26 IM10 IM40 IM21 IM25 IM33 IM45 SCLx SDAx In SDAx Out Note: Refer to Figure 29-1 for load conditions. DS61168C-page 268 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-30:
I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 Symbol Characteristics Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) TF:SCL TR:SCL SDAx and SCLx Rise Time SDAx and SCLx Fall Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) THD:STA Start Condition TSU:STO Stop Condition TSU:STA Start Condition THD:STO Stop Condition Setup Time Setup Time Hold Time Hold Time TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) 20 + 0.1 CB 20 + 0.1 CB 250 100 100 0 0 0 TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) 300 300 100 1000 300 300 0.9 0.3 CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns Note 1: BRG is the value of the I2C Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns. 2011 Microchip Technology Inc. Preliminary DS61168C-page 269 PIC32MX1XX/2XX TABLE 29-30:
I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics Min.(1) Max. Units Conditions Param. No. IM40 TAA:SCL Output Valid from Clock IM45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 2) 4.7 1.3 0.5 3500 1000 350 400 312 ns ns ns s s s pF ns The amount of time the bus must be free before a new transmission can start See Note 3 CB TPGD IM50 IM51 52 Note 1: BRG is the value of the I2C Baud Rate Generator. Bus Capacitive Loading Pulse Gobbler Delay 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns. DS61168C-page 270 Preliminary 2011 Microchip Technology Inc. FIGURE 29-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) PIC32MX1XX/2XX SCLx SDAx IS31 IS30 Start Condition Note: Refer to Figure 29-1 for load conditions. IS34 IS33 Stop Condition FIGURE 29-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS30 IS31 IS26 IS40 IS10 IS40 IS25 IS33 IS45 SCLx SDAx In SDAx Out Note: Refer to Figure 29-1 for load conditions. 2011 Microchip Technology Inc. Preliminary DS61168C-page 271 PIC32MX1XX/2XX TABLE 29-31:
I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics Min. Max. Units Conditions Param. No. IS10 TLO:SCL Clock Low Time 100 kHz mode IS11 THI:SCL Clock High Time IS20 TF:SCL SDAx and SCLx Fall Time IS21 TR:SCL SDAx and SCLx Rise Time IS25 TSU:DAT Data Input Setup Time IS26 THD:DAT Data Input Hold Time IS30 TSU:STA Start Condition Setup Time IS31 THD:STA Start Condition Hold Time IS33 TSU:STO Stop Condition Setup Time 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 4.7 1.3 0.5 4.0 0.6 0.5 20 + 0.1 CB 20 + 0.1 CB 250 100 100 0 0 0 4700 600 250 4000 600 250 4000 600 600 300 300 100 1000 300 300 0.9 0.3 PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF s s s s s s ns ns ns ns ns ns ns ns ns ns s s ns Only relevant for Repeated ns ns Start condition After this period, the first clock pulse is generated ns ns ns ns ns ns Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS61168C-page 272 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-31:
I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics Max. Units Conditions Param. No. IS34 THD:STO Stop Condition Hold Time IS40 TAA:SCL Output Valid from Clock IS45 TBF:SDA Bus Free Time Min. 4000 600 250 0 0 0 4.7 1.3 0.5 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 100 kHz mode 400 kHz mode 1 MHz mode
(Note 1) 3500 1000 350 ns ns ns ns ns ns s s s The amount of time the bus must be free before a new transmission can start CB IS50 pF Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). Bus Capacitive Loading 400 2011 Microchip Technology Inc. Preliminary DS61168C-page 273 PIC32MX1XX/2XX TABLE 29-32: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Symbol Characteristics Min. Typical Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply AVSS VREFH AD02 Reference Inputs AD05 AD05a AD06 AD07 VREFL VREF AD08 IREF Module VSS Supply Reference Voltage High AVSS + 2.0 Reference Voltage Low Absolute Reference Voltage (VREFH VREFL) Current Drain Analog Input AD12 AD13 AD14 AD15 VINH-VINL Full-Scale Input Span VINL Absolute VINL Input Voltage Absolute Input Voltage Leakage Current VIN AD17 RIN Recommended Impedance of Analog Voltage Source Greater of VDD 0.3 or 2.5 VSS 2.5 AVSS 2.0 VREFL AVSS 0.3 AVSS 0.3 250
+/- 0.001 Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 VREFH 2.0 AVDD V V V V V V
(Note 1) VREFH = AVDD (Note 3)
(Note 1)
(Note 3) 400 3 A A ADC operating ADC off VREFH AVDD/2 V V AVDD + 0.3
+/-0.610 V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k 5K
(Note 1) ADC Accuracy Measurements with External VREF+/VREF-
AD20c Nr AD21c INL Resolution Integral Nonlinearity
> -1 10 data bits AD22c DNL Differential Nonlinearity
> -1 AD23c GERR Gain Error AD24n EOFF Offset Error
> -1
> -1
< 1
< 1
< 1
< 1 bits LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V
(Note 2) LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V Guaranteed AD25c Note 1: These parameters are not characterized or tested in manufacturing. Monotonicity 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with a 1 kHz sine wave. DS61168C-page 274 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-32: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param. No. Symbol Characteristics Min. Typical Max. Units Conditions ADC Accuracy Measurements with Internal VREF+/VREF-
AD20d Nr AD21d INL Resolution Integral Nonlinearity
> -1 10 data bits AD22d DNL Differential Nonlinearity
> -1 AD23d GERR Gain Error AD24d EOFF Offset Error Monotonicity AD25d Dynamic Performance AD31b SINAD Signal to Noise and Distortion Effective Number of Bits
> -4
> -2 55 58.5
< 1
< 1
< 4
< 2
(Note 3) bits LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V
(Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V
(Notes 2,3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V
(Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V
(Note 3) Guaranteed dB (Notes 3,4) bits
(Notes 3,4) AD34b ENOB Note 1: These parameters are not characterized or tested in manufacturing. 9.0 9.5 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with a 1 kHz sine wave. 2011 Microchip Technology Inc. Preliminary DS61168C-page 275 PIC32MX1XX/2XX TABLE 29-33: 10-BIT CONVERSION RATE PARAMETERS PIC32 10-bit ADC Conversion Rates(2) ADC Speed 1 Msps to 400 ksps(1) TAD Min. 65 ns Sampling Time Min. 132 ns RS Max. VDD Temperature ADC Channels Configuration 500 3.0V to 3.6V
-40C to
+85C VREF- VREF+
ANx CHX SHA ADC Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V
-40C to
+85C Up to 300 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V
-40C to
+85C ANx ANx or VREF-
ANx ANx or VREF-
Note 1: External VREF- and VREF+ pins must be used for correct operation. 2: These parameters are characterized, but not tested in manufacturing. VREF- VREF+
AVSS AVDD or or CHX SHA ADC VREF- VREF+
AVSS AVDD or or CHX SHA ADC DS61168C-page 276 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-34: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Characteristics Min. Typical(1) Max. Units Conditions TAD Clock Parameters AD50 Conversion Rate AD55 AD56 TCONV FCNV TSAMP AD57 Timing Parameters AD60 TPCS ADC Clock Period(2) Conversion Time Throughput Rate
(Sampling Speed) Sample Time Conversion Start from Sample Trigger(3) AD61 TPSS AD62 TCSS AD63 TDPU Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1)(3) Time to Stabilize Analog Stage from ADC Off to ADC On(3) 65 1 TAD ns See Table 29-33 12 TAD 1000 400 ksps ksps TSAMP must be 132 ns AVDD = 3.0V to 3.6V AVDD = 2.5V to 3.6V 1.0 TAD 0.5 TAD 1.5 TAD Auto-Convert Trigger
(SSRC<2:0> = 111) not selected 0.5 TAD 2 s Note 1: These parameters are characterized, but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. 2011 Microchip Technology Inc. Preliminary DS61168C-page 277 PIC32MX1XX/2XX FIGURE 29-18:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 Set SAMP Clear SAMP AD61 AD60 TSAMP AD55 AD55 ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp eoc CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 Software sets ADxCON. SAMP to start sampling. 2 Sampling starts after discharge period. TSAMP is described in Section 17. 10-bit Analog-to-Digital Converter (ADC)
(DS61104) in the PIC32 Family Reference Manual. 3 Software clears ADxCON. SAMP to start conversion. 4 Sampling ends, conversion sequence starts. 5 Convert bit 9. 6 Convert bit 8. 7 Convert bit 0. 8 One TAD for end of conversion. DS61168C-page 278 Preliminary 2011 Microchip Technology Inc. FIGURE 29-19:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) PIC32MX1XX/2XX AD50 Set ADON ADCLK Instruction Execution SAMP ch0_dischrg ch0_samp eoc CONV ADxIF Buffer(0) Buffer(1) TSAMP AD55 AD55 TSAMP TCONV 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 Software sets ADxCON. ADON to start AD operation. 2 Sampling starts after discharge period. TSAMP is described in Section 17. 10-bit Analog-to-Digital Converter (ADC) (DS61104). 3 Convert bit 9. 4 Convert bit 8. 5 Convert bit 0. 6 One TAD for end of conversion. 7 Begin conversion of next channel. 8 Sample for time specified by SAMC<4:0>. FIGURE 29-20:
PARALLEL SLAVE PORT TIMING CS RD WR PMD<7:0>
PS5 PS6 PS3 PS4 PS7 PS1 PS2 2011 Microchip Technology Inc. Preliminary DS61168C-page 279 Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Min. Typ. Max. Units Conditions PIC32MX1XX/2XX TABLE 29-35: PARALLEL SLAVE PORT REQUIREMENTS AC CHARACTERISTICS Characteristics(1) Para m.No. Symbol TdtV2wr PS1 H TwrH2dt I TrdL2dt V TrdH2dtI RD Active or CS Inactive to Data In Valid before WR or CS Inactive (setup time) WR or CS Inactive to Data-In Invalid (hold time) RD and CS Active to Data-Out Valid PS4 PS2 PS3 20 40 0 60 10 Data-Out Invalid CS Active Time WR Active Time RD Active Time Tcs TWR TRD PS5 PS6 PS7 Note 1: These parameters are characterized, but not tested in manufacturing. TPB + 40 TPB + 25 TPB + 25 ns ns ns ns ns ns ns FIGURE 29-21:
PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PMA<13:18>
PMD<7:0>
PMRD PMWR PMALL/PMALH PMCS<2:1>
Address Address<7:0>
Address<7:0>
PM2 PM3 PM1 PM4 PM6 Data Data PM7 PM5 DS61168C-page 280 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-36: PARALLEL MASTER PORT READ TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Param. No. PM1 PM2 PM3 TLAT TADSU PMALL/PMALH Pulse Width Address Out Valid to PMALL/PMALH Invalid (address setup time) TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) PMRD Inactive to Address Out Invalid
(address hold time) PMRD Pulse Width PMRD or PMENB Active to Data In Valid (data setup time) TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time) PM4 TAHOLD TRD TDSU PM5 PM6 PM7 5 15 Typ. 1 TPB 2 TPB 1 TPB 1 TPB 80 Max. Units Conditions ns ns ns Note 1: These parameters are characterized, but not tested in manufacturing. FIGURE 29-22:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PMA<13:18>
PMD<7:0>
PMRD PMWR PMALL/PMALH PMCS<2:1>
Address PM2 + PM3 Address<7:0>
PM1 Data PM12 PM11 PM13 2011 Microchip Technology Inc. Preliminary DS61168C-page 281 Param. No. PM11 PM12 PIC32MX1XX/2XX TABLE 29-37: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Symbol Characteristics(1) Min. Typ. Max. Units Conditions TWR TDVSU PMWR Pulse Width Data Out Valid before PMWR or PMENB goes Inactive (data setup time) PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) 1 TPB 2 TPB 1 TPB Note 1: These parameters are characterized, but not tested in manufacturing. TABLE 29-38: OTG ELECTRICAL SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Characteristics(1) Min. Typical Max. Units Conditions USB313 VUSB USB Voltage USB315 VILUSB USB316 VIHUSB USB318 VDIFS Input Low Voltage for USB Buffer Input High Voltage for USB Buffer Differential Input Sensitivity USB319 VCM USB320 ZOUT USB321 VOL Differential Common Mode Range Driver Output Impedance Voltage Output Low USB322 VOH Voltage Output High 3.0 2.0 0.8 28.0 0.0 2.8 3.6 0.8 0.2 2.5 44.0 0.3 3.6 V V V V V V V Voltage on VUSB must be in this range for proper USB operation The difference between D+ and D-
must exceed this value while VCM is met 14.25 k load connected to 3.6V 14.25 k load connected to ground Note 1: These parameters are characterized, but not tested in manufacturing. DS61168C-page 282 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-39: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions:2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Param No. Symbol Characteristic Min. Typ. Max. Units Conditions CTMU CURRENT SOURCE CTMUI1 CTMUI2 CTMUI3 CTMUI4 CTMUFV1 VF IOUT1 IOUT2 IOUT3 IOUT4 Base Range(1) 10x Range(1) 100x Range(1) 1000x Range(1) Temperature Diode Forward Voltage(1,2) CTMUFV2 VFVR Temperature Diode Rate of Change(1,2) 0.55 5.5 55 550 0.598 0.658 0.721
-1.92
-1.74
-1.56 A A A A V CTMUICON<9:8> = 01 CTMUICON<9:8> = 10 CTMUICON<9:8> = 11 CTMUICON<9:8> = 00 TA = +25C, CTMUICON<9:8> = 01 TA = +25C, CTMUICON<9:8> = 10 TA = +25C, CTMUICON<9:8> = 11 mV/C CTMUICON<9:8> = 01 mV/C CTMUICON<9:8> = 10 mV/C CTMUICON<9:8> = 11 V V Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000). 2: Parameters are characterized but not tested in manufacturing. Measurements taken with the following conditions:
VREF+ = AVDD = 3.3V ADC module configured for conversion speed of 500 ksps All PMD bits are cleared (PMDx = 0) Executing a while(1) statement Device operating from the FRC with no PLL 2011 Microchip Technology Inc. Preliminary DS61168C-page 283 PIC32MX1XX/2XX FIGURE 29-23:
EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK TMS TDI TDO TRST*
TTRST*low Trf TTsetup TThold Trf TTDOout Trf Trf TTDOzstate Defined Undefined TABLE 29-40: EJTAG TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. Symbol Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated) Operating temperature
-40C TA +85C for Industrial
-40C TA +105C for V-temp Description(1) Min. Max. Units Conditions EJ1 EJ2 EJ3 EJ4 EJ5 EJ6 EJ7 EJ8 EJ9 TTCKCYC TTCKHIGH TTCKLOW TTSETUP TTHOLD TTDOOUT TCK Cycle Time TCK High Time TCK Low Time TAP Signals Setup Time Before Rising TCK TAP Signals Hold Time After Rising TCK TDO Output Delay Time from Falling TCK TTDOZSTATE TDO 3-State Delay Time from TTRSTLOW TRF Falling TCK TRST Low Time TAP Signals Rise/Fall Time, All Input and Output 25 10 10 5 3 25 5 5 ns ns ns ns ns ns ns ns ns Note 1: These parameters are characterized, but not tested in manufacturing. DS61168C-page 284 Preliminary 2011 Microchip Technology Inc. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 2 8 5 30.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 30-1:
I/O OUTPUT VOLTAGE HIGH (VOH) FIGURE 30-2:
I/O OUTPUT VOLTAGE LOW (VOL)
)
)
(
(
A A H H O O I I
-0.050
-0.050
-0.045
-0.045
-0.040
-0.040
-0.035
-0.035
-0.030
-0.030
-0.025
-0.025
-0.020
-0.020
-0.015
-0.010
-0.005 0.000 VOH (V) VOH (V) 3.6V 3.3V 3V Absolute Maximum I I
)
)
(
(
A A H H O O VOL(V) VOL(V) 3.6V 3.3V 3V Absolute Maximum 0.050 0.050 0.045 0.045 0.040 0.040 0.035 0.035 0.030 0.030 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 I P C 3 2 M X 1 X X 2 X X
/
FIGURE 30-3:
TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 30-5:
TYPICAL IIDLE CURRENT @ VDD = 3.3V
)
) A A
(
(
D D P P I I 400 400 350 350 300 300 250 250 200 200 150 150 100 50 0
-40
-30
-20
-10 0 10 20 30 40 50 60 70 80 90 100
)
) A A m m
(
(
t t n n e e r r r r u u C C E E L L D D I I I I 16 16 14 14 12 12 10 10 8 8 6 6 4 2 0 Temperature (Celsius) 0 10 20 MIPS 30 40 FIGURE 30-4:
TYPICAL IDD CURRENT @ VDD = 3.3V I P C 3 2 M X 1 X X 2 X X
/
D S 6 1 1 6 8 C
-
p a g e 2 8 6 P r e l i i m n a r y
)
) A A m m
(
(
D D D D I I 25 25 20 20 15 15 10 10 5 0 0 10 20 MIPS 30 40 i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. i 2 0 1 1 M c r o c h p T e c h n o o g y I i l n c
. P r e l i i m n a r y D S 6 1 1 6 8 C
-
p a g e 2 8 7 FIGURE 30-6:
TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 30-8:
TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE
)
) z z H H k k
(
(
y y c c n n e e u u q q e e r r F F C C R R F F 8000 8000 7990 7990 7980 7980 7970 7970 7960 7960 7950 7950 7940 7940 7930 7930 7920 7910 7900
)
) V V
(
(
e e g g a a t t l l o o V V d d r r a a w w r r o o F F 0.850 0.850 0.800 0.800 0.750 0.750 0.700 0.700 0.650 0.650 0.600 0.600 0.550 0.550 0.500 0 500 0.450 0.400 0.350 VF = 0.721 VF = 0.658 VF = 0.598 55 A, VFVR = -1.56 mV/C 5.5 A, VFVR = -1.74 mV/C 0.55 A, VFVR = -1.92 mV/C
-40
-30
-20
-10 0 10 20 30 40 50 60 70 80 90 100
-40
-30
-20
-10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (Celsius) Temperature (Celsius) FIGURE 30-7:
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
)
) z z H H k k
(
(
y y c c n n e e u u q q e e r r F F C C R R P P L L 33 33 32 32 31 31 30
-40
-30
-20
-10 0 10 20 30 40 50 60 70 80 90 100 Temperature (Celsius) I P C 3 2 M X 1 X X 2 X X
/
PIC32MX1XX/2XX NOTES:
DS61168C-page 288 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX 31.0 PACKAGING INFORMATION Package Marking Information 31.1 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC32MX220F 032B-I/SO 3e 1130235 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC32MX220F 032B-I/SP 3e 1130235 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Example PIC32MX220F 032B-I/SS 3e 1130235 Example 32MX220F 032BE/ML 1130235 3e Legend: XX...X Customer-specific information Y YY WW NNN 3e
*
Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week 01) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) 3e can be found on the outer packaging for this package. Note:
If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011 Microchip Technology Inc. Preliminary DS61168C-page 289 PIC32MX1XX/2XX 31.1 Package Marking Information (Continued) 36-Lead VTLA (TLA) Example XXXXXXXX XXXXXXXX YYWWNNN 32MX220F 032CE/TL 1130235 3e 44-Lead VTLA (TLA) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32 MX120F0 32DI/TL 1130235 3e 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 32MX220F 032D-E/ML 1130235 3e 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 32MX220F 032D-I/PT 3e 1130235 Legend: XX...X Customer-specific information Y YY WW NNN 3e
*
Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week 01) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) 3e can be found on the outer packaging for this package. Note:
If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. DS61168C-page 290 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX Package Details 31.2 This section provides the technical details of the packages.
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2011 Microchip Technology Inc. Preliminary DS61168C-page 291 PIC32MX1XX/2XX Note:
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For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS61168C-page 305 PIC32MX1XX/2XX Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61168C-page 306 Preliminary 2011 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision A (May 2011) This is the initial released version of this document. Revision B (October 2011) The following two global changes are included in this revision:
All packaging references to VLAP have been changed to VTLA throughout the document All references to VCORE have been removed All occurrences of the ASCL1, ASCL2, ASDA1, and ASDA2 pins have been removed PIC32MX1XX/2XX This revision includes the addition of the following devices:
PIC32MX130F064B PIC32MX130F064C PIC32MX130F064D PIC32MX150F128B PIC32MX150F128C PIC32MX150F128D Text and throughout the document. All other major changes are referenced by their respective section in Table A-1. PIC32MX230F064B PIC32MX230F064C PIC32MX230F064D PIC32MX250F128B PIC32MX250F128C PIC32MX250F128D incorporated formatting changes were V-temp temperature range (-40C to +105C) was added to all electrical specification tables TABLE A-1:
MAJOR SECTION UPDATES Section Name 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog 1.0 Device Overview 2.0 Guidelines for Getting Started with 32-bit Microcontrollers Update Description Split the existing Features table into two: PIC32MX1XX General Purpose Family Features (Table 1) and PIC32MX2XX USB Family Features (Table 2). Added the SPDIP package reference (see Table 1, Table 2, and Pin Diagrams). Added the new devices to the applicable pin diagrams. Changed PGED2 to PGED1 on pin 35 of the 36-pin VTLA diagram for PIC32MX220F032C, PIC32MX220F016C, PIC32MX230F064C, and PIC32MX250F128C devices. Added the SPDIP package reference and updated the pin number for AN12 for 44-pin QFN devices in the Pinout I/O Descriptions (see Table 1-1). Added the PGEC4/PGED4 pin pair and updated the C1INA-C1IND and C2INA-C2IND pin numbers for 28-pin SSOP/SPDIP/SOIC devices in the Pinout I/O Descriptions (see Table 1-1). Updated the Recommended Minimum Connection diagram (see Figure 2-1). 2011 Microchip Technology Inc. Preliminary DS61168C-page 307 PIC32MX1XX/2XX TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description 4.0 Memory Organization Added Memory Maps for the new devices (see Figure 4-3 and Figure 4-4). Removed the BMXCHEDMA bit from the Bus Matrix Register map (see Table 4-1). Added the REFOTRIM register, added the DIVSWEN bit to the REFOCON registers, added Note 4 to the ULOCK and SOSCEN bits and added the PBDIVRDY bit in the OSCCON register in the in the System Control Register map (see Table 4-16). Removed the ALTI2C1 and ALTI2C2 bits from the DEVCFG3 register and added Note 1 to the UPLLEN and UPLLIDIV<2:0> bits of the DEVCFG2 register in the Device Configuration Word Summary (see Table 4-17). Updated Note 1 in the Device and Revision ID Summary (see Table 4-18). Added Note 2 to the PORTA Register map (see Table 4-19). Added the ANSB6 and ANSB12 bits to the ANSELB register in the PORTB Register map (see Table 4-20). Added Notes 2 and 3 to the PORTC Register map (see Table 4-21). Updated all register names in the Peripheral Pin Select Register map (see Table 4-23). Added values in support of new devices (16 KB RAM and 32 KB RAM) in the Data RAM Size register (see Register 4-5). Added values in support of new devices (64 KB Flash and 128 KB Flash) in the Data RAM Size register (see Register 4-5). Added Note 5 to the PIC32MX1XX/2XX Family Clock Diagram (see Figure 8-1). Added the PBDIVRDY bit and Note 2 to the Oscillator Control register (see Register 8-1). Added the DIVSWEN bit and Note 3 to the Reference Oscillator Control register (see Register 8-3). Added the REFOTRIM register (see Register 8-4). Updated the ADC1 Module Block Diagram (see Figure 21-1). Updated the Notes in the ADC Input Select register (see Register 21-4). Updated the CTMU Block Diagram (see Figure 24-1). Added Note 3 to the CTMU Control register (see Register 24-1) Added Note 1 and the PGEC4/PGED4 pin pair to the ICESEL<1:0> bits in DEVCFG0: Device Configuration Word 0 (see Register 26-1). Removed the ALTI2C1 and ALTI2C2 bits from the Device Configuration Word 3 register (see Register 26-4). Removed 26.3.3 Power-up Requirements. Added Note 3 to the Connections for the On-Chip Regulator diagram (see Figure 26-2). Updated the Block Diagram of Programming, Debugging and Trace Ports diagram (see Figure 26-3). 8.0 Oscillator Configuration 21.0 10-bit Analog-to-Digital Converter (ADC) 24.0 Charge Time Measurement Unit (CTMU) 26.0 Special Features DS61168C-page 308 Preliminary 2011 Microchip Technology Inc. TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED) PIC32MX1XX/2XX Section Name 29.0 Electrical Characteristics 31.0 Packaging Information Product Identification System Update Description Updated the Absolute Maximum Ratings (removed Voltage on VCORE with respect to VSS). Added the SPDIP specification to the Thermal Packaging Characteristics
(see Table 29-2). Updated the Typical values for parameters DC20-DC24 in the Operating Current (IDD) specification (see Table 29-5). Updated the Typical values for parameters DC30a-DC34a in the Idle Current
(IIDLE) specification (see Table 29-6). Updated the Typical values for parameters DC40i and DC40n and removed parameter DC40m in the Power-down Current (IPD) specification (see Table 29-7). Removed parameter D320 (VCORE) from the Internal Voltage Regulator Specifications and updated the Comments (see Table 29-13). Updated the Minimum, Typical, and Maximum values for parameter F20b in the Internal FRC Accuracy specification (see Table 29-17). Removed parameter SY01 (TPWRT) and removed all Conditions from Resets Timing (see Table 29-20). Updated all parameters in the CTMU Specifications (see Table 29-39). Added the 28-lead SPDIP package diagram information (see 31.1 Package Marking Information and 31.2 Package Details). Added the SPDIP (SP) package definition. 2011 Microchip Technology Inc. Preliminary DS61168C-page 309 PIC32MX1XX/2XX Revision C (November 2011) All major changes are referenced by their respective section in Table A-2. TABLE A-2:
MAJOR SECTION UPDATES Section Name 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog 4.0 Memory Organization 29.0 Electrical Characteristics Update Description Revised the source/sink on I/O pins (see Input/Output on page 1). Added the SPDIP package to the PIC32MX220F032B device in the PIC32MX2XX USB Family Features (see Table 2). Removed ANSB6 from the ANSELB register and added the ODCB6, ODCB10, and ODCB11 bits in the PORTB Register Map (see Table 4-20). Updated the minimum value for parameter OS50 in the PLL Clock Timing Specifications (see Table 29-16). DS61168C-page 310 Preliminary 2011 Microchip Technology Inc. INDEX A AC Characteristics ............................................................ 254 10-Bit Conversion Rate Parameters ......................... 276 ADC Specifications ................................................... 274 Analog-to-Digital Conversion Requirements............. 277 EJTAG Timing Requirements ................................... 284 Internal FRC Accuracy.............................................. 256 Internal RC Accuracy ................................................ 256 OTG Electrical Specifications ................................... 282 Parallel Master Port Read Requirements ................. 281 Parallel Master Port Write ......................................... 282 Parallel Master Port Write Requirements.................. 282 Parallel Slave Port Requirements............................. 280 PLL Clock Timing...................................................... 256 Analog-to-Digital Converter (ADC).................................... 203 Assembler MPASM Assembler................................................... 242 B Block Diagrams ADC Module.............................................................. 203 Comparator I/O Operating Modes............................. 211 Comparator Voltage Reference ................................ 215 Connections for On-Chip Voltage Regulator............. 237 Core and Peripheral Modules ..................................... 19 CPU ............................................................................ 33 CTMU Configurations Time Measurement........................................... 217 DMA.......................................................................... 105 I2C Circuit ................................................................. 174 Input Capture ............................................................ 159 Interrupt Controller ...................................................... 87 JTAG Programming, Debugging and Trace Ports .... 237 Output Compare Module........................................... 163 PMP Pinout and Connections to External Devices ... 185 Reset System.............................................................. 83 RTCC........................................................................ 193 SPI Module ............................................................... 165 Timer1....................................................................... 151 Timer2/3/4/5 (16-Bit) ................................................. 155 Typical Multiplexed Port Structure ............................ 143 UART ........................................................................ 179 WDT and Power-up Timer ........................................ 235 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 237 C C Compilers MPLAB C18 .............................................................. 242 Charge Time Measurement Unit. See CTMU. Clock Diagram .................................................................... 96 Comparator Specifications............................................................ 253 Comparator Module .......................................................... 211 Comparator Voltage Reference (CVref............................. 215 Configuration Bit ............................................................... 225 Configuring Analog Port Pins............................................ 144 CPU Architecture Overview................................................. 34 Coprocessor 0 Registers ............................................ 35 Core Exception Types................................................. 36 EJTAG Debug Support ............................................... 36 Power Management.................................................... 36 PIC32MX1XX/2XX CPU Module ................................................................. 27, 33 CTMU Registers .................................................................. 218 Customer Change Notification Service............................. 315 Customer Notification Service .......................................... 315 Customer Support............................................................. 315 D DC and AC Characteristics Graphs and Tables ................................................... 285 DC Characteristics............................................................ 246 I/O Pin Input Specifications ...................................... 250 I/O Pin Output Specifications.................................... 251 Idle Current (IIDLE) .................................................... 248 Power-Down Current (IPD)........................................ 249 Program Memory...................................................... 252 Temperature and Voltage Specifications.................. 247 Development Support....................................................... 241 Direct Memory Access (DMA) Controller.......................... 105 E Electrical Characteristics .................................................. 245 AC............................................................................. 254 Errata.................................................................................. 16 External Clock Timer1 Timing Requirements ................................... 260 Timer2, 3, 4, 5 Timing Requirements ....................... 261 Timing Requirements ............................................... 255 F Flash Program Memory ...................................................... 79 RTSP Operation ......................................................... 79 I I/O Ports ........................................................................... 143 Parallel I/O (PIO) ...................................................... 144 Write/Read Timing.................................................... 144 Input Change Notification ................................................. 144 Instruction Set................................................................... 239 Inter-Integrated Circuit (I2C .............................................. 173 Internal Voltage Reference Specifications........................ 253 Internet Address ............................................................... 315 Interrupt Controller.............................................................. 87 IRG, Vector and Bit Location ...................................... 88 M Memory Maps PIC32MX11X/21X Devices......................................... 38 PIC32MX12X/22X Devices......................................... 39 PIC32MX130/230 Devices ......................................... 40 PIC32MX150/250 Devices ......................................... 41 Memory Organization ......................................................... 37 Layout......................................................................... 37 Microchip Internet Web Site.............................................. 315 MPLAB ASM30 Assembler, Linker, Librarian................... 242 MPLAB Integrated Development Environment Software.. 241 MPLAB PM3 Device Programmer .................................... 244 MPLAB REAL ICE In-Circuit Emulator System ................ 243 MPLINK Object Linker/MPLIB Object Librarian................ 242 O Oscillator Configuration ...................................................... 95 Output Compare ............................................................... 163 2011 Microchip Technology Inc. Preliminary DS61168C-page 311 PIC32MX1XX/2XX P Packaging ......................................................................... 289 Details ....................................................................... 291 Marking ..................................................................... 289 Parallel Master Port (PMP) ............................................... 185 PIC32 Family USB Interface Diagram............................... 122 Pinout I/O Descriptions (table) ............................................ 20 Power-on Reset (POR) and On-Chip Voltage Regulator................................ 237 Power-Saving Features..................................................... 221 CPU Halted Methods ................................................ 221 Operation .................................................................. 221 with CPU Running..................................................... 221 R Reader Response ............................................................. 316 Real-Time Clock and Calendar (RTCC)............................ 193 Register Maps............................................................... 4270 Registers
[pin name]R (Peripheral Pin Select Input)................. 149 AD1CHS (ADC Input Select) .................................... 209 AD1CON1 (A/D Control 1) ........................................ 201 AD1CON1 (ADC Control 1) .............................. 201, 205 AD1CON2 (ADC Control 2) ...................................... 207 AD1CON3 (ADC Control 3) ...................................... 208 AD1CSSL (ADC Input Scan Select) ......................... 210 ALRMDATE (Alarm Date Value)............................... 201 ALRMDATECLR (ALRMDATE Clear)....................... 201 ALRMDATESET (ALRMDATE Set) .......................... 201 ALRMTIME (Alarm Time Value) ............................... 200 ALRMTIMECLR (ALRMTIME Clear)......................... 201 ALRMTIMEINV (ALRMTIME Invert) ......................... 201 ALRMTIMESET (ALRMTIME Set) ............................ 201 BMXBOOTSZ (Boot Flash (IFM) Size ........................ 78 BMXCON (Bus Matrix Configuration) ......................... 73 BMXDKPBA (Data RAM Kernel Program Base Address) .................................................... 74 BMXDRMSZ (Data RAM Size Register) ..................... 77 BMXDUDBA (Data RAM User Data Base Address) ... 75 BMXDUPBA (Data RAM User Program Base Address) .................................................... 76 BMXPFMSZ (Program Flash (PFM) Size) .................. 78 BMXPUPBA (Program Flash (PFM) User Program Base Address) .................................................... 77 CM1CON (Comparator 1 Control) ............................ 212 CMSTAT (Comparator Control Register).................. 213 CNCONx (Change Notice Control for PORTx) ......... 150 CTMUCON (CTMU Control) ..................................... 218 CVRCON (Comparator Voltage Reference Control). 216 DCHxCON (DMA Channel x Control) ....................... 111 DCHxCPTR (DMA Channel x Cell Pointer)............... 118 DCHxCSIZ (DMA Channel x Cell-Size) .................... 118 DCHxDAT (DMA Channel x Pattern Data) ............... 119 DCHxDPTR (Channel x Destination Pointer)............ 117 DCHxDSA (DMA Channel x Destination Start Address) ................................................... 115 DCHxDSIZ (DMA Channel x Destination Size)......... 116 DCHxECON (DMA Channel x Event Control)........... 112 DCHxINT (DMA Channel x Interrupt Control) ........... 113 DCHxSPTR (DMA Channel x Source Pointer).......... 117 DCHxSSA (DMA Channel x Source Start Address).. 115 DCHxSSIZ (DMA Channel x Source Size) ............... 116 DCRCCON (DMA CRC Control)............................... 108 DCRCDATA (DMA CRC Data) ................................. 110 DCRCXOR (DMA CRCXOR Enable)........................ 110 DEVCFG0 (Device Configuration Word 0................. 226 DEVCFG1 (Device Configuration Word 1................. 228 DEVCFG2 (Device Configuration Word 2................. 230 DEVCFG3 (Device Configuration Word 3................. 232 DEVID (Device and Revision ID).............................. 234 DMAADDR (DMA Address)...................................... 107 DMAADDR (DMR Address)...................................... 107 DMACON (DMA Controller Control) ......................... 106 DMASTAT (DMA Status).......................................... 107 I2CxCON (I2C Control)............................................. 175 I2CxSTAT (I2C Status)............................................. 177 ICxCON (Input Capture x Control)............................ 160 IFSx (Interrupt Flag Status) ........................................ 92 INTCON (Interrupt Control)......................................... 90 INTSTAT (Interrupt Status)......................................... 91 IPCx (Interrupt Priority Control) .................................. 93 NVMADDR (Flash Address) ....................................... 81 NVMCON (Programming Control) .............................. 80 NVMDATA (Flash Program Data)............................... 82 NVMKEY (Programming Unlock)................................ 81 NVMSRCADDR (Source Data Address) .................... 82 OCxCON (Output Compare x Control) ..................... 164 OSCCON (Oscillator Control)..................................... 97 PMADDR (Parallel Port Address)............................. 190 PMAEN (Parallel Port Pin Enable)............................ 191 PMCON (Parallel Port Control)................................. 186 PMMODE (Parallel Port Mode)................................. 188 PMSTAT (Parallel Port Status (Slave Modes Only).. 192 REFOCON (Reference Oscillator Control) ............... 101 REFOTRIM (Reference Oscillator Trim)................... 103 RPnR (Peripheral Pin Select Output) ....................... 149 RSWRST (Software Reset) ........................................ 85 RTCCON (RTC Control)........................................... 194 RTCDATE (RTC Date Value) ................................... 199 RTCTIME (RTC Time Value).................................... 198 SPIxCON (SPI Control) ............................................ 166 SPIxCON2 (SPI Control 2) ....................................... 169 SPIxSTAT (SPI Status)............................................. 170 T1CON (Type A Timer Control)................................ 152 TPTMR (Temporal Proximity Timer)........................... 91 TxCON (Type B Timer Control) ................................ 157 U1ADDR (USB Address).......................................... 137 U1BDTP1 (USB BDT Page 1) .................................. 139 U1BDTP2 (USB BDT Page 2) .................................. 140 U1BDTP3 (USB BDT Page 3) .................................. 140 U1CNFG1 (USB Configuration 1)............................. 141 U1CON (USB Control).............................................. 135 U1EIE (USB Error Interrupt Enable)......................... 133 U1EIR (USB Error Interrupt Status).......................... 131 U1EP0-U1EP15 (USB Endpoint Control) ................. 142 U1FRMH (USB Frame Number High) ...................... 138 U1FRML (USB Frame Number Low)........................ 137 U1IE (USB Interrupt Enable) .................................... 130 U1IR (USB Interrupt) ................................................ 128 U1OTGCON (USB OTG Control) ............................. 126 U1OTGIE (USB OTG Interrupt Enable).................... 124 U1OTGIR (USB OTG Interrupt Status)..................... 123 U1OTGSTAT (USB OTG Status) ............................. 125 U1PWRC (USB Power Control)................................ 127 U1SOF (USB SOF Threshold).................................. 139 U1STAT (USB Status).............................................. 134 U1TOK (USB Token)................................................ 138 WDTCON (Watchdog Timer Control) ....................... 236 Resets................................................................................. 83 Revision History................................................................ 307 DS61168C-page 312 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX RTCALRM (RTC ALARM Control).................................... 196 S Serial Peripheral Interface (SPI) ....................................... 165 Software Simulator (MPLAB SIM)..................................... 243 Special Features ............................................................... 225 T Timer1 Module .................................................................. 151 Timer2/3, Timer4/5 Modules ............................................. 155 Timing Diagrams 10-Bit Analog-to-Digital Conversion
(ASAM = 0, SSRC<2:0> = 000)........................ 278 10-Bit Analog-to-Digital Conversion (CHPS<1:0> = 01, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001)............................................................... 279 EJTAG ...................................................................... 284 External Clock........................................................... 254 I/O Characteristics .................................................... 257 I2Cx Bus Data (Master Mode) .................................. 268 I2Cx Bus Data (Slave Mode) .................................... 271 I2Cx Bus Start/Stop Bits (Master Mode) ................... 268 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 271 Input Capture (CAPx)................................................ 261 OCx/PWM ................................................................. 262 Output Compare (OCx)............................................. 262 Parallel Master Port Read......................................... 280 Parallel Master Port Write ......................................... 281 Parallel Slave Port .................................................... 279 SPIx Master Mode (CKE = 0) ................................... 263 SPIx Master Mode (CKE = 1) ................................... 264 SPIx Slave Mode (CKE = 0) ..................................... 265 SPIx Slave Mode (CKE = 1) ..................................... 266 Timer1, 2, 3, 4, 5 External Clock............................... 260 UART Reception ....................................................... 184 UART Transmission (8-bit or 9-bit Data)................... 184 Timing Requirements Timing Specifications CLKO and I/O ........................................................... 257 I2Cx Bus Data Requirements (Master Mode) ........... 269 I2Cx Bus Data Requirements (Slave Mode) ............. 272 Input Capture Requirements..................................... 261 Output Compare Requirements................................ 262 Simple OCx/PWM Mode Requirements.................... 262 SPIx Master Mode (CKE = 0) Requirements ............ 263 SPIx Master Mode (CKE = 1) Requirements ............ 264 SPIx Slave Mode (CKE = 1) Requirements .............. 266 SPIx Slave Mode Requirements (CKE = 0) .............. 265 U UART ................................................................................ 179 USB On-The-Go (OTG) .................................................... 121 V VCAP pin............................................................................ 237 Voltage Regulator (On-Chip) ............................................ 237 W Watchdog Timer (WDT) .................................................... 235 WWW Address.................................................................. 315 WWW, On-Line Support ..................................................... 16 2011 Microchip Technology Inc. Preliminary DS61168C-page 313 PIC32MX1XX/2XX NOTES:
DS61168C-page 314 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers distributor, their representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support contact should THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, following information:
Product Support Data sheets and errata, the web site contains the application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software General Technical Support Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchips customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. the Microchip web site at To register, access Support, click on www.microchip.com. Under Customer Change Notification and the registration instructions. follow 2011 Microchip Technology Inc. Preliminary DS61168C-page 315 PIC32MX1XX/2XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. Technical Publications Manager Reader Response TO:
RE:
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional):
Would you like a reply? Y N Device:
PIC32MX1XX/2XX Questions:
1. What are the best features of this document?
Total Pages Sent ________ FAX: (______) _________ - _________ Literature Number:
DS61168C 2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS61168C-page 316 Preliminary 2011 Microchip Technology Inc. PIC32MX1XX/2XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Example:
PIC32MX110F032DT-I/PT:
General purpose PIC32, 32-bit RISC MCU with M4K core, 32 KB program memory, 44-pin, Industrial temperature, TQFP package. PIC32 MX 1XX F 032 D T - I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture Flash Memory Family MX = M4K MCU core Product Groups 1XX = General purpose microcontroller family 2XX = General purpose microcontroller family Flash Memory Family F
= Flash program memory Program Memory Size 016 = 16K 032 = 32K Pin Count Temperature Range Package B C D I V
= 28-pin
= 36-pin
= 44-pin
= -40C to +85C (Industrial)
= -40C to +105C (V-temp) ML = 28-Lead (6x6 mm) QFN (Plastic Quad Flatpack) ML = 44-Lead (8x8 mm) QFN (Plastic Quad Flatpack) PT = 44-Lead (10x10x1 mm) TQFP (Plastic Thin Quad Flatpack) SO = 28-Lead (7.50 mm) SOIC (Plastic Small Outline) SP = 28-Lead (300 mil) SPDIP (Skinny Plastic Dual In-line) SS = 28-Lead (5.30 mm) SSOP (Plastic Shrink Small Outline) TL = 36-Lead (5x5 mm) VTLA (Very Thin Leadless Array) TL = 44-Lead (6x6 mm) VTLA (Very Thin Leadless Array) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample 2011 Microchip Technology Inc. Preliminary DS61168C-page 317 PIC32MX1XX/2XX NOTES:
DS61168C-page 318 Preliminary 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-750-8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011 Microchip Technology Inc. Preliminary DS61168C-page 319 Worldwide Sales and Service ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support:
http://www.microchip.com/
support Web Address:
www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 08/02/11 DS61168C-page 320 Preliminary 2011 Microchip Technology Inc.
1 | User Manual Module Installation | Users Manual | 230.48 KiB |
Digitizer Instruction 1. Put digitizer on the fixture of panel 2. Peel off the tapes of the bracket 3. Attach the bracket to digitizer 4. Press to make sure that both bracket and digitizer are attached well to the panel
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2018-04-23 | 250 ~ 290 | DXX - Part 15 Low Power Communication Device Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2018-04-23
|
||||
1 | Applicant's complete, legal business name |
Getac Technology Corporation
|
||||
1 | FCC Registration Number (FRN) |
0018268243
|
||||
1 | Physical Address |
5F.,Building A,No.209,Sec.1 Nangang.,Rd.
|
||||
1 |
Taipei City, N/A 11568
|
|||||
1 |
Taiwan
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
T******@TIMCOENGR.COM
|
||||
1 | TCB Scope |
A1: Low Power Transmitters below 1 GHz (except Spread Spectrum), Unintentional Radiators, EAS (Part 11) & Consumer ISM devices
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
QYL
|
||||
1 | Equipment Product Code |
V110GD
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
K****** C****
|
||||
1 | Telephone Number |
+886-******** Extension:
|
||||
1 | Fax Number |
+886-********
|
||||
1 |
k******@getac.com.tw
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | If so, specify the short-term confidentiality release date (MM/DD/YYYY format) | 10/20/2018 | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DXX - Part 15 Low Power Communication Device Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Digitizer module | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Limited Single Modular Approval | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Limited Modular Approval. This device is approved for use in the Getac Notebook Model V110. Approved for OEM integration only. The grantee must provide OEM integrators with installation and operating instructions for satisfying FCC requirements.This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device. | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
Bureau Veritas CPS (H.K.) Ltd., Taoyuan Branch
|
||||
1 | Name |
K**** L******
|
||||
1 | Telephone Number |
+886-******** Extension:
|
||||
1 | Fax Number |
+886-********
|
||||
1 |
k******@tw.bureauveritas.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 250.00000000 | 290.00000000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC