FCC ID: QYLV110N RFID and NFC Module

 

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Community Reference Design TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication

(NFC) Transceiver IC TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 1 Device Overview 1.1 1 Features Supports Near Field Communication (NFC) Standards NFCIP-1 (ISO/IEC 18092) and NFCIP2

(ISO/IEC 21481) Completely Integrated Protocol Handling for ISO15693, ISO18000-3, ISO14443A/B, and FeliCa Integrated Encoders, Decoders, and Data Framing for NFC Initiator, Active and Passive Target Operation for All Three Bit Rates (106 kbps, 212 kbps, 424 kbps) and Card Emulation RF Field Detector With Programmable Wake-Up Levels for NFC Passive Transponder Emulation Operation RF Field Detector for NFC Physical Collision Avoidance. Integrated State Machine for ISO14443A Anticollision (Broken Bytes) Operation

(Transponder Emulation or NFC Passive Target) Input Voltage Range: 2.7 VDC to 5.5 VDC 1.2 Applications Programmable Output Power: +20 dBm (100 mW),

+23 dBm (200 mW) Programmable I/O Voltage Levels From 1.8 VDC to 5.5 VDC Programmable System Clock Frequency Output

(RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz Crystal or Oscillator Integrated Voltage Regulator Output for Other System Components (MCU, Peripherals, Indicators), 20 mA (Max) Programmable Modulation Depth Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection Programmable Power Modes for Ultra Low-Power System Design (Power Down <1 A) Parallel or SPI Interface (With 127-Byte FIFO) Temperature Range: 40C to 110C 32-Pin QFN Package (5 mm x 5 mm) Mobile Devices (Tablets, Handsets) Secure Pairing ( Bluetooth, Wi-Fi, Other Paired Short-Range Wireless Communication Tasks

(Firmware Updates) Wireless Networks) Product Identification or Authentication Public Transport or Event Ticketing Medical Equipment or Consumables Passport or Payment (POS) Reader Systems Access Control, Digital Door Locks Sharing of Electronic Business Cards 1.3 Description The TRF7970A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID and Near Field Communication (NFC) system. Built-in programming options make the device suitable for a wide range of applications for proximity and vicinity identification systems. The device can perform in one of three modes: RFID and NFC reader, NFC peer, or in card emulation mode. Built-in user-configurable programming options make the device suitable for a wide range of applications. The TRF7970A device is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed. Documentation, reference designs, EVM, and source code TI MSP430 MCUs or ARM MCUs are available. PART NUMBER TRF7970ARHB Device Information PACKAGE VQFN (32) BODY SIZE 5 mm x 5 mm 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 1.4 Functional Block Diagram Figure 1-1 shows the block diagram. RX_IN1 MUX RX_IN2 VDD_PA GAIN RSSI

(AUX) PHASE &

AMPLITUDE DETECTOR RF LEVEL DETECTOR RSSI

(EXTERNAL) PHASE &

AMPLITUDE DETECTOR GAIN RSSI

(MAIN) FILTER

& AGC ISO PROTOCOL HANDLING DIGITIZER DECODER LOGIC STATE CONTROL LOGIC

[CONTROL REGISTERS &

COMMAND LOGIC]

MCU INTERFACE L E V E L S H F T E R I TX_OUT TRANSMITTER ANALOG FRONT END FRAMING BIT FRAMING 127-BYTE FIFO VSS_PA EN EN2 ASK/OOK MOD OSC_IN OSC_OUT DIGITAL CONTROL STATE MACHINE CRYSTAL OR OSCILLATOR TIMING SYSTEM SERIAL CONVERSION CRC & PARITY VOLTAGE SUPPLY REGULATOR SYSTEMS

(SUPPLY REGULATORS AND REFERENCE VOLTAGES) Figure 1-1. Block Diagram www.ti.com VDD_I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 IRQ SYS_CLK DATA _CLK VIN VDD_A BAND_GAP VSS_A VDD_RF VSS_RF VDD_X VSS VSS_D 2 Device Overview Copyright 20112014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A www.ti.com TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 Table of Contents 5 1.4 1.3 1.2 1.1 1 Device Overview ......................................... 1 Features .............................................. 1 Applications........................................... 1 Description............................................ 1 Functional Block Diagram ............................ 2 2 Revision History ......................................... 4 3 Device Characteristics.................................. 5 Terminal Configuration and Functions.............. 6 4 Pin Assignments...................................... 6 4.1 Terminal Functions ................................... 7 4.2 Specifications ............................................ 9 Absolute Maximum Ratings .......................... 9 5.1 Recommended Operating Conditions ................ 9 Electrical Characteristics ............................ 10 Handling Ratings .................................... 11 Thermal Characteristics............................. 11 Switching Characteristics ........................... 11 6 Detailed Description ................................... 12 Overview ............................................ 12 System Block Diagram.............................. 15 Power Supplies...................................... 15 Receiver Analog Section .......................... 21 Receiver Digital Section........................... 22 Oscillator Section ................................... 27 Transmitter Analog Section ....................... 28 5.6 5.2 5.3 5.4 5.5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.9 6.8 Transmitter Digital Section ........................ 28 Transmitter External Power Amplifier and Subcarrier Detector ................................. 29 6.10 TRF7970A IC Communication Interface ............ 30 6.11 Special Direct Mode for Improved MIFARE Compatibility......................................... 48 6.12 NFC Modes.......................................... 48 6.13 Direct Commands from MCU to Reader ............ 51 6.14 Register Description................................. 55 7 Application Schematic and Layout 7.4 7.3 7.2 Considerations.......................................... 75 7.1 TRF7970A Reader System Using Parallel Microcontroller Interface............................. 75 TRF7970A Reader System Using SPI With SS Mode ................................................ 76 Layout Considerations .............................. 77 Impedance Matching TX_Out (Pin 5) to 50 ...... 77 Reader Antenna Design Guidelines ................ 79 8 Device and Documentation Support ............... 80 Documentation Support ............................. 80 Community Resources .............................. 80 Trademarks.......................................... 80 Electrostatic Discharge Caution..................... 80 Glossary ............................................. 80 7.5 8.1 8.2 8.3 8.4 8.5 9 Mechanical Packaging and Orderable Information .............................................. 80 Packaging Information .............................. 80 9.1 Copyright 20112014, Texas Instruments Incorporated Table of Contents 3 Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 2 Revision History www.ti.com NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (February 2014) to Revision K Page Changed Figure 1-1 to show 127-byte FIFO...................................................................................... 2 Moved Section 3 ...................................................................................................................... 5 Changed title of Section 4 .......................................................................................................... 6 Changed title of Section 5 ........................................................................................................... 9 Added ASK/OOK and MOD to VIL and VIH ........................................................................................ 9 Moved Section 5.3 .................................................................................................................. 10 Changed VDD_A TYP value from 3.5 V to 3.4 V ................................................................................. 10 Moved Section 5.4 .................................................................................................................. 11 Added V(ESD) MIN values, test specifications, and notes....................................................................... 11 Changed title of Section 5.5 from Dissipation Ratings to Thermal Characteristics......................................... 11 Moved Section 5.6 .................................................................................................................. 11 Changed title of Section 6.......................................................................................................... 12 Moved previous Section 3, Device Overview, to Section 6.1.................................................................. 12 Changed from "By default, the AGC is frozen after..." to "By default, the AGC window comparator is set after..." ... 21 Changed from "TX Pulse Length Control register (0x05)" to "TX Pulse Length Control register (0x06)" ............... 28 Changed from "18.8 s" to "18.8 s" in the sentence that starts with "If the register contains all zeros..."............... 28 Changed Table 6-18 to match Table 6-43 ....................................................................................... 50 Changed command 0x18 to "Test internal RF" ................................................................................. 51 Changed command 0x19 to "Test external RF" ................................................................................ 51 Moved Section 6.14................................................................................................................. 55 Changed the sentence that starts "The AGC action is fast..." from "finishes after four subcarrier pulses" to

"finishes within eight subcarrier pulses" ......................................................................................... 64 Moved Section 7..................................................................................................................... 75 Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ............... 77 Removed references to figure numbers in Figure 7-3.......................................................................... 78 4 Revision History Copyright 20112014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A www.ti.com TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 3 Device Characteristics Table 3-1 shows the supported modes of operation for the TRF7970A device. Table 3-1. Supported Modes of Operation P2P Initiator or Reader/Writer Card Emulation P2P Target Technology NFC-A/B (ISO14443A/B) NFC-F (JIS: X6319-4) NFC-V (ISO15693) Bit rate

(kbps) 106, 212, 424, 848 (1) 212, 424 6.7, 26.7 Technology NFC-A/B N/A N/A Bit rate

(kbps) 106 N/A N/A Technology NFC-A NFC-F N/A Bit rate

(kbps) 106 212, 424 N/A

(1) 848 kbps only applies to reader/writer mode. Copyright 20112014, Texas Instruments Incorporated Device Characteristics 5 Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 4 Terminal Configuration and Functions 4.1 Pin Assignments Figure 4-1 shows the pin assignments for the 32-pin RHB package. www.ti.com V D D _ X O S C _ N I O S C _ O U T V S S _ D E N S Y S _ C L K D A T A _ C L K E N 2 32 31 30 29 28 27 26 25 Pad 24 23 22 I/0_7 I/0_6 I/0_5 21 I/0_4 20 19 18 17 I/0_3 I/0_2 I/0_1 I/0_0 VDD_A VIN VDD_RF VDD_PA TX_OUT VSS_PA VSS_RX RX_IN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 V S S B G R X _ N 2 I

/

A S K O O K I R Q M O D V S S _ A V D D _ I

/

O Figure 4-1. 32-Pin RHB Package (Top View) 6 Terminal Configuration and Functions Copyright 20112014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A www.ti.com 4.2 Terminal Functions Table 4-1 describes the signals. TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 TERMINAL NAME NO. TYPE (1) Table 4-1. Terminal Functions DESCRIPTION VDD_A VIN VDD_RF VDD_PA TX_OUT VSS_PA VSS_RX RX_IN1 RX_IN2 VSS BAND_GAP ASK/OOK IRQ MOD VSS_A VDD_I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 EN2 DATA_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 OUT SUP OUT INP OUT SUP SUP INP INP SUP OUT BID OUT INP OUT SUP INP BID BID BID BID BID BID Internal regulated supply (2.7 V to 3.4 V) for analog circuitry External supply input to chip (2.7 V to 5.5 V) Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4) Supply for PA; normally connected externally to VDD_RF (pin 3) RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V) Negative supply for PA; normally connected to circuit ground Negative supply for RX inputs; normally connected to circuit ground Main RX input Auxiliary RX input Chip substrate ground Bandgap voltage (VBG = 1.6 V); internal analog voltage reference Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1. Can be configured as an output to provide the received analog signal output. Interrupt request External data modulation input for Direct Mode 0 or 1 Subcarrier digital data output (see registers 0x1A and 0x1B) Negative supply for internal analog circuits; connected to GND Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded. I/O pin for parallel communication I/O pin for parallel communication I/O pin for parallel communication TX Enable (in Special Direct Mode) I/O pin for parallel communication TX Data (in Special Direct Mode) I/O pin for parallel communication Slave Select signal in SPI mode I/O pin for parallel communication Data clock output in Direct Mode 1 and Special Direct Mode I/O pin for parallel communication 23 BID MISO for serial communication (SPI) 24 25 26 BID INP INP Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU). Data Clock input for MCU communication (parallel and serial) If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09):

SYS_CLK 27 OUT 13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz EN VSS_D 28 29 INP SUP 27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz If EN = 0 and EN2 = 1, then system clock is set to 60 kHz Chip enable input (If EN = 0, then chip is in sleep or power-down mode). Negative supply for internal digital circuits

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output Copyright 20112014, Texas Instruments Incorporated Terminal Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 www.ti.com TERMINAL NAME NO. TYPE (1) OSC_OUT OSC_IN VDD_X 30 31 32 OUT INP OUT OUT Table 4-1. Terminal Functions (continued) DESCRIPTION Crystal or oscillator output Crystal or oscillator input Crystal oscillator output Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, MCU) Thermal Pad PAD SUP Chip substrate ground 8 Terminal Configuration and Functions Copyright 20112014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A www.ti.com 5 Specifications TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 5.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) VIN IIN TJ Input voltage range Maximum current VIN Maximum operating virtual junction temperature Any condition Continuous operation, long-term reliability (3)

-0.3 V to 6 V 150 mA 140C 125C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to substrate ground terminal VSS.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device. 5.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN TA TJ VIL VIH Operating input voltage Operating ambient temperature Operating virtual junction temperature MIN 2.7

-40

-40 Input voltage - logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.8 x VDD_I/O TYP MAX UNIT 5 25 25 5.5 110 125 0.2 x VDD_I/O V C C V V Copyright 20112014, Texas Instruments Incorporated Specifications 9 Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 5.3 Electrical Characteristics www.ti.com TYP operating conditions are TA = 25C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPD1 IPD2 Supply current in Power Down Mode 1 Supply current in Power Down Mode 2

(Sleep Mode) ISTBY Supply current in stand-by mode All building blocks disabled, including supply-

voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0) The SYS_CLK generator and VDD_X remain active to support external circuitry; measured after 100-ms settling time (EN = 0, EN2 = 1) Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x) ION1 ION2 ION3 VPOR VBG VDD_A VDD_X Supply current without antenna driver current Oscillator, regulators, RX and AGC active, TX is off Supply current TX (half power) Supply current TX (full power) Oscillator, regulators, RX and AGC and TX active, POUT = 100 mW Oscillator, regulators, RX and AGC and TX active, POUT = 200 mW Power-on reset voltage Input voltage at VIN Bandgap voltage (pin 11) Internal analog reference voltage Regulated output voltage for analog circuitry (pin 1) VIN = 5 V Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V RRFOUT RRFIN Antenna driver output resistance (1) RX_IN1 and RX_IN2 input resistance Half-power mode, VIN = 2.7 V to 5.5 V Full-power mode, VIN = 2.7 V to 5.5 V VRF_INmax Maximum RF input voltage at RX_IN1 and RX_IN2 VRF_INmax should not exceed VIN VRF_INmin Minimum RF input voltage at RX_IN1 and RX_IN2 (input sensitivity) (2) fSUBCARRIER= 424 kHz fSUBCARRIER = 848 kHz fSYS_CLK SYS_CLK frequency fC Carrier frequency tCRYSTAL Crystal run-in time fD_CLKmax Maximum DATA_CLK frequency (4) ROUT Output resistance I/O_0 to I/O_7 RSYS_CLK Output resistance RSYS_CLK In power mode 2, EN = 0, EN2 = 1 Defined by external crystal Time until oscillator stable bit is set (register 0x0F) (3) Depends on capacitive load on the I/O lines, recommendation is 2 MHz (4) 0.5 5 A 120 200 A 1.9 3.5 mA 10.5 14 mA 70 78 mA 130 150 mA 1.4 1.5 3.1 3.1 4 25 2 2 1.6 3.4 3.4 8 4 10 3.5 1.4 2.1 60 13.56 3 8 2.6 1.7 3.8 3.8 V V V V 20 mA 12 6 20 2.5 3

k Vpp mVpp 120 kHz MHz ms 10 MHz 500 200 800 400

(1) Antenna driver output resistance

(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.

(3) Depends on the crystal parameters and components

(4) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 (12-ns time constant when 30-pF load used). 10 Specifications Copyright 20112014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A www.ti.com 5.4 Handling Ratings TRF7970A SLOS743K AUGUST 2011 REVISED APRIL 2014 TSTG V(ESD) Storage temperature range Electrostatic discharge Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all pins (2) Machine Model (MM) MIN MAX UNIT

-55

-2

-500 150 2 500

-200 200 C kV V V

(1)

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance. 5.5 Thermal Characteristics PACKAGE RHB (32 pin)

JC 31C/W

(1)

JA 36.4C/W POWER RATING (2) TA 25C 2.7 W TA 85C 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long-

term reliability. 5.6 Switching Characteristics TYP operating conditions are TA = 25C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Depends on capacitive load on the I/O lines (1) 250 62.5 50 ns tLO/HI tSTE,LEAD tSTE,LAG tSTE,DIS tSU,SI tHD,SI tSU,SO tHD,SO DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle Slave select lead time, slave select low to clock Slave select lag time, last clock to slave select high Slave select disable time, slave select rising edge to next slave select falling edge MOSI input data setup time MOSI input data hold time MISO input data setup time MISO input data hold time 200 200 300 15 15 15 15 30 50 75 ns ns ns ns ns ns ns ns tVALID,SO MISO output data valid time DATA_CLK edge to MISO valid, CL 30 pF

(1) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 (12-ns time constant when 30-pF load used). Copyright 20112014, Texas Instruments Incorporated Specifications 11 Submit Documentation Feedback Product Folder Links: TRF7970A Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

Reorient or relocate the receiving antenna.

Connect the equipment into an outlet on a circuit different from that Increase the separation between the equipment and receiver. to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help. FCC Caution:

Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment.

This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Radiation Exposure Statement:

The product is a low power device and its output power is lower than FCC SAR exemption level. This module can be used with Product name: V110. This device is intended only for OEM integrators under the following conditions:

1) The transmitter module may not be co-located with any other transmitter or antenna. The co-transmitting with other radio will need a separate evaluation. 2) Module approval valid only when this module is installed in the tested host Product name: V110. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed IMPORTANT NOTE: In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. End Product Labeling The final end product must be labeled in a visible area with the following: Contains FCC ID: QYLV110N. The grantee's FCC ID can be used only when all FCC compliance requirements are met. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.

 

 

























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z We shall not be liable for any loss or damage whatsoever resulting from your use of the fingerprint scanner or neglect of fingerprint scanner use, or any data loss resulting from such developments as fingerprint authentication malfunctioning. z It is not recommended that you use the fingerprint scanner in a below-

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40 z As you can use the computer in different orientations, be sure to swipe your finger in the correct direction. The fingerprint scanner has a small triangle icon to remind you of the direction.





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z The AC adapter is designed for use with your Computer only. Connecting the AC adapter to another device can damage the adapter. z The AC power cord supplied with your Computer is for use in the country where you purchased your Computer. If you plan to go overseas with the Computer, consult your dealer for the appropriate power cord. z When you disconnect the AC adapter, disconnect from the electrical outlet first and then from the Computer. A reverse procedure may damage the AC adapter or Computer. z When unplugging the connector, always hold the plug head. Never pull on the cord.



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44 CAUTION: After the computer has been fully recharged, do not immediately disconnect and reconnect the AC adapter to charge it again. Doing so may damage the battery.



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NOTE: You can hot swap one battery pack while the other one is supplying the power.



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