FCC ID: QYLPS336R RFID Module

www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEM Check for Samples: TRF7960, TRF7961 TRF7960 TRF7961 Parallel 8-Bit or Serial 4-Pin SPI Interface With MCU Using 12-Byte FIFO Ultra-Small 32-Pin QFN Package

(5 mm 5 mm) Available Tools Software Reference Design/EVM With Development Source Code Available for MSP430 1.2 APPLICATIONS Secure Access Control Product Authentication Printer Ink Cartridges Blood Glucose Monitors Contactless Payment Systems Medical Systems 12 Features 1 Introduction 1.1 Completely Integrated Protocol Handling Separate Internal High-PSRR Power Supplies for Analog, Digital, and PA Sections Provide Noise Isolation for Superior Read Range and Reliability Dual Receiver Inputs With AM and PM Demodulation to Minimize Communication Holes Receiver AM and PM RSSI Reader-to-Reader Anti-Collision High Integration Reduces Total BOM and Board Area Single External 13.56-MHz Crystal Oscillator MCU-Selectable Clock-Frequency Output of RF, RF/2, or RF/4 Adjustable 20-mA, High-PSRR LDO for Powering External MCU Easy to Use With High Flexibility Auto-Configured Default Modes for Each Supported ISO Protocol 12 User-Programmable Registers Selectable Receiver Gain and AGC Programmable Output Power

(100 mW or 200 mW) Adjustable ASK Modulation Range

(8% to 30%) Built-In Receiver Band-Pass Filter With User-Selectable Corner Frequencies Wide Operating Voltage Range of 2.7 V to 5.5 V Ultra-Low-Power Modes Power Down < 1 A Standby 120 A Active (Rx only) 10 mA 1.3 Description The TRF7960/61 is an integrated analog front end and data-framing system for a 13.56-MHz RFID reader system. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity RFID systems. The reader is configured by selecting the desired protocol control registers allows fine tuning of various reader parameters as needed. in the control registers. Direct access to all 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2Tag-it is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. the terms of Copyright 20062010, Texas Instruments Incorporated TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Table 1-1. PRODUCT SELECTION TABLE PROTOCOLS ISO14443A/B 106 kbps 212 kbps 424 kbps 848 kbps DEVICE TRF7960 TRF7961 ISO15693 ISO18000-3 Tag-it 2 Introduction Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 TRF7960 TRF7961 1 1.3 1.2 Introduction .............................................. 1 Features .............................................. 1 1.1 APPLICATIONS ...................................... 1 Description ........................................... 1 2 Description (continued) ................................ 4 Physical Characteristics ............................... 5 3 Terminal Functions ................................... 5 3.1 PACKAGING/ORDERING INFORMATION .......... 6 3.2 ELECTRICAL SPECIFICATIONS ..................... 7 ABSOLUTE MAXIMUM RATINGS .................. 7 4.1 DISSIPATION RATINGS TABLE .................... 7 RECOMMENDED OPERATING CONDITIONS ..... 7 4.2 4.3 4 5 4.6 4.4 4.5 ELECTRICAL CHARACTERISTICS ................. 8 Application Schematic for the TRF796x EVM

(Parallel Mode) ....................................... 9 Application Schematic for the TRF796x EVM (SPI Mode) ............................................... 10 System Description ................................... 11 Power Supplies ..................................... 11 5.1 Receiver Analog Section ......................... 17 5.2 Register Descriptions ............................... 24 5.3 Direct Commands From MCU to Reader ........... 34 5.4 Reader Communication Interface .................. 36 5.5 Parallel Interface Communication .................. 38 5.6 Serial Interface Communication .................... 40 5.7 External Power Amplifier Application ............... 44 5.8 Copyright 20062010, Texas Instruments Incorporated Contents 3 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 2 Description (continued) www.ti.com Figure 2-1. Typical Application A parallel or serial interface can be implemented for communication between the MCU and reader. Transmit and receive functions use internal encoders and decoders with a 12-byte FIFO register. For direct transmit or receive functions, the encoders / decoders can be bypassed so the MCU can process the data in real time. The transmitter has selectable output power levels of 100 mW (20 dBm) or 200 mW

(23 dBm) into a 50- load (5 -V supply) and is capable of ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise rejection for the complete reader system. Data transmission comprises low-level encoding for high-bit-rate systems for ISO14443 and Tag-it coding systems. automatic generation of SOF, EOF, CRC, and / or parity bits. ISO15693, modified Miller ISO14443-A, Included with the data encoding is for The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to cover a broad range of input sub-carrier signal options. The received signal strength for AM and PM modulation is accessible via the RSSI register. The receiver output is a digitized sub-carrier signal among a selectable protocol and bit rate as outlined in Table 5-11. A selected decoder delivers bit stream and a data clock as outputs. The receiver system also includes a framing system. This system performs CRC and / or parity check, removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to the MCU via a 12-byte FIFO register and MCU interface. The framing supports ISO14443 and ISO15693 protocols. The TRF7960/61 supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for additional system circuits. 4 Description (continued) Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 8 (Parallel)3 (SPI)ZMatchingCircuitTx_OutRx_IN1Rx_IN2VDD_XVDD_I/OSYS_CLKDATA_CLKVDDTRF796xMSP430Xtal13.56 MHzIRQXtal InXtal Out www.ti.com 3 Physical Characteristics 3.1 Terminal Functions TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 Figure 3-1. TRF796x Pin Assignments (Top View) TERMINAL NAME NO. TYPE(1) Table 3-1. Terminal Functions DESCRIPTION VDD_A VIN VDD_RF VDD_PA TX_OUT VSS_RF VSS_RX RX_IN1 RX_IN2 VSS BAND_GAP ASK/OOK IRQ MOD VSS_A VDD_I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 OUT SUP OUT INP OUT SUP SUP INP INP SUP OUT BID OUT INP SUP SUP BID BID BID BID BID Internal regulated supply (2.7 V 3.4 V) for analog circuitry External supply input to chip (2.7 V 5.5 V) Internal regulated supply (2.7 V 5 V), normally connected to VDD_PA (pin 4) Supply for PA; normally connected externally to VDD_RF (pin 3) RF output (selectable output power, 100 mW at 8 or 200 mW at 4 , with VDD = 5 V) Negative supply for PA; normally connected to circuit ground Negative supply for RX inputs; normally connected to circuit ground RX input, used for AM reception RX input, used for PM reception Chip substrate ground Band-gap voltage (1.6 V); internal analog voltage reference; must be ac-bypassed to ground. Also can be configured to provide the received analog signal output (ANA_OUT) Direct mode, selection between ASK and OOK modulation (0 = ASK, 1 = OOK) Interrupt request Direct mode, external modulation input Negative supply for internal analog circuits; normally connected to circuit ground Supply for I/O communications (1.8 V 5.5 V). Should be connected to VIN for 5-V communication, VDD_X for 3.3-V communication, or any other voltage from 1.8 V to 5.5 V. I/O pin for parallel communication I/O pin for parallel communication I/O pin for parallel communication I/O pin for parallel communication I/O pin for parallel communication

(1) SUP = Supply, INP = Input, BID = Bi-directional, OUT = Output Copyright 20062010, Texas Instruments Incorporated Physical Characteristics 5 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com TERMINAL NAME NO. TYPE(1) Table 3-1. Terminal Functions (continued) DESCRIPTION I/O_5 I/O_6 I/O_7 EN2 DATA_CLK SYS_CLK EN VSS_D OSC_OUT OSC_IN VDD_X Thermal Pad 22 23 24 25 26 27 28 29 30 31 32 BID BID BID INP INP OUT INP SUP OUT INP OUT I/O pin for parallel communication Strobe out clock for serial communication Data clock output in direct mode I/O pin for parallel communication MISO for serial communication (SPI) Serial bit data output in direct mode 1 or sub-carrier signal in direct mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Pulse enable and selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down to support the MCU. Pin can also be used for pulse wake-up from power-down mode. Clock input for MCU communication (parallel and serial) Clock for MCU (3.39 / 6.78 / 13.56 MHz) at EN = 1 and EN2 = don't care If EN = 0 and EN2 = 1, then system clock is set to 60 kHz Chip enable input (If EN = 0, then chip is in power-down mode). Negative supply for internal digital circuits; normally connected to circuit ground Crystal oscillator output Crystal oscillator input Internally regulated supply (2.7 V 3.4 V) for external circuitry (MCU) Connected to circuit ground 3.2 PACKAGING/ORDERING INFORMATION(1) PACKAGED DEVICES PACKAGE TYPE (2) TRANSPORT MEDIA QUANTITY TRF7960RHBT TRF7960RHBR TRF7961RHBT TRF7961RHBR RHB-32 RHB-32 Tape and reel Tape and reel Tape and reel Tape and reel 250 3000 250 3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Web site at www.ti.com. www.ti.com/sc/package . 6 Physical Characteristics Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 TRF7960 TRF7961 4 ELECTRICAL SPECIFICATIONS 4.1 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VIN IO TJ Tstg Supply voltage Output current Continuous power dissipation Maximum junction temperature, any condition (2) Maximum junction temperature, continuous operation, long-term reliability(2) Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ESDS rating HBM (human body model) CDM (charged device model) MM (machine model) VALUE UNIT 6 150 V mA See Dissipation Ratings Table C C C C kV 55 to 150 140 125 V 300 2 500 200

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified are not implied.

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. 4.2 DISSIPATION RATINGS TABLE PACKAGE RHB (32) JC

(C/W) 31

(1) JA

(C/W) 36.4 POWER RATING(2) TA 25C 2.7 W TA = 85C 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB.

(2) Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long-term reliability. 4.3 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VIN TJ TA Supply voltage Operating virtual junction temperature range Operating ambient temperature range MIN 2.7 40 40 TYP 5 25 MAX 5.5 125 110 UNIT V C C Copyright 20062010, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 7 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com 4.4 ELECTRICAL CHARACTERISTICS over temperature range VS = 5 V (unless otherwise noted) PARAMETER CONDITIONS Supply current in power-down mode All systems disabled, including supply-voltage regulators Supply current in power-down mode 2 The reference voltage generator and the VDD_X remain active to support external circuitry. Supply current in standby mode Oscillator running, supply-voltage regulators in low-consumption mode Supply current without antenna driver Oscillator, regulators, Rx and AGC, are all active. Tx is current off. Supply current with antenna driver current Oscillator, regulators, Rx, AGC, and Tx are all active. Pout = 100 mW. Supply current with antenna driver current Oscillator, regulators, Rx, AGC, and Tx are all active. Pout = 200 mW. Band Gap voltage Internal analog reference voltage Power on reset voltage (POR) Regulated supply for analog circuitry Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV difference. Regulated supply for external circuitry Rejection of external supply noise on the supply VDD_RF regulator The difference between the external supply and the regulated voltage is higher than 250 mV. Measured at 212 kHz. IPD IPD2 ISTBY ION1 ION2 ION3 BG VPOR VDD_A VDD_RF VDD_X PPSRR RRFOUT PA driver output resistance Half-power mode Full- power mode RRFIN VRFIN VSENS tSET_PD tSET_STBY tREC fSYS_CLK CLKMAX VIL VIH ROUT RSYS_CLK RX_IN1 and RX_IN2 input resistance Maximum input voltage Input sensitivity Set up time after power down Set up time after standby mode Recovery time after modulation

(ISO14443) At RX_IN1 and RX_IN2 inputs fSUB-CARRIER = 424 kHz fSUB-CARRIER = 848 kHz Modulation signal: sine, 424-kHz, 10-mVpp SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 Maximum CLK frequency Input logic low Input logic high Output resistance I/O_0 to I/O_7 Output resistance SYS_CLK low_io = H for VDD_I/O < 2.7 V low_io = H for VDD_I/O < 2.7 V TYP 25C 1 120 1.5 10 70 120 1.6 2 3.5 4.6 3.4 26 8 4 10 3.5 1.2 1.2 10 30 60 2 0.2 400 200 40C TO 110C 10 300 4 16 1.4 1.7 1.4 2.5 3.1 3.8 4 5.2 3.1 3.8 20 12 6 5 20 2.5 3 20 100 60 30 120 0.2 0.8 800 400 UNIT A A mA mA mA mA V V V V V dB k VPP mVPP mVPP ms s s kHz MHz VDD_I/O VDD_I/O MIN/

MAX MAX MAX MAX MAX MAX MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MAX MIN MAX MAX MAX MAX MAX MAX MAX MIN MAX TYP MAX MIN MAX MAX 8 ELECTRICAL SPECIFICATIONS Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 4.5 Application Schematic for the TRF796x EVM (Parallel Mode) TRF7960 TRF7961 Copyright 20062010, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 9 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TestPortorExtAnt Port1TRF796xRHB - 3223456789101112131415163231302928272625171819202122232433Thermal PadVDD_XOSC_INOSC_OUTVSS_DENSYS_CLKDATA_CLKEN2VDD_I/ OVSS_AMODIRQASK / OOKBAND GAPVSSRX2_PMRX1_AMVDD_AVSS_RXVSS_RFTX_OUTVDD_PAVDD_RFVINI / O_0I / O_1I / O_2I / O_3I / O_4I / O_5I / O_6I / O_71000 pF1000 pF1500 pF1500 pF680 pF680 pF220 pFVSWRAdjPhaseAdj330 nH150 nHFreqAdj100 pF27 pF2.2 uF10 nF10 nF10 nF10 nF2.2 uF2.2 uF2.2 uF0 Ohms0 Ohms27 pF27 pF13.56 MHzVSWRAdjDVccD/AVssXIN1 K1 KReader Pwr Enable (GPIO)Interrupt Capable GPIOMSP430(Family)4.7 uF10V0.1 uF1 KCLK (GPIO)PX.7PX.6PX.5PX.4PX.3PX.2PX.1PX.0Vcc1000.1 uF2.2 uF10 nF10K10 pFHarmonicSuppressionC1C2XtalCLCSC1 + C2=+AntennaCircuitAntQAdjRcalopen / short / load TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com 4.6 Application Schematic for the TRF796x EVM (SPI Mode) 10 ELECTRICAL SPECIFICATIONS Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 Test PortorExtAnt Port1TRF796xRHB - 3223456789101112131415163231302928272625171819202122232433Thermal PadVDD_XOSC_INOSC_OUTVSS_DENSYS_CLDATA_CLKEN2VDD_I/ OVSS_AMODIRQASK /BAND GAPVSSRX2_PMRX1_AMVDD_AVSS_RXVSS_RFTX_OUTVDD_PAVDD_RFVINI / O_0I / O_1I / O_2I / O_3I / O_4I / O_5I / O_6I / O_71000 pF1000 pF1500 pF1500 pF680 pF680 pF220 pFVSWRAdjPhaseAdj330 nH150 nHFreqAdj100 pF27 pF2.2F10 nF10 nF10 nF10 nF2.2F2.2F2.2F0 Ohms0 Ohms27 pF27 pF13.56 MHzVSWRAdjVccDVccD/AVssMISOMOSIXIN10 K10 K1 K1 KCLK (GPIO)Slave Select (GPIO)Reader Pwr Enable (GPIO)Interrupt Capable GPIOMSP430 (Family)4.7F10V0.1F1 K1000.1F2.2F10 nF10 pFHarmonicSuppression10 KC1C2XtalCLCSC1 + C2=+AntennaCircuitAntQAdjRcalopen / short / load www.ti.com 5 System Description 5.1 Power Supplies TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 The positive supply pin, VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. The positive supply input sources three internal regulators with output voltages VDD_RF, VDD_A and VDD_X that use external bypass capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader system. independent and have common control bits for output voltage setting. The The regulators are not regulators can be configured to operate in either automatic or manual mode. The automatic regulator mode setting ensures an optimal compromise between regulator PSRR and highest possible supply voltage for RF output power. Whereas, the manual mode allows the user to manually configure the regulator settings. VDD_RF VDD_A VDD_X VDD_PA The regulator VDD_RF (pin 3) is used to source the RF output stage. The voltage regulator can be set for either 5-V or 3-V operation. When configured for the 5-V operation, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing capability for 5-V operation is 150 mA maximum over the adjusted output voltage range. When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V, also in 100-mV steps. The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted output voltage range. Regulator VDD_A (pin 1) supplies voltage to analog circuits within the reader chip. The voltage setting is divided in two ranges. When configured for 5-V operation, the output voltage is fixed at 3.5 V. When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V in 100-mV steps. Note that when configured, both VDD_A and VDD_X regulators are configured together

(their settings are not independent). Regulator VDD_X (pin 32) can be used to source the digital I/O of the reader chip together with other external system components. When configured for 5-V operation, the output voltage is fixed at 3.4 V. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. The total current sourcing capability of the VDD_X regulator is 20 mA maximum over the adjusted output range. Note that when configured, both VDD_A and VDD_X regulators are configured together (their settings are not independent). The VDD_PA pin (pin 4) is the positive supply pin for the RF output stage and is externally connected to the regulator output VDD_RF (pin 3). 5.1.1 Negative Supply Connections The negative supply connections are all externally connected together (to GND). The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_TX (pin 6), and the negative supply for the RF receiver input is VSS_RX (pin 7). 5.1.2 Digital I/O Interface To allow compatible I/O signal levels, the TRF7960/61 has a separate supply input VDD_I/O (pin 16), with an input voltage range of 1.8 V to 5.5 V. This pin is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is connected directly to VDD_X to ensure that the I/O signal logic levels of the reader. levels of the MCU are the same as the internal Copyright 20062010, Texas Instruments Incorporated System Description 11 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.1.3 Supply Regulator Configuration www.ti.com The supply regulators can be automatically or manually configured by the control bits. The available options are shown in Table 5-1 through Table 5-4. Table 5-1 shows a 5-V system and the manual-mode regulator settings. Table 5-2 shows manual mode for selection of a 3-V system. Table 5-3 and Table 5-4 show the automatic-mode gain settings for 5-V and 3-V systems. The automatic mode is the default configuration. In automatic mode, the regulators are automatically set every time the system is activated by asserting the EN input HIGH. The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set HIGH (on the rising edge). The user can re-run the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the VIN level, but not higher than 5 V for VDD_RF, 3.5 V for VDD_A, and 3.4 V for VDD_X. This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio). As an example, the user can improve the PSRR if there is a noisy supply voltage from VDD_X by increasing the target voltage difference across the VDD_X regulator as shown for automatic regulator settings in Table 5-3 and Table 5-4. Table 5-1. Supply-Regulator Setting Manual 5-V System Byte Address B7 B6 00 0B 0B 0B 0B 0B 0B 0B 0B 0B 0 0 0 0 0 0 0 0 0 Byte Address B7 B6 00 0B 0B 0B 0B 0B 0B 0B 0B 0B 0 0 0 0 0 0 0 0 0 Option Bits Setting in Control Register B1 B5 B4 B3 B2 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Action 5-V system Manual regulator setting VDD_RF = 5 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.9 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.8 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.7 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.6 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.5 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.4 V, VDD_A = 3.5 V, and VDD_X = 3.4 V VDD_RF = 4.3 V, VDD_A = 3.5 V, and VDD_X = 3.4 V B0 1 1 0 1 0 1 0 1 0 Table 5-2. Supply-Regulator Setting Manual 3-V System Option Bits Setting in Control Register B1 B5 B4 B3 B2 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Action 3V system Manual regulator setting VDD_RF = 3.4 V, VDD_A, and VDD_X = 3.4 V VDD_RF = 3.3 V, VDD_A, and VDD_X = 3.3 V VDD_RF = 3.2 V, VDD_A, and VDD_X = 3.2 V VDD_RF = 3.1 V, VDD_A, and VDD_X = 3.1 V VDD_RF = 3.0 V, VDD_A, and VDD_X = 3.0 V VDD_RF = 2.9 V, VDD_A, and VDD_X = 2.9 V VDD_RF = 2.8 V, VDD_A, and VDD_X = 2.8 V VDD_RF = 2.7 V, VDD_A, and VDD_X = 2.7 V B0 0 1 0 1 0 1 0 1 0 12 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 Table 5-3. Supply-Regulator Setting Automatic 5-V System TRF7960 TRF7961 Byte Address B7 B6 00 0B 0B 0B 1 1 1

(1) X are don't cares Byte Address B7 B6 00 0B 0B 0B 1 1 1 Option Bits Setting in Control Register B1 B2(1) B5 B4 B3 x x x 1 1 0 Action B0 1 1 0 0 5-V system Automatic regulator setting 250-mV difference Automatic regulator setting 350-mV difference Automatic regulator setting 400-mV difference Table 5-4. Supply-Regulator Setting Automatic 3-V System Option Bits Setting in Control Register B1 B2(1) B5 B4 B3 x x x 1 1 0 Action B0 0 1 0 0 3-V system Automatic regulator setting 250-mV difference Automatic regulator setting 350-mV difference Automatic regulator setting 400-mV difference

(1) X are don't cares 5.1.4 Power Modes The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in the chip status control register (00h). The main reader enable input is EN (which has a threshold level of 1 V minimum). Any input signal level from 1.8 V to VIN can be used. When EN is set high, all of the reader regulators are enabled, together with the 13.56-MHz oscillator, while the SYS_CLK (output clock for external micro controller) is made available. The auxiliary-enable input EN2 has two functions. A direct connection from EN2 to VIN ensures availability of the regulated supply (VDD_X) and an auxiliary clock signal (60 kHz) on the SYS_CLK output (same for the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and clock to be available during power-down. A second function of the EN2 input is to enable start-up of the reader system from complete power down

(EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU or other system device that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader stays active. If the EN input is not set high within 100 s after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete power-down mode. This option can be used to wake the reader system from complete power down by using a push-button switch or by sending a single pulse. Copyright 20062010, Texas Instruments Incorporated System Description 13 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com After the reader EN line is high, the other power modes are selected by control bits. The power mode options and functions are listed in Table 5-5. Byte Address Option Bits Setting in Chip Status Control Register EN EN2 Functionality B7 STBY B6 B5 RFON B4 B3 RF PWR B2 B1 REC ON B0 Table 5-5. Power Modes 00 00 00 00 00 00 00 1 0 0 0 0 x 0 0 1 1 x x x 1 0 x 0 1 x x 0 0 1 1 1 1 1 0 1 x x x x x Complete power down VDD_X available SYS_CLK auxiliary frequency 60 kHz is ON All supply regulators active and in low power mode 13.56-MHz oscillator ON SYS_CLK clock available All supply regulators active 13.56-MHz oscillator ON SYS_CLK clock available All supply regulators active 13.56-MHz oscillator ON SYS_CLK clock available Receiver active All supply regulators active 13.56-MHz oscillator ON SYS_CLK clock available Receiver active Transmitter active half-power mode All supply regulators active 13.56-MHz oscillator running SYS_CLK clock available Receiver active Transmitter active full-power mode Current

<1 A 120 A 1.5 mA 3.5 mA 10 mA 70 mA

(at 5 V) 120 mA

(at 5 V) During reader inactivity, the TRF7960/61 can be placed in power down-mode (EN = 0). The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) where the regulated supply (VDD_X) and auxiliary clock 60 kHz (SYS_CLK) are available to the MCU or other system device. When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, is switched from the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform the required tasks. The control system (MCU) can then write appropriate bits to the chip status control register (address 00) and select the operation mode. the SYS_CLK output The STANDBY mode (bit 7 = 1 of register 00) is the active mode with the lowest current consumption. The reader is capable of recovering from this mode to full operation in 100 s. The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 of register 00) is the next active mode with low power consumption. The reader is capable of recovering from this mode to full operation in 25 s. The active mode with only the RF receiver section active (bit 1 = 1 of register 00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented. The active mode with the entire RF section active (bit 5 = 1 of register 00) is the normal mode used for transmit and receive operations. 14 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com 5.1.5 Timing Diagrams CHIP POWER UP TO CLOCK START TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 Figure 5-1. Power Up [VIN (Blue) to Crystal Start (Red)]

CHIP ENABLE TO CLOCK START Figure 5-2. EN2 Low and EN High (Blue) to Start of System Clock (Red) Copyright 20062010, Texas Instruments Incorporated System Description 15 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 C001C002 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com CHIP ENABLE TO CLOCK START Figure 5-3. EN2 High and EN Low (Blue) to Start of System Clock (Red) 16 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 C003 www.ti.com 5.2 Receiver Analog Section TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 The TRF7960/61 has two receiver inputs, RX_IN1 (pin 8) and RX_IN2 (pin 9). The two inputs are connected to an external filter to ensure that AM modulation from the tag is available on at least one of the two inputs. The external filter provides a 45 phase shift for the RX_IN2 input to allow further processing of a received PM-modulated signal (if it appears) from the tag. This architecture eliminates any possible communication holes that may occur from the tag to the reader. The two RX inputs are multiplexed to two receiver channels: the main receiver and the auxiliary receiver. Receiver input multiplexing is controlled by control bit B3 (pm-on) in the chip status control register

(address 00). The main receiver is composed of an RF-detection stage, gain, filtering with AGC, and a digitizing stage whose output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal. The primary function of the auxiliary receiver is to measure the RSSI of the modulation signal. It also has similar RF-detection, gain, filtering with AGC, and RSSI blocks. The default setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver (bit pm_on = 0). When a response from the tag is detected by the RSSI, values on both inputs are measured and stored in the RSSI level register (address 0F). The control system reads the RSSI values and switches to the stronger receiver input (RX_IN1 or RX_IN2 by setting pm_on = 1). The receiver input stage is an RF level detector. The RF amplitude level on RX_IN1 and RX_IN2 inputs should be approximately 3 VPP for a VIN supply level greater than 3.3 V. If the VIN level is lower, the RF input peak-to-peak voltage level should not exceed the VIN level. Note: VIN is the main supply voltage to the device at pin 2. The first gain and filtering stage following the RF-envelope detector has a nominal gain of 15 dB with an adjustable bandpass filter. The bandpass filter has adjustable 3-dB frequency steps (100 kHz to 400 kHz for high pass and 600 kHz to 1500 kHz for low pass). Following the bandpass filter is another gain-and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first stage. The internal filters are configured automatically, with internal presets for each new selection of a communication standard in the ISO control register (address 01). If required, additional fine tuning can be accomplished by writing directly to the RX special setting registers (address 0A). The second receiver gain stage and digitizer stage are included in the AGC loop. The AGC loop is activated by setting the bit B2 = 1 (agc-on) in the chip status control register (address 00). When activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher than an internal threshold level, gain reduction is activated. AGC activation is by default five times the internal threshold level. It can be reduced to three times the internal level by setting bit B1 = 1 (agcr) in the RX special setting register (address 0A). The AGC action is fast, typically finishing after four sub-carrier pulses. By default, the AGC action is blocked after the first few pulses of the sub-carrier signal. This prevents the AGC from interfering with the reception of the remaining data packet. In certain situations, this type of blocking is not optimal, so it can be removed by setting B0 = 1 (no_lim) in the RX special setting register (address 0A). The bits of the RX special settings register (address 0A), which control the receiver analog section, are shown in Table 5-20. 5.2.1 Received Signal Strength Indicator (RSSI) The RSSI measurement block measures the demodulated signal (except in the case of a direct command for RF-amplitude measurement described in the Direct Commands section). The measuring system latches the peak value, so the RSSI level can be read after the end of the receive packet. The RSSI register values reset with every transmission by the reader. This allows an updated RSSI measurement for each new tag response. Copyright 20062010, Texas Instruments Incorporated System Description 17 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Correlation between the RF input level and RSSI designation levels on the RX_IN1 and RX_IN2 are shown in Table 5-6 and Table 5-7. Table 5-6 shows the RSSI level versus RSSI bit value. The RSSI has seven levels (3 bits each) with 4-dB increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side envelope (positive or negative). Table 5-6. RSSI Level Versus Register Bit Value RSSI 1 2 3 4 5 6 7 Input level 2 mVpp 3.2 mVpp 5 mVpp 8 mVpp 13 mVpp 20 mVpp 32 mVpp As an example, from Table 5-7, let B2 = 1, B1 = 1, B0 = 0; this yields an RSSI value of 6. From Table 5-6 a Bit value of 6 would yield an RSSI level of 20 mVpp. Bit B7 B6 B5 B4 B3 B2 B1 B0 Signal Name Unused osc_ok rssi_x2 rssi_x1 rssi_x1 rssi_2 rssi_1 rssi_0 Table 5-7. RSSI Bit Value and Oscillator Status Register (0F) Function Comments Crystal oscillator stable MSB of auxiliary receiver RSSI Auxiliary receiver RSSI LSB of auxiliary receiver RSSI MSB of main receiver RSSI Main receiver RSSI LSB of main receiver RSSI 4 dB per step 5.2.2 Receiver Digital Section The received sub-carrier is digitized to form a digital representation of the modulated RF envelope. This digitized signal is applied to digital decoders and framing circuits for further processing. The digital part of the receiver consists of two sections, which partly overlap. The first section is the bit decoders for the various protocols, whereas the second section consists of framing logic. The bit decoders convert the sub-carrier coded signal to a bit stream and also to the data clock. Thus, the sub-carrier-coded signal is transformed to serial data and the data clock is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to noise or interference) sub-carrier signals. In the framing section, the serial bit-stream data is formatted in bytes. In this process, special signals like the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external microcontroller system. The start of the receive operation (successfully received SOF) sets the flags in the IRQ and status register. The end of the receive operation is indicated to the external system (MCU) by sending an interrupt request (pin 13 IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO. Any error in data format, parity, or CRC is detected, and the external system is notified of the error by an interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ and status register (address 0C). The bit-coding description of this register is given in Table 5-22. 18 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 The main register controlling the digital part of the receiver is the ISO control register (address 01). By writing to this register, the user selects the protocol to be used. With each new write in this register, the default presets are loaded in all related registers, so no further adjustments in other registers are needed for proper operation. Table 5-10 shows the coding of the ISO control register. Note that the TRF7961 does not include the ISO14443 functionality; its features/commands in this area are non-functional. The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit collision is detected, an interrupt request is sent and flag set in the IRQ and status register. The position of the bit collision is written in two registers. Register collision position, with address 0E, and in register collision position and interrupt mask (address 0D), in which only the bits B7 and B6 are used for collision position. The collision position is presented as a sequential bit number, where the count starts immediately after the start bit. For example, the collision in the first bit of the UID would give the value 00 0001 0000 in the collision-position registers. The count starts with 0, and the first 16 bits are the command code and the NVB byte. Note: the NVB byte is the number of valid bits. The receive section also has two timers. The RX-wait-time timer is controlled by the value in the RX wait time register (address 08). This timer defines the time after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents incorrect detections resulting from transients following the transmit operation. The value of the RX wait time register defines this time in increments of 9.44 s. This register is preset at every write to ISO control register (address 01) according to the minimum tag-response time defined by each standard. The RX no-response timer is controlled by the RX no response wait time register (address 07). This timer measures the time from the start of slot in the anti-collision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ status control register. This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 s. This register is also preset, automatically, for every new protocol selection. 5.2.3 Transmitter The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output stage. 5.2.3.1 Transmitter Analog The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF frequency for the RF output stage. Additionally, it also generates the clock signal for the digital section and clock signal displayed for the SYS_CLK (pin 27) which can be used by an external MCU system. During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60 kHz. During normal reader operation, SYS_CLK can be programmed by bits B4 and B5 in the modulator and SYS_CLK control register (address 09); available clock frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz. The reference crystal (HC49U) should have the following characteristics:

Parameter Frequency Mode of operation Type of resonance Frequency tolerance Aging Operation temperature range Equivalent series resistance Specification 13.560000 MHz Fundamental Parallel 20 ppm

< 5 ppm/year 40C to 85C 50 , minimum Copyright 20062010, Texas Instruments Incorporated System Description 19 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com NOTE The crystal oscillators two external shunt capacitor values are calculated based on the crystals specified load capacitance. The external capacitors (connected to the OSC pins 30 and 31), are calculated as two capacitors in series plus CS (oscillator's gate internal input/output capacitance plus PCB stray capacitance). The stray capacitance (CS) can be estimated at approximately 5 2 pF (typical). As an example, given a crystal with a required load capacitance (CL) of 18 pF, CL = ((C1 C2) / (C1 + C2)) + CS 18 pF = ((27 pF 27 pF) / (27 pF + 27 pF)) + 4.5 pF Hence, from this example, a 27-pF capacitor would be placed on pins 30 and 31 to ensure proper crystal oscillator operation. The transmit power level is selectable between half power of 100 mW (20 dBm) or full power of 200 mW

(23 dBm) when configured for 5-V automatic operation. The transmit output impedance is 8 when configured for half power and 4 when configured for full power. Selection of the transmit power level is set by bit B4 (rf_pwr) in the chip status control register (Table 5-9). When configured for 3-V automatic operation, the transmit power level is typically selectable between 33 mW (15 dBm) in half-power mode and 70 mW (18 dBm) in full-power mode (Vdd_RF at 3.3 V). Note that lower operating voltages result in reduced transmit power levels. In normal operation, the transmit modulation is configured by the selected ISO control register (address 01). External control of the transmit modulation is possible by setting the ISO control register (address 01) to direct mode. While in direct mode, the transmit modulation is made possible by selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by setting B6 = 1 (en_ook_p) in the modulator and SYS_CLK control register (address 09). ASK modulation depth is controlled by bits B0, B1 and B2 in the Modulator and SYS_CLK Control register (address 09). The range of the ASK modulation is 7%30%, or 100% (OOK). The coding of the modulator and SYS_CLK control register is shown in Table 5-19. The length of the modulation pulse is defined by the protocol selected in the ISO control register. With a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length can be corrected by using the TX pulse length register. If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 00h, the pulse length is equal to the value of the register in 73.7-ns increments. This means the range of adjustment can be between 73.7 ns and 18.8 s. 5.2.3.2 Transmitter - Digital the transmitter is very similar to that of The digital portion of the receiver. Before beginning data transmission, the FIFO should be cleared with a Reset command (0F). Data transmission is initiated with a selected command (described in the Direct Commands section, Table 5-29). The MCU then commands the reader to do a continuous Write command (3Dh, see Table 5-31) starting from register 1Dh. Data written into register 1Dh is the TX length byte1 (upper and middle nibbles), while the following byte in register 1Eh is the TX length byte2 (lower nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After the TX length bytes, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The TX length bytes and FIFO can be loaded with a continuous-write command because the addresses are sequential. If the data length is longer than the allowable size of the FIFO, the external system (MCU) is warned when the majority of data from the FIFO has already been transmitted by sending an interrupt request with a flag in the IRQ register signaling FIFO low/high status. The external system should respond by loading the next data packet into the FIFO. 20 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 At the end of the transmit operation, the external system is notified by another interrupt request with a flag in the IRQ register that signals the end of TX. The TX length register also supports incomplete bytes transmitted. The high two nibbles in register 1D and the nibble composed of bits B4B7 in register 1E store the number of complete bytes to be transmitted. Bit 0 (in register 1E) is a flag that signals the presence of additional bits to be transmitted that do not form a complete byte. The number of bits are stored in bits B1B3 of the same register (1E). The protocol is selected by the ISO control register (address 01), which also selects the receiver protocol. As defined by the selected protocol, the reader automatically adds all the special signals, like start of communication, end of communication, SOF, EOF, parity bits, and CRC bytes. The data is then coded to the modulation pulse level and sent to the modulation control of the RF output stage. This means that the external system is only required to load the FIFO with data, and all the low-level coding is done automatically. Also, all registers used in transmission are automatically preset to the optimum value when a new selection is entered into the ISO control register. Some protocols have options; two registers are provided to select the TX-protocol options. The first such register is ISO14443B TX options (address 02). It controls the SOF and EOF selection and EGT (extra guard time) selection for the ISO14443B protocol. The bit definitions of this register are given in Table 5-12. The second register controls the ISO14443 high bit-rate options. This register enables the use of different bit rates for RX and TX operations in the ISO14443 high bit-rate protocol. Additionally, it also selects the parity system for the ISO14443A high bit-rate selection. The bit definitions of this register are given in Table 5-13. The transmit section also has a timer that can be used to start the transmit operation at a precise time interval from a selected event. This is necessary if the tag requires a reply in an exact window of time following the tag response. The TX timer uses two registers (addresses 04 and 05). In first register

(address 04); two bits (B7 and B6) are used to define the trigger conditions. The remaining 6 bits are the upper bits and the 8 bits in register address 05 are lower bits, which are preset to the counter. The increment is 590 ns and the range of this counter is from 590 ns to 9.7 ms. The bit definitions (trigger conditions) are shown in Table 5-14. Copyright 20062010, Texas Instruments Incorporated System Description 21 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com 5.2.4 Direct Mode Direct mode allows the user to configure the reader in one of two ways. Direct mode 0 (bit 6 = 0, as defined in ISO control register) allows the user to use only the front-end functions of the reader, bypassing the protocol implementation in the reader. For transmit functions, the user has direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the user has direct access to the sub-carrier signal (digitized RF envelope signal) on I/O_6 (pin 23). Direct mode1 (bit 6 = 1, as defined in ISO control register) uses the sub-carrier signal decoder of the selected protocol (as defined in ISO control register). This means that the receive output is not the sub-carrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on I/O_6 (pin 23) and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the user has direct control over the RF modulation through the MOD input. This mode is provided so that the user can implement a protocol that has the same bit coding as one of the protocols implemented in the reader, but needs a different framing format. To select direct mode, the user must first choose which direct mode to enter by writing B6 in the ISO control register. This bit determines if the receive output is the direct sub-carrier signal (B6 = 0) or the serial data of the selected decoder. If B6 = 1, then the user must also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO control register. The reader actually enters the direct mode when B6 (direct) is set to 1 in the chip status control register. Direct mode starts immediately. The write command should not be terminated with a stop condition (see communication protocol), because the stop condition terminates the direct mode and clears B6. This is necessary as the direct mode uses one or two I/O pins (I/O_6, I/O_5). Normal parallel communication is not possible in direct mode. Sending a stop condition terminates direct mode. Figure 5-4 shows the different configurations available in direct mode. In mode 0, the reader is used as an AFE only, and protocol handling is bypassed. In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable framing level based on an existing ISO standard. In mode 2, data is ISO-standard formatted. SOF, EOF, and error checking are removed, so the microprocessor receives only bytes of raw data via a 12-byte FIFO. 22 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 TRF7960 TRF7961 5.2.5 Register Preset Figure 5-4. User-Configurable Modes After power-up and the EN pin low-to-high transition, the reader is in the default mode. The default configuration is ISO15693, single sub-carrier, high data rate, 1-out-of-4 operation. The low-level option registers (020B) are automatically set the circuitry optimally to the appropriate protocol parameters. to adapt When entering another protocol (writing to the ISO control register 01), the low-level option registers

(020B) are automatically configured to the new protocol parameters. After selecting the protocol, it is possible to change some low-level register contents if needed. However, changing to another protocol and then back, reloads the default settings, and the user must reload the custom settings. The Clo1 and Clo0 (register 09) bits, which define the microcontroller frequency available on the SYS_CLK pin, are the only two bits in the configuration registers that are not cleared during protocol selection. Copyright 20062010, Texas Instruments Incorporated System Description 23 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 Mode2:FullISOWithFramingandErrorChecking(TypicalMode)Analog Front End (AFE)Packetization/Framing14443A14443B15693Tag-itISO Encoder/DecodersMode 0:Raw, Sub-Carrier DataMode 1:Un-Framed Raw ISOFormatted Data TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.3 Register Descriptions www.ti.com Table 5-8. Register Address Space Adr (hex) Register Main Control Registers 00 01 Chip status control ISO control Protocol Sub-Setting Registers 02 03 04 05 06 07 08 09 0A 0B 16 17 18 19 ISO14443B TX options ISO 14443A high bit rate options TX timer setting, H-byte TX timer setting, L-byte TX pulse-length control RX no response wait RX wait time Modulator and SYS_CLK control RX special setting Regulator and I/O control Unused Unused Unused Unused Status Registers 0C 0D 0E 0F IRQ status Collision position and interrupt mask register Collision position RSSI levels and oscillator status FIFO Registers 1C 1D 1E 1F FIFO status TX length byte1 TX length byte2 FIFO I/O register Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NA NA NA NA R R/W R R R R/W R/W R/W 24 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 5.3.1 Control Registers Main Configuration Registers Table 5-9. Chip Status Control (00h) TRF7960 TRF7961 Controls the power mode, RF on / off, AGC, AM / PM Register default is 0x01. It is preset at EN = L or POR = H Bit B7 Bit Name stby Function 1 = standby mode 0 = active mode 1 = received sub-carrier signal (decoders bypassed) 0 = received decoded signal from selected decoder 1 = RF output active 0 = RF output not active 1 = half output power 0 = full output power 1 = RX_IN2 0 = RX_IN1 1 = AGC on 0 = AGC off 1 = Reciever enable for external field measurement 1 = 5 V operation (VIN) 0 = 3 V operation (VIN) B6 direct B5 B4 B3 B2 B1 B0 rf_on rf_pwr pm_on agc_on rec_on vrs5_3 Comments Standby mode keeps regulators and oscillator running en_rec =

L, en_tx = L The modulation control is direct through MOD input. The receiver sub-carrier signal is on I/0_6. When B5 = 1, it activates the RF field. 1 = RF driver at 8 0 = RF driver at 4 1 = Selects PM signal input 0 = Selects AM signal input AGC selection Receiver and oscillator are enabled; intended for external field measurement. Selects the VDD_RF range; 5 V (4.3 V 5 V), or 3 V (2.7 V 3.4 V) Copyright 20062010, Texas Instruments Incorporated System Description 25 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Table 5-10. ISO Control (01h) Controls the ISO selection Register default is 0x02, which is ISO15693 high bit rate, one sub-carrier, 1 out of 4. It is preset at EN = L or POR = H. Bit B7 Function Receiving without CRC Bit Name rx_crc_n Comments 1 = no RX CRC 0 = RX CRC 0 = output is sub-carrier data. 1 = output is bit stream (I/O_6) and bit clock (I/O_5) from decoder selected by ISO bits Should always be set to 0 dir_mode Direct mode type RFID mode B6 B5 B4 B3 B2 B1 B0 rfid iso_4 iso_3 iso_2 iso_1 iso_0 RFID mode See Table 5-11 Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 Protocol Table 5-11. RFID Mode Selections one sub-carrier one sub-carrier one sub-carrier one sub-carrier double sub-carrier double sub-carrier double sub-carrier double sub-carrier 1 out of 4 1 out of 256 1 out of 4 1 out of 256 1 out of 4 1 out of 256 1 out of 4 1 out of 256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 ISO15693 low bit rate ISO15693 low bit rate ISO15693 high bit rate ISO15693 high bit rate ISO15693 low bit rate ISO15693 low bit rate ISO15693 high bit rate ISO15693 high bit rate ISO14443A bit rate ISO14443A high bit rate ISO14443A high bit rate ISO14443A high bit rate ISO14443B bit rate ISO14443B high bit rate ISO14443B high bit rate ISO14443B high bit rate Tag-it 6.62 kbps 6.62 kbps 26.48 kbps 26.48 kbps 6.67 kbps 6.67 kbps 26.69 kbps 26.69 kbps 106 kbps 212 kbps 424 kbps 848 kbps 106 kbps 212 kbps 424 kbps 848 kbps Remarks Default for reader RX bit rate when TX bit rate is different than RX

(reg03) RX bit rate when TX bit rate is different than RX

(reg03) 26 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 5.3.2 Control Registers Sub Level Configuration Registers Table 5-12. ISO14443B TX Options (02h) TRF7960 TRF7961 Selects the ISO subsets for ISO14443B TX Register default is set to 0x00 at POR = H or EN = L Bit B7 B6 B5 B4 Bit Name egt2 egt1 egt0 eof_l0 Function TX EGT time select MSB TX EGT time select TX EGT time select LSB 1 = EOF, 0 = EOF, 1 = SOF, 0 = SOF, 1 = SOF, 0 = SOF, 1 = EGT after each byte 0 = EGT after last byte is omitted 0 length 11 etu 0 length 10 etu 1 length 03 etu 1 length 02 etu 0 length 11 etu 0 length 10 etu B3 B2 B1 B0 sof_l1 sof _l0 l_egt Unused Comments Three bit code defines the number of etu (0-7) which separate two characters. ISO14443B TX only ISO14443B TX only Table 5-13. ISO 14443A High-Bit-Rate Options (03h) Parity Register default is set to 0x00 at POR = H, or EN = L and at each write to ISO control register Bit B7 B6 B5 Function TX bit rate different than RX bit rate enable TX bit rate Bit Name dif_tx_br tx_br1 tx_br0 Comments Valid for ISO14443A/B high bit rate tx_br1 = 0, tx_br = 0 tx_br1 = 0, tx_br = 1 tx_br1 = 1, tx_br = 0 tx_br1 = 1, tx_br = 1 For 14443A high bit rate, coding and decoding 106 kbps 212 kbps 424 kbps 848 kbps 1 = parity odd except last byte which is even for TX 1 = parity odd except last byte which is even for RX B4 B3 B2 B1 B0 parity-2tx parity-2rx Unused Unused Unused Table 5-14. TX Timer H-Byte (04h) Register default is set to 0xC2 at POR = H or EN = L and at each write to ISO control register Bit B7 B6 Function Timer start condition Timer start condition Bit Name Tm_st1 Tm_st0 Comments tm_st1 = 0, tm_st0 = 0 tm_st1 = 0, tm_st0 = 1 tm_st1 = 1, tm_st0 = 0 tm_st1 = 1, tm_st0 = 1 beginning of TX SOF end of TX SOF beginning of RX SOF end of RX SOF B5 B4 B3 B2 B1 B0 Tm_lengthD Tm_lengthC Tm_lengthB Tm_lengthA Tm_length9 Tm_length8 Timer length MSB Timer length Timer length Timer length Timer length Timer length LSB Copyright 20062010, Texas Instruments Incorporated System Description 27 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Table 5-15. TX Timer L-Byte (05h) Register default is set to 0x00 at POR = H or EN = L and at each write to ISO control register Bit B7 B6 B5 B4 B3 B2 B1 B0 Function Timer length MSB Timer length Timer length Timer length Timer length Timer length Timer length Timer length LSB Bit Name Tm_length7 Tm_length6 Tm_length5 Tm_length4 Tm_length3 Tm_length2 Tm_length1 Tm_length0 Comments Defines the time when delayed transmission is started. RX wait range is 590 ns to 9.76 ms (1..16383) Step size 590 ns All bits low (00): Timer is disabled. Preset: 00 all other protocols Table 5-16. TX Pulse Length Control (06h) Function Pulse length MSB Controls the length of TX pulse Register default is set to 0x00 at POR = H or EN = L and at each write to ISO control register. Bit B7 B6 B5 B4 B3 B2 B1 B0 Comments The pulse range is 73.7 ns to 18.8 s (1255), step size 73.7 ns All bits low (00): pulse length control is disabled Preset: 9.44 s ISO15693 Preset: 11 s Tag-It Preset: 2.36 s ISO14443A Preset: 1.4 s ISO14443A at 212 kbps Preset: 737 ns ISO14443A at 424 kbps Preset: 442 ns ISO14443A at 848 kbps): pulse length control is disabled Bit Name Pul_p2 Pul_p1 Pul_p0 Pul_c4 Pul_c3 Pul_c2 Pul_c1 Pul_c0 Pulse length LSB Table 5-17. RX No Response Wait Time (07h) Function No response MSB Defines the time when no response Interrupt is sent Default: default is set to 0x0E at POR = H or EN = L and at each write to ISO control register. Bit B7 B6 B5 B4 B3 B2 B1 B0 Bit Name NoResp7 NoResp6 NoResp5 NoResp4 NoResp3 NoResp2 NoResp1 NoResp0 Comments Defines the time when no response interrupt is sent It starts from the end of TX EOF. RX no response wait range is 37.76 s to 962 8s (1...255), Step size 37.76 s Preset: 755 s ISO15693 Preset: 1812 s ISO15693 low data rate Preset: 604 s Tag-It Preset: 529 s all other protocols No response LSB 28 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 Table 5-18. RX Wait Time (08h) TRF7960 TRF7961 Function RX wait Defines the time after TX EOF when the RX input is disregarded Register default is set to 0x1F at POR = H or EN = L and at each write to ISO control register. Bit B7 B6 B5 B4 B3 B2 B1 Comments Defines the time during which the RX input is ignored. It starts from the end of TX EOF. RX wait range is 9.44 s to 2407 s (1...255), Step size 9.44 s Preset: 293 s ISO15693 Preset: 66 s ISO14443A and B Preset: 180 s Tag-It Bit Name Rxw7 Rxw6 Rxw5 Rxw4 Rxw3 Rxw2 Rxw1 Table 5-19. Modulator and SYS_CLK Control (09h) Controls the modulation depth, modulation input and ASK / OOK control Register default is set to 0x11 at POR = H or EN = L, and at each write to ISO control register, except Clo1 and Clo0. Bit B7 B6 Bit Name Unused en_ook_p Comments Function Valid only when ISO control register (01) is configured to direct mode 1 = enables external selection of ASK or OOK modulation SYS_CLK output frequency MSB SYS_CLK output frequency LSB Clo1 Clo0 en_ana Pm2 Pm1 Pm0 1 = Enables analog output on ASK/OOK pin

(pin12) Modulation depth MSB Modulation depth Modulation depth LSB B5 B4 B3 B2 B1 B0 Clo1 Clo0 CL_SYS Output state 0 0 1 1 0 1 0 1 disabled 3.3 MHz 6.78 MHz 13.56 MHz For test and measurement Pm2 0 0 0 0 1 1 1 1 Pm1 0 0 1 1 0 0 1 1 Pm0 Mod Type and %

0 1 0 1 0 1 0 1 ASK 10%

OOK (100%) ASK 7%

ASK 8.5%

ASK 13%

ASK 16%

ASK 22%

ASK 30%

Copyright 20062010, Texas Instruments Incorporated System Description 29 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Table 5-20. RX Special Setting Register (Address 0Ah) Sets the gains and filters directly Register default is set to 0x40 at POR = H or EN = L, and at each write to the ISO control register. Bit B7 B6 B5 B4 Comments Appropriate for 212-kHz sub-carrier system Appropriate for 424-kHz sub-carrier used in ISO15693 and Tag-It Appropriate for Manchester-coded 848-kHz sub-carrier used in ISO14443A Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443 Bit Name C212 C424 M848 hbt Function Bandpass 110 kHz to 570 kHz Bandpass 200 kHz to 900 kHz Bandpass 450 kHz to 1.5 MHz Bandpass 100 kHz to 1.5 MHz Gain reduced for 7 dB 01 gain reduction for 5 dB 10 gain reduction for 10 dB 11 gain reduction for 15 dB AGC activation level change gd1 gd2 agcr B3 B2 B1 B0 no-lim AGC action is not limited in time Sets the RX gain reduction AGC activation level changed from 5 times the digitizing level to 3 times the digitizing level. AGC action can be done any time during receive process. It is not limited to the start of receive. Table 5-21. Regulator and I/O Control (0Bh) Control the three voltage regulators Register default is set to 0x87 at POR = H or EN = L Bit B7 Bit Name auto_reg Function 0 = setting regulator by option bits

(vrs3_5 and vrs2, vrs1 and vrs0) 1 = automatic setting Support for external power amplifier 1 = enable low peripheral communication voltage B6 B5 B4 B3 B2 B1 B0 en_ext_pa io_low Unused Unused vrs2 vrs1 vrs0 Voltage set MSB Voltage set LSB Comments Auto system sets VDD_RF to VIN 250 mV and VDD_A and VDD_X to VIN 250 mV, but not higher than 3.4 V. Receiver inputs accept externally demodulated sub-carrier, OOK pin becomes modulation output for external amplifier. When HIGH, it decreases output resistance of logic outputs. Should be set HIGH when VDD_I/O voltage is below 2.7 V. Default is LOW. Default is LOW. vrs3_5 = L: VDD_RF, VDD_A, VDD_X range 2.7 V to 3.4 V 30 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com 5.3.3 Status Registers TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 Table 5-22. IRQ Status Register (0Ch) Displays the cause of IRQ and TX/RX status Register default is set to 0x00 at POR = H or EN = L, and at each write to the ISO control register. It is also automatically reset at the end of a read phase. The reset also removes the IRQ flag. Bit B7 Function IRQ set due to end of TX Bit Name Irq_tx Comments Signals that TX is in progress. The flag is set at the start of TX but the interrupt request is sent when TX is finished. Signals that RX SOF was received and RX is in progress. The flag is set at the start of RX but the interrupt request is sent when RX is finished. Signals FIFO high or low (less than 4 or more than 8) B6 B5 B4 B3 B2 B1 B0 Irg_srx IRQ set due to RX start Irq_fifo Irq_err1 Irq_err2 Irq_err3 Irq_col Irq_noresp Signals the FIFO is 1/3 > FIFO >

2/3 CRC error Parity error Byte framing or EOF error Collision error No-response interrupt Indicates receive CRC error Indicates parity error Indicates framing error For ISO14443A and ISO15693 single sub-carrier Signal to MCU that next slot command can be sent Table 5-23. Collision Position and Interrupt Mask Register (0Dh) Register default is set to 3E at POR = H and EN = L. Collision bits reset automatically after read operation. Bit B7 B6 B5 B4 B3 B2 Bit Name Col9 Col8 En_irq_fifo En_irq_err1 En_irq_err2 En_irq_err3 Comments Supported: ISO15693, single sub-carrier, and ISO14443A Function Bit position of collision MSB Bit position of collision Interrupt enable for FIFO Interrupt enable for CRC Interrupt enable for Parity Interrupt enable for Framing error or EOF Interrupt enable for collision error Enables no-response interrupt B1 B0 En_irq_col En_irq_noresp Table 5-24. Collision Position (0Eh) Function Bit position of collision MSB Displays the bit position of collision or error Register default is set to 0x00 at POR = H and EN = L. Automatically reset after read operation. Bit B7 B6 B5 B4 B3 B2 B1 B0 Bit Name Col7 Col6 Col5 Col4 Col3 Col2 Col1 Col0 Bit position of collision LSB Comments Supported is ISO15693, single sub-carrier, and ISO14443A In other protocols, it shows the bit position of error, either frame, SOF-EOF, parity, or CRC error. Copyright 20062010, Texas Instruments Incorporated System Description 31 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com Table 5-25. RSSI Levels and Oscillator Status Register (0Fh) Displays the signal strength on both reception channels and RF amplitude during RF-off state The RSSI values are valid from reception start till start of next transmission. Bit Comments B7 B6 B5 Bit Name Unused Oscok rssi_x2 Function Crystal oscillator stable indicator RSSI value of auxiliary channel (4 dB Auxiliary channel is by default PM. It can be set to AM with B3 of chip state per step) MSB control register (00). B4 B3 B2 B1 B0 rssi_x1 rssi_x0 rssi_2 rssi_1 rssi_0 RSSI value of auxiliary channel (4 dB per step) LSB RSSI value of active channel (4 dB per step) MSB RSSI value of active channel (4 dB per step) LSB Active channel is default AM and can be set to PM with option bit B3 of chip state control register (00). 32 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com 5.3.4 FIFO Control Registers Table 5-26. FIFO Status (1Ch) TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 Low nibbles of complete bytes to be transferred through FIFO; Information about a broken byte and number of bits to be transferred from it Bit B7 B6 B5 B4 B3 Comments Reserved for future use (RFU) Indicates that 9 bytes are already in the FIFO (for RX) Indicates that only 3 bytes are in the FIFO (for TX) Too much data was written to the FIFO Bits B0:B3 indicate how many bytes that are loaded in FIFO were not read out yet (displays N 1 number of bytes). If 8 bytes are in the FIFO, this number is 7. Function Set to LOW FIFO level HIGH FIFO level LOW FIFO overflow error FIFO bytes fb[3]

Bit Name RFU Fhil Flol Fove Fb3 B2 B1 B0 Fb2 Fb1 Fb0 FIFO bytes fb[2]

FIFO bytes fb[1]

FIFO bytes fb[0]

Table 5-27. TX Length Byte1 (1Dh) High 2 nibbles of complete bytes to be transferred through FIFO Register default is set to 0x00 at POR and EN=0. It is also automatically reset at TX EOF Bit B7 B6 B5 B4 B3 B2 B1 B0 Function Number of complete byte bn[11]

Number of complete byte bn[10]

Number of complete byte bn[9]

Number of complete byte bn[8]

Number of complete byte bn[7]

Number of complete byte bn[6]

Number of complete byte bn[5]

Number of complete byte bn[4]

Bit Name Txl11 Txl10 Txl9 Txl8 Txl7 Txl6 Txl5 Txl4 Comments High nibble of complete bytes to be transmitted Middle nibble of complete bytes to be transmitted Table 5-28. TX Length Byte2 (1Eh) Low nibbles of complete bytes to be transferred through FIFO; Information about a broken byte and number of bits to be transferred from it Register default is set to 0x00 at POR and EN=0. It is also automatically reset at TX EOF Bit B7 B6 B5 B4 B3 B2 B1 B0 Function Number of complete byte bn[3]

Number of complete byte bn[2]

Number of complete byte bn[1]

Number of complete byte bn[0]

Broken byte number of bits bb[2]

Broken byte number of bits bb[1]

Broken byte number of bits bb[0]

Broken byte flag Number of bits in the last broken byte to be transmitted. It is taken into account only when broken byte flag is set. Bit Name Txl3 Txl2 Txl1 Txl0 Bb2 Bb1 Bb0 Bbf Comments Low nibble of complete bytes to be transmitted If 1, indicates that last byte is not complete 8 bits wide. Copyright 20062010, Texas Instruments Incorporated System Description 33 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com 5.4 Direct Commands From MCU to Reader 5.4.1 Command Codes Table 5-29. Command Codes Command Code (hex) 00 03 0F 10 11 12 13 14 16 17 18 19 1A Command Idle Software Initialization Reset Transmission without CRC Transmission with CRC Delayed transmission without CRC Delayed transmission with CRC Transmit next time slot Block receiver Enable receiver Test internal RF (RSSI at RX input with TX ON) Test external RF (RSSI at RX input with TX OFF) Receiver gain adjust Comments Software initialization, same as power on reset ISO15693, Tag-It Note: The command code values from Table 5-29 are substituted in Table 5-32, bit 0 through bit 4. Also, the most-significant bit (MSB) in Table 5-31 must be set to 1. 5.4.2 Reset The reset command clears the FIFO contents and FIFO status register (1Ch). It also clears the register storing the collision error location (0Eh). 5.4.3 Transmission With CRC The transmission command must be sent first, followed by transmission length bytes, and FIFO data. The reader starts transmitting after the first byte is loaded into the FIFO. The CRC byte is included in the transmitted sequence. 5.4.4 Transmission Without CRC Same as Section 5.4.3 with CRC excluded. 5.4.5 Delayed Transmission With CRC The transmission command must be sent first, followed by the transmission length bytes, and FIFO data. The reader transmission is triggered by the TX timer. 5.4.6 Delayed Transmission Without CRC Same as above with CRC excluded. 5.4.7 Transmission Next Slot When this command is received, the reader transmits the next slot command. The next slot sign is defined by the protocol selection. 5.4.8 Receiver Gain Adjust This command should be executed when the MCU determines that no TAG response is coming and when 34 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 the RF and receivers are switched ON. When this command is received, the reader observes the digitized receiver output. If more than two edges are observed in 100 s, the window comparator voltage is increased. The procedure is repeated until the number of edges (changes of logical state) of the digitized is less than 2 (in 100 s). The command can reduce the input sensitivity in 5-dB reception signal increments up to 15 dB. This command ensures better operation in a noisy environment. The gain setting is reset to maximum gain at EN = 0, POR = 1. 5.4.9 Test External RF (RSSI at RX input with TX OFF) This command can be used in active mode when the RF receiver is switched ON, and the RF output is switched OFF (bit B1=1 in the chip status register, rec-on. See Table 5-9). The level of the RF signal received on the antenna is measured and displayed in the RSSI levels register. The relation between the 3-bit code and the external RF field strength [A/m] must be determined by calculation or by experiments for each antenna design. The antenna Q and connection to the RF input influence the result. The nominal relation between the RF peak-to-peak voltage at the receiver inputs and its corresponding RSSI level is presented as follows. Receiver Input [mVPP]

RSSI level 40 1 60 2 80 3 100 4 140 5 180 6 300 7 If the direct command test RF internal or test RF external is used immediately after activation, it should be preceded with a command enable RX to activate the RX section. For proper execution of the test RF commands, the RX section must be enabled. This happens automatically when a data exchange between the reader and the tag is done, or by sending a direct command enable RX. 5.4.10 Test Internal RF (RSSI at RX input with TX ON) This command measures the level of the RF carrier at the receive inputs. Its operating range is between 300 mVp and 2.1 Vp with a step size of 300 mV. The two values are displayed in the RSSI levels register. The command is intended for diagnostic purposes to set the correct RX_IN levels. The optimum RX_IN input level is approximately 1.6 Vp, or an RSSI level of 5 or 6. The nominal relationship between the input RF peak level and the RSSI code is presented as follows. Receiver Input [mVPp]

RSSI Level 300 1 600 2 900 3 1200 4 1500 5 1800 6 2100 7 5.4.11 Block Receiver The block receiver command puts the digital part of receiver (bit decoder and framer) in reset mode. This is useful in an extremely noisy environment, where the noise level could otherwise cause a constant switching of the sub-carrier input of the digital part of the receiver. The receiver (if not in reset) would try to catch a SOF signal, and if the noise pattern matched the SOF pattern, an interrupt would be generated, falsely signaling the start of an RX operation. A constant flow of interrupt requests can be a problem for the external system (MCU), so the external system can stop this by putting the receive decoders in reset mode. The reset mode can be terminated in two ways. The external system can send the enable receiver command. The reset mode is also automatically terminated at the end of a TX operation. The receiver can stay in reset after end of TX if the RX wait time register (address 08) is set. In this case, the receiver is enabled at the end of the wait time following the transmit operation. 5.4.12 Enable Receiver This command clears the reset mode in the digital part of the receiver if the reset mode was entered by the block receiver command. Copyright 20062010, Texas Instruments Incorporated System Description 35 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.5 Reader Communication Interface 5.5.1 Introduction www.ti.com The communication interface to the reader can be configured in two ways: a parallel 8-pin interface and a Data_Clk or a serial peripheral interface (SPI). These modes are mutually exclusive; only one mode can be used at a time in the application. When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired according to Table 5-30. At power up, the reader samples the status of these three pins. If they are not the same (all High or all Low) it enters one of the possible SPI modes. The reader always behaves as the slave while the microcontroller (MCU) behaves as the master device. The MCU initiates all communications with the reader and is also used to communicate with the higher levels (application layer). The reader has an IRQ pin to prompt the MCU for attention if the reader detects a response from the proximity/vicinity integrated circuit card (PICC/VICC). Communication is initialized by a start condition, which is expected to be followed by an Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and its format is shown in Table 5-31. Table 5-30. Pin Assignment in Parallel and Serial Interface Connection or Direct Mode Parallel-Direct DATA_CLK SPI with SS DATA_CLK from master SPI without SS DATA_CLK from master Parallel Pin DATA_ DATA_CLK CLK I/O_7 A/D[7]

I/O_6 A/D[6]

Direct mode, data out (sub-carrier or bit stream) MISO (2) = data-out (MCU-out) Direct mode, strobe bit clock out MOSI (1) = data-in (reader-in) See Note 3 SS slave select (4) at VDD at VDD at VSS IRQ interrupt MOSI(1) = data-in

(reader-in) MISO(2) = data-out

(MCU-out) See Note 3 at VDD at VSS at VSS IRQ interrupt I/O_5 (3) A/D[5]

I/O_4 A/D[4]

A/D[3]

I/O_3 A/D[2]

I/O_2 A/D[1]

I/O_1 I/O_0 A/D[0]

IRQ IRQ interrupt

(1) MOSI master out, slave in

(2) MISO master in, slave out

(3) IRQ interrupt

(4) Slave-select pin active-low IO_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary first to write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The IO_5 pin goes high in this second 8 clocks. But for normal SPI operation this pin IO_5 is not used. Table 5-31. Address/Command Word Bit Distribution Bit Function 0 = address, 1 = command 1 = read, 0 = write 1 = Cont. mode Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description Command control bit Read/Write Continuous address mode Address/Command bit 4 Address/Command bit 3 Address/Command bit 2 Address/Command bit 1 Address/Command bit 0 Address 0 R/W R/W Adr 4 Adr 3 Adr 2 Adr 1 Adr 0 Command 1 0 0 Cmd 4 Cmd 3 Cmd 2 Cmd 1 Cmd 0 36 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 The MSB (bit 7) determines if the word is to be used as a command or as an address. The last two columns of Table 5-31 show the function of the separate bits if either address or command is written. Data is expected once the address word is sent. In continuous-address mode (Cont. mode = 1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the address is incremented by one. Continuous mode can be used to write to a block of control registers in a single stream without changing the address;

the predefined standard control registers from the MCUs non-volatile memory to the reader. In non-continuous address mode (simple addressed mode), only one data word is expected after the address. for example, setup of Address mode is used to write or read the configuration registers or the FIFO. When writing more than 12 bytes to the FIFO, the continuous address mode should be set to 1. The command mode is used to enter a command resulting in reader action (initialize transmission, enable reader, and turn reader On/Off...) An example of expected communication between MCU and reader is shown below. Continuous address mode Start Adr x Data(x) Data(x+1) Data(x+2) Data(x+3) Data(x+4)

... Data(x+n) StopCont Non-continuous address mode (single address mode) Start Adr x Data(x) Adr y Data(y)

... Adr z Data(z) StopSgl Command mode Start Cmd x

(Optional data or command) Stop Copyright 20062010, Texas Instruments Incorporated System Description 37 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.6 Parallel Interface Communication www.ti.com In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high. This is used to reset the interface logic. Figure 5-5 shows the sequence of the data, with an 8-bit address word first, followed by data. Communication is ended by:

the StopSmpl condition, where the falling edge on the I/O_7 pin is expected while CLK is high the StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK is low in order to reset the parallel interface and be ready for the new communication sequence The StopSmpl condition is also used to terminate the direct mode. Figure 5-5. Parallel Interface Communication With Simple Stop Condition StopSmpl Figure 5-6. Parallel Interface Communication With Continuous Stop Condition StopCont 38 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 a1 [7]d1 [7]a2 [7]d2 [7]aN [7]dN [7]StartConditionStopSmplConditionCLKI/O_ [7]I/O_[6:0]a1 [6:0]a2 [6:0]d1 [6:0]d2 [6:0]aN [6:0]dN [6:0]50 nsa0 [7]d0 [7]StartConditionCLKI/O_[7]I/O_[6:0]a0 [6:0]d0 [6:0]xxd1 [6:0]d2 [6:0]d2 [7]dN [6:0]d3 [6:0]dN [7]xxStopContContinuous Moded1 [7]d3 [7]50 ns www.ti.com 5.6.1 Receive TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ status register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to determine the reason for the interrupt by reading the IRQ status register (address 0Ch), after which the MCU reads the data from the FIFO. If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation when the ninth byte is loaded into the FIFO (75% full). The MCU should again read the content of the IRQ status register to determine the cause of the interrupt request. If the FIFO is 75% full (as marked with flag B5 in IRQ status register and by reading the FIFO status register), the MCU should respond by reading the data from FIFO to make room for new incoming receive data. When the receive operation is finished, the interrupt is sent and the MCU must check how many words are still present in the FIFO before it finishes reading. If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the IRQ status register, which indicates that the MCU reception was completed incorrectly. 5.6.2 Transmit Before beginning data transmission, the FIFO should be cleared with a reset command (0F). Data transmission is initiated with a selected command (described in the Direct Commands section, Table 5-29). The MCU then commands the reader to do a continuous write command (3Dh, see Table 5-31) starting from register 1Dh. Data written into register 1Dh is the TX length byte1 (upper and middle nibbles), while the following byte in register 1Eh is the TX length byte 2 (lower nibble and broken byte length). Note that the TX byte length determines when the reader sends the EOF byte. After the TX length bytes are written, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written into the FIFO. The loading of TX length bytes and the FIFO can be done with a continuous-write command, as the addresses are sequential. At the start of transmission, the flag B7 (Irq_tx) is set in the IRQ status register. If the transmit data is shorter than or equal to 4 bytes, the interrupt is sent only at the end of the transmit operation. If the number of bytes to be transmitted is higher or equal to 5, then the interrupt is generated. This occurs also when the number of bytes in the FIFO reaches 3. The MCU should check the IRQ status register and FIFO status register and then load additional data to the FIFO, if needed. At the end of the transmit operation, an interrupt is sent to inform the MCU that the task is complete. Figure 5-7. Data Output Only When CLK Is High Copyright 20062010, Texas Instruments Incorporated System Description 39 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 StartConditionCLKI/O_[7]I/O_[6:0]a0 [6:0]d0 [6:0]xxd1 [6:0]d2 [6:0]dN [6:0]d3 [6:0]xxStopContValid Ouput Dataa0 [7]d0 [7]d2 [7]dN [7]d1 [7]d3 [7]Internal OEOutput Data50 ns TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.7 Serial Interface Communication www.ti.com interface is required, parallel When an SPI I/O_1, and I/O_0, must be hard wired according to Table 5-31. On power up, the reader looks for the status of these pins; if they are not the same (not all high, or not all low), the reader enters into one of two possible SPI modes. I/O pins, I/O_2, The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the reader's IRQ register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ status register. The dummy read is required in SPI mode because the reader's IRQ status register needs an additional clock cycle to clear the register. This is not required in parallel mode because the additional clock cycle is included in the Stop condition. A procedure for a dummy read is as follows:

A. Starting the dummy read:

(a) When using slave select (SS): set SS bit low.

(b) When not using SS: start condition is when SCLK is high (See Table 5-30). B. Send address word to IRQ status register (0Ch) with read and continuous address mode bits set to 1

(See Table 5-31). C. Read 1 byte (8 bits) from IRQ status register (0Ch). D. Dummy-read 1 byte from register 0Dh (collision position and interrupt mask). E. Stopping the dummy read:

(a) When using slave select (SS): set SS bit high.

(b) When not using SS: stop condition when SCLK is high (See Table 5-30). 5.7.1 SPI Interface Without SS* (Slave Select) Pin The serial interface without the slave select pin must use delimiters for the start and stop conditions. Between these delimiters, the address, data, and command words can be transferred. All words must be 8 bits long with MSB transmitted first. Figure 5-8. Serial SPI Interface Communication (No SS* Pin) In this mode, a rising edge on data-in (I/O_7, pin 24) while SCLK is high resets the serial interface and prepares it to receive data. Data-in can change only when SCLK is low and is taken by the reader on the SCLK rising edge. Communication is terminated by the stop condition when the data-in falling edge occurs during a high SCLK period. 5.7.2 SPI Interface With SS* (Slave Select) Pin The serial interface is in reset while the SS* signal is high. Serial data-in (MOSI) changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 5-9. Communication is terminated when the SS* signal goes high. All words must be 8 bits long with the MSB transmitted first. 40 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 b7b6b5b4b3b2b1b0StartConditionStopConditionSCLKData INData Out50 ns www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 TRF7960 TRF7961 Figure 5-9. SerialSPI Interface Communication (Write Mode) Copyright 20062010, Texas Instruments Incorporated System Description 41 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 SCLKMOSISS*B7B6B5B4B3B2B1B0Write Operation TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 www.ti.com The SPI read operation is shown in Figure 5-10. Figure 5-10. Serial SPI Interface Communication (Read Mode) The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 5-10. During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first). Note:

When using the hardware SPI (for example, an MSP430 hardware SPI) to implement the foregoing feature, care must be taken to switch the SCLK polarity after write phase for proper read operation. The example clock polarity for the MSP430-specific environment is shown in the write-mode and read-mode boxes of Figure 5-10. See the USART-SPI chapter for any specific microcontroller family for further information on the setting the appropriate clock polarity. This clock polarity switch must be done for all read (single, continuous) operations. The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also, the SS* should be low during the whole write and read operation. The continuous read operation is illustrated in Figure 5-11 42 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 Write ModeCKPH1, CKPL0 (MSP430)DataTransitionSCLK Falling EdgeMOSI ValidSCLK Rising EdgeSwitchSCLKPolarityRead ModeCKPH0, CKPL0 (MSP430)DataTransitionSCLK Rising EdgeMISO ValidSCLK Falling EdgeSingle Read OperationSCLKMOSIMISOSS*WriteAddress ByteRead Data ByteB7B7B6B6B5B5B4B4B3B3B2B2B1B1B0B0Don't CareNo DataTransitions (All High/Low) www.ti.com SLOU186FAUGUST 2006REVISED AUGUST 2010 TRF7960 TRF7961 Figure 5-11. SPI Interface Communication (Continuous Read Mode) Note:

Special steps are needed to read the TRF796x IRQ status register (register address 0x0C) in SPI mode. The status of the bits in this register is cleared after a dummy read. The following steps must be followed when reading the IRQ status register. 1. Write in command 0x6C: read 'IRQ status' register in continuous mode (eight clocks). 2. Read out the data in register 0x0C (eight clocks). 3. Generate another eight clocks (as if reading the data in register 0x0D) but ignore the MISO data line. This is shown in Figure 5-12. Figure 5-12. SPI Interface Communication (IRQ Status Register Read) Copyright 20062010, Texas Instruments Incorporated System Description 43 Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 MOSIMISOSS*SCLKB0B0B0B7B7B7B6B6B6B5B5B5B4B4B4B3B3B3B2B2B2B1B1B1NoDataTransitions(AllHigh/Low)NoDataTransitions(AllHigh/Low)DontCareContinuous Read OperationWriteAddressByteReadDataByte1ReadDataBytenMOSIMISOSS*SCLKB0B0B7B7B6B6B5B5B4B4B3B3B2B2B1B1NoDataTransitions(AllHigh/Low)NoDataTransitions(AllHigh/Low)DontCareIgnoreSpecial CaseIRQ Status Register ReadDummyReadRead Data inIRQ Status RegisterWriteAddressByte (0x6C) TRF7960 TRF7961 SLOU186FAUGUST 2006REVISED AUGUST 2010 5.7.2.1 FIFO Operation www.ti.com The FIFO is a 12-byte register at address 1Fh with byte storage locations 0 to 11. FIFO data is loaded in a cyclical manner and can be cleared by a reset command (0F). Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 4-bit FIFO byte counter (bits B0B3 in register 1Ch) that keeps track of the number of bytes loaded into the FIFO. If the number of bytes in the FIFO is n, the register value is n 1 (number of bytes in FIFO register). If 8 bytes are in the FIFO, the FIFO counter (bits B0B3 in register 1Ch) has the value 7. A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 1Dh and 1Eh) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided in register 1Eh (bits B0-B3). Together these counters make up the TX length value that determines when the reader generates the EOF byte. FIFO status flags are as follows:

1. FIFO overflow (bit B4 of register 1Ch) indicates that the FIFO was loaded too soon 2. FIFO level too low (bit B5 of register 1Ch) indicates that only three bytes are left to be transmitted

(Can be used during transmission) 3. FIFO level high (bit B6 of register 1Ch) indicates that nine bytes are already loaded into the FIFO

(Can be used during reception to generate a FIFO reception IRQ. This is to notify the MCU to service the reader in time to ensure a continuous data stream.) During transmission, the FIFO is checked for an almost-empty condition, and during reception for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single sequence is 12 bytes. (Note: The number of bytes in a frame, transmitted or received, can be greater than 12 bytes.) During transmission, the MCU loads the reader's FIFO (or during reception the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the number of bytes in the FIFO is less than 3 or greater than 9, so that MCU can send new data or remove the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not surpass the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception. Transmission starts automatically after the first byte is written into FIFO. 5.8 External Power Amplifier Application Applications requiring an extended read range can use an external power amplifier together with the TRF7960/61. This can be implemented by adding an external power amplifier on the transmit side and external sub-carrier detectors on the receive side. To implement the external power amplification feature, certain registers must be programmed as shown below. 1. Set bit B6 of the Regulator and I/O Control register to 1 (see Table 5-21). This setting has two functions, first to provide a modulated signal for the transmitter if needed, and second to configure the TRF7960/61 receiver inputs for an external demodulated sub-carrier input. 2. Set bit B3 of the modulation and SYS_CLK control register to 1 (see Table 5-19). This function configures the ASK / OOK pin for either a digital or analog output (B3 = 0 enables a digital output, B3 = 1 enables an analog output). 44 System Description Copyright 20062010, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TRF7960 TRF7961 www.ti.com PACKAGING INFORMATION PACKAGE OPTION ADDENDUM 25-Jul-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TRF7960RHBR ACTIVE TRF7960RHBT ACTIVE TRF7961RHBR ACTIVE TRF7961RHBT ACTIVE QFN QFN QFN QFN RHB RHB RHB RHB 32 32 32 32 3000 250 3000 250 Green (RoHS

& no Sb/Br) Green (RoHS

& no Sb/Br) Green (RoHS

& no Sb/Br) Green (RoHS

& no Sb/Br) Lead/

Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR Samples

(Requires Login) CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 www.ti.com 14-Jul-2012 PACKAGE MATERIALS INFORMATION TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ TRF7960RHBR TRF7960RHBT TRF7961RHBR TRF7961RHBT QFN QFN QFN QFN RHB RHB RHB RHB 32 32 32 32 3000 250 3000 250 Reel Diameter

(mm) 330.0 180.0 330.0 180.0 Reel Width W1 (mm) A0

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1 Quadrant 12.4 12.4 12.4 12.4 5.3 5.3 5.3 5.3 5.3 5.3 5.3 5.3 1.5 1.5 1.5 1.5 8.0 8.0 8.0 8.0 12.0 12.0 12.0 12.0 Q2 Q2 Q2 Q2 Pack Materials-Page 1 www.ti.com 14-Jul-2012 PACKAGE MATERIALS INFORMATION

*All dimensions are nominal Device Package Type Package Drawing Pins TRF7960RHBR TRF7960RHBT TRF7961RHBR TRF7961RHBT QFN QFN QFN QFN RHB RHB RHB RHB 32 32 32 32 SPQ 3000 250 3000 250 Length (mm) Width (mm) Height (mm) 367.0 210.0 367.0 210.0 367.0 185.0 367.0 185.0 35.0 35.0 35.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. 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Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity Applications Automotive and Transportation www.ti.com/automotive Communications and Telecom www.ti.com/communications Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Video and Imaging www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/omap www.ti.com/wirelessconnectivity www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video TI E2E Community e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2012, Texas Instruments Incorporated Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver.

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Radiation Exposure Statement:

The product is a low power device and its output power is lower than FCC SAR exemption level. This module can be used with Getac PDA: PS336. This device is intended only for OEM integrators under the following conditions:

1) The transmitter module may not be co-located with any other transmitter or antenna. The co-transmitting with other radio will need a separate evaluation. 2) Module approval valid only when this module is installed in the tested host Getac PDA: PS336. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed IMPORTANT NOTE: In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. End Product Labeling The final end product must be labeled in a visible area with the following: Contains FCC ID: QYLPS336R. The grantee's FCC ID can be used only when all FCC compliance requirements are met. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.