FCC ID: 2AVOJ-COAST20 Bluetooth Earphone

 

IRONPEAK COAST User Manual (English) Charging Check out the charging ports on the Left leg Red LED light will on when charging Charge the product for 1.5 hour for full charge before use until blue light is on, which means the device is charged to the full You will hear the beep when it reaches critical battery level Find Power Button on the Right leg and press and hold button for 2 sec to power on When the power is on,BLUE lights blink the Bluetooth pairing begins. Find IronPeak Coast Bluetooth option on your smart device and pair it When the pairing is completed you will see the Blue light and hear the beep Enjoy your outdoor activity with IronPeak Button Control Instruction Power Power Pairing on on Calls Music/Audio track TROUBLESHOOTING How to TURN ON: Press and hold the power button for 2 secs until you hear the beep and the Blue light is How to TURN OFF : Press and hold the power button for 2 secs until you hear the beep and the Red light is Taking incoming call : Press the power button and hear the beep that the call is now connected Ending call : Press the power button and hear the beep that the call has ended Play and Pause : Press the power button to play or pause the audio Volume control : Press the volume up/down buttons until you reach the desired volume Skip Track/ Previous Track : Press and hold the volume up/ down button for 2 sec until you find the desired PLEASE CONTACT OUR SUPPORT TEAM at info@ironpeak.co.kr LENS REPLACING INSTRUCTIONS NOTE: PLEASE VISIT OUR YOUTUBE CHANNEL FOR MORE DETAILED INSTRUCTIONS. NOTE: THE CORNER OF THE LENS WITH ACUTE/SHARP ANGEL IS TOWARD THE CENTER OF THE GLASSES NOTE: TOO MUCH FORCE MAY DAMAGE THE PRODUCT. PLEASE BE CAREFUL WARNING: To replace lenses, the size of the lenses must be identical to the default lenses of the Product(s). Failure to comply may damage the Product(s) Determine the right lens and the left lens. Failure to do so may damage the Product(s) (See the diagram below) 1. TO REMOVE LENSES 2. TO INSERT LENSES 1) Gently hold the frame with your fingers on outside, and your thumbs on inside of the lens. 2_Gentl press the lens outward while holding the frame with your fingers 1) Insert the lens from the inside of the frame. 2) Place the upper nose side edge of the lens in to the upper nose side grove of the frame, and gently press on the center of the lens. 3) Continue pressing around the edge of the lens until the lens is completely inserted. Speaker : Micro speaker Frame Material : TR90, Rubber Lens : NXT Sun lens Buttons : Tactile buttons Bluetooth Wireless Range : 40 meters Compatibility : Any Device (smartphone, computer, tablet, etc.) has Bluetooth and communication functions built-in Battery : Lithium-Polymer 150mAh * 2 / 3.7V Playtime : 10 hours Charging time : 1.5 hour Charging metod : Micro-5pin USB cable Weight : 53g WARNING SAFETY GUIDELINES Please read the Safety Guidelines below prior to using the Product(s). Failure to follow (or violating) these instructions may be dangerous, and shall void IronPeak Warranty

*WARNING!

1.PRODUCT(S) STORAGE AND MAINTENANCE GUIDELINES Please read the Product(s) storage and maintenance guidelines carefully. The Product(s) ma present a risk of fire, chemical burn, or explosion if mistreated. 1-1 DAMAGE 1) DO NOT impact the Product(s). This may cause damage to the Product(s) that could result in malfunctioning. Such examples include, but are not limited to:

2) DO NOT scratch or stab the Product(s) with sharp objects. 3) DO NOT drop the Product(s) 4) DO NOT apply unusual stress to the Product(s) 1-2 REPLACEMENT/MODIFICATION or electric shock. Such examples include, but are not limited to:

2) DO NOT attempt to replace the built-in-battery. 3) DO NOT attempt to repair/disassemble the Product(s) 1-3 MOISTURE/TEMPERATURE 1) DO NOT attempt to replace or modify the Product(s). This may cause short circuits that could result in a fire, 1) DO NOT expose the Product(s)under extreme conditions, Such examples include, but are not limited to:

Keep the Product(s) between 0 celcius -45c (32*F - 113 *F). Product(s) may not work temporarily in hot or cold environment even when the battery is fully charged. Keep the Product(s) away from extreme heat such a s microwave, stove, etc. 2) DO NOT keep the Product(s) under direct sunlight 3) DO NOT keep the Product(s) in motor vehicles or enclosed areas under extreme temperatures. 4) DO NOT keep/use/submerge the Product(s) in water. Such examples include but are not limited to :

5) Keep the Product(s) away from rain, moisture, or other liquid. The Product(s) are sweat resistant, but are not waterproof 6) DO NOT keep or use the Product(s) in humid areas. 7) DO NOT keep or use the Product(s) while swimming or taking a shower. 1-4 BATTERY/CHARGING 1) The Product(s) must be charged with the provided charging cable. 2) The Product(s) must be charged under supervision 3) If the Product(s) are left unused for a long period, please recharge fully before using the Product(s) again. 4) DO NOT charge the Product(s) IMMEDIATELY after physical activities. Sweat inside the charging port may cause circuits burning while charging. Keep the charging port dry before connecting to the charger. 5) DO NOT touch the Product(s) with wet hands while charging 1-5 GENERAL 1) Clean the Product(s) only with a soft dry cloth. 2) Dispose the Product(s) according to local standards and regulations. 3) Keep the Product(s) out of reach from children / pets. The Product(s) contain the parts that may be hazardous to children/pets 2 PRODUCT(S) USAGE GUIDELINES Please read the Product(s) usage guidelines carefully. Inappropriate usage of the Product(s) may cause personal injury or damage to the Product(s). 2-1 ATTENTION 1) Usage of the Product(s) will impair your ability to fully hear, or see. Be cautious while engaging in any activity that requires your full attention. Such examples include, but are not limited to :

2) DO NOT wear while driving if the usage of the product becomes distraction 3) Product(s) impair peripheral vision. Usage of colored lenses at night may be inappropriate. 2-2 HEALTH may affect your vision the Product(s). limited to:

2-3 GENERAL 1) DO NOT use sharpened/destroyed/damaged parts or the Product(s) as it may pressent a danger. Please contact IronPeak for support. Listening with the Product(s) at high volume may affect your hearing, which may result in permanent damage to your hearing without any noticeable discomfort. 2) DO NOT use the Product(s) for direct viewing of the sun or for protection against artificial light sources as it 3) If you experience discomfort, headache, dizziness, or ringing in your ears, IMMEDIATELY discontinue using 4) Under any medical conditions, please consult your doctor prior to usage. Such examples include, but are not 5) Patients with any electrical medical devices such as pacemaker and hearing aid. 6) Patients with cupulolithiasis. 1) If the Product(s) overheats, IMMEDIATELY discontinue using the Product(s). 2) DO NOT use the Product(s) for protective purpose. Product(s) are not designed to protect wear from all injury in the event of impact with hard objects. Such examples include, but are not limited to:

3) DO NOT use the Product(s) to protect eyes. 4) DO NOT use the Product(s) for industrial protection equipment. 5) DO NOT use the Product(s) improperly other than its original purpose. Such examples include, but are not liimted to:

6) DO NOT poke eyes, ears, or nose with the Product(s) 7) DO NOT put the Product(s) in mmouth. 8) The Product(s) are not intended for any use as industrial equipment. 9) Observe all signs and instructions that require an electrical device or RF radio product to be switched off in designated areas such as hospitals, explosive atmospheres, or airplanes. 10) DO NOT let children/pets to use the Product(s). The Product(s) contain the parts that may be hazardous to children/pets VISIT OUR CHANNEL Search IronPeak on Youtube for instructional videos Please visit www. IronPeakinc.com for more information CERTIFICATION This device complies with part 15 of the FCC Rules. Operation is subject to the following two condicitons (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: Changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment FCC Information to User This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is con-nected. Consult the dealer or an experienced radio/TV technician for help. Caution Modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment. FCC Compliance Information : This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation

 

 

 

 

 

 

 

 

 

 

FCC ID: 2AVOJ-COAST20 SAMPLE LABEL & LOCATION GP International Corp. M/N : Ironpeak Coast 2.0 FCC ID: 2AVOJ-COAST20 Copyright 2020, KRL Co., Ltd.

 

 

GP International Corp. Federal Communications Commission Authorization and Evaluation Division 1435 Oakland Mills Road Columbia, MD 21046 Date: 2020-02-06 SUBJECT: FCC Application for (FCC ID: 2AVOJ-COAST20) To Whom It May Concern:

We, the undersigned, hereby authorize David Zhang in Vista Laboratories, Inc. on our behalf, to apply to the Federal Communications Commission on our equipment. Any and all acts carried out by Vista Laboratories, Inc. on our behalf shall have the same effect as acts of our own. This is to advise that we are in full compliance with the Anti- Drug Abuse Act. We, the applicant, are not subject to a denial of federal benefits pursuant to Section 5301 of the Anti-Drug Act of 1988, 21 USC853a, and no party to the application is subject to a denial of federal benefits pursuant to that section. Sincerely,

(Must be signed by the person that is listed on the FCC Website) Clients signature:

Clients name & title: Min Jun, LEE / Manager Contact information / address: 82-70-4210-1038/ Ground floor, 190, Goejeong-ro, Seo-gu, Daejeon Date: 04/17/2018 VCB_F-01: Operating Procedures Form FCC Authorization v02 Page 1 of 1

 

 

 

 

 

 

Permanent Permanent*

Permanent Permanent Permanent Permanent*

GP International Corp. Federal Communications Commission Authorization and Evaluation Division Confidentiality Request regarding application for certification of FCC ID: 2AVOJ-

COAST20 Pursuant to Sections 0.457 and 0.459 of the Commissions Rules, we hereby request confidential treatment of information accompanying this application as outlined below:

Type of Confidentiality Requested Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term

*Requires further justification before permanent confidentiality will be allowed. The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these materials may be harmful to the applicant and provide unjustified benefits to its competitors. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

Pursuant to DA04-1705 June 15, 2004 of the Commissions public notice, we also request temporary confidential treatment of information accompanying this application as outlined below for an initial period of 180 days. Sincerely, Exhibit Type Block Diagrams External Photos Internal Photos Operation Description Parts List/BOM Schematics Test Setup Photos User manual Clients signature:

Clients name & title: Min Jun, LEE / Manager Contact information / address: +82-70-4210-1038 / Ground floor, 190, Goejeong-ro, Seo-

gu, Daejeon Date: 04/17/2018 VCB_F-01: Operating Procedures Form FCC Confidentiality v03 Page 1 of 1

 

 

Features 80MHz RISC MCU and 80MIPS Kalimba DSP Internal ROM, serial flash memory and EEPROM interfaces Stereo codec with 2 microphone inputs Radio includes integrated balun 5-band fully configurable EQ CSR's latest CVC technology for narrowband and wideband voice connections including wind noise reduction Wideband speech supported by HFP v1.6 profile and mSBC codec Voice recognition support for answering a call, enables true hands-free use Multipoint HFP connection to 2 phones for voice Multipoint A2DP connection enables a headset

(A2DP) connection to 2 A2DP source devices for music playback Secure simple pairing, CSR's proximity pairing and CSR's proximity connection Audio interfaces: IS and PCM Serial interfaces: UART, USB 2.0 (full-speed), IC and SPI aptX, SBC, MP3 and AAC decoder support Wired audio support (USB and analogue) Support for smartphone/tablet applications Integrated dual switch-mode regulators, linear regulators and battery charger External crystal load capacitors not required for typical crystals 3 LED outputs 68ball VFBGA 5.5 x 5.5 x 1mm 0.5mm pitch Green (RoHS compliant and no antimony or halogenated flame retardants) General Description BlueCore CSR8645 BGA is a product from CSR's Connectivity Centre. It is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems including basic rate, EDR to 3Mbps and Bluetooth low energy. The integrated peripherals reduce the number of external components required, including no requirement for external codec, battery charger, SMPS, LDOs, balun or external program memory, ensuring minimum production costs. The battery charger architecture enables the CSR8645 BGA to independently operate from the charger supply, ensuring dependable operation for all battery conditions. BlueCore CSR8645 BGA CSR8645 Stereo ROM Solution with aptX 2-mic CVC Audio Enhancement Fully Qualified Single-chip Bluetooth v4.0 System Production Information CSR8645A04 Issue 6 XTAL BT_RF Baseband I /O PIO 2.4GHz Radio

Balun ROM RAM MCU Kalimba DSP Serial Flash /

EEPROM SPI/ I2C UART/USB Audio In / Out Debug SPI C S R 8 6 4 5 B G A D a t a S h e e t Applications Stereo headsets Wired stereo headsets and headphones Portable stereo speakers The enhanced Kalimba DSP coprocessor with 80MIPS supports enhanced audio and DSP applications. The integrated audio codec supports 2 channels of ADC, 2 digital microphone inputs and stereo output, as well as a variety of audio standards. See CSR Glossary at www.csrsupport.com. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 1 of 114 CS-218182-DSP6 www.csr.com http://www.Datasheet4U.com Ordering Information Device CSR8645 Stereo ROM Solution with aptX Note:

Package Type Size Shipment Method Order Number VFBGA68ball 5.5 x 5.5 x 1mm

(Pb free) 0.5mm pitch Tape and reel CSR8645A04IBBCR CSR8645 BGA is a ROM-based device where the product code has the form CSR8645Axx. Axx is the specific ROM-variant, A04 is the ROM-variant for CSR8645 Stereo ROM Solution with aptX. Minimum order quantity is 2kpcs taped and reeled. Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative. Contacts General information Information on this product Customer support for this product Details of compliance and standards Help with this document www.csr.com Sales@csr.com www.csrsupport.com Product.compliance@csr.com Comments@csr.com CSR8645 Stereo ROM Solution with aptX Development Kit Ordering Information Description Order Number CSR8645 Stereo ROM Solution with aptX Audio Development Kit DK-8645-10064-1A C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 2 of 114 CS-218182-DSP6 www.csr.com Device Details Bluetooth low energy Dual-mode Bluetooth low energy radio Support for Bluetooth basic rate / EDR and low energy connections 3 Bluetooth low energy connections at the same time as basic rate A2DP Bluetooth Radio On-chip balun (50 impedance) No production trimming of external components Bluetooth v4.0 specification compliant Bluetooth Transmitter 9dBm (typical) RF transmit power with level control Class 1, Class 2 and Class 3 support, no external PA or TX/RX switch required Bluetooth Receiver

-92dBm (typical) /4 DQPSK receiver sensitivity and -82dBm (typical) 8DPSK receiver sensitivity Integrated channel filters Digital demodulator for improved sensitivity and co-

channel rejection Real-time digitised RSSI available to application Fast AGC for enhanced dynamic range Channel classification for AFH Physical Interfaces UART interface for debug USB 2.0 (full-speed) interface for audio and charger enumeration 1-bit SPI flash memory interface SPI interface for debug and programming IC interface for EEPROM Up to 22 general purpose PIOs with 3 extra open-

drain PIOs available when LED not used PCM and IS interfaces 3 LED drivers (includes RGB) with PWM flasher independent of MCU Integrated Power Control and Regulation Automatic power switching to charger when present 2 high-efficiency switch-mode regulators with 1.8V and 1.35V outputs direct from battery supply 3.3V linear regulator for USB supply Low-voltage linear regulator for internal digital circuits Low-voltage linear regulator for internal analogue circuits Power-on-reset detects low supply voltage Power management includes digital shutdown and wake-up commands for ultra-low power modes Bluetooth Synthesiser Fully integrated synthesiser requires no external VCO, varactor diode, resonator or loop filter Compatible with crystals 16MHz to 32MHz Battery Charger Kalimba DSP Enhanced Kalimba DSP coprocessor, 80MIPS, 24bit fixed point core 2 single-cycle MACs; 24 x 24-bit multiply and 56-bit accumulator 32-bit instruction word, dual 24-bit data memory 6K x 32-bit program RAM including 1K instruction cache for executing out of internal ROM 16K x 24-bit + 16K x 24-bit 2-bank data RAM Audio Interfaces Audio codec with 2 high-quality dedicated ADCs Microphone bias generator and up to 2 analogue microphone inputs 2 digital microphone inputs (MEMS) Enhanced side-tone gain control Supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1, 48 and 96kHz (DAC only) Auxiliary Features Package Option Crystal oscillator with built-in digital trimming 68ball VFBGA 5.5 x 5.5 x 1mm 0.5mm pitch Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Lithium ion / Lithium polymer battery charger Instant-on function automatically selects the power supply between battery and USB, which enables operation even if the battery is fully discharged Fast charging support up to 200mA with no external components Higher charge currents using external pass device Supports USB charger detection Support for thermistor protection of battery pack Support to enable end product design to PSE law:

Design to JIS-C 8712/8714 (batteries) Testing based on IEEE 1725 Internal ROM Baseband and Software Memory protection unit supporting accelerated VM 56KB internal RAM, enables full-speed data transfer, mixed voice/data and full piconet support Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping Transcoders for A-law, -law and linear voice from host and A-law, -law and CVSD voice over air Page 3 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t CSR8645 Stereo ROM Solution with aptX Details CSR8600 ROM Series Configuration Tool Configures the CSR8645 stereo ROM solution with aptX software features:

Bluetooth v4.0 specification features Reconnection policies, e.g. reconnect on power-on Audio features, including default volumes Button events: configuring button presses and durations for certain events, e.g. double press on PIO for last number redial LED indications for states, e.g. headset connected, and events, power on etc. Indication tones for events and ringtones HFP v1.6 supported features Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc. Advanced Multipoint settings CSR8645 Stereo ROM Solution with aptX Development Kit CSR8645 stereo ROM solution with aptX demonstrator board (DB-8645-10067-1A) Interface adapters and cables are available Works in conjunction with the CSR8600 ROM Series Configuration Tool and other supporting utilities C S R 8 6 4 5 B G A D a t a S h e e t Bluetooth Profiles Bluetooth v4.0 specification support HFP v1.6 wideband speech (HD voice ready) HSP v1.2 A2DP v1.2 AVRCP v1.4 Support for smartphone applications (apps) Improved Audio Quality CSRs latest 2-mic CVC audio enhancements for narrowband and wideband connections including:

2-mic far-end audio enhancements Near-end audio enhancements (noise suppression and AEQ) Wind noise reduction Packet loss concealment Bit error concealment Automatic gain control and automatic volume control Frequency expansion for improved speech intelligibility mSBC codec support for wideband speech Music Enhancements Configurable 5-band EQ for music playback (rock, pop, classical, jazz, dance etc) aptX, SBC, MP3, AAC and Faststream decoder Stereo widening (S3D) Volume Boost Additional Functionality Support for voice recognition Support for multi-language programmable audio prompts CSR's proximity pairing and CSR's proximity connection Multipoint support for HFP connection to 2 handsets for voice Multipoint support for A2DP connection to 2 A2DP sources for music playback Talk-time extension Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 4 of 114 CS-218182-DSP6 www.csr.com Functional Block Diagram SPI_DEBUG I2C PIO Serial Flash UART R G B USB XTAL AIO[0]

SPI

(Debug) I2C/SPI Master

/Slave Serial Flash Interface UART 4Mbps LED PWM Control and Output PIO Port USB v2.0 Full-speed 3.3V Clock Generation AUX ADC DMA ports Bluetooth Modem s t r o p A M D s t r o p A M D Memory Management Unit Bluetooth Baseband Audio Interface PIO Port System RAM ROM PM DM1 DM2 High-quality ADC High-quality ADC High-quality DAC High-quality DAC Voltage / Temperature Monitor 80MHz DSP 80MHz MCU VM Accelerator

(MPU) Digital Microphone Inputs

(MEMS) PCM1 / I2S PMU Interface and BIST Engine 0.85V to 1.2V Low-voltage VDD_DIG Linear Regulator SENSE 1.35V 1.35V Low-voltage VDD_ANA Low-voltage VDD_AUX Linear Regulator Linear Regulator 1.8V Switch-

mode 1.35V Switch-

mode Regulator Regulator SENSE SENSE SENSE SENSE 2 x D g i i t a l I M C s D g i i t a l A u d o i I V R E G N _ D G I I V D D _ D G _ M E M V D D _ A N A _ R A D O I V D D _ A U X V D D _ A U X _ 1 V 8 L X L _ 1 V 8 L X _ 1 V 3 5 S M P S _ 1 V 8 _ S E N S E S M P S _ 1 V 3 5 _ S E N S E 3 V 3 _ U S B TX RX Bluetooth Radio and Balun BT_RF MIC_AN MIC_AP MIC_BN MIC_BP SPKR_LN SPKR_LP SPKR_RN SPKR_RP VDD_AUDIO VDD_AUDIO_DRV MIC Bias MIC_BIAS Switch VBAT SENSE VBAT_SENSE Bypass LDO Li-ion Charger CHG_EXT VCHG C S R 8 6 4 5 B G A D a t a S h e e t 3

. 4

. 0 4 4 7 0 0 0

W T

G Page 5 of 114 CS-218182-DSP6 www.csr.com Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Document History Revision Date Change Reason 24 AUG 11 Internal publication of this document. 13 SEP 11 Original publication of this document. 28 SEP 11 Editorial updates. 17 JAN 12 Bluetooth v4.0 specfication added. Pre-production status. Power consumption figures added. Package Dimensions updated and pin configuration drawing removed. Editorial updates. 02 FEB 12 Internal release. 06 FEB 12 Production Information added. If you have any comments about this document, email comments@csr.com giving number, title and section with your feedback. 1 2 3 4 5 6 C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 6 of 114 CS-218182-DSP6 www.csr.com Status Information The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:

Advance Information Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-production Information Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. All electrical specifications may be changed by CSR without notice. Production Information Production Data Sheets supersede all previous document versions. Life Support Policy and Use in Safety-critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. CSR Green Semiconductor Products and RoHS Compliance CSR8645 BGA devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). CSR8645 BGA devices are also free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products. Trademarks, Patents and Licences Unless otherwise stated, words and logos marked with or are trademarks registered or owned by CSR plc or its affiliates. Bluetooth and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. Refer to www.csrsupport.com for compliance and conformance to standards information. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 7 of 114 CS-218182-DSP6 www.csr.com Contents 2.1.1 2.2.1 2.2.2 2.3.1 2.3.2 Ordering Information ....................................................................................................................................... 2 Contacts ................................................................................................................................................. 2 CSR8645 Stereo ROM Solution with aptX Development Kit Ordering Information ............................... 2 Device Details ................................................................................................................................................. 3 CSR8645 Stereo ROM Solution with aptX Details ......................................................................................... 4 Functional Block Diagram .............................................................................................................................. 5 Package Information ..................................................................................................................................... 14 1.1 Pinout Diagram .................................................................................................................................... 14 1.2 Device Terminal Functions .................................................................................................................. 15 1.3 Package Dimensions ........................................................................................................................... 21 1.4 PCB Design and Assembly Considerations ......................................................................................... 22 1.5 Typical Solder Reflow Profile ............................................................................................................... 22 Bluetooth Modem .......................................................................................................................................... 23 2.1 RF Ports ............................................................................................................................................... 23 BT_RF .................................................................................................................................... 23 2.2 RF Receiver ......................................................................................................................................... 23 Low Noise Amplifier ............................................................................................................... 23 RSSI Analogue to Digital Converter ....................................................................................... 23 2.3 RF Transmitter ..................................................................................................................................... 24 IQ Modulator .......................................................................................................................... 24 Power Amplifier ...................................................................................................................... 24 2.4 Bluetooth Radio Synthesiser ............................................................................................................... 24 2.5 Baseband ............................................................................................................................................. 24 Burst Mode Controller ............................................................................................................ 24 Physical Layer Hardware Engine ........................................................................................... 24 Clock Generation .......................................................................................................................................... 25 3.1 Clock Architecture ................................................................................................................................ 25 3.2 Input Frequencies and PS Key Settings .............................................................................................. 25 3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT ....................................................................................... 25 Crystal Calibration .................................................................................................................. 25 Bluetooth Stack Microcontroller .................................................................................................................... 27 4.1 VM Accelerator .................................................................................................................................... 27 Kalimba DSP ................................................................................................................................................ 28 Memory Interface and Management ............................................................................................................. 29 6.1 Memory Management Unit .................................................................................................................. 29 6.2 System RAM ........................................................................................................................................ 29 6.3 Kalimba DSP RAM .............................................................................................................................. 29 6.4 Internal ROM ....................................................................................................................................... 29 6.5 Serial Flash Interface ........................................................................................................................... 29 Serial Interfaces ............................................................................................................................................ 30 7.1 USB Interface ...................................................................................................................................... 30 7.2 UART Interface .................................................................................................................................... 30 7.3 Programming and Debug Interface ...................................................................................................... 32 7.3.1 Multi-slave Operation ............................................................................................................. 32 2.5.1 2.5.2 3.3.1 1 2 3 4 5 6 7 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 8 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 8 9 10 7.4 IC EEPROM Interface ........................................................................................................................ 33 Interfaces ...................................................................................................................................................... 34 8.1 Programmable I/O Ports, PIO .............................................................................................................. 34 8.2 Analogue I/O Ports, AIO ...................................................................................................................... 34 8.3 LED Drivers ......................................................................................................................................... 35 Audio Interface .............................................................................................................................................. 36 9.1 Audio Input and Output ........................................................................................................................ 37 9.2 Audio Codec Interface ......................................................................................................................... 37 Audio Codec Block Diagram .................................................................................................. 38 9.2.1 ADC ........................................................................................................................................ 38 9.2.2 ADC Sample Rate Selection .................................................................................................. 38 9.2.3 ADC Audio Input Gain ............................................................................................................ 39 9.2.4 ADC Pre-amplifier and ADC Analogue Gain .......................................................................... 39 9.2.5 ADC Digital Gain .................................................................................................................... 39 9.2.6 ADC Digital IIR Filter .............................................................................................................. 40 9.2.7 DAC ........................................................................................................................................ 40 9.2.8 DAC Sample Rate Selection .................................................................................................. 40 9.2.9 9.2.10 DAC Digital Gain .................................................................................................................... 40 9.2.11 DAC Analogue Gain ............................................................................................................... 41 9.2.12 DAC Digital FIR Filter ............................................................................................................. 41 9.2.13 Microphone Input ................................................................................................................... 42 9.2.14 Digital Microphone Inputs ....................................................................................................... 43 9.2.15 Line Input ............................................................................................................................... 43 9.2.16 Output Stage .......................................................................................................................... 44 9.2.17 Mono Operation ..................................................................................................................... 44 9.2.18 Side Tone ............................................................................................................................... 44 9.2.19 Integrated Digital IIR Filter ..................................................................................................... 46 9.3 PCM1 Interface .................................................................................................................................... 47 PCM Interface Master/Slave .................................................................................................. 48 9.3.1 Long Frame Sync ................................................................................................................... 48 9.3.2 9.3.3 Short Frame Sync .................................................................................................................. 49 9.3.4 Multi-slot Operation ................................................................................................................ 49 9.3.5 GCI Interface .......................................................................................................................... 50 Slots and Sample Formats ..................................................................................................... 50 9.3.6 Additional Features ................................................................................................................ 51 9.3.7 9.3.8 PCM Timing Information ........................................................................................................ 52 9.3.9 PCM_CLK and PCM_SYNC Generation ................................................................................ 55 9.3.10 PCM Configuration ................................................................................................................. 56 9.4 Digital Audio Interface (IS) .................................................................................................................. 56 Power Control and Regulation ...................................................................................................................... 60 10.1 1.8V Switch-mode Regulator ............................................................................................................... 63 10.2 1.35V Switch-mode Regulator ............................................................................................................. 63 10.3 1.8V and 1.35V Switch-mode Regulators Combined .......................................................................... 64 10.4 Bypass LDO Linear Regulator ............................................................................................................. 65 10.5 Low-voltage VDD_DIG Linear Regulator ............................................................................................. 66 10.6 Low-voltage VDD_AUX Linear Regulator ............................................................................................ 66 10.7 Low-voltage VDD_ANA Linear Regulator ............................................................................................ 66 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 9 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 11 12 13 14 10.8 Voltage Regulator Enable .................................................................................................................... 66 10.9 External Regulators and Power Sequencing ....................................................................................... 66 10.10Reset, RST# ........................................................................................................................................ 67 10.10.1 Digital Pin States on Reset .................................................................................................... 67 10.10.2 Status After Reset .................................................................................................................. 68 10.11Automatic Reset Protection ................................................................................................................. 68 Battery Charger ............................................................................................................................................ 69 11.1 Battery Charger Hardware Operating Modes ...................................................................................... 69 11.1.1 Disabled Mode ....................................................................................................................... 70 11.1.2 Trickle Charge Mode .............................................................................................................. 70 11.1.3 Fast Charge Mode ................................................................................................................. 70 11.1.4 Standby Mode ........................................................................................................................ 70 11.1.5 Error Mode ............................................................................................................................. 71 11.2 Battery Charger Trimming and Calibration .......................................................................................... 71 11.3 VM Battery Charger Control ................................................................................................................ 71 11.4 Battery Charger Firmware and PS Keys .............................................................................................. 71 11.5 External Mode ...................................................................................................................................... 71 Example Application Schematic ................................................................................................................... 73 Example Application Using Different Power Supply Configurations ............................................................. 74 Electrical Characteristics .............................................................................................................................. 77 14.1 Absolute Maximum Ratings ................................................................................................................. 77 14.2 Recommended Operating Conditions .................................................................................................. 78 14.3 Input/Output Terminal Characteristics ................................................................................................. 79 14.3.1 Regulators: Available For External Use ................................................................................. 79 14.3.2 Regulators: For Internal Use Only .......................................................................................... 81 14.3.3 Regulator Enable ................................................................................................................... 82 14.3.4 Battery Charger ...................................................................................................................... 82 14.3.5 USB ........................................................................................................................................ 84 14.3.6 Clocks .................................................................................................................................... 84 14.3.7 Stereo Codec: Analogue to Digital Converter ........................................................................ 85 14.3.8 Stereo Codec: Digital to Analogue Converter ........................................................................ 86 14.3.9 Digital ..................................................................................................................................... 87 14.3.10 LED Driver Pads .................................................................................................................... 88 14.3.11 Auxiliary ADC ......................................................................................................................... 88 14.3.12 Auxiliary DAC ......................................................................................................................... 89 14.4 ESD Protection .................................................................................................................................... 90 14.4.1 USB Electrostatic Discharge Immunity .................................................................................. 90 15 Power Consumption ..................................................................................................................................... 92 16 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 95 Software ........................................................................................................................................................ 97 17 17.1 CSR8645 Stereo ROM Solution with aptX .......................................................................................... 97 17.1.1 Advanced Multipoint Support ................................................................................................. 98 17.1.2 A2DP Multipoint Support ........................................................................................................ 98 17.1.3 Wired Audio Mode .................................................................................................................. 98 17.1.4 USB Modes Including USB Audio Mode ................................................................................ 99 17.1.5 Smartphone Applications (Apps) ............................................................................................ 99 17.1.6 Programmable Audio Prompts ............................................................................................... 99 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 10 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 17.1.7 CSRs Intelligent Power Management ................................................................................. 100 17.1.8 Proximity Pairing .................................................................................................................. 101 17.1.9 Proximity Connection ........................................................................................................... 101 17.2 6th Generation 2-mic CVC Audio Enhancements .............................................................................. 101 17.2.1 Wind Noise Reduction .......................................................................................................... 102 17.2.2 Dual-microphone Signal Separation .................................................................................... 102 17.2.3 Noise Suppression ............................................................................................................... 102 17.2.4 Acoustic Echo Cancellation .................................................................................................. 103 17.2.5 Comfort Noise Generator ..................................................................................................... 103 17.2.6 Equalisation .......................................................................................................................... 103 17.2.7 Automatic Gain Control ........................................................................................................ 103 17.2.8 Packet Loss Concealment ................................................................................................... 103 17.2.9 Adaptive Equalisation ........................................................................................................... 103 17.2.10 Auxiliary Stream Mix ............................................................................................................ 104 17.2.11 Clipper .................................................................................................................................. 104 17.2.12 Noise Dependent Volume Control ........................................................................................ 104 17.2.13 Fixed Gains .......................................................................................................................... 104 17.2.14 Frequency Enhanced Speech Intelligibility .......................................................................... 104 17.3 Music Enhancements ........................................................................................................................ 104 17.3.1 Audio Decoders .................................................................................................................... 104 17.3.2 aptX Decoder ....................................................................................................................... 104 17.3.3 Configurable EQ ................................................................................................................... 105 17.3.4 Stereo Widening (S3D) ........................................................................................................ 105 17.3.5 Volume Boost ....................................................................................................................... 106 17.4 CSR8645 Stereo ROM Solution with aptX Development Kit ............................................................. 106 Tape and Reel Information ......................................................................................................................... 107 18.1 Tape Orientation ................................................................................................................................ 107 18.2 Tape Dimensions ............................................................................................................................... 107 18.3 Reel Information ................................................................................................................................ 108 18.4 Moisture Sensitivity Level .................................................................................................................. 108 19 Document References ................................................................................................................................ 109 Terms and Definitions .......................................................................................................................................... 110 18 List of Figures Figure 1.1 Figure 2.1 Figure 3.1 Figure 5.1 Figure 6.1 Figure 7.1 Figure 7.2 Figure 8.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Device Pinout .................................................................................................................................. 14 Simplified Circuit BT_RF ................................................................................................................. 23 Clock Architecture ........................................................................................................................... 25 Kalimba DSP Interface to Internal Functions .................................................................................. 28 Serial Flash Interface ...................................................................................................................... 29 Universal Asynchronous Receiver .................................................................................................. 31 Example IC EEPROM Connection ................................................................................................. 33 LED Equivalent Circuit .................................................................................................................... 35 Audio Interface ................................................................................................................................ 36 Audio Codec Input and Output Stages ............................................................................................ 38 Audio Input Gain ............................................................................................................................. 39 Microphone Biasing ......................................................................................................................... 42 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 11 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Differential Input .............................................................................................................................. 43 Figure 9.5 Single-ended Input .......................................................................................................................... 43 Figure 9.6 Speaker Output ............................................................................................................................... 44 Figure 9.7 Side Tone ........................................................................................................................................ 45 Figure 9.8 Figure 9.9 PCM Interface Master ..................................................................................................................... 48 Figure 9.10 PCM Interface Slave ....................................................................................................................... 48 Figure 9.11 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 49 Figure 9.12 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 49 Figure 9.13 Multi-slot Operation with 2 Slots and 8-bit Companded Samples ................................................... 50 Figure 9.14 GCI Interface ................................................................................................................................... 50 Figure 9.15 16-bit Slot Length and Sample Formats .......................................................................................... 51 Figure 9.16 PCM Master Timing Long Frame Sync ........................................................................................... 53 Figure 9.17 PCM Master Timing Short Frame Sync .......................................................................................... 53 Figure 9.18 PCM Slave Timing Long Frame Sync ............................................................................................. 55 Figure 9.19 PCM Slave Timing Short Frame Sync ............................................................................................ 55 Figure 9.20 Digital Audio Interface Modes ......................................................................................................... 57 Figure 9.21 Digital Audio Interface Slave Timing ............................................................................................... 58 Figure 9.22 Digital Audio Interface Master Timing ............................................................................................. 59 1.80V and 1.35V Dual-supply Switch-mode System Configuration ................................................ 61 Figure 10.1 1.80V Parallel-supply Switch-mode System Configuration ............................................................. 62 Figure 10.2 Figure 10.3 1.8V Switch-mode Regulator Output Configuration ........................................................................ 63 1.35V Switch-mode Regulator Output Configuration ...................................................................... 64 Figure 10.4 Figure 10.5 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration ...................................... 65 Figure 11.1 Battery Charger Mode-to-Mode Transition Diagram ....................................................................... 70 Figure 11.2 Battery Charger External Mode Typical Configuration .................................................................... 72 Figure 13.1 External 1.8V Supply Example Application ..................................................................................... 74 Figure 13.2 External 3.3V Supply Example Application ..................................................................................... 75 Figure 13.3 USB Audio Dongle Example Application ......................................................................................... 76 Figure 17.1 Programmable Audio Prompts in External SPI Flash ................................................................... 100 Figure 17.2 Programmable Audio Prompts in External IC EEPROM .............................................................. 100 Figure 17.3 2-mic CVC Block Diagram ............................................................................................................ 102 Figure 17.4 Configurable EQ GUI with Drag Points ......................................................................................... 105 Figure 17.5 Volume Boost GUI with Drag Points ............................................................................................. 106 Tape Orientation ........................................................................................................................... 107 Figure 18.1 Figure 18.2 Tape Dimensions .......................................................................................................................... 107 Figure 18.3 Reel Dimensions ........................................................................................................................... 108 List of Tables Table 7.1 Table 7.2 Table 7.3 Table 8.1 Table 9.1 Table 9.2 Table 9.3 Table 9.4 PS Keys for UART/PIO Multiplexing ................................................................................................ 30 Possible UART Settings ................................................................................................................... 31 Standard Baud Rates ....................................................................................................................... 32 Alternative PIO Functions ................................................................................................................. 34 Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface ............................. 36 ADC Audio Input Gain Rate ............................................................................................................. 40 DAC Digital Gain Rate Selection ...................................................................................................... 41 DAC Analogue Gain Rate Selection ................................................................................................. 41 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 12 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Table 9.5 Side Tone Gain ................................................................................................................................ 45 Table 9.6 PCM Master Timing .......................................................................................................................... 52 Table 9.7 PCM Slave Timing ............................................................................................................................ 54 Table 9.8 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 56 Table 9.9 Digital Audio Interface Slave Timing ................................................................................................ 57 Table 9.10 IS Slave Mode Timing ..................................................................................................................... 58 Table 9.11 Digital Audio Interface Master Timing .............................................................................................. 59 Table 9.12 IS Master Mode Timing Parameters, WS and SCK as Outputs ...................................................... 59 Table 10.1 Recommended Configurations for Power Control and Regulation ................................................... 60 Table 10.2 Pin States on Reset .......................................................................................................................... 67 Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current ............................. 69 Table 14.1 ESD Handling Ratings ...................................................................................................................... 90 Table 14.2 USB Electrostatic Discharge Protection Level ................................................................................. 91 Table 16.1 Chemical Limits for Green Semiconductor Products ........................................................................ 95 List of Equations Equation 3.1 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .............................................................. 26 Equation 3.2 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz .......................................... 26 Equation 3.3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz .......................................... 26 Equation 7.1 Baud Rate ....................................................................................................................................... 31 Equation 8.1 LED Current .................................................................................................................................... 35 Equation 8.2 LED PAD Voltage ............................................................................................................................ 35 Equation 9.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 47 Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, HDC(z) .................................................................... 47 Equation 9.3 PCM_CLK Frequency Generated Using the Internal 48MHz Clock ................................................ 56 Equation 9.4 PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 56 C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 13 of 114 CS-218182-DSP6 www.csr.com 1 1.1 Package Information Pinout Diagram Orientation from Top of Device 1 2 3 4 5 6 7 8 9 10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 A B C D E F G H J K C1 C2 D1 D2 G1 G2 H1 H2 C9 C10 D9 D10 G9 G10 H9 H10 C S R 8 6 4 5 B G A D a t a S h e e t 1

. 1 8 3 4 7 0 0 0

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G E1 E2 E5 E6 E9 E10 F1 F2 F5 F6 F9 F10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Figure 1.1: Device Pinout Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 14 of 114 CS-218182-DSP6 www.csr.com 1.2 Device Terminal Functions Ball Pad Type Supply Domain Description A3 RF VDD_ANA_RADIO Bluetooth 50 transmitter output /

receiver input Ball Pad Type Supply Domain Description Analogue VDD_AUX For crystal or external clock input Drive for crystal Ball Pad Type Supply Domain Description Bidirectional 3V3_USB USB data plus with selectable internal 1.5k pull-up resistor USB data minus SPI/PCM Interface Ball Pad Type Supply Domain Description SPI_PCM#

J4 Input with weak pull-

down VDD_PADS_1 SPI/PCM# select input:

0 = PCM/PIO interface 1 = SPI SPI and PCM1 interfaces are mapped as alternative functions on the PIO port. PIO Port Ball Pad Type Supply Domain Description C S R 8 6 4 5 B G A D a t a S h e e t Radio BT_RF Oscillator XTAL_IN XTAL_OUT USB USB_P USB_N Note:

PIO[21]

PIO[20]

PIO[19]

PIO[18]

PIO[17]

C1 B1 H10 J10 D10 C10 C9 D9 H2 Bidirectional with weak pull-down Bidirectional with weak pull-down Bidirectional with weak pull-down Bidirectional with weak pull-down VDD_PADS_2 Programmable input / output line 21. VDD_PADS_2 Programmable input / output line 20. VDD_PADS_2 Programmable input / output line 19. VDD_PADS_2 Programmable input / output line 18. Bidirectional with strong pull-down VDD_PADS_1 Programmable input / output line 17. Alternative function:

UART_CTS: UART clear to send, active low Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 15 of 114 CS-218182-DSP6 www.csr.com PIO Port Ball Pad Type Supply Domain Description PIO[16]

PIO[15]

PIO[14]

PIO[13]

PIO[12]

PIO[11]

PIO[10]

PIO[9]

PIO[8]

PIO[7]

PIO[6]

F1 Bidirectional with strong pull-up VDD_PADS_1 D1 Bidirectional with strong pull-up VDD_PADS_1 F2 Bidirectional with strong pull-up VDD_PADS_1 G1 Bidirectional with strong pull-down VDD_PADS_1 E2 Bidirectional with strong pull-up VDD_PADS_1 G2 Bidirectional with strong pull-down VDD_PADS_1 F5 Bidirectional with strong pull-down VDD_PADS_1 G9 Bidirectional with strong pull-down VDD_PADS_2 E10 Bidirectional with strong pull-up VDD_PADS_2 Programmable input / output line 16. Alternative function:

UART_RTS: UART request to send, active low Programmable input / output line 15. Alternative function:

UART_TX: UART data output Programmable input / output line 14. Alternative function:

UART_RX: UART data input Programmable input / output line 13. Alternative function:

QSPI_IO[1]: SPI flash data bit 1 Programmable input / output line 12. Alternative function:

QSPI_FLASH_CS#: SPI flash chip select I2C_WP: IC bus memory write protect line Programmable input / output line 11. Alternative function:

QSPI_IO[0]: SPI flash data bit 0 I2C_SDA: IC serial data line Programmable input / output line 10. Alternative function:

QSPI_FLASH_CLK: SPI flash clock I2C_SCL: IC serial clock line Programmable input / output line 9. Alternative function:

UART_CTS: UART clear to send, active low Programmable input / output line 8. Alternative function:

UART_RTS: UART request to send, active low G10 Bidirectional with strong pull-down E9 Bidirectional with strong pull-down VDD_PADS_2 Programmable input / output line 7. VDD_PADS_2 Programmable input / output line 6. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 16 of 114 CS-218182-DSP6 www.csr.com PIO Port Ball Pad Type Supply Domain Description PIO[5]

PIO[4]

PIO[3]

PIO[2]

PIO[1]

PIO[0]

Codec MIC_AP MIC_AN MIC_BP MIC_BN J1 Bidirectional with weak pull-down VDD_PADS_1 E1 Bidirectional with weak pull-down VDD_PADS_1 J5 Bidirectional with weak pull-down VDD_PADS_1 H1 Bidirectional with weak pull-down VDD_PADS_1 F10 Bidirectional with strong pull-up VDD_PADS_2 F9 Bidirectional with strong pull-up VDD_PADS_2 Programmable input / output line 5. Alternative function:

SPI_CLK: SPI clock PCM1_CLK: PCM1 synchronous data clock Programmable input / output line 4. Alternative function:

SPI_CS#: chip select for SPI, active low PCM1_SYNC: PCM1 synchronous data sync Programmable input / output line 3. Alternative function:

SPI_MISO: SPI data output PCM1_OUT: PCM1 synchronous data output Programmable input / output line 2. Alternative function:

SPI_MOSI: SPI data input PCM1_IN: PCM1 synchronous data input Programmable input / output line 1. Alternative function:

UART_TX: UART data output Programmable input / output line 0. Alternative function:

UART_RX: UART data input Analogue programmable input / output line 0. C S R 8 6 4 5 B G A D a t a S h e e t AIO[0]

D2 Bidirectional VDD_AUX Test and Debug Ball Pad Type Supply Domain Description RST#

J3 Input with strong pull-up VDD_PADS_1 Reset if low. Pull low for minimum 5ms to cause a reset. Ball Pad Type Supply Domain Description A9 A10 B7 B8 Analogue in VDD_AUDIO Analogue in VDD_AUDIO Microphone input positive, channel A Microphone input negative, channel A Microphone input positive, channel B Microphone input negative, channel B Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 17 of 114 CS-218182-DSP6 www.csr.com Codec Ball Pad Type Supply Domain Description MIC_BIAS B9 Analogue out VBAT / 3V3_USB Microphone bias SPKR_LP SPKR_LN SPKR_RP SPKR_RN A4 B4 A6 B6 Analogue out VDD_AUDIO_DRV Analogue out VDD_AUDIO_DRV Speaker output positive, left Speaker output negative, left Speaker output positive, right Speaker output negative, right AU_REF A8 Analogue in VDD_AUDIO Decoupling of audio reference (for high-

quality audio) LED Drivers Ball Pad Type Supply Domain Description LED[2]

B10 Bidirectional VDD_PADS_2 LED[1]

K1 Bidirectional VDD_PADS_1 LED[0]

J2 Bidirectional VDD_PADS_1 C S R 8 6 4 5 B G A D a t a S h e e t LED driver. Alternative function: programmable output PIO[31]

Note:

As output is open-drain, an external pull-up is required when PIO[31] is configured as a programmable output. LED driver. Alternative function: programmable output PIO[30]. Note:

As output is open-drain, an external pull-up is required when PIO[30] is configured as a programmable output. LED driver. Alternative function: programmable output PIO[29]. Note:

As output is open-drain, an external pull-up is required when PIO[29] is configured as a programmable output. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 18 of 114 CS-218182-DSP6 www.csr.com Power Supplies and Control Ball Description SMPS_1V35_SENSE K10 1.35V switch-mode power regulator sense input. SMPS_1V8_SENSE 1.8V switch-mode power regulator sense input. 3V3_USB CHG_EXT LX_1V35 LX_1V8 VBAT_SENSE VBAT VCHG VDD_ANA_RADIO VDD_AUDIO VDD_AUDIO_DRV VDD_AUX VDD_AUX_1V8 VDD_DIG_MEM VDD_PADS_1 VDD_PADS_2 VREGENABLE J9 J6 K8 K6 H9 K7 J7 K5 C2 A7 B5 B2 A1 K2 E5 E6 K4 3.3V bypass linear regulator output. Positive supply for USB port. Connect external minimum 2.2F ceramic decoupling capacitor. External battery charger control. External battery charger transistor base control when using external charger boost. Otherwise leave unconnected. 1.35V switch-mode power regulator inductor connection. 1.8V switch-mode power regulator inductor connection. Battery positive terminal. Battery charger sense input. Connect directly to the battery positive pin. Charger input. Typically connected to VBUS (USB supply) as Section 12 shows. Bluetooth radio supply. Connect to 1.35V supply, see Section 12 for connections. Positive supply for audio. Connect to 1.35V supply, see Section 12 for connections. Positive supply for audio output amplifiers. Connect to 1.8V supply. Auxiliary supply. Connect to 1.35V supply, see Section 12 for connections. Auxiliary LDO regulator input. Connect to 1.8V supply, see Section 12 for connections. Digital LDO regulator output, see Section 12 for connections. Positive supply input for input/output ports. Positive supply input for input/output ports. Regulator enable input. Can also be sensed as an input. Regulator enable and multifunction button. A high input (tolerant to VBAT) enables the on-chip regulators, which can then be latched on internally and the button used as a multifunction input. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 19 of 114 CS-218182-DSP6 www.csr.com Power Supplies and Control Ball Description VREGIN_DIG VSS_AUDIO VSS_BT_LO_AUX VSS_BT_RF VSS_DIG VSS_SMPS_1V35 VSS_SMPS_1V8 K3 A5 A2 B3 F6 K9 J8 Digital LDO regulator input, see Section 12 for connections. Typically connected to a 1.35V supply. Ground connection for audio and audio driver. Ground connections for analogue circuitry and Bluetooth radio local oscillator. Bluetooth radio ground. Ground connection for internal digital circuitry. 1.35V switch-mode regulator ground. 1.8V switch-mode regulator ground. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 20 of 114 CS-218182-DSP6 www.csr.com 1.3 Package Dimensions Top View Side View Dimension Min Typ Max Dimension Min Typ Max Ca 2X A 10 987654321 D B A A3 A2 A1 0.8 0.87 1.0 0.16 0.21 0.26 E Ca 2X SE E1 e K J H G F E D C B A A B C D E F G H J K A1 Corner Index Area Bottom View 10 9 8 7 6 5 4 3 2 1 3 F C CG C Seating Plane 2 SD e D1 nX b 1 M C AB H J M C Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 C S R 8 6 4 5 B G A D a t a S h e e t A A1 A2 A3 a b D D1 E E1 e F G H J n SE 0.27 0.32 0.37 5.45 5.55 SD

0.21 0.45 0.05 5.5 4.5 5.5 4.5

5.45 5.55 Ball diam. 0.5 0.10 0.08 0.15 0.08 68 0.25 0.25 0.3

Solder land opening 0.275 Notes 1. Dimension b is measured at the maximum solder ball diameter, 2. Datum C (seating plane) is defined by the spherical crowns of 3. Parallelism measurement shall exclude any effect of mark on parallel to datum plane C. the solder ball. top surface of package. Description 68-ball Very Thin, Fine Pitch Ball Grid Array (VFBGA) Package 2 7

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G Size Pitch 5.5 x 5.5 x 1mm JEDEC MO-225 0.5mm Units mm Page 21 of 114 CS-218182-DSP6 www.csr.com 1.4 PCB Design and Assembly Considerations This section lists recommendations to achieve maximum board-level reliability of the 5.5 x 5.5 x 1mm VFBGA 68ball package:

NSMD lands, i.e. lands smaller than the solder mask aperture, are preferred because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. Ideally, use via-in-pad technology to achieve truly NSMD lands. Where this is not possible, a maximum of one trace connected to each land is preferred and this trace should be as thin as possible, this needs to take into consideration its current carrying and the RF requirements. 35m thick (1oz) copper lands are recommended rather than 17m thick (0.5oz). This results in a greater standoff which has been proven to provide greater reliability during thermal cycling. Land diameter should be the same as that on the package to achieve optimum reliability. Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder in the joint, increasing its reliability. When using a nickel gold plating finish, the gold thickness should be kept below 0.5m to prevent brittle gold/tin intermetallics forming in the solder. 1.5 Typical Solder Reflow Profile See Typical Solder Reflow Profile for Lead-free Devices for information. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 22 of 114 CS-218182-DSP6 www.csr.com 2 Bluetooth Modem 2.1 RF Ports 2.1.1 BT_RF CSR8645 BGA contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode impedance is 50 and the transmitter has been optimised to deliver power into a 50 load. VDD On-chip Balun BT_RF VSS_BT_RF _ PA

LNA

_ 2.2 RF Receiver Figure 2.1: Simplified Circuit BT_RF The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to GSM and WCDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise enables CSR8645 BGA to exceed the Bluetooth requirements for cochannel and adjacent channel rejection. For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed to the EDR modem. 2.2.1 Low Noise Amplifier The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun. 2.2.2 RSSI Analogue to Digital Converter The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference-limited environments. 2

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 23 of 114 CS-218182-DSP6 www.csr.com 2.3 RF Transmitter 2.3.1 IQ Modulator 2.3.2 Power Amplifier The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping. The internal PA output power is software controlled and configured through a PS Key. The internal PA on the CSR8645 BGA has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3 Bluetooth radio without requiring an external RF PA. 2.4 Bluetooth Radio Synthesiser The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v4.0 specification. 2.5 Baseband 2.5.1 Burst Mode Controller During transmission the BMC constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception. 2.5.2 Physical Layer Hardware Engine Dedicated logic performs:

Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding Firmware performs the following voice data translations and operations:

A-law/-law/linear voice data (from host) A-law/-law/CVSD (over the air) Voice interpolation for lost packets Rate mismatch correction The hardware supports all optional and mandatory features of the Bluetooth v4.0 specification including AFH and eSCO. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 24 of 114 CS-218182-DSP6 www.csr.com 3 Clock Generation CSR8645 BGA requires a Bluetooth reference clock frequency of 16MHz to 32MHz from an externally connected crystal. All CSR8645 BGA internal digital clocks are generated using a phase locked loop, which is locked to the frequency of the external reference clock source or safely free-runs at a reduced frequency if clock not present. 3.1 Clock Architecture Reference Clock Bluetooth Radio Auxiliary PLL Digital Circuitry 3

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G 3.2 Input Frequencies and PS Key Settings Figure 3.1: Clock Architecture CSR8645 BGA is configured to operate with a chosen reference frequency. PSKEY_ANA_FREQ sets this reference frequency for all frequencies using an integer multiple of 250kHz. The input frequency default setting for CSR8645 BGA is 26MHz depending on the software build. Full details are in the software release note for the specific build from www.csrsupport.com. 3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT CSR8645 BGA contains a crystal driver circuit that acts as a transconductance amplifier driving an external crystal between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the external crystal. No external crystal load capacitors are required for typical crystals. 3.3.1 Crystal Calibration The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the CSR8645 BGA, as well as the capacitance of the crystal. Correct calibration of the Bluetooth radio is done on a per-

device basis on the production line, with the trim value stored in non-volatile memory (PS Key). Crystal calibration uses a single measurement. The measurement finds the actual offset from the desired frequency and the offset is stored in PSKEY_ANA_FTRIM_OFFSET. The firmware then compensates for the frequency offset on the CSR8645 BGA. Typically, a TXSTART radio test is performed to obtain the actual frequency and it is compared against the output frequency with the requested frequency using an RF analyser. The test station calculates the offset ratio and programs it into PSKEY_ANA_FTRIM_OFFSET. The value in PSKEY_ANA_FTRIM_OFFSET is a 16-bit 2's complement signed integer which specifies the fractional part of the ratio between the true crystal frequency, factual, and the value set in PSKEY_ANA_FREQ, fnominal. Equation 3.1 shows the value of PSKEY_ANA_FTRIM_OFFSET in parts per 220 rounded to the nearest integer. For more information on TXSTART radio test see BlueTest User Guide. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 25 of 114 CS-218182-DSP6 www.csr.com PSKEY_ANA_FTRIM_OFFSET = (

factual fnominal 1) 220 Equation 3.1: Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET For a requested frequency of 2402MHz with an actual output of 2402.0168MHz the PSKEY_ANA_FTRIM_OFFSET value is 7, see Equation 3.2. PSKEY_ANA_FTRIM_OFFSET = (

2402.0168 2402 1) 220 7 Equation 3.2: Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz For a requested frequency of 2402MHz with an actual output of 2401.9832MHz the PSKEY_ANA_FTRIM_OFFSET value is -7 (0xfff9), see Equation 3.3. PSKEY_ANA_FTRIM_OFFSET = (

2401.9832 2402 1) 220 7 Equation 3.3: Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 26 of 114 CS-218182-DSP6 www.csr.com 4 Bluetooth Stack Microcontroller The CSR8645 BGA uses a 16-bit RISC 80MHz MCU for low power consumption and efficient use of memory. It contains a single-cycle multiplier and a memory protection unit for the VM accelerator, see Section 4.1. The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host interfaces. 4.1 VM Accelerator CSR8645 BGA contains a VM accelerator alongside the MCU. This hardware accelerator improves the performance of VM applications. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 27 of 114 CS-218182-DSP6 www.csr.com 5 Kalimba DSP The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over-air data or codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks within CSR8645 BGA. Kalimba DSP Core Memory Management Unit MCU Register Interface (including Debug) DSP MMU Port DSP, MCU and Memory Window Control Programmable Clock = 80MHz DSP RAMs l o r t n o C m a r g o r P P S D DM2 DM1 PM DSP Data Memory 2 Interface (DM2) DSP Data Memory 1 Interface (DM1) DSP Program Memory Interface (PM) Data Memory Inteface Address Generators Instruction Decode ALU s r e i t s g e R Program Flow DEBUG Clock Select PIO Internal Control Register MMU Interface Interrupt Controller Timer MCU Window Flash Window PIO In/Out IRQ to Subsystem IRQ from Subsystem 1s Timer Clock The key features of the DSP include:

Figure 5.1: Kalimba DSP Interface to Internal Functions 80MIPS performance, 24-bit fixed point DSP core 2 singlecycle MACs; 24 x 24-bit multiply and 56-bit accumulate 32-bit instruction word Separate program memory and dual data memory, allowing an ALU operation and up to 2 memory accesses in a single cycle Zero overhead looping, including a very low-power 32-instruction cache Zero overhead circular buffer indexing Single cycle barrel shifter with up to 56-bit input and 56-bit output Multiple cycle divide (performed in the background) Orthogonal instruction set Bit reversed addressing Low overhead interrupt For more information see Kalimba Architecture 3 DSP User Guide. C S R 8 6 4 5 B G A D a t a S h e e t 2

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G Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 28 of 114 CS-218182-DSP6 www.csr.com 6 Memory Interface and Management 6.1 Memory Management Unit The MMU provides dynamically allocated ring buffers that hold the data that is in transit between the host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers. The use of DMA ports also helps with efficient transfer of data to other peripherals. 6.2 System RAM 56KB of integrated RAM supports the RISC MCU and is shared between the ring buffers for holding voice/data for each active connection and the general-purpose memory required by the Bluetooth stack. 6.3 Kalimba DSP RAM Additional integrated RAM provides support for the Kalimba DSP:

16K x 24-bit for data memory 1 (DM1) 16K x 24-bit for data memory 2 (DM2) 6K x 32-bit for program memory (PM) 6.4 Internal ROM Internal ROM is provided for system firmware implementation. 6.5 Serial Flash Interface CSR8645 BGA supports external serial flash ICs. This enables additional data storage areas for device-specific data. CSR8645 BGA supports serial single I/O devices with a 1-bit I/O flash-memory interface. Figure 6.1 shows a typical connection between CSR8645 BGA and a serial flash IC. MCU MCU Program MCU Data Kalimba DSP Kalimba DSP Program Kalimba DSP Data Memory Management Unit h s a F l l a i r e S e c a f r e t n I QSPI_FLASH_CLK QSPI_FLASH_CS#

QSPI_IO[0]

QSPI_IO[1]

1.8V Serial Quad I/O Flash RESET#/HOLD#/IO3 VDD WP#/IO2 CLK CS#

DI/IO0 DO/IO1

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G CSR8645 BGA supports Winbond, Microchip/SST, Macronix and compatible serial flash devices for PS Key and voice prompt storage up to 16Mb. Figure 6.1: Serial Flash Interface Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 29 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 7 7.1 Serial Interfaces USB Interface CSR8645 BGA has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The USB interface on CSR8645 BGA acts as a USB peripheral, responding to requests from a master host controller. CSR8645 BGA contains internal USB termination resistors and requires no external resistor matching. CSR8645 BGA supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supports USB standard charger detection and fully supports the USB Battery Charging Specification, available from http://

www.usb.org. For more information on how to integrate the USB interface on CSR8645 BGA see the Bluetooth and USB Design Considerations Application Note. As well as describing USB basics and architecture, the application note describes:

Selective suspend, includes remote wake Power distribution for high and low bus-powered configurations Power distribution for self-powered configuration, which includes USB VBUS monitoring USB enumeration Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite beads USB suspend modes and Bluetooth low-power modes:

Global suspend Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration USB termination when interface is not in use Internal modules, certification and non-specification compliant operation Suspend mode current draw PIO status in suspend mode Resume, detach and wake PIOs 7.2 UART Interface CSR8645 BGA has one optional standard UART serial interface that provides a simple mechanism for communicating with other serial devices using the RS232 protocol, including for test and debug. The UART interface is multiplexed with PIOs and other functions, and hardware flow control is optional. PS Keys configure this multiplexing, see Table 7.1. C S R 8 6 4 5 B G A D a t a S h e e t PS Key PIO Location Option PSKEY_UART_RX_PIO PIO[0] (default) or PIO[14]

PSKEY_UART_TX_PIO PIO[1] (default) or PIO[15]

PSKEY_UART_RTS_PIO PIO[8] (default) or PIO[16]

PSKEY_UART_CTS_PIO PIO[9] (default) or PIO[17]

Table 7.1: PS Keys for UART/PIO Multiplexing Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 30 of 114 CS-218182-DSP6 www.csr.com Figure 7.1 shows the 4 signals that implement the UART function. PIO[1] or PIO[15]

UART_TX PIO[0] or PIO[14]

UART_RX PIO[8] or PIO[16]

UART_RTS PIO[9] or PIO[17]

UART_CTS Figure 7.1: Universal Asynchronous Receiver When CSR8645 BGA is connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. The remaining 2 signals, UART_CTS and UART_RTS, implement optional RS232 hardware flow control where both are active low indicators. UART configuration parameters, such as baud rate and packet format, are set using CSR8645 BGA firmware. To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated serial port adapter card. Table 7.2 shows the possible UART settings. Note:

Parameter Baud rate Flow control Parity Number of stop bits Bits per byte Minimum Maximum Possible Values 1200 baud (2%Error) 9600 baud (1%Error) 4Mbaud (1%Error) RTS/CTS or None None, Odd or Even 1 or 2 8 2

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G C S R 8 6 4 5 B G A D a t a S h e e t Table 7.2: Possible UART Settings Table 7.3 lists common baud rates and their associated values for the PSKEY_UART_BAUDRATE. There is no requirement to use these standard values. Any baud rate within the supported range is set in the PS Key according to the formula in Equation 7.1. Baud Rate =

PSKEY_UART_BAUDRATE 0.004096 Equation 7.1: Baud Rate Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 31 of 114 CS-218182-DSP6 www.csr.com 1200 2400 4800 9600 19200 38400 57600 76800 Error 1.73%

1.73%

1.73%

-0.82%

0.45%

-0.18%

Baud Rate Persistent Store Value Hex 0x0005 0x000a 0x0014 Dec 5 10 20 79 39 157 236 315 472 0x013b 0x01d8 0x0027 0x004f 0x03b0 0x009d 0x00ec Prepared for Victor Leung - w kk.co m.hk - M onday, F ebruary 20, 2012 Table 7.3: Standard Baud Rates 0x3afb 0x2c3d 0x075f 0x161e 0x1d7e 0x0ebf 15099 11325 7550 1887 3775 5662 944

-0.02%

0.00%

-0.01%

0.00%

0.00%

0.00%

0.03%

0.14%

0.03%

0.03%

115200 230400 460800 921600 1382400 1843200 2764800 3686400 7.3 Programming and Debug Interface CSR8645 BGA provides a debug SPI interface for programming, configuring (PS Keys) and debugging the CSR8645 BGA. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI/PCM# line are brought out to either test points or a header. To use the SPI interface, the SPI/PCM# line requires the option of being pulled high externally. CSR provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required. All are available from CSR. 7.3.1 Multi-slave Operation Avoid connecting CSR8645 BGA in a multi-slave arrangement by simple parallel connection of slave MISO lines. When CSR8645 BGA is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSR8645 BGA outputs 0 if the processor is running or 1 if it is stopped. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 32 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t CSR8645 BGA supports optional IC EEPROM for storage of PS Keys and voice prompt data if SPI flash is not used. Figure 7.2 shows an example IC EEPROM connection where:

7.4 IC EEPROM Interface PIO[10] is the IC EEPROM SCL line PIO[11] is the IC EEPROM SDA line PIO[12] is the IC EEPROM WP line R1 2.2k R2 2.2k R3 2.2k 1.8V C1 U1 8 7 6 5 VCC WP SCL SDA 10nF 1 2 3 4 A0 A1 A2 VSS 24AAxxx

. 1 1 7 5 5 8 0 0 0

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G PIO[12]/QSPI_FLASH_CS#/I2C_WP PIO[10]/QSPI_FLASH_CLK/I2C_SCL PIO[11]/QSPI_IO[0]/I2C_SDA Figure 7.2: Example IC EEPROM Connection Note:

The IC EEPROM requires external pull-up resistors, see Figure 7.2. CSR recommends 400kHz capable IC EEPROMs. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 33 of 114 CS-218182-DSP6 www.csr.com Interfaces 8 8.1 Programmable I/O Ports, PIO CSR8645 BGA provides 22 lines of programmable bidirectional I/O, PIO[21:0]. Some of the PIOs on the CSR8645 BGA have alternative functions, see Table 8.1. Debug SPI

(See Section 7.3) SPI Flash

(See Section 6.5) UART

(See Section 7.2) PCM

(See Section 9.3) EEPROM

(See Section 7.4) PCM1_IN PCM1_OUT PCM1_SYNC PCM1_CLK Function UART_RX (default) UART_TX (default) UART_RTS (default) UART_CTS (default)

UART_RX UART_TX UART_RTS UART_CTS

I2C_SCL I2C_SDA I2C_WP

QSPI_FLASH_CLK QSPI_IO[0]

QSPI_FLASH_CS#

QSPI_IO[1]

PIO[2]

SPI_MOSI PIO[3]

SPI_MISO PIO[4]

SPI_CS#

PIO[5]

SPI_CLK PIO PIO[0]

PIO[1]

PIO[8]

PIO[9]

PIO[10]

PIO[11]

PIO[12]

PIO[13]

PIO[14]

PIO[15]

PIO[16]

PIO[17]

Note:

Table 8.1: Alternative PIO Functions See the relevant software release note for the implementation of these PIO lines, as they are firmware build-

specific. 8.2 Analogue I/O Ports, AIO CSR8645 BGA has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for battery pack temperature measurements during charge control. See Section 12 for typical connections. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 34 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 8.3 LED Drivers CSR8645 BGA includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range of colours. All LEDs are controlled by firmware. The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current-limiting resistor. LED Supply D E L I LED Forward Voltage, VF LED[2, 1 or 0]

RLED Resistor Voltage Drop, VR Pad Voltage, VPAD; RON = 20 From Figure 8.1 it is possible to derive Equation 8.1 to calculate ILED. If a known value of current is required through the LED to give a specific luminous intensity, then the value of RLED is calculated. Figure 8.1: LED Equivalent Circuit ILED =

VDD V F R LED

+ R ON Equation 8.1: LED Current VDD = VF + VR + VPAD Equation 8.2: LED PAD Voltage For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across it, VR, keeps VPAD below 0.5V. Equation 8.2 also applies. Note:

The supply domain in Section 1.2 for LED[2:0] must remain powered for LED functions to operate. The LED current adds to the overall current. Conservative LED selection extends battery life. 2

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 35 of 114 CS-218182-DSP6 www.csr.com 9 Audio Interface The audio interface circuit consists of:

Stereo/dual-mono audio codec Dual analogue audio inputs Dual analogue audio outputs 2 digital microphone inputs Configurable PCM (PCM1) and IS interfaces, for configuration information contact CSR Figure 9.1 shows the functional blocks of the interface. The codec supports stereo/dual-mono playback and recording of audio signals at multiple sample rates with a 16-bit resolution. The ADC and the DAC of the codec each contain 2 independent high-quality channels. Any ADC or DAC channel runs at its own independent sample rate. Stereo / Dual-mono Codec MMU Voice Port Voice Port Memory Management Unit Register Interface Registers Figure 9.1: Audio Interface The interface for the digital audio bus shares the same pins as the PCM1 codec interface described in Section 9.3. Table 9.1 lists the alternative functions. Important Note:

The term PCM in Section 9.3 and its subsections refers to the PCM1 interface. PCM Interface IS Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK SD_OUT SD_IN WS SCK Table 9.1: Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface PCM1 Digital Audio Digital MICs Stereo Audio Codec Driver PCM1 Interface 2 x Digital MICs 2 x Differential DAC Outputs 2 x Differential ADC Inputs

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 36 of 114 CS-218182-DSP6 www.csr.com 9.1 Audio Input and Output The audio input circuitry consists of:

Programmable as either microphone or line input Programmable as either stereo or dual-mono inputs 2 independent 16-bit high-quality ADC channels:

Multiplexed with 1 of the digital microphone inputs, see Figure 9.2 and Section 9.2.14 Each channel is independently configurable to be either single-ended or fully differential Each channel has an analogue and digital programmable gain stage for optimisation of different microphones 2 digital microphone inputs (MEMS) The audio output circuitry consists of a dual differential class A-B output stage. Note:

CSR8645 BGA is designed for a differential audio output. If a single-ended audio output is required, use an external differential to single-ended converter. 9.2 Audio Codec Interface The main features of the interface are:

Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for IS stereo digital audio bus standard Support for PCM interface including PCM master codecs that require an external system clock Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel for audio output. With respect to audio input, software and any registers, channel 0 or channel A represents the left channel and channel 1 or channel B represents the right channel. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 37 of 114 CS-218182-DSP6 www.csr.com 9.2.1 Audio Codec Block Diagram Note:

L/R pins on digital microphones pulled up or down on the PCB Stereo Audio, Voice Band and Digital Microphone Input Digital Circuitry Digital MIC Interface PIO[EVEN]

PIO[ODD]

Clock Data Digital Mic Digital Codec 16 Input C MIC_BP MIC_BN MIC_AP MIC_AN PIO[EVEN]

PIO[ODD]

SPKR_LN SPKR_LP SPKR_RN SPKR_RP High-quality ADC Digital Codec 16 Input B High-quality ADC x u M Digital Codec 16 Input A Digital MIC Interface Digital Mic Clock Data Stereo Audio and Voice Band Output Low-pass Filter Low-pass Filter High-quality DAC 16 High-quality DAC 16

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G Figure 9.2: Audio Codec Input and Output Stages The CSR8645 BGA audio codec uses a fully differential architecture in the analogue signal path, which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV for the audio driver circuits. Figure 9.2 shows the CSR8645 BGA consists of 2 high-quality ADCs:

Each ADC has a second-order Sigma-Delta converter. Each ADC is a separate channel with identical functionality. There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage, see Section 9.2.4. 9.2.3 ADC Sample Rate Selection Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:

C S R 8 6 4 5 B G A D a t a S h e e t 9.2.2 ADC 8kHz 11.025kHz 16kHz 22.050kHz 24kHz 32kHz 44.1kHz 48kHz Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 38 of 114 CS-218182-DSP6 www.csr.com 9.2.4 ADC Audio Input Gain Figure 9.3 shows that the CSR8645 BGA audio input gain consists of:

An analogue gain stage based on a pre-amplifier and an analogue gain amplifier, see Section 9.2.5 A digital gain stage, see Section 9.2.6 ADC Pre-amplifier and ADC Analogue Gain:

-3dB to 42dB in 3dB steps ADC Digital Gain:

-24dB to 21.5dB in alternating 2.5dB and 3dB steps ADC Pre-amplifier:

0dB, 9dB, 21dB and 30dB ADC Analogue Gain:

-3dB to 12dB in 3dB steps Audio Input To Digital Codec System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain 9.2.5 ADC Pre-amplifier and ADC Analogue Gain Figure 9.3: Audio Input Gain CSR8645 BGA has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:

The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB The ADC analogue amplifier gain is -3dB to 12dB in 3dB steps The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps, see Figure 9.3 At mid to high gain levels it acts as a microphone pre-amplifier, see Section 9.2.13 At low gain levels it acts as an audio line level amplifier 9.2.6 ADC Digital Gain A digital gain stage inside the ADC varies from -24dB to 21.5dB, see Table 9.2. There is also a fine gain interface with a 9-bit gain setting allowing gain changes in 1/32 steps, for more infomation contact CSR. The firmware controls the audio input gain. 3 4 5 3 5 5 0 0 0

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 39 of 114 CS-218182-DSP6 www.csr.com Digital Gain Selection ADC Digital Gain Setting Digital Gain Selection ADC Digital Gain Setting Value Value 0 1 2 3 4 5 6 7

(dB) 3.5 0 6 9.5 12 15.5 18 21.5 8 9 10 11 12 13 14 15

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5 Table 9.2: ADC Audio Input Gain Rate 9.2.7 ADC Digital IIR Filter The ADC contains 2 integrated anti-aliasing filters:

A long IIR filter suitable for music (>44.1kHz) G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance

(which is the best selection for 8kHz / 16kHz / voice) 2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in functionality, as Figure 9.2 shows. 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage. C S R 8 6 4 5 B G A D a t a S h e e t For more information contact CSR. 9.2.8 DAC The DAC consists of:

9.2.9 DAC Sample Rate Selection Each DAC supports the following sample rates:

8kHz 11.025kHz 16kHz 22.050kHz 32kHz 40kHz 44.1kHz 48kHz 96kHz 9.2.10 DAC Digital Gain A digital gain stage inside the DAC varies from -24dB to 21.5dB, see Table 9.3. There is also a fine gain interface with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 40 of 114 CS-218182-DSP6 www.csr.com The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and analogue amplifier settings. Digital Gain Selection DAC Digital Gain Setting Digital Gain Selection DAC Digital Gain Setting Value Value

(dB) 3.5 0 6 9.5 12 15.5 18 21.5 0

-3

-6

-9 8 9 10 11 12 13 14 15 3 2 1 0

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5

-12

-15

-18

-21 9.2.11 DAC Analogue Gain Table 9.3: DAC Digital Gain Rate Selection Table 9.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB steps. The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue amplifier settings. Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain Value Setting (dB) Value Setting (dB) C S R 8 6 4 5 B G A D a t a S h e e t 0 1 2 3 4 5 6 7 7 6 5 4 9.2.12 DAC Digital FIR Filter Table 9.4: DAC Analogue Gain Rate Selection The DAC contains an integrated digital FIR filter with the following modes:

A default long FIR filter for best performance at 44.1kHz. A short FIR to reduce latency. A narrow FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8kHz / 16kHz. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 41 of 114 CS-218182-DSP6 www.csr.com 9.2.13 Microphone Input CSR8645 BGA contains an independent low-noise microphone bias generator. The microphone bias generator is recommended for biasing electret condensor microphones. Figure 9.4 shows a biasing circuit for microphones with a sensitivity between about 40 to 60dB (0dB = 1V/Pa). Where:

The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its output. The microphone bias generator maintains regulation within the limits 70A to 2.8mA, supporting a 2mA source typically required by 2 electret condensor microphones. If the microphone sits below these limits, then the microphone output must be pre-loaded with a large value resistor to ground. Biasing resistors R1 and R2 equal 2.2k. The input impedance at MIC_AN, MIC_AP, MIC_BN and MIC_BP is typically 6k. C1, C2, C3 and C4 are 100/150nF if bass roll-off is required to limit wind noise on the microphone. R1 and R2 set the microphone load impedance and are normally around 2.2k. Microphone Bias

(MIC_BIAS) C1 C2 C3 C4

MIC1 Microphone Bias

(MIC_BIAS) R1 R2

MIC2 MIC_AP MIC_AN Input Amplifier MIC_BP MIC_BN Input Amplifier C S R 8 6 4 5 B G A D a t a S h e e t 2

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G Figure 9.4: Microphone Biasing The microphone bias characteristics include:

CSR8645 BGA microphone supply is VBAT or 3V3_USB Power supply:

Minimum input voltage = Output voltage + drop-out voltage Maximum input voltage is 4.3V Drop-out voltage:

300mV maximum Output voltage:

1.8V or 2.6V Tolerance 90% to 110%

Output current:

70A to 2.8mA No load capacitor required Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 42 of 114 CS-218182-DSP6 www.csr.com 9.2.14 Digital Microphone Inputs The CSR8645 BGA interfaces to 2 digital microphone inputs. Figure 9.2 shows the interface between the codec and the digital microphone interface. Figure 9.2 shows that the digital microphone interface on the CSR8645 BGA has:

Clock lines linked to any even-numbered PIO as determined by the firmware. Data lines linked to any odd-numbered PIO as determined by the firmware. For the digital microphone interface to work in this configuration ensure the microphone uses a tristate between edges. The left and right selection for the digital microphones are appropriately pulled up or down for selection on the PCB. Note:

9.2.15 Line Input Section 9.2.4 states that if the pre-amplifier audio input gain is set at a low gain level it acts as an audio line level amplifier. In this line input mode the input impedance varies from 6k to 30k, depending on the volume setting. Figure 9.5 and Figure 9.6 show 2 circuits for line input operation and show connections for either differential or single-

ended inputs. Figure 9.5: Differential Input C1 C2 C3 C4 C1 C2 C3 C4 MIC_AN MIC_AP MIC_BN MIC_BP MIC_AP MIC_AN MIC_AP MIC_AN C S R 8 6 4 5 B G A D a t a S h e e t

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G Figure 9.6: Single-ended Input Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 43 of 114 CS-218182-DSP6 www.csr.com 9.2.16 Output Stage The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output stage amplifier. Figure 9.7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP for the left channel, and between SPKR_RN and SPKR_RP for the right channel. SPKR_LP SPKR_LN SPKR_RP SPKR_RN 9.2.17 Mono Operation Figure 9.7: Speaker Output Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono channel for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-mono channel operation. In single channel mono operation, disable the other channel to reduce power consumption. 9.2.18 Side Tone In some applications it is necessary to implement side tone. This side tone function involves feeding a properly gained microphone signal in to the DAC stream, e.g. earpiece. The side tone routing selects the version of the microphone signal from before or after the digital gain in the ADC interface and adds it to the output signal before or after the digital gain of the DAC interface, see Figure 9.8. 1 1

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 44 of 114 CS-218182-DSP6 www.csr.com DAC DAC Interface Digital Input Digital Gain Analogue Output Side Tone Route Demux Side Tone Gain Side Tone Side Tone Route Mux Digital Output Digital Gain Analogue Input ADC Interface ADC Figure 9.8: Side Tone The ADC provides simple gain to the side tone data. The gain values range from -32.6dB to 12.0dB in alternating steps of 2.5dB and 3.5dB, see Table 9.5. Value Side Tone Gain Value Side Tone Gain 1

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G C S R 8 6 4 5 B G A D a t a S h e e t 0 1 2 3 4 5 6 7

-32.6dB

-30.1dB

-26.6dB

-24.1dB

-20.6dB

-18.1dB

-14.5dB

-12.0dB 8 9 10 11 12 13 14 15 Table 9.5: Side Tone Gain

-8.5dB

-6.0dB

-2.5dB 0dB 3.5dB 6.0dB 9.5dB 12.0dB Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 45 of 114 CS-218182-DSP6 www.csr.com The values of side tone are shown for information only. During standard operation, the application software controls the side tone gain. Note:

Note:

The following PS Keys configure the side tone hardware:

PSKEY_SIDE_TONE_ENABLE PSKEY_SIDE_TONE_GAIN PSKEY_SIDE_TONE_AFTER_ADC PSKEY_SIDE_TONE_AFTER_DAC 9.2.19 Integrated Digital IIR Filter The filter has 10 configuration words:

1 for gain value 8 for coefficient values 1 for enabling and disabling the DC blocking CSR8645 BGA has a programmable digital filter integrated into the ADC channel of the codec. The filter is a 2-stage, second order IIR and is for functions such as custom wind noise reduction. The filter also has optional DC blocking. The gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN. The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit. For example:

01.1111111111 01.0000000000 00.0000000000 11.0000000000 10.0000000000

most positive number, close to 2 1 0

-1

-2, most negative number Equation 9.1 shows the equation for the IIR filter. Equation 9.2 shows the equation for when the DC blocking is enabled. The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in the following order:

C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 46 of 114 CS-218182-DSP6 www.csr.com 0 1 2 3 4 5 6 7 8 9

Gain b01 b02 a01 a02 b11 b12 a11 a12 DC Block (1 = enable, 0 = disable) C S R 8 6 4 5 B G A D a t a S h e e t Filter, H(z) = Gain

( 1 + b 01

+ b 02

( 1 + b 11

+ b 12 1 z 1 2 ) z 2 )

( 1 + a01 z

+a 02 z

( 1 + a11 z

+ a12 z 1 z 1 2 ) z 2 ) Equation 9.1: IIR Filter Transfer Function, H(z) Filter with DC Blocking, HDC (z) = H(z) ( 1 z1 ) Equation 9.2: IIR Filter Plus DC Blocking Transfer Function, HDC(z) 9.3 PCM1 Interface Section 9 describes the various digital audio interfaces multiplexed on the the PCM1 interface. The PCM1 interface also shares the same physical set of pins with the SPI interface, see Section 7.3 and Section 8.1. Either interface is selected using SPI_PCM#:

SPI_PCM# = 1 selects SPI SPI_PCM# = 0 selects PCM Important Note:

The term PCM refers to PCM1. The audio PCM interface on the CSR8645 BGA supports:

Continuous transmission and reception of PCM encoded audio data over Bluetooth. Processor overhead reduction through hardware support for continual transmission and reception of PCM data. A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not pass through the HCI protocol layer. Hardware on the CSR8645 BGA for sending data to and from a SCO connection. Up to 3 SCO connections on the PCM interface at any one time. PCM interface master, generating PCM_SYNC and PCM_CLK. PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK. Various clock formats including:

GCI timing environments 13-bit or 16-bit linear, 8-bit -law or A-law companded sample formats. Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC. Long Frame Sync Short Frame Sync The PCM configuration options are enabled by setting the PSKEY_PCM_CONFIG32. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 47 of 114 CS-218182-DSP6 www.csr.com 9.3.1 PCM Interface Master/Slave When configured as the master of the PCM interface, CSR8645 BGA generates PCM_CLK and PCM_SYNC. PCM_OUT PCM_IN PCM_CLK 128/256/512/1536/2400kHz PCM_SYNC 8/48kHz Figure 9.9: PCM Interface Master PCM_OUT PCM_IN PCM_CLK Up to 2400kHz PCM_SYNC 8/48kHz 4

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G C S R 8 6 4 5 B G A D a t a S h e e t 9.3.2 Long Frame Sync Figure 9.10: PCM Interface Slave Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When CSR8645 BGA is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long. When CSR8645 BGA is configured as PCM Slave, PCM_SYNC is from 1 cycle PCM_CLK to half the PCM_SYNC rate. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 48 of 114 CS-218182-DSP6 www.csr.com PCM_SYNC PCM_CLK PCM_SYNC PCM_CLK PCM_OUT 2 3 7 8 1 1 4 4 5 5 6 6 PCM_IN Undefined 2 3 7 8 Undefined Figure 9.11: Long Frame Sync (Shown with 8-bit Companded Sample) CSR8645 BGA samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 9.3.3 Short Frame Sync In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always 1 clock cycle long. PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined Figure 9.12: Short Frame Sync (Shown with 16-bit Sample) As with Long Frame Sync, CSR8645 BGA samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 9.3.4 Multi-slot Operation More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections are carried over any of the first 4 slots. 2

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 49 of 114 CS-218182-DSP6 www.csr.com LONG_PCM_SYNC Or SHORT_PCM_SYNC PCM_CLK PCM_SYNC PCM_CLK 2

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G C S R 8 6 4 5 B G A D a t a S h e e t PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples 9.3.5 GCI Interface CSR8645 BGA is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The 2 64kbps B channels are accessed when this mode is configured. PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care B1 Channel B2 Channel Figure 9.14: GCI Interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. 9.3.6 Slots and Sample Formats CSR8645 BGA receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are either 8 or 16 clock cycles:

8 clock cycles for 8-bit sample formats. 16 clock cycles for 8-bit, 13-bit or 16-bit sample formats. CSR8645 BGA supports:

13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. A sample rate of 8ksps. Little or big endian bit order. For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some codecs. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 50 of 114 CS-218182-DSP6 www.csr.com Sign Extension 8-bit Sample 8-bit Sample Zeros Padding PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 16-bit slot with 8-bit companded sample and sign extension selected. PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 16-bit slot with 8-bit companded sample and zeros padding selected. Sign Extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A 16-bit slot with 13-bit linear sample and sign extension selected. 13-bit Sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 13-bit Sample A 16-bit slot with 13-bit linear sample and audio gain selected. Figure 9.15: 16-bit Slot Length and Sample Formats 9.3.7 Additional Features CSR8645 BGA has a mute facility that forces PCM_OUT to be 0. In master mode, CSR8645 BGA is compatible with some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running. Audio Gain 3

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 51 of 114 CS-218182-DSP6 www.csr.com 9.3.8 PCM Timing Information Symbol Parameter Min Max Unit fmclk PCM_CLK frequency 4MHz DDS generation. Selection of frequency is programmable. See Section 9.3.10. 48MHz DDS generation. Selection of frequency is programmable. See Section 9.3.10. 2.9 PCM_SYNC frequency for SCO connection PCM_CLK high 4MHz DDS generation 980 PCM_CLK low 4MHz DDS generation 730 tmclkh (a) tmclkl (a)

PCM_CLK jitter 48MHz DDS generation ns pk-pk Typ 128 256 512 8

20 0

21 20 20 20 20 20 20

kHz kHz kHz ns ns ns ns ns ns ns ns ns ns tdmclksynch Delay time from PCM_CLK high to PCM_SYNC high tdmclkpout Delay time from PCM_CLK high to valid PCM_OUT tdmclklsyncl Delay time from PCM_CLK low to PCM_SYNC low (Long Frame Sync only) tdmclkhsyncl Delay time from PCM_CLK high to PCM_SYNC low tdmclklpoutz Delay time from PCM_CLK low to PCM_OUT high impedance tdmclkhpoutz Delay time from PCM_CLK high to PCM_OUT high impedance tsupinclkl Set-up time for PCM_IN valid to PCM_CLK low thpinclkl Hold time for PCM_CLK low to PCM_IN invalid

(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced. Table 9.6: PCM Master Timing Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 52 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t t dmclklsyncl t dmclkhsyncl PCM_SYNC PCM_CLK t dmclksynch f mlk t mclkh t mclkl PCM_OUT LSB (MSB) dmclkpout MSB (LSB)

,t t r f t dmclklpoutz t dmclkhpoutz PCM_IN LSB (MSB) supinclkl hpinclkl t MSB (LSB) Figure 9.16: PCM Master Timing Long Frame Sync t dmclksynch t dmclkhsyncl PCM_SYNC f mlk t mclkh t mclkl PCM_CLK PCM_OUT LSB (MSB) dmclkpout MSB (LSB)

,t t r f t dmclklpoutz t dmclkhpoutz PCM_IN LSB (MSB) supinclkl hpinclkl t MSB (LSB) Figure 9.17: PCM Master Timing Short Frame Sync t t t t C S R 8 6 4 5 B G A D a t a S h e e t 3

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G Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 53 of 114 CS-218182-DSP6 www.csr.com Symbol Parameter Typ Max fsclk fsclk tsclkl tsclkh tdpout PCM clock frequency (Slave mode: input) PCM clock frequency (GCI mode) PCM_CLK low time PCM_CLK high time thsclksynch Hold time from PCM_CLK low to PCM_SYNC high 2 tsusclksynch Set-up time for PCM_SYNC high to PCM_CLK low 20 Delay time from PCM_SYNC or PCM_CLK, whichever is later, to valid PCM_OUT data (Long Frame Sync only) tdsclkhpout Delay time from CLK high to PCM_OUT valid data tdpoutz tsupinsclkl thpinsclkl Delay time from PCM_SYNC or PCM_CLK low, whichever is later, to PCM_OUT data line high impedance Set-up time for PCM_IN valid to CLK low Hold time for PCM_CLK low to PCM_IN invalid

(a) Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

(b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK Table 9.7: PCM Slave Timing Min 64 128 200 200

20 2

Unit kHz kHz ns ns ns ns ns ns ns ns ns

(a)

(b)

20 15 15 C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 54 of 114 CS-218182-DSP6 www.csr.com f sclk t sclkh t tsclkl t hsclksynch t susclksynch PCM_CLK PCM_SYNC PCM_OUT MSB (LSB) LSB (MSB) t dpout t dsclkhpout

,t t r f t dpoutz t dpoutz t t supinsclkl hpinsclkl PCM_IN MSB (LSB) LSB (MSB) Figure 9.18: PCM Slave Timing Long Frame Sync t susclksynch t hsclksynch PCM_CLK PCM_SYNC PCM_OUT PCM_IN f sclk t sclkh t tsclkl t dsclkhpout MSB (LSB) t t supinsclkl hpinsclkl MSB (LSB) t dpoutz t dpoutz

,t t r f LSB (MSB) LSB (MSB) Figure 9.19: PCM Slave Timing Short Frame Sync 9.3.9 PCM_CLK and PCM_SYNC Generation CSR8645 BGA has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:

Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 55 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 2

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G Generating these signals by DDS from CSR8645 BGA internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. Generating these signals by DDS from an internal 48MHz clock (which enables a greater range of frequencies to be generated with low jitter but consumes more power). To select this second method set bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32. Equation 9.3 describes PCM_CLK frequency when generated from the internal 48MHz clock:

Equation 9.3: PCM_CLK Frequency Generated Using the Internal 48MHz Clock Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 9.4:

f =

CNT_RATE CNT_LIMIT 24MHz f =

PCM_CLK SYNC_LIMIT 8 CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_USE_LOW_JITTER_MODE. Equation 9.4: PCM_SYNC Frequency Relative to PCM_CLK 9.3.10 PCM Configuration Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_USE_LOW_JITTER_MODE, see BlueCore Audio API Specification and the PS Key file. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tristate of PCM_OUT. 9.4 Digital Audio Interface (IS) The digital audio interface supports the industry standard formats for IS, left-justified or right-justified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table 9.8 lists these alternative functions. Figure 9.20 shows the timing diagram. PCM Interface IS Interface PCM_OUT PCM_IN PCM_SYNC PCM_CLK SD_OUT SD_IN WS SCK Table 9.8: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see BlueCore Audio API Specification and the PS Key file. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 56 of 114 CS-218182-DSP6 www.csr.com Left Channel Right Channel SD_IN/OUT MSB LSB MSB LSB Left -justified Mode Left Channel Right Channel SD_IN/OUT MSB LSB MSB LSB Right -justified Mode Left Channel Right Channel WS SCK WS SCK WS SCK SD_IN/OUT MSB LSB MSB LSB I2 S Mode Figure 9.20: Digital Audio Interface Modes The internal representation of audio samples within CSR8645 BGA is 16-bit and data on SD_OUT is limited to 16-

bit per channel. Symbol Parameter Min Typ

tch tcl SCK Frequency WS Frequency SCK high time SCK low time

80 80

Max 6.2 96

Unit MHz kHz ns ns Table 9.9: Digital Audio Interface Slave Timing Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 57 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 2

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G Symbol Parameter Typ Max Unit ns ns ns ns ns

20

t sh Min 20 2.5

20 2.5 t ssu t cl t opd tssu tsh topd tisu tih WS valid to SCK high set-up time SCK high to WS invalid hold time SCK low to SD_OUT valid delay time SD_IN valid to SCK high set-up time SCK high to SD_IN invalid hold time t ch SCK(Input) WS(Input) SD_OUT SD_IN Table 9.10: IS Slave Mode Timing isut t ih Figure 9.21: Digital Audio Interface Slave Timing C S R 8 6 4 5 B G A D a t a S h e e t 2 2

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G Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 58 of 114 CS-218182-DSP6 www.csr.com Symbol Parameter Min Typ

SCK Frequency WS Frequency Table 9.11: Digital Audio Interface Master Timing Symbol Parameter Min Typ tspd topd tisu tih SCK low to WS valid delay time SCK low to SD_OUT valid delay time SD_IN valid to SCK high set-up time 18.44 SCK high to SD_IN invalid hold time Max 6.2 96 Max 39.27 18.44

Unit MHz kHz Unit ns ns ns ns

Table 9.12: IS Master Mode Timing Parameters, WS and SCK as Outputs

0 t spd topd WS(Output) SCK(Output) SD_OUT SD_IN t isu t ih Figure 9.22: Digital Audio Interface Master Timing C S R 8 6 4 5 B G A D a t a S h e e t 2

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G Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 59 of 114 CS-218182-DSP6 www.csr.com 10 Power Control and Regulation For greater power efficiency the CSR8645 BGA contains 2 switch-mode regulators:

1 generates a 1.80V supply rail with an output current of 185mA, see Section 10.1. 1 generates a 1.35V supply rail with an output current of 160mA, see Section 10.2. Combining the 2 switch-mode regulators in parallel generates a single 1.80V supply rail with an output current of 340mA, see Section 10.3. CSR8645 BGA contains 4 LDO linear regulators:

3.30V bypass regulator, see Section 10.4. 0.80V to 1.20V VDD_DIG linear regulator, see Section 10.5. 1.35V VDD_AUX linear regulator, see Section 10.6. 1.35V VDD_ANA linear regulator, see Section 10.7. The recommended configurations for power control and regulation on the CSR8645 BGA are:

3 switch-mode configurations:

A 1.80V and 1.35V dual-supply rail system using the 1.80V and 1.35V switch-mode regulators, see Figure 10.1. This is the default power control and regulation configuration for the CSR8645 BGA. A 1.80V single-supply rail system using the 1.80V switch-mode regulator. A 1.80V parallel-supply rail system for higher currents using the 1.80V and 1.35V switch-mode regulators with combined outputs, see Figure 10.2. A linear configuration using an external 1.8V rail omitting all regulators Table 10.1 shows settings for the recommended configurations for power control and regulation on the CSR8645 BGA. Supply Configuration Switch-mode Regulators VDD_AUX VDD_ANA Linear Regulator Linear Regulator Supply Rail 1.8V 1.35V 1.8V 1.35V Dual-supply SMPS Single-supply SMPS Parallel-

supply SMPS ON ON ON Linear supply OFF ON OFF OFF SMPS SMPS OFF ON OFF ON ON ON ON ON ON SMPS LDO SMPS LDO External LDO Table 10.1: Recommended Configurations for Power Control and Regulation For more information on CSR8645 BGA power supply configuration see the Configuring the Power Supplies on CSR8670 application note. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 60 of 114 CS-218182-DSP6 www.csr.com VCHG VBAT_SENSE VBAT Charger 50 to 200mA Charge Reference EN Bypass Linear OUT Regulator SENSE 3V3_USB 1.8V 1.35V 3.3V Reference VREGENABLE Analogue and Auxiliary IN 1.35V OUT Switch-mode EN Regulator SENSE IN 1.8V OUT Switch-mode EN Regulator SENSE VDD_AUX Regulator IN OUT EN SENSE Auxiliary Circuits VDD_ANA Regulator IN OUT EN SENSE Bluetooth Audio Circuits Mic Bias Audio Driver Audio Core Digital Core Circuits EN VDD_DIG Regulator IN OUT SENSE LX_1V35 SMPS_1V35_SENSE LX_1V8 SMPS_1V8_SENSE VDD_AUX_1V8 VDD_AUX VDD_ANA_RADIO MIC_BIAS VDD_AUDIO_DRV VDD_AUDIO VREGIN_DIG VDD_DIG_MEM I/O VDD_PADS_1 VDD_PADS_2 C S R 8 6 4 5 B G A D a t a S h e e t 3 4

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G Figure 10.1: 1.80V and 1.35V Dual-supply Switch-mode System Configuration Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 61 of 114 CS-218182-DSP6 www.csr.com VCHG VBAT_SENSE VBAT Charger 50 to 200mA Charge Reference EN Bypass Linear OUT Regulator SENSE 3V3_USB 1.8V 1.35V 3.3V Reference VREGENABLE Analogue and Auxiliary IN EN 1.35V SENSE Switch-mode Regulator OUT IN 1.8V OUT Switch-mode EN Regulator SENSE VDD_AUX Regulator IN OUT EN SENSE Auxiliary Circuits VDD_ANA Regulator IN OUT EN SENSE Bluetooth Audio Circuits Mic Bias Audio Driver Audio Core Digital Core Circuits EN VDD_DIG Regulator IN OUT SENSE SMPS_1V35_SENSE LX_1V35 LX_1V8 SMPS_1V8_SENSE VDD_AUX_1V8 VDD_AUX VDD_ANA_RADIO MIC_BIAS VDD_AUDIO_DRV VDD_AUDIO VREGIN_DIG VDD_DIG_MEM I/O VDD_PADS_1 VDD_PADS_2 C S R 8 6 4 5 B G A D a t a S h e e t 3

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G Figure 10.2: 1.80V Parallel-supply Switch-mode System Configuration Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 62 of 114 CS-218182-DSP6 www.csr.com 10.1 1.8V Switch-mode Regulator CSR recommends using the integrated switch-mode regulator to power the 1.80V supply rail. Figure 10.3 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7H), followed by a low ESR shunt capacitor, C3 (2.2F), is required between the LX_1V8 terminal and the 1.80V supply rail. Connect the 1.80V supply rail and the VDD_AUX_1V8 pin. C1 2.2F C2 2.2F VBAT 3V3_USB LX 1.8V Switch-mode Regulator SENSE To 1.35V Switch-mode Regulator Input L1 4.7H LX_1V8 1.8V Supply Rail SMPS_1V8_SENSE VSS_SMPS_1V8 C3 2.2F 2

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G Figure 10.3: 1.8V Switch-mode Regulator Output Configuration Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V8. Also minimise the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximise efficiency. For the regulator to meet the specifications in Section 14.3.1.1 requires a total resistance of <1.0 (<0.5 recommended) for the following:

The track between the battery and VBAT. The track between LX_1V8 and the inductor. The inductor, L1, ESR. The track between the inductor, L1, and the sense point on the 1.80V supply rail. The following enable the 1.80V switch-mode regulator:

VREGENABLE pin The CSR8645 BGA firmware with reference to PSKEY_PSU_ENABLES VCHG pin The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which also affects the 1.35V switch-mode regulator. When the 1.80V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB The regulator output LX_1V8 10.2 1.35V Switch-mode Regulator CSR recommends using the integrated switch-mode regulator to power the 1.35V supply rail. Figure 10.4 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7H), followed by a low ESR shunt capacitor, C3 (4.7F), is required between the LX_1V35 terminal and the 1.35V supply rail. Connect the 1.35V supply rail and the SMPS_1V35_SENSE pin. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 63 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t VBAT 3V3_USB C1 2.2F C2 2.2F LX 1.35V Switch-

mode Regulator SENSE SMPS_1V35_SENSE VSS_SMPS_1V35 To 1.8V Switch-mode Regulator Input L1 4.7H LX_1V35 1.35V Supply Rail C3 4.7F 2

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G Figure 10.4: 1.35V Switch-mode Regulator Output Configuration Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. Ensure a solid ground plane between C1, C2, C3 and VSS_SMPS_1V35. Also minimise the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximise efficiency. For the regulator to meet the specifications in Section 14.3.2.1 requires a total resistance of <1.0 (<0.5 recommended) for the following:

The track between the battery and VBAT. The track between LX_1V8 and the inductor. The inductor, L1, ESR. The track between the inductor, L1, and the sense point on the 1.35V supply rail. The following enable the 1.35V switch-mode regulator:

VREGENABLE pin The CSR8645 BGA firmware with reference to PSKEY_PSU_ENABLES VCHG pin The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which also affects the 1.80V switch-mode regulator. When the 1.35V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB The regulator output LX_1V35 10.3 1.8V and 1.35V Switch-mode Regulators Combined For applications that require a single 1.80V supply rail with higher currents CSR recommends combining the outputs of the integrated 1.80V and 1.35V switch-mode regulators in parallel to power a single 1.80V supply rail, see Figure 10.5. Figure 10.5 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7H), followed by a low ESR shunt capacitor, C3 (2.2F), is required between the LX_1V8 terminal and the 1.80V supply rail. Connect the 1.80V supply rail and the VDD_AUX_1V8 pin and ground the SMPS_1V35_SENSE pin. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 64 of 114 CS-218182-DSP6 www.csr.com 2

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G C S R 8 6 4 5 B G A D a t a S h e e t VBAT 3V3_USB C1 2.2F C2 2.2F LX 1.35V Switch-

mode Regulator SENSE LX_1V35 SMPS_1V35_SENSE VSS_SMPS_1V35 L1 4.7H LX_1V8 1.8V Supply Rail C3 2.2F LX 1.8V Switch-mode Regulator SENSE SMPS_1V8_SENSE VSS_SMPS_1V8 Figure 10.5: 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration Minimise the series resistance of the tracks between the regulator input VBAT and 3V3_USB, ground terminals, the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and low supply ripple. Ensure a solid ground plane between C1, C2, C3, VSS_SMPS_1V8 and VSS_SMPS_1V35. Also minimise the collective parasitic capacitance on the track between LX_1V8, LX_1V35 and the inductor L1, to maximise efficiency. For the regulator to meet the specifications in Section 14.3.1.2 requires a total resistance of <1.0 (<0.5 recommended) for the following:

The track between the battery and VBAT. The track between LX_1V8, LX_1V35 and the inductor. The inductor L1, ESR. The track between the inductor, L1, and the sense point on the 1.80V supply rail. The following enable the 1.80V switch-mode regulator:

VREGENABLE pin The CSR8645 BGA firmware with reference to PSKEY_PSU_ENABLES VCHG pin The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET. When the 1.80V switch-mode regulator is not required, leave unconnected:

The regulator input VBAT and 3V3_USB The regulator output LX_1V8 10.4 Bypass LDO Linear Regulator The integrated bypass LDO linear regulator is available as a 3.30V supply rail and is an alternative supply rail to the battery supply. This is especially useful when the battery has no charge and the CSR8645 BGA needs to power up. The input voltage should be between 4.75 / 3.10V and 5.25V. The integrated bypass LDO linear regulator can operate down to 3.0V with a reduced performance. Note:

Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 65 of 114 CS-218182-DSP6 www.csr.com Externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 2.2F to the 3V3_USB pin. The output voltage is switched on when VCHG gets above 3.0V. 10.5 Low-voltage VDD_DIG Linear Regulator The integrated low-voltage VDD_DIG linear regulator powers the digital circuits on CSR8645 BGA. Externally decouple the output of this regulator using a low ESR MLC capacitor of 470nF. 10.6 Low-voltage VDD_AUX Linear Regulator The integrated low-voltage VDD_AUX linear regulator is optionally available to provide a 1.35V auxiliary supply rail when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_AUX linear regulator, externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 470nF to the VDD_AUX pin. 10.7 Low-voltage VDD_ANA Linear Regulator The integrated low-voltage VDD_ANA linear regulator is optionally available to power the 1.35V analogue supply rail when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA linear regulator, externally decouple the output of this regulator using a 2.2F low ESR MLC capacitor to the VDD_ANA_RADIO pin. 10.8 Voltage Regulator Enable When using the integrated regulators the voltage regulator enable pin, VREGENABLE, enables the CSR8645 BGA and the following regulators:

1.8V switch-mode regulator 1.35V switch-mode regulator Low-voltage VDD_DIG linear regulator Low-voltage VDD_AUX linear regulator The VREGENABLE pin is active high, with a weak pull-down. CSR8645 BGA boots-up when the voltage regulator enable pin is pulled high, enabling the regulators. The firmware then latches the regulators on. The voltage regulator enable pin can then be released. The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works as an input line. VREGENABLE should be asserted after the VBAT supply when VREGENABLE is not used as a power-on button. 10.9 External Regulators and Power Sequencing CSR recommends that the integrated regulators supply the CSR8645 BGA and it is configured based on the information in this data sheet. If any of the supply rails for the CSR8645 BGA are supplied from an external regulator, then it should match or be better than the internal regulator available on CSR8645 BGA. For more information see regulator characteristics in Section 14. Note:

Note:

The internal regulators described in Section 10.1 to Section 10.7 are not recommended for external circuitry other than that shown in Section 12. For information about power sequencing of external regulators to supply the CSR8645 BGA contact CSR. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 66 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 10.10 Reset, RST#

CSR8645 BGA is reset from several sources:

RST# pin Power-on reset USB charger attach reset Software configured watchdog timer The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. CSR recommends applying RST# for a period >5ms. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate. 10.10.1 Digital Pin States on Reset Table 10.2 shows the pin states of CSR8645 BGA on reset. Pin Name I/O Type Full Chip Reset Pin Name I/O Type Full Chip Reset USB_DP Digital bidirectional USB_DN Digital bidirectional N/A N/A PUS PUS PDW PDW PDW PDW PDS PDS PUS PDS PIO[10]

PIO[11]

PIO[12]

PIO[13]

PIO[14]

PIO[15]

PIO[16]

PIO[17]

PIO[18]

PIO[19]

PIO[20]

PIO[21]

Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional Digital bidirectional PDS PDS PUS PDS PUS PUS PUS PDS PDW PDW PDW PDW Table 10.2: Pin States on Reset PIO[0]

PIO[1]

PIO[2]

PIO[3]

PIO[4]

PIO[5]

PIO[6]

PIO[7]

PIO[8]

PIO[9]

Note:

C S R 8 6 4 5 B G A D a t a S h e e t PUS = Strong pull-up PDS = Strong pull-down PUW = Weak pull-up PDW = Weak pull-down Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 67 of 114 CS-218182-DSP6 www.csr.com 10.10.2 Status After Reset The status of CSR8645 BGA after a reset is:

Warm reset: baud rate and RAM data remain available Cold reset: baud rate and RAM data not available 10.11 Automatic Reset Protection CSR8645 BGA includes an automatic reset protection circuit which restarts/resets CSR8645 BGA when an unexpected reset occurs, e.g. ESD strike or lowering of RST#. The automatic reset protection circuit enables resets from the VM without the requirement for external circuitry. Note:

The reset protection is cleared after typically 2s (1.6s min to 2.4s max). If RST# is held low for >2.4s CSR8645 BGA turns off. A rising edge on VREGENABLE or VCHG is required to power on CSR8645 BGA. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 68 of 114 CS-218182-DSP6 www.csr.com 11 Battery Charger 11.1 Battery Charger Hardware Operating Modes The battery charger hardware is controlled by the VM, see Section 11.3.The battery charger has 5 modes:

Disabled Trickle charge Fast charge Standby: fully charged or float charge Error: charging input voltage, VCHG, is too low The battery charger operating mode is determined by the battery voltage and current, see Table 11.1 and Figure 11.1. The internal charger circuit can provide up to 200mA of charge current, for currents higher than this the CSR8645 BGA can control an external pass transistor, see Section 11.5. Mode Battery Charger Enabled VBAT_SENSE Disabled Trickle charge Fast charge Standby Error No Yes Yes Yes Yes X

>0 and <Vfast

>Vfast and <Vfloat Iterm (a) and >(Vfloat - Vhyst)

>(VCHG - 50mV) Table 11.1: Battery Charger Operating Modes Determined by Battery Voltage and Current

(a) Iterm is approximately 10% of Ifast for a given Ifast setting C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 69 of 114 CS-218182-DSP6 www.csr.com Figure 11.1 shows the mode-to-mode transition voltages. These voltages are fixed and calibrated by CSR, see Section 11.2. The transition between modes can occur at any time. t n e r r u C e g r a h C Fast Charge Mode Constant Current Ifast Itrickle Trickle Charge Mode Vfast Fast Charge Mode Constant Voltage Standby Mode Iterm Vhyst Battery Voltage Vfloat

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G Figure 11.1: Battery Charger Mode-to-Mode Transition Diagram The battery voltage remains constant in Fast Charge Constant Voltage Mode, the curved line on Figure 11.1 is for clarity only. Note:

11.1.1 Disabled Mode 11.1.2 Trickle Charge Mode In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals. In the trickle charge mode, when the voltage on VBAT_SENSE is lower than the Vfast threshold, a current of approximately 10% of the fast charge current, Ifast, is sourced from the VBAT pin. The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes. 11.1.3 Fast Charge Mode When the voltage on VBAT_SENSE is greater than Vfast, the current sourced from the VBAT pin increases to Ifast. Ifast is between 10mA and 200mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to correct for process variation in the charger circuit. The current is held constant at Ifast until the voltage at VBAT_SENSE reaches Vfloat, then the charger reduces the current sourced to maintain a constant voltage on the VBAT_SENSE pin. When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standby mode. Iterm is typically 10% of the fast charge current. 11.1.4 Standby Mode When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltage on the VBAT_SENSE pin is monitored, and when it drops below a threshold set at Vhyst below the final charging voltage, Vfloat, the charger re-enters fast charge mode. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 70 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 11.1.5 Error Mode The charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly

(VBAT_SENSE is greater than VCHG - 50mV (typical)). In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation. 11.2 Battery Charger Trimming and Calibration The battery charger default trim values are written by CSR into internal ROM when each IC is characterised. CSR provides various PS Keys for overriding the default trims, see Section 11.4. 11.3 VM Battery Charger Control The VM charger code has overall supervisory control of the battery charger and is responsible for:

Responding to charger power connection/disconnection events Monitoring the temperature of the battery Monitoring the temperature of the die to protect against silicon damage Monitoring the time spent in the various charge states Enabling/disabling the charger circuitry based on the monitored information Driving the user visible charger status LED(s) 11.4 Battery Charger Firmware and PS Keys The battery charger firmware sets up the charger hardware based on the PS Key settings and call traps from the VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery capacity and type, which are set by the user in the PS Keys. For more information on the CSR8645 BGA, including details on setting up, calibrating, trimming and the PS Keys, see Lithium Polymer Battery Charger Calibration and Operation for CSR8670 application note. 11.5 External Mode The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across a resistor, Rsense, connected in series with the external pass device, see Figure 11.2. The voltage drop is determined by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across Rsense is typically 200mV. The value of the external series resistor determines the charger current. This current can be trimmed with a PS Key. In Figure 11.2, R1 (220m) and C1 (4.7F) form an RC snubber that is required to maintain stability across all battery ESRs. The battery ESR must be <1.0. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 71 of 114 CS-218182-DSP6 www.csr.com VCHG CHG_EXT VBAT_SENSE VBAT R1 220m C1 4.7F TR 1 External Pass Device Rsense BAT 1 Li+ Cell Figure 11.2: Battery Charger External Mode Typical Configuration

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G C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 72 of 114 CS-218182-DSP6 www.csr.com VBAT VBUS VBAT 3V3_USB 1V8_SMPS 1V35_SMPS 1V8_SMPS S1 MFB T X E _ G H C C1 2u2 E S N E S _ T A B V G H C V E L B A N E G E R V T A B V T X E _ G H C E S N E S _ T A B V C2 2u2 C3 2u2 L1 4u7 C4 2u2 C5 10n C6 10n L2 4u7 C7 4u7 C8 15p C9 2u2 C10 470n C11 100n 4 K 5 K 6 J 7 J 7 K 9 H 1 A 5 B 7 A 9 J B S U _ 3 V 3 6 K 8 V 1 _ X L 8 V 1 _ X U A _ D D V E S N E S _ 8 V 1 _ S P M S O I D U A _ D D V V R D _ O I D U A _ D D V 2 B X U A _ D D V 8 K 5 3 V 1 _ X L 0 1 K 2 C E S N E S _ 5 3 V 1 _ S P M S O I D A R _ A N A _ D D V 3 K I G D _ N G E R V I 2 K M E M _ G D _ D D V I 5 E 6 E 1 _ S D A P _ D D V 2 _ S D A P _ D D V CHARGER VBAT 1V8 SMPS BYPASS REG 3V3 1V35 SMPS AUX L DO ANA L DO 1V35 1V35 1V35 CSR8645 BGA PIO[2]/PCM1_IN/SPI_MOSI PIO[3]/PCM1_OUT/SPI_MISO PIO[4]/PCM1_SYNC/SPI_CS#

PIO[5]/PCM1_CLK/SPI_CLK SPI_PCM#

SPI_PCM#

PIO / PCM1 / Debug SPI / I2S SPI / PCM# High For SPI. Low For All Other Functions DIG LDO LED Outputs XTAL_IN C1 XTAL_OUT B1 PIO[29]/LED[0]

PIO[30]/LED[1]

PIO[31]/LED[2]

PIO[0]

PIO[1]

PIO[6]

PIO[7]

PIO[8]

PIO[9]

PIO[18]

PIO[19]

PIO[20]

PIO[21]

J2 K1 B10 F9 F10 E9 G10 E10 G9 D9 C9 C10 D10 H1 J5 E1 J1 J4 E2 F5 G2 G1 F2 D1 F1 H2 D2 XT1 26MHz LED_0 LED_1 LED_2 PIO_0 PIO_1 PIO_6 PIO_7 PIO_8 PIO_9 PIO_18 PIO_19 PIO_20 PIO_21 PIO_2 PIO_3 PIO_4 PIO_5 PIO_12 PIO_10 PIO_11 PIO_13 PIO_14 PIO_15 PIO_16 PIO_17 AIO_0 USB_P USB_N PIO[12] / QSPI_FLASH_CS# / I2C_WP PIO[10] / QSPI_FLASH_CLK / I2C_SCL PIO[11] / QSPI_IO[0] / I2C_SDA PIO[13] / QSPI_IO[1]

PIO[14] / UART_RX PIO[15] / UART_TX PIO[16] / UART_RTS PIO[17] / UART_CTS AIO[0]

USB_P USB_N H10 J10 N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S 4 B 4 A 6 B 6 A N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S Left Right Speakers (16 to 32) PIO PIO / Serial Flash / I2C PIO / UART Analogue Input / Output USB (12Mbps) J3 RST#

RSTB Reset X U A _ O L _ T B _ S S V F R _ T B _ S S V G I D _ S S V 8 V 1 _ S P M S _ S S V 5 3 V 1 _ S P M S _ S S V O I D U A _ S S V 2 A 3 B 6 F SP100 5 A 8 J 9 K STAR MIC BIAS F E R _ U A 8 A C12 2u2 N A _ C I M 0 1 A N 1 _ C I M P A _ C I M 9 A P 1 _ C I M S A I B _ C I M 9 B S A I B _ C I M C13 100n C14 100n C15 100n C16 100n P B _ C I M 7 B P 2 _ C I M N B _ C I M 8 B N 2 _ C I M R2 2k2 Dual-microphone Inputs Mic1 Mic2 MIC_1 L4 15nH MIC_2 L5 15nH R1 2k2 C17 15p C18 15p 12 Example Application Schematic ANT U2 OUT IN BT_RF A3 BT_RF Bluetooth RF 4 1 2 3 GND GND 2.45GHz PCB Layout Notes Ensure the following components are placed next to CSR8645 BGA and have good low impedance connections both to signal and GND C2 and C3 Ensure the following tracks have good low impedance connections

(no via share and short thick tracks) VSS_SMPS_1V8 to Battery Ground VSS_SMPS_1V35 to Battery Ground LX_1V8 to Inductor LX_1V35 to Inductor L1 to C4 Track L2 to C7 Track C4 to GND C7 to GND VDD_DIG to Ground VBAT to Battery and C2 should be <1 from battery VCHG to charger connector and C1 Ensure good low impedance ground return path through GND plane for SMPSU current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 and C4 Ensure routing from L2 to ball K3 and from L2 to C8/C9 and ball C2 are kept separate CSR recommends low Rdc inductors (<0.5) for L1 and L2 for optimum power efficiency For example Taiyo Yuden CB2012T4R7M Suggest analogue and digital grounds are separated if possible and star connected near VSS_AUDIO as shown Ensure analogue tracks stay over Analogue ground as much as possible Optional Ancilliary Circuits Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Optional Fast Charge 400m = 500mA USB / Charger Interface Lithium Polymer Battery

(Built-in Battery Protection) Battery Temperature Sensor VBAT VBUS Typical LEDs and Buttons Optional I2C EEPROM Memory Optional 1 x SPI Flash Memory VBUS USB_N USB_P CON100 USB MINI-B 1 2 3 4 5 VBUS D-

D+

ID GND D N G D N G 7 6 VBAT Li+ CELL CON101 3.7V 1V35_SMPS AIO_0 R100 9k1 THERM 10k C102 10n D Q1 PIO_n G S D100 BAT54C E U L B D101 D E R D102 D103 N E E R G R101 220R R102 330R R103 330R 1V8 1V8 1V8 1V8 1V8 S100 F4 S101 F3 S102 F2 S103 VOL+

S104 VOL-

PIO_12 PIO_10 PIO_11 R105 2k2 R106 2k2 R107 2k2 U101 VCC WP SCL SDA 8 7 6 5 10n 1 2 3 4 A0 A1 A2 VSS 24AAxxx 1V8_SMPS C100 1V8_SMPS 2 _ D E L 1 _ D E L 0 _ D E L n _ O P I n _ O P I n _ O P I n _ O P I n _ O P I Size of EEPROM Depends on Voice Prompt Requirements C101 10n PIO_11 PIO_13 1V8_SMPS U100 VDD 8 5 2 3 7 SI/SIO0 SO/SIO1 WP/SIO2 HOLD/SIO3 1 6 4 CE SCK VSS SPI Flash PIO_12 PIO_10 Digital Mic(s) 1V8_SMPS CLOCK PIO_n (even) DATA PIO_n (odd) VBUS CHG_EXT 1 VBAT_SENSE VBAT Q100 BCX51 3 2 R104 1%

400mR C105 4u7 R108 220mR Connect VBAT_SENSE to VBAT If Not Using This Circuit C S R 8 6 4 5 B G A D a t a S h e e t 2 3

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G Page 73 of 114 CS-218182-DSP6 www.csr.com 13 Example Application Using Different Power Supply Configurations VREGENABLE VREGENABLE VBAT & VCHG grounded 1V8_INPUT C2 470n R3 100k Q1 FDV301N or Equivalent D S G R2 100k GND GND VREGENABLE Delay Circuit VREGENABLE Should be Asserted After The System Supply Has Risen in This Configuration. This Circuit Provides The Required Delay. If An External Reset Signal Is Used CSR Recommends It is Also Included in VREGENABLE. Single 1.8V Only Supply. No USB, No Switch-mode. 1V8_INPUT 1V8_INPUT 1V8_INPUT 1V8_INPUT C3 100n C4 2u2 C5 100n C6 470n C8 15p C9 2u2 C10 470n C11 100n 4 K 5 K 6 J 7 J 7 K GND GND GND 9 H 1 A GND 5 B GND GND GND 0 1 K 2 C G H C V E L B A N E G E R V T A B V T X E _ G H C E S N E S _ T A B V 9 J B S U _ 3 V 3 6 K 8 V 1 _ X L 7 A O I D U A _ D D V 2 B X U A _ D D V 8 V 1 _ X U A _ D D V E S N E S _ 8 V 1 _ S P M S V R D _ O I D U A _ D D V E S N E S _ 5 3 V 1 _ S P M S I O D A R _ A N A _ D D V 3 K G I I D _ N G E R V 2 K M E M _ G I D _ D D V 5 E 6 E 1 _ S D A P _ D D V 2 _ S D A P _ D D V 1V35 8 K 5 3 V 1 _ X L CHARGER VBAT 1V8 SMPS BYPASS R EG 3V3 1V35 SMPS AUX LDO ANA LDO 1V35 1V35 1V35 ANT 4 IN BT_RF A3 BT_RF Bluetooth RF U2 OUT 2 3 GND GND 1 2.45GHz CSR8645 BGA DIG LDO LED Outputs XTAL_IN C1 XTAL_OUT B1 PIO[29]/LED[0]

PIO[30]/LED[1]

PIO[31]/LED[2]

J2 K1 B10 PIO[0]

PIO[1]

PIO[6]

PIO[7]

PIO[8]

PIO[9]

PIO[18]

PIO[19]

PIO[20]

PIO[21]

F9 F10 E9 G10 E10 G9 D9 C9 C10 D10 PIO[2]/PCM1_IN/SPI_MOSI PIO[3]/PCM1_OUT/SPI_MISO PIO[4]/PCM1_SYNC/SPI_CS#

PIO[5]/PCM1_CLK/SPI_CLK H1 J5 E1 J1 PIO[12] / QSPI_FLASH_CS# / I2C_WP PIO[10] / QSPI_FLASH_CLK / I2C_SCL PIO[11] / QSPI_IO[0] / I2C_SDA PIO[13] / QSPI_IO[1]

E2 F5 G2 G1 PIO[14] / UART_RX PIO[15] / UART_TX PIO[16] / UART_RTS PIO[17] / UART_CTS F2 D1 F1 H2 XT1 26MHz LED_0 LED_1 LED_2 PIO_0 PIO_1 PIO_6 PIO_7 PIO_8 PIO_9 PIO_18 PIO_19 PIO_20 PIO_21 PIO_2 PIO_3 PIO_4 PIO_5 PIO_12 PIO_10 PIO_11 PIO_13 PIO_14 PIO_15 PIO_16 PIO_17 SPI_PCM#

J4 SPI_PCM#

SPI / PCM# High For SPI. Low For All Other Functions PIO / PCM1 / Debug SPI / I2S PIO PIO / Serial Flash / I2C PIO / UART C S R 8 6 4 5 B G A D a t a S h e e t X U A _ O L _ T B _ S S V F R _ T B _ S S V G I D _ S S V 8 V 1 _ S P M S _ S S V 5 3 V 1 _ S P M S _ S S V I O D U A _ S S V 2 A 3 B 6 F SP100 5 A 8 J 9 K STAR MIC BIAS AIO[0]

D2 AIO_0 Analogue Input / Output F E R _ U A 8 A C12 2u2 S A I B _ C I M 9 B N A _ C I M 0 1 A N 1 _ C I M P A _ C I M 9 A P 1 _ C I M P B _ C I M 7 B P 2 _ C I M N B _ C I M 8 B N 2 _ C I M C13 100n C14 100n C15 100n C16 100n N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S 4 B 4 A 6 B 6 A N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S USB_P USB_N H10 J10 RST#

J3 RSTB Reset Dual-microphone Inputs Mic1 Mic2 R2 2k2 MIC_1 L4 15nH MIC_2 L5 15nH R1 2k2 C17 15p C18 15p MIC_BIAS Note :

For a 1.8V Input It Is Impossible to Maintain Mic Bias Performance. CSR Recommends An External Mic Bias Supply If Required. Figure 13.1: External 1.8V Supply Example Application Left Speakers (16 - 32) Right 1 1

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G Page 74 of 114 CS-218182-DSP6 www.csr.com Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Single 3.3V Only Supply. USB, Dual Switch-mode. 3V3_INPUT 1V8_SMPS 1V35_SMPS 1V8_SMPS RSTB C2 2u2 C3 2u2 L1 4u7 C4 2u2 C5 10n C6 10n L2 4u7 C7 4u7 C8 15p C9 2u2 C10 470n C11 100n 5 K G H C V 4 K E L B A N E G E R V 7 K T A B V 6 J 7 J T X E _ G H C E S N E S _ T A B V 9 J B S U _ 3 V 3 GND GND GND 9 H 1 A GND 5 B 6 K 8 V 1 _ X L 8 V 1 _ X U A _ D D V E S N E S _ 8 V 1 _ S P M S V R D _ O I D U A _ D D V 7 A I O D U A _ D D V 2 B X U A _ D D V 8 K 5 3 V 1 _ X L 0 1 K E S N E S _ 5 3 V 1 _ S P M S 2 C I O D A R _ A N A _ D D V 3 K I G D _ N G E R V I 2 K M E M _ G D _ D D V I 5 E 6 E 1 _ S D A P _ D D V 2 _ S D A P _ D D V CHARGER VBAT 1V8 SMPS BYPASS R EG 3V3 1V35 SMPS AUX LDO ANA LDO 1V35 1V35 1V35 ANT 4 IN BT_RF A3 BT_RF Bluetooth RF U2 OUT 2 3 GND GND 1 2.45GHz CSR8645 BGA DIG LDO LED O utputs PIO XTA L_IN C1 XTA L_OUT B1 PIO[29]/LED[0]

PIO[30]/LED[1]

PIO[31]/LED[2]

J2 K1 B10 PIO[0]

PIO[1]

PIO[6]

PIO[7]

PIO[8]

PIO[9]

PIO[18]

PIO[19]

PIO[20]

PIO[21]

F9 F10 E9 G10 E10 G9 D9 C9 C10 D10 PIO[2]/PCM1_IN/SPI_MOSI PIO[3]/PCM1_OUT/SPI_MISO PIO[4]/PCM1_SYNC/SPI_CS#

PIO[5]/PCM1_CLK/SPI_CLK H1 J5 E1 J1 PIO[12] / QSPI_FLASH_CS# / I2C_WP PIO[10] / QSPI_FLASH_CLK / I2C_SCL PIO[11] / QSPI_IO[0] / I2C_SDA PIO[13] / QSPI_IO[1]

E2 F5 G2 G1 F2 D1 F1 H2 PIO[14] / UART_RX PIO[15] / UART_TX PIO[16] / UART_RTS PIO[17] / UART_CTS XT1 26MHz LED_0 LED_1 LED_2 PIO_0 PIO_1 PIO_6 PIO_7 PIO_8 PIO_9 PIO_18 PIO_19 PIO_20 PIO_21 PIO_2 PIO_3 PIO_4 PIO_5 PIO_12 PIO_10 PIO_11 PIO_13 PIO_14 PIO_15 PIO_16 PIO_17 SPI_PCM#

J4 SPI_PCM#

SPI / PCM# High For SPI. Low For All Other Functions PIO / PCM1 / Debug SPI / I2S PIO / Serial Flash / I2C PIO / UART Analogue Input / Output USB (12Mbps) AIO[0]

D2 AIO_0 USB_P USB_N H10 J10 USB_P USB_N RST#

J3 RSTB Reset C S R 8 6 4 5 B G A D a t a S h e e t X U A _ O L _ T B _ S S V F R _ T B _ S S V I G D _ S S V 8 V 1 _ S P M S _ S S V 5 3 V 1 _ S P M S _ S S V I O D U A _ S S V 2 A 3 B 6 F SP100 5 A 8 J 9 K STAR MIC BIAS F E R _ U A 8 A C12 2u2 N A _ C I M 0 1 A N 1 _ C I M P A _ C I M 9 A P 1 _ C I M S A I B _ C I M 9 B S A I B _ C I M C13 100n C14 100n C15 100n C16 100n P B _ C I M 7 B P 2 _ C I M N B _ C I M 8 B N 2 _ C I M R2 2k2 N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S 4 B 4 A 6 B 6 A N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S Left Speakers (16 - 32) Right Dual-microphone Inputs Mic1 Mic2 MIC_1 L4 15nH MIC_2 L5 15nH R1 2k2 C17 15p C18 15p Figure 13.2: External 3.3V Supply Example Application Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012

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G Page 75 of 114 CS-218182-DSP6 www.csr.com USB Audio Dongle. Single Ganged, 1.8V Switch-mode. USB_VBUS DUAL_LX 1V8_SMPS 1V35 1V8_SMPS 1V8_SMPS 0402 C3 2u2 GND 9 J B S U _ 3 V 3 5 K G H C V 4 K E L B A N E G E R V 7 K T A B V 6 J 7 J T X E _ G H C E S N E S _ T A B V L1 4u7 C4 2u2 C5 10n C5 100n C6 470n C8 15p C9 2u2 C10 470n C11 100n GND 9 H 1 A GND GND GND GND 6 K 8 V 1 _ X L 8 V 1 _ X U A _ D D V E S N E S _ 8 V 1 _ S P M S 5 B V R D _ O I D U A _ D D V 7 A O I D U A _ D D V 2 B X U A _ D D V 8 K 5 3 V 1 _ X L 0 1 K E S N E S _ 5 3 V 1 _ S P M S 2 C O I D A R _ A N A _ D D V 3 K G I I D _ N G E R V 2 K M E M _ G I D _ D D V 5 E 6 E 1 _ S D A P _ D D V 2 _ S D A P _ D D V XT1 26MHz CHARGER VBAT 1V8 SMPS BYPASS R EG 3V3 1V35 SMPS AUX LDO ANA LDO 1V35 1V35 1V35 DIG LDO PIO[29]/LED[0]

PIO[30]/LED[1]

PIO[31]/LED[2]

J2 K1 B10 LED_0 LED_1 LED_2 LED outputs ANT 4 IN BT_RF A3 BT_RF Bluetooth RF U2 OUT 2 3 GND GND 1 2.45GHz CSR8645 BGA X U A _ O L _ T B _ S S V F R _ T B _ S S V G I D _ S S V 2 A 3 B 6 F SP100 5 A STAR O I D U A _ S S V 8 V 1 _ S P M S _ S S V 8 J 5 3 V 1 _ S P M S _ S S V 9 K MIC BIAS F E R _ U A 8 A C12 2u2 N A _ C I M 0 1 A N 1 _ C I M P A _ C I M 9 A P 1 _ C I M S A I B _ C I M 9 B S A I B _ C I M C13 100n C14 100n C15 100n C16 100n P B _ C I M 7 B P 2 _ C I M N B _ C I M 8 B N 2 _ C I M R2 2k2 Dual-microphone Inputs Mic1 Mic2 MIC_1 L4 15nH MIC_2 L5 15nH R1 2k2 C17 15p C18 15p Figure 13.3: USB Audio Dongle Example Application N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S 4 B 4 A 6 B 6 A N L _ R K P S P L _ R K P S N R _ R K P S P R _ R K P S Left Speakers (16 - 32) Right Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 XTAL_IN C1 XTAL_OUT B1 PIO[0]

PIO[1]

PIO[6]

PIO[7]

PIO[8]

PIO[9]

PIO[18]

PIO[19]

PIO[20]

PIO[21]

F9 F10 E9 G10 E10 G9 D9 C9 C10 D10 PIO[2]/PCM1_IN/SPI_MOSI PIO[3]/PCM1_OUT/SPI_MISO PIO[4]/PCM1_SYNC/SPI_CS#

PIO[5]/PCM1_CLK/SPI_CLK H1 J5 E1 J1 SPI_PCM#

J4 PIO[12] / QSPI_FLASH_CS# / I2C_WP PIO[10] / QSPI_FLASH_CLK / I2C_SCL PIO[11] / QSPI_IO[0] / I2C_SDA PIO[13] / QSPI_IO[1]

E2 F5 G2 G1 F2 D1 F1 H2 PIO[14] / UART_RX PIO[15] / UART_TX PIO[16] / UART_RTS PIO[17] / UART_CTS R105 2k2 R106 2k2 R107 2k2 1V8_SMPS C100 U101 VCC WP SCL SDA 8 7 6 5 10n A0 A1 A2 VSS 1 2 3 4 24AAxxx AIO[0]

D2 USB_P USB_N H10 J10 USB_P USB_N RST#

J3 USB (12Mb/ s) C S R 8 6 4 5 B G A D a t a S h e e t

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G Page 76 of 114 CS-218182-DSP6 www.csr.com 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Rating Storage temperature Supply Voltage Charger VCHG LEDs LED[2:0]

Battery VBAT_SENSE VREGENABLE VDD_AUDIO_DRV VDD_AUX_1V8 VDD_PADS_2 VDD_AUX_1V8 SMPS_1V35_SENSE 1.8V VDD_PADS_1 1.35V VDD_AUDIO VREGIN_DIG Min

-40

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4 Max 105 5.75 4.40 4.20 4.40 1.95 1.95 3.60 3.60 1.95 1.45 1.45 1.95 Unit C V V V V V V V V V V V V V C S R 8 6 4 5 B G A D a t a S h e e t Other terminal voltages VSS - 0.4 VDD + 0.4 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 77 of 114 CS-218182-DSP6 www.csr.com 14.2 Recommended Operating Conditions Charger VCHG 4.75 / 3.10 Rating Operating temperature range Supply Voltage LEDs LED[2:0]

Battery 1.8V VDD_PADS_1 VBAT_SENSE VREGENABLE VDD_AUDIO_DRV VDD_AUX_1V8 VDD_PADS_2 VDD_AUX_1V8 SMPS_1V35_SENSE Min

-40 1.10 0 0 1.70 1.70 1.70 1.70 1.25 1.30 1.30 1.30 Typ 20 5.00 3.70 3.70 3.70 1.80 1.80 1.80 1.80 1.80 1.35 1.35 Max 85 5.75 4.25 4.30 4.25 1.95 1.95 3.60 3.60 1.95 1.40 1.40 1.95 Unit C V V V V V V V V V V V V 1.35V VDD_AUDIO VREGIN_DIG 1.35 or 1.80 C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 78 of 114 CS-218182-DSP6 www.csr.com 14.3 Input/Output Terminal Characteristics Note:

For all I/O terminal characteristics:

14.3.1 Regulators: Available For External Use 14.3.1.1 1.8V Switch-mode Regulator Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative. 1.8V Switch-mode Regulator Input voltage Output voltage Normal Operation Transient settling time Load current Peak conversion efficiency(b) Switching frequency Transient settling time Load current Current available for external use Peak conversion efficiency Current available for external use, audio with 16 load(a) Inductor saturation current, audio and 16 load Inductor ESR 0.3 0.8 Low-power Mode, Automatically Entered in Deep Sleep 4.00 MHz Min 2.80 1.70

3.63 250 0.1 0.005 Typ 3.70 1.80 30 90 4.00 200 85

Max 4.25 1.90 185 25

5 5

Unit V V s mA mA

mA s mA mA

C S R 8 6 4 5 B G A D a t a S h e e t Switching frequency 100 200 kHz

(a) More current available for audio loads above 16.

(b) Conversion efficiency depends on inductor selection. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 79 of 114 CS-218182-DSP6 www.csr.com 14.3.1.2 Combined 1.8V and 1.35V Switch-mode Regulator Combined 1.8V and 1.35V Switch-mode Regulator Input voltage Output voltage Normal Operation Transient settling time Load current Current available for external use, audio with 16 load(a) Peak conversion efficiency(b) Switching frequency Inductor saturation current, audio and 16 load Transient settling time Load current Current available for external use Peak conversion efficiency

(a) More current available for audio loads above 16.

(b) Conversion efficiency depends on inductor selection. Min 2.80 1.70

3.63 400 0.1 0.005 Typ 3.60 1.80 30 90 4.00 200 85

Max 4.25 1.90 340 25

5 5

Unit V V s mA mA

mA s mA mA

4.00 MHz C S R 8 6 4 5 B G A D a t a S h e e t Inductor ESR 0.3 0.8 Low-power Mode, Automatically Entered in Deep Sleep Switching frequency 100 200 kHz Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 80 of 114 CS-218182-DSP6 www.csr.com

(a) Minimum input voltage of 4.75V is required for full specification, regulator operates at reduced load current from 3.1V. 14.3.2 Regulators: For Internal Use Only 14.3.2.1 1.35V Switch-mode Regulator 14.3.1.3 Bypass LDO Regulator Normal Operation Input voltage(a) Output voltage (Vin > 4.75V) Output current (Vin > 4.75V) 1.35V Switch-mode Regulator Input voltage Output voltage Normal Operation Transient settling time Load current Current available for external use Peak conversion efficiency(a) Switching frequency Transient settling time Load current Current available for external use Peak conversion efficiency 4.75 / 3.10 Min 3.00

Min 2.80 1.30

3.63 220 0.1 0.005 Typ 5.00 3.30

Typ 3.60 1.35 30 88 4.00 200 85

Max 5.25 3.60 250 Max 4.25 1.40 160

0

5 0

Unit V V mA Unit V V s mA mA

mA s mA mA

C S R 8 6 4 5 B G A D a t a S h e e t Inductor saturation current, audio and 16 load Inductor ESR 0.3 0.8 Low-power Mode, Automatically Entered in Deep Sleep 4.00 MHz Switching frequency 100 200 kHz

(a) Conversion efficiency depends on inductor selection. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 81 of 114 CS-218182-DSP6 www.csr.com 14.3.2.2 Low-voltage VDD_DIG Linear Regulator

(a) Output voltage level is software controlled 14.3.2.3 Low-voltage VDD_AUX Linear Regulator 14.3.2.4 Low-voltage VDD_ANA Linear Regulator Normal Operation Input voltage Output voltage(a) Internal load current Normal Operation Input voltage Output voltage Internal load current Normal Operation Input voltage Output voltage Load current 14.3.3 Regulator Enable VREGENABLE, Switching Threshold Rising threshold 14.3.4 Battery Charger Battery Charger Input voltage, VCHG(a)

(a) Reduced specification from 3.1V to 4.75V. Full specification >4.75V. Min 1.30 0.80

Min 1.70 1.30

Min 1.70 1.30 Min 1.0 Min 4.75 / 3.10 Typ 1.35 or 1.80 0.90 / 1.20

Typ 1.80 1.35 Typ 1.80 1.35 Typ

Typ 5.00 Max 1.95 1.25 80 Max 1.95 1.45 5 Max 1.95 1.45 60 Max

Max 5.75 Unit V V mA Unit V V mA Unit V V mA Unit V Unit V C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 82 of 114 CS-218182-DSP6 www.csr.com Trickle Charge Mode Min Charge current Itrickle, as percentage of fast charge current Vfast rising threshold Vfast rising threshold trim step size Vfast falling threshold Fast Charge Mode Charge current during constant current mode, Ifast Maximum charge setting

(VCHG-VBAT > 0.55V) Minimum charge setting

(VCHG-VBAT > 0.55V) Reduced headroom charge current, as a percentage of Ifast

(VCHG-VBAT < 0.55V) 50 Charge current step size Vfloat threshold, calibrated Charge termination current Iterm, as percentage of Ifast Standby Mode Voltage hysteresis on VBAT, Vhyst Error Charge Mode Headroom(a) error falling threshold

(a) Headroom = VCHG - VBAT Typ 10 2.9 0.1 2.8 Typ 200 10

10 4.20 10 Typ

Typ 50 Max 12

Max 206 100 4.24 20 Max 150 Max

Unit

V V V Unit mA mA

mA V

Unit mV Unit mV 8

7 Min 194 4.16 Min 100 Min

C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 83 of 114 CS-218182-DSP6 www.csr.com Sense voltage, between VBAT_SENSE and VBAT at maximum current 205 mV

(a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical External Charge Mode(a) Fast charge current, Ifast Control current into CHG_EXT Voltage on CHG_EXT External pass device hfe characteristics are listed in this table. 14.3.5 USB 3V3_USB for correct USB operation Input Threshold VIL input logic level low VIH input logic level high VOL output logic level low VOH output logic level high 14.3.6 Clocks Crystal Oscillator Frequency Crystal load capacitance Frequency stability Frequency tolerance Transconductance Min 200 0 0

195 Min 3.1

0 2.8 Min 16

2 Typ

50 200 Typ 3.3

9

Typ 26 Max 500 20 5.75

Max 3.6

0.2 Max 32 20 20

0.3 x 3V3_USB 3V3_USB Unit mA mA V

Unit V V V V V Unit MHz pF ppm ppm mS C S R 8 6 4 5 B G A D a t a S h e e t Output Voltage Levels to Correctly Terminated USB Cable 0.7 x 3V3_USB Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 84 of 114 CS-218182-DSP6 www.csr.com 14.3.7 Stereo Codec: Analogue to Digital Converter Conditions Min Typ Max Analogue to Digital Converter Parameter Resolution Input Sample Rate, Fsample

fin = 1kHz B/W = 20HzFsample/2

(20kHz max) A-Weighted THD+N < 0.1%

1.6Vpk-pk input fin = 1kHz B/W = 20HzFsample/2

(20kHz max) 1.6Vpk-pk input Fsample 8kHz 16kHz 32kHz 44.1kHz 48kHz Fsample 8kHz 48kHz SNR THD+N Digital gain Digital gain resolution = 1/32 Analogue gain Pre-amplifier setting = 0dB, 9dB, 21dB or 30dB Analogue setting = -3dB to 12dB in 3dB steps Stereo separation (crosstalk)

-88.5

8

-24

-3 93.5 92.5 91.4 90.4 89.6 0.0041 0.0072

16 48

21.5 42 Unit Bits kHz dB dB dB dB dB

dB dB dB C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 85 of 114 CS-218182-DSP6 www.csr.com 14.3.8 Stereo Codec: Digital to Analogue Converter Parameter Conditions Min Typ Max Digital to Analogue Converter Resolution Output Sample Rate, Fsample

SNR fin = 1kHz B/W = 20Hz20kHz A-Weighted THD+N < 0.1%

0dBFS input THD+N fin = 1kHz B/W = 20Hz20kHz 0dBFS input Fsample Load 48kHz 100k 48kHz 48kHz 32 16 Fsample Load 8kHz 100k 48kHz 100k 8kHz 8kHz 48kHz 48kHz 32 16 32 16

8

-24

-21

95.6 95.8 95.6 0.0025 0.0056 0.0108 0.0027 0.0067 0.0122

-87.5 16 96

0

Unit Bits kHz dB dB dB

dB dB dB C S R 8 6 4 5 B G A D a t a S h e e t Digital Gain Digital Gain Resolution = 1/32 21.5 Analogue Gain Analogue Gain Resolution = 3dB Stereo separation (crosstalk) Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 86 of 114 CS-218182-DSP6 www.csr.com 14.3.9 Digital Digital Terminals Input Voltage VIL input logic level low VIH input logic level high Tr/Tf Output Voltage Tr/Tf Input and Tristate Currents Strong pull-up Strong pull-down Weak pull-up Weak pull-down CI Input Capacitance VOL output logic level low, lOL = 4.0mA VOH output logic level high, lOH = -4.0mA 0.75 X VDD Min Typ Max Unit 0.7 x VDD VDD + 0.4

-0.4

-150 10

-5 0.33 1.0

-40 40

-1.0 1.0

0.4 25 0.4

5

-10 150

-0.33 5.0 5.0 V V ns V V ns A A A A pF C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 87 of 114 CS-218182-DSP6 www.csr.com 14.3.10 LED Driver Pads LED Driver Pads Current, IPAD High impedance state Current sink state LED pad voltage, VPAD IPAD = 10mA LED pad resistance VPAD < 0.5V

(a) LED output port is open-drain and requires a pull-up 14.3.11 Auxiliary ADC VOL output logic level low(a) VOH output logic level high(a) VIL input logic level low VIH input logic level high Auxiliary ADC Resolution Input voltage range(a) Accuracy

(Guaranteed monotonic) Offset Gain error Input bandwidth Conversion time Sample rate(b) Min Typ Max Unit A mA V V V V V Unit Bits LSB LSB LSB

kHz s 5 10 0.55 40

Max 10 1 1 1

0.8 2.75

0

-1 0

-1

-0.8 1.38

0 0 0.8 0.8

100 1.69 Min Typ VDD_AUX V INL DNL

(a) LSB size = VDD_AUX/1023

(b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function. 700 Samples/s C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 88 of 114 CS-218182-DSP6 www.csr.com Supply voltage, VDD_AUX 1.30 1.35 14.3.12 Auxiliary DAC Auxiliary DAC Resolution Output voltage range Full-scale output voltage LSB size Offset Integral non-linearity Settling time(a)

(a) The settling time does not include any capacitive load Min Typ VDD_AUX Max 10 1.40 1.40 2.64 1.32 1 250 Unit Bits V V V mV mV LSB ns 1.35 1.32

0 0

0 0

-1

1.30

-1.32 C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 89 of 114 CS-218182-DSP6 www.csr.com 14.4 ESD Protection Apply ESD static handling precautions during manufacturing. Table 14.1 shows the ESD handling maximum ratings. Condition Class Max Rating Human Body Model Contact Discharge per ANSI/ESDA/JEDEC JS001 2 2kV (all pins except CHG_EXT; CHG_EXT is rated at 1kV) Machine Model Contact Discharge per JEDEC/EIA JESD22A115 200V 200V (all pins) Charged Device Model Contact Discharge per JEDEC/EIA JESD22C101 III 500V (all pins) 14.4.1 USB Electrostatic Discharge Immunity Table 14.1: ESD Handling Ratings CSR8645 BGA has integrated ESD protection on the USB_DP and USB_DN pins as detailed in IEC 6100042. CSR has tested CSR8645 BGA assembled in development kits to assess the Electrostatic Discharge Immunity. The tests were based on IEC 6100042 requirements. Tests were performed up to level 4 (8kV contact discharge / 15kV air discharge). CSR can demonstrate normal performance up to level 2 (4kV contact discharge / 4kV air discharge) as per IEC 6100-4-2 classification 1. Above level 2, temporary degradation is seen (classification 2). CSR8645 BGA contains a reset protection circuit and software, which will attempt to re-make any connections lost in a ESD event. If the device at the far end permits this, self-recovery of the Bluetooth link is possible if CSR8645 BGA resets on an ESD strike. This classes CSR8645 BGA as IEC 6100042 classification 2 to level 4 (8kV contact discharge / 15kV air discharge). If self-recovery is not implemented, CSR8645 BGA is IEC 6100042 classification 3 to level 4. Any test detailed in the IEC-61000-4-2 level 4 test specification does not damage CSR8645 BGA. The CSR8645 BGA USB VBUS pin is protected to level 4 using an external 2.2F decoupling capacitor on VCHG. Note:

Important Note:

CSR recommends correct PCB routing and to route the VBUS track through a decoupling capacitor pad. When the USB connector is a long way from CSR8645 BGA, place an extra 1F or 2.2F capacitor near the USB connector. No components (including 22 series resistors) are required between CSR8645 BGA and the USB_DP and USB_DN lines. To recover from an unintended reset, e.g. a large ESD strike, the watchdog and reset protection feature can restart CSR8645 BGA and signal the unintended reset to the VM. Table 14.2 summarises the level of protection. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 90 of 114 CS-218182-DSP6 www.csr.com IEC 6100042 Level ESD Test Voltage

(Positive and Negative) IEC 6100042 Classification Comments 1 2 3 4 2kV contact / 2kV air Class 1 4kV contact / 4kV air Class 1 6kV contact / 8kV air Class 2 or class 3 8kV contact / 15kV air Class 2 or class 3 Normal performance within specification limits Normal performance within specification limits Temporary degradation or operator intervention required Temporary degradation or operator intervention required For more information contact CSR. Table 14.2: USB Electrostatic Discharge Protection Level C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 91 of 114 CS-218182-DSP6 www.csr.com 15 Power Consumption DUT Role Connection Packet Type Packet Size Slave Slave Slave SCO eSCO eSCO Slave SCO HV3 EV3 2EV3 HV3 30 30 60 30 Average Current 11.0 11.8 9.2 12.6 Unit mA mA mA mA 2-mic CVC:

8kHz sampling Narrowband 2-mic CVC:

8kHz sampling Narrowband 2-mic CVC:

Wideband 16kHz sampling 2-mic CVC:

16kHz sampling FESI Slave eSCO 2EV3 60 10.8 mA Slave eSCO 2EV3 60 11.4 mA Slave eSCO 2EV3 60 10.9 mA Slave Slave Slave Stereo high quality SBC:

Joint stereo Bit-Pool = 50, 16 blocks and 8 sub-

bands 48kHz sampling No sniff White noise Stereo low quality SBC:

Joint stereo Bit-Pool = 20, 16 blocks and 8 sub-

bands 48kHz sampling No sniff White noise Stereo high quality MP3:

White noise 192kbps 48kHz sampling No sniff

13.3 mA 11.8 mA 12.5 mA Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 92 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t DUT Role Connection Packet Type Packet Size Unit Average Current Stereo low quality MP3:

White noise 96kbps 48kHz sampling No sniff ACL ACL Sniff = 500ms Sniff = 1280ms Slave Slave Slave Master SCO Master eSCO Master eSCO Master SCO

HV3 EV3 2EV3 HV3

30 30 60 30 11.8 mA 213 142 10.8 11.2 8.8 12.5 A A mA mA mA mA Master eSCO 2EV3 60 10.5 mA Master eSCO 2EV3 60 11.0 mA Master eSCO 2EV3 60 10.6 mA 2-mic CVC:

8kHz sampling Narrowband 2-mic CVC:

8kHz sampling Narrowband 2-mic CVC:

Wideband 16kHz sampling 2-mic CVC:

16kHz sampling FESI C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 93 of 114 CS-218182-DSP6 www.csr.com DUT Role Connection Packet Type Packet Size Unit Average Current Stereo high quality SBC:

Joint stereo Bit-Pool = 50, 16 blocks and 8 sub-

bands 48kHz sampling No sniff White noise Stereo low quality SBC:

Joint stereo Bit-Pool = 20, 16 blocks and 8 sub-

bands 48kHz sampling No sniff White noise Stereo high quality MP3:

White noise 192kbps 48kHz sampling No sniff Stereo low quality MP3:

White noise 96kbps 48kHz sampling No sniff ACL ACL Sniff = 500ms Sniff = 1280ms

Master Master Master Master Master Master Note:

Current consumption values are taken with:

VBAT pin = 3.7V RF TX power set to 0dBm No RF retransmissions in case of eSCO Microphones and speakers disconnected Audio gateway transmits silence when SCO/eSCO channel is open LEDs disconnected AFH classification master disabled 13.2 mA 10.9 mA 11.8 mA 10.8 mA 197 142 A A C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 94 of 114 CS-218182-DSP6 www.csr.com 16 CSR Green Semiconductor Products and RoHS Compliance CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:

Restriction on Hazardous Substances directive guidelines in the EU RoHS Directive 2002/95/EC. This includes compliance with the requirements for Deca BDE, as per removal of exemption, implementation date 01-Jul-08 EU REACH, Regulation (EC) No 1907/2006:

List of substances subject to authorisation (Annex XIV) Restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (Annex XVII). This Annex now includes requirements that were contained within EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not limited to, the control of use of Perfluorooctane sulfonates (PFOS). Substances identified on candidate list as Substances of Very High Concern (SVHC), 53 substances as per update published 20 June 2011. EU Commission Decision 2009/251/EC:

EU Packaging and Packaging Waste, Directive 94/62/EC Montreal Protocol on substances that deplete the ozone layer Products containing dimethylfumarate (DMF) are not placed or made available on the market. Additionally, Table 16.1 shows that CSR Green semiconductor products are free from bromine, chlorine or antimony trioxide and other hazardous chemicals. Material Cadmium (Cd) Lead (Pb) Mercury (Hg) Hexavalent-Chromium (Cr VI) Polybrominated biphenyls (PBB) Polybrominated diphenyl ethers (PBDE) Bromine, Chlorine Antimony Trioxide (Sb2O3) Benzene Beryllium and compounds (other than Beryllium Oxide (BeO) Halogenated Diphenyl Methanes

(Monomethyltetrachloro Diphenyl Methane (CAS# 76253-60-6), Monomethyldichloro Diphenyl Methane (CAS# 81161-70-8), Monomethyldibromo Diphenyl Methane (CAS# 99788-47-8) Red phosphorous 1,1,1-trichloroethane Maximum Allowable Amount 1000ppm (solder), 100ppm (plastic) 900ppm, <1500ppm combined 100ppm 1000ppm 1000ppm 1000ppm 1000ppm 900ppm 1000ppm 1000ppm 1000ppm 1000ppm Banned Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 95 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Material Maximum Allowable Amount Aliphatic CHCs (chlorohydrocarbons) Benzotriazole (2-3',5'-Di-tert-butyl-2'-hydroxyphenyl) Beryllium Oxide Chlorinated paraffin (including short chain chlorinated paraffins carbon chain length 10-13 and medium chain chlorinated paraffins carbon chain length 14-17) Formaldehyde

(Banned in wooden, adhesive and plastic products) Banned as described NPs (nonylphenols) and NPEs (nonylphenol ethoxylates)

(Banned in textile, leather, metal, pulp and paper parts) Banned as described Hydrofluorocarbon (HFC) Organic tin compounds Perfluorocarbon (PFC) Polychlorinated napthalenes (PCN) Polychlorinated terphenyls (PCT) Polychlorinated biphenyls (PCB) Polyvinyl Chloride (PVC) Sulfur hexafluoride Tetrachloromethane (CAS# 56-23-5) Asbestos Phthalates Banned Banned Banned Banned Banned Banned Banned Banned Banned Banned Banned Banned Banned Banned as intentionally introduced Banned as intentionally introduced Radioactive substances Banned as intentionally introduced: reportable Tributyl tin (TBT) / Triphenyl tin (TPT) / Tributyl Tin Oxide (TBTO) Dibutyl Tin (DBT) and Dioctyl Tin Compounds (DOT) Banned as intentionally introduced Table 16.1: Chemical Limits for Green Semiconductor Products Products and shipment packaging are marked and labelled with applicable environmental marking symbols in accordance with relevant regulatory requirements. CSR has defined this Green standard based on current regulatory and customer requirements. For more information contact product.compliance@csr.com. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 96 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t 17 Software CSR8645 BGA:

Includes integrated Bluetooth v4.0 specification qualified HCI stack firmware Includes integrated CSR8645 Stereo ROM Solution with aptX, with 6th generation 2-mic CVC audio enhancements and a configurable EQ Can be shipped with CSRs CSR8645 stereo ROM solution with aptX development kit for CSR8645 BGA, order code DK-8645-10064-1A The CSR8645 BGA software architecture enables Bluetooth processing and the application program to run on the internal RISC MCU, and the audio enhancements on the Kalimba DSP. 17.1 CSR8645 Stereo ROM Solution with aptX The CSR8645 stereo ROM solution with aptX software supports:

6th generation 2-mic CVC audio enhancements PLC / BEC WNR mSBC wideband speech codec A2DP v1.2 HFP v1.6 and HSP v1.2 SCMS-T Bluetooth v4.0 specification is supported in the ROM software Secure simple pairing Proximity pairing (headset-initiated pairing) for greatly simplifying the out-of-box pairing process, for more information see Section 17.1.8 For connection to more than 1 mobile phone, advanced Multipoint is supported. This enables a user to take calls from a work and personal phone or a work phone and a VoIP dongle for Skype users. This has minimal impact on power consumption and is easy to configure. Most of the CSR8645 stereo ROM solution with aptX ROM software features are configured on the CSR8645 BGA using the Headset Configurator tool. The tool reads and writes headset configurations directly to the EEPROM, serial flash or alternatively to a PSR file. Configurable headset features include:

Bluetooth v4.0 specification features Reconnection policies, e.g. reconnect on power-on Audio features, including default volumes Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1] for last number redial LED indications for states, e.g. headset connected, and events, e.g. power on Indication tones for events and ringtones HFP v1.6 supported features Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc. Advanced Multipoint settings Configurable 5-band EQ for music playback (rock, pop, classical, jazz, dance etc) aptX, AAC, SBC, MP3 and Faststream decoder Stereo widening (S3D) Volume Boost USB audio mode for streaming high-quality music from a PC whilst charging, enables the headset to:

Playback high-quality stereo music, e.g. iTunes Use bidirectional audio in conversation mode, e.g. for Skype C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 97 of 114 CS-218182-DSP6 www.csr.com Wired audio mode for pendant-style headsets supports music playback using a line-in jack. Enables non Bluetooth operation in low battery modes or when using the headset in an airplane-mode. Support for smartphone applications (apps) The CSR8645 stereo ROM solution with aptX has undergone extensive interoperability testing to ensure it works with the majority of phones on the market 17.1.1 Advanced Multipoint Support Advanced Multipoint enables the connection of 2 devices to a CSR8645 BGA headset at the same time, examples include:

2 phones connected to a CSR8645 BGA headset Phone and a VoIP dongle connected to a CSR8645 BGA headset Phone and tablet The CSR8645 stereo ROM solution with aptX:

Supports up to 2 simultaneous connections (either HFP or HSP) Enables multiple-call handling from both devices at the same time Treats all headset buttons:

During a call from one device, as if there is 1 device connected During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (three-

way calling) During multiple calls (more than 1 on each device), as if there are multiple calls on a single device enabling the user to switch between the active and held calls 17.1.2 A2DP Multipoint Support A2DP Multipoint support enables the connection of 2 A2DP source devices to CSR8645 BGA at the same time, examples include:

2 A2DP-capable phones connected to a CSR8645 BGA headset A2DP-capable phone and an A2DP-only source device, e.g. a PC or an iPod touch The CSR8645 stereo ROM solution with aptX enables:

Music streaming from either of the connected A2DP source devices where the music player is controlled on the source device Advanced HFP Multipoint functions to interrupt music streaming for calls, and resume music streaming on the completion of the calls AVRCP v1.4 connections to both connected devices, enabling the headset to remotely control the primary device, i.e. the device currently streaming audio 17.1.3 Wired Audio Mode CSR8645 BGA supports a wired audio mode for playing music over a wired connection. This enables the headset to operate when the battery is too low for Bluetooth operation or in environments where the use of wireless technologies is not permitted, e.g. airplane-mode. The CSR8645 stereo ROM solution with aptX automatically routes the wired audio input to the headphone output when CSR8645 BGA is not powered. If CSR8645 BGA is powered, the audio path is routed through CSR8645 BGA, including via the DSP, this enables the headset to:

Mix audio sources, e.g. tones and programmable audio prompts Control the volume of the audio, i.e. volume up and volume down Utilise the 5 band EQ The wired audio mode can be used in conjunction with the USB audio mode, see Section 17.1.4. USB audio has priority if attached and is routed to the headset speaker if CSR8645 BGA is powered. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 98 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t In wired audio mode, if required, the headset is still available for Bluetooth audio. This enables seamless transition from wired audio mode to Bluetooth audio mode and back again. This transition is configurable to occur automatically as the battery voltage of the headset reduces to a point at which Bluetooth audio is no longer possible. The additional development board CNS11010 enables support for the wired input mode and is available as part of the development kit. 17.1.4 USB Modes Including USB Audio Mode CSR8645 BGA supports a variety of USB modes which enables the USB interface to extend the functionality of a CSR8645 BGA based stereo headset. CSR8645 BGA supports:

USB charger enumeration USB soundcard enumeration (USB audio mode) USB mass storage enumeration USB audio mode enables the headset to enumerate as a soundcard while charging from a USB master device, e.g. a PC. In this mode, the headset enumerates as either a stereo music soundcard (for high quality music playback) or a bidirectional voice quality soundcard. This enables the headset for either listening to music streaming from the USB host device or for voice applications, e.g. Skype. The USB audio mode operates at the same time as the wired audio mode and the USB audio interrupts the wired audio mode if USB audio is attached. This enables a headset to have both wired audio and USB modes connected at the same time. In USB audio mode, if required, the headset is still available for Bluetooth audio. 17.1.5 Smartphone Applications (Apps) CSR8645 BGA includes CSRs proprietary mechanism for communicating with smartphone apps, it enables full UI control of the headset from within the application running on a smartphone, e.g. Google Android OS-based handset. For more information on this feature contact CSR. 17.1.6 Programmable Audio Prompts CSR8645 BGA enables a user to configure and load pre-programmed audio prompts from:

An external EEPROM, in this implementation the prompts are stored in the same EEPROM as the PS Keys, see Figure 17.2. A larger EEPROM is necessary for programmable audio prompts. This implementation supports EEPROMs up to 512Kb. An EEPROM of 512Kb enables approximately 15 seconds of audio storage. An external SPI flash, in this implementation the prompts are stored in the same SPI flash as the PS Keys, see Figure 17.1. The programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone indications. A programmable audio prompt is assigned to any user event in place of a standard tone. Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-

defined higher quality ring tones/indications, e.g. custom power on/off tones. The Headset Configurator tool can generate the content for the programmable audio prompts from standard WAV audio files. The tool also enables the user to configure which prompts are assigned to which user events. Section 6.5 describes the SPI flash interface and Section 7.4 describes the IC interface to an external EEPROM. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 99 of 114 CS-218182-DSP6 www.csr.com CSR8645 SPI CSR8645 I2C SPI Flash PS Keys Configuration Patches Programmable Audio Prompts EEPROM PS Keys Configuration Patches Programmable Audio Prompts Figure 17.1: Programmable Audio Prompts in External SPI Flash 1

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G C S R 8 6 4 5 B G A D a t a S h e e t Figure 17.2: Programmable Audio Prompts in External IC EEPROM When using the SPI flash interface for programmable audio prompts, an EEPROM device is not required in the CSR8645 stereo ROM solution with aptX. 17.1.7 CSRs Intelligent Power Management IPM extends the available talk time of a CSR8645 BGA-based headset, by automatically reducing the audio processing performed by CVC at a series of low battery capacity thresholds. Configurable IPM features include:

IPM enable/disable The battery capacity that engages IPM A user-action to enable or disable the IPM If engaged, CVC processing reduces automatically on reaching the preset battery capacity. Once the audio is terminated, the DSP shuts down to achieve maximum power savings before the next call. IPM resets when recharging the headset. The talk time extension depends on:

The battery size The battery condition The threshold capacity configured for the IPM to engage Note:

Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 100 of 114 CS-218182-DSP6 www.csr.com 17.1.8 Proximity Pairing Proximity pairing is headset-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables the headset to find the closest discoverable phone. The headset then initiates the pairing activity and the user simply has to accept the incoming pairing invitation on the phone. This means that the phone-user does not have to hunt through phone menus to pair with the new headset. Depending on the phone UI:

For a Bluetooth v2.0 phone the headset pairing is with a PIN code For a Bluetooth v2.1 (or above) phone the headset pairing is without a PIN code Proximity pairing is based on finding and pairing with the closest phone. To do this, the headset finds the loudest phone by carrying out RSSI power threshold measurements. The loudest phone is the one with the largest RSSI power threshold measurement, and it is defined as the closest device. The headset then attempts to pair with and connect to this device. Proximity pairing is configurable using the Headset Configurator tool available from www.csrsupport.com. 17.1.9 Proximity Connection Proximity connection is an extension to proximity pairing, see Section 17.1.8. It enables the headsetuser to take advantage of the proximity of devices each time the headset powers up and not just during a first time pairing event. Proximity connection enables a user with multiple handsets to easily connect to the closest discoverable phone by comparing the proximity of devices to the headset at power-on to the list of previously paired devices. Proximity connection speeds up the headset connection process. It requires the headset to initiate a SLC connection to the nearest device first and combines this with the headset's storage of the last 8 paired/connected devices. Using proximity connection means functions like power on into an incoming call operate equally well for the most recently paired or connected device, as well as the least recently paired or connected device. 6th Generation 2-mic CVC Audio Enhancements 17.2 Important Note:

It is important to follow the industrial design considerations in CVC Two Microphone Headset Design Guidelines when designing headsets using 2-mic CVC. 2-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms developed to ensure easy design and build of echo and noisecancelling headset products. CVC enables greater acoustic design flexibility by incorporating software to compensate for cost-optimised microphonetospeaker coupling and placement. CVC-enabled headsets operate in a wide variety of acoustic environments. Sophisticated noise suppression technology reduces the impact of noise in the transmission channel. Using intelligent volume control and intelligibility improvements, the receive channel is also enhanced based on the acoustic noise in the listener's environment. The 6th generation CVC provides 3 new major features:

A high performance Wind Noise Reduction module provides significant reduction of both front and side wind noise. This uses a very low-power algorithm which automatically cuts in only on the detection of wind noise. A 16kHz sample rate for full compliance across the suite of DSP algorithms Frequency enhanced speech intelligibility 2-mic CVC includes a tuning tool enabling the developer to easily adapt CVC with different audio configurations and tuning parameters. The tool provides real-time system statistics with immediate feedback enabling designers to quickly investigate the effect of changes. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 101 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Figure 17.3 shows the functional block diagram of CSRs proprietary 2-mic CVC DSP solution for a dual-microphone headset product. Wind Noise Reduction Dual-microphone Signal Separation Noise Suppression Acoustic Echo Canceller Comfort Noise Equaliser AGC Mic Gain Side Tone NDVC Auxiliary Stream Mix l t t B u e o o h R a d o i 2

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G DAC Clipper AGC Equaliser Adaptive Equaliser Noise Suppression Packet Loss Concealment Section 17.2.3 to Section 17.2.13 describe the audio processing functions provided within CVC. Figure 17.3: 2-mic CVC Block Diagram 17.2.1 Wind Noise Reduction The wind noise algorithm achieves excellent wind noise reduction with very low power overhead, which has a negligible impact on battery life. The wind noise capability operates in the noise suppression block in the transmit path and dynamically detects and engages when wind noise is present. SNR improvements depend on wind direction, speech and microphone placement. Improvements of up to 32dB are achievable using the DSP module. CVC wind noise performance is further improved by suitable mechanical baffling of the microphone which is optimised during the tuning process. 17.2.2 Dual-microphone Signal Separation The dual-microphone signal separation is the major dynamic noise suppression block in 2-mic CVC. It separates the speech from the competing noises. It achieves this by first applying a pre-stage algorithm using a blind source separation processing technique. Blind source separation is a rules based filter which uses the 2 microphones' spatial information, direction of arrival and power ratios assumptions etc. Blind source separation results in speech (S1) and noise (S2) dominant outputs. These outputs are then processed by a post stage adaptive noise canceller filter to further reduce the environmental noise, resulting in a single-channel noise suppressed output. Depending on the acoustic arrangement of the microphone and the noise type, the dual-

microphone signal separation block provides up to 22dB SNR of dynamic noise suppression. 17.2.3 Noise Suppression The noise suppression block is implemented in both signal paths. It is independent and is individually tuned. Noise suppression is a sub-band stationary / quasi-stationary noise suppression algorithm that uses the temporal characteristics of speech and noise to remove the noise from the composite signal while maximising speech quality. The current implementation can improve the SNR by up to 20dB. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 102 of 114 CS-218182-DSP6 www.csr.com 17.2.4 Acoustic Echo Cancellation The AEC includes:

A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to the microphone input A Non-Linear Echo Reduction feature to address severe and distorted echo in speakerphones and car-kits. CVC measures the amount of residual echo after the primary AEC adaptive filter. If the residual echo exceeds a threshold, the NLER function will insert attenuation during far end speech activity, significantly reducing the echo. Creates a spectrally and temporally consistent noise floor for the far-end listener. Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when the non-linear processing of the AEC applies attenuation. The noise level applied is user-controllable. 17.2.5 Comfort Noise Generator The CNG:

17.2.6 Equalisation The equalisation filters:

17.2.7 Automatic Gain Control The AGC block attempts to:

Have independent equalisation modules provided in the send and receive signal paths:

Each module comprises of 5 bands of equalisation using cascaded 2nd order IIR filters Are fully configurable using a graphical tuning tool Provide static compensation for the frequency response of transducers in the system Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness Reduce distortion due to clipping Reduce amplitude variance observed from different users, phones and networks Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also provides the subsequent processing block a larger amplitude signal to process. The behaviour of the AGC differs from a dynamic range audio compressor. The convergence time for the AGC is much slower to reduce the non-

linear distortion. 17.2.8 Packet Loss Concealment Bit errors and packet loss can occur in the Bluetooth transmission due to a variety of reasons, e.g. Wi-Fi interference or RF signal degradation due to distance or physical objects. As a result of these errors, the user hears glitches referred to as pops and clicks in the audio stream. The PLC block improves the receive path audio quality in the presence of bit and packet errors within the Bluetooth link by using a variety of techniques such as pitch-based waveform substitution. The PLC significantly improves dealing with bit errors, using the BFI output from the firmware. The DSP calculates an average BER and selectively applies the PLC to the incoming data. This optimises audio quality for a variety of bit errors and packet loss conditions. The PLC is enabled in all modes. 17.2.9 Adaptive Equalisation The adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of nearend noise by altering the spectral shape of the receive path signal while maintaining the overall power level. The adaptive equaliser can also compensate for variations in voice transmission channels. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 103 of 114 CS-218182-DSP6 www.csr.com 17.2.10 Auxiliary Stream Mix The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice prompts with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents any speech from being lost. 17.2.11 Clipper The clipper block intentionally limits the amplitude of the receive signal prior to the reference input of the AEC to more accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier and the loudspeaker. This processing block can significantly improve the echo performance in cost-optimised loudspeakers. 17.2.12 Noise Dependent Volume Control The NDVC block improves the intelligibility of the receive path signal by increasing the analogue DAC gain value based on the send noise estimate from the send path noise suppression block. As the send noise estimate increases, the NDVC algorithm increases the analogue DAC gain value. The NDVC uses hysteresis to minimise the artefacts generated by rapidly adjusting the DAC gain due to the fluctuation in the environmental noise. 17.2.13 Fixed Gains There are fixed gain controls at all inputs and outputs to the system so that levels are set according to hardware constraints and industry standards. 17.2.14 Frequency Enhanced Speech Intelligibility Frequency enhanced speech intelligibility on the CSR8645 BGA works with the adaptive equalisation module, see Section 17.2.9, and the NDVC module, see Section 17.2.12, to enhance intelligibility in the presence of noise. This combination of functions creates higher frequency information, which in the presence of noise, makes it much easier for the listener to differentiate between consonant pairs, therefore improving intelligibility. This also reduces listener fatigue as it requires less concentration effort from the user. This can lead to improved dual-tasking performance. 17.3 Music Enhancements 17.3.1 Audio Decoders CSR8645 BGA supports:

aptX decoder A wide range of standard decoders:

SBC MP3 AAC Faststream codec:

Jitter handling and high quality sample rate matching Low power consumption Low-latency No video/lip-sync issues while watching a video or playing games 17.3.2 aptX Decoder The aptX audio decoder is available for high-quality stereo audio over Bluetooth. When incorporated in Bluetooth A2DP stereo products, aptX audio coding delivers full wired audio quality. The aptX audio codec source material is delivered transparently over the Bluetooth link, whether it is stored uncompressed or in an alternative compression

(MP3, AAC, FLAC) format. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 104 of 114 CS-218182-DSP6 www.csr.com Target applications for the aptX decoder include:

Bluetooth stereo headphones / headsets Bluetooth automotive audio Bluetooth stereo speakers Benefits of the aptX decoder include:

Outstanding Bluetooth Stereo audio quality Faithful reproduction of full audio bandwidth Minimization of lip-sync issues via low-delay audio decoding techniques Non-destructive transcoding from other standard coded audio formats Low code memory and data memory requirements A2DP-compliant negotiation back to the SBC decoder when connecting with legacy audio sources Key features of the aptX decoder include:

Multiple audio sample rate support, including Fs = 44.1 kHz and Fs = 48kHz Conveyance of CD-quality audio (16-bit and Fs = 44.1kHz) over Bluetooth at a data rate of 352kbps Frequency response maintained from 10 Hz to 22 kHz for Fs = 48kHz Algorithmic delay less than 1.89 ms for Fs = 48kHz Dynamic range for 16-bit audio in excess of 92 dB 17.3.3 Configurable EQ The configurable equaliser on the CSR8645 BGA:

Each EQ filter contains up to 5 fully tuneable stages of cascaded 2nd order IIR filters per bank Enables compensation for imperfections in loudspeaker performance and frequency adjustments to the received audio to enhance music brightness Contains tiering for multiple customer presets, e.g. rock, pop, classical, jazz, dance etc. Contains an easy to use GUI, with drag points, see Figure 17.4 C S R 8 6 4 5 B G A D a t a S h e e t Is configurable with up to 6 switchable bank presets. This enables the headset user to select between the EQ bank presets through button presses. Figure 17.4: Configurable EQ GUI with Drag Points 17.3.4 Stereo Widening (S3D) The stereo widening feature on CSR8645 BGA:

Simulates loudspeaker listening to provide 3D listening experience Is highly optimised at <1MIPS of the Kalimba DSP Reduces listener fatigue for headphone listening Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 105 of 114 CS-218182-DSP6 www.csr.com 17.3.5 Volume Boost The volume boost feature on the CSR8645 BGA is a dynamic range compander and provides:

Additional loudness without clipping Multi-stage compression and expansion Processing modules for dynamic bass boost Easy to use GUI, with drag points, see Figure 17.5 Louder audio output without distortion Figure 17.5: Volume Boost GUI with Drag Points 17.4 CSR8645 Stereo ROM Solution with aptX Development Kit CSR's audio development kit for the CSR8645 BGA, order code DK-8645-10064-1A, includes a CSR8645 stereo ROM solution with aptX demonstrator board and necessary interface adapters and cables are available. In conjunction with the CSR8600 ROM Series Configuration Tool and other supporting utilities the development kit provides the best environment for designing audio solutions with the CSR8645 BGA. Important Note:

The CSR8645 Stereo ROM Solution with aptX audio development kit is subject to change and updates, for up-

to-date information see www.csrsupport.com. C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 106 of 114 CS-218182-DSP6 www.csr.com 18 Tape and Reel Information For tape and reel packing and labelling see IC Packing and Labelling Specification. 18.1 Tape Orientation Figure 18.1 shows the general orientation of the CSR8645 BGA package in the carrier tape. Pin A1 Marker Circular Holes A A B B 1.5 +0.1/-0.0 8.00 MIN 1.50 MIN User Direction of Feed Figure 18.1: Tape Orientation 18.2 Tape Dimensions Figure 18.2 shows the dimensions of the tape for the CSR8645 BGA. 2.00 0.10 SEE NOTE 3 4.00 SEE NOTE 1 0.30 0.05 R 0.3 MAX 4.48 B0 K0 0.66 SECTION A - A R 0.5 TYP A0 4.48 Figure 18.2: Tape Dimensions C S R 8 6 4 5 B G A D a t a S h e e t 2

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G 1.75 0.10 7.5 0.1 SEE NOTE 3 16.0 0.3 A A Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 107 of 114 CS-218182-DSP6 www.csr.com A0 B0 K0 Unit Notes 6.00 6.00 1.50 mm 18.3 Reel Information 10 sprocket hole pitch cumulative tolerance 0.2. 1. 2. Camber in compliance with EIA 481. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole 4. Tolerances, unless noted, 1PL 0.2, 2PL 0.10 5. Material: PS + C C S R 8 6 4 5 B G A D a t a S h e e t

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G 5.5 x 5.5 x 1mm VFBGA Figure 18.3: Reel Dimensions Package Type Tape Width A Max B C D Min N Min W1 W2 Max W3 Min Max Units 16 332 1.5 20.2 50 19.1 16.4 19.1 mm 13.0

(0.5/-0.2) 16.4

(3.0/-0.2) 18.4 Moisture Sensitivity Level CSR8645 BGA is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020. Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 108 of 114 CS-218182-DSP6 www.csr.com 19 Document References Document Reference, Date BlueCore Audio API Specification CS-209064-DD BlueTest User Guide CS-102736-UG Bluetooth and USB Design Considerations CS-101412-AN Core Specification of the Bluetooth System Bluetooth Specification Version 4.0, 17 December 2009 CSR8645 BGA Performance Specification CS-218184-SP Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model (MM) JESD22-A115C ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Human Body Model

(HBM) - Component Level ANSI/ESDA/JEDEC JS-001-201 Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components JESD22-C101E IC Packing and Labelling Specification CS-112584-SP IEC 61000-4-2 Electromagnetic compatibility (EMC) Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test IEC 61000-4-2, Edition 2.0, 2008-12 Kalimba Architecture 3 DSP User Guide CS-202067-UG Lithium Polymer Battery Charger Calibration and Operation for CSR8670 CS-204572-AN Moisture / Reflow Sensitivity Classification for Nonhermitic Solid State Surface Mount Devices IPC / JEDEC J-STD-020 Optimising BlueCore5-Multimedia ADC Performance Application Note CS-120059-AN Selection of IC EEPROMS for Use with BlueCore bcore-an-008P Typical Solder Reflow Profile for Lead-free Device CS-116434-AN Universal Serial Bus Specification v2.0, 27 April 2000 USB Battery Charging Specification v1.1, 15 April 2009 Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 109 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Terms and Definitions Term 8DPSK Definition 8-phase Differential Phase Shift Keying

/4 DQPSK

/4 rotated Differential Quaternary Phase Shift Keying

-law A-law A2DP AAC AC ACL ADC AEC AEQ AFC AFH AG AGC ALU AVRCP BCCMD BCSP BEC BER BFI BIST BlueCore Bluetooth BMC CNG codec Audio companding standard (G.711) Audio companding standard (G.711) Advanced Audio Distribution Profile Advanced Audio Coding Alternating Current Asynchronous Connection-oriented Analogue to Digital Converter Acoustic Echo Cancellation Adaptive EQualiser Automatic Frequency Control Adaptive Frequency Hopping Audio Gateway Automatic Gain Control Arithmetic Logic Unit Audio/Video Remote Control Profile BlueCore Command BlueCore Serial Protocol Bit Error Concealment Bit Error Rate Bad Frame Indicator Built-In Self-Test Burst Mode Controller Comfort Noise Generation Coder decoder Group term for CSRs range of Bluetooth wireless technology ICs Set of technologies providing audio and data transfer over short-range radio connections Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 110 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t CVSD Continuous Variable Slope Delta Modulation Differential Non Linearity (ADC accuracy parameter) Digital Signal Processor (or Processing) EEPROM Electrically Erasable Programmable Read Only Memory Definition Cyclic Redundancy Check Cambridge Silicon Radio Clear to Send Clear Voice Capture Digital to Analogue Converter Direct Current Direct Digital Synthesis Direct Memory Access Device Under Test exempli gratia, for example Enhanced Data Rate Electronic Industries Alliance Electromagnetic Compatibility EQualiser Extended SCO Electrostatic Discharge Equivalent Series Resistance et cetera, and the rest, and so forth Finite Impulse Response (filter) Frequency Shift Keying Term CRC CSR CTS CVC DAC DC DDS DMA DNL DSP DUT e.g. EDR EIA EMC EQ eSCO ESD ESR etc FIR FSK G.722 GCI GSM GUI H4DS HBM An ITU-T standard wideband speech codec operating at 48, 56 and 64 kbps General Circuit Interface Global System for Mobile communications Graphical User Interface H4 Deep Sleep Human Body Model Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 111 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Definition Host Controller Interface Hands-Free Profile HeadSet Profile Inter-Integrated Circuit Interface Inter-Integrated Circuit Sound Id est, that is Input/Output Integrated Circuit IEEE Institute of Electronic and Electrical Engineers Intermediate Frequency Infinite Impulse Response (filter) Integral Non Linearity (ADC accuracy parameter) Intelligent Power Management In-Phase and Quadrature Integrated Services Digital Network Kilobit An inductor (L) and capacitor (C) network Low (voltage) Drop-Out Light-Emitting Diode Link Manager Low Noise Amplifier Least Significant Bit (or Byte) Multiplier and ACcumulator Megabit MicroController Unit Micro Electro Mechanical System Million Instructions Per Second Term HCI HFP HSP IC IS i.e. I/O IC IF IIR INL IPM IQ ISDN JEDEC Kalimba Kb LC LDO LED LM LNA LSB MAC Mb MCU MEMS MIPS Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association) An open platform DSP co-processor, enabling support of enhanced audio applications, such as echo and noise suppression, and file compression / decompression C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 112 of 114 CS-218182-DSP6 www.csr.com Term MISO MLC MMU MP3 mSBC N/A NDVC NSMD PA PC PCB PCM PIN PIO PIO PLC plc PWM RAM RC RF RGB RISC RoHS ROM RSSI RTS RX SBC Definition Master In Slave Out Multilayer Ceramic Memory Management Unit MPEG-1 audio layer 3 modified Sub-Band Coding Not Applicable Noise Dependent Volume Control Non Solder Mask Defined Power Amplifier Personal Computer Printed Circuit Board Pulse Code Modulation Personal Identification Number Parallel Input/Output Pulse Width Modulation Random Access Memory A Resistor and Capacitor network Radio Frequency Red Green Blue Reduced Instruction Set Computer Read Only Memory Received Signal Strength Indication Request To Send Receive or Receiver Sub-Band Coding Programmable Input/Output, also known as general purpose I/O Packet Loss Concealment Public Limited Company PS Key Persistent Store Key Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive

(2002/95/EC) Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 113 of 114 CS-218182-DSP6 www.csr.com C S R 8 6 4 5 B G A D a t a S h e e t Serial Copy Management System (SCMS-T). A content protection scheme for secure transport and use of compressed digital music SMPS Switch Mode Power Supply Definition Serial Clock Line Synchronous Connection-Oriented Serial Data (line)

(Bluetooth) Special Interest Group Service Level Connection Signal-to-Noise Ratio Serial Peripheral Interface To Be Defined Total Harmonic Distortion and Noise Transmit or Transmitter Universal Asynchronous Receiver Transmitter User Interface Universal Serial Bus Voltage Controlled Oscillator Virtual Machine Voice over Internet Protocol VFBGA Very thin, Fine pitch, Ball Grid Array W-CDMA Wideband Code Division Multiple Access Wireless Fidelity (IEEE 802.11 wireless networking) Wind Noise Reduction Term SCL SCMS SCO SDA SIG SLC SNR SPI TBD UI USB VCO VM VoIP THD+N TX UART Wi-Fi WNR C S R 8 6 4 5 B G A D a t a S h e e t Production Information This material is subject to CSR's non-disclosure agreement Cambridge Silicon Radio Limited 2011-2012 Page 114 of 114 CS-218182-DSP6 www.csr.com