FCC ID: 2AWVZ-JL500N RFID module

 

FM17520 Contactless Transceiver IC Datasheet Oct.2016 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 1 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION;

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Datasheet FM17520 Contactless Transceiver IC Ver 1.0 2 Contents Contents CONTENTS ............................................................................................................................................................................. 3 TABLES ................................................................................................................................................................................... 5 FIGURES ................................................................................................................................................................................. 8 1 PRODUCT OVERVIEW .................................................................................................................................................... 9 1.1 INTRODUCTION ..................................................................................................................................................................... 9 1.2 FEATURES ............................................................................................................................................................................ 9 1.3 BLOCK DIAGRAM ................................................................................................................................................................ 10 1.4 PINNING INFORMATION ....................................................................................................................................................... 11 FM17520 Pinning Assignment ............................................................................................................................... 11 1.4.1 2 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 13 2.1 GENERAL DESCRIPTION ........................................................................................................................................................ 13 ISO/IEC14443 A FUNCTIONALITY ........................................................................................................................................ 13 2.2 3 FM17520 REGISTER SET .............................................................................................................................................. 15 3.1 FM17520 REGISTERS OVERVIEW .......................................................................................................................................... 15 3.1.1 Registers Overview ................................................................................................................................................. 15 3.1.2 Register Bit Behavior .............................................................................................................................................. 17 3.2 REGISTER DESCRIPTION ........................................................................................................................................................ 17 3.2.1 Page 0Command and Status .............................................................................................................................. 17 3.2.2 Page 1Communication ....................................................................................................................................... 26 3.2.3 Page 2Configuration .......................................................................................................................................... 33 3.2.4 Page 3Test .......................................................................................................................................................... 38 3.2.5 Extended Register .................................................................................................................................................. 43 4 HOST INTERFACES ....................................................................................................................................................... 45 4.1.1 4.1.2 4.1.3 4.1 SPI INTERFACE ................................................................................................................................................................... 45 SPI Read Data ......................................................................................................................................................... 45 SPI Write Data ........................................................................................................................................................ 45 SPI Address Byte ..................................................................................................................................................... 45 4.2 ACCESSING EXTENDED REGISTER ............................................................................................................................................ 45 4.2.1 Write Extended Register ........................................................................................................................................ 46 4.2.2 Read Extended Register ......................................................................................................................................... 46 5 ANALOG INTERFACE AND CONTACTLESS UART ........................................................................................................... 47 5.1 GENERAL ........................................................................................................................................................................... 47 5.2 TX DRIVER ......................................................................................................................................................................... 47 5.3 SERIAL DATA SWITCH........................................................................................................................................................... 48 6 7 CRC COPROCESSOR ..................................................................................................................................................... 49 FIFO BUFFER ............................................................................................................................................................... 50 7.1 ACCESSING FIFO BUFFER ..................................................................................................................................................... 50 7.2 CONTROLLING FIFO BUFFER ................................................................................................................................................. 50 7.3 FIFO BUFFER STATUS INFORMATION ...................................................................................................................................... 50 8 INTERRUPT REQUEST SYSTEM ..................................................................................................................................... 51 8.1 INTERRUPT SOURCES OVERVIEW ............................................................................................................................................ 51 9 TIMER ......................................................................................................................................................................... 52 10 POWER REDUCTION MODES ....................................................................................................................................... 53 10.1 DEEP POWER DOWN ...................................................................................................................................................... 53 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 3 Contents 10.2 HARD POWER DOWN ..................................................................................................................................................... 53 10.2.1 Data Retention in HPD Mode ................................................................................................................................. 53 SOFT POWER DOWN....................................................................................................................................................... 54 TRANSMITTER OFF MODE ................................................................................................................................................ 54 10.3 10.4 11 LOW VOLTAGE DETECTION ......................................................................................................................................... 55 12 OSCILLATOR CIRCUITRY .............................................................................................................................................. 56 13 RESET AND OSCILLATOR START-UP TIME .................................................................................................................... 57 13.1 13.2 RESET TIMING REQUIREMENTS ......................................................................................................................................... 57 OSCILLATOR START-UP TIME ............................................................................................................................................ 57 14 COMMAND SET ........................................................................................................................................................... 58 14.1 14.2 14.3 GENERAL DESCRIPTION ................................................................................................................................................... 58 GENERAL BEHAVIOR ....................................................................................................................................................... 58 FM17520 COMMAND OVERVIEW .................................................................................................................................... 58 14.3.1 IDLE ........................................................................................................................................................................ 58 14.3.2 Mem ....................................................................................................................................................................... 58 14.3.3 Generate RandomID .............................................................................................................................................. 59 14.3.4 CalcCRC .................................................................................................................................................................. 59 14.3.5 Transmit ................................................................................................................................................................. 59 14.3.6 NoCmdChange ....................................................................................................................................................... 59 14.3.7 Receive ................................................................................................................................................................... 59 14.3.8 Transceive .............................................................................................................................................................. 59 14.3.9 Authent .................................................................................................................................................................. 59 14.3.10 SoftReset ................................................................................................................................................................ 60 15 TESTSIGNALS............................................................................................................................................................... 61 15.1 15.2 15.3 TESTBUS ....................................................................................................................................................................... 61 TESTSIGNALS AT PIN AUX1/AUX2 .................................................................................................................................... 62 PRBS .......................................................................................................................................................................... 62 TYPICAL APPLICATION DIAGRAM ................................................................................................................................ 63 CHARACTERISTICS ....................................................................................................................................................... 64 17.1 17.2 LIMITING VALUES ........................................................................................................................................................... 64 CHARACTERISTICS ........................................................................................................................................................... 64 17.2.1 SPI AC Characteristics............................................................................................................................................. 64 18 ORDERING INFORMATION .......................................................................................................................................... 66 19 PACKAGE INFORMATION ............................................................................................................................................ 67 19.1 QFN32 PACKAGE OUTLINE ............................................................................................................................................. 67 REVISION HISTORY ............................................................................................................................................................... 68 SALES AND SERVICE ............................................................................................................................................................. 69 16 17 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 4 Tables Tables FM17520 QFN32 PIN DESCRIPTION ................................................................................................................................ 12 TAB1-1 FM17520 ISO/IEC A COMMUNICATION OVERVIEW ............................................................................................................ 13 TAB2-1 REGISTERS OVERVIEW ..................................................................................................................................................... 16 TAB3-1 EXTENDED REGISTERS OVERVIEW ....................................................................................................................................... 16 TAB3-2 BEHAVIOR OF REGISTER BITS AND ITS DESCRIPTION ................................................................................................................ 17 TAB3-3 RFU REGISTER ............................................................................................................................................................... 17 TAB3-4 RFUREG BITS DESCRIPTION .............................................................................................................................................. 17 TAB3-5 COMMANDREG REGISTER ................................................................................................................................................ 17 TAB3-6 COMMANDREG BITS DESCRIPTION ..................................................................................................................................... 18 TAB3-7 COMMIENREG REGISTER ................................................................................................................................................. 18 TAB3-8 COMMIENREG BITS DESCRIPTION ...................................................................................................................................... 18 TAB3-9 DIVIENREG REGISTER ...................................................................................................................................................... 18 TAB3-10 DIVIENREG BITS DESCRIPTION ........................................................................................................................................... 19 TAB3-11 COMMIRQREG REGISTER ................................................................................................................................................. 19 TAB3-12 COMMIRQREG BITS DESCRIPTION ...................................................................................................................................... 19 TAB3-13 DIVIRQREG REGISTER ..................................................................................................................................................... 20 TAB3-14 DIVIRQREG BITS DESCRIPTION .......................................................................................................................................... 20 TAB3-15 ERRORREG REGISTER ....................................................................................................................................................... 20 TAB3-16 ERRORREG BITS DESCRIPTION ........................................................................................................................................... 21 TAB3-17 STATUS1REG REGISTER.................................................................................................................................................... 21 TAB3-18 STATUS1REG BITS DESCRIPTION ........................................................................................................................................ 22 TAB3-19 STATUS2REG REGISTER.................................................................................................................................................... 22 TAB3-20 STATUS2REG BITS DESCRIPTION ........................................................................................................................................ 22 TAB3-21 FIFODATAREG REGISTER ................................................................................................................................................. 23 TAB3-22 FIFODATAREG BITS DESCRIPTION ...................................................................................................................................... 23 TAB3-23 FIFOLEVELREG REGISTER ................................................................................................................................................. 23 TAB3-24 TAB3-25 FIFOLEVELREG BITS DESCRIPTION ..................................................................................................................................... 23 TAB3-26 WATERLEVELREG REGISTER .............................................................................................................................................. 23 TAB3-27 WATERLEVELREG BITS DESCRIPTION .................................................................................................................................. 24 TAB3-28 CONTROLREG REGISTER ................................................................................................................................................... 24 CONTROLREG BITS DESCRIPTION ........................................................................................................................................ 24 TAB3-29 BITFRAMINGREG REGISTER .............................................................................................................................................. 24 TAB3-30 BITFRAMINGREG BITS DESCRIPTION ................................................................................................................................... 25 TAB3-31 COLLREG REGISTER ......................................................................................................................................................... 25 TAB3-32 TAB3-33 COLLREG BITS DESCRIPTION .............................................................................................................................................. 25 EXREG REGISTER ............................................................................................................................................................ 25 TAB3-34 EXREG BITS DESCRIPTION ................................................................................................................................................. 25 TAB3-35 TAB3-36 RFU REGISTER ............................................................................................................................................................... 26 TAB3-37 RFUREG BITS DESCRIPTION .............................................................................................................................................. 26 TAB3-38 MODEREG REGISTER ....................................................................................................................................................... 26 TAB3-39 MODEREG BITS DESCRIPTION ............................................................................................................................................ 26 TXMODEREG REGISTER ................................................................................................................................................... 27 TAB3-40 TAB3-41 TXMODEREG BITS DESCRIPTION ........................................................................................................................................ 27 RXMODEREG REGISTER ................................................................................................................................................... 27 TAB3-42 RXMODEREG BITS DESCRIPTION ........................................................................................................................................ 28 TAB3-43 TXCONTROLREG REGISTER ............................................................................................................................................... 28 TAB3-44 TAB3-45 TXCONTROLREG BITS DESCRIPTION .................................................................................................................................... 28 TXASKREG REGISTER ...................................................................................................................................................... 29 TAB3-46 TXASKREG BITS DESCRIPTION ........................................................................................................................................... 29 TAB3-47 TXSELREG REGISTER ....................................................................................................................................................... 29 TAB3-48 TAB3-49 TXSELREG BITS DESCRIPTION ............................................................................................................................................ 29 RXSELREG REGISTER ....................................................................................................................................................... 30 TAB3-50 RXSELREG BITS DESCRIPTION ............................................................................................................................................ 30 TAB3-51 TAB3-52 RXTHRESHOLDREG REGISTER ............................................................................................................................................ 30 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 5 Tables RXTHRESHOLDREG BITS DESCRIPTION ................................................................................................................................. 30 TAB3-53 DEMODREG REGISTER ..................................................................................................................................................... 30 TAB3-54 DEMODREG BITS DESCRIPTION .......................................................................................................................................... 31 TAB3-55 RFU REGISTER ............................................................................................................................................................... 31 TAB3-56 RFUREG BITS DESCRIPTION .............................................................................................................................................. 31 TAB3-57 RFU REGISTER ............................................................................................................................................................... 31 TAB3-58 RFUREG BITS DESCRIPTION .............................................................................................................................................. 31 TAB3-59 TXREG REGISTER ............................................................................................................................................................ 32 TAB3-60 TXREG BITS DESCRIPTION ................................................................................................................................................. 32 TAB3-61 RXREG REGISTER ............................................................................................................................................................ 32 TAB3-62 RXREG BITS DESCRIPTION ................................................................................................................................................. 32 TAB3-63 RFU REGISTER ............................................................................................................................................................... 32 TAB3-64 RFUREG BITS DESCRIPTION .............................................................................................................................................. 32 TAB3-65 RFU REGISTER ............................................................................................................................................................... 32 TAB3-66 RFUREG BITS DESCRIPTION .............................................................................................................................................. 33 TAB3-67 RFU REGISTER ............................................................................................................................................................... 33 TAB3-68 RFUREG BITS DESCRIPTION .............................................................................................................................................. 33 TAB3-69 CRCRESULTREG REGISTER ............................................................................................................................................... 33 TAB3-70 CRCRESULTREG BITS DESCRIPTION .................................................................................................................................... 33 TAB3-71 CRCRESULTREG REGISTER ............................................................................................................................................... 33 TAB3-72 CRCRESULTREG BITS DESCRIPTION .................................................................................................................................... 33 TAB3-73 RFU REGISTER ............................................................................................................................................................... 34 TAB3-74 TAB3-75 RFUREG BITS DESCRIPTION .............................................................................................................................................. 34 TAB3-76 MODWIDTHREG REGISTER............................................................................................................................................... 34 TAB3-77 MODWIDTHREG BITS DESCRIPTION ................................................................................................................................... 34 TAB3-78 RFU REGISTER ............................................................................................................................................................... 34 RFUREG BITS DESCRIPTION .............................................................................................................................................. 34 TAB3-79 RFCFGREG REGISTER ...................................................................................................................................................... 34 TAB3-80 RFCFGREG BITS DESCRIPTION ........................................................................................................................................... 35 TAB3-81 TAB3-82 GSNONREG REGISTER ..................................................................................................................................................... 35 GSNONREG BITS DESCRIPTION ......................................................................................................................................... 35 TAB3-83 CWGSPREG REGISTER .................................................................................................................................................... 35 TAB3-84 TAB3-85 CWGSPREG BITS DESCRIPTION ......................................................................................................................................... 35 TAB3-86 MODGSPREG REGISTER .................................................................................................................................................. 36 TAB3-87 MODGSPREG BITS DESCRIPTION ....................................................................................................................................... 36 TMODEREG REGISTER ..................................................................................................................................................... 36 TAB3-88 TMODEREG BITS DESCRIPTION .......................................................................................................................................... 37 TAB3-89 TPRESCALERREG REGISTER ............................................................................................................................................... 37 TAB3-90 TAB3-91 TPRESCALERREG BITS DESCRIPTION .................................................................................................................................... 37 TRELOADHIREG REGISTER ................................................................................................................................................ 37 TAB3-92 TRELOADHIREG BITS DESCRIPTION .................................................................................................................................... 37 TAB3-93 TRELOADLOREG REGISTER ............................................................................................................................................... 37 TAB3-94 TAB3-95 TRELOADLOREG BITS DESCRIPTION .................................................................................................................................... 37 TCOUNTERVALHIREG REGISTER ........................................................................................................................................ 37 TAB3-96 TCOUNTERVALHIREG BITS DESCRIPTION ............................................................................................................................. 38 TAB3-97 TAB3-98 TCOUNTERVALLOREG REGISTER........................................................................................................................................ 38 TAB3-99 TCOUNTERVALLOREG BITS DESCRIPTION ............................................................................................................................ 38 TAB3-100 RFU REGISTER ............................................................................................................................................................... 38 TAB3-101 RFUREG BITS DESCRIPTION .............................................................................................................................................. 38 TAB3-102 TESTSEL1REG REGISTER ................................................................................................................................................... 38 TAB3-103 TESTSEL1REG BITS DESCRIPTION ....................................................................................................................................... 38 TAB3-104 TESTSEL2REG REGISTER ................................................................................................................................................... 39 TAB3-105 TESTSEL2REG BITS DESCRIPTION ....................................................................................................................................... 39 TAB3-106 TESTPINENREG REGISTER ................................................................................................................................................ 39 TAB3-107 TESTPINENREG BITS DESCRIPTION ..................................................................................................................................... 39 TAB3-108 TESTPINVALUEREG REGISTER ........................................................................................................................................... 39 TAB3-109 TESTPINVALUEREG BITS DESCRIPTION ................................................................................................................................ 40 TAB3-110 TESTBUSREG REGISTER .................................................................................................................................................... 40 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 6 Tables TAB3-111 TESTBUSREG BITS DESCRIPTION ........................................................................................................................................ 40 TAB3-112 TESTCTRLREG REGISTER ................................................................................................................................................... 40 TAB3-113 TESTCTRLREG BITS DESCRIPTION ....................................................................................................................................... 40 TAB3-114 RFTREG REGISTER .......................................................................................................................................................... 40 TAB3-115 RFTREG BITS DESCRIPTION ............................................................................................................................................... 41 TAB3-116 ANOLOGTESTREG REGISTER ............................................................................................................................................. 41 TAB3-117 ANOLOGTESTREG BITS DESCRIPTION .................................................................................................................................. 41 TAB3-118 TESTDAC1REG REGISTER ................................................................................................................................................ 41 TAB3-119 TESTDAC1REG BITS DESCRIPTION ..................................................................................................................................... 42 TAB3-120 TESTDAC2REG REGISTER ................................................................................................................................................ 42 TAB3-121 TESTDAC2REG BITS DESCRIPTION ..................................................................................................................................... 42 TAB3-122 TESTADCREG REGISTER .................................................................................................................................................. 42 TAB3-123 TESTADCREG BITS DESCRIPTION ....................................................................................................................................... 42 TAB3-124 RFTREG REGISTER .......................................................................................................................................................... 42 TAB3-125 RFTREG BITS DESCRIPTION ............................................................................................................................................... 42 TAB3-126 RFTREG REGISTER .......................................................................................................................................................... 43 TAB3-127 RFTREG BITS DESCRIPTION ............................................................................................................................................... 43 TAB3-128 RFTREG REGISTER .......................................................................................................................................................... 43 TAB3-129 RFTREG BITS DESCRIPTION ............................................................................................................................................... 43 TAB3-130 RFTREG REGISTER .......................................................................................................................................................... 43 TAB3-131 RFTREG BITS DESCRIPTION ............................................................................................................................................... 43 TAB3-132 HPDCTRL REGISTER ......................................................................................................................................................... 43 TAB3-133 HPDCTRL BITS DESCRIPTION ............................................................................................................................................. 44 TAB3-134 USERET REGISTER ........................................................................................................................................................... 44 TAB3-135 USERET BITS DESCRIPTION ............................................................................................................................................... 44 TAB3-136 LVDCTRL REGISTER ......................................................................................................................................................... 44 LVDCTRL BITS DESCRIPTION .............................................................................................................................................. 44 TAB3-137 MOSI AND MISO BYTE ORDER ......................................................................................................................................... 45 TAB4-1 MOSI AND MISO BYTE ORDER ......................................................................................................................................... 45 TAB4-2 TAB4-3 ADDRESS BYTE FORMAT ................................................................................................................................................... 45 BYTE DEFINITION OF EXTENDED REGISTER ............................................................................................................................ 45 TAB4-4 CONTROLLING SIGNALS AND SETTINGS ON PIN TX1 ............................................................................................................... 47 TAB5-1 CONTROLLING SIGNALS AND SETTINGS ON PIN TX2 ............................................................................................................... 48 TAB5-2 TAB6-1 CRC COPROCESSOR PARAMETERS ...................................................................................................................................... 49 INTERRUPT SOURCES ....................................................................................................................................................... 51 TAB8-1 LIST OF RETENTION REGISTERS IN HPD MODE ...................................................................................................................... 54 TAB10-1 COMMAND OVERVIEW .................................................................................................................................................... 58 TAB14-1 TESTSIGNAL ROUTING (TESTSEL2REG = 07H) ...................................................................................................................... 61 TAB15-1 TAB15-2 TESTSIGNALS DESCRIPTION ............................................................................................................................................... 61 TESTSIGNAL ROUTING (TESTSEL2REG = 0DH) ...................................................................................................................... 61 TAB15-3 TESTSIGNALS DESCRIPTION ............................................................................................................................................... 61 TAB15-4 TESTSIGNAL ROUTING (TESTSEL2REG = 19H) ...................................................................................................................... 61 TAB15-5 TAB15-6 TESTSIGNALS DESCRIPTION ............................................................................................................................................... 61 TESTSIGNALS DESCRIPTION ............................................................................................................................................... 62 TAB15-7 FM17520 LIMITING VALUES ............................................................................................................................................ 64 TAB17-1 RECOMMENDED OPERATING CONDITIONS FOR FM17520 ..................................................................................................... 64 TAB17-2 TAB17-3 SPI AC CHARACTERISTICS................................................................................................................................................. 65 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 7 Figures Figures FIG1-1 FM17520 BLOCK DIAGRAM ................................................................................................................................................. 10 FIG1-2 FM17520 QFN32 PINNING ASSIGNMENT (TOP VIEW) .............................................................................................................. 11 FIG2-1 FM17520 APPLICATION DIAGRAM ........................................................................................................................................ 13 FIG2-2 PCD STANDARD FRAMES ...................................................................................................................................................... 13 FIG2-3 PICC STANDARD FRAMES...................................................................................................................................................... 14 FIG4-1 EXTENDED REGISTER WRITE PROGRESS..................................................................................................................................... 46 FIG4-2 EXTENDED REGISTER READ PROGRESS ...................................................................................................................................... 46 FIG5-1 SERIAL DATA SWITCH FOR TX1 AND TX2 ................................................................................................................................. 48 QUARTZ CRYSTAL CONNECTION ......................................................................................................................................... 56 FIG12-1 FIG13-1 OSCILLATOR START-UP TIME ............................................................................................................................................. 57 TYPICAL APPLICATION DIAGRAM ........................................................................................................................................ 63 FIG16-1 TIMING DIAGRAM FOR SPI ............................................................................................................................................... 65 FIG17-1 FIG19-1 FM17520 QFN32 PACKAGE OUTLINE.............................................................................................................................. 67 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 8 1 Product Overview 1 Product Overview 1.1 Introduction The FM17520 is a highly integrated transceiver IC for contactless communication at 13.56 MHz, supporting Reader/Writer mode of ISO/IEC 14443A. The FM17520s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC14443A cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO/IEC14443A compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection. The FM17520 supports ISO/IEC14443A cards and transponders with transfer speeds from 106kbit/s to 424kbit/s in both directions. With the features of low voltage, low power and large operating distance, FM17520 is especially suitable for connectless Reader/Writer equipment with low power, low voltage and low cost requirements. 1.2 Features Supports ISO/IEC 14443 A Reader/Writer mode ISO14443A transfer speed communication at 106kbps, 212kbps, 424kbps, 848kbps Typical operating distance in Read/Write mode up to 50mm depending on the antenna size and tuning Supports SPI up to 10Mbps, with voltage levels according pad voltage supply Flexible interrupt modes Comfortable 64 byte send and receive FIFO-buffer Multiple low-power modes Soft powerdown mode Hard powerdown mode Deep powerdown mode(typical 1uA) Programmable timer Internal oscillator to connect 27.12 MHz quartz Wide voltage supply: 2.2V ~ 3.6V Integrated CRC Co-processor Programmable I/O pins Datasheet FM17520 Contactless Transceiver IC Ver 1.0 9 1.3 Block Diagram 1 Product Overview Fig1-1 FM17520 block diagram Datasheet FM17520 Contactless Transceiver IC Ver 1.0 10 Host Interface control Control Register Bank FIFO codec Control Engine Receiver Transmitter Encryption Unit CRC co-processor Interrupt control clock/reset control Programable timer Power Manage Unit 1.4 Pinning Information 1.4.1 FM17520 Pinning Assignment 1 Product Overview Fig1-2 FM17520 QFN32 pinning assignment (top view) Pin Description Pin Symbol Type Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NC PVDD DVDD DVSS PVSS NPD TIN TOUT PVDD2 TVSS TX1 TVDD TX2 TVSS AVDD VMID RX AVSS AUX1 AUX2 OSCIN

P P G G I I O P G O P O G P P I G O O I

pin power supply chip power supply digital ground pin ground power-down input, active low, reset chip when posedge on NPD pin test input test output pin power supply for TIN and TOUT pin transmitter output1 ground transmitter 1 modulated 13.56MHz energy carrier output transmitter power supply transmitter 2 modulated 13.56MHz energy carrier output transmitter output 2 ground analog power supply internal reference voltage RF signal input analog ground auxiliary outputs for test auxiliary outputs for test crystal oscillator input; also input externally generated Datasheet FM17520 Contactless Transceiver IC Ver 1.0 11 T U O C S O I N C S O S S N Q R I 2 X U A 1 X U A S S V A X R 24 23 22 21 20 19 18 17 FM17520

(QFN32) 1 2 3 4 5 6 7 8 C N D D V P D D V D S S V D S S V P D P N N T I T U O T 25 26 27 28 29 30 31 D1 D2 D3 D4 SCK MOSI MISO NC 32 16 15 14 13 12 11 10 9 VMID AVDD TVSS TX2 TVDD TX1 TVSS PVDD2 1 Product Overview Pin Symbol Type Description 22 23 24 25 26 27 28 29 30 31 32 OSCOUT IRQ NSS D1 D2 D3 D4 SCK MOSI MISO NC clock(27.12MHz) O O I IO IO IO IO I I O

crystal oscillator output interrupt request output, indicates an interrupt event SPI interface enable test port test port test port test port SPI serial clock input SPI master output and slave input SPI master input and slave output

Tab1-1 FM17520 QFN32 pin description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 12 2 Functional Description 2 Functional Description 2.1 General Description FM17520 Reader IC supports ISO/IEC14443 A protocols using various transfer speeds. Fig2-1 FM17520 application diagram 2.2 ISO/IEC14443 A Functionality Tab 2-1 lists the transfer speeds of ISO/IEC14443A supported by FM17520. Communication Direction Reader to Card(send data from FM17520 to a card) Card to Reader(FM17520 receives data from a card) Singal Type reader side modulation bit encoding bit length card side modulation subcarrier frequency bit encoding Transfer Speed 106 kBd 212 kBd 424 kBd 100%ASK 100%ASK 100%ASK modified Miller modified Miller modified Miller encoding encoding encoding

(128/13.56)s subcarrier load

(64/13.56)s subcarrier load

(32/13.56)s subcarrier load modulation modulation modulation 13.56MHz/16 13.56MHz/16 13.56MHz/16 Manchester encoding BPSK BPSK Tab2-1 FM17520 ISO/IEC A communication overview The communication between FM17520 and RFID meets ISO/IEC14443A. Fig 2-2 lists standard frames for PCD and PICC. Fig2-2 PCD standard frames Datasheet FM17520 Contactless Transceiver IC Ver 1.0 13 FM17522 Battery MCU PCD CARD PICC 2 Functional Description Fig2-3 PICC standard frames The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg registers ParityDisable bit. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 14 3 FM17520 Register Set 3 FM17520 Register Set 3.1 FM17520 Registers Overview 3.1.1 Registers Overview Page0Command and Status Page1Communication Page2Configuration Page3Test Page Addr Register Name Function 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D RFU CommandReg ComIEnReg DivIEnReg ComIrqReg DivIrqReg ErrorReg Status1Reg Status2Reg Reserved for future use Starts and stops command execution Controls bits to enable and disable the passing of Interrupt Requests Controls bits to enable and disable the passing of Interrupt Requests Contains Interrupt Request bits Contains Interrupt Request bits Error bits showing the error status of the last command executed Contains status bits for communication Contains status bits of the receiver and transmitter Input and output of 64 byte FIFO buffer Indicates the number of bytes stored in the FIFO FIFODataReg FIFOLevelReg WaterLevelReg Defines the level for FIFO underflow and overflow warning ControlReg Contains miscellaneous Control Registers BitFramingReg Adjustments for bit oriented frames CollReg EXReg RFU ModeReg TxModeReg RxModeReg TxControlReg TxASKReg TxSelReg RxSelReg DemodReg RFU RFU TxReg RxReg Shows the bit position of the first bit collision detected on the RF-interface Extended register(see Tab 3-2) Reserved for future use Defines general modes for transmitting and receiving Defines the data rate and framing during transmission Defines the data rate and framing during receiving Controls the logical behavior of the antenna driver pins TX1 and TX2 Controls the setting of the antenna drivers Selects the internal sources for the antenna driver Selects internal receiver settings Defines demodulator settings Reserved for future use Reserved for future use Defines some settings for the transmission of ISO/IEC 14443 Defines some settings for the receiving of ISO/IEC 14443 RxThresholdReg Selects thresholds for the bit decoder 0 1 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 15 3 FM17520 Register Set Page Addr Register Name Function Reserved for future use Reserved for future use Reserved for future use CRCResultReg Shows the actual result of the CRC calculation RFU RFU RFU RFU RFU ModWidthReg RFCfgReg GsNReg CWGsPReg ModGsPReg TModeReg TPrescalerReg Reserved for future use Controls the setting of the ModWidth Reserved for future use Configures the receiver gain Selects the conductance of the antenna driver pins TX1 and TX2 Selects the conductance of the antenna driver pins TX1 and TX2 Selects the conductance of the antenna driver pins TX1 and TX2 Defines settings for the internal timer TReloadReg Describes the 16-bit timer reload value TCounterValReg Shows the 16-bit actual timer value RFU TestSel1Reg TestSel2Reg TestPinEnReg TestPinValueReg TestBusReg TestCtrlReg RFT Reserved for future use General test signal configuration General test signal configuration and PRBS control Enables the pin output driver on D1-D4 Defines the values for the 4-bit parallel bus when it is used as I/O bus Shows the status of the internal testbus Test control Reserved for production tests AnalogTestReg Controls the pins AUX1 and AUX2 TestDAC1Reg Defines the test value for the TestDAC1 TestDAC2Reg Defines the test value for the TestDAC2 Shows the actual value of ADC I and Q TestADCReg Reserved for production tests RFT Tab3-1 Registers overview C-F Extended Registers (EXReg):

Page Addr Secondary Extended Addr Register Name Function 0 F 03 1B 1D HpdCtrl UseRet LVDctrl HPD/DPD mode control Controls data retention function in HPD mode Controls the low-voltage detection Tab3-2 Extended registers overview E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B 2 3 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 16 3.1.2 Register Bit Behavior 3 FM17520 Register Set The table belowdescribles the behavior and the access conditions of registers. Abbre viation Description Behavior r/w read and write dy dynamic read only These bits can be written and read by the-Controller. Since theyare used only for control means, their content is not influenced byinternal state machines. These bits can be written and read by the-Controller, and they may also be written by internalstate machines. These registers value is determined by internal states only. The

-Controller can read them only. write only These registers are write only. Reading them always returns ZERO.

These registers are reserved for future use. These registers are reserved for production tests and shall not bechanged. Tab3-3 Behavior of register bits and its description r w RFU RFT 3.2 Register Description 3.2.1 Page 0Command and Status 3.2.1.1 RFU_address00h Bit Definition Access Rights Reset Value 7

0 RFU RFU RFU RFU RFU RFU RFU RFU 6

0 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-4 RFU register Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-5 RFUReg bits description 3.2.1.2 CommandReg_address 01h Starts and stops command execution. RFU RFU RcvOff Power Down Command Bit Definition Access Rights Reset Value 7

0 6

0 5 r/w 1 4 dy 0 3 2 1 0 dy 0 dy 0 dy 0 dy 0 Tab3-6 CommandReg register Description Bit 7-6 5 Symbol

RcvOff 4 PowerDown Reserved for future use. Set to logic 1, the analog part of the receiver is switched off. Set to logic 1, Soft Power-down mode is entered. Set to logic 0, the FM17520 starts the wake up procedure. During this procedure, this bit still shows a 1. A 0 indicates that the FM17520 is Datasheet FM17520 Contactless Transceiver IC Ver 1.0 17 Bit Defin ition Acce ss Right Rese s t Valu e Bit 7 6 5 4 3 2 1 0 3 FM17520 Register Set Bit Symbol Description ready for operations. Remark: The bit Power Down cannot be set, when the command SoftReset has been activated. Command register. Activates a command according to the Command Code. Reading it shows, which command is actually executed Tab3-7 CommandReg bits description 3-0 Command 3.2.1.3 CommIEnReg_address 02h Control bits to enable and disable the passing of interrupt requests. 7 6 5 4 3 2 1 0 IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn r/w r/w r/w r/w r/w r/w r/w r/w 1 0 0 0 0 0 0 0 Symbol Irqlnv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Tab3-8 CommIEnReg register Description Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state. Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. Allows the error interrupt request (indicated by bit ErrIRq) to be propagated to pin IRQ. Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. Tab3-9 CommIEnReg bits description 3.2.1.4 DivIEnReg_address03h Control bits to enable and disable the passing of interrupt requests. Bit Definition Access Rights Reset Value IRQPushPull RFU RFU TinActIEn RFU CRCIEn RFU RFU 6

0 5

0 4 r/w 0 3

0 2 r/w 0 1

0 0

0 7 r/w 0 Tab3-10 DivIEnReg register Datasheet FM17520 Contactless Transceiver IC Ver 1.0 18 3 FM17520 Register Set Bit 7 6-5 4 3 2 1-0 Symbol IRQPushPull

TinActIEn RFU CRCIEn RFU Description Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. Reserved for future use. Allows the TIN active interrupt request to be propagated to pin IRQ. Reserved for future use. Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. Reserved for future use. Tab3-11 DivIEnReg bits description 4 3 2 1 0 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq dy dy dy dy dy 3.2.1.5 CommIRqReg_address04h 6 7 Set1 Contain Interrupt Request bits. Bit 5 Def initi on Ac ces s Rig hts Re set Val ue dy w 0 0 0 dy 1 0 1 0 0 Bit Symbol 7 6 5 Set1 TxIRq RxIRq 4 IdleIRq 3 HiAlertIRq 2 1 0 LoAlertIRq ErrIRq TimerIRq Tab3-12 CommIRqReg register Description Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg are cleared. Set to logic 1 immediately after the lastbit of the transmitted data was sent out. Set to logic 1 when the receiver detects the end of a valid datastream. If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO. Set to logic 1, when a command terminates by itself or when the CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1. Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1. Set to logic 1 if any error bit in the Error Register is set. Set to logic 1 when the timer decrements the TimerValue Register to zero. Tab3-13 CommIRqReg bits description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 19 3 FM17520 Register Set 3.2.1.6 DivIRqReg_address05h Contain Interrupt Request bits. 5 Bit 6 7 Definitio n Access Rights Reset Value w 0

0

0 Set2 RFU RFU TinActIRq RFU CRCIRq RFU RFU 4 dy x 3

0 2 dy 0 1

x 0

x Tab3-14 DivIRqReg register Bit Symbol Description 6-5 7 4 3 2 1-0 Set2 TinActIRq CRCIRq

Set to logic 1, Set2 defines thatthe marked bits in the register DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register DivIRqReg are cleared Reserved for future use. Set to logic 1, when TIN is active.This interrupt is set when either a rising or falling signal edge is detected. Reserved for future use. Set to logic 1, when the CRC command is active and all data are processed. Reserved for future use. Tab3-15 DivIRqReg bits description 3.2.1.7 ErrorReg_address06h BufferOvfl CollErr CRCErr ParityErr ProtocolErr 4 5 3 6 7 RFU WrErr TempErr Error bit register showing the error status of the last command executed. Bit 2 De fini tio n Ac ce ss Rig hts Re set Val ue 0 0 0 0 0 0 r r r

r r Tab3-16 ErrorReg register 1 0 r 0 r 0 Bit 7 6 5 Symbol WrErr TempErr

Description Set to logic 1, when data is written into FIFO by the host controller during the Authent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface. Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically. Remark: excuting new command can clear all error bits except TempErr. Reserved for future use. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 20 3.2.1.8 Status1Reg_address 07h Contain status bits of the CRC, Interrupt and FIFO buffer. 3 FM17520 Register Set Bit Symbol Description Set to logic 1, if the host controller or a FM17520s internal state machine 4 BufferOvfl

(e.g. receiver) tries to write datainto the FIFO-bufferalthough the FIFO-buffer is already full. 3 2 1 CollErr CRCErr ParityErr 0 ProtocolErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit/s. During communication schemes at 212 and 424kbit/s this bit is always set to logic 1. Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase. Set to logic 1, if the parity check has failed. It is cleared automatically at receiver start-up phase. Only valid for ISO/IEC 14443A communication at 106 kbit/s. Set to logic 1, if one out of the following cases occur:

Set to logic 1 if the SOF is incorrect. It is cleared automatically at receiver start-up phase. The bit is only valid for 106kbit/s in Communication mode. During the Authent Command, bit ProtocolErr is set to logic 1, if the number of bytes received in one data stream is incorrect. Tab3-17 ErrorReg bits description Bit Definition Access Rights Reset Value 7

0 Bit 7 Symbol

6 CRCOk CRCReady IRq 3 TRunning

HiAlert 5 4 2 1 RFU CRCOk CRCReady IRq TRunning RFU HiAlert LoAlert 6 r 0 5 r 1 4 r 0 3 r 0 2

0 1 r 0 0 r 1 Tab3-18 Status1Reg register Description Reserved for future use. Set to logic 1, if the CRC Result is zero. For data transmission and reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC coprocessor, during calculation the value changes to 0, when the calculation is done correctly, the value changes to 1. Set to logic 1, when the CRC calculation has finished. This bit is only valid for the CRC coprocessor calculation using the command CalcCRC. This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg). Set to logic 1, if the FM17520s timer unit is running. (The timer will decrement the TCounterValReg with the next timer clock.) Remark: In the gated mode the bit TRunning is set to logic 1, when the timer is enabled by the register bits. This bit is not influenced by the gated signal. Reserved for future use. Set to logic 1, when the numberof bytes stored in the FIFO-buffer fulfills the following equation:

HiAlert = (64 FIFOLength ) WaterLevel Example FIFOLength = 60, WaterLevel = 4 HiAlert = 1 FIFOLength = 59, WaterLevel = 4 HiAlert = 0 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 21 3 FM17520 Register Set Bit Symbol Description 0 LoAlert Set to logic 1, when the numberof bytes stored in the FIFO-buffer fulfills the following equation:

LoAlert = FIFOLength WaterLevel Example FIFOLength = 4, WaterLevel = 4 LoAlert = 1 FIFOLength = 5, WaterLevel = 4 LoAlert = 0 Tab3-19 Status1Reg bits description 3.2.1.9 Status2Reg_address 08h Contain status bits of the Receiver, Transmitter and Data mode detector. 3 6 5 7 4 TempSensClear RFU RFU RFU Crypto1On ModemState 2 1 0 r 0 r 0 r 0

0

0

0 dy 0 Tab3-20 Status2Reg register Bit Symbol Description TempSensClear r/w 0

Crypto1On Set to logic 1, this bit clears the temperature error, if the temperature is below the alarm limit of 125C. Reserved for future use. Reserved for future use. Reserved for future use. This bit indicates that the Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit is only valid in Reader/Writer mode for cards. This bit can only be set to logic 1 by a successful execution of the Authent Command. This bit shall be cleared by software. ModemState shows the state of the transmitter and receiver state machines. Value 000 001 Description IDLE Wait for StartSend in register BitFramingReg TxWait: Wait until RF field is present, if the bit TxWaitRF is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register. Sending RxWait: Wait until RF field is present, if the bit RxWaitRF is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register. Wait for data Receiving 101 110 Tab3-21 Status2Reg bits description 100 011 010 2-0 ModemState Bit Defini tion Acce ss Right s Reset Value 7 6 5 4 3 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 22 3.2.1.10 FIFODataReg_address 09h Input and output port of 64 byte FIFO buffer. 3 FM17520 Register Set Bit Definition Access Rights Reset Value 7 dy x 6 dy x 5 dy x 4 dy x FIFOData 3 dy x 2 dy x 1 dy x 0 dy x Tab3-22 FIFODataReg register Bit Symbol Description 7-0 FIFOData Data input and output port for the internal 64 byte FIFO buffer. The FIFO buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs. Tab3-23 FIFODataReg bits description 3.2.1.11 FIFOLevelReg_address 0Ah Indicate the number of bytes stored in the FIFO. Bit Definition Access Rights Reset Value FlushBuffer FIFOLevel 6 r 0 5 r 0 4 r 0 3 r 0 2 r 0 1 r 0 0 r 0 7 w 0 Tab3-24 FIFOLevelReg register Bit Symbol Description 7 FlushBuffer 6-0 FIFOLevel Set to logic 1, this bit clears the internal FIFO buffers read-pointer and write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0. Indicate the number of bytes stored in the FIFO-buffer. Writing to the FIFODataReg increments, reading decrements the FIFOLevel. Tab3-25 FIFOLevelReg bits description 3.2.1.12 WaterLevelReg_address 0Bh Define the level for FIFO underflow and overflow warning. 3 Bit 4 5 7 6 Definition RFU RFU Access Rights Reset Value 0 0

2 1 0 WaterLevel r/w r/w 0 0 r/w 1 r/w 0 r/w 0 r/w 0 Tab3-26 WaterLevelReg register Bit 7-6 5-0 Symbol

WaterLevel Description Reserved for future use. This register defines a warning level to indicate a FIFO buffer overflow or underflow. The bit HiAlert in Status1Reg is set to logic 1, if the remaining Datasheet FM17520 Contactless Transceiver IC Ver 1.0 23 3 FM17520 Register Set Bit Symbol Description number of bytes in the FIFO buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Tab3-27 WaterLevelReg bits description 3.2.1.13 ControlReg_address 0Ch 3.2.1.14 BitFramingReg_address 0Dh Adjustments for bit oriented frames. Some control bits. Bit 7 Definition TStopNow Access Rights Reset Value w 0 TStartNow RFU RFT RFU RxLastBits 5

0 4

1 3

0 2 r 0 1 r 0 0 r 0 6 w 0 Tab3-28 ControlReg register Bit Symbol Description 7 6 5 4 3 TStopNow TStartNow RFT

2-0 RxLastBits Set to logic 1, the timer stops immediately. Reading this bit will always return 0. Set to logic 1 starts the timer immediately. Reading this bit will always return 0. Reserved for future use. Reserved for production tests. Reserved for future use. Shows the number of valid bits in the last received byte. If 0, the whole byte is valid. Tab3-29 ControlReg bits description Bit 6 5 4 2 1 0 Definition StartSend RxAlign 3 RFU TxLastBits r/w 0 r/w 0 r/w 0 7 w 0 r/w 0

0 Tab3-30 BitFramingReg register r/w 0 r/w 0 Description Access Rights Reset Value Bit Symbol 7 StartSend Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command. Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions. Example:

RxAlign = 0: the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. RxAlign = 1: the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. RxAlign = 7: the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at bit position 0. This bit shall only be used for bitwise anticollision at 106 kbit/s in Communication mode. In all other modes it shall be set to logic 0. Reserved for future use. 6-4 RxAlign 3

Datasheet FM17520 Contactless Transceiver IC Ver 1.0 24 Bit Symbol 2-0 TxLastBits Description Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted. Tab3-31 BitFramingReg bits description 3 FM17520 Register Set 3.2.1.15 CollReg_address 0Eh Define the first bit collision detected on the RF interface. Values AfterColl RFU CollPos NotValid CollPos Bit Definition Access Rights Reset Value 7 r/w 1 6

5 R 1 Tab3-32 CollReg register 0 4 3 2 1 0 R R R R R x x x x x Bit Symbol Description 7 6 5 Values AfterColl

CollPosNotValid 4-0 CollPos If this bit is set to logic 0, all receiving bits will be cleared after a collision. This bit shall only be used during bitwise anticollision at 106 kbit/s, otherwise it shall be set to logic 1. Reserved for future use. Set to logic 1, if no Collision is detected or the Position of the Collision is out of the range of bits CollPos. These bits show the bit position of the first detected collision in a received frame, only data bits are interpreted. Example:

00h indicates a bit collision in the 32th bit 01h indicates a bit collision in the 1st bit 08h indicates a bit collision in the 8th bit These bits shall only be interpreted if bit CollPosNotValid is set to logic 0. Tab3-33 CollReg bits description Bit Definition Access Rights Reset Value EXmode 7 r/w 0 6 r/w 0 5 r/w 0 4 3 2 1 0 EXAddr r/w r/w r/w r/w r/w 0 0 0 0 0 Tab3-34 EXReg register Bit Symbol Description 7-6 EXmode 5-0 EXAddr Access modes to extended registers:

01: writing mode, bit5~0 writes secondary address 10: reading mode, bit5~0 reads secondary address 11: writing mode, bit5~0 writes data 00: reading mode, bit5~0 reads data See section 4.2 Accessing Extended Register for more information about access modes secondary address or data of extended registers Tab3-35 EXReg bits description 3.2.1.16 EXReg_address 0Fh Entrance for access extended registers. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 25 6

0 6

0 3 FM17520 Register Set 3.2.2 Page 1Communication 3.2.2.1 RFU_address 10h Bit Definition Access Rights Reset Value 7

0 RFU RFU RFU RFU RFU RFU RFU RFU 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-36 RFU register Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-37 RFUReg bits description 3.2.2.2 ModeReg_address 11h Define general mode settings for transmitting and receiving. Bit 7 Definition MSBFirst Access Rights Reset Value r/w 0 RFU TxWaitRF RFU PolTin RFT CRCPreset 5 r/w 1 4

1 3 r/w 1 2

1 1 0 r/w r/w 1 1 Tab3-38 ModeReg register Bit Symbol Description 7 6 5 4 3 2 MSBFirst TxWaitRF RFU RFU PolTin RFT 1-0 CRCPreset Set to logic 1, the CRC coprocessor calculates the CRC with MSB first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed. Remark: During RF communication this bit is ignored. Reserved for future use. Set to logic 1 the transmitter in reader/writer mode can only be started, if an RF field is generated. Reserved for future use. PolSigin defines the polarity of the TIN pin. Set to logic 1, the polarity of TIN pin is active high. Set to logic 0 the polarity of TIN pin is active low. Remark: The internal envelope signal is coded active low. Remark: Changing this bit will generate a TinActIRq event. Reserved for production tests. Defines the preset value for the CRC coprocessor for the command CalCRC. Remark: During any communication, the preset values are selected automatically according to the definition in the bits RxMode and TxMode. Value 00 01 10 11 Description 0000 6363 A671 FFFF Tab3-39 ModeReg bits description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 26 3.2.2.3 TxModeReg_address 12h Define the data rate and framing during transmission. 7 6 5 4 3 TxCRCEn TxSpeed InvMod RFU RFU RFU r/w 0 dy dy dy r/w 0 Tab3-40 TxModeReg register 0 0 0 3 FM17520 Register Set 2

0 1

0 0

0 Bit Definition Access Rights Reset Value Bit Symbol 7 TxCRCEn 6-4 TxSpeed 3 2-0 InvMod RFU Definition Access Rights Reset Value Bit 7 Symbol RxCRCEn 6-4 RxSpeed Description Set to logic 1, this bit enables the CRC generation during data transmission. Remark: This bit shall only be set to logic 0 at 106 kbit/s. Defines the bit rate while data transmission. Value 000 001 010 011 100 101 110 111 Set to logic 1, the modulation for transmitting data is inverted. Reserved for future use. Description 106 kbit 212 kbit 424 kbit 848 kbit Reserved Reserved Reserved Reserved Tab3-41 TxModeReg bits description 3.2.2.4 RxModeReg_address 13h Define the data rate and framing during reception. Bit 7 6 5 4 3 RxCRCEn RxSpeed RxNoErr RxMultiple RFU RFU r/w 0 dy 0 dy 0 dy 0 r/w 0 Tab3-42 RxModeReg register 2 r/w 0 1

0 0

0 Description Set to logic 1, this bit enables the CRC calculation during reception. Remark: This bit shall only be set to logic 0 at 106 kbit/s. Defines the bit rate while data transmission. Value 000 001 010 011 100 101 110 111 Description 106 kbit 212 kbit 424 kbit 848 kbit Reserved Reserved Reserved Reserved Datasheet FM17520 Contactless Transceiver IC Ver 1.0 27 3 FM17520 Register Set Bit 3 Symbol RxNoErr 2 RxMultiple 1-0 RFU Description If set to logic 1 a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the Receive and Transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host controller. If set to logic 1, at the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register. Reserved for future use. Tab3-43 RxModeReg bits description 3.2.2.5 TxControlReg_address 14h Control the antenna driver pins TX1 and TX2. Bit Defini tion Acce ss Right Rese s t Value InvTx2RF InvTx1Rf InvTx2RF InvTx1RF 7 On r/w 6 On r/w 5 Off r/w 4 Off r/w 3 Tx2C W r/w 1 0 Tx2RF Tx1RF En En RFU r/w r/w 2

0 1 0 0 0 0 0 0 Tab3-44 TxControlReg register Bit Symbol Description 7 6 5 4 3 2 1 0 InvTx2RFOn InvTx1RfOn InvTx2RFOff InvTx1RFOff Tx2CW RFU Tx2RFEn Tx1RFEn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is enabled. Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is enabled. Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is disabled. Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is disabled. Set to logic 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy carrier. Reserved for future use. Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data. Tab3-45 TxControlReg bits description 3.2.2.6 TxASKReg_address 15h Control the settings of the antenna driver. 5 Bit 6 7 Definiti RFU Force100 RFU RFU RFU RFU RFU RFU 4 3 2 1 0 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 28 3.2.2.7 TxSelReg_address 16h Select the sources for the antenna driver. 3 FM17520 Register Set Bit on Access Rights Reset Value 7

0 6 ASK r/w 0 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-46 TxASKReg register Bit Symbol 7 6 RFU Force100ASK 5-0 RFU Description Reserved for future use. Set to logic 1, Force100ASK forces a 100% ASK modulation independent of the setting in register ModGsPReg. Reserved for future use. Tab3-47 TxASKReg bits description 7

0 00 01 10 11 Bit 6 5 4 3 2 1 0 Definition RFU RFU DriverSel TOutSel r/w 0 r/w 0 r/w 0 Access Rights Reset Value Bit 7-6 Symbol

0 r/w 0 r/w 0 Tab3-48 TxSelReg register r/w 1 Description Reserved for future use. Selects the input of driver Tx1 and Tx2. Value 5-4 DriverSel 3-0 TOutSel 0011 Description Tristate Remark: In soft power down the drivers are only in Tristate mode if DriverSel is set to Tristate mode. Modulation signal (envelope) from the internal coder Modulation signal (envelope) from TIN High level Remark: The HIGH level depends on the setting of InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff. Selects the input for the TOUT Pin. Value 0000 0001 0010 Description Tristate Low level High level TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. Modulation signal (envelope) from the internal coder Serial data stream to be transmitted(before Miller coding) Reserved for future use. Serial data stream received(after Manchester decoding) 0100 0101 0110 0111 1000-1111 Reserved for future use. Tab3-49 TxSelReg bits description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 29 3.2.2.8 RxSelReg_address 17h Select internal receiver settings. 3 FM17520 Register Set Bit 7 6 5 4 3 2 1 0 Definition UartSel Access Rights Reset Value r/w 1 RxWait r/w 0 r/w 0 r/w 0 Tab3-50 RxSelReg register r/w 0 r/w 1 r/w 0 r/w 0 Bit Symbol Description 7-6 UartSel 5-0 RxWait Selects the input of the contactless UART Value 00 01 10 Description Constant Low Manchester with subcarrier from pin TIN Modulation signal from the internal analog module, default NRZ coded signal without subcarrier from pin TIN which is only valid for transfer speeds above 106 kbBd 11 After data transmission, the activation of the receiver is delayed for RxWait bit-clocks. During this frame guard time any signal at pin RX is ignored. This parameter is ignored by the Receive command. All other commands use this parameter. The counter starts with the last modulation pulse of the transmitted data stream. Tab3-51 RxSelReg bits description 3.2.2.9 RxThresholdReg_address 18h Select thresholds for the bit decoder. 6 Bit 7 5 4 2 1 0 Definition Access Rights Reset Value MinLevel RFU CollLevel r/w 1 r/w 0 r/w 0 r/w 0 r/w 1 r/w 0 r/w 0 Tab3-52 RxThresholdReg register 3

0 Bit 7-4 3 Symbol MinLevel

2-0 CollLevel Description Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. Reserved for future use. Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit. Tab3-53 RxThresholdReg bits description 3.2.2.10 DemodReg_address 19h Define demodulator settings. Bit 7 6 5 4 3 2 Definition AddIQ FixIQ RFU TauRcv Access Rights Reset Value r/w 0 r/w 1 r/w 0 r/w 1 Tab3-54 DemodReg register

0 r/w 1 1 0 TauSync r/w 0 r/w 1 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 30 Bit Symbol Description 3 FM17520 Register Set 01 Defines the use of I and Q channel during reception. Remark: FixIQ has to be set to logic 0 to enable the following settings. Value Description 00 Select the stronger channel Select the stronger and freeze the selected during communication combines the I and Q channel Reserved 10 11 If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to I channel. If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to Q channel. Reserved for future use. Changes the time constant of the internal during data reception. Remark: If set to 00, the PLL is frozen during data reception. Changes the time constant of the internal PLL during burst. Tab3-55 DemodReg bits description 7-6 AddIQ 5 4 3-2 1-0 FixIQ

TauRcv TauSync 3.2.2.11 RFU_address 1A h 3.2.2.12 RFU_address 1B h RFU RFU RFU RFU RFU RFU RFU RFU Tab3-56 RFU register Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-57 RFUReg bits description 6

0 6

0 5

0 5

0 4

0 4

0 3

0 3

0 2

0 2

0 1

0 1

0 0

0 0

0 Bit Definition Access Rights Reset Value Bit Definition Access Rights Reset Value 7

0 7

0 RFU RFU RFU RFU RFU RFU RFU RFU Tab3-58 RFU register Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-59 RFUReg bits description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 31 3 FM17520 Register Set 3.2.2.13 TxReg_address 1Ch Control part of transmission parameters in ISO/IEC 14443A. 4 Bit 7 5 6 Definition RFU RFU RFU RFU RFU RFU TxWait Access Rights Reset Value

0

1

1

0 Tab3-60 TxReg register 3

0 2

0 1 0 r/w 1 r/w 0 Bit 7-2 1-0 Symbol RFU TxWait Description Reserved for future use. These bits define the additional response time. Per default 7 bits are added to the value of the register bit. Tab3-61 TxReg bits description 3.2.2.14 RxReg_address 1D h Bit Definition Access Rights Reset Value 6

0 5

0 4 r/w 0 RFU RFU RFU ParityDisable RFU RFU RFU RFU 3

0 3

0 2

0 2

0 1

0 1

0 Tab3-62 RxReg register Description Bit 7-5 Symbol RFU 4 Parity Disable 3-0 RFU Reserved for future use. If this bit is set to logic 1, the generation of the Parity bit for transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled as a data bit. Reserved for future use. Tab3-63 RxReg bits description RFU RFU RFU RFU RFU RFU RFU RFU Bit Definition Access Rights Reset Value 6

0 5

0 4

0 Tab3-64 RFU register 7

0 7

0 3.2.2.15 RFU_address 1Eh Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-65 RFUReg bits description 3.2.2.16 RFU_address 1Fh Definition RFU RFU RFU RFU RFU RFU RFU RFU Bit Access Rights Reset Value 7

1 6

1 5

1 4

0 3

1 2

0 1

1 Tab3-66 RFU register 0

0 0

0 0

1 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 32 3 FM17520 Register Set Symbol Bit 7-0 RFU Reserved for future use. Description Tab3-67 RFUReg bits description 3.2.3 Page 2Configuration 3.2.3.1 RFU_address 20h Bit Definition Access Rights Reset Value 7

0 RFU RFU RFU RFU RFU RFU RFU RFU 6

0 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-68 RFU register Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-69 RFUReg bits description 3.2.3.2 CRCResultMSBReg_address 21h Show the actual result of the CRC calculation. Remark: The CRC is split into two 8-bit register. Remark: Setting the bit MSBFirst in ModeReg register reverses the bit ordering, the byte order is not changed. Bit 7 6 5 4 3 Definition Access Rights Reset Value CRCResultMSB r 1 Tab3-70 CRCResultReg register r 1 r 1 r 1 r 1 Bit Symbol Description 7-0 CRCResultMSB This register shows the actual value of the most significant byte of the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Tab3-71 CRCResultReg bits description 3.2.3.3 CRCResultLSBReg_address 22h 2 r 1 2 r 1 1 r 1 1 r 1 0 r 1 0 r 1 Bit 7 6 5 4 3 Definition Access Rights Reset Value CRCResultLSB r 1 Tab3-72 CRCResultReg register r 1 r 1 r 1 r 1 Bit Symbol Description 7-0 CRCResultLSB This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Tab3-73 CRCResultReg bits description 3.2.3.4 RFU_address 23h Bit 7 6 5 4 3 2 1 0 Definition RFU RFU RFU RFU RFU RFU RFU RFU Datasheet FM17520 Contactless Transceiver IC Ver 1.0 33 Bit Access Rights Reset Value Bit 7-0 3 FM17520 Register Set 7

0 6

0 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-74 RFU register Symbol Description RFU Reserved for future use. Tab3-75 RFUReg bits description 3.2.3.5 ModWidthReg_address24h Control the modulation width settings. Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value r/w 0 r/w 0 Tab3-76 ModWidthReg register r/w 1 ModWidth r/w r/w 0 0 r/w 1 r/w 1 r/w 0 Bit 7-0 Symbol ModWidth Description These bits define the width of the Miller modulation as multiples of the carrier frequency (ModWidth + 1)/fc. The maximum value is half the bit period. Tab3-77 ModWidthReg bits description Bit Definition Access Rights Reset Value 7

0 RFU RFU RFU RFU RFU RFU RFU RFU 6

0 5

0 4

0 3

0 2

0 1

0 0

0 Tab3-78 RFU register 3.2.3.6 RFU_address 25h Bit 7-0 Symbol Description RFU Reserved for future use. Tab3-79 RFUReg bits description 3.2.3.7 RFCfgReg_address 26h Configure the receiver gain. Bit Definition Access Rights Reset Value RFU 7

0 6 5 4 3 2 1 0 RxGain RFU r/w r/w r/w 1 0 0

1

0

0

0 Tab3-80 RFCfgReg register Bit 7 6-4 Symbol RFU RxGain*

Description Reserved for future use. This register defines the receivers signal voltage gain factor:

Value Description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 34 Bit Symbol Description 3 FM17520 Register Set 18 dB 23 dB 18 dB 23 dB 33 dB 38 dB 43 dB 48 dB 000 001 010 011 100 101 110 111 Reserved for future use. Tab3-81 RFCfgReg bits description 3-0 RFU 3.2.3.8 GsNReg_address 27h Select the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Bit 0 1 4 3 2 5 7 6 Definition Access Rights Reset Value r/w 1 Bit Symbol 7-4 CWGsN 3-0 ModGsN CWGsN r/w r/w 1 0 Tab3-82 GsNOnReg register r/w 0 r/w 0 ModGsN r/w 0 r/w 0 r/w 0 Description The value of this register defines the conductance of the output N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance. Remark: The conductance value is binary weighted. Remark: During soft Power-down mode the highest bit is forced to 1. Remark: This value is only used if the driver TX1 or TX2 are switched on. The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Remark: The conductance value is binary weighted. Remark: During soft Power-down mode the highest bit is forced to 1. Remark: This value is only used if the driver TX1 or Tx2 are switched on. Tab3-83 GsNOnReg bits description 3.2.3.9 CWGsPReg_address 28h Define the conductance of the P-driver during times of no modulation. 3 Bit 5 7 6 4 Definition RFU RFU CWGsP r/w

0 0 Tab3-84 CWGsPReg register r/w 0 r/w 1 2 1 0 r/w 0 r/w 0 r/w 0 Access Rights Reset Value

0 Bit 7-6 Symbol

5-0 CWGsP Description Reserved for future use. The value of this register defines the conductance of the output P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Remark: The conductance value is binary weighted. Remark: During soft Power-down mode the highest bit is forced to 1. Tab3-85 CWGsPReg bits description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 35 3.2.3.10 ModGsPReg_address 29h 3 FM17520 Register Set Define the driver P-output conductance during modulation. 4 Bit 6 7 5 3 2 1 0 Definition RFU RFU ModGsP Access Rights Reset Value

0 r/w

0 0 Tab3-86 ModGsPReg register r/w 0 r/w 1 r/w 0 r/w 0 r/w 0 Bit 7-6 Symbol

5-0 ModGsP Description Reserved for future use. The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index. Remark: The conductance value is binary weighted. Remark: During soft Power-down mode the highest bit is forced to 1. Tab3-87 ModGsPReg bits description 3.2.3.11 TModeRegTPrescalerReg_address 2Ah Define settings for the timer. Remark: The Prescaler value is split into two 8-bit registers. 4 Bit 7 5 6 Definition Access Rights Reset Value TAuto TGated TAutoRestart TPrescaler_Hi r/w 0 r/w r/w 0 0 r/w 0 r/w r/w r/w r/w 0 0 0 0 Tab3-88 TModeReg register 3 2 1 0 Bit Symbol Description 7 TAuto 6-5 TGated 4 TAutoRestart 3-0 TPrescaler_Hi Set to logic 1, the timer starts automatically at the end of the transmission in all communication modes at all speeds. The timer stops after the 5th bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is not set. If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to 1. Setting to logic 0 indicates, that the timer is not influenced by the protocol. The internal timer is running in gated mode. Remark: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. Value 00 01 10 11 Set to logic 1, the timer automatically restarts its count-down from TReloadValue, instead of counting down to 0. Set to logic 0 the timer decrements to 0 and the bit TimerIRq is set to logic 1. Defines higher 4 bits for TPrescaler. fTimer = 13.56 MHz/(2*TPreScaler+1) Where TPreScaler = [TPrescaler_HiTPrescaler_Lo] (total 12 bits) Description Non gated mode Gated by TIN Gated by AUX1

Datasheet FM17520 Contactless Transceiver IC Ver 1.0 36 Bit Symbol Description For detailed description, see section 9 Timer Unit. Tab3-89 TModeReg bits description 3.2.3.12 TPrescalerLoReg_address 2Bh 3 FM17520 Register Set Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value r/w 0 r/w 0 r/w 0 TPrescaler_Lo r/w r/w 0 0 r/w 0 r/w 0 r/w 0 Tab3-90 TPrescalerReg register Bit Symbol Description 7-0 TPrescaler_Lo Defines lower 8 bits for TPrescaler. The fTimer formula refers to the description of Tprescaler_Hi in TmodeReg register. Tab3-91 TPrescalerReg bits description 3.2.3.13 TReloadHiReg_address 2Ch Describe the 16-bit long timer reload value. 3.2.3.14 TReloadLoReg_address 2Dh Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value TReloadVal_Hi r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 Tab3-92 TReloadHiReg register Bit Symbol Description 7-0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. Tab3-93 TReloadHiReg bits description Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value TReloadVal_Lo r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 Tab3-94 TReloadLoReg register Bit Symbol Description 7-0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. Tab3-95 TReloadLoReg bits description 3.2.3.15 TcounterValHiReg_address 2Eh Show the current value of the timer. Bit Definition Access Rights Reset Value 7 r x 6 r x TCounterVal_Hi 5 r x 4 r x 3 r x 2 r x 1 r x 0 r x Tab3-96 TCounterValHiReg register Datasheet FM17520 Contactless Transceiver IC Ver 1.0 37 3 FM17520 Register Set 0 r x 0

0 Bit 7-0 Symbol Description TCounterVal_Hi Current value of the timer, higher 8 bits. Tab3-97 TCounterValHiReg bits description 3.2.3.16 TcounterValLoReg_address 2Fh Bit Definition Access Rights Reset Value 7 r x 6 r x 5 r x TCounterVal_Lo 4 r x 3 r x 2 r x 1 r x Tab3-98 TCounterValLoReg register Bit 7-0 Symbol Description TCounterVal_Lo Current value of the timer, lower 8 bits. Tab3-99 TCounterValLoReg bits description 3.2.4 Page 3Test 3.2.4.1 RFU_address 30h 4

0 4

0 RFU RFU RFU RFU RFU RFU RFU RFU Bit Definition Access Rights Reset Value 7

0 6

0 5

0 3

0 2

0 1

0 Tab3-100 RFU register Bit 7-0 Symbol RFU Description Reserved for future use. Tab3-101 RFUReg bits description 3.2.4.2 TestSel1Reg_address 31h General test signal configuration. 6 Bit 7 5 Definition RFU RFU RFU RFU RFU TstBusBitSel Access Rights Reset Value

0

0

0 Tab3-102 Bit 7-3 Symbol

2-0 TstBusBitSel 3

0 2 r/w 0 1 0 r/w 0 r/w 0 TestSel1Reg register Description Reserved for future use. Select the TestBus bit from the testbus to be propagated to TOUT. If AnalogSelAux2[3:0] in AnalogTestReg register is FFh, the selectable TestBus bit is propagated to AUX1 or AUX2 meanwhile. Tab3-103 TestSel1Reg bits description 3.2.4.3 TestSel2Reg_address 32h General test signal configuration and PRBS control. Bit Definition Access Rights 7 r/w 6 5 4 3 2 1 0 TstBusFlip PRBS9 PRBS15 TestBusSel r/w r/w r/w r/w r/w r/w r/w Datasheet FM17520 Contactless Transceiver IC Ver 1.0 38 Bit Reset Value 7 0 6 0 Tab3-104 5 0 4 0 3 0 2 0 1 0 0 0 TestSel2Reg register 3 FM17520 Register Set Bit Symbol Description 7 TstBusFlip 6 PRBS9 5 PRBS15 4-0 TestBusSel If set to logic 1, the testbus is mapped to the parallel port by the following order:

TstBusBit2, TstBusBit6, TstBusBit5, TstBusBit0. Refer to section 14 Testsignals. Starts and enables the PRBS9 sequence according ITU-TO150. Remark: All relevant registers to transmit data have to be configured before entering PRBS9 mode. Remark: The data transmission of the defined sequence is started by the Transmit command. Starts and enables the PRBS15 sequence according ITU-TO150. Remark: All relevant registers to transmit data have to be configured before entering PRBS15 mode. Remark: The data transmission of the defined sequence is started by the Transmit command. Selects the testbus. Refer to section 15 Testsignals. Tab3-105 TestSel2Reg bits description 3.2.4.4 TestPinEnReg_address33h Enable the pin output driver on D1-D4. Bit Definition Access Rights Reset Value RFU 7

1 6 5 4 3 2 1 RFU RFU TestPinEn r/w r/w 0 0 TestPinEnReg register r/w 0

0

0 Tab3-106 RFU 0

0 r/w 0 Bit 7-5 Symbol RFU 4-1 TestPinEn 0 RFU Description Reserved for future use. Enables the output driver on the D1~D4 test pins. Example:

Setting bit 1 to 1 enables D1 Setting bit 4 to 1 enables D4 Reserved for future use. Tab3-107 TestPinEnReg bits description 3.2.4.5 TestPinValueReg_address 34h Define the values for the 4-bit parallel port when it is used as I/O. Bit 7 6 4 3 2 1 Definition UselO RFU RFU Access Rights Reset Value r/w 0

0 Tab3-108 5

0 TestPinValue r/w r/w 0 0 r/w 0 r/w 0 TestPinValueReg register RFU 0

0 Bit 7 Symbol UselO Description Set to logic 1, this bit enables the I/O functionality for the 4-bit parallel port in case one of the serial interfaces is used. The input/output behavior is defined by TestPinEn in register Datasheet FM17520 Contactless Transceiver IC Ver 1.0 39 3 FM17520 Register Set Bit Symbol Description 6-5 RFU 4-1 TestPinValue 0 RFU TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal. Reserved for future use. Defines the value of the 4-bit parallel port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. Remark: Reading the register indicates the actual status of the pins D4~D1 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back. Reserved for future use. Tab3-109 TestPinValueReg bits description 3.2.4.6 TestBusReg_address 35h Show the status of the internal testbus. 0 r x 0

0 Bit 7 6 5 4 3 Definition Access Rights Reset Value r r x x Tab3-110 TestBus r r x x TestBusReg register r x 2 r x 1 r x Bit 7-0 Symbol TestBus Description Shows the status of the internal testbus. The testbus is selected by the register TestSel2Reg. See section 15 Testsignals. Tab3-111 TestBusReg bits description 3.2.4.7 TestCtrlReg_address 36h Test control. Bit 6 Definition RFT AmpRcv RFU RFU RFT RFT RFT RFT 7

0 5

0 4

0 3

0 2

0 1

0 TestCtrlReg register r/w 1 Tab3-112 Access Rights Reset Value Bit 7 Symbol 0 6 AmpRcv 5-4 3-0 RFU RFT Description Reserved for production tests. If set to logic 1, the internal signal processing in the receiver chain is performed non-linear. This increases the operating distance in communication modes at 106 kbit/s. Remark: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear. Reserved for future use. Reserved for production tests. Tab3-113 TestCtrlReg bits description 3.2.4.8 RFTReg_address 37h Bit 7 6 Definition Access Rights Reset Value 5 r x 4 r x RFT 3 r x RFTReg register r x r x Tab3-114 2 r x 1 r x 0 r x Datasheet FM17520 Contactless Transceiver IC Ver 1.0 40 3 FM17520 Register Set Bit 7-0 Symbol RFT Description Reserved for production tests. Tab3-115 RFTReg bits description 3.2.4.9 AnologTestReg_address 38h Control the pins AUX1 and AUX2. Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value AnalogSelAux1 AnalogSelAux2 r/w 0 r/w 0 Tab3-116 r/w 0 AnologTestReg register r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 Bit Symbol Description 7-4 AnalogSelAux1 Controls the AUX pin. 3-0 AnalogSelAux2 Tristate Remark: All test signals are described in section 15 Testsignals. Value Description 0000 0001 Output of TestDAC1 (AUX1), output of TestDAC2 (AUX2) [1]

0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Testsignal Corr1 [1]

Reserved Testsignal MinLevel [1]

Testsignal ADC channel I [1]

Testsignal ADC channel Q [1]

Reserved Testsignal for production test [1]

Reserved HIGH LOW TxActive RxActive Subcarrier detected TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg. 1111 Remark[1]: current output. A 1k ohm pull-down resistance is suggested to plus with AUX pin. Tab3-117 AnologTestReg bits description 3.2.4.10 TestDAC1Reg_address 39h Define the testvalue for TestDAC1. Bit 5 4 1 0 3 2 TestDAC1 Definition RFT RFU Access Rights Reset Value 7

0 6

0 r/w x TestDAC1Reg register r/w x r/w x Tab3-118 r/w x r/w x r/w x Bit 7 6 Symbol Description

Reserved for production tests. Reserved for future use. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 41 Bit 5-0 Symbol TestDAC1 Description Defines the testvalue for TestDAC1. The output of the DAC1 can be switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg. Tab3-119 TestDAC1Reg bits description 3 FM17520 Register Set 3.2.4.11 TestDAC2Reg_address 3Ah Define the testvalue for TestDAC2. Bit 5 4 1 0 3 2 TestDAC2 Definition RFU RFU Access Rights Reset Value 6

0 r/w x TestDAC2Reg register r/w x r/w x Tab3-120 r/w x r/w x r/w x Bit 7 6 5-0 Symbol

TestDAC2 Description Reserved for future use. Reserved for future use. Defines the testvalue for TestDAC2. The output of the DAC2 can be switched to AUX2 by setting AnalogSelAux2 to 0001 in register AnalogTestReg. Tab3-121 TestDAC2Reg bits description 3.2.4.12 TestADCReg_address 3Bh Show the actual value of ADC I and Q channel. 5 Bit 6 7 Definition Access Rights Reset Value ADC_I r x r x 4 r x 3 r x Tab3-122 TestADCReg register ADC_Q Bit 7-4 3-0 Symbol ADC_I ADC_Q Description Shows the actual value of ADC I channel. Shows the actual value of ADC Q channel. TestADCReg bits description Tab3-123 3.2.4.13 RFTReg_address 3Ch Bit 6 5 4 3 Definition RFT RFT RFT RFT RFT RFT RFT RFT 2 r x 2

1 1 r x 1

1 0 r x 0

1 Access Rights Reset Value

1 Tab3-124

1

1

1 RFTReg register Bit 7-0 Symbol

Description Reserved for production tests. Tab3-125 RFTReg bits description 7

0 r x 7

1 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 42 7

0 7

0 7

0 2

0 2

0 2

0 1

0 1

1 1

0 0

0 0

1 0

0 3.2.4.14 RFTReg_address 3Dh Bit 6 5 4 3 Definition RFT RFT RFT RFT RFT RFT RFT RFT 3 FM17520 Register Set Access Rights Reset Value

0 Tab3-126

0

0

0 RFTReg register Bit 7-0 Symbol

Description Reserved for production tests. Tab3-127 RFTReg bits description 3.2.4.15 RFTReg_address 3Eh Bit 6 5 4 3 Definition RFT RFT RFT RFT RFT RFT RFT RFT Access Rights Reset Value

0 Tab3-128

0

0

0 RFTReg register Bit 7-0 Symbol

Description Reserved for production tests. Tab3-129 RFTReg bits description 3.2.4.16 RFTReg_address 3Fh Bit 6 5 4 3 Definition RFT RFT RFT RFT RFT RFT RFT RFT Access Rights Reset Value

0 Tab3-130

0

0

0 RFTReg register Bit 7-0 Symbol

Description Reserved for production tests. Tab3-131 RFTReg bits description 3.2.5 Extended Register 3.2.5.1 HpdCtrl_address 0F/03h FM17520 implements a set of extended registers by taking advantage of 0F address. Detailed extended registers accessing description refers to section 4.2 Accessing Extended Register. Definition ExMode HPDEn Bit Access Rights Reset Value 7-6 r/w 00 5 r/w 0 4 r/w 0 3 r/w 0 2 RFT r/w 0 1 0 r/w 0 r/w 0 Tab3-132 HpdCtrl register Bit Symbol Description 7-6 ExMode Mode bits of extended registers. For details, see section 4.5 Accessing Extended Register. Configured according to different access requirements. The 00 is always back when reading them. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 43 3.2.5.2 UseRet_address 0F/1Bh 3 FM17520 Register Set Bit Symbol Description 5 HPDEn 4-0 RFT Low power mode control. Set to 0: chip enter into DPD mode combined with pin NPD=0, and register LPCDEn=0 (default value). Set to 1: chip enter into HPD mode combined with pin NPD=0, and register LPCDEn=0 (default value).

(When setting with HPDEn=0, LPCDEn=1, chip enter into LPCD mode. ) Reserved for production tests. Please keep all zero. Tab3-133 HpdCtrl bits description Bit Definition ExMode Access Rights Reset Value 7-6 r/w 00 5 RFU r/w 0 UseRet 4 r/w 1 3 r/w 0 Tab3-134 UseRet register 2 1 0 RFT r/w 0 r/w 0 r/w 0 Bit Symbol Description 4 UseRet 3-0 RFT Set to 1, the retention of key registers will be excuted in HPD or LPCD mode. That can simplify the initialization when out of HPD or LPCD mode. Setting to 0 indicates the retention invalid. Reserved for production tests. Please keep all zero. Tab3-135 UseRet bits description Definition ExMode LVDIrq LVDEff LVDIe LVDctrl Bit Access Rights Reset Value 7-6 r/w 00 5 RFU r/w 0 4 r/w 0 3 2 r/w 0 r/w 0 1 r/w 1 0 r/w 0 Bit 4 3 2 Symbol LVDIrq LVDEff LVDIe 1-0 LVDctrl Tab3-136 LVDctrl register Description Set to 1, when there is a Low Voltage alarm. Cleared by writing 0. Set to 0, Interrupt Request occurs when Low Voltage alarm. Set to 1, digit circuit resets when Low Voltage alarm. Setting this bit enables LVDIrq. The LVDIrq is disabled by default. Low Voltage Detection control:

00disable Low Voltage Detection 01alert when lower than 1.9V 10alert when lower than 2.1V(default value) 11alert when lower than 2.4V Tab3-137 LVDctrl bits description Remark: Please hold default values for the other extended registers in different address. Or uncertain consequence may occur. 3.2.5.3 LVDctrl_address 0F/1Dh Datasheet FM17520 Contactless Transceiver IC Ver 1.0 44 4 Host Interfaces 4 Host Interfaces 4.1 SPI Interface A serial peripheral interface (SPI compatible) is supported by FM17520 to enable high-speed (up to 10Mbit/s) communication to the host. The FM17520 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. 4.1.1 SPI Read Data Reading data using SPI requires the byte order shown in Tab 4-1 to be used. The first byte sent defines both the mode and the address. Byte 1 Byte n+1 Byte n Byte 0 Byte 2 Line MOSI MISO address 0 address 1 address 2 X data 0 data 1 address n data n-1 00 data n To Tab4-1 MOSI and MISO byte order 4.1.2 SPI Write Data Writing data using SPI requires the byte order shown in Tab 4-2 to be used. The first byte sent defines both the mode and the address. Line MOSI MISO Byte 0 address 0 X Byte 1 data 0 X Byte 2 data 1 X To Byte n Byte n+1 data n-1 data n X X Tab4-2 MOSI and MISO byte order 4.1.3 SPI Address Byte The first byte, defining mode and address, has to meet the following format in Tab 4-3. The MSB of the first byte defines the mode used. To read data from the FM17520 the MSB is set to logic 1. To write data to the FM17520, the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is always set to logic 0. 7MSB 1 = read 0 = write 0LSB address 1 0 6 4 3 5 2 Tab4-3 Address byte format 4.2 Accessing Extended Register The extended registers of FM17520 shall be accessed by two stages of address. All kinds of host interfaces can access the extended registers. The primary address is always set to 0Fh. The 6-bit secondary address can be latched by writing 0x0F register as usual. Tab 4-4 lists the byte definition of extended register at 0x0F. 7MSB 0LSB 1 6 2 3 4 5

=01

=10

=11

=00 Secondary address for extended register write access Secondary address for extended register read access Data for extended register write access Data for extended register read access Tab4-4 Byte definition of extended register Datasheet FM17520 Contactless Transceiver IC Ver 1.0 45 4 Host Interfaces 4.2.1 Write Extended Register The procedure for writing common registers of FM17520:

1. write address of target common register, and set writing mode meanwhile 2. write data to target common register The procedure for writing an extended register is as following 4 steps:

1. write 0F address, and set writing mode(according to SPI specification) 2. write secondary address of target extended register(01b + 6-bit secondary address) 3. write 0F address, and set writing mode(according to SPI specification) 4. write data to target extended register(11b + 6-bit data) Fig 4-1 lists the writing flow:

4.2.2 Read Extended Register Fig4-1 Extended register write progress The procedure for reading common registers of FM17520:

1. write address of target common register, and set reading mode meanwhile 2. read data back from target common register The procedure for reading an extended register is as following 4 steps:

1. write 0F address, and set writing mode(according to SPI specification) 2. write secondary address of target extended register(10b + 6-bit secondary address) 3. write 0F address, and set reading mode(according to SPI specification) 4. read data back from target extended register(00b + 6-bit data) Fig 4-2 lists the reading flow:

Fig4-2 Extended register read progress Datasheet FM17520 Contactless Transceiver IC Ver 1.0 46 Input 0F+W RegData 01+ExtWrRegAdrr RegAddr 0F+W RegData 11+ExtWrRegData Input 0F+W 10+ExtRdRegAdrr 0F+R Output RegData 00+ExtRdRegData 5 Analog Interface And Contactless UART 5 Analog Interface And Contactless UART 5.1 General FM17520 supports the external host online with framing and error checking of the contactless protocol requirements up to 848 kBd. It is supported thar an external circuit can be connected to the communication interface pins TIN and TOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates and processes bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols. Remarks: The size and tuning of the antenna and the power supply voltage have an important impact on the RF performance and operating distance. 5.2 TX Driver TX1 and TX2 are both contactless RF transmitting pins. The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering. The signal on pins TX1 and TX2 can be configured using the TxControlReg register. The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning. The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds. Tx1RF En Bit Force10 0ASK Bit InvTx1 RFOn Bit InvTx1 RFOff Bit Enve lope Pin TX1 GSPMos GSNMos Remarks X 0 0 1 0 1 X 0 1 1 X X X X X 0 1 0 1 0 1 X X pMod RF pCW RF pMod RF pCW RF 0 pMod RF_n pCW X nMod nCW nMod nCW nMod nCW Tab5-1 Controlling signals and settings on pin TX1 not specified if RF is switched off 100 % ASK: pin TX1pulled to logic 0,independent of theInvTx1RFOff bit Tx1RF En Bit Force10 0ASK Bit Tx2 CW Bit InvTx2 RFOn InvTx2 RFOff Bit Bit Enve lope Pin TX2 GSPMos GSNMos Remarks 0 X X X X X X X X X X X 0 1 0 1 X 0 1 0 0 1 pMod RF RF pCW RF_n pMod RF_n pCW RF pCW nMod nCW nMod nCW nCW 1 0 not specified if RF is switched off

conductance Datasheet FM17520 Contactless Transceiver IC Ver 1.0 47 5 Analog Interface And Contactless UART Tx1RF En Bit Force10 0ASK Bit Tx2 CW Bit InvTx2 RFOn InvTx2 RFOff Bit Bit Enve lope Pin TX2 GSPMos GSNMos Remarks 1 1 0 1 0 1 0 1 X X X X X X 0 1 0 1 X X RF_n pCW nCW pMod 0 pCW RF pMod 0 RF_n pCW RF pCW RF_n pCW nMod nCW nMod nCW nCW nCW Tab5-2 Controlling signals and settings on pin TX2 always CW forthe Tx2CW bit 100 % ASK:

pinTX2 pulledto logic 0(independe nt oftheInvTx2 RFOn/InvTx 2RFOff bits) pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register. pMod: PMOS conductance value for modulation defined by the ModGsPReg register. nCW: NMOS conductance value for continuous wave defined by the GsNRegregisters CWGsN[3:0]

The following abbreviations have been used in Tab 5-1 and Tab 5-2:

RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2. RF_n: inverted 13.56 MHz clock. GSPMos: conductance, configuration of the PMOS array. GSNMOS: conductance, configuration of the NMOS array. bits. bits. X: do not care. Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg andGsNReg registers are used for both drivers. nMod: NMOS conductance value for modulation defined by the GsNReg registersModGsN[3:0]

5.3 Serial Data Switch The analog front end and digital processing block of FM17520 can both connected with external signals by pins Tin and Tout. The TIN pin is capable of processing external digital signals on transfer speeds above 424 kbps. And internal signals can be output through TOUT pin. This function allows the analog front end of the FM17520 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Fig5-1 Serial data switch for TX1 and TX2 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 48 6 CRC Coprocessor 6 CRC Coprocessor The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg The following CRC coprocessor parameters can be configured:

registers CRCPreset[1:0] bits setting 8-bit registers representing the higher and lower bytes. The CRC polynomial for the 16-bit CRC is fixed to x16+x12+x5+1 The CRCResultReg register indicates the resultof the CRC calculation. This register is split into two The ModeReg registers MSBFirst bit indicates that data will be loaded with the MSB first. Parameter CRC register length CRC algorithm CRC preset value Value 16-bit CRC algorithm according to ISO/IEC 14443 A and ITU-T 0000h, 6363h, A671h or FFFFh depending on the setting of the ModeReg registers CRCPreset[1:0] bits Tab6-1 CRC coprocessor parameters Datasheet FM17520 Contactless Transceiver IC Ver 1.0 49 7 FIFO Buffer 7 FIFO Buffer FM17520 implements an 8*64 bit FIFO buffer.It buffers the input and output data streambetween the host and the FM17520s internal state machine. This makes it possible tomanage data streams up to 64 bytes long without the need to take timing constraints intoaccount. 7.1 Accessing FIFO Buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register.Writing to this register stores one byte in the FIFO buffer and increments the internal FIFObuffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and increments the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelRegregister. When the microcontroller starts a command, the FM17520 can, while the command is inprogress, access the FIFO buffer according to that command. The microcontrollermustensure that there are not any unintentional FIFO buffer accesses. 7.2 Controlling FIFO Buffer The FIFO buffer pointers can be reset by setting FIFOLevelReg registers FlushBuffer bitto logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorRegregisters BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longeraccessible allowing the FIFO buffer to be filled with another 64 bytes. 7.3 FIFO Buffer Status Information The host can get the following FIFO buffer status information:

Number of bytes stored in the FIFO buffer: FIFOLevelReg registers FIFOLevel[6:0]. cleared by setting the FIFOLevelReg registers FlushBuffer bit. FIFO buffer almost full warning: Status1Reg registers HiAlert bit. FIFO buffer almost empty warning: Status1Reg registers LoAlert bit. FIFO buffer overflow warning: ErrorReg registers BufferOvfl bit. The BufferOvfl bitcan only be The FM17520 can generate an interrupt signal when:

ComIEnReg registers LoAlertIEn bit is set to logic 1. It activates pin IRQ whenStatus1Reg registers LoAlert bit changes to logic 1. ComIEnReg registers HiAlertIEn bit is set to logic 1. It activates pin IRQ whenStatus1Reg registers HiAlert bit changes to logic 1. If the number of remaining bytes in FIFO buffer equals to or be less than the one defined by WaterLevel register, the HiAlert bit will be set. It is generated according to following equation:

HiAlert =(64 - FIFOLength) WaterLevel If the number of written bytes in FIFO buffer equals to or be less than the one defined by WaterLevel register, the LoAlert bit will be set. It is generated according to following equation:

LoAlert = FIFOLength WaterLevel Datasheet FM17520 Contactless Transceiver IC Ver 1.0 50 8 Interrupt Request System 8 Interrupt Request System The FM17520 indicates certain events by setting the Status1Reg registers IRq bit and, ifactivated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 8.1 Interrupt Sources Overview Tab 8-1 shows the available interrupt bits, the corresponding source and the condition for its activation. Interrupt Flag Interrupt Source Trigger Action TimerIRq TxIRq CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq timer unit transmitter CRC coprocessor receiver ComIrqReg register FIFO buffer FIFO buffer contactless UART the timer counts from 1 to 0 a transmitted data stream ends all data from the FIFO buffer has been processed a received data stream ends command execution finishes the FIFO buffer is almost full the FIFO buffer is almost empty an error is detected Tab8-1 Interrupt sources The ComIrqReg registers TimerIRq interrupt bit indicates an interrupt setby the timer unit which is set when the timer decrements from 1 to 0. The ComIrqReg registers TxIRq bit indicates that the transmitter has finished. If the statechanges from sending data to transmitting the end of the frame pattern, the transmitterunit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqRegregisters CRCIRq bit after processing all the FIFO buffer data which is indicated byCRCReady bit = 1. The ComIrqReg registers RxIRq bit indicates an interrupt when the end of the receiveddata is detected. The ComIrqReg registers IdleIRq bit is set if a command finishes andthe Command[3:0] value in the CommandReg register changes to Idle. The ComIrqReg registers HiAlertIRq bit is set to logic 1 when the Status1Reg registersHiAlert bit is set to logic 1 which means that the FIFO buffer has reached the levelindicated by the WaterLevel[5:0] bits. The ComIrqReg registers LoAlertIRq bit is set to logic 1 when the Status1Reg registersLoAlert bit is set to logic 1 which means that the FIFO buffer has reached the levelindicated by the WaterLevel[5:0] bits. The ComIrqReg registers ErrIRq bit indicates an error detected by the contactless UARTduring send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 51 9 Timer 9 Timer Time-out counter Stop watch Programmable one-shot Periodical trigger FM17520 implements a timer unit internally. The external host controller may use the timer to manage timing relevant tasks. The timer unit may work in one of the following modes:

Watch-dog counter The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer-related bits are set and these bits can be used to generate an interrupt. Timer The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter. The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between0 and 4095 in register TModeReg and TPrescalerReg. The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg. The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by settingthe TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on the configuration the timer will stop at 0 or restart with the value from register TReloadReg. The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually stopped by TStopNow in register ControlReg. Furthermore the timer can be activated automatically by setting the bit TAuto in theregister TModeReg to fulfill dedicated protocol requirements automatically. The time delay of a timer stage is the reload value +1. The definition of total time is:

t = ((TPrescaler*2+1)*TReload+1)/13.56MHz Maximum time:TPrescaler = 4095TReloadVal = 65535

=>tmax =(2*4095+1)*65536/13.56 MHz = 39.59s Example:

To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169. The timer has now an input clock of 25 us.The timer can count up to 65535 timeslots of each 25s. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 52 10 Power Reduction Modes 10 Power Reduction Modes FM17520 supports three power reduction modes and can adapt to different power requirements:

Deep Power Down mode Hard Power Down mode Soft Power Down mode 10.1 Deep Power Down The Deep Power Down mode of FM17520 turns off all digital circuits supply and the oscillator. All bi-directional I/O pins are set to three-state output, while all input pins are separated from internal circuit. FM17520 will get into DPD mode when the pad NPD pulled down if bit5 of extended register at 0F/03h is 0 (default value). The device exited DPD mode automatically after the NPD turns HIGH. Then all of configuration and initialization need to be reset. 10.2 Hard Power Down The Hard Power Down mode of FM17520 turns off the oscillator and the supply of most digital circuit. All bi-directional I/O pins are set to three-state output. All input pins are separated from internal circuit. FM17520 will get into HPD mode when the pad NPD pulled down if bit5 of extended register at 0F/03h is 1. FM17520 provides data retention for key registers under HPD mode. And when exit from HPD mode, FM17520 will resume all these key registers automatically. For details of retention registers, see section 10.2.1 Data Retention in HPD Mode. When exit HPD mode, re-initialization is necessary, if the data retention function is disabled (set bit4 of UseRet register 0F/1Bh to 0). 10.2.1 Data Retention in HPD Mode The 25-byte data of internal buffer related to Mem command will keep unchanged under HPD mode, no matter the data retention function is enabled or not. The key registers FM17520 provides in data retention function :

Register Address Retention bit CommIEnReg 02h DivIEnReg CollReg TxModeReg RxModeReg 03h 0Eh 12h 13h 7 6 5 4 3 2 1 0 7 4 2 7 7 3 7 3 2 IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn IRQPushPull TinActIEn CRCIEn ValuesAfterColl TxCRCEn InvMod RxCRCEn RxNoErr RxMuliple Datasheet FM17520 Contactless Transceiver IC Ver 1.0 53 Register Address Retention bit 10 Power Reduction Modes TxASKReg RxSelReg RxThresholdReg DemodReg ModWidthReg RFCfgReg GsNReg CWGsPReg ModGsPReg TModeReg TPrescalerLoReg TreloadValHiReg TReloadValLoReg 15h 17h 18h 19h 24h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh Force100ASK RxWait 6 5:0 7:4 MinLevel 2:0 CollLevel AddIQ 7:6 FixIQ 5 3:2 TauRcv 1:0 TauSync 7:0 ModWidth RxGain[2:0]

6:4 7:4 CWGsN 3:0 ModGSN 5:0 5:0 ModGsP[5:0]

7 6:5 4 3:0 7:0 7:0 7:0 TAuto Tgated TAutoRestart Tprescaler_Hi TPrescaler_Lo TReloadVal_Hi TReloadVal_Lo CWGsP Tab10-1 List of retention registers in HPD mode 10.3 Soft Power Down FM17520 enters Soft Power-down mode immediately after the CommandReg registers PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input and output pins do not change their state during SPD mode. Meanwhile, all register values, the FIFO buffer content and the configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediatelly clear it. It is cleared automatically by the FM17520 when Soft Power-down mode is exited. 10.4 Transmitter Off Mode In Transmitter Off mode, FM17520 switchs off the internal antenna drivers thereby, turning off the RF field. The Transmitter Off mode is entered by setting the TxControlReg registers Tx1RFEn bit and Tx2RFEn bit to logic 0. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 54 11 Low Voltage Detection FM17520 could detect supplys voltage and alarm when its voltage is low enough. The monitoring voltage can be configured by setting the LVDctrl register. As default, interrupt and alarm will occur when AVDD voltage is once lower than the monitoring one. The LVDctrl register can also be configured as low voltage reset mode. But that mode will limit the minimum operating voltage. 11 Low Voltage Detection Datasheet FM17520 Contactless Transceiver IC Ver 1.0 55 12 Oscillator Circuitry 12 Oscillator Circuitry Fig12-1 Quartz crystal connection The FM17520s clock provides a time basis for the synchronous systems encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 56 13 Reset And Oscillator Start-Up Time 13 Reset And Oscillator Start-Up Time 13.1 Reset Timing Requirements The reset signal is filtered bya spike filter before it enters thedigital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,the signal must be LOW for at least 100 ns. 13.2 Oscillator Start-Up Time If the FM17520 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the FM17520 depends on the oscillatoruesd and is shown in Fig 13-1. Fig13-1 Oscillator start-up time The timetstartup is the start-up time of the crystal oscillator circuit. The crystal oscillator start-uptime is defined by the crystal. The timetd is the internal delay time of the FM17520 when the clock signal is stable before the FM17520 can be addressed. The delay time is td = 1024/(27.12MHz) = 37.76s The timetOSC is the sum of td and tstartup. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 57 14 Command Set 14 Command Set 14.1 General Description 14.2 General Behavior The FM17520 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. Each command that needs a certain number of arguments, starts procession only when it has received Each command that needs a data bit stream(or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the Transceive command. Using this command, transmission is started with the BitFramingReg registers StartSend bit. the correct number of arguments from the FIFO buffer. command arguments and/or the data bytes to the FIFO buffer and then start the command. register, for example, the Idle command. Each command can be interrupted by the host writing a new command code to the CommandReg The FIFO buffer is not automatically cleared when commands start. This makes it possible to write 14.3 FM17520 Command Overview Command Command Code Action Idle Mem Generate RandomID CalcCRC Transmit Receive Transceive

Authent SoftReset 0000 0001 0010 0011 0100 1000 1100 1101 1110 1111 NoCmdChange 0111 no action, cancels current command execution stores 25 bytes into the internal buffer generates a 10-byte random ID number activates the CRC coprocessor transmits data from the FIFO buffer no command change, can be used the CommandReg register bits without affecting the command, for example, the PowerDown bit activates the receiver circuits transmits data from FIFO buffer to antenna and automatically to modify activates the receiver after transmission reserved for future use performs the M1 standard authentication as a reader resets FM17520 Tab14-1 Command overview 14.3.1 IDLE 14.3.2 Mem Place the FM17520 in Idle mode. The Idle command also terminates itself. Transfer 25 bytes from the FIFO buffer to the internal buffer. To read out the 25 bytes from the internal buffer the Mem command must be started with an empty FIFO buffer. In this case, the 25 bytes are transferred from the internal buffer to the FIFO. During a hard power-down, the 25 bytes in the internal buffer remain unchanged and are lost when in DPD mode or the power supply is removed from the FM17520. This command automatically terminates when finished and the Idle command becomes active. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 58 14 Command Set 14.3.3 Generate RandomID 14.3.4 CalcCRC This command generates a 10-byte random number and then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the FM17520 returns to Idle mode. The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte written to the FIFO buffer is added to the calculation. The CRC preset value is controlled by the ModeReg registers CRCPreset[1:0] bits. The value is loaded into the CRC coprocessor when the command starts. This command must be terminated by writing a command to the CommandReg register, such as, the Idle command. 14.3.5 Transmit The FIFO buffer content is immediately transmitted after starting this command. Beforetransmitting the FIFO buffer content, all relevant registers must be set for datatransmission. This command automatically terminates when the FIFO buffer is empty. It can beterminated by another command written to the CommandReg register. 14.3.6 NoCmdChange 14.3.7 Receive This command does not influence any running command in the CommandReg register. Itcan be used to manipulate any bit except the CommandReg register Command[3:0] bits,for example, the RcvOff bit or the PowerDown bit. The FM17520 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed. Remark: If the RxModeReg registers RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register. 14.3.8 Transceive This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream. Each transmit process must be started by setting the BitFramingReg registers StartSendbit to logic 1. This command must be cleared by writing any command to the CommandReg register. Remark: If the RxModeReg registers RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically. 14.3.9 Authent This command manages M1 authentication to enable a secure communication to any M1 Mini, M1 1K and M1 4K card. The following data is written to theFIFO buffer before the command can be activated:

Authentication command code (60h, 61h) Block address Card serial number byte 0 Card serial number byte 1 Card serial number byte 2 Card serial number byte 3 Sector key byte 0 Sector key byte 1 Sector key byte 2 Sector key byte 3 Sector key byte 4 Sector key byte 5 Datasheet FM17520 Contactless Transceiver IC Ver 1.0 59 14 Command Set In total 12 bytes are written into the FIFO. Remark: When the Authent command is active, all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg registers WrErr bit is set. This command automatically terminates when the M1 card is authenticated and theStatus2Reg registers Crypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, theTimerIRq bit can be used as the termination criteria. During authentication processing, theRxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination ofthe Authent command, either after processing the protocol or writing Idle to the CommandReg register. If an error occurs during authentication, the ErrorReg registers ProtocolErr bit is set tologic 1 and the Status2Reg registers Crypto1On bit is set to logic 0. 14.3.10 SoftReset This command performs a reset of the FM17520. The 25-bytes configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 60 15 Testsignals 15.1 Testbus 15 Testsignals The testbus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the FM17520. The testbus allows to route internal signals to the digital interface. The testbus signals are selected by accessing TestBusSel in register TestSel2Reg. Pins D6 Testsignal sdata D5 scoll D4 D3 D2 svalid sover RCV_reset D1 RFU Tab15-1 Testsignal routing (TestSel2Reg = 07h) Pins Testsignal Description D6 D5 D4 D3 D2 D1 sdata scoll svalid sover RCV_reset RFU shows the actual received data stream shows if in the actual bit a collision has been detected (106 kbit/s only) shows if sdata and scoll are valid shows that the receiver has detected a stop condition

(ISO/IEC 14443A mode only) shows if the receiver is reset

Tab15-2 Testsignals description Pins D6 D5 Testsignal clkstable clk27/8 D4 RFU D3 RFU D2 clk27 D1 RFU Tab15-3 Testsignal routing (TestSel2Reg = 0Dh) Pins Testsignal Description D6 D5 D4 D3 D2 D1 clkstable clk27/8 RFU RFU clk27 RFU shows if the oscillator delivers a stable signal shows the output signal of the oscillator divided by 8

shows the output signal of the oscillator

Tab15-4 Testsignals description Pins D6 D5 D4 D3 Testsignal RFU Tab15-5 Testsignal routing (TestSel2Reg = 19h) TRunning RFU RFU D2 RFU D1 RFU Pins Testsignal Description D6 D5 D4 D3 D2 D1 RFU TRunning RFU RFU RFU RFU

TRunning stops 1 clock cycle after TimerIRQ is raised

Tab15-6 Testsignals description Datasheet FM17520 Contactless Transceiver IC Ver 1.0 61 15.2 Testsignals at pin AUX1/AUX2 SelTest Description for AUX1/AUX2 15 Testsignals 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Tristate DAC: register TestDAC 1/2 DAC: testsignal corr1 RFU DAC: testsignal MinLevel DAC: ADC_I DAC: ADC_Q RFU RFU RFU High Low TxActive RxActive Subcarrier detected TstBusBit Tab15-7 Testsignals description Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Remark: The DAC has a current output, it is recommended to use a 1 k ohm pull-down resistance at pins AUX1/AUX2. 15.3 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined data stream the Transmit command has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode. Remark: All relevant register to transmit data have to be configured before entering PRBS mode according ITU-TO150. Datasheet FM17520 Contactless Transceiver IC Ver 1.0 62 16 Typical Application Diagram 16 Typical Application Diagram The figure below shows a typical application diagram based on FM17520. Fig16-1 Typical application diagram Datasheet FM17520 Contactless Transceiver IC Ver 1.0 63 CONTROLLER NPD IRQ FM17520 TX1 C1 Rq C2 C2 Lant C1 Rq PVDD2 PVDD DVDD AVDD TVDD C3 RX VMID TVSS TX2 R2 C4 L0 L0 1 R C0 C0 DVSS PVSS AVSS OSCIN OSCOUT 27.12MHz 17 Characteristics 17 Characteristics 17.1 Limiting Values AVDD, DVDD, TVDD,PVDD,PVDD2 Parameter Storage temperature ESDHMB ESDCDM Min

-40

-0.5 Max

+85 4.0 2 500 Unit C V KV V

*Remark: Any conditions beyond the limiting values will bring permanent damage to the device. Tab17-1 FM17520 limiting values 17.2 Characteristics Symbol Parameter Conditions Min Typ Max Unit AVDD analog supply DVDD[1]

digital supply TVDD[2]

transmitter supply PVDD[3]

pin supply PVDD2[4]

test pin supply IDPD IHPD ISPD Deep power-down current Hard power-down current (register retention) Soft power-down current IAVDD operating current VPVDD VAVDD=VDVDD VTVDD VPVDD VAVDD=VDVDD VTVDD VPVDD VAVDD=VDVDD VTVDD VPVDD VAVDD=VDVDD VTVDD AVDD=DVDD=TVDD=PV DD=3V; NPD=0, get into DPD mode AVDD=DVDD=TVDD=PV DD=3V; NPD=0, get into HPD mode AVDD=DVDD=TVDD=PV DD=3V; get ino SPD mode AVDD=3V; enable receiver(RcvOff bit=0) AVDD=3V; disable receiver(RcvOff bit=1) transmitting carrier wave continuously; VTVDD =3.0V 2.2 3.0 3.6 2.2 3.0 3.6 2.2 3.0 3.6 1.62 1.62 3.6 3.6 V V V V V 1 2 35 10 6 10 uA 12 uA 60 uA 13 mA 8 mA

[5]

ITVDD RF operating current 60 100 mA TA ambient temperature

-40

+85 C Tab17-2 Recommended operating conditions for FM17520

[1] AVDD must be equal to DVDD .

[2] TVDD must be the same or higher voltage than AVDD.

[3] PVDDmust always be the same or lower voltage thanAVDD.

[4] PVDD2 should be the same voltage to PVDD as a proposal.

[5]

ITVDDdepends on TVDD voltage and the configured parameter of antenna network. The ITVDDcan be controlledsmaller than 100mA, or even larger to get a longer RF operating distance, by configuring different antenna network based on different application requirements.

[6]

IDPD/IHPD/ISPD are currents consumed by the whole chip in corresponding modes. 17.2.1 SPI AC Characteristics Symbol Parameter Conditions Min Typ Max Unit tWL pulse width LOW line SCK 50 ns Datasheet FM17520 Contactless Transceiver IC Ver 1.0 64 Symbol Parameter Conditions Min Typ Max Unit tWH pulse width HIGH line SCK thSCKH-D SCK HIGH to data input hold time tSUD-SCKH thSCKL-Q data input to SCK HIGH set-up time SCK LOW to data output hold time tSCKL-NSSH SCK LOW to NSS HIGH time SCK to changing MOSI changing MOSI to SCK SCK to changing MISO tNHNL NSS high before communication 50 25 25 0 50 Tab17-3 SPI AC characteristics 17 Characteristics 25 25 ns ns ns ns ns ns Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.To send more than one data stream, the NSS must be set HIGH between the data streams. Fig17-1 Timing diagram for SPI Datasheet FM17520 Contactless Transceiver IC Ver 1.0 65 18 Ordering Information Device Number Package FM17520-QNA-A-G QFN32 Wrap Tray Operating Environment Industrial Temperature

(-40 ~ +85) 18 Ordering Information Datasheet FM17520 Contactless Transceiver IC Ver 1.0 66 19 Package Information 19.1 QFN32 Package Outline 19 Package Information Fig19-1 FM17520 QFN32 Package Outline Datasheet FM17520 Contactless Transceiver IC Ver 1.0 67 Revision History Revision History Rev Release Date Pages 1.0 Oct.2016 69 Chapters/Ta bles/Figures Initial Release. Modifications Datasheet FM17520 Contactless Transceiver IC Ver 1.0 68 Sales and Service Sales and Service Shanghai Fudan Microelectronics Group Co., Ltd. Address: Bldg No. 4, 127 Guotai Rd, Shanghai City China. Postcode: 200433 Tel: (86-021) 6565 5050 Fax: (86-021) 6565 9115 Shanghai Fudan Microelectronics (HK) Co., Ltd. Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2116 3288 2116 3338 Fax: (852) 2116 0882 Beijing Office Address: Room 423, Bldg B, Gehua Building, 1 QingLong Hutong, Dongzhimen Alley north Street, Dongcheng District, Beijing City, China. Postcode: 100007 Tel: (86-010) 8418 6608 Fax: (86-010) 8418 6211 Shenzhen Office Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel, Huaqiang Rd (North), Shenzhen City, China. Postcode: 518028 Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611 Fax: (86-0755) 8335 9011 Shanghai Fudan Microelectronics (HK) Ltd Taiwan Representative Office Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist., Taipei City 114, Taiwan Tel : (886-2) 7721 1889 Fax: (886-2) 7722 3888 Shanghai Fudan Microelectronics (HK) Ltd Singapore Representative Office Address : 237, Alexandra Road, #07-01 The Alexcier, Singapore 159929 Tel : (65) 6472 3688 Fax: (65) 6472 3669 Shanghai Fudan Microelectronics Group Co., Ltd NA Office Address :2490 W. Ray Road Suite#2 Chandler, AZ 85224 USA Tel : (480) 857-6500 ext 18 Web Site: http://www.fmsh.com/

Datasheet FM17520 Contactless Transceiver IC Ver 1.0 69 FCC Statement This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and

(2) this device must accept any interference received, including interference that may cause undesired operation. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. The device has been evaluated to meet general RF exposure requirement. The device can be used in portable exposure condition without restriction. If the FCC identification number is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following:

Contains Transmitter Module FCC ID:2AWVZ-JL500N Or ContainsFCC ID: 2AWVZ-JL500N When the module is installed inside another device, the user manual of the host must contain below warning statements;

1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference.

(2) This device must accept any interference received, including interference that may cause undesired operation. 2. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. The devices must be installed and used in strict accordance with the manufacturer's instructions as described in the user documentation that comes with the product. Any company of the host device which install this modular with limit modular approval should perform the test of radiated emissionand spurious emission according to FCC part 15C : 15.247 and 15.209 requirement,Only if the test result comply with FCC part 15C : 15.247 and 15.209 requirementthen the host can be sold legally.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2020-07-20 Equipment Autorisation Division Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 FCC ID:__ 2AWVZ-JL500N___ Product Name:___ RFID module ___ Model name: FM17520 Request for Confidentiality Pursuant to Sections 0.457 and 0.459 of the commissions rules, we hereby request that the following documents be held confidential:

(List here the documents for which you are seeking confidentiality for example ) Schematics Block diagram Operation description These materials contain trade secrets and proprietary information and are not customarily released to the public. The public disclosure of this information might be harmful to the company and provide unjustified benefits to our competitors. Sincerely, Name: Ericliang Title: Manager Company: Guangzhou Jetinno Intelligent Equipment Co.,LTD.