3161A-SL Wi-Fi Single-band 1X1 802.11b/g/n SDIO Module Datasheet FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information 3161A-SL Module Datasheet Office: 6 Floor, Building U6, Junxiang U8 Park, Hangcheng Avenue, Bao'an District, Shenzhen City, CHINA Factory: No.8, Litong Road, Liuyang Economic & Technical Development Zone, Changsha, Hunan, CHINA TEL: +86-755-2955-8186 Website: www.fn-link.com Customer Approval :
Company Title Signature Date Fn-Link FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information 3161A-SL Revision History Version Date Revision Content Draft Approved 1.0 1.1 2020/04/22 New version 2020/05/30 Add 1line sdio application Lxy Lxy Szs Szs FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information CONTENTS 3161A-SL 1 Overview....................................................................................................................................1 1.1 Introduction......................................................................................................................... 1 1.2 Features.............................................................................................................................. 1 1.3 General Specification........................................................................................................ 2 1.4 Recommended Operating Rating....................................................................................2 2 Wi-Fi RF Specification........................................................................................................... 3 2.1 2.4GHz RF Specification.................................................................................................. 3 3 Pin Assignments..................................................................................................................... 3 3.1 Pin Outline...........................................................................................................................4 3.2 Pin Definition.......................................................................................................................5 4 Dimensions...............................................................................................................................7 4.1 Module Picture................................................................................................................... 7 4.2 Marking Description...........................................................................................................7 4.3 Module Physical Dimensions........................................................................................... 8 4.4 Layout Recommendation..................................................................................................8 5 Host Interface Timing Diagram......................................................................................... 10 5.1 SDIO Pin Description...................................................................................................... 10 5.2 SDIO CLK Timing Diagram............................................................................................ 10 6 Reference Design................................................................................................................. 19 6.1 Low Power Dissipation Reference Design.................................................................. 19 6.2 Normal Power dissipation Reference Design............................................................. 20 7 Ordering Information........................................................................................................... 21 8 The Key Material List........................................................................................................... 21 9 Power on Sequence............................................................................................................. 22 10 Design Attention................................................................................................................. 22 11 Recommended Reflow Profile.........................................................................................22 12 Packing Information...........................................................................................................23 12.1 Reel................................................................................................................................. 23 12.2 Carrier Tape Detail........................................................................................................ 24 12.3 Packaging Detail............................................................................................................24 12.4 Moisture sensitivity........................................................................................................ 25 FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information 3161A-SL 1 Overview 1.1 Introduction 3161A-SL is a highly integrated 2.4 GHz Wi-Fi module that support the IEEE 802.11b/g/n baseband and RF circuit. It supports 20 MHz standard bandwidth and 5 MHz/10 MHz narrow bandwidth, and provides a physical layer rate up to 72.2 Mbit/s. Wi-Fi baseband supports the orthogonal frequency division multiplexing (OFDM) technology and is backward compatible with the direct sequence spread spectrum (DSSS) and complementary code keying (CCK) technologies, offering various data rates defined in the IEEE 802.11 b/g/n protocol. Module chipset integrates a high-performance 32-bit microprocessor, a hardware security engine, and various peripheral interfaces, including the SPI, UART, I2C, PWM, GPIO, and multi-channel ADC. In addition, it provides high-speed SDIO2.0 slave interfaces, with clock frequency up to 50 MHz. Its built-in SRAM and flash can operate independently and even programming is allowed on the flash. Block Diagram:
1.2 Features Operate at ISM frequency bands (2.4GHz) FN-LINK TECHNOLOGY LIMITED 1 Proprietary & Confidential Information 3161A-SL Maximum rate of 72.2 Mbit/s@HT20 MCS7 SDIO interface for Wi-Fi Low power dissipation High transmitting power High receiving sensitivity PHY supporting IEEE 802.11b/g/n MAC supporting IEEE802.11 d/e/h/i/k/v/w Module integrated 32K clock WFA WPA, WFA WPA2 personal, and WPS2.0 for Wi-Fi Built-in 352 KB SRAM and 288 KB ROM Main chipset Built-in 32bit MCU and 2 MB flash memory 1.3 General Specification Model Name 3161A-SL Product Description Support Wi-Fi functionality Dimension Wi-Fi Interface L x W x H: 12 x 12 x2.3 (typical) mm Support SDIO Ambient temperature
-40C to 85C Storage temperature
-40C to 85C RoHS RoHS directive 1.4 Recommended Operating Rating All hardware components are fully compliant with EU Ambient temperature VCC VDDIO Min. Typ. Max. Unit
-40 2.3
25 3.3 1.8V/3.3V 85 3.6
deg.C V V VCC = 3.3V(Unit:mA) Power Consumption
(2.4G HT20@17dbm) Sleep Mode TX Test mode RX Test mode
(2.4G HT20) 5uA 288 53 Note: Suggested power input range in 3.3V. FN-LINK TECHNOLOGY LIMITED 2 Proprietary & Confidential Information 3161A-SL 2 Wi-Fi RF Specification 2.1 2.4GHz RF Specification Feature WLAN Standard Frequency Range Description IEEE 802.11 b/g/n Wi-Fi compliant 2.4002.4835GHz Number of Channels Wi-Fi:
US: channel 1~11;
EU: channel 1~13;
Japan: channel 1~14;
Spectrum Mask Min. b/g/n Typ. b/g/n Max. b/g/n Unit b/g/n 1st side lobes(to fc 11MHZ) 2st side lobes(to fc 22MHZ)
-43/-30/-40
-52/-33/-58
dBr dBr ppm Freq. Tolerance Test Items Output Power Test Items SISO Receive Sensitivity
(11g,20MHz) @10% PER SISO Receive Sensitivity
(11n,20MHz) @10% PER
-20/-20/-20
20/20/20 Typical Value 802.11b /11Mbps : 16dBm 1.5 dB EVM -10dB 802.11g /54Mbps : 16dBm 1.5 dB EVM -25dB 802.11n /MCS7 : 16dBm 1.5 dB EVM -28dB EVM Test Value 1Mbps 2Mbps Standard Value PER @ -97 dBm
-94 dBm PER @ -95 dBm
-92 dBm
- 11Mbps PER @ -90 dBm
-87 dBm 6Mbps 9Mbps PER @ -94 dBm
-89 dBm PER @ -92 dBm
-88 dBm
- 12Mbps PER @ -91 dBm
-87 dBm
- 18Mbps PER @ -88 dBm
-86 dBm
- 24Mbps PER @ -85 dBm
-84 dBm
- 36Mbps PER @ -82 dBm
-80 dBm
- 48Mbps PER @ -79 dBm
-77 dBm
- 54Mbps PER @ -77 dBm
-75 dBm
- MCS=0 PER @ -93 dBm
-89 dBm
- MCS=1 PER @ -90 dBm
-86 dBm
- MCS=2 PER @ -89 dBm
-84 dBm
- MCS=3 PER @ -85 dBm
-82 dBm
- MCS=4 PER @ -82 dBm
-79 dBm SISO Receive Sensitivity
(11b,20MHz) @8% PER
- 5.5Mbps PER @ -92 dBm
-89 dBm FN-LINK TECHNOLOGY LIMITED 3 Proprietary & Confidential Information 3161A-SL
- MCS=5 PER @ -78 dBm
-76 dBm
- MCS=6 PER @ -76 dBm
-74 dBm
- MCS=7 PER @ -73 dBm
-72 dBm Maximum Input Level 802.11b: -10 dBm 802.11g/n: -20 dBm Antenna Reference PCB antenna with 0~2 dBi peak gain 3 Pin Assignments 3.1 Pin Outline
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FN-LINK TECHNOLOGY LIMITED 4 Proprietary & Confidential Information 6 Host wake device Host Wake up Wi-Fi,GPIO06 GPIO or configured as SDIO interrupt pin.
(If not used keep Floating) Floating (Dont connected to ground) Main power voltage source input 2.3V-3.6V 3.3V 3.2 Pin Definition NO Type Name GND WL_ANT GND NC NC GPIO8 NC VCC NC NC 12 PMU_POWRON GPIO2 SDIO_DATA_2 SDIO_DATA_3 17 SDIO_DATA_CLK SDIO_DATA_0 SDIO_DATA_1 GND NC VDDIO NC RTC_CLK O RTC_CLK I NC NC NC NC NC GND NC 1 2 3 4 5 7 8 9 10 11 13 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I I/O P I I/O I/O I/O I I/O I/O P I/O I 3161A-SL Voltage VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO Description Ground connections RF I/O port Ground connections Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Enable pin for WLAN device Defualt ON: pull high ; OFF: pull low SDIO data interrupt,or GPIO function. SDIO data line 2, GPIO09 SDIO data line 3, GPIO10 SDIO clock line, GPIO12 SDIO data line 0, GPIO13 SDIO data line 1, GPIO14 Ground connections Floating (Dont connected to ground) I/O Voltage supply input 1.8V/3.3V VDDIO Floating (Dont connected to ground) Floating(module have 32K clock), GPIO00 Floating(module have 32K clock), GPIO01 VDDIO VDDIO Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Ground connections Floating (Dont connected to ground) 16 SDIO_DATA_CMD I/O SDIO command line, GPIO11 FN-LINK TECHNOLOGY LIMITED 5 Proprietary & Confidential Information 3161A-SL 37 UART_LOG_TX For firmware download, VDDIO GND NC NC GND NC NC NC NC
I O Ground connections Floating (Dont connected to ground) Floating (Dont connected to ground) Ground connections UART0_LOG_TX,GPIO03 can floating this pin UART0_LOG_RX,GPIO04 can floating this pin Wi-Fi reset pin. GPIO07 Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) Floating (Dont connected to ground) 38 UART_LOG_RX For firmware download, VDDIO 39 WL_RST Low: reset enable, Defualt High: reset disable 40 Dev_Wake_Host Wi-Fi wake up host. GPIO05 VDDIO VDDIO P:POWER I:INPUT O:OUTPUT 3.3 Muti Pin definition 3861L all GPIO pin can configure as muti function,detail see below information. Pin NAME F.0 F.1 F.2 F.3 F.4 F.5 F.6 F.7 F.8 GPIO00 GPIO00 UART1_TXD SPI1_CLK PWM3 I2C1_SDA RTC_OSC_32K RTC32K_XOUT GPIO01 GPIO01 UART1_RXD SPI1_RXD PWM4 I2C1_SCL RTC32K_XINT GPIO02 GPIO02 UART1_RTS SPI1_TXD PWM2 SSI_CLK
GPIO03 UART0_LOG_TX UART1_CTS SPI1_CS1 PWM5 I2C1_SDA SSI_DATA GPIO03 GPIO04 UART0_LOG_RX
PWM1 I2C1_SCL GPIO04 GPIO05 UART1_RXD GPIO05 I2S0_MCK PWM2 BT_STATUS SPI0_CS1 GPIO06 UART1_TXD GPIO06 I2S0_TX PWM3 COEX_SWITH SPI0_CLK
39 GPIO07 UART1_CTS GPIO07 I2S0_CLK PWM0 BT_ACTIVE SPI0_RXD ADC3 GPIO08 UART1_RTS GPIO08 I2S0_WS PWM1 WLAN_ACTIVE SPI0_TXD GPIO09 GPIO09 UART2_RTS SPI0_TXD PWM0 I2C0_SCL I2S0_MCK SDIO_D2 ADC4 GPIO10 GPIO10 UART2_CTS SPI0_CLK PWM1 I2C0_SDA I2S0_TX SDIO_D3 GPIO11 GPIO11 UART2_TXD SPI0_RXD PWM2 I2S0_RX SDIO_CMD ADC5 GPIO12 GPIO12 UART2_RXD SPI0_CS1 PWM3 I2S0_CLK SDIO_CLK ADC0 GPIO13 GPIO13 UART2_RTS UART0_LOG_TX PWM4 I2C0_SDA I2S0_WS SDIO_D0 ADC6 SSI_DATA ADC1 ADC2
33 34 35 36 41 42 43 44 24 25 13 37 38 40 6 7 14 15 16 17 18 FN-LINK TECHNOLOGY LIMITED 6 Proprietary & Confidential Information 19 GPIO14 GPIO14 UART2_CTS UART0_LOG_RX PWM5 I2C0_SCL
SDIO_D1
SSI_CLK 3161A-SL Notes 1. IO Ispu/O. 2. 1mA. 3. 3.3/1.8V. 4 Dimensions 4.1 Module Picture L x W : 12 x 12 (+0.3/-0.1) mm H: 2.3 (0.2) mm Weight 0.66g 4.2 Marking Description
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FN-LINK TECHNOLOGY LIMITED 7 Proprietary & Confidential Information 3161A-SL 4.3 Module Physical Dimensions
(Unit: mm)
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6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 6 5 2 1
, 5 7
, 4 5 5 2
, 4 5 8
, 3 5 3
, 3 5 9
, 2 5 4
, 2 5 0
, 2 5 5
, 1 5 1
, 1 5 6
, 0 5 2
, 0 4.4 Layout Recommendation
(Unit: mm) FN-LINK TECHNOLOGY LIMITED 8 Proprietary & Confidential Information
< TOP VIEW >
3161A-SL 6,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 5 2
, 6 6 5 2 1
, 5 7
, 4 5 5 2
, 4 5 8
, 3 5 3
, 3 5 9
, 2 5 4
, 2 5 0
, 2 5 5
, 1 5 1
, 1 5 6
, 0 5 2
, 0 FN-LINK TECHNOLOGY LIMITED 9 Proprietary & Confidential Information 3161A-SL The secure digital input/output (SDIO) interface supports three working modes:
The maximum frequency of the interface clock is 25 MHz. The interface clock can work 5 Host Interface Timing Diagram 5.1 SDIO Pin Description Default speed mode (DS) in 1-bit or 4-bit mode. High speed mode (HS) SDR25 mode The maximum frequency of the interface clock is 50 MHz. The maximum frequency of the interface clock is 50 MHz SDIO Pin Description SD 4-Bit Mode DATA0 Data Line 0 DATA1 Data Line 1 DATA2 Data Line 2 DATA3 Data Line 3 CLK CMD Clock Command Line 5.2 SDIO CLK Timing Diagram The DS mode is the default mode after the SDIO is powered on. To ensure compatibility with various host components, the DS mode requires a low working rate and supports only the 25 DS Mode MHz clock. FN-LINK TECHNOLOGY LIMITED 10 Proprietary & Confidential Information 3161A-SL Figure 8-6 shows the output data timing in DS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode. FN-LINK TECHNOLOGY LIMITED 11 Proprietary & Confidential Information 3161A-SL Figure 8-7 shows the input data timing in DS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock falling edge, and tODLY(min) is the minimum delay of the output data relative to the clock falling edge. Table 8-12 describes the timing restrictions in DS mode. FN-LINK TECHNOLOGY LIMITED 12 Proprietary & Confidential Information 3161A-SL Note: In DS mode, the output data is referenced to the clock falling edge, and the input data is referenced to the clock rising edge. HS Mode The HS mode is entered after the SDIO is powered on and initialized because a higher working rate than the DS mode is required. In HS mode, the clock supports 50 MHz. For details about the restrictions on the clock, see Table 8-13. FN-LINK TECHNOLOGY LIMITED 13 Proprietary & Confidential Information 3161A-SL Figure 8-8 shows the input data timing in HS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode Figure 8-9 shows the input data timing in HS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock rising edge, and tOH is the minimum delay of the output data relative to the clock rising edge. FN-LINK TECHNOLOGY LIMITED 14 Proprietary & Confidential Information 3161A-SL Table 8-15 describes the timing restrictions in HS mode. Table 8-16 Timing restrictions in HS mode (VDDIO = 1.8 V) FN-LINK TECHNOLOGY LIMITED 15 Proprietary & Confidential Information 3161A-SL Note: The data signal timing in HS mode is different from that in DS mode. The output data and input data are referenced to the clock rising edge. SDR25 Mode The SDR25 mode is entered only after the voltage of the SDIO is switched. In this mode, the maximum interface clock frequency is 50 MHz. Table 8-17 describes the clock restrictions. FN-LINK TECHNOLOGY LIMITED 16 Proprietary & Confidential Information 3161A-SL FN-LINK TECHNOLOGY LIMITED 17 Proprietary & Confidential Information 3161A-SL FN-LINK TECHNOLOGY LIMITED 18 Proprietary & Confidential Information 6 Reference Design 6.1 4line SDIO Reference Design 3161A-SL L1 10pF WL_ANT C1 NP C2 NP HOST WAKE DEV MUTI FUNCTION 3.3V C3 4.7uF 1 2 3 4 5 6 7 8 9 GND WL_ANT GND NC NC GPIO8 NC VBAT 10 11 NC NC HOST2DEV_WAKE 33 32 31 30 29 28 27 26 25 24 23 GND NC GND NC NC NC NC NC NC RTC_CLK RTC_CLK VDDIO R21 NC/47K R20 NC/47K R19 NC/47K R18 NC/47K SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK SDIO_D0 SDIO_D1 HOST WAKE DEV PWRON SD_INT C39 NC/10pf UART0_LOG_RX UART0_LOG_TX WL_RST DEV WAKE HOST MUTI FUNCTION HOST HOST WAKE DEV PWRON SD_INT SDIO_D2 SDIO_D3 SDIO_CMD SDIO_CLK SDIO_D0 SDIO_D1 UART0_LOG_TX UART0_LOG_RX WL_RST DEV WAKE HOST GPIO O I D D V O I D D V R11 NC/4.7K R10 NC/4.7K C10 NC/680pF C11 NC/680pF X R _ G O L _ 0 T R A U X T _ G O L _ 0 T R A U T S R _ L W T S O H E K A W V E D E K A W _ T S O H 2 V E D 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 C N C N C N C N C N C N D N G T S R _ L W X R _ T R A U X T _ T R A U t p u r r e t i n _ D S N E _ W O P 2 _ A T A D _ O I D S 3 _ A T A D _ O I D S D M C _ A T A D _ O I D S K L C _ A T A D _ O I D S 0 _ A T A D _ O I D S 1 _ A T A D _ O I D S D N G C N O I D D V 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 N O R W P I T N _ D S 22R 22R 22R 22R 22R 22R R1 R5 R6 R7 R8 R9 O I D D V VDDIO C8 4.7uF SDIO_D1 SDIO_D0 SDIO_CLK SDIO_CMD SDIO_D3 SDIO_D2 Notes:
1. 4line WLAN module application, all wake function may not supported;
2. Can using Power EN pin to shut down module for power saving;
FN-LINK TECHNOLOGY LIMITED 19 Proprietary & Confidential Information 6.2 1line SDIO Reference Design 3161A-SL 1. Hi3861L Hi18EV300 GPIO8 GPIO11 GPIO12 GPIO13 Hisyslink Hi3861L SDIO 1 3161A WIFI (PORPower On Reset)GPIO2/GPIO6/GPIO8 2. Flash GPIO2/GPIO6/GPIO8 PIR USB Hi3861L POR 3. WIFI UART GPIO3/GPIO4 TX GPIO_3 RX GPIO4 UART UART 900Kbps-2Mbps UART GPIO3/4 LED (
) FN-LINK TECHNOLOGY LIMITED 20 Proprietary & Confidential Information 4. WIFI GPIO3/GPIO5/GPIO7/GPIO14 WIFI 5. GPIO7 GPIO GPIO ADC 6. WIFI IO VDDIO VDDIO 3.3V WIFI IO 3.3V 3161A-SL or MCU or UART1 PIR PIR_OUT PIR_OUT PIR_IN PIR_IN L6 10pF WL_ANT C49 NP C50 NP ADC or GPIO GPIO SDIO INT 3.3V C48 4.7uF 1 2 3 4 5 6 7 8 9 GND WL_ANT GND NC NC GPIO8 NC VBAT 10 11 NC NC HOST2DEV_WAKE GPIO06 button reset or UART0 LED LED 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 C N C N C N C N C N C N D N G T U O _ R P I C D A X R _ G O L _ 0 T R A U X T _ G O L _ 0 T R A U E K A W _ T S O H 2 V E D T S R _ L W X R _ T R A U X T _ T R A U G P I O 0 7 G P I O 0 4 G P I O 0 3 G P I O 0 5 33 32 31 30 29 28 27 26 25 24 23 GND NC GND NC NC NC NC NC NC RTC_CLK RTC_CLK GPIO01 GPIO00 2 0 O I P G 9 0 O I P G 0 1 O I P G 1 1 O I P G 2 1 O I P G 3 1 O I P G 4 1 O I P G t p u r r e t i n _ D S N E _ W O P 2 _ A T A D _ O I D S 3 _ A T A D _ O I D S D M C _ A T A D _ O I D S K L C _ A T A D _ O I D S 0 _ A T A D _ O I D S 1 _ A T A D _ O I D S D N G C N O I D D V 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 N O R W P 2 0 O P G I 9 0 O P G I 0 1 O P G I O I D D V I G P O 1 4 22R 22R 22R R36 R37 R38 I2C ADC battery charge status charge SDIO_D0 SDIO_CLK SDIO_CMD USB VDDIO C51 4.7uF V D D I O R44 NC/47K PWRON SDIO_INT C54 NC/10pf HOST PWRON SD_INT SDIO_D0 SDIO_CLK SDIO_CMD 7 Ordering Information Part No. Description FG3161ASLX-00 FG3161ASLX-01 Hi3861L, b/g/n Wi-Fi, 1T1R, 12X12mm, SDIO, PCB V1.0 Halogen Free,with shielding. Halogen Free,no shielding. Hi3861L, b/g/n Wi-Fi, 1T1R, 12X12mm, SDIO, PCB V1.0 8 The Key Material List Main Inductor 2.2uH ,20%DCR=0.125ohmIsat=1.5AIrms=1.5A 2016 MPIE201610-2R2M-LF) Main Shielding 3161A-SL-V1.0 Shielding cover, no insulation glue, no FN-LINK TECHNOLOGY LIMITED 21 Proprietary & Confidential Information 3161A-SL cover positioning foot (material: copper) Xintai 2520 40MHZ,13.8PF,7ppm,SR:50 ,E2SB40E00000GE
(HOSONIC) 2520 Main Crystal Alt. Crystal Main RTC Main Chipset 9 Power on Sequence 40MHz 15pF 10ppm -40~85 Q40000V024 12.5PF 32.768KHZ 3215 SF32K32768D31T-12.5 () Hi3861LRNIV100 WiFi IoT Soc,802.11b/g/n, WiFi Mesh, 2M Flash, SDIO,UART,QFN32, 5x5mm () 20PPM -40~85 C VCC / VDDIO supreme electrical order requirements In the process of power up, GPIO02 internal weak pull low ,the 40MHz crystal is selected.. 10 Design Attention 1. GPIO02 is the interrupt signal of SDIO, It also can be configured as dev wake host function. 2. GPIO8 can be setting as SDIO interrupt function. 3. PMU_PWRON is enable pin of the module. Default is pull high. 4. Wake function may not supported with recently applications, for power saving please using POWER EN pin enable or disable the module. 11 Recommended Reflow Profile Referred to IPC/JEDEC standard. Peak Temperature : <250C FN-LINK TECHNOLOGY LIMITED 22 Proprietary & Confidential Information Number of Times : 2 times 3161A-SL 12 Packing Information 12.1 Reel A roll of 1500pcs FN-LINK TECHNOLOGY LIMITED 23 Proprietary & Confidential Information 3161A-SL 12.2 Carrier Tape Detail 12.3 Packaging Detail FN-LINK TECHNOLOGY LIMITED 24 Proprietary & Confidential Information 3161A-SL 12.4 Moisture sensitivity The Modules is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions:
a) Calculated shelf life in sealed bag: 12 months at <40C and <90% relative humidity
(RH). b) Environmental condition during the production: 30C / 60% RH according to IPC/JEDEC J-STD-033A paragraph 5. c) The maximum time between the opening of the sealed bag and the reflow process must be 168 hours if condition b) IPC/JEDEC J-STD-033A paragraph 5.2 is respected d) Baking is required if conditions b) or c) are not respected e) Baking is required if the humidity indicator inside the bag indicates 10% RH or more FN-LINK TECHNOLOGY LIMITED 25 Proprietary & Confidential Information