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Intelligent Distributed Controls Limited Compact 2.4GHz 802.15.4 / ZigBee Ready Modules for Wireless Networking Applications in ZigBee Ready OEM Modules ZB100 - *
Industry Product Datasheet MOD: ZB100-1-J-S 001B0A0000000002 FCC ID: V7OZB100 MOD: ZB100-0-A 001B0A0000000005 FCC ID: V7OZB100 ZB100 Datasheet V1.0 www.idc.gb.com Page 1 of 28 Document Revision Version 1.0 Date 11/07/08 Document History Version 1.0 Date 11/07/08 ZB100 OEM Modules Product Datasheet Checked Date Approved Date Client Date Author S.Barnett Description of Changes Draft ZB100 Datasheet V1.0 www.idc.gb.com Page 2 of 28 ZB100 OEM Modules Product Datasheet Contents Introduction ...................................................................................................................................... 4 Applications ..................................................................................................................................... 4 Key Features .................................................................................................................................... 4 Module Description.......................................................................................................................... 5 System-on-Chip (SoC) .............................................................................................................................. 5 Block Diagram ........................................................................................................................................... 5 CC2431 Location Engine ....................................................................................................................... 6 Voltage Regulators.................................................................................................................................... 6 MCU Core................................................................................................................................................... 6 Memory ...................................................................................................................................................... 6 FLASH ................................................................................................................................................... 6 SRAM .................................................................................................................................................... 6 ROM....................................................................................................................................................... 6 Off-board Memory ................................................................................................................................ 7 DMA Controller.......................................................................................................................................... 7 GPIO........................................................................................................................................................... 7 ADC ............................................................................................................................................................ 8 Temperature Sensor ............................................................................................................................ 8 Battery Monitor..................................................................................................................................... 8 Timers ........................................................................................................................................................ 8 Timer 1 (16-bit) ..................................................................................................................................... 8 Timer 2 (MAC)....................................................................................................................................... 9 Timers 3 and 4 (8-bit) ........................................................................................................................... 9 Watchdog Timer ................................................................................................................................... 9 Sleep Timer........................................................................................................................................... 9 USARTs...................................................................................................................................................... 9 UART ................................................................................................................................................... 10 SPI ....................................................................................................................................................... 10 Random Number Generator / CRC......................................................................................................... 10 AES Coprocessor.................................................................................................................................... 10 2-wire Debug Interface............................................................................................................................ 11 MAC Address ................................................................................................................................. 11 Radio Section ................................................................................................................................. 12 Block Diagram ......................................................................................................................................... 12 Receiver ................................................................................................................................................... 12 Transmitter .............................................................................................................................................. 13 Frequency Sythesiser ............................................................................................................................. 13 Specifications................................................................................................................................. 14 DC Characteristics .................................................................................................................................. 14 Memory .................................................................................................................................................... 16 RF Frequency, Output Power Levels and Data Rates .......................................................................... 16 Absolute Maximum Ratings.......................................................................................................... 17 Physical Dimension and Environmental Conditions.................................................................. 17 Module Coding ........................................................................................................................................ 18 Module Dimensional Detail..................................................................................................................... 19 PCB Mounting Information..................................................................................................................... 20 Pin Configuration .................................................................................................................................... 21 Agency Certifications .................................................................................................................... 24 EUROPEAN UNION (ETSI) ...................................................................................................................... 24 UNITED STATES (FCC) ........................................................................................................................... 24 Approved Antenna List ................................................................................................................. 25 Glossary.......................................................................................................................................... 26 Related Documents ....................................................................................................................... 28 Disclaimer....................................................................................................................................... 28 Contact Information....................................................................................................................... 28 ZB100 Datasheet V1.0 www.idc.gb.com Page 3 of 28 Product Datasheet ZB100 OEM Modules Introduction The ZB100 range of OEM Modules from Intelligent Distributed Controls Limited, have been designed around the CC2430/CC2431 System on Chip (SoC) single chip solutions fromTexas Instruments. The range of RF transceiver modules are available with various RP-SMA, SMA and chip antenna configurations, and are supplied in a pin header footprint common to all variants. All modules are capable of supporting the industry leading ZigBee protocol stack (Z-Stack) from Texas Instruments, for wireless point-to-point, star, tree and mesh networks based on the IEEE 802.15.4 compliant PHY and MAC layers, and providing 16 channels in the 2.45GHz licence-free ISM band. The shielded module is only 21.6 x 35 mm in board area, 3.5mm thick excluding the pin headers and SMA or RP-SMA RF connector. The module footprint also includes a MAC address chip (each device being unique). In addition to the nominal 3.3V chip level supply (2.0 to 3.6V) for battery applications, the modules also contain an isolated regulator allowing the device to be powered from industrial power supply voltages anywhere between 4 and 30V, making the device ideal for industrial sensor applications. Applications Home control and industrial automation Industrial monitoring vibration, temperature etc. o Machinery condition monitoring o Environmental temperature, humidity, pressure, vibration, flow monitoring OEM wireless devices Asset tracking and inventory management Key Features Building automation / management o Lighting o Temperature o Smoke/CO detectors Wireless barcode and tag reading Remote metering Security o Access control o Role calling Compact Design all shielded modules have the same 21.6 x 35 mm board area footprint, antenna ready 2.0 3.6V supply voltage extending to 30V when using the on board isolated regulator On board unique MAC address chip Optional CC2431 SoC which includes a location detection hardware module Industry leading CC2420 RF transceiver core, IEEE 802.15.4 compliant FCC CFR 47 Part 15 (US) and ETSI EN 300 440 (EU) Certified for Unlicensed Operation 128kB FLASH, 8kB SRAM (4kB with data retention in all power modes) Memory space for Full-Funtion Device (FFD) Certified for use with up to 9dBi dipole omnidirectional antenna (FCC restricted on channel 26 see FCC Restrictions) AES security coprocessor Hardware programming and debug Instruments the Texas support using development kit Digital RSSI and optional harware location engine (CC2431) Over-the-air (OTA) programming capability 32.768kHz crystal controlled RTC 32MHz high speed 8051 core MCU with wide range of configurable IO interfaces sensor o Powerfull DMA o Watchdog Timer o 802.15.4 MAC timer, 16 bit timer and two 8 bit timers, random number gen. o Battery monitor and temperature o 20 general purpose IO lines available on pin header with 20mA sink/source on two pins o 12-bit ADC with up to 8 inputs and o 2 configurable UART / SPI interfaces o With 8051 core running at 32MHz and radio enabled, RX = 27mA, TX =
27mA o 0.5 A in powerdown mode, where external interrupts or the RTC can wake up the system o 0.3 A in stand-by mode, where external o Very fast wake-up from low power modes interrupts can wake up the system configurable resolution to active mode Very low power ZB100 Datasheet V1.0 www.idc.gb.com Page 4 of 28 Product Datasheet ZB100 OEM Modules Module Description System-on-Chip (SoC) The CC2430 System-on-Chip is provided by Texas Instruments, and combines the market leading CC2420 RF transceiver (Chipcon / Ti), with an industry standard high-performance and peripheral enhanced 8051 micro-controller unit (MCU). With the memory arrangement provided on the ZB100, and the ability to support the industry leading ZigBee protocol stack (Z-Stack) from Texas Instruments, this module range forms the basis for design solutions from the bottom end-device, right through to the most complex full-function device requirements. Below provides a detailed view of the SoC complete with all peripherals, and additional components forming the ZB100. Block Diagram VDD = 2.0 3.6V
------------- See Pin Configuration Table ------------
Debug**
2 _ 2 P
1 _ 2 P n T E S E R 7 _ 0 P 1 _ 0 P 7 _ 1 P 1 _ 1 P Timer 1 (16-bit) Timer 3 (8-bit) Timer 4 (8-bit)
(0) USART Timer 2 MAC 802.15.4 8051 Hi-speed Enhanced core 128kByte FLASH FLASH Write 8kByte SRAM Memory Arbitrator IO Controller USART
(1) Sleep Mode Controller Debug Interface Temp Mon. Audio / DC 8 Channels ADC 12-bit resolution Batt Mon. Sleep Timer DMA 8051 Core MCU Encryption Decryption Demodulator AGC Modulator AES Radio data interface IRQ Controller Processor CSMA / CA Strobe CC2420 RF Transceiver FIFO and Frame Control Radio Registers Connect Pin 21 to Pin 22 when powering from 4.0 30V supply Vunreg = 4.0 30V g e r n u V V 3
. 3
g e r V V 3
. 3 Digital Supplies On-chip 1.8V Regulator Analogue and Radio Supplies Power-On Reset Brown-out Input 4 30V DC Isolated Regulator Output 3.3V DC MAC address serial chip Watchdog Timer Hi-Speed RC Osc 32 kHz RC Osc Random #
Gen. CRC 32 MHz Crystal Osc 32.768 kHz Crystal Osc Clock Mux &
Calibration 32.000 MHz 32.768 kHz CC2431 ONLY Location Engine Receive Chain Frequency Synthesiser ~
Transmit Chain Chip Antenna SMA Jack or or RP-SMA Jack RF_P Balun RF_N RF Ground Plane CC2430 / 31 SoC C D V 0
**Debug Interface is shared with GPIO Port pins 2_1 and 2_2 C D V 0 Digital Analogue Mixed C D V 0 ZB100 Datasheet V1.0 www.idc.gb.com Page 5 of 28 ZB100 OEM Modules Product Datasheet CC2431 Location Engine The CC2431 System-on-Chip is identical to the CC2430 in respect of MCU, memory, peripherals and radio operation, with the addition of a hardware location detection module microcode in silicon. This can be used in applications requiring location management e.g. asset tracking. Mobile devices (blind nodes unknown position) receive signals from nodes with known locations. Based on the varying signal strengths from received from these fixed nodes, the location engine calculates an estimate of its own position. Accuracy of 3 to 5 metres in typical applications can be achieved. Coverage is approximately 64 x 64 metres, with a location estimate resolution of 0.5m. The time to perform the calculation takes less than 40s, and requires minimal CPU loading, as the calculations are performed in microcode. Once the result has been calculated, this can then be reported as an X/Y coordinate back through the network to say a PC for visual representation. Voltage Regulators The ZB100 module can be powered from two sources, both referenced to the modules 0V ground connections. 1) Battery / 3.3V DC source (VDD). This is the SoC digital chip supply and can be anywhere between 2.0 and 3.6V, and is primarily intended for battery powered applications. This provides power to all digital elements of the SoC, and also the Serial / MAC integrated circuit. 2) Higher voltage DC source (Vunreg). This connects to an isolated linear 3.3V regulator, which accepts DC input in the range of 4.0 to 30V, making it ideally suited to industrial applications. The output of the isolated regulator is then linked (on the OEM board) into the Battery / 3.3V DC source, providing the required 3.3V for the SoC. In addition, there is a 1.8V analogue regulator internal to the SoC powered from the, which provides power to the analogue sections and RF radio sections of the device. This is self-contained, and the 1.8V regulated output is not made available for any external devices. MCU Core The CC2430/31 SoC contains an enhanced 8051 micro-controller with the core CPU running at 32MHz. This operates the standard 8051 instruction set on 1 cycle per instruction as opposed to the standard 12 cycles per instruction. Memory The onboard memory of the ZB100 consists of the following:
FLASH 128kByte of FLASH memory divided into 64 pages of 2kbyte each. This is the smallest erasable unit in memory, whilst the smallest writable element is 32 bytes. The worst case FLASH memory endurance is 1000 erase/write cycles. Programming can be performed from within resident firmware, or over the 2-wire debug interface. Over-the-air programming is possible and available on the ZB100. FLASH sectors can be locked for security and auto powers down during low frequency CPU read access. SRAM A total of 8192 bytes of data memory is provided on chip, divided into two 4096 byte sectors, with the upper sector having data retention in all power modes, and the lower sector with retention in active and power mode 1 only. ROM The ROM is a 64bit 1-wire serial device that communicates over a single IO pin of the SoC. This provides a unique identity for the ZB100 module, with the option for this to be a complete UID-64 bit MAC address, which contains the IEEE assigned 24-bit company identifier (Intelligent Distributed Controls address. 001B0AH), 40-bit node and Ltd.
a ZB100 Datasheet V1.0 www.idc.gb.com Page 6 of 28 ZB100 OEM Modules Product Datasheet Off-board Memory Additional memory may be connected to the ZB100 via a serial port configured in SPI mode. Up to 2Mbyte of extra FLASH may be added in this way. DMA Controller A powerful DMA controller is provided which can be used to relieve the processor from data movement thereby improving the overall processing efficiency. The DMA controller can move data from/to a peripheral unit to/from memory with minimal CPU intervention. The DMA controller controls data exchange over the entire range of the XDATA memory space, and since most of the SFRs are mapped into the XDATA memory space, data transfers to/from peripherals can be manipulated. Use of the DMA can also reduce power consumption by keeping the CPU in a low power mode, whilst moving data to or from a peripheral unit. The main features of the DMA controller are given below:
Five independent DMA channels Three configurable levels of DMA channel priority 31 configurable transfer trigger events Single block and repeated transfer modes Supports length field in transfer data setting variable transfer length Can operate in word or byte size modes Independent control of source and destination address GPIO The CC2430/31 provides three 8-bit ports of general purpose IO Ports 0, 1 and 2. Ports 0 and 1 are complete 8-bit wide ports (P0_0 . P0_7; P1_0 . P1_7), and are available on the ZB100 header. Port 2 has only 5 usable elements, two of which are taken by the 32.768 kHz crystal for RTC applications, and P2_0 is directly interfaced to the serial number integrated circuit (MAC address). This leaves P2_1 and P2_2 brought out to the ZB100 header as two further general purpose IO pins. P2_1 and P2_2 are also used for the debug interface see later. All ports are both bit and byte addressable, and each port pin can be configured to operate as either a general purpose IO or as a peripheral IO. Each port pin has the following configurable features:
Output drive current of 4mA (Sink/Source), with the exception of P1_0 and P1_1 which are high current drives providing 20mA capability Configurable 20k pull-up or pull-down or tri-state when configured as an input with the exception of P1_0 and P1_1 Retention of IO mode and output value when in lowest power modes GPIOs configured as inputs can be used to generate inputs GPIOs (Port0 and Port1) configured as inputs can each be associated with one DMA trigger for immediate transfer to a mapped XDATA location on input transition changes Four radio test signals can be output on port pins P1_4 to P1_7 Peripheral units have two alternative port locations to maximise port utilisation and minimise pin selection conflicts Unused IO pins should either be configured as outputs or as inputs with the pull-up resistor configured. In both cases unused pins should not be connected to VDD or 0V to avoid excessive current consumption. ZB100 Datasheet V1.0 www.idc.gb.com Page 7 of 28 ZB100 OEM Modules Product Datasheet ADC The ADC supports uo to 12-bit analogue to digital conversion via a multiplexer which accepts up to eight single-ended channels through the GPIO interface. Two further internal channels are provided on chip temperature sensor, and a battery monitor input which is essentially the VDD supply divided by 3, for an early warning detection of battery failure. In addition a positive reference voltage multiplexer / selector can be programmed to choose between an on-chip reference voltage, the analogue voltage supply, a single ended external reference via AIN7, or a differential external reference via AIN6-ANI7. The ADC features are as follows:
Selectable decimation rates (7, 9, 10 and 12 bits) Eight individual single-ended input channels, which may be paired for differential signals Reference voltage, selectable between internal, single-ended external, differential external or AVDD_SOC (VDD) Interrupt request generation DMA triggers at end of conversions Temperature Sensor input Battery Monitor Input Temperature Sensor The temperature sensor provides a further additional channel to the ADC. This provides a voltage measurement relative to temperature over the temperature range of -40 to +80C. This provides an on-chip temperature reading accuracy of 2 C over the temperature range of -20 to +80C once a calibration has been performed at room temperature. The actual voltage reading for a given temperature is based on the temperature coefficient of 2.45mV/C calculated from the room calibration point. Battery Monitor The battery monitor AVDD_SOC/3 provides a further additional channel to the ADC. This provides a linear relationship to the SoC supply (VDD), thereby providing the ability (using a threshold value) to detect early warning of low-supply/battery status. Timers A total of six timers are provided by the SoC with varying configurable atributes as follows:
Timer 1 (16-bit) Timer 1 may be used for a wide variety of control and measurement applications (input capture, output compare and PWM) with the ability to perform motor control functionality. The main features of Timer 1 are as follows:
Three capture/compare channels Rising, falling or any edge capture Set, clear or toggle output compare Free-running, modulo or up/down counter operation Clock pre-scaler for divide by 1, 8, 32 or 128 DMA trigger function Interrupt request generated on each capture/compare and terminal count ZB100 Datasheet V1.0 www.idc.gb.com Page 8 of 28 ZB100 OEM Modules Product Datasheet Timer 2 (MAC) The MAC timer is mainly used for general time keeping in the 802.15.4 MAC layer, providing timing for the CSMA-CA algorithms. The main features of the MAC timer are as follows:
16-bit up-counter providing symbol/frame periods of 16s/320s Adjustable period with accuracy of 31.25ns 8-bit timer compare function 20-bit overflow count 20-bit overflow count compare function Start of Frame Delimiter capture function Timer start/stop synchronous with 32.768 kHz clock and time keeping maintained by Sleep Timer DMA trigger capability Interrupts generated on compare and overflow Timers 3 and 4 (8-bit) Timers 3 and 4 support typical requirements such as output compare and PWM functions, or basic software timing requirements. The main features of Timer 1 are as follows:
Two compare channels Free-running, modulo or up/down counter operation Clock pre-scaler for divide by 1, 2, 4, 8, 16, 32, 64 or 128 DMA trigger capability Interrupts generated on compare and terminal count Watchdog Timer The watchdog timer consists of a 15-bit counter clocked by the 32.768 kHz crystal oscillator. This provides a means of resetting the processor if it fails to reset the watchdog within the selected period through software. This may happen where the application is subject to an electrically noisy environment, power glitches etc. or where high reliabilty of the software is required. The watchdog timer provides the following features:
Four selectable time intervals 1.9 ms, 15.625 ms, 0.25 s, 1 s. Watchdog Mode (Generates CPU reset if timed out) Timer Mode (Generates Interrupt only if timed out) Independent from system clock Sleep Timer The sleep timer is used to set the interval from entering the low power sleep state and returning to active mode. 24-bit up counter driven from the 32.768 kHz oscillator. 24-bit compare for waking through interrupt Low power mode operation in PM2 Maximum period = 512 seconds (approx.8.5minutes) USARTs Two serial communication USARTs are provided on the SoC USART(0) and USART(1). These can be operated and configured separately into either UART (asynchronous) or SPI (synchronoue) modes. Both USARTs have identical functionality, but are configured on separate port pins. A second alternative configuration is also possible providing more efficient use of the port pins for peripheral use. ZB100 Datasheet V1.0 www.idc.gb.com Page 9 of 28 ZB100 OEM Modules Product Datasheet UART UART mode provides an asynchronous serial communications interface consisting of two or four wire (TxD, RxD and optionally CTS and RTS). In addition standard GPIO pins can be configured to provide further modem functions e.g. DSR, DTR and CD, as these can be interrupt configured. Each UART provides the following features:
8 or 9 data bits Odd, even or no parity Configurable Start and Stop bit level Configurable LSB or MSB first transfer Parity and framing error status Up to 230,400 bps data speed, configurable via an internal baud rate generator derived from the Independent receive and transmit interrupts Independent receive and transmit DMA triggers system clock SPI SPI mode provides a synchronous serial communication interface through either a 3-wire or 4-wire interface. The full 4-wire interface consists of the following pin functions:
MOSI Master Out Slave In MISO Master In Slave Out SCK Serial Clock SSN Slave Select The SPI mode provides the following features:
Selectable 3-wire or 4-wire interface Master or Slave presentation Configurable SCK polarity and phase, SCK speed is configured via an internal baud rate generator derived from the system clock Configurable LSB or MSB first transfer When selected for Slave presentation (4-wire mode), the SSN pin is used as an edge triggered chip-
select input. Random Number Generator / CRC The Random Number Generator is a 16-bit linear feedback shift register (Polynomial X16 +X15 + X2 + 1) and provides the following features:
Generates psuedo-random bytes for either use by the firmware, or by the Command Strobe Processor CSMA / CA Calculate CRC16 of bytes written to the upper Random Number Generator register Seeded by value written to the lower Random Number Generator register twice Usually for standard CRC16 calculations, the seed vakue is either 0x0000 or 0xFFFF. AES Coprocessor The data encryption is performed by a dedicated co-processor contained in the SoC silicon which supports the Advanced Encryption standard, AES. This allows encryption/decryption to be performed with minimal CPU intervention. This coprocessor provides the following features:
Supports all security suites in the IEEE 802.15.4 standard ECB, CBC, CFB, OFB, CTR and CBC-MAC modes with hardware support for CCM mode 128-bits key and IV/Nonce, and DMA transfer trigger capability ZB100 Datasheet V1.0 www.idc.gb.com Page 10 of 28 ZB100 OEM Modules The AES coprocessor can add security to wired links (UART / SPI) but primarily is intended for the wireless link. AES encryption is performed on blocks of data (128-bit wide), prior to transmitting a packet payload over the radio, and AES decryption after receiving a payload packet. Ref [4] for further detail on AES operation. Product Datasheet 2-wire Debug Interface The Debug Interface operates a proprietry 2-wire serial interface used for in-circuit debugging. Through this interface it is possible to erase and write (program) the FLASH memory, and debug by controlled program execution (stop/start, single stepping, breakpoints etc.). The 2-wire debug interface shares with two GPIO port pins, and the debug mode is entered by a specific operation of the debug clock in conjunction with the precessor RESETn pin. When not in debug mode, the port pins revert back to standard general purpose IO pins. The following details are for providing a programming interface for use with the Texas Instruments CC2430 Development Kit CC2430DK. This uses a 10-way ribbon interface for programming and debugging the SoC. In addition, this example interface can also provide a single SPI port. Alternatively Radio Test signals can be configured to be outputs on the Port Pins P1_4 to P1_7 as given below. Footprint of IDC00008S Module ZB100 Module
+3.3V 0V
+3.3V RESETn RESETn 2 4 6 8 10 2 4 6 8 10 2 4 6 8 10 P2_1 P1_5 P1_6 P1_7 MOSI Debug DD Debug DC CSn P2_2 P1_4 RESETn 2 4 6 8 10 12 14 16 18 20 22 INTERFACE HD2 1 3 5 7 9 HD3 1 3 5 7 9 SOC 1 3 5 7 9 SCLK MISO Debug DC Debug DD SCLK MOSI MISO M1 1 3 5 7 9 11 13 15 17 19 21 P0_6 P0_4 P0_2 P0_0 P1_1 P1_3 P1_5 P1_7 P2_2 Vunreg Vreg P0_7 P0_5 P0_3 P0_1 RESETn P1_0 P1_2 P1_4 P1_6 P2_1 3V3 SoC PROGRAMMING DEBUG / FLASH MAC Address The MAC address can be either hard-coded into FLASH, or take the address from the on-board 1-wire serial device connected to the CC2430/31 Port P2_0. This device can be either a generic 24-bit serial number, or a user specific EUI-64 global identifier whereby the first 24-bits provide the OUI, and the remaining 40-bits provide the serialisation. The IEEE assigned OUI for Intelligent Distributed Controls Limited is 00-1B-0A. OEMs may hardcode their own UID and serialisation or take the Intelligent Distributed Controls OUI as appropriate See Reference [6] for implimenting the 1-wire interface in software. P1_4 FIFO (One or more bytes in receive FIFO) P1_5 FIFOP (Unread receive FIFO bytes overflow) P1_6 SFD (Start of Frame Delimiter) P1_7 CCA (Clear Channel Assessment) Radio Test Signals Box Header 2x5 0V 0V 0V 0V ZB100 Datasheet V1.0 www.idc.gb.com Page 11 of 28 Product Datasheet ZB100 OEM Modules Radio Section The radio core is based on the industry standard Chipcon/TI CC2420 transceiver. The IEEE 802.15.4 compliant radio is shown below in a simplified block diagram. Operation of the radio is configured through a set of RF registers and controlled through a set of command strobes (single byte instructions) which control the functionality of the radio. E.g. enable frequency synthesiser, enable receive mode, enable transmit mode etc. The RF registers also provide status information from the radio. All command strobes from the CPU to the radio pass through the CSMA/CA Strobe Processor Refer to [1] for more detailed description of the radio operation. LNA Block Diagram TX/RX SWITCH PA Power Control AUTOMATIC GAIN CONTROL ADC ADC 0
90 FREQUENCY SYNTHESISER TX POWER CONTROL DAC DAC DIGITAL DEMODULATOR
-Digital RSSI
-Gain Control
-Image Suppression
-Channel Filtering
-Demodulation
-Frame synchronisation L O R T N O C I C G O L E C A F R E T N A T A D O D A R I I DIGITAL MODULATOR
-Data spreading
-Modulation RADIO REGISTER BANK Register Bus CSMA/CA STROBE PROCESSOR SFR bus FFCTRL IRQ HANDLING CC2420 Transceiver Receiver The CC2430/31 SoC contains a low-IF receiver. The received RF signal is amplifier by a low-noise amplifer
(LNA) and down-converted in quadrature to the 2MHz intermediate frequency. The complex I/Q signal is then bandpass filtered and amplified with a variable gain amplifier. The gain of the amplifier is digitally controlled, and the AGC feedback loop ensures that the ADC operates inside its dynamic range. The signal is digitised by the ADCs. The AGC, final channel filtering, demodulation, de-spreading, symbol-correlation and byte synchronisation are performed digitally. IRQ handling presents an interrupt when a start of frame delimiter has been detected. A 128 byte receive FIFO is provided to buffer the received data. The firmware may read the receive FIFO through the SFR interface, ideally by DMA transfer into CPU memory. The receive FIFO is provided with overflow detection, informing the CPU via interrupt. The CRC is verified in hardware, and the RSSI and correlation values are appended to the received frame. The clear channel assessment, CCA, is available through an interrupt in receive mode. AES decryption (if adopted) radio. the CPU and AES coprocessor then handled by independent from the is ZB100 Datasheet V1.0 www.idc.gb.com Page 12 of 28 ZB100 OEM Modules Product Datasheet Transmitter The CC2430/31 SoC transmitter is based on direct up-conversion. AES encryption (if adopted) is applied prior to transferring the data to the 128 byte transmit FIFO buffer. Preamble and start of frame delimiters are generated in hardware. The IEEE 802.15.4 direct sequence spread spectrum modulation format is then applied by taking each byte and slitting it into two symbols (4-bits each). The least significant symbol is transmitted first and for multi-byte fields, the least significant byte is transmitted first. Each symbol is mapped to one-of-sixteen pseudo-random sequences of 32 chips each. The chip sequence is then transmitted at 2MChip/s with the least significant chip first for each symbol. The modulation format is Offset Quadrature Phase Shift Keying (O-QPSK), with half-sine chip shaping. This is equivalent to Minimum Shift Keying (MSK), whereby each chip is transmitted as a half sine alternatively between the I and Q channels with one half period offset. The result for the I and Q channels are then output to the DACs, and then via low pass filtering to the up-conversion mixers. The resulting RF signal is then amplified in the programmable power amplifier (PA), and fed to the antenna via the differential connection. Output power is programmed through the TXCTRLL Register. The maximum power attainable is 0.6dBm. Internal TX/RX switching simplifies the antenna interface matching. The biasing of the PA and LNA is done by connecting the TX/RX switch to the two differential RF connections through a DC path. The signal then pass through a discrete microstrip balun to either the board mounted chip antenna, or SMA / RP-SMA RF connector. Frequency Sythesiser Frequency synthesis is provided by a completely integrated VCO and 90 phase splitter for the I and Q local oscillator (LO) signals to the up/down conversion mixers. The VCO operates in the frequency range 4800 4967 MHz, divided by two for the I and Q signals (2400 2483.5MHz). The VCO charateristics will change with temperature and/or voltage supply and the desired operating frequency. To compensate for this the PLL self-calibrates (bias current and tuning range) every time the RX mode or TX mode are enabled. The on-chip voltage regulator delivers the regulated 1.8 V supply voltage for the radio circuitry. ZB100 Datasheet V1.0 www.idc.gb.com Page 13 of 28 Specifications DC Characteristics Parameter Supply Inputs Operating Supply Voltage VDD External Supply Vunreg Isolated Regulator Output Voltage Isolated Regulator Output Current ZB100 OEM Modules Product Datasheet Min Typ Max Unit Condition/Note 2.0 3.3 3.6 4.0
30.0 V V SoC power supply (Header Pin 22) referenced to signal/RF ground plane (0V). Header Pin 19 Isolated Regulator output 3.3V -
Pin 21 requires linking to Pin 22 to power SoC. Isolated section therefore draws no leakage current when operating module from Pin 22 only
(E.g. battery). Minimum input voltage to guarantee 3.3V output. 3.234 3.3 3.366 V Header Pin 21 referenced to 0V. 50 100**
mA Nominally 50mA continuous (4-30V input),
** 100mA peak for short periods, dependent on input voltage. Regulator has current and thermal limiting. 75 380 450 Isolated Regulator Drop-out voltage Isolated Regulator quiescent current SoC Current Consumption CC2430 & CC2431 MCU Active Mode, 32 MHz, low MCU activity MCU Active Mode, 32 MHz, medium MCU activity MCU Active Mode, 32 MHz, high MCU activity 10.5 12.3 9.5 MCU Active and RX Mode MCU Active and TX Mode, 0dBm Power mode 1 (PM1) Power mode 2 (PM2) Power mode 3 (PM3) 26.7 26.9 190 0.5 0.3 mV Full load 100mA output. A Up to 8mA typical on full 100mA load. mA mA mA mA mA A A 32 MHz XOSC running. No radio or peripherals active. Low MCU activity : no flash access (i.e. only cache hit), no RAM access. 32 MHz XOSC running. No radio or peripherals active. Medium MCU activity: normal flash access1, minor RAM access. 32 MHz XOSC running. No radio or peripherals active. High MCU activity: normal flash access1, extensive RAM access and heavy CPU load. MCU running at full speed (32MHz), 32MHz XOSC running, radio in RX mode, -50 dBm input power. No peripherals active. Low MCU activity. MCU running at full speed (32MHz), 32MHz XOSC running, radio in TX mode, 0dBm output power. No peripherals active. Low MCU activity. Digital regulator on, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. A No clocks. RAM retention. POR active. ZB100 Datasheet V1.0 www.idc.gb.com Page 14 of 28 ZB100 OEM Modules Product Datasheet Parameter MAC address Chip Current Consumption (Active for initial read only on power up / reset) Unit Condition/Note Max Typ Min Active Power Standby Power IO Parameters General purpose Input programmable pull-up /
pull-down General purpose output drive current sink /
source ADC Resolution 7 5 0 20 4 A A k mA Powered via data pin of SoC, power, control address and data all via a single pin. No serial chip communication. P1_0 (Header Pin 12) and P1_1 (Header Pin 9) do not have this feature. All are configurable for external interrupt. P1_0 (Header Pin 12) and P1_1 (Header Pin 9) have 20mA drive capability. 12 bit Programmable conversion resolution /
decimation rate. Analogue Input Resistance Internal reference Input Voltage including External reference AIN6/AIN7 Conversion Time ADC Current Consumption Temperature Sensor Temp. Coeffidient Temp. Sensor Accuracy Temp. Sensor Current Consumtion Battery Monitor UART Mode maximum Baud Rate SPI Maximum Clock Rate Timer Input Capture Watchdog Timer 197 1.25 VDD 20 36 68 132 1.2 2.45 2 k Simulated usung converstion 4MHz clock speed. V V s s s s External reference can be selected on AIN7 /
P0_7 (Header Pin 2) or AIN6-AIN7 for differential input conversation. 7-bit setting (64 decimation rate). 9-bit setting (128 decimation rate). 10-bit setting (256 decimation rate. 12-bit setting (512 decimation rate). mA mV/C Fitted from -20 C to +80 C. C Over range -20 C to +80 C when using 2.45mV/C after 1-point calibration at room temperature. A When enabled. V Additional analogue input channel which measures the Analogue VDD divided by 3 for use as a battery monitor. 230,400 bps For system clock set to 32MHz. 4 MHz For system clock set to 32MHz. ns ms ms s s With Sysclk = 32MHz. Clock source 32.768kHz (count = 64) Clock source 32.768kHz (count = 512) Clock source 32.768kHz (count = 8192) Clock source 32.768kHz (count = 32768)
-2 0 31.25 280 VDD/3 1.9 15.625 0.25 1 ZB100 Datasheet V1.0 www.idc.gb.com Page 15 of 28 Memory ZB100 OEM Modules Product Datasheet Parameter FLASH Memory Page erase time Chip mass erase time Write time Data Retention Program erase/write SRAM SRAM MAC / Serial Chip Min 1000 Typ 128 20 200 20 100 4096 4096 64 Max Unit Condition/Note kbyte ms 64 pages of 2kbyte each ms s Per 4 bytes At room temperature endurance years cycles bytes Data retention in all power modes bytes bit Data retention in power modes 0 (active) and 1. ROM accessed through 1-wire interface RF Frequency, Output Power Levels and Data Rates Parameter RF Frequency Range Min 2400 Typ Max Unit 2483.5 MHz No. of channels Channel Spacing Radio bit rate Radio Chip Rate Receiver Sensitivity Nominal Output power Programmable output power range Antenna nominal RX /
TX impedance 16 5 250 2.0
-92 0 26 50 Mhz kbps MChip/s dBm dBm dBm Condition/Note Programmable in 1 MHz steps, 5 MHz between channels for compliance with [1].
** See RF channel table.
PER = 1%, as specified by [1]. Delivered to a single ended 50 load through a balun and output power control set to 0x5F
(TXCTRLL register). The output power is programmable in 16 steps from typically -25.2 to +0.6 dBm. The RF channels and associated frequencies defined by the IEEE 802.15.4 standard are as follows:
RF Channel 11 12 13 14 15 16 Frequency 2405 MHz 2410 MHz 2415 MHz 2420 MHz 2425 MHz 2430 MHz RF Channel 17 18 19 20 21 22 Frequency 2435 MHz 2440 MHz 2445 MHz 2450 MHz 2455 MHz 2460 MHz RF Channel 23 24 25 26 Frequency 2465 MHz 2470 MHz 2475 MHz 2480 MHz
[1]
IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs). ZB100 Datasheet V1.0 www.idc.gb.com Page 16 of 28 ZB100 OEM Modules Absolute Maximum Ratings Product Datasheet Parameter Supply Voltage VDD Supply Voltage Vunreg Voltage on any digital IO pin Min
-0.3
-0.3 Typ Max 3.9 VDD+0.3 max 3.9 Unit Condition/Note V V Header Pin 22 referenced to 0V. Header Pin 19 referenced to 0V. V
-50 Input RF Level Storage temp Caution!! ZB100 Modules are ESD sensitive devices. Precautions should be taken when handling the device in order to prevent permanent damage. Device not programmed. 10
+150 dBm C Physical Dimension and Environmental Conditions All modules are RoHS Compliant in construction. Parameter Value Notes / Module Codes Size board profile 21.6 x 35 mm Module height Total height above OEM daughter board
(See Dimensional drawings) Weight (approx.) 3.5 mm 4.8 mm 12.3 mm 16.3 mm 12.3 mm 12.3 mm 6 g 8 g 10 g 8 g 10 g Operating Temperature
-20C to +70C Excludes over-hang of SMA or RP-SMA RF connectors. See dimensional drawings for RF connector positions and board overhang etc. Board and RF shield combined - excluding pin headers. ZB100-0-A; ZB100-1-A ZB100-0-B; ZB100-0-D; ZB100-1-B; ZB100-1-D ZB100-0-C; ZB100-0-E; ZB100-1-C; ZB100-1-E ZB100-0-F-z; ZB100-0-H-z; ZB100-1-F-z; ZB100-1-H-z ZB100-0-G-z; ZB100-0-J-z; ZB100-1-G-z; ZB100-1-J-z ZB100-0-A; ZB100-1-A ZB100-0-B; ZB100-0-D; ZB100-1-B; ZB100-1-D ZB100-0-C; ZB100-0-E; ZB100-1-C; ZB100-1-E ZB100-0-F-z; ZB100-0-H-z; ZB100-1-F-z; ZB100-1-H-z ZB100-0-G-z; ZB100-0-J-z; ZB100-1-G-z; ZB100-1-J-z
-40C to +85C Storage and Operational with minor degradation of clock stability / accuracy. Operating Relative Humidity 80% RH For in-depth specifications please refer to the Related Documents - [1]. ZB100 Datasheet V1.0 www.idc.gb.com Page 17 of 28 Module Coding ZB100 OEM Modules Product Datasheet ZB100-x-y-z
(x) = System-on-Chip 0 = CC2430 1 = CC2431 (c/w location engine) Examples ZB100-0-A CC2430 with Chip Antenna ZB100-1-B CC2431 with vertical SMA Jack ZB100-0-J-R CC2430 with R/A RP-SMA bulkhead mounted in the rotated position
(y) = Antenna Style A = Chip Antenna B = Vertical SMA Jack C = Vertical SMA Bulkhead Jack D = Vertical RP-SMA Jack E = Vertical RP-SMA Bulkhead Jack F = R/A SMA Jack G = R/A SMA Bulkhead Jack H = R/A RP-SMA Jack J = R/A RP-SMA Bulkhead Jack R/A = Right-angled RP-SMA = Reverse Polarity SMA
(z) = R/A RF Connector Orientation S = Straight R = Rotated ZB100 Datasheet V1.0 www.idc.gb.com Page 18 of 28 ZB100 OEM Modules Product Datasheet
. 1.3mm 3.5mm m m 6 1 2 35.0mm Daughter board top surface Antenova Rufa Chip Antenna Module Dimensional Detail Chip Antenna Versions ZB100-0-A, ZB100-1-A R/A SMA and RP-SMA Versions ZB100-0-F-z; ZB100-0-H-z;
ZB100-1-F-z; ZB100-1-H-z R/A SMA and RP-SMA Bulkhead Versions ZB100-0-G-z; ZB100-0-J-z;
ZB100-1-G-z; ZB100-1-J-z Daughter board top surface 35.0mm 5.33mm 12.3mm m m 6
. 1 2 4.1mm 6.1mm 1.3mm 35.0mm m m 6
. 1 2 1.3mm ZB100 Datasheet V1.0 Vertical SMA and RP-SMA Versions ZB100-0-B; ZB100-0-D; ZB100-1-B; ZB100-1-D 35.0mm m m 6 1 2
. 1.3mm 5.33mm 4.1mm Daughter board top surface 12.3mm Vertical SMA and RP-SMA Bulkhead Versions ZB100-0-C; ZB100-0-E; ZB100-1-C; ZB100-1-E m m 6
. 1 2 Optional Rotated position 35.0mm 8.9mm 7.1mm 1.3mm 5.33mm 4.1mm 10.8mm 12.3mm Daughter board top surface www.idc.gb.com 5.33mm 4.1mm Daughter board top surface 16.3mm Optional Rotated position 8.9mm 11.75mm Page 19 of 28 ZB100 OEM Modules Product Datasheet PCB Mounting Information Daughter board PCB Layout and connector pads top view:
22 way header (See table) 2 off 10 way headers for 0V grounding The module requires a clearance hole on the daughter board. This area will need removing to allow for the SMA and RP-SMA RF connector legs and signal pin. Not applicable if using the chip antenna ZB100 Datasheet V1.0 www.idc.gb.com Page 20 of 28 ZB100 OEM Modules Product Datasheet Pin Configuration Connections of the 22-way header are as follows: 0V/Signal ground is provided by the two 10-way headers. Pin #
1 2 Pin Ref. P0_6 P0_7 3 P0_4 4 P0_5 5 P0_2 Use GPIO ADC - AIN6 GPIO ADC AIN7 GPIO ADC AIN4 USART0 / SPI
(SSN) USART0 / UART
(CTS) USART1 / SPI
(MOSI) USART1 / UART
(TxD) TIMER1
(CC2) GPIO ADC AIN5 USART0 / SPI
(SCK) USART0 / UART
(RTS) USART1 / SPI
(MISO) USART1 / UART
(RxD) GPIO ADC AIN2 USART0 / SPI
(MISO) USART0 / UART
(RxD) USART1 / SPI
(SSN) USART1 / UART
(CTS) TIMER1
(CC0) Description Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 6 single ended (Differential with AIN7) 8 12 bit resolution Configurable Pull Up / Pull Down in Input mode, interrupt source 4mA drive strength in output mode Analogue Input 7 single ended (Differential with AIN6) 8 12 bit resolution Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 4 single ended (Differential with AIN5) 8 12 bit resolution SPI0-SSN Data Slave Select (Input) UART0 Clear-to-Send (Input) SPI1-MISO Data - Master Input / Slave Output UART1 Transmit Data (Output) TIMER1 Channel 2 - Capture (Input) / Compare (Output) Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 5 single ended (Differential with AIN4) 8 12 bit resolution SPI0-SCK Clock (Output) UART0 Ready-to-Send (Output) SPI1-MISO Data - Master Input / Slave Outpu UART1 Receive Data (Input) Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 2 single ended (Differential with AIN3) 8 12 bit resolution SPI0-MISO Data - Master Input / Slave Output UART0 Receive Data (Input) SPI1-SSN Slave Select (Input) UART1 Clear-to-Send (Input) TIMER1 Channel 0 - Capture (Input) / Compare (Output) ZB100 Datasheet V1.0 www.idc.gb.com Page 21 of 28 ZB100 OEM Modules Product Datasheet Pin #
Pin Ref. 6 P0_3 7 8 9 P0_0 P0_1 P1_1 Use GPIO ADC AIN3 USART0 / SPI
(MOSI) USART0 / UART
(TxD) USART1 / SPI
(SCK) USART1 / UART
(RTS) TIMER1
(CC1) GPIO ADC AIN0 GPIO ADC AIN1 GPIO TIMER1
(CC1) TIMER4
(CC1)
(Alt2) 10 RESETn SoC RESET 11 P1_3 12 P1_0 13 P1_5
(Alt2) GPIO USART0 / SPI
(Alt2)
(SCK) USART0 / UART
(Alt2)
(RTS) TIMER3
(CC0) GPIO TIMER1
(CC2) TIMER4
(CC0) GPIO USART0 / SPI
(Alt2)
(MOSI) USART0 / UART
(Alt2)
(TxD) USART1 / SPI
(Alt2)
(SCK) USART1 / UART
(Alt2)
(RTS) Description Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 3 single ended (Differential with AIN2) 8 12 bit resolution SPI0-MOSI Data - Master Output / Slave Input UART0 Transmit Data (Output) SPI1-SCK Clock (Output) UART1 Ready-to-Send (Output) TIMER1 Channel 1 - Capture (Input) / Compare (Output) Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 0 single ended (Differential with AIN1) 8 12 bit resolution Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Analogue Input 1 single ended (Differential with AIN0) 8 12 bit resolution NO configurable Pull Up / Pull Down in Input Mode, interrupt source, 20mA drive strength in output mode TIMER1 Channel 1 - Capture (Input) / Compare (Output) Alternative Pin TIMER4 Channel 1 - Capture (Input) / Compare (Output) Used as SoC reset, or in conjunction with the two Debug pins DD and DC in order to enter the debug / programming mode Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI0-SCK Clock (Output) Alternative Pin UART0 Ready-to-Send (Output) Alternative Pin TIMER3 Channel 0 - Capture (Input) / Compare (Output) NO configurable Pull Up / Pull Down in Input Mode, interrupt source, 20mA drive strength in output mode TIMER1 Channel 2 - Capture (Input) / Compare (Output) Alternative Pin TIMER4 Channel 0 - Capture (Input) / Compare (Output) Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI0-MOSI Data - Master Output / Slave Input Alternative Pin UART0 Transmit Data (Output) Alternative Pin SPI1-SCK Clock (Output) Alternative Pin UART1 Ready-to-Send (Output) Alternative Pin ZB100 Datasheet V1.0 www.idc.gb.com Page 22 of 28 Pin #
Pin Ref. Use ZB100 OEM Modules Product Datasheet
(Alt2)
(Alt2) GPIO USART0 / SPI)
(Alt2)
(SSN) USART0 / UART
(Alt2)
(CTS) TIMER1
(CC0) GPIO USART1 / SPI
(Alt2)
(MISO) USART1 / UART
(Alt2)
(RxD) TIMER3
(CC1) GPIO USART0 / SPI
(Alt2)
(MISO) USART0 / UART
(Alt2)
(RxD) USART1 / SPI
(Alt2)
(SSN) USART1 / UART
(Alt2)
(CTS) TIMER3
(CC1) GPIO DC GPIO USART1 / SPI
(Alt2)
(MOSI) USART1 / UART
(Alt2)
(TxD) TIMER3
(CC0) Reg. Input
(Alt2) GPIO DD Description Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI0-SSN Data Slave Select (Input) Alternative Pin UART0 Clear-to-Send (Input) Alternative Pin TIMER1 Channel 0 - Capture (Input) / Compare (Output) Alternative Pin Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI1-MISO Data - Master Input / Slave Output Alternative Pin UART1 Receive Data (Input) Alternative Pin TIMER3 Channel 1 - Capture (Input) / Compare (Output) Alternative Pin Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI0-MISO Data - Master Input / Slave Output Alternative Pin UART0 Receive Data (Input) Alternative Pin SPI1-SSN Slave Select (Input) Alternative Pin UART1 Clear-to-Send (Input) Alternative Pin TIMER3 Channel 1 - Capture (Input) / Compare (Output) Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Debug Clock used in conjunction with RESETn and DD Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode SPI1-MOSI Data Master Output / Slave Input Alternative Pin UART1 Transmit Data (Output) Alternative Pin TIMER3 Channel 0 - Capture (Input) / Compare (Output) Alternative Pin On-board regulator (4 to 30V). The regulator can provide 100mA max. Configurable Pull Up / Pull Down in Input mode, interrupt source, 4mA drive strength in output mode Debug Data used in conjunction with RESETn and DC 14 P1_2 15 P1_7 16 P1_4 17 P2_2 18 P1_6 19 20 21 22 Vunreg P2_1 Vreg 3.3V Reg. Output SoC VDD Vout from the Regulator Section. Link to Pin 22 when powering the SoC using the on-board regulator. SoC Supply Voltage (2.0 to 3.6V) 3V battery powered connection point. NOTE: Refer to CC2430.pdf and/or CC2431.pdf Datasheets from the Texas Instruments Website for in-
depth detail for configuring and programming the SoC device. ZB100 Datasheet V1.0 www.idc.gb.com Page 23 of 28 ZB100 OEM Modules Product Datasheet Agency Certifications EUROPEAN UNION (ETSI) The ZB100 Module has been certified for use in European Union countries. If the ZB100 Modules are incorporated into a product, the manufacturer must ensure compliance of the final product to the European harmonised EMC and low-voltage/safety standards. A Declaration of Conformity must be issued for each of these standards and kept on file as described in Annex II of the R&TTE Directive. Furthermore, the manufacturer must maintain a copy of the ZB100 Modules documentation and ensure the final product does not exceed the specified power ratings, antenna specifications, and/or installation requirements as specified in the user manual. If any of these specifications are exceeded in the final product, a submission must be made to a notidied body for compliance testing to all required standards. IMPORTANT:
CE taking the form shown above. The CE markin must be affixed to a visible location on the OEM product. The CE mark shall consist of the initials If the CE marking is reduced or enlarged, the proportions given in the above example must be respected. The CE marking must have a height of at least 5mm except where this is not possible on account of the nature of the apparatus. The CE marking must be affixed visibly, legibly, and indelibly. o o o UNITED STATES (FCC) This equipment complies with Part 15 of the FCC rules and regulations. To fulfill the FCC Certification requirements, an OEM manufacturer must comply with the following regulations:
1. The modular transmitter must be labelled with its own FCC ID number, and, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following:
Chip Antenna RF connector Vertical RP-SMA RF connector Vertical RP-SMA bulkhead Example of Label required for OEM products containing the following Model codes:
ZB100-x-A ZB100-x-D ZB100-x-E ZB100-x-H-y RF connector Right-angled RP-SMA ZB100-x-J-y RF connectot Right-angled RP-SMA bulkhead Note: x refers to the System-on-Chip variant either CC2430 or CC2431. y refers to mountng position for right angled connectors See Model Coding Section. Contains FCC ID: VO7ZB100 The enclosed device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (i) this device may not cause harmful interference and (ii) this device must accept any interference received, including interference that may cause undesired operation. Any similar wording that expresses the same meaning may be used. ZB100 Datasheet V1.0 www.idc.gb.com Page 24 of 28 ZB100 OEM Modules Product Datasheet 2. For RF Connector models, the external antennas have been tested and approved specified below. The ZB100 (D, E, H or J) models may be integrated with other types or custom designed antennas which the OEM installer must authorize following the FCC 15.21 requirements. WARNING:
IMPORTANT:
IMPORTANT:
IMPORTANT:
The Original Equipment Manufacturer (OEM) must ensure that the OEM modular transmitter must be labeled with its own FCC ID number. This includes a clearly visible label on the outside of the final product enclosure that displays the contents shown below. If the FCC ID is not visible when the equipment is installed inside another device, then the outside of the device into which the equipment is installed must also display a label referring to the enclosed equipment. This equipemtn complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (i) this device may not cause harmful interference and (ii) this device must accept any interference received, including interference that may cause undesired operation (FCC 15.19) The internal / external antenna(s) used for this mobile transmitter must provide a separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Modifications not expressly approved by this company could void the users authority to operate this equipment
(FCC section 15.21) This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in residential areas is likely to cause harmful interference in which case the user will be required to correct the interference at his/her own expense (FCC section 15.105). Approved Antenna List Part Number 3030A5839-01 2010B4844-01 (SMA) 2010B6090-01 (RP-SMA) NET-WL-ANT009OSC Manufacturer / Description Antenova Rufa chip antenna
(Left-hand), frequency range 2400 2500MHz Antenova Titanis, swivel antenna
(1/2 wave), frequency range 2400 2500MHz Solwise omni-directional dipole with RP-SMA connector, frequency range 2400 2500MHz See Notes **
Gain, dBI ETSI FCC 2.1dBi Peak 2.2dBi Peak 8.50.5dBi
NOTES:
All testing has been carried out with the CC2430 / CC2431 programmed for maximum RF output power of 0.6 dBm (Register TXCTRLL = 0xFF). Any omni-directional dipole (articulated or straight) may be used providing the gain is less than that tested using the NET-WL-ANT009OSC (9dBi)
** Channel 26 - restriction for use under FCC Part 15 Rules. The output power for channel 26 (2480MHz) is restricted as follows:
1. Use an omni-directional dipole antenna with gain no greater than 3 dBi. 2. Reduce the radio power accordingly within the software. E.g. for the 9dBi antenna, the power outputs needs reducing by 6dB from maximum. ZB100 Datasheet V1.0 www.idc.gb.com Page 25 of 28 ZB100 OEM Modules Product Datasheet Glossary ADC AES AIN#
bps CBC CBC-MAC Cipher Block Chaining Message Analogue to Digital Converter Advanced Encryption Standard Analogue Input Channel #number Bits per Second Cipher Block Chaining CC#
CCA CCM CD CE Authentication Code Capture Compare #number Clear Channel Assessment, Radio Counter Mode + CBC-MAC Carrier Detect European marking to indicate conformity Cipher Feedback Central Processing Unit CFB CPU CSMA/CA Carrier Sense Multiple Access with CTR CTS DC(1) DC(2) DD DMA DSR DSSS DTR ECB ESD ETSI EUI FCC FFCTRL FFD FIFO FIFOP FLASH GPIO HW Collision Avoidanced Counter Mode (encryption) Clear to Send, UART Interface Direct Current Debug Clock Debug Data Direct Memory Access Data Set Ready Direct Sequence Spread Spectrum Data Terminal Ready Electronic Codebook (encryption) Electro Static Discharge European Telecommunications Standards Institute Extended Unique Identifier Federal Communications Commission FIFO and Frame Control Full-Function Device First In First Out FIFO receive buffer overflowed threshold, Radio Interface Non-volatile memory which can be electrically erased and re-programmed General Purpose Input/Output Hardware IEEE IF IRQ ISM Institute of Electrical and Electronic Engineers Intermediate Frequency Interrupt Request Industrial, Scientific and Medical frequency band - a part of the radio spectrum that can be used by anybody without a license in most countries Initialisation Vector (AES) 1024 bytes Inductor-Capacitor Low Noise Amplifer IV kByte LC LNA LR-WPAN Low Rate Wireless Personal Area LSB MAC MCU Network Least Significant Bit Medium Access Control layer Microcontroller Unit - For the ZB100, this refers to the 8051 core processor in either the CC2430 or CC2431 MISO Master In / Slave Out, SPI Interface MOSI Master Out / Slave In, SPI Interface MSB Most Significant Bit MSK Minimum Shift Keying NONCE Not Once (AES) OEM Original Equipment Manufacturer OFB Output Feedback (encryption) O-QPSK Offset-Quadrature Phase Shift OTA OUI PA PC PCB PER PHY PLL POR PWM R&TTE RAM Keying Over-the-Air upgrade/programming Organisationally Unique Identifier
(24-bit) Power Amplifier Personal Computer Printed Circuit Board Packet Error Rate Physical Layer Phase Locked Loop Power on Reset Pulse Width Modulator Radio and Telecommunications Terminal Equipment Random Access Memory ZB100 Datasheet V1.0 www.idc.gb.com Page 26 of 28 R/A RC RCOSC RF RP-SMA RSSI RTS ROM RoHS RTC RxD SCK SFR SMA SoC ZB100 OEM Modules Product Datasheet Right Angled Resistor / Capacitor RC Oscillator Radio Frequency Reverse Polarity Sub-miniature Version A coaxial RF connector with reversed gender (Required for FCC compliance) Received Signal Strength Indicator Ready to Send, UART Interface Read only memory Restriction on Hazardous Substances Real Time Clock Receive Data, UART Interface Serial Clock, SPI Interface Special Function Register Sub-miniature Version A coaxial RF connector System-on-Chip SPI SRAM SSN ST SW TI TxD TX UART UID USART VCO XOSC 802.15.4 Serial Peripheral Interface bus Static Random Access Memory Slave Select Number, SPI Interface Sleep Timer Software Texas Instruments Transmit Data, UART Interface Transmit, Radio Universal Asynchrouns Receiver/Transmitter Unique Identifier Universal Synchronous/Asynchrouns Receiver/Transmitter Voltage Controlled Oscillator Crystal Oscillator The IEEE 802.15.4-2003 standard applicable to low-rate wireless Personal Area Networks ZB100 Datasheet V1.0 www.idc.gb.com Page 27 of 28 ZB100 OEM Modules Product Datasheet Related Documents
[1]
[2]
[3]
Chipcon Products fromTexas Instruments CC2430 A True System-on-Chip solution for 2.4GHz IEEE 802.15.4 / ZigBee CC2430 Data Sheet (Rev. 2.1) SWRS036F Chipcon Products fromTexas Instruments CC2431 System-on-Chip for 2.4 GHz ZigBee/ IEEE 802.15.4 with Location Engine CC2431 Data Sheet (Rev. 2.01) SWRS034B Chipcon Products fromTexas Instruments Application Note AN042 CC2431 Location Engine Application Note AN042 (Rev. 1.0) SWRA095 Design Note DN108 Using AES Encryption in CC111xFx, CC243x, and CC251xFx SWRA172A CC1110DK/ CC2430DK/CC2510DK Development Kit - User Manual - Rev. 1.5 SWRU039 Dallas/Maxim 1-wire Communication Through Software App Note 126
[4]
[5]
[6]
Disclaimer Intelligent Distributed Controls Limited believes that at the time of issue, all information contained herein to be accurate. Intelligent Distributed Controls Limited reserves the right to make changes to this product or documentation without prior notice. Latest available revisions shall be provided on the Website. Contact Information Intelligent Distributed Controls Limited Suite 6 Keynes House Chester Park Alfreton Road Derby DE21 4AS United Kingdom Tel:
Fax:
E-mail:
Website:
Office Hours: 9:00am - 5:00pm GMT
+44(0)1332 604030
+44(0)1332 604031 sales @idc.gb.com www.idc.gb.com ZB100 Datasheet V1.0 www.idc.gb.com Page 28 of 28
1 | Voltage regulator Datasheet | Users Manual | 1.18 MiB |
L P 2 9 5 0
L P 2 9 5 1 S e r i e s o f i l j A d u s t a b e M c r o p o w e r V o l t a g e R e g u a t o r s l May 2005
(.05% typ.) and a very low output voltage temperature coef-
ficient, making the part useful as a low-power voltage refer-
ence. LP2950/LP2951 Series of Adjustable Micropower Voltage Regulators General Description The LP2950 and LP2951 are micropower voltage regulators with very low quiescent current (75A typ.) and very low dropout voltage (typ. 40mV at light loads and 380mV at 100mA). They are ideally suited for use in battery-powered systems. Furthermore, the quiescent current of the LP2950/
LP2951 increases only slightly in dropout, prolonging battery life. The LP2950-5.0 is available in the surface-mount D-Pak package, and in the popular 3-pin TO-92 package for pin-
compatibility with older 5V regulators. The 8-lead LP2951 is available in plastic, ceramic dual-in-line, LLP, or metal can packages and offers additional system functions. One such feature is an error flag output which warns of a low output voltage, often due to falling batteries on the input. It may be used for a power-on reset. A second feature is the logic-compatible shutdown input which enables the regulator to be switched on and off. Also, the part may be pin-strapped for a 5V, 3V, or 3.3V output (depending on the version), or programmed from 1.24V to 29V with an external pair of resistors. Careful design of the LP2950/LP2951 has minimized all contributions to the error budget. This includes a tight initial tolerance (.5% typ.), extremely good load and line regulation Features n 5V, 3V, and 3.3V versions available n High accuracy output voltage n Guaranteed 100mA output current n Extremely low quiescent current n Low dropout voltage n Extremely tight load and line regulation n Very low temperature coefficient n Use as Regulator or Reference n Needs minimum capacitance for stability n Current and Thermal Limiting n Stable with low-ESR output capacitors (10m to 6) LP2951 versions only n Error flag warns of output dropout n Logic-controlled electronic shutdown n Output programmable from 1.24 to 29V Block Diagram and Typical Applications LP2950 LP2951 00854625 00854601 2005 National Semiconductor Corporation DS008546 www.national.com Connection Diagrams TO-92 Plastic Package (Z) TO-252 (D-Pak) 1 5 9 2 P L 0 5 9 2 P L
Bottom View 00854602 Dual-In-Line Packages (N, J) Surface-Mount Package (M, MM) Top View 00854626 Metal Can Package (H) 00854670 Front View 8-Lead LLP Pin 4 is fused to center DAP Top View 00854671 Top View 00854619 10-Lead Ceramic Surface-Mount Package (WG) Top View 00854664 www.national.com 2 L P 2 9 5 0 L P 2 9 5 1
Ordering Information Package Temperature Part Number Package Marking Transport Media NSC Drawing Range TO-92 (Z) 40 < TJ < 125 TO-252
(D-Pak) 40 < TJ < 125 N (N-08E) 40 < TJ < 125 M (M08A) 40 < TJ < 125 MM
(MUA08A) 40 < TJ < 125 J (J08A) H (H08C) WG
(WG10A) 55 < TJ < 150 55 < TJ < 150 55 < TJ < 150 LP2950ACZ-3.0 LP2950CZ-3.0 LP2950ACZ-3.3 LP2950CZ-3.3 LP2950ACZ-5.0 LP2950CZ-5.0 LP2950CDT-3.0 LP2950CDTX-3.0 LP2950CDT-3.3 LP2950CDTX-3.3 LP2950CDT-5.0 LP2950CDTX-5.0 LP2951ACN-3.0 LP2951CN-3.0 LP2951ACN-3.3 LP2951CN-3.3 LP2951ACN LP2951CN LP2951ACM-3.0 LP2951ACMX-3.0 LP2951CM-3.0 LP2951CMX-3.0 LP2951ACM-3.3 LP2951ACMX-3.3 LP2951CM-3.3 LP2951CMX-3.3 LP2951ACM LP2951ACMX LP2951CM LP2951CMX LP2951ACMM-3.0 LP2951ACMMX-3.0 LP2951CMM-3.0 LP2951CMMX-3.0 LP2951ACMM-3.3 LP2951ACMMX-3.3 LP2951CMM-3.3 LP2951CMMX-3.3 LP2951ACMM LP2951ACMMX LP2951CMM LP2951CMMX LP2951J/883 LP2951H/883 LP2951WG/883 2950A CZ3.0 2950 CZ3.0 2950A CZ3.3 2950 CZ3.3 2950A CZ5.0 2950 CZ5.0 Bag Bag Bag Bag Bag Bag Z03A LP2950CDT-3.0 75 Units/Rail TD03B LP2950CDT-3.3 75 Units/Rail 2.5k Units Tape and Reel 2.5k Units Tape and Reel LP2950CDT-5.0 75 Units/Rail 2.5k Units Tape and Reel LP2951ACN-3.0 LP2951CN-3.0 LP2951ACN-3.3 LP2951CN-3.3 LP2951ACN LP2951CN 2951ACM30*
40 Units/Rail 40 Units/Rail 40 Units/Rail 40 Units/Rail 40 Units/Rail 40 Units/Rail 95 Units/Rail N08E M08A
(where * is die rev letter) 2.5k Units Tape and Reel 2951CM30*
95 Units/Rail
(where * is die rev letter) 2.5k Units Tape and Reel 2951ACM33*
95 Units/Rail
(where * is die rev letter) 2.5k Units Tape and Reel 2951CM33*
95 Units/Rail
(where * is die rev letter) 2.5k Units Tape and Reel 2951ACM*
95 Units/Rail
(where * is die rev letter) 2.5k Units Tape and Reel 2951CM*
95 Units/Rail
(where * is die rev letter) L0BA L0BB L0CA L0CB L0DA L0DB See MIL/AERO Datasheet See MIL/AERO Datasheet See MIL/AERO Datasheet 2.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel 40 Units/Rail Tray Tray MUA08A J08A H08C WG10A 3 www.national.com 1 5 9 2 P L 0 5 9 2 P L
Ordering Information (Continued) Package Temperature Part Number Package Marking Transport Media NSC Drawing Range 40 < TJ < 125 8-lead LLP SDC08A LP2951ACSD-3.0 LP2951ACSDX-3.0 LP2951CSD-3.0 LP2951CSDX-3.0 LP2951ACSD-3.3 LP2951ACSDX-3.3 LP2951CSD-3.3 LP2951CSDX-3.3 LP2951ACSD LP2951ACSDX LP2951CSD LP2951CSDX 51AC30 51AC30B 51AC33 51AC33B 2951AC 2951ACB 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel www.national.com 4 L P 2 9 5 0 L P 2 9 5 1
ESD Rating Human Body Model(Note 18) 2500V Operating Ratings (Note 1) Maximum Input Supply Voltage Junction Temperature Range
(TJ) (Note 8) LP2951 LP2950AC-XX, LP2950C-XX, LP2951AC-XX, LP2951C-XX 30V 55 to +150C 40 to +125C Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications. Input Supply Voltage SHUTDOWN Input Voltage, Error Comparator Output Voltage, (Note 9) FEEDBACK Input Voltage
(Note 9) (Note 10) Power Dissipation Junction Temperature (TJ) Ambient Storage Temperature Soldering Dwell Time, Temperature Wave Infrared Vapor Phase 0.3 to +30V 1.5 to +30V Internally Limited
+150C 65 to +150C 4 seconds, 260C 10 seconds, 240C 75 seconds, 219C Electrical Characteristics (Note 2) LP2951 LP2950AC-XX LP2951AC-XX Tested Limit Typ Typ
(Notes 3, 16) Tested Design Limit Limit
(Note 3)
(Note 4) Typ LP2950C-XX LP2951C-XX Tested Design Limit Limit
(Note 3)
(Note 4) Parameter Conditions
(Note 2) 3V Versions (Note 17) Output Voltage TJ = 25C 25C TJ 85C Full Operating Temperature Range 100A IL 100mA TJ TJMAX Output Voltage 3.3V Versions (Note 17) Output Voltage TJ = 25C 25C TJ 85C Full Operating Temperature Range 100A IL 100mA TJ TJMAX Output Voltage 5V Versions (Note 17) Output Voltage TJ = 25C 25C TJ 85C Full Operating 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 5.0 5.0 5.0 3.015 2.985 3.036 2.964 3.045 2.955 3.317 3.284 3.340 3.260 3.350 3.251 5.025 4.975 5.06 3.015 2.985 3.317 3.284 5.025 4.975 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 5.0 5.0 5.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 5.0 5.0 5.0 3.030 2.970 3.036 2.964 3.042 2.958 3.333 3.267 3.340 3.260 3.346 3.254 5.05 4.95 5.06 3.030 2.970 3.333 3.267 5.05 4.95 Units V max V min V max V min V max V min 3.045 2.955 3.060 2.940 3.072 V max 2.928 V min V max V min V max V min V max V min 3.350 3.251 3.366 3.234 3.379 V max 3.221 V min V max V min V max V min V max 5.075 4.925 5.1 5 www.national.com 1 5 9 2 P L 0 5 9 2 P L
Electrical Characteristics (Note 2)
(Continued) Parameter Conditions
(Note 2) LP2951 LP2950AC-XX LP2951AC-XX Tested Limit Typ Typ
(Notes 3, 16) Tested Design Limit Limit
(Note 3)
(Note 4) Typ LP2950C-XX LP2951C-XX Tested Design Limit Limit
(Note 3)
(Note 4) Units Temperature Range 100A IL 100mA TJ TJMAX 4.94 5.075 4.925 5.0 5.0 4.94 5.075 4.925 5.0 4.9 V min 5.12 V max 4.88 V min
(Note 12) 20 120 20 100 50 150 ppm/C Output Voltage All Voltage Options Output Voltage Temperature Coefficient Line Regulation
(Note 14) Load Regulation
(Note 14) Dropout Voltage
(Note 5) Ground Current Dropout Ground Current Current Limit
(VONOM + 1)V Vin 30V (Note 15) 100A IL 100mA IL = 100A IL = 100mA IL = 100A IL = 100mA Vin = (VONOM 0.5)V IL = 100A Vout = 0 Thermal Regulation
(Note 13) CL = 1F (5V Only) CL = 200F CL = 3.3F
(Bypass = 0.01F Pins 7 to 1
(LP2951) Output Noise, 10 Hz to 100 kHz 8-pin Versions Only Reference Voltage Reference Voltage Feedback Pin Bias Current Reference Voltage
(Note 7)
(Note 12) www.national.com 0.03 0.04 50 380 75 8 110 160 0.05 430 160 100 1.235 20 20 0.1 0.5 0.1 0.3 80 150 450 600 120 140 12 14 170 200 200 220 0.2 0.03 0.1 0.04 0.2
% max 0.4
% max 0.04 0.1 80 450 120 50 380 75 8 12 110 170 160 200 0.2 0.2 0.1 0.2 150 50 80 450 120 380 75 8 12 110 170 160 200 600 140 14 200 220 0.05 0.2 0.05 0.2 430 160 100 430 160 100 0.3 150 600 140 14 200 220 LP2951 LP2951AC-XX LP2951C-XX 1.25 1.26 1.22 1.2 1.27 1.19 40 60 1.235 1.25 1.235 1.26 1.22 40 1.26 1.2 1.27 1.19 60 20 50 1.21 40 1.27 1.2 1.285 1.185 60 20 20 6
% max
% max mV max mV max mV max mV max A max A max mA max mA max A max A max mA max mA max
%/W max V rms V rms V rms V max V max V min V min V max V min nA max nA max ppm/C Electrical Characteristics (Note 2)
(Continued) Parameter Conditions
(Note 2) LP2951 LP2950AC-XX LP2951AC-XX Tested Limit Typ Typ
(Notes 3, 16) Tested Design Limit Limit
(Note 3)
(Note 4) Typ LP2950C-XX LP2951C-XX Tested Design Limit Limit
(Note 3)
(Note 4) Units L P 2 9 5 0 L P 2 9 5 1
0.1 0.1 0.1 nA/C All Voltage Options Temperature Coefficient Feedback Pin Bias Current Temperature Coefficient Error Comparator Output Leakage Current Output Low Voltage Upper Threshold Voltage Lower Threshold Voltage Hysteresis Shutdown Input Input Logic Voltage Shutdown Pin Input Current VOH = 30V Vin = (VONOM 0.5)V IOL = 400A
(Note 6)
(Note 6)
(Note 6) Low (Regulator ON) High (Regulator OFF) Vshutdown = 2.4V 0.01 150 60 75 15 1.3 30 Vshutdown = 30V 450 Regulator Output Current in Shutdown
(Note 11) 3 1 2 250 400 40 25 95 140 0.6 2.0 50 100 600 750 10 20 0.01 1 0.01 1 150 250 40 95 60 75 15 1.3 30 50 450 600 3 10 2 400 25 140 0.7 2.0 100 750 20 150 250 40 95 60 75 15 1.3 30 50 450 600 3 10 A max A max mV max mV max mV min mV min mV max mV max mV V V max V min A max A max A max A max A max A max 2 400 25 140 0.7 2.0 100 750 20 Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: Unless otherwise specified all limits guaranteed for VIN = (VONOM + 1)V, IL = 100A and CL = 1F for 5V versions and 2.2F for 3V and 3.3V versions. Limits appearing in boldface type apply over the entire junction temperature range for operation. Limits appearing in normal type apply for TA = TJ = 25C. Additional conditions for the 8-pin versions are FEEDBACK tied to VTAP, OUTPUT tied to SENSE, and VSHUTDOWN 0.8V. Note 3: Guaranteed and 100% production tested. Note 4: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing AQL levels. Note 5: Dropout Voltage is defined as the input to output differential at which the output voltage drops 100 mV below its nominal value measured at 1V differential. At very low values of programmed output voltage, the minimum input supply voltage of 2V (2.3V over temperature) must be taken into account. Note 6: Comparator thresholds are expressed in terms of a voltage differential at the Feedback terminal below the nominal reference voltage measured at Vin =
(VONOM + 1)V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain = Vout/Vref = (R1 + R2)/R2.For example, at a programmed output voltage of 5V, the Error output is guaranteed to go low when the output drops by 95mV x 5V/1.235V = 384 mV. Thresholds remain constant as a percent of Vout as Vout is varied, with the dropout warning occurring at typically 5% below nominal, 7.5% guaranteed. Note 7: Vref Vout (Vin 1V), 2.3V Vin 30V, 100A IL 100mA, TJ TJMAX. Note 8: The junction-to-ambient thermal resistances are as follows: 180C/W and 160C/W for the TO-92 package with 0.40 inch and 0.25 inch leads to the printed circuit board (PCB) respectively, 105C/W for the molded plastic DIP (N), 130C/W for the ceramic DIP (J), 160C/W for the molded plastic SOP (M), 200C/W for the molded plastic MSOP (MM), and 160C/W for the metal can package (H). The above thermal resistances for the N, J, M, and MM packages apply when the package is soldered directly to the PCB. Junction-to-case thermal resistance for the H package is 20C/W. Junction-to-case thermal resistance for the TO-252 package is 5.4C/W. The value of JA for the LLP package is typically 51C/W but is dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For details of thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. Note 9: May exceed input supply voltage. 7 www.national.com 1 5 9 2 P L 0 5 9 2 P L
Electrical Characteristics (Note 2)
(Continued) Note 10: When used in dual-supply systems where the output terminal sees loads returned to a negative supply, the output voltage should be diode-clamped to ground. Note 11: Vshutdown 2V, Vin 30V, Vout = 0, Feedback pin tied to VTAP. Note 12: Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range. Note 13: Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a 50mA load pulse at VIN = 30V (1.25W pulse) for T = 10ms. Note 14: Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation. Note 15: Line regulation for the LP2951 is tested at 150C for IL = 1mA. For IL = 100A and TJ = 125C, line regulation is guaranteed by design to 0.2%. See Typical Performance Characteristics for line regulation versus temperature and load current. Note 16: A Military RETS specification is available on request. At time of printing, the LP2951 RETS specification complied with the boldface limits in this column. The LP2951H, WG, or J may also be procured as Standard Military Drawing Spec #5962-3870501MGA, MXA, or MPA. Note 17: All LP2950 devices have the nominal output voltage coded as the last two digits of the part number. In the LP2951 products, the 3.0V and 3.3V versions are designated by the last two digits, but the 5V version is denoted with no code at this location of the part number (refer to ordering information table). Note 18: Human Body Model 1.5k in series with 100pF. www.national.com 8 Typical Performance Characteristics Quiescent Current Dropout Characteristics L P 2 9 5 0 L P 2 9 5 1
Input Current Input Current 00854627 00854628 Output Voltage vs. Temperature of 3 Representative Units Quiescent Current 00854629 00854630 00854631 00854632 9 www.national.com Typical Performance Characteristics (Continued) Quiescent Current Quiescent Current 1 5 9 2 P L 0 5 9 2 P L
Quiescent Current Short Circuit Current 00854633 00854634 Dropout Voltage Dropout Voltage 00854635 00854636 00854637 00854638 www.national.com 10 Typical Performance Characteristics (Continued) LP2951 Minimum Operating Voltage LP2951 Feedback Bias Current L P 2 9 5 0 L P 2 9 5 1
LP2951 Feedback Pin Current LP2951 Error Comparator Output 00854639 00854640 LP2951 Comparator Sink Current Line Transient Response 00854641 00854642 00854643 00854644 11 www.national.com Typical Performance Characteristics (Continued) Load Transient Response Load Transient Response 1 5 9 2 P L 0 5 9 2 P L
LP2951 Enable Transient Output Impedance 00854645 00854646 Ripple Rejection Ripple Rejection 00854647 00854648 00854649 00854650 www.national.com 12 Typical Performance Characteristics (Continued) Ripple Rejection LP2951 Output Noise L P 2 9 5 0 L P 2 9 5 1
LP2951 Divider Resistance Shutdown Threshold Voltage 00854651 00854652 Line Regulation LP2951 Maximum Rated Output Current 00854653 00854654 00854655 00854656 13 www.national.com Typical Performance Characteristics (Continued) LP2950 Maximum Rated Output Current Thermal Response 1 5 9 2 P L 0 5 9 2 P L
Output Capacitor ESR Range 00854657 00854658 00854663 www.national.com 14 Application Hints EXTERNAL CAPACITORS A 1.0F (or greater) capacitor is required between the output and ground for stability at output voltages of 5V or more. At lower output voltages, more capacitance is required (2.2F or more is recommended for 3V and 3.3V versions). Without this capacitor the part will oscillate. Most types of tantalum or aluminum electrolytics work fine here; even film types work but are not recommended for reasons of cost. Many alumi-
num electrolytics have electrolytes that freeze at about 30C, so solid tantalums are recommended for operation below 25C. The important parameters of the capacitor are an ESR of about 5 or less and a resonant frequency above 500kHz. The value of this capacitor may be increased with-
out limit. Ceramic capacitors whose value is greater than 1000pF should not be connected directly from the LP2951 output to ground. Ceramic capacitors typically have ESR values in the range of 5 to 10m, a value below the lower limit for stable operation (see curve Output Capacitor ESR Range). The reason for the lower ESR limit is that the loop compen-
sation of the part relies on the ESR of the output capacitor to provide the zero that gives added phase lead. The ESR of ceramic capacitors is so low that this phase lead does not occur, significantly reducing phase margin. A ceramic output capacitor can be used if a series resistance is added (rec-
ommended value of resistance about 0.1 to 2). At lower values of output current, less output capacitance is required for stability. The capacitor can be reduced to 0.33F for currents below 10mA or 0.1F for currents below 1mA. Using the adjustable versions at voltages below 5V runs the error amplifier at lower gains so that more output capaci-
tance is needed. For the worst-case situation of a 100mA load at 1.23V output (Output shorted to Feedback) a 3.3F
(or greater) capacitor should be used. Unlike many other regulators, the LP2950 will remain stable and in regulation with no load in addition to the internal voltage divider. This is especially important in CMOS RAM keep-alive applications. When setting the output voltage of the LP2951 versions with external resistors, a minimum load of 1A is recommended. A 1F tantalum, ceramic or aluminum electrolytic capacitor should be placed from the LP2950/LP2951 input to ground if there is more than 10 inches of wire between the input and the AC filter capacitor or if a battery is used as the input. Stray capacitance to the LP2951 Feedback terminal can cause instability. This may especially be a problem when using high value external resistors to set the output voltage. Adding a 100pF capacitor between Output and Feedback and increasing the output capacitor to at least 3.3F will fix this problem. ERROR DETECTION COMPARATOR OUTPUT The comparator produces a logic low output whenever the LP2951 output falls out of regulation by more than approxi-
mately 5%. This figure is the comparators built-in offset of about 60mV divided by the 1.235 reference voltage. (Refer to the block diagram in the front of the datasheet.) This trip level remains 5% below normal regardless of the pro-
grammed output voltage of the 2951. For example, the error flag trip level is typically 4.75V for a 5V output or 11.4V for a 12V output. The out of regulation condition may be due either to low input voltage, current limiting, or thermal limit-
ing. L P 2 9 5 0 L P 2 9 5 1
Figure 1 below gives a timing diagram depicting the ERROR signal and the regulated output voltage as the LP2951 input is ramped up and down. For 5V versions, the ERROR signal becomes valid (low) at about 1.3V input. It goes high at about 5V input (the input voltage at which VOUT = 4.75V). Since the LP2951s dropout voltage is load-dependent (see curve in typical performance characteristics), the input volt-
age trip point (about 5V) will vary with the load current. The output voltage trip point (approx. 4.75V) does not vary with load. The error comparator has an open-collector output which requires an external pullup resistor. This resistor may be returned to the output or some other supply voltage depend-
ing on system requirements. In determining a value for this resistor, note that while the output is rated to sink 400A, this sink current adds to battery drain in a low battery condition. Suggested values range from 100k to 1 M. The resistor is not required if this output is unused. 00854620
*When VIN 1.3V, the error flag pin becomes a high impedance, and the error flag voltage rises to its pull-up voltage. Using VOUT as the pull-up voltage (see Figure 2), rather than an external 5V source, will keep the error flag voltage under 1.2V (typ.) in this condition. The user may wish to divide down the error flag voltage using equal-value resistors (10k suggested), to ensure a low-level logic signal during any fault condition, while still allowing a valid high logic level during normal operation. FIGURE 1. ERROR Output Timing PROGRAMMING THE OUTPUT VOLTAGE (LP2951) The LP2951 may be pin-strapped for the nominal fixed out-
put voltage using its internal voltage divider by tying the output and sense pins together, and also tying the feedback and VTAP pins together. Alternatively, it may be programmed for any output voltage between its 1.235V reference and its 30V maximum rating. As seen in Figure 2, an external pair of resistors is required. The complete equation for the output voltage is where VREF is the nominal 1.235 reference voltage and IFB is the feedback pin bias current, nominally 20nA. The mini-
mum recommended load current of 1A forces an upper limit of 1.2 M on the value of R2, if the regulator must work with no load (a condition often found in CMOS in standby). IFB will produce a 2% typical error in VOUT which may be eliminated at room temperature by trimming R1. For better accuracy, choosing R2 = 100k reduces this error to 0.17% while in-
creasing the resistor program current to 12A. Since the LP2951 typically draws 60A at no load with Pin 2 open-
circuited, this is a small price to pay. 15 www.national.com Application Hints (Continued) 1 5 9 2 P L 0 5 9 2 P L
*See Application Hints 00854607
**Drive with TTL-high to shut down. Ground or leave open if shutdown feature is not to be used. Note: Pins 2 and 6 are left open. FIGURE 2. Adjustable Regulator Typical Applications REDUCING OUTPUT NOISE In reference applications it may be advantageous to reduce the AC noise present at the output. One method is to reduce the regulator bandwidth by increasing the size of the output capacitor. This is the only way noise can be reduced on the 3 lead LP2950 but is relatively inefficient, as increasing the capacitor from 1F to 220F only decreases the noise from 430V to 160V rms for a 100kHz bandwidth at 5V output. Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4 to unity. Pick or about 0.01F. When doing this, the output capacitor must be increased to 3.3F to maintain stability. These changes reduce the output noise from 430V to 100V rms for a 100kHz bandwidth at 5V output. With the bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at higher output voltages. 1A Regulator with 1.2V Dropout 300mA Regulator with 0.75V Dropout Wide Input Voltage Range Current Limiter 00854622 00854621
*Minimum input-output voltage ranges from 40mV to 400mV, depending on load current. Current limit is typically 160mA. 00854609 www.national.com 16 Typical Applications (Continued) Low Drift Current Source 5 Volt Current Limiter L P 2 9 5 0 L P 2 9 5 1
*Minimum input-output voltage ranges from 40mV to 400mV, depending on load current. Current limit is typically 160mA. 00854610 Regulator with Early Warning and Auxiliary Output Latch Off When Error Flag Occurs 00854608 00854612 00854611 j Early warning flag on low input voltage j Main output latches off at lower input voltages j Battery backup on auxiliary output j Operation: Reg. #1s Vout is programmed one diode drop above 5V. Its error flag becomes active when Vin 5.7V. When Vin drops below 5.3V, the error flag of Reg. #2 becomes active and via Q1 latches the main output off. When Vin again exceeds 5.7V Reg. #1 is back in regulation and the early warning signal rises, unlatching Reg. #2 via D3. 17 www.national.com Typical Applications (Continued) 2 Ampere Low Dropout Regulator 1 5 9 2 P L 0 5 9 2 P L
00854613 For 5Vout, use internal resistors. Wire pin 6 to 7, & wire pin 2 to +Vout Bus. 5V Regulator with 2.5V Sleep Function Open Circuit Detector for 4 20mA Current Loop
*High input lowers Vout to 2.5V 00854614 00854615 www.national.com 18 Typical Applications (Continued) Regulator with State-of-Charge Indicator L P 2 9 5 0 L P 2 9 5 1
*Optional Latch off when drop out occurs. Adjust R3 for C2 Switching when Vin is 6.0V.
**Outputs go low when Vin drops below designated thresholds. 00854616 Low Battery Disconnect For values shown, Regulator shuts down when Vin < 5.5V and turns on again at 6.0V. Current drain in disconnected mode is 150A.
*Sets disconnect Voltage
**Sets disconnect Hysteresis 00854617 19 www.national.com Typical Applications (Continued) System Overtemperature Protection Circuit 1 5 9 2 P L 0 5 9 2 P L
LM34 for 125F Shutdown LM35 for 125C Shutdown 00854618 www.national.com 20 L P 2 9 5 0 L P 2 9 5 1
3 2 6 4 5 8 0 0 m a r g a i D c i t a m e h c S 21 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 1 5 9 2 P L 0 5 9 2 P L
Order Number LP2951WG/883 NS Package Number WG10A Metal Can Package (H) NS Package Number H08C www.national.com 22 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) L P 2 9 5 0 L P 2 9 5 1
Ceramic Dual-In-Line Package (J) NS Package Number J08A Surface Mount Package (M) NS Package Number M08A 23 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 1 5 9 2 P L 0 5 9 2 P L
Molded Dual-In-Line Package (N) NS Package Number N08E Molded TO-92 Package (Z) NS Package Number Z03A www.national.com 24 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) L P 2 9 5 0 L P 2 9 5 1
Surface Mount Package (MM) NS Package Number MUA08A D-Pak Package NS Package Number TD03B 25 www.national.com s r o t a l u g e R e g a t l o V r e w o p o r c i M e l b a t s u d A j f o s e i r e S 1 5 9 2 P L 0 5 9 2 P L
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) LLP Package NS Package Number SDC08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 2. A critical component BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no Banned Substances as defined in CSP-9-111S2. Leadfree products are RoHS compliant. the provisions of National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Franais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2008-08-18 | 2400 ~ 2483.5 | DTS - Digital Transmission System | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2008-08-18
|
||||
1 | Applicant's complete, legal business name |
Intelligent Distributed Controls Limited
|
||||
1 | FCC Registration Number (FRN) |
0017637208
|
||||
1 | Physical Address |
Suite 6, Keynes House, Chester Park
|
||||
1 |
Derby, DE21 4AS
|
|||||
1 |
United Kingdom
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
p******@trac-trl.com
|
||||
1 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
V7O
|
||||
1 | Equipment Product Code |
ZB100
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
S******** J******** B****
|
||||
1 | Title |
Mr.
|
||||
1 | Telephone Number |
+44(0******** Extension:
|
||||
1 | Fax Number |
+44(0********
|
||||
1 |
s******@idc.gb.com
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DTS - Digital Transmission System | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | ZB100 ZigBee Module | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Single Modular Approval | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Single Modular | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
Element Materials Technology Warwick Ltd
|
||||
1 | Name |
S**** B****
|
||||
1 | Telephone Number |
01684********
|
||||
1 | Fax Number |
01684********
|
||||
1 |
s******@element.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2400.00000000 | 2483.50000000 | 0.0090000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC