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1 | Datasheet | Users Manual | 149.83 KiB |
CS8900A Product Bulletin FEATURES Single-Chip IEEE 802.3 Ethernet Controller
Maximum Current Consumption = 55 mA (5V Supply) 3 V Operation Industrial Temperature Range
Comprehensive Suite of Software Drivers Available Efficient PacketPage Architecture Operates in I/O and Memory Space and as DMA Slave
Direct Bus Interface Full Duplex Operation
On-Chip RAM Buffers Transmit and Receive Frames 10BASE-T Port with Analog Filters, Provides:
Automatic Polarity Detection and Correction
AUI Port for 10BASE2, 10BASE5, and 10BASE-F Programmable Transmit Features:
Automatic Re-transmission on Collision Automatic Padding and CRC Generation Crystal LANTM Ethernet Controller OVERVIEW The CS8900A is a true single-chip, full-duplex, Ethernet solution, incorporating all of the analog and digital circuitry needed for a complete Ethernet circuit. Major functional blocks include: a direct bus interface; an 802.3 MAC engine; integrated buffer memory; a serial EEPROM interface; and a com-
plete analog front end with both 10BASE-T and AUI. The CS8900A is a low-cost Ethernet LAN Control-
ler optimized for embedded applications and Per-
Functional Block Diagram
(cont.)
(cont.) EEPROM 20 MHz XTAL CS8900A Ethernet Controller LED Control Clock EEPROM Control RAM B u s Bus Logic Encoder/
Decoder
PLL Memory Manager 802.3 MAC Engine Boundary Scan Test Logic Power Manager 10BASE-T RX Filters &
Receiver 10BASE-T TX Filters &
Transmitter AUI Transmitter AUI Collision AUI Receiver RJ-45 10BASE-T Attachment Unit Interface
(AUI) Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7851 http://www.cirrus.com Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved) NOV 01 PI271PP2 1
CONFIDENTIAL DRAFT CS8900A Crystal LANTM Ethernet Controller FEATURES (Continued from Page 1) Programmable Receive Features:
Stream Transfer for Reduced CPU Overhead Auto-Switch Between DMA and On-Chip Memory Early Interrupts for Frame Pre-Processing Automatic Rejection of Erroneous Packets EEPROM Support for Jumperless Configuration
Boot PROM Support for Diskless Systems
Boundary Scan and Loopback Test LED Drivers for Link Status and LAN Activity Standby and Suspend Sleep Modes
All the most popular drivers are available, including:
LINUX Microsoft
NDIS 2 DOS driver
NDIS 2 OS/2 driver
NDIS 3 drivers for Windows NT, Windows for Work-
groups, Windows 95, and Windows CE
Novell
ODI DOS driver
ODI OS/2 driver
ODI Server Packet Driver (TCP/IP) pSOS
Real-time OS drivers
RIPL (Remote Initial Program Load) for ODI and NDIS 2
RTOS/NCOS (ARM and Oracle) - In development SCO Setup/installation Utility: EEPROG Utility
(EEPROM programming utility)
UNIX VxWorks NOTE: To inquire about additional drivers, see Order-
ing Information on page 3 OVERVIEW (Continued from Page 1) sonal Computers. Its highly-integrated design eliminates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T trans-
mit and receive filters, and a direct Bus interface with 24 mA Drivers. In addition to high integration, the CS8900A offers a broad range of performance features and config-
uration options. Its unique PacketPage architec-
ture automatically adapts to changing network traffic patterns and available system resources. The result is increased system efficiency. The CS8900A is available in a 100-pin TQFP package ideally suited for small form-factor, cost-sensitive Ethernet applications. With the CS8900A, system engineers can design a complete Ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space. Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-
cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-
graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com. 2 PI271PP2
CONFIDENTIAL DRAFT CS8900A Crystal LANTM Ethernet Controller Low Power and Low Noise For low power needs, the CS8900A offers three power-down options: Hardware Standby, Hard-
ware Suspend, and Software Suspend. In Standby mode, the chip is powered down with the exception of the 10BASE-T receiver, which is enabled to lis-
ten for link activity. In either Hardware or Software Suspend mode, the receiver is disabled and power consumption drops to the micro-ampere range. In addition, the CS8900A has been designed for very low noise emission, thus shortening the time required for EMI testing and qualification. Complete Support The CS8900A comes with a suite of software driv-
ers for immediate use with most industry standard network operating systems. In addition, complete evaluation kits and manufacturing packages are available, significantly reducing the cost and time required to produce new Ethernet products. Ordering Information CS8900A-CQ, 0 to 70 C, 100-pin TQFP CS8900A-IQ, -40 to 85 C, 100-pin TQFP CS8900A-CQ, 30 to 70 C, 100-pin TQFP CRD8900A-1 Evaluation Kit If you have any questions, please contact the undersigned by phone or by email. www.cirrus.com/support/ or Field Applications Engineers. OVERVIEW (cont.) Key Benefits Very Low Cost The CS8900A is designed to provide the lowest-
cost Ethernet solution available for embedded applications, portable motherboards, and adapter cards. Cost-saving features include:
Integrated RAM eliminates the need for expensive external memory chips.
On-chip 10BASE-T filters allow designers to use simple isolation transformers instead of more costly filter/transformer packages. The serial EEPROM port, used for configuration and initialization, eliminates the need for expen-
sive switches and jumpers. The CS8900A is designed to be used on a 2-layer circuit board instead of a more expensive multi-
layer board. The 8900A-based solution offers the smallest footprint available, saving valuable printed circuit board area.
A set of certified software drivers is available at no charge, eliminating the need for costly software development. High Performance The CS8900A is a full 16-bit Ethernet controller designed to provide optimal system performance by minimizing time on the bus and CPU overhead per frame. It offers equal or superior performance for less money when compared to other Ethernet controllers. The CS8900As PacketPage architec-
ture allows software to select whichever access method is best suited to each particular CPU/bus configuration. When compared to older I/O-space designs, PacketPage is faster, simpler and more efficient. To boost performance further, the CS8900A includes several key features that increase throughput and lower CPU overhead, including:
StreamTransfer cuts up to 87% of interrupts to the host CPU during large block transfers.
Auto-Switch DMA allows the CS8900A to maxi-
mize throughput while minimizing missed frames. Early interrupts allow the host to preprocess incoming frames.
On-chip buffering of full frames cuts the amount of host bandwidth needed to manage Ethernet traffic. 3 PI271PP2
CONFIDENTIAL DRAFT CS8900A Crystal LANTM Ethernet Controller 20 MHz 5 V 4.99 k, 1%
4.7 k 97 77 XTAL1 XTAL2 SLEEP 98 93 76 TEST RES CS8900A RXD-
RXD+
TXD-
TXD+
DO-
DO+
CI-
CI+
DI-
DI+
92 91 88 87 84 83 82 81 80 79 1 100 , 1%
3 68 pF 10 BASE T Isolation Transformer 1:1 1:
2 16 14 11 9 RJ45 6 3 2 1 6 7 8 24.3 , 1%
24.3 , 1%
0.1 F 15 pin D 12 V 16 15 13 12 10 9 13 10 3 9 2 12 5 4, 6 AUI Isolation Transformer 1:1 1:1 1:1 1 2 4 5 7 8 39.2 , 1%
0.1 F BSTATUS/HCI 78 LANLED 100 99 17 LINKLED CSOUT 39.2 , 1%
39.2 , 1%
39.2 , 1%
0.1 F 5 V 680 680 Boot-PROM 20 22 27C256 CE OE PD[0:7]
19 1 74LS245 OE DIR EEPROM 93C46 CS DO DI CLK 1 4 3 2 Address Decoder PAL 4 ISA BUS LA[20:23]
BALE SA[0:19]
20 IRQ10 IRQ11 IRQ12 IRQ5 DRQ5 DACK5 DRQ6 DACK6 DRQ7 DACK7 SA[0:14]
SD[0:7]
16 15 8 3 6 5 4 7 28 29 62 61 49 36 63 75 34 33 64 32 31 30 35 15 16 13 14 11 12 EECS EEDATAIN EEDATAOUT EESK CHIPSEL ELCS SA[0:19]
MEMW MEMR IOW IOR REFRESH SBHE AEN RESET MEMCS16 IOCS16 IOCHRDY SD[0:15]
INTRQ0 INTRQ1 INTRQ2 INTRQ3 DMARQ0 DMACK0 DMARQ1 DMACK1 DMARQ2 DMACK2 Figure 1 Typical Connection Diagram 4 PI271PP2
1 | Manual | Users Manual | 1.45 MiB |
. IIPPSSeerriieess BB0099115500--1122 BBaassee SSttaattiioonn PPrroodduucctt OOwwnneerrss MMaannuuaall Date Released: December 4, 2003 Document #: 516.80516.POM Version: A Copyright 2003 IPMobileNet, Inc. 16842 Von Karman Avenue, Suite 200 Irvine, CA 92606 Voice: (949) 417-4590 Fax: (949) 417-4591 The term IC: before the radio certification number only signifies that Industry of Canada technical specifications were met. Operation is subject to the following two (2) conditions: (1) this devise may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of this device. The following U.S. Patents apply to this product:
Information contained in this document is subject to change without notice. All rights reserved. Reproductions, adaptations, or translation without prior written permission is prohibited, except as allowed under copyright laws. U.S. Patent numbers 5,640,695,6,018,647,6,243,393 391500 Page ii TABLE OF CONTENTS SECTION 1: THEORY OF OPERATION .................................................................................................... 4 General Block Diagram.................................................................................................................. 4 General Block Diagram Definitions..................................................................................... 4 Input/Output ........................................................................................................... 4 System Controller................................................................................................... 4 Modems........................................................................................................... 5 Diversity Reception.......................................................................................... 5 RX Injection............................................................................................................ 5 Transmitter............................................................................................................. 5 Receiver 1/ 2/ 3...................................................................................................... 5 Power Supply......................................................................................................... 5 B09150-12 Base Station Section Descriptions ........................................................................... 6 System Controller................................................................................................................ 6 Input/Output ........................................................................................................................ 6 Modem Switching................................................................................................................ 6 Modem ............................................................................................................................... 7 Receive Signal Strength Indication Comparator................................................................. 7 Baseband............................................................................................................................ 8 Receiver Board ................................................................................................................... 8 IF Amplifier .......................................................................................................................... 8 Receiver Injection................................................................................................................ 9 Exciter Board....................................................................................................................... 9 Analog Modulation ............................................................................................................ 10 Phase Locked Loop .......................................................................................................... 10 Power Amplifier................................................................................................................. 11 SECTION 2: FCC LABEL.......................................................................................................................... 12 B09150-12 Base Station FCC Label Placement ........................................................................ 12 B09150-12 Base Station FCC Label............................................................................................ 12 APPENDIX A: B09150-12 CIRCUIT BOARD DIAGRAM.......................................................................... 13 APPENDIX B: B09150-12 TEST DATA SHEET........................................................................................ 17 391500 Page 3 SECTION 1: THEORY OF OPERATION GENERAL BLOCK DIAGRAM General Block Diagram Definitions
For increased data security, the modem supports the U.S. Government developed Digital Encryption Standard (DES) data encryption and decryption protocols. This capability requires installation of third-
party IP compliant DES encryption and decryption software. The standard IPSeries base station circuit board contains five (5) main sections defined below:
Input/Output Circuitry associated with one of the following base stations data connectors:
System Controller 391500
RS232 Serial Port DB9 Data Connector
RJ45 Ethernet 10 Base T Interface Connection Houses the modem, diversity, and Ethernet circuitry. Manages the operation of the base stations modem providing transmit timeout protection in the event a fault causes the base station to become halted in the transmit mode. The system controller also handles the loading of selected transmit and receive frequencies into the injection synthesizer. Includes memory for storage through Electrically Erasable Programmable Read Only Memory (EEPROM) of the base stations operating parameters, which are retained after the base stations power is cycled off. Page 4 Modems Diversity Reception RX Injection Transmitter Receiver 1/Receiver 2/
Receiver 3 Power Supply SECTION 1: THEORY OF OPERATION Convert data into an analog audio waveform for transmission and analog audio from the receiver to serial data interface. There is one
(1) modem that is dedicated to the transmit operation and two (2) modems dedicated to the receive operation. The modem dedicated to the transmit supports a 115.2 kbps data transmission rate on the serial port, SLIP protocol, and a 19.2 kbps or 32 kbps over-the-air data transmission rate. Provides Forward Error Correction (FEC) and Error Detection (CRC), bit interleaving for more robust data communications, and third generation collision detection and correction capabilities. Circuitry selects one of three (3) diversity receiver audio outputs for processing by the modem by comparing the Received Signal Strength Indication (RSSI) output from each receiver. Audio from the receiver with the highest RSSI value is passed to the modems. The Injection Synthesizer board provides a highly stable local oscillator signal for the three (3) receivers. This displays a serial data input/output interface, synthesizer, and VCO. Consists of an exciter and a power amplifier module covering various frequency bands in segments. A different power amplifier module is required for each segment. The transmitter power control is included with the power supply circuitry on the same board. Uses three (3) discrete receivers tuned to the same frequency. The three (3) receivers are required to support IPMobileNets base station Diversity Reception System (DRS). NOTE:
Some installations use only two (2) receivers. The receivers are double-conversion superhetrodynes with an Intermediate Frequency (IF) of 45 MHz. Each receiver consist of bandpass filters, RF amplifiers, a mixer, 45 MHz crystal filter, and a one-chip IF system. The injection synthesizer provides the first local oscillator signal and outputs from each receiver including RSSI and analog audio for Diversity Reception. Power supply circuitry derives the various operating voltages required by the base station. Fixed voltage regulators are employed through the base station for this purpose. 391500 Page 5 SECTION 1: THEORY OF OPERATION B09150-12 Base Station Section Descriptions System Controller This section displays the Central Processing Unit (CPU)(U1), clock, and power-on reset circuitry. It provides more processing power than required for future capabilities to be incorporated without changing processors. Such capabilities include data encryption/decryption (DES) and remote fault monitoring. U1 features a 16-bit address bus and 128K of internal flash random access memory (RAM). NOTE: To enter the programming mode it is necessary to reset the switch (S1) and power up again. CPU operations are controlled by Y3 an 18.432 MHz clock module. Capacitor (C1) and an internal Schmidt trigger circuit inside of U1 generates the power on reset signal. The RESET* output from U1 drives a latch and decoder found elsewhere on the board. This section displays the RAM, decoder, EEPROM, and programming power supply circuitry. U2 is a 512K x 8 bit static RAM chip, which provides temporary storage of base station configuration data while the power is on. This is necessary in order to program the base station. U2 is controlled directly by the address, data, and control busses from the CPU. Chip U5 decodes the A11-A14 address bus to provide chip selects for the modem and EEPROM memory. Chip U6 is an 8-bit latch. It latches inputs from the D0-D7 bus and lights the front panel status indicators (TX, CD, RX1, RX2, and RX3). Chip U3 is a serial EEPROM, which provides 2K bits of pre-programmed data storage for the CPU. Data is clocked out of U3 by EECLK, and back into the CPU via EEDATA. A programming power supply is required for the flash RAM inside of the CPU, and this function is performed by U4. This chip is a low dropout voltage regulator with a shutdown control. Resistors R22 and R21 set the output voltage. When the base station configuration data is to be stored in flash RAM, the CPU makes VPP_ENABLE high. This turns on the regulator, producing a 12-volt output via VPP for the flash RAM. This section displays a dedicated processor and voltage regulator. Chip U7 is a processor, which permits manual keyboard operation of the base station. Regulator VR2 provides 5 volts DC power for all logic circuitry on the System Controller Board. Input/Output This section displays the CPU input/output circuitry. Chip U8 is an RS232 transceiver, which interfaces the CPU to the modem via J1. From there, the RS232 data goes directly to a rear panel DB9 connector. U8 converts 5-volt logic-level data to +/-12 volt data in RS232C form, and vice-versa. A charge pump power supply on the chip converts the +5 volt DC power to the +/-12 volt levels required. The charge pump uses capacitors (C28 to C31) to generate voltages. NOTE: The RS232 serial port data transmission rate of the base station is 115.2 KBPS. Modem Switching This section displays the connector wiring and modem switching circuitry. Connector J7 is routed to the front-panel TX, CD, and RX1-RX3 LED indicators. The base station will also accept modulation from an external source (modem or amplified microphone audio). Transmission gate U10A switches this signal source. 391500 Page 6 Modem SECTION 1: THEORY OF OPERATION This base station uses separate modems for receive and transmit functions so that full-duplex operation may be obtained. The A0-A1 address bus in addition to the individual read (RD*), write (WR*), and chip select (MODEMTXCS*) lines control all three (3) modems. Modem operations are timed by Y2, a 4.9152 MHz clock module. Modem chip U14 is dedicated to the transmit operation. Data from the D0-D7 bus is read by the chip, and then converted to a 4-level FSK analog signal, which appears on the TXOUT pin. Op amp U21B buffers the signal, which becomes the MODEM_TXMOD output. From this point, the signal is routed to the modulation circuitry on the Exciter Board. Chip U14 has the ability to demodulate receiver audio, although this capability is not used in most systems. Incoming data-bearing audio from the Diversity Reception circuitry (and selected receiver) appears at DISC_AUDIO. The signal passes through resistor R54 and into the modem chip. Resistor R52 and capacitor C41 serve as feedback elements, limiting both the gain and bandwidth of an amplifier within U14. The modem chip demodulates the audio into 8-bits of data, which exit U14 on the D0-D7 bus. Chip U14 also provides a bias voltage for the analog circuitry on the Exciter Board. This voltage is about 2.5 volts DC, and it appears on the VBIAS line. The purpose of VBIAS is to bias the Exciter Board analog circuitry for proper operation. Please note that if this voltage is low or missing, the Exciter Board circuitry may not work. Modem chip U15 is dedicated to the receive operation. Incoming data-bearing audio from the Diversity Reception circuitry (and selected receiver) appears at DISC_ AUDIO. The signal passes through resistor R56 and into the modem chip. Resistor R55 and capacitor C46 serve as feedback elements, limiting both the gain and bandwidth of an amplifier within U15. The modem chip breaks down the audio into 8 bits of data, which exit U15 on the D0-D7 bus. Modem chip U16 is also dedicated to the receive operation, although it may not be used in this application. The operation of U16 is exactly the same as U15. Receive Signal Strength Indication Comparator This section displays the RSSI comparator circuitry. A series of comparators (U20BCD) simultaneous compare RSSI1 to RSSI2, RSSI2 to RSSI3, and RSSI1 to RSSI3. Within this process eight (8) possible results are then forwarded by the comparators to a series of NAND gates (U18ABC), which reduce the number of results to three (3) and translates the results for an analog multiplexer (U19A). To determine which of the three (3) results is the strongest, the following needs to occur:
For Receiver 1 to be selected as the strongest signal, both input pins on the NAND gate (U18D) must go high (driving pin 7 of U19A). If Receiver 1 has the strongest signal, a light emitting diode
(LED)(D1) lights indicating Receiver 1 was selected.
For Receiver 2 to be selected as the strongest signal, the inverter (U17B) must go high (driving pin 6 of U19A). If Receiver 2 has the strongest signal, D2 lights indicating Receiver 2 was selected.
For Receiver 3 to be selected the strongest signal, the inverter (U17C) must go high (driving pin 5 of U19A). If Receiver 3 has the strongest signal, D3 lights indicating Receiver 3 was selected. SEL_RSSI is the output selected with the strongest signal. When RSSI voltage exceeds a threshold, another LED (D4) lights. As the other three (3) LEDs, this circuit is intended as a diagnostic tool. It provides a go/no go indication that an RF signal has been received. A pot (R74) sets the turn-on voltage. 391500 Page 7 SECTION 1: THEORY OF OPERATION Baseband This circuitry amplifies the audio from each receiver, routes it through a RF multiplexer, and selects the audio from the receiver with the highest RSSI value. The comparator circuit on the previous sheet controls it. There are three (3) channels of audio, with separate gain and DC offset adjustments to compensate for performance differences in the receivers. For example, incoming audio from receiver 1 appears at AUDIO 1. An op amp (U12D) is then amplifies the audio. A pot (R72) adjusts the gain, while another pot
(R57) adjusts the DC offset on the output. The amplifier output passes through a RF multiplexer (U19B), then drives a low pass filter (U9) through another op amp (U12A) and through the AUDIO_OUT line, which goes to a switch (S3) and to pin 4 of a connector (J3). The remaining audio circuits work in the same manner. The output from U19B also appears on DISC_AUDIO, which goes to the CPU (U1) and from there the audio is demodulated by the modems. Receiver Board
Please be aware that the base station uses three (3) identical receiver boards. As a result, the circuitry will be described only once. Front end. Incoming signals pass through a SAW filter (FLT1). The desired signals are amplified by U2 and additional selectivity is provided by a monolithic SAW filter (FLT2). Another amplifier (U1) further amplifies the signal and the output pass through a matched pair of M Monolithic filters (FLT4 and FLT5). IF Amplifier The incoming 45 MHz signal goes to U3 a super heterodyne IF subsystem. Inside the chip, the signal is applied to a mixer. The mixer also accepts a 44.545 MHz local oscillator input. The local oscillator consists of an internal amplifier, plus crystal (Y1) and associated components. The mixer output passes through Y2, a 455 KHz ceramic IF filter. It is amplified, passed through ceramic filter (Y3), and on to a second IF stage. The IF output drives a quadrature detector. The phase shift elements for the detector are C29 and FLT3. The recovered audio appears at pin 9, while RSSI appears at pin 7. Within the RSSI circuitry, chip U3 uses a detector, which converts the AGC voltage generated inside the chip into a DC level corresponding logarithmically to signal strength. RSSI is used by Diversity Reception on the System Controller to select the receiver with the highest quality signal. A filter consisting of a resistor (R14) and a capacitor (C32) provides high frequency de-emphasis for the audio. The audio is buffered by op amp U4A. From there the AUDIO output line goes to a connector, for hookup to Diversity Reception on the System Controller Board. Resistor (R15) and capacitor (C33) provides RF filtering for the DC RSSI voltage. The RSSI is buffered by op amp U4B. From there the RSSI output line goes to a connector, for hookup to Diversity Reception on the System Controller Board.
Several sets of 455 KHz IF filters (Y2 and Y3) are available to suit receiver selectivity requirements. Should replacement of these filters be required, exact replacement parts must be used. 391500 Page 8 SECTION 1: THEORY OF OPERATION Receiver Injection This displays a serial data input/output interface, synthesizer, and VCO. The I/O interface circuitry accepts clock, serial data, and enable signals from the System Controller Board via terminal block TB1. A lock detect (LD) status output is returned to the System Controller Board from the synthesizer. U1 is a hex Schmidt Trigger inverter, which squares up incoming signals for reliable operation of the synthesizer chip. This is necessary because of a cable run between the two (2) boards. The main section of this board is synthesizer chip (U2). The device contains the key components of a phase locked loop (PLL), including a 1.1 GHz prescaler, programmable divider, and phase detector. In operation, the desired frequency is loaded into U2 as a clocked serial bit stream via the CLK and DATA/I inputs. The lock detection circuitry consists of inverters U1E/U1F, diode CR1, and resistor R4. When the synthesizer is in lock, the LD pin on U2 is high, making the LD output on terminal block TB1 high. The EXC LD input on TB1 routes the lock detect output from the Exciter Board through diode CR1, and out through LD. This configuration tells the CPU on the System Controller Board that it is acceptable to process received data, or to key the transmitter when LD is high. Otherwise, if a fault in either synthesizer prevents a lock, receive and transmit operation will be inhibited. Other items of interest include a programming switch and serial data output. Switch (JMP1) may be used to program the firmware configuration inside chip U2. The system controller board performs programming so a jumper is installed in the LNVCC (operation) position instead. The EXT DATA output on block TB1 sends frequency programming data to the transmitter synthesizer on the Exciter Board. The injection signal is generated by module U7. This device is an RF oscillator with buffered outputs. The voltage is generated by the phase detector output (PD/O) of U2, which drives a loop filter consisting of R5, C8, C5, R3 and C9. The filter integrates the pulses, which normally appear on PD/O into a smooth DC control signal for the oscillator. This section displays the DC power supplies, frequency reference, and RF output circuitry. Regulator VR1 provides 9 volts DC for U7, and RF amplifier (U6). Regulator (VR2) provides a low noise 5-volt DC output for inverter (U1), synthesizer (U2), and reference (Y1). Reference module (Y1) provides a high-stability 12 MHz reference frequency. Y1 is a voltage controlled, temperature controlled crystal oscillator (VCTCXO). This device also has a VC input which accepts a control voltage from pot R10. The pot permits a slight shift in the reference frequency which enables the three (3) receivers to be tuned precisely to the assigned receive frequency. A diode (CR2) provides additional voltage regulation, improving the frequency stability of reference Y1. The RF output circuitry consists of RF amplifier (U6), and power splitters (U5, U3, and U4). U6 increases the signal level to correct for losses in the splitters. One output drives splitter U5, which provides local oscillator injection for receivers 2 and 3. The other output drives splitter (U4), which drives receiver 1 and the PLL_FEEDBACK input on chip U2. Exciter Board This section displays the input/output interface, transmitter keying, and power supply circuitry. The input/output interface is built around terminal block (TB1) and Schmidt Trigger inverters (U2). Incoming clock, serial data, and chip select signals on block TB1 are squared up by U2. Then they are sent to the appropriate inputs on the transmitter synthesizer (U9). The EXCDATA source comes from the receive synthesizer on the Injection Synthesizer Board. A Schmidt Trigger chip is used here because of a cable ran to the System Controller Board. The synthesizer returns a lock detect output to the Injection Synthesizer Board via U1 and EXCLD. 391500 Page 9 SECTION 1: THEORY OF OPERATION A regulator (VR2) powers the T/R switch circuitry. When the System Controller Board makes TXKEY*
low, inverter U1B goes high, turning on transistor Q2 and FET Q1. This applies 5-volt power to the TXENABLE output, turning on the T/R switch on the Power Amplifier Board. At the same time, transistor Q3 conducts, grounding the KEY* input of the Power Amplifier Board. Finally, inverter U1A goes high and turns on RF switch U7, connecting the VCO output to the Power Amplifier Board for transmission. The power supply consists of two (2) voltage regulators. A regulator (VR1) provides 9-volt power for the VCO. Another regulator (U3) provides low noise 5-volt power for the logic circuitry, synthesizer chip, and analog circuitry. Analog Modulation This section displays the analog modulation circuitry. Incoming modem audio from the System Controller Board appears at TXMOD, and is buffered by op amp U4A. If an external modulation source (modem or amplified microphone) is connected to the base stations DB9 connector, audio appears at EXTMOD. From there the audio passes through low pass filter U6. The audio is inverted and amplified by an op amp (U4B). It then passes on to the VCO module via VCOMOD. Pot R18 adjusts the level to suit the VCO. The 12 MHz reference is also modulated in order to counteract the corrective effects of the synthesizer loop circuitry. For example, if only the VCO were modulated, the synthesizer would try to compensate for the frequency error, caused by the modulation. This effectively reduces the amount of modulation available. Modulating the reference and the VCO simultaneously deceives the loop into not compensating for the modulation, because when the reference frequency goes high, the VCO frequency goes high, and vice-versa. An op amp (U5B) amplifies the AUDIO output from another op amp (U4B) and applies it to jumper block JMP1. Pot R12 adjusts the gain of U5B. Op amp (U5A) inverts the phase of the audio and applies it to the other side of jumper block JMP1. The purpose of the jumper block is to select the proper phase of the audio. If the wrong phase is used, on modulation peaks the reference will swing in the same direction as the VCO, canceling out most of the modulation. The output from the jumper block goes to the 10 MHz reference via REFMOD. The VBIAS input is a 2.5-volt DC source, which biases the op amps to the correct operating point. It is generated by modem chip (U14) on the System Controller Board. Phase Locked Loop This section displays phase locked loop (PLL) circuitry. The 12-MHz reference (Y1), runs synthesizer
(U9), which in turn controls VCO VCO1. The main section of this board is the synthesizer chip (U9). The device contains the key components of a PLL, including a 1.1 GHz prescaler, programmable divider, and phase detector. In operation, the desired frequency is loaded into U9 as a clocked serial bit stream via the CLK and DATA/I inputs. The lock detection circuitry consists of inverters U1F and U1E, diode CR1, and resistor R1. When the synthesizer is in lock, the LD pin on U9 is high, making the EXCLD output on terminal block (TB1) high. The EXCLD output on TB1 routes the lock detect output from the Exciter Board. This configuration tells the CPU on the System Controller Board that it is acceptable to process received data, or to key the transmitter when LD is high. Otherwise, if a fault in either synthesizer prevents a lock, receive and transmit operation will be inhibited. The switch (JMP1) is used to select the supply voltage to chip U9. The injection signal is generated by U7. The voltage is generated by the phase detector output (PD/O) of U9, which drives a loop filter 391500 Page 10 SECTION 1: THEORY OF OPERATION consisting of R30, C45, C28, and C37. The filter integrates the pulses, which normally appear on PDOUT into a smooth DC control signal for the VCO. The output of U7 is attenuated by module AT1, resulting in improved VCO stability. Power Amplifier The transmit injection signal from the RF injection section is applied to the high-powered linear amplifier
(U1) one (1) watt amplifier. The signal is then routed to the final power amplifier boosting the output signal to 40 watts. The transmitter output power is controlled with RV2. RV2 controls the output voltage of a voltage regulator (VR1). The signal KEY* enables the regulator. The output of the amplifier is routed to transmit antenna port ANT. 391500 Page 11 B09150-12 Base Station FCC Label Placement SECTION 2: FCC LABEL LABEL B09150-12 Base Station FCC Label 391500 System Controller Receiver - Top REWORK INSTRUCTION ADD JUMPER (30 AWG INSULATED WIRE) from U19 Pin2 to VIA (RVCC) APPENDIX A: CIRCUIT BOARD DIAGRAMS J2 J3 J1 U8 Y1 C76 1 U13 100 R80 R79 C74 R50 R66 T1 R65 76 R51 C75 75 S3 S2 C77 C28 U10 TP5 S1 TP8 TP4 U4 F1 25 26 C84 16 R62 C83 50 51 C56 109 108 C8 U14 C7 R31 73 72 U15 U16 32 U2 U7 Y2 R33 U20 U19 U18 U17 8 5 C 8 8 R 9 5 C 3 8 R 2 8 R 1 8 R D7
C90 9 3 R 0 4 R 1 4 R 2 4 R 3 4 R 4 4 R 12 U6 J8 1 C89 1 J7 U21 8 7 8 8 C 9 10 VR3 J5 1 2
391500 Page 13 Receiver Bottom Receiver Injection 391500 APPENDIX A: CIRCUIT BOARD DIAGRAMS
Page 14 Exciter Top Exciter Bottom 391500 APPENDIX A: CIRCUIT BOARD DIAGRAMS
Page 15 Power Amplifier APPENDIX A: CIRCUIT BOARD DIAGRAMS
391500 Page 16 APPENDIX B: B09150-12 TEST DATA SHEET Program and Configure the Base Station Date Serial Number Firmware Revision End User Tester Adjustment / Alignment Procedures Receiver Injection Parameter Injection Frequency Error at RXINJ1(within +/- 10 Hz of exact injection frequency) P3 & C2 Measured Spec
+/- 100 Hz 5 +/- 1 dBm Receiver Diversity Reception Controller 1, 2 & 3 Parameter Spec U3 Pin 4
+10 to +5 dBm Receiver 1 Measured RSSI Test Point TP1-4 2.8 to 3.0 VDC Distortion
(1 kHz Test Tone @ 5.0 kHz) SINAD 12 dB
(1 kHz Test Tone @ 5 kHz) SINAD 12 dB TP1 SINAD +50 dB TP1 Audio AC Amplitude
(1 kHz Test Tone @ 5 kHz Deviation) Audio DC Amplitude
(1 kHz Test Tone @ 5 kHz Deviation) Carrier Detect Light Set 3%<
-119dBm >
0.75 VDC
+/- 1 mV 2.75 +/- 1 mV 350 mVRMS
+/- 1mV 2.5 VDC
+/1 1mV
-116 dBm 391500 Receiver 2 Measured Receiver 3 Measured Page 17 APPENDIX B: B09150-12 TEST DATA SHEET Spec 240>
240>
240>
Spec
+/- 500 Hz Measured Measured RF Out Max Level set to Data Quality Parameter Receiver 1 Data Quality
(x=1400, 19 Command IPMessage Utility) Receiver 2 Data Quality
(x=1400, 19 Command IPMessage Utility) Receiver 3 Data Quality
(x=1400, 19 Command IPMessage Utility) Exciter Parameter Transmit Frequency Error
(Transmitting 1400 character test message) 5.1 kHz to 5.3 kHz Transmit Modulation Deviation
(5.3 kHz while transmitting 1400 character test message) Transmit Data Quality
(While transmitting 1400 character test message to the base station) Transmit Power Control Warning: Do Not exceed 40 Watts RF output power during this test Parameter RF Out Spec 240>
40 +/- 1 Watt Output Power
(Use x=1400,19 command) Test Check List Test Task Attached copy of Base Stations Firmware Settings Visual Inspection Copy Base Station Settings Below:
Completed
() 391500 Page 18
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2004-01-23 | 163 ~ 173 | TNB - Licensed Non-Broadcast Station Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2004-01-23
|
||||
1 | Applicant's complete, legal business name |
IP Mobilenet, LLC
|
||||
1 | FCC Registration Number (FRN) |
0020033890
|
||||
1 | Physical Address |
1221 East Dyer Road
|
||||
1 |
Santa Ana, California 92705
|
|||||
1 |
United States
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
i******@ckccertification.com
|
||||
1 | TCB Scope |
B2: General Mobile Radio And Broadcast Services equipment in the following 47 CFR Parts 22 (non-cellular) 73, 74, 90, 95, 97, & 101 (all below 3 GHz)
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
MI7
|
||||
1 | Equipment Product Code |
B09150-12
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
F****** R****
|
||||
1 | Title |
President
|
||||
1 | Telephone Number |
714-4********
|
||||
1 | Fax Number |
714-4********
|
||||
1 |
f******@ipmn.com
|
|||||
app s | Technical Contact | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
M**** C******
|
||||
1 | Physical Address |
5473-A Clouds Rest
|
||||
1 |
Mariposa, California 95338
|
|||||
1 |
United States
|
|||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
209-7********
|
||||
1 |
r******@ckc.com
|
|||||
app s | Non Technical Contact | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
M**** C********
|
||||
1 | Physical Address |
5473-A Clouds Rest
|
||||
1 |
Mariposa, California 95338
|
|||||
1 |
United States
|
|||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
209-7********
|
||||
1 |
r******@ckc.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | TNB - Licensed Non-Broadcast Station Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Base Station Data Radio Transceiver | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Does not apply | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Power listed is conducted. RF exposure compliance is addressed at the time of licensing, as required by the responsible FCC Bureau(s), including antenna co-location requirements of 1.1307(b)(3) | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
S**** B****
|
||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
866-7********
|
||||
1 |
r******@ckc.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 90 | 163.00000000 | 173.00000000 | 60.0000000 | 1.8857100000 ppm | 7K6F1D |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC