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Information | Users Manual | 889.53 KiB | March 09 2002 | |||
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Manual | Users Manual | 964.73 KiB | March 09 2002 | |||
1 | Cover Letter(s) | / March 09 2002 | ||||||
1 | Block Diagram | March 09 2002 | ||||||
1 | Cover Letter(s) | native | March 09 2002 | |||||
1 | Cover Letter(s) | / March 09 2002 | ||||||
1 | External Photos | March 09 2002 | ||||||
1 | Internal Photos | March 09 2002 | ||||||
1 | ID Label/Location Info | March 09 2002 | ||||||
1 | Test Report | March 09 2002 | ||||||
1 | RF Exposure Info | August 01 2003 / March 09 2002 | ||||||
1 | RF Exposure Info | April 02 2003 / March 09 2002 | ||||||
1 | Operational Description | March 09 2002 | ||||||
1 | Cover Letter(s) | / March 09 2002 | ||||||
1 | Test Report | March 09 2002 | ||||||
1 | Test Setup Photos | March 09 2002 | ||||||
1 | Parts List/Tune Up Info | October 09 2002 / March 09 2002 |
1 | Information | Users Manual | 889.53 KiB | March 09 2002 |
MX919B 4-Level FSK Modem Data Pump PRELIMINARY INFORMATION Applications Wireless Data Terminals Two Way Paging Systems Digital Radio Systems Wide Area Wireless Data Broadcasts Point to Point Wireless Data Links COMMUNICATION SEMICONDUCTORS DATA BULLETIN Features 4-Level Root Raised Cosine FSK Modulation Half Duplex, 4800 to 19.2kbps Increase Channel Bit Rate/Hz Full Data Packet Framing Enhanced Performance in Noisy Conditions Error Detection and Error Correction Low Power 3.3V/5.0V Operation Impulse and NRZ Signal Modes RADIO MODULATOR RF ANALOG TX DISCRIMINATOR ANALOG RX MX919B MODEM DATA PUMP DATA AND CONTROL BUS HOST C SYSTEM APPLICATION PROCESSING The MX919B is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host C and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link. The MX919B assembles application data received from the host C, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter. In receive mode, the MX919B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host C. CRC detected residual uncorrected data errors will be flagged. A readout of the SNR value during receipt of a packet is also provided. The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies. The MX919B may be used with a 3.0V to 5.5V power supply and is available in the following package styles:
24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP
(MX919BP). 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump Page 2 of 47 MX919B PRELIMINARY INFORMATION CONTENTS Section Page 1. Block Diagram............................................................................................................... 6 2. Signal List...................................................................................................................... 7 3. External Components ................................................................................................... 8 4. General Description ...................................................................................................... 9 4.1 Description of Blocks ......................................................................................................... 9 4.1.1 Data Bus Buffers..................................................................................................................... 9 4.1.2 Address and R/W Decode ...................................................................................................... 9 4.1.3 Status and Data Quality Registers.......................................................................................... 9 4.1.4 Command, Mode, and Control Registers ............................................................................... 9 4.1.5 Data Buffer.............................................................................................................................. 9 4.1.6 CRC Generator/Checker ........................................................................................................ 9 4.1.7 FEC Generator/Checker ......................................................................................................... 9 4.1.8 Interleave/De-Interleave Buffer............................................................................................... 9 4.1.9 Frame Sync Detect ................................................................................................................. 9 4.1.10 Rx Input Amp ........................................................................................................................ 10 4.1.11 RRC Low Pass Filter ............................................................................................................ 10 4.1.12 Tx Output Buffer.................................................................................................................... 11 4.1.13 Rx Level/Clock Extraction..................................................................................................... 12 4.1.14 Clock Oscillator and Dividers................................................................................................ 12 4.2 Modem - C Interaction ................................................................................................... 12 4.3 Binary to Symbol Translation ........................................................................................... 13 4.4 Frame Structure............................................................................................................... 14 4.5 The Programmers View................................................................................................... 15 4.5.1 Data Block Buffer.................................................................................................................. 15 4.5.2 Command Register............................................................................................................... 15 4.5.2.1 Command Register B7: AQSC - Acquire Symbol Clock ................................................ 16 4.5.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels................................. 16 4.5.2.3 Command Register B5: CRC ........................................................................................ 16 4.5.2.4 Command Register B4: TXIMP - Tx Level/Impulse Shape............................................ 16 4.5.2.5 Command Register B3 - Reserved ................................................................................ 16 4.5.2.6 Command Register B2, B1, B0: TASK........................................................................... 16 4.5.2.7 NULL: No effect.............................................................................................................. 18 4.5.2.8 SFSH: Search for Frame Sync plus Header Block ........................................................ 18 4.5.2.9 RHB: Read Header Block............................................................................................... 18 4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block ....................................................................... 18 4.5.2.11 SFS: Search for Frame Sync ......................................................................................... 18 4.5.2.12 R4S: Read 4 Symbols .................................................................................................... 19 4.5.2.13 T24S: Transmit 24 Symbols ........................................................................................... 19 4.5.2.14 THB: Transmit Header Block.......................................................................................... 19 4.5.2.15 TIB: Transmit Intermediate Block ................................................................................... 20 4.5.2.16 TLB: Transmit Last Block ............................................................................................... 20 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. RX TX/
Page 3 of 47 4-Level FSK Modem Data Pump MX919B PRELIMINARY INFORMATION 4.5.2.17 T4S: Transmit 4 Symbols ............................................................................................... 20 4.5.2.18 RESET: Stop any current action .................................................................................... 20 4.5.2.19 Task Timing .................................................................................................................... 20 4.5.2.20 RRC Filter Delay............................................................................................................. 21 4.5.3 Control Register.................................................................................................................... 22 4.5.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio ................................................. 22 4.5.3.2 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches............. 22 4.5.3.3 Control Register B3, B2: LEVRES - Level Measurement Modes .................................. 23 4.5.3.4 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes .................. 23 4.5.4 Mode Register....................................................................................................................... 24 4.5.4.1 Mode Register B7: IRQEN - IRQ Output Enable ......................................................... 24 4.5.4.2 Mode Register B6: INVSYM - Invert Symbols................................................................ 24 4.5.4.3 Mode Register B5:
- Tx/Rx Mode ...................................................................... 24 4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye.................................................................... 25 4.5.4.5 Mode Register B3: PSAVE - Powersave........................................................................ 25 4.5.4.6 Mode Register B2, B1, B0.............................................................................................. 25 4.5.5 Status Register ..................................................................................................................... 26 4.5.5.1 Status Register B7: IRQ - Interrupt Request.................................................................. 26 4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free.................................................... 26 4.5.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty............................................... 26 4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow ....................................... 26 4.5.5.5 Status Register B3: CRCERR - CRC Checksum Error.................................................. 27 4.5.5.6 Status Register B2, B1, B0............................................................................................. 27 4.5.6 Data Quality Register............................................................................................................ 27 4.6 CRC, FEC, and Interleaving............................................................................................. 27 4.6.1 Cyclic Redundancy Codes.................................................................................................... 27 4.6.1.1 CRC1.............................................................................................................................. 27 4.6.1.2 CRC2.............................................................................................................................. 28 4.6.1.3 Forward Error Correction................................................................................................ 28 Interleaving ..................................................................................................................... 28 4.6.1.4 4.7 Transmitted Symbol Shape.............................................................................................. 28 5. Application................................................................................................................... 30 5.1 Transmit Frame Example................................................................................................. 30 5.2 Receive Frame Example.................................................................................................. 33 5.3 Clock Extraction and Level Measurement Systems.......................................................... 36 5.3.1 Supported Types of Systems................................................................................................ 36 5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect ......................................... 36 5.3.3 Clock and Level Acquisition Procedure without RF Carrier Detect ...................................... 36 5.3.4 Automatic Acquisition Functions........................................................................................... 37 5.4 AC Coupling..................................................................................................................... 37 5.5 Radio Performance.......................................................................................................... 39 5.6 Received Signal Quality Monitor ...................................................................................... 40 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 4 of 47 4-Level FSK Modem Data Pump MX919B PRELIMINARY INFORMATION 6. Performance Specification......................................................................................... 41 6.1 Electrical Performance..................................................................................................... 41 6.1.1 Absolute Maximum Ratings .................................................................................................. 41 6.1.2 Operating Limits.................................................................................................................... 41 6.1.3 Operating Characteristics ..................................................................................................... 42 6.1.3.1 Operating Characteristics Notes: ................................................................................... 42 6.1.4 Timing ................................................................................................................................... 43 6.1.5 Typical Bit Error Rate............................................................................................................ 45 6.2 Packaging........................................................................................................................ 46 MX-COM, Inc. Reserves the right to change specifications at any time and without notice 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump Page 5 of 47 Figures MX919B PRELIMINARY INFORMATION Page Figure Figure 1: Block Diagram..................................................................................................................................... 6 Figure 2: Recommended External Components ................................................................................................ 8 Figure 3: Typical Modem C connections.......................................................................................................... 9 Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode................................................. 10 Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5).................... 11 Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)............ 11 Figure 7: Over-Air Signal Format ..................................................................................................................... 14 Figure 8: Alternative Frame Structures ............................................................................................................ 15 Figure 9: Transmit Task Overlapping............................................................................................................... 17 Figure 10: Receive Task Overlapping.............................................................................................................. 17 Figure 11: Transmit Task Timing Diagram....................................................................................................... 21 Figure 12: Receive Task Timing Diagram........................................................................................................ 21 Figure 13: RRC Low Pass Filter Delay............................................................................................................. 21 Figure 14: Ideal 'RXEYE' Signal....................................................................................................................... 25 Figure 15: Typical Data Quality Reading vs S/N.............................................................................................. 27 Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1........................................................... 28 Figure 17: Tx Signal Eye TXIMP = 0................................................................................................................ 29 Figure 18: Tx Signal Eye TXIMP = 1................................................................................................................ 29 Figure 19: Transmit Frame Example Flowchart, Main Program ...................................................................... 31 Figure 20: Tx Interrupt Service Routine ........................................................................................................... 32 Figure 21: Receive Frame Example Flowchart, Main Program ........................................................................ 34 Figure 22: Rx Interrupt Service routine ............................................................................................................ 35 Figure 23: Acquisition Sequence Timing.......................................................................................................... 36 Figure 24: Effect of AC Coupling on BER (without FEC) ................................................................................. 37 Figure 25: Decay Time - AC Coupling.............................................................................................................. 38 Figure 26: Typical Connections between Radio and MX919B......................................................................... 39 Figure 27: Received Signal Quality Monitor Flowchart .................................................................................... 40 Figure 28: C Parallel Interface Timings.......................................................................................................... 44 Figure 29: Typical Bit Error Rate With and Without FEC ................................................................................. 45 Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW ................................................. 46 Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS ................................................. 46 Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH................................................. 47 Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP ..................................................... 47 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 1. Block Diagram Page 6 of 47 MX919B PRELIMINARY INFORMATION R E L L O R T N O C E C A F R E T N I IRQ D0 D1 D2 D3 D4 D5 D6 D7 WR RD CS A0 A1 VDD VDD VBIAS VSS RXAMPOUT RXIN XTAL XTAL /
CLOCK STATUS REGISTER DATA QUALITY REGISTER 8 DATA BUS BUFFERS COMMAND REGISTER MODE REGISTER CONTROL REGISTER ADDRESS AND R/W DECODE DATA BUFFER FEC ENCODER/
DECODER CRC GENERATOR/
CHECKER INTERLEAVE/
DE-INTERLEAVE FRAME SYNC DETECT Tx Symbols Rx Symbols Rx Input Amp VBIAS Tx Rx CLOCK OSCILLATOR AND DIVIDERS RRC LOW PASS FILTER VBIAS Rx LEVEL/CLOCK EXTRACTION RxEye Rx Tx Rx Tx Tx Output Buffer DOC1 DOC2 TXOUT Figure 1: Block Diagram 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 2. Signal List Signal Pin No. IRQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D7 D6 D5 D4 D3 D2 D1 D0 RD WR VSS CS A0 A1 XTAL XTAL/CLOCK DOC2 DOC1 TXOUT VBIAS RXIN RXAMPOUT VDD Page 7 of 47 MX919B PRELIMINARY INFORMATION Type output A 'wire-ORable' output for connection to the host C's Interrupt Description Request input. When active, this output has a low impedance pull down to VSS. It has high impedance when inactive. BUS BUS BUS BUS BUS BUS BUS BUS input Read. An active low logic level input used to control the reading of data Pins 2-9 (D7-D0) are 8-bit, bi-directional, 3-state C interface data lines from the modem into the host C. Input Write. An active low logic level input used to control the writing of data into the modem from the host C. power Negative supply (ground). input Chip Select. An active low logic level input to the modem used to enable a data read or write operation. Logic level modem register select input Logic level modem register select input input input output Output of the on-chip oscillator. input output Connection to the Rx level measurement circuitry. Should be Input to the on-chip oscillator, for an external Xtal circuit or clock. capacitive coupled to VSS . output Connection to the Rx level measurement circuitry. Should be capacitive coupled to VSS output Tx signal output from the modem. output A bias line for the internal circuitry held at VDD/2. This pin must be bypassed to VSS by a capacitor mounted close to the device pins. Input to the Rx input amplifier. input output Output of the Rx input amplifier. power Positive supply. Levels and voltages are dependent upon this supply. This pin should be bypassed to VSS by a capacitor mounted close to the device pins. Table 1: Signal List 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 3. External Components Page 8 of 47 MX919B PRELIMINARY INFORMATION E C A F R E T N I R E L L O R T N O C IRQ D7 D6 D5 D4 D3 D2 D1 D0 RD WR CS A0 A1 VDD C1 VDD RXAMPOUT RXIN VBIAS TXOUT DOC1 DOC2 XTAL/CLOCK XTAL A1 A0 CS 24 23 22 21 20 19 18 17 16 15 14 13 MX919B 1 2 3 4 5 6 7 8 9 10 11 12 VSS C8 R2 R1 From Rx FM Discriminator R4 To Tx Frequency Modulator C7 C6 C5 C2 17 16 XTAL/CLOCK C3 X1 R3 C4 XTAL Figure 2: Recommended External Components Component Notes Value Tolerance Component Notes Value Tolerance R1 R2 R3 R4 C1 C2 C3 3 3 100k 1M 100k 0.1F 0.1F 20%
5%
20%
5%
20%
20%
20%
C4 C5 C6 C7 C8 X1 3 4 5 5 4 20%
5%
20%
20%
5%
2,3 Table 2: Recommended External Components Recommended External Component Notes:
1. See Section 4.1.10. 2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. 3. The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values
(including stray capacitance) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable. Crystal frequency tolerances are discussed in Section 4.5.3.4. 4. Values C5 and C8 should be equal to 750,000 / symbol rate, e.g. 5. Values C6 and C7 should be equal to 50,000 / symbol rate, e.g. Symbol Rate C5 and C8 2400 symbols/second 4800 symbols/second 9600 symbols/second 330pF 150pF 82pF Symbol Rate 2400 symbols/second 4800 symbols/second 9600 symbols/second C6 and C7 0.022F 0.01F 4700pF 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 9 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4. General Description 4.1 Description of Blocks 4.1.1 Data Bus Buffers Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host C's data bus lines. 4.1.2 Address and R/W Decode This block controls the transfer of data bytes between the C and the modem's internal registers according to the state of the Write and Read Enable inputs ( WR and RD ), the Chip Select input ( SC ), and the Register Address inputs A0 and A1. The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel C interface, which can be memory-mapped, as shown in Figure 3. Data Bus Address Bus VDD IRQ pull up resistor C D0:7 A0:1 A2:7 IRQ WR RD Address Decode Circuit D0:7 A0:1 CS MODEM IRQ WR RD Figure 3: Typical Modem C connections 4.1.3 Status and Data Quality Registers Two, 8-bit registers which the C can read, to determine the status of the modem and received data quality. 4.1.4 Command, Mode, and Control Registers The values written by the C to these 8-bit registers control the operation of the modem. 4.1.5 Data Buffer A 12-byte buffer used to hold receive or transmit data to or from the C. 4.1.6 CRC Generator/Checker A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits, which may be included in the transmitted data blocks so the receive modem can detect transmission errors. 4.1.7 FEC Generator/Checker In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols to binary data, using the FEC information to correct a large proportion of transmission errors. 4.1.8 This circuit interleaves data symbols within a block before transmission and de-interleaves the received data so that the FEC system is best able to handle short noise bursts or fades. 4.1.9 Frame Sync Detect This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization pattern that is transmitted to mark the start of every frame. Interleave/De-Interleave Buffer 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 10 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4.1.10 Rx Input Amp This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x VDD voltsP-P at the RXAMPOUT pin for a received '...+3 +3 -3 -3 ...' sequence. A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.4), otherwise the DC level of the received signal should be adjusted so that the signal at the modem's RXAMPOUT pin is centered around VBIAS (VDD/2). 4.1.11 RRC Low Pass Filter This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root Raised Cosine' frequency response defined by:
1 = )f(H for
< f < 0 b-1 2T 2
-Tf b 2 sin 1 2
=)f(H 0 = )f(H for
> f b+1 2T for b-1 2T
< f <
b+1 2T Where
= b 0.2,
= T 1 symbol rate This frequency response is illustrated in Figure 5 and Figure 6. In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency components which would otherwise cause interference into adjacent radio channels. The input applied to the RRC Tx filter may be impulses or full-width symbols depending on the setting of the Command Register TXIMP bit. See Section 4.7 MX919B Bit pairs
+3
+1
-1
-3 Input Data binary to symbol Level Coded Symbols Transmit filter Frequency modulator Modem Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode In receive mode, the filter is used to reject HF noise and to equalize the received signal to a form suitable for extracting the 4-level symbols. The equalization characteristics are determined by the setting of the Command Register TXIMP bit. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 0 Page 11 of 47 MX919B PRELIMINARY INFORMATION
-5
-10 dB
-15
-20
-25
-30 0 0.1 0.2 0.3 0.4 Frequency / Bit Rate 0.5 Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5) 0
-5
-10 dB
-15
-20
-25
-30 0 0.2 0.4 0.6 0.8 Frequency / Symbol Rate 1.0 Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5) 4.1.12 Tx Output Buffer This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. In receive mode, the input of this buffer is connected to VBIAS, unless the RXEYE bit of the Control Register is '1', in which case it is connected to the received signal. When changing from Rx to Tx mode, the input to this buffer will be connected to VBIAS for 8 symbol times while the RRC filter settles. Note: The RC low pass filter formed by the external components R4 and C5 between the TXOUT pin and the input to the radio's frequency modulator forms an important part of the transmit signal filtering. These components may form part of any DC level-shifting and gain adjustment circuitry. The value used for C5 should take into account stray circuit capacitance, and its ground connection should be positioned to give maximum attenuation of high frequency noise into the modulator. The signal at the TXOUT pin is centered around VBIAS. It is approximately 0.2 x VDD voltsP-P for a continuous +3 +3 -3 -3...' pattern with TXIMP = 0. For typical Tx Eye Diagrams refer to Section 4.7, Figure 17 and Figure 18. For typical Rx Eye Diagrams refer to Section 4.5.4.4, Figure 14. A capacitor may be placed in series with the input to the frequency modulator if AC coupling is desired. See Section 5.4. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 12 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4.1.13 Rx Level/Clock Extraction These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the received signal amplitude and DC offset. This information is then used to extract the received 4-
level symbols and also to provide an input to the received Data Quality measuring circuit. The external capacitors C6 and C7 form part of the received signal level measuring circuit. The capacitors C6 and C7 are driven from a very high impedance source so any measurement of the voltages on the DOC pins must be made via high input impedance (MOS input) voltage followers to avoid disturbance of the level measurement circuits. Further details of the level and clock extraction functions are given in Section 5.3. 4.1.14 Clock Oscillator and Dividers These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference frequency which may be generated by the on-chip Xtal oscillator or applied from an external source. Note: If the on-chip Xtal oscillator is to be used, then the external components X1, C3, C4, and R3 are required. If an external clock source is to be used, then it should be connected to the XTAL/CLOCK input pin, the XTAL pin should be left unconnected, and X1, C3, C4, and R3 should not be installed. 4.2 Modem - C Interaction In general, data is transmitted over-air in the form of messages, or 'Frames', consisting of a 'Frame Preamble'
followed by one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization pattern designed to allow the receiving modem to identify the start of a frame. The following data blocks are constructed from the 'raw' data using a combination of CRC (Cyclic Redundancy Checksum) generation, Forward Error Correction coding, and Interleaving. Details of the message formats handled by the modem are provided in Section 4.4, Figure 7, and Figure 8. To reduce the processing load on the associated C, the MX919B modem has been designed to perform as much of the computationally intensive work involved in Frame formatting and de-formatting and (when in receive mode) searching for and synchronizing onto the Frame Preamble. In normal operation, the modem will only require servicing by the C once per received or transmitted block. Therefore, to transmit a block, the controlling C needs only to load the unformatted 'raw' binary data into the modem's Data Block Buffer, then instruct the modem to format and transmit that data. The modem will then calculate and add the CRC bits as required, encode the result as 4-level symbols (with Forward Error Correction coding), and interleave the symbols before transmission. In receive mode, the modem can be instructed to assemble a block's worth of received symbols, de-interleave the symbols, translate them to binary, perform Forward Error Correction, and check the resulting CRC before placing the received binary data into the Data Block Buffer for the C to read. The modem can also handle the transmission and reception of unformatted data using the T4S, T24S, and R4S tasks as described in Sections 4.3 and 4.5.2. These tasks are normally used for the transmission of Symbol and Frame Synchronization sequences. These tasks may also be used for the transmission and reception of special test patterns or special data formats. In such a case, care should be taken to ensure that the transmitted TXOUT signal contains enough level and timing information for the receiving modem's level and clock extraction circuits to function correctly. See Section 5.3. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 13 of 47 4-Level FSK Modem Data Pump 4.3 Binary to Symbol Translation Although the over-air signal, and therefore the signals at the modem TXOUT and RXIN pins, consists of 4-
level symbols, the raw data passing between the modem and the C is in binary form. Translation between binary data and the 4-level symbols is done in one of two ways, depending on the task being performed. 1. Direct way: (simplest form) - converts between 2 binary bits and a single symbol. MX919B PRELIMINARY INFORMATION SYMBOL MSB LSB
+3
+1
-1
-3 1 1 0 0 1 0 0 1 3 Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks and six bytes translates to twenty-four symbols for the T24S task described in Section 4.5.2. Bits:
Symbols:
MSB 7 6 5 4 2 1 LSB 0 a send first b c d send last 2. FEC way: (more complicated) - essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, and RILB described in Section 4.5.2. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 4.4 Frame Structure Figure 7 shows how an over-air message frame may be constructed from a sequence of: a Symbol Sync pattern (preamble), a Frame Sync pattern, and one or more 'Header', 'Intermediate' or 'Last' blocks. Page 14 of 47 MX919B PRELIMINARY INFORMATION C binary data stored in MX919B data block memory configured as header, intermediate, or last block by MX919B task being executed. Byte 0 1 2 3 4 5 6 7 8 9 10 11 Header Block 7 6 5 4 3 2 1 0 Intermediate Block 7 6 5 4 3 2 1 0 Last Block 7 6 5 4 3 2 1 0 Data Bytes
(10) Data Bytes
(12) Data Bytes
(8) CRC 1
(2 bytes) CRC2
(4 bytes) 7 Byte 0 Byte 0 70 Byte 1 0 7 Byte 11 0
'000'
tri-bits 0 1 2 3 4 5 29 30 31 32 FEC Trellis Coding / Decoding
(Error Correction) 4-Level Symbols 0 1 2 64 65 Interleaving / De-interleaving Symbol Sync Frame Sync 24 Frame Preamble Over-air signal
(symbols) Frame Sync:
'Header'
Block Intermediate Blocks 66 66 66
'Last'
Block 66 Frame
-1
+1
-1 3
-3
+3
-3
-1
+1
-3
+3
+3
-1
+1
-3
-3
+1
+3
-1
-3
+1
-1 +1 sent first Symbol Sync: at least 24 symbols of '...+3 +3 -3 -3 ...' sequence Figure 7: Over-Air Signal Format
+3 last The 'Header' block is self-contained and includes its own checksum (CRC1). It would normally carry information such as the address of the calling and called parties, the number of following blocks in the frame
(if any), and miscellaneous control information. The number of following blocks (if any) is required to allow the Rx device software to expect the Last Block and interpret it as a Last Block rather than an Intermediate Block. There is no other indicator to differentiate a Last Block and an Intermediate Block. The 'Intermediate' block(s) contain only data, the checksum for all of the data in the 'Intermediate' and 'Last'
blocks (CRC2) being contained at the end of the 'Last' block. This arrangement, while efficient in terms of data capacity, may not be optimum for poor signal-to-noise conditions, since a reception error in any one of the 'Intermediate' or 'Last' blocks would invalidate the whole frame. In such conditions, increased throughput may be obtained by using the 'Header' block format for all blocks of the frame, so blocks that are received correctly can be identified as such, and do not need to be re-
transmitted. These, and some other possible frame structures, are shown in Figure 8. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump A B C SYMBOL SYNC FRAME SYNC SYMBOL SYNC FRAME SYNC SYMBOL SYNC FRAME SYNC Page 15 of 47 MX919B PRELIMINARY INFORMATION
'HEADER' BLOCKS
'INTERMEDIATE' BLOCKS
'LAST'
BLOCK
'INTERMEDIATE' BLOCKS Figure 8: Alternative Frame Structures The MX919B performs the entire block formatting and de-formatting required to convert data between C binary form and Over-Air as shown in Figure 7. 4.5 The Programmers View To the programmer, the modem appears as 4 write only 8-bit registers, shadowed by 3 read only registers. The individual registers are selected by the A0 and A1 chip inputs:
Write to Modem Read from Modem A1 A0 0 0 1 1 0 Data Buffer 1 Command Register 0 Control Register 1 Mode Register Data Buffer Status Register Data Quality Register Not used Note: There is a minimum time allowance between accesses of the modem's registers, see Section 6.1.4. 4.5.1 Data Block Buffer This is a 12-byte read/write buffer used to transfer data (as opposed to command, status, mode, data quality or control information) between the modem and the host C. To the C, the Data Block Buffer appears as a single 8-bit register. The modem ensures that sequential C reads or writes to the buffer are routed to the correct locations within the buffer. The C should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'. The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive mode, the modem will function correctly even if the received data is not read from the Data Buffer by the C. 4.5.2 Command Register Writing to this register tells the modem to perform a specific task as indicated by the TASK bits and modified by the AQSC, AQLEV, CRC, and TXIMP bits. Command Register 4 5 7 6 3 2 1 0 AQSC AQLEV CRC TXIMP Reserved Set to '0'
TASK When there is no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode, the input to the Tx RRC filter will be connected to VBIAS. In receive mode, the modem will continue to measure the received data quality and extract symbols from the received signal, supplying them to the de-interleave buffer, otherwise these received symbols are ignored. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. MX919B PRELIMINARY INFORMATION Page 16 of 47 4-Level FSK Modem Data Pump 4.5.2.1 Command Register B7: AQSC - Acquire Symbol Clock This bit has no effect in transmit mode. In receive mode, when a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register. Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-
started every time a byte written to the Command Register has the AQSC bit set to '1'. The use of the symbol clock acquisition sequence is described in Section 5.3. 4.5.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels This bit has no effect in transmit mode. In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is not set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond quickly at first, then gradually increasing their response time, therefore improving the measurement accuracy, until the 'normal' value set by the LEVRES bits of the Control Register is reached. Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-
started every time a byte written to the Command Register has the AQLEV bit set to '1'. The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3. 4.5.2.3 Command Register B5: CRC This bit allows the user to select between two different initial states of the CRC1 and CRC2 checksum generators. When this bit is set to 0, the CRC generators are initialized to all ones as for CCITT X25 CRC calculations. When this bit is set to 1, the CRC generators are initialized to all zeros. Setting this bit to 0 provides compatibility with the MX919, a prior member of the MX919 device family. Other systems may set this bit as required. Note: This bit must be set correctly every time the Command Register is written to. 4.5.2.4 Command Register B4: TXIMP - Tx Level/Impulse Shape This bit allows the user to choose between two transmit symbol waveform shapes as described in Section 4.7. Note: This bit must be set correctly every time the Command Register is written to. 4.5.2.5 Command Register B3 - Reserved This bit should always be set to '0'. 4.5.2.6 Command Register B2, B1, B0: TASK Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated when the C writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL' code. The C should not write a task (other than NULL or RESET) to the Command Register or write to or read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'. Different tasks apply in receive and transmit modes. When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit data from the Data Buffer, formatting it as required. The C should therefore wait until the BFREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte number 0 of the block should be written first. Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'. Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave Buffer. Once all of the data has been transferred from the Data Block Buffer, the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the chip IRQ output to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the C that it may write new data and the next task to the modem. This lets the C write the next task and its associated data to the modem while the modem is still transmitting the data from its previous task. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 4-Level FSK Modem Data Pump Page 17 of 47 MX919B PRELIMINARY INFORMATION Data from C to Block Buffer Task from C to Command Register Task 1 data Task 2 data BFREE Bit of Status Register IRQ Bit of Status Register IRQ Output (IRQEN = '1') TXOUT Signal from Task 1 from Task 2 Figure 9: Transmit Task Overlapping Set the BFREE bit of the Status Register to '0'. When the modem is in receive mode, the C should wait until the BFREE bit of the Status Register is '1', then write the desired task to the Command Register. Once the byte containing the desired task has been written to the Command Register, the modem will:
Wait until enough received symbols are in the De-interleave Buffer. Decode them as needed and transfer the resulting binary data to the Data Block Buffer Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the IRQ output to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the C that it may read from the Data Block Buffer and write the next task to the modem. If more than 1 byte is contained in the buffer, byte number 0 of the data will be read out first. In this way, the C can read data and write a new task to the modem while the received symbols needed for this new task are being received and stored in the De-interleave Buffer. RXIN Signal for Task 1 for Task 2 IRQ Output (IRQEN = '1') IRQ Bit of Status Register BFREE Bit of Status Register Task from C to Command Register Data from Block Buffer to C Task 1 Task 2 Task 1 data Detailed timings for the various tasks are provide in Figure 11 and Figure 12. Figure 10: Receive Task Overlapping 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 18 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump MX919B Modem Tasks:
B2 B1 B0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 Receive Mode NULL SFSH Search for FS + Header RHB Read Header Block RILB Read Intermediate or Last Block SFS Search for Frame sync R4S Read 4 symbols NULL Transmit Mode NULL T24S Transmit 24 symbols THB Transmit Header Block TIB Transmit Intermediate Block TLB Transmit Last Block T4S Transmit 4 symbols NULL RESET Cancel any current action RESET Cancel any current action 4.5.2.7 NULL: No effect This 'task' is provided so an AQSC or AQLEV command can be initiated without loading a new task. 4.5.2.8 SFSH: Search for Frame Sync plus Header Block This task causes the modem to search the received signal for a valid 24-symbol Frame Sync sequence followed by Header Block which has a correct CRC1 checksum. The task continues until a valid Frame Sync plus Header Block has been found. The search consists of two stages:
First the modem will attempt to match the incoming symbols against the 24-symbol Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Control Register. Once a match has been found, the modem will read in the next 66 symbols as if they were a 'Header'
block, decoding the symbols and checking the CRC1 checksum. If this is incorrect, the modem will resume the search, looking for a fresh Frame Sync pattern. If the received CRC1 is correct, the 10 decoded data bytes will be placed into the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1' and the CRCERR bit cleared to '0'. Once detecting that the BFREE bit of the Status Register has gone to '1', the C should read the 10 bytes from the Data Block Buffer and then write the next task to the modem's Command Register. 4.5.2.9 RHB: Read Header Block This task causes the modem to read the next 66 symbols as a 'Header' Block, decoding them, placing the resulting 10 data bytes and the 2 received CRC1 bytes into the Data Block Buffer, and setting the BFREE and IRQ bits of the Status Register to '1'. When the task is complete, it indicates that the C may read the data from the Data Block Buffer and write the next task to the modem's Command Register. The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1 checksum bytes. 4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block This task causes the modem to read the next 66 symbols as an 'Intermediate' or 'Last' block (the C should be able to tell from the 'Header' block how many blocks are in the frame and when to expect the 'Last' block). In each case, it will decode the 66 symbols and place the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register to '1' when the task is complete. If an 'Intermediate' block is received, then the C should read out all 12 bytes from the Data Block Buffer and ignore the CRCERR bit of the Status Register, for a 'Last' block the C need only read the first 8 bytes from the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2 checksum. 4.5.2.11 SFS: Search for Frame Sync This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Mode Register. When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' to indicate to the C that it should write the next task to the Command Register. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 19 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4.5.2.12 R4S: Read 4 Symbols This task causes the modem to read the next 4 symbols and translate them directly (without de-interleaving or FEC) to an 8-bit byte which is placed into the Data Block Buffer. The BFREE and IRQ bits of the Status Register are then set to '1' to indicate that the C may read the data byte from the Data Block Buffer and write the next task to the Command Register. This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task. Note: It is possible to construct message formats, which do not rely on the block formatting of the THB, TIB, and TLB tasks. This can be accomplished by using T4S or T24S tasks to transmit and R4S to receive the user's data. One should be aware, that the receive level and timing measurement circuits need to see a reasonably 'random' distribution of all four possible symbols in the received signal to operate correctly. Accordingly, binary data may benefit from scrambling before transmission if it is not reasonably 'random' to start with. 4.5.2.13 T24S: Transmit 24 Symbols This task, which is intended to facilitate the transmission of Symbol and Frame Sync patterns as well as special test sequences, takes 6 bytes of data from the Data Block Buffer and transmits them as 24 4-level symbols without any CRC or FEC. Byte 0 of the Data Block Buffer is sent first, byte 5 last. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1', indicating to the C that it may write the data and command byte for the next task to the modem. The tables below show what data needs to be written to the Data Block Buffer to transmit the MX919B Symbol and Frame Sync sequences:
Symbol Sync Values written to Data Block Buffer Symbols
-3
+3
+3
-3
-3
+3
-3
+3
+3
-3
-3
+3 Byte 0:
Byte 1:
Byte 2:
Byte 3:
Byte 4:
Byte 5:
Binary 11110101 11110101 11110101 11110101 11110101 11110101
-3
-3
-3
-3
-3
-3 Hex F5 F5 F5 F5 F5 F5 Frame Sync Values written to Data Block Buffer Symbols
+1
-1
+1
+3
-3
+3
-3
-1
+1
-1
+3
+1
+1 +3
-3
-3
+1 +3 Binary Byte 0:
Byte 1:
Byte 2:
Byte 3:
Byte 4:
Byte 5:
00100010 00110111 01001001 11110010 01011011 00011011 Hex 22 37 49 F2 5B 1B
+3
+3
+3
+3
+3
+3
-1
-1
-3
+3
-3
-1 4.5.2.14 THB: Transmit Header Block This task takes 10 bytes of data (Address and Control) from the Data Block Buffer, calculates and appends the 2-byte CRC1 checksum, translates the result to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Header' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 20 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4.5.2.15 TIB: Transmit Intermediate Block This task takes 12 bytes of data from the Data Block Buffer, updates the 4-byte CRC2 checksum for inclusion in the 'Last' block, translates the 12 data bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Intermediate' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. 4.5.2.16 TLB: Transmit Last Block This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CRC2 checksum, translates the resulting 12 bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Last' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'. 4.5.2.17 T4S: Transmit 4 Symbols This command is similar to T24S but takes only one byte from the Data Block Buffer, transmitting it as four 4-
level symbols. 4.5.2.18 RESET: Stop any current action This 'task' takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should be used when VDD is applied, to set the modem into a known state. Note: Due to delays in the transmit filter, it will take several symbol times for any change to appear at the TXOUT pin. 4.5.2.19 Task Timing The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation. t1 Modem Idle state. Time from writing first task to application of first transmit bit to Tx RRC filter. Any t2 Time from application of first symbol of the task to the Tx RRC filter until BFREE goes to a logic 1. t3 Time to transmit all symbols of the task. t4 Max time allowed from BFREE going to a logic 1 (high) for next task
(and data) to be written to modem. t5 Time to receive all symbols of task. t6 Maximum time between first symbol of task entering the de-interleave circuit and the task being written to modem. t7 Maximum time from the last bit of the task entering the de-interleave circuit to BFREE going to a logic 1 (high). T24S THB/TIB/TLB T4S T24S THB/TIB/TLB T4S T24S THB/TIB/TLB T4S SFS SFSH RHB/RILB R4S SFS SFSH RHB/RILB R4S Any 5 16 0 24 66 4 18 49 3 24 (minimum) 90 (minimum) 66 4 21 21 49 3 1 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Task Time
(symbol times) 1 to 2 4-Level FSK Modem Data Pump Page 21 of 47 MX919B PRELIMINARY INFORMATION Data to Data Block Buffer 1 Task to Command Register 1 2 2 t4 3 t4 3 t4 IBEMPTY Bit BFREE Bit t2 t3 t2 t3 t2 t3 t1 Symbols to RRC Filter from Task 1 from Task 2 from Task 3 Modem Tx Output Modem Rx Input Symbols to De-Interleave Circuit Data from Data Block Buffer Task to Command Register BFREE Bit Figure 11: Transmit Task Timing Diagram for Task 1 for Task 2 for Task 3 t5t5 1 t6 t5 1 t5 2 3 t6 2 t6 3 t7 t7 t7 Figure 12: Receive Task Timing Diagram 4.5.2.20 RRC Filter Delay The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through to the RRC filter in both transmit and receive modes, as illustrated below:
Delay from Tx Input symbol to TXOUT response. Tx Symbol to RRC Filter Delay from Rx Input
(from FM discriminator) to interpreted data in internal buffer. Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator RX Symbol to De-Interleave Buffer Symbol-times Figure 13: RRC Low Pass Filter Delay 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 4.5.3 Control Register This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock extraction, signal level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact matches. Page 22 of 47 MX919B PRELIMINARY INFORMATION Control Register 5 7 6 4 3 2 1 0 CKDIV FSTOL LEVRES PLLBW 4.5.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore determining the nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol rates. The table below shows how symbol rates of 2400/4800/9600 symbols/sec (4800/9600/19200bps) may be obtained from common Xtal frequencies:
B7 B6 0 0 1 0 0 1 1 1 Division Ratio:
Xtal Frequency/Symbol Rate 512 1024 2048 4096 Xtal Frequency (MHz) 2.4576 Symbol Rate (symbols/sec) / Bit Rate 4.9152 9.8304
(bps) 4800/9600 2400/4800 9600/19200 4800/9600 2400/4800 9600/19200 4800/9600 2400/4800 4.5.3.2 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches These two bits have no effect in transmit mode. In receive mode, they define the maximum number of mismatches allowed during a search for the Frame Sync pattern:
B5 B4 Mismatches allowed 0 0 1 1 0 2 4 6 0 1 0 1 Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol
'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for normal use. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 23 of 47 4-Level FSK Modem Data Pump 4.5.3.3 Control Register B3, B2: LEVRES - Level Measurement Modes These two bits have no effect in transmit mode. In receive mode they set the 'normal' or 'steady state'
operating mode of the Rx signal amplitude and DC offset measuring and tracking circuits. These circuits analyze the Rx signal envelope and charge the DOC1 and DOC2 capacitors to 'store' signal maximum and minimum references that are used in the data reception process. This setting is temporarily overridden during the automatic sequencing triggered by an AQLEV command when level is initially being acquired as described in Section 5.3. MX919B PRELIMINARY INFORMATION B3 B2 0 0 1 0 1 0 1 1 Mode Hold Level Track Lossy Peak Detect Slow Peak Detect In normal use the LEVRES bits should be set to '0 1' (Level Track). The other modes are intended for special purposes, for device testing, or are invoked automatically during an AQLEV sequence. In 'Slow Peak Detect' modes, the positive and negative excursions of the received signal (after filtering) are measured by peak rectifiers driving the DOC1 and DOC2 capacitors to establish the amplitude of the signal and any DC offset with regards to VBIAS. This mode provides good overall performance, particularly when acquiring level information at the start of a received message, but does not work as well with certain long sequences of repeated data byte values. It is also susceptible to large amplitude noise spikes, which can be caused by deep fades. The 'Lossy Peak Detect' mode is similar to 'Slow Peak Detect' but the capacitor discharge time constant is much shorter so this mode is not suitable for normal data reception and is only used within part of the automatic AQLEV acquisition sequence. In 'Level Track' mode the DOC capacitor voltages are slowly adjusted by the MX919B in such a way as to minimize the average errors seen in the received signal. This mode provides the best overall performance, being much more accurate than 'Slow Peak Detect' when receiving large amplitude noise spikes on long sequences of repeated data byte values. It does, however, depend on the measured levels and timing being approximately correct. If either of these is significantly wrong then the correction algorithm used by the 'Level Track' mode can actually drive the voltages on the DOC capacitors away from their optimum levels. For this reason, the automatic AQLEV acquisition sequence (see Section 5.3) forces the level measuring circuits into
'Slow Peak Detect' mode until a Frame Sync pattern has been found. 4.5.3.4 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes These two bits have no effect in transmit mode. In receive mode, they set the 'normal' or 'steady state'
bandwidth of the Rx clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itself with the Rx Signal to develop a local clock signal used in the data clock recovery process. This setting will be temporarily overridden during the automatic sequencing of an AQSC command when Rx clock extraction circuits are initially being trained as described in Section 5.3. B1 B0 0 0 1 0 1 0 1 1 PLL Mode Hold Level Track Lossy Peak Detect Slow Peak Detect The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the frequency of the receiving modem's crystal are both within 100ppm of nominal, except at the start of a symbol clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in Section 5.3 If the received symbol rate and the crystal frequency are both within 20ppm of nominal then selection of the
'Narrow Bandwidth' setting will provide better performance especially through fades or noise bursts which may otherwise pull the PLL away from its optimum timing. In this case however; it is recommended that the PLLBW bits only be set to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth'
mode for about 200 symbol times to ensure accurate lock has first been achieved. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 24 of 47 4-Level FSK Modem Data Pump The 'Hold' setting disables the feedback loop of the PLL which continues to run at a rate determined only by the actual crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating frequency immediately prior to the 'Hold' setting. 4.5.4 Mode Register The contents of this 8-bit write only register control the basic operating modes of the modem:
MX919B PRELIMINARY INFORMATION Mode Register 5 7 6 4 3 2 1 0 IRQEN INVSYM Tx/Rx RXEYE PSAVE Set to '000'
4.5.4.1 Mode Register B7: IRQEN - IRQ Output Enable When this bit is set to '1', the IRQ chip output pin is pulled low (VSS) given the IRQ bit of the Status Register is a '1'. 4.5.4.2 Mode Register B6: INVSYM - Invert Symbols This bit controls the polarity of the transmitted and received symbol voltages. B6 Symbol Signal at TXOUT Signal at RXAMPOUT 0 1
+3
-3
+3
-3 Above VBIAS Below VBIAS Below VBIAS Above VBIAS Below VBIAS Above VBIAS Above VBIAS Below VBIAS Note: B6 must be normally set to the same value in Tx and Rx devices for successful operation. 4.5.4.3 Mode Register B5:
Setting this bit to '1' places the modem into the Transmit mode, clearing it to '0' puts the modem into the Receive mode. Note: Changing between receive and transmit modes will cancel any current task.
- Tx/Rx Mode TX/
RX 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 25 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the modem for a special test mode, in which the input of the Tx output buffer is connected to the Rx Symbol/Clock extraction circuit at a point which carries the equalized receive signal. This may be monitored with an oscilloscope (at the TXOUT pin itself), to assess the quality of the complete radio channel including the Tx and Rx modem filters, the Tx modulator and the Rx IF filters, and FM demodulator. This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered signal (before Rx equalization) is not very recognizable so it is generally not useful. The resulting eye diagram (for reasonably random data) should ideally be as shown in the following Figure 14, with 4 distinct and equally spaced level crossing points. Figure 14: Ideal 'RXEYE' Signal Note: A two-channel oscilloscope is needed for this testing. One channel of the oscilloscope should be placed on the signal path of interest, such as the Tx output. If the Rx eye diagram is to be viewed, set the RXEYE bit in the Mode Register to 1 and connect the oscilloscope probe downstream of the external RC filter on the TXOUT pin. (This Mode Register bit causes the MX919B to enter a special test mode whereby the Rx output is placed on the TXOUT pin. This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered signal is not very recognizable and is generally not useful.) The other oscilloscope channel should be used for triggering and should ideally be placed on the transmitting MX919B IRQ pin. This will allow the triggering to be synchronized with the completion of each transmitted data word. If this triggering location is not practical, use the receiving MX919B IRQ signal for triggering. The falling edge of the IRQ line should be used for triggering. The data stream used for this testing should have a reasonably random structure. 4.5.4.5 Mode Register B3: PSAVE - Powersave When this bit is a 1, the modem will be in a powersave mode in which the internal filters, the Rx Symbol and Clock extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to VBIAS through a high value internal resistance. The Xtal clock oscillator, Rx input amplifier and the C interface logic will continue to operate. Setting the PSAVE bit to 0 restores power to all of the chip circuitry. Note: The internal filters, and therefore the TXOUT pin in transmit mode, will take approximately 20 symbol-
times to settle after the PSAVE bit has gone from 1 to 0. 4.5.4.6 Mode Register B2, B1, B0 These bits should be set to '000'. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 4.5.5 Status Register This register may be read by the C to determine the current state of the modem. Page 26 of 47 MX919B PRELIMINARY INFORMATION Status Register 5 7 6 4 3 2 1 0 IRQ BFREE DIBOVF IBEMPTY CRCERR Reserved 4.5.5.1 Status Register B7: IRQ - Interrupt Request This bit is set to '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a change to the Mode Register TX RX/
or PSAVE bits or The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by changing the Mode Register TX RX/
or PSAVE bits. or The Status Register DIBOVF bit going from '0' to '1'. The IRQ bit is cleared to '0' immediately after a read of the Status Register. If the IRQEN bit of the Mode Register is '1', then the chip IRQ output will be pulled low (VSS) when the IRQ bit is set to '1', and will go high impedance when the Status Register is read. 4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free This bit reflects the availability of the Data Block Buffer and is cleared to '0' when a task other than NULL or RESET is written to the Command Register. In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem when the modem is ready for the C to write new data to the Data Block Buffer and the next task to the Command Register. In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem when it has completed a task and any data associated with that task has been placed into the Data Block Buffer. The C may then read that data and write the next task to the Command Register. The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register TX RX/
4.5.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap in the transmit output signal. The bit is also set to '1' by a RESET task or by a change of the Mode Register TX RX/
these cases the IRQ bit will not be set. The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the Command Register. Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level (halfway between or PSAVE bits are changed. or PSAVE bits, but in
'+1' and '-1') signal will be sent to the RRC filter. In receive mode this bit will be '0'. 4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB or R4S task is written to the Command Register too late to allow continuous reception. The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the Command Register or by changing the TX RX/
In transmit mode this bit will be '0'. or PSAVE bits of the Mode Register. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. MX919B PRELIMINARY INFORMATION Page 27 of 47 4-Level FSK Modem Data Pump 4.5.5.5 Status Register B3: CRCERR - CRC Checksum Error In receive mode, this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error. Note: This bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is received. The bit is cleared to '0' by a RESET task or by changing the TX RX/
transmit mode this bit is '0'. 4.5.5.6 Status Register B2, B1, B0 These bits are reserved for future use. 4.5.6 Data Quality Register In receive mode, the MX919B continually measures the 'quality' of the received signal, by comparing the actual received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level FSK baseband signal. The result is placed into bits 3-7 of the Data Quality Register for the C to read at any time, bits 0-2 being always set to '0'. Figure 15 shows how the value (0-255) read from the Data Quality Register varies with received signal-to-noise ratio:
, or PSAVE bits of the Mode Register. In 250 200 150 DQ 100 50 0 5 7 9 11 13 S/N dB (noise in 2 x symbol-rate bandwidth) 15 Figure 15: Typical Data Quality Reading vs S/N The Data Quality readings are only valid when the modem has successfully acquired signal level and timing lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to
'Wide' or if the received signal waveform is distorted in any significant way. Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system performance in some applications. 4.6 CRC, FEC, and Interleaving 4.6.1 Cyclic Redundancy Codes 4.6.1.1 CRC1 This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block, which provides error detection coverage for the Header Block of a message. It is calculated by the modem from the first 80 bits of the Header Block (Bytes 0 to 9 inclusive) using the generator polynomial:
x16 + x12 + x5 + 1 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 4.6.1.2 CRC2 This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block, which provides error detection coverage for the combined Intermediate Blocks and Last Block of a message. It is calculated by the modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block using the generator polynomial:
MX919B PRELIMINARY INFORMATION Page 28 of 47 x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 Note: In receive mode the CRC2 checksum circuits are initialized on completion of any task other than NULL or RILB. In transmit mode the CRC2 checksum circuits are initialized on completion of any task other than NULL, TIB, or TLB. Command Register bit B5 (CRC) allows the user to select between two different forms of the CRC1 and CRC2 checksums. When this bit is set to '0', the CRC generators are initialized to 'all ones' for calculations such as CCITT X25 CRC. When this bit is set to '1', the CRC generators are initialized to
'all zeros'. Interleaving 4.6.1.3 Forward Error Correction In transmit mode, the MX919B uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header',
'Intermediate' or 'Last' Block into a 66-symbol (132 bits) sequence which includes FEC information. In receive mode, the MX919B decodes the received 66 symbols of a block into 96 bits of binary data using a
'Soft Decision' Viterbi algorithm to perform decoding and error correction. 4.6.1.4 The 66 symbols of a 'Header', 'Intermediate' or 'Last' block are interleaved by the modem before transmission to provide protection against the effects of noise bursts and short fades. In receive mode, the MX919B de-interleaves the received symbols prior to decoding. 4.7 Transmitted Symbol Shape Bit 4 of the Command Register (TXIMP) selects the transmit baseband signal and the receive signal equalization as follows:
If the TXIMP bit is '0', then the transmit baseband signal is generated by feeding full-symbol-time-width 4-level symbols into the RRC lowpass filter. The receive signal equalization is optimized for this type of signal. With this setting, the MX919B is compatible with the MX919A devices, another member of the MX919 device family. If the TXIMP bit is set to '1,' impulses, rather than full-symbol-time-width symbols are fed into the RRC filter when in TX mode, and the receive signal equalization is suitably adjusted in RX mode. TXIMP = 0 TXIMP = 1
+3
+1
-1
-3
+3
+1
-1
-3 1 symbol time 1 symbol time Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump Page 29 of 47 MX919B PRELIMINARY INFORMATION Figure 17: Tx Signal Eye TXIMP = 0 Figure 18: Tx Signal Eye TXIMP = 1 Note: Setting TXIMP to '1' affects the Tx output signal level as shown in Section 6.1.3 and the table below. Nominal Voltage difference between continuous +3 and continuous -3 symbol outputs Nominal VP-P for continuous +3+3-3-3 symbol pattern. TXIMP = 0 0.157VDD TXIMP = 1 0.157VDD 0.20VDD 0.22VDD 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 30 of 47 4-Level FSK Modem Data Pump 5. Application 5.1 Transmit Frame Example The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are provided below:
1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQEN and MX919B PRELIMINARY INFORMATION bits of the Mode Register are '1', the RXEYE and PSAVE bits are '0', and the INVSYM bit is set TX RX/
appropriately. 2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes (a preamble) to the Data Block Buffer and a T24S task to the Command Register. 3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'. 4. Write 6 byte Frame Sync to the Data Block Buffer and a T24S task to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'. 6. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register. 7. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'. 8. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register. 9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'. 10. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the IBEMPTY bit should be '0'. 12. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits should be '1'. Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely through the RRC filter. Figure 19 and Figure 20 illustrate the host C routines needed to send a single Frame consisting of Symbol and Frame Sync patterns, a Header block, and any number of Intermediate blocks and one Last Block. It is assumed that the Tx Interrupt Service Routine Figure 20 is called when the MX919B IRQ output line goes low. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump START Page 31 of 47 MX919B PRELIMINARY INFORMATION Ensure that the Control Register has been loaded with a suitable CKDIV value Ensure that the Mode Register IRQEN, PSAVE and RXEYE bits are '0', the TX/RX bit is '1', and the INVSYM bit is set appropriately Write a RESET task to the Command Register Read the Status Register BFREE bit = 1 ?
Yes No Set C variable 'IBLOCKS'
to the number of Intermediate blocks to be transmitted Set C variable 'STATE' to 0 Set the Mode Register IRQEN bit to '1'
Enable C's MX919B Tx Interrupt Service Routine Write 6 bytes of Symbol Sync pattern to the Data Buffer Write a T24S task to the Command Register Note: during this time the C may perform other functions, as the C variable 'STATE' is updated by the interrupt service routine Yes
'STATE' < 5 ?
No Disable C's MX919B Tx Interrupt Service Routine Set the Mode Register IRQEN bit to '0'
END with error No
'STATE' = 5 ?
Yes END Figure 19: Transmit Frame Example Flowchart, Main Program Notes 1. The RESET command in Figure 19 and the practice of disabling the MX919Bs IRQ output when not needed are not essential but can eliminate problems during debugging and if errors occur in operation 2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command Register. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump Page 32 of 47 MX919B PRELIMINARY INFORMATION RETURN
( Not MX919B IRQ ) START line goes low )
IRQ Read Status Register Value of C variable 'STATE' on entry to IRQ routine and corresponding MX919B's actions:
0: Symbol Sync pattern being transmitted, load Frame Sync pattern & T24S task. 1: Frame Sync pattern being transmitted, load Header Block bytes and THB task. 2: Header or Intermmediate Block being transmitted, load Intermediate or Last Block bytes & TIB or TLB task. 3: Last block being transmitted, ignore this interrupt. No IRQ bit = 1 ?
4: Waiting for end of transmission, finish on interrupt with IBEMPTY bit set. Yes No E BFREE bit = 1 ?
Yes
'STATE' = 4 ?
Yes No E No IBEMPTY bit = 1 ?
Yes Yes E IBEMPTY bit = 1 ?
E No
'STATE' = 0 ?
Set C variable 'STATE' to 9 No RETURN
( Error )
'STATE' = 1 ?
No
'STATE' = 2 ?
Yes Write 6 byte Frame Sync pattern to the Data Buffer then write a T24S task to the Command Register Write 10 Header Block data bytes to the Data Buffer then write a THB task to the Command Register Yes Yes No E No
'STATE' = 3 ?
Yes Write 12 Intermediate Block data bytes to the Data Buffer then write a TIB task to the Command Register No
'IBLOCKS' = 0 ?
Yes Write 8 Last Block data bytes to the Data Buffer then write a TLB task to the Command Register Decrement C variable
'IBLOCKS'
RETURN Increment C variable
'STATE'
RETURN Figure 20: Tx Interrupt Service Routine 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 33 of 47 4-Level FSK Modem Data Pump 5.2 Receive Frame Example The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one each Header, Intermediate and Last blocks are shown below;
1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW PSAVE, and RXEYE bits are '0', values, and that the IRQEN bit of the Mode Register is '1', the TX RX/
and the INVSYM bit is set appropriately. MX919B PRELIMINARY INFORMATION 2. Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3). 3. Read the Status Register to ensure that the BFREE bit is '1'. 4. Write a byte containing a SFSH task and with the AQSC and AQLEV bits set to '1' to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the CRCERR and DIBOVF bits should be '0'. 6. Check that the CRCERR bit of the Status Register is '0' and read 10 Header Block bytes from the Data Block Buffer. 7. Write a RILB task to the Command Register. 8. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the DIBOVF bit '0'. 9. Read 12 Intermediate Block bytes from the Data Block Buffer. 10. Write a RILB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'
and the DIBOVF bit '0'. 12. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from Data Buffer. Figure 21 and Figure 22 illustrate the host C routines needed to receive a single Frame consisting of Symbol and Frame Sync patterns, a Header Block, any number of Intermediate blocks and one Last block. It is assumed that the Rx Interrupt Service Routine Figure 22 is called when the MX919Bs IRQ output goes low. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump START Page 34 of 47 MX919B PRELIMINARY INFORMATION Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW values Ensure that the Mode Register IRQEN, PSAVE, RXEYE and TX/RX bits are '0', and the INVSYM bit is set appropriately Write a RESET task to the Command Register Read the Status Register BFREE bit = 1 ?
Yes No Wait until the received carrier has been present for at least 8 symbol times Set C variable 'STATE' to 0 Set the Mode Register IRQEN bit to '1'
Enable C's MX919B Rx Interrupt Service Routine Write a SFSH task to the Command Register with the AQSC and AQLEV bits set to '1'
Note: during this time the C may perform other functions, as the C variable 'STATE' is updated by the interrupt service routine Yes
'STATE' < 3 ?
No Disable C's MX919B Rx Interrupt Service Routine Set the Mode Register IRQEN bit to '0'
END with error No
'STATE' = 3 ?
Yes END Figure 21: Receive Frame Example Flowchart, Main Program Notes 1. The RESET command in Figure 21 and the practice of disabling the MX919Bs IRQ output when not needed are not essential but can eliminate problems during debugging and if errors occur in operation. 2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command Register. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 35 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump START line goes low )
IRQ Read Status Register IRQ bit = 1 ?
No RETURN
( Not MX919B IRQ ) Yes BFREE bit = 1 ?
Yes DIBOVF bit = 0 ?
Yes
'STATE' = 1 ?
Yes No No No E E Read 12 Intermediate Block bytes from the Data Buffer then write a RILB task to the Command Register Read 10 Header block bytes from the Data Buffer then write a RILB task to the Command Register SEE NOTE BELOW Decrement C variable
'IBLOCKS'
Set C variable 'IBLOCKS'
to the number of Intermediate Blocks to be received Value of C variable 'STATE' on entry to IRQ routine and corresponding MX919B's actions:
0 : Frame Sync has been recognized and Header block received, read out data and load RILB task. 1 : Intermediate block has been received, read out data and load RILB task. 2 : Last block has been received, read out data and finish. CRCERR bit = 0 ?
No Yes E Yes
'STATE' = 0 ?
No No
'STATE' = 2 ?
Yes No
'IBLOCKS' = 0 ?
Yes E Set C variable 'STATE' to 2 Set C variable 'STATE' to 9 RETURN RETURN
( Error ) Read 8 Last Block data bytes from the Data Buffer. Increment C variable
'STATE'
RETURN Figure 22: Rx Interrupt Service routine Note: This routine assumes that the number of Intermediate blocks in the Frame is contained within the Header Block Data. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 5.3 Clock Extraction and Level Measurement Systems 5.3.1 Supported Types of Systems The MX919B is intended for use in systems where:
1. The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first Frame MX919B PRELIMINARY INFORMATION Page 36 of 47 Sync pattern (see Figure 23). 2. A terminal may remain powered up indefinitely, transmitting concatenated Frames with or without intervening Symbol Sync patterns (each Frame having a Frame Sync pattern and symbol timing being maintained from one Frame to the next). 3. A receiving modem may be switched onto a channel before the distant transmitter has started up, or may be switched onto a channel where the transmitting station is already sending concatenated Frames 5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect When the receiving modem is enabled or switched onto a channel, it needs to establish the received symbol levels, clock timing, and look for a Frame Sync pattern in the incoming signal. This is best done by the following procedure:
1. Ensure that the Control Register's PLLBW bits are set to 'Wide' and the LEVRES bits to 'Track'. 2. Wait until a received carrier has been present for 8 symbol times. This 8-symbol delay gives time for the received signal to propagate through the modem's RRC filter. An 'RF received 8 symbol times' qualifying function can be included in a radio's carrier detect circuitry to take this into account. 3. Write a SFS or SFSH task to the Command Register with the AQSC and the AQLEV bits set to '1'. 4. When the modem interrupts to signal that it has recognized a Frame Sync pattern (or completed the SFSH task) then change the PLLBW bits to 'Medium'. Once the receiving modem has achieved level and symbol timing synchronization with a particular channel -
as evidenced by recognition of a Frame Sync pattern - then subsequent concatenated Frames can be read by simply issuing SFS or SFSH tasks at appropriate times, keeping the ASQSC and AQLEV bits at zero, and the PLLBW and LEVRES bits at their current 'Medium' and 'Track' settings, respectively. Noise Symbol Sync Frame Sync Rest of Frame Rx Signal from FM discriminator to Modem Set AQSC and AQLEV bits to start Acquisition sequences Level Measurement and Clock Extraction Circuits 8-Symbol delay determined by external circuit such as RF carrier detect Increasing accuracy and lengthening response times Figure 23: Acquisition Sequence Timing 5.3.3 Clock and Level Acquisition Procedure without RF Carrier Detect It is also possible to use the modem in a system where there is an indeterminate delay between the RF transmitter turn on time and the transmission moment of the Symbol Sync pattern, or where a receive carrier detect signal is not available to the controlling C, or where the transmitting terminal can send separate unsynchronized Frames. In these cases, each Frame should be preceded by, a Symbol Sync pattern which should be extended to about 100 symbols and the procedure provided in Section 5.3.2. used. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 37 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 5.3.4 Automatic Acquisition Functions Setting the AQSC and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude, and DC offset as quickly as possible before switching to accurate - but slower - measurement modes. These acquisition sequences act very quickly if triggered at the start of a received Symbol Sync pattern (as shown in Figure 23), but will still function correctly, although more slowly, if started any time during a normal Frame as when the receiver is switched onto a channel where the transmitter is operating continuously. The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits being put into 'Clamp' Mode for one symbol time to quickly set the voltages on the DOC pins to approximately correct levels. The level measurement circuits are then automatically set to 'Lossy Peak Detect' mode for 15 symbol times, then 'Slow Peak Detect' until a received Frame Sync pattern is recognized, after which the automatic sequence ends and the level measurement circuit mode reverts to the mode set by the LEVRES bits of the Control Register (normally 'Level Track'). The peak detectors used in both 'Slow' and 'Lossy Peak Detect' modes include additional low pass filtering of the received signal which greatly reduces the effect of pattern noise on the reference voltages held on the external DOC capacitors, but means that pairs of '+3' (and '-3') symbols need to be received to establish the correct levels. Two pairs of '+3' and two pairs of '-3' symbols received after the start of an AQLEV sequence are sufficient to correctly set the levels on the DOC capacitors. The automatic AQSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 16 symbol times (this mode is not one of those which can be selected by the Control Register PLLBW bits) then changes to 'Wide' bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control Register PLLBW bits. 5.4 AC Coupling For a practical circuit, ac coupling between the modem's transmit output to the frequency modulator and between the receiver's frequency discriminator and the receive input of the modem may be desired. There are, however, two issues which deserve consideration:
1. AC coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph illustrates the typical bit error rates at 4800 symbols/sec (9600bps) without FEC for reasonably random data with differing degrees of AC coupling:
1.E-01 1.E-02 B E R 1.E-03 1.E-04 Tx & Rx DC coupled Tx 5Hz, RxDC Tx 5Hz, Rx5Hz Tx 5Hz, Rx10Hz 4 5 6 7 8 9 10 11 12 13 S/N dB (Noise in 20 to 9600Hz band) 14 Figure 24: Effect of AC Coupling on BER (without FEC) 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 2. Any ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 25 below, the time for this step to decay to 37% of its original value is 'RC' where:
MX919B PRELIMINARY INFORMATION Page 38 of 47
=RC 2
(3dB cut
1 off frequency the of RC network) which is 32ms, or 153 symbol times at 4800 symbols/sec (9600bps) for a 5Hz network. Step Input to RC Circuit Output of RC Circuit 100%
37%
T = RC Figure 25: Decay Time - AC Coupling In general, it is best to DC couple the receiver discriminator to the modem and ensure that any AC coupling to the transmitter's frequency modulator has a -3dB cut-off frequency of no higher than 5Hz for 4800 symbols/sec (9600bps). 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. MX919B PRELIMINARY INFORMATION Page 39 of 47 4-Level FSK Modem Data Pump 5.5 Radio Performance The maximum data rate that can be transmitted over a radio channel using these modems depends on:
RF channel spacing. Allowable adjacent channel interference. Symbol rate. Peak carrier deviation (modulation index). Tx and Rx reference oscillator accuracy. Modulator and demodulator linearity. Receiver IF filter frequency and phase characteristics. Use of error correction techniques. Acceptable error rate. As a guide, 4800 symbols/sec (9600bps) can be achieved (subject to local regulatory requirements) over a system with 12.5kHz channel spacing if the transmitter frequency deviation is set to 2.5kHz peak for a repetitive ' +3 +3 -3 -3 ... ' pattern and the maximum difference between transmitter and receiver 'carrier'
frequencies is less than 2400Hz. The modulation scheme employed by these modems is designed to achieve high data throughput by exploiting as much as possible of the RF channel bandwidth. However; this does place constraints on the performance of the radio. Particular attention must be paid to:
Linearity, frequency, and phase response of the Tx Frequency Modulator. For a 4800 symbols/sec
(9600bps) system, the frequency response should be within 2dB over the range 3Hz to 5kHz, relative to 2400Hz. The bandwidth and phase response of the receiver's IF filters. Accuracy of the Tx and Rx reference oscillators, as any difference will shift the received signal towards the skirts of the IF filter response and cause a DC offset at the discriminator output. Viewing the equalized received signal eye diagram, using the Mode Register RXEYE function, provides a good indication of the overall RF transmitter/receiver performance. Rx FREQUENCY DISCRIMINATOR DC LEVEL ADJUSTMENT SIGNAL LEVEL ADJUSTMENT RXIN RXAMPOUT Tx FREQUENCY MODULATOR SIGNAL AND DC LEVEL ADJUSTMENT CC D0 - D7 A0 - A1 CS RD WR IRQ D0 - D7 A0 - A1 CS RD WR IRQ Rx CIRCUITS Tx CIRCUITS TXOUT MX919B MODEM Figure 26: Typical Connections between Radio and MX919B 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 40 of 47 MX919B PRELIMINARY INFORMATION 4-Level FSK Modem Data Pump 5.6 Received Signal Quality Monitor In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is recommended that the controlling software include a function which regularly checks that the modem is still receiving a good data signal and triggers a re-acquisition and possibly changes to another channel if a problem is encountered. This strategy has been shown to improve the system's overall performance in situation where fading, large noise bursts, severe co-channel interference, or loss of the received signal for long periods are likely to occur. Such a function can be simply implemented by regularly reading the Data Quality Register, which gives a measure of the overall quality of the received signal, as well as the current effectiveness of the modem's clock extraction and level measurement systems. Experience has shown that if two consecutive DQ readings are both less than 50 then it is worth instructing the MX919B to re-acquire the received signal levels and timing once it has been established that the received carrier level is satisfactory. Re-acquisition should follow the procedure given in Section 5.3. The intervals between Data Quality readings is not critical, but should be a minimum of 64 symbol times except for the first reading made after triggering the AQSC and AQLEV automatic acquisition sequences, which should be delayed for about 250 symbol times. A suitable algorithm is shown in Figure 27. AQSC/AQLEV task issued Reset timer. Set C variable 'LAST_DQ' to 99 No Timer > 250 ?
Note: Times are symbol times. Read DQ register into C variable 'THIS_DQ'
'THIS_DQ' < 50 ?
Yes
'LAST_DQ' < 50 ?
No No Yes Copy 'THIS_DQ' to 'LAST DQ'. Reset Timer. Re Acquire No Timer > 64 ?
Yes Figure 27: Received Signal Quality Monitor Flowchart 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 41 of 47 4-Level FSK Modem Data Pump 6. Performance Specification 6.1 Electrical Performance 6.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. MX919B PRELIMINARY INFORMATION General Supply (VDD VSS) Voltage on any pin to VSS Current VDD VSS Any other pin DW, LH, P Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature DS Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature Min.
-0.3
-0.3
-30
-30
-20
-55
-40
-55
-40 Max. 7.0 VDD + 0.3 30 30 20 800 13 125 85 550 9 125 85 Units V V mA mA mA mW mW/C above 25C C C mW mW/C above 25C C C 6.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Supply (VDD VSS) Symbol Rate Temperature Xtal Frequency Notes Min. Max. 5.5 9600 85 10.0 3.0 2400
-40 1.0 Units V Symbols/sec C MHz 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. Page 42 of 47 4-Level FSK Modem Data Pump 6.1.3 Operating Characteristics For the following conditions unless otherwise specified:
Xtal Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec, Noise Bandwidth = 0 to 9600Hz, VDD = 5.0V @ TAMB = 25C DC Parameters IDD IDD (VDD = 3.3V) IDD (Powersave Mode) IDD (Powersave Mode, VDD = 3.3V) AC Parameters TX Output TXOUT Impedance Signal Level TXIMP = 0 TXIMP = 1 Output DC Offset with respect to VDD/2 RX Input RXIN Impedance (at 100Hz) RXIN Amp Voltage Gain (input = 1mVRMS at 100Hz) Input Signal Level DC Offset with respect to VDD/2 XTAL/CLOCK INPUT High Pulse Width Low Pulse Width Input Impedance (at 100Hz) Inverter Gain (input = 1mVRMS at 100Hz) C Interface Input Logic 1 Level Input Logic 0 Level Input Leakage Current (VIN = 0 to VDD) Input Capacitance Output Logic 1 Level (IOH = 120A) Output Logic 0 Level (IOL = 360A) Off State Leakage Current (VOUT = VDD) MX919B PRELIMINARY INFORMATION Notes Min. Typ. Max. Units 1 1 1 1 2 3 3 4 5 5 6 6 7,8 7,8 7,8 7,8 8 8,9 9 0.8 0.88
-0.25 0.7
-0.5 40 40 10.0 20 70%
-5.0 92%
4.0 2.5 1.5 0.6 1.0 1.0 1.1 10.0 300 1.0 10.0 10.0 6.3 2.5 1.2 1.32 0.25 1.3 0.5 30%
5.0 8%
10 mA mA mA mA k VP-P VP-P V M V/V VP-P V ns ns M dB VDD VDD A pF VDD VDD A 6.1.3.1 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator. 2. Small signal impedance. 3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence, (Tx output level is proportional to VDD). 4. Measured at the TXOUT pin with the modem in the Tx idle mode. 5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence, TXIMP = 0 or 1, The optimum level and DC offset values are proportional to VDD. 6. Timing for an external input to the XTAL/CLOCK pin. 7. WR , RD , CS , A0 and A1 pins. 8. D0 - D7 pins. 9. IRQ pin. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 6.1.4 Timing Page 43 of 47 MX919B PRELIMINARY INFORMATION C Parallel Interface Timings (see Figure 28 ) Notes Min. tACSL Address valid to CS low time Address hold time tAH tCSH CS hold time tCSHI CS high time tCSRWL CS to WR or RD low time Read data hold time tDHR Write data hold time tDHW Write data setup time tDSW tRHCSL RD high to CS low time (write) tRACL Read access time from CS low tRARL Read access time from RD low tRL RD low time tRX RD high to D0-D7 3 state time tWHCSL WR high to CS low time (read) tWL 0 0 0 6 0 0 0 90 0 1 2 2 0 200 WR low time 200 Typ. Max. Units 175 145 50 ns ns ns clock cycles ns ns ns ns ns ns ns ns ns ns ns Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin. 2. With 30pF max to VSS on D0 - D7 pins. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump WRITE CYCLE (DATA TO MODEM) ADDRESS A0 A1, tACSL CS WR RD tRHCSL tCSRWL DATA D0 to D7 (1 byte) READ CYCLE (DATA FROM MODEM) tACSL tWHCSL ADDRESS A0 A1, CS WR RD DATA D0 to D7 (1 byte) Page 44 of 47 MX919B PRELIMINARY INFORMATION ADDRESS VALID tAH tCSH tWL tCSHI tDSW tDHW DATA VALID tAH tCSH tCSHI ADDRESS VALID tCSRWL tRL tRARL tRACL tDHR DATA VALID tRX Figure 28: C Parallel Interface Timings 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 6.1.5 Typical Bit Error Rate Page 45 of 47 MX919B PRELIMINARY INFORMATION BER with FEC BER without FEC BER 1E-1 1E-2 1E-3 1E-4 1E-5 1E-6 8 9 10 11 12 13 14 15 S/N dB (Noise in 2 x Symbol RateBandwidth) 16 Figure 29: Typical Bit Error Rate With and Without FEC Measured under nominal working conditions, LEVRES bits set to 'Level Track' or 'Slow Peak Detect' and PLLBW bits set to 'Medium' or 'Narrow' Bandwidth, Command Register TXIMP bit set to '0' or '1' (same for Tx and Rx devices), with pseudo-random data. Voltage Signal Voltage Noise calculates 20log Note:
N/S as 10
Where: Signal Voltage is the measured VRMS of a random 4-level signal. Noise Voltage is the VRMS of a flat Gaussian noise signal having a bandwidth from a few Hz to twice the symbol rate e.g. to 9600Hz when measuring a 4800 symbol/sec (9600bps) system. Both signals are measured at the same point in the test circuit. 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump 6.2 Packaging A ALTERNATIVE PIN LOCATION MARKING PIN 1 Y H J P Page 46 of 47 MX919B PRELIMINARY INFORMATION Z L T E W X B K C Package Tolerances DIM. MIN. TYP. MAX. A B C E H J K L P T W X Y Z 0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91) 0.016 (0.41) 0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17) 0.050 (1.27) 0.050 (1.27) 0.009 (0.23) 0.0125 (0.32) 0 5 45 5 10 7 NOTE : All dimensions in inches (mm.) Angles are in degrees Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW A Z L B E T X J P C PIN 1 PIN 1 Y H Package Tolerances DIM. MIN. TYP. MAX. 0.328 (8.33) 0.213 (5.39) 0.079 (2.00) 0.312 (7.90) 0.008 (0.21) 0.015 (0.38) 0.037 (0.95) 0.318 (8.07) 0.205 (5.20) 0.066 (1.67) 0.301 (7.65) 0.002 (0.05) 0.010 (0.25) 0.022 (0.55) A B C E H J L P T X Y Z NOTE : All dimensions in inches (mm.) 0.026 (0.65) 0.005 (0.13) 0.009 (0.22) 8 9 10 0 7 4 Angles are in degrees Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies. 4-Level FSK Modem Data Pump E B AD W PIN 1 P F G Page 47 of 47 MX919B PRELIMINARY INFORMATION C K Y W T J H Package Tolerances DIM. MIN. TYP. MAX. A B C D E F G H J K P T W Y 0.380 (9.61) 0.380 (9.61) 0.128 (3.25) 0.417 (10.60) 0.417 (10.60) 0.409 (10.40) 0.409 (10.40) 0.146 (3.70) 0.435 (11.05) 0.435 (11.05) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.018 (0.45) 0.047 (1.19) 0.049 (1.24) 0.006 (0.152) 30 45 6 0.022 (0.55) 0.048 (1.22) 0.051 (1.30) 0.009 (0.22) NOTE : All dimensions in inches (mm.) Angles are in degrees Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH A Package Tolerances DIM. MIN. TYP. MAX. B E1 Y E T C PIN1 K H L J J1 P 1.270 (32.26) 0.555 (14.04) 0.220 (5.59) 0.670 (17.02) 0.625 (15.88) 0.045 (1.14) 0.023 (0.58) 0.065 (1.65) 0.074 (1.88) 0.160 (4.05) 1.200 (30.48) 0.500 (12.70) 0.151 (3.84) 0.600 (15.24) 0.590 (14.99) 0.015 (0.38) 0.015 (0.38) 0.040 (1.02) 0.066 (1.67) 0.121 (3.07) A B C E E1 H J J1 K L P T Y NOTE : All dimensions in inches (mm.) 0.100 (2.54) 0.015 (0.38) 0.008 (0.20) 7 Angles are in degrees Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP 2001 MXCOM, INC. 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 All trademarks and service marks are held by their respective companies.
1 | Manual | Users Manual | 964.73 KiB | March 09 2002 |
IIPP44HHPPVV MMoobbiillee RRaaddiioo Owners Manual Date Prepared:
August 7, 2002 Document Control #: DC-67 Version: C-1 (Special Release) Copyright 2002 IPMobileNet, Inc. 11909 East Telegraph Road Santa Fe Springs, CA 90670-3785 Voice: (562) 946-9493 Fax: (562) 949-0223 TABLE OF CONTENTS SECTION 1: THEORY OF OPERATION ................................................................................. 3 General Block Diagram................................................................................................ 3 General Block Diagram Definitions..................................................................... 3 IP4HPV Mobile Radio Section Descriptions .............................................................. 5 Microcontroller.................................................................................................... 5 Support Circuitry ................................................................................... 5 Inputs/Outputs .................................................................................................... 5 Modem .............................................................................................................. 6 VLogic and Digital Ground ................................................................................. 6 Receiver 1 Front-End ......................................................................................... 7 Receiver 1 IF ...................................................................................................... 7 Transmit Modulation........................................................................................... 7 Injection Synthesizer .......................................................................................... 8 Transmitter/TR Switch........................................................................................ 8 Power and Analog Ground ................................................................................. 8 SECTION 2: FACTORY TEST PROCEDURE ....................................................................... 10 Equipment List ........................................................................................................... 10 Programming and Configuring Mobile Radio.......................................................... 11 Adjustment / Alignment Procedures ........................................................................ 12 Receiver Injection............................................................................................. 12 Receiver 1 ........................................................................................................ 12 Receiver 2 ........................................................................................................ 13 Transmit Data................................................................................................... 14 Transmit Power Control.................................................................................... 14 Receive Data.................................................................................................... 15 Final Test.......................................................................................................... 15 Uplink Hardware Timing Verification ................................................................ 17 Downlink Hardware Timing Verification............................................................ 19 SECTION 3: FCC LABEL ...................................................................................................... 21 IP4 HPV Mobile Radio FCC Label Placement .......................................................... 21 IP4 HPV Mobile Radio FCC Label ............................................................................. 21 APPENDIX A: IP4 HPV CIRCUIT BOARD DIAGRAM .......................................................... 44 APPENDIX B: IP4 HPV TEST DATA SHEET........................................................................ 45 IP4HPVGPS-MRFCCRpt.doc Page 2 SECTION 1: THEORY OF OEPRATION General Block Diagram General Block Diagram Definitions
For increased data security, the modem supports the Federal Government developed Digital Encryption Standard (DES) data encryption and decryption protocols. This capability requires installation of third party, Internet Protocol (IP) compliant DES encryption and decryption software on the system. The IP4HPV mobile radio is comprised of two (2) circuit boards, the digital board and the RF board. The digital circuit board contains the following sections:
Input/Output Microcontroller Modem Power Supply Circuitry associated with the radios DB9 data connector providing all the RS232 data and handshake functions, including the necessary level changes. Manages the operation of the radio, the modem, and determines which receiver provides a better signal from a given transmission. Also provides transmit time-out protection in the event a fault causes the radio to halt in the transmit mode. Converts serial data into an analog audio waveform for transmission and analog audio from the receiver to serial data. Within a single chip it provides forward error detection and correction, bit interleaving for more robust data communications, and third generation collision detection and correction capabilities. The power supply creates the various voltages required by the digital portion of the mobile radio. IP4HPVGPS-MRFCCRpt.doc Page 3 The RF circuit board contains the following sections:
Transmit Processing SECTION 1: THEORY OF OPERATION Circuitry that amplifies the analog audio signal from the modem and uses it to modulate the voltage controlled oscillator (VCO) and 10 MHz reference oscillator in the injection synthesizer section. Modulating the VCO and reference oscillator simultaneously results in a higher quality FM signal. Provides programmable, ultra stable signals for the radio. Synthesizer incorporates phase lock loop technology used for both receiving and transmitting. In the receive mode, the synthesizer provides a local oscillator signal of 45 MHz above or below the selected receive channel frequency. Consists of an exciter and power amplifier module. The transmitter covers the various frequency bands in segments. A different power amplifier module is required for each segment. The transmitter circuitry includes a T/R switch switching the antenna between transmitter and receiver 1
(TX/RX1). Required to support the mobile DRS; two (2) discrete receivers are tuned to the same channel and use two (2) antennas. The receivers are double-conversion superheterodyne with a first Intermediate Frequency (IF) of 45 MHz and a second IF frequency of 455 KHz. Each receiver consists of bandpass filters, an RF amplifier, a MMIC mixer, crystal filters, and a one-chip IF system. The injection synthesizer provides the first local oscillator signal. Outputs from each receiver include RSSI and analog audio for the baseband routing circuitry and modem. Consists of circuitry that derives the various operating voltages for the RF portion of the mobile radio. Injection Synthesizer Injection Transmitter Receiver 1/Receiver 2 Power Supply IP4HPVGPS-MRFCCRpt.doc Page 4 SECTION 1: THEORY OF OPERATION IP4HPV Mobile Radio Section Descriptions
The IP4HPV Mobile Radio works within a frequency range of 506 to 512 MHz and requires a 1/4-
wavelength antenna. This section provides detailed descriptions of each of the sections within the IP4HPV Mobile Radio. Refer to Appendix A to view the IP4HPV Mobile Radio Circuit Board Diagram. Microcontroller The microcontroller (U30) is a major component of the radio as it manages the operation of the radio. It also controls the operation of the modem, and determines which receiver provides a better signal from a given transmission. It provides transmit time-out protection in the event a fault causes the radio to halt in the transmit mode. It utilizes a reduced instruction set computer (RISC) architecture which provides low power operation and a powerful instruction set. Other features include a watchdog timer, serial universal asynchronous receiver/transmitter (UART), two 8-bit timers, and 2 KB of electrically erasable programmable read only memory (EEPROM) storage. NOTE:
The EEPROM Random Access Memory (RAM) stores the setup data entered by the technician even if there is a loss of power. Support circuitry The support circuitry consists of the following:
A Supervisor Control Chip (U25) provides power-on reset.
The clock controls microcontroller operation and is generated by crystal Y3 and a Pierce oscillator circuit (inside the U30-microcontroller).
The latch (U28) decodes low order address bits (A0-A7) from the address/data bits (AD0-AD7). It is controlled by Address Latch Enable (ALE) output of U30 and the bits are used by the modem.
A 512Kx8 Static RAM Chip (U31) provides temporary storage of the radios configuration data facilitating the technician with access to make changes.
Control logic is also an important part in the microcontroller section. The RAM chip select (RAMCS*) and modem chip select (MODEMCS*) command lines are created by U26A, U27BCD, and U44ABC. These gates decode four (4) high order address bits (A11-A15). The RAM is addressed by five (5) memory addresses (MA14-MA18) bits decoded by U26D, U27A, and U24. This logic decodes port address bits (PA14-PA18) to produce memory address bits (MA14-MA18) for the RAM chip. Input/Output Input/output components convert serial and handshake data from the modem section to RS232 levels, and vice-versa. Chip U22 is an RS232 transmitter and receiver. It converts data in 5-volt logic form to data in +/-12-volt form, as required by the RS232 standard. A charge pump power supply on the chip converts the +5-volt DC logic power on pin 26 to the +12-volt and 12-volt levels required. Capacitors C106-C109 generate these voltages by a charge pump. These values determine the operating voltages. IP4HPVGPS-MRFCCRpt.doc Page 5 SECTION 1: THEORY OF OPERATION Modem The single-chip modem circuit converts parallel data to an analog audio waveform for transmission and analog audio from a receiver to parallel data. In addition to the modem functions, the chip provides forward error detection and correction (FEC), bit interleaving and Viterbi Soft Decision Algorithms for more robust data communications. The microcontroller section controls the modem operation. Address bus, address/data bus, and control lines operate the modem chip. The modem circuitry is also run by a crystal-controlled clock, which consists of crystal Y1 and an internal Pierce oscillator. The received audio signal is demodulated into digital data appearing on the AD0-AD07 lines when the MODEMCS* and RD* lines are low. The data goes to the microcontroller section for futher processing, and then to the input/output section for conversion to RS232 or Ethernet signal levels. During a transmission, outgoing data appearing on the AD0-AD07 lines is converted into a 4-level FSK analog signal by the modem chip. This operation takes place when the MODEMCS* and WR* lines are low. Data from the users MDC or VIU passes through the input/output section and microcontroller section to the AD0-AD07 bus. After processing, data passes through a root raised cosine filter and is output to TXMOD. This modem supports 115.2 KBPS (serial port) and 19.2 KBPS (over-the-air) data transmission rates. VLogic and Digital Ground The VLogic and Digital Ground section consists of a pulse-width modulation (PWM) step-down DC-DC converter (U20) that provides an adjustable output. It also reduces noise in sensitive communications applications and minimizes drop out voltage. An external Schottky diode (D2) is required as an output rectifier to pass inductor current during the second half of each cycle to prevent the slow internal diode of the N-channel MOSFET from turning on. This diode operates in pulse-frequency modulation (PFM) mode and during transition periods while the synchronous rectifier is off. IP4HPVGPS-MRFCCRpt.doc Page 6 SECTION 1: THEORY OF OPERATION Receiver 1 Front-End This section contains components that include several RF Bandpass filters, a low-noise amplifier, and a MMIC mixer. Incoming signals pass through one (1) pre-selector filter (FLT7) that selectively provides a high degree of out-of-band signal rejection. A low-noise amplifier (U3) amplifies the selected signals and is followed by an image and noise reject filter (FLT8). The output from FLT8 passes through a mixer (U4). U4 is a MMIC mixer which mixes the receive injection (RXINJ1) signal from the synthesizer and the RF signal from the antenna to produce a 45 MHz IF signal. This 45 MHz signal passes through crystal filters (FLT3 and FLT4) to the Receiver 1 IF section to provide the bulk of the Receivers selectivity.
Receiver 2 Front-End operates identical to Receiver 1 Front-End. Receiver 1 IF The major contributor of the IF subsystem (U33) a complete 45 MHz superheterodyne receiver chip incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage regulator and audio and RSSI op amps. Incoming 45 MHz signals appearing at RX1_45MHz pass through the low-voltage high performance monolithic FM IF system. Within U33, the signals pass through a simple LC filter and are boosted by the RF amplifier. The output of the RF amplifier drives a mixer. A crystal oscillator is controlled by crystal Y4 and provides the injection frequency for the mixer. The mixer output passes through a 455 KHz ceramic filter (FL6). It is then amplified and passed through another ceramic filter (FL5) to a second gain stage. The IF output drives a quadrature detector. The phase shift elements for the detector are C123 and FLT5. The RSSI detector converts the AGC voltage generated inside the chip into a DC level corresponding logarithmically to the signal strength. The Diversity Reception Controller uses BRSSI1 to select the receiver with the best quality signal. The audio is amplified by an op amp (U19C) and delivered to the power and analog ground circuitry via the RXMOD1 output. High frequency de-emphasis is provided by a filter consisting of a resistor and a capacitor. In order to match the audio signal levels with the other circuitry, a gain control is included. A pot (R81) is necessary to adjust gain.
Receiver 2 IF operates identical to Receiver 1 IF. Transmit Modulation The analog circuitry in this section modulates the Transmitter. The data-bearing audio signal from the modem appears at TXMOD. The audio is amplified by op amp (U70D). The output of U70D drives two
(2) amplifiers (U70B and U70C). The transmitter uses dual-point modulation meaning the modulation is applied both to the VCO as well as the reference oscillator (VCTCXO). The upper amplifier (U70B) has adjustable gain. The output drives op amp (U70A), which inverts the phase of the signal. Upon the start of a transmission, the modulating signal passes through to the VCTCXO reference oscillator in the synthesizer. Some makes of VCTCXO oscillators do not require the modulation signal to be inverted and a jumper block (JMP4) is provided to accommodate the oscillators. IP4HPVGPS-MRFCCRpt.doc Page 7 SECTION 1: THEORY OF OPERATION The lower op amp (U70C) amplifies the signal from the low pass filter and applies it to the VCO via the VCOMOD output. Pot RV1 and RV2 are used to adjust maximum deviation. Injection Synthesizer The dual synthesizer chip (U38) is the major contributor of the injection synthesizer. This device contains the key components of a phase locked loop (PLL), including a prescaler, programmable divider, and phase detector. The selected frequencies are loaded into U38 as a clocked serial bit stream via the PLL DATA, PLL CLOCK and PLL ENABLE signals. Frequency stability is determined by a temperature-compensated crystal oscillator module (VCTCXO)
(Y5) at a frequency stability of 1 PPM from 30C to +60C. This device has an input (REFMOD) that accepts transmit modulation and voltage from a RX FREQ ADJUST pot. The pot allows the receiver to be fine-tuned to the exact operating frequency. Two (2) voltage control oscillators (VCO) are formed by integrated low-noise oscillators with buffered outputs (U39 and U40) and associated circuitry. The VCOs generate receiver and transmit injection signals. The receiver control voltage is generated by the phase detector output (PDOUT) of U38 driving a loop filter consisting of R111, R112, C185, C186, C42, R133, and C213. It integrates the pulses that normally appear on PDOUT into a smooth DC control signal for U40. The output of U40 is split by U63 leading to outputs RXINJ1 and RXINJ2. A second output of U40 is returned to the synthesizer FIN input via RXFB. This completes the loop signal path. The transmitter control voltage is generated by the phase detector output (PDOUT-L) of U38 driving a loop filter consisting of transmitter R135, R118, C195, C196, and C214. It integrates the pulses that normally appear on PDOUT-L into a smooth DC control signal for U39. Upon transmit, the analog signal from the modem and transmit processing circuitry is applied to the U39 tuning circuit at CR6. The output of U39 is the TXINJ signal. A second output of U39 returns to the synthesizer F-IN input via TXFB. Transmitter/TR Switch The transmitter section consists of a driver amplifier (U36) and a final power amplifier (U35). To transmit, 5-volt power is applied to the KEYPWR line. PA12V line is also powered up. This causes power amplifier (U35) to boost the RF power to the desired level. Up to 40 watts are available from the transmitter. Harmonic suppression is provided by C233, L43, and L44. Power and Analog Ground These sections consist of the power supplies and transmit control circuitry. Power from the vehicles battery appears at VBATT. Diode D1 protects the voltage regulators by clamping any transient spikes on the supply line. Such spikes typically occur while the engine is started. The supply line powers a series of voltage regulators and the transmitter control circuitry, as follows:
Voltage regulator U46 provides 8-volt power for most other sections in the radio.
Voltage regulator U21 powers the transmit driver and T/R switch diodes as controlled by the microcontroller.
Voltage regulator VR2 provides a low noise 3.3-volt source for the radio electronics. In the transmit control circuitry, to transmit, the microcontroller makes TXKEYOUT* high. Forcing the P-
channel device to conduct, applying 12-volts via PA12V to the transmitter power amplifier bias pins. IP4HPVGPS-MRFCCRpt.doc Page 8 SECTION 2: FACTORY TEST PROCEDURE Equipment List The following table lists the equipment required to perform the IP4 HPVGPS Mobile Radio Factory Test Procedure:
QTY DESCRIPTION MANUFACTURER MODEL 2 1 1 1 1 1 1 1 1 2 1 1 1 1 1 PCs One for Mobile One for Base Service Monitor Communication Test Set Digital multi-meter DC power supply w/ ammeter, 13.8V, 23 Amps or more 4-Channel Scope IP4HPV Mobile Radio IP4HPV Calibrated Base Station Internet Protocol Network Controller
(IPNC) UHF Antennas (generic mag mount) Serial cable DB9M-DB9F connectors IP power cable 3-foot RF jumper cable with type N connectors (generic) Scope test probe (generic, X1 attenuation) Ceramic tuning tool 1 ea
#0, #1, and #2 Phillips screwdrivers
(generic) Windows 9X w/
IPMessage AVR HP Tektronix Fluke Astron HP8920B or equivalent 77 or equivalent RM35A Tektronix TDS 460A PE7021-40 or equivalent IPMN p/n:
156-0245-020 IPMN p/n:
502-82017-52 IPMN p/n:
44010006 100 watt dummy load/attenuator Pasternack IP4HPVGPS-MRFCCRpt.doc Page 9 Step 2 Step 3 Step 4 SECTION 2: FACTORY TEST PROCEDURE Programming and Configuring Mobile Radio Once the appropriate equipment for performing the factory test are gathered, perform the following steps to program and configure an IP4HPV Mobile Radio:
Step 1 Enter the following information on the Test Data Sheet (see Appendix B):
Radio Serial number
Date test being performed
Tester's Name Program the radio to the current Firmware revision using the AVR programming utility. Connect a PC to the radio and launch the IPMessage program. In the IPMessage window, type factory default, press [ENTER], and the radio displays the radios default values. Enter the appropriate values for the radio's frequency band. The following values were used for a 506 to 512 MHz radio:
[From: 172.16.64.1] Host serial = 115200,N,8,1, timeout=200
[From: 172.16.64.1] Channel = 0
[From: 172.16.64.1] Channel Tx freq Rx freq Inj freq
[From: 172.16.64.1] Frequency= 0, 509.000000, 506.000000, 551.000000
[From: 172.16.64.1] IP Address = 172.16.64.1 (VIU = 0.0.0.0, PC = 192.168.3.5)
[From: 172.16.64.1] IPNC = 172.16.112.200
[From: 172.16.64.1] netmask = 255.255.255.0
[From: 172.16.64.1] Radio Mac Address = 00:08:ce:00:00:00
[From: 172.16.64.1] Hosting framing = SLIP no status messages
[From: 172.16.64.1] channel spacing = 25000
[From: 172.16.64.1] Injection = HIGH SIDE, 45 MHz
[From: 172.16.64.1] TX Power = 0
[From: 172.16.64.1] Car to car TX power = 0
[From: 172.16.64.1] serial number: undefined
[From: 172.16.64.1] TX quiet time = 5
[From: 172.16.64.1] TX sync time = 2- milliseconds
[From: 172.16.64.1] TX tail time = 5
[From: 172.16.64.1] TX delay = 0 slots
[From: 172.16.64.1] Radio data rate = 19200
[From: 172.16.64.1] Max data tx time = 60 seconds
[From: 172.16.64.1] PLL load to txkey delay = 2 milliseconds
[From: 172.16.64.1] Carrier detect delay time = 6 milliseconds
[From: 172.16.64.1] roam status times = 900 seconds
[From: 172.16.64.1] roam lost time = 60 seconds
[From: 172.16.64.1] Polarity = TX-, RX+
[From: 172.16.64.1] RSSI step = 12 (=234mV)
[From: 172.16.64.1] noise = -126dBm, -126dBm
[From: 172.16.64.1] num timeslots = 16
[From: 172.16.64.1] timeslot period = 992ms
[From: 172.16.64.1] timeslots per voice packet = 4
[From: 172.16.64.1] 06Feb2036 22:28:34 (PST), calibration=43
[From: 172.16.64.1] diversity speed = 5
[From: 172.16.64.1] receiver = 2
[From: 172.16.64.1] Receiver Hysteresis = 2
[From: 172.16.64.1] Internal GPS Port Address = 5000
[From: 172.16.64.1] Internal GPS Input Protocol = TSIP
[From: 172.16.64.1] Internal GPS Output Protocol = TSIP
[From: 172.16.64.1] 12dB SINAD = -120dBm (54 on RX0)
[From: 172.16.64.1] 12dB SINAD = -120dBm (54 on RX1)
[From: 172.16.64.1] 30dB S/N = -106dBm (72 on RX0)
[From: 172.16.64.1] 30dB S/N = -106dBm (72 on RX1)
[From: 172.16.64.1] 40dB S/N = -90dBm (114 on RX0)
[From: 172.16.64.1] 40dB S/N = -90dBm (114 on RX1)
[From: 172.16.64.1] 40dBm = (214) on RX0)
[From: 172.16.64.1] 40dBm = (214) on RX1)
[From: 172.16.64.1] PLL counter: 510.000000 MHz, N = 22200, R = 800 (400x2)
[From: 172.16.64.1] Suspend Tx = 0 seconds
[From: 172.16.64.1] DHCP Client disabled
[From: 172.16.64.1] DHCP Server disabled
[From: 172.16.64.1] diag message level = 0
[From: 172.16.64.1] TFTP options = 512 (block size), 0 (interval)
[From: 172.16.64.1] Internal GPS not found
[From: 172.16.64.1] Modem FEC = on IP4HPVGPS-MRFCCRpt.doc Page 10 SECTION 2: FACTORY TEST PROCEDURE Adjustment / Alignment Procedures Receiver Injection Perform the following steps to adjust the receiver injection and injection frequency:
Step 1 While monitoring the receiver injection frequency at RXINJ1, adjust potentiometer R81 for minimum frequency error of +/- 100Hz. Record this value on the Test Data Sheet. While monitoring the 44.545 MHz 2nd injection frequency at U34 pin 4, adjust trimmer capacitor CV4 for the maximum amplitude of this injection frequency. The maximum amplitude must be between -3 to -5 dBm. Record this value on the Test Data Sheet. Receiver 1 Perform the following steps to adjust receiver 1:
Step1 Inject an on-frequency carrier signal with an amplitude of -80 dBm, modulated with a 1 kHz test tone at +/- 5.0 kHz deviation into receiver 1's antenna port. While monitoring the voltage at RSSI1 Test Point with a DMM, adjust trimmer capacitor CV1 to midway between the points where the oscillation stops. While monitoring the DC level of the recovered modulation, adjust potentiometer R82 for a reading of 2.500 VDC +/- 1 mV DC. While monitoring the amplitude of the recovered audio signal, adjust potentiometer R81 and R82 for a reading of 350 mV RMS and 2.500 VDC. Steps 3 and 4 are interactive adjustments, therefore repeat steps 3 and 4 until further adjustment is no longer required (i.e. when 350 mV RMS and 2.500 VDC are realized). While monitoring the recovered audio signal at TP1, verify the distortion is less than 3%, adjust CV1 if necessary to achieve less than 3% distortion. Record this value on the Test Data Sheet. While monitoring the recovered audio signal at TP1, verify the SINAD is -118 dBm or better. Record this value on the Test Data Sheet. Step 2 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 IP4HPVGPS-MRFCCRpt.doc Page 11 SECTION 2: FACTORY TEST PROCEDURE Receiver 2 Perform the following steps to adjust receiver 2:
Step 1 Inject an on-frequency carrier signal with an amplitude of -80 dBm, modulated with a 1 kHz test tone at +/- 5.0 kHz deviation into Receiver 2's antenna port. While monitoring the voltage at RSSI2 Test Point with a DMM, adjust trimmer capacitor CV4 to midway between the points where the oscillation stops. While monitoring the DC level of the recovered modulation, adjust potentiometer R99 for a reading of 350 mV (+/-10 mV) RMS. While monitoring the amplitude of the recovered audio signal, adjust potentiometer R93 for a reading of 2.500 (+/-10 mV) VDC. Steps 3 and 4 are interactive adjustments, therefore repeat steps 3 and 4 until further adjustment is no longer required (i.e. when 350 mV RMS and 2.500 VDC are realized). While monitoring the recovered audio signal at TP1, verify the distortion is less than 3%, adjust CV4 if necessary to achieve less than 3% distortion. Record this value on the Test Data Sheet. While monitoring the recovered audio signal at TP1, verify the SINAD is -118 dBm or better. Record this value on the Test Data Sheet. Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 IP4HPVGPS-MRFCCRpt.doc Page 12 SECTION 2: FACTORY TEST PROCEDURE Transmit Data Perform the following steps to adjust transmit data:
Step 1 Step 2 Use IPMessage to set the transmit power to 0. Using the x=2000,n command of IPMessage to generate transmit data messages while observing the transmitted signal on the HP RF communications test set, adjust pot R33 for minimum frequency error while transmitting data messages. Turn potentiometer RV1 fully counterclockwise. Adjust RV2 for deviation of 4.9 kHz. Using calibrated base station, and monitoring the uplink received data quality on the base station's Hyperterminal screen, slowly turn RV1 clockwise until consistent data quality readings of 240 - 248 are achieved using 2000 character test messages. Data quality reading should not be less than 240 for 2000 character messages.
If unable to reach the data quality readings then ask for Technical Support. Poor data quality readings are indicative of poor group delay performance, or other defect. Verify transmit deviation, frequency error, and transmitting data messages quality and record this data on the Test Data Sheet. Power Setting Perform the following steps to adjust the transmit power control:
Step 1 Step 2 Attach a power attenuator to the transmit port of the radio. Using the x=2000,n command of IPMessage, and while monitoring the transmit power level on the HP communications test set, check the level of the transmit power. Using IPMessage set the power setting to txpower=0. The radio should have an output power level of approximately 1 mW. Record this value on the Test Data Sheet. Using IPMessage send the txpower= command to increase the power level settings until 40 Watts of output power is obtained. Record this value on the Test Data Sheet. Note that values on the table are to plot the codes vs. power output. The 40-Watt setting can be a code not on the table. Adjust txpower until the code is found that does not exceed 40.0 Watts. Record this value on the Test Data Sheet.
Do not to exceed 40 Watts of output power, as this may reduce the life of the amplifier. Step 3 Step 4 Step 5 Step 6 Step 3 IP4HPVGPS-MRFCCRpt.doc Page 13 SECTION 2: FACTORY TEST PROCEDURE Receive Data Perform the following steps to verify the receive data performance:
Step 1 Using the DOS ping command on the PC connected to the radio, ping the network controller to generate uplink and downlink data messages. The following command will generate one Hundred 500 character messages:
>;Ping 192.168.3.3 -n 100 -l 500 Observe the data quality readings on the IPMessage window of the PC connected to the radio using the V (for Verbose) command in the IPMessage program. With the mobile radio's antenna connected to receiver 1, verify the received data quality readings are consistently 248s. Data quality readings should also be verified at the base station using the V command on the Hyperterminal window. Verify receiver 2 data quality readings are also consistently 240 to 248s by changing the antenna from receiver 1 port to receiver 2 port. In this manner both uplink and downlink data quality can be verified. Record this data on the Test Data Sheet. Final Test A final test must be performed prior to shipping the IP4HPV mobile radio to the customer. This final test will verify that the timing characteristics are correct and that both transmit and receive data quality readings are consistently high. Perform the following steps for the final test:
Step 1 Step 2 Attach the 40dB 100-Watt power attenuator to the transmit port of the radio. Program the radio for full power operation. The tx power level setting can be found in the radio's Test Data Sheet.
Attach a digital scope to the base station as described in section the next section, Uplink Hardware Timing Verification. Using the x=2000,19 command (which will cause the radio to transmit 19 2000 character messages), verify the following:
The setting must not to exceed 40 Watts. Transmit frequency of radio is adjusted for minimum frequency error of +/- 100 Hz. The x=2000,19 command will generate different messages with differing DC components. Each message will slightly slew the frequency off from the center frequency). Be careful to closely monitor the variation in transmit frequency due to these different messages and ensure that on average the transit frequency error has been minimized to within +/-100 Hz. This indicates that some of these test messages will be slightly high in frequency, some messages will be slightly low in frequency, and some messages will be right on frequency. Verify the transmit deviation is 4.9 kHz Step 2 Step 3 Step 3 Step 4 IP4HPVGPS-MRFCCRpt.doc Page 14 Step 5 Step 6 Step 7 Step 8 Step 9 Step 10 Step 11 Step 12 Step 13 SECTION 2: FACTORY TEST PROCEDURE Verify the timing characteristics are identical to the plots in the next section, Uplink Hardware Timing Verification. At the base station monitor PC, verify that all the data quality readings are 240 and higher. Move the scope probes to monitor the timing at the mobile radio as described in Downlink Hardware Timing Verification. Generate test messages by pinging the IPNC from the PC attached to the radio. The following command will cause 100 pings, 500 bytes in length to be transmitted from the mobile radio and echoed by the IPNC through the base station:
.>;Ping 192.168.3.3 -n 100 -l 500 -w 2000 Set CRC =1 Enable on the radio Verify the timing characteristics are identical to those in Downlink Hardware Timing Verification. Verify that both receivers on the mobile radio report data quality readings of 240 or higher
(248 is typical). This can be accomplished by installing the antenna on the TX/RX1 port and verifying RX1 is selected by observing the RX1 LED on the mobile radio and installing the antenna on the RX2 port and verifying RX2 is selected by observing the RX2 LED on the mobile radio. Reset CRC = 0 Disable on the radio In IPMessage, type the ? command to radio. Copy the radio settings and paste them into the Test Data File. Perform a close visual inspection of the radio closely inspecting manufacturing related problems (loose screws, solder particles, etc.). IP4HPVGPS-MRFCCRpt.doc Page 15 SECTION 2: FACTORY TEST PROCEDURE Uplink Hardware Timing Verification Figure 2-1 below displays an oscilloscope plot of an uplink data message from the mobile to the base station. Channel 1 is connected to the base station's RSSI (XXX-12), channel 2 is connected to the base station's recovered modulation, and channel 3 is connected to the base station's modem chip select line. The scopes acquisition mode is high-resolution. Figure 2-1: Oscilloscope Plot of an Uplink Data Message As seen in the above plot, the mobile radio's transmit carrier has ramped up to full power (channel 1) in just a few milliseconds. The recovered modulation (channel 2) is stable by this time. There follows a few milliseconds of quiet time followed by 12 milliseconds of symbol sync time. The recovered modulation from a mobile radio should look identical to this plot. The recovered modulation signal should be approximately 1.0 Volts peak-to-peak and should be centered at approximately 2.5 VDC as is indicated in the figure above.
IP4HPVGPS-MRFCCRpt.doc Page 16 SECTION 2: FACTORY TEST PROCEDURE Figure 2-2 displays another oscilloscope plot of an up-link data message from the mobile to the base station. As in the last plot, channel 1 is connected to the base station's RSSI (J5-12), channel 2 is connected to the base station's recovered modulation test point, and channel 3 is connected to the base station's modem chip select line (U16-13). The scope's acquisition mode is now in the peak detect mode. This enables the base station's modem CS (Chip Select) line to be viewed. Figure 2-2: Another Oscilloscope Plot of an Uplink Data Message The base station's microcontroller, upon detecting a step response in the RSSI (caused by the mobile radio's transmitter coming up to power), waits a period of time equal to the programmed value of the base station's carrier detect delay time. The microcontroller then instructs the modem to search for the modem synchronization preamble. When the base station instructs the modem to look for sync tones, the modem's CS line transitions low. This can be seen in the above plot. Approximately 10 milliseconds after the mobile radio's transmitter causes a step increase in the base station's RSSI, the CS signal goes low momentarily. As can be seen, the sync tones are stable by this time and the modem quickly establishes synchronization. IP4HPVGPS-MRFCCRpt.doc Page 17 SECTION 2: FACTORY TEST PROCEDURE Downlink Hardware Timing Verification Figure 2-3 displays a plot of the downlink timing characteristics. Channel 1 is connected to RSSI, channel 2 is connected to recovered audio, and channel 3 is connected to the modem CS pin. The scope is in the high-resolution acquisition mode.
There is a very short period of quiet time (no modulation) followed by approximately 12 milliseconds of modem synchronization time (sync time). Figure 2-3: Downlink Timing Characteristics Plot IP4HPVGPS-MRFCCRpt.doc Page 18 SECTION 2: FACTORY TEST PROCEDURE The plot in Figure 2-4 is the same as before but now the scope is in the peak detect acquisition mode. After the mobile radio detects a step response in the RSSI (caused by a down-link transmission), the radio's microcontroller waits an amount of time equal to the programmed value of the "carrier detect delay time" then instructs the modem to look for frame sync. When the microcontroller instructs the modem to look for frame sync, it asserts the modem's CS line (active low). In this plot, the modem's CS line can be seen to transition low approximately 3 milliseconds after the base station's transmitter has come up to full power. Figure 2-4: Downlink Timing Characteristics Plot in Peak Detect Acquisition Mode The recovered modulation should be centered at approximately 2.5 VDC and should have an amplitude of approximately 800 mV peal-to-peak as indicated in the plot above. IP4HPVGPS-MRFCCRpt.doc Page 19 SECTION 3: FCC LABEL 400 512 MHz DIVERSITY MOBILE DATA FCC ID : M17-IPMNIP4 IP4HPV Mobile Radio FCC Label Placement Serial No. Model: IP4HPV IP4HPV Mobile Radio FCC Label FCC ID : M17-IPMNIP4 Serial No. Model: IP4HPV IP4HPVGPS-MRFCCRpt.doc Page 20 APPENDIX A: CIRCUIT BOARD DIAGRAM IP4 HPV Mobile Radio Digital Circuit Board
IP4 HPV Mobile Radio RF Circuit Board
IP4HPVGPS-MRFCCRpt.doc Page 21 APPENDIX B: IP4HPV TEST DATA SHEET Program and Configure Radio Date Serial Number Firmware Revision Tester Adjustment / Alignment Procedures Receiver Injection Parameter Injection Frequency Error at RXINJ1(within +/- 100 Hz of exact injection frequency) U34 pin 4 power level Receiver 1& 2 Parameter Audio DC Amplitude
(1 kHz Test tone @ 5.0 kHz Deviation) Audio AC Amplitude
(1 kHz Test tone @ 5.0 kHz Deviation) Distortion
(1 kHz Test tone @ 5.0 kHz Deviation) SINAD 12 dB
(1 kHz Test tone @ 5.0 kHz Deviation) Spec 2.5 VDC
+/- 1mV 350 mVRMS
+/- 1mV 3%<
-118dBm >
Spec
+/- 100 Hz
-3 to -5 dBm Receiver 1 Measured Measured Receiver 2 Measured IP4HPVGPS-MRFCCRpt.doc Page 22 Transmit Section Parameter APPENDIX B: IP4HPV TEST DATA SHEET Spec Measured Transmit Modulation Deviation
(4.9 kHz while transmitting 2000 character test message) 4.9 kHz Transmit Data Quality
(While transmitting 2000 character test messages to the base station) Transmit Frequency Error
(Transmitting 2000 character test message) 240 >
+/- 100Hz Transmit Power Control Caution: Do not to exceed 40-Watts RF output power during this test. Transmit Power Setting 0 25 50 75 100 125 150 175 200 225 250 Expected RF Out
~ 1mW RF Out Watts Parameter Maximum power output setting without exceeding 40.0Watts Digital Code Measure IP4HPVGPS-MRFCCRpt.doc Page 23 APPENDIX B: IP4HPV TEST DATA SHEET Data Quality Parameter Receiver 1 Data Quality
(While receiving 500 character pings from base station, 100 pings min, no errors allowed, CRC errors enabled) Receiver 2 Data Quality
(While receiving 500 character pings from base station, 100 pings min, no errors allowed, CRC errors enabled) Final Tests Uplink Final Parameter Transmit Frequency Error Transmit Modulation Deviation Uplink Hardware Timing Verified Transmit Carrier ramp up time Symbol Sync time
(Stable Amplitude to with in 100mV during the period) Recovered modulation signal Verify Sync Start
(RSSI to CS first going low) Verify Fram Sync (From end of Sync to CS second time going low) Transmit Data Quality
(While transmitting 19, 2000 character test messages to the base station) Spec 240>
240>
Spec
+/- 100 Hz
(Transmitting 19, 2000 character test message) 4.9 kHz
(while transmitting 19,2000 character test message) 2mS < X < 4mS 12ms +/- 1ms 1 V PtoP ~
2.5 VDC ~
10mS +/- 0.5 4 +/- 0.1 mS 240 >
Measured Measured IP4HPVGPS-MRFCCRpt.doc Page 24 APPENDIX B: IP4HPV TEST DATA SHEET Downlink Final Parameter Spec Measured 3.0 +/- 0.5ms 800 mV~
2.5VDC~
3.2 +/- 0.5 mS 240>
Lit 240>
Lit Completed Completed Downlink Hardware Timing Verification Sync start
(RSSI to CS first going low) Recovered Modulation Levels Frame Sync
(From end of Sync to CS second time going low) Receiver 1 Data Quality
(While receiving 500 character "pings" from base station, 100 pings min, no errors allowed, CRC errors enabled) LED Receiver 1 Receiver 2 Data Quality
(While receiving 500 character "pings" from base station, 100 pings min, no errors allowed, CRC errors enabled) LED Receiver 2 Attach copy of all firmware settings Visual inspection Copy Radio Setting below IP4HPVGPS-MRFCCRpt.doc Page 25
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2002-09-03 | 509 ~ 511.9 | TNB - Licensed Non-Broadcast Station Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2002-09-03
|
||||
1 | Applicant's complete, legal business name |
IP Mobilenet, LLC
|
||||
1 | FCC Registration Number (FRN) |
0020033890
|
||||
1 | Physical Address |
1221 East Dyer Road
|
||||
1 |
Santa Ana, California 92705
|
|||||
1 |
United States
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
d******@ckccertification.com
|
||||
1 | TCB Scope |
B2: General Mobile Radio And Broadcast Services equipment in the following 47 CFR Parts 22 (non-cellular) 73, 74, 90, 95, 97, & 101 (all below 3 GHz)
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
MI7
|
||||
1 | Equipment Product Code |
IPMNIP4
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
F****** R******
|
||||
1 | Title |
President
|
||||
1 | Telephone Number |
714-4********
|
||||
1 | Fax Number |
714-4********
|
||||
1 |
f******@ipmn.com
|
|||||
app s | Technical Contact | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
M******** C******
|
||||
1 | Physical Address |
5473A Clouds Rest
|
||||
1 |
Mariposa, California 95338
|
|||||
1 |
United States
|
|||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
209-9********
|
||||
1 |
s******@ckc.com
|
|||||
app s | Non Technical Contact | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
M**** C********
|
||||
1 | Physical Address |
5473A Clouds Rest
|
||||
1 |
Mariposa, California 95338
|
|||||
1 |
United States
|
|||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
209-9********
|
||||
1 |
s******@ckc.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | TNB - Licensed Non-Broadcast Station Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | HPV/GPS Mobile Radio | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Does not apply | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | This device must transmit with a source-based time-averaging duty factor not exceeding 55.65 %. The antenna(s) used for this transmitter must be installed to provide a separation distance of at least 76.16 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
CKC Laboratories, Inc.
|
||||
1 | Name |
S****** B****
|
||||
1 | Telephone Number |
209-9******** Extension:
|
||||
1 | Fax Number |
866-7********
|
||||
1 |
r******@ckc.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 90 | 509.00000000 | 511.90000000 | 34.0000000 | 0.4102000000 ppm | 20K0F1D |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC