all | frequencies |
|
exhibits | applications |
---|---|---|---|---|
manual |
app s | submitted / available | |||||||
---|---|---|---|---|---|---|---|---|
1 |
|
User manual | Users Manual | 1.38 MiB | ||||
1 | Cover Letter(s) | |||||||
1 | External Photos | |||||||
1 | Internal Photos | |||||||
1 | ID Label/Location Info | |||||||
1 | ID Label/Location Info | |||||||
1 | Cover Letter(s) | |||||||
1 | Cover Letter(s) | |||||||
1 | Test Report | |||||||
1 | Test Setup Photos |
1 | User manual | Users Manual | 1.38 MiB |
LBA7130 Document Title A7130 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 4Mbps data rate Revision History Rev. No. History 0.0 0.1 0.2 0.3 0.4 0.5 Initial issue. Update ch8 and the application circuit. Modify the tape reel information and the add Shenzhen office address. Add Ch20 WOR and Ch21 AES128. Add section 16.4.3 FIFO extension and Ch21 AES128. Update sleep current, Xtal start up time and PDL formula, TMOE timing, WTR Timing, and Ch14. Remove 3Mbps data rate Add descriptions for HECF, FECF and CRCF clear method in 9.2.1 Issue Date Dec, 2009 July, 2011 July, 2011 Aug., 2011 Apr., 2012 Remark Objective Preliminary, Preliminary, Preliminary, Preliminary,, Aug.,2012 Preliminary 0.6 Add suggestion in WOR function Oct. 2012 Preliminary Important Notice:
AMICCOM r eserves t he right t o make changes t o its products or to discontinue any integrated circuit product or se rvice without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support a pplications, de vices o r sys tems or ot her critical ap plications. Use of AM ICCOM products in such applications is understood to be fully at the risk of the customer. Oct., 2012, Version 0.6 (PRELIMINARY) 1 AMICCOM Electronics Corporation LBA7130 Table of Contents 1. General Description....................................................................................................................................................... 5 2. Typical Applications ....................................................................................................................................................... 5 3. Feature ......................................................................................................................................................................... 5 4. Pin Configurations......................................................................................................................................................... 6 5. Pin Description (I: input; O: output, I/O: input or output)................................................................................................... 7 6. Chip Block Diagram....................................................................................................................................................... 8 7. Absolute Maximum Ratings............................................................................................................................................ 9 8. Electrical Specification..................................................................................................................................................10 9. Control Register ...........................................................................................................................................................12 9.1 Control register table............................................................................................................................................12 9.2 Control register description ..................................................................................................................................15 9.2.1 Mode Register (Address: 00h)....................................................................................................................15 9.2.2 Mode Control Register (Address: 01h)......................................................................................................15 9.2.3 Calibration Control Register (Address: 02h)..............................................................................................16 9.2.4 FIFO Register I (Address: 03h).................................................................................................................16 9.2.5 FIFO Register II (Address: 04h)................................................................................................................16 9.2.6 FIFO DATA Register (Address: 05h) .........................................................................................................16 9.2.7 ID DATA Register (Address: 06h)................................................................................................................16 9.2.8 RC OSC Register I (Address: 07h) .............................................................................................................17 9.2.9 RC OSC Register II (Address: 08h).............................................................................................................17 9.2.10 RC OSC Register III (Address: 09h)..........................................................................................................17 9.2.11 CKO Pin Control Register (Address: 0Ah) .................................................................................................17 9.2.12 GIO1 Pin Control Register I (Address: 0Bh)...............................................................................................18 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) .............................................................................................20 9.2.14 Clock Register (Address: 0Dh)..................................................................................................................21 9.2.15 PLL Register I (Address: 0Eh)...................................................................................................................21 9.2.16 PLL Register II (Address: 0Fh)..................................................................................................................21 9.2.17 PLL Register III (Address: 10h).................................................................................................................22 9.2.18 PLL Register IV (Address: 11h).................................................................................................................22 9.2.19 PLL Register V (Address: 12h)...............................................................................................................22 9.2.20 Channel Group Register I (Address: 13h)..................................................................................................22 9.2.21 Channel Group Register II (Address: 14h).................................................................................................22 9.2.22 TX Register I (Address: 15h).....................................................................................................................23 9.2.23 TX Register II (Address: 16h)....................................................................................................................23 9.2.24 Delay Register I (Address: 17h) ................................................................................................................23 9.2.25 Delay Register II (Address: 18h) ...............................................................................................................24 9.2.26 RX Register (Address: 19h)......................................................................................................................24 9.2.27 RX Gain Register I (Address: 1Ah)............................................................................................................25 9.2.28 RX Gain Register II (Address: 1Bh)...........................................................................................................25 9.2.29 RX Gain Register III (Address: 1Ch) .........................................................................................................25 9.2.30 RX Gain Register IV (Address: 1Dh).........................................................................................................26 9.2.31 RSSI Threshold Register (Address: 1Eh) ..................................................................................................26 9.2.32 ADC Control Register (Address: 1Fh)........................................................................................................26 9.2.33 Code Register I (Address: 20h).................................................................................................................26 9.2.34 Code Register II (Address: 21h)................................................................................................................27 9.2.35 Code Register III (Address: 22h)...............................................................................................................27 9.2.36 IF Calibration Register I (Address: 23h).....................................................................................................27 9.2.37 IF Calibration Register II (Address: 24h)....................................................................................................28 9.2.38 VCO current Calibration Register (Address: 25h).......................................................................................28 9.2.39 VCO band Calibration Register I (Address: 26h)........................................................................................28 9.2.40 VCO band Calibration Register II (Address: 27h).......................................................................................29 9.2.41 VCO Deviation Calibration Register I (Address: 28h) .................................................................................29 9.2.42 VCO Deviation Calibration Register II (Address: 29h)................................................................................29 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) ........................................................................................30 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1) .........................................................................................30 Oct., 2012, Version 0.6 (PRELIMINARY) 2 AMICCOM Electronics Corporation LBA7130 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) .........................................................................................30 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) .........................................................................................31 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) .........................................................................................31 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5) .........................................................................................31 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6) .........................................................................................31 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7) .........................................................................................31 9.2.44 VCO Modulation Delay Register (Address: 2Bh)........................................................................................31 9.2.45 Battery detect Register (Address: 2Ch).....................................................................................................32 9.2.46 TX test Register (Address: 2Dh) ...............................................................................................................32 9.2.47 Rx DEM test Register I (Address: 2Eh) .....................................................................................................32 9.2.48 Rx DEM test Register II (Address: 2Fh).....................................................................................................33 9.2.49 Charge Pump Current Register I (Address: 30h) .......................................................................................33 9.2.50 Charge Pump Current Register II (Address: 31h).......................................................................................33 9.2.51 Crystal test Register (Address: 32h)..........................................................................................................33 9.2.52 PLL test Register (Address:33h) ...............................................................................................................34 9.2.53 VCO test Register I (Address:34h)............................................................................................................34 9.2.54 RF Analog Test Register (Address: 35h)....................................................................................................34 9.2.55 AES Key data Register (Address: 36h)......................................................................................................35 9.2.56 Channel Select Register (Address: 37h)....................................................................................................35 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0).........................................................................................35 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1).........................................................................................35 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2).........................................................................................36 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3).........................................................................................36 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4).........................................................................................36 9.2.58 Data Rate Clock Register (Address: 39h)..................................................................................................36 9.2.59 FCR Register (Address: 3Ah) ...................................................................................................................36 9.2.60 ARD Register (Address: 3Bh) ...................................................................................................................37 9.2.61 AFEP Register (Address: 3Ch)..................................................................................................................37 9.2.62 FCB Register (Address: 3Dh) ...................................................................................................................37 9.2.63 KEYC Register (Address: 3Eh) .................................................................................................................38 9.2.64 USID Register (Address: 3Fh) ..................................................................................................................38 10. SPI.............................................................................................................................................................................39 10.1 SPI Format ........................................................................................................................................................40 10.2 SPI Timing Characteristic...................................................................................................................................40 10.3 SPI Timing Chart................................................................................................................................................41 10.3.1 Timing Chart of 3-wire SPI........................................................................................................................41 10.3.2 Timing Chart of 4-wire SPI........................................................................................................................41 10.4 Strobe Commands.............................................................................................................................................42 10.4.1 Strobe Command - Sleep Mode................................................................................................................42 10.4.2 Strobe Command - ldle Mode ...................................................................................................................42 10.4.3 Strobe Command - Standby Mode ............................................................................................................43 10.4.4 Strobe Command - PLL Mode...................................................................................................................43 10.4.5 Strobe Command - RX Mode....................................................................................................................44 10.4.6 Strobe Command - TX Mode ....................................................................................................................44 10.4.7 Strobe Command FIFO Write Pointer Reset ...........................................................................................44 10.4.8 Strobe Command FIFO Read Pointer Reset...........................................................................................45 10.4.9 Strobe Command Deep Sleep Mode......................................................................................................45 10.5 Reset Command................................................................................................................................................46 10.6 ID Accessing Command.....................................................................................................................................46 10.6.1 ID Write Command...................................................................................................................................46 10.6.2 ID Read Command ..................................................................................................................................47 10.7 FIFO Accessing Command.................................................................................................................................47 10.7.1 TX FIFO Write Command .........................................................................................................................47 10.7.2 Rx FIFO Read Command.........................................................................................................................48 11. State machine.............................................................................................................................................................49 11.1 Key states..........................................................................................................................................................49 11.2 FIFO mode ........................................................................................................................................................50 11.3 Direct mode .......................................................................................................................................................51 12. Crystal Oscillator ........................................................................................................................................................54 12.1 Use External Crystal ..........................................................................................................................................54 Oct., 2012, Version 0.6 (PRELIMINARY) 3 AMICCOM Electronics Corporation LBA7130 12.2 Use External Clock ............................................................................................................................................54 13. System Clock .............................................................................................................................................................55 13.2 Data Rate Setting ..............................................................................................................................................55 14. Transceiver LO Frequency..........................................................................................................................................56 14.1 LO Frequency Setting ........................................................................................................................................56 14.2 IF Side Band Select ...........................................................................................................................................57 14.2.1 Auto IF Exchange.....................................................................................................................................58 14.2.2 Fast Exchange.........................................................................................................................................59 14.3 Auto Frequency Compensation...........................................................................................................................60 15. Calibration..................................................................................................................................................................60 15.1 Calibration Procedure ........................................................................................................................................60 16. FIFO (First In First Out)...............................................................................................................................................61 16.1 TX Packet Format in FIFO mode........................................................................................................................61 16.1.1 Basic FIFO mode.....................................................................................................................................61 16.1.2 Advanced FIFO mode...............................................................................................................................61 16.2 Bit Stream Process in FIFO mode.......................................................................................................................62 16.3 Transmission Time.............................................................................................................................................63 16.4 Usage of TX and RX FIFO .................................................................................................................................63 16.4.1 Easy FIFO ...............................................................................................................................................64 16.4.2 Segment FIFO .........................................................................................................................................65 16.4.3 FIFO Extension........................................................................................................................................67 17. ADC (Analog to Digital Converter) ...............................................................................................................................71 17.1 RSSI Measurement............................................................................................................................................71 18. Battery Detect ............................................................................................................................................................73 19. Auto-ack and auto-resend...........................................................................................................................................74 19.1 Basic FIFO plus auto-ack auto-resend................................................................................................................74 19.2 Advanced FIFO plus auto-ack and auto-resend...................................................................................................74 19.3 WTR Behavior during auto-ack and auto-resend.................................................................................................76 19.6 Examples of auto-ack and auto-resend...............................................................................................................77 20. RC Oscillator..............................................................................................................................................................79 20.1 WOR Function...................................................................................................................................................79 20.2 TWOR Function.................................................................................................................................................80 21. AES128 Security Packet .............................................................................................................................................80 22. Application circuit........................................................................................................................................................81 22.1 MD7130-A01 .....................................................................................................................................................81 22.2 MD7130-F07 .....................................................................................................................................................82 23. Abbreviations..............................................................................................................................................................83 24. Ordering Information...................................................................................................................................................83 25. Package Information...................................................................................................................................................84 26. Top Marking Information..............................................................................................................................................85 27. Reflow Profile.............................................................................................................................................................86 28. Tape Reel Information.................................................................................................................................................87 29. Product Status............................................................................................................................................................89 Oct., 2012, Version 0.6 (PRELIMINARY) 4 AMICCOM Electronics Corporation LBA7130 1. General Description A7130 is a high performance and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity receiver (- 88dBm @4Mbps) and programmable power amplifier 5dBm. Based on Data Rate Register (39h), user can configure on-air data rates to 4Mbps. A7130 supports fast settling time (90 us) for frequency hopping system. For packet handling, A7130 has built-in separated 64-bytes TX/ RX FIFO (could be logically extended t o 4K b ytes) for da ta buffering and bu rst transmission, aut o-ack a nd auto-resend, CRC for error packet filtering, FEC for 1-bit data correction per code word, RSSI for clear channel assessment, thermal sensor for monitoring relative temperature, WOR (Wake on RX) function to support periodically wake up from sleep mode to RX mode and listen for incoming packets without MCU interaction, data whitening for data encryption / decryption. In addition, A7130 ha s bu ilt-in AES128 co -processor (Adva nced Encr yption St andard) for advan ced dat a e ncryption and decryption which consists of the transformation of a 128-bit block into an encrypted 128-bit block. Those functions are very easy to use while developing a wireless system. All features are integrated in a small QFN 4X4 20 pins package. A7130s control registers ar e a ccessed via 3- wire o r 4-wire S PI interface s uch as TX/RF FIFO, ID r egister, RSSI value, frequency hopping to chip calibration procedures. Another one, via SPI as well, is the unique Strobe command, A7130 can be controlled from power saving mode (deep s leep, sl eep, idle, standby), PLL mode, TX mode and RX mode. The other connections between A7130 and MCU are GIO1 and GIO2 (multi-function GPIO) to output A7130s status so that MCU could use either polling or int errupt scheme for radio control. Overall, this de vice is very easy-to-use for developing a w ireless application with a MCU. 2. Typical Applications n 2.4GHz video baby monitor n 2.4GHz PC peripherals n HiFi quality wireless audio streaming 3. Feature n 2408 ~ 2468 MHz ISM system n Wireless metering and building automation n Wireless toys and game controllers n n n n n n n n n n n n n n n n n n
-88dBm at 4Mbps on-air data rate. Small size (QFN4 X4, 20 pins). Frequency band: 2408 ~ 2468MHz. FSK or GFSK modulation Low current consumption: RX 27mA (4Mbps), TX 29mA (at 5dBm output power). Deep sleep current (0.1 uA). Sleep current (2.5 uA). On chip regulator, support input voltage 2.0 ~ 3.6 V. Data rate 4Mbps. Programmable TX power level from 5 dBm. Ultra High sensitivity:
u Fast settling time (90 us) synthesizer for frequency hopping system. On chip low power RC oscillator for WOR (Wake on RX) function. Built-in AES128 co-processor AGC (Auto Gain Control) for the wide RSSI dynamic range. AFC (Auto Frequency Compensation) for frequency drift due to temperature. Support low cost crystal (16 / 18 MHz). Low Battery Detector indication. Easy to use. u u Unique Strobe command via SPI. u ONE register setting for new channel frequency. u CRC Error Packet Filtering. u u Dynamic FIFO length. u u 8-bits RSSI measurement for clear channel indication. Auto Calibrations. Auto-acknowledgement and auto-resend. Support 3-wire or 4-wire SPI. Oct., 2012, Version 0.6 (PRELIMINARY) 5 AMICCOM Electronics Corporation LBA7130 u u u u u u Auto IF function. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 4K bytes). Support FIFO mode frame sync to MCU. Support direct mode with recovery clock output to MCU. 4. Pin Configurations RSSI BP_BG RFI RFO RFC 1 2 3 4 5 A _ D D V I G E R O K C 2 O G I 1 O G I 0 2 9 1 8 1 7 1 6 1 15 14 13 12 0 6 7 8 9 1 11 O C V _ V P C L L P _ V I X O X GND SDIO VDD_D SCK SCS Fig 4-1. A7130 QFN 4x4 Package Top View Oct., 2012, Version 0.6 (PRELIMINARY) 6 AMICCOM Electronics Corporation 5. Pin Description (I: input; O: output, I/O: input or output) LBA7130 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol RSSI BP_BG RFI RFO RFC V_VCO CP V_PLL XI XO SCS SCK VDD_D SDIO GND GIO1 GIO2 CKO REGI VDD_A Function Description LNA input. Connected to matching circuit. PA input. Connected to matching circuit. RF Choke input. Connected to matching circuit. VCO supply voltage input. I/O O Connected to a bypass capacitor for RSSI. O Connected to a bypass capacitor for internal Regulator bias point. I O I I O Charge-pump. Connected to loop filter. PLL supply voltage input. I Crystal oscillator input. I O Crystal oscillator output. I I I I/O SPI read/write data. G G round I/O Multi-function GIO1 / 4-wire SPI data output. I/O Multi-function GIO2 / 4-wire SPI data output. O I O SPI chip select. SPI clock input pin. Connected to a bypass capacitor to supply voltage for digital part. Multi-function clock output. Regulator input (External Power Input) Internal Regulator output to supply V_VCO (pin 6), V_PLL (pin 8) and RFC (pin 5). Ground. Back side plate shall be well-solder to ground; otherwise, it will impact RF performance. Back side plate G Oct., 2012, Version 0.6 (PRELIMINARY) 7 AMICCOM Electronics Corporation LBA7130 6. Chip Block Diagram Fig 6-1. A7130 Block Diagram Oct., 2012, Version 0.6 (PRELIMINARY) 8 AMICCOM Electronics Corporation LBA7130 7. Absolute Maximum Ratings Parameter With respect to Supply voltage range (VDD) Digital IO pins range Voltage on the analog pins range Input RF level Storage Temperature range ESD Rating GND GND GND HBM MM Rating
-0.3 ~ 3.6
-0.3 ~ VDD+0.3
-0.3 ~ 2.1 10
-55 ~ 125 2K 100 Unit V V V dBm C V V
*Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
*Device is ESD sensitive. Use appropriate ESD precautions. HBM (Human Body Mode) is tested under MIL-STD-883F Method 3015.7. MM (Machine Mode) is tested under JEDEC EIA/JESD22-A115-A.
*Device is Moisture Sensitivity Level III (MSL 3). Oct., 2012, Version 0.6 (PRELIMINARY) 9 AMICCOM Electronics Corporation LBA7130 8. Electrical Specification
(Ta=25, VDD=3.3V, FXTAL =16MHz, with Match circuit and low pass filter, On Chip Regulator = 1.8V, unless otherwise noted.) Parameter General Operating Temperature Supply Voltage (VDD) Current Consumption Current Consumption
(DBL =0 at 0Fh, bit7) PLL block Crystal start up time*2
(3225 SMD type) Crystal frequency Crystal tolerance Crystal ESR VCO Operation Frequency PLL phase noise PLL settling time*3 Transmitter Output power range Out Band Spurious Emission *4 Frequency deviation*5 Data rate TX ready time*6 Receiver Receiver sensitivity
@ BER = 0.1%
Description Min. Type Max. Unit
-40 2.0 with internal regulator Deep Sleep mode*1
(No registers retention) Sleep mode (WOR off) *1 Sleep mode (WOR on) *1 Idle Mode (Regulator on) *1 Standby Mode
(XOSC on, CLK Gen. on) PLL mode RX Mode (4Mbps) TX Mode (5dBm) TX Mode (3dBm) TX Mode (0dBm) TX Mode ( -5dBm) TX Mode ( -17dBm) Idle to standby
(Xtal osc. is stable at 20ppm) Idle to standby
(Xtal osc. is stable at 10ppm) Data rate: 4Mbps Data rate: 4M/bps 2408 Offset 10k Offset 500K Offset 1M Loop filter based on app. circuit.
(Standby to PLL) 3.3 0.1 2.5 3.5 0.3 2.7 12.5 27 29 24 20 18 16 1 2 16 50 75 90 100 30 30MHz~1GHz 1GHz~12.75GHz 1.8GHz~ 1.9GHz 5.15GHz~ 5.3GHz Data rate 4Mbps Standby to TX Data rate 4Mbps Data rate 4Mbps (GFSK)
-17 0 1M 4M 90
-88
-85 85 3.6 80 2468 5
-36
-30
-47
-47 C V mA mA mA mA mA mA mA mA mA mA mA mA ms ms MHz ppm ohm MHz dBc mS dBm dBm dBm dBm dBm Hz bps mS dBm Oct., 2012, Version 0.6 (PRELIMINARY) 10 AMICCOM Electronics Corporation LBA7130 IF Filter bandwidth IF center frequency Interference *7
(4Mbps , IF = 4MHz) Maximum Operating Input Power RX Spurious Emission *4 RSSI Range RX Ready Time Regulator Regulator settling time Band-gap reference voltage Regulator output voltage Digital IO DC characteristics High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Output Voltage (VOH) Low Level Output Voltage (VOL) IFS = [11], 4Mbps IFS = [11], 4Mbps Co-Channel (C/I0) 4MHz Adjacent Channel 8MHz Adjacent Channel 12MHz Adjacent Channel 16MHz Adjacent Channel Image (C/IIM)
@RF input (BER=0.1%) 30MHz~1GHz 1GHz~12.75GHz AGC = 0 AGC = 1 Pin 2 connected to 470pF.
(Sleep to idle).
@IOH= -0.5mA
@IOL= 0.5mA 4.8M 4M 11 0
- 10
- 20
- 30
- 10 80 0.5 1.28 1.8 Hz Hz dB dB dB dB dB dB dBm dBm dBm dBm ms ms V V V V V V 5
-57
-47
-50
-20 2.3 VDD 0.2*VDD VDD 0.4
-95
-95 1.79 0.8*VDD 0 VDD-0.4 0 be pulled high only); otherwise, leakage current will be induced. Note 1: When digital I/O pins are configured as input, those pins shall NOT be floating but pull either high or low (SCS shall Note 2: Xtal settling time is depend on Xtal package type, Xtal ESR and Xtal Cm. Note 3: Refer to Delay Register I (17h) to set PDL (PLL settling delay). Note 4: With external RF filter that provides minimum 17dB of attenuation in the band: 30MHz ~ 2GHz and 3GHz ~12.75GHz. Note 5: Refer to TX Register II (16h) to set FD [7:0]. Note 6: Refer to Delay Register I (17h) to set PDL and TDL. Note 7: The wanted signal is set above sensitivity level +3dB. The modulation data of wanted signal and interferer are PN9 and PN15, respectively. Oct., 2012, Version 0.6 (PRELIMINARY) 11 AMICCOM Electronics Corporation LBA7130 9. Control Register A7130 contains 69 control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire (SCS, SCK, SDIO, GIO1/GIO2) SPI interface (max. 15 Mbps). Please refer to Chapter 10 for SPI timing. In general, most of control registers are just need to configure the recommended values based on A7130 reference code. 9.1 Control register table R/W W R W R R/W W R W R W R/W R/W W R W W W W R Address /
Name 00h Mode 01h 02h Calc Mode control 03h FIFO I 04h FIFO II 05h FIFO Data 06h ID Data RC OSC I 07h 08h RC OSC II 09h RC OSC III CKO Pin 0Ah 0Bh 0Ch GPIO1 Pin I GPIO2 Pin II 0Dh Clock 0Eh PLL I 0Fh PLL II 10h PLL III 11h PLL IV 12h PLL V 13h 15h TX I Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESETN RESETN RESETN HECF DDPC DDPC RESETN FECF ARSSI ARSSI RESETN CRCF AIF AIF
FEP7 LENF7 FPM1 FIFO7 ID7
FEP6 LENF6 FPM0 FIFO6 ID6
FEP5 LENF5 PSA5 FIFO5 ID5 CER DFCD CD VCC
FEP4 LENF4 PSA4 FIFO4 ID4 XER WORE WORE VBC FEP11 LENF11 FEP3 LENF3 PSA3 RESETN PLLER FMT FMT VDC FEP10 LENF10 FEP2 LENF2 PSA2 RESETN RESETN TRSR FMS FMS FBC FEP9 LENF9 FEP1 LENF1 PSA1 TRER ADCM ADCM RSSC FEP8 LENF8 FEP0 LENF0 PSA0 FIFO3 FIFO2 FIFO1 FIFO0 ID3 ID2 ID1 ID0 W WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 R RCOC0 RCOC7 RCOC6 RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 RTCS RCOT2
RCOT1/
RTCC1
RCOT0/
RTCC0
ECKOE CKOS3 CKOS2 CKOS1 CALWC RCOSC_E CALWR CKOS0 CKOI
TSEL
CKOE TWORE
SCKI VKM VPM GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1I GIO1OE BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 GRC2 GRC2 GRC1 GRC1 GRC0 GRC0 GIO2I CGS
CHN7 DBL DBL BIP7 IP7 CHN4 CHR3 CHR3 BIP4 IP4 CHN5 RRC0 RRC0 BIP5 IP5 CHN6 RRC1 RRC1 BIP6 IP6 CHN3 CHR2 CHR2 BIP3 IP3 R/W W R W R W R FS YN-FP15 AC14-FP14 AC13-FP13 AC12-FP12 AC11-FP11 AC10-FP10 AC9-FP9 W R Channel Group I R/W Channel Group II R/W CHGH7 GDR CHN1 CHR0 CHR0 BIP1 IP1 BFP9 CHN2 CHR1 CHR1 BIP2 IP2 AC7-FP7 AC6-FP6 AC1-FP1 AC5-FP5 AC4-FP4 AC3-FP3 AC2-FP2 TMDE CHGH6 CHGH5 CHGH4 CHGH3 CHGH2 CHGH1 CHGL6 CHGL5 CHGL4 CHGL3 CHGL2 CHGL7 CHGL1 FDP2 FDP1 BFP12 BFP10 BFP15 BFP14 BFP13 BFP11 TXDI TME BFP4 BFP1 BFP6 BFP3 BFP2 BFP7 BFP5 14h GF W GIO2OE XS
CHN0 BIP8 IP8 BIP0 IP0 BFP8 AC8-FP8 BFP0 AC0-FP0 CHGL0 CHGH0 FDP0 Oct., 2012, Version 0.6 (PRELIMINARY) 12 AMICCOM Electronics Corporation LBA7130 FD7 FD6 FD5 DPR2 DPR1 DPR0 FD4 TDL1 FD3 TDL0 FD2 PDL2 FD1 PDL1 FD0 PDL0 WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 CRCINV WS6 WS5 CKGS1 CKGS0 16h TX II 17h Delay I 18h Delay II 19h RX 1Ah 1Bh 1Ch 1Dh RX Gain I RX Gain II RX Gain III RX Gain IV 1Eh RSSI Threshold 1Fh ADC Control 20h Code I 21h Code II 22h Code III 23h IF Calibration I IF Calibration II 24h 25h VCO current Calibration VCO band Calibration I 26h 27h VCO band Calibration II VCO deviation Calibration I 28h 29h VCO deviation Calibration II 2Ah DASP0 DASP1 DASP2 DASP3 DASP4 DASP5 DASP6 W W W W W R W R W R W W R W W W W W R W R W R W R W R W R W R W W W W W R W LNAGE PRS
AGCE MIC MICR RSAGC1 RSAGC0 RH7
RL7 LIMC RTH7 ADC7 AVSEL1 MCS MSCRC RH6 RDU RL6 IFBC1 RTH6 ADC6 AVSEL0 WHTS EDRL TRT2
RSIS
DCD0
MDAG6 ADAG6 DEVS2 DEVA6 MDEV6 ADEV6 RFSP CELS HFR
PWORS
ROSCS
DCD1
MDAG7 ADAG7 DEVS3 DEVA7 MVDS ADEV7 QLIM STS DCV7 VMG7 VMG7
RXSM1 RXSM0 AFCE IGC1 IGCR1 VTL2 RH5 IFS1 RL5 IFBC0 RTH5 ADC5 MVSEL1 FECS HECS TRT1
VCRLS
DAGS
MDAG5 ADAG5 DEVS1 DEVA5 MDEV5 IGC0 IGCR0 VTL1 RH4 IFS0 RL4 IFAS RTH4 ADC4 MVSEL0 CRCS ETH2 WS4 MFBS FBCF TRT0 FCD4 MVCS VCCF CWS
MDAG4 ADAG4 DEVS0 DEVA4 MDEV4 MGC1 MGCR1 VTL0 RH3 RSM1 RL3 MHC1 RTH3 ADC3 RADC IDL1 ETH1 WS3 MFB3 FB3 ASMV2 FCD3 VCOC3 VCB3 MVBS VBCF MDAG3 ADAG3 DAMR_M DEVA3 MDEV3 RXDI MGC0 MGCR0 VTH2 RH2 RSM0 RL2 MHC0 RTH2 ADC2 FSARS IDL0 ETH0 WS2 MFB2 FB2 ASMV1 FCD2 VCOC2 VCB2 MVB2 VB2 MDAG2 ADAG2 VMTE_M DEVA2 MDEV2 ADEV2 DMG LGC1 LGCR1 VTH1 RH1 ERSSM RL1 LHC1 RTH1 ADC1 XADS PML1 ULS LGC0 LGCR0 VTH0 RH0 RSS RL0 LHC0 RTH0 ADC0 CDM PML0 PMD1 PMD0 WS1 MFB1 FB1 ASMV0 FCD1 VCOC1 VCB1 MVB1 VB1 MDAG1 ADAG1 VMS_M DEVA1 MDEV1 ADEV1 WS0 MFB0 FB0 AMVS FCD0 VCOC0 VCB0 MVB0 VB0 MDAG0 ADAG0 MSEL DEVA0 MDEV0 ADEV0 CSXTL2 CSXTL1 CSXTL0 VRPL1 VMRB2 VRPL0 VMRB1 INTPRC VMRB0 ADEV4 ADEV5 ADEV3 INTRC
(CSXTL5) CSXTL4 CSXTL3 RGC0 VMRB3 RGS VTRB1 RGC1 VTRB0 VTRB3 VTRB2 DCV6 VMG6 VMG6
HPLS DCV5 VMG5 VMG5 PKT1 HRS DCV4 VMG4 VMG4 PKT0 PACTL DCV3 VMG3 VMG3 PKS IWS DCV2 VMG2 VMG2 PKIS1 CNT DCV1 VMG1 VMG1 PKIS0 MXD DCV0 VMG0 VMG0 IFPK LXD W --
Oct., 2012, Version 0.6 (PRELIMINARY) 13 AMICCOM Electronics Corporation LBA7130 W W R W W W W W W W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 LVR
RMP1 DMT DCH1 RGV1 RGV1 RMP0 DCM1 DCH0 RGV0 RGV0 TXCS DCM0 DCL2 QDS BDF PAC1 MLP1 DCL1 BVT2 BVT2 PAC0 MLP0 DCL0 BVT1 BVT1 TBG2 SLF2 RAW BVT0 BVT0 TBG1 SLF1 BD_E BD_E TBG0 SLF0 CDTM1 CDTM0 CPM3 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 CPTX3 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 CDPM MDEN CPS OLM CPH CPCS DBD XCC XCP1 XCP0 PRIC1 PRIC0 PRRC1 PRRC0 SDPW NSDO W DEVGD2 DEVGD1 DEVGD0 AGT2 KEY6 CHI2 EPRG MPA1 PTM0
STMP SDR6 FCL0 VPOAK ARD6 SPSS
F6 W AGT3 W/R KEY7 CHI3 MPOR APG PTM1
SDR7 FCL1 ARTEF ARD7 EACKF
F7 W W W W W W W W R W W R W/R W W TLB1 AGT0 KEY4 CHI0 MRGS FBG4 CTR4 CRS1 STM4 TLB0 RFT3 KEY3 CHD3 MRSS FBG3 CTR3 CRS0 STM3 RLB1 RFT2 KEY2 CHD2 MTMS FBG2 CTR2 CTS2 STM2 RLB0 RFT1 KEY1 CHD1 MADS FBG1 CTR1 CTS1 STM1 VBS RFT0 KEY0 CHD0 MBGS FBG0 CTR0 CTS0 STM0 AGT1 KEY5 CHI1 MIGS MPA0 CTR5 CRS2 STM5 SDR5 ARC3 RCR3 ARD5 ACKFEP5 EARTS SDR4 ARC2 RCR2 ARD4 ACKFEP4 EARTS F5 F4 SDR3 ARC1 RCR1 ARD3 ACKFEP3 EARTS F3 AESS RND3 SDR2 ARC0 RCR0 ARD2 ACKFEP2 TXSID2 F2
SDR0 EARTS EARTS ARD0 SDR1 EACKS EACKS ARD1 ACKFEP1 ACKFEP0 TXSID1 TXSID0 F1 F0 AKFS EDCRS RND2 RND1 RND0 MEDCS AFIDS ARTMS MIDS RND7 RND6 RND5 RND4 VCO modulation Battery detect 2Bh Delay 2Ch 2Dh TX test 2Eh Rx DEM test I Rx DEM test II Charge Pump Current I Charge Pump Current II Crystal test PLL test VCO test 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h RF Analog test Key Data Channel Select ROM_P0 ROMP1 ROMP2 ROMP3 ROMP4 39h Data Rate CLK 3Ah FCR 3Bh ARD 3Ch AFEP 3Dh FCB 3Eh KEYC 3Fh USID Legend: -- = unimplemented Oct., 2012, Version 0.6 (PRELIMINARY) 14 AMICCOM Electronics Corporation LBA7130 9.2 Control register description 9.2.1 Mode Register (Address: 00h) Name Mode Bit 0 R/W Bit 7 TRER HECF R W RESETN RESETN RESETN RESETN RESETN RESETN RESETN RESETN Bit 2 PLLER Bit 5 CRCF Bit 1 TRSR Bit 6 FECF Bit 4 CER Bit 3 XER RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear HECF: Head Control Flag. (HECF will be clear after issue a strobe command.) HEC is CRC-8 result for the optional Packet Header (Please refer to chapter 16 for details)
[0]: HEC pass. [1]: HEC error. FECF: FEC flag. (FECF will be clear after issue any strobe command.)
[0]: FEC pass. [1]: FEC error. CRCF: CRC flag. (CRCF will be clear after issue any strobe command.)
[0]: CRC pass. [1]: CRC error. CER: RF chip enable status.
[0]: RF chip is disabled. [1]: RF chip is enabled. XER: Internal crystal oscillator enabled status.
[0]: Crystal oscillator is disabled. [1]: Crystal oscillator is enabled. PLLE: PLL enabled status.
[0]: PLL is disabled. [1]: PLL is enabled. TRER: TRX state enabled status.
[0]: TRX is disabled. [1]: TRX is enabled. TRSR: TRX Status Register.
[0]: RX state. [1]: TX state. Serviceable if TRER=1 (TRX is enable). 9.2.2 Mode Control Register (Address: 01h) Name Mode Control I R/W Bit 7 R DDPC DDPC W Bit 6 ARSSI ARSSI Bit 5 AIF AIF Bit 4 DFCD CD Bit 3 WORE WORE Bit 2 FMT FMT Bit 1 FMS FMS Bit 0 ADCM ADCM DDPC (Direct mode data pin control): Direct mode modem data can be accessed via SDIO pin.
[0]: Disable. [1]: Enable. ARSSI: Auto RSSI measurement while entering RX mode.
[0]: Disable. [1]: Enable. AIF (Auto IF Offset): RF LO frequency will auto offset one IF frequency while entering RX mode.
[0]: Disable. [1]: Enable. CD: Carrier detector (Read only).
[0]: Input power below threshold. [1]: Input power above threshold. DFCD: Data Filter by CD : The received packet would be filtered if the input power level is below RTH (1Eh).
[0]: Disable. [1]: Enable. WORE: WOR (Wake On RX) Function Enable.
[0]: Disable. [1]: Enable. FMT: Reserved for internal usage only. Shall be set to [0]. FMS: Direct/FIFO mode select.
[0]: Direct mode. [1]: FIFO mode. ADCM: ADC measurement enable (Auto clear when done).
[0]: Disable measurement or measurement finished. [1]: Enable measurement. Refer to chapter 17 for details. Oct., 2012, Version 0.6 (PRELIMINARY) 15 AMICCOM Electronics Corporation 9.2.3 Calibration Control Register (Address: 02h) Bit 5 Name Bit 6 Mode Control II
R/W Bit 7 R/W
LBA7130 Bit 4 VCC Bit 3 VBC Bit 2 VDC Bit 1 FBC Bit 0 RSSC VCC: VCO Current calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. VBC: VCO Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. FBC: IF Filter Bank calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. RSSC: RSSI calibration enable (Auto clear when done).
[0]: Disable. [1]: Enable. 9.2.4 FIFO Register I (Address: 03h) Bit 15 Name FIFO I R/W W R W R Bit 14 Bit 13 Bit 12
FEP7 LENF7 FEP6 LENF6 FEP5 LENF5 FEP4 LENF4 Bit 10 Bit 11 FEP10 FEP11 LENF11 LENF10 FEP2 FEP3 LENF3 LENF2 Bit 9 FEP9 LENF9 FEP1 LENF1 Bit 8 FEP8 LENF8 FEP0 LENF0 FEP [11:0]: FIFO End Pointer for TX FIFO and Rx FIFO. Data Sequence is FEP[7:0] and FEP[15:8]. Please refer to chapter 16 for details. LENF [11:0]: Received FIFO Length for dynamic FIFO function. (Ready Only) When EDRL =1, that means dynamic FIFO is enabled, MCU can read LENF [11:0] to know the RX FIFO length of the coming packet. Please refer to chapter 16 for details. 9.2.5 FIFO Register II (Address: 04h) Name FIFO II R/W W Bit 7 FPM1 Bit 6 FPM0 Bit 5 PSA5 Bit 4 PSA4 Bit 3 PSA3 Bit 2 PSA2 Bit 1 PSA1 Bit 0 PSA0 FPM [1:0]: FIFO Pointer Margin PSA [5:0]: Used for Segment FIFO. Refer to chapter 16 for details. 9.2.6 FIFO DATA Register (Address: 05h) Bit 6 Bit 7 Bit Name R/W W R/W FIFO [7:0]: TX FIFO / RX FIFO TX FIFO and RX FIFO share the same address (05h). TX FIFO and RX FIFO are separated physical 64 Bytes. Refer to chapter 16 for details. Bit 5 Bit 3 Bit 4 TX-FIFO[7:0]
RX-FIFO[7:0]
Bit 2 Bit 1 Bit 0 9.2.7 ID DATA Register (Address: 06h) Name ID DATA R/W Bit 7 ID7 R/W Bit 6 ID6 Bit 5 ID5 Bit 4 ID4 Bit 3 ID3 Bit 2 ID2 Bit 1 ID1 Bit 0 ID0 ID [7:0]: ID data. When this address is accessed, ID Data is input or output sequential (ID Byte 0,1, 2 and 3) corresponding to Write or Read. Oct., 2012, Version 0.6 (PRELIMINARY) 16 AMICCOM Electronics Corporation Recommend to set ID Byte 0 = 5xh or Axh. Refer to section 10.6 for details. LBA7130 9.2.8 RC OSC Register I (Address: 07h) Bit 6 RCOC6 Name RC OSC I R/W Bit 7 RCOC7 R W WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 Bit 2 RCOC2 Bit 0 RCOC0 Bit 5 RCOC5 Bit 4 RCOC4 Bit 3 RCOC3 Bit 1 RCOC1 RCOC [7:0]: Reserved for internal usage (read only). 9.2.9 RC OSC Register II (Address: 08h) Bit 6 Name RC OSC II R/W Bit 7 W WOR_SL9 WOR_SL8 WOR_AC5 WOR_AC4 WOR_AC3 WOR_AC2 WOR_AC1 WOR_AC0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WOR_AC [5:0]: 6-bits WOR Active Timer for WOR and TWOR Function WOR_SL [9:0]: 10-bits WOR Sleep Timer for WOR and TWOR Function. WOR_SL [9:0] are from address (07h) and (08h), Active period = (WOR_AC+1) x (1/4092). Sleep period = (WOR_SL+1) x (1/32) x (1/4092). 9.2.10 RC OSC Register III (Address: 09h) Name RC OSC III R/W Bit 7 W R
RTCS RCO Bit 6 T2
Bit 5 RCOT1/
RTCC1
Bit 4 RCOT0/
RTCC0
Bit 2 Bit 3 CALWC RCOSC_E CALWR
Bit 1 TSEL
Bit 0 TWORE
RTCS: internal Oscillator selection in sleep mode. Recommend RTCS= [0].
[0]: RC oscillator. [1]: RTC oscillator. RCOT[2:0]: Reserved for internal used. Recommend RCOT= [000]. RCOT[1:0]: RCOSC current select for RC oscillator calibration.
[00]: 240nA [01]: 280nA [10]: 320nA [11]: 360nA TSEL: Timer select for TWOR function.
[0]: Use WOR_AC. [1]: Use WOR_SL. CALWC: RC Oscillator Calibration Enable.
[0]: Disable. [1]: Enable. CALWR: RC Oscillator Calibration ending indication.
[0]: ending. [1]: Not ending. RCOSC_E: RC-oscillator enable.
[0]: Disable. [1]: Enable. TSEL: Timer Duty select for TWOR function.
[0]: Use WOR_AC. [1]: Use WOR_SL. TWORE: Enable TWOR function.
[0]: WOR mode. [1]: TWOR mode. 9.2.11 CKO Pin Control Register (Address: 0Ah) Name R/W Bit 7 CKO Pin Control W ECKOE Bit 6 CKOS3 Bit 5 CKOS2 Bit 4 CKOS1 Bit 3 CKOS0 Bit 2 CKOI Bit 1 CKOE Bit 0 SCKI ECKOE: CKO pin Output Enable.
[0]: Disable. [1]: Enable. CKOS [3:0]: CKO pin output select. Oct., 2012, Version 0.6 (PRELIMINARY) 17 AMICCOM Electronics Corporation
[0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode.
[0010]: FPF (FIFO pointer flag).
[0011]: EOP, EOVBC, EOFBC, EOVCC, EOVDC, RSSC_OK. (Internal usage only).
[0100]: External clock output= FSYCK / 2.
[0101]: External clock output / 2= FSYCK / 4.
[0110]: RXD
[0111]: FSYNC.
[1000]: WCK.
[1001]: PF8M.(8Mhz, internal usage)
[1010]: ROSC.
[1011]: MXDEC(SLF[0]=1:~OKADCN, SLF[1]=0: DEC , internal usage)
[1100]: BDF (Battery Detect flag).
[1101]: FSYCK ..
[1110]: VPOAK.
[1111]: WRTC (internal usage) CKOI: CKO pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. CKOE: CKO pin Output Enable.
[0]: High Z. [1]: Enable. SCKI: SPI clock input invert.
[0]: Non-inverted input. [1]: Inverted input. 9.2.12 GIO1 Pin Control Register I (Address: 0Bh) Bit 5 Name R/W Bit 7 VKM Bit 6 VPM Bit 4 Bit 3 Bit 2 GIO1S3 GIO1S2 GIO1S1 GIO1S0 GIO1 Pin Control I W VKM: Valid packet mode select.
[0]: by event. [1]: by pulse. VPM: Valid Pulse width select.
[0]: 20u. [1]: 40u. LBA7130 Bit 1 GIO1I GI O1OE Bit 0 TX Mode (disable auto-resend, EAR=0). Oct., 2012, Version 0.6 (PRELIMINARY) 18 AMICCOM Electronics Corporation RX Mode (disable Auto-ack, EAK =0). LBA7130 Note1, If auto-resend is enabled (EAR = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note2, If auto-ack is enabled (EAK = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note3, VPOAKs behavior is controlled by VPM (0Bh) and VPW (0Bh). Refer to chapter 19 for details GIO1S [3:0]: GIO1 pin function select. GIO1S [3:0]
TX state RX state WTR (Wait until TX or RX finished) EOAC (end of access code) TMEO (TX modulation enable) FSYNC (frame sync) CD (carrier detect) Preamble Detect Output (PMDO) If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) In phase demodulator input(DMII)or VT[0] (internal usage) SDO ( 4 wires SPI data out) TRXD In/Out (Direct mode) RXD (Direct mode) TXD (Direct mode) PDN_RX External FSYNC input in RX direct mode (internal usage) MXINC(SLF[0]=1:EOADC.SLF[1]=0:INC.) (internal usage) FPF VPOAK (Valid Packet or Auto ACK OK Output) FMTDO (internal usage)
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
If GIO1S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend.If GIO1S = [1011] and direct mode is selected, the internal frame sync function will be disabled. In such case, A7130 supports to accept an external frame sync signal from MCU to feed to GIO1 pin to determine the timing of fixing DC estimation voltage of demodulator. GIO1I: GIO1 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. GIO1OE: GIO1pin output enable.
[0]: High Z. [1]: Enable. Oct., 2012, Version 0.6 (PRELIMINARY) 19 AMICCOM Electronics Corporation LBA7130 Bit 1 GIO2I GI O2OE Bit 0 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) Bit 5 R/W Bit 7 Name Bit 6 Bit 4 Bit 3 Bit 2 GIO2 Pin Control II W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00].
[00]: FSYCK. [01]: FSYCK / 2. [10]: FSYCK / 4. [11]: FSYCK / 8. GIO2S [3:0]: GIO2 pin function select. GIO2S
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
TX state RX state WTR (Wait until TX or RX finished) EOAC (end of access code) TMEO (TX modulation enable) FSYNC (frame sync) CD (carrier detect) Preamble Detect Output (PMDO) If RCOSC_E =1, output TWOR. If RCOSC_E =0, output CWTR signal. (internal usage) Quadrature phase demodulator input (DMIQ) (internal usage) SDO (4 wires SPI data out) TRXD In/Out (Direct mode) RXD (Direct mode) TXD (Direct mode) PDN_TX ROMOK(ROM Program OK) (internal usage) BDF (Battery Detect Flag) FPF VPOAK (Valid Packet or Auto ACK OK Output) DCK (internal usage) If GIO2S = [0100] and RCOSC_E = 0, CWTR is an internal signal to monitor TX/RX cycles of auto-ack and auto-resend. GIO2I: GIO2 pin output signal invert.
[0]: Non-inverted output. [1]: Inverted output. GIO2OE: GIO2 pin Output Enable.
[0]: High Z. [1]: Enable. TX-Strobe PLL Mode 10 us + (PDL+TDL) No Command Required Preamble + ID Code + Payload
+ CRC Next Instruction Auto Back PLL Mode In TX mode SPI
(SCS,SCK,SDIO) RF Port
(Output) GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO2 Pin - TMEO
(GIO2S[3:0]=0010) T0 T1
< 1us In RX mode 16 us PA Ramp Down T2 T3 Oct., 2012, Version 0.6 (PRELIMINARY) 20 AMICCOM Electronics Corporation LBA7130 No Command Required Preamble + ID Code + Payload
+ CRC Next Instruction Auto Back PLL Mode SPI
(SCS,SCK,SDIO) RX-Strobe PLL Mode 10us+PDL+TDL RF Port
(Input) GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO2 Pin - FSYNC
(GIO2S[3:0]=0001) ID-Matched T0 T1
< 1us T2 9.2.14 Clock Register (Address: 0Dh) Name Clock Bit 6 CGC0 IFS0 Bit 4 GRC2 GRC2 Bit 3 GRC1 GRC1 Bit 2 GRC0 GRC0 R/W Bit 7 CGC1 W IFS1 R Bit 5 GRC3 GRC3 CGC [1:0]: Clock Gen. Current select. Shall be set to [10]. GRC [3:0]: Clock generation reference counter. Recommend GRC = [0111] for 16MHz Xtal. GRC [3:0] is used to let below formula be true when CGS = 1. FXTAL x (DBL+1) / (GRC+1) = 2MHz. CGS: Clock generator enable. Recommend CGS = [1]
[0]: Disable. [1]: Enable. XS: Crystal oscillator select. Recommend XS = [1]
[0]: External clock. [1]: Crystal. IFS [1:0]: IF band selection. (Ready only) Bit 1 CGS
Bit 0 XS
9.2.15 PLL Register I (Address: 0Eh) Name PLL I R/W Bit 7 R/W CHN7 Bit 6 CHN6 Bit 5 CHN5 Bit 4 CHN4 Bit 3 CHN3 Bit 2 CHN2 Bit 1 CHN1 Bit 0 CHN0 CHN [7:0]: LO channel number select. Refer to chapter 14 for details. 9.2.16 PLL Register II (Address: 0Fh) Name PLL II R/W Bit 7 DBL R W DBL Bit 6 RRC1 RRC1 Bit 5 RRC0 RRC0 Bit 4 CHR3 CHR3 Bit 3 CHR2 CHR2 Bit 2 CHR1 CHR1 Bit 1 CHR0 CHR0 Bit 0 IP8 BIP8 DBL: Crystal frequency doublers selection.
[0]: Disable. FXREF = FXTAL.
[1]: Enable. FXREF =2 * FXTAL. In FIFO mode, recommend to set DBL =0. In Direct mode, recommend to set DBL =1. Please refer to A7130 reference code for details. RRC [1:0]: RF PLL reference counter setting. Recommend RRC = [00]. The PLL comparison frequency, FPFD = FCRYSTAL *(DBL+1) / (RRC+1). Oct., 2012, Version 0.6 (PRELIMINARY) 21 AMICCOM Electronics Corporation LBA7130 CHR [3:0]: PLL channel step setting. In FIFO mode, recommend to set CHR [3:0] = [0111]. In Direct mode, recommend to set CHR [3:0] = [1111]. Please refer to chapter 14 and A7130 reference code for details. 9.2.17 PLL Register III (Address: 10h) Name PLL III R/W Bit 7 IP7 R W BIP7 Bit 6 IP6 BIP6 Bit 5 IP5 BIP5 Bit 4 IP4 BIP4 Bit 3 IP3 BIP3 Bit 2 IP2 BIP2 Bit 1 IP1 BIP1 Bit 0 IP0 BIP0 BIP [8:0]: LO base frequency integer part setting. (0Fh and 10h) In FIFO mode, recommend to set BIP [8:0] = [0x096]. In Direct mode, recommend to set BIP [8:0] = [0x04B]. Please refer to chapter 14 and A7130 reference code for details. IP [8:0]: LO frequency integer part value. IP [8:0] are from address (0Fh) and (10h), Refer to chapter 14 for details. 9.2.18 PLL Register IV (Address: 11h) Name PLL IV R/W Bit 7 R RAC15 W BFP15 BF Bit 6 RAC14 P14 Bit 5 RAC13 BFP13 Bit 4 RAC12 BFP12 BF Bit 3 RAC11 P11 Bit 2 RAC10 BFP10 9.2.19 PLL Register V (Address: 12h) PLL V Name Bit 6 RAC6 BFP6 R/W Bit 7 R RAC7 W BFP7 Bit 4 RAC4 BFP4 BFP [15:0]: LO base frequency fractional part setting. (11h and 12h) In FIFO mode, recommend to set BFP [15:0] = [0x0004]. In Direct mode, recommend to set BFP [15:0] = [0x0002]. Please refer to chapter 14 and A7130 reference code for details. RAC [15:0]: Auto Frequency compensation value if AFC (19h) =1. Bit 5 RAC5 BFP5 AFC = 1 AFC = 0 RAC [15:0]
PLLFF [15:0]
{SYNCF, AC [14:0]}
Note LO Freq. compensation value Bit 3 RAC3 BFP3 Bit 2 RAC2 BFP2 Bit 1 RAC9 BFP9 Bit 1 RAC1 BFP1 Bit 0 RAC8 BFP8 Bit 0 RAC0 BFP0 9.2.20 Channel Group Register I (Address: 13h) Name CHGI R/W Bit 7 R/W CHGL7 Bit 6 CHGL6 Bit 5 CHGL5 Bit 4 CHGL4 Bit 3 CHGL3 Bit 2 CHGL2 Bit 1 CHGL1 Bit 0 CHGL0 CHGL [7:0]: PLL channel group low boundary setting for auto-calibration. Recommed CHGL[7:0] = 0x3C. Refer to A7130 reference code for details. 9.2.21 Channel Group Register II (Address: 14h) Name CHGII R/W Bit 7 R/W CHGH7 Bit 6 CHGH6 Bit 5 CHGH5 Bit 4 CHGH4 Bit 3 CHGH3 Bit 2 CHGH2 Bit 1 CHGH1 Bit 0 CHGH0 CHGH [7:0]: PLL channel group high boundary setting for auto-calibration. Recommed CHGH[7:0] = 0x78. Refer to A7130 reference code for details. PLL calibration frequency is divided into 3 groups by CHGL and CHGH:
Group1 Group2 Channel 0 ~ CHGL-1 CHGL ~ CHGH-1 Oct., 2012, Version 0.6 (PRELIMINARY) 22 AMICCOM Electronics Corporation LBA7130 Group3 CHGH ~ 255 9.2.22 TX Register I (Address: 15h) Name TX I R/W Bit 7 W GDR Bit 6 GF Bit 5 TMDE Bit 4 TXDI Bit 3 TME Bit 2 FDP2 Bit 1 FDP1 Bit 0 FDP0
[1]: Enable. GDR: Gaussian Filter Over Sampling Rate Select. Recommend GDR = [1].
[0]: BT= 0.7 [1]: BT= 0.5 GF: Gaussian Filter Select.
[0]: Disable. TMDE: TX modulation enable for VCO modulation. Recommend TMDE = [1].
[0]: Disable. [1]: Enable. TXDI: TX data invert. Recommend TXDI = [0].
[0]: Non-invert. [1]: Invert. TME: TX modulation enable. Recommend TME = [1].
[0]: Disable. [1]: Enable. FDP [2:0]: Frequency deviation power setting. Recommend FDP = [110]. In FIFO mode, recommend to set FDP [2:0] = [111]. In Direct mode, recommend to set FDP [2:0] = [110]. Please refer to chapter 14 and A7130 reference code for details. 9.2.23 TX Register II (Address: 16h) Name TXI R/W Bit 7 FD7 W Bit 6 FD6 Bit 5 FD5 Bit 4 FD4 Bit 3 FD3 Bit 2 FD2 Bit 1 FD1 Bit 0 FD0 FD [7:0]: Frequency deviation setting. FDEV = (FPFD /216) x FD[7:0] x 2(FDP-1). Where FPFD= FXTAL * (DBL+1) / (RRC [1:0]+1), PLL comparison frequency. FDP[2:0]
Data Rate 111 4Mbps FIFO mode 4Mbps Direct mode 110 FD[7:0]
0x40 0x40 Fdev 1MHz 1MHz 9.2.24 Delay Register I (Address: 17h) Name Delay R/W Bit 7 DPR2 W Bit 6 DPR1 Bit 5 DPR0 Bit 4 TDL1 Bit 3 TDL0 Bit 2 PDL2 Bit 1 PDL1 Bit 0 PDL0 DPR [2:0]: Delay scale. Recommend DPR = [000]. TDL [1:0]: Delay for TX settling from WPLL to TX. TDL Delay= 20 * (TDL [1:0]+1)*(DPR [2:0]+1) us. DPR [2:0]
000 000 000 000 PDL [2:0]: Delay for TX settling from PLL to WPLL. PDL Delay= 10 + {20 * (PDL [2:0]+1)*(DPR [2:0]+1)} us. WPLL to TX 20 us 40 us 60 us 80 us TDL [1:0]
00 01 10 11 Note Recommend DPR [2:0]
PDL [2:0]
000 000 000 001 PLL to WPLL
(LO freq changed) 30 us 50 us Note Recommend Oct., 2012, Version 0.6 (PRELIMINARY) 23 AMICCOM Electronics Corporation LBA7130 000 000 000 G IO 1 P in
(W T R ) R F O P in 010 011 100 P L L M od e 70 us 90 us 110 us T X M od e T X S tro be 10 u s + P D L T D L PA R a m p D o w n 16 u s P a cke t 9.2.25 Delay Register II (Address: 18h) Name Delay R/W Bit 7 W WSEL2 WSEL1 WSEL0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [011].
[000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us.
[100]: 1ms.
[110]: 2ms. [111]: 2.5ms.
[101]: 1.5ms. C rystal O scilla to r G IO 1 P in
(W T R ) R F O P in Id le m o de 30 0 us W S E L T X or R X S tro be C m d 1 0 u s + P D L T D L Pa ck et (Pream ble + ID + P aylo ad) RSSC_D [1:0]: RSSI calibration switching time (10us ~ 40us). Recommend RSSC_D = [00].
[00]: 10us. [01]: 20us. [10]: 30us. [11]: 40us. RS_DLY [2:0]: RSSI measurement delay (10us ~ 80us). Recommend RS_DLY = [000].
[000]: 10us. [001]: 20us. [010]: 30us. [011]: 40us.
[100]: 50us. [101]: 60us. [110]: 70us. [111]: 80us. 9.2.26 RX Register (Address: 19h) Name RX R/W Bit 7 W LNAGE Bit 6 AGCE RXSM1 Bit 5 Bit 4 RXSM0 Bit 3 AFCE Bit 2 RXDI Bit 1 DMG Bit 0 ULS LNAGE: Auto LNA Gain Control Select.
[0]: Disable. [1]: Enable. AGCE: Auto Front end Gain Control Select.
[0]: Disable. [1]: Enable. RXSM1: RX clock recovery circuit moving average filter length. Recommend RXSM1 = [1].
[0]: 4 bits. [1]: 8 bits. RXSM0: Demodulator LPF Bandwidth Select. Recommend RXSM0 = [1].
[0]: 2*IF. [1]: 1*IF. AFCE: Frequency compensation select.
[0]: Disable. [ 1]: Enable. RXDI: RX data output invert. Recommend RXDI = [0].
[0]: Non-inverted output. [1]: Inverted output. DMG: Demodulator Gain Select. Recommend DMG = [1].
[0]: x 1. [1]: x 3. Oct., 2012, Version 0.6 (PRELIMINARY) 24 AMICCOM Electronics Corporation LBA7130 ULS: RX Up/Low side band select. Recommend ULS = [0].
[0]: Up side band, [1]: Low side band. Refer to section 14.2 for details. 9.2.27 RX Gain Register I (Address: 1Ah) Bit 6 MIC MICR R/W Bit 7 W PRS R RX Gain I Name
Bit 5 IGC1 IGCR1 Bit 4 IGC0 IGCR0 Bit 3 MGC1 MGCR1 Bit 2 MGC0 MGCR0 Bit 1 LGC1 LGCR1 Bit 0 LGC0 LGCR0 PRS: Limiter amplifier discharge manual select. Recommend PRS =[0]. MIC: Mixer buffer gain setting. Recommend MIC =[1].
[0]: 0dB. [1]: 6dB. IGC [1:0]: IFA Attenuation Select. Recommend IGC =[10].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. MGC [1:0]: Mixer Gain Attenuation select. Recommend MGC =[11].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. LGC [1:0]: LNA Gain Attenuation select. Recommend LGC =[11].
[00]: 0dB. [01]: 6dB. [10]: 12dB. [11]: 18dB. 9.2.28 RX Gain Register II (Address: 1Bh) Bit 6 RH6 Name R/W Bit 7 R RH7 W RSAGC1 RX Gain II RSAGC0 Bit 5 RH5 VTL2 Bit 4 RH4 VTL1 Bit 3 RH3 VTL0 Bit 2 RH2 VTH2 Bit 1 RH1 VTH1 Bit 0 RH0 VTH0 RSAGC [1:0]: AGC clock select. Recommend RSAGC = [11].
[00]: IF/ 8. [01]: IF / 4. [10]: IF / 2. [11]: IF. VTL [2:0]: VCO tuning voltage lower threshold level setting. Recommend VTL = [000].
[000]: 0.1V. [001]: 0.2V. [010]: 0.3V. [011]: 0.4V.
[100]: 0.5V. [101]: 0.6V. [110]: 0.7V. [111]: 0.8V VTH [2:0]: VCO tuning voltage upper threshold level setting. Recommend VTH = [010].
[000]: VDD_A 0.6V. [001]: VDD_A 0.7V. [010]: VDD_A 0.8V. [011]: VDD_A 0.9V
[100]: VDD_A 1.0V. [101]: VDD_A 1.1V. [110]: VDD_A 1.2V. [111]: VDD_A 1.3V Remark: VDD_A is on chip analog regulator output voltage where is set to 1.8V. RH [7:0]: RSSI Calibration High Threshold. (Read only) 9.2.29 RX Gain Register III (Address: 1Ch) Name RX Gain III R/W Bit 7 RL7 R W
Bit 6 RL6 RDU Bit 5 RL5 IFS1 Bit 4 RL4 IFS0 Bit 3 RL3 RSM1 Bit 2 RL2 RSM0 Bit 1 RL1 ERSSM Bit 0 RL0 RSS RDU: Clock Generator Select. Recommend RDU = [0].
[0]: 128MHZ [1]: 96MHZ. IFS [1:0]: IF Frequency Select.
[00]: reserved. [01]: reserved. [10]: reserved [11]: 4MHZ. RSM [1:0]: RSSI Margin = RTH RTL. Recommend RSM = [11].
[00]: 5. [01]: 10. [10]: 15. [11]: 20. Refer to chapter 17 for details. ERSSM: Ending Mode Select in RSSI Measurement. Recommend ERSSM = [0].
[0]: RSSI ending by RX. [1]: RSSI ending by SYNC_Ok. RSS: RSSI measurement select. (XADS=0, RSS=0, default mode is thermal sensor.)
[0]: Disable. [1]: Enable (recommend). Oct., 2012, Version 0.6 (PRELIMINARY) 25 AMICCOM Electronics Corporation LBA7130 RL [7:0]: RSSI Calibration Low Threshold. (Ready only) 9.2.30 RX Gain Register IV (Address: 1Dh) Name RX Gain III R/W Bit 7 W LIMC Bit 6 IFBC1 Bit 5 IFBC0 Bit 4 IFAS Bit 3 MHC1 Bit 2 MHC0 Bit 1 LHC1 Bit 0 LHC0 LIMC: IF limiter current select. Recommend LIMC = [1].
[0]: 0.3mA. [1]: 0.6mA. IFBC [1:0]: IF BPF current Select. Recommend IFBC = [11].
[00]: 0.75 mA.. [01]: 1.4mA. [10]: 2.1mA. [11]: 3.5mA. IFAS: IF Amp current select. Recommend IFAS = [0].
[0]: 0.3mA. [1]: 0.6mA. MHC: Mixer Current Select. Recommend MHC = [01].
[00]: 0.6mA. [01]: 1.2mA. [10]: reserved. [11]: reserved. LHC[1:0]: LNA Current Select. Recommend LHC = [11].
[00]: 0.5mA. [01]: 1mA. [10]: 1.5mA. [11]: 2mA. 9.2.31 RSSI Threshold Register (Address: 1Eh) Name RSSI Threshold R/W Bit 7 ADC7 R W RTH7 RTH [7:0]: Carrier detect threshold. Refer to Chapter 17 for details. CD (Carrier Detect)=1 when RSSI RT H. CD (Carrier Detect)=0 when RSSI < RTL. Bit 6 ADC6 RTH6 Bit 5 ADC5 RTH5 Bit 4 ADC4 RTH4 Bit 3 ADC3 RTH3 Bit 2 ADC2 RTH2 Bit 1 ADC1 RTH1 Bit 0 ADC0 RTH0 ADC [7:0]: ADC output value for RSSI measurement. ADC input voltage= 1.2 * ADC [7:0] / 256 V. 9.2.32 ADC Control Register (Address: 1Fh) Bit 4 Bit 5 Bit 6 Name ADC Control Bit 1 XADS Bit 3 RADC Bit 2 FSARS AVSEL0 MVSEL1 MVSEL0 R/W Bit 7 W AVSEL1 Bit 0 CDM AVSEL [1:0]: ADC average times (for Carrier / temeperature sensor / external ADC). Recommend AVSEL = [11].
[00]: No average. [01]: Average 2 times. [10]: Average 4 times. [11]: Average 8 times. MVSEL [1:0]: ADC average times (for VCO calibration and RSSI ). Recommend MVSEL = [11].
[00]: Average 8 times. [01]: Average 16 times. [10]: Average 32 times. [11]: Average 64 times. RADC: ADC Read Out Average Mode. Recommend RADC = [0].
[0]: by AVSEL.
[1]: by MVSEL. FSARS: ADC clock select. Recommend FSARS = [0].
[0]: 4MHz. [1]: 8MHz. XADS: External ADC Input Signal Select.
[0]: Disable. [1]: Enable. CDM: RSSI measurement mode. Recommend CDM = [1].
[0]: Single mode. [1]: Continuous mode. 9.2.33 Code Register I (Address: 20h) Name Code I R/W Bit 7 W MCS Bit 6 WHTS Bit 5 FECS Bit 4 CRCS Bit 3 IDL1 Bit 2 IDL0 Bit 1 PML1 Bit 0 PML0 Oct., 2012, Version 0.6 (PRELIMINARY) 26 AMICCOM Electronics Corporation LBA7130 MSC: Manchester Enable.
[0]: Disable. [1]: Enable. WHTS: Data Whitening (Data Encryption) Select.
[0]: Disable. [1]: Enable (The data is whitening by multiplying PN7). FECS: FEC Select.
[0]: Disable. [1]: Enable (The FEC is (7, 4) Hamming code). CRCS: CRC Select. Recommend CRCS = [1].
[0]: Disable. [1]: Enable. IDL [1:0]: ID Code Length Select. Recommend IDL= [01].
[00]: 2 bytes. [01]: 4 bytes. [10]: 6 bytes. [11]: 8 bytes. PML [1:0]: Preamble Length Select. Recommend PML= [11].
[00]: 1 byte. [01]: 2 bytes. [10]: 3 bytes. [11]: 4 bytes. 9.2.34 Code Register II (Address: 21h) Name Code II R/W Bit 7 W MSCRC Bit 6 EDRL Bit 5 HECS Bit 4 ETH2 Bit 3 ETH1 Bit 2 ETH0 Bit 1 PMD1 Bit 0 PMD0 MSCRC: Mask CRC (CRC Data Filtering Enable). Recommend MSCRC = [1].
[0]: Disable. [1]: Enable. EDRL: Enable FIFO Dynamic Length
[0]: Disable. [1]: Enable. Please refer to chapter 16 for details. HECS: HEC Header CRC-8 select.
[0]: Disable. [1]: Enable. Please refer to chapter 16 for details. ETH [2:0]: Received ID Code Error Tolerance. Recommend ETH = [001].
[000]: 0 bit, [001]: 1 bit. [010]: 2 bit. [011]: 3 bit. [100]: 4 bit, [101]: 5 bit. [110]: 6 bit. [111]: 7 bit. PMD [1:0]: Preamble pattern detection length. Recommend PMD = [10].
[00]: 0bit. [01]: 4bits. [10]: 8bits. [11]: 16bits. 9.2.35 Code Register III (Address: 22h) Name Code III R/W Bit 7 W CRCINV Bit 6 WS6 Bit 5 WS5 Bit 4 WS4 Bit 3 WS3 Bit 2 WS2 Bit 1 WS1 Bit 0 WS0 CRCINV: CRC Inverted Select.
[0]: Non-inverted. [1]: inverted. WS [6:0]: Data Whitening seed setting (data encryption key). The data is whitened by multiplying with PN7. Please refer to chapter 16 for details. 9.2.36 IF Calibration Register I (Address: 23h) Name IF Calibration I R/W Bit 7 R W
HFR Bit 6
Bit 5
CKGS1 CKGS0 Bit 4 FBCF MFBS Bit 3 FB3 MFB3 Bit 2 FB2 MFB2 Bit 1 FB1 MFB1 Bit 0 FB0 MFB0 HFR: Half Rate setting. Recommend HFR = [0].
[0]: Clk gen. by 32 x Data Rate. [1]: Clk gen. by 16 x Data Rate. CKGS[1:0]: Clock gen. data rate manual setting. Recommend CKGS = [11].
[00]: reserved. [01]: reserved. [10]: reserved. [11]: 4MHZ. When RDU=0, CKGS[1:0] = IFS[1:0]
When RDU=1, CKGS[1:0] = Manual setting. MFBS: IF filter calibration value select. Recommend MFBS = [0]. Oct., 2012, Version 0.6 (PRELIMINARY) 27 AMICCOM Electronics Corporation LBA7130
[0]: Auto calibration value. [1]: Manual calibration value. MFB [3:0]: IF filter manual calibration value. FBCF: IF filter auto calibration flag (read only).
[0]: Pass. [1]: Fail. FB [3:0]: IF filter calibration value (read only). MFBS= 0: Auto calibration value (AFB), MFBS= 1: Manual calibration value (MFB). 9.2.37 IF Calibration Register II (Address: 24h) Name IF Calibration II R/W Bit 7 R W PWORS
Bit 6
TRT2 Bit 5 TRT1 Bit 4 FCD4 TRT0 Bit 3 FCD3 ASMV2 Bit 2 FCD2 ASMV1 Bit 1 FCD1 ASMV0 Bit 0 FCD0 AMVS PWORS: TX high power setting. Recommend PWORS = [1].
[0]: Disable. [1]: Enable. TRT [2:0]: TX Ramp down discharge current select. Recommend TRT = [111]. AMSV [2:0]: TX Ramp up Timing Select. Recommend AMSV = [111].
[000]: 2us, [001]: 4us. [010]: 6us. [011]: 8us. [100]: 10us, [101]: 12us. [110]: 14us. [111]: 16us. Real case of TX ramping up is AMSV [2:0] multiplied by 2^(RMP[1:0]) AMVS: TX Ramp Up Enable. Recommend AMVS = [1].
[0]: Disable. [1]: Enable. FCD [4:0]: IF filter calibration deviation from goal (read only). 9.2.38 VCO current Calibration Register (Address: 25h) Name VCO current Calibration R/W Bit 7 R W ROSCS
Bit 6
RSIS Bit 5
VCRLS Bit 4 VCCF MVCS VCO Bit 3 VCB3 C3 Bit 2 VCB2 VCOC2 Bit 1 VCB1 VCOC1 Bit 0 VCB0 VCOC0 ROSCS: WOR RC select. Recommend ROSCS = [1]
RSIS: WOR current select. Recommend RSIS = [0]
VCRLS: VCO Current Resistor Select. Recommend VCRLS = [0]
[0]: low current select. [1]: high current select. MVCS: VCO current calibration value select. Recommend MVCS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. VCOC [3:0]: VCO current manual calibration value. VCCF: VCO Current Auto Calibration Flag (read only).
[0]: Pass. [1]: Fail. VCB [3:0]: VCO current calibration value (read only). MVCS= 0: Auto calibration value (VCB). MVCS= 1: Manual calibration value (VCOC). 9.2.39 VCO band Calibration Register I (Address: 26h) Name VCO Single band Calibration I R/W Bit 7 R W DCD1
Bit 6
DCD0 Bit 5
DAGS Bit 4
CWS Bit 3 VBCF MVBS Bit 2 VB2 MVB2 Bit 1 VB1 MVB1 Bit 0 VB0 MVB0 DCD [1:0]: VCO Deviation Calibration Delay. Recommend DCD = [11]. Delay time = PDL (Delay Register I, 17h) ( DDC + 1 ). DAGS: DAG Calibration Value Select. Recommend DAGS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. Oct., 2012, Version 0.6 (PRELIMINARY) 28 AMICCOM Electronics Corporation LBA7130 CWS: Clock Disable for VCO Modulation. Recommend CWS = [1].
[0]: Enable. [1]: Disable. MVBS: VCO bank calibration value select. Recommend MVBS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. MVB [2:0]: VCO band manual calibration value. VBCF: VCO band auto calibration flag (read only).
[0]: Pass. [1]: Fail. VB [2:0]: VCO bank calibration value (read only). MVBS= 0: Auto calibration value (AVB). MVBS= 1: Manual calibration value (MVB). 9.2.40 VCO band Calibration Register II (Address: 27h) Name VCO Single band Calibration II R/W Bit 7 W DAGM7 DAGB7 R Bit 6 DAGM6 DAGB6 Bit 5 DAGM5 DAGB5 Bit 4 DAGM4 DAGB4 Bit 3 DAGM3 DAGB3 Bit 2 DAGM2 DAGB2 Bit 1 DAGM1 DAGB1 Bit 0 DAGM0 DAGB0 DAGM [7:0]: DAG Manual Setting Value. DAGB [7:0]: Auto DAG Calibration Value (read only). 9.2.41 VCO Deviation Calibration Register I (Address: 28h) Name VCO Deviation Calibration I R/W Bit 7 DEVA7 R W DEVS3 Bit 6 DEVA6 DEVS2 Bit 5 DEVA5 DEVS1 Bit 4 Bit 1 DEVA4 DEVA1 DEVS0 DAMR_M VMTE_M VMS_M Bit 2 DEVA2 Bit 3 DEVA3 Bit 0 DEVA0 MSEL DEVS [3:0]: Deviation Output Scaling. Recommend DEVS = [0111]. DAMR_M: DAMR Manual Enable. Recommend DAMR_M = [0].
[0]: Disable. [1]: Enable. VMTE_M: VMT Manual Enable. Recommend VMTE_M = [0].
[0]: Disable. [1]: Enable. VMS_M: VM Manual Enable. Recommend VMS_M = [0].
[0]: Disable. [1]: Enable. MSEL: VMS, VMTE and DAMR control select. Recommend MSEL = [0].
[0]: Auto control. [1]: Manual control. DEVA [7:0]: Deviation Output Value (read only). MVDS (29h)= 0: Auto calibration value ((DEVC / 8) (DEVS + 1)), MVDS (29h)= 1: Manual calibration value (DEVM [6:0]). VCO Deviation Calibration II Bit 6 R/W Bit 7 DEVC7 DEVC6 R MVDS DEVM 6 W 9.2.42 VCO Deviation Calibration Register II (Address: 29h) Bit 4 Name DEVC4 DEVM4 MVDS: VCO Deviation Calibration Select. Recommend MVDS = [0].
[0]: Auto calibration value. [1]: Manual calibration value. DEVM [6:0]: VCO Deviation Manual Calibration Value. DEVC [7:0]: VCO Deviation Auto Calibration Value (read only). Bit 5 DEVC5 DEVM5 Bit 3 DEVC3 DEVM3 Bit 2 DEVC2 DEVM2 Bit 1 DEVC1 DEVM1 Bit 0 DEVC0 DEVM0 Oct., 2012, Version 0.6 (PRELIMINARY) 29 AMICCOM Electronics Corporation LBA7130 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) Name DASP0 R/W Bit 7 W Bit 6 RFSP QLIM Bit 4 Bit 5 Bit 0 INTXC
(CSXTL5) CSXTL4 CSXTL3 CSXTL2 CSXTL1 CSXTL0 Bit 3 Bit 2 Bit 1 QLIM: quick charge select for IF limiter amp. Recommend QLIM = [0].
[0]: disable. [1]: enable. (QLIM fall down delay 10 us). RFSP: RF single port Select. Recommend RFSP = [0].
[0]: LNA (RFI) and PA (RFO) are combined internally to RFI pin.
[1]: LNA (RFI) and PA (RFO) are separated to RFI pin and RFO pin. INTXC: internal crystal oscillator capacitor selection. Recommend INTXC = [1].
[0]: disable. [1]: enable. CSXTAL[4:0]: On-chip Crystal loading select. Recommend CSXTAL = [10100] if Xtal Cload = 18 pF.
{INTXC,CSXTAL[4:0]} On-chip Xtal Capacitor (pF) 0XXXXX 100000 100001 100010 111110 111111 0 16 17 18 46 47 9.2.43 DASP1 (Address: 2Ah, Page 1 by AGT[3:0]=1) Name DASP1 R/W Bit 7 W STS Bit 6 CELS Bit 5 RGS Bit 4 RGC1 Bit 3 RGC0 Bit 2 VRPL1 Bit 1 VRPL0 Bit 0 INTPRC STS: Start up mode select. Shall be set to [0]. CELS: Digital voltage select in standby mode. Recommend CELS = [1]. RGS: Low Power Regulator Voltage Select. Recommend RGS = [0]. LVR (2Ch) 0 0 1 1 RGS 0 1 0 1 Low Power Regulator Voltage Note 3/5 *REGI 3/4 * REGI 1.8 V 1.6 V Recommended RGC [1:0]: Low power band-gap current select. Recommend RGC = [01]. VRPL [1:0]: internal PLL loop filter resistor value select. Recommend VRPL = [00].
[00]: 500 ohm. [01]: 666 ohm. [10]: 1 K ohm. [11]: 2K ohm. INTPRC: Internal PLL loop filter resistor and capacitor select. Recommend INTPRC = [1].
[0]: disable. [1]: enable 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) Name DASP2 R/W Bit 7 W VTRB3 Bit 4 VTRB0 VTRB [3:0]: Resistor Bank for VT RC Filtering. Shall be set to [0000]. VMRB [3:0]: Resistor Bank for VM RC Filtering. Shall be set to [0000]. Bit 5 VTRB1 Bit 6 VTRB2 Bit 3 VMRB3 Bit 2 VMRB2 Bit 1 VMRB1 Bit 0 VMRB0 Oct., 2012, Version 0.6 (PRELIMINARY) 30 AMICCOM Electronics Corporation LBA7130 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) Name DASP3 R/W Bit 7 W DCV7 Bit 6 DCV6 Bit 5 DCV5 Bit 4 DCV4 Bit 3 DCV3 Bit 2 DCV2 Bit 1 DCV1 Bit 0 DCV0 DCV [7:0]: Demodulator Fix mode DC value. Recommend DCV = [0x80]. 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) Name DASP4 R/W Bit 7 W/R VMG7 Bit 6 VMG6 Bit 5 VMG5 Bit 4 VMG4 Bit 3 VMG3 Bit 2 VMG2 Bit 1 VMG1 Bit 0 VMG0 VMG [7:0]: VM Center Value for Deviation Calibration. Recommend VMG [7:0] = [0x80]. 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5)
Bit 6 Name DASP5 R/W Bit 7 W Bit 4 PKT0 PKT[1:0]: VCO Peak Detect Current Select. Recommend PKT = [00]. PKS: VCO Current Calibration Mode Select. Recommend PKS = [0]. PKIS[1:0]: AGC Peak Detect Current Select. Recommend PKIS = [00]. IFPK: AGC Amplifier Current Select. Recommend IFPK = [0]. Bit 5 PKT1
Bit 3 PKS Bit 2 PKIS1 Bit 1 PKIS0 Bit 0 IFPK 9.2.43 DASP6 (Address: 2Ah, Page 6 by AGT[3:0]=6) Name DASP6 R/W Bit 7 W
Bit 6 HPLS Bit 5 HRS Bit 4 PACTL Bit 3 IWS Bit 2 CNT Bit 1 MXD Bit 0 LXD HPLS: High Power LNA Gain Select. Recommend HPLS = [0].
[0]: LGC set to 6dB when in TX Mode. [1]: LGC set to 24dB when in TX Mode. HRS: Reserved for internal usage only. Shall be set to [0]. PACTL: Reserved for internal usage only. Shall be set to [0]. IWS: Reserved for internal usage only. Shall be set to [1]. CNT: Reserved for internal usage only. Shall be set to [0]. MXD: Reserved for internal usage only. Shall be set to [1]. LXD: Reserved for internal usage only. Shall be set to [0]. 9.2.43 DASP7 (Address: 2Ah, Page 7 by AGT[3:0]=7) Bit 5 MS Name DASP7 Bit 6 VRSEL Bit 4 MSCL4 R/W Bit 7 W XDS Bit 3 MSCL3 XDS: VCO Modulation Data Sampling Clock selection. Recommend XDS = [0].
[0]: 8x over-sampling Clock. [ 1]: XCPCK Clock. VRSEL: AGC Function select. Recommend VRSEL = [1].
[0]: RSSI AGC. [1 ]: Normal AGC. MS: AGC Manual scale select. Recommend MS = [0].
[0]: By (RHRL). [ 1]: By MSCL[4:0]. MSCL[4:0]: AGC Manual Scale setting. Recommend MSCL = [00000]. Bit 2 MSCL2 Bit 1 MSCL1 Bit 0 MSCL0 9.2.44 VCO Modulation Delay Register (Address: 2Bh) Bit Name R/W Bit 7 W DMV1 Bit 6 Bit 5 DMV0 DEVFD2 Bit 4 Bit 2 DEVFD1 DEVFD0 DEVD2 Bit 3 Bit 1 DEVD1 Bit 0 DEVD0 Oct., 2012, Version 0.6 (PRELIMINARY) 31 AMICCOM Electronics Corporation LBA7130 DMV [1:0]: Demodulator D/A Voltage Range Select. Recommend DMV = [11].
[00]: 1/32*1.2. [01]: 1/16*1.2. [10]: 1/8*1.2. [11]: 1/4*1.2. DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. Recommend DEVFD = [011]. DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Recommend DEVD = [100]. 9.2.45 Battery detect Register (Address: 2Ch) Bit 1 BVT0 BVT0 Bit 0 BD_E BD_E Name Battery detect Bit 4 QDS BDF Bit 2 BVT1 BVT1 Bit 3 BVT2 BVT2 Bit 6 RGV1 RGV1 R/W Bit 7 LVR W R
Bit 5 RGV0 RGV0 LVR: Low Power Bandgap Select. Recommend LVR = [1].
[0]: Disable. [1]: Enable. RGV [1:0]: VDD_D and VDD_A voltage setting in non-Sleep mode. Recommend RGV = [11].
[00]: 2.1V. [01]: 2.0V. [10]: 1.9V. [11]: 1.8V. QDS: VDD Quick Discharge Select. Recommend QDS = [1].
[0]: Disable. [1]: Enable. BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. BD_E: Battery Detect Enable.
[0]: Disable. [1]: Enable. It will be clear after battery detection is triggered. BDF: Battery detection flag.
[0]: Battery voltage < BVT [2:0]. [1]: Battery voltage BVT [2:0]. 9.2.46 TX test Register (Address: 2Dh) Name TX test R/W Bit 7 RMP1 W Bit 6 RMP0 Bit 5 TXCS Bit 4 PAC1 Bit 3 PAC0 Bit 2 TBG2 Bit 1 TBG1 Bit 0 TBG0 RMP [1:0]: PA ramp up timing scale. Recommend RMP = [00]. TXCS: TX Current Setting. Recommend TXCS = [1].
[0]: lowest current. [1]: highest current. PAC [1:0]: PA Current Setting. TBG [2:0]: TX Buffer Setting. Typical power (dBm) PWORS (24h) TBG TXCS PAC Typical current (mA) RF Band 2.4GHz 5 0
-5
-17 Refer to A7130 App. Note for more settings. 1 1 0 0 7 0 4 0 1 1 1 1 2 0 0 0 29 20 18 16 9.2.47 Rx DEM test Register I (Address: 2Eh) Name Rx DEM test I R/W Bit 7 W DMT Bit 6 DCM1 Bit 5 DCM0 Bit 4 MLP1 Bit 3 MLP0 Bit 2 SLF2 Bit 1 SLF1 Bit 0 SLF0 DMT: Reserved for internal usage only. Shall be set to [0]. DCM [1:0]: Demodulator DC estimation mode. Recommend DCM = [10].
(The average length before hold is selected by DCL in RX DEM Test Register II.)
[00]: Fix mode (For testing only). DC level is set by DCV [7:0]. Oct., 2012, Version 0.6 (PRELIMINARY) 32 AMICCOM Electronics Corporation LBA7130
[01]: Preamble hold mode. DC level is preamble average value.
[10]: ID hold mode. DC level is the average value hold about 8 bit data rate later if preamble is detected.
[11]: Payload average mode (For internal usage). DC level is payload data average. MLP1: Reserved for internal usage. Shall set MLP1 = [0]. MLP0: Reserved for internal usage. Shall set MLP0 = [0]. SLF [2:0]: Symbol Recovery Loop Filter Setting. Shall be SLF[2:0] = [111]. 9.2.48 Rx DEM test Register II (Address: 2Fh) Name Rx DEM test II R/W Bit 7 W DCH1 Bit 6 DCH0 Bit 5 DCL2 Bit 4 DCL1 Bit 3 DCL0 Bit 2 RAW Bit 1 CDTM1 Bit 0 CDTM0 DCH [1:0]: DC Estimation of AGC hold mode. Recommend DCH = [11].
[00]: hold when PMDO. [01]: hold when Fsync. [10]: no hold. [11]: no hold. DCL [2]: DC Estimation Average Length After ID Detected. Recommend DCL[2] = [1].
[0]: 128 bits. [1]: 256 bits. DCL [1:0]: DC Estimation Average Length Before ID Detected. Recommend DCL[1:0] = [10].
[00]: 8 bits. [01]: 16 bits. [10]: 32 bits. [11]: 64 bits. RAW: Raw Data Output Select. Recommend RAW = [1].
[0]: latch data output. [1]: RAW data output. CDTM [1:0]: Preamble carrier detect setting. Recommend CDTM = [11].
[00]: 12. [01]: 24. [10]: 36. [11]: 48. 9.2.49 Charge Pump Current Register I (Address: 30h) Name CPC I R/W Bit 7 CPM3 W Bit 6 CPM2 Bit 5 CPM1 Bit 4 CPM0 Bit 3 CPT3 Bit 2 CPT2 Bit 1 CPT1 Bit 0 CPT0 CPM [3:0]: Charge Pump Current Setting for VM loop. Recommend CPM = [1111]. Charge pump current = (CPM + 1) / 16 mA. CPT [3:0]: Charge Pump Current Setting for VT loop. Recommend CPT = [0000]. Charge pump current = (CPT + 1) / 16 mA. 9.2.50 Charge Pump Current Register II (Address: 31h) Name CPC II R/W Bit 7 W CPTX3 Bit 6 CPTX2 Bit 5 CPTX1 Bit 4 CPTX0 Bit 3 CPRX3 Bit 2 CPRX2 Bit 1 CPRX1 Bit 0 CPRX0 CPTX [3:0]: Charge Pump Current Setting for TX mode. Recommend CPTX = [0011]. Charge pump current = (CPTX + 1) / 16 mA. CPRX [3:0]: Charge Pump Current Setting for RX mode. Recommend CPRX = [0111]. Charge pump current = (CPRX + 1) / 16 mA. 9.2.51 Crystal test Register (Address: 32h) Name Crystal test R/W Bit 7 W CDPM Bit 6 CPS Bit 5 CPH Bit 4 CPCS Bit 3 DBD Bit 2 XCC Bit 1 XCP1 Bit 0 XCP0 CDPM:First Time Preamble Detect mode select. Recommend CDPM = [0]. CPS: PLL charge pump enable. Recommend CPS = [1].
[0]: Enable. [1]: Disable. CPH: Charge Pump High Current. Shall be set to [0].
[0]: Normal. [1]: High. CPCS: Charge Pump Current Select. Shall be set to [1].
[0]: Use CPM for TX, CPT for RX. [1]: Use CPTX for TX, CPRX for RX. Oct., 2012, Version 0.6 (PRELIMINARY) 33 AMICCOM Electronics Corporation LBA7130 DBD: Crystal Frequency Doubler High Level Pulse Width Select. Recommend DBD = [0].
[0]: about 8 ns. [1]: about 16 ns. XCC: Crystal Startup Current Selection. Recommend XCC = [1].
[0]: about 0.7 mA. [1]: about 1.5 mA. XCP [1:0]: Crystal Oscillator Regulated Couple Setting. Recommend XCP = [01].
[00]: 1.5mA. [01]: 0.5mA. [10]: 0.35mA. [11]: 0.3mA. 9.2.52 PLL test Register (Address:33h) Bit 6 OLM R/W Bit 7 W MDEN Name PLL test Bit 5 PRIC1 Bit 4 PRIC0 PRRC1 Bit 3 Bit 2 PRRC0 Bit 1 SDPW Bit 0 NSDO MDEN : Use for Manual VCO Calibration. Shall be set to [0]. OLM: Open Loop Modulation Enable. Shall be set to [0].
[0]: Disable. [1]: Enable. PRIC [1:0]: Prescaler IF Part Current Setting. Shall be set to [01].
[00]: 0.95mA. [01]: 1.05mA. [10]: 1.15mA. [11]: 1.25mA. PRRC [1:0]: Prescaler RF Part Current Setting. Shall be set to [01].
[00]: 1.0mA. [01]: 1.2mA. [10]: 1.4mA. [11]: 1.6mA. SDPW: Clock Delay For Sigma Delta Modulator. Shall be set to [0].
[0]: 13 ns. [1]: 26 ns. NSDO: Sigma Delta Order Setting. Shall be set to [1].
[0]: order 2. [1]: order 3. 9.2.53 VCO test Register I (Address:34h) Bit 6 Name VCO test I R/W Bit 7 W DEVGD2 DEVGD1 DEVGD0 Bit 5 Bit 4 TLB1 Bit 3 TLB0 Bit 2 RLB1 Bit 1 RLB0 Bit 0 VBS DEVGD [2:0]: Sigma Delta Modulator Data Delay Setting. Recommend DEVGD = [000]. TLB [1:0]: LO Buffer Current Select. Recommend TLB[1:0] = [10].
[00]: 0.6mA. [01]: 0.75mA. [10]: 0.9mA. [11]: 1.05mA. RLB [1:0]: RF divider Current Select. Recommend RLB[1:0] = [10].
[00]: 1.2mA. [01]: 1.5mA. [10]: 1.8mA. [11]: 2.1mA. VBCS : VCO Buffer Current Setting. Recommend VBCS = [1].
[0]: 1mA. [1]: 1.5mA. 9.2.54 RF Analog Test Register (Address: 35h) Name RFT R/W Bit 7 W AGT3 Bit 6 AGT2 Bit 5 AGT1 Bit 4 AGT0 Bit 3 RFT3 Bit 2 RFT2 Bit 1 RFT1 Bit 0 RFT0 AGT[3:0]:Page selection for both DASP (2Ah) and ROMP (38h). DASP Register Group ROMP Register Group AGT[3:0]
(35h) 0 1 2 3 4 5 6
(2Ah) DASP0 (page 0) DASP1 (page 1) DADP2 (page 2) DASP3 (page 3) DASP4 (page 4) DASP5 (page 5) DASP6 (page 6)
(38h) ROMP0 (page 0) ROMP1 (page 1) ROMP2 (page 2) ROMP3 (page 3) ROMP4 (page 4) Note Internal usage only Internal usage only Internal usage only Internal usage only Internal usage only Oct., 2012, Version 0.6 (PRELIMINARY) 34 AMICCOM Electronics Corporation RFT [3:0]: RF analog pin configuration for testing. Recommend RFT= [0000]. 9.2.55 AES Key data Register (Address: 36h) Name Key Data R/W Bit 7 KEYO7 R W KEYI7 Bit 5 KEYO5 KEYI5 KEYI [7:0]: AES128 key input, total 16-btyes. (Write only). KEYO [7:0]: AES128 key output, total 16-bytes. (Read only). Select by KEYOS (3Eh). Bit 6 KEYO6 KEYI6 Bit 4 KEYO4 KEYI4 Bit 3 KEYO3 KEYI3 Bit 2 KEYO2 KEYI2 LBA7130 Bit 1 KEYO1 KEYI1 Bit 0 KEYO0 KEYI0 A E S K e y D a t a ( t o t a l 1 6 B y t e s ) K E Y [ 7 : 0 ]
K E Y [ 1 5 : 8 ]
K E Y [ 1 2 7 : 1 2 0 ]
9.2.56 Channel Select Register (Address: 37h) Name Channel Select R/W Bit 7 CHI3 W Bit 6 CHI2 Bit 5 CHI1 Bit 4 CHI0 Bit 3 CHD3 Bit 2 CHD2 Bit 1 CHD1 Bit 0 CHD0 CHI [3:0]: Auto IF Offset Channel Number Setting. Recommend CHI [3:0] = [0111]. FCHSP (CHI + 1 ) = FIF Refer to chapter 14 for FCHSP setting. CHD [3:0]: Channel Frequency Offset for Deviation Calibration. Recommend CHD [3:0] = [0111]. Offset channel number = +/- (CHD + 1). 9.2.57 ROMP0 (Address: 38h, Page 0 by AGT[3:0]=0) Name ROMP0 R/W Bit 7 W MPOR Bit 6 EPRG Bit 5 MIGS Bit 4 MRGS Bit 3 MRSS Bit 2 MTMS Bit 1 MADS Bit 0 MBGS MPOR: manual SPI read in OTP program cycle. EPRG: enable OTP program in test mode.
[0]: disable. [1]: enable. MIGS: IF gain setting select.
[0]: SPI setting. [1]: OTP setting. MRGS: LNA and mixer gain setting select.
[0]: SPI setting. [1]: OTP setting. MRSS: RSSI voltage fine trim setting select.
[0]: SPI setting. [1]: OTP setting. MTMS: Temp voltage fine trim setting select.
[0]: SPI setting. [1]: OTP setting. MADS: ADC fine trim setting select.
[0]: SPI setting. [1]: OTP setting. MBGS: Bandgap voltage fine trim setting select.
[0]: SPI setting. [1]: OTP setting. 9.2.57 ROMP1 (Address: 38h, Page 1 by AGT[3:0]=1) Name ROMP1 R/W Bit 7 W APG Bit 6 MPA1 Bit 5 MPA0 Bit 4 FBG4 Bit 3 FBG3 Bit 2 FBG2 Bit 1 FBG1 Bit 0 FBG0 APG: OTP program select. Oct., 2012, Version 0.6 (PRELIMINARY) 35 AMICCOM Electronics Corporation LBA7130
[1]: auto program. [0]: manual SPI setting. MPA [1:0]: OPT address setting in manual SPI OTP program. FBG [4:0]: Bandgap voltage SPI fine trim setting. 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2) Name ROMP2 R/W Bit 7 W PTM1 Bit 6 PTM0 Bit 5 CTR5 Bit 4 CTR4 Bit 3 CTR3 Bit 2 CTR2 Bit 1 CTR1 Bit 0 CTR0 PTM [1:0]: OTP program operation mode select. Recommend PTM = [00]. CTR [5:0]: ADC voltage SPI fine trim setting. 9.2.57 ROMP3 (Address: 38h, Page 3 by AGT[3:0]=3) Name ROMP3 R/W Bit 7 W FGC1 Bit 6 FGC0 Bit 5 CRS2 Bit 4 CRS1 Bit 3 CRS0 Bit 2 SRS2 Bit 1 SRS1 Bit 0 SRS0 FGC[1:0]: BPF fine gain control. CRS [2:0]: RSSI voltage offset fine trim setting. SRS [2:0]: RSSI voltage curve slope fine time setting. 9.2.57 ROMP4 (Address: 38h, Page 4 by AGT[3:0]=4) Name ROMP4 R/W Bit 7 W
Bit 6 STMP Bit 5 STM5 Bit 4 STM4 Bit 3 STM3 Bit 2 STM2 Bit 1 STM1 Bit 0 STM0 STMP: Temp voltage ADC reading select.
[0]: 1 scale / degree C. [1]: 2 scale/degree C. STM [5:0]: Temperature voltage SPI fine trim setting. 9.2.58 Data Rate Clock Register (Address: 39h) Name Data Rate Clock W R/W Bit 7 SDR7 Bit 6 SDR6 Bit 5 SDR5 Bit 4 SDR4 Bit 3 SDR3 Bit 2 SDR2 Bit 1 SDR1 Bit 0 SDR0 SDR [1:0]: Data Rate Setting. On-air Data rate = FIF / (SDR+1). Xtal 16 MHz Bit 5 RCR3 ARC3 Bit 4 RCR2 ARC2 Bit 3 RCR1 ARC1 Bit 2 RCR0 ARC0 Bit 1 EAK EAK Bit 0 EAR EAR Data Rate 4M Please refer to chapter 13 for details. FIF (Hz) 4M SDR [7:0]
0x00 9.2.59 FCR Register (Address: 3Ah) Bit 6 VPOAK FCL0 FCR Name R/W Bit 7 ARTEF R W FCL1 FCL [1:0] : FCB Length.
[00]: No Frame Control.
[01]: 1 byte FCB (3Dh).
[10]: 2 byte FCB (3Dh).
[11]: 4 byte FCB (3Dh). Please refer to chapter 16 and 19 for details. ARC [3:0] : Auto Resend Cycle Setting.
[0000]: resend disable. Oct., 2012, Version 0.6 (PRELIMINARY) 36 AMICCOM Electronics Corporation LBA7130
[0011]: 3 [0100]: 4 [0101]: 5 [0110]: 6 [0111]: 7 [1000]: 8 [1001]: 9 [1010]: 10
[0010]: 2
[0001]: 1
[1011]: 11 [1100]: 12 [1101]: 13 [1110]: 14 [1111]: 15 EAK : Enable Auto ACK.
[0]: Disable. [1]: Enable. EAR : Enable Auto Resend.
[0]: Disable. [1]: Enable. ARTEF: Auto re-transmission ending flag (read only).
[0]: Resend not end VPOAK : Valid Packet or ACK OK Flag. (read only and auto clear by Strobe command)
[0]: Neither valid packet nor ACK OK. [1]: Valid packet or ACK OK. RCR [3:0] (read) : Decremented of ARC[3:0]. Please refer to chapter 16 and 19 for details.
[1 ]: Finish resend. 9.2.60 ARD Register (Address: 3Bh) Name ARD R/W Bit 7 W ARD7 Bit 6 ARD6 Bit 5 ARD5 Bit 4 ARD4 Bit 3 ARD3 Bit 2 ARD2 Bit 1 ARD1 Bit 0 ARD0 ARD[7:0] : Auto Resend Delay ARD Delay = 200 us * (ARD+1) (200us ~ 51.2 ms)
[0000-0000]: 200 us.
[0000-0001]: 400 us.
[0000-0010]: 600 us.
[1111-1111]: 51.2 ms. Please refer to chapter 19 for details. 9.2.61 AFEP Register (Address: 3Ch) ACKFEP4 ACKFEP3 ACKFEP2 ACKFEP1 ACKFEP0 Bit 1 SID1 Bit 0 SID0 0 0 EAF Bit 3 Bit 4 Bit 5 Bit 6 AFEP Name Bit 2 SID2 SPSS ACKFEP5 EARTS2 EARTS1 EARTS0 R/W Bit 7 R W EAF: Enable ACK FIFO.
[0]: Disable. [1]: Enable. SPSS : Mode Back Select for Auto ACK/Resend.
[0]: Standby mode. [1]: PLL mode. ACKFEP [5:0]: FIFO Length setting for auto-ack packet. ACK FIFO Length = (ACKFEP[5:0] + 1) max. 64 bytes. EARTS [2:0]: Enable Auto Resend Read. SID [2:0]: Serial Packet ID. This device increases SID each time for every new packet and keep the same SID when retransmitting. Please refer to chapter 16 and 19 for details. 9.2.62 FCB Register (Address: 3Dh) Name FCB R/W Bit 7 R/W F7 Bit 6 F6 Bit 5 F5 Bit 4 F4 Bit 3 F3 Bit 2 F2 Bit 1 F1 Bit 0 F0 FCB [7:0]: Frame Control Buffer, total 20-bytes. Oct., 2012, Version 0.6 (PRELIMINARY) 37 AMICCOM Electronics Corporation LBA7130 Strobe Cmd NA NA Bit-Map 0 0 1 1 SID2 SID1 SID0 For auto-resend. Description ACK info by users attaching 1
[7:0]
[7:0]
[7:0]
Byte Name 0 FCB0 FCB1 1 FCB2 2 3 FCB3 Remark:
1. Please refer to section 10.4.10 for details. 2. SID is auto incremental for every new packet if FCB0 is enabled. 3. FCB0 ~ FCB3 is controlled by FCL[1:0] (3Ah) 4. User can attach wanted ACK information to FCB1 ~ FCB3 if auto-ack is enabled (EAK =1). Please refer to chapter 16 and 19 for details. P re a m b le ID c o d e a u to a c k /re se n d F C B 4 b yte s 4 by te s 1 ~ 4 b yte s d y n a m ic F IF O F E P 1 2 b its P H Y H e a d e r (s e lf- g e n e ra te d ) M A C H e a d e r (s e l f-g e n e ra te d ) P a y lo a d P h y . 6 4 b y te s
(C R C ) 2 b yte s 9.2.63 KEYC Register (Address: 3Eh) Name KEYC R/W Bit 7 W KEYOS Bit 6 AFIDS Bit 5 ARTMS Bit 4 MIDS Bit 3 AESS Bit 2
Bit 1 AKFS Bit 0 EDCRS KEYOS: AES128 Key source read select.
[0]: If AKFS=1, from RX received encrypted AES128 key data. If AKFS=0, from SPI write AES128 key data.
[1]: From encrypted/decrypted AES128 key data. Please refer to chapter 21 for details. AFIDS: FIFO ID appendixes Select.
[0]: Disable. [1]: Enable. ARTMS: auto-resend Interval Mode Select.
[0]: random interval. [1]: fixed interval. Please refer to chapter 16 and 19 for details. MIDS: FIFO control byte address mapping for FIFO ID select.
[0]: Received device ID. [1]: internal FIFO control byte ID. AESS: encryption format selection.
[1]: Standard AES 128 bit. [0]: proprietary 32 bit. Please refer to chapter 21 for details. AKFS: Data packet with decrypted key appendixes select.
[0]: Disable. [1]: Enable. EDRCS: Data encrypt or decrypt select.
[0]: Disable. [1]: Enable. 9.2.64 USID Register (Address: 3Fh) Name USID R/W Bit 7 RND7 W Bit 6 RND6 Bit 5 RND5 Bit 4 RND4 Bit 3 RND3 Bit 2 RND2 Bit 1 RND1 Bit 0 RND0 RND [7:0]: Random seed for auto-resend interval. Please refer to chapter 16 and 19 for details. Oct., 2012, Version 0.6 (PRELIMINARY) 38 AMICCOM Electronics Corporation LBA7130 10. SPI A7130 only supports one SPI interface with maximum data rate up to 15Mbps. MCU should assert SCS pin low (SPI chip select) to active accessing of A7130. Via SPI interface, user can access control registers and issue Strobe command. Figure 10.1 gives an overview of SPI access manners. 3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire SPI, SDIO pin is configured as bi-direction to be data input and output. For 4-wire SPI, SDIO pin is data input and GIO1 (or GIO2) pin is data output. In such case, GIO1S (0bh) or GIO2S (0ch) should be set to [0110]. For SPI write operation, SDIO pin is latched into A7130 at the rising edge of SCK. For SPI read operation, if input address is latched by A7130, data output is aligned at falling edge of SCK. Therefore, MCU can latch data output at the rising edge of SCK. To control A7130s internal state machine, it is very easy to send Strobe command via SPI interface. The Strobe command is a unique command set with total 8 commands. See section 10.3, 10.4 and 10.5 for details. 3-Wire SPI 4-Wire SPI SPI chip select Data In SCS pin = 0 SDIO pin Data Out SDIO pin SCS pin = 0 SDIO pin GIO1 (GIO1S=0110) /
GIO2 (GIO2S=0110) SCS Read/Write register ADDRreg DataByte ADDRreg DataByte ADDRreg DataByte Read/Write RF FIFO Read/Write ID register Sleep Mode Idle Mode STBY Mode PLL Mode RX Mode TX Mode ADDRFIFO DataByte0 DataByte1 DataByte2 DataByte3 DataByten ADDRID DataByte0 DataByte1 DataByte2 DataByte3 Strobe CommandSleep Mode Strobe CommandIdle Mode Strobe CommandSTBY Mode Strobe CommandPLL Mode Strobe CommandRX Mode Strobe CommandTX Mode FIFO Write Reset FIFO Read Reset Strobe CommandFIFO Write Reset Strobe CommandFIFO Read Reset Figure 10.1 SPI Access Manners Oct., 2012, Version 0.6 (PRELIMINARY) 39 AMICCOM Electronics Corporation LBA7130 10.1 SPI Format The first bit (A7) is critical to indicate A7130 the following instruction is Strobe command or control register. See Table 10.1 for SPI format. Based on Table 10.1, To access control registers, just set A7=0, then A6 bit is used to indicate read (A6=1) or write operation (A6=0). See Figure 10.2 (3-wire SPI) and Figure 10.3 (4-wire SPI) for details. A1 A0 7 6 5 4 Table 10.1 SPI Format Data Byte (8 bits) Data 3 2 1 0 CMD R/W A7 A6 A5 Address Byte (8 bits) Address A2 A4 A3 Address byte:
Bit 7: Command bit
[0]: Control registers.
[1]: Strobe command. Bit 6: R/W bit
[0]: Write data to control register.
[1]: Read data from control register. Bit [5:0]: Address of control register Data Byte:
Bit [7:0]: SPI input or output data, see Figure 10.2 and Figure 10.3 for details. 10.2 SPI Timing Characteristic No matter 3-wire or 4-wire SPI interface is configured, the maximum SPI data rate is 10 Mbps. To active SPI interface, SCS pin must be set to low. For correct data latching, user has to take care hold time and setup time between SCK and SDIO. See Table 10.2 for SPI timing characteristic. Parameter FC TSE THE TSW THW TDR Description FIFO clock frequency. Enable setup time. Enable hold time. TX Data setup time. TX Data hold time. RX Data delay time. Min. 50 50 50 50 0 Max. 10 50 Unit MHz ns ns ns ns ns Table 10.2 SPI Timing Characteristic Oct., 2012, Version 0.6 (PRELIMINARY) 40 AMICCOM Electronics Corporation LBA7130 10.3 SPI Timing Chart In this section, 3-wire and 4-wire SPI interface read / write timing are described. 10.3.1 Timing Chart of 3-wire SPI SCS SCK SDIO SCS SCK SDIO A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at the rising edge of SCK 3-Wire serial interface - Write operation A7 A6 A5 A4 A3 A2 A1 A0 DR7 DR6 DR5 DR1 DR0 RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at rising edge of SCK 3-Wire serial interface - Read operation Figure 10.2 Read/Write Timing Chart of 3-Wire SPI 10.3.2 Timing Chart of 4-wire SPI SCS SCK SDIO SCS SCK SDI GIOx A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 RF IC will latch address bit at rising edge of SCK RF IC will latch data bit at rising edge of SCK 4-Wire serial interface - Write operation A7 A6 A5 A4 A3 A2 A1 A0 x x DR7 DR6 DR5 DR2 DR1 DR0 RF IC will latch address bit at rising edge of SCK RF IC will change the data when falling edge of SCK MCU can latch data at the rising edge of SCK 4-Wire serial interface - Read operation Figure 10.3 Read/Write Timing Chart of 4-Wire SPI Oct., 2012, Version 0.6 (PRELIMINARY) 41 AMICCOM Electronics Corporation LBA7130 10.4 Strobe Commands A7130 supports 8 Strobe commands to control internal state machine for chips operations. Table 10.3 is the summary of Strobe commands. Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected, A3
~ A0 are dont care conditions. In such case, SCS pin can be remaining low for asserting next commands. Strobe Command when AFIDS =0 (3Eh) and MIDS =0 (3Eh) Description Strobe Command A5 0 0 0 0 1 1 0 0 1 1 A3 1 1 x x x x x x x x Remark: x means dont care A7 1 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 1 1 1 1 A4 0 0 0 1 0 1 0 1 0 1 A2 0 0 x x x x x x x x A1 0 1 x x x x x x x x Idle mode A0 0 Deep Sleep mode (I/Os are in tri-state) 1 Deep Sleep mode (I/Os are pulled high) x Sleep mode x x Standby mode x PLL mode x RX mode x TX mode x FIFO write pointer reset x FIFO read pointer reset Table 10.3 Strobe Commands by SPI interface 10.4.1 Strobe Command - Sleep Mode Refer to Table 10.3 user can issue 4 bits (1000) Strobe command directly to set A7130 into Sleep mode. Below are the Strobe command table and timing chart. Strobe Command A7 1 A6 0 Strobe Command A5 0 A4 0 A3 x A2 X A1 x Description A0 x Sleep mode Figure 10.4 Sleep mode Command Timing Chart 10.4.2 Strobe Command - ldle Mode Refer to Table 10.3, user can issue 4 bits (1001) Strobe command directly to set A7130 into Idle mode. Below is the Strobe command table and timing chart. Oct., 2012, Version 0.6 (PRELIMINARY) 42 AMICCOM Electronics Corporation LBA7130 A2 X A1 x A0 x Description Idle mode SCS SCK Strobe Command Strobe Command A5 0 A4 1 A3 x A7 1 A6 0 SCS SCK SDIO A7 A6 A5 A4 SDIO A7 A6 A5 A4 A3 A2 A1 A0 Idle mode Idle mode Figure 10.5 Idle mode Command Timing Chart 10.4.3 Strobe Command - Standby Mode Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7130 into Standby mode. Below is the Strobe command table and timing chart. Strobe Command A7 1 A6 0 Strobe Command A5 1 A4 0 A3 x A2 X A1 x Description A0 x Standby mode 10.4.4 Strobe Command - PLL Mode Figure 10.6 Standby mode Command Timing Chart Refer to Table 10.3, user can issue 4 bits (1011) Strobe command directly to set A7130 into PLL mode. Below are the Strobe command table and timing chart. Strobe Command A7 1 A6 0 Strobe Command A5 1 A4 1 A3 x A2 X A1 x Description A0 x PLL mode Oct., 2012, Version 0.6 (PRELIMINARY) 43 AMICCOM Electronics Corporation LBA7130 10.4.5 Strobe Command - RX Mode Figure 10.7 PLL mode Command Timing Chart Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7130 into RX mode. Below are the Strobe command table and timing chart. Strobe Command A7 1 A6 1 Strobe Command A5 0 A4 0 A3 x A2 X A1 x Description A0 x RX mode 10.4.6 Strobe Command - TX Mode Figure 10.8 RX mode Command Timing Chart Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7130 into TX mode. Below are the Strobe command table and timing chart. Strobe Command A7 1 A6 1 Strobe Command A5 0 A4 1 A3 x A2 x A1 x Description A0 x TX mode 10.4.7 Strobe Command FIFO Write Pointer Reset Figure 10.9 TX mode Command Timing Chart Oct., 2012, Version 0.6 (PRELIMINARY) 44 AMICCOM Electronics Corporation Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7130 FIFO write pointer. Below is the Strobe command table and timing chart. LBA7130 Strobe Command A7 1 A6 1 Strobe Command A5 1 A4 0 A3 x A2 x A1 x Description A0 x FIFO write pointer reset Figure 10.10 FIFO write pointer reset Command Timing Chart 10.4.8 Strobe Command FIFO Read Pointer Reset Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7130 FIFO read pointer. Below are the Strobe command table and timing chart. Strobe Command A7 1 A6 1 Strobe Command A5 1 A4 1 A3 x A2 x A1 x Description A0 x FIFO read pointer reset Figure 10.11 FIFO read pointer reset Command Timing Chart 10.4.9 Strobe Command Deep Sleep Mode Refer to Table 10.3, user can issue (8 bits) deep sleep Strobe command directly to switch off power supply to A7130.In this mode, A7130 is staying minimum current consumption. All registers are no data retention and re-calibration flow is necessary. Below are the Strobe command table and timing chart. Strobe Command A7 1 1 A6 0 0 Strobe Command A5 0 0 A4 0 0 A3 1 1 A2 0 0 A1 0 1 Description A0 0 Tri-state of GIO1 / GIO2 (no register retention) 1 Internal Pull-High of GIO1 / GIO2 (no register retention) Oct., 2012, Version 0.6 (PRELIMINARY) 45 AMICCOM Electronics Corporation LBA7130 Figure 10.12 Deep Sleep Mode Timing Chart 10.5 Reset Command In addition to power on reset (POR), MCU could issue software reset to A7130 by setting Mode Register (00h) through SPI interface as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7130 is informed to generate internal signal RESETN to initial itself. After reset command, A7130 is in standby mode and calibration procedure shall be issued again. SCS SCK SDIO RESETN A7 A6 A5 A4 A3 A2 A1 A0 DW7 DW6 DW5 DW1 DW0 10.6 ID Accessing Command Figure 10.14 Reset Command Timing Chart Reset RF chip A7130 has built-in 32-bits ID Registers for customized identification code. It is accessed via SPI interface. ID length is recommended to be 32 bits by setting IDL (1Fh). Therefore, user can toggle SCS pin to high to terminate ID accessing command when ID data is output completely. Figure 10.13 and 10.14 are timing charts of 32-bits ID accessing via 3-wire SPI. 10.6.1 ID Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of ID write command. Step1: Deliver A7~A0 = 00000110 (A6=0 for write, A5~A0 = 000110 for ID addr, 06h). Step2: By SDIO pin, deliver 32-bits ID into A7130 in sequence by Data Byte 0 (recommend 5xh or Axh), 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Oct., 2012, Version 0.6 (PRELIMINARY) 46 AMICCOM Electronics Corporation LBA7130 Figure 10.15 ID Write Command Timing Chart 10.6.2 ID Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command. Step1: Deliver A7~A0 = 01000110 (A6=1 for read, A5~A0 = 000110 for ID addr, 06h). Step2: SDIO pin outputs 32-bits ID in sequence by Data Byte 0, 1, 2 and 3. Step3: Toggle SCS pin to high when step2 is completed. Figure 10.16 ID Read Command Timing Chart 10.7 FIFO Accessing Command To use A7130s FIFO mode, enable FMS (01h) =1 via SPI interface. Before TX delivery, just write wanted data into TX FIFO
(05h) then issue TX Strobe command. Similarly, user can read RX FIFO (05h) once payload data is received. MCU can use polling or interrupt scheme to do FIFO accessing. FIFO status can output to GIO1 (or GIO2) pin by setting GIO1S (0Bh) or GIO2S (0Ch). Figure 10.15 and 10.16 are timing charts of FIFO accessing via 3-wire SPI. 10.7.1 TX FIFO Write Command User can refer to Figure 10.2 for SPI write timing chart in details. Below is the procedure of TX FIFO write command. Step1: Deliver A7~A0 = 00000101 (A6=0 for write control register and issue FIFO A [5:0] = 05h). Step2: By SDIO pin, deliver (n+1) bytes TX data into TX FIFO in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when step2 is completed. Step4: Send Strobe command of TX mode (Figure 10.9) to do TX delivery. Oct., 2012, Version 0.6 (PRELIMINARY) 47 AMICCOM Electronics Corporation LBA7130 Figure 10.17 TX FIFO Write Command Timing Chart 10.7.2 Rx FIFO Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of RX FIFO read command. Step1: Deliver A7~A0 = 01000101 (A6=1 for read control register and issue FIFO at address 05h). Step2: SDIO pin outputs RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n. Step3: Toggle SCS pin to high when RX FIFO is read completely. Figure 10.18 RX FIFO Read Command Timing Chart Oct., 2012, Version 0.6 (PRELIMINARY) 48 AMICCOM Electronics Corporation LBA7130 11. State machine From accessing data point of view, if FMS=1, FIFO mode is enabled, otherwise, A7130 is in direct mode. SPI chip select SCS SCS SPI Clock SCK SCK SPI Data In SDIO SPI Data Out SDIO SDIO GIO1 or GIO2 3-Wire SPI 4-Wire SPI FMS register FIFO (FMS=1) Direct (FMS=0) FIFO (FMS=1) Direct (FMS=0) From current consumption point of view, A7130 has below 8 operation modes.
(1) Deep Sleep mode
(2) Sleep mode
(3) Idle mode
(4) Standby mode
(5) PLL mode
(6) TX mode
(7) RX mode
(8) Star-networking mode 11.1 Key states After power on reset or software reset or deep sleep mode, user has to do calibration process because all control registers are in initial values. The calibration process of A7130 is very easy, user only needs to issue Strobe commands and enable calibration registers. And then, the calibrations are automatically completed by A7130s internal state machine. Table 11.1 shows a summary of key circuitry among those strobe commands. A7 1 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 1 1 1 1 Mode Deep Sleep
(Tri-state) Deep Sleep
(pull-high) Sleep Idle Standby PLL TX RX Strobe Command when AFIDS =0 (3Eh) and MIDS =0 (3Eh) Description Strobe Command A5 0 0 0 0 1 1 0 0 1 1 A4 0 0 0 1 0 1 0 1 0 1 A3 1 1 x x x x x x x x A2 0 0 x x x x x x x x A1 0 1 x x x x x x x x Idle mode A0 0 Deep Sleep mode (I/Os are in tri-state) 1 Deep Sleep mode (I/Os are pulled high) x Sleep mode x x Standby mode x PLL mode x RX mode x TX mode x FIFO write pointer reset x FIFO read pointer reset Register retention Regulator Xtal Osc. VCO PLL No No Yes Yes Yes Yes Yes Yes OFF OFF ON ON ON ON ON ON OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF ON ON ON RX OFF OFF OFF OFF OFF OFF OFF ON TX OFF OFF OFF OFF OFF OFF ON OFF Strobe Command
(1000-1000)b
(1000-1011)b
(1000-xxxx)b
(1001-xxxx)b
(1010-xxxx)b
(1011-xxxx)b
(1101-xxxx)b
(1100-xxxx)b Remark: x means dont care Table 11.1. Operation mode and strobe command Oct., 2012, Version 0.6 (PRELIMINARY) 49 AMICCOM Electronics Corporation LBA7130 11.2 FIFO mode This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transmission, only one Strobe command is needed. Once transmission is done, A7130 is auto back to standby mode. Figure 11.1 and Figure 11.2 are TX and RX timing diagram respectively. Figure 11.3 illustrates state diagram of FIFO mode. Strobe CMD
(SCS,SCK,SDIO) TX Strobe RF settling 10us +(PDL+TDL) RFO Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) Preamble + ID Code + Payload Transmitting Time Next Instruction T0 T1 Auto Back Standby Mode T2 Figure 11.1 TX timing of FIFO Mode Strobe CMD
(SCS,SCK,SDIO) RX strobe RX settling Wait Packet RFI Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) Preamble + ID Code + Payload Receiving Time Next Instruction T0 T1 T2 Auto Back Standby Mode T3 Figure 11.2 RX timing of FIFO Mode Oct., 2012, Version 0.6 (PRELIMINARY) 50 AMICCOM Electronics Corporation LBA7130 Figure 11.3 State diagram of FIFO Mode 11.3 Direct mode This mode is suitable to let MCU to drive customized packet to A7130 directly by setting FMS = 0. In TX mode, MCU shall send customized packet in bit sequence (simply called raw TXD) to GIO1 or GIO2 pin. In RX mode, the receiving raw bit streams (simply called RXD) can be configured output to GIO1 or GIO2 pin. Be aware that a customized packet shall be preceded by a 32 bits preamble to let A7130 get a suitable DC estimation voltage. After calibration flow, for every state transition, user has to issue Strobe command to A7130 for fully manual control. This mode is also suitable for the requirement of versatile packet format. Figure 11.4 and Figure 11.5 are TX and RX timing diagram in direct mode respectively. Figure 14.6 illustrates state diagram of direct mode. Oct., 2012, Version 0.6 (PRELIMINARY) 51 AMICCOM Electronics Corporation LBA7130 RF settling 10us+(PDL+TDL) Carrier only Modulated signals Preamble + customized raw TXD STB strobe Manually back to STB Modulation auto enable 32-bits preamble T0 T1 T3 T4 Figure 11.4 TX timing of Direct Mode RX settling Wait packet Coming packet Preamble + customized raw TXD STB strobe Manually back to STB Preamble detect output Strobe CMD
(SCS,SCK,SDIO) TX Strobe RFO Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - TMEO
(GIO1S[3:0]=0010) GIO2 Pin - TXD
(GIO2S[3:0]=1001) Strobe CMD
(SCS,SCK,SDIO) RX Strobe RFO Pin GIO1 Pin - WTR
(GIO1S[3:0]=0000) GIO1 Pin - PMDO
(GIO1S[3:0]=0011) GIO2 Pin - RXD
(GIO2S[3:0]=1000) T0 T1 T3 T4 Figure 11.5 RX timing of Direct Mode Oct., 2012, Version 0.6 (PRELIMINARY) 52 AMICCOM Electronics Corporation LBA7130 Figure 11.6 State diagram of Direct Mode Oct., 2012, Version 0.6 (PRELIMINARY) 53 AMICCOM Electronics Corporation LBA7130 12. Crystal Oscillator A7130 needs external crystal or external clock that is either 16 MHz (or 18MHz) to generate internal wanted clock. Relative Control Register Clock Register (Address: 0Dh) Name Clock R/W Bit 7 CGC1 W IFS1 R Bit 6 CGC0 IFS0 Bit 5 GRC3 GRC3 Bit 4 GRC2 GRC2 Bit 3 GRC1 GRC1 Bit 2 GRC0 GRC0 Bit 1 CGS
Bit 0 XS
12.1 Use External Crystal Figure 12.1 shows the connection of crystal network between XI and XO pins. C1 and C2 capacitance built inside A7130 are used to adjust different crystal loading. User can set INTXC [4:0] to meet crystal loading requirement. A7130 supports low cost crystal within 50 ppm accuracy. Be aware that crystal accuracy requirement includes initial tolerance, temperature drift, aging and crystal loading. Crystal Accuracy 50 ppm Crystal ESR 80 ohm Fig12.1 Crystal oscillator circuit, set INTXC[4:0] for the internal C1 and C2 values. 12.2 Use External Clock A7130 has built-in AC couple capacitor to support external clock input. Figure 12.2 shows how to connect. In such case, XI pin is left opened. XS shall be low to select external clock. The frequency accuracy of external clock shall be controlled within 50 ppm, and the amplitude of external clock shall be within 1.2 ~ 1.8 V peak-to-peak. Fig12.2 External clock source. R is used to tune Vpp = 1.2~1.8V Oct., 2012, Version 0.6 (PRELIMINARY) 54 AMICCOM Electronics Corporation LBA7130 13. System Clock A7130 supports different crystal frequency by programmable Clock Register. Based on this, three important internal clocks FCGR , FDR and FSYCK are generated.
(1) FXTAL: Crystal frequency.
(2) FXREF: Crystal Ref. Clock = FXREF * (DBL+1).
(3) FCGR: Clock Generation Reference = 2MHz = FXREF / (GRC+1).
(4) FSYCK: System Clock is related to FIF and FDR.
(6) FDR: Data Rate Clock = FIF / (SDR+1). Data Rate DBL (0Fh) 4Mbps 4Mbps 0 (FIFO mode) 1 (Direct mode) FCGR 2MHz 2MHz CLK Gen. FCGR X 32 FCGR X 64 FSYCK 64MHz 128MHz FIF 4MHz 4MHz FDR 4MHz 4MHz Table 13.1 System clock and related clock sources XI XO FXTAL GRC RDU/CGC CGS CE XS CE CE FXREF DBL X 2 0 1
(GRC+1) PLL x64/x32 FCGR= 2MHz Clock Generator 1 0 FSYCK FIF auto scaler FDR
/ (SDR+1) FPFD
/ (RRC+1) VCO auto scaler
/ 2 4MHz 8MHz 0 1 FADC FSARS Fig13.1 System clock block diagram 13.2 Data Rate Setting User has to choose 16MHz Xtal (or 18MHz) for 4Mbps applications. For more data rate options, please contact AMICCOM FAE team. Data rate 4Mbps Xtal 16MHz 16MHz DBL
(0Fh) 0 1 GRC
(0Dh) 0111 1111 RDU
(1Ch) 0 0 CGS
(0Dh) 1 1 RRC
(0Fh) 00 00 CGC
(0Dh) 10 10 CGS
(0Dh) 1 1 IFS
(1Ch) 11 11 SDR [7:0]
Note
(39h) 0x00 FIFO mode 0x00 Direct mode Oct., 2012, Version 0.6 (PRELIMINARY) 55 AMICCOM Electronics Corporation LBA7130 14. Transceiver LO Frequency A7130 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up LO
(Local Oscillator) frequency for two ways radio transmission. To target full range of 2.4GHz ISM band (2408 MHz to 2468 MHz), A7130 applies offset concept by LO frequency FLO =
FLO_BASE + FOFFSET. Therefore, this device is easy to implement frequency hopping and multi-channels by just ONE register setting, PLL Register I (CHN [7:0]). Below is the LO frequency block diagram. FXTAL X (DBL+1)
/ (RRC[1:0]+1) BIP[8:0] +
BFP[15:0]/ 2 16 CHN / [4*(CHR+1)]
1 0 0 AC[14:0]/ 216 FLO_BASE
FOFFSET PFD VCO FLO Divider FPFD AFC FLO
Fig14.1 Frequency synthesizer block diagram 14.1 LO Frequency Setting From Figure 14.1, FLO is not only for TX radio frequency but also to be RX LO frequency. To set up FLO, it is easy by below 4 steps. 1. 2. 3. 4. Set FLO_BASE ~ 2400.001MHz. Set FCHSP = 500 KHz. Set FOFFSET = CHN [7:0] x FCHSP The LO frequency, FLO = FLO_BASE + FOFFSET FLO_BASE FLO FLO_BASE F LO_BASE
F PFD
BIP
]0:8[
FOFFSET BFP
]0:15[
16 2
DBL
)1
F XTAL RRC 1]0:1[
BIP
]0:8[
BFP
]0:15[
16 2
) Base on the above formula, i.e. 16 MHz, please refer to Table 14.1 and 14.2 as a calculation example to get LO frequency. DBL = 0 for FIFO mode STEP 1 2 ITEMS FXTAL DBL VALUE 16 MHz 0 NOTE Crystal Frequency Disable double function Oct., 2012, Version 0.6 (PRELIMINARY) 56 AMICCOM Electronics Corporation LBA7130 3 4 5 6 RRC BIP[8:0]
BFP[15:0]
FLO_BASE 0 0x096 0x0004 2400.001 MHz If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency 1 2 3 4 5 6 1 2 1 1 0 0 DBL = 1 for Direct mode STEP ITEMS FXTAL DBL RRC BIP[8:0]
BFP[15:0]
FLO_BASE ITEMS FLO_BASE CHR[3:0]
4 6 7 CHN[7:0]
FLO FTXRF How to set FTXRF = FLO = FLO_BASE + FOFFSET ~ 2405.001 MHz VALUE STEP VALUE 16 MHz 1 0 0x04B 0x0002 NOTE Crystal Frequency Enable double function If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency 2400.001 MHz Table 14.1 How to set FLO_BASE 2400.001 MHz
[0111]
[1111]
0x0A 2405.001 MHz 2405.001 MHz Table 14.2 How to set FTXRF NOTE After set up BIP and BFP To get FCHSP= 500 KHz if DBL =0 for FIFO mode. To get FCHSP= 500 KHz if DBL =1 for Direct mode. FOFFSET= 500 KHz * (CHN) = 5MHz Get FLO= FLO_BASE + FOFFSET FTXRF = FLO For 16MHz crystal, below is the calculation detail for FFPD and FCHSP. F CHSP
F PFD
CHR 0:3 4
)1
FXTAL (MHz) 16 16 DBL
(0Fh) 0 1 RRC
(0Fh) 00 00 FPFD (MHz) CHR [3:0]
FCHSP (KHz) Note 16 32 0111 1111 500 500 Recommend Recommend 14.2 IF Side Band Select Since A7130 is a low-IF TRX, in RX mode, the FRXLO shall be set to shift a FIF (i.e. FIF = 4MHz @ 4Mbps) regarding to coming FTXRF. Therefore, A7130 offers two methods to set up FLO while A7130 is exchanging from TX mode to RX mode. AIF register is used to enable Auto IF function for Auto IF exchange mode. And ULS registers is used for fast exchange mode because of reduction of PLL settling time.
(1) Auto IF exchange mode AIF (01h) ULS (19h)
(2) Fast exchange mode AIF (01h) ULS (19h) 0 1 0 1 FRXLO Formula FRXLO = FLO FIF FRXLO = FLO FIF Note Auto-minus a FIF because ULS = 0 Auto-plus a FIF because ULS = 1 FRXLO Formula FRXLO = FLO FRXLO = FLO Note The coming FTXRF shall be (FRXLO + FIF ) The coming FTXRF shall be (FRXLO - FIF ) Oct., 2012, Version 0.6 (PRELIMINARY) 57 AMICCOM Electronics Corporation LBA7130 14.2.1 Auto IF Exchange A7130 supports Auto IF offset function by setting AIF = 1. In such case, FTXRF between master and slave is the same so that there is only one carrier frequency (Fcarrier) during communications. Meanwhile, FRXLO during TRX exchanging is auto shifted FIF. See below Figures and Table 14.3 for details. Master AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXRF for a (FIF). FLO_BASE FRXLO FTXRF = FLO = FCarrier FOFFSET =5MHz FIF 4MHz @ 4Mbps Master TX RX AIF 1 1 ULS 0 0 CHN[7:0]
0x0A 0x0A FCHSP (KHz) FLO_BASE (MHz) 500 500 2400.001 2400.001 Slave AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXRF for a (FIF). FLO_BASE FRXLO FTXRF = FLO = FCarrier FOFFSET =5MHz FIF 4MHz @ 4Mbps Slave TX RX AIF 1 1 ULS 0 0 CHN[7:0]
0x0A 0x0A FCHSP (KHz) FLO_BASE (MHz) 500 500 2400.001 2400.001 FTXRF (MHz) 2405.001
FTXRF (MHz) 2405.001
FRXLO (MHz)
2401.001 FRXLO (MHz)
2401.001 Table 14.3 Auto IF exchange mode while TRX exchanging Oct., 2012, Version 0.6 (PRELIMINARY) 58 AMICCOM Electronics Corporation LBA7130 14.2.2 Fast Exchange Fast exchange can reduce the PLL settling time during TRX exchanging because FRXLO and FTXRF are kept to the same FLO in either master or slave side. However, there are two on-air frequency (FCarrier (master), FCarrier (slave)) during communications. In such case, user has to control ULS =0 in master side and ULS = 1 in slave side for two ways radio. See below Figures and Table 14.4 for details. Master AIF=0 and ULS=0, Master is set to up side band. FTXLO = FLO = FCarrier (Master) FLO_BASE FRXLO FOFFSET =5MHz Slave AIF=0 and ULS=1, Slave is set to low side band. FIF 4MHz @ 4Mbps FLO_BASE FOFFSET =9MHz Master TX RX Slave TX RX AIF 0 0 AIF 0 0 ULS 0 0 ULS 1 1 CHN[7:0]
0x0A 0x0A CHN[7:0]
0x12 0x12 FTXLO= FLO = FCarrier (Slave) FRXLO FCHSP (KHz) FLO_BASE (MHz) 500 500 500 500 2400.001 2400.001 2400.001 2400.001 FTXRF (MHz) 2405.001
FTXRF (MHz) 2409.001
FRXLO (MHz) 2405.001 FRXLO (MHz) 2409.001
FCHSP (KHz) FLO_BASE (MHz) Table 14.4 Fast exchange mode while TRX exchanging Oct., 2012, Version 0.6 (PRELIMINARY) 59 AMICCOM Electronics Corporation LBA7130 14.3 Auto Frequency Compensation The AFC function (Auto Frequency Compensation) supports to use low accuracy crystal (50 ppm) on A7130 without sensitivity degradation. The AFC concept is automatically fine tune RX LO frequency (FRXLO). User can read AC [14:0] to know the compensation value of FRXLO. FXTAL X (DBL+1)
/ (RRC[1:0]+1) FPFD PFD FLO VCO BIP[8:0] +
BFP[15:0]/ 2 16 CHN / [4*(CHR+1)]
1 0 AFC AC[14:0]/ 216 0 FLO_BASE
FOFFSET FLO
Divider Figure 14.3 Block Diagram of enabling AFC function For AFC procedure, please refer to A7130s reference code and contact AMICCOM FAE team for details. 15. Calibration A7130 needs calibration process after deep sleep mode or power on reset or software reset. Below are six calibration items inside the device. 1. 2. 3. 4. 5. 6. VCO Current Calibration. VCO Bank Calibration. VCO Deviation Calibration. IF Filter Bank Calibration. RSSI Calibration. RC Oscillator Calibration. 15.1 Calibration Procedure The purpose to execute the above calibration items is to deal with Foundry process deviation. After calibrations, A7130 will be set to the best working conditions without concerning Foundry process deviation to impact A7130s RF performance. In general, user can use A7130s auto calibration function by just enabling calibration items and checking its calibration flag. For detailed calibration procedures, please refer to A7130 reference code of initRF() subroutine and A7130_Cal() subroutine. 1. Initialize A7130 by calling the subroutine of initRF(). n n Initialize all control registers by calling the subroutine of A7130_Config(). Execute all calibration items by calling the subroutine of A7130_Cal(). Oct., 2012, Version 0.6 (PRELIMINARY) 60 AMICCOM Electronics Corporation LBA7130 16. FIFO (First In First Out) A7130 has the separated physical 64-bytes TX and RX FIFO inside the device. To use A7130s FIFO mode, user just needs to enable FMS =1. For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, RX circuitry synchronizes ID Code and stores received payload into RX FIFO. 16.1 TX Packet Format in FIFO mode 16.1.1 Basic FIFO mode If FCL[1:0] = 00 and ENRL = 0, A7130 is formed a Basic FIFO mode which can also support Auto-ack/ Auto-resend function. There is no MAC header in TX packet format. ID code is a PHY header used to be the frame sync to enable RX FIFO receiving. D a ta w h iten in g (o p tio n a l) F E C e nc o d ed /d e co d e d (o p tio n a l) C R C -1 6 c alc u la tio n (o p tio n a l) P re a m b le 4 b yte s ID co d e 4 b y te s ID code P ay lo a d P h y . 6 4 b y te s
(C R C ) 2 by te s ID Byte 0 ID Byte 1 ID Byte 2 ID Byte 3 Figure 16.1 TX packet format of basic FIFO mode Preamble:
The packet is led by a self-generated preamble which is composed of alternate 0 and 1. If the first bit of ID code is 0, preamble shall be 01010101. In the contrast, if the first bit of ID code is 1, preamble shall be 10101010. Preamble length is recommended to set 4 bytes by PML [1:0] (20h). ID code:
ID code is recommended to set 4 bytes by IDL[1:0] = [01] and ID Code is stored into ID Data register by sequence ID Byte 0, 1, 2 and 3. If RX circuitry check ID code is correct, payload will be written into RX FIFO. In addition, user can set ID code error tolerance (0~ 7bit error) by setting ETH [2:0] during ID synchronization check. Payload:
Payload length is programmable by FEP [11:0]. The physical FIFO depth is 64 bytes. A7130 also supports logical FIFO extension up to 4K bytes. CRC:
In FIFO mode, if CRC is enabled (CRCS=1), 2-bytes of CRC value is self-generated and attached at the footer of the packet. In the same way, RX circuitry will check CRC value and show the result to CRC Flag. 16.1.2 Advanced FIFO mode A7130 supports to self generated MAC header to form an advanced FIFO mode by enabling FCL[1:0], ENRL.. Therefore, A7130 can support ACK FIFO (FCB1~FCB3) and dynamic FIFO length depending on configurations. Oct., 2012, Version 0.6 (PRELIMINARY) 61 AMICCOM Electronics Corporation LBA7130 P re a m b le ID c o d e a u to a c k /re se n d F C B d y n a m ic F IF O F E P P a y lo a d 4 b y te s 4 b yte s 1 ~ 4 b y te s 1 2 b its P h y . 6 4 b y te s
(C R C ) 2 b yte s P H Y H e a d e r (s e lf- g e n e ra te d ) M A C H e a d e r (s e lf -g e n e ra te d ) Figure 16.2 TX packet format of advanced FIFO mode. FCB:
If FCL[1:0] 00, FCB header is enabled to support ACK FIFO by (FCB1~FCB3). The FCB is frame control byte. FCB0 is NOT allowed to program but carry a dedicated header (00111b) and SID [2:0] (Serial ID of packet number). FCB1~3 are used for customized information in FCB field. FCB FCB 0 FCB 1 FCB 2 FCB 3 Figure 16.3 FCB (Frame Control Field) FEP:
If ENRL = 1, A7130 supports dynamic FIFO. FEP [11:0] is self-generated to add into TX packet. In RX side, FEP[11:0] of the coming TX packet will be detected and stored into LENF [11:0] register. HEC:
If HECS = 1, A7130 supports to self-generated a HEC byte which is a local CRC-8 of the MAC header. This HEC byte is an optional feature to calculate CRC result of MAC Header. HEC is located at the end of the MAC header. P re a m b le ID c o d e F C B F E P M A C h e a d e r H e a d e r C R C H E C P a y lo a d 4 b yte s 4 by te s 1 ~ 4 b yte s 1 2 b its 1 b y te P h y . 6 4 b y te s
(C R C ) 2 b yte s P H Y H e a d e r (s e lf- g e n e ra te d ) M A C H e a d e r (s e l f-g e n e ra te d ) Figure 16.4 HEC (CRC for MAC Header) 16.2 Bit Stream Process in FIFO mode A7130 supports 3 optional bit stream process for payload in FIFO mode, they are,
(1) CCITT-16 CRC
(2) (7, 4) Hamming FEC
(3) Data Whitening by XOR PN7 (7-bits Pseudo Random Sequence). The initial seed of PN7 is set by WS [6:0]
CRC (Cyclic Redundancy Check):
1. 2. CRC is enabled by CRCS= 1. TX circuitry calculates the CRC value of payload (preamble and ID code are excluded) and transmits 2-bytes CRC value after payload. RX circuitry checks CRC value and shows the result to CRCF. If CRCF=0, received payload is correct, else error occurred. Oct., 2012, Version 0.6 (PRELIMINARY) 62 AMICCOM Electronics Corporation LBA7130 FEC (Forward Error Correction):
1. 2. 3. FEC is enabled by FECS= 1. Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code. Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically.
(ex., 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.) RX circuitry decodes received code words automatically. Each code word can correct 1-bit error. Once 1-bit error occurred, FECF=1 (00h). Data Whitening:
1. 2. Data whitening is enabled by WHTS= 1. Payload and CRC value (if CRCS=1) or their encoded code words (if FECS=1) are encrypted by bit XOR operation with PN7. The initial seed of PN7 is set by WS [6:0]. RX circuitry decrypts received payload and 2-bytes CRC (if CRCS=1) automatically. Please noted that user shall set the same WS [6:0] (22h) to TX and RX. 16.3 Transmission Time Based on CRC and FEC options, the transmission time are different. See table 16.1 for details. Data Rate = 4 Mbps Data Rate Preamble 4Mbps
(bits) 32 32 32 32 ID Code
(bits) 32 32 32 32 Payload
(bits) 512 512 512 512 CRC
(bits) Disable 16 bits Disable 16 x 7 / 4 FEC Disable Disable 512 x 7 / 4 512 x 7 / 4 Transmission Time / Packet 576 bit X 0.25 us = 144 us 592 bit X 0.25 us = 148 us 960 bit X 0.25 us = 240 us 988 bit X 0.25 us = 247 us Table 16.1 Transmission time 16.4 Usage of TX and RX FIFO In application points of view, A7130 supports 2 options of FIFO arrangement.
(1) Easy FIFO
(2) Segment FIFO
(3) FIFO extension For FIFO operation, A7130 supports Strobe command to reset TX and RX FIFO pointer as shown below. User can refer to section 10.5 for details. Strobe Command A7 1 1 A6 1 1 Strobe Command A5 1 1 A4 0 1 A3 x x A2 x x A1 X X Description A0 x FIFO write pointer reset (for TX FIFO) x FIFO read pointer reset (for RX FIFO) Oct., 2012, Version 0.6 (PRELIMINARY) 63 AMICCOM Electronics Corporation LBA7130 16.4.1 Easy FIFO In Easy FIFO mode, max FIFO length is 64 bytes. FIFO length is equal to ( FEP [11:0] +1 ) where FEP [11:0] is max 0x003F. User just needs to control FEP [11:0] (03h) and disable PSA and FPM as shown below. TX-FIFO
(byte) 1 8 16 32 64 RX-FIFO
(byte) 1 8 16 32 64 FEP[11:0]
(03h) 0x00 0x07 0x0F 0x1F 0x3F PSA[5:0]
(04h) 0 0 0 0 0 FPM[1:0]
(04h) 0 0 0 0 0 Table 16.2 Control registers of Easy FIFO Initialize all control registers (refer A7130 reference code). Set FEP [11:0] = 0x003F for 64-bytes FIFO. Send Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Transmitting 1. 2. 3. 4. MCU writes 64-bytes data to TX FIFO. 5. 6. D Send TX Strobe Command and monitor WTR signal. one. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) can be used to trigger MCU for RX FIFO reading. 2. 3. MCU monitors WTR signal and then read 64-bytes from RX FIFO. 4. D Send Strobe command RX FIFO read pointer reset. one. Figure 16.5 Easy FIFO Oct., 2012, Version 0.6 (PRELIMINARY) 64 AMICCOM Electronics Corporation LBA7130 16.4.2 Segment FIFO In Segment FIFO, TX FIFO length is equal to (FEP [11:0] PSA [5:0]1). FPM [1:0] should be zero. This function is very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [11:0]) and issues TX strobe command. Table 16.4 explains the details if TX FIFO is arranged into 8 segments, each TX segment and RX FIFO length are 8 bytes. Segment 1 2 3 4 5 6 7 8 PSA PSA1 PSA2 PSA3 PSA4 PSA5 PSA6 PSA7 PSA8 FEP FEP1 FEP2 FEP3 FEP4 FEP5 FEP6 FEP7 FEP8 TX FIFO Length 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes 8 bytes PSA[5:0]
0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 FEP[11:0]
0x07 0x0F 0x17 0x1F 0x27 0x2F 0x37 0x3F FPM[1:0]
0 0 0 0 0 0 0 0 RX FIFO Length 8 bytes PSA[5:0]
0 FEP[11:0]
0x0007 FPM[1:0]
0 Table 16.3 Segment FIFO is arranged into 8 segments Initialize all control registers (refer A7130 reference code). Issue Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Transmitting 1. 2. 3. MCU writes fixed code into corresponding segment FIFO once and for all. 4. To consign Segment 1, set PSA = 0x00 and FEP= 0x0007 To consign Segment 2, set PSA = 0x08 and FEP= 0x000F To consign Segment 3, set PSA = 0x10 and FEP= 0x0017 To consign Segment 4, set PSA = 0x18 and FEP= 0x001F To consign Segment 5, set PSA = 0x20 and FEP= 0x0027 To consign Segment 6, set PSA = 0x28 and FEP= 0x002F To consign Segment 7, set PSA = 0x30 and FEP= 0x0037 To consign Segment 8, set PSA = 0x38 and FEP= 0x003F Issue TX Strobe Command and monitor WTR signal. 5. 6. D one. Procedures of RX FIFO Reading 1. When RX FIFO is full, WTR (or FSYNC) is used to trigger MCU for RX FIFO reading. 2. 3. MCU monitors WTR signal and then read 8-bytes from RX FIFO. 4. D Issue Strobe command RX FIFO read pointer reset. one. Oct., 2012, Version 0.6 (PRELIMINARY) 65 AMICCOM Electronics Corporation LBA7130 Figure 16.6 Segment FIFO Mode Oct., 2012, Version 0.6 (PRELIMINARY) 66 AMICCOM Electronics Corporation LBA7130 16.4.3 FIFO Extension A7130 supports FIFO extension up to 4K bytes from the 64 bytes physical TX FIFO and RX FIFO. The FIFO extension length is configured by (FEP [11:0] +1 and PSA [5:0] =0). FPM [1:0] is used to set the FPF threshold which FPF is FIFO Pointer Flag to inform MCU the timing of reading RX FIFO and refilling TX FIFO. Please be notice, SPI speed is important to prevent error operation (over-write) in FIFO extension mode. We recommend the min. SPI speed shall be equal or greater than (A70 on-air data rate + 500Kbps).Please refer to A7130s reference code
(FIFO extension) for details. For example, if A7130 data rate = 4Mbps and FIFO extension = 256 bytes. FIFO Length
(byte) 256 TX FPF Threshold Delta = 04 Delta = 08 Delta = 12 Delta = 16 FIFO Length
(byte) 256 Max. SPI Data Rate 10 Mbps 10 Mbps 10 Mbps 8 Mbps RX FPF Threshold Delta = 60 Delta = 56 Delta = 52 Delta = 48 Max. SPI Data Rate 10 Mbps 10 Mbps 10 Mbps 8 Mbps Control Registers FEP[7:0]
FPM[1:0] PSA[5:0]
0xFF 00 01 10 11 0 0 0 0 Table 16.4 How to set FIFO extension when A7130 is at 4Mbps data rate Issue TX Strobe command. Initialize all control registers (refer A7130 reference code). Set FEP [11:0] = 0x0FF for 256-bytes FIFO extension. Set FPM [1:0] = 11 for FPF threshold. Set CKO Register = 0x12 Issue Strobe command TX FIFO write pointer reset. Procedures of TX FIFO Extension 1. 2. 3. 4. 5. 6. MCU writes 1st 64-bytes TX FIFO. 7. 8. MCU monitors FPF from A7130s CKO pin. 9. 10. Monitor FPF. 11. FPF triggers MCU to write 3rd 48-bytes TX FIFO. 12. Monitor FPF. 13. FPF triggers MCU to write 4th 48-bytes TX FIFO. 14. Monitor FPF. 15. FPF triggers MCU to write 5th 48-bytes TX FIFO. 16. D one. FPF triggers MCU to write 2nd 48-bytes TX FIFO. Oct., 2012, Version 0.6 (PRELIMINARY) 67 AMICCOM Electronics Corporation LBA7130 Figure 16.7 TX FIFO Extension Oct., 2012, Version 0.6 (PRELIMINARY) 68 AMICCOM Electronics Corporation Procedures of RX FIFO Reading LBA7130 FPF triggers MCU to read 1st 48-bytes RX FIFO. Initialize all control registers (refer A7130 reference code). Set FEP [11:0] = 0x0FF for 256-bytes FIFO extension. Set FPM [1:0] = [11b] for FPF threshold. Set CKO Register = 0x12 Issue Strobe command RX FIFO read pointer reset. Issue RX Strobe command. 1. 2. 3. 4. 5. 6. 7. MCU monitors FPF from A7130s CKO pin. 8. 9. Monitor FPF. 10. FPF triggers MCU to read 2nd 48-bytes RX FIFO. 11. Monitor FPF. 12. FPF triggers MCU to read 3rd 48-bytes RX FIFO. 13. Monitor FPF. 14. FPF triggers MCU to read 4th 48-bytes RX FIFO. 15. Monitor FPF. 16. FPF triggers MCU to read 5th 48-bytes RX FIFO. 17. Monitor WTR falling edge or WTR = low, read the rest 16-bytes RX FIFO 18. D one. Oct., 2012, Version 0.6 (PRELIMINARY) 69 AMICCOM Electronics Corporation LBA7130 Figure 16.8 RX FIFO Extension Mode Oct., 2012, Version 0.6 (PRELIMINARY) 70 AMICCOM Electronics Corporation LBA7130 17. ADC (Analog to Digital Converter) A7130 has built-in 8-bits ADC for RSSI measurement and internal thermal sensor by enabling ADCM. User can just use the recommended values of ADC from Table 17.1. Please noted that ADC clock can be selected by s etting FSARS (4MHz or 8MHz). The ADC converting time is 20 x ADC clock periods. XADS
(1Fh) 0 RSS
(1Ch) 1 ARSSI
(01h) 1 ADCM
(01h) 1 ERSSM
(1Ch) 1 FSARS
(1Fh) 0 CDM
(1Fh) 1 Standby Mode Thermal sensor RX Mode RSSI Table 17.1 Setting of RSSI measurement 17.1 RSSI Measurement A7130 supports 8-bits digital RSSI to detect RF signal strength. RSSI value is stored in ADC [7:0] (1Eh). Fig 17.1 shows a typical plot of RSSI reading as a function of input power. Be aware RSSI accuracy is about 6dBm. ADC value Curve (AGC on,25) e u l a V C D A e u l a V C D A 300 250 200 150 100 50 0 250 200 150 100 50 0 Average
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5 0 5 10 Input Power (dBm) ADC value Curve (AGC off,25) Average
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5 0 5 10 Input Power (dBm) Figure 17.1 Typical RSSI characteristic Oct., 2012, Version 0.6 (PRELIMINARY) 71 AMICCOM Electronics Corporation Auto RSSI measurement for TX Power of the coming packet:
LBA7130 Set wanted FRXLO. Set recommend values of Table 17.1. Enable ADCM = 1. Send RX Strobe command. 1. 2. 3. 4. 5. Once frame sync (FSYNC) is detected or exiting RX mode, user can read digital RSSI value from ADC [7:0] for TX power of the coming packet. Strobe CMD
(SCS,SCK,SDIO) RX-Strobe RX Mode MCU Read ADC[7:0]
RX Ready Time Received Packet Read 8-bits RSSI value RF-IN GIO1 Pin - WTR
(GPIO1S[3:0]=0000) GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001) T0 T1 T2 T3 T4 T0-T1: Settling Time T2-T3: Receiving Packet T3 : Exit RX mode automatically in FIFO mode T3-T4: MCU read RSSI value @ ADC [7:0]
Figure 17.2 RSSI Measurement of TX RSSI of the coming packet. Auto RSSI measurement for Background Power:
1. 2. 3. 4. 5. Set wanted FRXLO. Set recommend values of Table 17.1. Enable ADCM = 1. Send RX Strobe command. Stay in RX mode at least 140 us and then exiting RX mode. User can read digital RSSI value from ADC [7:0] for the background power. Strobe CMD
(SCS,SCK,SDIO) RX-Strobe RFI Pin GIO1 Pin - WTR
(GPIO1S[3:0]=0000) GIO2 Pin - FSYNC
(GPIO2S[3:0]=0001) Min. 140 us MCU Read ADC[7:0]
No Packet MCU reads 8-bits RSSI value that is refresh every 40 us T0 T1 T0-T1: MCU Delay Loop from PLL to RX mode for RSSI measurment T1 : Auto RSSI Measurment is done by 8-times average. MCU can read RSSI value from ADC [7:0]
Figure 17.3 Measurement of Background RSSI. Oct., 2012, Version 0.6 (PRELIMINARY) 72 AMICCOM Electronics Corporation LBA7130 18. Battery Detect A7130 has a built-in battery detector to check supply voltage (REGI pin). The detecting range is 2.0V ~ 2.7V into 8 levels. Battery detect Register (Address: 2Ch) Name Battery detect R/W Bit 7 W LVR
R Bit 6 RGV1 RGV1 Bit 5 RGV0 RGV0 Bit 4 QDS BDF Bit 3 BVT2 BVT2 Bit 2 BVT1 BVT1 Bit 1 BVT0 BVT0 Bit 0 BD_E BD_E BVT [2:0]: Battery voltage detect threshold.
[000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V.
[100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V. BD_E: Battery Detect Enable.
[0]: Disable. [1]: Enable. It will be clear after battery detection is triggered. BDF: Battery detection flag.
[0]: Battery voltage less than threshold. [1]: Battery voltage greater than threshold. Below is the procedure to detect low voltage input (ex. below 2.1V):
1. 2. 3. 4. Set A7130 in standby or PLL mode. Set BVT [2:0] = [001] and enable BD_E = 1. After 5 us, BD_E is auto clear. User can read BDF or output BDF to GIO1 pin or CKO pin. If REGI pin > 2.1V, BDF = 1 (battery high). Else, BDF = 0 (battery low). Oct., 2012, Version 0.6 (PRELIMINARY) 73 AMICCOM Electronics Corporation LBA7130 19. Auto-ack and auto-resend A7130 supports auto-resend and auto-ack scheme by enable EAK = 1 (auto-ack) and EAR = 1 (auto-resend). In application points of view, this feature is also ok to enable together with other feature options like FCB and/or EDRL (dynamic FIFO). 19.1 Basic FIFO plus auto-ack auto-resend Set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. Please refer to the below TX and ACK packet format of the sender and the receiver site respectively. 19.2 Advanced FIFO plus auto-ack and auto-resend In addition to set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. User can also enable an optional MAC header (FCB field) in the TX packet together with auto-ack and auto resend scheme. Please refer to the below TX and ACK packet format of the sender and the receiver site. Oct., 2012, Version 0.6 (PRELIMINARY) 74 AMICCOM Electronics Corporation LBA7130 Oct., 2012, Version 0.6 (PRELIMINARY) 75 AMICCOM Electronics Corporation LBA7130 19.3 WTR Behavior during auto-ack and auto-resend If auto-ack and auto-resend are enabled (EAR = EAK = 1), WTR represents a completed transmission period and CWTR is a debug signal which represents the cyclic TX period and cyclic RX period. Please refer to the below timing diagrams for details. The sender site (auto-resend) The receiver site (auto-ack) Remark: Refer to 3Bh for ARD[7:0] setting (auto resend delay). Refer to 3Fh for RND[7:0] setting (random seed for resend interval). Refer to 3Ah for EAK (enable auto-ack). Refer to 3Ah for EAR (enable auto-resend). Refer to 0Bh for VKM and VPM. Oct., 2012, Version 0.6 (PRELIMINARY) 76 AMICCOM Electronics Corporation LBA7130 19.6 Examples of auto-ack and auto-resend Once EAK and EAR are enabled, below case 1 ~ case 3 illustrate the most common cases as a timing reference (assume ARD
= 800 us) in two ways radio communications.
<Case1> Always success
<Case2> Success in second packet Oct., 2012, Version 0.6 (PRELIMINARY) 77 AMICCOM Electronics Corporation
<Case3> always resend failure LBA7130 Oct., 2012, Version 0.6 (PRELIMINARY) 78 AMICCOM Electronics Corporation LBA7130 20. RC Oscillator A7130 has an internal RC oscillator to supports WOR (Wake On RX) and TWOR (Timer Wake On RX) function. RCOSC_E
(09h) is used to enable RC oscillator. WORE (01h) is used to enable WOR function and TWORE (09h) is used to enable TWOR function. After done calibrations of RC oscillator, WOR and TWOR function can be operated from -40 to 85. Parameter Calibrated Freq. Sleep period RX period Operation temperature Min 3.8K 7.82 0.244
-40 Max 4.2K Unit Hz 8007.68 ms ms 85 Note
[( WOR_SL [9:0] ) +1] x 7.8 ms
[( WOR_AC [5:0] ) +1] x 244 us After calibration. 20.1 WOR Function When WOR is enabled (WORE = 1 and RCOSC_E =1), A7130 periodically wakes up f rom sleep and li sten (auto-enter RX mode) for incoming packets without MCU interaction. Therefore, A7130 will stay in sleep mode based on WOR_SL timer and RX mode based on WOR_AC timer unless a packet is received. The internal RC oscillator used for the WOR function varies with temperature and CMOS process deviation. In order to keep the frequency as accurate as possible, the RC oscillator shall be calibrated (CALWC=1) whenever possible. After done calibrations, MCU shall set WORE=1 and issue sleep strobe command to start WOR function. After a period (WOR_SL) in sleep mode, the device goes to RX mode to check coming packets. And then, A7130 is back to sleep mode for the next WOR cycle. To end up WOR function, MCU just needs to set WORE = 0. Beware, please turn on MSCRC (21h, CRC data filtering) when CRCS = 1
(20h, CRC select) in WOR function. Strobe CMD
(SCS,SCK,SDIO) sleep No Command Required Strobe cmd RF In Pin GIO1 -- WTR GIO1S[3:0]=0000 Sleep WOR_SL[9:0]
RX Sleep WOT_SL[9:0]
Start WOR
(sleep strobe) Coming packet RX End of WOR
(set WORE = 0) Oct., 2012, Version 0.6 (PRELIMINARY) 79 AMICCOM Electronics Corporation LBA7130 20.2 TWOR Function The RC oscillator inside A7130 can also be used to supports programmable TWOR (Timer Wake-On, TWORE=1) function which enables A7130 to output a periodic square wave from GIO1 (or GIO2). The duty cycle of this square wave is set by WOR_AC (08h) or WOR_SL (08h and 07h) regarding to TSEL (09h). User can use this square wave to wake up MCU or other purposes. 21. AES128 Security Packet A7130 has a built-in AES128 co-processor to generate a security packet by a general purpose MCU. In addition to support 128-bits key length (AES128), A7130 also support a proprietary 32-bits key length called AES32. Software procedure to use AES128. Step1: Write 16-bytes AES128 key to KEYI [127:0] (36h) Step2: Set AESS=1 (3Eh) to select standard AES128 Step3. Set AKFS=0 (3Eh) to disable attaching AES128 KEYI [127:0] into the TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7130 will execute AES128 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7130 will execute AES128 decryption and store plain text back to RX FIFO. Remark 1. The unit size of AES128 encryption packet is 16-bytes. 2. 3. In TX side, if plain text is not dividable by 16-bytes, i.e. 5-bytes only, the TX packet is complement to be 16-bytes. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. Software procedure to use AES32. Step1: Write 4-bytes AES128 key to KEYI [31:0] (36h) Step2: Set AESS=0 (3Eh) to select proprietary AES32. Step3. Set AKFS=0 (3Eh) to not attach AES128 KEYI [31:0] to the wanted TX packet. Step4: Set EDCRS=1 (3Eh) to enable AES co-processor. Step5: Write plain text to TX FIFO Step6: Issue TX strobe command and then A7130 will execute AES32 encryption and deliver the cipher text without latency. Step7: In RX side with the same configurations, A7130 will execute AES32 decryption and store plain text back to RX FIFO. Remark 1. 2. 3. The unit size of AES32 encryption packet is 4-bytes. In TX side, if plain text is not dividable by 4-bytes, i.e. 5-bytes only, the TX packet is complement to 8-bytes. In RX side, the coming cipher text will be decrypted and restore 5-bytes plain text back to RX FIFO. Oct., 2012, Version 0.6 (PRELIMINARY) 80 AMICCOM Electronics Corporation LBA7130 22. Application circuit 22.1 MD70-A01 AMICCOMs ref. design module, MD7130-A01, max 5 dBm output power, application circuit example. C4 2.2uF C3 4.7uF A _ D D V I N V O K C 2 O G I 1 O G I 0 2 9 1 8 1 7 1 6 1 C1 470pF C2 100pF TP1 ANTENNA ANT L2 2.7nH C15 1.8pF VDD_A U1 GND SDIO VDD_D SCK SCS 15 14 13 12 11 I G E R O K C 2 O G I 1 O G I A _ D D V BP_RSSI BP_BG RFI RFO RFC A7130PKG O C V _ D D V L L P _ D D V P C 6 7 8 9 0 1 I X O X A7130 1 2 3 4 5 C5 100pF C6 0.1uF VIN GND CKO GIO2 GIO1 SDIO SCK SCS GND GND CON/10P 2.0 1 2 3 4 5 6 7 8 9 10 J1 1 2 J2 CON/2P 2.0 1 2 J3 CON/2P 2.0 C7 2.2uF SDIO SCK SCS C8 2.2nF A _ D D V R1 NC C9 NC Y1 NC C12 NC C13 NC C10 0.1uF C11 100pF Y2 NC 4 GND 3 GND 1 Y3 16MHz XTAL_3.2*2.5 2 4 GND 3 Remark 1. 2. 3. 4. RF Matching to 50. RX and TX signal are combined internally to RFI pin only so that RFSP bit = 0 (DASP0 register = 0x34). Recommend 16MHz crystal with 18 pF Cload. Recommend to let C12 and C13 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]). 1 GND 2 Oct., 2012, Version 0.6 (PRELIMINARY) 81 AMICCOM Electronics Corporation LBA7130 22.2 MD70-F07 AMICCOMs ref. design module, MD7130-F07, typical 17 dBm output power together with a range extendor A7700. D C B A 1 2 LNA_OUT PA_IN R1 47 C16 1pF C10 1pF TP1 TEST POINT C11 NC C6 1.5pF C19 1.5pF L7 2.4nH L8 2.4nH C25 1pF C33 TRX 8.2pF C42 NC VDD_PA 1 2 3 4 W S X R W S X T C12 NC 3 3 I G E R C15 NC BG R6 6.8K 6 1 5 1 4 1 3 1 M G H GND W S X R W S X T G B ANT NC VDD_PA D N G C N A B _ D D V A _ D D V 5 6 7 8 U2 12 11 10 9 BGS RFO GND RFI RFO RFI A7700 C36 NC L1 4.7nH REGI33 C8 NC C7 8.2pF C13 0.1uF REGI33 C57 100pF 3 C5 4.7uF C3 1nF C2 100pF 1 2 3 4 5 L10 3.3nH L9 3.3nH C29 100pF VDD_A 4 C20 2.2uF SDIO SCK SCS C18 2.2uF O K C 2 O I G 1 O I G A _ D D V 3 3 I G E R 0 2 9 1 8 1 7 1 6 1 I G E R O K C 2 O I G 1 O I G A _ D D V BP_RSSI BP_BG RFI RFO RFC A7130PKG O C V _ D D V L L P _ D D V P C I X O X U1 GND SDIO VDD_D SCK SCS 15 14 13 12 11 A70 6 7 8 9 0 1 R10 NC VDD_A C31 2.2nF C30 0.1uF Y1 1 2 16MHz Y2 16MHz 2 1 C14 0.1uF C32 NC L3 0R L2 3nH C38 NC LNA_OUT CKO R11 NC R12 0R PA_IN C9 1.2pF C1 2.2pF REGI33 CKO or GND GIO2 GIO1 SDIO SCK SCS TX SW RX SW GND J2 1 2 3 4 5 6 7 8 9 10 3 2 Y3 GND 4 1 GND CRYSTAL/5*3.2 C34 NC C37 NC Title Size A4 Date:
File:
CON/10P 2.0 MD70-F07-05(2L) Number 2012.01.12 12-Jan-2012 Sheet of C:\Documents and Settings\ac0086\\MD7130~2.DDB Drawn By:
4 Revision D C B A 1 2 3 Remark 1. RF matching to 50. 2. RX and TX signal are separated to RFI pin and RFO pin so that RFSP bit = 1 (DASP0 register = 0x74). 3. Recommend 16MHz crystal with 18 pF Cload. 4. Recommend to let C34 and C37 NC because of enabling on-chip Xtal Capacitors by (INTXC = 1 and CSXTAL = [10100]). Oct., 2012, Version 0.6 (PRELIMINARY) 82 AMICCOM Electronics Corporation LBA7130 23. Abbreviations ADC AIF FC AGC BER BW CD CHSP CRC DC FEC FIFO FSK ID IF ISM LO MCU PFD PLL POR RX RXLO RSSI SPI SYCK TX TXRF VCO XOSC XREF XTAL Analog to Digital Converter Auto IF Frequency Compensation Automatic Gain Control Bit Error Rate Bandwidth Carrier Detect Channel Step Cyclic Redundancy Check Direct Current Forward Error Correction First in First out Frequency Shift Keying Identifier Intermediate Frequency Industrial, Scientific and Medical Local Oscillator Micro Controller Unit Phase Frequency Detector for PLL Phase Lock Loop Power on Reset Receiver Receiver Local Oscillator Received Signal Strength Indicator Serial to Parallel Interface System Clock for digital circuit Transmitter Transmitter Radio Frequency Voltage Controlled Oscillator Crystal Oscillator Crystal Reference frequency Crystal 24. Ordering Information Part No. Package Units Per Reel / Tray A71C30AQFI/Q QFN20L, Pb Free, Tape & Reel, -4085 A71C30AQFI A71C30AH QFN20L, Pb Free, Tray, -4085 Die form, -4085 3K 490EA 100EA Oct., 2012, Version 0.6 (PRELIMINARY) 83 AMICCOM Electronics Corporation LBA7130 25. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions 16 20 E C 5 2
. 0 1 A TOP VIEW D BOTTOM VIEW 0.25 C D2 15 11 11 15 10 6 2 E e 10 6 L 16 20 1 5 5 e 1 b 0.10 M C A B
0.10 C A 3 A y C Seating Plane C Symbol Dimensions in inches Max 0.032 0.002 0.012 0.161 0.083 0.161 0.083 Min 0.028 0.000 0.007 0.154 0.075 0.154 0.075 0.012 Nom 0.030 0.001 0.008 REF 0.010 0.158 0.079 0.158 0.079 0.020 BSC 0.016 0.003 A A1 A3 b D D2 E E2 e L y Dimensions in mm Min 0.70 0.00 Nom 0.75 0.02 Max 0.80 0.05 0.203 REF 0.18 3.90 1.90 3.90 1.90 0.25 4.00 2.00 4.00 2.00 0.30 4.10 2.10 4.10 2.10 0.50 0.020 0.30 0.50 BSC 0.40 0.08 Oct., 2012, Version 0.6 (PRELIMINARY) 84 AMICCOM Electronics Corporation LBA7130 26. Top Marking Information A71C30AQFI Part No. : A71C30AQFI Pin Count : 20 Package Type Dimension : 4*4 mm Mark Method Character Type : Arial
: Laser Mark
: QFN J 70 C1 N N N N NN N N N Y Y W XW A K F L C2 G C3 D B I v CHARACTER SIZE : (Unit in mm) A : 0.55 B : 0.36 C1 : 0.25 C2 : 0.3 C3 : 0.2 D : 0.03 F=G I=J K=L 0.8 0 0.6 8 Y Y W W X N N N N N N N N N
:DATECODE
: PKG HOUSE ID
: LOT NO.
(max. 9 characters) 70 1.6 0 0.6 5 Oct., 2012, Version 0.6 (PRELIMINARY) 85 AMICCOM Electronics Corporation LBA7130 27. Reflow Profile Actual Measurement Graph Oct., 2012, Version 0.6 (PRELIMINARY) 86 AMICCOM Electronics Corporation LBA7130 28. Tape Reel Information Cover / Carrier Tape Dimension TYPE 20 QFN 4*4 24 QFN 4*4 32 QFN 5*5 QFN3*3 / DFN-10 20 SSOP 24 SSOP P 8 8 8 4 12 12 A0 4.35 4.4 5.25 3.2 8.2 8.2 B0 4.35 4.4 5.25 3.2 7.5 8.8 P0 4.0 4.0 4.0 4.0 4.0 4.0 P1 2.0 2.0 2.0 2.0 2.0 2.0 D0 1.5 1.5 1.5 1.5 1.5 1.5 D1 1.5 1.5 1.5
1.5 1.5 E 1.75 1.75 1.75 1.75 1.75 1.75 Unit: mm W 12 12 12 8 16 16 F 5.5 5.5 5.5 1.9 7.5 7.5 TYPE 20 QFN (4X4) 24 QFN (4X4) 32 QFN (5X5) QFN3*3 / DFN-10 20 SSOP 24 SSOP K0 1.1 1.4 1.1 0.75 2.5 2.1 t 0.3 0.3 0.3 0.25 0.3 0.3 COVER TAPE WIDTH 9.2 9.2 9.2 8 13.3 13.3 Oct., 2012, Version 0.6 (PRELIMINARY) 87 AMICCOM Electronics Corporation LBA7130 REEL DIMENSIONS UNIT IN mm TYPE G N T M D K L R 20 QFN(4X4) 24 QFN(4X4) 32 QFN(5X5) DFN-10 12.8+0.6/-0.4 48 QFN(7X7) 16.8+0.6/-0.4 28 SSOP (150mil) 20.4+0.6/-0.4 20 SSOP 24 SSOP 16.4+2.0/-0.0 100 REF 100 REF 100 REF 100 REF 18.2(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 330 0.00/-1.0 20.2 22.2(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 25(MAX) 1.750.25 13.0+0.5/-0.2 2.00.5 22.4(MAX) 1.750.25 13.0+0.2/-0.2 1.90.4 330 0.00/-1.0 20.2 330 0.00/-1.0 20.2 330 0.00/-1.0 20.2 T L R D N K M G Oct., 2012, Version 0.6 (PRELIMINARY) 88 AMICCOM Electronics Corporation LBA7130 29. Product Status Data Sheet Identification Objective Product Status Planned or Under Development Preliminary Engineering Samples and First Production No Identification Noted Full Production Obsolete Not In Production Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains the final specifications. AMICCOM reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications on a product that has been discontinued by AMICCOM. The data sheet is printed for reference information only. RF ICs AMICCOM Headquarter A3, 1F, No.1, Li-Hsin Rd. 1, Hsinchu Science Park, Taiwan 30078 Tel: 886-3-5785818 Shenzhen Office Rm., 2003, DongFeng Building, No. 2010, Shennan Zhonglu Rd., Futian Dist., Shenzhen, China Post code: 518031 Web Site http://www.amiccom.com.tw Oct., 2012, Version 0.6 (PRELIMINARY) 89 AMICCOM Electronics Corporation Modular Approal:
The LBA 7130RF module is designed to comply with the FCC statement. FCC ID is OIE51402TR. The host system using LBA 7130RF, should have label indicated FCC ID: OIE51402TR. This radio module must not installed to co-locate and operating Simultaneously with other radios in host system, additional testing and equipment authorization may be required to operating simultaneously with other radio FCC Statement 1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1)This device may not cause harmful interference, and
(2)This device must accept any interference received, including interference that may cause undesired operation. 2. Changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment.
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2013-03-21 | 2408 ~ 2468 | DXX - Part 15 Low Power Communication Device Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2013-03-21
|
||||
1 | Applicant's complete, legal business name |
LB Technology Co., Ltd.
|
||||
1 | FCC Registration Number (FRN) |
0021869573
|
||||
1 | Physical Address |
No. 5 of Xiaoyang Rd, First Industrial Park
|
||||
1 |
Guangdong
|
|||||
1 |
China
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
t******@siemic.com
|
||||
1 | TCB Scope |
A2: Low Power Transmitters (except Spread Spectrum) and radar detectors operating above 1 GHz
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
OIE
|
||||
1 | Equipment Product Code |
51402TR
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
Y**** Y******
|
||||
1 | Title |
Manager
|
||||
1 | Telephone Number |
00867********
|
||||
1 | Fax Number |
00867********
|
||||
1 |
y******@lbtech.com.cn
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DXX - Part 15 Low Power Communication Device Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | LBA 7130RF | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Limited Single Modular Approval | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Grant Comments | Limited Single Modular Approval. | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
Accurate Technology Co., Ltd.
|
||||
1 | Name |
S**** L****
|
||||
1 | Telephone Number |
86-75********
|
||||
1 | Fax Number |
86-75********
|
||||
1 |
s******@atc-lab.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2408.00000000 | 2468.00000000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC