FCC ID: 2ADHKWBZ351 Wireless MCU module with BLE 5.2 compliant and Zigbee 3.0 Radio

 

MICROCHIP CONFIDENTIAL PIC32CX-BZ3 and WBZ35x Family High-Performance Ultra-Low Power 2.4 GHz Wireless MCUs with 32-bit ARM Cortex-M4F, Secure Boot, Touch and 2 Msps 12-bit ADC Introduction The PIC32CX-BZ3 family of SoC's is a general purpose, low-cost, 32-bit Microcontroller (MCU) with Cortex M4F ARM processor, Bluetooth low energy 5.2 or Zigbee wireless connectivity, ultra-low power 2.4 GHz transceiver, hardware-based security accelerator, Touch and Secure boot. The WBZ35x modules are targeted to be fully RF certified wireless modules built around PIC32CX-BZ3. The WBZ35x modules are available with a PCB antenna. The PIC32CX-BZ3 family supports a rich set of standard peripherals, such as SERCOM (SPI, I2C, UART) and QSPI, and enables a low-cost system for an IoT solution, automotive connectivity applications with reliable information exchange. The Secure Boot ROM can perform an integrity check or authenticate the firmware stored in the application Flash region prior to the firmware execution. This verification mechanism is a key element to ensure the system root of trust for the deployment and execution of the Secure firmware. PIC32CX-BZ3 SoC Family Features Operating Conditions 1.9V to 3.6V, -40C to +125C, DC to 64 MHz AEC Q100 Grade 1 qualified with reduced parameters 1.9V to 3.6V, -40C to +105C, DC to 64 MHz AEC Q100 Grade 2 qualified Core: 64 MHz ARM Cortex-M4F 3.35 Coremark/MHz 4 KB Combined Instruction Cache and Data Cache 8-Zone Memory Protection Unit (MPU) Thumb-2 Instruction Set Digital Signal Processing ASE Rev 2 Nested Vector Interrupt Controller (NVIC) Embedded Trace Module (ETM) with Instruction Trace Stream Core Sight Embedded Trace Buffer (ETB) Trace Port Interface Unit (TPIU) IEEE 754-Compliant Floating Point Unit (FPU) Memories 64-KB ROM for Secure Boot Support for asymmetric secure boot 3072 Bits of eFuse Secure Boot key storage Debug Lock 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1 Confidential PIC32CX-BZ3 and WBZ35x Family 512-KB On-Chip Self-programmable Flash with:

Error Correction Code (ECC) Prefetch module to speed up Flash accesses 20k cycles endurance (100k cycles with erase retry option) and 20 years of data retention support 32-KB Boot Flash Memory (8 Pages) User boot code configuration Flexible device configuration 96-KB Multi-port Programmable QoS SRAM Main Memory 32-KB of Error Correction Code (ECC) RAM option 32-KB of RAM space for Coresight ETB debug usage, when enabled Up to 32-KB of SRAM can be retained in Backup mode Up to 4-KB of Tightly Coupled Memory (TCM) System Internal and External Clock Options Power-On Reset (POR) and Brown-Out Detect (BOD) External Interrupt Controller (EIC) Up to four external interrupts One non-maskable interrupt Extensive Debug and Trace Capabilities 2-pin Serial Wire Debug (SWD) programming and debugging interface ETM trace interface pins for serial wire trace Supported Connectivity Standards Complies with:

Bluetooth for Bluetooth Low Energy 5.2 IEEE 802.15.4, Zigbee 3.0 Power Supply Integrated PMU with:

Buck (DC-DC/switching) mode; supports high-power (PWM) and low-power (PSK) mode MLDO (linear) mode Integrated On-Chip 1.5V Low Dropout (LDO) Regulator for eFuse Integrated On-Chip 1.2V Core Low Dropout Regulator (CLDO) POR and BOR on 3.3V and 1.2V Rails Run, Idle, Standby Sleep, Deep Sleep and Extreme Deep Sleep Modes Sleep Walking Peripherals Embedded Buck/LDO Regulator Supporting On-The-Fly (OTF) Selection 2.4 GHz RF Transceiver Integrated 2.4 GHz Ultra Low-Power RF Transceiver Shared between Bluetooth and IEEE 802.15.4 Modems and Link (MAC) Controllers Integrated TRX Switch and Balun with One single-ended RFIO for TX/RX High Efficiency Switching Power Amplifier (PA) Programmable Transmit Output Power Ranges from -25 dBm to +10 dBm with 1 dB Step Size Supported Data Rates:

Bluetooth 5.2 2 Mbps, 1 Mbps, 500 kbps and 125 kbps IEEE 802.15.4 250 kbps Proprietary 2.4 GHz 2 Mbps, 1 Mbps and 500 kbps Hardware Radio Arbiter with Programmable Quality of Service (QoS):

Resolution Up to per packet level Time-division coexistence between Bluetooth and 802.15.4 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 2 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Based on shared transceiver and antenna Maintains connections of 802.15.4 and Bluetooth simultaneously Bluetooth Bluetooth Low Energy 5.2 Certified Typical Receiver Power Sensitivity:

-95 dBm for Bluetooth Low Energy 2 Mbps

-98 dBm for Bluetooth Low Energy 1 Mbps

-108 dBm for Bluetooth Low Energy 125 Kbps Bluetooth Low Energy Supported Features:

Low energy power control 2M uncoded PHY Long range coded PHY Channel selection algorithm #2 Advertising extensions, offloads CPU with hardware based scheduler High duty cycle non-connectible advertising Data length extensions Secure connections Privacy upgrades Robust to interference with wideband RSSI detector ECDH P256 Hardware Engine for Link Key Generation, when Bluetooth Pairing AES128 Hardware Module for Real-Time Bluetooth Payload Data Encryption Bluetooth Qualification Test Facility (BQTF) Certification Supports SIG Defined/Custom Bluetooth Low Energy Profiles and Services IEEE 802.15.4 PLCP Service Data Unit (PSDU) Data Rate: 250 Kbps Proprietary data rates: 500 Kbps, 1 Mbps and 2 Mbps Programmable RX Mode

-103 dBm RX sensitivity for 250 Kbps in Continuous mode

-98 dBm RX sensitivity in RPC mode RPC mode provides lower power consumption in RX mode to support California Green Energy Specification at the system level Hardware Assisted MAC Auto acknowledge Auto retry Channel access back-off Automated FCS check Automatic Address filtering Zigbee 3.0 Specification Compliant SFD Detection; Spreading; De-spreading; Framing; CRC-16 Computation Independent TX/RX Buffers for Improved CPU Offloading 128-byte TX and 128-byte RX frame buffer High Performance Peripherals 16-Channel Direct Memory Access Controller (DMAC) Built-in CRC with memory CRC generation and monitors hardware support One Quad I/O Serial Peripheral Interface (QSPI) Execute-In-Place (XIP) support Dedicated AHB memory zone System Peripherals 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 3 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 32-Channel Event System All channels can be connected to any event generator All channels provide a pure asynchronous path Twelve channels support synchronous and re-synchronous Two Serial Communication Interfaces (SERCOM), Each Configurable to Operate as:

Universal Synchronous Asynchronous Receiver Transmitter (USART) with full duplex and single-wire half duplex configuration ISO7816 I2C up to 1 MHz LIN Host/Client RS485 SPI inter-byte space One SERCOM Configured as I2C Only Interface Eight 16-bit Timers/Counters (TC), Each Configurable as:

16-bit TC with two compare/capture channels 8-bit TC with two compare/capture channels 32-bit TC with two compare/capture channels by paring two TCs Two 24-bit Timer/Counters for Control (TCC) with Extended Functions:

Up to six compare channels with optional complementary output Generation of synchronized Pulse Width Modulation (PWM) pattern across port pins Deterministic fault protection, fast decay and configurable dead-time between complementary output Dithering to increase resolution up to 5 bits and reduces quantization error One 16-bit Timer/Counters for Control (TCC) with Extended Functions:

Up to two compare channels with optional complementary output 32-bit Real Time Counter (RTCC) with Clock/Calendar Function Up to four wake-up pins with tamper detection and debouncing filter Watchdog Timer (WDT) with Window Mode Deadman Timer (DMT) Frequency Meter (FREQM) Configurable Custom Logic (CCL) with two Look-up Table (LUT) One 7-bit General Purpose Digital-to-Analog Converter (DAC) provides Voltage Reference to Analog Comparator One 12-bit, 2 Msps Analog-to-Digital Converter (ADC) SAR Core with up to Eight Channels:

Differential and single-ended input Automatic offset and gain error compensation Up to Two Analog Comparator (AC) with Window Compare Function (One AC is shared with MVREF FSM

(AC_CMP1) and One Dedicated (AC_CMP0)) Up to Eight CVD Channels for Touch Button Support (Using Shared ADC SAR Core) One Temperature Sensor (Die Temperature) Built Into Wireless Subsystem Cryptography High Performance Cryptographic Accelerators for AES, Secure Hash Algorithm (SHA), RSA and ECC NIST 800-90B Compliant TRNG Integrated Scatter Gather DMA Oscillators 16 MHz, 20 PPM Crystal/Resonator Oscillator or External Clock (POSC) for 2.4 GHz RF Transceiver Shared System PLL with RF Subsystem 32.768 kHz Ultra-low Power Internal Oscillator (LPRC) Higher Accuracy 32.768 kHz, 250 ppm Clock Options 32 kHz clock derived from POSC 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 4 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 32.768 kHz crystal/resonator oscillator (SOSC) External 32.768 kHz clock source 8 MHz Internal RC Oscillator (FRC) I/O Flexible Peripheral Pin Select (PPS) Support High-current Sink/Source on Most I/O Pins Configurable Open-Drain Output on Digital I/O Pins 3.3V, 5V Tolerant Input Pins (Digital Pins Only) Up to 27 Programmable I/O Pins Package PIC32CX5109BZ31048 48-pin QFN Size 6 mm x 6 mm x1 mm PIC32CX5109BZ31032 32-pin QFN Size 5 mm x 5 mm x 1 mm WBZ35x Module Features The following section lists the WBZ35x module related features, which complements SoC features. WBZ35x Module Variants WBZ351 based on (PIC32CX5109BZ31048 SoC) WBZ351PC (Trust&GO) WBZ351PE (without Trust&GO) WBZ350 based on (PIC32CX5109BZ31032 SoC) WBZ350PC (Trust&GO) WBZ350PE (without Trust&GO) Antenna On-board PCB Antenna Security Integrated Trust&GO Clock Management Integrated 16 MHz POSC Advanced Analog 12-bit ADC Up to eight analog channels (WBZ351) Up to four analog channels (WBZ350) CVD Touch Support Using Shared ADC 7-bit General Purpose DAC Input/Output Up to 27 GPIO Pins (WBZ351) Up to 14 GPIO Pins (WBZ350) Package and Operating Conditions WBZ351 Package:

39-pin SMD package with Shield CAN 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 5 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Size 15.5 mm x 20.7 mm x2.8 mm WBZ350 Package:

30-pin SMD package with Shield CAN Size 13.4 mm x 18.7 mm x2.8 mm Operating Conditions:

1.9V to 3.6V for variants without Trust&GO 2V to 3.6V for variants with Trust&GO Operating temperature: -40C to +85C Certifications (Planned) FCC, ISED and CE Radio Regulations Bluetooth SIG RoHS and REACH Compliant 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 6 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Table of Contents Introduction.....................................................................................................................................................1 PIC32CX-BZ3 SoC Family Features..............................................................................................................1 WBZ35x Module Features..............................................................................................................................5 1. Configuration Summary........................................................................................................................ 16 2. PIC32CX-BZ3 and SoC Description..................................................................................................... 17 2.1. PIC32CX-BZ3 SoC Block Diagram............................................................................................ 17 2.2. Pinout Diagram...........................................................................................................................17 3. WBZ35 Module Description.................................................................................................................. 19 3.1. Pinout Diagram...........................................................................................................................19 3.2. Basic Connection Requirement..................................................................................................20 3.3. WBZ35 Module Placement Guidelines.......................................................................................24 3.4. WBZ35 Module Routing Guidelines........................................................................................... 25 3.5. WBZ35 Module RF Considerations............................................................................................25 3.6. WBZ35 Module Antenna Considerations................................................................................... 26 3.7. WBZ35 Module Reflow Profile Information................................................................................ 27 3.8. WBZ35 Module Assembly Considerations................................................................................. 28 4. Pinout and Signal Descriptions List.......................................................................................................29 5. I/O Ports and Peripheral Pin Select (PPS)............................................................................................32 5.1. Overview.................................................................................................................................... 32 5.2. Features..................................................................................................................................... 32 5.3. Block Diagram............................................................................................................................ 32 5.4. Parallel I/O (PIO) Ports...............................................................................................................33 5.5. Peripheral Pin Select (PPS)....................................................................................................... 36 5.6. Peripheral Multiplexing............................................................................................................... 50 5.7. Function Priority for Device Pins................................................................................................ 51 5.8. Operation in Power Saving Modes.............................................................................................57 5.9. Results of Various Resets.......................................................................................................... 57 5.10. Port Register Summary.............................................................................................................. 58 5.11. Register Description................................................................................................................... 61 5.12. Peripheral Pin Select (PPS) Input Mapping Register Summary.................................................90 5.13. Peripheral Pin Select (PPS) Output Mapping Register Summary..............................................97 5.14. Register Description................................................................................................................. 103 6. Power Subsystem............................................................................................................................... 106 6.1. Block Diagram.......................................................................................................................... 106 6.2. VDD Voltage Domain Overview .............................................................................................. 107 6.3. VDD-AON Power Domain Overview ....................................................................................... 108 6.4. VDDBKUPcore Power Domain................................................................................................ 108 6.5. PMU Controller.........................................................................................................................108 6.6. Voltage Regulators................................................................................................................... 108 6.7. Power Supply Modes............................................................................................................... 108 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 7 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 6.8. Typical Power Supply Connection for SoC...............................................................................109 6.9. Typical Power Supply Connection for WBZ35x Module........................................................... 110 6.10. Power-Up Sequence................................................................................................................ 110 7. Product Memory Mapping Overview................................................................................................... 112 7.1. Embedded Memories............................................................................................................... 113 7.2. Physical Memory Map.............................................................................................................. 113 7.3. Boot ROM.................................................................................................................................113 7.4. Flash Memory Parameters....................................................................................................... 113 7.5. eFuse Memory..........................................................................................................................113 7.6. SRAM Memory Configuration...................................................................................................114 7.7. Boot Flash Device Configuration Word.....................................................................................116 7.8. Boot Flash Code Protection Register....................................................................................... 117 8. Processor and Architecture................................................................................................................. 118 8.1. Cortex M4F Processor..............................................................................................................118 8.2. Nested Vector Interrupt Controller (NVIC)................................................................................120 8.3. High-Speed Bus System.......................................................................................................... 125 9. Prefetch Cache (PCHE)...................................................................................................................... 128 9.1. Introduction...............................................................................................................................128 9.2. Features................................................................................................................................... 128 9.3. Overview.................................................................................................................................. 128 9.4. Product Dependencies............................................................................................................. 130 9.5. Prefetch Behavior.....................................................................................................................131 9.6. Configurations.......................................................................................................................... 131 9.7. Predictive Prefetch Behavior.................................................................................................... 131 9.8. Coherency Support.................................................................................................................. 132 9.9. Effects of Reset........................................................................................................................ 132 9.10. Error Conditions....................................................................................................................... 132 9.11. Register Summary....................................................................................................................134 9.12. Register Description................................................................................................................. 134 10. Cortex M Cache Controller (CMCC)................................................................................................... 141 10.1. Overview.................................................................................................................................. 141 10.2. Features................................................................................................................................... 141 10.3. Block Diagram.......................................................................................................................... 142 10.4. Signal Description.................................................................................................................... 143 10.5. Product Dependencies............................................................................................................. 143 10.6. Functional Description..............................................................................................................143 10.7. DEBUG Mode...........................................................................................................................146 10.8. DFT Mode................................................................................................................................ 146 10.9. RAM Properties........................................................................................................................ 147 10.10. Register Summary.................................................................................................................. 148 10.11. Register Description................................................................................................................ 149 11. Flash Controller (FC)...........................................................................................................................162 11.1. Overview.................................................................................................................................. 162 11.2. Features................................................................................................................................... 162 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 8 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 11.3. Functional Block Diagram........................................................................................................ 163 11.4. Product Dependencies............................................................................................................. 163 11.5. Flash Memory Addressing........................................................................................................164 11.6. Memory Configuration.............................................................................................................. 164 11.7. Boot Flash Memory (BFM) Partitions....................................................................................... 165 11.8. Program Flash Memory (PFM) Partitions.................................................................................166 11.9. Error Correcting Code (ECC) and Flash Programming............................................................166 11.10. Interrupts................................................................................................................................. 167 11.11. Error Detection ....................................................................................................................... 167 11.12. NVMKEY Register Unlocking Sequence.................................................................................168 11.13. Word Programming................................................................................................................. 169 11.14. Quad Word Programming....................................................................................................... 170 11.15. Row Programming...................................................................................................................171 11.16. Page Erase..............................................................................................................................172 11.17. Program Flash Memory (PFM) Erase..................................................................................... 174 11.18. Pre-Program............................................................................................................................175 11.19. Device Code Protection bit (CP)............................................................................................. 175 11.20. Effects of Various Resets........................................................................................................ 175 11.21. Register Summary...................................................................................................................176 11.22. Register Description................................................................................................................ 177 12. Device Service Unit (DSU)..................................................................................................................193 12.1. Overview.................................................................................................................................. 193 12.2. Features................................................................................................................................... 193 12.3. DSU Block Diagram................................................................................................................. 193 12.4. Signal Description.................................................................................................................... 193 12.5. Product Dependencies............................................................................................................. 194 12.6. Debug Operation...................................................................................................................... 195 12.7. Chip Erase................................................................................................................................196 12.8. Programming............................................................................................................................197 12.9. Intellectual Property Protection................................................................................................ 197 12.10. Device Identification................................................................................................................ 199 12.11. Functional Description.............................................................................................................201 12.12. Register Summary.................................................................................................................. 204 12.13. Register Description................................................................................................................206 13. Clock and Reset Unit (CRU)............................................................................................................... 235 13.1. Overview.................................................................................................................................. 235 13.2. Features................................................................................................................................... 235 13.3. Clock System........................................................................................................................... 236 13.4. Resets...................................................................................................................................... 243 13.5. Register Summary....................................................................................................................249 13.6. Register Description................................................................................................................. 252 14. Power Management Unit (PMU)......................................................................................................... 274 14.1. Overview.................................................................................................................................. 274 14.2. Features................................................................................................................................... 274 14.3. Functional Description..............................................................................................................274 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 9 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 14.4. Register Summary....................................................................................................................279 14.5. Register Description................................................................................................................. 279 14.6. Register Summary....................................................................................................................282 14.7. Register Description................................................................................................................. 282 15. Watchdog Timer (WDT).......................................................................................................................287 15.1. Introduction...............................................................................................................................287 15.2. Features................................................................................................................................... 287 15.3. Block Diagram.......................................................................................................................... 287 15.4. Watchdog Timer Operation...................................................................................................... 287 15.5. Interrupt and Reset Generation................................................................................................291 15.6. Operation in Debug and Power-Saving Modes........................................................................ 291 15.7. Effects of Various Resets......................................................................................................... 292 15.8. Register Summary....................................................................................................................293 15.9. Register Description................................................................................................................. 293 16. Deadman Timer (DMT)....................................................................................................................... 295 16.1. Overview.................................................................................................................................. 295 16.2. Features................................................................................................................................... 295 16.3. Block Diagram.......................................................................................................................... 295 16.4. DMT Operation.........................................................................................................................296 16.5. Register Summary....................................................................................................................299 16.6. Register Description................................................................................................................. 300 17. RAM Error Correction Code (RAMECC)............................................................................................. 309 17.1. Overview.................................................................................................................................. 309 17.2. Features................................................................................................................................... 309 17.3. Block Diagram.......................................................................................................................... 309 17.4. Signal Description.................................................................................................................... 309 17.5. Product Dependencies............................................................................................................. 310 17.6. Functional Description.............................................................................................................. 311 17.7. Register Summary....................................................................................................................312 17.8. Register Description................................................................................................................. 312 18. System Configuration and Register Locking (CFG)............................................................................ 319 18.1. Overview.................................................................................................................................. 319 18.2. Features................................................................................................................................... 319 18.3. Modes of Operation..................................................................................................................320 18.4. Locking and Unlocking the System Configuration Registers....................................................320 18.5. NMI Events...............................................................................................................................321 18.6. Register Locking.......................................................................................................................321 18.7. Effects of Various Resets......................................................................................................... 322 18.8. Register Summary....................................................................................................................323 18.9. Register Description................................................................................................................. 324 19. Peripheral Module Disable (PMD).......................................................................................................359 19.1. Overview.................................................................................................................................. 359 19.2. Enabling Peripherals................................................................................................................ 359 19.3. Controlling Configuration Changes.......................................................................................... 359 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 10 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 19.4. PMD Register Summary...........................................................................................................360 19.5. Register Description................................................................................................................. 360 20. Peripheral Access Controller (PAC).................................................................................................... 368 20.1. Overview.................................................................................................................................. 368 20.2. Features................................................................................................................................... 368 20.3. Block Diagram.......................................................................................................................... 368 20.4. Product Dependencies............................................................................................................. 368 20.5. Functional Description..............................................................................................................369 20.6. Register Summary....................................................................................................................372 20.7. Register Description................................................................................................................. 372 21. Real-Time Counter and Calendar (RTCC).......................................................................................... 392 21.1. Overview.................................................................................................................................. 392 21.2. Features................................................................................................................................... 392 21.3. Block Diagram.......................................................................................................................... 392 21.4. Signal Description.................................................................................................................... 393 21.5. Product Dependencies............................................................................................................. 394 21.6. Functional Description..............................................................................................................395 21.7. Register Summary - Mode 0 - 32-Bit Counter.......................................................................... 406 21.8. Register Description - Mode 0 - 32-Bit Counter....................................................................... 407 21.9. Register Summary - Mode 0 - 32-Bit Counter.......................................................................... 429 21.10. Register Description - Mode 1 - 16-Bit Counter...................................................................... 430 21.11. Register Summary - Mode 0 - 32-Bit Counter......................................................................... 452 21.12. Register Description - Mode 2 - Clock/Calendar.....................................................................453 22. Direct Memory Access Controller (DMAC)..........................................................................................475 22.1. Overview.................................................................................................................................. 475 22.2. Features................................................................................................................................... 475 22.3. Block Diagram.......................................................................................................................... 477 22.4. Signal Description.................................................................................................................... 477 22.5. Product Dependencies............................................................................................................. 477 22.6. Functional Description..............................................................................................................478 22.7. Register Summary....................................................................................................................501 22.8. Register Description................................................................................................................. 506 22.9. DMAC Register Summary (SRAM).......................................................................................... 534 22.10. Register Description - SRAM.................................................................................................. 534 23. External Interrupt Controller (EIC).......................................................................................................541 23.1. Overview.................................................................................................................................. 541 23.2. Features................................................................................................................................... 541 23.3. Block Diagram.......................................................................................................................... 541 23.4. Signal Description.................................................................................................................... 542 23.5. Product Dependencies............................................................................................................. 542 23.6. Functional Description..............................................................................................................543 23.7. Register Summary....................................................................................................................549 23.8. Register Description................................................................................................................. 550 24. Configurable Custom Logic (CCL)...................................................................................................... 564 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 11 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 24.1. Overview.................................................................................................................................. 564 24.2. Features................................................................................................................................... 564 24.3. Block Diagram.......................................................................................................................... 564 24.4. Signal Description.................................................................................................................... 565 24.5. Product Dependencies............................................................................................................. 566 24.6. Functional Description..............................................................................................................567 24.7. Register Summary....................................................................................................................576 24.8. Register Description................................................................................................................. 576 25. Frequency Meter (FREQM).................................................................................................................581 25.1. Overview.................................................................................................................................. 581 25.2. Features................................................................................................................................... 581 25.3. Block Diagram.......................................................................................................................... 581 25.4. Signal Description.................................................................................................................... 581 25.5. Product Dependencies............................................................................................................. 581 25.6. Functional Description..............................................................................................................583 25.7. Register Summary....................................................................................................................585 25.8. Register Description................................................................................................................. 585 26. Event System (EVSYS).......................................................................................................................595 26.1. Overview.................................................................................................................................. 595 26.2. Features................................................................................................................................... 595 26.3. Block Diagram.......................................................................................................................... 595 26.4. Signal Description.................................................................................................................... 595 26.5. Product Dependencies............................................................................................................. 596 26.6. Functional Description..............................................................................................................597 26.7. Register Summary....................................................................................................................603 26.8. Register Description................................................................................................................. 607 27. Serial Communication Interface (SERCOM).......................................................................................624 27.1. Overview.................................................................................................................................. 624 27.2. Features................................................................................................................................... 624 27.3. Block Diagram.......................................................................................................................... 624 27.4. Signal Description.................................................................................................................... 624 27.5. Product Dependencies............................................................................................................. 625 27.6. Functional Description..............................................................................................................626 28. SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART).............. 631 28.1. Overview.................................................................................................................................. 631 28.2. USART Features...................................................................................................................... 631 28.3. Block Diagram.......................................................................................................................... 632 28.4. Signal Description.................................................................................................................... 632 28.5. Product Dependencies............................................................................................................. 632 28.6. Functional Description..............................................................................................................634 28.7. Register Summary....................................................................................................................649 28.8. Register Description................................................................................................................. 650 29. SERCOM Serial Peripheral Interface (SERCOM SPI)........................................................................677 29.1. Overview.................................................................................................................................. 677 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 12 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 29.2. Features................................................................................................................................... 677 29.3. Block Diagram.......................................................................................................................... 677 29.4. Signal Description.................................................................................................................... 678 29.5. Product Dependencies............................................................................................................. 678 29.6. Functional Description..............................................................................................................679 29.7. Register Summary....................................................................................................................689 29.8. Register Description................................................................................................................. 689 30. SERCOM Inter-Integrated Circuit (SERCOM I2C).............................................................................. 708 30.1. Overview.................................................................................................................................. 708 30.2. Features................................................................................................................................... 708 30.3. Block Diagram.......................................................................................................................... 709 30.4. Signal Description.................................................................................................................... 709 30.5. Product Dependencies............................................................................................................. 709 30.6. Functional Description.............................................................................................................. 711 30.7. Register Summary....................................................................................................................727 30.8. Register Description - I2C Client.............................................................................................. 728 30.9. Register Summary....................................................................................................................746 30.10. Register Description I2C Host.............................................................................................. 747 31. Quad Serial Peripheral Interface (QSPI).............................................................................................767 31.1. Overview.................................................................................................................................. 767 31.2. Features................................................................................................................................... 767 31.3. Block Diagram.......................................................................................................................... 768 31.4. Signal Description.................................................................................................................... 768 31.5. Product Dependencies............................................................................................................. 768 31.6. Functional Description..............................................................................................................770 31.7. Register Summary....................................................................................................................787 31.8. Register Description................................................................................................................. 788 32. Analog-to-Digital Converter (ADC)......................................................................................................809 32.1. Overview.................................................................................................................................. 809 32.2. Features................................................................................................................................... 809 32.3. Block Diagram.......................................................................................................................... 809 32.4. ADC Operation......................................................................................................................... 810 32.5. ADC Module Configuration.......................................................................................................813 32.6. Additional ADC Functions........................................................................................................ 821 32.7. Interrupts.................................................................................................................................. 828 32.8. Power-Saving Modes of Operation.......................................................................................... 830 32.9. Effects of Reset........................................................................................................................ 831 32.10. Transfer Function.................................................................................................................... 831 32.11. ADC Sampling Requirements................................................................................................. 831 32.12. Register Summary.................................................................................................................. 833 32.13. Register Description................................................................................................................835 33. Capacitive Voltage Divider (CVD) Controller.......................................................................................873 33.1. Overview.................................................................................................................................. 873 33.2. Features................................................................................................................................... 873 33.3. Block Diagram.......................................................................................................................... 873 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 13 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 33.4. CVD Module Operation............................................................................................................ 873 33.5. Register Summary....................................................................................................................879 33.6. Register Description................................................................................................................. 881 34. Analog Comparators (AC)...................................................................................................................914 34.1. Overview.................................................................................................................................. 914 34.2. Features................................................................................................................................... 914 34.3. Block Diagram.......................................................................................................................... 915 34.4. Product Dependencies............................................................................................................. 915 34.5. Functional Description..............................................................................................................917 34.6. Register Summary....................................................................................................................925 34.7. Register Description................................................................................................................. 925 35. Timer/Counter (TC)............................................................................................................................. 943 35.1. Overview.................................................................................................................................. 943 35.2. Features................................................................................................................................... 943 35.3. Block Diagram.......................................................................................................................... 944 35.4. Signal Description.................................................................................................................... 944 35.5. Product Dependencies............................................................................................................. 945 35.6. Functional Description..............................................................................................................946 35.7. Register Summary....................................................................................................................961 35.8. Register Description - 8-bit Mode.............................................................................................961 35.9. Register Summary....................................................................................................................982 35.10. Register Description - 16-bit Mode..........................................................................................982 35.11. Register Summary.................................................................................................................1003 35.12. Register Description - 32-bit Mode........................................................................................1004 36. Timer/Counter for Control Applications (TCC).................................................................................. 1022 36.1. Overview................................................................................................................................ 1022 36.2. Features................................................................................................................................. 1022 36.3. Block Diagram........................................................................................................................ 1023 36.4. Signal Description.................................................................................................................. 1023 36.5. Product Dependencies........................................................................................................... 1024 36.6. Functional Description............................................................................................................1025 36.7. Register Summary..................................................................................................................1057 36.8. Register Description............................................................................................................... 1059 37. Zigbee Bluetooth Radio Subsystem (ZBT)........................................................................................1097 37.1. Overview................................................................................................................................ 1097 37.2. Features................................................................................................................................. 1097 37.3. Wireless Subsystem Top Level Diagram................................................................................1099 37.4. Analog RF Front-end..............................................................................................................1099 37.5. Digital Front-end.....................................................................................................................1099 37.6. Bluetooth Low-Energy Link Controller....................................................................................1099 37.7. Zigbee Subsystem..................................................................................................................1100 37.8. Radio Arbiter...........................................................................................................................1100 37.9. Register Banks....................................................................................................................... 1100 37.10. Coexistence Interface............................................................................................................1100 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 14 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family 38. Electrical Characteristics................................................................................................................... 1101 38.1. Absolute Maximum Electrical Characteristics.........................................................................1101 38.2. DC Electrical Characteristics.................................................................................................. 1101 38.3. Thermal Specifications........................................................................................................... 1102 38.4. Active Current Consumption DC Electrical Specifications......................................................1102 38.5. Idle Current Consumption DC Electrical Specifications..........................................................1104 38.6. Sleep Current Consumption DC Electrical Specifications...................................................... 1106 38.7. Deep Sleep Current Consumption DC Electrical Specifications.............................................1108 38.8. XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications................... 1109 38.9. External XTAL and Clock AC Electrical Specifications........................................................... 1110 38.10. XOSC32 AC Electrical Specifications....................................................................................1112 38.11. Low Power Internal 32 kHz RC Oscillator AC Electrical Specifications................................. 1114 38.12. FRC AC Electrical Specifications.......................................................................................... 1115 38.13. Frequency AC Electrical Specifications.................................................................................1115 38.14. QSPI Module Electrical Specifications.................................................................................. 1116 38.15. Power Supply DC Module Electrical Specifications...............................................................1117 38.16. I/O PIN AC/DC Electrical Specifications................................................................................1123 38.17. I2C Module Electrical Specifications......................................................................................1125 38.18. SPI Module Electrical Specifications..................................................................................... 1130 38.19. ADC Electrical Specifications................................................................................................ 1133 38.20. Bluetooth Low Energy RF Characteristics.............................................................................1136 38.21. Zigbee RF Characteristics.....................................................................................................1148 39. Packaging Information.......................................................................................................................1158 39.1. PIC32CX-BZ3 SoC Packaging Information............................................................................ 1158 39.2. WBZ35x Module Packaging Information................................................................................ 1165 40. Document Revision History............................................................................................................... 1170 Microchip Information............................................................................................................................... 1171 The Microchip Website...................................................................................................................... 1171 Product Change Notification Service.................................................................................................1171 Customer Support............................................................................................................................. 1171 Microchip Devices Code Protection Feature..................................................................................... 1171 Legal Notice.......................................................................................................................................1171 Trademarks....................................................................................................................................... 1172 Quality Management System............................................................................................................ 1173 Worldwide Sales and Service............................................................................................................1174 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 15 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configuration Summary 1. Table 1-1. PIC32CX-BZ3 and WBZ35x Family Features Configuration Summary Peripherals Analog Security Wireless Device

) B K

y r o m e M M O R t o o B

) B K

y r o m e M m a r g o r P

) B K

y r o m e M a t a D

) s t i B

E S U F E

) t i b

6 1

t i b

4 2

C C T I P S Q s l e n n a h C A M D C C T R

T U L L C C T D W T M D t n e m e r u s a e M y c n e u q e r F

) s l e n n a h C

m e t s y S t n e v E i s e n L t p u r r e t n I l a n r e t x E

) s l e n n a h C

e r a p m o C

) t i b

6 1

C T s n P i e g a k c a P M O C R E S 48 QFN 3 32 QFN 2 i s n P O P G I s l e n n a h C

s r o t a r a p m o C g o l a n A 27 2/4 14 1/0 27 2/4 14 1/0 D V C C A D r o s n e S e r u t a r e p m e T S E A G N R T y h p a r g o t p y r C y e K c i l b u P r o t i n o M k c e h C y t i r g e t n I t s u r T

f o

t o o R

) m B d

r e w o P X T x a M 2

. 5 h t o o t e u B l 0

. 3 i e e b g Z

4

. 5 1

. 2 0 8 8 4 8 4 1 Y Y Y Y Y Y 10 Y Y

) s l e n n a h C

C D A 8 4 8 4 PIC32CX5109BZ31048 PIC32CX5109BZ31032 WBZ351 WBZ350 64 512 96 3072 8/2 2/1 Y 16 Y 1/2 Y Y Y 32 4 39 LGA 30 LGA 3 2 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 16 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family PIC32CX-BZ3 and SoC Description 2. PIC32CX-BZ3 and SoC Description This chapter illustrates the block diagrams of the PIC32CX-BZ3 SoC. 2.1 PIC32CX-BZ3 SoC Block Diagram The following figure illustrates the block diagram of the core and peripheral modules in the PIC32CX-BZ3 SoC. Figure 2-1. PIC32CX-BZ3 SoC Block Diagram B D D N G p a g d n a B S S V A I O D D V

D D V D D V A R O P 3 3 R O B 2 1 R O B R O B P Z C D C D

O D L M l r t C U M P P C

C D A E S U F E O D L C A D O D L C

) V 2

. 1

G E R R W P 16 MHz XTAL N O A D D V

C S O S C R P L

M E S G E R V P L U t n C S D X PORT A/B O W S K L C E C A R T x A T A D E C A R T TPIU 24-bit SysTick Cortex-M4F CPU WDSP ETM-Coresight ETB MPU FPU K L C W S I O D W S Serial Wire

(SWD) DSU Config RoT(Boot ROM, EFUSE) Port-B Port-A GP-PortB GP-PortA 12-bit ADC+CVD 7-bit DAC Control ANx/

CVDx OUT

B A T R O P Single Bank Flash Flash Ctrl, WFT Wireless Subsystem Flash Controller DMA Controller

(16 Channel) Crypto AES TRNG HASH Public Key Crypto SRAM Control RAMECC I-Cache D-Cache Pre-fetch Cache CM4 CMCC 4 KB AHB High Speed Bus Matrix P O R T A B

PLL-SYS PB-Bridge-D AHB-APB Bridge A (PA) AHB-APB Bridge C (PC) AHB-APB Bridge B (PB) Event System FRC Osc Dividers CRU DMT WDT Timer/Counter for Control (TCC) (x3) Timer/Counter

(TC) (x8) SERCOM 0,1 (x2) FREQM PAC NMI EXTINTx EIC Control WOx QSIOx SIOx WOx SIOx

B A T R O P Quad SPI SERCOM2

(I2C) CCLIOx CCL (x2) Analog Comparator (x1) D S C n t D S W D T R T C C VDDBKUPCORE TAMPERx AN[3:0]

2.2 Pinout Diagram This section provides details on pin diagrams and signal names along with the device pinout for each variant of PIC32CX5109BZ31048 and PIC32CX5109BZ31032 SoC. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 17 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family PIC32CX-BZ3 and SoC Description Figure 2-2. PIC32CX5109BZ31048 and PIC32CX5109BZ31032 SoC Pin Diagram (Bottom View) 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 PIC32CX5109BZ31048 B o t t o m V i e w 32 31 30 29 28 27 26 25 PIC32CX5109BZ31032 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 18 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description 3. WBZ35 Module Description The WBZ35 modules are fully certified wireless modules built around PIC32CX-BZ3 SoC. The WBZ35 module integrates 16 MHz crystal and Trust&Go in addition to the circuits for power supply decoupling, RF matching and following antenna options:

PCB antenna (WBZ35xPE) U.FL connector for external antenna (WBZ35xUE) The Trust&GO is a pre-configured and pre-provisioned secure element of Microchips family of security focused devices. The operating voltage range for WBZ35 module is 1.9V-3.6V. It supports various peripherals as illustrated in the following figure. The following figure represents the WBZ35 module block diagram. Figure 3-1. WBZ35 Module Block Diagram WBZ35 Module Power Supply and Filtering NMCLR 16 MHz Crystal Power DC-DC/MLDO CLDO Bandgap Oscillators 32.768 kHz Osc Pins PWM Timer/Counter System Peripherals SWD/Trace Debug Debug PIC32CX-BZ3 SoC PCB Antenna with U.Fl provision Crypto AES HASH Public Key Crypto TRNG t o o B e r u c e S M O R E S U F E M Q E R F L C C

Cortex M4 CPU WDSP 64 MHz

B P A B H A M A R S Flash Wireless Subsystem Radio Transceiver Bluetooth Zigbee SERCOM QSPI GPIO/EIC PPS ADC+CVD/

AC/DAC RF Matching Circuit I2C ECC608B I2C/SPI/USART QSPI GPIO Analog Pins 3.1 Pinout Diagram The following figures illustrate the modules pinout diagrams. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 19 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Figure 3-2. WBZ351 and WBZ350 Module Pin Diagram (Top View) 26 25 24 23 22 21 WBZ351 WBZ350 Note:It is required that the exposed paddle on the bottom of the module be connected to ground in the PCB. See Pinout and Signal Descriptions List from Related Links. Related Links 4. Pinout and Signal Descriptions List 3.2 Basic Connection Requirement The WBZ35 module requires attention to a minimal set of device pin connections before proceeding with development. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 20 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Figure 3-3. Module Basic Connection and Interface Diagram for WBZ351 VDD GND R1 10k C1 0.1uF R2 0 GND VDD C2 0.1uF C3 4.7uF GND GND GND P B0 P B3 P B5 PA11 PA12 P B6 P B7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 EGND GND GND NMCLR P B0 P B3 P B5 AVDD GND PA11 PA12 GND P B6 P B7 WBZ351 8 B P 9 B P 4 A P 3 1 B P 1 A P D N G 1 1 B P 2 A P 0 A P 2 1 B P 5 A P 6 A P D N G P B4 P B1 P B2 PA3 PB10 PA14 PA13 PA10 PA7 PA9 PA8 VDD VDD 39 38 37 36 35 34 33 32 31 30 29 28 27 P B4 P B1 P B2 PA3 PB10 PA14 PA13 PA10 PA7 PA9 PA8 VDD C4 0.1uF C5 4.7uF 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 3 2 4 2 5 2 6 2 GND GND 8 B P 9 B P 4 A P 3 1 B P 1 A P 1 1 B P 2 A P 0 A P 2 1 B P 5 A P 6 A P GND GND 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 21 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Figure 3-4. Module Basic Connection and Interface Diagram for WBZ350 VDD R1 10k C1 0.1uF R2 0 GND VDD C2 0.1uF C3 4.7uF GND 1 2 3 4 5 6 7 8 9 10 GND NMCLR PA4 AVDD GND PA11 PA12 GND PB5 PA3 PA4 PA11 PA12 PB5 PA3 WBZ350 EP_PAD NC NC NC GND NC PA7 PA8 PA10 PA9 GND 31 30 29 28 27 26 25 24 23 22 21 PA7 PA8 PA10 PA9 GND 4 B P 6 B P 8 B P 9 B P 7 B P D D V D D V D N G 5 A P 6 A P 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 4 B P 6 B P 8 B P 9 B P 7 B P GND 5 A P 6 A P VDD C4 0.1uF C5 4.7uF GND GND 3.2.1 Power Pins It is recommended to add a bulk and a decoupling capacitor at the input supply pin (VDD, AVDD and GND pins) of the WBZ35 module. It is recommended to have a 4.7 F on the AVDD pin and 4.7 F and a 0.1 F on the VDD pin. The value of the capacitors are based on typical application requirements and are the minimum recommended values. Depending on the application requirement (in other words, a noisy power line or other known noise sources), the values of capacitors can be adjusted to provide a clean supply to the module. All capacitors must be placed close to the Module Power supply pins. Figure 3-5. Recommended Module Power Supply Connections WBZ35 AVDD VDD

(1) C3 4.7 F

(1) C2 0.1 F GND GND Notes:

1. 2. Value of the C2 and C3 capacitors may vary based on the application requirement. The C2 and C3 capacitors must be placed close to the module pin. 3.2.2 Master Clear (NMCLR) Pin The NMCLR pin provides for two specific device functions:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 22 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Device Reset Device programming and debugging Pulling the NMCLR pin low, generates a device Reset. Module Basic Connection and Interface Diagram illustrates a typical NMCLR circuit, see Module Basic Connection and Interface Diagram in the Basic Connection Requirement from Related Links. The module has sufficient filtering (0.1 F) and pull-up (10k) on the Reset line. On a typical application no extra filtering is required on this pin. Figure 3-6. Example of NMCLR Pin Connections VDD R 10k 0.1 F(2) C WBZ35 NMCLR R1(1) 1 k Notes:

1. 2. 470 R1 1 k limits any current flowing into NMCLR from the external capacitor C, in the event of NMCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the NMCLR pin VIH and VIL specifications are met without interfering with the Debug/Programmer tools. The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. Related Links 3.2. Basic Connection Requirement 3.2.3 SWD Lines The CM4_SWCLK, CM4_SWDIO and CM4_SWO pins are used for SWD Programming and debugging purposes. It is recommended that the CM4_SWCLK and CM4_SWDIO pin be used for the WBZ35 module for SWD as the default configuration (CM4_SWO can be optional). Keep the trace length between the SWD pins of the WBZ35 module and the SWD header as short as possible. If the SWD connector is expected to experience an ESD event, a series resistor is recommended with the value in the range of a few tens of s, not to exceed 100. Note:Provide an option for adding an external pull-up on SWDIO. 3.2.4 Unused I/O Pins It is recommended that unused I/O pins not be allowed to float as inputs. They can be configured as inputs and pulled up. Alternatively, depending on the application, they can be pulled down as well. 3.2.4.1 GPIO Pins/PPS Functions Most of the WBZ35 module pins can be configured as GPIOs pins or for PPS functionality. To find the functionality supported by each of these GPIOs, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. It is recommended that a series resistor be added on the host board for all critical, high frequency pins and clocks for EMI considerations. The value of the series resistor depends on the actual pin configuration. These resistors must be placed close to the module. Example of Host Board on Top Layer illustrates the placement of the series resistor;

see the Example of Host Board on Top Layer figure in the WBZ35 Module Routing Guidelines from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 3.4. WBZ35 Module Routing Guidelines 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 23 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description 3.3 WBZ35 Module Placement Guidelines For any Bluetooth Low Energy/Zigbee product, the antenna placement affects the performance of the whole system. The antenna requires free space to radiate RF signals and it must not be surrounded by the ground plane. Thus, for best PCB antenna performance, the WBZ35 module should be placed at the edge of the host board. The WBZ35 module ground outline edge should be aligned with the edge of the host board ground plane as shown in the following figure. A low-impedance ground plane for the WBZ35 module ensures the best radio performance (best range and lowest noise). The ground plane can be extended beyond the minimum recommendation as required for the host board EMC and noise reduction. For best performance, keep metal structures and components (such as mechanical spacers, bump-on, and so on) at least 31.75 mm away from the PCB trace antenna as illustrated in the following figure. The antenna on the WBZ35 module should not be placed in direct contact with or close proximity to plastic casing or objects. Keep a minimum clearance of 10 mm in all directions around the PCB antenna as shown in the following figure. Keeping Metallic and Plastic objects close to the antenna can detune the antenna and reduce the performance of the device. Exposed GND pads on the bottom of the WBZ35 module must be soldered to the host board (see Example of Host Board on Top Layer figure in the WBZ35 Module Routing Guidelines from Related Links). A PCB cutout or a Copper keepout is required under RF test point. See WBZ35 Module Packaging Information from Related Links. Copper keepout areas are required on the top layer under voltage test points. See WBZ35 Module Packaging Information from Related Links. Alternatively, the entire region except the exposed ground paddle can be solder-masked. The following figure illustrates the examples of WBZ35 module placement on a host board with a ground plane. Refer to the following figure for placement specific guidance. Figure 3-7. Module Placement Guidelines Module PCB Edge 16mm 31.75 mm (Keep out clearance region) for all metalic and plastic structures around the antenna. Refer to antenna specific details of the respective antenna. Edge of Host PCB Ground Plane No Copper Region 6mm Host PCB Ground Plane 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 24 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Related Links 3.4. WBZ35 Module Routing Guidelines 39.2. WBZ35x Module Packaging Information 3.4 WBZ35 Module Routing Guidelines Use the multi-layer host board for routing signals on the inner layer and the bottom layer. The top layer (underneath the module) of the host board must be ground with as many GND vias as possible, shown in the following figure. Avoid fan-out of the signals under the module or antenna area. Use a via to fan-out signals to theedge of the WBZ35 module. For a better GND connection to the WBZ35 module, solder the exposed GND pads of the WBZ35 module on the host board. For the module GND pad, use a GND via of a minimum 10 mil (hole diameter) for good ground to all the layers and thermal conduction path. Having a series resistor on the host board for all GPIOs is recommended. These resistors must be placed close to the WBZ35 module. Refer to the following figure for the placement of the series resistor. The SOSC crystal (32.768 kHz) on the host board must be placed close to the WBZ35 module and follow the shortest trace routing length with no vias (see the following figure). Figure 3-8. Example of Host Board on Top Layer Copper Keep out Region End of Ground Plane on the Base Board 32 kHz Crystal Placement and Routing Host PCB Board Edge Optional Series Resistor on the Digital Lines Module Footprint Exposed Grounding Pad Underneath Module No Routing Underneath the Module 3.5 WBZ35 Module RF Considerations The overall performance of the system is significantly affected by the product design, environment and application. The product designer must ensure system-level shielding (if required) and verify the performance of the product features and applications. Consider the following guidelines for optimal RF performance:

The WBZ35 module must be positioned in a noise-free RF environment and must be kept far away from high-frequency clock signals and any other sources of RF energy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 25 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description The antenna must not be shielded by any metal objects. The power supply must be clean and noise-free. Make sure that the width of the traces routed to GND, VDD rails are sufficiently large for handling peak TX current consumption. Note: The WBZ35 module includes RF shielding on top of the board as a standard feature. 3.6 WBZ35 Module Antenna Considerations 3.6.1 PCB Antenna For the WBZ35 module, the PCB antenna is fabricated on the top copper layer and covered in a solder mask. The layers below the antenna do not have copper trace. It is recommended that the module be mounted on the edge of the host board and to have no PCB material below the antenna structure of the module and no copper traces or planes on the host board in that area. The following table lists the technical specification of the PCB antenna when tested with the WBZ35 module mounted on an Evaluation Board. Table 3-1. PCB Antenna Specification for WBZ35 Parameter Operating frequency Peak gain Efficiency Specification 2400 to 2480 MHz 2.5 dBi at 2430 MHz 50

3.6.2 External Antenna Placement Recommendations The following recommendations must be applied for the placement of the antenna and its cable:

The antenna cable must not be routed over circuits generating electrical noise on the host board or alongside or underneath the module. It is preferred that the cable is routed straight out of the module. The antenna must not be placed in direct contact or in close proximity of the plastic casing/objects. (Except when the selected antenna specifically recommends it). Do not enclose the antenna within a metal shield. Keep any components that may radiate noise, signals or harmonics within the 2.4 GHz to 2.5 GHz frequency band away from the antenna and, if possible, shield those components. Any noise radiated from the host board in this frequency band degrades the sensitivity of the module. The antenna must be placed at a distance greater than 5 cm away from the module. The following figure shows the antenna keepout area where the antenna must not be placed. These recommendations are based on an open-air measurement and do not take into account any metal shielding of the customer end product. When a metal enclosure is used, the antenna can be located closer to the WBZ35 module. Note: These are generic guidelines and it is recommended that customers check and fine-tune the antenna positioning in the final host product based on RF performance. The following figure provides an indication on how the antenna cable must be routed depending on the location of the antenna with respect to the WBZ35 PCB; there are two possible options for the optimum routing of the cable. 2022 Microchip T echnology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 26 Microchip Confidential PIC32CX-BZ3 and WBZ35x Family WBZ35 Module Description Refer to the solder paste data sheet for specific reflow profile recommendations from the vendor. Use no-clean flux solder paste. Do not wash as moisture can be trapped under the shield. Use only one flow. If the PCB requires multiple flows, apply the module on the final flow. 3.7.1 Cleaning The exposed GND pad helps to self-align the module, avoiding pad misalignment. The recommendation is to use the no clean solder pastes. Ensure full drying of no-clean paste fluxes as a result of the reflow process. As per the recommendation by the solder paste vendor, this requires longer reflow profiles and/or peak temperatures toward the high end of the process window. The uncured flux residues can lead to corrosion and/or shorting in accelerated testing and possibly the field. 3.8 WBZ35 Module Assembly Considerations The WBZ35 module is assembled with an EMI shield to ensure compliance with EMI emission and immunity rules. The EMI shield is made of a tin-plated steel (SPTE) and is not hermetically sealed. Use the solutions such as IPA and similar solvents to clean this module. Cleaning solutions containing acid must never be used on the module. 3.8.1 Conformal Coating The modules are not intended for use with a conformal coating, and the customer assumes all risks (such as the module reliability, performance degradation and so on) if a conformal coating is applied to the modules. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 28 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Pinout and Signal Descriptions List 4. Pinout and Signal Descriptions List This following table provides details signal names classified by the peripherals along with the device pinout for each variant of the PIC32CX-BZ3 and the WBZ35x module. Table 4-1. Pinout and Signal Descriptions List SoC Module PIC32CX5109BZ 31032 PIC32CX5109BZ 31048 WBZ351 WBZ350 0(3) 0(3) 0(3), 1, 2, 8, 11, 19, 26 0(3), 1, 5, 8, 18, 21, 27 GND Pin Name(1)(2)(5) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 22 18 21 24 19 VPMU_VDD QSPI_DATA0/RTC_IN3/RPA0/IOCA0/RA0 QSPI_SCK/RTC_IN2/RPA1/IOCA1/RA1 QSPI_DATA3/RTC_IN1/RPA2/IOCA2/RA2 SERCOM0_PAD0/AC_CMP0/RPA5/IOCA5/RA5 27, 28 16, 17 VDD 25 31 29 30 32 23 17 15 14 16 33 34 3 20 25 24 22 23 14 13 3 2 TRD3/SERCOM0_PAD1/AC_CMP1_ALT/RPA6/IOCA6/RA6 TRCLK/SERCOM1_PAD0/RPA7/IOCA7/RA7 SERCOM1_PAD1/RPA8/IOCA8/RA8 SERCOM1_PAD2/RTC_IN0_ALT/RPA9/IOCA9/RA9 SERCOM1_PAD3/RTC_OUT_ALT/RPA10/IOCA10/RA10 QSPI_DATA1/RPB12/IOCB12/RB12 QSPI_CS/RTC_EVENT(6)/RPB13/IOCB13/RB13 CM4_SWDIO/SERCOM0_PAD2/RPB9/INT0/IOCB9/RB9 CM4_SWCLK/RPB8/IOCB8/RB8 SERCOM0_PAD3/RTC_OUT(6)/RPA4/IOCA4/RA4 SERCOM2_PAD0(7)/AC_CMP1/RPA13/IOCA13/RA13 SERCOM2_PAD1(7)/RPA14/IOCA14/RA14 NMCLR VDDCORE CLDO_IN XO_N XO_P VDD_RF/VDD_PLL 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 29 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Pinout and Signal Descriptions List

...........continued SoC Module PIC32CX5109BZ 31032 PIC32CX5109BZ 31048 WBZ351 WBZ350 Pin Name(1)(2)(5) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4 38 37 5 39 7 6 12 13 36 35 20 9 10 11 4 9 12 15 10 6 7 CLDO_OUT RFLDO_OUT BUCK_CLDO BUCK_PA RF_IO NC AN4/CVD4/CVDR4/CVDT4/AC_AIN2/RPB0/IOCB0/RB0 AN5/CVD5/CVDR5/CVDT5/AC_AIN3/RPB1/IOCB1/RB1 AN6/CVD6/CVDR6/CVDT6/AC_AIN0/RPB2/IOCB2/RB2 AN7/CVD7/CVDR7/CVDT7/AC_AIN1/RPB3/IOCB3/RB3 AN0/CVD0/CVDR0/CVDT0/RPB4/IOCB4/RB4(8) AVDD (VDDA) TRD0/AN1/CVD1/CVDR1/CVDT1/RPB5/IOCB5/RB5(8) TRD1/AN2/CVD2/CVDR2/CVDT2/RPB6/IOCB6/RB6(8) CM4_SWO/AN3/CVD3/CVDR3/CVDT3/LVDIN/RPB7/IOCB7/

RB7(8) TRD2/SCLKI/DACOUT/ANN0/RTC_IN0/RPA3/IOCA3/RA3 VDD RPB10/IOCB10/RB10 QSPI_DATA2/RPB11/IOCB11/RB11 SOSCI/RA11(4) SOSCO/RA12(4) PMU_MLDO_BUCK_VSENSE/PMU_MLDO_OUT VPMU_VDD PMU_BK_LX 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 30 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Pinout and Signal Descriptions List

...........continued SoC Module PIC32CX5109BZ 31032 PIC32CX5109BZ 31048 WBZ351 WBZ350 Notes:

Pin Name(1)(2)(5) 1. 2. 3. 4. 5. 6. 7. 8. All GPIOs (RAn and RBn) can be used by remappable peripherals via PPS. All GPIOs (RAn and RBn) can be used as I/O Change Notification (IOCAn and IOCBn). The metal paddle at the bottom of the device must be connected to the system ground. This pin can be used as an Input only pin if SOSC is not used. These I/O pins are 5.5V tolerant: NMCLR, RA0, RA1, RA2, RA4, RA5, RA6, RA7, RA8, RA10, RA13, RA14, RB10, RB11, RB12 and RB13. All other I/O pins are 3.3V tolerant. The RTC_OUT and RTC_EVENT signals are multiplexed. Any one of the signal can be out at a time in pin limited variants

(32-pin variant). The SERCOM2 has only I2C functionality. The SERCOM2_PAD0 is I2C_SERCOM_SDA and the SERCOM2_PAD1 is I2C_SERCOM_SCL. JTAG is the default functionality on these pins. It is recommended to write 0 to CFGCON0.JTAGEN register during Application initialization to use these pins for regular GPIO functionality. See CFGCON0 register from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 31 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5. I/O Ports and Peripheral Pin Select (PPS) 5.1 Overview General purpose I/O (GPIO) pins allow the PIC32CX-BZ3 devices to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. For more details on pin multiplexing, see GPIO Pins/PPS Functions from Related Links. There are default priorities for each GPIO pin as well. For details on priorities, see Function Priority for Device Pins from Related Links. It must be noted that fuse values stored in Boot Flash memory (NVR) can be used to alter the power-on default function for certain GPIO pin. See System Configuration and Register Locking (CFG) from Related Links. Related Links 3.2.4.1. GPIO Pins/PPS Functions 5.7. Function Priority for Device Pins 18. System Configuration and Register Locking (CFG) 5.2 Features Some of the key features of the I/O ports are:

Individual output pin open-drain enable/disable Individual input pin weak pull-up and pull-down Monitor selective inputs and generate interrupt when change in pin state is detected Operation during Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Slew rate control (not available on all devices) Flexibility for Peripheral Pin remapping through PPS 5.3 Block Diagram The following figure illustrates a block diagram of a typical multiplexed I/O port. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 32 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Figure 5-1. Typical Multiplexed Port Structure Block Diagram PIO Module RD ODC Data Bus PB1_CLK WR ODC RD TRIS WR TRIS WR LAT WR PORT RD LAT RD PORT Sleep PB1_CLK Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PPS Control PB1_CLK ODC D CK Q Q EN TRIS LAT D CK EN D CK EN Q Q Q Q 1 0 I/O Cell 0 1 1 0 1 0 Output Multiplexers I/O Pin Q Q D CK Q Q D CK Synchronization Peripheral Input Peripheral Input Buffer R 5.4 Parallel I/O (PIO) Ports Each I/O port has 14 registers directly associated with the operation of the port. Each I/O port pin has a corresponding bit in these registers. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a 1, then the pin is an input. All port pins are defined as inputs after a Reset. Throughout this section, the letter x, denotes any or all port module instances. For example, TRISx represents TRISA or TRISB. Any bit and its associated data and control registers that is not valid for a particular device will be disabled and will read as zeros. 5.4.1 I/O Ports Configuration 5.4.1.1 Configuring Port Functions (PORTx) The PORTx registers allow I/O pins to be accessed:

A write to a PORTx register writes to the corresponding LATx register (PORTx data latch). Those I/O port pin(s) configured as outputs are updated. A write to a PORTx register is effectively the same as a write to a LATx register. A read from a PORTx register reads the synchronized signal applied to the port I/O pins. 5.4.1.2 Configuring Latch Functions (LATx) The LATx registers (PORTx data latch) hold data written to port I/O pins:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 33 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) A write to a LATx register latches data to corresponding port I/O pins. Those I/O port pins configured as outputs are updated. A read from a LATx register reads the data held in the PORTx data latch, not from the port I/O pins. 5.4.1.3 Open-Drain Configuration (ODCx) Each I/O pin can be individually configured for either normal digital output or open-drain output. This is controlled by the open-drain control register, ODCx, associated with each I/O pin. If the ODCx bit for an I/O pin is a 1, the pin acts as an open-drain output. If the ODCx bit for an I/O pin is a 0, the pin is configured for a normal digital output (the ODCx bit is valid only for output pins). After a Reset, the status of all the bits of the ODCx register is set to 0. The open-drain feature allows the generation of outputs higher than VDD (for example, 5V) on any desired 5V-

tolerant pins using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. The ODCx register setting functions in all of the I/O modes, allowing the output to behave as an open-drain even if a peripheral is controlling the pin. Although, the user may achieve the same result by manipulating the corresponding LATx and TRISx bits, this procedure does not allow the peripheral to operate in the Open-Drain mode (except for the default operation of the I2C pins). I2C pins are already open-drain pins; therefore, the ODCx settings do not influence the I2C pins. 5.4.1.4 Configuring Analog and Digital Port Pins (ANSELx) The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRISx bits set. To use port pins for I/O functionality with digital modules, such as Timers, SERCOMs and so on, the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are, by default, analog and not digital. If the TRISx bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or the comparator module. When the PORTx register is read, all pins configured as analog input channels are read as cleared (a low-level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. 5.4.1.5 Configuring Tri-State Functions (TRISx) The TRISx registers configure the data direction flow through port I/O pins. The TRISx register bits determine whether a PORTx I/O pin is an input or an output:

If a data direction bit is 1, the corresponding I/O port pin is an input. If a data direction bit is 0, the corresponding I/O port pin is an output. A read from a TRISx register reads the last value written to that register. All I/O port pins are defined as inputs after a Power-on Reset (POR). 5.4.1.6 I/O Port Write/Read Timing One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction is an NOP. 5.4.1.7 Input Change Notification (CN) The Input Change Notification (CN) function of the I/O ports allows PIC32CX-BZ3 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change of states even in the Sleep mode, when the clocks are disabled. The following control registers are associated with the CN functionality of each I/O port:

Change Notice Pull-up Enable (CNPUEx) Change Notice Pull-down Enable (CNPDx) Change Notice Control (CNCONx) Change Notice Enable (CNENx/CNNEx) Change Notice Status (CNSTATx/CNFx) or the positive edge control Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source or sink source connected to the pin and eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUEx and the CNPDx registers, 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 34 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. Note:Pull-ups and pull-downs on change notification pins must always be disabled when the port pin is configured as a digital output The CNCONx registers provide change notice control. The CNENx/CNNEx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. CNENx enables a mismatch CN interrupt condition when EDGEDETECT is not set. When EDGEDETECT is set, CNNEx controls the negative edge while CNENx controls the positive. On devices that do not have EDGEDETECT, this CN logic acts as if EDGEDETECT is not set. The CNSTATx/CNFx registers indicate whether a change occurred on the corresponding pin since the last read of the PORTx bit. The CNFx registers indicate the type of change that occurred. 5.4.1.7.1 CN Configuration and Operation The CN pins are configured as follows:

Set the desired CN I/O pin as an input by setting the corresponding TRISx register bits = 1. Enable the CN Module by setting the ON bit (CNCONx[15]) = 1. Enable the individual CN input pins, and optional pull-ups or pull-downs. 1. Disable the CPU interrupts. 2. 3. 4. 5. Read the corresponding PORTx registers to clear the CN interrupt. 6. Configure the CN Interrupt Priority bits, NVIC.IP register. 7. Clear the CN Interrupt Flag bit, by setting the corresponding CLRPEND bit in NVIC.IPCR register. 8. Configure the CN pin interrupt for a specific edge detect using the EDGEDETECT bit in the CNCONx register, and set up edge control using the CNENx/CNNEx bits. Enable the CN Interrupt Enable bit, by setting the corresponding enable bit in NVIC.ISER register. 9. 10. Enable CPU interrupts. The CNSTATx/CNFx registers indicate, whether a change occurred on the corresponding pin since the last read of the PORTx bit. The CNFx registers indicate the type. When a CN interrupt occurs in the Mismatch mode, the user must read the PORTx register associated with the CN pins. This will clear the mismatch condition and set up the CN logic to detect the next pin change. The current PORTx value can be compared to the PORTx read value obtained at the last CN interrupt or during initialization, and used to determine which pin is changed. The CN pins have a minimum input pulse-width specification. See Electrical Characteristics from Related Links. Related Links 38. Electrical Characteristics 5.4.1.8 Slew Rate Control Some I/O pins can be configured for various types of slew rate control on its associated port. This is controlled by the slew rate control bits in the SRCON1x and SRCON0x registers that are associated with each I/O port. The slew rate control is configured using the corresponding bit in each register, as shown in the following table. As an example, writing 0x0001, 0x0000 to SRCON1A and SRCON0A, respectively, can enable slew rate control on the RA0 pin and sets the slew rate to the slow edge rate. Table 5-1. Slew Rate Control Bit Settings(1) SRCON1x SRCON0x Description 1 1 0 0 1 0 1 0 Slew rate control is enabled and is set to the slowest edge rate Slew rate control is enabled and is set to the slow edge rate Slew rate control is enabled and is set to the medium edge rate Slew rate control is disabled and is set to the fastest edge rate 1. By default, all the port pins are set to the fastest edge rate. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 35 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.4.1.9 CLR, SET and INV Registers Every I/O module register has corresponding SET, CLR and INV registers, which provide atomic bit manipulations. As the name of the registers imply, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as 1 are modified. Bits specified as 0 are not modified. For example, Writing 0x0001 to the TRISASET register sets only bit 0 in the base register TRISA Writing 0x0020 to the PORTBCLR register clears only bit 5 in the base register PORTB Writing 0x9000 to the LATAINV register inverts only bits 15 and 12 in the base register LATA Reading the SET, CLR and INV registers returns an undefined value. To see the influences of a write operation to a SET, CLR or INV register, the base register must be read instead. A typical method to toggle an I/O pin requires a read-modify-write operation performed on a PORTx register in the software. For example, a read from a PORTx register, mask and modify the desired output bit or bits, and write the resulting value back to the PORTx register. This method is vulnerable to a read-modify-write issue where the port value may change after it is read and before the modified data can be written back, thus, changing the previous state. This method also requires more instructions. A more efficient and atomic method uses the PORTxINV register. A write to the PORTxINV register effectively performs a read-modify-write operation on the target base register, equivalent to the software operation described previously; however, it is done in the hardware. To toggle an I/O pin using this method, a 1 is written to the corresponding bit in the PORTxINV register. This operation reads the PORTx register, inverts only those bits specified as 1, and writes the resulting value to the LATx register, thus, toggling the corresponding I/O pins all in a single atomic instruction cycle. PORTAINV = 0x0001. 5.5 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. The PPS configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, the users can better modify the device to their entire application, rather than trimming the application to fit the device. This feature operates over a fixed subset of digital I/O pins. The users may independently map the input and/or output of most digital peripherals to these I/O pins. The PPS configuration is performed in the software and generally does not require the device to be reprogrammed. The hardware safeguards that prevent accidental or spurious changes to the peripheral mapping are included once the PPS configuration is established. In PPS mode, Maximum peripheral clock frequency = Direct mode clock frequency/2. Note:Direct Mode is a mode in which peripherals are running based on Function Priority for Pins and not using PPS. 5.5.1 Re-mappable Pin Groupings The remappable pins, as well as the available input and output functions are divided into five groups. The remappable pins of group k may be assigned pin functions only from group k, k = 1,2,3,4,5. The pins used by each peripheral are spread across all five groups when possible to maximize flexibility. 5.5.2 Available Pins The number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation RPn in their full pin designation, where:

RP Designates a remappable peripheral n Remappable port number 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 36 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.5.3 Available Peripherals The peripherals managed by the PPS are all digital-only peripherals. These include general serial communications

(SERCOM), general purpose timer clock inputs, timer-related peripherals (input capture and output compare), interrupt-on-change inputs and reference clocks (input and output). In comparison, some digital-only peripheral modules are never included in the PPS feature. This is because the peripherals function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the ADC. A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 5.5.4 RP Register Protection The <INPUT>R and RPxxR registers are implemented with two levels of protection:

I/O Lock Feature All PPS registers may only be written while CFGCON0.IOLOCK = 0; once the IOLOCK is set, the registers cannot be written. IOLOCK Protection The state of the IOLOCK bit can only be changed once it is unlocked using the CFGCON0.CFGLOCK[1:0] register. These features prevent the RP registers from being inadvertently written during normal operation because changing the pinout functionality may have detrimental system-level outcome. 5.5.5 Controlling PPS The PPS features are controlled through two sets of SFRs: one to map peripheral inputs and another to map outputs. They are separately controlled; therefore, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is mapped. 5.5.5.1 Remappable Inputs 5.5.5.1.1 Enabling Remappable Peripheral Inputs With PPS, each remappable input pin function (EXTINT0, SERCOM0_PAD3 and so on.) is assigned to be driven from a specific device pin by programming the corresponding <INPUT>R[3:0] register (meaning, EXTINT0R[3:0], SCOM0P3R[3:0], and so on.) with a value defined in the Input Pin Selection Group 1, Input Pin Selection Group 2, Input Pin Selection Group 3, Input Pin Selection Group 4, Input Pin Selection Group 5 tables and [pin name]R register. See these tables in the Remappable Input Example and [pin name]R from Related Links. Assigning a remappable input pin function does not automatically enable the digital input buffer on the pin. The buffer must be enabled for each remap pin (RPx) by disabling all higher priority pin functions on that pin. Typically, all functions other than GPIO are considered higher priority than remap pins. See Function Priority for Device Pins for the list and priority of pin functions on each pin from Related Links. The mapping is dynamic; therefore in order to avoid glitching outputs, the user is responsible for turning off the appropriate peripherals before remapping the pin functions associated with that peripheral. Since on Reset all inputs are mapped to a default value and all outputs are disabled, the mapping may safely be performed after any device Reset. Related Links 5.5.5.1.3. Remappable Input Example 5.14.1. [pin name]R 5.7. Function Priority for Device Pins 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 37 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.5.5.1.2 Remappable Input Priority Since only a single pin can be selected for any of the remappable peripheral inputs, priority encoding is not needed for RP inputs. Note:A remappable input function does not have any control over the output of the RPx pin. In this way, it is possible to drive a remappable output function on a RPx pin and a completely different remappable input function on the same pin. This can be useful, for instance, in driving a EVSYS output back into a Timer clock or gating input by assigning both functions to the same remap pin. Note:To allow flexibility on a different pin variant, same input functions are repeated in multiple groups. Therefore, in order to differentiate between them Off code is provided in the Input Pin Selection Group tables. See these tables in the Remappable Input Example from Related Links. The software must ensure that unused group register offset of a (repeated) input function is programmed to 4h0 for proper operation. Failure to do so will lead to unknown behavior. Related Links 5.5.5.1.3. Remappable Input Example 5.5.5.1.3 Remappable Input Example For example, following figure illustrates the remappable pin selection for the EXTINT0 input. In order to remap the EXTINT0 input to a particular pin, the EXTINT0R remap register must be programmed. Since EXTINT0 is in group 1, it can be mapped to any pin that is in group 1 (RPA3, RPA7, RPA9, RPA11, RPB0, RPB4, RPB8, and so on). In order to map EXTINT0 to RPB0, program the value 4 (4b0100) into the EXINTR0R SFR register. See the Input Pin Selection Group 1 table in the Input Mapping in PIC32CX-BZ3 Family of Devices from Related Links . Figure 5-2. EXTINT0 Remappable Pin Selection EXTINT0R[3:0]

RPA3 RPA7 RPA11 RPn EXTINT0 Input to Peripheral 0 1 2 n Note:For input only, PPS functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to 1). Related Links 5.5.5.1.4. Input Mapping in PIC32CX-BZ3 Family of Devices 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 38 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.5.5.1.4 Input Mapping in PIC32CX-BZ3 Family of Devices The following tables provide input mapping in PIC32CX-BZ3 family of devices Table 5-2. Input Pin Selection Group 1 Peripheral Pin (pin name)

[pin name]R SFR

[pin name]R bits

[pin name]R Value to RPn Pin Selection EXTINT0 EXTINT0R EXTINT0R[3:0]

0000 = Off SERCOM0_PAD3 SCOM0P3R SCOM0P3R[3:0]

0001 = RPA3 SERCOM1_PAD2 SCOM1P2R SCOM1P2R[3:0]

QD1 CCLIN0 CCLIN3 TC0_WO0G1 TC1_WO0G1 TC2_WO0G1 TC3_WO0G1 TC4_WO0G1 TC5_WO0G1 TC6_WO0G1 TC7_WO0G1 QD1R CCLIN0R CCLIN3R QD1R[3:0]

CCLIN0R[3:0]

CCLIN3R[3:0]

TC0WO0G1R TC0WO0G1R[3:0]

TC1WO0G1R TC1WO0G1R[3:0]

TC2WO0G1R TC2WO0G1R[3:0]

TC3WO0G1R TC3WO0G1R[3:0]

TC4WO0G1R TC4WO0G1R[3:0]

TC5WO0G1R TC5WO0G1R[3:0]

TC6WO0G1R TC6WO0G1R[3:0]

TC7WO0G1R TC7WO0G1R[3:0]

0010 = RPA7 0011 = RPA11*

0100 = RPB0*

0101 = RPB4 0110 = RPB8 0111 = RPB12*

1000 = RPA2*

1001 = RPA6 1010 = RPA10 1011 = RPA14 1100 = RPB3 1101 = RPB7 1110 = RPB11 1111 = RPA9 Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 39 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-3. Input Pin Selection Group 2 Peripheral Pin (pin name)

[pin name]R SFR

[pin name]R bits

[pin name]R Value to RPn Pin Selection EXTINT1 EXTINT1R EXTINT1R[3:0]

0000 = Off SERCOM0_PAD0 SCOM0P0R SCOM0P0R[3:0]

0001 = RPA4 SERCOM1_PAD3 SCOM1P3R SCOM1P3R[3:0]

QD2 CCLIN1 CCLIN4 TC0_WO0G2 TC1_WO1G2 TC2_WO1G2 TC3_WO1G2 TC4_WO1G2 TC5_WO1G2 TC6_WO1G2 TC7_WO1G2 QD2R CCLIN1R CCLIN4R QD2R[3:0]

CCLIN1R[3:0]

CCLIN4R[3:0]

TC0WO0G2R TC0WO0G2R[3:0]

TC1WO1G2R TC1WO1G2R[3:0]

TC2WO1G2R TC2WO1G2R[3:0]

TC3WO1G2R TC3WO1G2R[3:0]

TC4WO1G2R TC4WO1G2R[3:0]

TC5WO1G2R TC5WO1G2R[3:0]

TC6WO1G2R TC6WO1G2R[3:0]

TC7WO1G2R TC7WO1G2R[3:0]

0010 = RPA8 0011 = RPA12*

0100 = RPB1*

0101 = RPB5 0110 = RPB9 0111 = RPB13*

1000 = RPA3 1001 = RPA7 1010 = RPA11*

1011 = RPB0*

1100 = RPB4 1101 = RPB8 1110 = RPB12*

1111 = RPA0*

Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 40 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-4. Input Pin Selection Group 3 Peripheral Pin (pin name)

[pin name]R SFR

[pin name]R bits

[pin name]R Value to RPn Pin Selection EXTINT2 EXTINT2R EXTINT2R[3:0]

0000 = Off SERCOM1_PAD0 SCOM1P3R SCOM1P3R[3:0]

0001 = RPA5 QD3 CCLIN2 CCLIN5 TC0_WO1G3 TC2_WO0G3 TC3_WO0G3 TC3_WO0G3 TC4_WO0G3 TC5_WO0G3 TC6_WO0G3 TC7_WO0G3 QD3R CCLIN2R CCLIN5R QD3R[3:0]

CCLIN2R[3:0]

CCLIN5R[3:0]

TC0WO1G3R TC0WO1G3R[3:0]

TC1WO0G3R TC1WO0G3R[3:0]

TC2WO0G3R TC2WO0G3R[3:0]

TC3WO0G3R TC3WO0G3R[3:0]

TC4WO0G3R TC4WO0G3R[3:0]

TC5WO0G3R TC5WO0G3R[3:0]

TC6WO0G3R TC6WO0G3R[3:0]

TC7WO0G3R TC7WO0G3R[3:0]

0010 = RPA9 0011 = RPA13*

0100 = RPB2*

0101 = RPB6 0110 = RPB10*

0111 = RPA0*

1000 = RPA4 1001 = RPA8 1010 = RPA12*

1011 = RPB1*

1100 = RPB5 1101 = RPB9 1110 = RPB13*

1111 = RPA1*

Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 41 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-5. Input Pin Selection Group 4 Peripheral Pin (pin name)

[pin name]R SFR

[pin name]R bits

[pin name]R Value to RPn Pin Selection EXTINT3 NMI EXTINT3R EXTINT3R[3:0]

0000 = Off NMIR NMIR[3:0]

0001 = RPA6 SERCOM0_PAD2 SCOM0P2R SCOM0P2R[3:0]

QD0 TC0_WO1G4 TC2_WO1G4 TC3_WO1G4 TC4_WO1G4 TC5_WO1G4 TC6_WO1G4 TC7_WO1G4 QD0R QD0R[3:0]

TC0WO1G4R TC0WO1G4R[3:0]

TC2WO1G4R TC2WO1G4R[3:0]

TC3WO1G4R TC3WO1G4R[3:0]

TC4WO1G4R TC4WO1G4R[3:0]

TC5WO1G4R TC5WO1G4R[3:0]

TC6WO1G4R TC6WO1G4R[3:0]

TC7WO1G4R TC7WO1G4R[3:0]

0010 = RPA10 0011 = RPA14*

0100 = RPB3*

0101 = RPB7 0110 = RPB11*

0111 = RPA1*

1000 = RPA5 1001 = RPA9 1010 = RPA13*

1011 = RPB2*

1100 = RPB6 1101 = RPB10*

1110 = RPB8 1111 = RPA2*

Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 42 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-6. Input Pin Selection Group 5 Peripheral Pin (pin name)

[pin name]R SFR

[pin name]R bits

[pin name]R Value to RPn Pin Selection SERCOM0_PAD1 SCOM0P1R SCOM0P1R[3:0]

0000 = Off SERCOM1_PAD1 SCOM1P1R SCOM1P1R[3:0]

0001 = RPA3 REFI REFIR REFIR[3:0]

0010 = RPA5 0011 = RPA6 0100 = RPA7 0101 = RPB5 0110 = RPB6 0111 = RPB8 1000 = RPB9 1001 = Off 1010 = Off 1011 = Off 1100 = Off 1101 = Off 1110 = Off 1111 = Off 5.5.5.2 Remappable Output The remappable pin output assigns a peripheral output function to an output pin. Once the group for the output pin is identified, see the following table which shows peripheral output functions and its group. Each remappable output can be programmed to an output function that is from its same output group number. As an example, if RPA0 is part of GROUP2, then it can be programmed to have any GROUP2 output function on its pin. Therefore, for a given output peripheral signal, the user must first choose which remappable pin to use, choose a Group number for that pin, and then program the control registers for that pin. For example, RPA<0-10, 13, 14>

G<1, 2, 3, 4> R or RPB<0-13> G<1, 2, 3, 4>R. See Remappable Output Pin Configuration Group1, Remappable Output Pin Configuration Group2, Remappable Output Pin Configuration Group3, and Remappable Output Pin Configuration Group4 tables in the Pin Output RP Registers from Related Links. The rules for which group belong to which pin must be followed, such that multiple peripherals are not driving the same pin from different groups. For instance, pin RPA0 (PA0) as an output belongs to Group2 and Group3. If the peripheral driving the signal to RPA0 is coming from Group2, the software must ensure that all Group3 signals for RPA0 are disabled with an OFF value in the corresponding RPA0G3R control register. A null output is associated with the output register reset value of 0. This is done to ensure that remappable outputs remain disconnected from all output pins, by default. Related Links 5.5.5.2.1. Pin Output RP Registers 5.5.5.2.1 Pin Output RP Registers Register RPnR shows the RP Remap Register format for output functions. See RPnR from Related Links. Each RP pin has a 4-bit field that can be assigned to the desired output function. See the following tables for a complete list of output function values and its associated register names. The mapping is dynamic, therefore in order to avoid glitching outputs, the user must ensure to turn off the appropriate peripherals before remapping the functions. Since on Reset, all inputs are mapped to a default value and all outputs are disabled, the mapping must be performed after any device Reset. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 43 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Figure 5-3. Example Multiplexing of Remappable Output Signal for RPA0 (Map Output Function to Pin) RPA0G2R[4:0]

1'b0 SERCOM0_PAD0 SERCOM0_PAD3

(Others) 0 1 2 31 RPA0 Related Links 5.14.2. RPnR 5.5.5.2.2 Output Mapping in PIC32CX-BZ3 Family of Devices The following tables provide output mapping in PIC32CX-BZ3 family of devices Table 5-7. PPS Output Groups Group1 Off Group2 Off SERCOM0_PAD1 SERCOM0_PAD0 Group3 Off Off Group4 Off SERCOM0_PAD2 SERCOM1_PAD1 SERCOM0_PAD3 SERCOM0_PAD0 Off REFO1 REFO2 REFO3 REFO4 QSPI_SCK Off Off Off Off Off Off Off Off Off Off Off Off SERCOM0_PAD2 SERCOM0_PAD3 SERCOM0_PAD0 Off SERCOM1_PAD2 SERCOM1_PAD3 SERCOM1_PAD3 Off Off SERCOM1_PAD2 SERCOM1_PAD3 SERCOM1_PAD0 TCC0_WO1 TCC0_WO5 TCC0_WO3 TCC1_WO1 TCC1_WO5 TCC1_WO3 TCC2_WO1 Off TC0_WO1 TC1_WO1 TC2_WO1 TC3_WO1 TC4_WO1 TCC0_WO2 TCC0_WO0 TCC0_WO4 TCC1_WO2 TCC1_WO0 TCC1_WO4 TCC2_WO0 Off TC0_WO0 TC1_WO0 TC2_WO0 TC3_WO0 TC4_WO0 TCC0_WO3 TCC0_WO1 TCC0_WO5 TCC1_WO3 TCC1_WO1 TCC1_WO5 TCC2_WO1 Off TC0_WO0 TC1_WO1 TC2_WO1 TC3_WO1 TC4_WO1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 44 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Group1 Off Off Off Off Off Off Off Off Group2 TC5_WO1 TC6_WO1 TC7_WO1 QSPI_CS QSPI_DATA0 QSPI_DATA3 QSPI_DATA2 CCL_OUT1 Group3 TC5_WO0 TC6_WO0 TC7_WO0 QSPI_CS QSPI_DATA1 QSPI_DATA0 QSPI_DATA3 CCL_OUT0 Group4 TC5_WO1 TC6_WO1 TC7_WO1 QSPI_CS QSPI_DATA2 QSPI_DATA1 QSPI_DATA0 CCL_OUT1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 45 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-8. Remappable Output Pin Configuration Group1 RPn Port Pin RPnG1R SFR RPnG1R bits RPnG1R Value to Peripheral Pin Selection RPA3 RPA5 RPA6 RPA7 RPB5 RPB6 RPB7 RPB8 RPB9 RPA3G1R RPA5G1R RPA6G1R RPA7G1R RPA3G1R[4:0]

00000 = Off RPA5G1R[4:0]

00001 = SERCOM0_PAD1 RPA6G1R[4:0]

00010 = SERCOM1_PAD1 RPA7G1R[4:0]

00011 = REFO1 RPB5G1R RPB5G1R[4:0]

RPB6G1R RPB6G1R[4:0]

RPB7G1R RPB7G1R[4:0]

00100 = REFO2 00101 = REFO3 00110 = REFO4 RPB8G1R RPB8G1R[4:0]

00111 = QSPI_SCK RPB9G1R RPB9G1R[4:0]

01000 = Off 01001 = Off 01000 = Off 01001 = Off 01010 = Off 01011 = Off 01100 = Off 01101 = Off 01110 = Off 01111 = Off 10000 = Off 10001 = Off 10010 = Off 10011 = Off 10100 = Off 10101 = Off 10110 = Off 10111 = Off 11000 = Off 11001 = Off 11010 = Off 11011 = Off 11100 = Off 11101 = Off 11110 = Off 11111 = Off Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 46 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-9. Remappable Output Pin Configuration Group2 RPn Port Pin RPnG2R SFR RPnG2R bits RPnG2R Value to Peripheral Pin Selection RPA0*

RPA3 RPA4 RPA6 RPA7 RPA8 RPB0*

RPB1*

RPB4 RPB5 RPB8 RPB12*

RPB13*

RPA0G2R RPA3G2R RPA4G2R RPA0G2R [4:0]

00000 = Off RPA3G2R[4.0]

00001 = SERCOM0_PAD0 RPA4G2R[4.0]

00010 = SERCOM0_PAD3 RPA6G2R RPA6G2R[4.0]

00011 = SERCOM0_PAD2 RPA3G2R RPA7G2R[4.0]

00100 = Off RPA8G2R RPA8G2R[4.0]

00101 = SERCOM1_PAD3 RPB0G2R RPB0G2R[4.0]

00110 = SERCOM1_PAD2 RPB1G2R RPB1G2R[4.0]

RPB4G2R RPB4G2R[4.0]

RPB5G2R RPB5G2R[4.0]

RPB8G2R RPB8G2R[4.0]

RPB12G2R RPB12G2R[4.0]

RPB13G2R RPB13G2R[4.0]

00111 = TCC0_WO1 01000 = TCC0_WO5 01001 = TCC0_WO3 01010 = TCC1_WO1 01011 = TCC1_WO5 01100 = TCC1_WO3 01101 = TCC2_WO1 01110 = Off 01111 = TC0_WO1 10000 = TC1_WO1 10001 = TC2_WO1 10010 = TC3_WO1 10011 = TC4_WO1 10100 = TC5_WO1 10101 = TC6_WO1 10110 = TC7_WO1 10111 = QSPI_CS 11000 = QSPI_DATA0 11001 = QSPI_DATA3 11010 = QSPI_DATA2 11011 = CCL_OUT1 11100 = Reserved 11101 = Reserved 11110 = Reserved 11111 = Reserved Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 47 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-10. Remappable Output Pin Configuration - Group3 RPn Port Pin RPnG3R SFR RPnG3R bits RPnG3R Value to Peripheral Pin Selection RPA0*

RPA1*

RPA3 RPA4 RPA5 RPA8 RPA9 RPA0G3R RPA1G3R RPA3G3R RPA0G3R [4:0]

00000 = Off RPA1G3R[4.0]

00001 = Off RPA3G3R[4.0]

00010 = SERCOM0_PAD0 RPA4G3R RPA4G3R[4.0]

00011 = SERCOM0_PAD3 RPA5G3R RPA5G3R[4.0]

00100 = SERCOM1_PAD2 RPA8G3R RPA8G3R[4.0]

00101 = Off RPA9G3R RPA9G3R[4.0]

00110 = SERCOM1_PAD3 RPA13*

RPA13G3R RPA13G3R[4.0]

RPB1*

RPB2*

RPB6 RPB9 RPB10*

RPB13*

RPB1G3R RPB1G3R[4.0]

RPB2G3R RPB2G3R[4.0]

RPB6G3R RPB6G3R[4.0]

RPB9G3R RPB9G3R[4.0]

RPB10G3R RPB10G3R[4.0]

RPB13G3R RPB13G3R[4.0]

00111 = TCC0_WO2 01000 = TCC0_WO0 01001 = TCC0_WO4 01010 = TCC1_WO2 01011 = TCC1_WO0 01100 = TCC1_WO4 01101 = TCC2_WO0 01110 = Off 01111 = TC0_WO0 10000 = TC1_WO0 10001 = TC2_WO0 10010 = TC3_WO0 10011 = TC4_WO0 10100 = TC5_WO0 10101 = TC6_WO0 10110 = TC7_WO0 10111 = QSPI_CS 11000 = QSPI_DATA1 11001 = QSPI_DATA0 11010 = QSPI_DATA3 11011 = CCL_OUT0 11100 = Reserved 11101 = Reserved 11110 = Reserved 11111 = Reserved Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 48 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-11. Remappable Output Pin Configuration Group4 RPn Port Pin RPnG4R SFR RPnG4R bits RPnG4R Value to Peripheral Pin Selection RPA1*

RPA2*

RPA4 RPA5 RPA6 RPA8 RPA9 RPA10 RPA13*

RPA14*

RPB2*

RPB3*

RPB7 RPB10*

RPB11*

RPA1G4R RPA2G4R RPA4G4R RPA1G4R[4:0]

00000 = Off RPA2G4R[4.0]

00001 = SERCOM0_PAD2 RPA4G4R[4.0]

00010 = Off RPA5G4R RPA5G4R[4.0]

00011 = SERCOM0_PAD0 RPA6G4R RPA6G4R[4.0]

00100 = SERCOM1_PAD3 RPA8G4R RPA8G4R[4.0]

00101 = Off RPA9G4R RPA9G4R[4.0]

00110 = SERCOM1_PAD0 RPA10G4R RPA10G4R[4.0]

RPA13G4R RPA13G4R[4.0]

RPA14G4R RPA14G4R[4.0]

RPB2G4R RPB2G4R[4.0]

RPB3G4R RPB3G4R[4.0]

RPB7G4R RPB7G4R[4.0]

RPB10G4R RPB10G4R[4.0]

RPB11G4R RPB11G4R[4.0]

00111 = TCC0_WO3 01000 = TCC0_WO1 01001 = TCC0_WO5 01010 = TCC1_WO3 01011 = TCC1_WO1 01100 = TCC1_WO5 01101 = TCC2_WO1 01110 = Off 01111 = TC0_WO0 10000 = TC1_WO1 10001 = TC2_WO1 10010 = TC3_WO1 10011 = TC4_WO1 10100 = TC5_WO1 10101 = TC6_WO1 10110 = TC7_WO1 10111 = QSPI_CS 11000 = QSPI_DATA2 11001 = QSPI_DATA1 11010 = QSPI_DATA0 11011 = CCL_OUT1 11100 = Reserved 11101 = Reserved 11110 = Reserved 11111 = Reserved Note:* denotes that these pins and its associated registers are not available in the 32-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 49 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.6 Peripheral Multiplexing Many pins also support one or more peripheral modules. When configured to operate with a peripheral, a pin may not be used for general input or output. In many cases, a pin must still be configured for input or output, although some peripherals override the TRISx configuration. Typical Multiplexed Port Structure Block Diagram (see Related Links) shows how ports are shared with other peripherals, and the associated I/O pin to which they are connected. Multiple peripheral functions may be multiplexed on each I/O pin. The priority of the peripheral function depends on the order of the pin descriptions in Function Priority for Device Pins (see Related Links). Note:The output of a pin can be controlled by the TRISx register bit or, in some cases, by the peripheral itself. Related Links 5.3. Block Diagram 5.7. Function Priority for Device Pins 5.6.1 Multiplexed Digital Input Peripheral The following conditions are characteristics of a multiplexed digital input peripheral:

Peripheral does not control the TRISx register. Some peripherals require the pin be configured as an input by setting the corresponding TRISx bit = 1. Peripheral input path is independent of I/O input path and uses an input buffer that is dependent on the peripheral. PORTx register data input path is not affected and can read the pin value. 5.6.2 Multiplexed Digital Output Peripheral The following conditions are characteristics of a multiplexed digital output peripheral:

Peripheral controls the output data. Some peripherals require the pin be configured as an output by setting the corresponding TRISx bit = 0. If a peripheral pin has an automatic tri-state feature, the peripheral can tri-state the pin. Pin output driver type can be affected by peripheral (example: drive strength, slew rate, and so on.). PORTx register output data has no effect. 5.6.3 Multiplexing Digital Bidirectional Peripheral The following conditions are characteristics of a multiplexed digital bidirectional peripheral:

Peripheral automatically configures the pin as an output, but not as an input. Some peripherals require the pin be configured as an input by setting the corresponding TRISx bit = 1. Peripherals control output data. Pin output driver type can be affected by peripheral (example: drive strength, slew rate, and so on.). PORTx register data input path is not affected and can read the pin value. PORTx register output data has no effect. 5.6.4 Multiplexing Analog Input Peripheral The following condition is characteristic of a multiplexed analog input peripheral:

All digital port input buffers are disabled PORTx registers read 0 to prevent crowbar current. 5.6.5 Multiplexing Analog Output Peripheral The following conditions are characteristic of a multiplexed analog output peripheral:

All digital port input buffers are disabled. PORTx registers read 0 to prevent crowbar current. Analog output is driven onto the pin, independent of the associated TRISx setting. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 50 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.7 Function Priority for Device Pins The device pins have an associated priority order in which functionality is exhibited on each pin. This priority order impacts the availability of PPS functionality. For example, if SERCOM0 is enabled with outputs chosen to be High Speed mode in the DEVCFG1 fuses (bit 17), pins PB9, PA4, PA5, and PA6 are given priority to be used as SERCOM0 pins instead of GPIO/PPS pins. See the following tables for the priority in which functions are brought out on each device pin. Top entry is higher priority and bottom entry is lower priority for each specific pin. Table 5-12. Priority for Device Pins PAn (n = 0-14) Pin Name Function In Priority Order Reference Peripheral pa0*

QSPI_DATA0 pa1*

RTC_IN3 RPA0 IOCA0 RA0 QSPI_SCK RTC_IN2 RPA1 IOCA1 RA1 pa2*

QSPI_DATA3 pa3 RTC_IN1 RPA2 IOCA2 RA2 TRD2 SCLKI DACOUT ANN0 RTC_IN0 RPA3 IOCA3 RA3 QSPI RTCC PPS Change notification GPIO QSPI RTCC PPS Change notification GPIO QSPI RTCC PPS Change notification GPIO Trace (Debug) Secondary Oscillator DAC ADC (Differential) RTCC PPS Change notification GPIO 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 51 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Pin Name Function In Priority Order Reference Peripheral pa4 SERCOM0_PAD3 SERCOM0 RTC_OUT RPA4 IOCA4 RA4 pa5 SERCOM0_PAD0 RTCC PPS Change Notification GPIO SERCOM0 AC_CMP0 Analog comparator pa6 RPA5 IOCA5 RA5 TRD3 SERCOM0_PAD1 AC_CMP1_ALT RPA6 IOCA6 RA6 pa7 TRACECLK SERCOM1_PAD0 RPA7 IOCA7 RA7 pa8 SERCOM1_PAD1 RPA8 IOCA8 RA8 pa9 SERCOM1_PAD2 RTC_IN0_ALT RPA9 IOCA9 RA9 PPS Change notification GPIO Trace (Debug) SERCOM0 Analog comparator PPS Change notification GPIO Trace (Debug) SERCOM1 PPS Change notification GPIO SERCOM1 PPS Change notification GPIO SERCOM1 RTCC PPS Change notification GPIO 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 52 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Pin Name Function In Priority Order Reference Peripheral pa10 SERCOM1_PAD3 SERCOM1 RTC_OUT_ALT RPA10 IOCA10 RA10 SOSCI RPA11 RA11 SOSCO RPA12 RA12 pa11 pa12 RTCC PPS Change notification GPIO Secondary oscillator PPS (Re-mappable input only) GPIO (input only) Secondary oscillator PPS (Re-mappable input only) GPIO (input only) pa13*

SERCOM2_PAD0 SERCOM2 (I2C only) AC_CMP1 RPA13 IOCA13 RA13 Analog comparator PPS Change notification GPIO pa14*

SERCOM2_PAD1 SERCOM2 (I2C) RPA14 IOCA14 RA14 PPS Change notification GPIO Note:

1.

* indicates pins are not available on the 32-pin package, and available only on the 48-pin package. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 53 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Table 5-13. Priority for Device Pins PBn (n = 0-13) Pin Name Function In Priority Order Reference Peripheral pb0*

pb1*

pb2*

AN4 CVD4 CVDR4 CVDT4 AC_AIN2 RPB0 IOCB0 RB0 AN5 CVD5 CVDR5 CVDT5 ADC CVD CVD CVD Analog comparator PPS Change notification GPIO ADC CVD CVD CVD AC_AIN3 Analog comparator RPB1 IOCB1 RB1 AN6 CVD6 CVDR6 CVDT6 AC_AIN0 RPB2 IOCB2 RB2 PPS Change notification GPIO ADC CVD CVD CVD Analog comparator PPS Change notification GPIO 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 54 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Pin Name Function In Priority Order Reference Peripheral pb3*

pb4 pb5 pb6 AN7 CVD7 CVDR7 CVDT7 AC_AIN1 RPB3 IOCB3 RB3 AN0 CVD0 CVDR0 CVDT0 RPB4 IOCB4 RB4 TRD0 AN1 CVD1 CVDR1 CVDT1 RPB5 IOCB5 RB5 TRD1 AN2 CVD2 CVDR2 CVDT2 RPB6 IOCB6 RB6 ADC CVD CVD CVD Analog comparator PPS Change notification GPIO ADC CVD CVD CVD PPS Change notification GPIO Trace (Debug) ADC CVD CVD CVD PPS Change notification GPIO Trace (Debug) ADC CVD CVD CVD PPS Change notification GPIO 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 55 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Pin Name Function In Priority Order Reference Peripheral pb7 pb8 SWO AN3 CVD3 CVDR3 CVDT3 LVDIN RPB7 IOCB7 RB7 SWCLK RPB8 IOCB8 RB8 pb9 CM4_SWDIO SERCOM0_PAD2 RPB9 INT0 IOCB9 RB9 RPB10 IOCB10 RB10 pb10*

pb11*

QSPI_DATA2 RPB11 IOCB11 RB11 pb12*

QSPI_DATA1 RPB12 IOCB12 RB12 Debug ADC CVD CVD CVD LVD Voltage reference PPS Change notification GPIO Debug PPS Change notification GPIO Debug SERCOM0 PPS Wake-up Interrupt Change notification GPIO PPS Change notification GPIO QSPI PPS Change notification GPIO QSPI PPS Change notification GPIO 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 56 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Pin Name Function In Priority Order Reference Peripheral pb13*

QSPI_CS RTC_EVENT RPB13 IOCB13 RB13 QSPI RTCC PPS Change notification GPIO Note:

1.

* indicates that pins are not available on the 32-pin package. 5.8 Operation in Power Saving Modes 5.8.1 I/O Port Operation in Sleep Mode As the device enters the Sleep mode, the system clock is disabled; however, the CN module continues to operate. If one of the enabled CN pins changes state, the corresponding interrupt flag is set in NVIC and device wakes from the Sleep (or Idle) mode and executes the CN Interrupt Service Routine. 5.8.2 I/O Port Operation in Idle Mode As the device enters the Idle mode, the system clock sources remain functional. The SIDL bit (CNCONx[13]) selects whether the module will stop or continues to function in the Idle mode. If SIDL = 1, the module continues to sample Input CN I/O pins in the Idle mode; however, synchronization is disabled. If SIDL = 0, the module continues to synchronize and samples input CN I/O pins in the Idle mode. 5.9 Results of Various Resets Table 5-14. Results of Resets Available Reset Name Device Reset Description All I/O registers are forced to their reset states upon a device Reset. Power-on Reset (PoR) All I/O registers are forced to their reset states upon a Power-on Reset (POR). Watchdog Reset All I/O registers are unchanged upon a Watchdog Reset. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 57 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.10 Port Register Summary See PORT A module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 ANSA3 2 1 0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x00 ANSELA 0x04

... 0x0F Reserved 0x10 TRISA 0x14

... 0x1F Reserved 0x20 PORTA 0x24

... 0x2F Reserved 0x30 LATA 0x34

... 0x3F Reserved 0x40 ODCA 0x44

... 0x4F Reserved 0x50 CNPUA 0x54

... 0x5F Reserved 0x60 CNPDA 0x64

... 0x6F Reserved TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx TRISAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx RAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx LATAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx ODCAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPUAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx CNPDAx 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 58 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 ON FRZ SIDL EDGEDETEC T CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNENAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNSTATAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNNEAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx CNFAx SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR0x SR1x SR1x SR1x SR1x SR1x SR1x SR1x SR1x SR1x SR1x SR1x SR1x ANSBx ANSBx ANSBx ANSBx ANSBx ANSBx ANSBx ANSBx 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x70 CNCONA 0x74

... 0x7F Reserved 0x80 CNENA 0x84

... 0x8F Reserved 0x90 CNSTATA 0x94

... 0x9F Reserved 0xA0 CNNEA 0xA4

... 0xAF Reserved 0xB0 CNFA 0xB4

... 0xBF Reserved 0xC0 SRCON0A 0xC4

... 0xCF Reserved 0xD0 SRCON1A 0xD4

... 0xFF Reserved 0x0100 ANSELB 0x0104

... 0x010F Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 59 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx TRISBx RBx RBx RBx RBx RBx RBx RBx RBx RBx RBx RBx RBx RBx RBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx LATBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx ODCBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPUBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx CNPDBx ON FRZ SIDL EDGEDETEC T CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx CNENBx 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x0110 TRISB 0x0114

... 0x011F Reserved 0x0120 PORTB 0x0124

... 0x012F Reserved 0x0130 LATB 0x0134

... 0x013F Reserved 0x0140 ODCB 0x0144

... 0x014F Reserved 0x0150 CNPUB 0x0154

... 0x015F Reserved 0x0160 CNPDB 0x0164

... 0x016F Reserved 0x0170 CNCONB 0x0174

... 0x017F Reserved 0x0180 CNENB 0x0184

... 0x018F Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 60 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0190 CNSTATB 0x0194

... 0x019F Reserved 0x01A0 CNNEB 0x01A4

... 0x01AF Reserved 0x01B0 CNFB 0x01B4

... 0x01BF Reserved 0x01C0 SRCON0B 0x01C4

... 0x01CF Reserved 0x01D0 SRCON1B 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNSTATBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNNEBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx CNFBx SR0x SR0x SR0x SR0x SR1x SR1x SR1x SR1x Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 5.11 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 61 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.1 Analog Select Register for PortA Name:

Offset:

Reset:

Property:

ANSELA 0x00 0x8

The ANSELA register controls the operation of the analog portA pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset 2 3 ANSA3 R/W 1 Bit 3 ANSA3Analog Select for PA3 Configures the PA3 as an analog input when this bit is set to 1. 9 1 8 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 62 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.2 Tri-state Functions for PortA Name:

Offset:

Reset:

Property:

TRISA 0x10 0x0

The TRISA register configures the data direction flow through port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 TRISAx R/W 0 14 TRISAx R/W 0 6 TRISAx R/W 0 13 TRISAx R/W 0 5 TRISAx R/W 0 12 TRISAx R/W 0 4 TRISAx R/W 0 11 TRISAx R/W 0 3 TRISAx R/W 0 10 TRISAx R/W 0 2 TRISAx R/W 0 9 TRISAx R/W 0 1 TRISAx R/W 0 8 TRISAx R/W 0 0 TRISAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14 TRISAx(x = 0 to 14; x = 0 for bit0 mapped to PA0, x = 14 for bit14 mapped to PA14) Tri-state pins for PortA The tri-state data direction bit configures the selected I/O pin of Port A as an input or output. Value 1 0 Description Configures the I/O as input Configures the I/O as output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 63 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.3 Port Pin Data for PortA Name:

Offset:

Reset:

Property:

PORTA 0x20 0x0

A write to a PORTA register writes to the corresponding LATA register (PORTA data latch). Those I/O port pin(s) configured as outputs are updated. A write to a PORTA register is effectively the same as a write to a LATA register. A read from a PORTA register reads the synchronized signal applied to the port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 RAx R/W 0 14 RAx R/W 0 6 RAx R/W 0 13 RAx R/W 0 5 RAx R/W 0 12 RAx R/W 0 4 RAx R/W 0 11 RAx R/W 0 3 RAx R/W 0 10 RAx R/W 0 2 RAx R/W 0 9 RAx R/W 0 1 RAx R/W 0 8 RAx R/W 0 0 RAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14 RAx(x = 0 to 14; x = 0 for bit0 mapped to PA0, x = 14 for bit14 mapped to PA14) Port pin configuration for PortA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 64 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.4 Latch Functions for PortA Name:

Offset:

Reset:

Property:

LATA 0x30 0x0

The LATA register (PORTA data latch) holds data written to port I/O pins. A write to a LATA register latches data to corresponding port I/O pins. Those I/O port pins configured as outputs are updated. A read from a LATA register reads the data held in the PORTA data latch, not from the port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 LATAx R/W 0 14 LATAx R/W 0 6 LATAx R/W 0 13 LATAx R/W 0 5 LATAx R/W 0 12 LATAx R/W 0 4 LATAx R/W 0 11 LATAx R/W 0 3 LATAx R/W 0 10 LATAx R/W 0 2 LATAx R/W 0 9 LATAx R/W 0 1 LATAx R/W 0 8 LATAx R/W 0 0 LATAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14 LATAx(x = 0 to 14; x = 0 for bit0 mapped to PA0, x = 14 for bit14 mapped to PA14) Latch configuration for PortA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 65 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.5 Open-Drain Configuration for PortA Name:

Offset:

Reset:

Property:

ODCA 0x40 0x0

This register configures each I/O pin individually for either normal digital output or open-drain output, associated with each I/O pin. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 ODCAx R/W 0 14 ODCAx R/W 0 6 ODCAx R/W 0 13 ODCAx R/W 0 5 ODCAx R/W 0 12 11 4 ODCAx R/W 0 3 ODCAx R/W 0 10 ODCAx R/W 0 2 ODCAx R/W 0 9 ODCAx R/W 0 1 ODCAx R/W 0 8 ODCAx R/W 0 0 ODCAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 ODCAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Open-Drain Configuration for PortA Note:After a Reset, the status of all the bits of the ODCA register is set to 0. Value 1 0 Description Configures an I/O pin as an open-drain output. Configures an I/O pin as an normal digital output. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 66 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.6 Change Notice Pull-up for PortA Name:

Offset:

Reset:

Property:

CNPUA 0x50 0x0

This register enables the weak internal pull-ups connected with an I/O pin when any of the control bits is set. Note:This register must always be disabled when the port pin is configured as a digital output. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 CNPUAx R/W 0 14 CNPUAx R/W 0 6 CNPUAx R/W 0 13 CNPUAx R/W 0 5 CNPUAx R/W 0 12 11 4 CNPUAx R/W 0 3 CNPUAx R/W 0 10 CNPUAx R/W 0 2 CNPUAx R/W 0 9 CNPUAx R/W 0 1 CNPUAx R/W 0 8 CNPUAx R/W 0 0 CNPUAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNPUAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Pull-up configuration for PortA Value 1 0 Description Enables the weak pull-up associated with an I/O pin. Disables the weak pull-up associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 67 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.7 Change Notice Pull-down for PortA Name:

Offset:

Reset:

Property:

CNPDA 0x60 0x0

This register enables the weak pull-down connected with an I/O pin when any of the control bits is set. Note:This register must always be disabled when the port pin is configured as a digital output. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 CNPDAx R/W 0 14 CNPDAx R/W 0 6 CNPDAx R/W 0 13 CNPDAx R/W 0 5 CNPDAx R/W 0 12 11 4 CNPDAx R/W 0 3 CNPDAx R/W 0 10 CNPDAx R/W 0 2 CNPDAx R/W 0 9 CNPDAx R/W 0 1 CNPDAx R/W 0 8 CNPDAx R/W 0 0 CNPDAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNPDAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Pull-down configuration for PortA Value 1 0 Description Enables the weak pull-down associated with an I/O pin. Disables the weak pull-down associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 68 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.8 Change Notice Control for PortA Name:

Offset:

Reset:

Property:

CNCONA 0x70 0x0

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset 15 ON R/W 0 Bit 7 Access Reset 14 FRZ R/W 0 6 13 SIDL R/W 0 5 12 10 11 EDGEDETECT R/W 0 4 3 2 9 1 8 0 Bit 15 ONChange Notice (CN) Control ON bit 1 = Change Notice is enabled 0 = Change Notice is disabled Bit 14 FRZFreeze in the Debug mode bit 1 = Freezes the module operation when in the Debug mode 0 = Continues the module operation when in the Debug mode Bit 13 SIDLStop in the Idle mode bit 1 = Discontinues the module operation when device enters the Idle mode 0 = Continues the module operation even in the Idle mode Bit 11 EDGEDETECTChange Notification Style bit 1 = Edge Style. Detects edge transitions. This is associated with CNENA (positive edge)/ CNNEA (negative edge)/

CNFA. 0 = Mismatch Style. Detects change from last PortA read. This is associated with CNENA/CNSTATA. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 69 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.9 Change Notice Enable for PortA Name:

Offset:

Reset:

Property:

CNENA 0x80 0x0

This register contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. When EDGEDETECT is set, CNENA controls the positive edge. CNENA enables a mismatch CN interrupt condition when EDGEDETECT is not set. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 CNENAx R/W 0 14 CNENAx R/W 0 6 CNENAx R/W 0 13 CNENAx R/W 0 5 CNENAx R/W 0 12 11 4 CNENAx R/W 0 3 CNENAx R/W 0 10 CNENAx R/W 0 2 CNENAx R/W 0 9 CNENAx R/W 0 1 CNENAx R/W 0 8 CNENAx R/W 0 0 CNENAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNENAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Enable for PortA Value 1 0 Description Enables a mismatch/positive edge CN interrupt condition associated with an I/O pin. Disables a mismatch/positive edge CN interrupt condition associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 70 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.10 Change Notice Status for PortA Name:

Offset:

Reset:

Property:

CNSTATA 0x90 0x0

This register indicates whether a change occurred on the corresponding pin since the last read of the PortA bit. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit 7 CNSTATAx Access Reset R 0 14 CNSTATAx R 0 6 CNSTATAx R 0 13 CNSTATAx R 0 5 CNSTATAx R 0 12 11 4 CNSTATAx R 0 3 CNSTATAx R 0 10 CNSTATAx R 0 2 CNSTATAx R 0 9 CNSTATAx R 0 1 CNSTATAx R 0 8 CNSTATAx R 0 0 CNSTATAx R 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNSTATAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Status for PortA 1 indicates change occurred in an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 71 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.11 Change Notice Enable for PortA Name:

Offset:

Reset:

Property:

CNNEA 0xA0 0x0

This register contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. When EDGEDETECT is set, CNNEA controls the negative edge. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 CNNEAx R/W 0 14 CNNEAx R/W 0 6 CNNEAx R/W 0 13 CNNEAx R/W 0 5 CNNEAx R/W 0 12 11 4 CNNEAx R/W 0 3 CNNEAx R/W 0 10 CNNEAx R/W 0 2 CNNEAx R/W 0 9 CNNEAx R/W 0 1 CNNEAx R/W 0 8 CNNEAx R/W 0 0 CNNEAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNNEAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Enable for PortA Value 1 0 Description Enables a negative edge CN interrupt condition associated with an I/O pin. Disables a negative edge CN interrupt condition associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 72 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.12 Change Notice Flag for PortA Name:

Offset:

Reset:

Property:

CNFA 0xB0 0x0

This register indicates edge-detect style change occurred on the corresponding pin since the last read of the PortA bit. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 CNFAx R/W 0 14 CNFAx R/W 0 6 CNFAx R/W 0 13 CNFAx R/W 0 5 CNFAx R/W 0 12 11 4 CNFAx R/W 0 3 CNFAx R/W 0 10 CNFAx R/W 0 2 CNFAx R/W 0 9 CNFAx R/W 0 1 CNFAx R/W 0 8 CNFAx R/W 0 0 CNFAx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,13,14 CNFAx(x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14; x=0 for bit0 mapped to PA0, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Change Notice Flag for PortA When CNCONAx = 1 CNFAx stores the occurrence of the CN event until cleared by the software. When CNCONAx = 0 CNFAx Reads 0. Description Value An Enabled Edge Event occurred on pin PORTAx 1 An Enabled Edge Event did not occur on pin PORTAx 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 73 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.13 Slew Rate Control 0 for PortA Name:

Offset:

Reset:

Property:

SRCON0A 0xC0 0x0

This register configures the slew rate control bits associated with Port A. Note:To configure the slew rate, user must also configure the SRCON1A register associated with Port A. See Slew Rate Control Bit Settings table in the Slew Rate Control from Related Links. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 SR0x R/W 0 14 SR0x R/W 0 6 SR0x R/W 0 13 SR0x R/W 0 5 SR0x R/W 0 12 11 3 4 SR0x R/W 0 10 SR0x R/W 0 2 SR0x R/W 0 9 SR0x R/W 0 1 SR0x R/W 0 8 SR0x R/W 0 0 SR0x R/W 0 Bits 0,1,2,4,5,6,7,8,9,10,13,14 SR0x(x = 0, 1, 2, 4, 5, 6, 7, 8, 9, 10; x=0 for bit0 mapped to PA0, x=2 for bit 2, x=4 for bit4, x=10 for bit 10, x=13 for bit13, x=14 for bit 14 mapped to PA14) Slew Rate Control 0 for PortA. Related Links 5.4.1.8. Slew Rate Control 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 74 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.14 Slew Rate Control 1 for PortA Name:

Offset:

Reset:

Property:

SRCON1A 0xD0 0x0

This register configures the slew rate control bits associated with Port A. Note:To configure the slew rate, user must also configure the SRCON0A register associated with Port A. See Slew Rate Control Bit Settings table in the Slew Rate Control from Related Links. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 SR1x R/W 0 14 SR1x R/W 0 6 SR1x R/W 0 13 SR1x R/W 0 5 SR1x R/W 0 12 11 3 4 SR1x R/W 0 10 SR1x R/W 0 2 SR1x R/W 0 9 SR1x R/W 0 1 SR1x R/W 0 8 SR1x R/W 0 0 SR1x R/W 0 Bits 0,1,2,4,5,6,7,8,9,10,13,14 SR1x(x = 0, 1, 2, 4, 5, 6, 7, 8, 9, 10; x=0 for bit0, x=2 for bit 2, x=4 for bit4, x=10 for bit10, x=13 for bit13, x=14 for bit14) Slew Rate Control 1 for PortA Related Links 5.4.1.8. Slew Rate Control 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 75 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.15 Analog Select Register for PortB Name:

Offset:

Reset:

Property:

ANSELB 0x100 0x8

The ANSELB register controls the operation of the analog PortB pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset 7 ANSBx R/W 0 6 ANSBx R/W 0 5 ANSBx R/W 0 4 ANSBx R/W 0 3 ANSBx R/W 0 2 ANSBx R/W 0 1 ANSBx R/W 0 0 ANSBx R/W 1 Bits 0,1,2,3,4,5,6,7 ANSBx(x = 0 to 7; x = 0 for bit0, x = 7 for bit7) Analog Select for PB Configures the PB as an analog input when this bit is set to 1. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 76 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.16 Tri-state Functions for PortB Name:

Offset:

Reset:

Property:

TRISB 0x110 0x0

The TRISB register configures the data direction flow through port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 TRISBx R/W 0 6 TRISBx R/W 0 13 TRISBx R/W 0 5 TRISBx R/W 0 12 TRISBx R/W 0 4 TRISBx R/W 0 11 TRISBx R/W 0 3 TRISBx R/W 0 10 TRISBx R/W 0 2 TRISBx R/W 0 9 TRISBx R/W 0 1 TRISBx R/W 0 8 TRISBx R/W 0 0 TRISBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 TRISBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Tri-state pins for PortB The tri-state data direction bit configures the selected I/O pin of Port B as an input or output. Value 1 0 Description Configures the I/O as input Configures the I/O as output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 77 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.17 Port Pin Data for PortB Name:

Offset:

Reset:

Property:

PORTB 0x120 0x0

A write to a PORTB register writes to the corresponding LATB register (PORTB data latch). Those I/O port pin(s) configured as outputs are updated. A write to a PORTB register is effectively the same as a write to a LATB register. A read from a PORTB register reads the synchronized signal applied to the port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 RBx R/W 0 6 RBx R/W 0 13 RBx R/W 0 5 RBx R/W 0 12 RBx R/W 0 4 RBx R/W 0 11 RBx R/W 0 3 RBx R/W 0 10 RBx R/W 0 2 RBx R/W 0 9 RBx R/W 0 1 RBx R/W 0 8 RBx R/W 0 0 RBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 RBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) PortB configuration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 78 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.18 Latch Functions for PortB Name:

Offset:

Reset:

Property:

LATB 0x130 0x0

The LATB register (PORTB data latch) holds data written to port I/O pins. A write to a LATB register latches data to corresponding port I/O pins. Those I/O port pins configured as outputs are updated. A read from a LATB register reads the data held in the PORTB data latch, not from the port I/O pins. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 LATBx R/W 0 6 LATBx R/W 0 13 LATBx R/W 0 5 LATBx R/W 0 12 LATBx R/W 0 4 LATBx R/W 0 11 LATBx R/W 0 3 LATBx R/W 0 10 LATBx R/W 0 2 LATBx R/W 0 9 LATBx R/W 0 1 LATBx R/W 0 8 LATBx R/W 0 0 LATBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 LATBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Latch configuration for PortB 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 79 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.19 Open-Drain Configuration for PortB Name:

Offset:

Reset:

Property:

ODCB 0x140 0x0

This register configures each I/O pin individually for either normal digital output or open-drain output, associated with each I/O pin. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 ODCBx R/W 0 6 ODCBx R/W 0 13 ODCBx R/W 0 5 ODCBx R/W 0 12 ODCBx R/W 0 4 ODCBx R/W 0 11 ODCBx R/W 0 3 ODCBx R/W 0 10 ODCBx R/W 0 2 ODCBx R/W 0 9 ODCBx R/W 0 1 ODCBx R/W 0 8 ODCBx R/W 0 0 ODCBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 ODCBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Open-Drain Configuration for PortB Note:After a Reset, the status of all the bits of the ODCB register is set to 0. Value 1 0 Description Configures an I/O pin as an open-drain output. Configures an I/O pin as an normal digital output. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 80 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.20 Change Notice Pull-up for PortB Name:

Offset:

Reset:

Property:

CNPUB 0x150 0x0

This register enables the weak internal pull-ups connected with an I/O pin when any of the control bits is set. Note:This register must always be disabled when the port pin is configured as a digital output. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 CNPUBx R/W 0 6 CNPUBx R/W 0 13 CNPUBx R/W 0 5 CNPUBx R/W 0 12 CNPUBx R/W 0 4 CNPUBx R/W 0 11 CNPUBx R/W 0 3 CNPUBx R/W 0 10 CNPUBx R/W 0 2 CNPUBx R/W 0 9 CNPUBx R/W 0 1 CNPUBx R/W 0 8 CNPUBx R/W 0 0 CNPUBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNPUBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Pull-up configuration for PortB Value 1 0 Description Enables the weak pull-up associated with an I/O pin. Disables the weak pull-up associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 81 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.21 Change Notice Pull-down for PortB Name:

Offset:

Reset:

Property:

CNPDB 0x160 0x0

This register enables the weak pull-down connected with an I/O pin when any of the control bits is set. Note:This register must always be disabled when the port pin is configured as a digital output. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 CNPDBx R/W 0 6 CNPDBx R/W 0 13 CNPDBx R/W 0 5 CNPDBx R/W 0 12 CNPDBx R/W 0 4 CNPDBx R/W 0 11 CNPDBx R/W 0 3 CNPDBx R/W 0 10 CNPDBx R/W 0 2 CNPDBx R/W 0 9 CNPDBx R/W 0 1 CNPDBx R/W 0 8 CNPDBx R/W 0 0 CNPDBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNPDBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Pull-down configuration for PortB Value 1 0 Description Enables the weak pull-down associated with an I/O pin. Disables the weak pull-down associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 82 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.22 Change Notice Control for PortB Name:

Offset:

Reset:

Property:

CNCONB 0x170 0x0

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset 15 ON R/W 0 Bit 7 Access Reset 14 FRZ R/W 0 6 13 SIDL R/W 0 5 12 10 11 EDGEDETECT R/W 0 4 3 2 9 1 8 0 Bit 15 ONChange Notice (CN) Control ON bit 1 = Change Notice is enabled 0 = Change Notice is disabled Bit 14 FRZFreeze in the Debug mode bit 1 = Freezes the module operation when the emulator is in the Debug mode 0 = Continues the module operation when the emulator is in the Debug mode Bit 13 SIDLStop in the Idle mode bit 1 = Discontinues the module operation when in the Idle mode 0 = Continues the module operation when in the Idle mode Bit 11 EDGEDETECTChange Notification Style bit 1 = Edge Style. Detects edge transitions. This is associated with CNENB (positive edge)/ CNNEB (negative edge)/

CNFA. 0 = Mismatch Style. Detects change from last PortA read. This is associated with CNENB/CNSTATB. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 83 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.23 Change Notice Enable for PortB Name:

Offset:

Reset:

Property:

CNENB 0x180 0x0

This register contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. When EDGEDETECT is set, CNENB controls the positive edge. CNENB enables a mismatch CN interrupt condition when EDGEDETECT is not set Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 CNENBx R/W 0 6 CNENBx R/W 0 13 CNENBx R/W 0 5 CNENBx R/W 0 12 CNENBx R/W 0 4 CNENBx R/W 0 11 CNENBx R/W 0 3 CNENBx R/W 0 10 CNENBx R/W 0 2 CNENBx R/W 0 9 CNENBx R/W 0 1 CNENBx R/W 0 8 CNENBx R/W 0 0 CNENBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNENBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Enable for PortB Value 1 0 Description Enables a mismatch/positive edge CN interrupt condition associated with an I/O pin. Disables a mismatch/positive edge CN interrupt condition associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 84 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.24 Change Notice Status for PortB Name:

Offset:

Reset:

Property:

CNSTATB 0x190 0x0

This register indicates whether a change occurred on the corresponding pin since the last read of the PortB bit. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit 7 CNSTATBx Access Reset R 0 6 CNSTATBx R 0 13 CNSTATBx R 0 5 CNSTATBx R 0 12 CNSTATBx R 0 4 CNSTATBx R 0 11 CNSTATBx R 0 3 CNSTATBx R 0 10 CNSTATBx R 0 2 CNSTATBx R 0 9 CNSTATBx R 0 1 CNSTATBx R 0 8 CNSTATBx R 0 0 CNSTATBx R 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNSTATBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Status for PortB 1 indicates change occurred in an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 85 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.25 Change Notice Enable for PortB Name:

Offset:

Reset:

Property:

CNNEB 0x1A0 0x0

This register contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. When EDGEDETECT is set, CNNEB controls the negative edge. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 CNNEBx R/W 0 6 CNNEBx R/W 0 13 CNNEBx R/W 0 5 CNNEBx R/W 0 12 CNNEBx R/W 0 4 CNNEBx R/W 0 11 CNNEBx R/W 0 3 CNNEBx R/W 0 10 CNNEBx R/W 0 2 CNNEBx R/W 0 9 CNNEBx R/W 0 1 CNNEBx R/W 0 8 CNNEBx R/W 0 0 CNNEBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNNEBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Enable for PortB Value 1 0 Description Enables a mismatch/negative edge CN interrupt condition associated with an I/O pin. Disables a mismatch/negative edge CN interrupt condition associated with an I/O pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 86 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.26 Change Notice Flag for PortB Name:

Offset:

Reset:

Property:

CNFB 0x1B0 0x0

This register indicates the edge-detect style change occurred on the corresponding pin since the last read of the PortB bit. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 CNFBx R/W 0 6 CNFBx R/W 0 13 CNFBx R/W 0 5 CNFBx R/W 0 12 CNFBx R/W 0 4 CNFBx R/W 0 11 CNFBx R/W 0 3 CNFBx R/W 0 10 CNFBx R/W 0 2 CNFBx R/W 0 9 CNFBx R/W 0 1 CNFBx R/W 0 8 CNFBx R/W 0 0 CNFBx R/W 0 Bits 0,1,2,3,4,5,6,7,8,9,10,11,12,13 CNFBx(x = 0 to 13; x = 0 for bit0 mapped to PB0, x = 13 for bit13 mapped to PB13) Change Notice Flag for PortB When CNCONBx = 1 CNFBx stores the occurrence of the CN event until cleared by the software. When CNCONBx = 0 CNFBx Reads 0. Description Value An Enabled Edge Event occurred on pin PORTBx 1 An Enabled Edge Event did not occur on pin PORTBx 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 87 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.27 Slew Rate Control 0 for PortB Name:

Offset:

Reset:

Property:

SRCON0B 0x1C0 0x0

This register configures the slew rate control bits associated with PortB. Note:To configure the slew rate, user must also configure the SRCON1B register associated with PortB. See Slew Rate Control Bit Settings table in the Slew Rate Control from Related Links. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 13 SR0x R/W 0 5 12 SR0x R/W 0 4 11 SR0x R/W 0 3 10 SR0x R/W 0 2 9 1 8 0 Bits 10,11,12,13 SR0x(x = 10, 11, 12, 13; x = 10 for bit10 mapped to PB10, x = 13 for bit13 mapped to PB13) Slew Rate Control 0 for PortB Related Links 5.4.1.8. Slew Rate Control 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 88 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.11.28 Slew Rate Control 1 for PortB Name:

Offset:

Reset:

Property:

SRCON1B 0x1D0 0x0

This register configures the slew rate control bits associated with Port B. Note:To configure the slew rate, user must also configure the SRCON0A register associated with Port B. See Slew Rate Control Bit Settings table in the Slew Rate Control from Related Links. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 13 SR1x R/W 0 5 12 SR1x R/W 0 4 11 SR1x R/W 0 3 10 SR1x R/W 0 2 9 1 8 0 Bits 10,11,12,13 SR1x(x = 10, 11, 12, 13; x = 10 for bit10 mapped to PB10, x = 13 for bit13 mapped to PB13) Slew Rate Control 1 for PortB Related Links 5.4.1.8. Slew Rate Control 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 89 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.12 Peripheral Pin Select (PPS) Input Mapping Register Summary See PPS module in the Product Memory Mapping Overview from Related Links for base address. Table 5-15. Peripheral Pin Select Input Registers Name Bit Pos. Bits Offset 0x000 EXTINT0R 0x004 EXTINT1R 0x008 EXTINT2R 0x00C EXTINT3R 0x03C NMIR 0x040 SCOM0P0R 0x044 SCOM0P1R 0x048 SCOM0P2R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 EXTINT0R[3:0]

EXTINT1R[3:0]

EXTINT2R[3:0]

EXTINT3R[3:0]

NMIR[3:0]

SCOM0P0R[3:0]

SCOM0P1R[3:0]

SCOM0P2R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 90 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Name Bit Pos. Bits

...........continued Offset 0x04C SCOM0P3R 0x050 SCOM1P0R 0x054 SCOM1P1R 0x058 SCOM1P2R 0x05C SCOM1P3R 0x084 QD0R 0x088 QD1R 0x08C QD2R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 SCOM0P3R[3:0]

SCOM1P0R[3:0]

SCOM1P1R[3:0]

SCOM1P2R[3:0]

SCOM1P3R[3:0]

QD0R[3:0]

QD1R[3:0]

QD2R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 91 Microchip Confidential Confidential...........continued Offset 0x090 Name QD3R 0x094 REFIR 0x098 CCLIN0R 0x09C CCLIN1R 0x0A0 CCLIN2R 0x0A4 CCLIN3R 0x0A8 CCLIN4R 0x0AC CCLIN5R PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Bit Pos. Bits 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 QD3R[3:0]

REFIR[3:0]

CCLIN0R[3:0]

CCLIN1R[3:0]

CCLIN2R[3:0]

CCLIN3R[3:0]

CCLIN4R[3:0]

CCLIN5R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 92 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Name Bit Pos. Bits

...........continued Offset 0x0B0 TC0WO0G1R 0x0B4 TC0WO0G2R 0x0B8 TC0WO1G3R 0x0BC TC0WO1G4R 0x0C0 TC1WO0G1R 0x0C4 TC1WO1G2R 0x0C8 TC2WO0G1R 0x0CC TC2WO0G3R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 TC0WO0G1R[3:0]

TC0WO0G2R[3:0]

TC0WO1G3R[3:0]

TC0WO1G4R[3:0]

TC1WO0G1R[3:0]

TC1WO0G2R[3:0]

TC2WO0G1R[3:0]

TC2WO0G3R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 93 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Name Bit Pos. Bits

...........continued Offset 0x0D0 TC2WO1G2R 0x0D4 TC2WO1G4R 0x0D8 TC3WO0G1R 0x0DC TC3WO0G3R 0x0E0 TC3WO1G2R 0x0E4 TC3WO1G4R 0x0E8 TC4WO0G1R 0x0EC TC4WO0G3R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 TC2WO1G2R[3:0]

TC2WO1G4R[3:0]

TC3WO0G1R[3:0]

TC3WO0G3R[3:0]

TC3WO1G2R[3:0]

TC3WO1G4R[3:0]

TC4WO0G1R[3:0]

TC4WO0G3R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 94 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Name Bit Pos. Bits

...........continued Offset 0x0F0 TC4WO1G2R 0x0F4 TC4WO1G4R 0x0F8 TC5WO0G1R 0x0FC TC5WO0G3R 0x100 TC5WO1G2R 0x104 TC5WO1G4R 0x108 TC6WO0G1R 0x10C TC6WO0G3R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 TC4WO1G2R[3:0]

TC4WO1G4R[3:0]

TC5WO0G1R[3:0]

TC5WO0G3R[3:0]

TC5WO1G2R[3:0]

TC5WO1G4R[3:0]

TC6WO0G1R[3:0]

TC6WO0G3R[3:0]

0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 95 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) Name Bit Pos. Bits

...........continued Offset 0x110 TC6WO1G2R 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7 6 5 4 3 2 1 TC6WO1G2R[3:0]

TC6WO1G4R[3:0]

TC7WO0G1R[3:0]

TC7WO0G3R[3:0]

TC7WO1G2R[3:0]

TC7WO1G4R[3:0]

0 0x114 TC6WO1G4R 0x118 TC7WO0G1R 0x11C TC7WO0G3R 0x120 TC7WO1G2R 0x124 TC7WO1G4R Related Links 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 96 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.13 Peripheral Pin Select (PPS) Output Mapping Register Summary See PPS module in the Product Memory Mapping Overview from Related Links for base address. Table 5-16. Peripheral Pin Select Output Registers Offset 0x200 RPA0G2R*

Register Name Bit Pos. 0x204 RPA0G3R*

0x208 RPA1G3R*

0x20C RPA1G4R*

0x214 RPA2G4R*

0x218 RPA3G1R 0x21C RPA3G2R 0x220 RPA3G3R 7 6 5 Bits 4 3 2 1 0 RPA0G2R[4:0]

RPA0G3R[4:0]

RPA1G3R[4:0]

RPA1G4R[4:0]

RPA2G4R [4:0]

RPA3G1R[4:0]

RPA3G2R[4:0]

RPA3G3R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 97 Microchip Confidential Confidential...........continued Offset 0x224 Register Name Bit Pos. RPA4G2R 0x228 RPA4G3R 0x22C RPA4G4R 0x230 RPA5G1R 0x234 RPA5G3R 0x238 RPA5G4R 0x23C RPA6G1R 0x240 RPA6G2R PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPA4G2R[4:0]

RPA4G3R[4:0]

RPA4G4R[4:0]

RPA5G1R[4:0]

RPA5G3R[4:0]

RPA5G4R[4:0]

RPA6G1R[4:0]

RPA6G2R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 98 Microchip Confidential Confidential...........continued Offset 0x244 Register Name Bit Pos. RPA6G4R 0x248 RPA7G1R 0x24C RPA7G2R 0x250 RPA8G2R 0x254 RPA8G3R 0x258 RPA8G4R 0x260 RPA9G3R 0x264 RPA9G4R PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPA6G4R[4:0]

RPA7G1R[4:0]

RPA7G2R[4:0]

RPA8G2R[4:0]

RPA8G3R[4:0]

RPA8G4R[4:0]

RPA9G3R[4:0]

RPA9G4R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 99 Microchip Confidential Confidential...........continued Offset 0x26C Register Name Bit Pos. RPA10G4R 0x278 RPA13G3R*

0x27C RPA13G4R*

0x284 RPA14G4R*

0x290 RPB0G2R*

0x294 RPB1G2R*

0x298 RPB1G3R*

0x29C RPB2G3R*

PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPA10G4R[4:0]

RPA13G3R[4:0]

RPA13G4R[4:0]

RPA14G4R[4:0]

RPB0G2R[4:0]

RPB1G2R[4:0]

RPB1G3R[4:0]

RPB2G3R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 100 Microchip Confidential Confidential...........continued Offset 0x2A0 Register Name Bit Pos. RPB2G4R*

0x2A8 RPB3G4R*

0x2B0 RPB4G2R 0x2B4 RPB5G2R 0x2B8 RPB5G1R 0x2BC RPB6G3R 0x2C0 RPB6G1R 0x2C4 RPB7G1R PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPB2G4R[4:0]

RPB3G4R[4:0]

RPB4G2R[4:0]

RPB5G2R[4:0]

RPB5G1R[4:0]

RPB6G3R[4:0]

RPB6G1R[4:0]

RPB7G1R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 101 Microchip Confidential Confidential...........continued Offset 0x2C8 Register Name Bit Pos. RPB7G4R 0x2CC RPB8G1R 0x2D0 RPB8G2R 0x2D4 RPB9G1R 0x2D8 RPB9G3R 0x2DC RPB10G3R*

0x2E0 RPB10G4R*

0x2E8 RPB11G4R*

PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPB7G4R[4:0]

RPB8G1R[4:0]

RPB8G2R[4:0]

RPB9G1R[4:0]

RPB9G3R[4:0]

RPB10G3R[4:0]

RPB10G4R[4:0]

RPB11G4R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 102 Microchip Confidential Confidential...........continued Offset 0x2F0 Register Name Bit Pos. RPB12G2R*

0x2F4 RPB13G2R*

0x2F8 RPB13G3R*

PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 7 6 5 Bits 4 3 2 1 0 RPB12G2R[4:0]

RPB13G2R[4:0]

RPB13G3R[4:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Note:* indicates pins are not available on the 32-pin package, and available only on the 48-pin package. Related Links 7. Product Memory Mapping Overview 5.14 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 103 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.14.1 Peripheral Pin Select Input Register Name:

Offset:

Reset:

Property:

Notes:

[pin name]R See the following Note 0x00

1. For Offset address, see Peripheral Pin Select Input Registers table in the Peripheral Pin Select (PPS) Input Mapping Register Summary from Related Links. 2. Register values can only be changed if the IOLOCK Configuration bit (CFGCON0.IOLOCK) = 0. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 3 1 2

[pin name]R[3:0]

8 0 Access Reset R/W-0 0 R/W-0 0 R/W-0 0 R/W-0 0 Bits 3:0 [pin name]R[3:0]Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Input Pin Selection Group 1, Input Pin Selection Group 2, Input Pin Selection Group 3, Input Pin Selection Group 4 and, Input Pin Selection Group 5 tables in the Input Mapping in PIC32CX-BZ3 Family of Devices for input pin selection values from Related Links. Note:This field is only writable, when CFGCON0.IOLOCK = 0. Related Links 5.12. Peripheral Pin Select (PPS) Input Mapping Register Summary 5.5.5.1.4. Input Mapping in PIC32CX-BZ3 Family of Devices 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 104 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family I/O Ports and Peripheral Pin Select (PPS) 5.14.2 Peripheral Pin Select Output Register Name:

Offset:

Reset:

Property:

RPnR See the following Note 0x0

Notes:

1. For the Offset address, see the Peripheral Pin Select Output Registers table in the Peripheral Pin Select (PPS) Input Mapping Register Summary from Related Links. 2. Register values can only be changed if the IOLOCK Configuration bit (CFGCON0.IOLOCK) = 0. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 Access Reset 4 R/W 0 3 R/W 0 2 RPnR[4:0]

R/W 0 9 1 8 0 R/W 0 R/W 0 Bits 4:0 RPnR[4:0]Peripheral Pin Select Output Register Output bits. For output pin selection values, see Remappable Output Pin Configuration Group1, Remappable Output Pin Configuration Group2, Remappable Output Pin Configuration Group3, and Remappable Output Pin Configuration Group4 tables in the Input Mapping in PIC32CX-BZ3 Family of Devices from Related Links. Note:This field is only writable, when CFGCON0.IOLOCK = 0. Related Links 5.12. Peripheral Pin Select (PPS) Input Mapping Register Summary 5.5.5.1.4. Input Mapping in PIC32CX-BZ3 Family of Devices 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 105 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem 6. Power Subsystem 6.1 Block Diagram The following figure shows detailed view of the power subsystem on the PIC32CX-BZ3 device. Figure 6-1. Power Subsystem Block Diagram VDD DOMAIN POR33 BOR33 ZPBOR BOR12 BANDGAP FRC AVDD Filter VDDCORE LPRC SOSC DAC PLVD ADC RFLDO_OUT VDD_RF CLDO_OUT VDD Main Supply

(1.9V-3.6V) VPMU_VDD Filter DC-DC, MLDO PMU_MLDO_OUT 4.7 H BUCK_CLDO Filter Filter CLDO RFLDO PMU_BK_LX 10 F BUCK_PA OSCILLATOR XON XOP ZB / BLE MODEM ZB / BLE MAC ALWAYS ON BACKUP DS SYSTEM CONTROLLER VDDIO LPRC RTCC DSWDT SRAM CTRL Filter ULP VREG XDS SYSTEM CONTROLLER INT0 / NMCLR VDD CORE CPU SUBSYSTEM 512 KB FLASH CORTEX M4 CPU AN / GPIO NVM CTRL PMU CONTROLLER VDD / VDDIO PMU CONTROLLER VDDCORE FLASH_AVDD Filter ETM MPU FPU CPU PERIPHERALS CRU The power domains of PIC32CX-BZ3 SoC are as follows:

VDD - 1.9V to 3.6V, Main Supply powering VDDIO, FLASH_VDD, AVDD, PMU_VDDIO, PMU_VDDP. All other supplies are derived from VDD with or without filtering. VDDIO 1.9V to 3.6, powering the AON (Always ON), PMU Controller, AN/GPIO, INT0/NMCLR, BKUP 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 106 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem FLASH_VDD 1.9V to 3.6V, Filtered version of VDD (powering the Flash) AVDD 1.9V to 3.6V, Filtered version of VDD for system analog functionality PMU_VDDIO 1.9V to 3.6V, Filtered version of VDD (powering the PMU sub-system) PMU_VDDP 1.9V to 3.6V, Filtered version of VDD (powering the PMU sub-system) GND Common GND for digital, analog and RF sub-systems Other power supply pins as follows:

CLDO_OUT (1.2V 5%) Output pin for the internal voltage regulator for decoupling, this pin must not be used as an external power supply source CLDO is powered with 1.35V 5% from the combination of DC-DC, MLDO and external board filtering VDDCORE is derived from CLDO_OUT Powers the core, memories, and peripherals PMU_BK_LX Pin for connecting the inductor for the internal switching regulator PMU_MLDO_OUT (1.35V 3.7%) 1.35V PMU output pin. This is the shared output pin for both MLDO and the DC-DC converter MLDO_OUT powers the internal LDOs in the Bluetooth/ZigBee subsystem For decoupling recommendations for the different power supplies, refer to the schematic checklist. 6.2 VDD Voltage Domain Overview The PIC32CX-BZ3 Power System VDD Integration Block (SIB) consists of the following modules:

Power-on Reset (POR) This module is used to hold all the components in their inactive state until VDD has reached a stable operating voltage. This module is used to ensure that the supply voltage is sufficient for proper operation of all other analog modules (PD_AVDD) in the Power SIB. Bandgap (BG) This module provides a stable reference voltage for Brown-out Reset, ADC, Flash, Comparators, and low-voltage detect. The ADC, Flash, and Comparators are outside the Power SIB module. Single core voltage regulator (CLDO) based architecture is used in RF-Analog section. Voltage regulator (CLDO) is fed with 1.35V 5% from combination of DC-DC and MLDO and external board filtering. Brown-out Reset (BOR) The BOR module is used to monitor the VDD supply voltage. This module provides a more accurate trip point, but is only enabled when the POR event is inactive and the bandgap reference voltage is enabled and ready. This module is used to ensure that the supply voltage is above the minimum operating voltage needed for program memory reads to be valid. Zero-power BOR (ZPBOR) This low power BOR is used during Deep Sleep operation. The ZPBOR is enabled only when DSZPBOR configuration bit is a 1. Flash Low-Voltage Detect (LVD) uses PLVD. Master Clear Filter (MCLRF) NMCLR generates a device Reset request based on the state of a device input pin. To minimize the effects of noise and to avoid unwanted Reset conditions, the MCLRF function filters the input pin to assure a specific pulse duration of the low input pulse. Note:Nominal pulses below 400 ns are ignored. Programmable Low-Voltage Detect of VDD (PLVD) consists of the following sub-modules:

LVD comparator Resistor ladder Analog voltage switch LVD control (VDDCORE DOMAIN) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 107 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem 6.3 VDD-AON Power Domain Overview The PIC32CX-BZ3 VDD-AON power domain block consists of the following modules:

SOSCs Analog Component acts as a secondary oscillator with a low power 32.768 KHz crystal oscillator used for accurate time keeping. Extreme Deep Sleep System Controller (XDS) with the semaphore used for context saving. Deep Sleep Regulator (ULPVREG) is an ultra low power regulator, provides power during deep sleep modes and/or retention power to the rest of the system in various modes of operation. VDDBKUPCORE is the voltage output. Low Power RC oscillator (LPRC) operates at a nominal frequency of 32.768 KHz (2%) 6.4 VDDBKUPcore Power Domain The PIC32CX-BZ3 VDDBKUPCORE domain consists of the following modules:

Real Time Clock Calender (RTCC) Deep Sleep WDT (DSWDT) Deep Sleep System Controller (DSCTRL) 32.768 kHz Oscillator Controller (digital) (SOSC_DIG) 6.5 PMU Controller The PMU controller acts as control unit to monitor/program the BUCK/MLDO and provides unified control to various LDOs present on the PIC32CX-BZ3 device. The PMU controller does not contain LDOs or BUCK/MLDO source. All the regulators are represented outside of the PMU controller unit and fed into the PMU controller. 6.6 Voltage Regulators The following voltage regulators are available in power subsystem:

VREG (DC-DC/MLDO):

MLDO mode Linear voltage regulator generating 1.35V for powering CLDO and RF LDO; operates from 1.9V to 3.6V DC-DC Switching voltage regulator generating 1.35V; operates from 2.3V to 3.6V ULP_VREG Ultra-low power voltage regulator for operation in back-up mode RF LDO Powering the different blocks of the RF subsystem CLDO Powering the VDDCORE of PIC32CX-BZ3 6.7 Power Supply Modes The PIC32CX-BZ3 supports a single power supply from 1.9V to 3.6V. The IO supply cannot be decoupled from main supply. The same voltage must be applied to VDDx, PMU_VDDIO, VPMU_VDDC, and AVDD with different levels of filtering. The internal voltage regulator has following four different modes:

RUN mode The PIC32CX-BZ3 device automatically gets into RUN mode upon power-up. This is the default state of the device. MLDO mode A soft start-up using MLDO is provided, limiting the charging current. The MLDO also helps to extend the supply voltage range down to 1.9V below Buck BOR. This mode does not require external inductor. BUCK mode The most efficient mode when the CPU and peripherals are running. In this mode, the SoC is powered by the DC-DC converter. This mode requires external LC-filtering and appropriate decoupling on-board before supplying power to other blocks. BUCK mode has two operating modes:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 108 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem PWM (Pulse Width Modulation) mode Buck can deliver the highest output current with good efficiency. The internal switching clock in this mode is 1 MHz to 2 MHz. In PWM mode, it is expected to reach an efficiency of 85%. PSM (Pulse Skipping Mode) This mode is recommended when the load current demand is low. The PSM mode is a type of frequency modulation scheme with an efficiency up to 80%. Low-power modes The PIC32CX-BZ3 supports various low-power modes; Sleep, Deep-Sleep (DS) and Extreme Deep Sleep (XDS). See Power Management Unit (PMU) from Related Links for more details on how to transition from RUN mode to low-power modes. IDLE mode See Power Management Unit (PMU) from Related Links. Selecting between Switching (BUCK) mode and Linear (MLDO) mode can be done by software on-the-fly, but the power supply must be designed according to which mode is to be used. Related Links 14. Power Management Unit (PMU) 6.8 Typical Power Supply Connection for SoC Figure 6-2. Typical Power Supply Connection for SoC VDD (1.9V to 3.6V) FB FB FB FB FB VDDIO AVDD 10 F 0.1 F 10 F 0.1 F PMU_VDDIO/PMU_VDDC 0.1 F VPMU_VDDP 10 F 0.1 F FAVDD 0.1 F CLDO_OUT CLDO_IN VDDCORE PIC32CX-BZ3 4.7 H PMU_BK_LX 10 F 0.1 F MLDO_OUT RFLDO_OUT BUCK_CLDO VDD_RF 1 F 1 F BUCK_PA 1 F 0.1 F 1 F 1 F 0.1 F 1 F For more details, see WBZ35 Module Schematics. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 109 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem 6.9 Typical Power Supply Connection for WBZ35x Module The WBZ35x modules requires only a single power supply on the VDD pins of the module. VDD ranges from 1.9V to 3.6V for non-ECC WBZ35x modules VDD ranges from 2V to 3.6V for ECC variants of the WBZ35x modules Figure 6-3. WBZ35x Module Schematics with VDD and Optional Bulk Capacitors Main Supply (1.9V to 3.6V) 10 F 0.1 F VDD VDD VDDA WBZ35x 10 F GND PADDLE GND For more details, see WBZ35 Module Schematics. 6.10 Power-Up Sequence Characteristics of power-up sequence are as follows:

The VDD/AVDD domains must rise at the same time. At power-on reset, the PIC32CX-BZ3 operates in the MLDO mode. The LDOs start with their default settings and VDDCORE is powered-up. The RF block is maintained in the sleep mode during the power-up time. The PMU controller switches the MLDO mode to DC-DC mode based on device settings in Flash BCFG/TCFG area. 6.10.1 Starting of Voltage Regulators The characteristics of power-up voltage regulators are as follows:

On power-up, the internal regulator starts in MLDO mode After MLDO boots up, the CLDO gets initialized Now the code execution can start The RF system is maintained in sleep-mode during the power-up time 6.10.2 Starting-up of Crystals The characteristics of power-up crystals are as follows:

The power-up of the SOC happens with the internal oscillators. After the power-up, the user software can request to switch on the SOSC and the XOSC crystals. 6.10.3 BOR and POR The Brown-out Reset (BOR) monitors the VDD supply voltage. On detection of a brown-out condition, the BOR re-arms the POR. In this device, the min BOR trip point is the voltage below which the IO is deemed to be un-trusted;

thus, it generates a reset. There are three BOR in PIC32CX-BZ3 and WBZ35x:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 110 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Subsystem BOR3.3 to monitor VDD BOR1.2 to monitor VDDCORE ZPBOR monitors VDD during the deep sleep and extreme deep sleep mode if enabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 111 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview 7. Figure 7-1. Product Mapping Product Memory Mapping Overview System Peripheral Bridge-A Peripheral Bridge-B Peripheral Bridge-C Peripheral Bridge-D Secure Boot ROM Unimplemented 0x4000_0000 0x4000_0400 0x4000_0800 Boot Flash (BFM) 0x4000_0C00 Device Config

(BFM) OTP (BFM) Unimplemented Flash (PFM) 0x4000_1000 0x4000_1400 0x4000_1800 0x4000_1C00 0x4000_2000 0x4000_2400 Unimplemented 0x4000_2800 CMCC-TCM Unimplemented QSPI (XIP) 0x4000_2C00 0x4000_3000 0x4000_3400 0x4000_3800 Unimplemented 0x4000_3C00 0x4000_4000 0x4001_FFFF 0x4100_0000 0x4100_2000 0x4100_4000 0x4100_6000 0x4100_8000 0x4100_A000 0x4101_0000 0x4101_7000 0x4101_FFFF DSU CMCC DMAC EVSYS RAMECC Reserved WZBT Reserved 0x4200_0000 0x4200_0400 0x4200_0800 0x4200_1800 0x4200_1C00 0x4200_2000 0x4200_2400 0x4200_2800 0x4201_0000 0x4201_1000 0x4201_2000 0x4201_FFFF QSPI SERCOM2 Reserved CCL AC Reserved HMTX Reserved RTCC DSCON Reserved PAC FREQM EIC SERCOM0 SERCOM1 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TCC0 TCC1 TCC2 Reserved 0x4400_0000 0x4400_0500 0x4400_0600 0x4400_0800 0x4400_0A00 0x4400_0C00 0x4400_0E00 0x4400_1000 0x4400_1400 0x4400_1A00 0x4400_1E00 0x4400_2200 0x4400_2400 0x4400_2700 0x4400_2A00 0x4400_2B00 0x4400_2C00 0x4400_3C00 0x4400_3E00 0x4401_0000 0x4401_2000 0x4401_2400 0x4401_2800 0x4401_3E00 0x4401_4000 0x4401_6000 0x4401_FFFF Device Config

(CFG) WDT FC PFW CRU BOR_CMP DMT PPS ADCCON ADCCFG ADCOUT Reserved CVD Reserved PORT A PORT B ROT DAC Reserved Reserved ICD PCHE Reserved PMU Reserved Reserved d r a d n a t S n o l s a r e h p i r e P s u B l a r e h p i r e P F F F F _ 0 0 4 4 x 0 o t 0 0 0 0 _ 0 0 4 4 x 0 t s a F n o s u B l a r e h p i r e P l s a r e h p i r e P F F F F _ 1 0 4 4 x 0 o t 0 0 0 0 _ 1 0 4 4 x 0 0x0000_0000 0x0001_0000 0x0080_0000 0x0080_5000 0x0080_6000 0x0082_7000 0x0100_0000 0x0108_0000 0x0200_0000 0x0200_1000 0x0400_0000 0x0500_0000 0x2000_0000 0x2001_8000 0x4000_0000 0x4002_0000 0x4100_0000 0x4102_0000 0x4200_0000 0x4202_0000 0x4300_0000 0x4302_0000 0x4400_0000 0x4402_0000 0x4500_0000 0x4500_2000 0xE000_0000 0xFFFF_3FFF 0x4001_FFFF 0x40FF_FFFF 0x4101_FFFF 0x41FF_FFFF 0x4201_FFFF 0x42FF_FFFF 0x4301_FFFF 0x43FF_FFFF System RAM Unimplemented PB-A Unimplemented PB-B Unimplemented PB-C Unimplemented Crypto Unimplemented PB-D Unimplemented MCROM Unimplemented CM4F Sysyem Registers CM4F System Registers 0xE000_0000 0xE000_1000 0xE000_2000 0xE000_3000 0xE000_E000 0xE000_F000 0xE004_0000 0xE004_1000 0xE004_2000 0xE004_3000 0xE00F_F000 0xE010_0000 0xFFFF_FFFF ITM DWT FPB Reserved SCS Reserved TPIU ETM ETB Reserved CROM Reserved Notes:

Access attempts to any unimplemented memory location generate a bus error. 1. 2. QSPI (XIP) space cacheable and bufferable attribute is controlled using CFGCON1.QSCHE_EN. 3. The MCROM is the microcode crypto ROM associated with the crypto engine. Only the crypto engine has read permissions to MCROM. The DAP derives the base address of the components from CoreSight ROM (CROM) entry values. 4. 5. Component Base address = CROM Base address + CROM Entry value. 6. Refer to CM4F documentation for details on each component register space (developer.arm.com/

documentation/ddi0439/b/System-Control/Register-summary). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 112 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview 7.1 Embedded Memories Internal ROM for Secure Boot Internal high-speed Flash Internal high-speed RAM with retention capability in the low power modes eFuse One-Time-Programmable memory Secure boot key storage 7.2 Physical Memory Map The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. Table 7-1. Physical Memory Map Memory Boot ROM Boot Flash Embedded Program Flash Embedded SRAM Peripheral Bridge A Peripheral Bridge B Peripheral Bridge C Peripheral Bridge D eFuse Start Address 0x00000000 0x00800000 0x01000000 0x20000000 0x40000000 0x41000000 0x42000000 0x44000000 Size PIC32CX510x/WBZ35x 64 KB 32 KB 512 KB 96 KB 3072 bits 7.3 7.4 Boot ROM A 64 KB ROM is dedicated for the secure boot firmware as a part of root of trust (RoT) macro. On a POR, secure boot firmware which actually authenticates rest of the program image in the Flash is always run. Keys and credentials required for code authentication are stored as a part of the eFuses in RoT macro. Flash Memory Parameters A single page contains 4K Bytes, which is applicable to all the device part numbers listed in the Configuration Summary from Related Links. Number of pages available in a device part number will vary depending on available maximum Flash memory size. Equation 7-1.Calculating Flash Memory NumberofPages =

Related Links 1. Configuration Summary FlasSize Bytes PageSize Bytes 7.5 eFuse Memory An eFuse is one-time-programmable (OTP) memory exists as a part of root of trust macro to facilitate key and other required credential storage needed by secure boot. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 113 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview 7.6 SRAM Memory Configuration Retention Depending on the application and power budget needs, part of the system memory can be retained in the Deep Sleep mode. The amount of the SRAM retained in this mode is software selectable, by writing the WCMSIZ register in the PMU module, up to 32 KB of SRAM. By default, no retention is selected. Figure 7-2. Retention Options Full SRAM Size (Top) 32 KB Retention 16 KB Retention 0x20000000 No Memory Retention 32 KB 16 KB 0 KB (Bottom) RAM Error Correction For safety applications, the PIC32CX-BZ3 family embeds error correction codes (ECC) to detect and correct single bit errors, or to enable dual error detection for the system memory. The ECC is software selectable through the DEVCFG0.FRECCDIS bit in the Boot Flash device configuration. By default, ECC is disabled. ECC can be applied only for 32 KB of SRAM. When enabled, the top 32 KB of memory will be reserved to store the ECC, and will not be available for the application. Therefore, when ECC is enabled, usable System RAM is 64 KB (96-32 KB) for the 96 KB data RAM variant. ECC support for Row A or Row B can be selected using CFGCON1.ECC_SEL_MEM bit. If CFGCON1.ECC_SEL_MEM is 0, ECC will support the contents in Row A. If CFGCON1.ECC_SEL_MEM is 1, ECC will support the contents in Row B. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 114 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview Figure 7-3. Memory with RAM Error Correction PIC32CX510x 96 KB 64 KB 32 KB Row C Error Correction Row B Row A Note:ECC is not possible with SRAM retention enabled. 0x20000000 0 KB CoreSight ETB Connection When enabled, the bottom 32 KB system memory space is reserved for CoreSight ETB debug usage. Therefore, when Coresight ETB is enabled, usable System RAM is 64 KB (96-32 KB) for the 96 KB data RAM variant. The following figure shows an example where both ECC and CoreSight ETB are enabled. Figure 7-4. Memory with ECC and CoreSight ETB PIC32CX510x 96 KB Row C Error Correction Row B 64 KB 32 KB Row A CoreSight ETB 0x20000000 0 KB 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 115 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview 7.7 Boot Flash Device Configuration Word The PIC32CX-BZ3 device provides several user writable configuration registers related to the configuration and operation of the system. The device configuration words are programmed in Boot Flash memory (NVR pages) and get loaded on equivalent registers after the device Reset. The following table shows the device configuration words in Boot Flash. Table 7-2. Boot Flash and Device Configuration Word Physical Address Register Name Bit Range 31:0 0x00805E88 ALTFUSERID 31:0 See USER_ID in the CFG Register Summary from Related Links 0x00805E8C ALTDEVCFG4 31:0 See CFGCON4(L) in the CFG Register Summary from Related Links 0x00805E90 ALTDEVCFG2 31:0 See CFGCON2(L) in the CFG Register Summary from Related Links 0x00805E94 ALTDEVCFG1 31:0 See CFGCON1(L) in the CFG Register Summary from Related Links 0x00805E98 ALTDEVCFG0 31:0 See CFGCON0(L) in the CFG Register Summary from Related Links 0x00805E9C ALTFBCFG0 0x00805F88 FUSERID 0x00805F8C DEVCFG4 0x00805F90 DEVCFG2 0x00805F94 DEVCFG1 0x00805F98 DEVCFG0 0x00805F9C FBCFG0 0x00805FBC FCPN0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 7:0 15:8 23:16 31:24 See BCFG0 in the CFG Register Summary from Related Links See USER_ID in the CFG Register Summary from Related Links See CFGCON4(L) in the CFG Register Summary from Related Links See CFGCON2(L) in the CFG Register Summary from Related Links See CFGCON1(L) in the CFG Register Summary from Related Links See CFGCON0(L) in the CFG Register Summary from Related Links See BCFG0 in the CFG Register Summary from Related Links CP 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 116 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Product Memory Mapping Overview 7.8 Boot Flash Code Protection Register Name:

Offset:

Reset:

Property:

FCPN0 0x00805FBC 0x00000000 Note:Offset is an absolute address of this register. Bit 31 30 29 Access Reset Bit 23 22 21 Access Reset 28 CP R p 20 27 26 25 24 19 18 17 16 Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 28 CPFlash (BFM, PFM) Code Protect Note:The value of this bit is the inverse polarity of the value read from the BCFG0 register. 9 1 8 0 Value 0 1 Description Protection is disabled. Protection is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 117 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture 8. Processor and Architecture 8.1 Cortex M4F Processor The ARMCortex-M4F processor is a high performance 32-bit processor designed for the microcontroller market. It offers the following significant benefits to developers:

Outstanding processing performance combined with fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Efficient processor core, system, and memories Ultra low-power consumption with integrated sleep modes Platform security robustness, with integrated memory protection unit (MPU). The implemented ARM Cortex-M4F is revision r0p1 For additional information, refer to http://www.arm.com The Cortex-M4F processor is built on a high-performance processor core with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE 754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic, and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4F processor implements a version of the Thumb instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M4F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M4F processor closely integrates a configurable Nested Vector Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a Non-Maskable interrupt (NMI), and provides up to 8 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs), dramatically reducing interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state. 8.1.1 System Level Interface The Cortex-M4F processor provides multiple interfaces using AMBA technology to provide high-speed, low-latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M4F processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data, and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive. 8.1.2 Integrated Configurable Debug The Cortex-M4F processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area far smaller than traditional trace units, enabling many low cost MCUs to implement full instruction trace for the first time. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 118 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture To enable simple and cost-effective profiling of the system events these generate, a stream of software-generated messages, data trace, and profiling information is exported over three different ways:

Output off chip using the TPIU, through a single pin, called Serial Wire Viewer (SWV). Limited to ITM system trace Output off chip using the TPIU, through a 4-bit pin interface. Bandwidth is limited Internally stored in RAM, using the CoreSight ETB. Bandwidth is then optimal but capacity is limited The Flash Patch and Breakpoint Unit (FPB) provides up to 8 hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to 8 words in the program code in the Code memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable memory, for example Flash, is available in the device. During initialization, the application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration, which means the program in the non-modifiable ROM can be patched. 8.1.3 Cortex-M4F Processor Features and Configuration IEEE 754-compliant single-precision Floating Point Unit (FPU) Integrated sleep modes for low power consumption Thumb instruction set combines high code density with 32-bit performance Fast code execution permits slower processor clock or increases Sleep mode time Hardware division and fast digital-signal-processing orientated multiply accumulate Saturating arithmetic for signal processing Deterministic, high-performance interrupt handling for time-critical applications Memory Protection Unit (MPU) for safety-critical applications Extensive debug and trace capabilities: Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing and code profiling. Features Interrupts Cortex-M4F Options 1 to 240 Number of priority bits 3 to 8 Data endianness Little-endian or big-endian SysTick Timer calibration value MPU Present or Not present PIC32CX-BZ3 Configuration 43 3 = eight levels of priority Little-endian 0x80000000 Present Debug support level 0 = No debug. No DAP, breakpoints, watchpoints, Flash patch or halting debug 3 = Full debug plus DWT data matching 1 = Minimum debug. Two breakpoints, one watchpoint, no Flash patch 2 = Full debug minus DWT data matching 3 = Full debug plus DWT data matching Trace support level 0 = No trace. No ETM, ITM or DWT triggers and counters 1 = Standard trace. ITM and DWT triggers and counters, but no ETM 2 = Full trace. Standard trace plus ETM 3 = Full trace plus HTM port 2 = Full trace. Standard trace plus ETM JTAG Present or Not present Not present 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 119 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture

...........continued Features Cortex-M4F Options PIC32CX-BZ3 Configuration Bit Banding Present or Not present FPU Present or Not present Not present Present 8.1.4 Cortex-M4F Core Peripherals Nested Vectored Interrupt Controller System Control Block System Timer The Nested Vector Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control and reporting of system exceptions. Refer to the Cortex-M4 Technical Reference Manual for more details (http://www.arm.com). The system timer, SysTick, is a 24-bit countdown timer. Use this as a Real-Time Operating System (RTOS) tick timer or as a simple counter. The SysTick timer runs on the processor clock and it does not decrement when the processor is halted for debugging. Refer to the Cortex-M4 Technical Reference Manual for more details (http://www.arm.com). Memory Protection Unit The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions and an optional predefined background region. Refer to the Cortex-M4 Technical Reference Manual for more details (http://www.arm.com). Floating-Point Unit The Floating Point Unit (FPU) provides IEEE 754-compliant operations on single-precision, 32-

bit, floating-point values. Refer to the Cortex-M4 Technical Reference Manual for more details

(http://www.arm.com). 8.1.5 Cortex-M4F Address Map Address 0xE000E008-0xE000E00F Core Peripheral System control block 0xE000E010-0xE000E01F System timer 0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller 0xE000ED00-0xE000ED3F 0xE000ED90-0xE000ED93 System control block MPU Type Register 0xE000ED94-0xE000EDB8 Memory Protection Unit 0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller 0xE000EF30-0xE000EF44 Floating Point Unit 8.2 Nested Vector Interrupt Controller (NVIC) 8.2.1 8.2.2 Overview The Nested Vectored Interrupt Controller (NVIC) in the PIC32CX-BZ3 family devices supports 43 interrupts with eight different priority levels. For more details, refer to the Cortex-M4 Technical Reference Manual (www.arm.com). Interrupt Line Mapping Each of the interrupt lines is connected to one peripheral instance, as shown in the following table. Each peripheral can have one or more interrupt flags, located in the peripherals Interrupt Flag Status and Clear (INTFLAG) register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 120 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by configuring in the peripherals Interrupt Enable register. An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. Depending on their criticality, the interrupt requests for one peripheral are either ORed together on system level, generating one interrupt or directly connected to an NVIC interrupt lines. This is described in the following table. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers

(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt. Table 8-1. NVIC Interrupt Mapping Module EIC NMI - External Interrupt Control RTCC - Real-Time Counter and Calendar EIC - External Interrupt Controller FREQM - Frequency Meter Source NMI CMP A 0..3 OVF A PER A 0..7 TAMPER A EXTINT 0..3 DONE FC - Flash Controller and PCHE Flash Controller Program/erase complete PORT-A PORT-B DMAC - Direct Memory Access Controller EVSYS - Event System Interface PAC - Peripheral Access Controller RAM ECC PFW CRC Done PCACHE PortA Input Change Interrupt PortB Input Change Interrupt SUSP 0..3 TCMPL 0..3 TERR 0..3 SUSP 4..15 TCMPL 4..15 TERR 4..15 EVD 0..3 OVR 0..3 EVD 4..11 OVR 4..11 ERR SINGLEE-0 DualE-1 Line NMI 0 1 2 3 4 5 6 7 8 9 10 11 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 121 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture Line 12 13 14

...........continued Module Source SERCOM0 - Serial Communication Interface 0(1) Order: USART, I2CM, I2CS, SPI SERCOM1 - Serial Communication Interface 1(1) Order: USART, I2CM, I2CS, SPI TCC0 - Timer Counter Control 0 0 1 2 3 4 5 7 0 1 2 3 4 5 7 CNT A DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A MC 0..5 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 122 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture

...........continued Module TCC1 - Timer Counter Control 1 TCC2 - Timer Counter Control 2 TC0 - Basic Timer Counter 0 TC1 - Basic Timer Counter 1 TC2 - Basic Timer Counter 2 Source CNT A DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A MC 0..5 CNT A DFS A ERR A FAULTA A FAULTB A FAULT0 A FAULT1 A OVF TRG UFS A MC 0..1 ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF Line 15 16 17 18 19 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 123 Microchip Confidential Confidential...........continued Module TC3 - Basic Timer Counter 3 TC4 - Basic Timer Counter 4 TC5 - Basic Timer Counter 5 TC6 - Basic Timer Counter 6 TC7 - Basic Timer Counter 7 ADC AC - Analog Comparators CRYPTO QSPI - Quad SPI interface PIC32CX-BZ3 and WBZ35x Family Processor and Architecture Source ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF ERR A MC 0 MC 1 OVF ADC_GIRQ ADC_DIRQ0, ADC_DIRQ1 ADC_AIRQ0, ADC_AIRQ1 ADC_FLT ADC_FCC ADC_BGVR_RDY COMP 0 COMP 1 WIN 0 INT0 INT1 INT2 QSPI Line 20 21 22 23 24 25 34 35 36 26 27 28 41 29 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 124 Microchip Confidential Confidential...........continued Module Wireless Subsystem (WZBT) CVD SERCOM2 Serial Communication Interface 2(1) I2CM, I2CS PIC32CX-BZ3 and WBZ35x Family Processor and Architecture Line 30 31 32 33 37 42 38 40 Source ZB_INT0 BT_INT0 BT_INT1 ARBITER CLKI_WAKEUP_NMI BT_LC CVD 0 1 2 3 4 5 6 7 Note:

1. The integer number specified in the source refers to the respective bit position in the INTFLAG register of respective peripheral. 8.3 High-Speed Bus System The high speed system bus matrix connects a multitude of initiator logic cores / IPs to a multitude of target logic cores / IPs, supporting AHB2/APB2 buses. 8.3.1 Features High-Speed Bus Matrix has the following features:

AMBA Advanced High-performance Bus (AHB Lite) compliant interfaces Symmetric crossbar bus switch implementation Allows concurrent accesses from different Initiator to different target 32-bit data bus APB compliant user interface 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 125 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture 8.3.2 Configuration Figure 8-1. High-Speed Bus Matrix Interconnectivity High-Speed Bus Target 1 M A R S 2 M A R S 3 M A R S 4 M A R S E H C P U P C 4 M C E H C P S L A R E H P R E P I

A B B P

B B B P

C B B P

D B B P

I P S Q

) M O R

T O R O T P Y R C 0 1 2 3 4 5 6 7 8 9 10 11 12 r o t a i t i n I s u B d e e p S

h g H i CM4CPU CM4CC DMA RD DMA WR DSU/ICD CRYPTO 0 1 2 3 4 5 Table 8-2. High Speed Bus Matrix Initiator High-Speed Bus Matrix Initiator Initiator ID CM4CPU - Cortex M4F Processor CM4CC - Cortex-M Cache Controller DMA RD - DMA-Read DMA-WR - DMA-Write DSU/ICD (private test mode only) - Device Service Unit/In-Chip Debugger CRYPTO Table 8-3. High-Speed Bus Matrix Target 0 1 2 3 4 5 High-Speed Bus Matrix Target Target ID SRAM1 - SRAM Port 1 SRAM2 - SRAM Port 2 SRAM3 - SRAM Port 3 SRAM4 - SRAM Port 4 0 1 2 3 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 126 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Processor and Architecture

...........continued High-Speed Bus Matrix Target Target ID PCHE - Pre-fetch Cache of CM4CC PCHE - Pre-fetch Cache of Peripherals PB-B-A - Peripheral Bridge A PB-B-B - Peripheral Bridge B PB-B-C - Peripheral Bridge C PB-B-D - Peripheral Bridge D QSPI - Quad SPI Interface ROT - Root of Trust CRYPTO 4 5 6 7 8 9 10 11 12 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 127 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9. Prefetch Cache (PCHE) 9.1 Introduction The Prefetch Cache is a performance-enhancing module included in the PIC32CX-BZ3 devices, along with the L1 cache (Cortex M Cache Controller CMCC) to the Cortex M4F CPU. 9.2 Features The Prefetch module increases the system performance for most of the applications. The Prefetch module includes the following features:

Fully associative lines for:

Four lines for CPU instructions cache Two lines for CPU data cache Two lines for peripheral data cache 16-byte cache lines and 128-bits parallel memory fetch Configurable predictive prefetch for CPU instructions cache Error detection and correction (ECC) 9.3 Overview When running the Prefetch module at high-clock rates, insert the Wait states into Program Flash Memory (PFM) read transactions to meet the access time of the PFM. The user can hide the Wait states to the core by prefetching and storing the instructions in a temporary holding area that the CPU can access quickly. Although, the data path to the CPU is 32 bits wide, the data path to the PFM is 128 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency. The Prefetch module holds a subset of PFM in temporary holding spaces known as lines. Each line contains a tag and data field. Normally, the lines hold a copy of what is currently in memory to make instructions or data available to the CPU without the Wait states. The CPU or a peripheral may request the data located in the PFM. If the requested data is not currently stored in the Prefetch module line, a read is performed to the PFM at the correct address, and the data is supplied to the Prefetch module and to the CPU or peripheral. If the requested data is stored in the Prefetch module and is valid, the data is supplied to the CPU or peripheral without Wait states. The following figure shows a block diagram of the Prefetch module. Logically, the Prefetch module fits between the System Bus module and the PFM. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 128 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) Figure 9-1. Prefetch Cache Block Diagram U P C

s u B m e t s y S Bus Control Prefetch Buffer Line Control Tag Data U P C

s u B m e t s y S Program Flash Memory (PFM) 9.3.1 Line Organization The Prefetch module consists of two arrays, data and tag, each of which hold four lines. A data array consists of program instructions, program data or peripheral data. Address matches are based on the physical address, not the virtual address. Each line in the tag array contains the following information:

Tag Physical address of the data held in the data line Valid bit Each line in the data array, contains 16 bytes of data. Depending on the line, the data can be CPU instructions, CPU data or peripheral data. The following figures illustrate the organization of a line. Figure 9-2. Tag Line LTAG[28:4]

LValid 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 129 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) Figure 9-3. Data Line 31 31 31 31 WORD 3 WORD 2 WORD 1 WORD 0 0 0 0 0 9.4 Product Dependencies Not applicable. 9.4.1 I/O Lines Not applicable. 9.4.2 Power Management 9.4.2.1 Standby Sleep Mode When the device enters the Standby Sleep mode, the Prefetch module is disabled and placed into a low-power state where no clocking occurs in the module. 9.4.2.2 Idle Mode When the device enters the Idle mode, iCache, Prefetch and dCache clocks are internally gated-off, the aCache

(peripheral data) clock remains functional for peripheral accesses and the CPU stops executing code. Any outstanding prefetch completes before the Prefetch module stops its clock through automatic clock gating. 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.4.9 Clocks The PCHE interfaces with the CPU through the AHB (SYS_CLK). DMA Not applicable. Interrupts The interrupt request line is connected to the interrupt controller. Using the PCACHE interrupt(s) requires the NVIC interrupt controller to be configured first. Events Not applicable. Debug Operation The behavior of the Prefetch module is unaltered in the Debug mode. Register Access Protection Not applicable. Analog Connections Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 130 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.5 Prefetch Behavior The Prefetch module complements an L1 CPU (CMCC) cache rather than replacing it. A four 128-bit (16-byte) lines hold instructions, two 128-bit (16-byte) lines hold CPU data and two 128-bit (16-byte) lines hold peripheral data from the PFM. The Prefetch module uses the Wait state's value from the PFMWS[3:0] bits (CHECON[3:0]) and Address Wait state ADRWS bit (CHECON[8]) to determine how long it must wait for Flash access when it reads instructions or data from the PFM. If the instructions or data already reside in the Prefetch module line, the Prefetch module returns the instruction or data in zero Wait states. For CPU instructions, if predictive prefetch is enabled and the code is 100% linear, the Prefetch module will provide instructions back to the CPU with the Wait states only on the first instruction of the Prefetch module line. If the CPU accesses uncacheable addresses, it bypasses the cache. During the bypass, the prefetch module accesses the PFM for every instruction, incurring an address setup time defined by ADRWS and a Flash access time as defined by PFMWS bits. Therefore, the total Flash wait states is a sum of ADRWS and PFMWS. The Bypass mode is also forced for a cache if its associated I/D/A CHEEN bit (CHECON) is zero. To allow caching for I and/or D caches, set the I and/or D *CHEEN bit to one. To enable a cache, set the ACHEEN bit to one. 9.6 Configurations The CHECON register controls the general configurations available for accelerating the instruction and data accesses to the Flash memory system. The Prefetch module implements the following general options:

The PFMWS[3:0] bits (CHECON[3:0]) control the number of system clock cycles required to access the PFM. The total Flash Wait states is a sum of ADRWS and PFMWS. The PREFEN[1:0] bits (CHECON[5:4]) control the predictive and prefetched instruction, which allows the cache controller to fetch the next 16-byte aligned set of instructions. The PFMSECEN bit (CHECON[7]) controls the Prefetch module that generates an interrupt event on a specific count of single bit errors corrected by the Flash Error Correction Code (ECC). The ADRWS bit (CHECON[8]) controls the number of system clock cycles required for address setup to PFM. The CHEPERF bit (CHECON[12]) controls the gathering statistics of the CPU instruction cache. The ICHECOH bit (CHECON[16]) controls the auto invalidate for the CPU instruction cache. The DCHECOH bit (CHECON[17]) controls the auto invalidate for the CPU data cache. The ACHECOH bit (CHECON[18]) controls the auto invalidate for the peripheral data cache. The ICHEINV bit (CHECON[20]) controls the manual invalidate for the CPU instruction cache. The DCHEINV bit (CHECON[21]) controls the manual invalidate for the CPU data cache. The ACHEINV bit (CHECON[22]) controls the manual invalidate for the peripheral data cache. The ICHEEN bit (CHECON[24]) controls the CPU instruction cache enable. The DCHEEN bit (CHECON[25]) controls the CPU data cache enable. The ACHEEN bit (CHECON[26]) controls the peripheral data cache enable. 9.7 Predictive Prefetch Behavior When the user configures the module for predictive prefetch, the module predicts the next line address, fetches the instruction and, then, stores it in the prefetch buffer. If the requested instruction is not in a Prefetch module line and the read address matches the predicted address, the content of the prefetch buffer is loaded in the Prefetch module line while simultaneously returning the critical word to the read initiator. On enabling the predictive prefetch, the prefetch function starts predicting based on the first address read to the PFM. When the user places the first line in the Prefetch module, the module increments the address to the next 16-byte aligned address and starts a PFM access. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 131 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) The predictive prefetches, like all PFM read accesses, are never aborted. If a new address request does not match the predicted address, a new PFM access occurs after the current access finishes. The PREFEN [1:0] bits

(CHECON[5:4]) can start a predictive prefetch. This allows the cache controller to speculatively fetch the next 16-byte aligned set of instructions. The predictive prefetch feature is available only for CPU instruction but not for CPU data and peripheral. If the selected system clock speed is sufficiently low enough to access the Flash at zero Wait states, the predictive prefetch is detrimental and may be disabled. 9.8 Coherency Support When a PFM programming event occurs flash programming initiated by the Flash controller, the Prefetch module invalidates all lines and the contents of the prefetch buffer. If a transaction is in progress, the invalidation occurs after completion. When programming or erasing a Flash page, a read of that Flash page will cause the transaction to stall until the erase or program event completes. The Prefetch module provides two methods for coherency control:

Auto Invalidate via I/D/A CHECOH Manual Invalidate via I/D/A CHEINV The user can choose to auto invalidate the each/any cache on a PFM programming event by setting *CHECOH =

1. This is the safest option. However, the user has the option to never auto invalidate each/any cache by setting

*CHECOH = 0. In addition to using *CHECOH, *CHEINV can be used as an alternate invalidate method to invalidate each/any cache manually. If using *CHEINV to manually invalidate each/any cache due to a PFM programming event, stop all instruction/data fetches from the desired Flash, set *CHEINV, wait for it to clear and, then, start the programming sequence. When using *CHEINV to invalidate each/any cache for reasons other than programming, it can be set at any time but only takes effect after any pending transactions complete. 9.9 Effects of Reset 9.9.1 On Reset Upon a device Reset, the following occurs:

All lines are invalidated All tag bits are cleared 9.9.2 After Reset The module operates as per the values in the CHECON register. See the CHECON register from Related Links. Related Links 9.12.1. CHECON 9.10 Error Conditions The Prefetch module handles and reports information about two error types: ECC Double-bit Error Detected (DED) and ECC Single-bit Error Corrected (SEC). The ECC Error detection logic is enabled and disabled using the configuration bits, ECCCTL[1:0] (CFGCON0/DEVCFG0[29:28]). The ECC logic increases the read access delay from the PFM. Depending on the frequency of the system clock, the Wait states may be different between ECC-enabled and ECC-disabled. Note:ECC errors are captured for predictive prefetch reads of the PFM. However, those errors are not reported until, and unless, that data is used by the system. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 132 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.10.1 ECC Double-bit Error Detected (DED) A read from the Flash memory that results in a PFM ECC DED causes the Prefetch module to return a bus exception error to the initiator. If that initiator is the CPU, it recognizes the bus exception error, prevents the instruction from executing, or read data from loading, and generates an exception using the bus exception error vector. When an ECC DED error occurs, the PFMDED bit (CHESTAT[27]) is set. The exception handling code can, then, check this bit to determine whether the exception was caused by a PFM ECC DED event. This bit must be cleared in software by the exception handler. Note:CPU instructions or data prefetched from the PFM will always be loaded into the Prefetch module, even if a DED error is generated. The Prefetch module line containing the DED data will be tagged as valid until the line is replaced. 9.10.2 ECC Single Error Corrected (SEC) A PFM ECC SEC event is not a critical error and as such is reported through an interrupt. The user has the option to enable or disable this interrupt through the PFMSECEN bit (CHECON[7]). The data in the Prefetch module is correct, and no further ECC events are generated for addresses that hit the data line as long as that data is in the Prefetch module. Each read that returns from the PFM with an ECC SEC status causes the PFMSECCNT[7:0] bits (CHESTAT[7:0]) to decrement by one. If PFMSECCNT[7:0] is zero and a PFM ECC SEC event occurs, the PFMSEC bit (CHESTAT[26]) is set and an interrupt is generated. Therefore, the PFMSECCNT[7:0] bits should be set to the number of PFM ECC SEC events desired for an interrupt minus 1. For example, to generate an interrupt after five PFM ECC SEC events, PFMSECCNT[7:0] should be set to four (00000100). The Prefetch module does not reload the PFMSECCNT[7:0]

bits when it reaches zero. Software must write the desired count each time it services the PFMSEC interrupt. Software can generate an ECC SEC interrupt by setting the PFMSECEN bit and then setting the PFMSEC bit. If the PFMSEC bit is already set when PFMSECEN is set, the Prefetch module will also generate an ECC SEC interrupt. The ECC SEC interrupt persists as long as the PFMSECEN and PFMSEC bits remain set. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 133 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.11 Register Summary See PCHE module in the Product Memory Mapping Overview from Related Links for base address. Note:CHECON and CHESTAT registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CHECON 0x04

... 0x0F Reserved 0x10 CHESTAT 0x14

... 0x1F Reserved 0x20 CHEHIT 0x24

... 0x2F Reserved 0x30 CHEMIS 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 PFMSECEN PREFEN[1:0]

PFMWS[3:0]

ACHEINV DCHEINV ICHEINV ACHECOH DCHECOH ICHECOH CHEPERF ADRWS ACHEEN DCHEEN ICHEEN PFMSECCNT[7:0]

PFMDED PFMSEC CHEHIT[7:0]

CHEHIT[15:8]

CHEHIT[23:16]

CHEHIT[31:24]

CHEMIS[7:0]

CHEMIS[15:8]

CHEMIS[23:16]

CHEMIS[31:24]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 9.12 Register Description Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 134 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.12.1 CHECON - Prefetch Module Control Register Name:

Offset:

Reset:

Property:

CHECON 0x00 0x0700010F

Bit 31 30 29 28 27 Access Reset Bit 23 Access Reset 22 ACHEINV R/S/HC 0 21 DCHEINV R/S/HC 0 Bit 15 14 13 Access Reset 20 ICHEINV R/S/HC 0 12 CHEPERF R/W 0 Bit 7 6 PFMSECEN Access Reset R/W 0 5 4 PREFEN[1:0]

R/W 0 R/W 0 3 R/W 1 Bit 26 ACHEENPeripheral Data Cache Enable bit Value 1 0 Description Caching enabled Caching disabled (and all lines invalidated) Bit 25 DCHEENData Cache Enable bit Value 1 0 Description Caching enabled Caching disabled (and all lines invalidated) Bit 24 ICHEENInstruction Data Cache Enable bit Value 1 0 Description Caching enabled Caching disabled (and all lines invalidated) 26 ACHEEN R/W 1 25 DCHEEN R/W 1 24 ICHEEN R/W 1 19 18 ACHECOH R/W 0 17 DCHECOH R/W 0 11 10 9 1 2 PFMWS[3:0]

R/W 1 R/W 1 16 ICHECOH R/W 0 8 ADRWS R/W 1 0 R/W 1 Bit 22 ACHEINVManual Invalidate Control for Peripheral Data Cache Note:

1. Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times. Value 1 0 Description Force invalidate cache/invalidate busy Cache invalidation follows ACHECOH/invalid complete Bit 21 DCHEINVManual Invalidate Control for Data Cache Note:

1. Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times. Value 1 0 Description Force invalidate cache/invalidate busy Cache invalidation follows DCHECOH/invalid complete 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 135 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) Bit 20 ICHEINVManual Invalidate Control for Instruction Cache Notes:

Predictive Prefetch Buffer (PFB) is included with iCache invalidate. 1. 2. Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times. Value 1 0 Description Force invalidate cache/invalidate busy Cache invalidation follows ICHECOH/invalid complete Bit 18 ACHECOHAuto Cache Coherency Control for Peripheral Data Cache Note:ACHECOH must be stable before initiation of programming to ensure correct invalidation of data. Value 1 0 Description Auto invalidate cache on a programming event No auto invalidated cache on a programming event Bit 17 DCHECOHAuto Cache Coherency Control for Data Cache Note:DCHECOH must be stable before initiation of programming to ensure correct invalidation of data. Value 1 0 Description Auto invalidate cache on a programming event No auto invalidated cache on a programming event Bit 16 ICHECOHAuto Cache Coherency Control for Instruction Cache Note:ICHECOH must be stable before initiation of programming to ensure correct invalidation of data. Value 1 0 Description Auto invalidate cache on a programming event No auto invalidated cache on a programming event Bit 12 CHEPERFCache Performance Counters Enable Note:Performance counters are reset on 0 to 1 transition of this bit. Value 1 0 Description Performance counters is enabled Performance counters is disabled Bit 8 ADRWSAddress Wait State Enable Total Flash wait states are ADRWS + PFMWS. Value 1 0 Description Add 1 address Wait state - allowing for higher clock frequencies Add 0 address Wait states - allowing for higher performance at lower clock frequencies Bit 7 PFMSECENFlash Single-bit Error Corrected (SEC) Interrupt Enable bit Value 1 0 Description Generate an interrupt when PFMSEC is set Do not generate an interrupt when PFMSEC is set Bits 5:4 PREFEN[1:0]Instruction Predictive Prefetch Enable Value 01 00 Description Instruction predictive prefetch enabled for cacheable regions only Instruction predictive prefetch disabled Note:Other values are unavailable. Bits 3:0 PFMWS[3:0]PFM Access Time Defined in Terms of SYSCLK Wait States bits Total Flash Wait states are ADRWS + PFMWS. Value 1111 Description Fifteen Wait states 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 136 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) Description Fourteen Wait states One Wait state Zero Wait state Value 1110

... 0001 0000 Notes:

1. 2. This is not the Wait state seen by the CPU. For the Wait states to SYSCLK relationship, see Electrical Characteristics from Related Links. Related Links 38. Electrical Characteristics 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 137 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.12.2 CHESTAT - Prefetch Module Status Register Name:

Offset:

Reset:

Property:

CHESTAT 0x10 0x00000000

Bit 31 30 29 28 Access Reset 27 PFMDED HS, R/C 0 26 PFMSEC HS, R/W 0 25 24 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 3 4 PFMSECCNT[7:0]

2 9 1 8 0 Access HS, HC, R/W HS, HC, R/W HS, HC, R/W HS, HC, R/W HS, HC, R/W HS, HC, R/W HS, HC, R/W HS, HC, R/W Reset 0 0 0 0 0 0 0 0 Bit 27 PFMDEDFlash Double-bit Error Detected (DED) Status bit This bit is set in hardware and can only be cleared (i.e., set to 0) in software. Value 1 0 Description A DED error has occurred A DED error has not occurred Bit 26 PFMSECFlash Single-bit Error Corrected (SEC) Status bit Note:The error event is reported to the CPU via using the PCACHE interrupt event (See Nested Vector Interrupt Controller (NVIC) from Related Links). Value 1 0 Description A SEC error occurred when PFMSECCNT[7:0] was equal to zero A SEC error has not occurred Bits 7:0 PFMSECCNT[7:0]Flash SEC Count bits Decrements by 1 its count value each time an SEC error occurs. Holds at zero. When an SEC error occurs when PFMSECCNT[7:0] is zero, the PFMSEC status bit is set. If PFMSECEN is also set, a Prefetch module interrupt event is generated. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 138 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) 9.12.3 CHEHIT Prefetch Module Hit Statistics Register Name:

Offset:

Reset:

Property:

CHEHIT 0x20 0x00000000

Bit 31 Access Reset R/HC 0 Bit 23 Access Reset R/HC 0 Bit 15 Access Reset R/HC 0 Bit 7 Access Reset R/HC 0 30 R/HC 0 22 R/HC 0 14 R/HC 0 6 R/HC 0 29 R/HC 0 21 R/HC 0 13 R/HC 0 5 R/HC 0 28 27 CHEHIT[31:24]

R/HC 0 20 R/HC 0 19 CHEHIT[23:16]

R/HC 0 12 R/HC 0 11 CHEHIT[15:8]

R/HC 0 4 R/HC 0 3 CHEHIT[7:0]

R/HC 0 R/HC 0 26 R/HC 0 18 R/HC 0 10 R/HC 0 2 R/HC 0 25 R/HC 0 17 R/HC 0 9 R/HC 0 1 R/HC 0 24 R/HC 0 16 R/HC 0 8 R/HC 0 0 R/HC 0 Bits 31:0 CHEHIT[31:0]Instruction Cache Hit Count bits When CHECON.CHEPERF = 1, CHEHIT increments once per iCache or Predictive Prefetch Buffer (PFB) hit. Note:CHEHIT is Reset on 0 to 1 transition of CHECON.CHEPERF. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 139 Microchip Confidential Confidential 9.12.4 CHEMIS Prefetch Module Miss Statistics Register PIC32CX-BZ3 and WBZ35x Family Prefetch Cache (PCHE) Name:

Offset:

Reset:

Property:

CHEMIS 0x30 0x00000000

Bit 31 Access Reset R/HC 0 Bit 23 Access Reset R/HC 0 Bit 15 Access Reset R/HC 0 Bit 7 Access Reset R/HC 0 30 R/HC 0 22 R/HC 0 14 R/HC 0 6 R/HC 0 29 R/HC 0 21 R/HC 0 13 R/HC 0 5 R/HC 0 28 27 CHEMIS[31:24]

R/HC 0 20 R/HC 0 19 CHEMIS[23:16]

R/HC 0 12 R/HC 0 11 CHEMIS[15:8]

R/HC 0 4 R/HC 0 3 CHEMIS[7:0]

R/HC 0 R/HC 0 26 R/HC 0 18 R/HC 0 10 R/HC 0 2 R/HC 0 25 R/HC 0 17 R/HC 0 9 R/HC 0 1 R/HC 0 24 R/HC 0 16 R/HC 0 8 R/HC 0 0 R/HC 0 Bits 31:0 CHEMIS[31:0]Instruction Cache Miss Count bits When CHECON.CHEPERF = 1, CHEMIS increments once per iCache or Predictive Prefetch Buffer (PFB) miss. Note:CHEMIS is Reset on 0 to 1 transition of CHECON.CHEPERF. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 140 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10. Cortex M Cache Controller (CMCC) 10.1 Overview The Cortex M Cache Controller provides an L1 cache to the Cortex M CPU. The CMCC sits transparently between the CPU and the cache leading to improved performance. The CMCC interfaces with the CPU through the AHB and is connected to the APB bus interface for its configuration. 10.2 Features Physically addressed and physically tagged L1 data and instruction cache set to 4 KB L1 cache line size set to 16 Bytes L1 cache integrates 32-bit bus master interface Unified 4-Way set associative cache architecture Lock-Down feature, which allows cached to be locked per way Write through cache operations, read allocate Configurable as data and instruction Tightly Coupled Memory (TCM) Round Robin victim selection policy Event Monitoring, with one programmable 32-bit counter Cache Interface includes cache maintenance operations registers 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 141 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.3 Block Diagram Figure 10-1. CMCC Block Diagram CM4F Cortex M Interface CMCC RAM Interface Cache Controller Registers Interface APB Interface METADATA RAM DATA RAM TAG RAM Memory Interface High-Speed Bus Matrix Figure 10-2. CMCC Organization 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 142 Microchip Confidential WAY 0WAY 1WAY 2WAY 3Base Address + 0x00000000Base Address + 0x00000400Base Address + 0x00000800Base Address + 0x00000C00Line 0Line 1Line 2Line 3Line 4......Line 634 Bytes4 Bytes4 Bytes4 BytesLine nConfidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.4 Signal Description Not applicable. 10.5 Product Dependencies Not applicable. 10.5.1 I/O Lines Not applicable. 10.5.2 Power Management The CMCC will continue to function as long as the CPU is not sleeping and the CMCC is enabled. 10.5.3 Clocks The CMCC interfaces with the CPU through the AHB (SYS_CLK) and is connected to the APB bus (PB2_CLK) interface for its configuration. 10.5.4 DMA Not applicable. 10.5.5 Interrupts Not applicable. 10.5.6 Events Not applicable. 10.5.7 Debug Operation When the CPU is halted in debug mode, the CMCC is halted. Any read access by the debugger in cached zones are not cached. 10.5.8 Register Access Protection Not applicable. 10.5.9 Analog Connections Not applicable. 10.6 Functional Description 10.6.1 Principle of Operation 10.6.2 Initialization and Normal Operation On reset, the cache controller data entries are all invalidated, and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated through the use of its configuration registers. The configuration interface is memory mapped in the APB bus. Use the following sequence to enable the cache controller:

Verify that the CMCC is disabled, reading the value of the SR.CSTS. Enable the CMCC by writing '1' in CTRL.CEN. The MODULE is disabled by writing a '0' in CTRL.CEN. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 143 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.6.3 Change Cache Size It is possible to change the cache size by writing to the Cache Size Configured By Software bits in the Cache Configuration register (CFG.CSIZESW). Use the following sequence to change the cache size:

Disable the CMCC controller by writing a zero to the Cache Controller Enable bit in the Cache Control register

(CTRL.CEN=0). Check the Cache Controller Status bit in the Cache Status register to verify that the CMCC is successfully disabled (SR.CSTS=0). Change CFG.CSIZESW to its new value. Enable the CMCC by writing CTRL.CEN=1. 10.6.4 Data Cache Disable The Instructions alone can be cached by disabling the Data cache, as described in the following steps:

1. Disable the cache controller by writing a 0 to CTRL.CEN. 2. Check SR.CSTS to verify whether the CMCC is successfully disabled. 3. Write CFG.DCDIS = 1. 4. Enable the CMCC by writing CTRL.CEN = 1. 10.6.5 Instruction Cache Disable The Data alone can be cached by disabling the Instruction cache, as described in the following steps:

1. Disable the cache controller by writing CTRL.CEN = 0. 2. Check SR.CSTS to verify that the CMCC is successfully disabled. 3. Write CFG.ICDIS = 1. 4. Enable the CMCC by writing CTRL.CEN = 1. 10.6.6 Cache Load and Lock It is possible to lock a specific way for code optimization by writing the Lock Way register (LCKWAY.LCKWAY). The locked way will not be updated by the CMCC as part of cache operations. The load and lock mechanism can be implemented to use cache memory in a deterministic way. Follow these steps to load and lock a way:

1. Disable cache controller by clearing the CTRL.CEN bit. 2. Invalidate the desired WAY line by line. This will reset the round robin algorithm of the invalidated line, that will become eligible for the next load operation. 3. Disable the Instruction cache, but keep the Data cache enabled. 4. 5. Enable the cache by setting the CTRL.CEN bit. Place the respective piece of code and/or data to the corresponding WAY due to simple LOAD operations. Loading the piece of code and/or data will force the cache to refill the previous invalidated line in the right way. No need to load all the bytes of the line, only the first byte. The cache will automatically refill the complete line. Lock the specific WAY by setting LCKWAY.LCKWAY[3:0]. 6. 7. Re-enable the instruction cache. The locked WAY is now loaded and ready to operate. The remaining WAYS can be used as I-cache or D-cache as required. 10.6.7 Tightly Coupled Memory Users can use a part of the cache as Tightly Coupled Memory (TCM). The cache size is determined by the Cache Size Configuration by Software bits in the Cache Configuration register (CFG.CSIZESW). The relation between cache and TCM is as given below:

TCM size = maximum Cache size - configured Cache size. The TCM start address can be obtained from the product memory mapping. The cache memory starts first from the address followed by the TCM memory. Size of the Way is fixed and the number of ways varies according to the available size for the cache memory. See Product Memory Mapping Overview from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 144 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) Table 10-1. TCM Sizes Max. Cache Configured Cache TCM Size 4 KB 4 KB 4 KB 4 KB 4 KB 2 KB 1 KB 0 KB 0 KB 2 KB 3 KB 4 KB The TCM is also accessible in its maximum size when the CMCC is disabled. The TCM does not need to be locked in order to operate. Note:Writing into the cache DATA RAM region through the CPU can overwrite the valid cache lines. This can result in data corruption when the cache controller is accessing the data for cache transactions. Access the DATA RAM region only after configuring it as TCM. Related Links 7. Product Memory Mapping Overview 10.6.8 Cache Maintenance 10.6.8.1 Cache Invalidate by Line Operation When an invalidate by line command is issued, the CMCC resets the valid bit information of the decoded cache line. As the line is no longer valid, the replacement counter points to that line. Disable the cache controller by writing a zero to the Cache Controller Enable bit in the Cache Control register

(CTRL.CEN). Check SR.CSTS to verify that the CMCC is successfully disabled. Perform an invalidate by line by writing the set {index,way} in the Cache Maintenance 1 register

(MAINT1.INDEX, MAINT1.WAY). Enable the CMCC by writing a '1' to CTRL.CEN. 10.6.8.2 Cache Invalidate All Operation Use the following sequence to invalidate all cache entries. Disable the cache controller by writing a zero to the Cache Enable bit in the Cache Control register

(CTRL.CEN). Check SR.CSTS to verify that the CMCC is successfully disabled. Perform a full invalidate operation by writing a '1' to the Cache Controller Invalidate All bit in the Cache Maintenance 0 register (MAINT0.INVALL). Enable the CMCC by writing a '1' to CTRL.CEN. 10.6.9 Cache Performance Monitoring The Cortex M cache controller includes a programmable monitor/32-bit counter. The monitor can be configured to count the number of clock cycles, the number of data hit or the number of instruction hit. It is important to know that the Cortex-M4 processor prefetches instructions ahead of execution. It performs only 32-bit read access on the Instruction Bus, which means:

One arm instruction is fetched per bus access Two thumb instructions are fetched per bus access As a consequence, two thumb instructions (e.g., NOP) need one bus access, which results in the HIT counter incrementing by 1. Use the following sequence to activate the counter:

Configure the monitor counter by writing the MCFG.MODE. CYCLE_COUNT is used to increment the counter along with the program counter, to count the number of cycles. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 145 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) IHIT_COUNT is the instruction Hit counter, which increments the counter when there is a hit for the instruction in the cache. DHIT_COUNT is the data Hit counter which increments the counter when there is a hit for the data in the cache. Enable the counter by writing a '1' to the Cache Controller Monitor Enable bit in the Cache Monitor Enable register (MEN.MENABLE). If required, reset the counter by writing a '1' to the Cache Controller Software Reset bit in the Cache Monitor Control register (MCTRL.SWRST). Check the value of the monitor counter by reading the MSR.EVENT_CNT bit field. 10.7 DEBUG Mode In Debug mode, TAG and METADATA RAM blocks content is read/written through the AHB bus interface if the CMCC is disabled. When the CMCC is enabled, the TAG and METADATA RAM blocks are non readable. Debug access has the same R/W properties as the CPU access for the DATA RAM block. The TAG, METADATA and DATA RAM blocks' R/W properties are summarized in RAM Properties. Use the following sequence to perform read access with the Debugger to the three RAM blocks:

Disable the cache controller by writing a zero to the Cache Controller Enable bit in the Cache Control register

(CTRL.CEN). Check the Cache Controller Status bit in the Cache Status register (SR.CSTS) to verify that the CMCC is successfully disabled. Perform a read or write access through Debugger:

@ CMCC_AHB_ADDR for DATA RAM,

@ CMCC_AHB_ADDR_TAG for TAG RAM,

@ CMCC_AHB_ADDR_MTDATA for METADATA RAM. If a write access has been performed in the TAG, METADATA, or DATA RAM in the cache section, an invalid operation must be performed before re-enabling the CMCC. Related Links 10.9. RAM Properties 10.8 DFT Mode In DFT mode, TAG and METADATA RAM blocks content is R/W through the AHB bus interface if the CMCC is disabled. When the CMCC is enabled, the TAG and METADATA RAM blocks are non readable. DFT access has the same R/W properties than CPU access for the DATA RAM block. The TAG, METADATA and DATA RAM blocks R/W properties are summarized in a specific chapter. Use the following sequence to read/write the three RAM blocks:

Disable the cache controller by writing a zero to the Cache Controller Enable bit in the Cache Control register

(CTRL.CEN). Check the Cache Controller Status bit in the Cache Status register (SR.CSTS) to verify that the CMCC is successfully disabled. Enable DSU Test mode. Perform a read or write access through CPU:

@ CMCC_AHB_ADDR for DATA RAM,

@ CMCC_AHB_ADDR_TAG for TAG RAM,

@ CMCC_AHB_ADDR_MTDATA for METADATA RAM. If a write access has been performed in the TAG, METADATA, or DATA RAM in the cache section, an invalid operation must be performed before re-enabling the CMCC. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 146 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) Related Links 10.9. RAM Properties 10.9 RAM Properties The following table shows the different access properties of the three RAM blocks, according the different modes described in the previous chapters. Table 10-2. Access to RAM Access Condition DATA RAM TAG RAM METADATARAM CPU access when CMCC DISABLED R/W no R/W - hardfault no R/W - hardfault CPU access when CMCC ENABLED CACHE section configured: R/W(1) TCM section configured: R/W no R/W - hardfault no R/W - hardfault Debugger access when CMCC DISABLED R/W R/W R/W Debugger access when CMCC ENABLED CACHE section configured: R/W(1) TCM section configured: R/W no R/W no R/W CPU Test access when CMCC DISABLED R/W R/W R/W CPU Test access when CMCC ENABLED CACHE section configured: R/W(1) TCM section configured: R/W no R/W no R/W Note:

1. A write operation in this zone can corrupt the coherency of the cache. An invalidate operation may be needed. Related Links 10.7. DEBUG Mode 10.8. DFT Mode 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 147 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.10 Register Summary See CMCC module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 LCKDOWN WAYNUM[1:0]

4 RRP CLSIZE[2:0]

3 2 1 LRUP RANDP GCLK 0 AP CSIZE[2:0]

0x00 TYPE 0x04 CFG 0x08 CTRL 0x0C SR 0x10 LCKWAY 0x14

... 0x1F Reserved 0x20 MAINT0 0x24 MAINT1 0x28 MCFG 0x2C MEN 0x30 MCTRL 0x34 MSR 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 CSIZESW[2:0]

DCDIS ICDIS GCLKDIS LCKWAY[3:0]

CEN CSTS INVALL INDEX[7:4]

MODE[1:0]

MENABLE SWRST INDEX[3:0]

WAY[3:0]

EVENT_CNT[7:0]

EVENT_CNT[15:8]

EVENT_CNT[23:16]

EVENT_CNT[31:24]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 148 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 149 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.1 Cache Type Name:

Offset:

Reset:

Property: R TYPE 0x00 0x000012D2 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 Access Reset Bit Access Reset 7 LCKDOWN R 1 6 R 1 WAYNUM[1:0]

Bits 13:11 CLSIZE[2:0]Cache Line Size R 0 5 R 0 12 CLSIZE[2:0]

R 1 4 RRP R 1 11 R 0 3 LRUP R 0 10 R 0 2 RANDP R 0 9 CSIZE[2:0]

R 1 1 GCLK R 1 8 R 0 0 AP R 0 This field configures the Cache Line Size. 0x02 is the value read for PIC32CX-BZ3 devices, as cache line size is 16 bytes. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Description Cache Line Size is 4 bytes Cache Line Size is 8 bytes Cache Line Size is 16 bytes Cache Line Size is 32 bytes Cache Line Size is 64 bytes Cache Line Size is 128 bytes Reserved Name CLSIZE_4B CLSIZE_8B CLSIZE_16B CLSIZE_32B CLSIZE_64B CLSIZE_128B

Bits 10:8 CSIZE[2:0]Cache Size This bit field configures the cache size. 0x02 is the value read for PIC32CX-BZ3 devices, as cache size is 4 KB. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Cache Size is 1 KB Cache Size is 2 KB Cache Size is 4 KB Cache Size is 8 KB Cache Size is 16 KB Cache Size is 32 KB Cache Size is 64 KB Reserved Name CSIZE_1KB CSIZE_2KB CSIZE_4KB CSIZE_8KB CSIZE_16KB CSIZE_32KB CSIZE_64KB

Bit 7 LCKDOWNLock Down Supported Value 0 1 Description Lockdown is not supported Lockdown is supported 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 150 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) Bits 6:5 WAYNUM[1:0]Number of Way This bit field configures the mapping of the cache. 0x02 is the value read for PIC32CX-BZ3 devices, as the device supports 4-Way set associative. Name Value DMAPPED 0x0 ARCH2WAY 0x1 ARCH4WAY 0x2 ARCH8WAY 0x3 Description Direct Mapped Cache 2-WAY set associative 4-WAY set associative 8-WAY set associative Bit 4 RRPRound Robin Policy Supported Value 0 1 Description Round Robin Policy is not supported Round Robin Policy is supported Bit 3 LRUPLeast Recently Used Policy Supported Value 0 1 Description Least Recently Used Policy is not supported Least Recently Used Policy is supported Bit 2 RANDPRandom Selection Policy Supported Value 0 1 Description Random victim selection is not supported Random victim selection is supported Bit 1 GCLKDynamic Clock Gating Description Cache controller does not support clock gating Cache controller uses dynamic clock gating Value 0 1 Bit 0 APAccess Port Access Allowed Value 0 1 Description Access Port Access is disabled Access Port Access is enabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 151 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.2 Cache Configuration Name:

Offset:

Reset:

Property: R/W CFG 0x04 0x00000020 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 Access Reset 6 R/W 0 5 CSIZESW[2:0]

R/W 1 4 R/W 0 3 2 DCDIS R/W 0 1 ICDIS R/W 0 0 GCLKDIS R/W 0 Bits 6:4 CSIZESW[2:0]Cache Size Configured by Software This field configures the cache size. Value 0x0 0x1 0x2 0x3 Name CONF_CSIZE_1KB CONF_CSIZE_2KB CONF_CSIZE_4KB Description The Cache Size is configured to 1 KB The Cache Size is configured to 2 KB The Cache Size is configured to 4 KB Reserved Bit 2 DCDISData Cache Disable Writing a 0 to this bit enables data caching. Writing a 1 to this bit disables data caching. Bit 1 ICDISInstruction Cache Disable Writing a 0 to this bit enables instruction caching. Writing a 1 to this bit disables instruction caching. Bit 0 GCLKDISGCLK Dynamic Clock Gating Writing a 0 to this bit disables the Dynamic Clock Gating feature. Writing a 1 to this bit enables the Dynamic Clock Gating feature. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 152 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.3 Cache Control Name:

Offset:

Reset:

Property: Write-only CTRL 0x08 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 CENCache Controller Enable Writing a '0' to this bit disables the CMCC. Writing a '1' to this bit enables the CMCC. 9 1 8 0 CEN W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 153 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.4 Cache Status Name:

Offset:

Reset:

Property: Read-only SR 0x0C 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 CSTSCache Controller Status Writing to this bit has no effect. Reading 0 shows CMCC is disabled. Reading 1 shows CMCC is enabled. 9 1 8 0 CSTS R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 154 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.5 Cache Lock per Way Name:

Offset:

Reset:

Property: Read/Write LCKWAY 0x10 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset Bits 3:0 LCKWAY[3:0]Lockdown Way Register This field selects which way is locked. 3 R/W 0 9 1 8 0 2 LCKWAY[3:0]

R/W 0 R/W 0 R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 155 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.6 Cache Maintenance 0 Name:

Offset:

Reset:

Property: Write-only MAINT0 0x20 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 INVALLCache Controller Invalidate All Writing a '0' to this bit has no effect. Writing a '1' to this bit invalidates all cache entries. 9 1 8 0 INVALL W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 156 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.7 Cache Maintenance 1 Name:

Offset:

Reset:

Property: Write-only MAINT1 0x24 0x00000000 31 W 0 23 Bit Access Reset Bit Access Reset 30 W 0 22 WAY[3:0]

29 W 0 21 28 W 0 20 27 26 25 24 19 18 17 16 Bit 15 14 13 12 Access Reset Bit Access Reset 7 W 0 INDEX[3:0]

6 W 0 5 W 0 4 W 0 11 W 0 3 INDEX[7:4]

10 W 0 2 9 W 0 1 8 W 0 0 Bits 31:28 WAY[3:0]Invalidate Way Value 0x0 0x1 0x2 0x3 0x4-0xF Name WAY0 WAY1 WAY2 WAY3 Description Way 0 is selection for index invalidation Way 1 is selection for index invalidation Way 2 is selection for index invalidation Way 3 is selection for index invalidation Reserved Bits 11:4 INDEX[7:0]Invalidate Index This field selects the index value for invalidation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 157 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.8 Cache Monitor Configuration Name:

Offset:

Reset:

Property: Read/Write MCFG 0x28 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset 9 1 8 0 MODE[1:0]

R/W 0 R/W 0 Bits 1:0 MODE[1:0]Cache Controller Monitor Counter Mode This field selects the type of data monitored. Value 0x0 0x1 0x2 0x3 Name CYCLE_COUNT IHIT_COUNT DHIT_COUNT Description Cycle counter Instruction hit counter Data hit counter Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 158 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.9 Cache Monitor Enable Name:

Offset:

Reset:

Property: Read/Write MEN 0x2C 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 MENABLECache Controller Monitor Enable Writing a 0 to this bit disables the monitor counter. Writing a 1 to this bit enables the monitor counter. 9 1 8 0 MENABLE R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 159 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.10 Cache Monitor Control Name:

Offset:

Reset:

Property: Write-only MCTRL 0x30 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 SWRSTCache Controller Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the event counter register. 9 1 8 0 SWRST W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 160 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Cortex M Cache Controller (CMCC) 10.11.11 Cache Monitor Status Name:

Offset:

Reset:

Property: Read-only MSR 0x34 0x00000000 Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 EVENT_CNT[31:24]

R R 0 0 20 19 EVENT_CNT[23:16]

R R 0 0 11 12 EVENT_CNT[15:8]

R R 0 0 4 3 EVENT_CNT[7:0]

R R 0 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 EVENT_CNT[31:0]Monitor Event Counter This field indicates the Monitor Event Counter value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 161 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11. Flash Controller (FC) 11.1 Overview The PIC32CX-BZ3 devices contain a single bank of Flash memory with their Program Flash Memory (PFM) partition and Boot Flash Memory (BFM) partition for storing user code or non-volatile data. The Flash controller is used to access the Flash memory. The peripheral bus interface is used for commands and configuration of the Flash controller. 11.2 Features Flash Controller PB-Bridge-D interface that provides access to the Flash controller registers AHB Initiator for bus hosted reads the row programming data from SRAM Write Protect for Program Flash (PFM) Single page protection resolution Protect Less Than Address Protect Greater Than or Equal to Address Individual page write protection for boot Flash (BFM) Error-correction code (ECC) support Supports chip and page erase Supports Single Word, Quad Word and row program options Supports flash Erase/Retry to increase Retention and Endurance Flash Memory 128-bit wide Flash Memory Access 4 Kbytes page size Row size is 1 KB (256 IW) Flash-based OTP (one-time-programmable) page The Flash controller allows the Flash memory to be accessed through the following methods:

1. Run-Time Self-Programming (RTSP) 2. Serial Wire Debug (SWD) programming using DSU (See Device Service Unit (DSU) from Related Links and PIC32CX-BZ3 Programming Specification.) Related Links 12. Device Service Unit (DSU) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 162 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.3 Functional Block Diagram Figure 11-1. Flash Memory Block Diagram NVMDATA3[31:0]

NVMDATA2[31:0]

NVMDATA1[31:0]

NVMDATA0[31:0]

Word/Quad word:0 Row:1 0 1 0 1 0 1 0 1 FC Program Data Buffer pgm data 3 pgm data 2 pgm data 1 pgm data 0 r e f f u B B H A AHB Initiator Flash Controller Flash Wrapper 11 10 01 00 Flash Memory Word 3 Word 2 Word 1 Word 0 Row/Quad word 0:NVMADDR[3:2]

Word:2'b0 ECC Parity/Control NVMADDR[3:2]

NVMADDR[31:4]

11.4 Product Dependencies Not applicable. 11.4.1 I/O Lines Not applicable. 11.4.2 Power Management The Flash Controller does not operate in power-saving/ low power/sleep modes. If a WAIT instruction is encountered when programming, the CPU will stop execution (stall), wait for the programming operation to complete, then enter the Power-Saving/low power mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 163 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.4.3 Clocks AHB (SYS_CLK) Initiator for bus mastered reads of row programming data from system FlexRAM. PB1_CLK bus clock is used for control register access. 11.4.4 DMA Not applicable. 11.4.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the Flash controller interrupt(s) requires the NVIC interrupt controller to be configured first. 11.4.6 Events Not applicable. 11.4.7 Debug Operation Programming operations will continue to completion if the processor execution is halted in Debug mode. 11.4.8 Register Access Protection Not applicable. 11.4.9 Analog Connections Not applicable. 11.5 Flash Memory Addressing Flash memory addressing uses physical addresses only. For more information on addressing, see Product Memory Mapping Overview from Related Links. Related Links 7. Product Memory Mapping Overview 11.6 Memory Configuration 11.6.1 Flash Memory Construction Flash memory is divided into pages. A page is the smallest unit of memory that can be erased at one time. Each page of memory is segmented into four rows. A row is the largest unit of memory that can be programmed at one time. A row consists of 64 Quad (128-bit) Word. Each Quad Word consists of a four instruction (32-bit) Word. Flash memory can be programmed in rows, Quad Word (128-bit) or Single Word (32-bit) units. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 164 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Figure 11-2. Flash Construction Flash Bank consisting of n pages Flash Bank Page n Page 3 Page 2 Page 1 Page 0 Each page consists of 4 rows Each Quad Word consists of 4 instruction (32-bit) word Row 3 Row 2 Row 1 Row 0 Word 3 Word 1 Word 0 QW 63 QW 1 QW 0 Each row consists of 64 quad (128-bit) words 11.6.2 Flash Memory Organization The Device Flash memory is divided into two logical Flash partitions:

1. Main Program Flash Memory (PFM) 2. Boot Flash Boot/Configuration Flash Memory (BFM) a. b. Device/Boot Configuration Device and boot configuration data c. OTP (One Time Programmable) User system calibration data Each Flash section has a different protection status; refer to the following table. Table 11-1. Protection Status Flash Partition Memory Region Write Protection Erase Protection Chip Erase through DSU BFM Boot Flash Device/Boot Configuration OTP (One-Time-

Programmable) Yes. Page-wise Configurable Yes. Page-wise Configurable Erased Yes. Configurable Yes. Configurable Erased Yes. Configurable Always Erase protected. Can not be erased Not Erased PFM Program Flash Yes. Configurable Yes. Configurable Erased 11.7 Boot Flash Memory (BFM) Partitions 11.7.1 BFM Write Protection Pages in the BFM regions can be protected individually using bits in the NVMLBWP register. At Reset, all pages are in a write-protected state and must be disabled prior to performing any programming operations on the BFM regions. There is also an unlock bit, ULOCK(NVMLBWP[31]), that is set at Reset and can be cleared by the user software. When cleared, changes to write protection for that region can no longer be made. Once cleared, the ULOCK bit can only be set by a Reset. The NVMLBWP write-protect register can only be changed when the unlock sequence is followed. See NVMKEY Register Unlocking Sequence from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 165 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Related Links 11.12. NVMKEY Register Unlocking Sequence 11.8 Program Flash Memory (PFM) Partitions 11.8.1 PFM Write Protection Write protection for the PFM region is implemented by pages, defined by the NVMPWPLT and NVMPWPGTE registers. The NVMPWP* registers define an area within the program space (PFM) that is write-protected. This write-protected address resolves to Flash page boundaries; therefore, the 12 LSBs for a 4 KB page Flash of any address written to the NVMPWP* registers are ignored. The width of each NVMPWP* address register is determined by the size of the Flash. The NVMPWPLT register is used to set the Program Flash pages lower than the provided address as write-protected. The NVMPWPGTE register is used to set the Program Flash pages greater than or equal to the provided address as write-protected. Therefore, a value of all 0s in the NVMPWPLT register and all 1s in the NVMPWPGTE register results in no region of Flash being write-protected (default state at Reset). There is also an unlock bit, ULOCK (NVMPWPLT [31] and NVMPWPGTE[31]), that is set at Reset and can be cleared by the user software. When cleared, changes to the write-protection of the PFM can no longer be made, including the ULOCK bit. The NVMPWPLT and NVMPWPGTE write-protected register can only be changed when the unlock sequence is followed. See NVMKEY Register Unlocking Sequence from Related Links. Related Links 11.12. NVMKEY Register Unlocking Sequence 11.9 Error Correcting Code (ECC) and Flash Programming The PIC32CX-BZ3 devices incorporate Error Correcting Code (ECC) features that detect and correct errors resulting in extended Flash memory life. For more details on this feature, see Prefetch Cache from Related Links. ECC is implemented in 128-bit Quad Flash Words or 32-bit Single Word. As a result, when programming Flash memory on a device where ECC is employed, the programming operation must be, at minimum, four instruction Words or in groups of four instruction Words. This is the reason that the Quad Word programming command exists and why row programming always programs multiples of four Words. For a given software application, ECC can be enabled at all times, disabled at all times or dynamically enabled using the ECCCTL Configuration bits in the CFGCON0 register. When ECC is enabled at all times, the Single Word NVMOP programming command does not function and the Quad Word is the smallest unit of memory that can be programmed. When ECC is disabled or enabled dynamically, both the Single Word and Quad Word programming NVMOP commands are functional and the programming method used determines how ECC is handled. In the case of dynamic ECC, if the memory was programmed with the Singe Word command, ECC is turned off for that Word, and, when it is read, no error correction is performed. If the memory was programmed with the Quad Word or Row Programming commands, ECC data is written and tested for errors (and corrected if needed) when read. The following table describes the different ECC scenarios. Table 11-2. ECC Programming Summary ECCCTL Setting Programming Operation Data Read Single Word Write Quad Word Write Row Write Disabled Allowed Allowed Allowed Enabled Not allowed Allowed Allowed ECC is never applied on a Flash read ECC is applied on every Flash Word read 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 166 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC)

...........continued ECCCTL Setting Programming Operation Data Read Single Word Write Quad Word Write Row Write Dynamic Allowed but when used, the programmed word is flagged to NOT USE ECC Writes ECC data and flags programmed words to USE ECC Writes ECC data and flags programmed words to USE ECC ECC is only applied on words that are flagged to USE ECC Note:When using dynamic ECC, all non-ECC locations must be programmed with the 32-bit Word programming command, while all ECC-enabled locations must be programmed with a 128-bit Quad Word or Row programming command. Divisions between ECC and non-ECC memory must be on even Quad Word boundaries (address bits 0 through 3 are equal to 0). Related Links 9. Prefetch Cache (PCHE) 11.10 Interrupts An interrupt is generated when the WR bit is cleared by the Flash Controller upon completion of a Flash program or erase operation. The interrupt event will cause a CPU interrupt if it was configured and enabled in the Nested Interrupt Vector Controller. See Nested Vector Interrupt Controller (NVIC) from Related Links for the vector mapping table. The interrupt occurs regardless of the outcome of the program or erase operation, successful or unsuccessful. The only exception is the No Operation (NOP) programming operation (NVMOP = 0), which is used to manually clear the error flags and does not create an interrupt event on completion but does clear the WR bit. The Flash Controller interrupts are not persistent, and, therefore, no additional steps are required to clear the cause or source of the interrupt. Once the Interrupt Controller is configured, the Flash event causes the CPU to jump to the vector assigned to the Flash event. The CPU starts executing the code at the vector address. The user software at this vector address must perform the required operations and, then, exit. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 11.10.1 Interrupts and CPU Stalling Code cannot be fetched by the CPU from the same Flash bank, either BFM or PFM, that is the target of the programming operation. When this operation is attempted, the CPU will cease to execute code (stall) while the programming operation is in progress. CPU code execution does not resume until the programming operation is complete, and, when this occurs, any pending interrupts, including those from the Flash Controller, will be processed in order of priority. Note:Code that is already loaded into the processor cache will continue to execute up to the point where an attempt is made to fetch code or data from the same Flash bank as the active programming operation. At this point the CPU will stall. The stalling of the CPU can also be avoided by placing any needed executable code in SRAM during Flash programming. 11.11 Error Detection The NVMCON register includes two bits for detecting error conditions during a program or erase operation. They are Low-Voltage detect error, LVDERR bit (NVMCON[12]), and Write Error, WRERR bit (NVMCON[13]). The WRERR is set each time the WR bit (NVMCON[15]) is set, initiating a programming operation. When the Flash operation is complete, indicated by hardware clearing the value of the WR bit (i.e., WR bit is set to 0), hardware will update the value in the WRERR bit to indicate if an error occurred. Firmware must check the value of the WR bit to 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 167 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) see if the Flash operation completed before checking the value of the WRERR bit. When the WRERR bit is set, any future attempt to initiate programming or erase operation is ignored. WRERR must be cleared before commencing Flash program or erase operations. The LVDERR bit is set when a Brown-out Reset (BOR) occurs during a programming operation. The only Reset that clears the LVDERR bit is a Power-on Reset (POR). Other Reset types do not affect the LVDERR bit. When the LVDERR bit is set, any attempt to initiate programming or erase operation is ignored. The LVDERR bit must be cleared before commencing Flash program or erase operations. Both the WRERR and LVDERR bits must be cleared manually in software by initiating a Flash operation (setting WR) referred to as NOP (0x00) (see the NVMOP bit fields). Note:Executing the NVMOP NOP command clears WRERR, LVDERR and WR bits, but does not generate an interrupt event on completion. Table 11-3. Programming Error Cause and Effects Cause of Error Effect on Programming Erase Operation Indication A low-voltage event occurred during a programming sequence. The last programming or erase operation may not have completed. LVDERR = 1, WRERR = 1 A non-POR Reset occurred during programming. Programming or erase operation is aborted. WRERR = 1 Attempt to program or erase a page out of the Flash memory range. Erase or programming operation is not initiated. WRERR = 1 Attempt to erase or program a write-

protected PFM page. Erase or programming operation is not initiated. WRERR = 1 Attempt to erase or program a write-

protected BFM page. Operation occurs, but the page is not programmed or erased. WRERR = 0 Bus host error or row programming data underrun error during programming. Programming or erase operation is aborted. WRERR = 1 11.12 NVMKEY Register Unlocking Sequence Important register settings that could compromise the Flash memory if inadvertently changed are protected by a register unlocking sequence. This feature is implemented using the NVMKEY register. The NVMKEY register is a write-only register that is used to implement an unlock sequence to help prevent accidental writes or erasures of Flash memory. In some instances, the operation is also dependent on the setting of the WREN bit (NVMCON[14]), as shown in the following table. Table 11-4. NVMKEY Register Unlocking and WREN Operation WREN Setting Unlock Sequence Required Changing value of NVMOP[3:0]

(NVMCON[3:0]) Setting WR (NVMCON[15]) to start a write or erase operation Changing any fields in the NVMPWP* register Changing any fields in the NVMLBWP register 0 1 No Yes Yes Yes 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 168 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) The following steps must be followed in the exact order as shown to enable writes to registers that require this unlock sequence:

1. Write 0x00000000 to NVMKEY. 2. Write 0xAA996655 to NVMKEY. 3. Write 0x556699AA to NVMKEY. 4. Write the value to the register NVMCON, NVMCON2, NVMPWP* or NVMLBWP requiring the unlock sequence. When using the unlock sequence to set or clear bits in the NVMCON register, as shown in Step 4, Steps 2 through 4 must be executed without any other activity on the peripheral bus that is in use by the Flash Controller. Interrupts and DMA transfers that access the same peripheral bus as the Flash Controller must be disabled. In addition, the operation in Step 4 must be atomic. The Set, Clear and Invert registers may be used, where applicable, for the target register in Step 4. The following code shows code written in the C language to initiate a NVM Operation (NVMOP) command. In this particular example, the WR bit is being set in the NVMCON register and, therefore, must include the unlock sequence. Initiate NVM Operation (System Unlock Sequence Example):

void NVMInitiateOperation(void)

// Disable Interrupts asm volatile(di%0 : =r(int_status));

uint32_t globalInterruptState= __get_PRIMASK();

// Disable Interrupts __disable_irq();

NVMKEY = 0x0;

NVMKEY = 0xAA996655;

NVMKEY = 0x556699AA;

NVMCONSET = 1 << 15;// must be an atomic instruction

// Restore Interrupts __set_PRIMASK(globalInterruptState);

Note:Once the unlock codes are written to the NVMKEY register, the next activity on the same peripheral bus as the Flash Controller will Reset the lock. As a result, only atomic operations can be used. Use of the NVMCONSET register sets the WR bit in a single instruction without changing other bits in the register. Using NVMCONbits.WR = 1 will fail, as this line of code compiles to a read-modify-write sequence. 11.13 Word Programming The smallest block of data that can be programmed in a single operation is one Flash write Word (32-bit). The data to be programmed must be written to the NVMDATA0 register, and the address of the Word must be loaded into the NVMADDR register before the programming sequence is initiated. The instruction Word at the physical location pointed to by the NVMADDR register is, then, programmed. Programming occurs on 32-bit Word boundaries;

therefore, bits 0 and 1 of the NVMADDR register are ignored. When a Word is programmed, it must be erased before it can be programmed again, even if changing a bit from an erased 1 state to a 0 state. Word programming will only succeed if the target address is in a page that is not write-protected. Programming to a write-protected PFM page will fail and result in the WRERR bit being set in the NVMCON register. Programming a write-protected BFM page will fail but does not set the WRERR bit. A programming sequence consists of the following steps:

1. Write 32-bit data to be programmed to the NVMDATA0 register. 2. 3. Load the NVMADDR register with the address to be programmed. Set the WREN bit = 1 and NVMOP bits = 1 in the NVMCON register. This defines and enables the programming operation. Initiate the programming operation. (See NVMKEY Register Unlocking Sequence from Related Links.) 4. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 169 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 5. Monitor the WR bit of the NVMCON register to flag completion of the operation. 6. Clear the WREN bit in the NVMCON register. 7. Check for errors and process accordingly. The following code shows code for Word programming, where a value of 0x12345678 is programmed into location 0x1008000. Word Programming Code Example:

// Set up Address and Data Registers NVMADDR= 0x1008000; // physical address NVMDATA0 = 0x12345678; // value

// set the operation, assumes WREN = 0 NVMCONbits.NVMOP = 0x1; // NVMOP for Word programming

// Enable Flash for write operation and set the NVMOP NVMCONbits.WREN = 1;

// Start programming NVMInitiateOperation(); // see Initiate NVM Operation (Unlock Sequence Example)

// Wait for WR bit to clear while (NVMCONbits.WR);

// Disable future Flash Write/Erase operations NVMCONbits.WREN = 0;

// Check Error Status if(NVMCON & 0x3000) // mask for WRERR and LVDERR

// process errors

Related Links 11.12. NVMKEY Register Unlocking Sequence 11.14 Quad Word Programming The process for Quad Word programming is identical to Word programming except that all four of the NVMDATAx registers are used. The value of the NVMDATA0 register is programmed at address NVMADDR, NVMDATA1 at NVMADDR + 0x4, NVMDATA2 at NVMADDR + 0x8, and NVMDATA3 at address NVMDATA + 0xC. Quad Word programming is always performed on a Quad Word boundary; therefore, NVMADDR address bits 3 through 0 are ignored. Quad Word programming will only succeed if the target address is in a page that is not write-protected. When a Quad Word is programmed, it must be erased before any Word in it can be programmed again, even if changing a bit from an erased 1 state to a 0 state. Where a value of 0x11111111 is programmed into location 0x1008000, 0x22222222 into 0x1008004, 0x33333333 into 0x1008008, and 0x44444444 into location 0x100800C. Refer to the following code example for details. Quad Word Programming Code Example:

// Set up Address and Data Registers NVMADDR = 0x1008000; // physical address NVMDATA0 = 0x11111111; // value written to 0x1008000 NVMDATA1 = 0x22222222; // value written to 0x1008004 NVMDATA2 = 0x33333333; // value written to 0x1008008 NVMDATA3 = 0x44444444; // value written to 0x100800C

// set the operation, assumes WREN = 0 NVMCONbits.NVMOP = 0x2; // NVMOP for Quad Word programming 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 170 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC)

// Enable Flash for write operation and set the NVMOP NVMCONbits.WREN = 1;

// Start programming NVMInitiateOperation(); // see Initiate NVM Operation (Unlock Sequence Example)

// Wait for WR bit to clear while(NVMCON & NVMCON_WR);

// Disable future Flash Write/Erase operations NVMCONbits.WREN = 0;

// Check Error Status if(NVMCON & 0x3000) // mask for WRERR and LVDERR bits 11.15 Row Programming The largest block of data that can be programmed is a row. Unlike Word and Quad Word Programming where the data source is stored in SFR memory, Row programming source data is stored in SRAM. The NVMSRCADDR register is a pointer to the physical location of the source data for Row programming. Like other Non-Volatile Memory (NVM) programming commands, the NVMADDR register points to the target address of the operation. Row programming always occurs on row boundaries with the row size of 1024, bits 0 through 9 of the NVMADDR register are ignored. Row Word programming will only succeed if the target address is in a page that is not write-protected. When a row is programmed, it must be erased before any Word in it can be programmed again, even if changing a bit from an erased 1 state to a 0 state. Array rowbuff is populated with data and programmed into a row located at physical address 0x1008000. Note:When assigning the value to the NVMSRCADDR register, it must be converted to a physical address. Row Programming Code Example:

unsigned long rowbuff[256]; // example is for a 256 Word row size. int x; // loop counter

// put some data in the source buffer for (x = 0; x < (sizeof(rowbuff) * sizeof (int)); x++)

((char *)rowbuff)[x] = x;

// set destination row address NVMADDR = 0x1008000; // row physical address

// set source address. Must be converted to a physical address. NVMSRCADDR = (unsigned int)((int)rowbuff & 0x1FFFFFF);

// define Flash operation NVMCONbits.NVMOP = 0x3; // NVMOP for Row programming

// Enable Flash Write NVMCONbits.WREN = 1;

// commence programming NVMInitiateOperation(); // see Initiate NVM Operation (Unlock Sequence Example)

// Wait for WR bit to clear while(NVMCONbits.WR);

// Disable future Flash Write/Erase operations NVMCONbits.WREN = 0;

// Check Error Status if(NVMCON & 0x3000) // mask for WRERR and LVDERR bits

// process errors 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 171 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC)

11.16 Page Erase A Page Erase performs an erase of a single page of either PFM or BFM. The page to be erased is selected using the NVMADDR register. Pages are always erased on page boundaries;

therefore, for a device with an instruction Word page size of 4096, bits 0 through 11 of the NVMADDR register are ignored. A Page Erase will only succeed if the target address is a page that is not write-protected. Erasing a write-protected page will fail and result in the WRERR bit being set in the NVMCON register. The following code shows the code for a single Page Erase operation at address 0x1008000. Page Erase Code Example:

// set destination page address NVMADDR = 0x1008000; // page physical address

// define Flash operation NVMCONbits.NVMOP = 0x4; // NVMOP for Page Erase

// Enable Flash Write NVMCONbits.WREN = 1;

// commence programming NVMInitiateOperation(); // see Initiate NVM Operation (Unlock Sequence Example)

// Wait for WR bit to clear while(NVMCONbits.WR);

// Disable future Flash Write/Erase operations NVMCONbits.WREN = 0;

// Check Error Status if(NVMCON & 0x3000) // mask for WRERR and LVDERR bits

// process errors

11.16.1 Page Erase Retry Page Erase Retry is a method to improve the life of a Flash by attempting to erase again if the Page Erase was not successful. Page Erase Retry can only be used for a Page Erase. Page Erase Retry works by increasing the voltage used on the Flash when erasing. Initially, the minimum voltage necessary is applied by setting the RETRY[1:0] bits (NVMCON2[9:8]) = 00. If the page erase is not successful, the voltage may be increased by incrementing the setting of the RETRY[1:0] bits. Note:Each Flash page, as it ages and wears, may have different voltage requirements; therefore, a higher setting on one Flash page does not indicate that the same setting must be used on all pages. The maximum voltage for Page Erase is used when the RETRY[1:0] bits = 11. If Page Erase is not successful after 7 trials, this means that the Flash for that page, or the Words that did not erase, must be considered non-functional. Together with the normal Page Erase controls, Page Erase Retry also uses the WS[4:0], CREAD1, VREAD1 and RETRY[1:0] bits in the NVMCON2 register. The ERS[3:0] bits (NVMCON2[31:28]) are for the benefit of software performing the programming sequence in the event that a drop in power causes a BOR event but not a POR event. Perform the following steps to set up a Page Erase Retry:

1. 2. 3. Set the NVMADDR register with the address of the page to be erased. Execute the write unlock sequence. Save the value of the NVMCON2 register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 172 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 4. Do the following in the NVMCON2 register:

a. b. c. d. e. Set the ERS[3:0] bits as desired. Set the WS[4:0] bits per the description. Set the VREAD1 bit to 1. Set the CREAD1 bit to 1. Set the RETRY[1:0] bits to 00. 5. Run the unlock sequence using the Page Erase command to start the sequence. 6. Wait for the WR bit (NVMCON[15]) to be cleared by hardware. 7. Clear the WREN bit (NVMCON[14]). 8. Verify the erase using the CPU. To shorten the verify time, use CREAD1 = 1 to perform a hardware compare to logic 1 of each bit in the Flash Word including ECC. A successful compare yields a read of 0x00000001 in the lowest addressed word in a Flash Word (128 bits). This is the Compare Word. All other Words are 0x00010000. If any bit is logic 0, all Words in the Flash Word read 0x00000000. Remember to increment the address by the number of bytes in a Flash Word between reads. If all Compare Words verify correctly, the Page Erase Retry process is complete. Go to step 11. If a Compare Word yields a read of 0x00000000, perform steps 4 through 9 up to six more times with the following change to step 4:

a. Increment the RETRY[1:0] bits by one if the bit has not already reached the 11 setting. 9. 10. b. Maintain all other fields. 11. Restore the value of the NVMCON2 register, which was saved in step 3. Notes:

1. When CREAD1 is set to 1 to perform hardware compare, the compare happens on entire Flash panel (PFM, BFM). Hence, the code which does this page erase retry operation must be executed from SRAM. 2. When the VREAD1 = 1, the Flash uses the WS[3:0] bits for Flash access wait state generation to the panel selected by NVMADDR. Software is responsible for writing the VREAD1 bit back to 0 when both erase and verify is complete. The device configuration boot page (the page containing the DEVCFGx values) does not support Page Erase Retry. 3. The following code provides code for a single page erase operation at address 0x1008000, where Page Erase Retry is used. Page Erase Retry Code Example:

uint32_tsaveNVMCON2;

uint32_t*cmpPtr;

uint8_terased;

uint8_ttryCount;

// set destination page address NVMADDR = 0x1008000; // Page physical address

// define flash operation NVMCONbits.NVMOP = 0x4; // NVMOP for Page Erase

// Unlock sequence NVMKEY = 0x0;

NVMKEY = 0xAA996655;

NVMKEY = 0x556699AA;

// save NVMCON2 saveNVMCON2 = NVMCON2;

// set up Page Erase Retry NVMCON2bits.ERS = 0; // Stage 0 - SW use only NVMCON2bits.VREAD1 = 1;

NVMCON2bits.CREAD1 = 1;

NVMCON2bits.RETRY = 0b00;

tryCount = 0; // Up to 4 attempts do {

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 173 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) tryCount++;

// commence programming NVMInitiateOperation();

// Wait for WR bit to clear while(NVMCONbits.WR);

// Turn off WREN NVMCONbits.WREN = 0;

// Check that the page was erased erased = 1;

cmpPtr = (uint32_t *)NVMADDR;

erased &= (*cmpPtr == 0x00000001);

cmpPtr++;

erased &= (*cmpPtr == 0x00010000);

cmpPtr++;

erased &= (*cmpPtr == 0x00010000);

cmpPtr++;

erased &= (*cmpPtr == 0x00010000);

if (!erased) {

// Erase failed. Try with different settings. NVMCON2bits.RETRY++;

NVMCONbits.NVMOP = 0x4;

NVMCONbits.WREN = 1;

} while (!erased && (tryCount < 4));

// Restore settings NVMCON2 = saveNVMCON2;

11.17 Program Flash Memory (PFM) Erase Program Flash memory can be erased entirely. All three discrete NVMOP values, 0111, 0110, 0101, do the same operation of erase of entire Flash. When erasing the entire PFM area, in case of RTSP (Run Time Self Programming), the code must be executing from BFM. When erasing the entire PFM area, PFM write-protection must be completely disabled. The following code shows code for erasing the entire Flash bank. Program Flash Erase Code Example:

// define Flash operation NVMCONbits.NVMOP = 0x7; // NVMOP for entire PFM erase

// Enable Flash Write NVMCONbits.WREN = 1;

// commence programming NVMInitiateOperation(); // see Initiate NVM Operation (Unlock Sequence Example)

// Wait for WR bit to clear while(NVMCONbits.WR);

// Disable future Flash Write/Erase operations NVMCONbits.WREN = 0;

// Check Error Status if(NVMCON & 0x3000) // mask for WRERR and LVDERR bits

// process errors

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 174 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.18 Pre-Program The PIC32CX-BZ3 Flash supports an option to programming that increases endurance and retention. This feature is called Pre-Program, and it requires the user to perform the programming operation twice, first, with NVMCON2.NVMPREPG = 1 and, secondly, with NVMCON2.NVMPREPG = 0. Any of the programming operations

(Single, Quad, Row) can be performed with this method. In all other respects, the SFR setup is identical. To use this feature, set or clear the NVMCON2.NVMPREPG SFR bit prior to setting the NVMWR bit. Pre-Program, typically double, the native Endurance and Retention of the Flash. 11.19 Device Code Protection bit (CP) The PIC32CX-BZ3 family of devices features code protection, which, when enabled, prevents reading of the Flash memory by an external programming device (SWD through DSU). When code protection is enabled, it can only be disabled by erasing the device with the Chip Erase command through an external programmer. See Device Service Unit (DSU) from Related Links. When programming a device that has opted to utilize code protection, the external programming device must perform verification prior to enabling code protection. Enabling code protection must be the last step of the programming process. For the location of the code protection enable bits, refer to PIC32CX-BZ3 Programming Specification and System Configuration Registers (CFG) from Related Links. Related Links 12. Device Service Unit (DSU) 18. System Configuration and Register Locking (CFG) 11.20 Effects of Various Resets Device Resets, other than a Power-on Reset (POR), reset the entire contents of the NVMPWP and NVMLBWP registers. All other register content persists through a non-POR reset. All Flash Controller registers are forced to their reset states upon a POR. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 175 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.21 Register Summary See FC module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 NVMCON 0x04

... 0x0F Reserved 0x10 NVMCON2 0x14

... 0x1F Reserved 0x20 NVMKEY 0x24

... 0x2F Reserved 0x30 NVMADDR 0x34

... 0x3F Reserved 0x40 NVMDATA0 0x44

... 0x4F Reserved 0x50 NVMDATA1 0x54

... 0x5F Reserved 0x60 NVMDATA2 0x64

... 0x6F Reserved 0x70 NVMDATA3 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 WR WREN WRERR LVDERR NVMOP[3:0]

TEMP CREAD1 VREAD1 ERS[3:0]

WS[4:0]

NVMPREPG RETRY[1:0]

SLEEP NVMKEY[7:0]

NVMKEY[15:8]

NVMKEY[23:16]

NVMKEY[31:24]

NVMADDR[7:0]

NVMADDR[15:8]

NVMADDR[23:16]

NVMADDR[31:24]

NVMDATA[7:0]

NVMDATA[15:8]

NVMDATA[23:16]

NVMDATA[31:24]

NVMDATA[7:0]

NVMDATA[15:8]

NVMDATA[23:16]

NVMDATA[31:24]

NVMDATA[7:0]

NVMDATA[15:8]

NVMDATA[23:16]

NVMDATA[31:24]

NVMDATA[7:0]

NVMDATA[15:8]

NVMDATA[23:16]

NVMDATA[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 176 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x74

... 0xBF Reserved 0xC0 NVMSRCADDR 0xC4

... 0xCF Reserved 0xD0 NVMPWPLT 0xD4

... 0xDF Reserved 0xE0 NVMPWPGTE 0xE4

... 0xEF Reserved 0xF0 NVMLBWP 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ULOCK ULOCK ULOCK Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 11.22 Register Description NVMSRCADDR[7:0]

NVMSRCADDR[15:8]

NVMSRCADDR[23:16]

NVMSRCADDR[31:24]

PWPLT[7:0]

PWPLT[15:8]

PWPLT[23:16]

PWPGTE[7:0]

PWPGTE[15:8]

PWPGTE[23:16]

LBWP[7:0]

LBWP[15:8]

LBWP[23:16]

Flash program, erase, and write protection operations are controlled using the following Non-Volatile Memory (NVM) control registers:

NVMCON: Programming Control Register This register is the control register for Flash program/erase operations. This register is used to select the operation to be performed, initiate the operation, and provide status of the result when the operation is complete. NVMCON2: Programming Control2 Register This register is the control and status register for Flash program/erase operations. NVMKEY: Programming Unlock Register This is a write-only register that is used to implement an unlock sequence to help prevent accidental writes/

erasures of Flash memory and write permission settings. NVMADDR: Flash Address Register This register is used to store the physical target address for row, Quad Double Word and Single Double Word programming as well as page erasing. NVMDATAx: Flash Program Data Register (x = 0-3) These registers hold the data to be programmed during Flash Word program operations. NVMSRCADDR: Source Data Address Register This register is used to point to the physical address of the data to be programmed when executing a row program operation. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 177 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) NVMPWPLT: Flash Program Write Protect Lower Register This register is used to set the program flash pages lower than provided address as a write protected. NVMPWPGTE: Flash Program Write Protect Greater Register This register is used to set the program flash pages greater than provided address as a write protected. NVMLBWP: Flash Boot Write Protect Register This register is used to set the boot flash partition pages as a write protected. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 178 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.1 NVMCON - Programming Control Register Name:

Offset:

Reset:

Property:

NVMCON 0x00 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset 15 WR R/HS/HC 0 14 WREN R/W 0 13 WRERR R/HS/HC 0 12 LVDERR R/HS/HC 0 11 10 Bit 7 6 5 4 Access Reset Bit 15 WR Write Control Bit(1) 3 R/W 0 9 1 8 0 2 NVMOP[3:0]

R/W 0 R/W 0 R/W 0 Note:This field can only be modified when WREN = 1, TEMP = 1, and the NVMKEY unlock sequence is satisfied. Value 1 0 Description Initiate a Flash operation. Hardware clears this bit when the operation completes Flash operation complete or inactive Bit 14 WREN Write Enable Bit(1) Description Enables writes to WR Disables writes to WR Value 1 0 Bit 13 WRERR Write Error Bit(1) Note:Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR). Value 1 0 Description Program or erase sequence did not complete successfully Program or erase sequence completed normally Bit 12 LVDERR Low Voltage Detect Error Bit(1) The error is only captured for programming/erase operations (when WR = 1). Note:Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR). Value 1 0 Description Low voltage is detected (possible data corruption if WRERR is set) Normal voltage is detected Bits 3:0 NVMOP[3:0]NVM Operation bits These bits are only writable when WREN = 0. Value 1111 Description Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 179 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Description Chip Erase Operation: Erases PFM, BFM (except configuration page) when accessed through SWD interface only Reserved Program erase operation: erase all of program Flash memory (PFM) (all pages must be unprotected) Upper program Flash memory erase operation: erases only the upper mapped region of program Flash

(all pages in that region must be unprotected). Its a single bank flash in PIC32CX-BZ3, so this NVMOP performs same as NVMOP = 0111. Lower program Flash memory erase operation: erases only the lower mapped region of program Flash

(all pages in that region must be unprotected). Its a single bank flash in PIC32CX-BZ3, so this NVMOP performs same as NVMOP = 0111. Page erase operation: erases page selected by NVMADDR, if it is not write-protected Row program operation: programs row selected by NVMADDR, if it is not write-protected Quad Word (128-bit) program operation: programs the 128-bit Flash Word selected by NVMADDR, if it is not write-protected Word program operation: programs word selected by NVMADDR, if it is not write-protected(2) No operation Value 1110

... .. 1000 0111 0110 0101 0100 0011 0010 0001 0000 Notes:

1. 2. These bits are only reset by a POR and are not affected by other Reset sources. This operation results in a No Operation (NOP) when the Dynamic Flash ECC Configuration bits = 00

(ECCCTL[1:0](CFGCON0[29:28])), which enables ECC at all times. For all other ECCCTL[1:0]bit settings, this command will execute, but will not write the ECC bits for the Word. It can cause DED (Double-bit Error Detected) errors if dynamic Flash ECC is enabled (ECCCTL[1:0] = 01). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 180 Microchip Confidential Confidential 11.22.2 NVMCON2 - Programming Control 2 Register Name:

Offset:

Reset:

Property:

NVMCON2 0x10 0x011F4000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset Bit 15 Access Reset ERS[3:0]

30 R/W 0 22 29 R/W 0 21 28 R/W 0 20 R/W 1 14 TEMP R 1 13 CREAD1 R/W 0 12 VREAD1 R/W 0 PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 27 26 25 19 R/W 1 11 18 WS[4:0]

R/W 1 10 24 SLEEP R/W 1 16 R/W 1 8 R/W 0 RETRY[1:0]

0 NVMPREPG R/W 0 17 R/W 1 9 R/W 0 1 Bit 7 6 5 4 3 2 Access Reset Bits 31:28 ERS[3:0]Erase Retry State These bits are used by software to track the software state of the erase retry procedure in the event of a system Reset (NMCLR) or Brown Out Reset (BOR) event. Bit 24 SLEEPPower Down in Sleep mode Note:This field can only be modified when the NVMKEY unlock sequence is satisfied. Value 1 0 Description Configures Flash for power down when the system is in Sleep mode Configures Flash for standby when the system is in Sleep mode Bits 20:16 WS[4:0]Flash Access Wait State Control for VREAD1 = 1 Notes:

1. When VREAD1 = 1, WS[4:0] only affects the memory containing NVMADDR[31:0]. This field can only be modified when the NVMKEY unlock sequence is satisfied. 2. Value 11111 11110

... 00010 00001 00000 Description 31 wait states (32 total system clocks) 30 wait states (31 total system clocks) 2 wait states (3 total system clocks) 1 wait state (2 total system clocks) 0 wait state (1 total system clock) Bit 14 TEMPOperating Temperature Control bit This bit is always read as 1 for PIC32CX-BZ3 device. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 181 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Bit 13 CREAD1Compare Read of Logic 1 bit Compare read 1 causes all bits in a Flash Word (including ECC if it exists) to be evaluated during the read. If all bits are 1, the lowest Word in the Flash Word evaluates to 0x0000_0001, all other Words are 0x0001_0000. If any bit is 0, the read evaluates to 0x0000_0000 for all Words in the Flash Word. Notes:

1. When using erase retry in an ECC Flash system, CREAD1 = 1 must be used. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied. Value 1 0 Description Compare read enabled, only if VREAD1 = 1 Compare read disabled Bit 12 VREAD1Verify Read of logic 1 Control bit Notes:

1. When VREAD1 = 1, Flash wait state control is from WS[] for the memory containing NVMADDR[]. 2. Using erase retry and verify read procedure increase life of Flash memory. 3. This field can only be modified when NVMCON.WR == 0 and the NVMKEY unlock sequence is satisfied. Value 1 0 Description Selects erase retry procedure with verify read Selects single erase without verify read Bits 9:8 RETRY[1:0]Erase Retry Control bit, only used when VREAD1 = 1 Note:This field can only be modified when NVMCON.WR == 0. Value 11 10 01 00 Description Erase strength for fourth up to seventh retry cycle Erase strength for third retry cycle Erase strength for second retry cycle Erase strength for first retry cycle Bit 0 NVMPREPGNVM Pre-Program Control Bit Note:This field can only be modified when NVMCON.NVMWR= = 0. Value 1 0 Description Program Operations include Pre-Program step Program Operations exclude Pre-Program step 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 182 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.3 NVMKEY Programming Unlock Register Name:

Offset:

Reset:

Property:

NVMKEY 0x20 0x00000000

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 W 0 23 W 0 15 W 0 7 W 0 30 W 0 22 W 0 14 W 0 6 W 0 29 W 0 21 W 0 13 W 0 5 W 0 28 27 NVMKEY[31:24]

W W 0 0 20 19 NVMKEY[23:16]

W W 0 0 12 11 NVMKEY[15:8]

W 0 4 W 0 W 0 3 W 0 NVMKEY[7:0]

26 W 0 18 W 0 10 W 0 2 W 0 25 W 0 17 W 0 9 W 0 1 W 0 24 W 0 16 W 0 8 W 0 0 W 0 Bits 31:0 NVMKEY[31:0]Unlock Register bits These bits are write-only and read 0 on any read. Note:This register is used as part of the unlock sequence to prevent inadvertent writes to the program Flash. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 183 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.4 NVMADDR Flash Address Register Name:

Offset:

Reset:

Property:

NVMADDR 0x30 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMADDR[31:24]

R/W 0 R/W 0 20 19 NVMADDR[23:16]

R/W 0 R/W 0 11 12 NVMADDR[15:8]

R/W 0 R/W 0 3 4 NVMADDR[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMADDR[31:0]Flash (Word) Address bits Table 11-5. Flash (Word) Address Bits NVMOP Page Erase Row program Word program Quad Word program Notes:

Flash Address Bits Address identifies the page to erase Any address within a 4 Kbytes page boundary will cause the page to be erased Address identifies the row to program The value of the address must be aligned to a row boundary Address identifies the 32-bit Word to program NVMADDR[1:0] bits are ignored Must be aligned to a Word boundary Address identifies the 128-bit Quad Word to program NVMADDR[3:0] bits are ignored Must be aligned to a Quad Word boundary 1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. For all other NVMOP[3:0] bit settings, the Flash address is ignored. For additional information on these bits, see the NVMCON register from Related Links. The bits in this register are reset by a POR only and are not affected by other Reset sources. 3. Related Links 11.22.1. NVMCON 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 184 Microchip Confidential Confidential 11.22.5 NVMDATA0 Flash Program Data Register 0 PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Name:

Offset:

Reset:

Property:

NVMDATA0 0x40 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMDATA[31:24]

R/W 0 R/W 0 20 19 NVMDATA[23:16]

R/W 0 12 R/W 0 11 NVMDATA[15:8]

R/W 0 4 R/W 0 3 NVMDATA[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMDATA[31:0]Flash Programming Data bits The value in this register is written to Flash when a program operation is commanded. Single Word program (32-bit) Writes NVMDATA0 to the target Flash address defined in NVMADDR[31:2]. Quad Word program (128-bit) Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR[31:4]. NVMDATA0 contains the Least Significant Instruction Word. Notes:

1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. The bits in this register are reset on a POR only and are unaffected by other Reset sources. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 185 Microchip Confidential Confidential 11.22.6 NVMDATA1 Flash Program Data Register 1 PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Name:

Offset:

Reset:

Property:

NVMDATA1 0x50 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMDATA[31:24]

R/W 0 R/W 0 20 19 NVMDATA[23:16]

R/W 0 12 R/W 0 11 NVMDATA[15:8]

R/W 0 4 R/W 0 3 NVMDATA[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMDATA[31:0]Flash Programming Data bits The value in this register is written to Flash when a program operation is commanded. Single Word program (32-bit) Writes NVMDATA0 to the target Flash address defined in NVMADDR[31:2]. Quad Word program (128-bit) Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR[31:4]. NVMDATA0 contains the Least Significant Instruction Word. Notes:

1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. The bits in this register are reset on a POR only and are unaffected by other Reset sources. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 186 Microchip Confidential Confidential 11.22.7 NVMDATA2 Flash Program Data Register 2 PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Name:

Offset:

Reset:

Property:

NVMDATA2 0x60 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMDATA[31:24]

R/W 0 R/W 0 20 19 NVMDATA[23:16]

R/W 0 12 R/W 0 11 NVMDATA[15:8]

R/W 0 4 R/W 0 3 NVMDATA[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMDATA[31:0]Flash Programming Data bits The value in this register is written to Flash when a program operation is commanded. Single Word program (32-bit) Writes NVMDATA0 to the target Flash address defined in NVMADDR[31:2]. Quad Word program (128-bit) Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR[31:4]. NVMDATA0 contains the Least Significant Instruction Word. Notes:

1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. The bits in this register are reset on a POR only and are unaffected by other Reset sources. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 187 Microchip Confidential Confidential 11.22.8 NVMDATA3 Flash Program Data Register 3 PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) Name:

Offset:

Reset:

Property:

NVMDATA3 0x70 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMDATA[31:24]

R/W 0 R/W 0 20 19 NVMDATA[23:16]

R/W 0 12 R/W 0 11 NVMDATA[15:8]

R/W 0 4 R/W 0 3 NVMDATA[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMDATA[31:0]Flash Programming Data bits The value in this register is written to Flash when a program operation is commanded. Single Word program (32-bit) Writes NVMDATA0 to the target Flash address defined in NVMADDR[31:2]. Quad Word program (128-bit) Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR[31:4]. NVMDATA0 contains the Least Significant Instruction Word. Notes:

1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. The bits in this register are reset on a POR only and are unaffected by other Reset sources. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 188 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.9 NVMSRCADDR Source Data Address Register Name:

Offset:

Reset:

Property:

NVMSRCADDR 0xC0 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 NVMSRCADDR[31:24]

R/W R/W 0 0 20 19 NVMSRCADDR[23:16]

R/W R/W 0 0 12 11 NVMSRCADDR[15:8]

R/W R/W 0 0 4 3 NVMSRCADDR[7:0]

R/W R/W 0 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 NVMSRCADDR[31:0]Source Data (Word) Address bits This is the system physical Word address of the data (in DRM) to be programmed into the Flash when NVMCON.NVMOP is set to row programming. Notes:

1. Hardware prevents writes to this register when NVMCON.WR = 1. 2. The bits in this register are reset on a POR only and are unaffected by other reset sources. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 189 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.10 NVMPWPLT Flash Program Write Protect Lower Register Name:

Offset:

Reset:

Property:

NVMPWPLT 0xD0 0x80000000

Bit Access Reset 31 ULOCK R/C 1 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 29 28 27 26 25 24 22 R/W 0 14 R/W 0 6 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 20 19 PWPLT[23:16]

R/W 0 12 R/W 0 11 PWPLT[15:8]

R/W 0 4 R/W 0 R/W 0 3 R/W 0 PWPLT[7:0]

18 R/W 0 10 R/W 0 2 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bit 31 ULOCKNVMPWPLT Register Unlock bit Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied. This field can be cleared at the same time as writing to PWPLT[23:0]. Value 1 0 Description NVMPWPLT register is not locked and can be modified NVMPWPLT register is locked and cannot be modified Bits 23:0 PWPLT[23:0]Flash Program Write Protect Less Than Address Pages at Flash addresses less than this value are write-protected. Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1. This is a byte address force to align to page boundaries. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 190 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.11 NVMPWPGTE Flash Program Write Protect Greater Register Name:

Offset:

Reset:

Property:

NVMPWPGTE 0xE0 0x80FFFFFF

Bit Access Reset 31 ULOCK R/C 1 Bit 23 Access Reset R/W 1 Bit 15 Access Reset R/W 1 Bit 7 Access Reset R/W 1 30 29 28 27 26 25 24 22 R/W 1 14 R/W 1 6 R/W 1 21 R/W 1 13 R/W 1 5 R/W 1 20 19 PWPGTE[23:16]

R/W 1 12 R/W 1 11 PWPGTE[15:8]

R/W 1 4 R/W 1 3 PWPGTE[7:0]

R/W 1 R/W 1 18 R/W 1 10 R/W 1 2 R/W 1 17 R/W 1 9 R/W 1 1 R/W 1 16 R/W 1 8 R/W 1 0 R/W 1 Bit 31 ULOCKNVMPWPGTE Register Unlock bit Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied. This field can be cleared at the same time as writing to PWPGTE[23:0]. Value 1 0 Description NVMPWPGTE register is not locked and can be modified NVMPWPGTE register is locked and cannot be modified Bits 23:0 PWPGTE[23:0]Flash Program Write Protect Address Pages at Flash addresses greater than or equal to this value are write-protected. Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied and ULOCK = 1. This is a byte address forced to align to page boundaries. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 191 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Flash Controller (FC) 11.22.12 NVMLBWP - Flash Boot Write Protect Register Name:

Offset:

Reset:

Property:

NVMLBWP 0xF0 0x80FFFFFF

Bit Access Reset 31 ULOCK R/C 1 Bit 23 Access Reset R/W 1 Bit 15 Access Reset R/W 1 Bit 7 Access Reset R/W 1 30 29 28 27 26 25 24 22 R/W 1 14 R/W 1 6 R/W 1 21 R/W 1 13 R/W 1 5 R/W 1 20 19 LBWP[23:16]

R/W 1 12 R/W 1 4 R/W 1 LBWP[15:8]

LBWP[7:0]

R/W 1 11 R/W 1 3 R/W 1 18 R/W 1 10 R/W 1 2 R/W 1 17 R/W 1 9 R/W 1 1 R/W 1 16 R/W 1 8 R/W 1 0 R/W 1 Bit 31 ULOCKLower Boot Write Protect (LBWPn) Unlock bit Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied. This field can be cleared at the same time as writing to LBWP[msb:lsb]. Value 1 0 Description LBWPn bits are not locked and can be modified LBWPn bits are locked and cannot be modified Bits 23:0 LBWP[23:0]Boot Pages Write Protect bits Notes:

1. 2. This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1. The OTP page is always erase protected and its associated LBWP bit is only for write protection. Value 1 0 Description Erase and write protection for upper boot page n is enabled Erase and write protection for upper boot page n is disabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 192 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12. Device Service Unit (DSU) 12.1 Overview The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU Reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or unavailable when the device is protected by the Code Protect bit and SECCFG.DEBUG_LCK bit. 12.2 Features CPU Reset Extension Debugger Probe Detection (Cold- and Hot-Plugging) Chip-Erase Command and Status 32-Bit Cyclic Redundancy Check (CRC32) of any Memory Accessible Through the Bus Matrix ARM CoreSight Compliant Device Identification Two Debug Communications Channels with DMA Connection Debug Access Port Security Filter 12.3 DSU Block Diagram Figure 12-1. DSU Block Diagram GPIO 12.4 Signal Description The DSU uses three signals to function. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 193 Microchip Confidential DSUSWCLKCORESIGHT ROMDAP SECURITY FILTERCRC-32CHIP ERASEcpu_reset_extensionCPUDAPSWDIOFLASHDBGMHIGH-SPEED BUS MATRIXMSdebugger_presentDEBUGGER PROBEINTERFACEAHB-APCONTROLLERNMCLRConfidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) Table 12-1. Signal Description Signal Name NMCLR CM4_SWCLK CM4_SWDIO Type Digital input Digital input Digital I/O Description External Reset pin Software clock pin Software bidirectional data pin 12.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 12.5.1 I/O Lines The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU Reset phase (see Debugger Probe Detection from Related Links). The Hot-Plugging feature depends on the GPIO configuration. If the SWCLK pin function is changed in the port, the Hot-Plugging feature is not disabled. Hot-Plugging is disabled with the CFGCON0.HPLUGDIS bit, which is enabled by default. Therefore to use the SWCLK pin for GPIO functions, it must be disabled by setting CFGCON0.HPLUGDIS = 1. Related Links 12.6.3. Debugger Probe Detection 12.5.2 Power Management The DSU will continue to operate in any sleep mode (Standby Sleep, Idle) where the selected source clock is running. 12.5.3 Clocks The DSU bus clocks (CLK_DSU_APB (PB2_CLK) and CLK_DSU_AHB (SYS_CLK)) can be enabled and disabled by the CRU. 12.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. See Direct Memory Access Controller (DMAC) from Related Links. The CFG.DCCDMALEVEL bit field must be configured depending on the DMA channels access modes (read or write for DCC0 and DCC1). Related Links 22. Direct Memory Access Controller (DMAC) 12.5.5 Interrupts Not applicable. 12.5.6 Events Not applicable. 12.5.7 Register Access Protection Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Debug Communication Channel 0 register (DCC0) Debug Communication Channel 1 register (DCC1) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 194 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) Notes:

Optional write protection is indicated by the PAC Write Protection property in the register description. When the CPU is halted in the Debug mode, all write-protection is automatically disabled. Write protection does not apply for accesses through an external debugger. 12.5.8 Analog Connections Not applicable. 12.6 Debug Operation 12.6.1 Principle of Operation The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources:

CPU Reset extension Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification. Debug using SWD will be blocked on secured devices (SECCFG.DEBUG_LCK). 12.6.2 CPU Reset Extension CPU Reset extension refers to the extension of the Reset phase of the CPU core after the external Reset is released. This ensures that the CPU is not executing code at start-up while a debugger is connected to the system. The debugger is detected on a NMCLR release event when SWCLK is low. At start-up, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the Reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a 1 to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to 0. Writing a 0 to STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU Reset extension when the device is protected by the Code Protect bit (FCPN0.CP) or by SECCFG.DEBUG_LCK bit. Trying to do so sets the Protection Error bit (PERR) of the Status A register (STATUSA.PERR). Figure 12-2. Typical CPU Reset Extension Set and Clear Timing Diagram SWCLK NMCLR DSU CRSTEXT Clear CPU Reset Extension CPU_STATE reset running 12.6.3 Debugger Probe Detection 12.6.3.1 Cold Plugging Cold-Plugging is the detection of a debugger when the system is in Reset. Cold-Plugging is detected when the CPU Reset extension is requested, as described above. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 195 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.6.3.2 Hot-Plugging Hot-Plugging is the detection of a debugger probe when the system is not in Reset. Hot-Plugging is not possible under Reset because the detector is reset when POR or NMCLR are asserted. Hot-Plugging is active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK pin function is changed in the port, the Hot-Plugging features is not disabled. Hot-Plugging is disabled with the CFGCON0.HPLUGDIS bit, which is enabled by default. Therefore, to use the SWCLK pin for GPIO functions it must be disabled by setting CFGCON0.HPLUGDIS

= 1. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register

(STATUSB.HPE). Figure 12-3. Hot-Plugging Detection Timing Diagram SWCLK NMCLR CPU_STATE reset running Hot-Plugging The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the Code Protect bit (FCPN0.CP) or SECCFG.DEBUG_LCK bit. This detection requires that pads are correctly powered. Thus, at cold start-up, this detection cannot be done until POR is released. If the device is protected using Code protect (FCPN0.CP) or SECCFG.DEBUG_LCK bit, Cold-Plugging is the only way to detect a debugger probe, and so the external Reset timing must be longer than the POR timing. If external Reset is deasserted before POR release, the user must retry the procedure above until it gets connected to the device. 12.7 Chip Erase Chip erase consists of removing all sensitive information stored in the chip and clearing the Code Protect bit. Therefore, all volatile memories and the Flash memory will be erased. The OTP Boot flash memory page will not be erased. When the device is protected using FCPN0.CP or SECCFG.DEBUG_LCK bit, the debugger must first reset the device in order to be detected. This ensures that internal registers are reset after the Protected state is removed. The chip erase operation is triggered by writing a 1 to the chip erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the chip erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE). The chip erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a chip erase after a Cold-Plugging procedure to ensure that the device is in a known and Safe state. The recommended sequence is as follows:

1. 2. Issue the Cold-Plugging procedure (See Cold-Plugging from Related Links). The device then:

a. Detects the debugger probe. b. Holds the CPU in Reset. Issue the chip erase command by writing a 1 to CTRL.CE. The device then:

a. Clears the system volatile memories. b. Erases the whole Flash array (excluding OTP). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 196 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) c. Erases the Lock Row, and Code Protect bit protection. 3. Check for completion by polling STATUSA.DONE (read as 1 when completed). 4. Reset the device to let the Flash Controller update the fuses. Related Links 12.6.3.1. Cold Plugging 12.8 Programming Programming the Flash or RAM memories is only possible when the device is not protected by the Code Protect bit. Important:When the device is secured using SECCFG.DEBUG_LCK, row programming is not supported because SRAM memory is not accessible by the external debugger. Either word programming or quad word programming is possible based on the CFGCON0.ECCCTL setting. The programming procedure is as follows:

1. 2. 3. 4. 5. 6. 7. 8. At power-up, NMCLR is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (See Power-on Reset (POR) electrical characteristics from Related Links). The system continues to be held in this Static state until the internally regulated supplies have reached a safe Operating state. The power management starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal Resets are maintained due to the external Reset. The debugger maintains a low level on SWCLK. NMCLR is released, resulting in a debugger Cold-Plugging procedure. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released. A chip erase is issued to ensure that the Flash is fully erased prior to programming. Programming is available through the AHB-AP. See the PIC32CX-BZ3 Programming Specification and Flash Controller for more details. Note:Programming of Boot Flash Memory (BFM) pages is allowed only when the bit 3 at address 0x410001FC is set to 1. After the operation is completed, the chip can be restarted either by asserting NMCLR, toggling power, or writing a 1 to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Ensure that the SWCLK pin is high when releasing NMCLR to prevent extending the CPU Reset. Related Links 13.4.2.1.1. Power-on Reset (POR) 12.9 Intellectual Property Protection Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and this is accomplished by setting the Code Protect bit or DEBUG_LCK bit. There are two protection mechanism in PIC32CX-BZ3 devices. One is code protection and another is secured device as following:

2. 1. Code Protect: When the Code protect is enabled by configuring FCPN0.CP in Boot Flash memory, the device is locked from programming and debugging. Only chip erase can retrieve the device to normal programming and debugging condition. When issuing a chip erase, sensitive information is erased from volatile memory and Flash. Secured Device: DEBUG_LCK bits in eFuse (SECCFG.DEBUG_LCK in Root of Trust) determines if the device is locked for debug. If the DEBUG_LCK bits are non-zero, device is a secured device. Securing of the device implies:

a. No un-authenticated firmware can be executed. b. The debug features of the device are not available and are locked down. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 197 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) c. Device programming through SWD interface is still available. Debugger can be plugged in only through the cold-plugging procedure. Hot plugging feature is not available (See Cold Plugging and Hot Plugging from Related Links). Since the DEBUG_LCK bits are in eFuse (one time programmable memory), once locked, the device is permanently locked for debug unlike the Code protect mechanism which can be cleared on a chip erase. d. Important:On a secured device (non-zero value of SECCFG.DEBUG_LCK), if the boot key is zero, it implies that secure boot code need not authorize the firmware code. Therefore, programming through external debugger is disabled on a device which is secured and secure boot key is zero. When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (For more details, refer to the ARM Debug Interface v5 Architecture Specification on www.arm.com). The DSU is intended to be accessed either:

Internally from the CPU, without any limitation, even when the device is protected Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:

The first 0x100 bytes form the internal address range The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000. The DSU Operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the following table. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 198 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) Internal address range

(cannot be accessed from debug tools when the device is protected by the Code Protect bit or by SECCFG.DEBUG_LCK bit) Figure 12-4. APB Memory Mapping DSU Operating registers Mirrored DSU Operating registers 0x0000 0x00FF 0x0100 0x01FF 0x1000 0x1FFF Empty External address range

(can be accessed from debug tools with some restrictions) DSU CoreSight ROM Some features that are not activated by APB transactions are not available when the device is protected:

Table 12-2. Feature Availability Under Protection Feature Code Protected and Unsecured Code Protected and Secured Not Code Protected and Unsecured Not Code Protected and Secured CPU Reset Extension Clear CPU Reset Extension Yes No Debugger Cold-Plugging Yes MEM-AP access during Cold-Plugging No Debugger Hot-Plugging No Notes:

Yes No Yes No No Yes Yes Yes Yes Yes Yes No Yes Yes No Code Protected means FCPN0.CP of Flash fuse configuration bit is set. Secured means SECCFG.DEBUG_LCK bits of eFuse are non zero values. Related Links 12.6.3.1. Cold Plugging 12.6.3.2. Hot-Plugging 12.10 Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a Microchip device implementing a DSU. The DSU contains identification registers to differentiate the device. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 199 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.10.1 CoreSight Identification A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:

Figure 12-5. Conceptual 64-bit Peripheral ID Table 12-3. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size Description JEP-106 CC code 4 Microchip continuation code: 0x0 JEP-106 ID code 4KB count RevAnd CUSMOD PARTNUM REVISION 7 4 4 4 12 4 Microchip device ID: 0x1F Indicates that the CoreSight component is a ROM: 0x0 Not used; read as 0 Not used; read as 0 Contains 0xCD0 to indicate that DSU is present DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) For more details, refer to the ARM Debug Interface Version 5 Architecture Specification. Location PID4 PID1+PID2 PID4 PID3 PID3 PID0+PID1 PID2 12.10.2 Chip Identification Method The DSU DID register identifies the device as shown in the following table:

Table 12-4. DSU DID Encoding Field Revision Family Series Die DEVSEL Size 4 bits 5 bits 6 bits 8 bits 8 bits Value 0x0 0b00000 0b00000 0x9E RoT eFuse (device_id) Comments Immutable Field (0x0=Rev-

A0) Family[4:0]

Series[5:0]

Immutable Field = Mask ID

[7:0]

Determines variants of product {VSEL[7:0]}

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 200 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.11 Functional Description 12.11.1 Principle of Operation The DSU provides memory services, such as CRC32 that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first;

then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one. 12.11.2 Basic Operation 12.11.2.1 Initialization The module is enabled by enabling its clocks, see Clock and Reset Unit (CRU) from Related Links. The DSU registers can be PAC write-protected, see Peripheral Access Controller (PAC) from Related Links. Related Links 13. Clock and Reset Unit (CRU) 20. Peripheral Access Controller (PAC) 12.11.2.2 Operation From a Debug Adapter Debug adapters must access the DSU registers in the external address range 0x100-0x2000. If the device is protected by the Code Protect bit, accessing the first 0x100 bytes causes the system to return an error. See Intellectual Property Protection from Related Links. When the device debug is locked through Secure Device, other than DSU external address range, Flash Controller registers, eFuse controller registers and Flash Memory addresses are placed under MEM-AP permissible address range to allow programming. Table 12-5. Permissible Address Range for External Debugger when Secured Device Parameter Description PERM_ADDR_START1 Permissible address range start PERM_ADDR_END1 Permissible address range end PERM_ADDR_START2 Second permissible address range start PERM_ADDR_END2 Second permissible address range end FLASH_ADDR_START Flash address start FLASH_ADDR_END Flash address end Value 0x4400_0600 0x4400_07FF 0x4400_2C00 0x4400_3BFF 0x0080_0000 0x0107_FFFF Related Links 12.9. Intellectual Property Protection 12.11.2.3 Operation From the CPU There are no restrictions when accessing DSU registers from the CPU. However, the user must access DSU registers in the internal address range (0x00x100) to avoid external security restrictions. See Intellectual Property Protection from Related Links. Related Links 12.9. Intellectual Property Protection 12.11.3 32-bit Cyclic Redundancy Check (CRC32) The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area

(including Flash and AHB RAM). When the CRC32 command is issued from:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 201 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) The internal range, the CRC32 can be operated at any memory location The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see the following table) Table 12-6. AMOD Bit Descriptions when Operating CRC32 AMOD[1:0] Short Name External Range Restrictions 0 1-3 ARRAY CRC32 is restricted to the full Flash array area. DATA forced to 0xFFFFFFFF before calculation (no seed). Reserved The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320

(reversed representation). 12.11.3.1 Starting CRC32 Calculation CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word-aligned. The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non inverted if used as starting point for subsequent CRC32 calculations. If the device is in protected state by the Code protect or SECCFG.DEBUG_LCK security bit, it is only possible to calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the contents of a protected device. The actual test is started by writing a 1 in the 32-bit Cyclic Redundancy Check bit of the Control register

(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing 1 to CTRL.SWRST). 12.11.3.2 Interpreting the Results The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred. 12.11.4 Debug Communication Channels The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger even if the device is protected by the Code Protect bit or SECCFG.DEBUG_LCK bit. The registers can be used to exchange data between the CPU and the debugger, during run time as well as in Debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are accessible when the Protected state is active. When the device is protected, however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held under Reset). Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. 12.11.5 System Services Availability when Accessed Externally and Device is Protected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 202 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) Table 12-7. Available Features when Operated from External Address Range and the Device is Protected Features Availability From External Address Range and the Device is Code Protected or Secured Device Chip erase command and status Yes CRC32 Yes, only full array of Flash CoreSight Compliant Device identification Debug communication channels Yes Yes STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 203 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.12 Register Summary See DSU module in the Product Memory Mapping Overview from Related Links for base address. Bit Pos. 7 6 5 4 CE PERR HPE 3 FAIL DCCD1 2 CRC BERR CRSTEXT DCCD0 DBGPRES 1 0 SWRST DONE PROT Offset 0x00 0x01 0x02 0x03 Name CTRL STATUSA STATUSB Reserved 0x04 ADDR 0x08 LENGTH 0x0C DATA 0x10 DCC0 0x14 DCC1 0x18 DID 0x1C CFG 0x20

... 0x37 Reserved 0x38 UUID0 0x3C UUID1 0x40 UUID2 0x44 UUID3 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ADDR[5:0]

AMOD[1:0]

LENGTH[5:0]

ADDR[13:6]

ADDR[21:14]

ADDR[29:22]

LENGTH[13:6]

LENGTH[21:14]

LENGTH[29:22]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

DEVSEL[7:0]

DIE[7:0]

FAMILY[0]

PROCESSOR[3:0]

SERIES[5:0]

FAMILY[4:1]

ETBRAMEN DCCDMALEVEL[1:0]

LQOS[1:0]

UUID[7:0]

UUID[15:8]

UUID[23:16]

UUID[31:24]

UUID[7:0]

UUID[15:8]

UUID[23:16]

UUID[31:24]

UUID[7:0]

UUID[15:8]

UUID[23:16]

UUID[31:24]

UUID[7:0]

UUID[15:8]

UUID[23:16]

UUID[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 204 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x48 SECCFG 0x4C CTR_STAT 0x50 BOOT_STATUS 0x54 BOOT_KEY0

... 0x80 BOOT_KEY11 0x84

... 0xEF Reserved 0xF0 DCFG0 0xF4 DCFG1 0xF8

... 0x0FFF Reserved 0x1000 ENTRY0 0x1004 ENTRY1 0x1008 END 0x100C

... 0x1FCB Reserved 0x1FCC MEMTYPE 0x1FD0 PID4 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 DEBUG_LCK[1:0]

UUID_LCK[1:0]

BOOT_KEY_LCK[1:0]

ROOT_KEY_LCK[1:0]

ADD_BOOT_ KEY ROLLBACK_CTR[7:0]

BOOT_STATUS[7:0]

BOOT_KEY[7:0]

BOOT_KEY[15:8]

BOOT_KEY[23:16]

BOOT_KEY[31:24]

BOOT_KEY[7:0]

BOOT_KEY[15:8]

BOOT_KEY[23:16]

BOOT_KEY[31:24]

DCFG[7:0]

DCFG[15:8]

DCFG[23:16]

DCFG[31:24]

DCFG[7:0]

DCFG[15:8]

DCFG[23:16]

DCFG[31:24]

ADDOFF[11:4]

ADDOFF[19:12]

ADDOFF[11:4]

ADDOFF[19:12]

END[7:0]

END[15:8]

END[23:16]

END[31:24]

ADDOFF[3:0]

ADDOFF[3:0]

FMT EPRES FMT EPRES SMEMP FKBC[3:0]

JEPCC[3:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 205 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU)

...........continued Offset 0x1FD4

... 0x1FDF Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved 0x1FE0 PID0 0x1FE4 PID1 0x1FE8 PID2 0x1FEC PID3 0x1FF0 CID0 0x1FF4 CID1 0x1FF8 CID2 0x1FFC CID3 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 PARTNBL[7:0]

JEPIDCL[3:0]

PARTNBH[3:0]

REVISION[3:0]

JEPU JEPIDCH[2:0]

REVAND[3:0]

CUSMOD[3:0]

PREAMBLEB0[7:0]

CCLASS[3:0]

PREAMBLE[3:0]

PREAMBLEB2[7:0]

PREAMBLEB3[7:0]

Related Links 7. Product Memory Mapping Overview 12.13 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. See Register Access Protection from Related Links. Related Links 12.5.7. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 206 Microchip Confidential Confidential 12.13.1 Control Name:

Offset:

Reset:

Property: PAC Write-Protection CTRL 0x00 0x00 Bit 7 6 5 Access Reset Bit 4 CEChip-Erase PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 4 CE W 0 3 2 CRC W 0 1 0 SWRST W 0 Writing a 0 to this bit has no effect. Writing a 1 to this bit starts the Chip-Erase operation. Bit 2 CRC32-bit Cyclic Redundancy Check Writing a 0 to this bit has no effect. Writing a 1 to this bit starts the cyclic redundancy check algorithm. Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets the module. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 207 Microchip Confidential Confidential 12.13.2 Status A STATUSA Name:

0x01 Offset:

Reset:

0x00 Property: PAC Write Protection Bit 7 6 5 Access Reset Bit 4 PERRProtection Error PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 4 PERR R/W 0 3 FAIL R/W 0 2 BERR R/W 0 1 CRSTEXT R/W 0 0 DONE R/W 0 Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in Protected state is issued. Bit 3 FAILFailure Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. Bit 2 BERRBus Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Bus Error bit. This bit is set when a bus error is detected. Bit 1 CRSTEXTCPU Reset Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU Reset phase. Bit 0 DONEDone Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. This bit is set when a DSU operation is completed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 208 Microchip Confidential Confidential 12.13.3 Status B Name:

Offset:

Reset:

Property: PAC Write-Protection STATUSB 0x02 0x0x Bit 7 6 5 Access Reset Bit 4 HPEHot-Plugging Enable PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 4 HPE R 0 3 DCCD1 R 0 2 DCCD0 R 0 1 DBGPRES R x 0 PROT R x Writing a 0 to this bit has no effect. Writing a 1 to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power-reset or a external reset can set it again. Bits 2, 3 DCCDDebug Communication Channel x Dirty Writing a 0 to this bit has no effect. Writing a 1 to this bit has no effect. This bit is set when DCC is written. This bit is cleared when DCC is read. Bit 1 DBGPRESDebugger Present Writing a 0 to this bit has no effect. Writing a 1 to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. Bit 0 PROTProtected Writing a 0 to this bit has no effect. Writing a 1 to this bit has no effect. This bit is set at power-up when the device is code protected and FCPN0.CP (See FCPN0 from Related Links) bit in Devconfig Boot Flash memory is set to enable code protection. This bit is never cleared. Related Links 7.8. FCPN0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 209 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.4 Address Name:

Offset:

Reset:

Property: PAC Write Protection ADDR 0x04 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 ADDR[29:22]

R/W 0 20 R/W 0 19 ADDR[21:14]

ADDR[13:6]

R/W 0 12 R/W 0 4 R/W 0 ADDR[5:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 AMOD[1:0]

24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:2 ADDR[29:0]Address Initial word start address needed for memory operations. Bits 1:0 AMOD[1:0]Access Mode The functionality of these bits is dependent on the operation mode. Bit description when operating CRC32 (see 32-bit Cyclic Redundancy Check (CRC32) from Related Links). Related Links 12.11.3. 32-bit Cyclic Redundancy Check (CRC32) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 210 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.5 Length Name:

Offset:

Reset:

Property: PAC Write Protection LENGTH 0x08 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 28 27 LENGTH[29:22]

R/W 0 20 R/W 0 19 LENGTH[21:14]

R/W 0 12 R/W 0 11 LENGTH[13:6]

R/W 0 4 LENGTH[5:0]

R/W 0 R/W 0 R/W 0 3 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 24 R/W 0 16 R/W 0 8 R/W 0 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 Bits 31:2 LENGTH[29:0]Length Length in words needed for memory operations. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 211 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.6 Data Name:

Offset:

Reset:

Property: PAC Write Protection DATA 0x0C 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DATA[31:0]Data Memory operation initial value or result value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 212 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.7 Debug Communication Channel x Name:

Offset:

Reset:

Property:

DCC 0x10 + n*0x04 [n=0..1]

0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 Bits 31:0 DATA[31:0]Data Data register. 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 213 Microchip Confidential Confidential 12.13.8 Device Identification DID Name:

Offset:

0x18 Property: PAC Write Protection Bit Access Reset Bit Access Reset 31 R p 23 FAMILY[0]

R f Bit 15 Access Reset Bit Access Reset R d 7 R x 30 29 PROCESSOR[3:0]

R R p p 22 14 R d 6 R x 21 R s 13 R d 5 R x PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 28 R p 20 R s 12 R d 4 R x DIE[7:0]

DEVSEL[7:0]

27 R f 19 R s 11 R d 3 R x SERIES[5:0]

26 R f 18 R s 10 R d 2 R x FAMILY[4:1]

25 R f 17 R s 9 R d 1 R x 24 R f 16 R s 8 R d 0 R x Bits 31:28 PROCESSOR[3:0]Processor The value of this field defines the processor used on the device. Bits 27:23 FAMILY[4:0]Product Family The value of this field corresponds to the product family part of the ordering code. Bits 21:16 SERIES[5:0]Product Series The value of this field corresponds to the product series part of the ordering code. Bits 15:8 DIE[7:0]Die Number Identifies the die family. 0x9E for PIC32CX-BZ3 family of devices. Bits 7:0 DEVSEL[7:0]Device Selection This bit field identifies a device within a product family and product series. The value corresponds to the Flash memory density, pin count and device variant parts of the ordering code. Refer to ordering information for DEVSEL[7:0] values of different variants. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 214 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.9 Configuration Name:

Offset:

Reset:

Property: PAC Write-Protection CFG 0x1C 0x00000002 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 Access Reset Bit 4 ETBRAMENTrace Control 4 ETBRAMEN R/W 0 3 2 DCCDMALEVEL[1:0]

R/W R/W 0 0 9 1 8 0 LQOS[1:0]

R/W 1 R/W 0 ETB Ram Enable Writing a one to this bit will reserve the first 32KB of the RAM for the Trace ETB ram buffer. Bits 3:2 DCCDMALEVEL[1:0]DMA Trigger Level Value 0x0 0x1 0x2 -

0x3 Description DMA Trigger rises when DCC is empty. DMA Trigger rises when DCC is full. Reserved Bits 1:0 LQOS[1:0]Latency Quality Of Service These bits define the priority access during the memory access. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 215 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.10 Unique Identifier Register n Name:

Offset:

Reset:

Property:

UUID 0x38 + n*0x04 [n=0..3]

0x00000000

These registers contain the unique identifier of the device. It is stored in eFuse memory in Root of Trust module which is directly driven in this register. Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 UUID[31:24]

UUID[23:16]

UUID[15:8]

UUID[7:0]

28 R 0 20 R 0 12 R 0 4 R 0 27 R 0 19 R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 UUID[31:0]Unique Identifier bits These bits provide the unique identifier value. The four 32-bit UUID registers contain the 128-bit UUID. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 216 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.11 Secure Configuration Name:

Offset:

Reset:

Property:

SECCFG 0x48 0x00000000

This register contains the secure configuration setting of the device. It is stored in eFuses memory in Root of Trust module which is directly driven in this register. Note:

*_LCK bits in this register refer to the program locks of corresponding eFuses. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 Access Reset 16 ADD_BOOT_K EY R 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset 7 6 DEBUG_LCK[1:0]

R R 0 0 5 4 UUID_LCK[1:0]

R 0 R 0 BOOT_KEY_LCK[1:0]

ROOT_KEY_LCK[1:0]

R 0 3 R 0 2 R 0 1 R 0 0 Bit 16 ADD_BOOT_KEYAdditional Boot Key This bit is the LSB of the Y co-ordinate in the compressed Secure Boot Key. Bits 11:10 BOOT_KEY_LCK[1:0]Lock Bits for Secure Boot Key Value 11 10 01 00 Description Secure boot key is locked and cannot be programmed Secure boot key is locked and cannot be programmed Secure boot key is locked and cannot be programmed Secure boot key is not locked Bits 9:8 ROOT_KEY_LCK[1:0]Lock Bits for Storage Root Key Value 11 10 01 00 Description Storage root key is locked and cannot be programmed Storage root key is locked and cannot be programmed Storage root key is locked and cannot be programmed Storage root key is not locked Bits 7:6 DEBUG_LCK[1:0]Lock Bits for Debug Value 11 10 01 00 Description Debug is locked. Not possible to debug. Debug is locked. Not possible to debug. Debug is locked. Not possible to debug. Debug is not locked. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 217 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) Bits 5:4 UUID_LCK[1:0]Programming Lock Bits for Unique ID Fuses Value 11 10 01 00 Description Unique ID is locked and cannot be programmed Unique ID is locked and cannot be programmed Unique ID is locked and cannot be programmed Unique ID is not locked 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 218 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.12 Rollback Counter Status Name:

Offset:

Reset:

Property:

CTR_STAT 0x4C 0x0000009C

This register has Rollback Counter information. It is stored in eFuse memory in Root of Trust module which is directly driven in this register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 5 R 0 4 3 ROLLBACK_CTR[7:0]

R 0 R 0 2 R 0 9 1 R 0 8 0 R 0 Bits 7:0 ROLLBACK_CTR[7:0]Rollback Counter status This bit contains the Rollback Counter status. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 219 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.13 Boot Status Name:

Offset:

Reset:

Property:

BOOT_STATUS 0x50 0x0

This register reflects the SEC_BOOT.BOOT_STATUS bits in Root of Trust module. The secure boot firmware in ROM manages the SEC_BOOT.BOOT_STATUS bits to indicate secure boot status. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 5 R 0 4 3 BOOT_STATUS[7:0]

R 0 R 0 2 R 0 9 1 R 0 8 0 R 0 Bits 7:0 BOOT_STATUS[7:0]

These bits hold 8-bit code which is written to SEC_BOOT.BOOT_STATUS bits to indicate the secure boot status, such as authentication success, failure or any other indication. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 220 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.14 Secure Boot Key n Name:

Offset:

Reset:

Property:

BOOT_KEY 0x54 + n*0x04 [n=0..11]

0x00000000

These registers read the secure boot key. Secure boot key is stored in eFuse in Root of Trust module which is directly driven in this register. The twelve 32-bit BOOT_KEY registers contain the 384-bit secure public boot key. Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 BOOT_KEY[31:24]

R R 0 0 20 19 BOOT_KEY[23:16]

R R 0 0 12 11 BOOT_KEY[15:8]

R R 0 0 4 3 BOOT_KEY[7:0]

R R 0 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 BOOT_KEY[31:0]Secure Boot key bits These bits provide the secure boot key. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 221 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.15 Device Configuration Name:

Offset:

Reset:

Property: PAC Write-Protection DCFG 0xF0 + n*0x04 [n=0..1]

0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DCFG[31:24]

R/W 0 20 R/W 0 19 DCFG[23:16]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 3 R/W 0 DCFG[15:8]

DCFG[7:0]

26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DCFG[31:0]Device Configuration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 222 Microchip Confidential Confidential 12.13.16 CoreSight ROM Table Entry x Name:

Offset:

Reset:

Property: PAC Write-Protection ENTRY 0x1000 + n*0x04 [n=0..1]

0xxxxxx00x 31 R x 23 R x 15 R x 7 Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 30 R x 22 R x 14 R x 6 29 R x 21 R x 13 R x 5 ADDOFF[3:0]

PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 26 R x 18 R x 10 25 R x 17 R x 9 24 R x 16 R x 8 28 27 ADDOFF[19:12]

R R x x 20 19 ADDOFF[11:4]

R x 11 R x 12 R x 4 3 2 1 FMT R 1 0 EPRES R x Bits 31:12 ADDOFF[19:0]Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 FMTFormat Always reads as 1, indicating a 32-bit ROM table. Bit 0 EPRESEntry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not code protected indicating that the entry is not present. This bit is cleared at power-up if the device is not code protected indicating that the entry is present. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 223 Microchip Confidential Confidential 12.13.17 CoreSight ROM Table End Name:

Offset:

Reset:

Property:

END 0x1008 0x00000000

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) END[31:24]

END[23:16]

END[15:8]

END[7:0]

28 R 0 20 R 0 12 R 0 4 R 0 27 R 0 19 R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 END[31:0]End Marker Indicates the end of the CoreSight ROM table entries. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 224 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.18 CoreSight ROM Table Memory Type Name:

Offset:

Reset:

Property:

MEMTYPE 0x1FCC x determined by Debug Access Level (DAL)0x0000000X

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 SMEMPSystem Memory Present 9 1 8 0 SMEMP R x This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up if the device is not code protected, indicating that the system memory is accessible from a debug adapter. This bit is cleared at power-up if the device is code protected, indicating that the system memory is not accessible from a debug adapter. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 225 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.19 Peripheral Identification 4 Name:

Offset:

Reset:

Property:

PID4 0x1FD0 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 FKBC[3:0]

5 R 0 4 R 0 3 R 0 JEPCC[3:0]

2 R 0 9 1 R 0 8 0 R 0 Bits 7:4 FKBC[3:0]4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 JEPCC[3:0]JEP-106 Continuation Code These bits will always return zero when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 226 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.20 Peripheral Identification 0 Name:

Offset:

Reset:

Property:

PID0 0x1FE0 0x000000D0

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 1 6 R 1 5 R 0 PARTNBL[7:0]

4 R 1 3 R 0 2 R 0 9 1 R 0 8 0 R 0 Bits 7:0 PARTNBL[7:0]Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 227 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.21 Peripheral Identification 1 Name:

Offset:

Reset:

Property:

PID1 0x1FE4 0x0000009C

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 1 JEPIDCL[3:0]

6 R 0 5 R 0 4 R 1 3 R 1 9 1 2 PARTNBH[3:0]

R 1 R 0 8 0 R 0 Bits 7:4 JEPIDCL[3:0]Low Part of the JEP-106 Identity Code These bits will always return 0x9 when read (JEP-106 identity code is 0x29). Bits 3:0 PARTNBH[3:0]Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 228 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.22 Peripheral Identification 2 Name:

Offset:

Reset:

Property:

PID2 0x1FE8 0x0000000A

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit Access Reset 7 R 0 6 5 REVISION[3:0]

R 0 R 0 4 R 0 3 JEPU R 1 2 R 0 1 JEPIDCH[2:0]

R 1 8 0 R 0 Bits 7:4 REVISION[3:0]Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. Bit 3 JEPUJEP-106 Identity Code is Used This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 JEPIDCH[2:0]JEP-106 Identity Code High These bits will always return 0x2 when read, (JEP-106 identity code is 0x29). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 229 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.23 Peripheral Identification 3 Name:

Offset:

Reset:

Property:

PID3 0x1FEC 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 REVAND[3:0]

6 R 0 5 R 0 4 R 0 3 R 0 CUSMOD[3:0]

2 R 0 9 1 R 0 8 0 R 0 Bits 7:4 REVAND[3:0]Revision Number These bits will always return 0x0 when read. Bits 3:0 CUSMOD[3:0]ARM CUSMOD These bits will always return 0x0 when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 230 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.24 Component Identification 0 Name:

Offset:

Reset:

Property:

CID0 0x1FF0 0x0D

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 5 R 0 4 3 PREAMBLEB0[7:0]

R R 1 0 2 R 1 9 1 R 0 8 0 R 1 Bits 7:0 PREAMBLEB0[7:0]Preamble Byte 0 These bits will always return 0x0D when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 231 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.25 Component Identification 1 Name:

Offset:

Reset:

Property:

CID1 0x1FF4 0x00000010

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit Access Reset 7 R 0 CCLASS[3:0]

6 R 0 5 R 0 4 R 1 3 R 0 2 1 PREAMBLE[3:0]

R R 0 0 8 0 R 0 Bits 7:4 CCLASS[3:0]Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (For more details, refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 PREAMBLE[3:0]Preamble These bits will always return 0x0 when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 232 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.26 Component Identification 2 Name:

Offset:

Reset:

Property:

CID2 0x1FF8 0x05

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 5 R 0 4 3 PREAMBLEB2[7:0]

R R 0 0 2 R 1 9 1 R 0 8 0 R 1 Bits 7:0 PREAMBLEB2[7:0]Preamble Byte 2 These bits will always return 0x05 when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 233 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Device Service Unit (DSU) 12.13.27 Component Identification 3 Name:

Offset:

Reset:

Property:

CID3 0x1FFC 0xB1

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 1 6 R 0 5 R 1 4 3 PREAMBLEB3[7:0]

R R 0 1 2 R 0 9 1 R 0 8 0 R 1 Bits 7:0 PREAMBLEB3[7:0]Preamble Byte 3 These bits will always return 0xB1 when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 234 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13. Clock and Reset Unit (CRU) 13.1 Overview The Clock and Reset Unit (CRU) provides both clocking and reset functions. This chapter describes the clocking and reset functionality, summarizes the clock distribution and terminology in the PIC32CX-BZ3 device. CRU handles the clock control to provide system clocks and interface peripheral clocks. Clock is distributed to different peripheral through peripheral specific configuration. For more details on configuration, see the respective peripherals chapters. CRU controls switching and synchronization of clock sources. 13.2 Features The Clock and Reset Unit has the following features:

Supports the following as system clock sources:

16 MHz Primary Crystal Oscillator (POSC) 8 MHz Fast RC Oscillator (FRC) 32.768 kHz Low Power RC Oscillator (LPRC) 32.768 kHz Secondary Crystal Oscillator (SOSC) 64 MHz System PLL (RFPLLPGM MHz)) Provides control registers for PLL Provides glitch-free clock switching between various clock sources Post dividers on processor clock generator to slow down system clock for power save A fail safe clock monitor that detects clock failure and provides automatic switching to the FRC Provides control registers for user interface of clocks and resets Provides configuration bits for oscillator selection and calibration of on-chip oscillators Provides control registers to generate a reference clock output Provide resets for the system Provides NMI interrupts for the system Multiple PB clock (peripheral clock) dividers One System Clock, SYS_CLK, from which almost all clocks used throughout the system are derived Three Peripheral Clocks, created by independent integer dividers of the SYS_CLK:

PB1_CLK: PB-Bridge-D and PB-Bridge-A PB2_CLK: PB-Bridge-B and PB-Bridge-C PB3_CLK: DS/XDS Bus Clock. Six Reference Output Clocks (REFO1 - REFO6) with the following clock sources:

System clock (SYS_CLK) PB1 Bus Clock (PB1_CLK) 16 MHz Primary Crystal Oscillator (POSC) 8 MHz Fast RC Oscillator (FRC) 32.768 kHz Low Power RC Oscillator (LPRC) 32.768 kHz Secondary Crystal Oscillator (SOSC) 64 MHz System PLL (RFPLL PGM MHz), SPLL_CLK1 REFI Pin Provides clock source for Backup core for sleep operations 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 235 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.3 Clock System 13.3.1 Block Diagram The Clock System along with the PMD (for more details, see Peripheral Module Disable Chapter) provides gated clock output for all peripheral buses. The following figure shows the Clock System diagram. Figure 13-1. CRU - Clock System Diagram Configuration PB BUS UPB BUS BIF SFR Decode/CTRL FRC Calibration FRC Oscillator xPLLCON PBxDIV REFOxCON REFOxTRIM OSCCON OSCTRM OSCCON.FRCDIV[2:0]

ADC cp_clk AD-CP spll_clk2 frc_clk I V D _ C R F i i r e d v D M G P rf_64mhz_clk XTAL_IN z H M 6 1 ZBT RF 16 MHz XTL OSC XTAL_OUT rf_ref_clk_16 posc_clk RFPLL Wrapper frc_clk VDD-AON LPRC Oscilator SOSC_CTRL z H k 8 6 7 2 3

. SOSCI SOSCO SOSC REFI

0

3

C S O C N O C C S O

. Fail Safe Clock Monitor

(FSCM) LP Modes Event Switch Master Clock Switch

(MCS)

[ ]0

[ ]1

[ ]2

[ ]4

[ ]3 spll_clk1 posc_clk

(16 MHz) lprc_clk sosc_clk cru_fscm_event l

, k c _ 1 b p l

, k c _ 2 b p l k c _ 3 b p l k c _ s y s Clock Source Generator

(CLKGEN) N O C x O F E R FRC spll_clk1 posc_clk (16 MHz) lprc_clk sosc_clk spll_clk3 (RFPLL 64-MHz) pb1_clk sys_clk

[ ]0

[ ]1

[ ]2

[ ]4

[ ]3

[ ]5

[ ]6

[ ]7

[ ]8 refo_clk_en[6:1]

refo_clk[6:1]

Reference Clock Generator

(REFO[6:1]) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 236 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Figure 13-2. RFPLL Wrapper posc_clk frc_clk rf_64mhz_clk PGM-DIV

(4'b) CLKGATE spll_clk2 SPLLCON.SPLL2POSTDIV2[3:0]

SPLL2_CLK_REQ PGM-DIV

(8'b) CLKGATE spll_clk1 RFPLL Wrapper SPLLCON.SPLL1POSTDIV1[7:0]

SPLL1_CLK_REQ Figure 13-3. Peripheral Clock Generation (GCLK) Peripheral Channel refo_clk[1]

refo_clk[2]

refo_clk[3]

refo_clk[4]

refo_clk[5]

refo_clk[6]

32KHz_LPCLK gclk_<peripheral>

gclk_<peripheral>

CLKGATE gclk_<peripheral>

X U M H C P CFGPCLKGENx.CD CFGPCLKGENx.CSEL[2:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 237 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Figure 13-4. Low Power Clock Generation (LPCLK) E R O C P K U B D D V L E S C K 1 _ P K B V 4 N O C G F C

. I L E S V D _ P K B V 4 N O C G F C

. c t r _ k l c p l 1 0 K L C P L _ z H K 1 r o 2 3

. 5 2 1 3 0 1 K L C P L _ z H K 2 3 r o 1 4 2 0 1

. K L C P L _ z H K 2 3

) c r p l

t d w s d _ k l c p l

) c s o s

t d w s d _ k l c p l L E S C _ M T N C T R 4 N O C G F C

. K L C P L _ z H K 2 3 D O M _ K L C P L M 4 N O C G F C

. LPCLKMUX 1 0

, 2 3

. 3 _ P K B V 4 N O C G F C L E S C K 2 C S O S

) z H K 8 6 7 2 3

) z H K 8 6 7 2 3

. C R P L

) z H K 2 3

t u o _ v i d k l c p l I V D K L C P L 0 5 2 G C n e v i d c s o p _ g f c

n e v i d c r f _ g f c

) z H M 8

C R F LPCLKDIVMUX 0 1 n e v i d c s o p _ g f c 2

) z H M 6 1

C S O P 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 238 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) The CRU Master Clock Switch (MCS) selects which input clock is fed to the CLKGEN Synchronous Clock Generator. The CLKGEN generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks

(APB and AHB) and the synchronous (to the CPU) user interfaces of the peripherals. It contains prescalers for the CPU and bus clocks. 13.3.2 Oscillators 13.3.2.1 Fast RC Oscillator (FRC) The on-chip 8 MHz Fast RC Oscillator (FRC) is a fast with precise frequency internal RC oscillator. The FRC oscillator is accurate to provide the clock frequency which is necessary to maintain baud rate tolerance for serial data transmissions. Power-on Reset (POR) sets OSCCON.NOSC[3:0] = 0000, hence, the device starts with FRC when powered-up. The oscillator module provides a 6-bit wide user tuning adjustment using the OSCTRM.TUN[5:0] bits. 13.3.2.1.1 Enabling the FRC The FRC oscillator is powered when, OSCCON.NOSC[3:0] = 4b0000 or a Fail-safe clock monitor is enabled and a clock fail is detected, forcing a switch to FRC. It is also enabled, whenever, SPLL_CLK2 of ADC PMU Controller, Flash Controller, and 32KHz_LPCLK (32 KHz) request as source. 13.3.2.1.2 Frequency Tuning in User Mode In addition to the factory calibration, the base frequency can be tuned in the user's application. This frequency tuning capability allows the user to deviate from the factory calibrated frequency. The user can tune the frequency by writing to the OSCTRM.TUN[5:0] register bits. 13.3.2.2 Low Power RC Oscillator (LPRC) The Low Power Internal RC Oscillator (LPRC) operates at a nominal frequency of 32.768 kHz. Note:The LPRC is not a 50% duty cycle clock; however, it maintains an average frequency over a number of base clocks. The LPRC can be used as both a source for the system clock and a reference for Backup core modules. These modules include the Deep Sleep Watchdog (DSWDT), clock monitor circuits and other modules that require a 32 kHz reference clock. 13.3.2.3 Primary Oscillator (POSC) A 16 MHz 20 ppm crystal/resonator oscillator or external clock is the primary oscillator for 2.4G RF transceiver. This is the input clock source for System PLL providing up to 64 MHz clock. 13.3.2.4 Secondary Oscillator (SOSC) The Secondary Oscillator (SOSC) is a low-power 32.768 kHz crystal oscillator, which provides accurate time keeping. The Secondary Oscillator has the following features:

32.768 kHz operation Provides system clock (SYS_CLK) output Provides source to CRU or LPCLKGEN on request Provides clock for the low power mode 13.3.3 System and Peripheral Bus Clock Generation (CLKGEN) The CLKGEN module generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well as, the synchronous (to the CPU) user interfaces of the peripherals. It contains prescalers for the CPU and bus clocks. There are two types of clocks generated by this module, called system clocks and peripheral clocks. The system clock (SYS_CLK) is typically used by the CPU, and it supports components such as memory subsystems, and fast peripherals. The peripheral bus clocks (PB1_CLK, PB2_CLK, and PB3_CLK) are used to clock slow perpipheral devices attached to the pb_bus. The PBx_CLK outputs are based on the SYS_CLK frequency with a fixed divisor. The divisor is determined by the value of the PBxDIV registers. The system and peripheral bus clocks are stopped when in Sleep mode. The clocks are restarted by disabling the sleep enable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 239 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.3.4 FRC Divider (FRCDIV) The Fast RC (FRC) oscillator can be divided and used as a system clock and REFO clock with the help of divider setting using the OSCCON.FRCDIV[2:0] register bits. The divisor is configured for eight divider selections: /1, /2, /4, /8, /16, /32, /64, /256. 13.3.5 RFPLL Wrapper The output of RFPLL wrapper is used as a system clock or REFO clock source. Selection of the system clock source is performed with the OSCCON.NOSC[3:0] register field. The RFPLL wrapper generates two clocks:

SPLL_CLK1 (PGM MHz) Clock frequencies = 64 MHz/(1-255) frequency choices Clock ready indication SPLL_CLK2 (PGM MHz) Clock frequencies = 64 MHz/(1-15) and optional clock disable option Clock ready indication Clocks are produced only when the consumer generates a request; CRU is the consumer for SPLL_CLK1

(SPLL_CLK1 is chosen through OSCCON.NOSC[3:0]) and ADC charge pump is the consumer for SPLL_CLK2,

(SPLLCON.SPLL_BYP[1:0]). Along with the clocks, individual clock ready is also generated which indicates that clocks are ready for consumption. 13.3.6 Reference Clock (REFO_CLK) Generation The reference clock generator module uses multiple clock sources as input source and generates six different reference clock outputs. The REFOxCON registers are used to configure the input clock source and divisor. The Clock sources for Reference clock generator:

System clock (SYS_CLK) PB1 bus clock (PB1_CLK) 16 MHz Primary Crystal Oscillator (POSC) 8 MHz Fast RC Oscillator (FRC) 32.768 kHz Low Power RC Oscillator (LPRC) 32.768 kHz Secondary Crystal Oscillator (SOSC) 64 MHz system PLL (RFPLL PGM MHz, SPLL_CLK1, SPLL_CLK3) REFI pin External clock input (REFI) is provided on anyone of the supported I/O pins. For details on supported input pins, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. The following table lists the clocks source mapping for both the CLKGEN generator and REFO_CLK generator. Table 13-1. CRU Source and Output Clock Mapping Clock Source CLKGEN Selection

(OSCCON.NOSC[3:0]) REFO Selection

(REFOxCON.ROSEL[3:0]) FRC SPLL_CLK1 POSC (16 MHz) SOSC LPRC SPLL_CLK3 (RFPLL, 64 MHz) PB1_CLK 0000 0001 0010 0011 0100

0000 0001 0010 0011 0100 0101 0110 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 240 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU)

...........continued Clock Source SYS_CLK REFI Pin

CLKGEN Selection

(OSCCON.NOSC[3:0]) REFO Selection

(REFOxCON.ROSEL[3:0]) 0111 1000 Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 13.3.7 Peripheral Clock Generation (GCLK) All the six Reference Clock Generator outputs are given as input for GCLK generator module for peripheral clock generation. The GCLK module provides selection among following clocks:

REFO1 to REFO6 clocks Low power clock (32KHz_LPCLK) (either LPRC, SOSC, or 32 KHz clock derived from POSC/FRC) The GCLK generator provides the Generic Clocks (GCLK_<Periperhal>) for system peripherals via Peripheral Channels. There are a total of 26 Peripheral Channels, with the mapping as shown in following table. The peripheral channels are fixed configuration, mapped in CFGPCLKGENx register. CFGPCLKGENx dictates the peripheral clock selection and enables the clock for specific peripheral. Table 13-2. Peripheral Clock Generation Peripheral Clock Pchannel Index Position in CFGPCLKGENx GCLK_EIC, GCLK_CCL GCLK_FREQM_MSR GCLK_FREQM_REF GCLK_SERCOM0_CORE, GCLK_SERCOM1_CORE GCLK_SERCOM2_CORE GCLK_TC0 GCLK_TC1 GCLK_TC2, GCLK_TC3 GCLK_TC4, GCLK_TC5 GCLK_TC6, GCLK_TC7 GCLK_EVSYS_CH_0 GCLK_EVSYS_CH_1 GCLK_EVSYS_CH_2 GCLK_EVSYS_CH_3 GCLK_EVSYS_CH_4 GCLK_EVSYS_CH_5 GCLK_EVSYS_CH_6 GCLK_EVSYS_CH_7 GCLK_EVSYS_CH_8 GCLK_EVSYS_CH_9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 2 1 3 4 24 25 26 27 28 8 9 10 11 12 13 14 15 16 17 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 241 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU)

...........continued Peripheral Clock Pchannel Index Position in CFGPCLKGENx GCLK_EVSYS_CH_10 GCLK_EVSYS_CH_11 GCLK_TCC0 GCLK_TCC1, GCLK_TCC2 GCLK_AC GCLK_CM4_TRACE 20 21 22 23 24 25 18 19 21 5 20 7 The following figure shows an example, where SERCOM0 is clocked by the SPLL_CLK1. The SPLL_CLK1 is input to REFO generator. The Generic Clock Generator uses the REFO_CLK1 as its clock source and feeds into Peripheral Channel 3. The Generic Clock channel 3, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface is clocked by PB1_CLK bus clock. Figure 13-5. Example of SERCOM0 Clock GCLK REFO_CLK REFO_CLK1 Generic Clock Generator Peripheral Channel 3 GCLK_SERCOM0_CORE SERCOM 0 CLKGEN PB1_CLK SPLL_CLK1 13.3.8 LPCLK Divider Low power clock divider module provides clock source for low power domain (VDDBUKUPCORE) modules. There are two sources of sleep clock sources, such as, 32 KHz, and 32.768KHz clock. These clock sources are either from LPRC, SOSC, or derived from POSC/FRC modules such as, RTCC requires 32.768 KHz in the RTC mode, whereas Bluetooth link controller requires 32 KHz clock to maintain Bluetooth clock in the standby sleep mode. Therefore, if LPCLK source is 32 KHz, the RTC divider must be 31.25 which, the user can select using CFGCON4.VBKP_DIVSEL. If LPCLK source is 32.768 KHz, program CFGCON4.MLPCLK_MOD to divide it by 1.024. See Power Management Unit (PMU) for low power mode from Related Links. Related Links 14. Power Management Unit (PMU) 13.3.9 Start-Up Considerations The presence of hardware NVR configuration fuses on the PIC32CX-BZ3 device allows the system configuration fuses to be ready upon exiting reset. The following start-up conditions exist:

On any device Reset, no start-up time is required to transfer configuration values from the NVR memory into the configuration holding registers. Once the device is active, the user may change the primary system clock source from FRC to SPLL by using the OSCCON register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 242 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.3.10 Fail-Safe Clock Monitor The Clock System includes a Fail-safe Clock Monitor (FSCM). The FSCM monitors the SYS_CLK for continuous operation. If it detects that the SYS_CLK has failed, it switches the SYS_CLK over to the FRC oscillator and triggers a NMI. The FRC is an untuned 8 MHz oscillator that drives the SYS_CLK during FSCM event. When the NMI is executed, software can restart the main oscillator or shut down the system. The SYS_CLK and the FSCM halt in the Sleep modes prevents FSCM detection. 13.4 Resets The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The device Reset sources are as follows:

Power-on Reset (Vdd, I/O, or POR) Brown-out Reset (BOR/ZPBOR) Master Clear Reset (NMCLR) Watchdog Timer Reset (NMI Counter) Dead Man Timer Reset (NMI Counter) Software Reset (SWR) Configuration Mismatch Reset (CMR) A simplified block diagram of the Reset module is shown in the following figure. Any active source of reset will make the system Reset (SYSRST) signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Figure 13-6. CRU-System Reset Block Diagram NMCLR NMI Time-out Power-up Timer Brown-out Reset Standby Sleep or Idle WDT Time-out DMT Time-out Voltage regulator enabled VDD VDD Rise Detect Configuration Mismatch Reset Software Reset Glitch Filter NMCLR DMTR/WDTR POR BOR CMR SWR SYSRST 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 243 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.4.1 Control Registers Most types of device resets set its corresponding Status bits in the RCON register to indicate the type of Reset. The one exception is for the Non-maskable Interrupt (NMI) time-out Reset. A Power-on Reset (POR) clears all RCON bits, except the BOR and POR bits (RCON[1:0]), which are set. The user software may set or clear any of the bits at any time during code execution. The RCON bits serve only as Status bits. Setting a Reset status bit in software does not cause a system Reset to occur. The RCON register also has other bits associated with the Watchdog Timer (WDT) and device power-saving states. For more information on the function of these bits. See Using the RCON Status Bits from Related Links. The RSWRST control register has only one bit, SWRST. This bit is used to force a software Reset condition. A delay equal to the duration of the number of RNMICON.NMICNT, the system clocks begins as it is decremented to zero. During this interval, the program can clear the WDT or DMT flag bits, if desired, to avoid a Reset. If the active flag is not cleared, the device resets at the end of the interval. The RNMICON.NMICNT value can be set to zero for no delay and up to 255 SYS_CLK cycles. The user can also trigger the NMI interrupt by setting the RNMICON.SWNMI bit in software, or if the RNMICON.CF bit is set by the FSCM. But these do not begin the countdown and do not automatically lead to a reset. The Resets module consists of the following Special Function Registers (SFRs):

RCON - Reset Control Register RSWRST - Software Reset Register RNMICON - Non-maskable Interrupt (NMI) Control Register Related Links 13.4.3.3. Using the RCON Status Bits 13.4.2 Modes of Operation 13.4.2.1 System Reset (SYSRST) The internal System Reset (SYSRST) can be generated from multiple Reset sources, such as:

Power-on Reset (POR) Brown-out Reset (BOR/ZPBOR) Master Clear Reset (NMCLR)(EXTR) Watchdog Time-out Reset (WDTO) Deadman Timer Reset (DMTR) Software Reset (SWR) Configuration Mismatch Reset (CMR) 13.4.2.1.1 Power-on Reset (POR) A power-on event generates an internal POR pulse when a VDD rise is detected above VPOR. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and VDD rise-rate specifications, see Electrical Characteristics from Related Links. This device has on-chip internal voltage regulator and its power-on delay is designated as TPU. For more information on the TPU specification, see Electrical Characteristics from Related Links. When the POR event has expired, but the device Reset is still asserted while device configuration settings load, and the clock oscillator sources configure, the clock monitoring circuitry waits for the oscillator source to become stable. The clock source of this device when exiting from Reset, is always OSCCON.NOSC. After these delays expire, the system Reset, SYSRST, is de-asserted. Before allowing the CPU to start code execution, eight system clock cycles (SYS_CLK) are required before the synchronized Reset to the CPU core is de-asserted. Once the device is active, the user may change the primary system clock source from FRC to SPLL by using the OSCCON register The power-on event sets the BOR and POR status bits (RCON[1:0]). For more information on the values of the delay parameters, see Electrical Characteristics from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 244 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Note:When the device exits the Reset condition (begins normal operation), the device operating parameters

(voltage, frequency, temperature, and so on.) must be within their operating ranges; otherwise, the device will not function correctly. Related Links 38. Electrical Characteristics 13.4.2.1.2 Master Clear Reset (EXTR) Whenever the master clear pin (NMCLR) is driven low, the Reset event is synchronized with the system clock, SYS_CLK, before asserting the system Reset, SYSRST, provided the input pulse on NMCLR is longer than a certain minimum width, as specified in the Electrical Specifications. The NMCLR pin provides a filter to minimize the effects of noise and to avoid unwanted Reset events. The status bit, RCON.EXTR, is set to indicate the NMCLR Reset. EXTR is not a true POR. The user can configure NMCLR pin to generate a POR event by configuring the CFGCON1.SMCLR bit, rather than a EXTR event. 13.4.2.1.3 Software Reset (SWR) This device does not provide a specific RESET instruction; however, a device Reset can be performed in software

(software Reset) by executing a software Reset command sequence. The software Reset acts like a NMCLR Reset. The software Reset sequence requires the system unlock sequence to be executed before writing the RSWRST.SWRST bit. A software Reset is performed as follows:

1. Write the system unlock sequence. 2. Set the SWRST bit (RSWRST[0]) = 1. 3. Read the RSWRST register. Setting the SWRST bit (RSWRST[0]) will arm the software Reset. The subsequent read of the RSWRST register triggers the software Reset, which should occur on the next clock cycle following the read operation. To ensure no other user code is executed before the Reset event occurs, it is recommended that four NOP instructions or a while(1); statement is placed after the READ instruction. The SWR Status bit (RCON[6]) is set to indicate the software Reset. 13.4.2.1.4 Watchdog Timer Reset (WDTO) A Watchdog Timer (WDT) Reset event is synchronized with the system clock (SYS_CLK), before asserting the system Reset. The RNMICON.WDTR flag will be set if there is a WDT event when in the CPU run mode. The device will Reset after the NMI counter expires and RCON.WDTO flag will be set. A WDT timeout during the Standby Sleep or Idle mode will wake-up the processor. The WDTO flag will be set if there is a WDT event. The RNMICON.WDTS flag will be set if there is a WDT event during the Standby Sleep/Idle mode. The WDTS flag will trigger the NMI interrupt, but will not start the NMI counter, nor cause a device Reset. RCON.WDTO will not be affected. See Power Management Unit (PMU) for power modes from Related Links. Related Links 14. Power Management Unit (PMU) 13.4.2.1.5 Brown-out Reset (BOR) This device has a simple Brown-out Reset (BOR) capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry generates a BOR event, which is synchronized with the system clock, SYS_CLK, before asserting the system Reset. This event is captured by the BOR flag bit (RCON[1]). For more information, see Electrical Characteristics from Related Links. Related Links 38. Electrical Characteristics 13.4.2.1.6 Configuration Mismatch Reset (CMR) To maintain the integrity of the stored configuration values, all device Configuration bits are loaded and implemented as a complementary set of bits. As the Configuration Words are being loaded, for each bit loaded as 1, a 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 245 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) complementary value of 0 is stored into its corresponding background word location and vice versa. The bit pairs are compared every time the Configuration Words are loaded, including in Standby Sleep mode. During this comparison, if the Configuration bit values are not found opposite to each other, a configuration mismatch event is generated, which causes a device Reset. If a device Reset occurs as a result of a configuration mismatch, the CMR Status bit (RCON[9]) is set. 13.4.2.1.7 Deadman Timer Reset (DMTR) A Deadman Timer (DMT) Reset is generated when the DMT count has expired. The primary function of the DMT is to Reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in Standby Sleep mode. The DMT consists of a 32-bit counter with a time-out count match value as specified by the CFGCON2.DMTCNT bits in the Configuration register. A DMT is typically used in mission critical and safety critical applications, where any single failure of the software functionality and sequencing must be detected. For more information on the DMT reset, see Deadman Timer (DMT) from Related Links. Related Links 16. Deadman Timer (DMT) 13.4.2.2 Non-maskable Interrupt (NMI) The NMI timer provides a delay between DMT or WDT events and a device Reset. Set the delay in System Clock counts from 0 to 255 in the NMICNT[15:0] bits (RNMICON[15:0]). If these bits are set to zero, there will be no delay between the RNMICON.DMTO or RNMICON.WDTR flag and a device Reset. If set to a non-zero value, the NMI interrupt has that number of system clocks to clear flags or save data for debugging purposes. If the corresponding NMI flag is not cleared in RNMICON before the counter reaches zero, then a device Reset will be issued. If the corresponding NMI flag in RNMICON is cleared before the counter reaches zero, then the counter is stopped, then reloaded with the NMICNT value again and waits for another NMI event to occur. A device reset will not be asserted in this case and software will be able to return from this interrupt. The RNMICON.DMTO flag will be set if there is a DMT event. The device will be Reset after the NMI counter expires. The RNMICON.WDTR flag will be set if there is a WDT event. The device will be Reset after the NMI counter expires. The RNMICON.WDTS flag will be set if there is a WDT event during Standby Sleep mode. The RNMICON.WDTS flag will trigger the NMI interrupt, but will not start the NMI counter, nor cause a Reset. The RNMICON.CF bit may be set by the Fail-Safe Clock Monitor (FSCM) if there a clock failure is detected. The CF flag will trigger the NMI interrupt, but will not start the timer, nor cause a Reset. The RNMICON.SWNMI bit can be set in software to cause a NMI interrupt, but will not start the NMI counter, nor cause a Reset. 13.4.2.3 Determining the Source of Device Reset After a device Reset, the RCON register can be examined to confirm the source of the Reset. All reset status bits in the RCON register must be cleared after reading them to ensure the RCON value will provide meaningful results after the next device Reset. 13.4.3 Effects of Various Resets The Reset value of the Reset Control register, RCON, depends on the type of device Reset, as indicated in the following table. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 246 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Table 13-3. Status Bits, Their Significance and Initialization Condition for RCON Register(1) Condition R T X E R W S O T D W O T M D Power-on Reset or NMCLR set as POR Brown-out Reset NMCLR Reset during the Run Mode NMCLR Reset during the Idle Mode NMCLR Reset during the Standby Sleep Mode Software Reset Command Configuration Word Mismatch Reset WDT Time-out Reset during the Run Mode and NMI counter expires WDT Time-out Reset during the Idle Mode 0 0 1 1 1

WDT Time-out Reset during the Standby Sleep Mode *

DMT Time-out Reset and NMI counter expires Interrupt Exit from the Idle Mode Interrupt Exit from the Standby Sleep Mode

0 0

1

0 0

1

0 0

1

1. Legends:

* = unchanged

) 2

P E E L S Y B D N A T S 0 0

1

1

1 R M C R O B R O P

) 2

E L D I 0 0

1

1

1

0 0

1

1 1

1

2. The device enters the STANDBY SLEEP or IDLE states, when it executes WAIT (WFI) instruction along with the sleep sequence. See Power Management Unit (PMU) for SLEEP/ILDE modes from Related Links. Related Links 14. Power Management Unit (PMU) 13.4.3.1 Special Function Register (SFR) Reset States Most of the SFRs associated with the CPU and peripherals are reset to a particular value at a device Reset. This also applies to a WDT/DMT NMI condition, which is treated as a full device Reset by the CPU and peripherals. The Reset value for the Reset Control register, RCON, is depending on the type of device Reset, see Status Bits, Their Significance and Initialization Condition for RCON Register table in Effects of Various Resets from Related Links. Related Links 13.4.3. Effects of Various Resets 13.4.3.2 Configuration Word Register Reset States All Reset conditions force the configuration settings to be reloaded. The POR and BOR reset all the Configuration Word registers before loading the configuration settings. For all other Reset conditions, the Configuration Word registers are not Reset prior to being reloaded. 13.4.3.3 Using the RCON Status Bits The user software can read the RCON register after any system Reset to determine the cause of the reset. The following table provides a summary of the Reset flag bit operation. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 247 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Note:The status bits in the RCON register must be cleared after they are read, so that the next RCON register value after a device Reset will be meaningful. Table 13-4. Reset Flag Bit Operation Flag Bit Set by Cleared by POR (RCON[0]) BOR (RCON[1]) IDLE (RCON[2]) POR POR, BOR User Software User Software WAIT Instruction User Software, POR, BOR STANDBY SLEEP (RCON[3]) WAIT Instruction User Software, POR, BOR WDTO (RCON[4]) DMTO (RCON[5]) SWR (RCON[6]) EXTR (RCON[7]) CMR (RCON[9]) BCFGFAIL (RCON[26]) BCFGERR (RCON[27]) WDT timeout and NMI counter expires DMT Timeout and NMI counter expires User Software, POR, BOR User Software, POR, BOR Software Reset Command User Software, POR, BOR NMCLR Reset User Software, POR, BOR Configuration Mismatch Reset User Software, POR, BOR Non-recoverable error in Primary and Alternate configuration words User Software, POR, BOR Recoverable error in primary configuration words User Software, POR, BOR 13.4.4 CRU Clock Configuration Registers The Register Summary table shows the mapping of the registers in memory as well as the details of the bit fields in each register. Each register has an associated SET/CLR/INV function register with the suffix appended to the register name, for example: <reg>SET, <reg>CLR, <reg>INV. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 248 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.5 Register Summary See CRU module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links Offset Name Bit Pos. 7 6 5 CLKLOCK DRMEN 2SPDSLP COSC[3:0]

4 SLPEN 3 CF 2 1 0 SOSCEN OSWEN NOSC[3:0]

FRCDIV[2:0]

TUN[5:0]

0x00 OSCCON 0x04

... 0x0F Reserved 0x10 OSCTRM 0x14

... 0x1F Reserved 0x20 SPLLCON 0x24

... 0x2F Reserved 0x30 RCON 0x34

... 0x3F Reserved 0x40 RSWRST 0x44

... 0x5F Reserved 0x60 RNMICON 0x64

... 0x6F Reserved 0x70 REFO1CON 0x74

... 0x7F Reserved 0x80 REFO1TRIM 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 SPLLFLOCK SPLLPWDN SPLL1POSTDIV1[7:0]

SPLL2POSTDIV2[3:0]

SPLL_BYP[1:0]

EXTR SWR DMTO WDTO SLEEP IDLE DPSLP BOR CMR POR VBAT POR_IO POR_CORE BCFGERR BCFGFAIL NVMLTA NVMEOL SWRST SWNMI EXT PLVD CF DMTO WDTS WDTR NMICNT[7:0]

NMICNT[15:8]

ON FRZ SIDL OE RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 ROSEL3 ROSEL2 ROSEL1 ROSEL0 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 249 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x84

... 0x8F Reserved 0x90 REFO2CON 0x94

... 0x9F Reserved 0xA0 REFO2TRIM 0xA4

... 0xAF Reserved 0xB0 REFO3CON 0xB4

... 0xBF Reserved 0xC0 REFO3TRIM 0xC4

... 0xCF Reserved 0xD0 REFO4CON 0xD4

... 0xDF Reserved 0xE0 REFO4TRIM 0xE4

... 0xEF Reserved 0xF0 REFO5CON 0xF4

... 0xFF Reserved 0x0100 REFO5TRIM 0x0104

... 0x010F Reserved 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ON FRZ SIDL OE RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 ROSEL3 ROSEL2 ROSEL1 ROSEL0 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 ON FRZ SIDL OE RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 ROSEL3 ROSEL2 ROSEL1 ROSEL0 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 ON FRZ SIDL OE RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 ROSEL3 ROSEL2 ROSEL1 ROSEL0 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 ON FRZ SIDL OE RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 ROSEL3 ROSEL2 ROSEL1 ROSEL0 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 250 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU)

...........continued Offset Name Bit Pos. 7 6 5 ON FRZ SIDL RSLP RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 DIVSW_EN RODIV1 RODIV9 ACTIVE RODIV0 RODIV8 4 OE 3 2 1 0 ROSEL3 ROSEL2 ROSEL1 ROSEL0 0x0110 REFO6CON 0x0114

... 0x011F Reserved 0x0120 REFO6TRIM 0x0124

... 0x012F Reserved 0x0130 PB1DIV 0x0134

... 0x013F Reserved 0x0140 PB2DIV 0x0144

... 0x014F Reserved 0x0150 PB3DIV 0x0154

... 0x015F Reserved 0x0160 SLEWCON 0x0164

... 0x016F Reserved 0x0170 CLKSTAT 0x0174

... 0x018F Reserved 0x0190 CLK_DIAG 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ROTRIM0 ROTRIM8 ROTRIM7 ROTRIM6 ROTRIM5 ROTRIM4 ROTRIM3 ROTRIM2 ROTRIM1 PB1DIVON PB2DIVON PB3DIVON PB1DIV[6:0]

PB1DIVRDY PB2DIV[6:0]

PB2DIVRDY PB3DIV[6:0]

PB3DIVRDY SLW_UP SLW_DN SLW_BUSY SLW_DIV[2:0]

SYS_DIV[3:0]

SLW_DELAY[3:0]

SPLL3RDY LPRCRDY SOSCRDY POSCRDY SPLL1RDY FRCRDY SPLL3_STOP SPLL1_STOP LPRC_STOP FRC_STOP SOSC_STOP POSC_STOP NMICTR7 NMICTR6 NMICTR5 NMICTR4 NMICTR3 NMICTR2 NMICTR1 NMICTR0 NMICTR15 NMICTR14 NMICTR13 NMICTR12 NMICTR11 NMICTR10 NMICTR9 NMICTR8 Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 251 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 252 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.1 CRU Oscillator Control Name:

Offset:

Reset:

OSCCON 0x00 0x00200003 Note:The system unlock sequence must be done before writing this register. For more details, see Register Locking from Related Links. Bit 31 30 29 28 27 26 25 FRCDIV[2:0]

R/W/L 0 24 R/W/L 0 R/W/L 0 20 19 18 17 16 12 R 0 4 SLPEN R/W/L 0 11 10 9 8 NOSC[3:0]

R/W/L 0 2 R/W/L 0 3 CF R/W/HS/L 0 R/W/L 0 R/W/L 0 1 SOSCEN R/W/L 1 0 OSWEN R/W/HC/L 1 Access Reset Bit Access Reset 23 DRMEN R/W/L 0 Bit 15 Access Reset Bit R 0 7 CLKLOCK Access Reset R/W/L 0 22 14 R 0 6 21 2SPDSLP R/W/L 1 COSC[3:0]

13 R 0 5 Bits 26:24 FRCDIV[2:0]Fast RC Clock Divider bits Value 000 001 010 011 100 101 110 111 Description FRC is divided by 1 (default value) FRC is divided by 2 FRC is divided by 4 FRC is divided by 8 FRC is divided by 16 FRC is divided by 32 FRC is divided by 64 FRC is divided by 256 Bit 23 DRMENEnable Dream Mode bit Value 1 0 Description When the SLEEP/WAIT (WFI) instruction is executed and SLPEN = 1, DMA transfer complete causes the device to enter the SLEEP mode. DMA transfer has no effect Bit 21 2SPDSLP2-Speed start-up enabled in the Standby Sleep mode bit Note:CFGCON2.WAKE2SPD specifies the default Reset value. Value 1 0 Description When the device exits the Standby Sleep mode, the SYS_CLK will be from FRC until the selected clock is ready When the device exits the Standby Sleep mode, the SYS_CLK will be from the selected clock 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 253 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Bits 15:12 COSC[3:0]Current Oscillator Selection bits (Read-only) Notes:

Default value on reset is 4b0000. Loaded with NOSC[3:0] at the completion of a successful clock switch. Set to FRC value (0000), when FSCM detects a failure and switches clock to FRC. Value 0000 0001 0010 0011 0100 0101-111 1 Description Fast RC oscillator (FRC) divided by OSCCON.FRCDIV System PLL Clock-1 (SPLL_CLK1 module) (input clock is 64 MHz from RFPLL wrapper and divider set by SPLLCON) Primary Oscillator (POSC) Secondary Oscillator (SOSC) Low Power RC Oscillator (LPRC) Reserved for future use Bits 11:8 NOSC[3:0]New Oscillator Selection bits Note:Default value on reset is 4b0000. Value 0000 0001 0010 0011 0100 0101-111 1 Description Fast RC oscillator (FRC) divided by OSCCON.FRCDIV System PLL Clock-1 (SPLL_CLK1 module) (input clock is 64 MHz from RFPLL wrapper and divider set by SPLLCON) Primary oscillator- POSC Secondary Oscillator (SOSC) Low Power RC Oscillator (LPRC) Reserved for future use Bit 7 CLKLOCKClock Lock Enabled bit Notes:

Once set, this bit can only be cleared via a Device Reset. When active, this bit prevents writes to the following registers: NOSC[3:0], and OSWEN. Value 1 0 Description All clock and PLL configuration registers are locked. These include OSCCON, OSCTRM, SPLLCON, PBxDIV Clock and PLL selection registers are not locked, configurations may be modified. Bit 4 SLPENEnable SLEEP Mode bit Value 1 0 Description When a WAIT Instruction is executed, the device enters the STANBDY SLEEP mode When a WAIT instruction is executed, the device enters the IDLE mode Bit 3 CFClock Fail Detect bit (Read/Writable/Clearable by application) Notes:

Writing 1 to this bit initiates the clock switching sequence by the clock switch state machine Reset occurs when the clock switch state machine initiates a valid clock switching sequence This bit is set when clock fail event is detected Value 1 0 Description FSCM has detected clock failure FSCM has not detected clock failure Bit 1 SOSCENLow Power Secondary Oscillator Enable bit Note:Set the value specified by SOSCEN configuration bits in CFGCON2.SOSCSEL on RESET. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 254 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Value 1 0 Description Enable Secondary Oscillator Disable Secondary Oscillator Bit 0 OSWENOscillator Switch Enable bit Notes:

Writing 0 to this bit has no effect. Hardware clears this bit after a successful clock switch Hardware clears this bit after a redundant clock switch (NOSC = COSC) Hardware clears this bit after FSCM switches the oscillator to Fail-Safe Clock Source (FRC) Value 1 0 Description Requests oscillator switch to select as specified by NOSC[3:0] bits Oscillator switch is complete 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 255 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.2 CRU Oscillator Trimming Name:

Offset:

Reset:

OSCTRM 0x10 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 9 1 8 0 Access Reset R/W/L 0 R/W/L 0 TUN[5:0]

R/W/L 0 R/W/L 0 R/W/L 0 R/W/L 0 Bits 5:0 TUN[5:0]Internal Fast RC (FRC) Oscillator Tuning bits This bit field specifies the user tuning capability for the internal fast RC oscillator. Note:The system unlock sequence must be done before this register can be written. Description Maximum Frequency Value 011111 011110

... 000001 000000 111111 111110

... 100001 100000 Minimum Frequency Center Frequency, oscillator is running at calibrated frequency 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 256 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.3 SPLL Control Name:

Offset:

Reset:

SPLLCON 0x20 0xC0010028 Note:The system unlock sequence must be done before this register is written. Bit 31 30 29 28 27 26 25 24 SPLL_BYP[1:0]

Access Reset R/W/L 1 R/W/L 1 Bit 23 22 21 20 19 18 17 16 Access Reset R/W/L 0 SPLL2POSTDIV2[3:0]

R/W/L R/W/L 0 0 R/W/L 1 Bit 15 14 13 12 11 10 9 8 Access Reset R/W/L 0 R/W/L 0 R/W/L 0 Bit 7 6 5 Access Reset SPLL1POSTDIV1[7:0]

R/W/L R/W/L 0 0 4 SPLLFLOCK R/W/L 0 3 SPLLPWDN R/W/L 1 Bits 31:30 SPLL_BYP[1:0]SPLL Bypass; SPLL_CLK2 clock source selection Notes:

R/W/L 0 R/W/L 0 R/W/L 0 2 1 0 Dictates clock source for ADC CP (Analog to Digital Converter Charge Pump) (SPLL_CLK2) Clock generation only Clock source must be preselected and kept ready before the need of ADC CP arrives. Failure to do so will result in loss of clock for one or two cycles when ADC CP is enabled. Value 00 x1 10 Description RFPLL Clock is the clock source for ADC CP Clock Generation. FRC is used as clock source for ADC CP Clock Generation. POSC is used as clock source for ADC CP Clock Generation. Bits 19:16 SPLL2POSTDIV2[3:0]ADC-CP (SPLL2) Post Divide Value Value 1 SPLLPOST DIV2 15 0 Description Divide-by SPLL2POSTDIV2 No Clock; Clock disabled Bits 15:8 SPLL1POSTDIV1[7:0]SPLL1 Post Divide Value Description Divide-by SPLL1POSTDIV1 Value 2 SPLLPOST DIV 255 0,1 Divide-by 1 Bit 4 SPLLFLOCKSystem PLL Force Lock 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 257 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Value 1 0 Description Force the SPLL lock signal to be asserted Do not force the SPLL lock signal to be asserted Bit 3 SPLLPWDNPLL Power Down Register bit Value 1 0 Description PLL is powered down PLL is active 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 258 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.4 Reset Control Register Name:

Offset:

Reset:

Property:

RCON 0x30 0x00000000

Bit Access Reset 31 POR_IO R/W/HS 0 30 POR_CORE R/W/HS 0 29 28 27 BCFGERR R/W/HS 0 26 BCFGFAIL R/W/HS 0 25 NVMLTA R/W/HS 0 Bit 23 22 21 20 19 18 17 Access Reset Bit 15 14 13 12 11 Access Reset Bit Access Reset 7 EXTR R/W/HS 0 6 SWR R/W/HS 0 5 DMTO R/W/HS 0 4 WDTO R/W/HS 0 3 SLEEP R/W/HS 0 10 DPSLP R/W/HS 0 2 IDLE R/W/HS 0 9 CMR R/W/HS 0 1 BOR R/W/HS 0 24 NVMEOL R/W/HS 0 16 VBAT R/W/HS 0 8 0 POR R/W/HS 0 Bit 31 POR_IOI/O Voltage POR Flag bit 1 = A Power-on Reset has occurred due to I/O voltage. 0 = A Power-on Reset has not occurred due to I/O voltage. This bit is set by hardware at detection of an I/O POR event. User software must clear this bit to view next detection. Note:Writing 1 to this bit does not cause POR_IO reset. Bit 30 POR_CORECore Voltage POR Flag bit 1 = A Power-on Reset has occurred due to core voltage. 0 = A Power-on Reset has not occurred due to core voltage. This bit is set by hardware at detection of a core POR event. User software must clear this bit to view next detection. Note:Writing 1 to this bit does not cause POR_IO reset. Bit 27 BCFGERRBCFG Error Flag bit 0 = A BCFG error has not occurred. 1 = A BCFG error has occurred. This bit is set when a primary BCFG value has an error but the secondary BCFG value is valid and used. Bit 26 BCFGFAILBCFG Failure Flag bit 0 = A BCFG failure has not occurred. 1 = A BCFG failure has occurred. This bit is set when both the Primary and Secondary BCFG values has an unrecoverable error. Only the default values are in effect. Bit 25 NVMLTANVM Life Time Alert Flag bit 0 = A NVM LTA error has not occurred. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 259 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 1 = A NVM LTA error has occurred. This bit is set due to charge leakage, and the NVM (Flash) is nearing EOL. Bit 24 NVMEOLNVM End of Life Flag bit 0 = A NVM EOL failure has not occurred. 1 = A NVM EOL failure has occurred. This bit may not be visible to user, because the part does not come out of Reset if the bit is asserted. Bit 16 VBATVBAT Mode Flag bit 1 = A POR exit from VBAT has occurred. A true POR must be established with the valid VBAT voltage level on the VBAT pin. 0 = A POR exit from VBAT has not occurred. Bit 10 DPSLPDeep Sleep Mode Flag bit 1 = Deep Sleep mode has occurred. 0 = Deep Sleep mode has not occurred. This bit is set by hardware at the time of entry into the Deep Sleep mode. User software must clear this bit to view next detection. Bit 9 CMRConfiguration Mismatch Reset Flag bit 1 = A CMR event has occurred. 0 = A CMR event has not occurred. Note:Writing 1 to this bit does not cause Mismatch Reset. Bit 7 EXTRExternal Reset (NMCLR) Status bit 1 = A Master Clear (pin) Reset has occurred. 0 = A Master Clear (pin) Reset has not occurred. Note:Writing 1 to this bit does not cause a (NMCLR). Bit 6 SWRSoftware Reset Flag bit 1 = A SWR has occurred. 0 = A SWR has not occurred. Note:Writing 1 to this bit does not cause SWR. Bit 5 DMTODeadman Timer Time-out Flag bit 1 = DMT Time-out has occurred and caused a Reset. 0 = DMT Time-out has not occurred. Note:Writing 1 to this bit does not cause DMT Reset. Bit 4 WDTOWatchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred and caused a Reset. 0 = WDT Time-out has not occurred. Note:Writing 1 to this bit does not cause WDT Reset. Bit 3 SLEEPWake from Standby Sleep Flag bit 1 = Device has been in Standby Sleep mode. 0 = Device has not been in Standby Sleep mode. Note:Writing 1 to this bit does not invoke the Standby Sleep mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 260 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Bit 2 IDLEWake from Idle Flag bit 1 = Device was in Idle mode. 0 = Device was not in Idle mode. Note:Writing 1 to this bit does not invoke the Idle mode. Bit 1 BORBOR Flag bit 1 = A BOR has occurred. 0 = A BOR has not occurred. This bit is set by hardware at detection of a BOR event. User software must clear this bit to view next detection. Note:Writing 1 to this bit does not cause a BOR. Bit 0 PORPOR Flag bit 1 = A Power-on Reset has occurred. 0 = A Power-on Reset has not occurred. This bit is set by hardware at detection of a POR event. User software must clear this bit to view next detection. Note:Writing 1 to this bit does not cause a POR. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 261 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.5 Software Reset Register Name:

Offset:

Reset:

Property:

RSWRST 0x40 0x00000000

Note:The system unlock sequence must be done before writing this register. For more details, see Register Locking from Related Links. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 0 SWRSTSoftware Reset Trigger bit 9 1 8 0 SWRST W/HC 0 1 = Enable SWR event. A subsequent read of this register triggers the system Reset sequence. The system unlock sequence must be done before the bit can be written. This bit always reads a value of logic 0. Related Links 18.6. Register Locking 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 262 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.6 NMI Control Register Name:

Offset:

Reset:

Property:

RNMICON 0x60 0x00000000

Note:The system unlock sequence must be done before writing this register. See System Configuration and Register Locking (CFG) from Related Links. Bit 31 30 29 28 27 26 Access Reset Bit Access Reset 23 SWNMI R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 22 21 20 19 EXT R/W 0 11 12 NMICNT[15:8]

R/W 0 4 R/W 0 3 NMICNT[7:0]

R/W 0 R/W 0 18 PLVD R/W 0 10 R/W 0 2 R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 25 DMTO R/W 0 17 CF R/W 0 9 R/W 0 1 R/W 0 24 WDTR R/W 0 16 WDTS R/W 0 8 R/W 0 0 R/W 0 Bit 25 DMTODeadman Timer Time-out Flag bit (this causes a Reset when NMICNT expires) 1 = DMT Time-out has occurred and caused a NMI. 0 = DMT Time-out has not occurred. Note:Writing 1 to this bit cause a user initiated DMT NMI event and NMICNT start. Bit 24 WDTRWatchdog Timer Time-out in Run Flag bit 1 = WDT Time-out has occurred and caused a NMI (this may cause a Reset if NMICNT expires). 0 = WDT Time-out has not occurred. Note:Writing '1' to this bit cause a user initiated WDT NMI event and NMICNT start. Bit 23 SWNMISoftware NMI Trigger bit 1 = Writing 1 to this bit generates an NMI. 0 = Writing 0 to this bit has no effect. Bit 19 EXTExternal / Generic NMI Event bit 1 = A general NMI event has been detected and caused an NMI. 0 = A general NMI event has not been detected. Note:Writing 1 to this bit cause a user initiated EXT NMI event. Bit 18 PLVDProgrammable Low Voltage Detect Event bit 1 = PLVD has detected a low voltage condition and caused an NMI 0 = PLVD has not detected a low voltage condition 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 263 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Note:Writing 1 to this bit cause a user initiated PLVD NMI event. Bit 17 CFClock Fail Detect bit (Read/Clear-able by application) 1 = FSCM has detected clock failure and caused an NMI 0 = FSCM has not detected clock failure Note:Writing 1 to this bit causes a user-initiated clock failure NMI event, but does not cause a clock switch. Bit 16 WDTSWatch-Dog Timer Time-out in Standby Sleep Flag bit 1 = WDT Time-out has occurred during the Standby Sleep mode and caused a wake-up from sleep. 0 = WDT Time-out has not occurred during the Standby Sleep mode. Note:Writing 1 to this bit cause a user initiated WDT NMI event. Bits 15:0 NMICNT[15:0]NMI Reset counter value bit This bit field specifies the reload value used by the NMI Reset counter. The following events generate an NMI event and/or reset, when the NMI_CNT expires on:

WDT event DMT event Values Description No delay between NMI assertion and device Reset event. 0x0000 0x0001 0x0002

................. ................ ................ 0xFFFE 0xFFFF Number of SYSCLK cycles that Software has to clear the NMI event before a device Reset is performed. If the NMI event is cleared before the counter reached zero, then no device Reset is asserted. Related Links 18. System Configuration and Register Locking (CFG) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 264 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.7 Reference Oscillator x Control REFOxCON 0x70 + (x-1)*0x20 [x=1..6]

0x00000000 Name:

Offset:

Reset:

Notes:

Do not write REFOCON.ROSEL while the REFOCON.ACTIVE bit is 1 - This results in undefined behavior. Do not write REFOCON when REFOCON.ON != REFOCON.ACTIVE - This results in undefined behavior. This register can always be accessed regardless of the SYSKEY value. Bit 31 Access Reset Bit Access Reset Bit Access Reset 23 RODIV7 R/W 0 15 ON R/W 0 Bit 7 Access Reset 30 RODIV14 R/W 0 22 RODIV6 R/W 0 14 FRZ R/W 0 6 29 RODIV13 R/W 0 21 RODIV5 R/W 0 13 SIDL R/W 0 5 28 RODIV12 R/W 0 20 RODIV4 R/W 0 12 OE R/W 0 4 27 RODIV11 R/W 0 19 RODIV3 R/W 0 11 RSLP R/W 0 3 ROSEL3 R/W 0 26 RODIV10 R/W 0 18 RODIV2 R/W 0 10 25 RODIV9 R/W 0 17 RODIV1 R/W 0 24 RODIV8 R/W 0 16 RODIV0 R/W 0 9 DIVSW_EN HC/ R/W 0 8 ACTIVE HS/HC/ R 0 2 ROSEL2 R/W 0 1 ROSEL1 R/W 0 0 ROSEL0 R/W 0 Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 RODIVReference Clock Divider bits Specifies 1/2 period of reference clock in the source clocks. Example: Period of REFO_CLK = [Reference source * 2] * RODIV Value 0x7FFF 0x7FFE

... .. .. 0x0003 0x0002 0x0001 0x0000 Description REFOx clock is Base clock frequency divided by 65,534 (32,767 *2) REFOx clock is Base clock frequency divided by 65,532 (32,766 * 2) REFOx clock is Base clock frequency divided by 6 (3*2) REFOx clock is Base clock frequency divided by 4 (2*2) REFOx clock is Base clock frequency divided by 2 (1*2) REFOx clock is same frequency as Base clock (no divider) Bit 15 ONOutput Enable bit Value 1 0 Description Enables the Reference Oscillator Module Disables the Reference Oscillator Module Bit 14 FRZFreeze in Debug mode bit Value 1 0 Description When emulator is in the Debug mode, module freezes operation When emulator is in the Debug mode, module continues operation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 265 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Bit 13 SIDLPeripheral Stop in Idle Mode bit Value 1 0 Description Discontinue module operation when device enters the Idle mode Continues module operation in the Idle mode Bit 12 OEReference Clock Output Enable bit Value 1 0 Description Reference clock is driven out on REFOx pin Reference clock is not driven out on REFOx pin Bit 11 RSLPReference Oscillator Run in Standby Sleep bit Note:This bit is ignored when ROSEL[3:0] = (0000 or 0001). Value 1 0 Description Reference Oscillator output continues to run in Standby Sleep Reference Oscillator output is disabled in Standby Sleep Bit 9 DIVSW_ENClock RODIV/ROTRIM switch enabled Description Clock Divider Switching is in progress Clock Divider Switch is completed Value 1 0 Bit 8 ACTIVEReference Clock Request Status bit Value 1 0 Description Reference clock request is active (User should not update this REFOCON register) Reference clock request is not active (User can update this REFOCON register) Bits 0, 1, 2, 3 ROSELReference Clock Source Select bits Description Reserved Select one of various clock sources to be used as the reference clock. Value 1001 -

1111 1000 0111 0110 0101 0100 0011 0010 0001 0000 REFI Pin System clock, SYS_CLK (reference clock reflects any device clock switching) Peripheral clock, PB1_CLK (reference clock reflects any peripheral clock switching) System PLL (Clock-3), SPLL_CLK3 LPRC SOSC POSC System PLL (Clock-1), SPLL_CLK1 FRC 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 266 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.8 Reference Oscillator x Trim REFOxTRIM 0x80 + (x-1)*0x20 [x=1..6]

0x00000000 Name:

Offset:

Reset:

Notes:

Do not write REFOxTRIM when REFOxCON.ON != REFOxCON.ACTIVE - This results in undefined behavior. This register can always be accessed regardless of the SYSKEY value. Bit 31 ROTRIM8 Access Reset R/W 0 30 ROTRIM7 R/W 0 29 ROTRIM6 R/W 0 28 ROTRIM5 R/W 0 27 ROTRIM4 R/W 0 26 ROTRIM3 R/W 0 25 ROTRIM2 R/W 0 24 ROTRIM1 R/W 0 Bit 23 ROTRIM0 Access Reset R/W 0 22 21 20 19 18 17 16 Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset 9 1 8 0 Bits 23, 24, 25, 26, 27, 28, 29, 30, 31 ROTRIMTrim bits - Provides fractional additive to RODIV value for 1/2 period of REFOx clock Note:ROTRIM values greater than zero are only valid when RODIV values are greater than 0. Value 0000_0000_0 0000_0000_1 0000_0001_0

... .. 100000000

... .. 1111_1111_0 1111_1111_1 Description 0/512 (0.0) divisor is added to RODIV value 1/512 (0.001953125) divisor is added to RODIV value 2/512 (0.00390625) divisor is added to RODIV value

... .. 256/512 (0.5000) divisor is added to RODIV value

... .. 510/512 (0.99609375) divisor is added to RODIV value 511/512 (0.998046875) divisor is added to RODIV value 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 267 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.9 PBx Clock Divisor Control Name:

Offset:

Reset:

PBxDIV 0x0130 + (x-1)*0x10 [x=1..3]

0x00008800 Note:The system unlock sequence must be done before this register can be written. The Reset value for PB3DIV[6:0] is 0x09. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 PBxDIVON R 1 7 Access Reset Bit Access Reset 6 R/W 0 5 R/W 0 4 R/W 0 11 PBxDIVRDY R 1 3 PBxDIV[6:0]

R/W 0 10 2 R/W 0 9 1 8 0 R/W 0 R/W 0 Bit 15 PBxDIVON(x=1 to 3) Output Enable bit Value 1 0 Description Enables PBx Output clock Disables PBx Output clock Note:Do not write PB1DIV.PB1DIVON bit as 0, as the CRU system uses this clock, and it is one of the source for REFO. Bit 11 PBxDIVRDY(x=1 to 3) PBx Peripheral Clock Divisor Ready Value 1 0 Description Indicates the PB clock divisor logic is not switching divisors and the PBxDIV may be written. Indicates the PB clock divisor logic is currently switching values and the PBxDIV cannot be written. Bits 6:0 PBxDIV[6:0](x=1 to 3) PBx Peripheral Clock Divisor Control value Description Value 000_0000 Divide by 1 PBx Clock same frequency as SYS_CLK 000_0001 Divide by 2 PBx Clock is 1/2 of SYS_CLK 000_0010 Divide by 3 PBx Clock is 1/3 of SYS_CLK 000_0011 Divide by 4 PBx Clock is 1/4 of SYS_CLK

... .. 000_1111 Divide by 16 PBx Clock is 1/16 of SYS_CLK 001_0000 Divide by 17 PBx Clock is 1/17 of SYS_CLK

... .. 111_1110 Divide by 127 PBx Clock is 1/127 of SYS_CLK 111_1111 Divide by 128 PBx Clock is 1/128 of SYS_CLK

... .. .. .. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 268 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.10 Slew Rate Control for Clock Switching SLEWCON 0x160 0x00000000 Name:

Offset:

Reset:

Notes:

The system unlock sequence must be done before this register is written. Updates to this register do not take affect until OSCCON.OSWEN is set. Bit 31 30 29 28 Access Reset Bit 23 22 21 20 Access Reset Bit 15 14 13 12 Access Reset 27 R/W c 19 R/W c 11 Bit 7 6 5 4 3 Access Reset 26 25 SLW_DELAY[3:0]

R/W c 18 R/W c 17 SYS_DIV[3:0]

R/W c 10 R/W c R/W c 9 SLW_DIV[2:0]

R/W c 2 SLW_UP R/W c 1 SLW_DN R/W c 24 R/W c 16 R/W c 8 R/W c 0 SLW_BUSY R/W c Bits 27:24 SLW_DELAY[3:0]Number of clocks generated at each slew step for a clock switch Note:The input, cfg_slewcon_sel[] defines the reset value of this register field. Value 0000 0001

... 1111 Description 1 clock is generated at each slew step 2 clocks is generated at each slew step

... 16 clocks are generated at each slew step Bits 19:16 SYS_DIV[3:0]PBx Peripheral Clock Divisor Control value Value 0000 0001 0010

... 1111 Description Divide by 1 - SYS_CLK_OUT same frequency as SYS_CLK source - Default Divide by 2 - SYS_CLK_OUT is 1/2 of SYS_CLK source Divide by 3 - SYS_CLK_OUT is 1/3 of SYS_CLK source

... Divide by 16 - SYS_CLK_OUT is 1/16 of SYS_CLK source Bits 10:8 SLW_DIV[2:0]Divisor steps are used when doing slewed clock switches Note:Each Divisor step lasts for four clocks Value 000 001 010 011 100

... Description No Divisor is used Divide by 2 (21), then no divisor is used Divide by 4 (22), then by 2, then no divisor is used Divide by 8 (23), then by 4, then by 2, then no divisor is used Divide by 16 (24), then by 8, then by 4, then by 2, then no divisor is used

... 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 269 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Value 111 Description Divide by 128 (27), then by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor is used Bit 2 SLW_UPEnables clock slew for switching up to faster clocks Value 0 1 Description Disables Clock Slewing Enables Clock Slewing on a clock switch or exits from the Standby Sleep mode Bit 1 SLW_DNEnables clock slew for switching down to slower clocks Value 0 1 Description Disables Clock Slewing Enables Clock Slewing on a clock switch Bit 0 SLW_BUSYClock Switch Slewing Active Status Bit - Read-Only Value 0 1 Description Clock Switch has reached its final value Clock frequency is being actively Slewed 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 270 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.11 Clock Status Name:

Offset:

Reset:

CLKSTAT 0x170 0x00000000 Note:The corresponding RDY bits are updated only after clock switch request is initiated via OSCCON.NOSC[3:0]. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 Access Reset 5 SPLL3RDY R/HS/HC 0 4 LPRCRDY R/HS/HC 0 3 SOSCRDY R/HS/HC 0 2 POSCRDY R/HS/HC 0 1 SPLL1RDY R/HS/HC 0 0 FRCRDY R/HS/HC 0 Bit 5 SPLL3RDYSystem PLL (Clock-3) Ready Status value Description SPLL_CLK3 is stable and ready SPLL_CLK3 is not stable and not ready Value 1 0 Bit 4 LPRCRDYLPRC Ready Status value Value 1 0 Description LPRC is stable and ready LPRC is not stable and not ready Bit 3 SOSCRDYSOSC Ready Status value Value 1 0 Description SOSC is stable and ready SOSC is not stable and not ready Bit 2 POSCRDYPrimary Oscillator Ready Status value Value 1 0 Description POSC is stable and ready POSC is not stable and not ready Bit 1 SPLL1RDYSystem PLL (Clock-1) Ready Status value Description SPLL_CLK1 is stable and ready SPLL_CLK1 is not stable and not ready Value 1 0 Bit 0 FRCRDYFRC Ready Status value Value 1 0 Description FRC is stable and ready FRC is not stable and not ready 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 271 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) 13.6.12 User Clock Diagnostics Control Name:

Offset:

Reset:

CLK_DIAG 0x190 0x00000000 Note:The system unlock sequence must be done before this register can be written. Bit 31 NMICTR15 Access Reset R 0 30 NMICTR14 R 0 29 NMICTR13 R 0 28 NMICTR12 R 0 Bit Access Reset 23 NMICTR7 R 0 22 NMICTR6 R 0 21 NMICTR5 R 0 20 NMICTR4 R 0 27 NMICTR11 R 0 19 NMICTR3 R 0 26 NMICTR10 R 0 18 NMICTR2 R 0 25 NMICTR9 R 0 17 NMICTR1 R 0 24 NMICTR8 R 0 16 NMICTR0 R 0 Bit 15 14 13 12 11 10 Access Reset Bit 7 6 Access Reset 5 4 SPLL3_STOP SPLL1_STOP LPRC_STOP R/W 0 R/W 0 R/W 0 3 2 FRC_STOP R/W 0 9 1 8 0 SOSC_STOP POSC_STOP R/W 0 R/W 0 Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 NMICTRInternal value of internal NMI Counter This field reflects the actual value of internal NMI counter Bit 5 SPLL3_STOPSPLL Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description SPLL_CLK3 clock source runs as normal SPLL_CLK3 clock source is stopped Bit 4 SPLL1_STOPSPLL Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description SPLL_CLK1 clock source runs as normal SPLL_CLK1 clock source is stopped Bit 3 LPRC_STOPLPRC Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description LPRC clock source runs as normal LPRC clock source is stopped Bit 2 FRC_STOPFRC Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description FRC clock source runs as normal FRC clock source is stopped 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 272 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Clock and Reset Unit (CRU) Bit 1 SOSC_STOPSOSC Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description SOSC clock source runs as normal SOSC clock source is stopped Bit 0 POSC_STOPPOSC Clock Stop Control value Note:This gating logic is outside the CRU module. Value 0 1 Description POSC clock source runs as normal POSC clock source is stopped 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 273 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14. Power Management Unit (PMU) 14.1 Overview This chapter describes the Power Management Unit (PMU) in the PIC32CX-BZ3 wireless microcontroller with the various power saving modes it provides. The PMU controls the sleep modes and the power domain gating of the device. Various sleep modes are provided to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In the Active mode, the CPU is executing application code. When the device enters the Sleep mode, program execution is stopped and some modules and clock domains are automatically switched off according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from the Sleep mode to Active mode. Note:The PMU is a complex power controller that requires specific configuration and handling by the software for correct, safe operation of the SOC. The software SDK and operational stacks provided by Microchip handles the start-up and operation of the PMU. Therefore, Microchip highly recommends using this software framework for all application development on the device. 14.2 Features Low power modes: Idle, Standby Sleep, Deep Sleep, Extreme Deep Sleep SleepWalking/Dream available in the Standby Sleep mode FlexRAM (SRAM) retention in the Standby Sleep, and Deep Sleep mode I/O lines retention in the Deep Sleep mode 14.3 Functional Description 14.3.1 Power Modes The power modes and power management of different modules of the PIC32CX-BZ3 are shown in the following table. Table 14-1. Power Modes and Power Management Features Functions Device Power Modes Run Idle SleepWalking/

Dream(1) Standby Sleep Deep Sleep Extreme Deep Sleep CPU Peripherals Flash Core System Memory Radio DSWDT RTCC FlexRAM

(SRAM) On On On On On On On On Clock Gated Idle Idle Idle Idle On On Idle Clock Gated Clock Gated On Demand Clock Gated On Demand Clock Gated On Demand Retention Mode On Demand Clock Gated On On On On Off Off Off Off Off On On On Demand Retention Mode Retention Mode

(On Demand) Off Off Off Off Off Off Off Off 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 274 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) SleepWalking/

Dream(1) On On Demand On On Demand On On Standby Sleep Deep Sleep Extreme Deep Sleep On Off On Off Off Off On Off On Off Off Off Off Off

...........continued Functions Device Power Modes Run Idle On On On On On On On On On On XTAL(16 MHz) FRC LPRC SPLL SOSC Note:

1. Dream (Sleep Walking) is not a mode by itself but is a companion mode to the Standby Sleep mode. This mode cannot be entered directly through a software command. All transitions from the Run state to any of the low power states is simply initiated by WFI command from the CPU. However, prior to initiating the WFI command. 14.3.1.1 Operation All power saving modes are controlled by sub-systems: XDS/DS Controller, CRU, PMU Controller, and Wireless Subsystem. To enter into the different low power modes, the software performs the following actions:

Disabling all interrupts Setting up the DSCON.DSEN, OSCCON.SLPEN, OSCCON.DRMEN and Wireless Subsystem Sleep mode control bits Set the Wireless Subsystem into the Low Power mode Enable the appropriate wake-up events Checking for any pending interrupts and, if present, abort deep sleep and service the interrupt If no pending interrupts, then issue a SLEEP/WFI command from the CPU to get into the appropriate Low Power mode The low power modes entry and exit commands and wake-up resources are shown in the following table. Table 14-2. Low Power Saving Modes Entry and Exit commands and Wake-up Resources Device Power Modes Entry Commands Run Idle WFI Instruction + ~OSCCON.SLPEN Dream OSCCON.DREAM + Event + Standby Sleep mode Standby Sleep

~DSCON.DSEN+OSCCON.SLPEN +Wireless Sleep followed by WFI Wake-up Resources IRQ2, Reset, Others(1) IRQ, Reset, Others IRQ, Reset, Others Deep Sleep DSCON.DSEN + {RTCC (Enabled) or DSWDT (Enabled)} +

Wireless Sleep followed by WFI INT0, RTCC, DSWDT, Reset Extreme Deep Sleep DSCON.DSEN + {RTCC (Disabled) and DSWDT (Disabled) and INT0 (Enabled)} + Wireless Sleep followed by WFI INT0, Reset Note:

1. Others = System Wake-up (Dream), WDT (Timeout Event), DMT (Timeout Event), PLVD Event, PMU Event, External NMI/INT, DSU/ICD Debug Event, CPU Debug Event. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 275 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.3.1.2 Run Mode In the Run mode, the CPU is actively executing code. This mode provides normal operation of the processor and all peripherals that are currently enabled. On power-up, the device automatically gets into the Run mode. There are no special instructions required to get into the Run mode 14.3.1.3 Idle Mode In the Idle mode, all active peripherals can be clocked but the CPU core is clock gated off and no code is executed. This mode can be useful for applications that only require the processor to run when an interrupt occurs. The device enters the Idle mode, when the OSCCON.SLPEN bit is low and the CPU executes a WFI instruction. Note:When exiting from Standby Sleep mode, the CRU transitions the system to the Idle mode before transitioning to the RUN mode. This transition to the Idle mode is used to support the Dream mode and always occurs regardless of the CRU transitioning to the Dream mode or the Run mode. Therefore, when exiting the Standby Sleep mode, both the RCON.SLEEP and RCON.IDLE bits will be set. 14.3.1.4 Dream Mode In the Dream mode (or Sleep Walking mode), the CPU is clock gated but peripherals can be turned on on-demand by events related to those peripherals. No code is executed. When the DRMEN bit in the OSCCON register is set, it allows the DMA controller to switch between the Idle mode and the Standby Sleep mode. When the OSCCON.SLPEN bit is set and the OSCCON.DRMEN bit is set, the CRU monitors the DMAC to make sure all transfers are complete before going into the Standby Sleep mode. If OSCCON.SLPEN = 1, OSCCON.DRMEN = 1, and peripheral clock requests are active, the CRU goes into the Idle mode until all peripheral clock requests are non-active; at which time the CRU goes into the Standby Sleep mode. If OSCCON.SLPEN is not set, the DRMEN bit has no affect as the DMA clocks are still running in the Idle mode. If the CRU recognizes a wake/interrupt event whose priority will wake the DMA but not the CPU, the CRU transitions to the Idle mode. Therefore, the DMA can perform the needed operations and, when the DMA is finished, the CRU will go back to the Standby Sleep mode. During this time, the CPU is still asleep. If the wake event is such that the CPU must handle the event, the whole system will exit the Standby Sleep mode and transition back to the Run mode. 14.3.1.5 Standby Sleep Mode In the Standby Sleep mode, the FlexRAM (SRAM) is in the Retention mode while the CPU and most peripherals are clock gated off and no code is executed. Standby Sleep Entry The Standby Sleep mode is entered when DSCON.DSEN is clear and the OSCCON.SLPEN bit is set and the CPU executes a WFI instruction. This causes the device clocks to be held low (0). Entry into the Standby Sleep mode from any other mode does not require a clock switch. This is due to the fact that once the device is in the Standby Sleep mode, no clocks are required. Note:If software writes to the CRU SFR before going into the Standby Sleep mode, it is recommended to perform read on the SFR to flush the write, before executing the WFI instruction that initiates the Standby Sleep mode. Standby Sleep Exit Unless the Two-Speed Start-up is enabled, there are no clock switching events when exiting the Sleep mode. With Two-Speed Start-up disabled, the Standby Sleep mode is effectively extended until the selected clock is ready. Once the clock is ready, the device enters the RUN mode. If Two-Speed Start-up is enabled, the device comes out of Standby Sleep and starts running with the FRC as the clock source and performs an automatic clock switch to the selected clock source. Two-speed start-up is not permanently enabled and is software programmable through CFGCON2.WAKE2SPD bit and OSCCON.2SPDSLP bit. 14.3.1.6 Deep Sleep Mode In the Deep Sleep mode, the FlexRAM (SRAM) is in the Retention mode (on demand) while the CPU and peripherals

(see Table 14-2 for available peripherals as wake-up source) are OFF and no code is executed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 276 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) Deep Sleep Mode Entry The Deep Sleep mode is entered by performing the following steps:

Set Wireless Subsystem into the Low power mode. Set the DSEN bit in the DSCON register. Enable the Deep Sleep wake-up source (See Table 14-2). 1. Disable all interrupts. 2. 3. 4. 5. Check for any pending interrupts and if present, abort deep sleep and service the interrupt. If there are no pending interrupts then, issue a SLEEP/WFI command from the CPU. 6. To minimize the chance that Deep Sleep will be spuriously entered, the SLEEP/WFI command must be issued as the next instruction following the setting of the DSCON.DSEN bit. This sequence can still be interrupted by interrupts and other system latencies, but will not prevent the Deep Sleep mode being entered once the SLEEP/WFI command is executed. The DSEN bit is then automatically cleared when exiting the Deep Sleep mode. Note:The DSWSRC register clears automatically when the DSEN bit is set, regardless of whether the Deep Sleep mode is actually entered or not. Therefore, software must read this entire register after exiting the Deep Sleep mode and before re-enabling the Deep Sleep mode. Deep Sleep Mode Exit The Deep Sleep mode will be exited on any of the following events:

1. Device exits Deep Sleep due to a wake-up event (place all the already available points 1 to 5 as sub-pulltin under this). The DSEN bit is automatically cleared. 2. 3. Read the Deep Sleep Status bit and clear it. 4. Read the DSSEMA1 registers (optional). 5. Once all state related configuration is complete, clear the DSSR bit in the DSCON register. 6. Device releases all held logic and/or I/Os. Until this occurs, the control and data bits for the I/Os will have no effect on the actual I/O state. Software resumes normal operation. POR event (De-assertion) on the VDD supply. 7. 8. 9. DSWDT time-out (if DSWDT is enabled). When the DSWDT timer times out, the Deep Sleep mode will be exited. 10. RTCC alarm (if RTCC is enabled). 11. Assertion (0) of the (NMCLR) pin. 12. Assertion of the INT0 pin (if the interrupt was enabled before the Deep Sleep mode was entered). The polarity configuration (Refer CFGCON0.INT0P) is used to determine the assertion level (0 or 1) of the pin that will cause an exit from the Deep Sleep mode. Note:Any interrupts pending when entering the Deep Sleep mode are cleared, and that exiting from the Deep Sleep mode requires a change on the INT0 pin while in the Deep Sleep mode. 14.3.1.6.1 Enabling Retention RAM in the Deep Sleep Mode There is no separate backup SRAM available for the PIC32CX-BZ3 family of devices. Any context saving needs to be done in the data FlexRAM (SRAM). Depending on the size requirement of the data to be retained while in the Deep Sleep mode, the right size FlexRAM (SRAM) may be selected in WCMCFG, and WCMSIZ registers. See WCMCFG and WCMSIZ from Related Links. Related Links 14.5.1. WCMCFG 14.5.2. WCMSIZ 14.3.1.6.2 Software Restore Even though exiting from the Deep Sleep mode looks like a Power-on Reset to the device, it is possible to save the connected state of the device in FlexRAM (SRAM) memory. A mechanism, called software restore, allows software to indicate when the re-configuration of the device has finished, and it is safe to release the state of this logic and/or I/Os. This is done by clearing the DSCON.DSSR bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 277 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.3.1.6.3 Zero-Power BOR (ZPBOR) The ZPBOR is a low power BOR used during the Deep Sleep operation. The ZPBOR is enabled only when the CFGCON4.DSZPBOREN configuration bit is set as 1. See CFGCON4(L) from Related Links. Related Links 18.9.4. CFGCON4(L) 14.3.1.6.4 Deep Sleep Watchdog Timer (DSWDT) The Deep Sleep Watchdog Timer is a configurable timer with a time-out range of 1 ms to over 24 days. The DSWDT is configured using the CFGCON4.DSWDTEN, CFGCON4.DSWDTPS[3:0] and CFGCON4.DSWDTLPRC. See CFGCON4(L) from Related Links. The DSWDT is a separate timer from the devices WDT that is used in the Run mode. The devices WDT does not have to be enabled for the DSWDT to function. Entry into the Deep Sleep mode automatically resets the DSWDT. Related Links 18.9.4. CFGCON4(L) 14.3.1.7 Extreme Deep Sleep (XDS) Mode In the Extreme Deep Sleep mode, INT0 which is external interrupt pin alone is active and can wake-up the device. Exiting XDS is equivalent to Power-on Reset. RCON register provides status whether its a normal power up or exiting from XDS. Extreme Deep Sleep Mode Entry 1. Disable all the interrupts, except INT0 (as desired). 2. Disable RTCC, DSWDT and WCM Retention. 3. Set the DSEN bit in the DSCON register. 4. Check for the pending interrupts, and, if present, abort the Extreme Deep Sleep mode and service the 5. interrupt. If there are no pending interrupts, issue a WFI command from the CPU. To minimize the chance of entering the Extreme Deep Sleep mode spuriously, it is recommended that the WFI command be issued as the next instruction following the setting of the DSCON.DSEN bit. This sequence can still be interrupted by interrupts and other system latencies, but it will not prevent the system entering the Extreme Deep Sleep mode once the WFI command is executed. The DSEN bit is then automatically cleared when exiting the Extreme Deep Sleep mode. Extreme Deep Sleep Mode Exit The Extreme Deep Sleep mode will be exited on any of the following events:

1. 2. POR event on the VDD supply. Assertion of the (NMCLR) pin or INT0 pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 278 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.4 Register Summary See PMU module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00

... 0x53 Reserved 0x54 WCMCFG 0x58

... 0x5F Reserved 0x60 WCMSIZ 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Related Links 7. Product Memory Mapping Overview 14.5 Register Description SRAM2_CFG[2:0]

SRAM1_CFG[2:0]

SRAM1_SIZE[1:0]

Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 279 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.5.1 WCMCFG Register Name:

Offset:

Reset:

Property:

WCMCFG 0x54 0x00001100

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit 7 Access Reset 14 R/W 0 6 13 SRAM2_CFG[2:0]

R/W 0 5 12 R/W 1 4 11 3 10 R/W 0 2 9 SRAM1_CFG[2:0]

R/W 0 1 8 R/W 1 0 Bits 14:12 SRAM2_CFG[2:0]CMCC Memory Configuration in the Standby Sleep mode Notes:

This field is only writable when CFGCON0.PMULOCK = 0. These bits are only applicable for controlling state of memory in the Standby Sleep Mode. 1. 2. 3. Memories cannot be completely turned off dynamically in the PIC32CX-BZ3 (unless in DS and CLDO is OFF). Therefore, option 000 is unavailable. The power consumption of these modes are : ON > NAP > RET > RET+NAP. Description CMCCRAM in the ON mode CMCCRAM in the NAP mode CMCCRAM in the RET mode CMCCRAM in the RET + NAP mode CMCCRAM is powered OFF (Option is unavailable) 4. Value 1xx 011 010 001 000 Bits 10:8 SRAM1_CFG[2:0]FLEXRAM (SRAM) Configuration in the Standby Sleep mode Notes:

This field is only writable when CFGCON0.PMULOCK = 0. These bits are only applicable for controlling state of memory in the Standby Sleep Mode. 1. 2. 3. Memories cannot be completely turned off dynamically in the PIC32CX-BZ3 (unless in DS and CLDO is OFF). Therefore, option 000 is unavailable. The power consumption of these modes are : ON > NAP > RET > RET+NAP. Description FLEXRAM in the ON mode FLEXRAM in the NAP mode FLEXRAM in the RET mode FLEXRAM in the RET + NAP mode FLEXRAM is powered OFF (Option is unavailable) 4. Value 1xx 011 010 001 000 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 280 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.5.2 WCMSIZ Register Name:

Offset:

Reset:

Property:

WCMSIZ 0x60 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bits 9:8 SRAM1_SIZE[1:0]Flex RAM Retention Size Configuration in the Deep Sleep mode Note:This field is only writable when CFGCON0.PMULOCK = 0. Value 11 10 01 00 Description Not available 32K Flex RAM is available in retention 16K Flex RAM is available in retention Flex RAM is completely powered OFF in Deep Sleep mode 8 9 SRAM1_SIZE[1:0]

R/W 0 1 R/W 0 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 281 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.6 Register Summary See DSCON module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 DSCON 0x04 DSWSRC 0x08 DSSEMA1 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 DSEN XSEMAEN RTCPWREQ ZPBOR DSSR RTCCWDIS DSWDT RTCC MCLR INT0 DSSEMA1[7:0]

DSSEMA1[15:8]

DSSEMA1[23:16]

DSSEMA1[31:24]

Related Links 7. Product Memory Mapping Overview 14.7 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 282 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.7.1 DS Control Name:

Offset:

Reset:

DSCON 0x00 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset 15 DSEN R/W/HC 0 14 13 XSEMAEN R/W 0 12 RTCPWREQ R/W 0 Bit 7 6 5 4 3 2 Access Reset Bit 15 DSENDeep Sleep Enable bit Value 0 1 Description Enters the Standby Sleep mode on a WFI command Enters the Deep Sleep mode on a WFI command Bit 13 XSEMAENXSEMA General Purpose Registers Enable bit Value 0 1 Description No general purpose register retention in the Deep Sleep mode Enables the general purpose register retention in the Deep Sleep mode 11 10 9 8 RTCCWDIS R/W 0 0 DSSR R/C/HS/HC 0 1 ZPBOR R/W/C/HS 0 Bit 12 RTCPWREQRTCC Module Disable bit To enable RTCC function, RTCC module level registers must be programmed in addition to DSCON.RTCPWREQ bit. Value 0 1 Description Enables the RTCC module Disables the RTCC module Bit 8 RTCCWDISRTCC Wake-up Disable bit Value 0 1 Description Enables the wake-up from RTCC Disables the wake-up from RTCC Bit 1 ZPBORDeep Sleep BOR Event Status bit Value 0 1 Description CFGCON4.DSZPBOREN is disabled, or VDD did not drop below the DSBOR threshold during the Deep Sleep mode CFGCON4.DSZPBOREN is enabled and VDD dropped below the DSBOR threshold during the Deep Sleep mode Note:Unlike all other events, a DSBOR event does not cause a wake-up from the Deep Sleep mode. This bit is present only as a status bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 283 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) Bit 0 DSSRI/O pin State Release bit Value 0 1 Description Release I/O pins and allow their respective TRIS and LAT bits to control their states Upon waking from Deep Sleep, the I/O pins maintain their previous states (Not user settable). Note:The DSSR register bit is readable and clearable (but not settable) by the software. This bit is automatically set when entering the Deep Sleep mode. While exiting the Deep Sleep mode, due to any wake-up source other than NMCLR, once all state related configuration is complete the software must clear the DSSR bit. Once the DSSR bit is cleared, the I/Os will be controlled by their I/O registers. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 284 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.7.2 DSWSRC Name:

Offset:

Reset:

DSWSRC 0x04 0x00000000 The DSWSRC register is only writable by software when DSCON.DSSR = 0. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 9 1 8 INT0 R/W/C/HS 0 0 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 Access Reset 4 DSWDT R/W/C/HS 0 3 RTCC R/W/C/HS 0 2 MCLR R/W/C/HS 0 Bit 8 INT0Deep Sleep Interrupt-on-change #0 bit Value 0 1 Description Interrupt-on-change #0 (INT0) is not asserted during the Deep Sleep Interrupt-on-change #0 (INT0) is asserted during the Deep Sleep Bit 4 DSWDTDeep Sleep Watchdog Timer Time-out bit Description DSWDT does not time out during the Deep Sleep DSWDT timed out during the Deep Sleep Value 0 1 Bit 3 RTCCDeep Sleep Real Time Clock and Calendar Alarm bit Value 0 1 Description Deep Sleep RTC and calendar does not trigger an alarm during the Deep Sleep Deep Sleep RTC and calendar triggers an alarm during the Deep Sleep Bit 2 MCLRDeep Sleep MCLR Event bit Value 0 1 Description

(NMCLR) pin is not active or is active, but not asserted during the Deep Sleep

(NMCLR) pin is active and is asserted during the Deep Sleep 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 285 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Power Management Unit (PMU) 14.7.3 DSSEMA1 Register Name:

Offset:

Reset:

Property:

DSSEMA1 0x08 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DSSEMA1[31:24]

R/W 0 R/W 0 20 19 DSSEMA1[23:16]

R/W 0 12 R/W 0 11 DSSEMA1[15:8]

R/W 0 4 R/W 0 3 DSSEMA1[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DSSEMA1[31:0]Deep Sleep Persistent General Purpose Register bits The contents of the DSSEMA1 register are retained, even in the Deep Sleep mode. The DSSEMA1 is disabled by default in the Deep Sleep mode but can be enabled with the XSEMAEN bit (DSCON[13]). All register bits are Reset only in the case of a VDD Power-on Reset (POR) event outside of the Deep Sleep mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 286 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) 15. Watchdog Timer (WDT) 15.1 Introduction The Watchdog Timer (WDT) can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. The user can configure the WDT in Windowed mode or non-Windowed mode. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Standby Sleep or Idle mode. 15.2 Features Configuration using Fuses (DEVCFG) or Software controlled Up to 32 Configurable Time-Out Periods Can wake the Device from Standby Sleep or Idle mode Independent Run and Standby Sleep mode Counters WDT may use alternate Clock source and Postscaler for Run mode Counter Independent 5-bit Postscalers for Run and Standby Sleep mode Counters Hardware and Software enabled Two Clock sources Windowed WDT Note:When the CPU is running on the same clock or clock frequency as the WDT, the lowest pre-scale values may not allow the CPU to have enough time to reset the WDT before it expires. 15.3 Block Diagram Figure 15-1. Block Diagram SYS_CLK 26 26 SLPDIV<4:0> (WDTCON<5:1>) WDTRMCS<1:0>(CFGCON2<11:10>) 15.4 Watchdog Timer Operation The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction or wake-up the processor in the event of a time-out while in Standby Sleep mode. If enabled, the WDT will increment until it overflows or times out. A WDT time-out will force a device Reset, except during Standby Sleep or Idle modes. To prevent a WDT time-out Reset, the user application must periodically clear the WDT by writing a key word 0x5743 to the WDTCLRKEY[15:0] bits (WDTCON[31:16]) through a single 16-bit write. Related Links 15.9.1. WDTCON 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 287 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) 15.4.1 Modes of Operation The WDT has two modes of operation: Non-Windowed and Programmable Windowed. The Programmable Windowed mode can be enabled by setting the Watchdog Window Enable (WDTWINEN) bit

(WDTCON[0]). In Programmable Windowed mode, software can clear the WDT only when the counter is in its final window before a period match occurs. There are four window size options. This window is active when the timer counter is greater than a predetermined value for each option. Any attempts to clear the WDT when the window is not active will cause a device Reset. In Non-Windowed mode, software can clear the WDT anytime before the period match occurs. 15.4.2 Enabling and Disabling the WDT The WDT is enabled or disabled by the device configuration or controlled through software by writing to the WDTCON register. See WDTCON from Related Links for more details. Related Links 15.9.1. WDTCON 15.4.3 Device Configuration Controlled WDT If the DEVCFG2.WDTEN Configuration bit is set, the WDT is always enabled. The ON control bit (WDTCON[15]) will reflect this by reading a 1. In this mode, the ON bit cannot be cleared in software. The DEVCFG2.WDTEN Configuration bit will not be cleared by any form of reset. To disable the WDT, the configuration must be rewritten to the device. Note:The WDT is enabled by default on an unprogrammed device. The DEVCFG2.WINDIS Configuration bit can be used to enable or disable the Programmable Windowed mode. The window size for the WDT Programmable Windowed mode can be configured using the DEVCFG2.WINSZ Configuration bits. 15.4.4 Software Controlled WDT If the DEVCFG2.WDTEN Configuration bit is a 0, the WDT module can be enabled or disabled (the default condition) by software. In this mode, the ON bit (WDTCON[15]) reflects the status of the WDT under software control. A 1 indicates the WDT module is enabled and a 0 indicates it is disabled. If the DEVCFG2.WINDIS Configuration bit is a 0, the WDT Programmable Windowed mode can be enabled or disabled by software. The Programmable Windowed mode can be configured using the WDTWINEN bit (WDTCON[0]). A 1 indicates that Programmable Windowed mode is enabled and 0 indicates it is disabled. The window sizes can be configured by setting the DEVCFG2.WINSZ configuration bits only, and cannot be set in software. The WDT is enabled in software by setting the Watchdog Timer control bit, ON (WDTCON[15]). The ON control bit is cleared on any device Reset. The bit is not cleared upon a wake from Standby Sleep or exit from Idle mode. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during noncritical segments for maximum power savings. This bit can also be used to disable the WDT while the device is awake to eliminate the need for WDT servicing, and then re-enable it before the device is put into Idle mode or Standby Sleep mode to wake the device at a later time. 15.4.4.1 Watchdog Timer Programmable Window The window size is determined by the Configuration bits, DEVCFG2.WINSZ and WDTPS. In the Programmable Windowed mode (WDTCON.WDTWINEN = 1), the WDT must be cleared based on the setting of the Window Size Configuration bits (DEVCFG2.WINSZ[1:0]), see the following figure. These bit settings are:

11 = WDT window is 25% of the WDT period 10 = WDT window is 37.5% of the WDT period 01 = WDT window is 50% of the WDT period 00 = WDT window is 75% of the WDT period If the WDT is cleared before the allowed window, a system Reset is immediately generated. See Clock and Reset Unit (CRU) from Related Links for more information on which type of reset occurs. The Windowed mode is useful for resetting the device during unexpected quick or slow execution of a critical portion of the code. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 288 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) Figure 15-2. Programmable Windowed WDT Watchdog Time-out Period

(TWTO) Disallowed Window Allowed Window

([25, 37.5, 50, or 75%] x TWTO) Figure 15-3. Non-Windowed WDT Watchdog Time-out Period

(TWTO) Allowed Window Related Links 13. Clock and Reset Unit (CRU) 15.4.5 WDT Operation in Power-Saving Modes The WDT, if enabled, will continue operation in Standby Sleep mode or Idle mode. The WDT module may be used to wake the device from Standby Sleep mode or Idle mode. When the WDT times out in a Standby Sleep mode or Idle mode, a Non-Maskable Interrupt (NMI) is generated and the WDTO bit (RCON[4]) is set. The NMI vectors execution to the CPU start-up address, but does not reset registers or peripherals. If the device is in Standby Sleep, the SLEEP status bit (RCON[3]) will also be set. If the device is in Idle, the IDLE status bit (RCON[2]) will also be set. These bits allow the start-up code to determine the cause of the wake-up. 15.4.6 WDT NMI Reset Delay It is possible to program a delay time between a WDT event and a device Reset using NMI reset counter. See Resets from Related Links for more details. Related Links 13.4. Resets 15.4.7 Resetting the WDT The following events will reset both internal WDT counters:

Disabling the WDT via the ON bit on any device Reset Any counter value greater than the selected WDT period The following event will reset the Run Mode Counter:

Detection of a correct write value (0x5743) to the WDTCLRKEY[15:0] bits(WDTCON[31:16]) The following event will reset the Standby Sleep Mode Counter:

Exiting from Idle or Standby Sleep due to WDT event Note:The WDT is not reset when the device enters a Power-Saving mode. The WDT module must be serviced prior to entering a Power-Saving mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 289 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) 15.4.8 WDT Period Selection The Sleep Mode Counter always uses the 32 kHz LPRC clock source. The Run Mode Counter will use the clock source selected by the DEVCFG2.WDTRMCS[1:0] Configuration Bits in fuses to be either the 32 kHz LPRC clock or the SYS_CLK. Note:The WDT module time-out period is directly related to the frequency of the LPRC Oscillator when clock source is 32 kHz LPRC. The frequency of the LPRC Oscillator will vary as a function of device operating voltage and temperature. See Electrical Characteristics from Related Links for LPRC clock frequency specifications. Related Links 38. Electrical Characteristics 15.4.9 WDT Postscalers The WDT has a 5-bit postscaler to create a wide variety of time-out periods. This postscaler provides 1:1 through 1:1048576 divider ratios, see the following table. Time-out periods that range between 1 ms and 1048.576 seconds

(nominal) can be achieved using the postscaler. Table 15-1. WDT Time-out Period versus Postscaler Settings(1),(2) WDTPSR[4:0]/WDTPSS[4:0] Postscaler Ratio Time-out Period (Non-

windowed Mode) Time-out Period (Programmable Windowed mode)(3) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 Notes:

1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 1:512 1:1024 1:2048 1:4096 1:8192 1:16384 1:32768 1:65536 1:131072 1:262144 1:524288 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1.024s 2.048s 4.096s 8.192s 16.384s 32.768s 65.536s 131.072s 262.144s 524.288s 1:1045876 1048.576s 0.75 ms 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 0.768s 1.536s 3.072s 6.144s 12.228s 24.576s 49.152s 98.304s 196.608s 393.216s 786.432s 1. 2. 3. All other combinations will result in operation as if the postscaler was set to 10100. The periods listed are based on a 32 kHz (nominal) input clock. In this case, DEVCFG2.WINSZ = 00. The WDT window is 75% of the selected WDT period. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 290 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) The settings are chosen using the DEVCFG2.WDTPSR[4:0] inputs for the Run Mode Counter and the DEVCFG1.WDTPSS[4:0] inputs for the Standby Sleep Mode Counter. The time-out period of the WDT is calculated, as shown in the following equation. WDTPeriod = 1 ms 2 Postscaler 15.5 Interrupt and Reset Generation The NMI timer provides a delay between WDT events and a device Reset. Set the delay in System Clock counts from 0 to 255 in the NMICNT[15:0] bits (RNMICON[15:0]). If these bits are set to zero, there will be no delay between the WDTO flag and a device Reset. If set to a non-zero value, the NMI interrupt has that number of system clocks to clear flags or save data for debugging purposes. If the corresponding NMI flag(RNMICON.WDTR) is not cleared in RNMICON before the counter reaches zero, then a device Reset will be issued. If the corresponding NMI flag in RNMICON is cleared before the counter reaches zero, then the counter is stopped, then reloaded with the NMICNT value again and waits for another NMI event to occur. A device reset will not be asserted in this case and software will be able to return from this NMI interrupt. The WDTS flag will be set if there is a WDT event during Standby Sleep/Idle mode. The WDTS flag will wake the CPU from Standby Sleep/Idle mode, but will not start the NMI counter, nor cause a Reset. To detect a WDT Reset, the WDTO bit (RCON[4]), SLEEP bit (RCON[3]) and IDLE bit(RCON[2]) must be tested. If the WDTO bit is a 1, the event was due to a WDT time-out. The SLEEP and IDLE bits can then be tested to determine if the WDT event occurred while the device was awake or if it was in Standby Sleep or Idle mode. 15.6 Operation in Debug and Power-Saving Modes 15.6.1 WDT Operation in Power-Saving Modes The WDT can be used to wake the device from Standby Sleep or Idle modes. The WDT continues to operate in power-saving modes. A time-out can then be used to wake the device. This allows the device to remain in Standby Sleep mode until the WDT expires or another interrupt wakes the device. If the device does not re-enter Standby Sleep or Idle mode following a wake-up, the WDT must be disabled or periodically serviced to prevent a device Reset. 15.6.2 WDT Operation in Standby Sleep Mode The WDT, if enabled, will continue operation in Standby Sleep mode. The WDT may be used to wake the device from Sleep mode. When the WDT times out in Sleep, a NMI is generated and the WDTO bit (RCON[4]) is set. The NMI vectors execution to the CPU start-up address, but does not reset registers or peripherals. The Standby Sleep status bit (RCON[3]) will be set indicating the device was in Standby Sleep mode. These bits allow the start-up code to determine the cause of the wake-up. 15.6.3 WDT Operation in Idle Mode The WDT, if enabled, will continue operation in Idle mode. The WDT may be used to wake the device from Idle mode. When the WDT times out in Idle, a NMI is generated and the WDTO bit (RCON[4]) is set. The NMI vectors execution to the CPU start-up address, but does not reset registers or peripherals. The IDLE status bit (RCON[2]) will be set indicating the device was in Idle mode. These bits allow the start-up code to determine the cause of the wake-up. 15.6.4 Time Delays During Wake-up The delay between a WDT time-out and the beginning of code execution depends on the Power-Saving mode. There will be a time delay between the WDT event in Standby Sleep mode and the beginning of code execution. The duration of this delay consists of the start-up time for the oscillator in use and the PWRT delay, if it is enabled. Unlike a wake-up from Standby Sleep mode, there are no time delays associated with wake-up from Idle mode. The system clock is running during Idle mode; therefore, no start-up delays are required at wake-up. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 291 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) 15.6.5 WDT Operation in Debug Mode The WDT is always suspended in Debug mode, and therefore does not time-out. 15.7 Effects of Various Resets Any form of device Reset will clear the WDT. The reset will return the WDTCON register to the default value and the WDT will be disabled unless it is enabled by the device configuration. Note:After a device Reset, the WDT ON bit (WDTCON[15]) will reflect the state of the DEVCFG2.WDTEN. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 292 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) 15.8 Register Summary See WDT module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 WDTCON 7:0 15:8 23:16 31:24 ON SLPDIV[4:0]

WDTWINEN RUNDIV[4:0]

WDTCLRKEY[7:0]

WDTCLRKEY[15:8]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 15.9 Register Description Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Following conventions are used in the register description:

-n = Value at POR R = Readable bit W = Writable bit

= Unimplemented bit, read as 0 1 = Bit is set 0 = Bit is cleared Reset values are shown in hexadecimal. x = Bit is unknown y = Values set from Configuration bits on POR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 293 Microchip Confidential Confidential 15.9.1 WDTCON - Watchdog Timer Control Register PIC32CX-BZ3 and WBZ35x Family Watchdog Timer (WDT) Name:

Offset:

Reset:

Property:

WDTCON 0x00 0x00

Bit Access Reset Bit Access Reset Bit Access Reset 31 W 0 23 W 0 15 ON R/W y 30 W 0 22 W 0 14 Bit 7 6 Access Reset 29 W 0 21 W 0 13 5 R y 28 27 WDTCLRKEY[15:8]

W W 0 0 20 19 WDTCLRKEY[7:0]

W W 0 0 26 W 0 18 W 0 12 R y 4 R y 11 R y 10 RUNDIV[4:0]

R y 3 SLPDIV[4:0]

R y 2 R y 25 W 0 17 W 0 9 R y 1 R y 24 W 0 16 W 0 8 R y 0 WDTWINEN R/W 0 Bits 31:16 WDTCLRKEY[15:0]Watchdog Timer Clear Key bits To clear the WDT to prevent a time-out, software must write the value 0x5743 to this location using a single 16-bit write. Anything other than a 16-bit write will not reset the WDT. You must use a 16-bit write for the WDTCLRKEY[15:0] bits. Bit 15 ONWatchdog Timer Enable bit Note:

1. This bit only has control when the WDTEN bit (DEVCFG2/CFGCON2[23]) = 0. Value 1 0 Description WDT is enabled WDT is disabled Bits 12:8 RUNDIV[4:0]Watchdog Timer Postscaler Run Counter Value bits On Reset, these bits are set to the values of the WDTPSR[4:0] Configuration bits in CFGCON2. Bits 5:1 SLPDIV[4:0]Watchdog Timer Postscaler Sleep Counter Value bits On Reset, these bits are set to the values of the WDTPSS[4:0] Configuration bits in CFGCON1. Bit 0 WDTWINENWatchdog Timer Window Enable bit Value 1 0 Description Enable windowed WDT Disable windowed WDT 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 294 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16. Deadman Timer (DMT) 16.1 Overview The Deadman Timer (DMT) module is designed to enable users to be able to monitor the health of their application software by requiring periodic timer interrupts within a user-specified timing window. The DMT module is a synchronous counter and when enabled, counts instruction fetches and causes a system reset if the DMT counter is not cleared within a set number of instructions. The DMT is typically connected to the system clock that drives the processor. The user specifies the timer time-out value and a mask value that specifies the range of the window, which is the range of counts that is not considered for the comparison event. 16.2 Features 32-bit configurable count-limit based on counting instructions fetched Hardware- or software-enabled control User-configurable time-out period or instruction count Two instruction sequence to clear timer 32-bit configurable window to clear timer 16.3 Block Diagram The following figure shows the block diagram of the Deadman Timer. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 295 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) Figure 16-1. Deadman Timer Block Diagram improper sequence flag ON Instruction Fetched Strobe System Reset Force DMT Event Counter Initialization Value PB1_CLK Clock 32-bit counter ON Proper Clear Sequence Flag ON System Reset 32 DMT Count Reset Load DMT event to NMI(3)

(COUNTER) = DMT Max Count(1)

(COUNTER) DMT Window Interval(2) Window Interval Open Notes:

1. 2. 3. The DMT Max Count is controlled by the DMTCNT[4:0] bits in the CFGCON2 register Maximum = 2^31. The DMT Window Interval is controlled by the DMTINTV[2:0] bits in the CFGCON2 register. For more details, see Resets from Related Links. Related Links 13.4. Resets 16.4 DMT Operation 16.4.1 Mode of Operation The primary function of the Deadman Timer (DMT) module is to reset the processor in the event of a software malfunction. The DMT module, which works on the system clock, is a free running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. The instructions are not fetched when the processor is in the Standby Sleep mode. The DMT module consists of a 32-bit counter, the read-only DMTCNT register with a time-out count match value as specified by the 32-bit DMT count configuration fuse bits CFGCON2.DMTCNT[4:0]. Whenever the count match occurs, a DMT reset event will occur and the DMTEVENT bit in DMTSTAT register will be set. A DMT module is typically used in mission critical and safety critical applications, where any failure of the software functionality and sequencing must be detected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 296 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.4.2 Enabling and Disabling the DMT Module Because of the nature of the Deadman Timer, the PMD register bit is not provided to enable/disable the module. The DMT module can be enabled or disabled by the DMT enable (DMTEN) bit in the Configuration Control Register 2

(CFGCON2) fuse register or it can be enabled through software by writing to the Deadman Timer Control (DMTCON) register. Once the DMT is enabled, it may not be disabled without a device reset. If the DMTEN configuration bit in the CFGCON2 fuse register is set, the DMT is always enabled. The ON control bit

(DMTCON[15]) in DMTCON register will reflect this by reading a 1. In this mode, the ON bit (DMTCON[15]) cannot be cleared in software. To disable the DMT, the DMTEN configuration bit must be cleared in the CFGCON2 fuse register. When DMTEN is cleared to 0 in the CFGCON2, the DMT is disabled in hardware. Software can enable the DMT by setting the ON bit in the DMTCON register. However, for software control, the DMTEN configuration bit in the CFGCON2 fuse register must be set to 0. 16.4.3 DMT Count Windowed Interval The DMT module has the Windowed Operation mode. The DMT interval (DMTINV[2:0]) bits in the Configuration Control Register 2 (CFGCON2) fuse register sets the window interval value. The PSINTV[31:0] bits in DMT interval post status register (DMTPSINTV) allows the software to read the DMT window interval value. That means this register reads the value that is written to the DMT interval (DMTINV[2:0]) bits in the Configuration Control Register 2

(CFGCON2) fuse register. In the Windowed mode, software can clear the DMT only when the counter is in its final window before a count match occurs. That is, if the DMT counter value is greater than or equal to the value written to the window interval value, only then the DMT clear sequence can be executed in the DMT module. If the DMT is cleared before the allowed window, a DMT reset event is immediately generated. 16.4.4 DMT Count Selection The Deadman Timer count is set by the DMT count configuration (DMTCNT[4:0]) bits in the Configuration Control Register 2 (CFGCON2) fuse register. The current DMT count value can be obtained by reading the DMT count register DMTCNT. The PSCNT[31:0] bits in the DMT count post status register (DMTPSCNT) allows the software to read the maximum count selected for the DMT. The PSCNTx bit values are the values that are initially written to the DMTCNTx bits in the CFGCON2 fuse register. Whenever the DMT event occurs, the user can always compare to see whether the current counter value in the DMTCNT register is equal to the value of the DMTPSCNT register, which holds the maximum count value. Whenever the DMT current counter value in DMTCNT reaches the value of the DMTPSINTV register, the window interval opens permitting the user to execute the DMT clear sequence. The open window interval is indicated by the WINOPN bit in DMTSTAT register. The UPRCNT[15:0] bits in the DMT hold register (DMTHOLDREG) holds the value of the last read DMT upper count values whenever DMTCNT is last read. 16.4.5 DMT Operation in Power-Saving Modes As the DMT module is only incremented by instruction fetches, the count value will not change when the core is inactive. The DMT module remains inactive in the Standby Sleep and Idle modes. As soon as the device wakes-up from Standby Sleep or Idle, the DMT counter starts incrementing again for every instruction fetch. 16.4.6 Resetting the DMT The DMT can be reset in two ways: one way is after a system reset and another way is by writing an ordered sequence to the DMT pre-clear register (DMTPRECLR) and DMT clear register (DMTCLR) in a specific two-step sequence. Clearing the DMT counter value requires the following sequence of operations:

1. 2. The STEP1[7:0] bits in the DMTPRECLR register must be written as 01000000 (0x40). This action sets the enable for clearing state, which enables the DMT to be cleared by step 2. The STEP2[7:0] bits in the DMTCLR register must be written as 00001000 (0x08). This can only be done if preceded by step 1 and if the DMT is in the open window interval. Once these values are written, following are cleared to zero:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 297 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) DMTCNT counter DMTPRECLR register DMTCLR register DMTSTAT register If any value other than 0x40 is written to the STEP1x bits, the BAD1 bit in the DMTSTAT register will be set and it causes a DMT event to occur. Any value other than 0x08, written to the STEP2x bits, will cause the BAD2 bit to be set in the DMTSTAT register. Also, if step 2 is not preceded by step 1, or step 2 is not carried out in the open window interval, it causes the BAD2 flag to be set. Immediately, a DMT event will occur. In both these cases, the DMTEVENT bit in the DMTSTAT register will be set. Refer to the flowchart shown in the following figure. Figure 16-2. Flowchart for Clearing the DMT Start DMT Enable Insert Preclear Sequence Is Sequence Proper?

No BAD1 Flag Set DMT Event Yes Is Counter>=DMT Window Interval?

No Insert Clear Sequence BAD2 Flag Set DMT Event Yes Insert Clear Sequence Is Sequence Proper?

No BAD2 Flag Set DMT Event Yes DMT Reset Occurs Stop 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 298 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.5 Register Summary Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 DMTCON 0x04

... 0x0F Reserved 0x10 DMTPRECLR 0x14

... 0x1F Reserved 0x20 DMTCLR 0x24

... 0x2F Reserved 0x30 DMTSTAT 0x34

... 0x3F Reserved 0x40 DMTCNT 0x44

... 0x4F Reserved 0x50 DMTHOLDREG 0x54

... 0x5F Reserved 0x60 DMTPSCNT 0x64

... 0x6F Reserved 0x70 DMTPSINTV 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ON STEP1[7:0]

STEP2[7:0]

BAD1 BAD2 DMT_EVENT WINOPN COUNTER[7:0]

COUNTER[15:8]

COUNTER[23:16]

COUNTER[31:24]

UPRCNT[7:0]

UPRCNT[15:8]

PSCNT[7:0]

PSCNT[15:8]

PSCNT[23:16]

PSCNT[31:24]

PSINTV[7:0]

PSINTV[15:8]

PSINTV[23:16]

PSINTV[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 299 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Note:All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 300 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.1 Deadman Timer Control Name:

Offset:

Reset:

Property:

DMTCON 0x00 0x00

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset 15 ON HC 0 14 13 12 11 10 Bit 7 6 5 4 3 2 Access Reset Bit 15 ONOn bit The ON bit reflects the status of the configuration fuse CFGCON2.DMTEN, if the fuse is set. Value 1 0 Description Enables the Deadman Timer if the event configuration fuse is not enabled. The DMT disabled. 9 1 8 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 301 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.2 Deadman Timer Preclear Name:

Offset:

Reset:

Property:

DMTPRECLR 0x10 0x00

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset R/W 0 Bit 7 Access Reset 14 R/W 0 6 13 R/W 0 5 STEP1[7:0]

12 R/W 0 4 11 R/W 0 3 10 R/W 0 2 9 R/W 0 1 8 R/W 0 0 Bits 15:8 STEP1[7:0]Pre-Clear Enable bit when write pattern is:

Description Value 01000000 Enables the Deadman Timer Pre-Clear (STEP 1). all other write patterns Sets DMTSTAT.BAD1 flag to 1. Note:Bits 15:8 are cleared when a DMT reset event occurs. STEP1 is also cleared if DMTCLR.STEP2 is loaded with the correct value in the correct sequence. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 302 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.3 Deadman Timer Clear Name:

Offset:

Reset:

Property:

DMTCLR 0x20 0x00

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 STEP2[7:0]

4 R/W 0 3 R/W 0 2 R/W 0 9 1 8 0 R/W 0 R/W 0 Bits 7:0 STEP2[7:0]Clear Timer bit when write pattern is:

Description Value 00001000 Clears DMTPRECLR.STEP1, DMTCLR.STEP2 and the Dead Man Timer if and only if preceded by the correct loading of Pre-Clear Enable (STEP1) in the correct sequence. The write to the DMTCLR.STEP2 field may be verified by reading DMTCNT and observing the counter being reset. The DMTSTAT.BAD2 flag is set to 1, the value in the DMTPRECLR.STEP1 will remain unchanged, and the new value being written DMTCLR.STEP2 will be captured. Note:These bits 7:0 are also cleared when a DMT reset event occurs. all other write patterns 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 303 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.4 Deadman Timer Status Name:

Offset:

Reset:

Property:

DMTSTAT 0x30 0x00

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 BAD1 R 0 6 BAD2 R 0 5 DMT_EVENT R 0 4 3 2 9 1 8 0 WINOPN R 0 Bit 7 BAD1When an incorrect DMTPRECLR.STEP1 value is detected, this bit is set. It is cleared by a Reset. Bit 6 BAD2When an incorrect value of DMTCLR.STEP2 is detected, this bit is set. It is cleared by a Reset. Bit 5 DMT_EVENTThis bit is set when the Deadman timer event is detected (counter expired or bad STEP1[7:0] or STEP2[7:0] value is entered prior to the counter increment). This bit remains set and is cleared only by a Reset. Bit 0 WINOPNDeadman Timer Clear Window bit. A value of 1 indicates that a STEP2 clear action can take place, and if this clearing action occurs as part of a correct sequence of actions, the DMT counter will be cleared. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 304 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.5 Deadman Timer Count Name:

Offset:

Reset:

Property:

DMTCNT 0x40 0x00

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 COUNTER[31:24]

R R 0 0 20 19 COUNTER[23:16]

R R 0 0 11 12 COUNTER[15:8]

R R 0 0 4 3 COUNTER[7:0]

R 0 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 COUNTER[31:0]Read current contents of DMT Counter. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 305 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) 16.6.6 Deadman Timer Count Holding Register Name:

Offset:

Reset:

Property:

DMTHOLDREG 0x50 0x00

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 12 11 UPRCNT[15:8]

R 0 4 R 0 UPRCNT[7:0]

R 0 3 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 UPRCNT[15:0]

It is the content of DMTCNT.COUNTER[31:16] when the counter was last read to ensure a synchronous snapshot of the counter. This register is initialized to 0 on reset and is only loaded when the DMTCNT register is read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 306 Microchip Confidential Confidential 16.6.7 Post Status Configure DMT Count Status Register PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) Name:

Offset:

Reset:

Property:

DMTPSCNT 0x60 0x00

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 PSCNT[31:24]

R 0 20 R 0 19 PSCNT[23:16]

R 0 12 R 0 4 R 0 PSCNT[15:8]

PSCNT[7:0]

R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 PSCNT[31:0]

DMT Instruction Count Value Configuration Fuse Status bits. This bit always reflects the value of CFGCON2.DMTCNT. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 307 Microchip Confidential Confidential 16.6.8 Post Status Configure DMT Interval Status Register PIC32CX-BZ3 and WBZ35x Family Deadman Timer (DMT) Name:

Offset:

Reset:

Property:

DMTPSINTV 0x70 0x00

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 PSINTV[31:24]

R 0 20 R 0 19 PSINTV[23:16]

R 0 12 R 0 4 R 0 PSINTV[15:8]

PSINTV[7:0]

R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 PSINTV[31:0]DMT Window Interval Configuration Status bits. This bit reflects the value of CFGCON2.DMTINTV. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 308 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17. RAM Error Correction Code (RAMECC) 17.1 Overview For safety applications, the PIC32CX-BZ3 family can embed error correction codes (ECC) to detect and correct single bit errors or to enable dual error detection in SRAM. As discussed in Memories chapter, when the RAMECC is enabled, the top half of SRAM memory will be reserved to store error correction codes and will not be available for the application. See SRAM Memory Configuration from Related Links. ECC calculation is software selectable through the CFGCON0.FRECCDIS bit in the Boot Flash Configuration. For additional information, see System Configuration and Register Locking (CFG) from Related Links. Related Links 7.6. SRAM Memory Configuration 18. System Configuration and Register Locking (CFG) 17.2 Features Single bit correction and dual bit detection. Error Interrupt. Operates Idle and Standby Sleep mode. Interrupts generated by RAMECC can be used to wake up the device from Standby Sleep mode. 17.3 Block Diagram Figure 17-1. RAMECC Block Diagram Write data 32 ECC calculation 4x5 HADDR ERRADDR RAM Block 32 4x5 ECCDIS ECC logic 32 HRDATA ECCERR and ECCDUAL status 17.4 Signal Description Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 309 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines Not applicable. 17.5.2 Power Management The RAMECC will continue to operate in any sleep mode (Standby Sleep, Idle) where the selected source clock is running. The RAMECCs interrupts can be used to wake up the device from sleep modes. See Power Management Unit (PMU) from Related Links for details on the different sleep modes. Related Links 14. Power Management Unit (PMU) 17.5.3 DMA Not applicable. 17.5.4 Interrupts The interrupt request line is connected to the interrupt controller. Using the RAMECC interrupt(s) requires the interrupt controller to be configured first. 17.5.5 Events Not applicable. 17.5.6 Debug Operation When the CPU is halted in debug mode the RAMECC will correct and log ECC errors based on the table below. Table 17-1. ECC Debug Operation DBGCTRL.ECCELOG DBGCTRL.ECCDIS Description 0 1 X 0 0 1 ECC errors from debugger reads are corrected but not logged in INTFLAG. ECC errors from debugger reads are corrected and logged in INTFLAG. ECC errors from debugger reads are not corrected or logged in INTFLAG. If the RAMECC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 17.5.7 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers:

Interrupt Flag Status and Clear (INTFLAG) register Status (STATUS) register. Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through an external debugger, see Peripheral Access Controller (PAC) from Related Links. Related Links 20. Peripheral Access Controller (PAC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 310 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.5.8 Analog Connections Not applicable. 17.6 Functional Description 17.6.1 Principle of Operation Error Correcting Code (ECC) is implemented to detect and correct errors that may arise in the RAM arrays. The ECC logic is capable of double error detection and single error correction per 8-bit byte. Upon single bit error detection, the Single Bit Error interrupt flag is raised (INTFLAG.SINGLEE). If a dual error is detected, the Dual Error interrupt flag (INTFLAG.DUALE) is raised. When the first error is detected, the ERRADDR register is frozen with the failing address and remains frozen until INTFLAG.DUALE and INTFLAG.SINGLEE are cleared. If a dual bit error occurs while INTFLAG.SINGLEE is set, the ERRADDR register is updated with the dual bit error information and INTFLAG.DUALE is also set. The INTFLAG.SINGLEE and INTFLAG.DUALE bits are both cleared on ERRADDR read. The block diagram shows the ECC interface. When ECC is disabled (CTRLA.ECCDIS=1), the ECC field in RAM is left unchanged on writes. On reads, ECC errors are not corrected or flagged. Related Links 17.3. Block Diagram 17.6.2 Interrupts The RAMECC has the following interrupt sources:

Dual Bit Error (DUALE): Indicates that a dual bit error has been detected. Single Bit Error (SINGLEE): Indicates that a single bit error has been detected. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear

(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set

(INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the ERRADDR register is read, the interrupt is disabled, or the RAMECC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note:Interrupts must be globally enabled for interrupt requests to be generated. Related Links 17.8.3. INTFLAG 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 311 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.7 Register Summary See RAMECC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 0x01 0x02 0x03 INTENCLR INTENSET INTFLAG STATUS 0x04 ERRADDR 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 0x08

... 0x0E 0x0F Reserved DBGCTRL 7:0 Related Links 7. Product Memory Mapping Overview 17.8 Register Description ERRADDR[7:0]

ERRADDR[15:8]

DUALE DUALE DUALE SINGLEE SINGLEE SINGLEE ECCDIS ERRADDR[17:16]

ECCELOG ECCDIS Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description (see Register Access Protection from Related Links). Related Links 17.5.7. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 312 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.1 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x00 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 Access Reset 1 DUALE R/W 0 0 SINGLEE R/W 0 Bit 1 DUALEDual Bit Error Interrupt Enable Clear Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Dual Bit Error Interrupt Enable bit, which disables the Dual Bit Error interrupt. Value 0 1 Description The Dual Bit Error interrupt is disabled. The Dual Bit Error interrupt is enabled. Bit 0 SINGLEESingle Bit Error Interrupt Enable Clear Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Single Bit Error Interrupt Enable bit, which disables the Single Bit Error interrupt. Value 0 1 Description The Single Bit Error interrupt is disabled. The Single Bit Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 313 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.2 Interrupt Enable Set Name:

Offset:

Reset:

Property: Write-Protected INTENSET 0x01 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 Access Reset 1 DUALE R/W 0 0 SINGLEE R/W 0 Bit 1 DUALEDual Bit Error Interrupt Enable Set Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Dual Bit Error Interrupt Enable bit, which enables the Dual Bit Error interrupt. Value 0 1 Description The Dual Bit Error interrupt is disabled. The Dual Bit Error interrupt is enabled. Bit 0 SINGLEESingle Bit Error Interrupt Enable Set Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Single Bit Error Interrupt Enable bit, which disables the Single Bit Error interrupt. Value 0 1 Description The Single Bit Error interrupt is disabled. The Single Bit Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 314 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.3 Interrupt Flag Status and Clear Name:

Offset:

Reset:

INTFLAG 0x02 0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 DUALEDual Bit ECC Error Interrupt This flag is set on the occurrence of a dual bit ECC error. Writing a '0' to this bit has no effect. Reading the ECCADDR register will clear the Dual Bit Error interrupt flag. Value 0 1 Description No dual bit errors have been received since the last clear. At least one dual bit error has occurred since the last clear. Bit 0 SINGLEESingle Bit ECC Error Interrupt This flag is set on the occurrence of a single bit ECC error. Writing a '0' to this bit has no effect. Reading the ECCADDR register will clear the Single Bit Error interrupt flag. Value 0 1 Description No errors have been received since the last clear. At least one single bit error has occurred since the last clear. 1 DUALE R/W 0 0 SINGLEE R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 315 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.4 Status Name:

Offset:

Reset:

Property: Read-only STATUS 0x03 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 ECCDISECC Disable 0 ECCDIS R 0 This bit is fuse updated at startup based on DEVCFG0/CFGCON0.FRECCDIS bit in the Boot Flash device configuration. When enabled, the calculated ECC is written to SRAM along with data. ECC correction and detection is enabled for reads. Value 0 1 Description ECC detection and correction is enabled. ECC detection and correction is disabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 316 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.5 Error Address Name:

Offset:

Reset:

Property: Read-only ERRADDR 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 ERRADDR[17:16]

R R 0 0 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 11 12 ERRADDR[15:8]

R R 0 0 4 3 ERRADDR[7:0]

R 0 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 17:0 ERRADDR[17:0]ECC Error Address The RAM address offset from RAM start that caused an ECC error. If a single bit error is followed by a dual bit error, this register will be updated with the address of the dual bit error, otherwise it stalls on the first error occurrence. This register will read as zero unless INTFLAG.SINGLEE and/or INTFLAG.DUALE are 1. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 317 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family RAM Error Correction Code (RAMECC) 17.8.6 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x0F 0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 ECCELOGECC Error Log 1 ECCELOG R/W 0 0 ECCDIS R/W 0 When DBGCTRL.ECCDIS=0, This bit controls whether ECC errors are logged in the INTFLAG register. When DBGCTRL.ECCDIS=1, this bit has no meaning. Value 0 1 Description ECC errors for debugger reads are not logged. ECC errors for debugger reads are logged if DBGCTRL.ECCDIS=0. Bit 0 ECCDISECC Disable By default, ECC errors during debugger reads are corrected and logged based on DBGCTRL.ECCELOG. Setting this bit will disable ECC correction and logging. Value 0 1 Description ECC errors are are corrected for debugger reads and logged based on DBGCTRL.ECCELOG. ECC errors are masked for debugger reads. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 318 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18. System Configuration and Register Locking (CFG) 18.1 Overview A PIC32CX-BZ3 family device includes several non-volatile (programmable) configuration words that define the device behavior. The device configuration words are located in Boot Flash device config memory. These configuration words are loaded on equivalent system configuration registers after the device Reset. The write access to the system configuration registers is controlled through locking registers. 18.2 Features This PIC32CX-BZ3 device provides several user writable configuration registers related to the configuration and operation of the system. Permission Group Configuration Register (CFGPG) defines the permission group. System Key Register (SYSKEY) defines the system key. Configuration Control Register 0 (CFGCON0(L)) provides control, selection and locking for various features of the device. Note:The registers those are marked with (L) are loadable from Flash. PPS register locking PMD register locking CFGPG register locking Config register locking Trace port enable Flash, SRAM ECC control RTCC, AC Alternate pinout selection SERCOM slew rate enable Configuration Control Register 1 (CFGCON1(L)) provides control, selection and locking for various features of the device. QSPI DDR mode clock enable High-speed SERCOM, QSPI enable WDT sleep mode prescale configuration I2C slew rate control Configuration Control Register 2 (CFGCON2(L)) provides control, selection and locking for various features of the device. DMT enable and configuration WDT enable and configuration Clock monitoring and control Oscillator enable and configuration 2-Speed start-up enabled in Sleep Mode bit Configuration Control Register 4 (CFGCON4(L)) provides control, selection and locking for various features of the device. Deep sleep modules control SOSC configuration control RTCC event control User Unique ID Register (USERID(L)) provides the end user with a 16-bit ID field that may be read out directly through the SWD interface via the USERID SWD instruction. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 319 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.3 Modes of Operation 18.3.1 System Configuration Words The device configuration words programmed in Boot Flash memory (NVR pages) gets loaded on equivalent registers after the device reset. The following table shows the mapping between Boot Flash memory region and loading registers. Registers marked with (L) are loadable from Flash and they can be controlled by SW after the boot with correct unlock sequence. After programming the configuration words, the user must reset the device to ensure the configuration data is reloaded with the new programmed values. Table 18-1. Device Configuration in Flash vs Register Device Configuration (Flash) Physical Address in Flash Reloaded Register FBCFG0 FBCFG1/DEVCFG0 FBCFG2/DEVCFG1 FBCFG3/DEVCFG2 FBCFG4/DEVCFG4 FBCFG5/FUSERID 0x0080_5F9C 0x0080_5F98 0x0080_5F94 0x0080_5F90 0x0080_5F8C 0x0080_5F88 BCFG0 (0x4400_0200) CFGCON0(L) (0x4400_0000) CFGCON1(L) (0x4400_0010) CFGCON2(L) (0x4400_0020) CFGCON4(L) (0x4400_0040) USERID(L) (0x4400_00A0) Other than device configurations in boot flash region, there are some more system configuration registers. They are run time programmable and do not have associated Flash region. CFGPGQOS This register defines the permission group settings for various bus masters on the device bus matrix. CFGPCLKGENx (x = 1, 2, 3, and 4) These registers dictate the peripheral clock selection and enable the clock for specific peripheral. See Clock and Reset Unit (CRU) from Related Links for more details. Related Links 13. Clock and Reset Unit (CRU) 18.3.1.1 System Configuration Register Protection To ensure data integrity of each system configuration word, a comparison is continuously made between each configuration bit and its stored complement. If a mismatch is detected, a Configuration Mismatch Reset is generated causing a device Reset. 18.3.2 Alternate System Configuration Words In the PIC32CX-BZ3 family of devices, the configuration words select various device configurations, and are located at physical addresses from 0x00805F80 (FBCFG7). If an unrecoverable ECC error occurs when reading the configuration words, the alternate configuration words are used to configure the device from Boot Flash memory. This configuration can be identical to the primary configuration words, or different to operate in another condition. The alternate configuration words are located at physical addresses from 0x00805E80 (ALTFBCFG7). To flag that an ECC error has occurred, the BCFGERR

(RCON[27]) bit is set. If uncorrectable ECC errors are found in both primary and alternate words, the BCFGFAIL (RCON[26]) bit is set and the default configuration is used. After programming the configuration words, the user application must reset the device to ensure the configuration data is reloaded with the new programmed values. 18.4 Locking and Unlocking the System Configuration Registers Write access to the system configuration registers is controlled via the CFGCON0.CFGLOCK[1:0] register bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 320 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.5 NMI Events The only system configuration that gets Reset on an NMI event are CPUPG bits in the CFGPGQOS register. This allows application firmware to pass control back to the bootloader and re-enable reads of all configuration words from Boot Flash NVR pages if reads of the Boot Flash pages were disabled using group permissions. 18.6 Register Locking Several modules contain registers that are protected from errant code causing unwanted changes by the system lock feature. When the system lock is in effect, system lock protected registers are not writable. The system lock feature protects registers that are system critical. The PIC32CX-BZ3 provides different methods of register level locking:

18.6.1 1-Way Lock This mechanism provides 1-way lock (once locked, only a Reset can unlock) using the CFGCON0.IOLOCK, CFGCON0.PMDLOCK, CFGCON0.PMULOCK, and CFGCON0.PGLOCK register bits. This method includes protection for the following registers:

All PPS registers using CFGCON0.IOLOCK All PMD registers using CFGCON0.PMDLOCK CFGPGQOS register using CFGCON0.PGLOCK All PMU registers using CFGCON0.PMULOCK 18.6.2 1-Way or 2-Way Lock (Software Selectable) If CFGCON0.CFGLOCK[1:0] is 10, it locks the registers, but it is also possible to unlock by writing 00 to CFGCON0.CFGLOCK[1:0]. If CFGCON0.CFGLOCK[1:0] is 11, it locks the registers, and it is no longer possible to unlock as CFGCON0.CFGLOCK[1:0] bits are also locked. Only system Reset can unlock. This mechanism provides 1-way or 2-way lock (software selectable) using the CFGCON0.CFGLOCK[1:0] register bits. This method applies to the following registers:

BCFG0 CFGCON0 CFGCON1 CFGCON2 CFGCON4 CFGPCLKGENx USER_ID 18.6.3 2-Way Lock and Unlock Each module that uses the system lock feature describes register bits and functions, which are affected by this system lock feature. A specific sequence of writes to the SYSKEY register unlock the access to those register bits and features. This locking method provides a 2-way (locking and unlocking) write lock of system critical registers. It includes protection for the following registers:

CRU.OSCCON CRU.OSCTRM CRU.SPLLCON CRU.RSWRST CRU.RNMICON CRU.PB1DIV CRU.PB2DIV CRU.PB3DIV CRU.SLEWCON 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 321 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... CRU.CLK_DIAG 18.6.3.1 Unlock Requirements The unlock sequence must be atomic. If any other peripheral bus access occurs on the same peripheral bus on which SYSKEY resides during the unlock attempt sequence, the unlock fails. Therefore, turn off all bus initiators, such as DMA; and disable interrupts. 18.6.3.2 Unlock Sequence The following steps to be followed to unlock the CFG registers. The unlock sequencer, looks for steps 3 and 4 to be atomic. For this sequence, atomic means that there is no other activity on the peripheral bus between steps 3 and 4. Step 2 is only needed to ensure that the sequence starts from a known locked state. Suspend all other Peripheral Bus accesses 1. 2. Write SYSKEY = 0x00000000 3. Write SYSKEY = 0xAA996655 4. Write SYSKEY = 0x556699AA 18.6.3.3 Lock Sequence When the system is unlocked, any write to the SYSKEY register causes the system lock to become active. 18.6.3.4 Lock/Unlock Indication The SYSKEY register read value indicates the status of the unlock sequence. A value of 0x00000000 indicates the system is still locked. A value of 0x00000001 indicates the sequence succeeded and the system is unlocked. 18.7 Effects of Various Resets The configuration data is reloaded from the corresponding Boot Flash memory configuration words on the following types of reset:

Power-on Reset (POR) Brown-out Reset (BOR) External Reset (NMCLR) Configuration Mismatch Reset (CM) Watchdog Timer Reset (WDTR) Software Reset (SWR) NMI Time-out Reset (NMITR) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 322 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.8 Register Summary See CFG module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CFGCON0(L) 0x04

... 0x0F Reserved 0x10 CFGCON1(L) 0x14

... 0x1F Reserved 0x20 CFGCON2(L) 0x24

... 0x3F Reserved 0x40 CFGCON4(L) 0x44

... 0x4F Reserved 0x50 CFGPGQOS 0x54

... 0x5F Reserved 0x60 CFGPCLKGEN1 0x64

... 0x6F Reserved 0x70 CFGPCLKGEN2 7:0 CPENFILT ACCMP1_ALT EN ADCPOVR JTAGEN TROEN SWOEN 15:8 23:16 31:24 CFGLOCK[1:0]

IOLOCK PMDLOCK PGLOCK PMULOCK RTCOUT_ALT EN RTCIN0_ALT EN SLRTEN2 SLRTEN1 SLRTEN0 HPLUGDIS SMBUSEN2 SMBUSEN1 SMBUSEN0 FRECCDIS ECCCTL[1:0]

INT0P INT0E PCM 7:0 ZBTWKSYS ECC_SEL_M EM TRCEN 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 QSCHE_EN SMCLR SLRCTRL2 SLRCTRL1 SLRCTRL0 CMP1_OE CMP0_OE I2CDSEL2 I2CDSEL1 I2CDSEL0 CCL_OE SCOM_HSEN[1:0]

QSPI_HSEN CLKZBREF QSPIDDRM WDTPSS[4:0]

FSCMEN CKSWEN WAKE2SPD SOSCSEL WDTRMCS[1:0]

POSCMD[1:0]

WDTEN DMTEN WINDIS WDTSPGM WDTPSR[4:0]

DMTCNT[4:0]

WINSZ[1:0]

DMTINTV[2:0]

ACMP_CYCLE[2:0]

SOSC_CFG[7:0]

MLPCLK_MO D VBKP_DIVSE L VBKP_32KCSEL[1:0]

VBKP_1KCSE L RTCEVENT_ EN RTCEVENTSEL[1:0]

DSWDTPS[2:0]

DSZPBOREN CPEN_DLY[2:0]

RTCEVTYPE RTCNTM_CS EL LPOSCEN UVREGROVR DSBITEN DSWDTEN DSWDTLPRC DSWDTPS[4:3]

CRYPTOQOS[1:0]

WISIBQOS[1:0]

CRYPTOPG[1:0]

FCQOS[1:0]

CPUQOS[1:0]

CPUPG[1:0]

DMAPG[1:0]

DSUPG[1:0]

7:0 FREQMRCD FREQMRCSEL[2:0]

EICCD EICCSEL[2:0]

15:8 23:16 31:24 SERCOM01C D TCC12CD CM4TCD SERCOM01CSEL[2:0]

FREQMMCD FREQMMCSEL[2:0]

TCC12CSEL[2:0]

CM4TCSEL[2:0]

SERCOM2CD SERCOM2CSEL[2:0]

7:0 15:8 23:16 31:24 EVSYSC2CD EVSYSC4CD EVSYSC6CD EVSYSC8CD EVSYSC2SEL[2:0]

EVSYSC4SEL[2:0]

EVSYSC6SEL[2:0]

EVSYSC8SEL[2:0]

EVSYSC1CD EVSYSC3CD EVSYSC5CD EVSYSC7CD EVSYSC1SEL[2:0]

EVSYSC3SEL[2:0]

EVSYSC5SEL[2:0]

EVSYSC7SEL[2:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 323 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... ..........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x74

... 0x7F Reserved 7:0 0x80 CFGPCLKGEN3 15:8 0x84

... 0x8F Reserved 0x90 CFGPCLKGEN4 0x94

... 0x9F Reserved 0xA0 USER_ID 0xA4

... 0xAF Reserved 0xB0 SYSKEY 0xB4

... 0x01FF Reserved 0x0200 BCFG0 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 EVSYSC10C D EVSYSC12C D TCC0CD EVSYSC10SEL[2:0]

EVSYSC9CD EVSYSC9SEL[2:0]

EVSYSC12SEL[2:0]

EVSYSC11CD EVSYSC11SEL[2:0]

TCC0CSEL[2:0]

ACCD ACCSEL[2:0]

TC1CD TC45CD TC1CSEL[2:0]

TC45CSEL[2:0]

TC0CD TC23CD TC67CD TC0CSEL[2:0]

TC23CSEL[2:0]

TC67CSEL[2:0]

USER_ID[7:0]

USER_ID[15:8]

SYSKEY[7:0]

SYSKEY[15:8]

SYSKEY[23:16]

SYSKEY[31:24]

BINFOVALID0 SIGN CP PCSCMODE Related Links 7. Product Memory Mapping Overview 18.9 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 324 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 325 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.1 Configuration Control Register 0 Name:

Offset:

Reset:

Property:

CFGCON0(L) 0x00 0x7100000b

The CFGLOCK[1:0] register bits are writable only when CFGLOCK[0] = 0. The IOLOCK, PMDLOCK and PGLOCK register bits can only be cleared on a system reset. Thereafter, these bits are writable using CFGLOCK. This register is loaded with trusted data from FBCFG1/DEVCFG0 during pre-boot period. Trusted data from Flash means, when there is no BCFG* fail status and BINFOVALID = 0 during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication then Reset values (described in the following register description) are retained and new values from FBCFG1 are not loaded. Under all conditions, Flash loading is omitted for the following bits in CFGCON0 register:

IOLOCK CFGLOCK[1:0]

PMDLOC PGLOCK PMULOCK JTAGEN HPLUGDIS Hence, writing these bits in Boot Flash will not have effect on the configuration register. Bit 31 Access Reset Bit Access Reset 23 SLRTEN2 R/W/L 0 30 FRECCDIS R/L 1 22 SLRTEN1 R/W/L 0 29 28 ECCCTL[1:0]

R/W/L 1 R/W/L 1 27 26 INT0P R/W/L 0 25 INT0E R/W/L 0 21 SLRTEN0 R/W/L 0 20 HPLUGDIS R/W 0 19 SMBUSEN2 R/W/L 0 18 SMBUSEN1 R/W/L 0 17 SMBUSEN0 R/W/L 0 Bit 15 14 CFGLOCK[1:0]

13 IOLOCK 12 PMDLOCK 11 PGLOCK 10 9 PMULOCK RTCOUT_ALTE Access Reset R/W/L 0 R/W/L 0 Bit 7 CPENFILT Access Reset R/W/L 0 6 ACCMP1_ALTE N R/W/L 0 R/S/L 0 5 R/S/L 0 R/S/L 0 4 ADCPOVR 3 JTAGEN R/W/L 0 R/W/L 1 R/S/L 0 2 TROEN R/W/L 0 N R/W/L 0 1 SWOEN R/W/L 1 24 PCM R/W/L 1 16 8 RTCIN0_ALTE N R/W/L 0 0 Bit 30 FRECCDISFlex RAM (SRAM) ECC Control Note:Only a read-only fuse bit, sets the initialization value of RAMECC Control. True RAMECC override is available in the RAMECC module. Value 1 0 Description ECC is disabled ECC is enabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 326 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Bits 29:28 ECCCTL[1:0]Flash ECC Control Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 11 10 01 00 Description ECC and dynamically ECC are disabled ECC and dynamically ECC are disabled Dynamically ECC is enabled ECC is enabled (NVMCON.NVMOP[3:0] != 1 (Word programming)) Bit 26 INT0PINT0P Polarity Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description INT0 Polarity (High) INT0 Polarity (Low) Bit 25 INT0EINT0 Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description INT0 is enabled INT0 is disabled Bit 24 PCMPCHE I/D Cacheable Mode Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Always enabled from outside. Can be further enabled/disabled by PCHE SFR registers. The cache-ability is controlled by the CPU via HPROT[3] of ARM protection control bus. Bit 23 SLRTEN2Slew Rate Enable for SERCOM2 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate is enabled Slew rate is disabled Bit 22 SLRTEN1Slew Rate Enable for SERCOM1 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate is enabled Slew rate is disabled Bit 21 SLRTEN0Slew Rate Enable for SERCOM0 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate is enabled Slew rate is disabled Bit 20 HPLUGDISHot Plugging Disable (outside fuse loading) Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Hot plugging is disabled Hot plugging is enabled Bit 19 SMBUSEN2SMBus Enable for SERCOM2 Note:This bit is only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 327 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description SMBus is enabled SMBus is disabled Bit 18 SMBUSEN1SMBus Enable for SERCOM1 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description SMBus is enabled SMBus is disabled Bit 17 SMBUSEN0SMBus Enable for SERCOM0 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description SMBus is enabled SMBus is disabled Bits 15:14 CFGLOCK[1:0]Configuration Register Lock Note:These bits are only writable when CFGLOCK[1:0] is 00 or 10. Value 11 10 01 00 Description All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG*

and USER_ID) are locked and cannot be written. CFGLOCK value cannot be changed. All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG*

and USER_ID) are locked and cannot be written. CFGLOCK value can be changed. Reserved for future use All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG*

and USER_ID) are not locked and can be written. CFGLOCK value can be changed. Bit 13 IOLOCKI/O Lock Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description I/O Remap SFR bits are locked and cannot be modified I/O Remap SFR bits are not locked and can be modified Bit 12 PMDLOCKPeripheral Module Disable (PMD) Lock Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description PMDx SFR bits are locked and cannot be modified PMDx SFR bits are not locked and can be modified Bit 11 PGLOCKPermission Group Lock Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description CFGPG SFR bits are locked and cannot be modified CFGPG SFR bits are not locked and can be modified Bit 10 PMULOCKPMU Controller Register Lock Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description PMU* SFR bits are locked and cannot be modified PMU* SFR bits are not locked and can be modified Bit 9 RTCOUT_ALTENRTCOUT Alternate Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 328 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description RTC/OUT is available on PA10 RTC/OUT is available on PA4 Bit 8 RTCIN0_ALTENRTCIN0 Alternate Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description RTC_IN0 is available on PA9 RTC_IN0 is available on PA3 Bit 7 CPENFILTADC CP Filter Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description ADC CP filter is enabled ADC CP filter is disabled Bit 6 ACCMP1_ALTENAC CMP1 Alternate Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description AC_CMP1 Out is available on PA6 AC_CMP1 Out is available on PA13 Bit 4 ADCPOVRADC Charge Pump Override Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Overridden (Software controlled) Hardware controlled Bit 3 JTAGENJTAG Enable Note:JTAG functionality is not available in the PIC32CX-BZ3 devices. The default value of this bit is 1. It is recommended to write 0 to this bit during Application initialization to use JTAG pins for regular GPIO functionality. For pin details, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. Bit 2 TROENTrace Output Enable Notes:

When CFGCON1.TRCEN = 0, the value of this bit is ignored but has the effect of being 0. This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Start Trace Clock and enable Trace Outputs (Trace probe must be present) Stop Trace Clock and disable Trace Outputs Bit 1 SWOENSWO Enable on 2-wire Debug interface Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description SWO is enabled SWO is disabled Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 329 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.2 Configuration Control Register 1 Name:

Offset:

Reset:

Property:

CFGCON1(L) 0x10 0x1f00443b

This register is loaded with trusted data from FBCFG2/DEVCFG1 during pre-boot period. Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication then Reset values (described in the following register description) are retained and new values from FBCFG2 are not loaded. Under all conditions, Flash loading is omitted for ZBTWKSYS bit in CFGCON1 register. Hence, writing this bit in Boot Flash will not have effect on the configuration register. Bit 31 30 CLKZBREF R/W/L 0 29 QSPIDDRM R/W/L 0 23 I2CDSEL2 R/W/L 0 22 I2CDSEL1 R/W/L 0 21 I2CDSEL0 R/W/L 0 Access Reset Bit Access Reset 28 27 R/W/L 1 19 R/W/L 1 20 CCL_OE R/W/L 0 Bit 15 QSCHE_EN Access Reset R/W/L 0 14 SMCLR R/W/L 1 13 SLRCTRL2 R/W/L 0 12 SLRCTRL1 R/W/L 0 11 SLRCTRL0 R/W/L 0 26 WDTPSS[4:0]

R/W/L 1 25 24 R/W/L 1 R/W/L 1 18 17 SCOM_HSEN[1:0]

R/W/L 0 16 QSPI_HSEN R/W/L 0 R/W/L 0 10 9 CMP1_OE R/W/L 0 8 CMP0_OE R/W/L 0 Bit 7 6 ZBTWKSYS ECC_SEL_ME Access Reset R/W/L 0 M R/W/L 0 5 TRCEN R/W/L 1 Bit 30 CLKZBREFExternal Reference Clock 4 3 2 1 0 The external reference clock output from Zigbee wireless subsystem on REFO1 pin which is configurable through PPS. Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Clock from Zigbee wireless subsystem on PPS.REFO1 is enabled No clock from Zigbee wireless subsystem on PPS.REFO1 Bit 29 QSPIDDRMQSPI Double Data Rate (DDR) Mode Clock Enable Notes:

When using the QSPI DDR mode, System Clock (SYS_CLK) must be <= 32 MHz. This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description QSPI DDR mode clock is enabled QSPI DDR mode clock is disabled Bits 28:24 WDTPSS[4:0]Watchdog Timer Post-scale Select Sleep bits Note:These bits are only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 330 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description 1:1048576 1:524288 1:262144 1:131072 1:65536 1:32768 1:16384 1:8192 1:4096 1:2048 1:1024 1:512 1:256 1:128 1:64 1:32 1:16 1:8 1:4 1:2 1:1 Bit 23 I2CDSEL2I2C Delay Select for SERCOM2 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description I2C delay is enabled. TDLY_B delay gets added. See Electrical Characteristics from Related Links for TDLY_B delay value. I2C delay is disabled. TDLY_A is the default delay gets added. See Electrical Characteristics from Related Links for TDLY_A delay value. Bit 22 I2CDSEL1I2C Delay Select for SERCOM1 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description I2C delay is enabled I2C delay is disabled Bit 21 I2CDSEL0I2C Delay Select for SERCOM0 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description I2C delay is enabled I2C delay is disabled Bit 20 CCL_OECCL Pads (via PPS) Output Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description CCL pads (via PPS) output is enabled CCL pads (via PPS) output is disabled Bits 18:17 SCOM_HSEN[1:0]SERCOM (Direct) Enable, 17 = SERCOM0, and 18 = SERCOM1 Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Direct mode (High-Speed) is enabled Via PPS is enabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 331 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Bit 16 QSPI_HSENQSPI (Direct) Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Direct Mode (High-Speed) is enabled Via PPS is enabled Bit 15 QSCHE_ENQSPI Address Space Cache Attribute Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Cache attribute is enabled Caching is disabled Bit 14 SMCLRSelects CRU handling of NMCLR Control Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Does not reset all state of device NMCLR Reset NMCLR external Reset causes a faux POR Bit 13 SLRCTRL2I2C Slew Rate Control for SERCOM2 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate control is configured via SERCOM configuration Slew rate control is configured via GPIO configuration Bit 12 SLRCTRL1I2C Slew Rate Control for SERCOM1 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate control is configured via SERCOM configuration Slew rate control is configured via GPIO configuration Bit 11 SLRCTRL0I2C Slew Rate Control for SERCOM0 Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Slew rate control is configured via SERCOM configuration Slew rate control is configured via GPIO configuration Bit 9 CMP1_OEAnalog Comparator-1 Output Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description AC_CMP1 output is enabled AC_CMP1 output is disabled Bit 8 CMP0_OEAnalog Comparator-0 Output Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description AC_CMP0 output is enabled AC_CMP0 output is disabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 332 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Bit 7 ZBTWKSYSZBT Subsystem External Wake-up source Notes:

Write only bit, with read-as zero; when 1 is written, creates one pulse on the ZBT subsystem.external_NMI0 pin. This enables external system wake-up to ZBT subsystem. This allows CPU and ZBT subsystem wake-up/

sleep to be independent of each other. Flash fuse loading is excluded for this bit. Bit 6 ECC_SEL_MEMECC Row Selection This bit comes into effect only for 96K memory variant and if CFGCON0.FRECCDIS = 0. For other cases, this bit setting has no effect. Note:This bit is only writable when CFGLOCK[1:0] = 00. Value 1 0 Description RowC ECC is applied for Row B RowC ECC is applied for Row A Bit 5 TRCENTrace Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Trace features in the CPU are enabled Trace features in the CPU are disabled Related Links 38. Electrical Characteristics 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 333 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.3 Configuration Control Register 2 Name:

Offset:

Reset:

Property:

CFGCON2(L) 0x20 0x00

This register is loaded with trusted data from FBCFG3/DEVCFG2 during pre-boot period. Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication then reset values (described in the following register description) are retained and new values from FBCFG3 are not loaded. Under all conditions Flash loading is omitted for POSCMD[1:0] bits in CFGCON2 register. Hence, writing these bits in Boot Flash will not have effect on the configuration register. Bit Access Reset 31 DMTEN R/W/L 0 Bit 23 WDTEN R/W/L 0 Access Reset 30 29 R/W/L 1 22 WINDIS R/W/L 1 R/W/L 1 21 WDTSPGM R/W/L 1 28 DMTCNT[4:0]

R/W/L 1 27 26 25 24 WINSZ[1:0]

R/W/L 1 R/W/L 1 R/W/L 1 R/W/L 1 20 19 R/W/L 1 R/W/L 1 18 WDTPSR[4:0]

R/W/L 1 17 16 R/W/L 1 R/W/L 1 Bit Access Reset 15 FSCMEN R/W/L 1 14 CKSWEN R/W/L 1 13 WAKE2SPD R/W/L 1 12 SOSCSEL R/W/L 1 11 10 WDTRMCS[1:0]

9 8 POSCMD[1:0]

R/W/L 1 R/W/L 1 R/W/L 1 Bit 7 6 5 Access Reset R/W/L 1 4 DMTINTV[2:0]

R/W/L 1 3 2 R/W/L 1 R/W/L 0 1 ACMP_CYCLE[2:0]

R/W/L 0 Bit 31 DMTENDead Man Timer Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description DMT is enabled always and DMTCON.ON bit does not have control DMT disabled (control is placed on the DMTCON.ON bit) Bits 30:26 DMTCNT[4:0]Dead Man Timer Count Select Note:

These bits are only writable when CFGLOCK[1:0] is 00. Value 00000 00001

... 10100 10101 10110 10111 11000 -

11111 Description Counter value is 2^8 for DMTPSCNT[31:0]

Counter value is 2^9 for DMTPSCNT[31:0]

... Counter value is 2^28 for DMTPSCNT[31:0]

Counter value is 2^29 for DMTPSCNT[31:0]

Counter value is 2^30 for DMTPSCNT[31:0]

Counter value is 2^31 for DMTPSCNT[31:0]

Reserved R/W/L 1 0 R/W/L 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 334 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Bits 25:24 WINSZ[1:0]Watchdog Timer Window Size Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 00 01 10 11 Description Window size is 75%

Window size is 50%

Window size is 37.5%

Window size is 25%

Bit 23 WDTENWatchdog Timer Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description WDT is enabled always and WDTCON.ON bit does not have control WDT is disabled (control is placed on the WDTCON.ON bit) Bit 22 WINDISWindowed Watchdog Timer Disable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Standard WDT selected; windowed WDT disabled Windowed WDT enabled Bit 21 WDTSPGMWatchdog Timer Stop during Flash Programming Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description The WDT stops during NVR programming The WDT runs during NVR programming Bits 20:16 WDTPSR[4:0]Watchdog Timer Post-scale Select Run bits Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description 1:1048576 1:524288 1:262144 1:131072 1:65536 1:32768 1:16384 1:8192 1:4096 1:2048 1:1024 1:512 1:256 1:128 1:64 1:32 1:16 1:8 1:4 1:2 1:1 Bit 15 FSCMENFail-Safe Clock Monitor Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 335 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description FSCM enabled FSCM disabled Bit 14 CKSWENSoftware Clock Switching Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Software clock switching enabled Software clock switching disabled Bit 13 WAKE2SPD2-Speed startup enabled in Sleep mode Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description When the device EXITS Sleep Mode, the SYS_CLK will be from FRC until the selected clock is ready. When the device EXITS Sleep Mode, the SYS_CLK will be from the selected clock. Bit 12 SOSCSELSOSC Selection Configuration Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Crystal (SOSCI/SOSCO) mode Digital (SCLKI) mode Bits 11:10 WDTRMCS[1:0]WDT RUN Mode Clock Select Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 11 10 01 00 Description LPRC Reserved Reserved WDT PB Clock (PB1_CLK) Bits 9:8 POSCMD[1:0]Primary Oscillator Configuration Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 11 10 01 00 Description Primary oscillator is disabled Reserved Reserved Primary oscillator mode is selected Bits 5:3 DMTINTV[2:0]Dead Man Timer Count Window Interval Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 000 001 010 011 100 101 110 111 Description Window/Interval value is zero for DMTPSINTV[31:0] - windowed mode is disabled Window/Interval value is 1/2 Counter value for DMTPSINTV[31:0]

Window/Interval value is 3/4 Counter value for DMTPSINTV[31:0]

Window/Interval value is 7/8 Counter value for DMTPSINTV[31:0]

Window/Interval value is 15/16 Counter value for DMTPSINTV[31:0]

Window/Interval value is 31/32 Counter value for DMTPSINTV[31:0]

Window/Interval value is 63/64 Counter value for DMTPSINTV[31:0]

Window/Interval value is 127/128 Counter value for DMTPSINTV[31:0]

Bits 2:0 ACMP_CYCLE[2:0]AC Comparator Result Wait Cycles Note:These bits are only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 336 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value n Description Wait for 32 s* ACMP_CYCLE[2:0]+1 cycles to generate comparator done indication 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 337 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.4 Configuration Control Register 4 Name:

Offset:

Reset:

Property:

CFGCON4(L) 0x40 0x840e4000

This register is loaded with trusted data from FBCFG4/DEVCFG4 during pre-boot period. Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication then reset values (described in the following register description) are retained and new values from FBCFG4 are not loaded. 30 LPOSCEN 29 UVREGROVR 28 DSBITEN 27 DSWDTEN 26 DSWDTLPRC 25 24 DSWDTPS[4:3]

Bit 31 RTCNTM_CSE L R/W/L 1 Access Reset R/W/L 0 Bit 23 Access Reset R/W/L 0 22 DSWDTPS[2:0]

R/W/L 0 R/W/L 0 21 R/W/L 0 R/W/L 0 20 DSZPBOREN R/W/L 0 R/W/L 0 19 R/W/L 1 R/W/L 1 18 CPEN_DLY[2:0]

R/W/L 1 R/W/L 0 17 R/W/L 1 R/W/L 0 16 RTCEVTYPE R/W/L 0 Bit 15 14 13 12 11 10 9 8 MLPCLK_MOD VBKP_DIVSEL VBKP_32KCSEL[1:0]

VBKP_1KCSEL RTCEVENT_E RTCEVENTSEL[1:0]

Access Reset R/W/L 0 R/W/L 1 R/W/L 0 R/W/L 0 R/W/L 0 N R/W/L 0 R/W/L 0 R/W/L 0 Bit 7 6 5 Access Reset R/W/L 0 R/W/L 0 R/W/L 0 4 3 SOSC_CFG[7:0]

R/W/L 0 R/W/L 0 2 1 0 R/W/L 0 R/W/L 0 R/W/L 0 Bit 31 RTCNTM_CSELRTCC Counter Mode Clock Select Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Raw 32 KHz clock Processed 32 KHz clock Bit 30 LPOSCENLow Power (Secondary) Oscillator Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Enable Low Power (Secondary) Oscillator, also at Reset Disable Low Power (Secondary) Oscillator Bit 29 UVREGROVRULPVREG Retention Mode Override Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description ULPVREG forced in the Retention mode ULPVREG controlled by XDS/DS FSM Bit 28 DSBITENDeep Sleep Bit Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 338 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description Enable DS bit in DSCON Disable DS bit in DSCON Bit 27 DSWDTENDeep Sleep Watchdog Timer Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Enable DSWDT during deep sleep Disable DSWDT during deep sleep Bit 26 DSWDTLPRCDeep Sleep Watchdog Timer Reference Clock Select Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Select LPRC as DSWDT reference clock Select SOSC as DSWDT reference clock Bits 25:21 DSWDTPS[4:0]Deep Sleep Watchdog Timer Postscale Select The DS WDT prescaler is 32; this creates an approximate base time unit of 1 ms. Note:These bits are only writable when CFGLOCK[1:0] is 00. Value 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description 1:236 (25.7 days) 1:235 (12.8 days) 1:234 (6.4 days) 1:233 (77.0 hours) 1:232 (38.5 hours) 1:231 (19.2 hours) 1:230 (9.6 hours) 1:229 (4.8 hours) 1:228 (2.4 hours) 1:227 (72.2 minutes) 1:226 (36.1 minutes) 1:225 (18.0 minutes) 1:224 (9.0 minutes) 1:223 (4.5 minutes) 1:222 (135.3 s) 1:221 (67.7 s) 1:220 (33.825 s) 1:219 (16.912 s) 1:218 (8.456 s) 1:217 (4.228 s) 1:65536 (2.114 s) 1:32768 (1.057 s) 1:16384 (528.5 ms) 1:8192 (264.3 ms) 1:4096 (132.1 ms) 1:2048 (66.1 ms) 1:1024 (33 ms) 1:512 (16.5 ms) 1:256 (8.3 ms) 1:128 (4.1 ms) 1:64 (2.1 ms) 1:32 (1 ms) Bit 20 DSZPBORENDeep Sleep Zero-Power BOR Enable Note:This bit is only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 339 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description Enable ZPBOR during deep sleep Disable ZPBOR during deep sleep Bits 19:17 CPEN_DLY[2:0]Charge-pump Ready Digital Delay (Safety delay to Analog CP Ready) n = (n+1) LPRC Clock Cycle Delay Note:These bits are only writable when CFGLOCK[1:0] is 00. Bit 16 RTCEVTYPERTCC Event Type Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description RTC_EVENT RTC_OUT Bit 15 MLPCLK_MODLPCLK Modifier in Counter/Delay Mode Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Divide-by 1.024 (Recommended when LPCLK = 32.768 KHz) Divide-by 1 (Recommended when LPCLK = 32 KHz) Bit 14 VBKP_DIVSELVDDBUKPCORE LPCLK Clock Divider Selection Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Divide by 31.25 (Recommended when LPCLK = 32 KHz) Divide-by 32 (Recommended when LPCLK = 32.768 KHz) Bits 13:12 VBKP_32KCSEL[1:0]VDDBUKPCORE 32 KHz Clock Source Selection Notes:

When the field is 00 or 01 and Deep Sleep mode is entered and SOSC is not available, it is recommended that firmware change this value to 11(LPRC) before entering Deep Sleep. Any change of clock source will result in gaps in LPCLK output. This bit is only writable when CFGLOCK[1:0] is 00. Value 11 10 01 00 Description LPRC SOSC POSC FRC Bit 11 VBKP_1KCSELVDDBUKPCORE LPCLK Clock Selection Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Divide by 32 or 31.25 clock depending on VBKP_DIVSEL 32 KHz low power clock Bit 10 RTCEVENT_ENOutput Enable for RTCC Event Output Note:This bit is only writable when CFGLOCK[1:0] is 00. Value 1 0 Description Enables RTCC-Event output Disables RTCC-Event output Bits 9:8 RTCEVENTSEL[1:0]RTCC Event Selection Note:These bits are only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 340 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 00 01 1x Description 1-Second clock Alarm pulse 32 KHz clock Bits 7:0 SOSC_CFG[7:0]SOSC Configuration Bits Gain configuration for SOSC Oscillator:

G3>G2>G1>G0 11 = Gain is G3 10 = Gain is G2 01 = Gain is G1 00 = Gain is G0 Note:These bits are only writable when CFGLOCK[1:0] is 00. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 341 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.5 Permission Group Configuration Name:

Offset:

Reset:

Property:

CFGPGQOS 0x50 0xe044004c

All bits in this register are writable only when CFGCON0.PGLOCK = 0. There is no Flash location for this register because the purpose of this register to provide SW based protection mechanism to device memory mapped region. Bit 31 30 29 28 27 26 25 24 WISIBQOS[1:0]

FCQOS[1:0]

Access Reset R/W/L 1 R/W/L 1 R/W/L 1 R/W/L 0 Bit 23 22 CRYPTOQOS[1:0]

21 20 CRYPTOPG[1:0]

Access Reset R/W/L 0 R/W/L 1 R/W/L 0 R/W/L 0 DSUPG[1:0]

R/W/L 0 R/W/L 0 19 18 17 16 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 Access Reset DMAPG[1:0]

R/W/L 0 R/W/L 0 1 0 CPUPG[1:0]

R/W/L 0 R/W/L 0 3 2 CPUQOS[1:0]

R/W/L 1 R/W/L 1 Bits 31:30 WISIBQOS[1:0]Wireless SIB QOS Control bits Note:This field is only writable when CFGCON0.PGLOCK = 0 Value 00 01 10 11 Description Disable; Background Low; Sensitive bandwidth Medium; Sensitive latency High; Critical latency Bits 29:28 FCQOS[1:0]FC Controller QOS Control bits Note:This field is only writable when CFGCON0.PGLOCK = 0 Value 00 01 10 11 Description Disable; Background Low; Sensitive bandwidth Medium; Sensitive latency High; Critical latency Bits 25:24 DSUPG[1:0]DSU Permission Group The DSU bus master has access to Access Controlled memory regions in the Bus Structures Permission Groups SFRs. DSUPG[1:0] == 2b11 : Initiator is assigned to Permission Group 3 DSUPG[1:0] == 2b10 : Initiator is assigned to Permission Group 2 DSUPG[1:0] == 2b01 : Initiator is assigned to Permission Group 1 DSUPG[1:0] == 2b00 : Initiator is assigned to Permission Group 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 342 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Note:This field is only writable when CFGCON0.PGLOCK = 0 Bits 23:22 CRYPTOQOS[1:0]Crypto QOS Control bits Note:This field is only writable when CFGCON0.PGLOCK = 0 Value 00 01 10 11 Description Disable; Background Low; Sensitive bandwidth Medium; Sensitive latency High; Critical latency Bits 21:20 CRYPTOPG[1:0]Crypto Permission Group The Crypto bus master has access to Access Controlled memory regions in the Bus Structures Permission Groups SFRs. CRYPTOPG[1:0] == 2b11 : Initiator is assigned to Permission Group 3 CRYPTOPG[1:0] == 2b10 : Initiator is assigned to Permission Group 2 CRYPTOPG[1:0] == 2b01 : Initiator is assigned to Permission Group 1 CRYPTOPG[1:0] == 2b00 : Initiator is assigned to Permission Group 0 Note:This field is only writable when CFGCON0.PGLOCK = 0 Bits 9:8 DMAPG[1:0]DMA (Rd/Wr) Permission Group The DMA bus master has access to Access Controlled memory regions in the Bus Structures Permission Groups SFRs. DMAPG[1:0] == 2b11 : Initiator is assigned to Permission Group 3 DMAPG[1:0] == 2b10 : Initiator is assigned to Permission Group 2 DMAPG[1:0] == 2b01 : Initiator is assigned to Permission Group 1 DMAPG[1:0] == 2b00 : Initiator is assigned to Permission Group 0 Note:This field is only writable when CFGCON0.PGLOCK = 0 Bits 3:2 CPUQOS[1:0]CPU I/D and System Bus QOS Control bits Note:This field is only writable when CFGCON0.PGLOCK = 0 Value 00 01 10 11 Description Disable; Background Low; Sensitive bandwidth Medium; Sensitive latency High; Critical latency Bits 1:0 CPUPG[1:0]CPU (Code) Permission Group The CPU Bus master has access to Access Controlled memory regions in the Bus Structures Permission Groups SFRs. CPUPG[1:0] == 2b11 : Initiator is assigned to Permission Group 3 CPUPG[1:0] == 2b10 : Initiator is assigned to Permission Group 2 CPUPG[1:0] == 2b01 : Initiator is assigned to Permission Group 1 CPUPG[1:0] == 2b00 : Initiator is assigned to Permission Group 0 Notes:

CPUPG[1:0] automatically reverts to 2b00 when the CPU acknowledges entering into an NMI exception. This field is only writable when CFGCON0.PGLOCK = 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 343 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.6 Peripheral Clock Generator 1 Name:

Offset:

Reset:

Property:

CFGPCLKGEN1 0x60 0x00000000

The CFGPCLKGEN1 dictates the peripheral clock selection described in Clock and Reset Unit chapter. There is no Flash location for this register because the purpose of this register is to provide application based peripheral clocking selection. This is best handled in the application software drivers. Bit Access Reset 31 CM4TCD R/W 0 Bit Access Reset 23 TCC12CD R/W 0 Bit 15 SERCOM01CD R/W 0 Access Reset Bit 7 FREQMRCD Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 CM4TCSEL[2:0]

R/W 0 21 TCC12CSEL[2:0]

R/W 0 13 SERCOM01CSEL[2:0]

R/W 0 5 FREQMRCSEL[2:0]

R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 26 25 24 19 SERCOM2CD R/W 0 11 FREQMMCD R/W 0 3 EICCD R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 SERCOM2CSEL[2:0]

R/W 0 9 FREQMMCSEL[2:0]

R/W 0 1 EICCSEL[2:0]

R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bit 31 CM4TCDCM4_Trace Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 30:28 CM4TCSEL[2:0]CM4_Trace Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 23 TCC12CDTCC1 and TCC2 Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 22:20 TCC12CSEL[2:0]TCC1 and TCC2 Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 Description No clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 344 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1-6 7 Description REFO1-6 clock is selected Low power clock is selected Bit 19 SERCOM2CDSERCOM2 Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 18:16 SERCOM2CSEL[2:0]SERCOM2 Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 15 SERCOM01CDSERCOM0 and SERCOM1 Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 14:12 SERCOM01CSEL[2:0]SERCOM0 and SERCOM1 Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 11 FREQMMCDFREQM Measurement Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 10:8 FREQMMCSEL[2:0]FREQM Measurement Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 7 FREQMRCDFREQM Reference Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 6:4 FREQMRCSEL[2:0]FREQM Reference Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 345 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 3 EICCDEIC Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 2:0 EICCSEL[2:0]EIC Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 346 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.7 Peripheral Clock Generator 2 Name:

Offset:

Reset:

Property:

CFGPCLKGEN2 0x70 0x00000000

The CFGPCLKGEN2 dictates the peripheral clock selection described in Clock and Reset Unit chapter. There is no Flash location for this register because the purpose of this register is to provide application based peripheral clocking selection. This is best handled in the application software drivers. Bit 31 EVSYSC8CD R/W 0 Access Reset Bit 23 EVSYSC6CD R/W 0 Access Reset Bit 15 EVSYSC4CD R/W 0 Access Reset Bit 7 EVSYSC2CD R/W 0 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 EVSYSC8SEL[2:0]

R/W 0 21 EVSYSC6SEL[2:0]

R/W 0 13 EVSYSC4SEL[2:0]

R/W 0 5 EVSYSC2SEL[2:0]

R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 EVSYSC7CD R/W 0 19 EVSYSC5CD R/W 0 11 EVSYSC3CD R/W 0 3 EVSYSC1CD R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 EVSYSC7SEL[2:0]

R/W 0 17 EVSYSC5SEL[2:0]

R/W 0 9 EVSYSC3SEL[2:0]

R/W 0 1 EVSYSC1SEL[2:0]

R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bit 31 EVSYSC8CDEVSYS Channel 8 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 30:28 EVSYSC8SEL[2:0]EVSYS Channel 8 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 27 EVSYSC7CDEVSYS Channel 7 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 26:24 EVSYSC7SEL[2:0]EVSYS Channel 7 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 Description No clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 347 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1-6 7 Description REFO1-6 clock is selected Low power clock is selected Bit 23 EVSYSC6CDEVSYS Channel 6 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 22:20 EVSYSC6SEL[2:0]EVSYS Channel 6 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 19 EVSYSC5CDEVSYS Channel 5 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 18:16 EVSYSC5SEL[2:0]EVSYS Channel 5 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 15 EVSYSC4CDEVSYS Channel 4 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 14:12 EVSYSC4SEL[2:0]EVSYS Channel 4 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 11 EVSYSC3CDEVSYS Channel 3 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 10:8 EVSYSC3SEL[2:0]EVSYS Channel 3 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 348 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 7 EVSYSC2CDEVSYS Channel 2 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 6:4 EVSYSC2SEL[2:0]EVSYS Channel 2 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 3 EVSYSC1CDEVSYS Channel 1 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 2:0 EVSYSC1SEL[2:0]EVSYS Channel 1 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 349 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.8 Peripheral Clock Generator 3 Name:

Offset:

Reset:

Property:

CFGPCLKGEN3 0x80 0x00000000

The CFGPCLKGEN3 dictates the peripheral clock selection described in Clock and Reset Unit chapter. There is no Flash location for this register because the purpose of this register is to provide application based peripheral clocking selection. This is best handled in the application software drivers. Bit 31 30 29 28 27 26 25 24 Access Reset Bit Access Reset 23 TCC0CD R/W 0 Bit 15 EVSYSC12CD R/W 0 Access Reset Bit 7 EVSYSC10CD R/W 0 Access Reset 22 R/W 0 14 R/W 0 6 R/W 0 21 TCC0CSEL[2:0]

R/W 0 13 EVSYSC12SEL[2:0]

R/W 0 5 EVSYSC10SEL[2:0]

R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 19 ACCD R/W 0 11 EVSYSC11CD R/W 0 3 EVSYSC9CD R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 ACCSEL[2:0]

R/W 0 9 EVSYSC11SEL[2:0]

R/W 0 1 EVSYSC9SEL[2:0]

R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bit 23 TCC0CDTCC0 Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 22:20 TCC0CSEL[2:0]TCC0 Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 19 ACCDAnalog Comparator Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 18:16 ACCSEL[2:0]Analog Comparator Peripheral Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 Description No clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 350 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1-6 7 Description REFO1-6 clock is selected Low power clock is selected Bit 15 EVSYSC12CDEVSYS Channel 12 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 14:12 EVSYSC12SEL[2:0]EVSYS Channel 12 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 11 EVSYSC11CDEVSYS Channel 11 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 10:8 EVSYSC11SEL[2:0]EVSYS Channel 11 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 7 EVSYSC10CDEVSYS Channel 10 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 6:4 EVSYSC10SEL[2:0]EVSYS Channel 10 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 3 EVSYSC9CDEVSYS Channel 9 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 2:0 EVSYSC9SEL[2:0]EVSYS Channel 9 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 351 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 352 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.9 Peripheral Clock Generator 4 Name:

Offset:

Reset:

Property:

CFGPCLKGEN4 0x90 0x00000000

The CFGPCLKGEN4 dictates the peripheral clock selection described in Clock and Reset Unit chapter. There is no Flash location for this register because the purpose of this register is to provide application based peripheral clocking selection. This is best handled in the application software drivers. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 Access Reset Bit Access Reset Bit Access Reset 15 TC45CD R/W 0 7 TC1CD R/W 0 14 R/W 0 6 R/W 0 13 TC45CSEL[2:0]

R/W 0 5 TC1CSEL[2:0]

R/W 0 12 R/W 0 4 R/W 0 19 TC67CD R/W 0 11 TC23CD R/W 0 3 TC0CD R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 TC67CSEL[2:0]

R/W 0 9 TC23CSEL[2:0]

R/W 0 1 TC0CSEL[2:0]

R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bit 19 TC67CDTC6 and TC7 Peripheral Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 18:16 TC67CSEL[2:0]TC6 and TC7 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 15 TC45CDTC4 and TC5 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 14:12 TC45CSEL[2:0]TC4 and TC5 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 Description No clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 353 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1-6 7 Description REFO1-6 clock is selected Low power clock is selected Bit 11 TC23CDTC2 and TC3 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 10:8 TC23CSEL[2:0]TC2 and TC3 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 7 TC1CDTC1 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 6:4 TC1CSEL[2:0]TC1 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 clock is selected Low power clock is selected Bit 3 TC0CDTC0 Clock Enable Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1 Description Clock is disabled Clock is enabled Bits 2:0 TC0CSEL[2:0]TC0 Clock Selection Note:This field is only writable when CFGCON0.PGLOCK is 0 Value 0 1-6 7 Description No clock is selected REFO1-6 is clock selected Low power clock is selected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 354 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.10 User Unique ID Name:

Offset:

Reset:

Property:

USER_ID 0xA0 0x00000000

The User ID is a 16-bit ID that may be programmed to differentiate products that use the same device. The User ID value may be read directly out of the USER_ID register or through the SWD interface. There is no dedicated status bit to indicate when the User ID value is loaded into the USER_ID register, and is ready to be read from SWD. It is assumed that a non-zero value for the User ID will be used to indicate that the User ID is loaded. The USER_ID register is reset on power-up then is loaded with trusted data from FBCFG5 during pre-boot period and it is controlled. Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication then reset values (described in the following register description) are retained and new values from FBCFG5/FUSERID are not loaded. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset R/W/L 0 R/W/L 0 R/W/L 0 USER_ID[15:8]

R/W/L 0 R/W/L 0 R/W/L 0 R/W/L 0 R/W/L 0 Bit 7 6 5 4 3 2 1 0 Access Reset R/W/L 0 R/W/L 0 R/W/L 0 USER_ID[7:0]

R/W/L 0 R/W/L 0 R/W/L 0 R/W/L 0 R/W/L 0 Bits 15:0 USER_ID[15:0]User unique ID Note:This field is only writable when CFGLOCK[1:0] is 00 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 355 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 29 SIGN R c 21 28 CP R c 20 27 26 25 24 19 18 17 16 18.9.11 Boot Configuration 0 Name:

Offset:

Reset:

Property:

BCFG0 0x200 0x00

Bit 31 BINFOVALID0 R c Access Reset 30 Bit 23 22 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 31 BINFOVALID0First 256-bit BCFG information is valid Notes:

1 PCSCMODE R c 8 0 1. 2. 3. This bit is added to know if the information from Flash is valid or invalid. The BCFG area is critical to device boot up. Trusted FBCFG* data = (BINFOVALID = 0) and (BCFGFAIL = 0). It is recommended for application to program this bit to zero for proper operation. Value 1 0 Description FBCFG0 to FBCFG7 is not valid (Untrusted, flash values are ignored and safe values are used) FBCFG0 to FBCFG7 is valid (Trusted and loaded from Flash) Bit 29 SIGNFlash SIGN bit This bit is a read only bit. Reading this bit returns the value of the SIGN bit in the FSIGN0 fuse location (invisible to user) in the NVR memory. Description Value Unsigned 1 Signed 0 Bit 28 CPCode Protect The CP bit is a read only bit. Reading this bit returns the inverted value of the CP bit in the FCPN0 Flash location

(~FCPN0.CP && ~FSIGN0.SIGN). To set Code Protect, the CP bit in the FCPN0 fuse location in the NVR memory must be set to 1. Value 1 0 Description Protection enabled Protection disabled Bit 1 PCSCMODEPCHE Single cache mode Note:This bit must be changed only when there are no active accesses to Flash from CPU. If changed while CPU is accessing Flash may result in System hang. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 356 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... Value 1 0 Description PCHE ICache Only. CPU Instructions (code, data) go to PCHE ICache only. PCHE ICache and DCache. CPU opcodes go to PCHE ICache port and data goes to PCHE DCache port. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 357 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family System Configuration and Register Locking ... 18.9.12 System Key Register Name:

Offset:

Reset:

SYSKEY 0xB0 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 SYSKEY[31:24]

R/W 0 20 R/W 0 19 SYSKEY[23:16]

R/W 0 12 R/W 0 11 SYSKEY[15:8]

R/W 0 4 R/W 0 3 SYSKEY[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 SYSKEY[31:0]System Key Keys are written to this register as part of a sequence to unlock system critical registers. A successful key write to this register will set the system signal. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 358 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) 19. Peripheral Module Disable (PMD) 19.1 Overview The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using an appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, therefore writing to those registers does not have effect and read values are invalid. 19.2 Enabling Peripherals The Peripheral Module Disable (PMD) register bits control the operation of individual peripherals on the device. When a peripherals associated PMD bit is 0, the peripheral is enabled and operates as programmed. However, when the associated PMD bit is 1, the peripheral logic, memory map and SFR bits are removed from visibility and the peripheral is held in reset. This disabled state provides for the lowest power state of the peripheral. Before a peripheral may be configured or used, clear the corresponding PMD register bit to enable the peripheral. There are some caveats to use PMD bits. The following must be observed:

1. Disabling a peripheral while its ON bit is 0 results in an undefined behavior of the external interface. For bus initiators, the software must verify that the module is not busy after setting ON bit to 0 before 2. disabling it. Setting the PMD bit when there is a pending interrupt results in an undefined behavior. Therefore, all interrupt flags must be cleared before setting the associated PMD bit. 3. 19.3 Controlling Configuration Changes Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. The PIC32CX-BZ3 devices include a Control register lock sequence feature to prevent alterations to the enabled or disabled peripherals. 19.3.1 Control Register Lock Under normal operation, writing to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in the hardware. The CFGCON0.PMDLOCK configuration bit controls the register lock. Setting CFGCON0.PMDLOCK prevents write to the control registers and clearing CFGCON0.PMDLOCK allows write operation. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 359 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) 19.4 PMD Register Summary See PMD module in the Product Memory Mapping Overview from Related Links for base address. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00

... 0xBF Reserved 0xC0 PMD1 0xC4

... 0xCF Reserved 0xD0 PMD2 0xD4

... 0xDF Reserved 0xE0 PMD3 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ADCMD ACMD QSPIMD CVDMD ADCSARMD RTCCMD REFO4MD REFO3MD REFO2MD REFO1MD REFO6MD REFO5MD TC3MD TC2MD TC1MD TC0MD TCC2MD TCC1MD TCC0MD DACMD TC7MD SER2MD SER1MD SER0MD TC6MD TC5MD TC4MD Related Links 7. Product Memory Mapping Overview 19.5 Register Description Some peripherals include module enable bits internally. The PMD bit is used for clock gating of the PBx_CLK and GCLK for all peripherals. If the peripheral also includes the internal enable bit, the PMD bit and internal enable configuration bit must be configured by software for that peripheral. The following table summarizes each peripherals enable and disable controls. For more details on the internal enable/disable control, see Peripheral Access Controller (PAC) from Related Links. Table 19-1. Module Enable/Disable Controls Module PMD control Module control Enable/Disable Strategy AC ADC CCL CVD CMCC DAC DMAC DSU Present Present NA Present NA Present NA NA Present Present Present Present Present Present Present NA Disable at PMD or Module Disable at PMD or Module Disable at Module Disable at PMD or Module Disable at Module Disable at PMD or Module Disable at Module Always Enabled (Dynamic On/Off) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 360 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD)

...........continued Module PMD control Module control Enable/Disable Strategy EIC EVSYS FREQM PAC QSPI NA NA NA NA Present RAMECC NA RTCC Present SERCOM Present TC TCC Present Present Present NA Present NA Present NA Present Present Present Present Disable at Module Always Enabled (Dynamic On/Off) Disable at Module Always Enabled (Dynamic On/Off) Disable at PMD or Module Disabled by default Disable at PMD or Module Disable at PMD or Module Disable at PMD or Module Disable at PMD or Module Note:For Modules with both PMD control and Module control, Enable = PMDx=0 AND Module Enable=1, Disable

=PMDx=1 OR Module Enable=0. Related Links 20. Peripheral Access Controller (PAC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 361 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) 19.5.1 PMD1 - Peripheral Module Disable 1 Register Name:

Offset:

Reset:

Property:

PMD1 0x00C0 0x00000000

Note:This register bits are only writable when CFGCON0.PMDLOCK = 0. Bit 31 30 Access Reset 29 QSPIMD R/W/L 0 28 27 26 25 24 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 RTCCMD R/W/L 0 9 CVDMD R/W/L 0 8 ADCSARMD R/W/L 0 5 4 3 2 1 0 Access Reset Bit Access Reset 7 ADCMD R/W/L 0 6 ACMD R/W/L 0 Bit 29 QSPIMDQSPI Module Disable Value 1 0 Description Disables the QSPI module Enables the QSPI module Bit 16 RTCCMDRTCC Module Disable (Unused at top level, part of XDS controller SFR) Value 1 0 Description Disables the RTCC module Enables the RTCC module Bit 9 CVDMDShared CVD Module Disable bit Value 1 0 Description Disables the corresponding shared CVD module Enables the corresponding shared CVD module Bit 8 ADCSARMDShared ADC SAR Core Module Disable bit Value 1 0 Description Disables the shared ADC SAR Core module. Enables the shared ADC SAR Core module. Bit 7 ADCMDADC Controller Module Disable Value 1 0 Description Disables the ADC Controller module Enables the ADC Controller module Bit 6 ACMDAC Module Disable Value 1 Description Disables the AC module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 362 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) Value 0 Description Enables the AC module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 363 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) 19.5.2 PMD2 - Peripheral Module Disable 2 Register Name:

Offset:

Reset:

Property:

PMD2 0x00D0 0x00000000

Note:This register bits are only writable when CFGCON0.PMDLOCK = 0. Bit 31 REFO4MD Access Reset R/W/L 0 30 REFO3MD R/W/L 0 29 REFO2MD R/W/L 0 28 REFO1MD R/W/L 0 27 26 25 REFO6MD R/W/L 0 24 REFO5MD R/W/L 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 9 1 8 0 Access Reset Bit 31 REFO4MDReference (Clock) Out 4 Disable Value 1 0 Description Disables the Reference (clock) out 4 Enables the Reference (clock) out 4 Bit 30 REFO3MDReference (Clock) Out 3 Disable Value 1 0 Description Disables the Reference (clock) out 3 Enables the Reference (clock) out 3 Bit 29 REFO2MDReference (Clock) Out 2 Disable Value 1 0 Description Disables the Reference (clock) out 2 Enables the Reference (clock) out 2 Bit 28 REFO1MDReference (Clock) Out 1 Disable Value 1 0 Description Disables the Reference (clock) out 1 Enables the Reference (clock) out 1 Bit 25 REFO6MDReference (Clock) Out 6 Disable Value 1 0 Description Disables the Reference (clock) out 6 Enables the Reference (clock) out 6 Bit 24 REFO5MDReference (Clock) Out 5 Disable Value 1 Description Disables the Reference (clock) out 5 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 364 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) Value 0 Description Enables the Reference (clock) out 5 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 365 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) 19.5.3 PMD3 - Peripheral Module Disable 3 Register Name:

Offset:

Reset:

Property:

PMD3 0x00E0 0x00000000

Note:This register bits are only writable when CFGCON0.PMDLOCK = 0. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset 7 TC3MD R/W/L 0 14 TCC2MD R/W/L 0 6 TC2MD R/W/L 0 13 TCC1MD R/W/L 0 5 TC1MD R/W/L 0 12 TCC0MD R/W/L 0 4 TC0MD R/W/L 0 11 TC7MD R/W/L 0 3 DACMD R/W/L 0 10 TC6MD R/W/L 0 2 SER2MD R/W/L 0 9 TC5MD R/W/L 0 1 SER1MD R/W/L 0 8 TC4MD R/W/L 0 0 SER0MD R/W/L 0 Bit 14 TCC2MDTCC2 Module Disable Value 1 0 Description Disables the TCC2 module Enables the TCC2 module Bit 13 TCC1MDTCC1 Module Disable Value 1 0 Description Disables the TCC1 module Enables the TCC1 module Bit 12 TCC0MDTCC0 Module Disable Value 1 0 Description Disables the TCC0 module Enables the TCC0 module Bit 11 TC7MDTC7 Module Disable Value 1 0 Description Disables the TC7 module Enables the TC7 module Bit 10 TC6MDTC6 Module Disable Value 1 0 Description Disables the TC6 module Enables the TC6 module Bit 9 TC5MDTC5 Module Disable Description Disables the TC5 module Value 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 366 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Module Disable (PMD) Value 0 Description Enables the TC5 module Bit 8 TC4MDTC4 Module Disable Description Disables the TC4 module Enables the TC4 module Value 1 0 Bit 7 TC3MDTC3 Module Disable Description Disables the TC3 module Enables the TC3 module Value 1 0 Bit 6 TC2MDTC2 Module Disable Description Disables the TC2 module Enables the TC2 module Value 1 0 Bit 5 TC1MDTC1 Module Disable Description Disables the TC1 module Enables the TC1 module Value 1 0 Bit 4 TC0MDTC0 Module Disable Description Disables the TC0 module Enables the TC0 module Value 1 0 Bit 3 DACMDDAC Module Disable Value 1 0 Description Disables the DAC module Enables the DAC module Bit 2 SER2MDSERCOM 2 Module Disable Value 1 0 Description Disables the SERCOM 2 module Enables the SERCOM 2 module Bit 1 SER1MDSERCOM 1 Module Disable Value 1 0 Description Disables the SERCOM 1 module Enables the SERCOM 1 module Bit 0 SER0MDSERCOM 0 Module Disable Value 1 0 Description Disables the SERCOM 0 module Enables the SERCOM 0 module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 367 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20. Peripheral Access Controller (PAC) 20.1 Overview The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral registers within the device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access, enable protected access, access when clock synchronization or software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the slave bus level, when an access to a non-existing address is detected. Note:The modules attached to PB-Bridge-D bridge and wireless subsystem as well as RTCC, and DSCON are excluded from PAC. The protection mechanism described in System Configuration Registers (CFG) protects critical system registers. See System Configuration and Register Locking (CFG) from Related Links. Related Links 18. System Configuration and Register Locking (CFG) 20.2 Features Manages write protection access and reports access errors for the peripheral modules or bridges. Manages security attribution for the peripheral modules (SAML11_DEVICE_NAME) 20.3 Block Diagram Figure 20-1. PAC Block Diagram IRQ APB PAC INTFLAG PAC CONTROL Slave ERROR SLAVEs Peripheral ERROR BUSn WRITE CONTROL Peripheral ERROR BUS0 PERIPHERAL m PERIPHERAL 0 PERIPHERAL m WRITE CONTROL PERIPHERAL 0 20.4 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 20.4.1 IO Lines Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 368 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.4.2 Power Management The PAC can continue to operate in any Sleep modes (Idle, Standby Sleep) where the selected source clock is running. The PAC interrupts can be used to wake up the device from Sleep modes. The events can trigger other operations in the system without exiting sleep modes. 20.4.3 DMA Not applicable. 20.4.4 Interrupts The interrupt request line is connected to the Interrupt Controller (NVIC). Using the PAC interrupt requires the Interrupt Controller to be configured first. Table 20-1. Interrupt Lines Instances PAC 20.4.5 Events NVIC Line PACERR The events are connected to the Event System, which may need configuration. See Event System (EVSYS) from Related Links. Related Links 26. Event System (EVSYS) 20.4.6 Debug Operation When the CPU is halted in Debug mode, write protection of all peripherals is disabled and the PAC continues normal operation. 20.4.7 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following PAC registers:

Write Control (WRCTRL) register AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Note:PAC write protection does not apply to accesses through an external debugger. 20.5 Functional Description 20.5.1 Principle of Operation The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripherals protection can be set, cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the peripherals. In addition, slave bus errors can be also reported in the cases where reserved area is accessed by the application. 20.5.2 Basic Operation 20.5.2.1 Initialization, Enabling and Resetting The PAC is always enabled after reset. Only a hardware reset will reset the PAC module. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 369 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.5.2.2 Operations The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral Bridges, except the peripherals on PB-Bridge-D bus. If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all peripherals connected to the corresponding Peripheral Bridge n. See Peripheral Access Errors from Related Links. The PAC module also report the errors occurring at client bus level when an access to reserved area is detected. AHB Subordinate Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the corresponding client. See AHB Subordinate Bus Errors from Related Links. 20.5.2.3 Peripheral Access Errors The following events will generate a Peripheral Access Error:

Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected. Only the registers denoted as PAC Write-Protection in the modules datasheet can be protected. If a peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected and if a write access is attempted, data will not be written and peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will be set. Illegal access: Access to an unimplemented register within the module. Synchronized write error: For write-synchronized registers an error will be reported if the register is written while a synchronization is ongoing. When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set. 20.5.2.4 Write Access Protection Management Peripheral access control can be enabled or disabled by writing to the WRCTRL register. The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key value that defines the operation to be done on the control access bit. These operations can be clear protection, set protection and set and lock protection bit. The clear protection operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral. The set protection operation will set the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this peripheral. The set and lock protection operation will set the write access protection for the peripheral selected by WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access protection will only be cleared by a hardware reset. The peripheral access control status can be read from the corresponding STATUSn register. 20.5.2.5 Write Access Protection Management Errors Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGx.PAC bit corresponding to the module. PAC also offers an additional safety feature for correct program execution with an interrupt generated on double write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection operation is detected then the PAC returns an error, and similarly for a double clear protection operation. In addition, an error is generated when writing a set and lock protection to a write-protected peripheral or when a write access is done to a locked set protection. This can be used to ensure that the application follows the intended program flow by always following a write protect with an unprotect and conversely. However in applications where a write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulates the write protection status or when the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 370 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will set the INTFLAGx.PAC flag. 20.5.2.6 AHB Subordinate Bus Errors The PAC module reports errors occurring at the AHB Subordinate bus level. These errors are generated when an access is performed at an address where no subordinate (bridge or peripheral) is mapped . These errors are reported in the corresponding bits of the INTFLAGAHB register. 20.5.2.7 Generating Events The PAC module can also generate an event when any of the Interrupt Flag register bits is set. To enable the PAC event generation, the control bit EVCTRL.ERREO must be set to 1. 20.5.3 DMA Operation Not applicable. 20.5.4 Interrupts The PAC has the following interrupt source:

Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC This interrupt is a synchronous wake-up source Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear

(INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. 20.5.5 Events The PAC can generate the following output event:

Error (ERR): Generated when one of the interrupt flag registers bits is set Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding output event. Writing a '0' to this bit disables the corresponding output event. 20.5.6 Sleep Mode Operation In Sleep mode, the PAC is kept enabled if an available bus master (CPU, DMA) is running. The PAC will continue to catch access errors from the module and generate interrupts or events. 20.5.7 Synchronization Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 371 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.6 Register Summary See PAC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 PERID[7:0]

PERID[15:8]

KEY[7:0]

0x00 WRCTRL 0x04 0x05

... 0x07 0x08 0x09 0x0A

... 0x0F EVCTRL Reserved INTENCLR INTENSET 7:0 7:0 Reserved ERREO ERR ERR 0x10 INTFLAGAHB 0x14 INTFLAGA 0x18 INTFLAGB 0x1C INTFLAGC 0x20

... 0x33 Reserved 0x34 STATUSA 0x38 STATUSB 0x3C STATUSC 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 PB-B PB-A PFLASH CFLASH SRAM3 CRYPTO BOOTROM SRAM2 QSPI SRAM1 PB-D SRAM0 PB-C TC2 TCC2 TC1 TCC1 TC0 TCC0 SERCOM1 SERCOM0 TC7 TC6 EIC TC5 FREQM TC4 RAMECC EVSYS DMAC PAC TC3 DSU AC CCL SERCOM2 QSPI HMTX TC2 TCC2 TC1 TCC1 TC0 TCC0 SERCOM1 SERCOM0 TC7 TC6 EIC TC5 FREQM TC4 RAMECC EVSYS DMAC PAC TC3 DSU AC CCL SERCOM2 QSPI HMTX Related Links 7. Product Memory Mapping Overview 20.7 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 372 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. See Register Access Protection from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the "Enable-Protected" property in each individual register description. Related Links 20.4.7. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 373 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.1 Write Control Name:

Offset:

Reset:

Property:

WRCTRL 0x00 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset RW 0 Bit 15 Access Reset RW 0 Bit 7 Access Reset RW 0 22 RW 0 14 RW 0 6 RW 0 21 RW 0 13 RW 0 5 RW 0 KEY[7:0]

PERID[15:8]

PERID[7:0]

20 RW 0 12 RW 0 4 RW 0 19 RW 0 11 RW 0 3 RW 0 18 RW 0 10 RW 0 2 RW 0 17 RW 0 9 RW 0 1 RW 0 16 RW 0 8 RW 0 0 RW 0 Bits 23:16 KEY[7:0]Peripheral Access Control Key These bits define the peripheral access control key:

Value 0x0 0x1 0x2 0x3 Description No action Clear the peripheral write control Set the peripheral write control Set and lock the peripheral write control until the next hardware reset Name OFF CLEAR SET LOCK Bits 15:0 PERID[15:0]Peripheral Identifier The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is calculated following formula:

Where, BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge PERID = 32* BridgeNumber + N B, etc). N represents the peripheral index from the respective Bridge Number. For example, PAC peripheral belongs to Peripheral Bridge A at the 0 bit position (see INTFLAGA from Related Links). Therefore, PERID = 32*0+0 = 0 for PAC peripheral. Table 20-2. PERID Values Periph. Bridge Name BridgeNumber PERID Values A B C Related Links 20.7.6. INTFLAGA 0 1 2 0+N 32+N 64+N 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 374 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.2 Event Control Name:

Offset:

Reset:

Property:

EVCTRL 0x04 0x00

Bit 7 6 5 4 3 2 1 Access Reset 0 ERREO RW/-/RW 0 Bit 0 ERREOPeripheral Access Error Event Output This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:

Value 0 1 Description Peripheral Access Error Event Output is disabled. Peripheral Access Error Event Output is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 375 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.3 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x08 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 Access Reset 0 ERR RW 0 Bit 0 ERRPeripheral Access Error Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request. Value 0 1 Description Peripheral Access Error interrupt is disabled. Peripheral Access Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 376 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.4 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x09 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 2 1 Access Reset Bit 0 ERRPeripheral Access Error Interrupt Enable 0 ERR RW 0 This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:

Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request. Value 0 1 Description Peripheral Access Error interrupt is disabled. Peripheral Access Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 377 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.5 Bridge Interrupt Flag Status Name:

Offset:

Reset:

Property:

INTFLAGAHB 0x10 0x00000000

These flags are cleared by writing a 1 to the corresponding bit. These flags are set when an access error is detected by the corresponding AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 Access Reset Bit Access Reset 7 PB-B RW 0 6 PB-A RW 0 5 PFLASH RW 0 12 CRYPTO RW 0 4 CFLASH RW 0 11 BOOTROM RW 0 3 SRAM3 RW 0 10 QSPI RW 0 2 SRAM2 RW 0 9 PB-D RW 0 1 SRAM1 RW 0 8 PB-C RW 0 0 SRAM0 RW 0 Bit 12 CRYPTOInterrupt Flag for Crypto This flag is set when an access error is detected by the Crypto AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the crypto interrupt flag. Bit 11 BOOTROMInterrupt Flag for Boot ROM This flag is set when an access error is detected by the Boot ROM Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the Boot ROM interrupt flag. Bit 10 QSPIInterrupt Flag for QSPI This flag is set when an access error is detected by the QSPI AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the QSPI interrupt flag. Bit 9 PB-DInterrupt Flag for PB-Bridge-D This flag is set when an access error is detected by the PB-D AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the PB-D interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 378 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Bit 8 PB-CInterrupt Flag for PB-C (PB-Bridge-C) This flag is set when an access error is detected by the PB-C Bridge AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the PB-C interrupt flag. Bit 7 PB-BInterrupt Flag for PB-B (PB-Bridge-B) This flag is set when an access error is detected by the PB-B Bridge AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the PB-B interrupt flag. Bit 6 PB-AInterrupt Flag for PB-A (PB-Bridge-A) This flag is set when an access error is detected by the PB-A Bridge AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the PB-A interrupt flag. Bit 5 PFLASHInterrupt Flag for PFLASH (Peripheral Flash) This flag is set when an access error is detected by the PFLASH AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the PFLASH interrupt flag. Bit 4 CFLASHInterrupt Flag for CFLASH (CPU Flash) This flag is set when an access error is detected by the CFLASH AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the CFLASH interrupt flag. Bit 3 SRAM3Interrupt Flag for SRAM3 This flag is set when an access error is detected by the SRAM3 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the SRAM3 interrupt flag. Bit 2 SRAM2Interrupt Flag for SRAM2 This flag is set when an access error is detected by the SRAM2 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the SRAM2 interrupt flag. Bit 1 SRAM1Interrupt Flag for SRAM1 This flag is set when an access error is detected by the SRAM1 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the SRAM1 interrupt flag. Bit 0 SRAM0Interrupt Flag for SRAM0 This flag is set when an access error is detected by the SRAM0 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 has no effect. Writing a 1 to this bit will clear the SRAM0 interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 379 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.6 Peripheral Interrupt Flag Status - Bridge A Name:

Offset:

Reset:

Property:

INTFLAGA 0x14 0x00000000 These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to these bits has no effect. Writing a 1 to these bits will clear the corresponding INTFLAGx interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset Bit Access Reset 15 TCC2 RW 0 7 TC2 RW 0 14 TCC1 RW 0 6 TC1 RW 0 13 TCC0 RW 0 5 TC0 RW 0 12 TC7 RW 0 11 TC6 RW 0 4 SERCOM1 RW 0 3 SERCOM0 RW 0 10 TC5 RW 0 2 EIC RW 0 9 TC4 RW 0 1 FREQM RW 0 8 TC3 RW 0 0 PAC RW 0 Bit 15 TCC2Interrupt Flag for TCC2 This bit is set when a Peripheral Access Error occurs while accessing the TCC2, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 14 TCC1Interrupt Flag for TCC1 This bit is set when a Peripheral Access Error occurs while accessing the TCC1, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 13 TCC0Interrupt Flag for TCC0 This bit is set when a Peripheral Access Error occurs while accessing the TCC0, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 12 TC7Interrupt Flag for TC7 This bit is set when a Peripheral Access Error occurs while accessing the TC7, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 380 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Bit 11 TC6Interrupt Flag for TC6 This bit is set when a Peripheral Access Error occurs while accessing the TC6, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 10 TC5Interrupt Flag for TC5 This bit is set when a Peripheral Access Error occurs while accessing the TC5, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 9 TC4Interrupt Flag for TC4 This bit is set when a Peripheral Access Error occurs while accessing the TC4, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 8 TC3Interrupt Flag for TC3 This bit is set when a Peripheral Access Error occurs while accessing the TC3, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 7 TC2Interrupt Flag for TC2 This bit is set when a Peripheral Access Error occurs while accessing the TC2, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 6 TC1Interrupt Flag for TC1 This bit is set when a Peripheral Access Error occurs while accessing the TC1, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 5 TC0Interrupt Flag for TC0 This bit is set when a Peripheral Access Error occurs while accessing the TC0, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 4 SERCOM1Interrupt Flag for SERCOM1 This bit is set when a Peripheral Access Error occurs while accessing the SERCOM1, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 3 SERCOM0Interrupt Flag for SERCOM0 This bit is set when a Peripheral Access Error occurs while accessing the SERCOM0, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 381 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Bit 2 EICInterrupt Flag for EIC This bit is set when a Peripheral Access Error occurs while accessing the EIC, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 1 FREQMInterrupt Flag for FREQM This bit is set when a Peripheral Access Error occurs while accessing the FREQM, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. Bit 0 PACInterrupt Flag for PAC This bit is set when a Peripheral Access Error occurs while accessing the PAC, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 382 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.7 Peripheral Interrupt Flag Status Bridge B Name:

Offset:

Reset:

Property:

INTFLAGB 0x18 0x00000000 These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to these bits has no effect. Writing a 1 to these bits will clear the corresponding INTFLAGx interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 Access Reset 4 RAMECC RW 0 3 EVSYS RW 0 2 DMAC RW 0 9 1 8 0 DSU RW 0 Bit 4 RAMECCInterrupt Flag for RAMECC This flag is set when a Peripheral Access Error occurs while accessing the RAMECC, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the RAMECC interrupt flag. Bit 3 EVSYSInterrupt Flag for EVSYS This flag is set when a Peripheral Access Error occurs while accessing the EVSYS, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the EVSYS interrupt flag. Bit 2 DMACInterrupt Flag for DMAC This flag is set when a Peripheral Access Error occurs while accessing the DMAC, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the DMAC interrupt flag. Bit 0 DSUInterrupt Flag for DSU This flag is set when a Peripheral Access Error occurs while accessing the DSU, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the DSU interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 383 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.8 Peripheral Interrupt Flag Status - Bridge C Name:

Offset:

Reset:

Property:

INTFLAGC 0x1C 0x00000000 These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to these bits has no effect. Writing a 1 to these bits will clear the corresponding INTFLAGx interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 AC RW 0 6 CCL RW 0 5 4 3 2 9 HMTX RW 0 1 SERCOM2 RW 0 8 0 QSPI RW 0 Bit 9 HMTXHMATRIX APB Protection Enable This flags is set when a Peripheral Access Error occurs while accessing the HMATRIX, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the HMATRIX interrupt flag. Bit 7 ACInterrupt Flag for AC This flags is set when a Peripheral Access Error occurs while the AC, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the AC interrupt flag. Bit 6 CCLInterrupt Flag for CCL This flags is set when a Peripheral Access Error occurs while accessing the CCL, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the CCL interrupt flag. Bit 1 SERCOM2Interrupt Flag for SERCOM2 This flags is set when a Peripheral Access Error occurs while accessing the SERCOM2, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the SERCOM2 interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 384 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Bit 0 QSPIInterrupt Flag for QSPI This flags is set when a Peripheral Access Error occurs while accessing the QSPI, and will generate an interrupt request if INTENCLR/SET.ERR is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the QSPI interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 385 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.9 Peripheral Write Protection Status A Name:

Offset:

Reset:

Property: PAC Write-Protection STATUSA 0x34 0x00000000 Writing to this register has no effect. Reading STATUS register returns peripheral write protection status:

Value Description 0 1 Peripheral is not write protected. Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset Bit Access Reset 15 TCC2 R 0 7 TC2 R 0 14 TCC1 R 0 6 TC1 R 0 13 TCC0 R 0 5 TC0 R 0 12 TC7 R 0 11 TC6 R 0 4 SERCOM1 R 0 3 SERCOM0 R 0 10 TC5 R 0 2 EIC R 0 9 TC4 R 0 1 FREQM R 0 8 TC3 R 0 0 PAC R 0 Bit 15 TCC2TCC2 APB Protect Enable Value 0 1 Description TCC2 peripheral is not write protected TCC2 peripheral is write protected Bit 14 TCC1TCC1 APB Protect Enable Value 0 1 Description TCC1 peripheral is not write protected TCC1 peripheral is write protected Bit 13 TCC0TCC0 APB Protect Enable Value 0 1 Description TCC0 peripheral is not write protected TCC0 peripheral is write protected Bit 12 TC7TC7 APB Protect Enable Value 0 1 Description TC7 peripheral is not write protected TC7 peripheral is write protected Bit 11 TC6TC6 APB Protect Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 386 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Value 0 1 Description TC6 peripheral is not write protected TC6 peripheral is write protected Bit 10 TC5TC5 APB Protect Enable Value 0 1 Description TC5 peripheral is not write protected TC5 peripheral is write protected Bit 9 TC4TC4 APB Protect Enable Value 0 1 Description TC4 peripheral is not write protected TC4 peripheral is write protected Bit 8 TC3TC3 APB Protect Enable Value 0 1 Description TC3 peripheral is not write protected TC3 peripheral is write protected Bit 7 TC2TC2 APB Protect Enable Value 0 1 Description TC2 peripheral is not write protected TC2 peripheral is write protected Bit 6 TC1TC1 APB Protect Enable Value 0 1 Description TC1 peripheral is not write protected TC1 peripheral is write protected Bit 5 TC0TC0 APB Protect Enable Value 0 1 Description TC0 peripheral is not write protected TC0 peripheral is write protected Bit 4 SERCOM1SERCOM1 APB Protect Enable Value 0 1 Description SERCOM1 peripheral is not write protected SERCOM1 peripheral is write protected Bit 3 SERCOM0SERCOM0 APB Protect Enable Value 0 1 Description SERCOM0 peripheral is not write protected SERCOM0 peripheral is write protected Bit 2 EICEIC APB Protect Enable Description EIC peripheral is not write protected EIC peripheral is write protected Value 0 1 Bit 1 FREQMFREQM APB Protect Enable Value 0 1 Description FREQM peripheral is not write protected FREQM peripheral is write protected Bit 0 PACPAC APB Protect Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 387 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Value 0 1 Description PAC peripheral is not write protected PAC peripheral is write protected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 388 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.10 Peripheral Write Protection Status - Bridge B Name:

Offset:

Reset:

Property: PAC Write-Protection STATUSB 0x38 0x00000000 Writing to this register has no effect. Reading STATUS register returns peripheral write protection status:

Value Description 0 1 Peripheral is not write protected. Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 Access Reset 4 RAMECC R 0 3 EVSYS R 0 2 DMAC R 0 9 1 8 0 DSU R 0 Bit 4 RAMECCRAMECC APB Protect Enable Value 0 1 Description RAMECC peripheral is not write protected RAMECC peripheral is write protected Bit 3 EVSYSEVSYS APB Protect Enable Value 0 1 Description EVSYS peripheral is not write protected EVSYS peripheral is write protected Bit 2 DMACDMAC APB Protect Enable Value 0 1 Description DMAC peripheral is not write protected DMAC peripheral is write protected Bit 0 DSUDSU APB Protect Enable Value 0 1 Description DSU peripheral is not write protected DSU peripheral is write protected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 389 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) 20.7.11 Peripheral Write Protection Status - Bridge C Name:

Offset:

Reset:

Property: PAC Write-Protection STATUSC 0x3C 0x00000000 Writing to this register has no effect. Reading STATUS register returns peripheral write protection status:

Value Description 0 1 Peripheral is not write protected. Peripheral is write protected. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 AC R 0 6 CCL R 0 5 4 3 2 9 HMTX R 0 1 SERCOM2 R 0 8 0 QSPI R 0 Bit 9 HMTXHMATRIX APB Protection Enable Value 0 1 Description HMATRIX APB is not write protected HMATRIX APB is write protected Bit 7 ACAC APB Protection Enable Value 0 1 Description AC peripheral is not write protected AC peripheral is write protected Bit 6 CCLCCL APB Protection Enable Value 0 1 Description CCL peripheral is not write protected CCL peripheral is write protected Bit 1 SERCOM2SERCOM2 APB Protection Enable Value 0 1 Description SERCOM2 peripheral is not write protected SERCOM2 peripheral is write protected Bit 0 QSPIQSPI APB Protection Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 390 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Peripheral Access Controller (PAC) Value 0 1 Description QSPI peripheral is not write protected QSPI peripheral is write protected 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 391 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21. Real-Time Counter and Calendar (RTCC) 21.1 Overview The Real-Time Counter (RTCC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTCC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake up, or overflow wake up mechanisms, or from the wake inputs. The RTCC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and overflow event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5s, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more than 136 years. 21.2 Features 32-bit counter with 10-bit prescaler Multiple clock sources 32-bit or 16-bit counter mode Two 32-bit or four 16-bit compare values Clock/Calendar mode Time in seconds, minutes, and hours (12/24) Date in day of month, month, and year Leap year correction Digital prescaler correction/tuning for increased accuracy Overflow, alarm/compare match and prescaler interrupts and events Optional clear on alarm/compare match 4 general purpose registers 1 backup register with retention capability Tamper Detection Timestamp on event or up to 4 inputs with debouncing Active layer protection 21.3 Block Diagram Figure 21-1. RTCC Block Diagram (Mode 0 32-Bit Counter) 0x00000000 MATCHCLR LPCLK_RTC CLK_RTC_OSC PRESCALER CLK_RTC_CNT COUNT OVF Periodic Events

CMPn COMPn 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 392 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Figure 21-2. RTCC Block Diagram (Mode 1 16-Bit Counter) Figure 21-3. RTCC Block Diagram (Mode 2 Clock/Calendar) Figure 21-4. RTCC Block Diagram (Tamper Detection) 21.4 Signal Description Table 21-1. Signal Description Signal INn [n=0..3]

OUT Description Tamper detection input Tamper detection output Type Digital input Digital output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 393 Microchip Confidential CLK_RTC_OSCCLK_RTC_CNTLPCLK_RTCPRESCALERCOMPnPERCOUNT0x0000Periodic Events==CMPnOVF CLK_RTC_CNTCLK_RTC_OSCLPCLK_RTCPRESCALERPeriodic EventsMASKnCLOCKALARMn=0x00000000OVFMATCHCLRALARMn=PRESCALERDEBOUNCEDEBOUNCEDEBOUNCETIMESTAMPCAPTUREINnIN1IN0OUTTamper Input [0..3]PCB Active LayerProtectionTAMPEVTTAMPERALARMFREQCORRCLOCKConfidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC)

...........continued Signal RTC_EVENT Description RTC event output Type Digital output 21.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 21.5.1 I/O Lines In order to use the I/O lines of this peripheral, the RTC must be enabled and no higher priority peripherals for the RTC pins can be enabled. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 21.5.2 Power Management The RTC will continue to operate in any sleep modes (Standby Sleep, Deep Sleep, Idle) where the selected source clock is running. The RTC interrupts can be used to wake-up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. See Power Management Unit

(PMU) from Related Links for details on the different sleep modes. The RTCC can only be reset by a power on reset (POR) or by setting the Software Reset bit in the Control A register

(CTRLA.SWRST = 1). 21.5.3 Clocks A 32 KHz or 1 KHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. The 32 KHz clock source can be FRC, POSC, SOSC or LPRC based on the mux selection controlled by the CFGCON4.VBKP_32KCSEL bit. The 1 KHz clock source is based on the mux selection controlled by the CFGCON4.VBKP_1KCSEL bit. This oscillator clock is asynchronous to the bus clock (PB3_CLK). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. 21.5.4 DMA The DMA request lines (or line if only one request) are connected to the DMA Controller (DMAC). Using the RTC DMA requests requires the DMA Controller to be configured first. See Direct Memory Access Controller (DMAC) from Related Links. Related Links 22. Direct Memory Access Controller (DMAC) 21.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the Interrupt Controller to be configured first. 21.5.6 Events The events are connected to the Event System. See Event System (EVSYS) from Related Links. Related Links 26. Event System (EVSYS) 21.5.7 Debug Operation When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation during debugging. See DBGCTRL from Related Links. Related Links 21.8.7. DBGCTRL 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 394 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the Interrupt Flag Status and Clear (INTFLAG) register. Write-protection is denoted by the "PAC Write-Protection"

property in the register description. Write-protection does not apply to accesses through an external debugger. See Peripheral Access Controller (PAC) from Related Links. Related Links 20. Peripheral Access Controller (PAC) 21.6 Functional Description 21.6.1 Principle of Operation The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. The RTC can function in one of these modes:

Mode 0 - COUNT32: RTC serves as 32-bit counter Mode 1 - COUNT16: RTC serves as 16-bit counter Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality 21.6.2 Basic Operation 21.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the RTC is disabled

(CTRLA.ENABLE = 0):

Operating Mode bits in the Control A register (CTRLA.MODE) Prescaler bits in the Control A register (CTRLA.PRESCALER) Clear on Match bit in the Control A register (CTRLA.MATCHCLR) Clock Representation bit in the Control A register (CTRLA.CLKREP) BKUP registers Reset On Tamper bit in Control A register (CTRLA.BKTRST) GP registers Reset On Tamper Enable in Control A register (CTRLA.GPTRST) The following registers are enable-protected:

Control B register (CTRLB) Event Control register (EVCTRL) Tamper Control register (TAMPCTRL) Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE = 0). If the RTC is enabled (CTRLA.ENABLE = 1), these operations are necessary: first write CTRLA.ENABLE = 0 and check whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in CTRLA register can be written at the same time as CTRLA.ENABLE is written to 1, but not at the same time as CTRLA.ENABLE is written to 0. Enable-protection is denoted by the Enable-Protectedproperty in the register description. The RTC prescaler divides the source clock for the RTC counter. Note:In Clock/Calendar mode, the prescaler must be configured to provide a 1 Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:

fCLK_RTC_CNT =

The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT. 2 fCLK_RTC_OSC PRESCALER 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 395 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.6.2.2 Enabling, Disabling, and Resetting The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is disabled by writing CTRLA.ENABLE=0. The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before resetting it. 21.6.2.3 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates in 32-bit Counter mode. See RTC Block Diagram (Mode 0 32-Bit Counter) figure in the Block Diagram from Related Links. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare registers (COMPn, n=01). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMPn occurs. This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMPn and INTFLAG.OVF will both be set simultaneously on a compare match with COMPn. Related Links 21.3. Block Diagram 21.6.2.4 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates in 16-bit Counter mode. See RTC Block Diagram (Mode 1 16-Bit Counter) figure in the Block Diagram from Related Links. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..) is set on the next 0-to-1 transition of CLK_RTC_CNT. Related Links 21.3. Block Diagram 21.6.2.5 Clock/Calendar (Mode 2) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates in Clock/Calendar mode. See RTC Block Diagram (Mode 2 Clock/Calendar) figure in the Block Diagram from Related Links. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as:

Seconds Minutes Hours Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled. The date is represented in this form:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 396 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Day as the numeric day of the month (starting at 1) Month as the numeric month of the year (1 = January, 2 = February, etc.) Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020 etc). Example: the year value 0x2D, added to a reference year 2016, represents the year 2061. The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). The clock value is continuously compared with the 32-bit Alarm registers (ALARMn, n=01). When an alarm match occurs, the Alarm n Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm n Mask register

(MASKn.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next counter cycle when an alarm match with ALARMn occurs. This allows the RTC to generate periodic interrupts or events with longer periods than it would be possible with the prescaler events only (see Periodic Intervals from Related Links). Note:When CTRLA.MATCHCLR is 1, INTFLAG.ALARMn and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARMn. Related Links 21.3. Block Diagram 21.6.8.1. Periodic Intervals 21.6.3 DMA Operation The RTC generates the following DMA request:

Tamper (TAMPER): The request is set on capture of the timestamp. The request is cleared when the Timestamp register is read. If the CPU accesses the registers which are source for DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted, if enabled. 21.6.4 Interrupts The RTC has the following interrupt sources:

Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero. Tamper (TAMPER): Indicates detection of valid signal on a tamper input pin or tamper event input. Compare (CMPn): Indicates a match between the counter value and the compare register. Alarm (ALARMn): Indicates a match between the clock value and the alarm register. Period n (PERn): The corresponding bit in the prescaler has toggled, see Periodic Intervals from Related Links. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear

(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC, see Nested Vector Interrupt Controller (NVIC) from Related Links. The user must read the INTFLAG register to determine which interrupt condition is present. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 397 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Note:Interrupts must be globally enabled for interrupt requests to be generated, see Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 21.6.8.1. Periodic Intervals 21.6.5 Events The RTC can generate the following output events and can be used by the EVSYS module:

Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero. Tamper (TAMPER): Generated on detection of valid signal on a tamper input pin or tamper event input. Compare (CMPn): Indicates a match between the counter value and the compare register. Alarm (ALARMn): Indicates a match between the clock value and the alarm register. Period n (PERn): The corresponding bit in the prescaler has toggled, see Periodic Intervals from Related Links. Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of time. RTC Event (RTC_EVENT): Generates specific external signal on the RTC EVENT I/O pin. Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO = 1) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. See Event System (EVSYS) from Related Links for more details on configuring the event system. The RTC can take the following actions on an input event:

Tamper (TAMPEVT): Capture the RTC counter to the timestamp register. See Tamper Detection from Related Links. Writing a one to an Event Input bit into the Event Control register (EVCTRL.xxxEI) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. RTC Event (RTC_EVENT): Other than the above events, which are mapped to the EVSYS module, the following events can generate specific external signal on the RTC EVENT I/O pin. 32 KHz clock Alarm pulse 1-second clock These event signals are configured using CFGCON4.RTCEVENTSEL[1:0] bits. Note:The RTC_OUT and RTC_EVENT signals are multiplexed and any one of the signal can be out at a time in pin limited variants. The selection between RTC_OUT and RTC_EVENT is configurable through CFGCON4.RTCEVTYPE bit. Related Links 21.6.8.5. Tamper Detection 21.6.8.1. Periodic Intervals 26. Event System (EVSYS) 21.6.6 Sleep Mode Operation The RTC will continue to operate in any sleep modes (Standby Sleep, Deep Sleep) where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the NVIC Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU continues executing right from the first instruction that followed the entry into sleep. The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event System (EVSYS) from Related Links. Related Links 26. Event System (EVSYS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 398 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in Control A register, CTRLA.SWRST Enable bit in Control A register, CTRLA.ENABLE Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC) Clock Read Synchronization bit in Control A register (CTRLA.COUNTSYNC) The following registers are synchronized when written:

Counter Value register, COUNT Clock Value register, CLOCK Counter Period register, PER Compare n Value registers, COMPn Alarm n Value registers, ALARMn Frequency Correction register, FREQCORR Alarm n Mask register, MASKn The General Purpose n registers (GPn) The following registers are synchronized when read:

The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is

'1'

The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1'

The Timestamp Value register (TIMESTAMP) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. 21.6.8 Additional Features 21.6.8.1 Periodic Intervals The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of:

fCLK_RTC_OSC n+3 fPERIODIC(n) =

fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. 2 Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRLA.PRESCALER is zero. Then, no periodic events will be generated. Figure 21-5. Example Periodic Events Note:This example also applies to interrupts. Just replace EVCTRL.PEREOn with the PERn fields of INTENCLR, INTENSET, and INTFLAG. For Modes 0 and 2, n = 0,..7. For Mode 1 n = 2...7. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 399 Microchip Confidential CLK_RTC_OSCPER0PER1PER2PER3Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.6.8.2 Frequency Correction The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 8192 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 128 of these periods. The resulting correction is as follows:

Correction in ppm =

This results in a resolution of 0.95367ppm. 10 FREQCORR.VALUE 8192 128 6 ppm The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value. 21.6.8.3 Backup Registers The RTC includes one Backup register (BKUP0). This register maintain its content in the Deep Sleep mode. It can be used to store user-defined values. If more user-defined data must be stored than the Backup register can hold, the General Purpose registers (GPn) can be used. 21.6.8.4 General Purpose Registers The RTC includes four General Purpose registers (GPn). These registers are reset only when the RTC is reset or when tamper detection occurs while CTRLA.GPTRST=1, and remain powered while the RTC is powered. They can be used to store user-defined values while other parts of the system are powered off. The general purpose registers 2*n and 2*n+1 are enabled by writing a 1 to the General Purpose Enable bit n in the Control B register (CTRLB.GPnEN). The GP registers share internal resources with the COMPARE/ALARM features. Each COMPARE/ALARM register have a separate read buffer and write buffer. When the general purpose feature is enabled the even GP uses the read buffer while the odd GP uses the write buffer. When the COMPARE/ALARM register is written, the write buffer hold temporarily the COMPARE/ALARM value until the synchronisation is complete (bit SYNCBUSY.COMPn going to 0). After the write is completed the write buffer can be used as a odd general purpose register without affecting the COMPARE/ALARM function. If the COMPARE/ALARM function is not used, the read buffer can be used as an even general purpose register. In this case, writing the even GP will temporarily use the write buffer until the synchronisation is complete (bit SYNCBUSY.GPn going to 0). Thus an even GP must be written before writing the odd GP. Changing or writing an even GP needs to temporarily save the value of the odd GP. Before using an even GP, the associated COMPARE/ALARM feature must be disabled by writing a 1 to the General Purpose Enable bit in the Control B register (CTRLB.GPnEN). To re-enable the compare/alarm, CTRLB.GPnEN must be written to zero and the associated COMPn/ALARMn must be written with the correct value. It is recommended to use the Backup register (BKUPn) first to store user-defined values, and use the GPn only when the user-defined values exceed the capacity of the provided BKUPn. An example procedure to write the general purpose registers GP0 and GP1 is:

1. Wait for any ongoing write to COMP0 to complete (SYNCBUSY.COMP0 = 0). If the RTC is operating in Mode 1, wait for any ongoing write to COMP1 to complete as well (SYNCBUSY.COMP1 = 0). 2. Write CTRLB.GP0EN = 1 if GP0 is needed. 3. Write GP0 if needed. 4. Wait for any ongoing write to GP0 to complete (SYNCBUSY.GP0 = 0). Note that GP1 will also show as busy when GP0 is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 400 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 5. Write GP1 if needed. The following table provides the correspondence of General Purpose Registers and the COMPARE/ALARM read or write buffer in all RTC modes. Table 21-2. General Purpose Registers Versus Compare/Alarm Registers: n in 0, 2, 4, 6... Register GPn COMPn/2 write buffer Mode 0 Mode 1 Mode 2 Write Before GPn+1 COMPn/2 read buffer

(COMPn , COMPn+1) write buffer

(COMPn , COMPn+1) read buffer ALARMn/2 write buffer GPn+1 ALARMn/2 read buffer

21.6.8.5 Tamper Detection The RTC provides four tamper channels that can be used for tamper detection. The action of each tamper channel is configured using the Input n Action bits in the Tamper Control register

(TAMPCTRL.INnACT):

Off: Detection for tamper channel n is disabled. Wake: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be captured in the TIMESTAMP register. Capture: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register. Active Layer Protection: A mismatch of an internal RTC signal routed between INn and OUTn pins will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register. In order to determine which tamper source caused a tamper event, the Tamper ID register (TAMPID) provides the detection status of each tamper channel. These bits remain active until cleared by software. A single interrupt request (TAMPER) is available for all tamper channels. The RTC also supports an input event (TAMPEVT) for generating a tamper condition within the Event System. The tamper input event is enabled by the Tamper Input Event Enable bit in the Event Control register

(EVCTRL.TAMPEVTEI). Up to four polarity external inputs (INn) can be used for tamper detection. The polarity for each input is selected with the Tamper Level bits in the Tamper Control register (TAMPCTRL.TAMPLVLn). Separate debouncers are embedded for each external input. The debouncer for each input is enabled/disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB). The debouncing period duration is configurable using the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer). When TAMPCTRL.DEBNCn = 0, INn is detected asynchronously. See the following figure for an example. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 401 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Figure 21-6. Edge Detection with Debouncer Disabled When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates synchronously or asynchronously, and whether majority detection is enabled or not. For more details, refer to the following table. Synchronous versus asynchronous stability debouncing is configured by the Debounce Asynchronous Enable bit in the Control B register (CTRLB.DEBASYNC):

Synchronous (CTRLB.DEBASYNC = 0): INn is synchronized in two CLK_RTC periods and then must remain stable for four CLK_RTC_DEB periods before a valid detection occurs. See the following figure for an example. Figure 21-7. Edge Detection with Synchronous Stability Debouncing Asynchronous (CTRLB.DEBASYNC = 1): The first edge on INn is detected. Further detection is blanked until INn remains stable for four CLK_RTC_DEB periods. See the following figure for an example. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 402 Microchip Confidential CLK_RTCCLK_RTC_DEBINOUTNENEPETAMLVL=0CLK_RTCCLK_RTC_DEBINOUTNENEPETAMLVL=1PENEPEPENEPEOUTTAMLVL=0CLK_RTCCLK_RTC_DEBINOUTNENEPETAMLVL=1PENEPEWhenever an edge is detected, input must bestable for 4 consecutive CLK_RTC_DEB inorder for edge to be considered validCLK_RTCCLK_RTC_DEBINNENEPEPENEPEWhenever an edge is detected, input must bestable for 4 consecutive CLK_RTC_DEB inorder for edge to be considered validConfidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Figure 21-8. Edge Detection with Asynchronous Stability Debouncing Majority debouncing is configured by the Debounce Majority Enable bit in the Control B register (CTRLB.DEBMAJ). INn must be valid for two out of three CLK_RTC_DEB periods. See the following figure for an example. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 403 Microchip Confidential CLK_RTCCLK_RTC_DEBINOUTOnce a new edge is detected, ignore subsequent edgesuntil input is stable for 4 consecutive CLK_RTC_DEBNENEPETAMLVL=0CLK_RTCCLK_RTC_DEBINOUTOnce a new edge is detected, ignore subsequent edgesuntil input is stable for 4 consecutive CLK_RTC_DEBNENEPETAMLVL=1PENEPEPENEPEConfidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Figure 21-9. Edge Detection with Majority Debouncing Table 21-3. Debouncer Configuration TAMPCTRL. DEBNCn CTRLB. DEBMAJ CTRLB. DEBASYNC Description 0 1 1 1 X 0 0 1 X 0 1 X Detect edge on INn with no debouncing. Every edge detected is immediately triggered. Detect edge on INn with synchronous stability debouncing. Edge detected is only triggered when INn is stable for 4 consecutive CLK_RTC_DEB periods. Detect edge on INn with asynchronous stability debouncing. First detected edge is triggered immediately. All subsequent detected edges are ignored until INn is stable for 4 consecutive CLK_RTC_DEB periods. Detect edge on INn with majority debouncing. Pin INn is sampled for 3 consecutive CLK_RTC_DEB periods. Signal level is determined by majority-rule (LLL, LLH, LHL, HLL = '0'

and LHH, HLH, HHL, HHH = '1'). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 404 Microchip Confidential 100110111111011101110CLK_RTCCLK_RTC_DEBININ shift 0IN shift 1IN shift 2MAJORITY3OUTCLK_RTCCLK_RTC_DEBININ shift 0IN shift 1IN shift 2MAJORITY3OUT111011101010001000000000111000TAMLVL=1TAMLVL=00-to-1 transition1-to-0 transitionNENEPEPENEPE000111111100110111111011101110111011101010001000000000111000NENEPEPENEPE000111111Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.6.8.5.1 Timestamp As part of tamper detection the RTC can capture the counter value (COUNT/CLOCK) into the TIMESTAMP register. Three CLK_RTC periods are required to detect the tampering condition and capture the value. The TIMESTAMP value can be read once the Tamper flag in the Interrupt Flag register (INTFLAG.TAMPER) is set. If the DMA Enable bit in the Control B register (CTRLB.DMAEN) is 1, a DMA request will be triggered by the timestamp. In order to determine which tamper source caused a capture, the Tamper ID register (TAMPID) provides the detection status of each tamper channel and the tamper input event. A DMA transfer can then read both TIMESTAMP and TAMPID in succession. A new timestamp value cannot be captured until the Tamper flag is cleared, either by reading the timestamp or by writing a 1 to INTFLAG.TAMPER. If several tamper conditions occur in a short window before the flag is cleared, only the first timestamp may be logged. However, the detection of each tamper will still be recorded in TAMPID. The Tamper Input Event (TAMPEVT) will always perform a timestamp capture. To capture on the external inputs

(INn), the corresponding Input Action field in the Tamper Control register (TAMPCTRL.INnACT) must be written to 1. If an input is set for wake functionality it does not capture the timestamp; however the Tamper flag and TAMPID will still be updated. Note:The TIMESTAMP value should be read once, and INTFLAG.TAMPER must be cleared. The next value should be read only after the INTFLAG.TAMPER is set again. 21.6.8.5.2 Active Layer Protection The RTC provides a mean of detecting broken traces on the PCB, also known as Active layer Protection. In this mode, a generated internal RTC signal can be directly routed over critical components on the board using the RTC_OUT output pin to one RTC INn input pin. A tamper condition is detected if there is a mismatch on the generated RTC signal. The Active Layer Protection mode and the generation of the RTC signal is enabled by setting the RTCOUT bit in the Control B register (CTRLB.RTCOUT). Note:The Active Layer Protection works with one output pin (RTC_OUT) and multiple input pin INn. This is achieved by clearing the Separate Tamper Output bit CTRLB.SEPTO. Enabling active layer protection requires the following steps:

Enable the RTC prescaler output by writing a 1 to the RTC Out bit in the Control B register (CTRLB.RTCOUT). The I/O pins must also be configured to correctly route the signal to the external pins. Select the frequency of the output signal by configuring the RTC Active Layer Frequency field in the Control B register (CTRLB.ACTF). CLK_RTC CTRLB.ACTF +1 CLK_RTC_OUT =

Enable the tamper input n (INn) in Active Layer mode by writing 3 to the corresponding Input Action field in the Tamper Control register (TAMPCTRL.INnACT). When active layer protection is enabled and INn and OUTn pin are used, the value of INn is sampled on the falling edge of CLK_RTC and compared to the expected value of OUTn. Therefore up to one half of a CLK_RTC period is available for propagation delay through the trace. 2 Enable Active Layer Protection by setting CTRLB.RTCOUT bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 405 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.7 Register Summary - Mode 0 - 32-Bit Counter See RTCC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 MATCHCLR MODE[1:0]

ENABLE SWRST 0x00 CTRLA 0x02 CTRLB 0x04 EVCTRL 0x08 INTENCLR 0x0A INTENSET 0x0C 0x0E 0x0F INTFLAG DBGCTRL Reserved 0x10 SYNCBUSY 0x14 0x15

... 0x17 FREQCORR Reserved 0x18 COUNT 0x1C

... 0x1F Reserved 0x20 COMP0 0x24 COMP1 0x28

... 0x3F Reserved 0x40 GP0 0x44 GP1 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 15:8 23:16 31:24 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 COUNTSYN C GPTRST BKTRST PRESCALER[3:0]

DMAEN RTCOUT DEBASYNC DEBMAJ ACTF[2:0]

GP2EN GP0EN DEBF[2:0]

PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 OVFEO TAMPEREO PER7 OVF PER7 OVF PER7 OVF PER6 PER5 PER4 PER3 PER2 TAMPER PER6 PER5 PER4 PER3 PER2 TAMPER PER6 PER5 PER4 PER3 PER2 TAMPER CMPEOn[1:0]

TAMPEVEI PER1 CMP1 PER1 CMP1 PER1 CMP1 PER0 CMP0 PER0 CMP0 PER0 CMP0 DBGRUN COMP1 COMP0 COUNT FREQCORR ENABLE SWRST COUNTSYN C SIGN VALUE[6:0]

GP3 GP2 GP1 GP0 COUNT[7:0]

COUNT[15:8]

COUNT[23:16]

COUNT[31:24]

COMP[7:0]

COMP[15:8]

COMP[23:16]

COMP[31:24]

COMP[7:0]

COMP[15:8]

COMP[23:16]

COMP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 406 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x48 GP2 0x4C GP3 0x50

... 0x5F Reserved 0x60 TAMPCTRL 0x64 TIMESTAMP 0x68 TAMPID 0x6C

... 0x7F Reserved 0x80 BKUP0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

IN3ACT[0]

IN2ACT[1:0]

IN1ACT[1:0]

IN2ACT[1:0]

IN0ACT[1:0]

TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 DEBNC3 DEBNC2 DEBNC1 DEBNC0 IN3ACT[1]

COUNT[7:0]

COUNT[15:8]

COUNT[23:16]

COUNT[31:24]

TAMPID3 TAMPID2 TAMPID1 TAMPID0 TAMPEVT BKUP[7:0]

BKUP[15:8]

BKUP[23:16]

BKUP[31:24]

Related Links 7. Product Memory Mapping Overview 21.8 Register Description - Mode 0 - 32-Bit Counter This Register Description section is valid if the RTC is in COUNT32 mode (CTRLA.MODE=0). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 407 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.1 Control A in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property: Enable-Protected, Write-Synchronized CTRLA 0x00 0x0000 Bit 15 COUNTSYNC R/W 0 Access Reset 14 GPTRST R/W 0 13 BKTRST R/W 0 12 Bit 7 6 5 4 MATCHCLR Access Reset R/W 0 Bit 15 COUNTSYNCCOUNT Read Synchronization Enable 11 R/W 0 3 R/W 0 MODE[1:0]

10 9 PRESCALER[3:0]

R/W 0 2 R/W 0 R/W 0 1 ENABLE R/W 0 8 R/W 0 0 SWRST R/W 0 The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value 0 1 Description COUNT read synchronization is disabled COUNT read synchronization is enabled Bit 14 GPTRSTGP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bit 13 BKTRSTBKUP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description BKUPn registers will not reset when a tamper condition occurs. BKUPn registers will reset when a tamper condition occurs. Bits 11:8 PRESCALER[3:0]Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock

(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC-0xF Description CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/2 CLK_RTC_CNT = GCLK_RTC/4 CLK_RTC_CNT = GCLK_RTC/8 CLK_RTC_CNT = GCLK_RTC/16 CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 CLK_RTC_CNT = GCLK_RTC/1024 Reserved Name OFF DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 408 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Bit 7 MATCHCLRClear on Match This bit defines if the counter is cleared or not on a match. This bit is not synchronized. Value 0 1 Description The counter is not cleared on a Compare/Alarm match The counter is cleared on a Compare/Alarm match Bits 3:2 MODE[1:0]Operating Mode This bit group defines the operating mode of the RTC. This bit is not synchronized. Value 0x0 0x1 0x2 0x3 Name COUNT32 COUNT16 CLOCK

Description Mode 0: 32-bit counter Mode 1: 16-bit counter Mode 2: Clock/calendar Reserved Bit 1 ENABLEEnable Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value 0 1 Description The peripheral is disabled The peripheral is enabled Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay between writing CTRLA.SWRST and until the Reset is complete. CTRLA.SWRST will be cleared when the Reset is complete. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description There is no Reset operation ongoing The Reset operation is ongoing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 409 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.2 Control B in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property: Enable-Protected CTRLB 0x02 0x0000 Bit 15 14 R/W 0 13 ACTF[2:0]

R/W 0 12 R/W 0 7 DMAEN R/W 0 6 RTCOUT R/W 0 5 DEBASYNC R/W 0 4 DEBMAJ R/W 0 Access Reset Bit Access Reset 11 3 10 R/W 0 2 9 DEBF[2:0]

R/W 0 1 GP2EN R/W 0 8 R/W 0 0 GP0EN R/W 0 Bits 14:12 ACTF[2:0]Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_OUT = CLK_RTC / 2 CLK_RTC_OUT = CLK_RTC / 4 CLK_RTC_OUT = CLK_RTC / 8 CLK_RTC_OUT = CLK_RTC / 16 CLK_RTC_OUT = CLK_RTC / 32 CLK_RTC_OUT = CLK_RTC / 64 CLK_RTC_OUT = CLK_RTC / 128 CLK_RTC_OUT = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bits 10:8 DEBF[2:0]Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_DEB = CLK_RTC / 2 CLK_RTC_DEB = CLK_RTC / 4 CLK_RTC_DEB = CLK_RTC / 8 CLK_RTC_DEB = CLK_RTC / 16 CLK_RTC_DEB = CLK_RTC / 32 CLK_RTC_DEB = CLK_RTC / 64 CLK_RTC_DEB = CLK_RTC / 128 CLK_RTC_DEB = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bit 7 DMAENDMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value 0 1 Description Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 RTCOUTRTC Output Enable Value 0 1 Description The RTC active layer output is disabled. The RTC active layer output is enabled. Bit 5 DEBASYNCDebouncer Asynchronous Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 410 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0 1 Description The tamper input debouncers operate synchronously. The tamper input debouncers operate asynchronously. Bit 4 DEBMAJDebouncer Majority Enable Value 0 1 Description The tamper input debouncers match three equal values. The tamper input debouncers match majority two of three values. Bit 1 GP2ENGeneral Purpose 2 Enable Value 0 1 Description COMP1 compare function enabled. GP2/GP3 disabled. COMP1 compare function disabled. GP2/GP3 enabled. Bit 0 GP0ENGeneral Purpose 0 Enable Value 0 1 Description COMP0 compare function enabled. GP0/GP1 disabled. COMP0 compare function disabled. GP0/GP1 enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 411 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.3 Event Control in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property: Enable-Protected EVCTRL 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 TAMPEVEI R/W 0 CMPEOn[1:0]

R/W 0 1 PEREO1 R/W 0 R/W 0 0 PEREO0 R/W 0 Access Reset Bit Access Reset Bit Access Reset 15 OVFEO R/W 0 7 PEREO7 R/W 0 14 TAMPEREO R/W 0 13 12 11 10 9 8 6 PEREO6 R/W 0 5 PEREO5 R/W 0 4 PEREO4 R/W 0 3 PEREO3 R/W 0 2 PEREO2 R/W 0 Bit 16 TAMPEVEITamper Event Input Enable Value 0 1 Description Tamper event input is disabled and incoming events will be ignored. Tamper event input is enabled and incoming events will capture the COUNT value. Bit 15 OVFEOOverflow Event Output Enable Value 0 1 Description Overflow event is disabled and will not be generated. Overflow event is enabled and will be generated for every overflow. Bit 14 TAMPEREOTamper Event Output Enable Value 0 1 Description Tamper event output is disabled and will not be generated. Tamper event output is enabled and will be generated for every tamper input. Bits 9:8 CMPEOn[1:0]Compare n Event Output Enable [n = 1..0]

Value 0 1 Description Compare n event is disabled and will not be generated. Compare n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 PEREOnPeriodic Interval n Event Output Enable [n = 7..0]

Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 412 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.4 Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property:

INTENCLR 0x08 0x0000

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow Interrupt Enable 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this but will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value 0 1 Description The Tamper interrupt is disabled. The Tamper interrupt is enabled. Bits 8, 9 CMPnCompare n Interrupt Enable [n = 1..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt. Value 0 1 Description The Compare n interrupt is disabled The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value 0 1 Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 413 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.5 Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property:

INTENSET 0x0A 0x0000

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow Interrupt Enable 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value 0 1 Description The Tamper interrupt is disabled. The Tamper interrupt is enabled. Bits 8, 9 CMPnCompare n Interrupt Enable [n = 1..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare n Interrupt Enable bit, which and enables the Compare n interrupt. Value 0 1 Description The Compare n interrupt is disabled. The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value 0 1 Description Periodic Interval n interrupt is disabled. Periodic Interval n interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 414 Microchip Confidential Confidential 21.8.6 Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0) PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Name:

Offset:

Reset:

Property:

INTFLAG 0x0C 0x0000

Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 TAMPERTamper event This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/

INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bits 8, 9 CMPnCompare n [n = 1..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMPn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n [n = 7..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/

SET.PERn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 415 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.7 Debug Control Name:

Offset:

Reset:

Property:

DBGCTRL 0x0E 0x00

Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNDebug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. DBGRUN R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 416 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.8 Synchronization Busy in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property:

SYNCBUSY 0x10 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 Access Reset Bit 15 COUNTSYNC R 0 Access Reset 14 13 12 19 GP3 R 0 11 18 GP2 R 0 10 17 GP1 R 0 9 16 GP0 R 0 8 Bit 7 Access Reset 6 COMP1 R 0 5 COMP0 R 0 4 3 COUNT R 0 2 FREQCORR R 0 1 ENABLE R 0 0 SWRST R 0 Bits 16, 17, 18, 19 GPnGeneral Purpose n Synchronization Busy Status Value 0 1 Description Write synchronization for GPn register is complete. Write synchronization for GPn register is ongoing. Bit 15 COUNTSYNCCount Read Sync Enable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.COUNTSYNC bit is complete. Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bits 5, 6 COMPnCompare n Synchronization Busy Status [n = 1..0]

Value 0 1 Description Write synchronization for COMPx register is complete. Write synchronization for COMPx register is ongoing. Bit 3 COUNTCount Value Synchronization Busy Status Description Read/write synchronization for COUNT register is complete. Read/write synchronization for COUNT register is ongoing. Value 0 1 Bit 2 FREQCORRFrequency Correction Synchronization Busy Status Value 0 1 Description Write synchronization for FREQCORR register is complete. Write synchronization for FREQCORR register is ongoing. Bit 1 ENABLEEnable Synchronization Busy Status Value 0 Description Write synchronization for CTRLA.ENABLE bit is complete. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 417 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 1 Description Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 SWRSTSoftware Reset Synchronization Busy Status Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description Write synchronization for CTRLA.SWRST bit is complete. Write synchronization for CTRLA.SWRST bit is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 418 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.9 Frequency Correction FREQCORR Name:

0x14 Offset:

Reset:

0x00 Property: Write-Synchronized Note:This register is write-synchronized: SYNCBUSY.FREQCORR must be checked to ensure the FREQCORR register synchronization is complete. Bit Access Reset 7 SIGN R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 VALUE[6:0]

R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 SIGNCorrection Sign Value 0 1 Description The correction value is positive, i.e., frequency will be decreased. The correction value is negative, i.e., frequency will be increased. Bits 6:0 VALUE[6:0]Correction Value These bits define the amount of correction applied to the RTC prescaler. Value 0 1 - 127 Description Correction is disabled and the RTC frequency is unchanged. The RTC frequency is adjusted according to the value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 419 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.10 Counter Value in COUNT32 mode (CTRLA.MODE=0) Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized COUNT 0x18 0x00000000 Notes:

1. 2. This register is read-synchronized when CTRLA.COUNTSYNC = 1: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 COUNT[31:24]

R/W 0 20 R/W 0 19 COUNT[23:16]

R/W 0 12 R/W 0 11 COUNT[15:8]

R/W 0 4 R/W 0 3 COUNT[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 COUNT[31:0]Counter Value These bits define the value of the 32-bit RTC counter in mode 0. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 420 Microchip Confidential Confidential 21.8.11 Compare 0 Value in COUNT32 mode (CTRLA.MODE=0) PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Name:

Offset:

Reset:

Property: Write-Synchronized COMP0 0x20 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 COMP[31:24]

R/W 0 20 R/W 0 19 COMP[23:16]

R/W 0 12 R/W 0 11 COMP[15:8]

R/W 0 4 R/W 0 COMP[7:0]

R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 COMP[31:0]Compare Value The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is one. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 421 Microchip Confidential Confidential 21.8.12 Compare 1 Value in COUNT32 mode (CTRLA.MODE=1) PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Name:

Offset:

Reset:

Property: Write-Synchronized COMP1 0x24 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 COMP[31:24]

R/W 0 20 R/W 0 19 COMP[23:16]

R/W 0 12 R/W 0 11 COMP[15:8]

R/W 0 4 R/W 0 COMP[7:0]

R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 COMP[31:0]Compare Value The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is one. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 422 Microchip Confidential Confidential 21.8.13 General Purpose n Name:

Offset:

Reset:

Property:

GPn 0x40 + n*0x04 [n=0..3]

0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 GP[31:24]

GP[23:16]

GP[15:8]

GP[7:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 GP[31:0]General Purpose These bits are for user-defined general purpose use, see General Purpose Registers from Related Links. Related Links 21.6.8.4. General Purpose Registers 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 423 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.14 Tamper Control Name:

Offset:

Reset:

Property: Enable-Protected TAMPCTRL 0x60 0x00000000 Bit 31 30 29 28 Access Reset Bit 23 22 21 20 Access Reset Bit 15 14 13 12 Access Reset 27 DEBNC3 26 DEBNC2 25 DEBNC1 24 DEBNC0 0 0 0 0 19 TAMLVL3 18 TAMLVL2 17 TAMLVL1 16 TAMLVL0 0 11 0 10 0 9 0 8 IN3ACT[1]

0 Bit 7 IN3ACT[0]

Access Reset 0 6 0 IN2ACT[1:0]

5 0 4 0 IN1ACT[1:0]

3 0 2 0 IN2ACT[1:0]

1 0 0 IN0ACT[1:0]

0 Bits 24, 25, 26, 27 DEBNCnDebounce Enable of Tamper Input INn [n=0..3]

Note:Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description Debouncing is disabled for Tamper input INn Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 TAMLVLnTamper Level Select of Tamper Input INn [n=0..3]

Note:Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description A falling edge condition will be detected on Tamper input INn. A rising edge condition will be detected on Tamper input INn. Bits 8:7 IN3ACT[1:0]Tamper Channel 3 Action These bits determine the action taken by Tamper Channel 3. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 6:5 IN2ACT[1:0]Tamper Channel 2 Action These bits determine the action taken by Tamper Channel 2. Value 0x0 0x1 0x2 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 424 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 4:3 IN1ACT[1:0]Tamper Channel 1 Action These bits determine the action taken by Tamper Channel 1. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 0:1, 1:2, 2:3, 3:4 INnACTTamper Channel n Action [n=0..3]

These bits determine the action taken by Tamper Channel n. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 425 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.15 Timestamp Name:

Offset:

Reset:

Property:

TIMESTAMP 0x64 0x0

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 28 27 COUNT[31:24]

R 0 20 R 0 19 COUNT[23:16]

R 0 12 R 0 4 R 0 COUNT[15:8]

COUNT[7:0]

R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 COUNT[31:0]Count Timestamp Value The 32-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 426 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.16 Tamper ID Name:

Offset:

Reset:

TAMPID 0x68 0x00000000 Bit Access Reset 31 TAMPEVT R/W 0 30 29 28 27 26 25 24 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 Access Reset 3 TAMPID3 R/W 0 2 TAMPID2 R/W 0 1 TAMPID1 R/W 0 0 TAMPID0 R/W 0 Bit 31 TAMPEVTTamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper input event has not been detected A tamper input event has been detected Bits 0, 1, 2, 3 TAMPIDnTamper on Channel n Detected [n=0..3]

Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper condition has not been detected on Channel n A tamper condition has been detected on Channel n 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 427 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.8.17 Backup0 Name:

Offset:

Reset:

BKUP0 0x80 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 BKUP[31:24]

R/W 0 20 R/W 0 19 BKUP[23:16]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 3 R/W 0 BKUP[15:8]

BKUP[7:0]

26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 BKUP[31:0]Backup These bits are user-defined for general purpose use in the Backup domain. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 428 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.9 Register Summary - Mode 0 - 32-Bit Counter See RTCC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x02 CTRLB 0x04 EVCTRL 0x08 INTENCLR 0x0A INTENSET 0x0C 0x0E 0x0F INTFLAG DBGCTRL Reserved 0x10 SYNCBUSY 0x14 0x15

... 0x17 0x18 0x1A

... 0x1B 0x1C 0x1E

... 0x1F 0x20 FREQCORR Reserved COUNT Reserved PER Reserved COMP0 0x22 COMP1 0x24 COMP2 0x26 0x28

... 0x3F COMP3 Reserved 0x40 GP0 0x44 GP1 7:0 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 15:8 23:16 31:24 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 MODE[1:0]

ENABLE SWRST COUNTSYN C GPTRST BKTRST PRESCALER[3:0]

DMAEN RTCOUT DEBASYNC DEBMAJ ACTF[2:0]

GP2EN GP0EN DEBF[2:0]

PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 OVFEO TAMPEREO CMPEOn[3:0]

PER7 OVF PER7 OVF PER7 OVF PER6 PER5 PER4 TAMPER PER6 PER5 PER4 TAMPER PER6 PER5 PER4 TAMPER PER3 CMP3 PER3 CMP3 PER3 CMP3 PER2 CMP2 PER2 CMP2 PER2 CMP2 PER1 CMP1 PER1 CMP1 PER1 CMP1 TAMPEVEI PER0 CMP0 PER0 CMP0 PER0 CMP0 DBGRUN COMP2 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST COUNTSYN C GP3 GP2 GP1 GP0 COMP3 SIGN VALUE[6:0]

COUNT[7:0]

COUNT[15:8]

PER[7:0]

PER[15:8]

COMP[7:0]

COMP[15:8]

COMP[7:0]

COMP[15:8]

COMP[7:0]

COMP[15:8]

COMP[7:0]

COMP[15:8]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 429 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x48 GP2 0x4C GP3 0x50

... 0x5F Reserved 0x60 TAMPCTRL 0x64 TIMESTAMP 0x68 TAMPID 0x6C

... 0x7F Reserved 0x80 BKUP0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

IN3ACT[0]

IN2ACT[1:0]

IN1ACT[1:0]

IN2ACT[1:0]

IN0ACT[1:0]

TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 DEBNC3 DEBNC2 DEBNC1 DEBNC0 IN3ACT[1]

COUNT[7:0]

COUNT[15:8]

TAMPID3 TAMPID2 TAMPID1 TAMPID0 TAMPEVT BKUP[7:0]

BKUP[15:8]

BKUP[23:16]

BKUP[31:24]

Related Links 7. Product Memory Mapping Overview 21.10 Register Description - Mode 1 - 16-Bit Counter This Register Description section is valid if the RTC is in COUNT16 mode (CTRLA.MODE=1). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 430 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.1 Control A in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property: Enable-Protected, Write-Synchronized CTRLA 0x00 0x0000 Bit 15 COUNTSYNC R/W 0 Access Reset 14 GPTRST R/W 0 13 BKTRST R/W 0 12 Bit 7 6 5 4 Access Reset 11 R/W 0 3 R/W 0 MODE[1:0]

10 9 PRESCALER[3:0]

R/W 0 2 R/W 0 R/W 0 1 ENABLE R/W 0 8 R/W 0 0 SWRST R/W 0 Bit 15 COUNTSYNCCOUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value 0 1 Description COUNT read synchronization is disabled COUNT read synchronization is enabled Bit 14 GPTRSTGP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description GPn registers will not reset when a tamper condition occurs. GPn registers will reset when a tamper condition occurs. Bit 13 BKTRSTBKUP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description BKUPn registers will not reset when a tamper condition occurs. BKUPn registers will reset when a tamper condition occurs. Bits 11:8 PRESCALER[3:0]Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock

(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/2 CLK_RTC_CNT = GCLK_RTC/4 CLK_RTC_CNT = GCLK_RTC/8 CLK_RTC_CNT = GCLK_RTC/16 CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 Name OFF DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 431 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0xB 0xC-0xF Name DIV1024

Description CLK_RTC_CNT = GCLK_RTC/1024 Reserved Bits 3:2 MODE[1:0]Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value 0x0 0x1 0x2 0x3 Description Mode 0: 32-bit counter Mode 1: 16-bit counter Mode 2: Clock/calendar Reserved Name COUNT32 COUNT16 CLOCK

Bit 1 ENABLEEnable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register

(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value 0 1 Description The peripheral is disabled The peripheral is enabled Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST will be cleared when the Reset is complete. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description There is no Reset operation ongoing The Reset operation is ongoing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 432 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.2 Control B in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property: Enable-Protected CTRLB 0x02 0x0000 Bit 15 14 R/W 0 13 ACTF[2:0]

R/W 0 12 R/W 0 7 DMAEN R/W 0 6 RTCOUT R/W 0 5 DEBASYNC R/W 0 4 DEBMAJ R/W 0 Access Reset Bit Access Reset 11 3 10 R/W 0 2 9 DEBF[2:0]

R/W 0 1 GP2EN R/W 0 8 R/W 0 0 GP0EN R/W 0 Bits 14:12 ACTF[2:0]Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_OUT = CLK_RTC / 2 CLK_RTC_OUT = CLK_RTC / 4 CLK_RTC_OUT = CLK_RTC / 8 CLK_RTC_OUT = CLK_RTC / 16 CLK_RTC_OUT = CLK_RTC / 32 CLK_RTC_OUT = CLK_RTC / 64 CLK_RTC_OUT = CLK_RTC / 128 CLK_RTC_OUT = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bits 10:8 DEBF[2:0]Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_DEB = CLK_RTC / 2 CLK_RTC_DEB = CLK_RTC / 4 CLK_RTC_DEB = CLK_RTC / 8 CLK_RTC_DEB = CLK_RTC / 16 CLK_RTC_DEB = CLK_RTC / 32 CLK_RTC_DEB = CLK_RTC / 64 CLK_RTC_DEB = CLK_RTC / 128 CLK_RTC_DEB = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bit 7 DMAENDMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value 0 1 Description Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 RTCOUTRTC Output Enable Value 0 1 Description The RTC active layer output is disabled. The RTC active layer output is enabled. Bit 5 DEBASYNCDebouncer Asynchronous Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 433 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0 1 Description The tamper input debouncers operate synchronously. The tamper input debouncers operate asynchronously. Bit 4 DEBMAJDebouncer Majority Enable Value 0 1 Description The tamper input debouncers match three equal values. The tamper input debouncers match majority two of three values. Bit 1 GP2ENGeneral Purpose 2 Enable Value 0 1 Description COMP1 compare function enabled. GP2/GP3 disabled. COMP1 compare function disabled. GP2/GP3 enabled. Bit 0 GP0ENGeneral Purpose 0 Enable Value 0 1 Description COMP0 compare function enabled. GP0/GP1 disabled. COMP0 compare function disabled. GP0/GP1 enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 434 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.3 Event Control in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property: Enable-Protected EVCTRL 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 Access Reset Bit Access Reset Bit Access Reset 15 OVFEO R/W 0 7 PEREO7 R/W 0 13 12 14 TAMPEREO R/W 0 11 R/W 0 6 PEREO6 R/W 0 5 PEREO5 R/W 0 4 PEREO4 R/W 0 3 PEREO3 R/W 0 10 9 CMPEOn[3:0]

R/W 0 2 PEREO2 R/W 0 R/W 0 1 PEREO1 R/W 0 16 TAMPEVEI R/W 0 8 R/W 0 0 PEREO0 R/W 0 Bit 16 TAMPEVEITamper Event Input Enable Value 0 1 Description Tamper event input is disabled, and incoming events will be ignored Tamper event input is enabled, and incoming events will capture the COUNT value Bit 15 OVFEOOverflow Event Output Enable Value 0 1 Description Overflow event is disabled and will not be generated. Overflow event is enabled and will be generated for every overflow. Bit 14 TAMPEREOTamper Event Output Enable Value 0 1 Description Tamper event output is disabled, and will not be generated. Tamper event output is enabled, and will be generated for every tamper input. Bits 11:8 CMPEOn[3:0]Compare n Event Output Enable [n = 3..0]

Value 0 1 Description Compare n event is disabled and will not be generated. Compare n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 PEREOnPeriodic Interval n Event Output Enable [n = 7..0]

Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 435 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.4 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property:

INTENCLR 0x08 0x0000

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 13 12 5 PER5 R/W 0 4 PER4 R/W 0 11 CMP3 R/W 0 3 PER3 R/W 0 10 CMP2 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 Bit 15 OVFOverflow Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value 0 1 Description The Tamper interrupt is disabled. The Tamper interrupt is enabled. Bits 8, 9, 10, 11 CMPnCompare n Interrupt Enable [n = 3..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt. Value 0 1 Description The Compare n interrupt is disabled. The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Description Value Periodic Interval n interrupt is disabled. 0 Periodic Interval n interrupt is enabled. 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 436 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.5 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property:

INTENSET 0x0A 0x0000

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 13 12 5 PER5 R/W 0 4 PER4 R/W 0 11 CMP3 R/W 0 3 PER3 R/W 0 10 CMP2 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 Bit 15 OVFOverflow Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value 0 1 Description The Tamper interrupt is disabled. The Tamper interrupt is enabled. Bits 8, 9, 10, 11 CMPnCompare n Interrupt Enable [n = 3..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Compare n Interrupt Enable bit, which and enables the Compare n interrupt. Value 0 1 Description The Compare n interrupt is disabled. The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Description Value Periodic Interval n interrupt is disabled. 0 Periodic Interval n interrupt is enabled. 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 437 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.6 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1) Name:

Offset:

Reset:

Property:

INTFLAG 0x0C 0x0000

Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 13 12 5 PER5 R/W 0 4 PER4 R/W 0 11 CMP3 R/W 0 3 PER3 R/W 0 10 CMP2 R/W 0 2 PER2 R/W 0 9 CMP1 R/W 0 1 PER1 R/W 0 8 CMP0 R/W 0 0 PER0 R/W 0 Bit 15 OVFOverflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 TAMPERTamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/

INTENSET.TAMPER is one. Writing a '0' to this bit has no effect. Writing a one to this bit clears the Tamper interrupt flag. Bits 8, 9, 10, 11 CMPnCompare n [n = 3..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMPn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n [n = 7..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/

SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 438 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.7 Debug Control Name:

Offset:

Reset:

Property:

DBGCTRL 0x0E 0x00

Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNDebug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. DBGRUN R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 439 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.8 Synchronization Busy in COUNT16 mode (CTRLA.MODE=1) Name:

Offset:

Reset:

SYNCBUSY 0x10 0x00000000 Bit 31 30 29 28 27 26 25 24 16 GP0 R 0 8 COMP3 R 0 0 SWRST R 0 Access Reset Bit 23 22 21 20 Access Reset Bit 15 COUNTSYNC R 0 Access Reset 14 13 12 19 GP3 R 0 11 18 GP2 R 0 10 17 GP1 R 0 9 Bit Access Reset 7 COMP2 R 0 6 COMP1 R 0 5 COMP0 R 0 4 PER R 0 3 COUNT R 0 2 FREQCORR R 0 1 ENABLE R 0 Bits 16, 17, 18, 19 GPnGeneral Purpose n Synchronization Busy Status Value 0 1 Description Write synchronization for GPn register is complete. Write synchronization for GPn register is ongoing. Bit 15 COUNTSYNCCount Read Sync Enable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.COUNTSYNC bit is complete. Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bits 5, 6, 7, 8 COMPnCompare n Synchronization Busy Status [n = 3..0]

Value 0 1 Description Write synchronization for COMPn register is complete. Write synchronization for COMPn register is ongoing. Bit 4 PERPeriod Synchronization Busy Status Value 0 1 Description Write synchronization for PER register is complete. Write synchronization for PER register is ongoing. Bit 3 COUNTCount Value Synchronization Busy Status Description Read/write synchronization for COUNT register is complete. Read/write synchronization for COUNT register is ongoing. Value 0 1 Bit 2 FREQCORRFrequency Correction Synchronization Busy Status Value 0 1 Description Write synchronization for FREQCORR register is complete. Write synchronization for FREQCORR register is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 440 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Bit 1 ENABLEEnable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.ENABLE bit is complete. Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 SWRSTSoftware Reset Synchronization Busy Status Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description Write synchronization for CTRLA.SWRST bit is complete. Write synchronization for CTRLA.SWRST bit is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 441 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.9 Frequency Correction FREQCORR Name:

0x14 Offset:

Reset:

0x00 Property: Write-Synchronized Note:This register is write-synchronized: SYNCBUSY.FREQCORR must be checked to ensure the FREQCORR register synchronization is complete. Bit Access Reset 7 SIGN R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 VALUE[6:0]

R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 SIGNCorrection Sign Value 0 1 Description The correction value is positive, i.e., frequency will be decreased. The correction value is negative, i.e., frequency will be increased. Bits 6:0 VALUE[6:0]Correction Value These bits define the amount of correction applied to the RTC prescaler. Value 0 1 - 127 Description Correction is disabled and the RTC frequency is unchanged. The RTC frequency is adjusted according to the value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 442 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.10 Counter Value in COUNT16 mode (CTRLA.MODE = 1) Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized COUNT 0x18 0x0000 Notes:

1. 2. This register is read-synchronized when CTRLA.COUNTSYNC = 1: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register synchronization is complete. Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 COUNT[15:8]

R/W 0 4 R/W 0 3 COUNT[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 COUNT[15:0]Counter Value These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE = 1). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 443 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.11 Counter Period in COUNT16 mode (CTRLA.MODE = 1) PER Name:

0x1C Offset:

Reset:

0x0000 Property: Write-Synchronized Note:This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register synchronization is complete. Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 PER[15:8]

PER[7:0]

12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 PER[15:0]Counter Period These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 444 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.12 Compare n Value in COUNT16 mode (CTRLA.MODE = 1) COMP Name:

0x20 + n*0x02 [n=0..3]

Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 COMP[15:8]

R/W 0 4 R/W 0 COMP[7:0]

R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 COMP[15:0]Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 445 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.13 Tamper Control Name:

Offset:

Reset:

Property: Enable-Protected TAMPCTRL 0x60 0x00000000 Bit 31 30 29 28 Access Reset Bit 23 22 21 20 Access Reset Bit 15 14 13 12 Access Reset 27 DEBNC3 26 DEBNC2 25 DEBNC1 24 DEBNC0 0 0 0 0 19 TAMLVL3 18 TAMLVL2 17 TAMLVL1 16 TAMLVL0 0 11 0 10 0 9 0 8 IN3ACT[1]

0 Bit 7 IN3ACT[0]

Access Reset 0 6 0 IN2ACT[1:0]

5 0 4 0 IN1ACT[1:0]

3 0 2 0 IN2ACT[1:0]

1 0 0 IN0ACT[1:0]

0 Bits 24, 25, 26, 27 DEBNCnDebounce Enable of Tamper Input INn [n=0..3]

Note:Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description Debouncing is disabled for Tamper input INn Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 TAMLVLnTamper Level Select of Tamper Input INn [n=0..3]

Note:Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description A falling edge condition will be detected on Tamper input INn. A rising edge condition will be detected on Tamper input INn. Bits 8:7 IN3ACT[1:0]Tamper Channel 3 Action These bits determine the action taken by Tamper Channel 3. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 6:5 IN2ACT[1:0]Tamper Channel 2 Action These bits determine the action taken by Tamper Channel 2. Value 0x0 0x1 0x2 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 446 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 4:3 IN1ACT[1:0]Tamper Channel 1 Action These bits determine the action taken by Tamper Channel 1. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 0:1, 1:2, 2:3, 3:4 INnACTTamper Channel n Action [n=0..3]

These bits determine the action taken by Tamper Channel n. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 447 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.14 Timestamp Name:

Offset:

Reset:

Property:

TIMESTAMP 0x64 0x0000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 COUNT[15:8]

COUNT[7:0]

12 R 0 4 R 0 11 R 0 3 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 COUNT[15:0]Count Timestamp Value The 16-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 448 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.15 Tamper ID Name:

Offset:

Reset:

TAMPID 0x68 0x00000000 Bit Access Reset 31 TAMPEVT R/W 0 30 29 28 27 26 25 24 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 Access Reset 3 TAMPID3 R/W 0 2 TAMPID2 R/W 0 1 TAMPID1 R/W 0 0 TAMPID0 R/W 0 Bit 31 TAMPEVTTamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper input event has not been detected A tamper input event has been detected Bits 0, 1, 2, 3 TAMPIDnTamper on Channel n Detected [n=0..3]

Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper condition has not been detected on Channel n A tamper condition has been detected on Channel n 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 449 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.10.16 Backup0 Name:

Offset:

Reset:

BKUP0 0x80 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 BKUP[31:24]

R/W 0 20 R/W 0 19 BKUP[23:16]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 3 R/W 0 BKUP[15:8]

BKUP[7:0]

26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 BKUP[31:0]Backup These bits are user-defined for general purpose use in the Backup domain. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 450 Microchip Confidential Confidential 21.10.17 General Purpose n Name:

Offset:

Reset:

Property:

GPn 0x40 + n*0x04 [n=0..3]

0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 GP[31:24]

GP[23:16]

GP[15:8]

GP[7:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 GP[31:0]General Purpose These bits are for user-defined general purpose use, see General Purpose Registers from Related Links. Related Links 21.6.8.4. General Purpose Registers 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 451 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.11 Register Summary - Mode 0 - 32-Bit Counter See RTCC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 MATCHCLR CLKREP MODE[1:0]

ENABLE SWRST 0x00 CTRLA 0x02 CTRLB 0x04 EVCTRL 0x08 INTENCLR 0x0A INTENSET 0x0C 0x0E 0x0F INTFLAG DBGCTRL Reserved 0x10 SYNCBUSY 0x14 0x15

... 0x17 FREQCORR Reserved 0x18 CLOCK 0x1C

... 0x1F Reserved 0x20 ALARM0 0x24 0x25

... 0x27 MASK0 Reserved 0x28 ALARM1 0x2C 0x2D

... 0x3F MASK1 Reserved 0x40 GP0 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 7:0 15:8 7:0 7:0 15:8 23:16 31:24 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 15:8 23:16 31:24 7:0 7:0 15:8 23:16 31:24 CLOCKSYN C GPTRST BKTRST PRESCALER[3:0]

DMAEN RTCOUT DEBASYNC DEBMAJ ACTF[2:0]

GP2EN GP0EN DEBF[2:0]

PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 OVFEO TAMPEREO ALARMEO1 ALARMEO0 TAMPEVEI PER7 OVF PER7 OVF PER7 OVF PER6 PER5 PER4 PER3 PER2 PER1 PER0 TAMPER ALARM1 ALARM0 PER6 PER5 PER4 PER3 PER2 PER1 PER0 TAMPER ALARM1 ALARM0 PER6 PER5 PER4 PER3 PER2 PER1 PER0 TAMPER ALARM1 ALARM0 DBGRUN ALARM1 ALARM0 CLOCK FREQCORR ENABLE SWRST CLOCKSYN C MASK1 MASK0 GP3 GP2 GP1 GP0 SIGN VALUE[6:0]

MINUTE[1:0]

MONTH[1:0]

HOUR[3:0]

SECOND[5:0]

MINUTE[5:2]

DAY[4:0]

YEAR[5:0]

HOUR[4]

MONTH[3:2]

MINUTE[1:0]

MONTH[1:0]

HOUR[3:0]

SECOND[5:0]

MINUTE[5:2]

DAY[4:0]

HOUR[4]

YEAR[5:0]

MONTH[3:2]

SEL[2:0]

MINUTE[1:0]

MONTH[1:0]

HOUR[3:0]

SECOND[5:0]

MINUTE[5:2]

DAY[4:0]

HOUR[4]

YEAR[5:0]

MONTH[3:2]

SEL[2:0]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 452 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x44 GP1 0x48 GP2 0x4C GP3 0x50

... 0x5F Reserved 0x60 TAMPCTRL 0x64 TIMESTAMP 0x68 TAMPID 0x6C

... 0x7F Reserved 0x80 BKUP0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

GP[7:0]

GP[15:8]

GP[23:16]

GP[31:24]

IN3ACT[0]

IN2ACT[1:0]

IN1ACT[1:0]

IN2ACT[1:0]

IN0ACT[1:0]

TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 DEBNC3 DEBNC2 DEBNC1 DEBNC0 IN3ACT[1]

MINUTE[1:0]

MONTH[1:0]

HOUR[3:0]

SECOND[5:0]

MINUTE[5:2]

DAY[4:0]

YEAR[5:0]

HOUR[4]

MONTH[3:2]

TAMPID3 TAMPID2 TAMPID1 TAMPID0 TAMPEVT BKUP[7:0]

BKUP[15:8]

BKUP[23:16]

BKUP[31:24]

Related Links 7. Product Memory Mapping Overview 21.12 Register Description - Mode 2 - Clock/Calendar This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 453 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.1 Control A in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property: Enable-Protected, Write-Synchronized CTRLA 0x00 0x0000 Bit 15 CLOCKSYNC R/W 0 Access Reset Bit 7 MATCHCLR Access Reset R/W 0 12 13 BKTRST R/W 0 5 4 14 GPTRST R/W 0 6 CLKREP R/W 0 11 R/W 0 3 R/W 0 MODE[1:0]

10 9 PRESCALER[3:0]

R/W 0 2 R/W 0 R/W 0 1 ENABLE R/W 0 8 R/W 0 0 SWRST R/W 0 Bit 15 CLOCKSYNCCLOCK Read Synchronization Enable The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register. This bit is not enable-protected. Value 0 1 Description CLOCK read synchronization is disabled CLOCK read synchronization is enabled Bit 14 GPTRSTGP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bit 13 BKTRSTBKUP Registers Reset On Tamper Enable All BKUPn registers are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description BKUPn registers will not reset when a tamper condition occurs. BKUPn registers will reset when a tamper condition occurs. Bits 11:8 PRESCALER[3:0]Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock

(CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC-0xF Description CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/1 CLK_RTC_CNT = GCLK_RTC/2 CLK_RTC_CNT = GCLK_RTC/4 CLK_RTC_CNT = GCLK_RTC/8 CLK_RTC_CNT = GCLK_RTC/16 CLK_RTC_CNT = GCLK_RTC/32 CLK_RTC_CNT = GCLK_RTC/64 CLK_RTC_CNT = GCLK_RTC/128 CLK_RTC_CNT = GCLK_RTC/256 CLK_RTC_CNT = GCLK_RTC/512 CLK_RTC_CNT = GCLK_RTC/1024 Reserved Name OFF DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 DIV512 DIV1024

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 454 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Bit 7 MATCHCLRClear on Match This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized. Description Value The counter is not cleared on a Compare/Alarm match 0 The counter is cleared on a Compare/Alarm match 1 Bit 6 CLKREPClock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description 24 Hour 12 Hour (AM/PM) Bits 3:2 MODE[1:0]Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value 0x0 0x1 0x2 0x3 Description Mode 0: 32-bit counter Mode 1: 16-bit counter Mode 2: Clock/calendar Reserved Name COUNT32 COUNT16 CLOCK

Bit 1 ENABLEEnable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register

(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value 0 1 Description The peripheral is disabled The peripheral is enabled Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST will be cleared when the Reset is complete. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description There is no Reset operation ongoing The Reset operation is ongoing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 455 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.2 Control B in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property: Enable-Protected CTRLB 0x2 0x0000 Bit 15 14 R/W 0 13 ACTF[2:0]

R/W 0 12 R/W 0 7 DMAEN R/W 0 6 RTCOUT R/W 0 5 DEBASYNC R/W 0 4 DEBMAJ R/W 0 Access Reset Bit Access Reset 11 3 10 R/W 0 2 9 DEBF[2:0]

R/W 0 1 GP2EN R/W 0 8 R/W 0 0 GP0EN R/W 0 Bits 14:12 ACTF[2:0]Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_OUT = CLK_RTC / 2 CLK_RTC_OUT = CLK_RTC / 4 CLK_RTC_OUT = CLK_RTC / 8 CLK_RTC_OUT = CLK_RTC / 16 CLK_RTC_OUT = CLK_RTC / 32 CLK_RTC_OUT = CLK_RTC / 64 CLK_RTC_OUT = CLK_RTC / 128 CLK_RTC_OUT = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bits 10:8 DEBF[2:0]Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description CLK_RTC_DEB = CLK_RTC / 2 CLK_RTC_DEB = CLK_RTC / 4 CLK_RTC_DEB = CLK_RTC / 8 CLK_RTC_DEB = CLK_RTC / 16 CLK_RTC_DEB = CLK_RTC / 32 CLK_RTC_DEB = CLK_RTC / 64 CLK_RTC_DEB = CLK_RTC / 128 CLK_RTC_DEB = CLK_RTC / 256 Name DIV2 DIV4 DIV8 DIV16 DIV32 DIV64 DIV128 DIV256 Bit 7 DMAENDMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value 0 1 Description Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 RTCOUTRTC Out Enable Value 0 1 Description The RTC active layer output is disabled. The RTC active layer output is enabled. Bit 5 DEBASYNCDebouncer Asynchronous Enable 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 456 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0 1 Description The tamper input debouncers operate synchronously. The tamper input debouncers operate asynchronously. Bit 4 DEBMAJDebouncer Majority Enable Value 0 1 Description The tamper input debouncers match three equal values. The tamper input debouncers match majority two of three values. Bit 1 GP2ENGeneral Purpose 2 Enable Value 0 1 Description COMP1 compare function enabled. GP2/GP3 disabled. COMP1 compare function disabled. GP2/GP3 enabled. Bit 0 GP0ENGeneral Purpose 0 Enable Value 0 1 Description COMP0 compare function enabled. GP0 disabled. COMP0 compare function disabled. GP0 enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 457 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.3 Event Control in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property: Enable-Protected EVCTRL 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 Access Reset Bit Access Reset Bit Access Reset 15 OVFEO R/W 0 7 PEREO7 R/W 0 13 12 11 10 14 TAMPEREO R/W 0 9 ALARMEO1 R/W 0 6 PEREO6 R/W 0 5 PEREO5 R/W 0 4 PEREO4 R/W 0 3 PEREO3 R/W 0 2 PEREO2 R/W 0 1 PEREO1 R/W 0 16 TAMPEVEI R/W 0 8 ALARMEO0 R/W 0 0 PEREO0 R/W 0 Bit 16 TAMPEVEITamper Event Input Enable Value 0 1 Description Tamper event input is disabled, and incoming events will be ignored. Tamper event input is enabled, and all incoming events will capture the CLOCK value. Bit 15 OVFEOOverflow Event Output Enable Value 0 1 Description Overflow event is disabled and will not be generated. Overflow event is enabled and will be generated for every overflow. Bit 14 TAMPEREOTamper Event Output Enable Value 0 1 Description Tamper event output is disabled, and will not be generated Tamper event output is enabled, and will be generated for every tamper input. Bits 8, 9 ALARMEOnAlarm n Event Output Enable [n = 1..0]

Value 0 1 Description Alarm n event is disabled and will not be generated. Alarm n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 PEREOnPeriodic Interval n Event Output Enable [n = 7..0]

Value 0 1 Description Periodic Interval n event is disabled and will not be generated. Periodic Interval n event is enabled and will be generated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 458 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.4 Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property:

INTENCLR 0x08 0x0000

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow Interrupt Enable 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 ALARM1 R/W 0 1 PER1 R/W 0 8 ALARM0 R/W 0 0 PER0 R/W 0 Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Bits 8, 9 ALARMnAlarm n Interrupt Enable [n = 1..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Alarm n Interrupt Enable bit, which disables the Alarm n interrupt. Value 0 1 Description The Alarm n interrupt is disabled. The Alarm n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Description Value Periodic Interval n interrupt is disabled. 0 Periodic Interval n interrupt is enabled. 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 459 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.5 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property:

INTENSET 0x0A 0x0000

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow Interrupt Enable 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 ALARM1 R/W 0 1 PER1 R/W 0 8 ALARM0 R/W 0 0 PER0 R/W 0 Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. Bit 14 TAMPERTamper Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value 0 1 Description The Tamper interrupt it disabled. The Tamper interrupt is enabled. Bits 8, 9 ALARMnAlarm n Interrupt Enable [n = 1..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Alarm n Interrupt Enable bit, which and enables the Alarm n interrupt. Value 0 1 Description The Alarm n interrupt is disabled. The Alarm n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n Interrupt Enable [n = 7..0]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Description Value Periodic Interval n interrupt is disabled. 0 Periodic Interval n interrupt is enabled. 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 460 Microchip Confidential Confidential 21.12.6 Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2) PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Name:

Offset:

Reset:

Property:

INTFLAG 0x0C 0x0000

Bit Access Reset Bit Access Reset 15 OVF R/W 0 7 PER7 R/W 0 14 TAMPER R/W 0 6 PER6 R/W 0 Bit 15 OVFOverflow 13 12 11 10 5 PER5 R/W 0 4 PER4 R/W 0 3 PER3 R/W 0 2 PER2 R/W 0 9 ALARM1 R/W 0 1 PER1 R/W 0 8 ALARM0 R/W 0 0 PER0 R/W 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 TAMPERTamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/

INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bits 8, 9 ALARMnAlarm n [n = 1..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.ALARMn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Alarm n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 PERnPeriodic Interval n [n = 7..0]

This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/

SET.PERx is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 461 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.7 Debug Control Name:

Offset:

Reset:

Property:

DBGCTRL 0x0E 0x00

Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNDebug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The RTC is halted when the CPU is halted by an external debugger. The RTC continues normal operation when the CPU is halted by an external debugger. DBGRUN R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 462 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.8 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2) Name:

Offset:

Reset:

Property:

SYNCBUSY 0x10 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 Access Reset Bit 15 CLOCKSYNC R 0 Access Reset 14 13 Bit 7 Access Reset 6 ALARM1 R 0 5 ALARM0 R 0 12 MASK1 R 0 4 19 GP3 R 0 11 MASK0 R 0 3 CLOCK R 0 18 GP2 R 0 10 17 GP1 R 0 9 16 GP0 R 0 8 2 FREQCORR R 0 1 ENABLE R 0 0 SWRST R 0 Bits 16, 17, 18, 19 GPnGeneral Purpose n Synchronization Busy Status Value 0 1 Description Write synchronization for GPn register is complete. Write synchronization for GPn register is ongoing. Bit 15 CLOCKSYNCClock Read Sync Enable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.CLOCKSYNC bit is complete. Write synchronization for CTRLA.CLOCKSYNC bit is ongoing. Bits 11, 12 MASKnMask n Synchronization Busy Status [n = 1..0]

Value 0 1 Description Write synchronization for MASKx register is complete. Write synchronization for MASKx register is ongoing. Bits 5, 6 ALARMnAlarm n Synchronization Busy Status [n = 1..0]

Value 0 1 Description Write synchronization for ALARMx register is complete. Write synchronization for ALARMx register is ongoing. Bit 3 CLOCKClock Register Synchronization Busy Status Description Read/write synchronization for CLOCK register is complete. Read/write synchronization for CLOCK register is ongoing. Value 0 1 Bit 2 FREQCORRFrequency Correction Synchronization Busy Status Value 0 Description Write synchronization for FREQCORR register is complete. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 463 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 1 Description Write synchronization for FREQCORR register is ongoing. Bit 1 ENABLEEnable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.ENABLE bit is complete. Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 SWRSTSoftware Reset Synchronization Busy Status Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description Write synchronization for CTRLA.SWRST bit is complete. Write synchronization for CTRLA.SWRST bit is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 464 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.9 Frequency Correction FREQCORR Name:

0x14 Offset:

Reset:

0x00 Property: Write-Synchronized Note:This register is write-synchronized: SYNCBUSY.FREQCORR must be checked to ensure the FREQCORR register synchronization is complete. Bit Access Reset 7 SIGN R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 VALUE[6:0]

R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 SIGNCorrection Sign Value 0 1 Description The correction value is positive, i.e., frequency will be decreased. The correction value is negative, i.e., frequency will be increased. Bits 6:0 VALUE[6:0]Correction Value These bits define the amount of correction applied to the RTC prescaler. Value 0 1 - 127 Description Correction is disabled and the RTC frequency is unchanged. The RTC frequency is adjusted according to the value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 465 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.10 Clock Value in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized CLOCK 0x18 0x00000000 Notes:

1. 2. This register is read-synchronized and write-synchronized: SYNCBUSY.CLOCK must be checked to ensure the CLOCK register synchronization is complete. This register must be written with 32-bit accesses only. Bit 31 Access Reset R/W 0 Bit 23 30 R/W 0 22 MONTH[1:0]

Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 R/W 0 14 R/W 0 6 HOUR[3:0]

MINUTE[1:0]

Access Reset R/W 0 R/W 0 Bits 31:26 YEAR[5:0]Year 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 YEAR[5:0]

28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 DAY[4:0]

R/W 0 11 R/W 0 3 26 R/W 0 18 R/W 0 10 R/W 0 2 SECOND[5:0]

R/W 0 R/W 0 25 24 MONTH[3:2]

R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 R/W 0 16 HOUR[4]

R/W 0 8 R/W 0 0 R/W 0 MINUTE[5:2]

The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. Bits 25:22 MONTH[3:0]Month 1 January 2 February

... 12 December Bits 21:17 DAY[4:0]Day Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year. Bits 16:12 HOUR[4:0]Hour When CTRLA.CLKREP = 0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1). Bits 11:6 MINUTE[5:0]Minute 0 59 Bits 5:0 SECOND[5:0]Second 0 59 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 466 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.11 Alarm n Value in Clock/Calendar mode (CTRLA.MODE = 2) Name:

Offset:

Reset:

Property: Write-Synchronized ALARM 0x20 + n*0x08 [n=0..1]

0x00000000 The 32-bit value of ALARMn is continuously compared with the 32-bit CLOCK value, based on the masking set by MASKn.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is 1. YEAR[5:0]

Bit 31 Access Reset R/W 0 Bit 23 30 R/W 0 22 MONTH[1:0]

Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 R/W 0 14 R/W 0 6 HOUR[3:0]

MINUTE[1:0]

Access Reset R/W 0 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 DAY[4:0]

R/W 0 11 R/W 0 3 26 R/W 0 18 R/W 0 10 R/W 0 2 SECOND[5:0]

R/W 0 R/W 0 25 24 MONTH[3:2]

R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 R/W 0 16 HOUR[4]

R/W 0 8 R/W 0 0 R/W 0 MINUTE[5:2]

Bits 31:26 YEAR[5:0]Year The alarm year. Years are only matched if MASKn.SEL is 6 Bits 25:22 MONTH[3:0]Month The alarm month. Months are matched only if MASKn.SEL is greater than 4. Bits 21:17 DAY[4:0]Day The alarm day. Days are matched only if MASKn.SEL is greater than 3. Bits 16:12 HOUR[4:0]Hour The alarm hour. Hours are matched only if MASKn.SEL is greater than 2. Bits 11:6 MINUTE[5:0]Minute The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1. Bits 5:0 SECOND[5:0]Second The alarm second. Seconds are matched only if MASKn.SEL is greater than 0. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 467 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.12 Alarm n Mask in Clock/Calendar mode (CTRLA.MODE = 2) MASK Name:

0x24 + n*0x08 [n=0..1]

Offset:

Reset:

0x00 Property: Write-Synchronized Bit 7 6 5 4 3 Access Reset Bits 2:0 SEL[2:0]Alarm Mask Selection 2 R/W 0 1 SEL[2:0]

R/W 0 0 R/W 0 These bits define which bit groups of Alarm n are valid. Description Value Alarm Disabled 0x0 Match seconds only 0x1 Match seconds and minutes only 0x2 Match seconds, minutes, and hours only 0x3 Match seconds, minutes, hours, and days only 0x4 Match seconds, minutes, hours, days, and months only 0x5 Match seconds, minutes, hours, days, months, and years 0x6 Reserved 0x7 Name OFF SS MMSS HHMMSS DDHHMMSS MMDDHHMMSS YYMMDDHHMMSS

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 468 Microchip Confidential Confidential 21.12.13 General Purpose n Name:

Offset:

Reset:

Property:

GPn 0x40 + n*0x04 [n=0..3]

0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 GP[31:24]

GP[23:16]

GP[15:8]

GP[7:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 GP[31:0]General Purpose These bits are for user-defined general purpose use, see General Purpose Registers from Related Links. Related Links 21.6.8.4. General Purpose Registers 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 469 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.14 Tamper Control Name:

Offset:

Reset:

Property: Enable-Protected TAMPCTRL 0x60 0x00000000 Bit 31 30 29 28 Access Reset Bit 23 22 21 20 Access Reset Bit 15 14 13 12 Access Reset 27 DEBNC3 26 DEBNC2 25 DEBNC1 24 DEBNC0 0 0 0 0 19 TAMLVL3 18 TAMLVL2 17 TAMLVL1 16 TAMLVL0 0 11 0 10 0 9 0 8 IN3ACT[1]

0 Bit 7 IN3ACT[0]

Access Reset 0 6 0 IN2ACT[1:0]

5 0 4 0 IN1ACT[1:0]

3 0 2 0 IN2ACT[1:0]

1 0 0 IN0ACT[1:0]

0 Bits 24, 25, 26, 27 DEBNCnDebounce Enable of Tamper Input INn [n=0..3]

Note:Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description Debouncing is disabled for Tamper input INn Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 TAMLVLnTamper Level Select of Tamper Input INn [n=0..3]

Note:Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL). Value 0 1 Description A falling edge condition will be detected on Tamper input INn. A rising edge condition will be detected on Tamper input INn. Bits 8:7 IN3ACT[1:0]Tamper Channel 3 Action These bits determine the action taken by Tamper Channel 3. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 6:5 IN2ACT[1:0]Tamper Channel 2 Action These bits determine the action taken by Tamper Channel 2. Value 0x0 0x1 0x2 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 470 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) Value 0x3 Name ACTL Description Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 4:3 IN1ACT[1:0]Tamper Channel 1 Action These bits determine the action taken by Tamper Channel 1. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUTn pins or inside the TrustRAM. When a mismatch occurs, capture timestamp and set Tamper flag Bits 0:1, 1:2, 2:3, 3:4 INnACTTamper Channel n Action [n=0..3]

These bits determine the action taken by Tamper Channel n. Value 0x0 0x1 0x2 0x3 Description Name Off (Disabled) OFF WAKE Wake and set Tamper flag CAPTURE Capture timestamp and set Tamper flag ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 471 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.15 Timestamp Value Name:

Offset:

Reset:

Property:

TIMESTAMP 0x64 0

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 MONTH[1:0]

MINUTE[1:0]

29 R 0 21 R 0 13 R 0 5 R 0 YEAR[5:0]

28 R 0 20 R 0 12 R 0 4 R 0 HOUR[3:0]

27 R 0 19 DAY[4:0]

R 0 26 R 0 18 R 0 10 11 R 0 3 R 0 MINUTE[5:2]

R 0 2 R 0 SECOND[5:0]

25 R 0 17 R 0 9 R 0 1 R 0 MONTH[3:2]

24 R 0 16 HOUR[4]

R 0 8 R 0 0 R 0 Bits 31:26 YEAR[5:0]Year The year value is captured by the TIMESTAMP when a tamper condition occurs. Bits 25:22 MONTH[3:0]Month The month value is captured by the TIMESTAMP when a tamper condition occurs. Bits 21:17 DAY[4:0]Day The day value is captured by the TIMESTAMP when a tamper condition occurs. Bits 16:12 HOUR[4:0]Hour The hour value is captured by the TIMESTAMP when a tamper condition occurs. Bits 11:6 MINUTE[5:0]Minute The minute value is captured by the TIMESTAMP when a tamper condition occurs. Bits 5:0 SECOND[5:0]Second The second value is captured by the TIMESTAMP when a tamper condition occurs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 472 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.16 Tamper ID Name:

Offset:

Reset:

TAMPID 0x68 0x00000000 Bit Access Reset 31 TAMPEVT R/W 0 30 29 28 27 26 25 24 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 Access Reset 3 TAMPID3 R/W 0 2 TAMPID2 R/W 0 1 TAMPID1 R/W 0 0 TAMPID0 R/W 0 Bit 31 TAMPEVTTamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper input event has not been detected A tamper input event has been detected Bits 0, 1, 2, 3 TAMPIDnTamper on Channel n Detected [n=0..3]

Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value 0 1 Description A tamper condition has not been detected on Channel n A tamper condition has been detected on Channel n 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 473 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Real-Time Counter and Calendar (RTCC) 21.12.17 Backup0 Name:

Offset:

Reset:

BKUP0 0x80 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 BKUP[31:24]

R/W 0 20 R/W 0 19 BKUP[23:16]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 3 R/W 0 BKUP[15:8]

BKUP[7:0]

26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 BKUP[31:0]Backup These bits are user-defined for general purpose use in the Backup domain. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 474 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22. Direct Memory Access Controller (DMAC) 22.1 Overview The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The DMA part of the DMAC has several DMA channels which all can receive different types of transfer triggers to generate transfer requests from the DMA channels to the arbiter (see DMAC Block Diagram in the Block Diagram from Related Links). The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel to start transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally. The DMAC has four bus interfaces:

The data transfer bus is used for performing the actual DMA transfer. The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued. The write-back bus is used to write the transfer descriptor back to SRAM. All buses are AHB Manager interfaces except for the AHB/APB Bridge bus, which is an APB Subordinate interface. Burst transfer options, buffered active channel to pre-fetch descriptors and advance quality of service features ensure low-latency transfers for high-speed peripherals or high-speed operations. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Note:Traditional Direct Memory Access Controller (DMAC) documentation uses the terminology Master and Slave. The equivalent Microchip terminology used in this document is Host and Client respectively. Related Links 22.3. Block Diagram 22.2 Features Data transfer from:

Peripheral to peripheral Peripheral to memory Memory to peripheral Memory to memory Transfer trigger sources Software Events from Event System Dedicated requests from peripherals SRAM based transfer descriptors Single transfer using one descriptor Multi-buffer or circular buffer modes by linking multiple descriptors 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 475 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Up to 16 channels Enable 16 independent transfers Automatic descriptor fetch for each channel Suspend/resume operation support for each channel Flexible arbitration scheme 4 configurable priority levels for each channel Fixed or round-robin priority scheme within each priority level From 1 to 256KB data transfer in a single block transfer Multiple addressing modes Static Configurable increment scheme Optional interrupt generation On block transfer complete On error detection On channel suspend 8 event inputs One event input for each of the 8 least significant DMA channels Can be selected to trigger normal transfers, periodic transfers or conditional transfers Can be selected to suspend or resume channel operation 4 event outputs One output event for each of the 4 least significant DMA channels Selectable generation on AHB, block, or transaction transfer complete Error management supported by write-back function Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer CRC polynomial software selectable to CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.3) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 476 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.3 Block Diagram Figure 22-1. DMAC Block Diagram CPU M Write-Back Buffer S HIGH SPEED BUS MATRIX S AHB/APB Bridge M M S a t a D r e f s n a r T a t a D r e f s n a r T Host Interface Fifo Arbiter Active Channel AHB/APB Bridge Fetch Engine Pre-Fetch Channel CRC Engine Interrupts Optional Event System Peripheral k c A

t s e u q e R k c A

t u p n I t n e v E t u p t u O t n e v E SRAM Transfer Control Descriptor r o t p i r c s e D h c t e F k c a b

e t i r W DMAC Internal Architecture DMA Channels Channel n Channel 0 n 22.4 Signal Description Not applicable. 22.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 22.5.1 I/O Lines Not applicable. 22.5.2 Power Management The DMAC will continue to operate in any Sleep mode (Idle, Standby Sleep) where the selected source clock is running. The DMACs interrupts can be used to wake up the device from Sleep modes. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. On hardware or software Reset, all registers are set to their Reset value. 22.5.3 Clocks An AHB clock (SYS_CLK) is required to clock the DMAC. The PB2_CLK is used when writing and reading the I/O registers of the DMAC. 22.5.4 DMA Not applicable. 22.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 477 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.5.6 Events The events are connected to the event system, see Event System (EVSYS) from Related Links. Related Links 26. Event System (EVSYS) 22.5.7 Debug Operation When the CPU is halted in Debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to 22.8.6. DBGCTRL for details. 22.5.8 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Pending register (INTPEND) Channel Interrupt Flag Status and Clear register (CHINTFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. 22.5.9 Analog Connections Not applicable. 22.6 Functional Description 22.6.1 Principle of Operation The DMAC consists of a DMA module and a CRC module. 22.6.1.1 DMA The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes:

Figure 22-2. DMA Transfer Sizes Link Enabled Link Enabled Link Enabled Beat transfer Burst transfer Block transfer DMA transaction Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. A block transfer can be interrupted. Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list. A transfer descriptor describes how a block transfer must be carried out by the DMAC, and it must remain in SRAM

(see Transfer Descriptors from Related Links). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 478 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) The figure above shows several block transfers linked together, which are called linked descriptors (see Linked Descriptors from Related Links). A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer when the according DMA channel is granted access as the active channel again. For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an optional output event can be generated. When a transaction is completed, depending on the configuration, the DMA channel will either be suspended or disabled. Related Links 22.6.2.3. Transfer Descriptors 22.6.3.1. Linked Descriptors 22.6.1.2 CRC The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 22.6.3.8. CRC Operation for details. 22.6.2 Basic Operation 22.6.2.1 Initialization DMAC Initialization Before DMAC is enabled, it must be configured as defined below:

The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register. The SRAM address of where the write-back section must be located must be written to the Write-Back Memory Base Address (WRBADDR) register. Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register

(CTRL.LVLENx=1) DMA Channel Initialization Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as defined below:

DMA Channel Configuration:

The channel number of the DMA channel to configure must be written to the Channel Control A

(CHCTRLA) register. Trigger action must be selected by writing the Trigger Action bit field in the Channel Control A

(CHCTRLA.TRIGACT) register. Trigger source must be selected by writing the Trigger Source bit field in the Channel Control A

(CHCTRLA.TRIGSRC) register. Transfer Descriptor The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control (BTCTRL.BEATSIZE) register. The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control

(BTCTRL.VALID) register. Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register. Source address for the block transfer must be selected by writing the Block Transfer Source Address

(SRCADDR) register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 479 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register. CRC Calculation If CRC calculation is needed, the CRC engine must be configured before it is enabled, as described below:

The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control

(CRCCTRL.CRCSRC) register. The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control

(CRCCTRL.CRCPOLY) register. If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control (CRCCTRL.CRCBEATSIZE) register. Register Properties The following DMAC registers are enable-protected, that is, they can only be written when the DMAC is disabled

(CTRL.DMAENABLE=0):

The Descriptor Base Memory Address (BASEADDR) register The Write-Back Memory Base Address (WRBADDR) register The following DMAC bit is enable-protected, that is, it can only be written when the DMAC and CRC are disabled

(CTRL.DMAENABLE=0 and CRCCTRL.CRCSRC=0):

The Software Reset bit in the Control (CTRL.SWRST) register The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled:

The Channel Software Reset bit in the Channel Control A (CHCTRLA.SWRST) register The following CRC registers are enable-protected, that is, they can only be written when the CRC is disabled

(CRCCTRL.CRCSRC=0):

The CRC Control (CRCCTRL) register CRC Checksum (CRCCHKSUM) register Enable-protection is denoted by the Enable-Protected property in the register description. 22.6.2.2 Enabling, Disabling, and Resetting The DMAC is enabled by writing the DMA Enable bit in the Control (CTRL.DMAENABLE) register to '1'. The DMAC is disabled by writing a '0' to the CTRL.DMAENABLE register. A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to

'1', after the corresponding channel ID to the channel is configured. A DMA channel is disabled by writing a '0' to CHCTRLAn.ENABLE. The CRC is enabled by writing a value to the CRC Source bits in the Control register (CRCCTRL.CRCSRC). The CRC is disabled by writing a '0' to CRCCTRL.CRCSRC. The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state. A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register

(CHCTRLAn.SWRST), after the corresponding channel is configured. The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the Reset to take effect. 22.6.2.3 Transfer Descriptors The transfer descriptors, together with the channel configurations, decide how a block transfer must be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one) and receives a transfer trigger, its first transfer descriptor must be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 480 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address

(BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see the following figure). All first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel number (see Linked Descriptors from Related Links). The write-back memory section is where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors are stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0 (see Linked Descriptors from Related Links). Figure 22-3. Memory Sections DESCADDR Channel 0 Last Descriptor DESCADDR Channel 0 Descriptor n-1 Descriptor Section Channel n First Descriptor Channel 2 First Descriptor Channel 1 First Descriptor Channel 0 First Descriptor BASEADDR Write-Back Section Channel n Ongoing Descriptor Channel 2 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 0 Ongoing Descriptor Device Memory Space WRBADDR 0x00000000 DSTADDR SRCADDR BTCNT BTCTRL DESCADDR DSTADDR SRCADDR BTCNT BTCTRL DESCADDR DSTADDR SRCADDR BTCNT BTCTRL Undefined Undefined Undefined Undefined Undefined The size of the descriptor and write-back memory sections are dependent on the number of the most significant enabled DMA channel m, as shown below:

For memory optimization, it is recommended to use the less significant DMA channels, if not all channels are Size = 128bits m + 1 required. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 481 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) The descriptor and write-back memory sections can either be two separate memory sections, or they can share a memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. Related Links 22.6.3.1. Linked Descriptors 22.6.2.4 Arbitration If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers

(PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The next transfer descriptor will be fetched from SRAM memory and stored internally in the Pre-Fetch Channel. The active channel is the DMA channel being granted access to perform its next burst transfer. When the Active Channel has completed a burst transfer, the descriptor stored in the Pre-Fetch Channel is transferred to the Active Channel and a new burst will take place. When the descriptor stored in the Pre-Fetch Channel is transferred to the Active Channel, the corresponding PENDCH.PENDCHx will be cleared. In the same way, depending on trigger action settings and if the upcoming burst transfer is the first for the transfer request or not, the corresponding Busy Channel x bit in the Busy Channels register (BUSYCH.BUSYCHx), will either be set or remain 1. When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel and block transfer configuration. If the DMA channel is set to wait for a new transfer trigger, suspended or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. The status will also be indicated in CHINTFLAGn.SUSP. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. Figure 22-4. Arbiter Overview Channel 0 Channel N Channel Pending Channel Suspend Channel Priority Level Channel Burst Done Channel Pending Channel Suspend Channel Priority Level Channel Burst Done Arbiter Priority decoder Channel Number Empty Pre-Fetch Channel Level Enable CTRL.LVLENx ACTIVE.LVLEXx PRICTRLx.LVLPRI Active Channel e n o D t s r u B Host Interface Burst Transfer Priority Levels When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx). Each DMA channel supports up to 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Priority Level register (CHPRILVL.PRILVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. A priority level is enabled by writing the Priority Level x Enable bit in the Control register (CTRL.LVLENx) to 1, for the corresponding level. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 482 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Within each priority level, the DMAC's arbiter can be configured to prioritize statically or dynamically. For the arbiter to perform static arbitration within a priority level, the Level X Round-Robin Scheduling Enable bit in the Priority Control x register (PRICTRL0.RRLVLENx) has to be written to 0. When static arbitration is enabled (PRICTRL0.RRLVLENx is 0), the arbiter will prioritize a low channel number over a high channel number as shown in the following figure. When using the static scheme, there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. Figure 22-5. Static Priority Scheduling Lowest Channel Channel 0 Highest Priority

. Channel x Channel x+1

. Highest Channel Channel N Lowest Priority The dynamic arbitration scheme in the DMAC is round-robin. Round-robin arbitration is enabled by writing PRICTRL0.RRLVLEN to 1, for a given priority level x. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in the following figure. The channel number of the last channel being granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register (PRICTRL0.LVLPRIx) for the corresponding priority level. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 483 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Figure 22-6. Dynamic (Round-Robin) Priority Scheduling Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel 0 Channel x Channel x+1 Lowest Priority Highest Priority Channel N 22.6.2.5 Data Transmission

. Channel x Channel x+1 Channel x+2

. Channel N Lowest Priority Highest Priority Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel. Once the arbiter has granted a DMA channel access as the active channel (see DMAC Block Diagram in the Block Diagram from Related Links) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated (see Addressing from the Related Links). The arbitration procedure is performed after each transfer. If the current DMA channel is granted access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will perform a new transfer. If a different DMA channel than the current active channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register

(DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel. Related Links 22.3. Block Diagram 22.6.2.7. Addressing 22.6.2.6 Transfer Triggers and Actions A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel n Control A

(CHCTRLAn.TRIGSRC). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 484 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) The trigger actions are available in the Trigger Action bit group in the Channel n Control A register

(CHCTRLAn.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor in the list is executed. As long as the list still has descriptors to execute, the channel will be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions can also be configured to generate a request for a burst transfer (CHCTRLAn.TRIGACT=0x2) or transaction transfer

(CHCTRLAn.TRIGACT=0x3) instead of a block transfer (CHCTRLAn.TRIGACT=0x0). The following figure shows an example where triggers are used with two linked block descriptors. Figure 22-7. Trigger Action and Transfers Beat Trigger Action Trigger Lost CHENn Trigger PENDCHn BUSYCHn Data Transfer BEAT BEAT BEAT BEAT BEAT BEAT Block Transfer Block Transfer Block Trigger Action CHENn Trigger PENDCHn BUSYCHn Trigger Lost Data Transfer BEAT BEAT BEAT BEAT BEAT BEAT Block Transfer Block Transfer Transaction Trigger Action Trigger Lost CHENn Trigger PENDCHn BUSYCHn Data Transfer BEAT BEAT BEAT BEAT BEAT BEAT Block Transfer Block Transfer If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request will be kept pending (CHSTATUSn.PEND=1), and the new transfer can start after the ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel n Status register

(CHSTATUSn.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 485 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.6.2.7 Addressing Each block transfer needs to have both a source address and a destination address defined. The source address is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the Transfer Destination Address (DSTADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register

(BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat. When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:

If BTCTRL.STEPSEL=1:

If BTCTRL.STEPSEL=0:

SRCADDR = SRCADDRSTART + BTCNT BEATSIZE + 1 2 STEPSIZE SRCADDR = SRCADDRSTART + BTCNT BEATSIZE + 1 SRCADDRSTART is the source address of the first beat transfer in the block transfer BTCNT is the initial number of beats remaining in the block transfer BEATSIZE is the configured number of bytes in a beat STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0). Figure 22-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat. When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and calculated as follows:

where BTCTRL.STEPSEL is zero DSTADDR = DSTADDRSTART + BTCNT BEATSIZE + 1 2 STEPSIZE 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 486 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) where BTCTRL.STEPSEL is one DSTADDR = DSTADDRSTART + BTCNT BEATSIZE + 1 DSTADDRSTART is the destination address of the first beat transfer in the block transfer BTCNT is the initial number of beats remaining in the block transfer BEATSIZE is the configured number of bytes in a beat STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment destination address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0). Figure 22-9. Destination Address Increment DST Data Buffer a b c d 22.6.2.8 Internal FIFO To improve the bandwidth, the DMAC can support FIFO operation. When single-beat burst configuration is selected

(CHCTRALx.BURSTLEN = SINGLE), the channel waits until the FIFO can transmit or accept a single beat transfer before it requests a bus access to write to the destination address. In all other cases, the channel waits until the FIFO threshold is reached before it requests a bus access to write to the destination address. The threshold is configurable and can be set by writing the THRESHOLD bits in the Channel x Control A register. If the DMAC completes the read operations before the threshold is reached, the write to the destination is automatically enabled. If the FIFO is empty and the read from source is ongoing, the DMA will wait again until the FIFO threshold is reached before it requests a bus access to write the destination. 22.6.2.9 Error Handling If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register

(CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write-back memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register

(CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated. 22.6.3 Additional Features 22.6.3.1 Linked Descriptors A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors. Memory Sections illustrates how linked descriptors work (see Memory Sections figure in the Transfer Descriptors from Related Links). When the first block transfer is completed on DMA channel 0, the DMAC fetches the next 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 487 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) transfer descriptor, which is pointed to by the value stored in the Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR = 0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched from SRAM (see Data Transmission from Related Links). Related Links 22.6.2.5. Data Transmission 22.6.2.3. Transfer Descriptors 22.6.3.1.1 Adding Descriptor to the End of a List To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR =

0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor. 22.6.3.1.2 Modifying a Descriptor in a List In order to add descriptors to a linked list, the following actions must be performed:

Enable the Suspend interrupt for the DMA channel. Enable the DMA channel. 1. 2. 3. Reserve memory space in SRAM to configure a new descriptor. 4. Configure the new descriptor:

Set the next descriptor address (DESCADDR) Set the destination address (DESCADDR) Set the source address (SRCADDR) Configure the block transfer control (BTCTRL) including Optionally enable the suspend block action Set the descriptor VALID bit 5. Clear the VALID bit for the existing list and for the descriptor which has to be updated. 6. Read DESCADDR from the write-back memory. If the DMA has not already fetched the descriptor that requires changes (in other words, DESCADDR is wrong):

Update the DESCADDR location of the descriptor from the list Optionally clear the suspend block action Set the descriptor VALID bit to 1 Optionally enable the Resume Software command If the DMA is executing the same descriptor as the one that requires changes:

Set the Channel Suspend Software command and wait for the suspend interrupt Update the next descriptor address (DESCADDR) in the write-back memory Clear the interrupt sources and set the Resume Software command Update the DESCADDR location of the descriptor from the list Optionally clear the suspend block action Set the descriptor VALID bit to 1 7. Go to step 4 if needed. 22.6.3.1.3 Adding a Descriptor Between Existing Descriptors To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. 2. If DMA is executing descriptor B, descriptor C cannot be inserted. If DMA has not started to execute descriptor A, follow the steps:

a. Set the descriptor A VALID bit to '0'. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B. Set the DESCADDR value of descriptor C to point to descriptor B. Set the descriptor A VALID bit to '1'. b. c. d. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 488 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 3. If DMA is executing descriptor A:

a. b. c. Apply the software suspend command to the channel and Perform steps 2.1 through 2.4. Apply the software resume command to the channel. 22.6.3.2 Transfer Quality of Service Each priority level group has dedicated quality of service settings. The setting can be written in the corresponding Quality of Service bit group in the Priority Control x register (PRICTRL0.QOSn). Figure 22-10. Quality of Service Transfer Trigger Channel 0 Transfer Trigger Channel 1 Fetch Operation CH0 CH1 CH0 CH1 Data Transfer Active CH0 Active CH1 Active CH0 Active CH1 Quality of Service Value

( QOS CH0 < QOS CH1) QOS CH0 QOS CH1 QOS CH0 QOS CH1 When a channel is stored in the Pre-Fetch or Active Channel, the corresponding PRICTRLx.QOS bits value is stored in the respective channel. As shown in Quality of Service, the DMAC will select the highest QOS value between Active and Pre-Fetch channels. This value will apply to all DMAC buses. 22.6.3.3 Channel Suspend The channel operation can be suspended at any time by software by writing a 1 to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set

(CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated. By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register

(BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register (CHASTATUS.FERR) will be set. Note:Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored. For more details on transfer descriptors (see Transfer Descriptors from Related Links). Related Links 22.6.2.3. Transfer Descriptors 22.6.3.4 Channel Resume and Next Suspend Skip A channel operation can be resumed by software by setting the Resume command in the Command bit field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 489 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Figure 22-11. Channel Suspend/Resume Operation CHENn Memory Descriptor Descriptor 0

(suspend disabled) Descriptor 1

(suspend enabled) Descriptor 2

(suspend enabled) Descriptor 3

(last) Channel suspended Block Transfer 0 Block Transfer 1 Block Transfer 2 Block Transfer 3 Suspend skipped Transfer Fetch Resume Command 22.6.3.5 Event Input Actions The event input actions are available only on the least significant DMA channels. For more details on channels with event input support (see Event System (EVSYS) from Related Links). Before using event input actions, the event controller must be configured first according to the following table, and the Channel Event Input Enable bit in the Channel Event Control register (CHEVCTRL.EVIE) must be written to 1. See Events from Related Links. Table 22-1. Event Input Action Action None Normal Transfer Conditional Transfer on Strobe Conditional Transfer Conditional Block Transfer Channel Suspend Channel Resume Skip Next Block Suspend Increase priority CHEVCTRL.EVACT CHCTRLA.TRIGSRC DISABLE Any peripheral NOACT TRIG TRIG CTRIG CBLOCK SUSPEND RESUME SSKIP INCPRI Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost. The following figure shows an example where beat transfers are enabled by internal events. Figure 22-12. Burst Event Trigger Action Peripheral Trigger Trigger Lost Event PENDCHn BUSYCHn Data Transfer Block Transfer Block Transfer BURST BURST BURST BURST BURST BURST 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 490 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Conditional Transfer on Strobe The event input is used to trigger a transfer on peripherals with pending transfer requests. This event action is intended to be used with peripheral triggers, for example, for timed communication protocols or periodic transfers between peripherals: only when the peripheral trigger coincides with the occurrence of a (possibly cyclic) event the transfer is issued. The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the previous trigger action is completed (in other words, the channel is not pending) and when an active event is received. If the peripheral trigger is active, the DMA waits for an event before the peripheral trigger is internally registered. When both event and peripheral transfer trigger are active, both CHSTATUS.PEND and PENDCH.PENDCHn are set. A software trigger will now trigger a transfer. The following figure shows an example where the peripheral beat transfer is started by a conditional strobe event action. Figure 22-13. Periodic Event with Burst Peripheral Triggers Trigger Lost Trigger Lost Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BURST Conditional Transfer The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and the second peripheral is the source of the trigger. Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally, the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending Channel n Bit in the Pending Channels register is set (PENDCH.PENDCHn), and the event is acknowledged. A software trigger will now trigger a transfer. The following figure shows an example where conditional event is enabled with peripheral beat trigger requests. Figure 22-14. Conditional Event with Burst Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BURST BURST Conditional Block Transfer The event input is used to trigger a conditional block transfer on peripherals. Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 491 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) The following figure shows an example where conditional event block transfer is started with peripheral beat trigger requests. Figure 22-15. Conditional Block Transfer with Burst Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer Block Transfer BURST BURST BURST BURST Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB access is completed. For more details on Channel Suspend (see Channel Suspend from Related Links). Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. See Channel Suspend from Related Links. Skip Next Block Suspend This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged. Increase priority This event can be used to increase a channel priority and to request higher quality of service (QOS), when critical transfers must be done. When the event is detected, the channel will have the highest priority and the output Quality of Service value is internally forced to the maximum value. The event is acknowledged when the trigger action execution is completed. When acknowledged, the channel will recover its initial priority level and quality of service settings. Related Links 22.6.3.3. Channel Suspend 22.6.6. Events 26. Event System (EVSYS) 22.6.3.6 Event Output Selection The event output selections are available only for channels supporting event outputs. The Channel Event Output Enable can be set in the corresponding Channel n Event Control register

(CHEVCTRL.EVOE). The Event Output Mode bits in the Channel n Event Control register (CHEVCTRL.EVOMODE) selects the event type the channel will generate. The transfer events (CHEVCTRL.EVOMODE = DEFAULT) are strobe events and their duration is one CLK_DMAC_AHB clock period. The transfer event type selection is available in each Descriptor Block Control location (BTCTRL.EVOSEL). Block or burst event output generation is supported. The trigger action event (CHEVCTRL.EVOMODE = TRIGACT) is a level, active while the trigger action execution is not completed. Block Event Output When the block event output is selected, an event strobe is generated when the block transfer is completed. The pulse width of a block event output from a channel is one AHB clock cycle. It is also possible to use this event type 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 492 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) to generate an event when the transaction is complete. For this type of application, the block event selection must be set in the last transfer descriptor only, as shown below. Figure 22-16. Block Event Output Generation Block Transfer Block Transfer BURST BURST BURST BURST Data Transfer Event Output Burst Event Output When the burst event output is selected, an event strobe is generated when each burst transfer within the corresponding block is completed. The pulse width of a burst event output from a channel is one AHB clock cycle. The figure below shows an example where the burst event output is set in the second descriptor of a linked list. Figure 22-17. Burst Event Output Generation Block Transfer Block Transfer BURST BURST BURST BURST Data Transfer Event Output Trigger Action Event Output When the trigger action event output is selected, an event level is generated. The event output is set when the transfer trigger occurred, and cleared when the corresponding trigger action is completed. The following figure shows an example for each trigger action type. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 493 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Figure 22-18. Trigger Action Event Output Generation Burst Trigger Action Event Output Transfer Trigger Data Transfer Event Output Block Transfer BURST BURST BURST Block Trigger Action Event Output Transfer Trigger Data Transfer Event Output Block Transfer Block Transfer BURST BURST BURST BURST Transaction Trigger Action Event Output Transfer Trigger Data Transfer Event Output 22.6.3.7 Aborting Transfers Block Transfer Block Transfer BURST BURST BURST BURST Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC. When a DMA channel disable request or DMAC disable request is detected:

Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the write-back memory section is updated. This prevents transfer corruption before the channel is disabled. All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled. 22.6.3.8 CRC Operation A Cyclic Redundancy Check (CRC) is an error detection technique used to find errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the data is received, the device or application repeats the calculation using the DSU's CRC engine. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 494 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32

(IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is n bits in length, and will detect the fraction 1-2-n of all longer error bursts. CRC-16:

Polynomial: x16+ x12+ x5+ 1 Hex value: 0x1021 CRC-32:

Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in CRC Generator Block Diagram. The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register

(CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input data in a byte by byte manner. Figure 22-19. CRC Generator Block Diagram DMAC Channels CRCDATAIN CRCCTRL 8 16 8 32 CRC-16 CRC-32 crc32 CHECKSUM bit-reverse +

complement Checksum read 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 495 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) CRC on DMA data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC engine. CRC using the I/O interface Before using the CRC engine with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set. 22.6.3.9 Memory CRC Generation When enabled, it is possible to automatically calculate a memory block checksum. When the channel is enabled and the descriptor is fetched, the CRC Checksum register (CRCCHKSUM) is reloaded with the initial checksum value (CHKINIT) stored in the Block Transfer Destination Address register (DSTADDR). The DMA read and calculate the checksum over the data from the source address.When the checksum calculation is completed, the CRC value is stored in the CRC Checksum register (CRCCHKSUM), the Transfer Complete interrupt flag is set

(CHINTFLAGn.TCMPL) and optional interrupt is generated. If linked descriptor is in the list (DESCADDR !=0), the DMA will fetch the next descriptor and CRC calculation continues as described above. When the last list descriptor is executed, the channel is automatically disabled. In order to enable the memory CRC generation, the following actions must be performed:

The CRC module must be set to be used with a DMA channel (CRCCTRL.CRCSRC) 1. 2. Reserve memory space addresses to configure a descriptor or a list of descriptors 3. Configure each descriptor:

Set the next descriptor address (DESCADDR) Set the destination address with the initial checksum value (DSTADDR = CHKINIT) in the first descriptior in a list Set the transfer source address (SRCADDR) Set the block transfer count (BTCNT) Set the memory CRC generation operation mode (CRCCTRL.CRCMODE = CRCGEN) Enable optional interrupts 4. Enable the corresponding DMA channel (CHCTRLAn.ENABLE) The figure below shows the CRC computation slots and descriptor configuration when single or linked-descriptors transfers are enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 496 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Figure 22-20. CRC Computation with Single Linked Transfers List with Single Descriptor List with Multiple Linked Descriptors Source Memory Source Memory Descriptor 0 0x0 0x2 0x4 0x8 0xc BTCTRL BTCNT = N SRCADDR =

ADDR 1 CHKINIT DESCADDR=

0x00000000 Transfer start address: ADDR1 - N Data 0 Data 1 Descriptor 0 Transfer start address: ADDR1 - N Data 0 Data 1 Desc of this buffer 0x0 0x2 0x4 0x8 0xc BTCTRL BTCNT = N SRCADDR =

ADDR 1 CHKINIT DESCADDR = next desc Desc of this buffer n o i t a t u p m o C C R C ADDR1 Data N-1 outside ADDR1 Data N-1 outside Data N Data N+ 1 Transfer start address: ADDR2 - M Descriptor n (last) 0x0 0x2 0x4 BTCTRL BTCNT = M SRCADDR =

ADDR 2 0x8 DONT CARE 0xc DESCADDR=

0x00000000 Desc of this buffer n o i t a t u p m o C C R C Notes :

Figures assumes that STEPSIZE is 0 (X1) T o ease understanding (buffer base address is SRCADDR minus BTCNT items). ADDR2 Data M-1 outside 22.6.3.10 Memory CRC Monitor When enabled, it is possible to continuously check a a memory block data integrity by calculating and checking the CRC checksum. The expected CRC checksum value must be located in the last memory block location, as shown in the table below:

CRCCTRL.CRCPOLY CRCCTRL.CRCBEATSIZE Last Memory Block Byte CHECKSUM Result Locations Value (MSB Byte First) CRC-16 CRC-32 Byte Half-word Word Byte Half-word Word Expected CRC[7:0]

Expected CRC[15:8]

0x00 0x00 Expected CRC[7:0]

Expected CRC[15:8]

Expected CRC[31:24]

Expected CRC[23:16]

Expected CRC[15:8]

Expected CRC[7:0]

0x00000000 CRC Magic Number

(0x2144DF1C) When the channel is enabled and the descriptor is fetched, the CRC Checksum register (CRCCHKSUM) is reloaded with the initial checksum value (CHKINIT), stored in the DSTADDR location of the first descriptor. The DMA read and calculate the checksum over the entire data from the source address. When the checksum calculation is completed the DMA read the last beat from the memory, the calculated CRC value from the CRC Checksum register is compared to zero or CRC magic number, depending on CRC polynomial selection. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 497 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) If the CHECKSUM does not match the comparison value the DMA channel is disabled, and both the CRC Error bit in the Channel n Status register (CHSTATUSn.CRCERR) and Transfer Error interrupt flag (CHINTFLAGn.TERR) are set. If enabled, the Transfer Error interrupt is generated. If the calculated checksum value matches the compare value, the Transfer Complete interrupt flag

(CHINTFLAGn.TCMPL) is set, optional interrupt is generated and the DMA will perform the following actions, depending on the descriptor list settings:

If the list has only one descriptor, the DMA will re-fetch the descriptor If the current descriptor is the last descriptor from the list, the DMA will fetch the first descriptor from the list When the fetch is completed, the DMA restarts the operations described above when new triggers are detected. In order to enable the memory CRC monitor, the following actions must be performed:

The CRC module must be set to be used with a DMA channel (CRCCTRL.CRCSRC) 1. 2. Reserve memory space addresses to configure a descriptor or a list of descriptors 3. Configure each descriptor Set the next descriptor address (DESCADDR) In the first list descriptor, set the destination address with the initial checksum value (DSTADDR =

CHKINIT) Set the transfer source address (SRCADDR) Set the block transfer count (BTCNT) Set the memory CRC monitor operation mode (CRCCTRL.CRCMODE = CRCMON) Enable optional interrupts 4. Enable the corresponding DMA channel (CHCTRLAn.ENABLE) Figure 22-21. CRC Computation and Check with Single or Linked Transfers List with Single Descriptor List with Multiple Linked Descriptors Source Memory Source Memory Transfer start address: ADDR1 - N Data 0 Data 1 Descriptor 0 Transfer start address: ADDR1 - N Data 0 Data 1 Descriptor 0 0x0 0x2 0x4 0x8 0xc BTCTRL BTCNT = N SRCADDR =

ADDR 1 CHKINIT DESCADDR=

0x00000000 Desc of this buffer n o i t a t u p m o C C R C Data N-2 Expected CRC ADDR1 outside 0x0 0x2 0x4 0x8 0xc BTCTRL BTCNT = N SRCADDR =

ADDR 1 CHKINIT DESCADDR

= next desc address Desc of this buffer n o i t a t u p m o C C R C Data N-1 ADDR1 outside Data N Data N+ 1 Transfer start address: ADDR2 - M Descriptor n (last) 0x0 0x2 0x4 BTCTRL BTCNT = M SRCADDR =

ADDR 2 0x8 DONT CARE 0xc DESCADDR=

0x00000000 Desc of this buffer n o i t a t u p m o C C R C Data M-2 Expected CRC ADDR2 outside Notes :

Figures assumes that STEPSIZE is 0 (X1). T o ease understanding, buffer base address is SRCADDR minus BTCNT items. 22.6.4 DMA Operation Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 498 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.6.5 Interrupts The DMAC channels have the following interrupt sources:

Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. See Data Transmission from Related Links. Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor has been fetched. See Error Handling from Related Links. Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. See Channel Suspend and Data Transmission from Related Links. Each interrupt source has an Interrupt flag associated with it. The Interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the Interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear Interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. See Nested Vector Interrupt Controller (NVIC) from Related Links. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which Interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register

(INTPEND), which provides the lowest channel number with pending interrupt and the respective Interrupt flags. Note:Interrupts must be globally enabled for interrupt requests to be generated. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 22.6.3.3. Channel Suspend 22.6.2.9. Error Handling 22.6.2.5. Data Transmission 22.6.6 Events The DMAC can generate the following output events:

Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. See Event Output Selection from Related Links. Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event. The DMAC can take the following actions on an input event:

Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled Channel Suspend Operation (SUSPEND): suspend a channel operation Channel Resume Operation (RESUME): resume a suspended channel operation Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition Increase Priority (INCPRI): increase channel priority Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. See Event Input Actions from Related Links for more details on event input actions. Note:Event input and outputs are not available for every channel. See Features from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 499 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Related Links 22.2. Features 22.6.3.5. Event Input Actions 22.6.3.6. Event Output Selection 22.6.7 Sleep Mode Operation DMAC will behave as in DREAM mode. See Dream Mode from Related Links. Related Links 14.3.1.4. Dream Mode 22.6.8 Synchronization Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 500 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.7 Register Summary See DMAC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRL 0x02 CRCCTRL 0x04 CRCDATAIN 0x08 CRCCHKSUM 0x0C 0x0D 0x0E

... 0x0F CRCSTATUS DBGCTRL Reserved 0x10 SWTRIGCTRL 0x14 PRICTRL0 0x18

... 0x1F 0x20 0x22

... 0x23 Reserved INTPEND Reserved 0x24 INTSTATUS 0x28 BUSYCH 0x2C PENDCH 0x30 ACTIVE 0x34 BASEADDR 7:0 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 CRCMODE[1:0]

LVLENx3 LVLENx2 LVLENx1 LVLENx0 DMAENABLE SWRST CRCPOLY[1:0]

CRCSRC[5:0]

CRCBEATSIZE[1:0]

CRCDATAIN[7:0]

CRCDATAIN[15:8]

CRCDATAIN[23:16]

CRCDATAIN[31:24]

CRCCHKSUM[7:0]

CRCCHKSUM[15:8]

CRCCHKSUM[23:16]

CRCCHKSUM[31:24]

SWTRIGn[7:0]

SWTRIGn[15:8]

CRCERR CRCZERO CRCBUSY DBGRUN RRLVLEN0 RRLVLEN1 RRLVLEN2 RRLVLEN3 QOS00[1:0]

QOS01[1:0]

QOS02[1:0]

QOS03[1:0]

LVLPRI0[4:0]

LVLPRI1[4:0]

LVLPRI2[4:0]

LVLPRI3[4:0]

PEND BUSY FERR CRCERR ID[4:0]

SUSP TCMPL TERR CHINTn[7:0]

CHINTn[15:8]

BUSYCHn[7:0]

BUSYCHn[15:8]

PENDCHn[7:0]

PENDCHn[15:8]

ABUSY ID[4:0]

LVLEXx3 LVLEXx2 LVLEXx1 LVLEXx0 BTCNT[7:0]

BTCNT[15:8]

BASEADDR[7:0]

BASEADDR[15:8]

BASEADDR[23:16]

BASEADDR[31:24]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 501 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 0x38 WRBADDR 0x3C

... 0x3F Reserved 0x40 CHCTRLA0 0x44 0x45 0x46 0x47

... 0x4B 0x4C 0x4D 0x4E 0x4F CHCTRLB0 CHPRILVL0 CHEVCTRL0 Reserved CHINTENCLR0 CHINTENSET0 CHINTFLAG0 CHSTATUS0 0x50 CHCTRLA1 0x54 0x55 0x56 0x57

... 0x5B 0x5C 0x5D 0x5E 0x5F CHCTRLB1 CHPRILVL1 CHEVCTRL1 Reserved CHINTENCLR1 CHINTENSET1 CHINTFLAG1 CHSTATUS1 0x60 CHCTRLA2 0x64 0x65 0x66 0x67

... 0x6B 0x6C 0x6D 0x6E 0x6F CHCTRLB2 CHPRILVL2 CHEVCTRL2 Reserved CHINTENCLR2 CHINTENSET2 CHINTFLAG2 CHSTATUS2 0x70 CHCTRLA3 0x74 0x75 0x76 0x77

... 0x7B CHCTRLB3 CHPRILVL3 CHEVCTRL3 Reserved WRBADDR[7:0]

WRBADDR[15:8]

WRBADDR[23:16]

WRBADDR[31:24]

RUNSTDBY ENABLE SWRST TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 502 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 0x7C 0x7D 0x7E 0x7F CHINTENCLR3 CHINTENSET3 CHINTFLAG3 CHSTATUS3 0x80 CHCTRLA4 0x84 0x85 0x86 0x87

... 0x8B 0x8C 0x8D 0x8E 0x8F CHCTRLB4 CHPRILVL4 CHEVCTRL4 Reserved CHINTENCLR4 CHINTENSET4 CHINTFLAG4 CHSTATUS4 0x90 CHCTRLA5 0x94 0x95 0x96 0x97

... 0x9B 0x9C 0x9D 0x9E 0x9F CHCTRLB5 CHPRILVL5 CHEVCTRL5 Reserved CHINTENCLR5 CHINTENSET5 CHINTFLAG5 CHSTATUS5 0xA0 CHCTRLA6 0xA4 0xA5 0xA6 0xA7

... 0xAB 0xAC 0xAD 0xAE 0xAF CHCTRLB6 CHPRILVL6 CHEVCTRL6 Reserved CHINTENCLR6 CHINTENSET6 CHINTFLAG6 CHSTATUS6 0xB0 CHCTRLA7 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

0xB4 0xB5 0xB6 0xB7

... 0xBB 0xBC 0xBD 0xBE CHCTRLB7 CHPRILVL7 CHEVCTRL7 Reserved CHINTENCLR7 CHINTENSET7 CHINTFLAG7 7:0 7:0 7:0 2 SUSP SUSP SUSP FERR 1 TCMPL TCMPL TCMPL BUSY 0 TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP TCMPL TCMPL TCMPL TERR TERR TERR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 503 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 RUNSTDBY CRCERR FERR BUSY ENABLE PEND SWRST TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

0xBF CHSTATUS7 0xC0 CHCTRLA8 0xC4 0xC5 0xC6 0xC7

... 0xCB 0xCC 0xCD 0xCE 0xCF CHCTRLB8 CHPRILVL8 CHEVCTRL8 Reserved CHINTENCLR8 CHINTENSET8 CHINTFLAG8 CHSTATUS8 0xD0 CHCTRLA9 0xD4 0xD5 0xD6 0xD7

... 0xDB 0xDC 0xDD 0xDE 0xDF CHCTRLB9 CHPRILVL9 CHEVCTRL9 Reserved CHINTENCLR9 CHINTENSET9 CHINTFLAG9 CHSTATUS9 0xE0 CHCTRLA10 0xE4 0xE5 0xE6 0xE7

... 0xEB 0xEC 0xED 0xEE 0xEF CHCTRLB10 CHPRILVL10 CHEVCTRL10 Reserved CHINTENCLR10 CHINTENSET10 CHINTFLAG10 CHSTATUS10 0xF0 CHCTRLA11 CHCTRLB11 CHPRILVL11 CHEVCTRL11 Reserved 0xF4 0xF5 0xF6 0xF7

... 0xFB 0xFC 0xFD 0xFE 0xFF CHINTENCLR11 CHINTENSET11 CHINTFLAG11 CHSTATUS11 7:0 7:0 7:0 7:0 SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND CRCERR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 504 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 RUNSTDBY ENABLE SWRST TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

RUNSTDBY CRCERR TRIGSRC[7:0]

TRIGACT[1:0]

THRESHOLD[1:0]

EVOE EVIE EVOMODE[1:0]

BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND ENABLE SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY ENABLE TERR TERR TERR PEND SWRST BURSTLEN[3:0]

CMD[1:0]

PRILVL[1:0]

EVACT[2:0]

0x0100 CHCTRLA12 0x0104 0x0105 0x0106 0x0107

... 0x010B 0x010C 0x010D 0x010E 0x010F CHCTRLB12 CHPRILVL12 CHEVCTRL12 Reserved CHINTENCLR12 CHINTENSET12 CHINTFLAG12 CHSTATUS12 0x0110 CHCTRLA13 0x0114 0x0115 0x0116 0x0117

... 0x011B 0x011C 0x011D 0x011E 0x011F CHCTRLB13 CHPRILVL13 CHEVCTRL13 Reserved CHINTENCLR13 CHINTENSET13 CHINTFLAG13 CHSTATUS13 0x0120 CHCTRLA14 0x0124 0x0125 0x0126 0x0127

... 0x012B 0x012C 0x012D 0x012E 0x012F CHCTRLB14 CHPRILVL14 CHEVCTRL14 Reserved CHINTENCLR14 CHINTENSET14 CHINTFLAG14 CHSTATUS14 0x0130 CHCTRLA15 CHCTRLB15 CHPRILVL15 CHEVCTRL15 Reserved 0x0134 0x0135 0x0136 0x0137

... 0x013B 0x013C 0x013D 0x013E 0x013F CHINTENCLR15 CHINTENSET15 CHINTFLAG15 CHSTATUS15 7:0 7:0 7:0 7:0 Related Links 7. Product Memory Mapping Overview SUSP SUSP SUSP FERR TCMPL TCMPL TCMPL BUSY TERR TERR TERR PEND CRCERR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 505 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. See Register Access Protection from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the "Enable-Protected" property in each individual register description. Related Links 22.5.8. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 506 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.1 Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRL 0x00 0x0000 Bit 15 14 13 12 Access Reset 11 LVLENx3 R/W 0 10 LVLENx2 R/W 0 9 LVLENx1 R/W 0 Bit 7 6 5 4 3 2 Access Reset Bits 8, 9, 10, 11 LVLENxxPriority Level x Enable 1 DMAENABLE R/W 0 8 LVLENx0 R/W 0 0 SWRST R/W 0 When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, see Arbitration from Related Links. These bits are not enable-protected. Value 0 1 Description Transfer requests for Priority level x will not be handled. Transfer requests for Priority level x will be handled. Bit 1 DMAENABLEDMA Enable Setting this bit will enable the DMA module. Writing a 0 to this bit will disable the DMA module. When writing a 0 during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit when the DMAC module is disabled (DMAENABLE bit set to 0 ), resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value 0 1 Description There is no Reset operation ongoing. A Reset operation is ongoing. Related Links 22.6.2.4. Arbitration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 507 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.2 CRC Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CRCCTRL 0x02 0x0000 Bit 15 14 CRCMODE[1:0]

Access Reset R/W 0 Bit 7 Access Reset R/W 0 6 13 R/W 0 5 12 R/W 0 4 11 10 CRCSRC[5:0]

R/W 0 3 R/W 0 2 9 R/W 0 1 8 R/W 0 0 CRCPOLY[1:0]

R/W 0 R/W 0 CRCBEATSIZE[1:0]

R/W R/W 0 0 Bits 15:14 CRCMODE[1:0]CRC Operating Mode These bits define the block transfer mode. Value 0x0 0x1 0x2 0x3 CRCMON CRCGEN Name DEFAULT Description Default operating mode Reserved Memory CRC monitor operating mode Memory CRC generation operating mode Bits 13:8 CRCSRC[5:0]CRC Input Source Name NOACT IO Description No action I/O interface Reserved These bits select the input source for generating the CRC. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Value 0x00 0x01 0x02 -

0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F DMA channel 0 DMA channel 1 DMA channel 2 DMA channel 3 DMA channel 4 DMA channel 5 DMA channel 6 DMA channel 7 DMA channel 8 DMA channel 9 DMA channel 10 DMA channel 11 DMA channel 12 DMA channel 13 DMA channel 14 DMA channel 15 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 Bits 3:2 CRCPOLY[1:0]CRC Polynomial Type These bits select the CRC polynomial type. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 508 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Value 0x0 0x1 0x2-0x3 Name CRC16 CRC32 Description CRC-16 (CRC-CCITT) CRC32 (IEEE 802.3) Reserved Bits 1:0 CRCBEATSIZE[1:0]CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value 0x0 0x1 0x2 0x3 Description 8-bit bus transfer 16-bit bus transfer 32-bit bus transfer Reserved Name BYTE HWORD WORD 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 509 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.3 CRC Data Input Name:

Offset:

Reset:

Property: PAC Write Protection CRCDATAIN 0x04 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 CRCDATAIN[31:24]

R/W R/W 0 0 20 19 CRCDATAIN[23:16]

R/W R/W 0 0 11 12 CRCDATAIN[15:8]

R/W 0 R/W 0 4 3 CRCDATAIN[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 CRCDATAIN[31:0]CRC Data Input These bits store the data for which the CRC checksum is computed. A new CRC checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 510 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.4 CRC Checksum Name:

Offset:

Reset:

Property: PAC Write Protection, Enable-Protected CRCCHKSUM 0x08 0x00000000 The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared

(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set

(i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content. Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 CRCCHKSUM[31:24]

R/W R/W 0 0 20 19 CRCCHKSUM[23:16]

R/W R/W 0 0 12 11 CRCCHKSUM[15:8]

R/W R/W 0 0 4 3 CRCCHKSUM[7:0]

R/W R/W 0 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 CRCCHKSUM[31:0]CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 511 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.5 CRC Status Name:

Offset:

Reset:

Property: PAC Write-Protection CRCSTATUS 0x0C 0x00 Bit 7 6 5 4 3 Access Reset 2 CRCERR R 0 1 CRCZERO R 0 0 CRCBUSY R/W 0 Bit 2 CRCERRCRC Error This bit is read 1 when the memory CRC monitor detects data corruption. Bit 1 CRCZEROCRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero. Bit 0 CRCBUSYCRC Module Busy When used with an I/O interface (CRCCTRL.CRCSRC=0x1):

This bit is cleared by writing a 1 to it This bit is set when the CRC Data Input (CRCDATAIN) register is written Writing a 1 to this bit will clear the CRC Module Busy bit Writing a 0 to this bit has no effect When used with a DMA channel (CRCCTRL.CRCSRC=0x20..,0x3F):

This bit is cleared when the corresponding DMA channel is disabled This bit is set when the corresponding DMA channel is enabled Writing a 1 to this bit has no effect Writing a 0 to this bit has no effect 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 512 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.6 Debug Control DBGCTRL Name:

0x0D Offset:

Reset:

0x00 Property: PAC Write Protection Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNDebug Run This bit is not reset by a Software Reset. This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The DMAC is halted when the CPU is halted by an external debugger. The DMAC continues normal operation when the CPU is halted by an external debugger. DBGRUN R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 513 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.7 Software Trigger Control Name:

Offset:

Reset:

Property: PAC Write-Protection SWTRIGCTRL 0x10 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 SWTRIGn[15:8]

R/W 0 4 R/W 0 3 SWTRIGn[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 SWTRIGn[15:0]Channel n Software Trigger [n = 15..0]

This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a 1 to it. This bit is set if CHSTATUS.PEND is already 1 when writing a 1 to that bit. Writing a 0 to this bit will clear the bit. Writing a 1 to this bit will generate a DMA software trigger on channel n, if CHSTATUS.PEND = 0 for channel n. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 514 Microchip Confidential Confidential 22.8.8 Priority Control 0 Name:

Offset:

Reset:

Property: PAC Write-Protection PRICTRL0 0x14 0x40404040 Bit 31 RRLVLEN3 Access Reset R/W 0 Bit 23 RRLVLEN2 Access Reset R/W 0 Bit 15 RRLVLEN1 Access Reset R/W 0 Bit 7 RRLVLEN0 Access Reset R/W 0 QOS03[1:0]

QOS02[1:0]

QOS01[1:0]

QOS00[1:0]

30 R/W 1 22 R/W 1 14 R/W 1 6 R/W 1 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 LVLPRI3[4:0]

R/W 0 18 LVLPRI2[4:0]

R/W 0 10 LVLPRI1[4:0]

R/W 0 2 LVLPRI0[4:0]

R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 7, 15, 23, 31 RRLVLENLevel Round-Robin Scheduling Enable For details on arbitration schemes, see Arbitration from Related Links. Value 0 1 Description Static arbitration scheme for channels with level 0 priority. Round-robin arbitration scheme for channels with level 0 priority. Bits 5:6, 13:14, 21:22, 29:30 QOSLevel Quality of Service 0x0 0x1 0x2 0x3 DISABLE Background (no sensitive operation) LOW Sensitive to bandwidth MEDIUM Sensitive to latency Critical Latency Bits 0:4, 8:12, 16:20, 24:28 LVLPRILevel Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to 0). Related Links 22.6.2.4. Arbitration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 515 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.9 Interrupt Pending Name:

Offset:

Reset:

Property:

INTPEND 0x20 0x0000

This register allows the user to identify the lowest DMA channel with pending interrupt. An interrupt that handles several channels should consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register. Bit Access Reset 15 PEND R 0 14 BUSY R 0 13 FERR R 0 12 CRCERR R/W 0 Bit 7 6 5 Access Reset Bit 15 PENDPending 4 R/W 0 11 3 R/W 0 10 SUSP R/W 0 2 ID[4:0]

R/W 0 9 TCMPL R/W 0 1 R/W 0 8 TERR R/W 0 0 R/W 0 This bit will read '1' when the channel selected by Channel ID field (ID) is pending. Bit 14 BUSYBusy This bit will read '1' when the channel selected by Channel ID field (ID) is busy. Bit 13 FERRFetch Error This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor. Bit 12 CRCERRCRC Error This bit will read '1' when the channel selected by Channel ID field (ID) has a CRC Error Status Flag bit set, and is set when the CRC monitor detects data corruption. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID). Bit 10 SUSPChannel Suspend This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID). Bit 9 TCMPLTransfer Complete This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID). Bit 8 TERRTransfer Error This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field (ID). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 516 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Bits 4:0 ID[4:0]Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel

(with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 517 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.10 Interrupt Status Name:

Offset:

Reset:

Property:

INTSTATUS 0x24 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 CHINTn[15:8]

CHINTn[7:0]

12 R 0 4 R 0 11 R 0 3 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 CHINTn[15:0]Channel n Pending Interrupt [n=15..0]

This bit is set when Channel n has a pending interrupt/the interrupt request is received. This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 518 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.11 Busy Channels Name:

Offset:

Reset:

Property:

BUSYCH 0x28 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 12 11 BUSYCHn[15:8]

R R 0 0 4 3 BUSYCHn[7:0]

R 0 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 BUSYCHn[15:0]Busy Channel n [n=15..0]

This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel n is detected, or when DMA channel n is disabled. This bit is set when DMA channel n starts a DMA transfer. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 519 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.12 Pending Channels Name:

Offset:

Reset:

Property:

PENDCH 0x2C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 12 11 PENDCHn[15:8]

R R 0 0 4 3 PENDCHn[7:0]

R 0 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 PENDCHn[15:0]Pending Channel n [n=0..15]

This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT. This bit is set when a transfer is pending on DMA channel n. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 520 Microchip Confidential Confidential 22.8.13 Active Channel and Levels Name:

Offset:

Reset:

Property:

ACTIVE 0x30 0x00000000

Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 ABUSY R 0 30 R 0 22 R 0 14 29 R 0 21 R 0 13 Bit 7 6 5 Access Reset PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 28 R 0 20 R 0 12 R 0 4 BTCNT[15:8]

BTCNT[7:0]

27 R 0 19 R 0 11 R 0 3 LVLEXx3 R 0 26 R 0 18 R 0 10 ID[4:0]

R 0 2 LVLEXx2 R 0 25 R 0 17 R 0 9 R 0 24 R 0 16 R 0 8 R 0 1 LVLEXx1 R 0 0 LVLEXx0 R 0 Bits 31:16 BTCNT[15:0]Active Channel Block Transfer Count These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel access. The value is valid only when the active channel Active Busy flag (ABUSY) is set. Bit 15 ABUSYActive Channel Busy This bit is cleared when the active transfer count is written back in the write-back memory section. This bit is set when the next descriptor transfer count is read from the write-back memory section. Bits 12:8 ID[4:0]Active Channel ID These bits hold the channel index currently stored in the active channel registers. The value is updated each time the arbiter grants a new channel transfer access request. Bits 0, 1, 2, 3 LVLEXxxLevel x Channel Trigger Request Executing [x=3..0]

This bit is set when a level-x channel trigger request is executing or pending. This bit is cleared when no request is pending or being executed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 521 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.14 Descriptor Memory Section Base Address Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected BASEADDR 0x34 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 BASEADDR[31:24]

R/W R/W 0 0 20 19 BASEADDR[23:16]

R/W R/W 0 0 11 12 BASEADDR[15:8]

R/W 0 R/W 0 4 3 BASEADDR[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 BASEADDR[31:0]Descriptor Memory Base Address These bits store the Descriptor memory section base address. The value must be 64-bit aligned. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 522 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.15 Write-Back Memory Section Base Address Name:

Offset:

Reset:

Property: PAC Write Protection, Enable-Protected WRBADDR 0x38 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 WRBADDR[31:24]

R/W 0 R/W 0 20 19 WRBADDR[23:16]

R/W 0 R/W 0 11 12 WRBADDR[15:8]

R/W 0 R/W 0 4 3 WRBADDR[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 WRBADDR[31:0]Write-Back Memory Base Address These bits store the Write-Back memory base address. The value must be 64-bit aligned. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 523 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.16 Channel Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CHCTRLA 0x40 + n*0x10 [n=0..15]

0x00000000 Bit 31 30 Access Reset Bit 23 22 29 28 THRESHOLD[1:0]

R/W 0 21 R/W 0 20 TRIGACT[1:0]

Access Reset Bit 15 Access Reset R/W 0 Bit 7 Access Reset 14 R/W 0 6 RUNSTDBY R/W 0 R/W 0 13 R/W 0 5 Bits 29:28 THRESHOLD[1:0]FIFO Threshold 26 25 BURSTLEN[3:0]

27 R/W 0 19 11 R/W 0 12 TRIGSRC[7:0]

R/W 0 4 R/W 0 3 R/W 0 18 10 R/W 0 2 24 R/W 0 16 8 R/W 0 R/W 0 17 9 R/W 0 1 ENABLE R/W 0 0 SWRST R/W 0 These bits define the threshold from which the DMA starts to write to the destination. These bits have no effect in the case of single beat transfers. These bits are not enable-protected. Value 0x0 0x1 0x2 0x3 Description Destination write starts after each beat source addess read Destination write starts after 2-beats source address read Destination write starts after 4-beats source address read Destination write starts after 8-beats source address read Name 1BEAT 2BEATS 4BEATS 8BEATS Bits 27:24 BURSTLEN[3:0]Burst Length These bits define the burst mode. These bits are not enable-protected. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD Name SINGLE 2BEAT 3BEAT 4BEAT 5BEAT 6BEAT 7BEAT 8BEAT 9BEAT 10BEAT 11BEAT 12BEAT 13BEAT 14BEAT Description Single-beat burst 2-beats burst length 3-beats burst length 4-beats burst length 5-beats burst length 6-beats burst length 7-beats burst length 8-beats burst length 9-beats burst length 10-beats burst length 11-beats burst length 12-beats burst length 13-beats burst length 14-beats burst length 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 524 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) Value 0xE 0xF Name 15BEAT 16BEAT Description 15-beats burst length 16-beats burst length Bits 21:20 TRIGACT[1:0]Trigger Action These bits define the trigger action used for a transfer. These bits are not enable-protected. Value 0x0 0x1 0x2 0x3 BURST TRANSACTION Name BLOCK Description One trigger required for each block transfer Reserved One trigger required for each burst transfer One trigger required for each transaction Bits 15:8 TRIGSRC[7:0]Trigger Source These bits define the peripheral that will be the source of a trigger. Table 22-2. Triggers Map Number Name 0x00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 DISABLE; Only software/event triggers RTC_DMAC_ID_TIMESTAMP DSU_DMAC_ID_DCC0 DSU_DMAC_ID_DCC1 SERCOM0_DMAC_ID_RX SERCOM0_DMAC_ID_TX SERCOM1_DMAC_ID_RX SERCOM1_DMAC_ID_TX SERCOM2_DMAC_ID_RX SERCOM2_DMAC_ID_TX TCC0_DMAC_ID_OVF TCC0_DMAC_ID_MC_0 TCC0_DMAC_ID_MC_1 TCC0_DMAC_ID_MC_2 TCC0_DMAC_ID_MC_3 TCC0_DMAC_ID_MC_4 TCC0_DMAC_ID_MC_5 TCC1_DMAC_ID_OVF TCC1_DMAC_ID_MC_0 TCC1_DMAC_ID_MC_1 TCC1_DMAC_ID_MC_2 TCC1_DMAC_ID_MC_3 TCC1_DMAC_ID_MC_4 TCC1_DMAC_ID_MC_5 TCC2_DMAC_ID_OVF TCC2_DMAC_ID_MC_0 TCC2_DMAC_ID_MC_1 TC0_DMAC_ID_OVF TC0_DMAC_ID_MC_0 TC0_DMAC_ID_MC_1 TC1_DMAC_ID_OVF TC1_DMAC_ID_MC_0 TC1_DMAC_ID_MC_1 TC2_DMAC_ID_OVF TC2_DMAC_ID_MC_0 TC2_DMAC_ID_MC_1 TC3_DMAC_ID_OVF TC3_DMAC_ID_MC_0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 525 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC)

...........continued Number Name 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TC3_DMAC_ID_MC_1 TC4_DMAC_ID_OVF TC4_DMAC_ID_MC_0 TC4_DMAC_ID_MC_1 TC5_DMAC_ID_OVF TC5_DMAC_ID_MC_0 TC5_DMAC_ID_MC_1 TC6_DMAC_ID_OVF TC6_DMAC_ID_MC_0 TC6_DMAC_ID_MC_1 TC7_DMAC_ID_OVF TC7_DMAC_ID_MC_0 TC7_DMAC_ID_MC_1 QSPI_DMAC_ID_RX QSPI_DMAC_ID_TX Bit 6 RUNSTDBYChannel run in standby This bit is used to keep the DMAC channel running in standby sleep mode. This bit is not enable-protected. Value 0 1 Description The DMAC channel is halted in standby. The DMAC channel continues to run in standby. Bit 1 ENABLEChannel Enable Writing a 0 to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Writing a 1 to this bit will enable the DMA channel. This bit is not enable-protected. Value 0 1 Description DMA channel is disabled. DMA channel is enabled. Bit 0 SWRSTChannel Software Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a 1 to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 526 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.17 Channel Control B Name:

Offset:

Reset:

Property: PAC Write-Protection CHCTRLB 0x44 + n*0x10 [n=0..15]

0x00 Bit 7 6 5 4 3 2 Access Reset Bits 1:0 CMD[1:0]Software Command CMD[1:0]

1 R/W 0 0 R/W 0 These bits define the software commands. See Channel Suspend and Channel Resume and Next Suspend Skip from Related Links. These bits are not enable-protected. CMD[1:0]

0x0 0x1 0x2 0x3 Name NOACT SUSPEND RESUME

Description No action Channel suspend operation Channel resume operation Reserved Related Links 22.6.3.4. Channel Resume and Next Suspend Skip 22.6.3.3. Channel Suspend 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 527 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.18 Channel Priority Level Name:

Offset:

Reset:

Property: PAC Write-Protection CHPRILVL 0x45 + n*0x10 [n=0..15]

0x00 Bit 7 6 5 4 3 2 Access Reset Bits 1:0 PRILVL[1:0]Channel Priority Level PRILVL[1:0]

1 R/W 0 0 R/W 0 These bits define the priority level used for the DMA channel. The available levels are shown below, where a high level has priority over a low level. These bits are not enable-protected. Description Value Channel Priority Level 0 (Lowest Level) 0x0 Channel Priority Level 1 0x1 Channel Priority Level 2 0x2 Channel Priority Level 3 (Highest Level) 0x3 Name LVL0 LVL1 LVL2 LVL3 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 528 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.19 Channel Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CHEVCTRL 0x46 + n*0x10 [n=0..15]

0x00 Bit Access Reset 7 EVOE R/W 0 6 EVIE R/W 0 5 4 EVOMODE[1:0]

R/W 0 R/W 0 3 2 R/W 0 1 EVACT[2:0]

R/W 0 0 R/W 0 Bit 7 EVOEChannel Event Output Enable This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the Channel Event Output Selection bits (CHEVCTRL.EVOMODE). Value 0 1 Description Channel event generation is disabled. Channel event generation is enabled. Bit 6 EVIEChannel Event Input Enable Value 0 1 Description Channel event action will not be executed on any incoming event. Channel event action will be executed on any incoming event. Bits 5:4 EVOMODE[1:0]Channel Event Output Mode These bits define the channel event output selection. For more details on event output generation, see Event Output Selection from Related Links. Value 0x0 0x1 0x2-0x3 Description Block event output selection. See BTCTRL.EVOSEL for available selections. Ongoing trigger action Reserved Name DEFAULT TRIGACT Bits 2:0 EVACT[2:0]Channel Event Input Action These bits define the event input action. The action is executed only if the corresponding EVIE bit in the CHEVCTRL register of the channel is set. For more details on event actions, see Event Input Actions from Related Links. These bits are available only for channels with event input support. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description No action Transfer and periodic transfer trigger Conditional transfer trigger Conditional block transfer Channel suspend operation Channel resume operation Skip next block suspend action Increase priority Name NOACT TRIG CTRIG CBLOCK SUSPEND RESUME SSKIP INCPRI Related Links 22.6.3.5. Event Input Actions 22.6.3.6. Event Output Selection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 529 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.20 Channel Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection CHINTENCLR 0x4C + n*0x10 [n=0..15]

0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. Bit 7 6 5 4 3 Access Reset Bit 2 SUSPChannel Suspend Interrupt Enable 2 SUSP R/W 0 1 TCMPL R/W 0 0 TERR R/W 0 Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt. Value 0 1 Description The Channel Suspend interrupt is disabled. The Channel Suspend interrupt is enabled. Bit 1 TCMPLChannel Transfer Complete Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt. Value 0 Description The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed. The Channel Transfer Complete interrupt is enabled. 1 Bit 0 TERRChannel Transfer Error Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Value 0 1 Description The Channel Transfer Error interrupt is disabled. The Channel Transfer Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 530 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.21 Channel Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection CHINTENSET 0x4D + n*0x10 [n=0..15]

0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. Bit 7 6 5 4 3 Access Reset Bit 2 SUSPChannel Suspend Interrupt Enable 2 SUSP R/W 0 1 TCMPL R/W 0 0 TERR R/W 0 Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend interrupt. Value 0 1 Description The Channel Suspend interrupt is disabled. The Channel Suspend interrupt is enabled. Bit 1 TCMPLChannel Transfer Complete Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel Transfer Complete interrupt. Value 0 1 Description The Channel Transfer Complete interrupt is disabled. The Channel Transfer Complete interrupt is enabled. Bit 0 TERRChannel Transfer Error Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Value 0 1 Description The Channel Transfer Error interrupt is disabled. The Channel Transfer Error interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 531 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.22 Channel Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

CHINTFLAG 0x4E + n*0x10 [n=0..15]

0x00

Bit 7 6 5 4 3 Access Reset Bit 2 SUSPChannel Suspend 2 SUSP R/W 0 1 TCMPL R/W 0 0 TERR R/W 0 This flag is cleared by writing a 1 to it. This flag is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Channel Suspend interrupt flag for the corresponding channel. For details on available software commands, see CHCTRLB in the DMAC Register Summary from Related Links. For details on available event input actions, see CHCTRLB in the DMAC Register Summary from Related Links. For details on available block actions, see BTCTRL in the DMAC Register Summary (SRAM) from Related Links. Bit 1 TCMPLChannel Transfer Complete This flag is cleared by writing a 1 to it. This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Transfer Complete interrupt flag for the corresponding channel. Bit 0 TERRChannel Transfer Error This flag is cleared by writing a 1 to it. This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Transfer Error interrupt flag for the corresponding channel. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 532 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.8.23 Channel Status Name:

Offset:

Reset:

Property:

CHSTATUS 0x4F + n*0x10 [n=0..15]

0x00

Bit 7 6 5 4 Access Reset Bit 3 CRCERRChannel CRC Error 3 CRCERR R/W 0 2 FERR R 0 1 BUSY R 0 0 PEND R 0 This bit is set when the CRC monitor detects data corruption. This bit is cleared by writing 1 to it, or by clearing the CRC Error bit in the INTPEND register (INTPEND.CRCERR). See INTPEND in the DMAC Register Summary from Related Links. Bit 2 FERRChannel Fetch Error This bit is cleared when a software resume command is executed. This bit is set when an invalid descriptor is fetched. Bit 1 BUSYChannel Busy This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled. This bit is set when the DMA channel starts a DMA transfer. Bit 0 PENDChannel Pending This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, see CHCTRLB in the DMAC Register Summary from Related Links. This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 533 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.9 DMAC Register Summary (SRAM) Offset Name Bit Pos. 7 6 5 4 3 2 1 0x00 BTCTRL 0x02 BTCNT 0x04 SRCADDR 0x08 DSTADDR 0x0C DESCADDR 7:0 15:8 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0 VALID BLOCKACT[1:0]

EVOSEL[1:0]

STEPSIZE[2:0]

STEPSEL DSTINC SRCINC BEATSIZE[1:0]

BTCNT[7:0]

BTCNT[15:8]

SRCADDR[7:0]

SRCADDR[15:8]

SRCADDR[23:16]

SRCADDR[31:24]

DSTADDR[7:0]

DSTADDR[15:8]

DSTADDR[23:16]

DSTADDR[31:24]

DESCADDR[7:0]

DESCADDR[15:8]

DESCADDR[23:16]

DESCADDR[31:24]

22.10 Register Description - SRAM Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. See Register Access Protection from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the "Enable-Protected" property in each individual register description. Related Links 22.5.8. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 534 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.10.1 Block Transfer Control Name:

Offset:

Reset:

Property:

BTCTRL 0x00 0x0000

The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 Access Reset R/W 0 14 STEPSIZE[2:0]

R/W 0 Bit 7 6 13 R/W 0 5 Access Reset 12 STEPSEL R/W 0 11 DSTINC R/W 0 3 4 BLOCKACT[1:0]

R/W 0 R/W 0 Bits 15:13 STEPSIZE[2:0]Address Increment Step Size 10 SRCINC R/W 0 2 9 8 BEATSIZE[1:0]

R/W 0 1 R/W 0 0 VALID R/W 0 EVOSEL[1:0]

R/W 0 R/W 0 These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Next ADDR = ADDR + (Beat size in byte) * 1 Next ADDR = ADDR + (Beat size in byte) * 2 Next ADDR = ADDR + (Beat size in byte) * 4 Next ADDR = ADDR + (Beat size in byte) * 8 Next ADDR = ADDR + (Beat size in byte) * 16 Next ADDR = ADDR + (Beat size in byte) * 32 Next ADDR = ADDR + (Beat size in byte) * 64 Next ADDR = ADDR + (Beat size in byte) * 128 Name X1 X2 X4 X8 X16 X32 X64 X128 Bit 12 STEPSELStep Selection This bit selects if source or destination addresses are using the step size settings. Value 0x0 0x1 Description Step size settings apply to the destination address Step size settings apply to the source address Name DST SRC Bit 11 DSTINCDestination Address Increment Enable Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register. Value 0 1 Description The Destination Address Increment is disabled The Destination Address Increment is enabled Bit 10 SRCINCSource Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register. Value 0 1 Description The Source Address Increment is disabled The Source Address Increment is enabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 535 Microchip Confidential Confidential Bits 9:8 BEATSIZE[1:0]Beat Size PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses. Value 0x0 0x1 0x2 other Description 8-bit bus transfer 16-bit bus transfer 32-bit bus transfer Reserved Name BYTE HWORD WORD Bits 4:3 BLOCKACT[1:0]Block Action These bits define what actions the DMAC must take after a block transfer has completed. BLOCKACT[1:0] Name Description 0x0 0x1 0x2 0x3 NOACT INT Channel will be disabled if it is the last block transfer in the transaction Channel will be disabled if it is the last block transfer in the transaction and block interrupt SUSPEND Channel suspend operation is completed BOTH Both channel suspend operation and block interrupt Bits 2:1 EVOSEL[1:0]Event Output Selection These bits define the event output selection. EVOSEL[1:0]

0x0 0x1 0x2 0x3 Name DISABLE BLOCK BEAT Description Event generation disabled Event strobe when block transfer complete Reserved Event strobe when beat transfer complete Bit 0 VALIDDescriptor Valid Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor. The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Value 0 1 Description The descriptor is not valid The descriptor is valid 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 536 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.10.2 Block Transfer Count Name:

Offset:

Property:

BTCNT 0x02

The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 BTCNT[15:8]

R/W 0 4 R/W 0 BTCNT[7:0]

R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 BTCNT[15:0]Block Transfer Count This bit group holds the 16-bit block transfer count. During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 537 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.10.3 Block Transfer Source Address Name:

Offset:

Property:

SRCADDR 0x04

The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 Access Reset

0 Bit 23 Access Reset

0 Bit 15 Access Reset Bit Access Reset

0 7

0 30

0 22

0 14

0 6

0 29

0 21

0 13

0 5

0 28 27 SRCADDR[31:24]

0 0 20 19 SRCADDR[23:16]

0 0 11 12 SRCADDR[15:8]

0 0 4 3 SRCADDR[7:0]

0

0 26

0 18

0 10

0 2

0 25

0 17

0 9

0 1

0 24

0 16

0 8

0 0

0 Bits 31:0 SRCADDR[31:0]Transfer Source Address This bit field holds the block transfer source address. When source address incrementation is disabled (BTCTRL.SRCINC=0), SRCADDR corresponds to the last beat transfer address in the block transfer. When source address incrementation is enabled (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:

If BTCTRL.STEPSEL = 1:

If BTCTRL.STEPSEL= 0:

SRCADDR = SRCADDRSTART + BTCNT BEATSIZE + 1 2 STEPSIZE SRCADDR = SRCADDRSTART + BTCNT BEATSIZE + 1 SRCADDRSTART is the source address of the first beat transfer in the block transfer BTCNT is the initial number of beats remaining in the block transfer BEATSIZE is the configured number of bytes in a beat STEPSIZE is the configured number of beats for each incrementation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 538 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.10.4 Block Transfer Destination Address Name:

Offset:

Property:

DSTADDR 0x08

The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 31 Access Reset

0 Bit 23 Access Reset

0 Bit 15 Access Reset Bit Access Reset

0 7

0 30

0 22

0 14

0 6

0 29

0 21

0 13

0 5

0 28 27 DSTADDR[31:24]

0 0 20 19 DSTADDR[23:16]

0 0 12 11 DSTADDR[15:8]

0 0 DSTADDR[7:0]

4

0 3

0 26

0 18

0 10

0 2

0 25

0 17

0 9

0 1

0 24

0 16

0 8

0 0

0 Bits 31:0 DSTADDR[31:0]Transfer Destination Address This bit field holds the block transfer destination address. When destination address incrementation is disabled (BTCTRL.DSTINC = 0), DSTADDR corresponds to the last beat transfer address in the block transfer. When destination address incrementation is enabled (BTCTRL.DSTINC = 1), DSTADDR is calculated as follows:

If BTCTRL.STEPSEL = 1:

If BTCTRL.STEPSEL = 0:

DSTADDR = DSTADDRSTART + BTCNT BEATSIZE + 1 DSTADDR = DSTADDRSTART + BTCNT BEATSIZE + 1 2 DSTADDRSTART is the destination address of the first beat transfer in the block transfer BTCNT is the initial number of beats remaining in the block transfer BEATSIZE is the configured number of bytes in a beat STEPSIZE is the configured number of beats for each incrementation STEPSIZE 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 539 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Direct Memory Access Controller (DMAC) 22.10.5 Next Descriptor Address Name:

Offset:

Property:

DESCADDR 0x0C

The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit Access Reset Bit Access Reset 31

23

Bit 15 Access Reset Bit Access Reset

7

30

22

14

6

29

21

13

5

28 27 DESCADDR[31:24]

20 19 DESCADDR[23:16]

11 12 DESCADDR[15:8]

4 3 DESCADDR[7:0]

26

18

10

2

25

17

9

1

24

16

8

0

Bits 31:0 DESCADDR[31:0]Next Descriptor Address This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 540 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23. External Interrupt Controller (EIC) 23.1 Overview The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Also, each external pin can be configured to be asynchronous in order to wake-up the device from Sleep modes where all clocks have been disabled. External pins can generate an event. A separate Non-Maskable Interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the NVIC. 23.2 Features Interrupt on Rising, Falling, or Both Edges Up to four external pins (EXTINTx), plus one non-maskable pin (NMI) Dedicated, Individually Maskable Interrupt for Each Pin Synchronous or Asynchronous Edge Detection mode Asynchronous Interrupts for Sleep Modes Without Clock Filtering of External Pins Event Generation from EXTINTx Interrupt pin Debouncing Interrupt on High or Low Levels 23.3 Block Diagram Figure 23-1. EIC Block Diagram EXTINTx NMI FILTENx SENSEx[2:0]

Filter Edge/Level Detection NMIFILTEN NMISENSE[2:0]

Filter Edge/Level Detection intreq_extint Interrupt inwake_extint evt_extint Wake Event intreq_nmi Interrupt inwake_nmi Wake 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 541 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.4 Signal Description Signal Name EXTINT[3..0]

NMI Type Digital Input Digital Input Description External interrupt pin Non-maskable interrupt pin One signal may be available on several pins. 23.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 I/O Lines To use EICs I/O lines, configure the I/O pins using the I/O Peripheral Pin Select (PPS). 23.5.2 Power Management The EIC will continue to operate in any Sleep mode (Standby Sleep, Idle) where the selected source clock is running. The EICs interrupts can be used to wake up the device from Sleep modes. Events connected to the Event System can trigger other operations in the system without exiting Sleep modes. 23.5.3 Clocks The EIC bus clock (PB1_CLK) can be enabled and disabled by the CRU, the default state of PB1_CLK can be found in the CRU and PMD registers. Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra Low-Power 32 KHz clock (32KHz_LPCLK, for highest power efficiency). One of the clock sources must be configured and enabled before using the peripheral:

GCLK_EIC is configured and enabled in the CRU registers. For more details, see Clock and Reset Unit (CRU) from Related Links. 32KHz_LPCLK is provided by the various internal, and external low power clock sources. For more details on configuration and selection of the clock, see Clock and Reset Unit (CRU) from Related Links. Both GCLK_EIC and 32KHz_LPCLK are asynchronous to the user interface clock (PB1_CLK). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Related Links 13. Clock and Reset Unit (CRU) 23.5.4 DMA Not applicable. 23.5.5 Interrupts There are four external interrupts (EXTINT) and one Non-Maskable Interrupt (NMI). All the EXTINT interrupt request lines are connected to a single interrupt in the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is connected to non-maskable interrupt of the interrupt controller, but does not require the interrupt to be configured. 23.5.6 Events The events are connected to the Event System. Using the events requires the Event System to be configured first. Related Links 26. Event System (EVSYS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 542 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.5.7 Debug Operation When the CPU is halted in Debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 23.5.8 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Status and Clear register (INTFLAG) Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. 23.5.9 Analog Connections Not applicable. 23.6 Functional Description 23.6.1 Principle of Operation The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC or by 32KHz_LPCLK. Related Links 23.6.3. External Pin Processing 23.6.2 Basic Operation 23.6.2.1 Initialization The EIC must be initialized in the following order:

1. 2. If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL). Enable GCLK_EIC or 32KHz_LPCLK when one of the following configurations is selected:

The NMI uses edge detection or filtering One EXTINT uses filtering One EXTINT uses synchronous edge detection One EXTINT uses debouncing GCLK_EIC is used when a frequency higher than 32 KHz is required for filtering. 32KHz_LPCLK is recommended when power consumption is the priority. For 32KHz_LPCLK, write a 1 to the Clock Selection bit in the Control A register (CTRLA.CKSEL). 3. Configure the EIC input sense and filtering by writing the Configuration register (CONFIG). 4. Optionally, enable the asynchronous mode. 5. Optionally, enable the debouncer mode. 6. Enable the EIC by writing a 1 to CTRLA.ENABLE. The following bits are enable-protected, meaning that it can only be written when the EIC is disabled

(CTRLA.ENABLE=0):

Clock Selection bit in Control A register (CTRLA.CKSEL) The following registers are enable-protected:

Event Control register (EVCTRL) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 543 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) Configuration register (CONFIG) External Interrupt Asynchronous Mode register (ASYNCH) Debouncer Enable register (DEBOUNCEN) Debounce Prescaler register (DPRESCALER) Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to 1, but not at the same time as CTRLA.ENABLE is being cleared. Enable-protection is denoted by the Enable-Protected property in the register description. See NMICTRL, CTRLA, CONFIG, ASYNCH, DEBOUNCEN, DPRESCALER, EVCTRL registers in the EIC Register Summary from Related Links. 23.6.2.2 Enabling, Disabling and Resetting The EIC is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is disabled by writing CTRLA.ENABLE to 0. The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled. 23.6.3 External Pin Processing Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the Config n register (CONFIG.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met. When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when the interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or 32KHz_LPCLK. Filtering is enabled if the bit Filter Enable x in the Configuration n register (CONFIG.FILTENx) is written to 1. The majority vote filter samples the external pin three times with GCLK_EIC or 32KHz_LPCLK and outputs the value when two or more samples are equal. Table 23-1. Majority Vote Filter Samples [0, 1, 2]

Filter Output

[0,0,0]

[0,0,1]

[0,1,0]

[0,1,1]

[1,0,0]

[1,0,1]

[1,1,0]

[1,1,1]

0 0 0 1 0 1 1 1 When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Level detection and asynchronous edge detection does not require GCLK_EIC or 32KHz_LPCLK, but interrupt and events can still be generated. If filtering or synchronous edge detection or debouncing is enabled, the EIC automatically requests GCLK_EIC or 32KHz_LPCLK to operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the CRU. In these modes the external pin is sampled at the EIC clock rate, thus pulses with duration lower than two EIC clock periods may not be properly detected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 544 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) Figure 23-2. Interrupt Detection Latency by Modes (Rising Edge) The detection latency depends on the detection mode. Table 23-2. Detection Latency Detection Mode Latency (Worst Case) Level without filter Five PB1_CLK periods Level with filter Four GCLK_EIC/32KHz_LPCLK periods + five PB1_CLK periods Edge without filter Four GCLK_EIC/32KHz_LPCLK periods + five PB1_CLK periods Edge with filter Six GCLK_EIC/32KHz_LPCLK periods + five PB1_CLK periods 23.6.4 Additional Features 23.6.4.1 Non-Maskable Interrupt (NMI) The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a 1 to the NMI Filter Enable bit

(NMICTRL.NMIFILTEN). If edge detection or filtering is required, enable GCLK_EIC or 32KHz_LPCLK. NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC module is not required to be enabled. When an NMI is detected, the Non-maskable Interrupt flag in the NMI Flag Status and Clear register is set

(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set. 23.6.4.2 Asynchronous Edge Detection Mode (No Debouncing) The EXTINT edge detection operates synchronously or asynchronously, as selected by the Asynchronous Control Mode bit for external pin x in the External Interrupt Asynchronous Mode register (ASYNCH.ASYNCH[x]). The EIC edge detection is operated synchronously when the Asynchronous Control Mode bit (ASYNCH.ASYNCH[x]) is '0'

(default value). It is operated asynchronously when ASYNCH.ASYNCH[x] is written to '1'. In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt (NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register (CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag (NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. The EIC clock is needed in this mode. The Synchronous Edge Detection Mode can be used in Idle and Standby sleep modes. In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable interrupt (NMI) pins set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or NMIFLAG) directly. The EIC clock is not needed in this mode. The asynchronous edge detection mode can be used in Idle and Standby sleep modes. 23.6.4.3 Interrupt Pin Debouncing The external interrupt pin (EXTINT) edge detection can use a debouncer to improve input noise immunity. When selected, the debouncer can work in the synchronous mode or the asynchronous mode, depending on the 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 545 Microchip Confidential intreq_extint[x](edge detection / filter)intreq_extint[x](edge detection / no filter)intreq_extint[x](level detection / filter)intreq_extint[x](level detection / no filter)EXTINTxPB1_CLKGCLK_EICclear INTFLAG.EXTINT[x]No interruptNo interruptConfidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) configuration of the ASYNCH.ASYNCH[x] bit for the pin. The debouncer uses the EIC clock as defined by the bit CTRLA.CKSEL to clock the debouncing circuitry. The debouncing time frame is set with the debouncer prescaler DPRESCALER.PRESCALERn, which provides the low frequency clock tick that is used to reject higher frequency signals. The debouncing mode for pin EXTINT x can be selected only if the Sense bits in the Configuration y register

(CONFIG.SENSEx) are set to RISE, FALL or BOTH. If the debouncing mode for pin EXTINT x is selected, the filter mode for that pin (CONFIG.FILTENx) can not be selected. The debouncer manages an internal valid pin state that depends on the external interrupt (EXTINT) pin transitions, the debouncing mode and the debouncer prescaler frequency. The valid pin state reflects the pin value after debouncing. The external interrupt pin (EXTINT) is sampled continously on EIC clock. The sampled value is evaluated on each low frequency clock tick to detect a transitional edge when the sampled value is different of the current valid pin state. The sampled value is evaluated on each EIC clock when DPRESCALER.TICKON=0 or on each low frequency clock tick when DPRESCALER.TICKON=1, to detect a bounce when the sampled value is equal to the current valid pin state. Transitional edge detection increments the transition counter of the EXTINT pin, while bounce detection resets the transition counter. The transition counter must exceed the transition count threshold as defined by the DPRESCALER.STATESn bitfield. In the synchronous mode the threshold is 4 when DPRESCALER.STATESn=0 or 8 when DPRESCALER.STATESn=1. In the asynchronous mode the threshold is 4. The valid pin state for the pins can be accessed by reading the register PINSTATE for both synchronous or asynchronous debouncing mode. Synchronous edge detection In this mode the external interrupt (EXTINT) pin is sampled continously on EIC clock. 1. 2. 3. A pin edge transition will be validated when the sampled value is consistently different of the current valid pin state for 4 (or 8 depending on bit DPRESCALER.STATESn) consecutive ticks of the low frequency clock. Any pin sample, at the low frequency clock tick rate, with a value opposite to the current valid pin state will increment the transition counter. Any pin sample, at EIC clock rate (when DPRESCALER.TICKON=0) or the low frequency clock tick (when DPRESCALER.TICKON=1), with a value identical to the current valid pin state will return the transition counter to zero. 4. When the transition counter meets the count threshold, the pin edge transition is validated and the pin state PINSTATE.PINSTATE[x] is changed to the detected level. The external interrupt flag (INTFLAG.EXTINT[x]) is set when the pin state PINSTATE.PINSTATE[x] is changed. 5. Figure 23-3. EXTINT Pin Synchronous Debouncing (Rising Edge) In the synchronous edge detection mode, the EIC clock is required. The synchronous edge detection mode can be used in Idle and Standby sleep modes. Asynchronous edge detection In this mode, the external interrupt (EXTINT) pin directly drives an asynchronous edges detector which triggers any rising or falling edge on the pin:

1. 2. 3. 4. 5. Any edge detected that indicates a transition from the current valid pin state will immediately set the valid pin state PINSTATE.PINSTATE[x] to the detected level. The external interrupt flag (INTFLAG.EXTINT[x] is immediately changed. The edge detector will then be idle until no other rising or falling edge transition is detected during 4 consecutive ticks of the low frequency clock. Any rising or falling edge transition detected during the idle state will return the transition counter to 0. After 4 consecutive ticks of the low frequency clock without bounce detected, the edge detector is ready for a new detection. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 546 Microchip Confidential CLK_EICCLK_PRESCALEREXTINTxPIN_STATEINTGLAGTRANSITIONLOWHIGHSet INTFLAGConfidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) Figure 23-4. EXTINT Pin Asynchronous Debouncing (Rising Edge) In this mode, the EIC clock is requested. The asynchronous edge detection mode can be used in Idle and Standby sleep modes. 23.6.5 DMA Operation Not applicable. 23.6.6 Interrupts The EIC has the following interrupt sources:

External interrupt (EXTINTx) pins. See 23.6.2. Basic Operation. Non-maskable interrupt (NMI) pin. See 23.6.4. Additional Features. Each interrupt source has an associated Interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an Interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET = 1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR = 1). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the INTFLAG register for details on how to clear Interrupt flags. The EIC has one interrupt request line for all external interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine which Interrupt condition is present. Notes:

1. 2. Interrupts must be globally enabled for interrupt requests to be generated. If an external interrupt (EXTINT) is common on two or more I/O pins, only one will be active (the first one programmed).TPUBSAMD-367 Related Links 8. Processor and Architecture 23.6.7 Events The EIC can generate the following output events:

External event from pin (EXTINT0-3) Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this bit disables the corresponding output event. For more details on configuring the event system, see Event System

(EVSYS) from Related Links. When the condition on pin EXTINTx matches the configuration in the CONFIG register, the corresponding event is generated, if enabled. Related Links 26. Event System (EVSYS) 23.6.8 Sleep Mode Operation In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in the CONFIG register, and the corresponding bit in the Interrupt Enable Set register (INTENSET) is written to 1. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 547 Microchip Confidential CLK_EICCLK_PRESCALEREXTINTxPIN_STATEINTGLAGTRANSITIONLOWHIGHSet INTFLAGConfidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) Note:As soon as the EIC module is enabled and SENSEx is configured with different settings than no detection, the INTFLAGx bit will record the activity on the EXTINTx pin whether or not the Interrupt Enable bit is set. Figure 23-5. Wake-up Operation Example (High-Level Detection, No Filter, Interrupt Enable Set) PB1_CLK EXTINTx intwake_extint[x]

intreq_extint[x]

wake from sleep mode clear INTFLAG.EXTINT[x]

23.6.9 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in control register (CTRLA.SWRST) Enable bit in control register (CTRLA.ENABLE) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 548 Microchip Confidential Confidential 0x00 0x01 0x02 0x03 CTRLA NMICTRL NMIFLAG Reserved 0x04 SYNCBUSY 0x08 EVCTRL 0x0C INTENCLR 0x10 INTENSET 0x14 INTFLAG 0x18 ASYNCH 0x1C CONFIG 0x20

... 0x2F Reserved 0x30 DEBOUNCEN 0x34 DPRESCALER 0x38 PINSTATE 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.7 Register Summary See EIC module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 CKSEL 3 2 1 0 ENABLE SWRST NMIASYNCH NMIFILTEN NMISENSE[2:0]

NMI ENABLE SWRST EXTINTEO[3:0]

EXTINT[3:0]

EXTINT[3:0]

EXTINT[3:0]

ASYNCH[3:0]

FILTEN1 FILTEN3 SENSE1[2:0]

SENSE3[2:0]

FILTEN0 FILTEN2 SENSE0[2:0]

SENSE2[2:0]

DEBOUNCEN[3:0]

STATES0 PRESCALER0[2:0]

TICKON PINSTATE[3:0]

Related Links 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 549 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 550 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized CTRLA 0x00 0x00 Bit 7 6 5 Access Reset Bit 4 CKSELClock Selection 4 CKSEL RW 0 3 2 1 ENABLE RW 0 0 SWRST W 0 The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 KHz is required for filtering) or by 32KHz_LPCLK (when power consumption is the priority). This bit is not Write-Synchronized. Value 0 1 Description The EIC is clocked by GCLK_EIC. The EIC is clocked by 32KHz_LPCLK. Bit 1 ENABLEEnable Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is Write-Synchronized. Value 0 1 Description The EIC is disabled. The EIC is enabled. Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not Enable-Protected. This bit is Write-Synchronized. Value 0 1 Description There is no ongoing reset operation. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 551 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.2 Non-Maskable Interrupt Control Name:

Offset:

Reset:

Property: PAC Write-Protection NMICTRL 0x01 0x00 Bit 7 6 5 Access Reset 4 NMIASYNCH R/W 0 3 NMIFILTEN R/W 0 2 R/W 0 1 NMISENSE[2:0]

R/W 0 0 R/W 0 Bit 4 NMIASYNCHNon-Maskable Interrupt Asynchronous Edge Detection Mode The NMI edge detection can be operated synchronously or asynchronously to the EIC clock. In Synchronous Edge Detection Mode, the non-maskable interrupt (NMI) pin is sampled using the EIC clock as defined by the bit CTRLA.CKSEL. The non-maskable interrupt flag (NMIFLAG) is set when the pin and the pin sampler have a different value. In this mode, the EIC clock is required. The Synchronous Edge Detection mode can be used in all sleep modes, except STANDBY. In Asynchronous Edge Detection Mode, the non-maskable interrupt (NMI) pins directly drives the set of the non-

maskable interrupt flag (NMIFLAG). In this mode, the EIC clock is not requested. The Asynchronous Edge Detection Mode can be used in all sleep modes. Description Value The NMI edge detection is synchronously operated. 0 The NMI edge detection is asynchronously operated. 1 Bit 3 NMIFILTENNon-Maskable Interrupt Filter Enable Value 0 1 Description NMI filter is disabled. NMI filter is enabled. Bits 2:0 NMISENSE[2:0]Non-Maskable Interrupt Sense Configuration These bits define on which edge or level the NMI triggers. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 -

0x7 Description No detection Rising-edge detection Falling-edge detection Both-edge detection High-level detection Low-level detection Reserved Name NONE RISE FALL BOTH HIGH LOW

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 552 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.3 Non-Maskable Interrupt Flag Status and Clear Name:

Offset:

Reset:

NMIFLAG 0x2 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 NMINon-Maskable Interrupt 0 NMI RW 0 This flag is cleared by writing a '1' to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a '0' to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 553 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.4 Synchronization Busy Name:

Offset:

Reset:

SYNCBUSY 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 1 ENABLEEnable Synchronization Busy Status Value 0 1 Description Write synchronization for CTRLA.ENABLE bit is complete. Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 SWRSTSoftware Reset Synchronization Busy Status Description Write synchronization for CTRLA.SWRST bit is complete. Write synchronization for CTRLA.SWRST bit is ongoing. Value 0 1 1 ENABLE R 0 0 SWRST R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 554 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.5 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x08 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 Access Reset 3 R/W 0 8 0 2 1 EXTINTEO[3:0]

R/W 0 R/W 0 R/W 0 Bits 3:0 EXTINTEO[3:0]External Interrupt Event Output Enable The bit x of EXTINTEO enables the event associated with the EXTINTx pin. Value 0 1 Description Event from pin EXTINTx is disabled. Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external interrupt sensing configuration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 555 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.6 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x0C 0x00000000 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset Bits 3:0 EXTINT[3:0]External Interrupt Enable 3 R/W 0 9 1 8 0 2 EXTINT[3:0]

R/W 0 R/W 0 R/W 0 The bit x of EXTINT disables the interrupt associated with the EXTINTx pin. Writing a 0 to bit x has no effect. Writing a 1 to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EXTINTx. Value 0 1 Description The external interrupt x is disabled. The external interrupt x is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 556 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.7 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x10 0x00000000 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset Bits 3:0 EXTINT[3:0]External Interrupt Enable 3 R/W 0 9 1 8 0 2 EXTINT[3:0]

R/W 0 R/W 0 R/W 0 The bit x of EXTINT enables the interrupt associated with the EXTINTx pin. Writing a 0 to bit x has no effect. Writing a 1 to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx. Value 0 1 Description The external interrupt x is disabled. The external interrupt x is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 557 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.8 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x14 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset Bits 3:0 EXTINT[3:0]External Interrupt 3 R/W 0 9 1 8 0 2 EXTINT[3:0]

R/W 0 R/W 0 R/W 0 The flag bit x is cleared by writing a 1 to it. This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR/SET.EXTINT[x] is 1. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the External Interrupt x flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 558 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.9 External Interrupt Asynchronous Mode Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected ASYNCH 0x18 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset 3 RW 0 9 1 2 ASYNCH[3:0]

RW 0 RW 0 8 0 RW 0 Bits 3:0 ASYNCH[3:0]Asynchronous Edge Detection Mode The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin. Value 0 1 Description The EXTINT x edge detection is synchronously operated. The EXTINT x edge detection is asynchronously operated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 559 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.10 External Interrupt Sense Configuration Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CONFIG 0x1C 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit Access Reset Bit Access Reset 15 FILTEN3 RW 0 7 FILTEN1 RW 0 14 RW 0 6 RW 0 13 SENSE3[2:0]

RW 0 5 SENSE1[2:0]

RW 0 12 RW 0 4 RW 0 11 FILTEN2 RW 0 3 FILTEN0 RW 0 10 RW 0 2 RW 0 9 SENSE2[2:0]

RW 0 1 SENSE0[2:0]

RW 0 8 RW 0 0 RW 0 Bits 3, 7, 11, 15 FILTENxFilter Enable x [x=3..0]

Note: The filter must be disabled if the asynchronous detection is enabled. Value 0 1 Description Filter is disabled for EXTINT[x] input. Filter is enabled for EXTINT[x] input. Bits 0:2, 4:6, 8:10, 12:14 SENSExInput Sense Configuration x [x=3..0]

These bits define on which edge or level the interrupt or event for EXTINT[x] will be generated. Description Value No detection 0x0 Rising-edge detection 0x1 Falling-edge detection 0x2 Both-edge detection 0x3 High-level detection 0x4 Low-level detection 0x5 Reserved 0x6 -

0x7 Name NONE RISE FALL BOTH HIGH LOW

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 560 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.11 Debouncer Enable Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DEBOUNCEN 0x30 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 Access Reset 3 RW 0 2 1 DEBOUNCEN[3:0]

RW RW 0 0 Bits 3:0 DEBOUNCEN[3:0]Debouncer Enable The bit x of DEBOUNCEN set the Debounce mode for the interrupt associated with the EXTINTx pin. Value 0 1 Description The EXTINT x edge input is not debounced. The EXTINT x edge input is debounced. 8 0 RW 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 561 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.12 Debouncer Prescaler Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DPRESCALER 0x34 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 Access Reset 3 STATES0 RW 0 2 RW 0 1 PRESCALER0[2:0]

RW 0 Bit 16 TICKONPin Sampler frequency selection This bit selects the clock used for the sampling of bounce during transition detection. Value 0 1 Description The bounce sampler is using GCLK_EIC. The bounce sampler is using the low frequency clock. 16 TICKON RW 0 8 0 RW 0 Bit 3 STATES0Debouncer number of states This bit selects the number of samples by the debouncer low frequency clock needed to validate a transition from current pin state to next pin state in synchronous debouncing mode for pins EXTINT[3:0]. Value 0 1 Description The number of low frequency samples is 3. The number of low frequency samples is 7. Bits 2:0 PRESCALER0[2:0]Debouncer Prescaler These bits select the debouncer low frequency clock for pins EXTINT[3:0]. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description EIC clock divided by 2 EIC clock divided by 4 EIC clock divided by 8 EIC clock divided by 16 EIC clock divided by 32 EIC clock divided by 64 EIC clock divided by 128 EIC clock divided by 256 Name F/2 F/4 F/8 F/16 F/32 F/64 F/128 F/256 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 562 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family External Interrupt Controller (EIC) 23.8.13 Pin State Name:

Offset:

Reset:

PINSTATE 0x38 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset 3 R 0 9 1 2 PINSTATE[3:0]

R 0 R 0 8 0 R 0 Bits 3:0 PINSTATE[3:0]Pin State These bits return the valid pin state of the debounced external interrupt pin EXTINTx. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 563 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24. Configurable Custom Logic (CCL) 24.1 Overview The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device pins, to events, or to other internal peripherals. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. Each LookUp Table (LUT) consists of three inputs, a truth table, an optional synchronizer/filter, and an optional edge detector. Each LUT can generate an output as a user programmable logic expression with three inputs. Inputs can be individually masked. The output can be combinatorially generated from the inputs, and can be filtered to remove spikes. Optional sequential logic can be used. The inputs of the sequential module are individually controlled by two independent, adjacent LUT (LUT0/LUT1) outputs, enabling complex waveform generation. 24.2 Features Glue logic for general purpose PCB design Two programmable Look-up Tables (LUTs) Combinatorial logic functions: AND, NAND, OR, NOR, XOR, XNOR, NOT Sequential logic functions: Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch Flexible LUT inputs selection:

I/Os Events Internal peripherals Subsequent LUT output Output can be connected to the I/O pins or the Event System Optional synchronizer, filter or edge detector available on each LUT output 24.3 Block Diagram Figure 24-1. Configurable Custom Logic LUTCTRL0

(INSEL) LUT0 LUTCTRL0

(FILTSEL) LUTCTRL0

(EDGESEL) SEQCTRL

(SEQSEL0) CTRL

(ENABLE) Filter / Synch CLR Edge Detector CLR Sequential CLR Event System OUT0 I/O Internal Events I/O Peripherals Truth Table 8 LUTCTRL0

(ENABLE) D Q CLK_CCL_APB GCLK_CCL LUTCTRL1

(INSEL) Internal Events I/O Peripherals CLK_CCL_APB GCLK_CCL LUT1 LUTCTRL1

(FILTSEL) LUTCTRL1

(EDGESEL) Truth Table 8 Filter / Synch CLR Edge Detector CLR LUTCTRL1

(ENABLE) D Q CTRL

(ENABLE) Event System OUT1 I/O UNIT 0 UNIT 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 564 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) LUTCTRL0

(INSEL) LUT0 LUTCTRL0

(FILTSEL) LUTCTRL0

(EDGESEL) SEQCTRL

(SEQSEL0) CTRL

(ENABLE) Filter / Synch CLR Edge Detector CLR Sequential CLR Event System OUT0 I/O Internal Events I/O Peripherals Truth Table 8 LUTCTRL0

(ENABLE) D Q CLK_CCL_APB GCLK_CCL LUTCTRL1

(INSEL) Internal Events I/O Peripherals CLK_CCL_APB GCLK_CCL Internal Events I/O Peripherals Truth Table 8 LUTCTRL0

(ENABLE) D Q CLK_CCL_APB GCLK_CCL LUTCTRL1

(INSEL) Internal Events I/O Peripherals CLK_CCL_APB GCLK_CCL LUT1 LUTCTRL1

(FILTSEL) LUTCTRL1

(EDGESEL) Truth Table 8 Filter / Synch CLR Edge Detector CLR LUTCTRL1

(ENABLE) D Q CTRL

(ENABLE) Event System OUT1 I/O UNIT 0 LUTCTRL0

(INSEL) LUT0 LUTCTRL0

(FILTSEL) LUTCTRL0

(EDGESEL) SEQCTRL

(SEQSEL0) CTRL

(ENABLE) Filter / Synch CLR Edge Detector CLR Sequential CLR Event System OUT0 I/O LUT1 LUTCTRL1

(FILTSEL) LUTCTRL1

(EDGESEL) Truth Table 8 Filter / Synch CLR Edge Detector CLR LUTCTRL1

(ENABLE) D Q CTRL

(ENABLE) Event System OUT1 I/O UNIT 0 UNIT 1 24.4 Signal Description Pin Name OUT[n:0]

IN[3n+2:0]

Type Digital output Digital input 1. n (n=1) is the number of CCL groups. Description Output from lookup table Input to lookup table See I/O Ports and Peripheral Pin Select (PPS) from Related Links for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 565 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 24.5.1 I/O Lines The CCL can take inputs and generate output through I/O pins. For this to function properly, the I/O pins must be configured to be used by a Look Up Table (LUT) using PPS configuration. 24.5.2 Power Management This peripheral can continue to operate in any Sleep mode (Standby Sleep, Idle) where its source clock is running. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. 24.5.3 Clocks The CCL bus clock PB2_CLK (CLK_CCL_APB) can be enabled and disabled in the CRU. A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using input events, filter, edge detection or sequential logic. GCLK_CCL is required when input events, a filter, an edge detector, or a sequential sub-module is enabled. This generic clock is asynchronous to the user interface clock. See Clock and Reset Unit (CRU) from Related Links. Related Links 13. Clock and Reset Unit (CRU) 24.5.4 DMA Not applicable. 24.5.5 Interrupts Not applicable. 24.5.6 Events The CCL can use events from other peripherals and generate events that can be used by other peripherals. For this feature to function, the events have to be configured properly. See Event System (EVSYS) from Related Links. Related Links 26. Event System (EVSYS) 24.5.7 Debug Operation When the CPU is halted in Debug mode the CCL continues normal operation. However, the CCL cannot be halted when the CPU is halted in Debug mode. If the CCL is configured in a way that requires it to be periodically serviced by the CPU, improper operation or data loss may result during debugging. 24.5.8 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). See Peripheral Access Controller (PAC) from Related Links. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. PAC write protection does not apply to accesses through an external debugger. Related Links 20. Peripheral Access Controller (PAC) 24.5.9 Analog Connections Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 566 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.6 Functional Description 24.6.1 Principle of Operation Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins, internal peripherals, and the internal Event System as both input and output channels. The CCL can serve as glue logic between the device and external devices. The CCL can eliminate the need for external logic component and can also help the designer overcome challenging real-time constrains by combining core independent peripherals in clever ways to handle the most time critical parts of the application independent of the CPU. 24.6.2 Operation 24.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is disabled (LUTCTRLx.ENABLE=0):

Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is disabled (LUTCTRLx.ENABLE=0):

LUT Control x (LUTCTRLx) register, except the ENABLE bit Enable-protected bits in the LUTCTRLx registers can be written at the same time as LUTCTRLx.ENABLE is written to

'1', but not at the same time as LUTCTRLx.ENABLE is written to '0'. Enable-protection is denoted by the Enable-Protected property in the register description. 24.6.2.2 Enabling, Disabling, and Resetting The CCL is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The CCL is disabled by writing a '0' to CTRL.ENABLE. Each LUT is enabled by writing a '1' to the Enable bit in the LUT Control x register (LUTCTRLx.ENABLE). Each LUT is disabled by writing a '0' to LUTCTRLx.ENABLE. The CCL is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the CCL will be reset to their initial state, and the CCL will be disabled. 24.6.2.3 Lookup Table Logic The lookup table in each LUT unit can generate any logic expression OUT as a function of three inputs (IN[2:0]), as shown in Figure 24-2. One or more inputs can be masked. The truth table for the expression is defined by TRUTH bits in LUT Control x register (LUTCTRLx.TRUTH). Figure 24-2. Truth Table Output Value Selection LUT TRUTH[0]

TRUTH[1]

TRUTH[2]

TRUTH[3]

TRUTH[4]

TRUTH[5]

TRUTH[6]

TRUTH[7]

OUT LUTCTRL

(ENABLE) Table 24-1. Truth Table of LUT IN[2:0]

IN[2]

0 IN[1]

0 IN[0]

0 OUT TRUTH[0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 567 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL)

...........continued IN[2]

IN[1]

IN[0]

1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 24.6.2.4 Truth Table Inputs Selection Input Overview The inputs can be individually:

Masked Driven by peripherals:

OUT TRUTH[1]

TRUTH[2]

TRUTH[3]

TRUTH[4]

TRUTH[5]

TRUTH[6]

TRUTH[7]

Analog comparator output (AC) Timer/Counters waveform outputs (TC) Serial Communication output transmit interface (SERCOM) Driven by internal events from Event System Driven by other CCL sub-modules The Input Selection for each input y of LUT x is configured by writing the Input y Source Selection bit in the LUT x Control register (LUTCTRLx.INSELy). Masked Inputs (MASK) When a LUT input is masked (LUTCTRLx.INSELy = MASK), the corresponding TRUTH input (IN) is internally tied to zero, as shown in this figure:

Figure 24-3. Masked Input Selection Internal Feedback Inputs (FEEDBACK) When selected (LUTCTRLx.INSELy = FEEDBACK), the Sequential (SEQ) output is used as input for the corresponding LUT. The output from an internal sequential sub-module can be used as input source for the LUT, see figure below for an example for LUT0 and LUT1. The sequential selection for each LUT follows the formula:

IN 2N i = SEQ N With N representing the sequencer number and i=0,1,2 representing the LUT input index. IN 2N+1 i = SEQ N For additional information, see Sequential Logic from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 568 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Figure 24-4. Feedback Input Selection Linked LUT (LINK) When selected (LUTCTRLx.INSELy=LINK), the subsequent LUT output is used as the LUT input (for example, LUT1 is the input for LUT0), as shown in the following figure:

Figure 24-5. Linked LUT Input Selection LUT0 SEQ 0 CTRL

(ENABLE) LUT1 LUT(2n - 2) SEQ n CTRL

(ENABLE) LUT(2n-1) Internal Events Inputs Selection (EVENT) Asynchronous events from the Event System can be used as input selection, as shown in the following figure. For each LUT, one event input line is available and can be selected on each LUT input. Before enabling the event selection by writing LUTCTRLx.INSELy=EVENT, the Event System must be configured first. By default, CCL includes an edge detector. When the event is received, an internal strobe is generated when a rising edge is detected. The pulse duration is one GCLK_CCL clock cycle. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 569 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Figure 24-6. Event Input Selection I/O Pin Inputs (IO) When the I/O pin is selected as LUT input (LUTCTRLx.INSELy = IO), the corresponding LUT input will be connected to the pin, as shown in the figure below. Figure 24-7. I/O Pin Input Selection Analog Comparator Inputs (AC) The AC outputs can be used as input source for the LUT (LUTCTRLx.INSELy=AC). The analog comparator outputs are distributed following the formula:

With N representing the LUT number and i=[0,1,2] representing the LUT input index. IN N i = AC N % ComparatorOutput_Number Before selecting the comparator output, the AC must be configured first. The output of comparator 0 is available on even LUTs ("LUT(2x)": LUT0) and the comparator 1 output is available on odd LUTs ("LUT(2x+1)": LUT1), as shown in the figure below. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 570 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Figure 24-8. AC Input Selection LUT0 TRUTH OUT0 COMP0 CMP0 LUT1 TRUTH OUT1 COMP1 CMP1 Timer/Counter Inputs (TC) The TC waveform output WO[0] can be used as input source for the LUT (LUTCTRLx.INSELy = TC). Only consecutive instances of the TC, that is, TCx and the subsequent TC(x+1), are available as default and alternative TC selections (for example, TC0 and TC1 are sources for LUT0, TC1 and TC2 are sources for LUT1). See the figure below for an example for LUT0. More general, the Timer/Counter selection for each LUT follows the formula:

IN N i = DefaultTC N % TC_Instance_Number Where N represents the LUT number and i represents the LUT input index (i=0,1,2). IN N i = AlternativeTC N + 1 % TC_Instance_Number Before selecting the waveform outputs, the TC must be configured first. Figure 24-9. TC Input Selection WO[0]

WO[0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 571 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Timer/Counter for Control Application Inputs (TCC) The TCC waveform outputs can be used as input source for the LUT. Only WO[2:0] outputs can be selected and routed to the respective LUT input (that is, IN0 is connected to WO0, IN1 to WO1, and IN2 to WO2), as shown in the figure below. Note:

The TCC selection for each LUT follows the formula:

Where N represents the LUT number and i represents the LUT input index (i=0,1,2). IN N i = TCC N % TCC_Instance_Number .WO i Before selecting the waveform outputs, the TCC must be configured first. Figure 24-10. TCC Input Selection OUT0 Serial Communication Output Transmit Inputs (SERCOM) The serial engine transmitter output from Serial Communication Interface (SERCOM TX, TXD for USART, MOSI for SPI) can be used as input source for the LUT. The figure below shows an example for LUT0 and LUT1. The SERCOM selection for each LUT follows the formula:

With N representing the LUT number and i=0,1,2 representing the LUT input index. IN N i = SERCOM[N % SERCOM_Instance_Number Before selecting the SERCOM as input source, the SERCOM must be configured first: the SERCOM TX signal must be output on SERCOMn/pad[0], which serves as input pad to the CCL. Figure 24-11. SERCOM Input Selection Related Links 24.6.2.7. Sequential Logic 24.6.2.5 Filter By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when the inputs change value. These glitches can be removed by clocking through filters, if demanded by application needs. The Filter Selection bits in LUT Control register (LUTCTRLx.FILTSEL) define the synchronizer or digital filter options. When a filter is enabled, the OUT output will be delayed by two to five GCLK cycles. One APB clock after the corresponding LUT is disabled, all internal filter logic is cleared. Note:Events used as LUT input will also be filtered, if the filter is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 572 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Figure 24-12. Filter FILTSEL OUT D Q D Q D Q G D Q R R R R Input GCLK_CCL CLR 24.6.2.6 Edge Detector The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge, the TRUTH table should be inverted. The edge detector is enabled by writing '1' to the Edge Selection bit in LUT Control register (LUTCTRLx.EDGESEL). In order to avoid unpredictable behavior, either the filter or synchronizer must be enabled. Edge detection is disabled by writing a '0' to LUTCTRLx.EDGESEL. After disabling a LUT, the corresponding internal Edge Detector logic is cleared one APB clock cycle later. Figure 24-13. Edge Detector 24.6.2.7 Sequential Logic Each LUT pair can be connected to the internal sequential logic, which can be configured to work as D flip flop, JK flip flop, gated D-latch or RS-latch by writing the Sequential Selection bits on the corresponding Sequential Control x register (SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK_CCL clock and optionally each LUT filter or edge detector must be enabled. Note:While configuring the sequential logic, the even LUT must be disabled. When configured, the even LUT must be enabled. Gated D Flip-Flop (DFF) When the DFF is selected, the D-input is driven by the even LUT output LUT0, and the G-input is driven by the odd LUT output LUT1, as shown in the following figure. Figure 24-14. D Flip Flop 0 When the even LUT is disabled LUTCTRL0.ENABLE=0, the flip-flop is asynchronously cleared. The reset command

(R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in the following table. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 573 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Table 24-2. DFF Characteristics R 1 0 G X 1 0 D X 1 0 X OUT Clear Set Clear Hold state (no change) JK Flip-Flop (JK) When this configuration is selected, the J-input is driven by the even LUT output LUT0, and the K-input is driven by the odd LUT output LUT1, as shown in the following figure. Figure 24-15. JK Flip Flop 0 When the even LUT is disabled LUTCTRL0.ENABLE=0, the flip-flop is asynchronously cleared. The reset command

(R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in the following table. Table 24-3. JK Characteristics R 1 0 0 0 0 J X 0 0 1 1 K X 0 1 0 1 OUT Clear Hold state (no change) Clear Set Toggle Gated D-Latch (DLATCH) When the DLATCH is selected, the D-input is driven by the even LUT output LUT0, and the G-input is driven by the odd LUT output LUT1, as shown in the following figure. Figure 24-16. D-Latch even LUT odd LUT D G Q OUT When the even LUT is disabled LUTCTRL0.ENABLE=0, the latch output will be cleared. The G-input is forced enabled for one more APB clock cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in the following table. Table 24-4. D-Latch Characteristics G 0 1 D X 0 OUT Hold state (no change) Clear 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 574 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL)

...........continued G 1 D 1 OUT Set RS Latch (RS) When this configuration is selected, the S-input is driven by the even LUT output LUT0, and the R-input is driven by the odd LUT output LUT1, as shown in the following figure. Figure 24-17. RS-Latch even LUT odd LUT S R Q OUT When the even LUT is disabled LUTCTRL0.ENABLE=0, the latch output will be cleared. The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in the following table. Table 24-5. RS-Latch Characteristics S 0 0 1 1 R 0 1 0 1 OUT Hold state (no change) Clear Set Forbidden state 24.6.3 Events The CCL can generate the following output events:

LUTn where n=0-1: Lookup Table Output Value Writing a 1 to the LUT Control Event Output Enable bit (LUTCTRL.LUTEO) enables the corresponding output event. Writing a 0 to this bit disables the corresponding output event. The CCL can take the following actions on an input event:

INSELx where x=0-2: The event is used as input for the TRUTH table. See Event System (EVSYS) from Related Links. Writing a 1 to the LUT Control Event Input Enable bit (LUTCTRL.LUTEI) enables the corresponding action on input event. Writing a 0 to this bit disables the corresponding action on input event. Related Links 26. Event System (EVSYS) 24.6.4 Sleep Mode Operation When using the GCLK_CCL internal clocking, writing the Run In Standby bit in the Control register

(CTRL.RUNSTDBY) to '1' will allow GCLK_CCL to be enabled in Standby Sleep mode. If CTRL.RUNSTDBY=0, the GCLK_CCL will be disabled in Standby Sleep mode. If the Filter, Edge Detector or Sequential logic are enabled, the LUT output will be forced to zero in STANDBY mode. In all other cases, the TRUTH table decoder will continue operation and the LUT output will be refreshed accordingly. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 575 Microchip Confidential Confidential Offset Name CTRL Reserved 0x00 0x01

... 0x03 0x04 0x05

... 0x07 PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.7 Register Summary See CCL module in the Product Memory Mapping Overview from Related Links for base address. Bit Pos. 7:0 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST SEQCTRLX 7:0 Reserved SEQSEL[3:0]

0x08 LUTCTRL0 0x0C LUTCTRL1 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 EDGESEL FILTSEL[1:0]

ENABLE INSEL2[3:0]

INSEL1[3:0]

LUTEO LUTEI INVEI TRUTH[7:0]

EDGESEL FILTSEL[1:0]

ENABLE INSEL2[3:0]

INSEL1[3:0]

LUTEO LUTEI INVEI TRUTH[7:0]

Related Links 7. Product Memory Mapping Overview 24.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, see Register Access Protection from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the "Enable-Protected" property in each individual register description. Related Links 24.5.8. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 576 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.8.1 Control Name:

Offset:

Reset:

Property: PAC Write-Protection CTRL 0x00 0x00 Note:CTRL register (except the bits ENABLE & SWRST) is Enable Protected when CCL.CTRL.ENABLE = 1. Bit 7 Access Reset 6 RUNSTDBY R/W 0 Bit 6 RUNSTDBYRun in Standby 5 4 3 2 1 ENABLE R/W 0 0 SWRST W 0 This bit indicates if the GCLK_CCL clock must be kept running in Standby Sleep mode. The setting is ignored for configurations where the generic clock is not required. For details, see Sleep Mode Operation from Related Links. Important:This bit must be written before enabling the CCL. Value 0 1 Description Generic clock is not required in standby sleep mode. Generic clock is required in standby sleep mode. Bit 1 ENABLEEnable Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the CCL to their initial state. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. Related Links 24.6.4. Sleep Mode Operation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 577 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.8.2 Sequential Control X Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-protected SEQCTRLX 0x04 0x00 Note:SEQCTRLX register is Enable-protected when CCL.LUTCTRL0.ENABLE = 1. Bit 7 6 5 4 Access Reset Bits 3:0 SEQSEL[3:0]Sequential Selection 3 R/W 0 2 1 SEQSEL[3:0]

R/W 0 R/W 0 0 R/W 0 These bits select the sequential configuration:

Sequential Selection Value 0x0 0x1 0x2 0x3 0x4 0x5 -

0xF Name DISABLE DFF JK LATCH RS Description Sequential logic is disabled D flip flop JK flip flop D latch RS latch Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 578 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) 24.8.3 LUT Control n Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-protected LUTCTRL 0x08 + n*0x04 [n=0..1]

0x00000000 Note:The LUTCTRLn register is Enable Protected when CCL.LUTCTRLn.ENABLE = 1. Bit 31 Access Reset R/W 0 Bit 23 Access Reset 30 R/W 0 22 LUTEO R/W 0 29 R/W 0 21 LUTEI R/W 0 27 R/W 0 19 TRUTH[7:0]

28 R/W 0 20 INVEI R/W 0 26 R/W 0 18 25 R/W 0 17 Bit 15 14 Access Reset Bit 7 EDGESEL Access Reset R/W 0 13 R/W 0 6 5 12 11 INSEL2[3:0]

R/W 0 R/W 0 4 10 R/W 0 3 FILTSEL[1:0]

R/W 0 R/W 0 9 R/W 0 8 INSEL1[3:0]

R/W 0 2 1 ENABLE R/W 0 24 R/W 0 16 0 Bits 31:24 TRUTH[7:0]Truth Table These bits define the value of truth logic as a function of inputs IN[2:0]. Bit 22 LUTEOLUT Event Output Enable Value 0 1 Description LUT event output is disabled. LUT event output is enabled. Bit 21 LUTEILUT Event Input Enable Value 0 1 Description LUT incoming event is disabled. LUT incoming event is enabled. Bit 20 INVEIInverted Event Input Enable Value 0 1 Description Incoming event is not inverted. Incoming event is inverted. Bits 8:11, 9:12, 10:13 INSELxLUT Input x Source Selection These bits select the LUT input x source:

Description Value Masked input 0x0 Feedback input source 0x1 Linked LUT input source 0x2 Event input source 0x3 I/O pin input source 0x4 AC input source: CMP[0] (LUT0) / CMP[1] (LUT1) 0x5 Name MASK FEEDBACK LINK EVENT IO AC 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 579 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Configurable Custom Logic (CCL) Name Value TC 0x6 ALTTC 0x7 TCC 0x8 SERCOM 0x9 0xA-0xF Reserved Description TC input source: TC0 WO[0] (LUT0) / TC1 WO[0] (LUT1) Alternative TC input source: TC1 WO[0] (LUT0) / TC2 WO[0] (LUT1) TCC input source: TCC0 (LUT0) / TCC1 (LUT1) SERCOM input source: SERCOM0 PAD0 (LUT0) / SERCOM1 PAD0 (LUT1) Reserved Bit 7 EDGESELEdge Selection Value 0 1 Description Edge detector is disabled. Edge detector is enabled. Bits 5:4 FILTSEL[1:0]Filter Selection These bits select the LUT output filter options:

Filter Selection Value 0x0 0x1 0x2 0x3 Name DISABLE SYNCH FILTER

Description Filter disabled Synchronizer enabled Filter enabled Reserved Bit 1 ENABLELUT Enable Value 0 1 Description The LUT is disabled. The LUT is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 580 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25. Frequency Meter (FREQM) 25.1 Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 25.2 Features Ratio can be measured with 24-bit accuracy Accurately measures the frequency of an input clock with respect to a reference clock Reference clock can be selected from the available GCLK_FREQM_REF sources Measured clock can be selected from the available GCLK_FREQM_MSR sources 25.3 Block Diagram Figure 25-1. FREQM Block Diagram GCLK_FREQM_MSR CLK_MSR EN COUNTER VALUE START GCLK_FREQM_REF CLK_REF EN TIMER DONE ENABLE REFNUM INTFLAG 25.4 Signal Description Not applicable. 25.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 581 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.5.1 I/O Lines Other than the internal GCLK sources, clock provided on REFI line is the external clock input source for GCLK_FREQM_REF/GCLK_FREQM_MSR, which can be used as measurement or reference clock sources. This requires the I/O pins to be configured using PPS configuration. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 25.5.2 Power Management The FREQM continues to operate in the Idle mode, where the selected source clock is running. The FREQMs interrupts can be used to wake-up the device from the Idle mode. See Power Management Unit (PMU) from Related Links for more details on the different sleep modes. Related Links 14. Power Management Unit (PMU) 25.5.3 Clocks The clock for the FREQM bus interface (PB1_CLK) is enabled and disabled by the CRU generator. Two generic clocks are used by the FREQM: Reference Clock (GCLK_FREQM_REF) and Measurement Clock

(GCLK_FREQM_MSR). GCLK_FREQM_REF is required to clock the internal reference timer, which acts as the frequency reference. GCLK_FREQM_MSR is required to clock a ripple counter for frequency measurement. These clocks must be configured and enabled in the generic clock controller before using the FREQM. See Clock and Reset Unit (CRU) from Related Links. Related Links 13. Clock and Reset Unit (CRU) 25.5.4 DMA Not applicable. 25.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using FREQM interrupt requires the interrupt controller to be configured first. 25.5.6 Events Not applicable. 25.5.7 Debug Operation When the CPU is halted in debug mode the FREQM continues its normal operation. The FREQM cannot be halted when the CPU is halted in debug mode. If the FREQM is configured in a way that requires it to be periodically serviced by the CPU, improper operation or data loss may result during debugging. 25.5.8 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except the following registers:

Control B register (CTRLB) Status register (STATUS) Interrupt Flag Status and Clear register (INTFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 582 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.6 Functional Description 25.6.1 Principle of Operation FREQM counts the number of periods of the measured clock (GCLK_FREQM_MSR) with respect to the reference clock (GCLK_FREQM_REF). The measurement is done for a period of REFNUM/fCLK_REF and stored in the Value register (VALUE.VALUE). REFNUM is the number of Reference clock cycles selected in the Configuration A register

(CFGA.REFNUM). The frequency of the measured clock,

, is calculated by

. The error can be maximum two measured clock cycles. fCLK_MSR fCLK_MSR = VALUE REFNUM 25.6.2 Basic Operation fCLK_REF 25.6.2.1 Initialization Before enabling FREQM, the device and peripheral must be configured:

Each of the generic clocks (GCLK_FREQM_REF and GCLK_FREQM_MSR) must be configured and enabled. Important:The reference clock must be slower than the measurement clock. Write the number of Reference clock cycles for which the measurement is to be done in the Configuration A register (CFGA.REFNUM). This must be a non-zero number. The following register is enable-protected, meaning that it can only be written when the FREQM is disabled

(CTRLA.ENABLE=0):

Configuration A register (CFGA) Enable-protection is denoted by the "Enable-Protected" property in the register description. 25.6.2.2 Enabling, Disabling and Resetting The FREQM is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is disabled by writing CTRLA.ENABLE=0. The FREQM is reset by writing a 1 to the Software Reset bit in the Control A register (CTRLA.SWRST). On software reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be disabled. Then ENABLE and SWRST bits are write-synchronized. 25.6.2.3 Measurement In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the duration of the measurement. The measurement is given in number of GCLK_FREQM_REF periods. Note:The REFNUM field must be written before the FREQM is enabled. After the FREQM is enabled, writing a 1 to the START bit in the Control B register (CTRLB.START) starts the measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement starts, and cleared when the measurement is complete. There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt Enable Set register (INTENSET.DONE) is 1 and a measurement is finished, the Measurement Done bit in the Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated. The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured clock GCLK_FREQM_MSR is then:

fCLK_MSR = VALUE REFNUM fCLK_REF 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 583 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) Notes:

1. In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status

(STATUS.OVF) must be checked. 2. Due to asynchronous operations, the VALUE Error measurement can be up to two samples. If an overflow condition occurred, indicated by the overflow bit in the STATUS register (STATUS.OVF), either the number of reference clock cycles must be reduced (CFGA.REFNUM) or a faster reference clock must be configured. Once the configuration is adjusted, clear the overflow status by writing a 1 to STATUS.OVF. Then, another measurement can be started by writing a 1 to CTRLB.START. Note:See CFGA, CTRLB, STATUS, INTENSET, INTFLAG, VALUE registers in the Register Summary - FREQM from Related Links. 25.6.3 DMA Operation Not applicable. 25.6.4 Interrupts The FREQM has one interrupt source:

DONE: A frequency measurement is done. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. The interrupt can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the FREQM is reset. See INTFLAG register Related Links for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. This interrupt is a synchronous wake-up source. Note that interrupts must be globally enabled for interrupt requests to be generated. Related Links 25.8.6. INTFLAG 25.6.5 Events Not applicable. 25.6.6 Sleep Mode Operation The FREQM will continue to operate in Idle mode where the selected source clock is running. The FREQMs interrupts can be used to wake up the device from Idle mode. For lowest chip power consumption in sleep modes, FREQM should be disabled before entering a Standby Sleep mode. 25.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits and registers are write-synchronized:

Software Reset bit in Control A register (CTRLA.SWRST) Enable bit in Control A register (CTRLA.ENABLE) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 584 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.7 Register Summary See FREQM module in the Product Memory Mapping Overview from Related Links for base address. Offset 0x00 0x01 0x02 0x04

... 0x07 0x08 0x09 0x0A 0x0B Name CTRLA CTRLB CFGA Reserved INTENCLR INTENSET INTFLAG STATUS 0x0C SYNCBUSY 0x10 VALUE Bit Pos. 7 6 5 4 3 2 1 0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 REFNUM[7:0]

ENABLE SWRST START DONE DONE DONE BUSY OVF ENABLE SWRST VALUE[7:0]

VALUE[15:8]

VALUE[23:16]

Related Links 7. Product Memory Mapping Overview 25.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 585 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.1 CTRLA - Control A Register Name:

Offset:

Reset:

Property: PAC Write-Protection CTRLA 0x00 0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 ENABLEEnable 1 ENABLE R/W 0 0 SWRST R/W 0 Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled or disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register

(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the FREQM to their initial state, and the FREQM will be disabled. Writing a 1 to this bit will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will be cleared when the Reset is complete. This bit is not enable-protected. Value 0 1 Description There is no ongoing Reset operation. The Reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 586 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.2 CTRLB - Control B Register Name:

Offset:

Reset:

Property:

CTRLB 0x01 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 STARTStart Measurement Value 0 1 Description Writing a '0' has no effect. Writing a '1' starts a measurement. 0 START W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 587 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.3 CFGA - Configuration A Register Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-protected CFGA 0x02 0x0000 Bit 15 14 13 12 11 10 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 3 REFNUM[7:0]

R/W 0 R/W 0 2 R/W 0 9 1 8 0 R/W 0 R/W 0 Bits 7:0 REFNUM[7:0]Number of Reference Clock Cycles Selects the duration of a measurement in number of GCLK_FREQM_REF cycles. This must be a non-zero value, i.e. 0x01 (one cycle) to 0xFF (255 cycles). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 588 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.4 INTENCLR - Interrupt Enable Clear Register Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x08 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 DONEMeasurement Done Interrupt Enable 0 DONE R/W 0 Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done interrupt. Value 0 1 Description The Measurement Done interrupt is disabled. The Measurement Done interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 589 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.5 INTENSET - Interrupt Enable Set Register Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x09 0x00 Bit 7 6 5 4 3 2 1 Access Reset 0 DONE R/W 0 Bit 0 DONEMeasurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done interrupt. Value 0 1 Description The Measurement Done interrupt is disabled. The Measurement Done interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 590 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.6 INTFLAG - Interrupt Flag Status and Clear Register Name:

Offset:

Reset:

Property:

INTFLAG 0x0A 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 DONEMesurement Done This flag is cleared by writing a '1' to it. This flag is set when the STATUS.BUSY bit has a one-to-zero transition. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DONE interrupt flag. 0 DONE R/W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 591 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.7 STATUS - Status Register Name:

Offset:

Reset:

Property:

STATUS 0x0B 0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 OVFSticky Count Value Overflow This bit is cleared by writing a '1' to it. This bit is set when an overflow condition occurs to the value counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the OVF status. Bit 0 BUSYFREQM Status Value 0 1 Description No ongoing frequency measurement. Frequency measurement is ongoing. 1 OVF R/W 0 0 BUSY R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 592 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.8 SYNCBUSY - Synchronization Busy Register Name:

Offset:

Reset:

Property:

SYNCBUSY 0x0C 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 1 ENABLEEnable This bit is cleared when the synchronization of CTRLA.ENABLE is complete. This bit is set when the synchronization of CTRLA.ENABLE is started. Bit 0 SWRSTSynchronization Busy This bit is cleared when the synchronization of CTRLA.SWRST is complete. This bit is set when the synchronization of CTRLA.SWRST is started. 1 ENABLE R 0 0 SWRST R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 593 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Frequency Meter (FREQM) 25.8.9 VALUE - Value Register Name:

Offset:

Reset:

Property:

VALUE 0x10 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 23 R 0 15 R 0 7 R 0 22 R 0 14 R 0 6 R 0 21 R 0 13 R 0 5 R 0 20 19 VALUE[23:16]

R 0 12 R 0 4 R 0 VALUE[15:8]

VALUE[7:0]

R 0 11 R 0 3 R 0 18 R 0 10 R 0 2 R 0 17 16 R 0 9 R 0 1 R 0 R 0 8 R 0 0 R 0 Bits 23:0 VALUE[23:0]Measurement Value Result from measurement. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 594 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26. Event System (EVSYS) 26.1 Overview The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users. Peripherals that generate events are called event generators. A peripheral can have one or more event generators and can have one or more event users. Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based system. 26.2 Features 32 configurable event channels:

All channels can be connected to any event generator All channels provide a pure asynchronous path Twelve channels provide a resynchronized or synchronous path 81 event generators. 57 event users. Configurable edge detector. Peripherals can be event generators, event users, or both. Sleep-Walking and interrupt for operation in sleep modes. Software event generation. Each event user can choose which channel to respond to. Optional Static or Round-Robin interrupt priority arbitration. 26.3 Block Diagram Figure 26-1. Event System Block Diagram Clock Request [n:0]

Event Channel n Event Channel 1 Event Channel 0 Asynchronous Path CHANNEL0.PATH USER m+1 USER m USERm.CHANNEL SleepWalking Detector Synchronized Path Edge Detector D Q R Channel_EVT_n EVT Channel_EVT_0 CHANNEL0.EVGEN SWEVT.CHANNEL0 CHANNEL0.EDGSEL GCLK_EVSYS_0 Resynchronized Path D Q D Q D Q R R R EVT ACK DQ DQ DQ R R R PERIPHERAL0 PERIPHERAL x To Peripheral x Peripheral x Event Acknowledge 26.4 Signal Description Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 595 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 26.5.1 I/O Lines Not applicable. 26.5.2 Power Management The EVSYS can be used to wake up the CPU from Idle and Standby Sleep mode, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. See Power Management Unit (PMU) from Related Links for details on the different sleep modes. In sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS clock. Some event generators can generate an event when their clocks are stopped. The generic clock for the channel

(GCLK_EVSYS_CH_n) will be restarted if that channel uses a synchronized path or a resynchronized path. It does not need to wake the system from sleep. Related Links 14. Power Management Unit (PMU) 26.5.3 Clocks The EVSYS bus clock (PB2_CLK) can be enabled and disabled in the CRU. Each EVSYS channel which can be configured as synchronous or resynchronized has a dedicated generic clock (GCLK_EVSYS_CH_n). These are used for event detection and propagation for each channel. These clocks must be configured and enabled in the generic clock generator before using the EVSYS. See Peripheral Clock Generation (GCLK) from Related Links for more details on clock generation. Important:Only EVSYS channel 0 to 11 can be configured as synchronous or resynchronized. Related Links 13.3.7. Peripheral Clock Generation (GCLK) 26.5.4 DMA Not applicable. 26.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the EVSYS interrupts requires the interrupt controller to be configured first (see Nested Vector Interrupt Controller (NVIC) from Related Links). Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 26.5.6 Events Not applicable. 26.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging. 26.5.8 Register Access Protection Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 596 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) Channel Pending Interrupt (INTPEND) Channel n Interrupt Flag Status and Clear (CHINTFLAGn) Note:Optional write protection is indicated by the "PAC Write Protection" property in the register description. When the CPU is halted in debug mode, all write protection is automatically disabled. Write protection does not apply for accesses through an external debugger. 26.5.9 Analog Connections Not applicable. 26.6 Functional Description 26.6.1 Principle of Operation The Event System consists of channels which route the internal events from peripherals (generators) to other internal peripherals. Each event generator can be selected as source for multiple channels, but a channel cannot be set to use multiple event generators at the same time. A channel path can be configured in asynchronous, synchronous or resynchronized mode of operation. The mode of operation must be selected based on the requirements of the application. When using synchronous or resynchronized path, the Event System includes options to transfer events to users when rising, falling or both edges are detected on event generators. See Channel Path from Related Links. Related Links 26.6.2.6. Channel Path 26.6.2 Basic Operation 26.6.2.1 Initialization Before enabling event routing within the system, the Event Users Multiplexer and Event Channels must be selected in the Event System (EVSYS), and the two peripherals that generate and use the event must be configured. Follow these steps to configure the event:

1. In the peripheral generating the event, enable output of event by writing a 1 to the respective Event Output Enable bit ("EO") in the peripheral's Event Control register, for example, AC.EVCTRL.WINEO0 or RTC.EVCTRL.OVFEO. 2. Configure the EVSYS:

a. Configure the Event User multiplexer by writing the respective EVSYS.USERm register, see User Multiplexer Setup from Related Links. b. Configure the Event Channel by writing the respective EVSYS.CHANNELn register, see Event System Channel from Related Links. 3. Configure the action to be executed by the event user peripheral by writing to the Event Action bits (EVACT) in 4. the respective Event control register, for example, TC.EVCTRL.EVACT. Note:This step is not applicable for all the peripherals. In the event user peripheral, enable event input by writing a 1 to the respective Event Input Enable bit ("EI") in the peripheral's Event Control register, for example, AC.EVCTRL.IVEI0. Note:The ADC, CVD, and ZB modules do not have EVCTRL register, and hence EVCTRL register configuration is not applicable for these modules. Related Links 26.6.2.3. User Multiplexer Setup 26.6.2.4. Event System Channel 26.6.2.2 Enabling, Disabling, and Resetting The EVSYS is always enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 597 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) The EVSYS is reset by writing a 1 to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the EVSYS will be reset to their initial state and all ongoing events will be canceled. Refer to CTRLA.SWRST register for details. 26.6.2.3 User Multiplexer Setup The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channels output and must be configured to select one of these channels, as shown in Block Diagram section. The channel is selected with the Channel bit group in the User register

(USERm.CHANNEL). The user multiplexer must always be configured before the channel. A list of all available event users is found in the User (USERm) register description. Related Links 26.3. Block Diagram 26.6.2.4 Event System Channel An event channel can select one event from a list of event generators. Depending on configuration, the selected event could be synchronized, resynchronized or asynchronously sent to the users. When synchronization or resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate internal events when rising, falling or both edges are detected on the selected event generator. An event channel is able to generate internal events for the specific software commands. A channel block diagram is shown in Block Diagram section. Related Links 26.3. Block Diagram 26.6.2.5 Event Generators Each event channel can receive the events from all event generators. All event generators are listed in the Event Generator bit field in the Channel n register (CHANNELn.EVGEN). For details on event generation, refer to the corresponding module chapter. The channel event generator is selected by the Event Generator bit group in the Channel register (CHANNELn.EVGEN). By default, the channels are not connected to any event generators (ie, CHANNELn.EVGEN = 0) 26.6.2.6 Channel Path There are different ways to propagate the event from an event generator:

Asynchronous path Synchronous path Resynchronized path The path is decided by writing to the Path Selection bit group of the Channel register (CHANNELn.PATH). Asynchronous Path When using the asynchronous path, the events are propagated from the event generator to the event user without intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CH_n) is not mandatory, meaning that an event will be propagated to the user without any clock latency. When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel x Status register (CHSTATUSx) is always zero. The edge detection is not required and must be disabled by software. Each peripheral event user has to select which event edge must trigger internal actions. For further details, refer to each peripheral chapter description. Synchronous Path The synchronous path must be used when the event generator and the event channel share the same generator for the generic clock. If they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. When using the synchronous path, the channel is able to generate interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 598 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) Resynchronized Path The resynchronized path are used when the event generator and the event channel do not share the same generator for the generic clock. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. When the resynchronized path is used, the channel is able to generate interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. 26.6.2.7 Edge Detection When synchronous or resynchronized paths are used, edge detection must be enabled. The event system can execute edge detection in three different ways:

Generate an event only on the rising edge Generate an event only on the falling edge Generate an event on rising and falling edges. Edge detection is selected by writing to the Edge Selection bit group of the Channel register (CHANNELn.EDGSEL). 26.6.2.8 Event Latency The latency from event generator to event user depends on the channel's configuration:

Asynchronous Path: The maximum routing latency of an external event is related to the internal signal routing and it is device dependent. Synchronous Path: The maximum routing latency of an external event is one GCLK_EVSYS_CH_n clock cycle. Resynchronized Path: The maximum routing latency of an external event is three GCLK_EVSYS_CH_n clock cycles. The maximum propagation latency of a user event to the peripheral clock core domain is three peripheral clock cycles. The event generators, event channel and event user clocks ratio must be selected in relation with the internal event latency constraints. Events propagation or event actions in peripherals may be lost if the clock setup violates the internal latencies. 26.6.2.9 The Overrun Channel n Interrupt The Overrun Channel n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAGn.OVR) will be set, and the optional interrupt will be generated in the following cases:

One or more event users on channel n is not ready when there is a new event An event occurs when the previous event on channel m has not been handled by all event users connected to that channel The flag will only be set when using synchronous or resynchronized paths. In the case of asynchronous path, the INTFLAGn.OVR is always read as zero. 26.6.2.10 The Event Detected Channel n Interrupt The Event Detected Channel n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAGn.EVD) is set when an event coming from the event generator configured on channel n is detected. The flag will only be set when using a synchronous or resynchronized path. In the case of an asynchronous path, the INTFLAGn.EVD is always zero. 26.6.2.11 Channel Status The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:

The CHSTATUSn.BUSYCH bit will be set when an event on the corresponding channel n has not been handled by all event users connected to that channel. The CHSTATUSn.RDYUSR bit will be set when all event users connected to the corresponding channel are ready to handle incoming events on that channel. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 599 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.6.2.12 Software Event A software event can be initiated on a channel by writing a '1' to the Software Event bit in the Channel register

(SWEVT.CHANNELn). Then the software event can be serviced as any event generator; i.e., when a bit is set to 1, the corresponding event will be generated on the respective channel. 26.6.2.13 Interrupt Status and Interrupts Arbitration The Interrupt Status register stores all channels with pending interrupts, as shown in the following figure. Figure 26-2. Interrupt Status Register 31 30 1 0 INTSTATUS CHINTFLAG31.OVR CHINTENSET31.OVR CHINTFLAG31.EVD CHINTENSET31.EVD CHINTFLAG0.OVR CHINTENSET0.OVR CHINTFLAG0.EVD CHINTENSET0.EVD The Event System can arbitrate between all channels with pending interrupts. The arbiter can be configured to prioritize statically or dynamically the incoming events. The priority is evaluated each time a new channel has an interrupt pending, or an interrupt has been cleared. The Channel Pending Interrupt register (INTPEND) will provide the channel number with the highest interrupt priority, and the corresponding channel interrupt flags and status bits. By default, static arbitration is enabled (PRICTRL.RREN is 0), the arbiter will prioritize a low channel number over a high channel number as shown below. When using the status scheme, there is a risk of high channel numbers never being granted access by the arbiter. This can be avoided using a dynamic arbitration scheme. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 600 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) Figure 26-3. Static Priority Lowest Channel Channel 0 Highest Priority

. Channel x Channel x+1

. Highest Channel Channel N Lowest Priority The dynamic arbitration scheme available in the Event System is round-robin. Round-robin arbitration is enabled by writing PRICTRL.RREN to one. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel, as shown in the following figure. The channel number of the last channel being granted access, will be stored in the Channel Priority Number bit group in the Priority Control register (PRICTRL.PRI). Figure 26-4. Round-Robin Scheduling Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel 0 Channel x Channel x+1 Lowest Priority Highest Priority Channel N

. Channel x Channel x+1 Channel x+2

. Channel N Lowest Priority Highest Priority 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 601 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) The Channel Pending Interrupt register (INTPEND) also offers the possibility to indirectly clear the interrupt flags of a specific channel. Writing a flag to one in this register, will clear the corresponding interrupt flag of the channel specified by the INTPEND.ID bits. 26.6.3 Interrupts The EVSYS has the following interrupt sources for each channel:

Overrun Channel n interrupt (OVR) Event Detected Channel n interrupt (EVD) These interrupts events are asynchronous wake-up sources. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the corresponding Channel n Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Note:Interrupts must be globally enabled to allow the generation of interrupt requests. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Channel n Interrupt Enable Set (CHINTENSET) register, and disabled by writing a '1' to the corresponding bit in the Channel n Interrupt Enable Clear (CHINTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the Event System is reset. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts, and must read the Channel n Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register

(INTPEND), which provides the highest priority channel with pending interrupt and the respective interrupt flags. 26.6.4 Sleep Mode Operation The Event System can generate interrupts to wake up the device from IDLE or STANDBY sleep mode. To be able to run in standby, the Run in Standby bit in the Channel register (CHANNELn.RUNSTDBY) must be set to '1'. When the Generic Clock On Demand bit in Channel register (CHANNELn.ONDEMAND) is set to '1' and the event generator is detected, the event channel will request its clock (GCLK_EVSYS_CHANNEL_n). The event latency for a resynchronized channel path will increase by two GCLK_EVSYS_CHANNEL_n clock (i.e., up to five GCLK_EVSYS_CHANNEL_n clock cycles). A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and CHANNELn.ONDEMAND:

Table 26-1. Event Channel Sleep Behavior CHANNELn.PATH CHANNELn. ONDEMAND CHANNELn. RUNSTDBY Sleep Behavior ASYNC SYNC/RESYNC SYNC/RESYNC SYNC/RESYNC 0 0 1 1 0 1 0 1 Only run in IDLE modes if an event must be propagated. Disabled in STANDBY sleep mode. Run in both IDLE and STANDBY sleep modes. Only run in IDLE modes if an event must be propagated. Disabled in STANDBY sleep mode. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. Run in both IDLE and STANDBY sleep modes. Two GCLK_EVSYS_n latency added in RESYNC path before the event is propagated internally. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 602 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.7 Register Summary See EVSYS module in the Product Memory Mapping Overview from Related Links for base address. Offset 0x00 0x01

... 0x03 Name CTRLA Reserved 0x04 SWEVT 0x08 0x09

... 0x0F 0x10 0x12

... 0x13 PRICTRL Reserved INTPEND Reserved 0x14 INTSTATUS 0x18 BUSYCH 0x1C READYUSR 0x20 CHANNEL0 0x24 0x25 0x26 0x27 CHINTENCLR0 CHINTENSET0 CHINTFLAG0 CHSTATUSn0 0x28 CHANNEL1 0x2C 0x2D 0x2E 0x2F CHINTENCLR1 CHINTENSET1 CHINTFLAG1 CHSTATUSn1 0x30 CHANNEL2 0x34 0x35 0x36 0x37 CHINTENCLR2 CHINTENSET2 CHINTFLAG2 CHSTATUSn2 Bit Pos. 7 6 5 4 3 2 1 0 SWRST CHANNEL7 CHANNEL6 CHANNEL5 CHANNEL4 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 CHANNEL15 CHANNEL14 CHANNEL13 CHANNEL12 CHANNEL11 CHANNEL10 CHANNEL9 CHANNEL8 CHANNEL23 CHANNEL22 CHANNEL21 CHANNEL20 CHANNEL19 CHANNEL18 CHANNEL17 CHANNEL16 CHANNEL31 CHANNEL30 CHANNEL29 CHANNEL28 CHANNEL27 CHANNEL26 CHANNEL25 CHANNEL24 RREN PRI[4:0]

BUSY READY ID[3:0]

EVD OVR CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT11 CHINT10 CHINT1 CHINT9 CHINT0 CHINT8 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8 7:0 7:0 15:8 23:16 31:24 7:0 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 READYUSR7 READYUSR6 READYUSR5 READYUSR4 READYUSR3 READYUSR2 READYUSR1 READYUSR0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 READYUSR1 1 READYUSR1 0 READYUSR9 READYUSR8 ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 603 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x38 CHANNEL3 0x3C 0x3D 0x3E 0x3F CHINTENCLR3 CHINTENSET3 CHINTFLAG3 CHSTATUSn3 0x40 CHANNEL4 0x44 0x45 0x46 0x47 CHINTENCLR4 CHINTENSET4 CHINTFLAG4 CHSTATUSn4 0x48 CHANNEL5 0x4C 0x4D 0x4E 0x4F CHINTENCLR5 CHINTENSET5 CHINTFLAG5 CHSTATUSn5 0x50 CHANNEL6 0x54 0x55 0x56 0x57 CHINTENCLR6 CHINTENSET6 CHINTFLAG6 CHSTATUSn6 0x58 CHANNEL7 0x5C 0x5D 0x5E 0x5F CHINTENCLR7 CHINTENSET7 CHINTFLAG7 CHSTATUSn7 0x60 CHANNEL8 0x64 0x65 0x66 0x67 CHINTENCLR8 CHINTENSET8 CHINTFLAG8 CHSTATUSn8 0x68 CHANNEL9 0x6C 0x6D 0x6E 0x6F CHINTENCLR9 CHINTENSET9 CHINTFLAG9 CHSTATUSn9 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 604 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

EVD EVD EVD OVR OVR OVR BUSYCH RDYUSR ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x70 CHANNEL10 0x74 0x75 0x76 0x77 CHINTENCLR10 CHINTENSET10 CHINTFLAG10 CHSTATUSn10 0x78 CHANNEL11 0x7C 0x7D 0x7E 0x7F CHINTENCLR11 CHINTENSET11 CHINTFLAG11 CHSTATUSn11 0x80 CHANNEL12 0x84

... 0x87 Reserved 0x88 CHANNEL13 0x8C

... 0x8F Reserved 0x90 CHANNEL14 0x94

... 0x97 Reserved 0x98 CHANNEL15 0x9C

... 0x9F Reserved 0xA0 CHANNEL16 0xA4

... 0xA7 Reserved 0xA8 CHANNEL17 0xAC

... 0xAF Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 605 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0xB0 CHANNEL18 0xB4

... 0xB7 Reserved 0xB8 CHANNEL19 0xBC

... 0xBF Reserved 0xC0 CHANNEL20 0xC4

... 0xC7 Reserved 0xC8 CHANNEL21 0xCC

... 0xCF Reserved 0xD0 CHANNEL22 0xD4

... 0xD7 Reserved 0xD8 CHANNEL23 0xDC

... 0xDF Reserved 0xE0 CHANNEL24 0xE4

... 0xE7 Reserved 0xE8 CHANNEL25 0xEC

... 0xEF Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 606 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0xF0 CHANNEL26 0xF4

... 0xF7 Reserved 0xF8 CHANNEL27 0xFC

... 0xFF Reserved 0x0100 CHANNEL28 0x0104

... 0x0107 Reserved 0x0108 CHANNEL29 0x010C

... 0x010F Reserved 0x0110 CHANNEL30 0x0114

... 0x0117 Reserved 0x0118 CHANNEL31 0x011C

... 0x011F 0x0120

... Reserved USER0 0x0158 USER56 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

ONDEMAND RUNSTDBY EDGSEL[1:0]

PATH[1:0]

EVGEN[6:0]

CHANNEL[5:0]

CHANNEL[5:0]

Related Links 7. Product Memory Mapping Overview 26.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. For more details, see Register Access Protection and Peripheral Access Controller (PAC) from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 607 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) Related Links 20. Peripheral Access Controller (PAC) 26.5.8. Register Access Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 608 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection CTRLA 0x00 0x00 Bit 7 6 5 4 3 2 1 Access Reset Bit 0 SWRSTSoftware Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the EVSYS to their initial state. Note:Before applying a Software Reset it is recommended to disable the event generators. 0 SWRST W 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 609 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.2 Software Event Name:

Offset:

Reset:

Property: PAC Write-Protection SWEVT 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 CHANNEL31 CHANNEL30 CHANNEL29 CHANNEL28 CHANNEL27 CHANNEL26 CHANNEL25 CHANNEL24 Access Reset Bit W 0 23 W 0 22 W 0 21 W 0 20 W 0 19 W 0 18 W 0 17 W 0 16 CHANNEL23 CHANNEL22 CHANNEL21 CHANNEL20 CHANNEL19 CHANNEL18 CHANNEL17 CHANNEL16 Access Reset Bit W 0 15 W 0 14 W 0 13 W 0 12 CHANNEL15 CHANNEL14 CHANNEL13 CHANNEL12 W 0 W 0 W 0 W 0 W 0 W 0 11 CHANNEL11 W 0 10 CHANNEL10 W 0 9 CHANNEL9 W 0 Access Reset Bit W 0 7 CHANNEL7 Access Reset W 0 6 CHANNEL6 W 0 5 CHANNEL5 W 0 4 CHANNEL4 W 0 3 CHANNEL3 W 0 2 CHANNEL2 W 0 1 CHANNEL1 W 0 W 0 8 CHANNEL8 W 0 0 CHANNEL0 W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 CHANNELx Channel x Software Selection [x=0..31]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will trigger a software event for channel x. These bits always return 0 when read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 610 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.3 Priority Control Name:

Offset:

Reset:

Property: PAC Write-Protection PRICTRL 0x08 0x00 Bit Access Reset 7 RREN RW 0 6 5 4 RW 0 3 RW 0 2 PRI[4:0]

RW 0 1 RW 0 0 RW 0 Bit 7 RRENRound-Robin Scheduling Enable For details on scheduling schemes, see Interrupt Status and Interrupts Arbitration from Related Links. Value 0 1 Description Static scheduling scheme for channels with level priority Round-robin scheduling scheme for channels with level priority Bits 4:0 PRI[4:0]Channel Priority Number When round-robin arbitration is enabled (PRICTRL.RREN=1) for priority level, this register holds the channel number of the last EVSYS channel being granted access as the active channel with priority level. The value of this bit group is updated each time the INTPEND or any of CHINTFLAG registers are written. When static arbitration is enabled (PRICTRL.RREN=0) for priority level, and the value of this bit group is nonzero, it will not affect the static priority scheme. This bit group is not reset when round-robin scheduling gets disabled (PRICTRL.RREN written to zero). Related Links 26.6.2.13. Interrupt Status and Interrupts Arbitration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 611 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.4 Channel Pending Interrupt Name:

Offset:

Reset:

INTPEND 0x10 0x4000 An interrupt that handles several channels should consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register. Bit Access Reset 15 BUSY R 0 14 READY R 1 13 12 11 10 Bit 7 6 5 4 Access Reset Bit 15 BUSYBusy 3 RW 0 ID[3:0]

2 RW 0 9 EVD RW 0 1 RW 0 8 OVR RW 0 0 RW 0 This bit is read '1' when the event on a channel selected by Channel ID field (ID) has not been handled by all the event users connected to this channel. Bit 14 READYReady This bit is read '1' when all event users connected to the channel selected by Channel ID field (ID) are ready to handle incoming events on this channel. Bit 9 EVDChannel Event Detected This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if CHINTENCLR/SET.EVD is '1'. When the event channel path is asynchronous, the EVD bit will not be set. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn) of this peripheral, where n is determined by the Channel ID bit field (ID) in this register. Bit 8 OVRChannel Overrun This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request will be generated if CHINTENCLR/SET.OVRx is '1'. There are two possible overrun channel conditions:

One or more of the event users on channel selected by Channel ID field (ID) are not ready when a new event occurs An event happens when the previous event on channel selected by Channel ID field (ID) has not yet been handled by all event users When the event channel path is asynchronous, the OVR interrupt flag will not be set. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear it. It will also clear the corresponding flag in the Channel n Interrupt Flag Status and Clear register (CHINTFLAGn) of this peripheral, where n is determined by the Channel ID bit field (ID) in this register. Bits 3:0 ID[3:0]Channel ID These bits store the channel number of the highest priority. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 612 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.5 Interrupt Status Name:

Offset:

Reset:

INTSTATUS 0x14 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit Access Reset 7 CHINT7 R 0 6 CHINT6 R 0 5 CHINT5 R 0 4 CHINT4 R 0 11 CHINT11 R 0 3 CHINT3 R 0 10 CHINT10 R 0 2 CHINT2 R 0 9 CHINT9 R 0 1 CHINT1 R 0 8 CHINT8 R 0 0 CHINT0 R 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 CHINTxChannel x Pending Interrupt This bit is set when Channel x has a pending interrupt. This bit is cleared when the corresponding Channel x interrupts are disabled, or the source interrupt sources are cleared. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 613 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.6 Busy Channels Name:

Offset:

Reset:

BUSYCH 0x18 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset 11 BUSYCH11 R 0 10 BUSYCH10 R 0 Bit 7 BUSYCH7 Access Reset R 0 6 BUSYCH6 R 0 5 BUSYCH5 R 0 4 BUSYCH4 R 0 3 BUSYCH3 R 0 2 BUSYCH2 R 0 9 BUSYCH9 R 0 1 BUSYCH1 R 0 8 BUSYCH8 R 0 0 BUSYCH0 R 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 BUSYCHBusy Channel x This bit is set if an event occurs on channel x has not been handled by all event users connected to channel x. This bit is cleared when channel x is idle. When the event channel x path is asynchronous, this bit is always read 0. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 614 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.7 Ready Users Name:

Offset:

Reset:

READYUSR 0x1C 0x00000FFF Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 READYUSR11 READYUSR10 READYUSR9 READYUSR8 R 1 3 R 1 2 R 1 1 R 1 0 READYUSR7 READYUSR6 READYUSR5 READYUSR4 READYUSR3 READYUSR2 READYUSR1 READYUSR0 Access Reset R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 READYUSRnReady User for Channel n This bit is set when all event users connected to channel n are ready to handle incoming events on channel n. This bit is cleared when at least one of the event users connected to the channel is not ready. When the event channel n path is asynchronous, this bit is always read zero. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 615 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.8 Channel n Control Name:

Offset:

Reset:

Property: PAC Write-Protection CHANNEL 0x20 + n*0x08 [n=0..31]

0x00008000 This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 ONDEMAND Access Reset RW 1 14 RUNSTDBY RW 0 Bit 7 Access Reset 6 RW 0 5 RW 0 4 RW 0 Bit 15 ONDEMANDGeneric Clock On Demand 13 12 11 10 EDGSEL[1:0]

RW 0 3 EVGEN[6:0]

RW 0 RW 0 2 RW 0 PATH[1:0]

9 RW 0 1 RW 0 8 RW 0 0 RW 0 This bit is used to determine whether the generic clock is requested. Value 0 Description Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. Generic clock is requested on demand while an event is handled 1 Bit 14 RUNSTDBYRun in Standby This bit is used to define the behavior during standby sleep mode. Value 0 1 Description The channel is disabled in standby sleep mode. The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. Bits 11:10 EDGSEL[1:0]Edge Detection Selection These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. Value 0x0 0x1 0x2 0x3 Name NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path RISING_EDGE FALLING_EDGE BOTH_EDGES Event detection only on the rising edge of the signal from the event generator Event detection only on the falling edge of the signal from the event generator Event detection on rising and falling edges of the signal from the event generator Description Bits 9:8 PATH[1:0]Path Selection These bits are used to choose which path will be used by the selected channel. Note:The path choice can be limited by the channel source, see USERm from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 616 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) Important:Only EVSYS channel 0 to 11 can be configured as synchronous or resynchronized. Value 0x0 0x1 0x2 Other Name SYNCHRONOUS RESYNCHRONIZED ASYNCHRONOUS

Description Synchronous path Resynchronized path Asynchronous path Reserved Bits 6:0 EVGEN[6:0]Event Generator Selection These bits are used to choose the event generator to connect to the selected channel. Table 26-2. Event Generator Selection Value 0x00 - 0x07 0x08 - 0x0B 0x0C 0x0D 0x0E - 0x11 0x12 - 0x15 0x16 0x17 0x18 0x19 0x1A-0x1F 0x20 0x21 0x22 0x23 - 0x28 0x29 0x2A 0x2B 0x2C - 0x2D 0x2E 0x2F-0x30 0x31 0x32 - 0x33 0x34 0x35 - 0x36 0x37 0x38 - 0x39 0x3A 0x3B - 0x3C 0x3D 0x3E - 0x3F 0x40 0x41 - 0x42 0x43 0x44 - 0x45 0x46 0x47 - 0x48 0x49 - 0x4A 0x4B 0x4C Name RTC_PERx RTC_CMPx RTC_TAMPER RTC_OVF EIC_EXTINTx DMAC_CHx PAC_ACCERR TCC0_OVF TCC0_TRG TCC0_CNT TCC0_MCx TCC1_OVF TCC1_TRG TCC1_CNT TCC1_MCx TCC2_OVF TCC2_TRG TCC2_CNT TCC2_MCx TC0_OVF TC0_MCx TC1_OVF TC1_MCx TC2_OVF TC2_MCx TC3_OVF TC3_MCx TC4_OVF TC4_MCx TC5_OVF TC5_MCx TC6_OVF TC6_MCx TC7_OVF TC7_MCx ADC_RESRDY Not used AC_COMPx AC_WIN_0 Not used Description RTC period x=0..7 RTC comparison x=0..3 RTC tamper detection RTC Overflow EIC external interrupt x=0..3 DMA channel x=0..3 PAC Acc. error TCC0 Overflow TCC0 Trigger Event TCC0 Counter TCC0 Match/Compare x=0..5 TCC1 Overflow TCC1 Trigger Event TCC1 Counter TCC1 Match/Compare x=0..5 TCC2 Overflow TCC2 Trigger Event TCC2 Counter TCC2 Match/Compare x=0..1 TC0 Overflow TC0 Match/Compare x=0..1 TC1 Overflow TC1 Match/Compare x=0..1 TC2 Overflow TC2 Match/Compare x=0..1 TC3 Overflow TC3 Match/Compare x=0..1 TC4 Overflow TC4 Match/Compare x=0..1 TC5 Overflow TC5 Match/Compare x=0..1 TC6 Overflow TC6 Match/Compare x=0..1 TC7 Overflow TC7 Match/Compare x=0..1 ADC End-Of-Scan Ready Interrupt AC Comparator, x=0..1 AC0 Window 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 617 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS)

...........continued Value 0x4D - 0x4E 0x4F 0x50 Related Links 26.8.13. USERm Name CCL_LUTOUTx ZB_TX_TS_ACTIVE ZB_RX_TS_ACTIVE Description CCL LUTOUT x-0..1 ZB Transmit Packet Active time ZB Receive Packet Active time 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 618 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.9 Channel n Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection CHINTENCLR 0x24 + n*0x08 [n=0..11]

0x00 Bit 7 6 5 4 3 2 Access Reset 1 EVD RW 0 0 OVR RW 0 Bit 1 EVDChannel Event Detected Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Event Detected Channel Interrupt Enable bit, which disables the Event Detected Channel interrupt. Value 0 1 Description The Event Detected Channel interrupt is disabled. The Event Detected Channel interrupt is enabled. Bit 0 OVRChannel Overrun Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Overrun Channel Interrupt Enable bit, which disables the Overrun Channel interrupt. Value 0 1 Description The Overrun Channel interrupt is disabled. The Overrun Channel interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 619 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.10 Channel n Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection CHINTENSET 0x25 + n*0x08 [n=0..11]

0x00 Bit 7 6 5 4 3 2 Access Reset 1 EVD RW 0 0 OVR RW 0 Bit 1 EVDChannel Event Detected Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Event Detected Channel Interrupt Enable bit, which enables the Event Detected Channel interrupt. Value 0 1 Description The Event Detected Channel interrupt is disabled. The Event Detected Channel interrupt is enabled. Bit 0 OVRChannel Overrun Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Overrun Channel Interrupt Enable bit, which enables the Overrun Channel interrupt. Value 0 1 Description The Overrun Channel interrupt is disabled. The Overrun Channel interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 620 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.11 Channel n Interrupt Flag Status and Clear Name:

Offset:

Reset:

CHINTFLAG 0x26 + n*0x08 [n=0..11]

0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 EVDChannel Event Detected 1 EVD RW 0 0 OVR RW 0 This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if CHINTENCLR/SET.EVD is 1. When the event channel path is asynchronous, the EVD interrupt flag will not be set. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Event Detected Channel interrupt flag. Bit 0 OVRChannel Overrun This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request will be generated if CHINTENCLR/SET.OVR is 1. There are two possible overrun channel conditions:

One or more of the event users on the channel are not ready when a new event occurs. An event happens when the previous event on channel has not yet been handled by all event users. When the event channel path is asynchronous, the OVR interrupt flag will not be set. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Overrun Channel interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 621 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.12 Channel n Status Name:

Offset:

Reset:

CHSTATUSn 0x27 + n*0x08 [n=0..11]

0x01 Bit 7 6 5 4 3 2 Access Reset Bit 1 BUSYCHBusy Channel 1 BUSYCH R 0 0 RDYUSR R 0 This bit is cleared when channel is idle. This bit is set if an event on channel has not been handled by all event users connected to channel. When the event channel path is asynchronous, this bit is always read '0'. Bit 0 RDYUSRReady User This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel are ready to handle incoming events on the channel. When the event channel path is asynchronous, this bit is always read zero. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 622 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Event System (EVSYS) 26.8.13 Event User m Name:

Offset:

Reset:

Property: PAC Write-Protection USERm 0x0120 + m*0x01 [m=0..56]

0x0 Bit 7 6 Access Reset 5 R/W 0 4 R/W 0 3 2 CHANNEL[5:0]

R/W 0 R/W 0 1 R/W 0 0 R/W 0 Bits 5:0 CHANNEL[5:0]Channel Event Selection These bits select channel n to connect to the event user m. Note:A value x of this bit field selects channel n = x-1. Table 26-3. User Multiplexer Number m USERm m = 0 m = 1..8 m = 9 m = 10 m = 11 m = 12..13 m = 14..19 m = 20..21 m = 22..27 m = 28..29 m = 30..31 m = 32 m = 33 m = 34 m = 35 m = 36 m = 37 m = 38 m = 39 m = 40..51 m = 52..53 m = 54..55 m = 56 User Multiplexer RTC_TAMPER DMAC_CH0..7 CM4_TRACE_START CM4_TRACE_STOP CM4_TRACE_TRIG TCC0 EV0..1 TCC0 MC0..5 TCC1 EV0..1 TCC1 MC0..5 TCC2 EV0..1 TCC2 MC0..1 TC0 EVU TC1 EVU TC2 EVU TC3 EVU TC4 EVU TC5 EVU TC6 EVU TC7 EVU ADC_TRIGGER5..16 AC_SOC0..1 CCL_LUTIN0..1 CVD_TRIGGER Description RTC Tamper Channel 0..7 CM4 trace start CM4 trace stop CM4 trace trigger TCC0 EVx TCC0 MCx TCC1 EVx TCC1 MCx TCC2 EVx TCC2 MCx TC0 EVU TC1 EVU TC2 EVU TC3 EVU TC4 EVU TC5 EVU TC6 EVU TC7 EVU ADC_TRIGGERx AC_SOCx CCL_LUTINx CVD_TRIGGER Path Type(1) A, S, R S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A, S, R A A, S, R A, S, R A 1) A = Asynchronous path, S = Synchronous path, R = Resynchronized path 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 623 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) 27. Serial Communication Interface (SERCOM) 27.1 Overview The device supports up to three SERCOM modules. Two SERCOMs (SERCOM0/1) can be configured to support a number of modes: I2C, SPI and USART. One of the SERCOM (SERCOM2) has only I2C functionality. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality and mode specific transmitter and receiver logic. It can use the internal generic clock or an external clock. 27.2 Features Interface for Configuring into one of the following:

Inter-Integrated Circuit (I2C) two-wire serial interface Serial Peripheral Interface (SPI) Universal Synchronous/Asynchronous Receiver/Transmitter (USART) System Management Bus (SMBus) compatible Single Transmit Buffer and Double Receive Buffer Baud-rate Generator Address Match/Mask Logic Operational in Idle, and Standby Sleep mode with an External Clock Source Can be used with DMA 27.3 Block Diagram Figure 27-1. SERCOM Block Diagram SERCOM Register Interface CONTROL/STATUS TX/RX DATA BAUD/ADDR Mode Specific Mode n Mode 1 Mode 0 Serial Engine Transmitter Receiver Baud Rate Generator Address Match PAD[3:0]

27.4 Signal Description See the respective SERCOM mode chapters for details. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 624 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) 27.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines Using the SERCOM I/O lines requires the I/O pins to be configured using the System Configuration registers or PPS. The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 27.5.2 Power Management The SERCOM can operate in any Sleep mode (Idle, Standby Sleep) provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from sleep modes. 27.5.3 Clocks The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a Host. The slow clock

(GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. See Clock and Reset Unit (CRU) from Related Links. The generic clocks are asynchronous to the bus clock (PBx_CLK). Therefore, writing to certain registers will require synchronization between the clock domains. Related Links 13. Clock and Reset Unit (CRU) 27.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used. See Direct Memory Access Controller (DMAC) from Related Links. Related Links 22. Direct Memory Access Controller (DMAC) 27.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the SERCOM interrupts are used. 27.5.6 Events Not applicable. 27.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control

(DBGCTRL) register for details. 27.5.8 Register Access Protection Registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC). Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 625 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) PAC write protection does not apply to accesses through an external debugger. 27.5.9 Analog Connections Not applicable. 27.6 Functional Description 27.6.1 Principle of Operation The basic structure of the SERCOM serial engine is shown in SERCOM Serial Engine. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock. Figure 27-2. SERCOM Serial Engine Selectable Internal Clk

(GCLK) Ext Clk Transmitter Address Match BAUD TX DATA ADDR/ADDRMASK Baud Rate Generator 1/- /2- /16 TX Shift Register Receiver RX Shift Register Baud Rate Generator Status RX Buffer STATUS RX DATA Equal The transmitter consists of a single write buffer and a Shift register. The receiver consists of a one-level (I2C), or two-level (USART, SPI) receive buffer and a Shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I2C operation. 27.6.2 Basic Operation 27.6.2.1 Initialization The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register

(CTRLA.MODE) as shown in the table below. Table 27-1. SERCOM Modes CTRLA.MODE Description 0x0 0x1 0x2 0x3 USART with external clock USART with internal clock SPI in client operation SPI in host operation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 626 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM)

...........continued CTRLA.MODE 0x4 0x5 0x6-0x7 Description I2C client operation I2C host operation Reserved For further initialization information, see the respective SERCOM mode chapters:

27.6.2.2 Enabling, Disabling, and Resetting This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing 1 to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details. 27.6.2.3 Clock Generation Baud-Rate Generator The baud-rate generator, as shown in the following figure, generates internal clocks for asynchronous and synchronous communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external. For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divide-

by-1) output is used while receiving. For synchronous communication, the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. Figure 27-3. Baud Rate Generator Selectable Internal Clk

(GCLK) Ext Clk Baud Rate Generator fref 1 0 Base Period

/2

/8 CTRLA.MODE[0]

/1

/2

/16 Tx Clk CTRLA.MODE Rx Clk 0 1 1 0 1 0 Clock Recovery The following table contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode. For asynchronous operation, there are two modes:

Arithmetic mode: the BAUD register value is 16 bits (0 to 65,535) Fractional mode: the BAUD register value is 13 bits, while the fractional adjustment is 3 bits. In this mode the BAUD setting must be greater than or equal to 1. fractional mode, the BAUD register value is 13 bits, while the fractional adjustment is 3 bits. In this mode the BAUD setting must be greater than or equal to 1. For synchronous operation, the BAUD register value is 8 bits (0 to 255). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 627 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) Table 27-2. Baud Rate Equations Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation Asynchronous Arithmetic Asynchronous Fractional Synchronous fBAUD fBAUD fref 16 fref S fBAUD =

fref 16 1 BAUD 65536 fBAUD =

fref S BAUD +

FP 8 fBAUD fBAUD =

fref 2 fref 2 BAUD + 1 S - Number of samples per bit, which can be 16, 8, or 3. BAUD = 65536 1 S fBAUD fref BAUD =

fref S fBAUD FP 8 BAUD =

fref 2 fBAUD 1 The Asynchronous Fractional option is used for auto-baud detection. The baud rate error is represented by the following formula:

Error = 1 27.6.3 Additional Features ExpectedBaudRate ActualBaudRate 27.6.3.1 Address Match and Mask The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on the mode. Address With Mask An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted. Figure 27-4. Address With Mask ADDR ADDRMASK

Match rx shift register Two Unique Addresses The two addresses written to ADDR and ADDRMASK will cause a match. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 628 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) Figure 27-5. Two Unique Addresses ADDR rx shift register ADDRMASK

Match Address Range The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 27-6. Address Range ADDRMASK rx shift register ADDR

== Match 27.6.3.1.1 Address Mask An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note:Writing the ADDR.ADDRMASK to all zeros will match a single unique address, while writing ADDR.ADDRMASK to all ones will result in all addresses being accepted. Figure 27-7. Address With Mask ADDR ADDRMASK

Match rx shift register 27.6.3.1.2 Two Unique Addresses The two addresses written to ADDR and ADDRMASK will cause a match. Figure 27-8. Two Unique Addresses ADDR rx shift register ADDRMASK

Match 27.6.3.1.3 Address Range The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 629 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Serial Communication Interface (SERCOM) Figure 27-9. Address Range ADDRMASK rx shift register ADDR

== Match 27.6.4 DMA Operation The available DMA interrupts depend on the operation mode of the SERCOM peripheral. Refer to the Functional Description sections of the respective SERCOM mode. 27.6.5 Interrupts Interrupt sources are mode specific. See the respective SERCOM mode chapters for details. Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register

(INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SERCOM is reset. For details on clearing Interrupt flags, refer to the INTFLAG register description. The value of INTFLAG indicates which Interrupt condition occurred. The user must read the INTFLAG register to determine which Interrupt condition is present. Note:Interrupts must be globally enabled for interrupt requests to be generated. 27.6.6 Events Not applicable. 27.6.7 Sleep Mode Operation The peripheral can operate in any Sleep mode (Idle, Standby Sleep) where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake-up the device from Sleep modes. Refer to the different SERCOM mode chapters for details. 27.6.8 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 630 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28. SERCOM Synchronous and Asynchronous Receiver and Transmitter

(SERCOM USART) 28.1 Overview The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 28.3. Block Diagram. Labels in uppercase letters are synchronous to PB1_CLK and accessible for CPU. Labels in lowercase letters can be programmed to run on the internal generic clock or an external clock. The transmitter consists of a single write buffer, a Shift register, and control logic for different frame formats. The write buffer supports data transmission without any delay between frames. The receiver consists of a two-level receive buffer and a Shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. 28.2 USART Features Internal or external clock source for asynchronous and synchronous operation Full-duplex operation Asynchronous (with clock reconstruction) or synchronous operation Baud-rate generator Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits Odd or even parity generation and parity check Selectable LSB- or MSB-first data transfer Buffer overflow and frame error detection Noise filtering, including false start-bit detection and digital low-pass filter Collision detection Can operate in all sleep modes Operation at speeds up to half the system clock for internally generated clocks Operation at speeds up to the system clock for externally generated clocks RTS and CTS flow control LIN host support LIN client support IrDA modulation and demodulation up to 115.2kbps Auto-baud and break character detection ISO 7816 T=0 or T=1 protocols for Smart Card interfacing RS485 Support Start-of-frame detection Two-Level Receive Buffer Can work with DMA 32-bit extension for better system bus utilization Note:SERCOM2 does not have USART functionality. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 631 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.3 Block Diagram Figure 28-1. USART Block Diagram GCLK

(internal) BAUD TX DATA Baud Rate Generator CTRLA.MODE

/1 - /2 - /16 TX Shift Register XCK CTRLA.MODE RX Shift Register TxD RxD Status Two-level RX Buffer STATUS RX DATA 28.4 Signal Description Table 28-1. SERCOM USART Signals Signal Name PAD[3:0]

Type Digital I/O Description General SERCOM pins One signal can be mapped to one of several pins. Note:For details on pin mapping, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 28.5 Product Dependencies To use this peripheral, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines Using the USARTs I/O lines requires the I/O pins to be configured using the System Configuration registers (See System Configuration and Register Locking (CFG) from Related Links) (SCOM_HSEN[1:0] of CFGCON1/DEVCFG1 register). If SERCOM pins are selected through PPS, the PPS registers has to be configured (See I/O Ports and Peripheral Pin Select (PPS) from Related Links). If SCOMx_HSEN =1, SERCOM uses dedicated pins. If SCOMx_HSEN = 0, SERCOM uses PPS path, and I/O pins are multiplexed to pins groups defined in PPS section. When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins according to the table below. If the receiver or transmitter is disabled, these pins can be used for other purposes. Table 28-2. USART Pin Configuration Pin TxD Pin Configuration Output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 632 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... ..........continued Pin RxD XCK Pin Configuration Input Output or input The configuration of the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register

(CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in the above table. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 18. System Configuration and Register Locking (CFG) 28.5.2 Power Management This peripheral can continue to operate in any Sleep mode (Idle, Standby Sleep) where its source clock is running. The interrupts can wake-up the device from Sleep modes. 28.5.3 Clocks A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the CRU registers before using it for SERCOMx_CORE. See Clock and Reset Unit (CRU) and Overview from Related Links This generic clock is asynchronous to the bus clock (PB1_CLK). Therefore, writing to certain registers will require synchronization to the clock domains. Related Links 13. Clock and Reset Unit (CRU) 28.1. Overview 28.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). To use DMA requests with this peripheral, the DMAC must be configured first (see Direct Memory Access Controller (DMAC) from Related Links). Related Links 22. Direct Memory Access Controller (DMAC) 28.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the NVIC must be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 28.5.6 Events Not applicable. 28.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control

(DBGCTRL) register for details. Related Links 28.8.14. DBGCTRL 28.5.8 Register Access Protection Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 633 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... PAC write protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. 28.5.9 Analog Connections Not applicable. 28.6 Functional Description 28.6.1 Principle of Operation The USART uses the following lines for data transfer:

RxD for receiving TxD for transmitting XCK for the transmission clock in synchronous operation USART data transfer is frame based. A serial frame consists of:

1 start bit From 5 to 9 data bits (MSB or LSB first) No, even or odd parity bit 1 or 2 stop bits A frame starts with the Start bit followed by one character of Data bits. If enabled, the parity bit is inserted after the Data bits and before the first Stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately, or the communication line can return to the Idle (high) state. The figure below illustrates the possible frame formats. Values inside brackets ([x]) denote optional bits. Figure 28-2. Frame Formats Frame

(IDLE) St 0 1 2 3 4

[5]

[6]

[7]

[8]

[P]

Sp1

[Sp2]

[St/IDLE]

St Start bit. Signal is always low. n, [n]

Data bits. 0 to [4..8]

[P]

Parity bit. Either odd or even. Sp, [Sp]

Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state. 28.6.2 Basic Operation 28.6.2.1 Initialization The following registers are enable-protected, meaning they can only be written when the USART is disabled

(CTRL.ENABLE=0):

Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits. Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 634 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Baud register (BAUD) Any writes to these registers when the USART is enabled or is being enabled (CTRL.ENABLE is one) will be discarded. Writes to these registers while the peripheral is being disabled, will be completed after the disabling is complete. When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the USART is enabled, it must be configured by these steps:

1. 2. 3. 4. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register

(CTRLA.MODE). Select either Asynchronous (0) or Synchronous (1) Communication mode by writing the Communication Mode bit in the CTRLA register (CTRLA.CMODE). Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO). Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register

(CTRLA.TXPO). 7. 5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size. 6. Enable Parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM). Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data transmission. To use parity mode:

a. b. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity. 8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE). 9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate. 10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN). 28.6.2.2 Enabling, Disabling, and Resetting This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing 1 to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details. 28.6.2.3 Clock Generation and Selection For both Synchronous and Asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line. The Synchronous mode is selected by writing a 1 to the Communication Mode bit in the Control A register

(CTRLA.CMODE), the Asynchronous mode is selected by writing 0 to CTRLA.CMODE. The internal clock source is selected by writing 1 to the Operation Mode bit field in the Control A register

(CTRLA.MODE), the external clock source is selected by writing 0 to CTRLA.MODE. The SERCOM baud-rate generator is configured as in the following figure. In Asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used. In Synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. For more details on configuring the baud rate (see Clock Generation Baud-Rate Generator from Related Links). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 635 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Figure 28-3. Clock Generation XCKInternal Clk

(GCLK) Baud Rate Generator 1 0 Base Period

/2

/8 CTRLA.MODE[0]

/1

/2

/16 XCK Related Links 27.6.2.3. Clock Generation Baud-Rate Generator 28.6.2.3.1 Synchronous Clock Operation 1 0 Tx Clk CTRLA.CMODE Rx Clk 0 1 1 0 In Synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling, and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling, and which is used for TxD change:

When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of XCK. When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Figure 28-4. Synchronous Mode XCK Timing Change CTRLA.CPOL=1 CTRLA.CPOL=0 XCK RxD / TxD XCK RxD / TxD Change Sample When the clock is provided through XCK (CTRLA.MODE=0x0), the Shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency. Sample 28.6.2.4 Data Register The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading the DATA register will return the contents of the RxDATA register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 636 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.6.2.5 Data Transmission Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be moved to the Shift register when the Shift register is empty and ready to send a new frame. After the Shift register is loaded with data, the data frame will be transmitted. When the entire data frame including Stop bit(s) has been transmitted and no new data was written to DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the optional interrupt can be generated. The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set. 28.6.2.5.1 Disabling the Transmitter The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN). Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is no data in the Transmit Shift register and TxDATA to transmit. 28.6.2.6 Data Reception The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according to the baud rate or XCK clock, and shifted into the receive Shift register until the first Stop bit of a frame is received. The second Stop bit will be ignored by the receiver. When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents of the Shift register will be moved into the two-level receive buffer. Then, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt will be generated. The received data can be read from the DATA register when the Receive Complete Interrupt flag is set. 28.6.2.6.1 Disabling the Receiver Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost. 28.6.2.6.2 Error Bits The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow

(BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared by writing 1 to it. These bits are also cleared automatically when the receiver is disabled. There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON):

When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared. When CTRLA.IBON=0, the Buffer Overflow condition is attending data through the receive FIFO, which will then set the INTFLAG.ERROR bit. After the received data is read, STATUS.BUFOVF (and INTFLAG.ERROR ) will be set along with INTFLAG.RXC. 28.6.2.6.3 Asynchronous Data Reception The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver. 28.6.2.6.4 Asynchronous Operational Range The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 637 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... get the baud rate desired. In this case, the BAUD register value must be set to give the lowest possible error (see Clock Generation Baud-Rate Generator from Related Links). Recommended maximum receiver baud-rate errors for various character sizes are shown in the following table. Table 28-3. Asynchronous Receiver Error for 16-fold Oversampling D

(Data bits+Parity) RSLOW [%]

RFAST [%] Max. total error [%]

Recommended max. Rx error [%]

5 6 7 8 9 10 94.12 94.92 95.52 96.00 96.39 96.70 107.69

+5.88/-7.69 106.67

+5.08/-6.67 105.88

+4.48/-5.88 105.26

+4.00/-5.26 104.76

+3.61/-4.76 104.35

+3.30/-4.35 2.5 2.0 2.0 2.0 1.5 1.5 The following equations calculate the ratio of the incoming data rate and internal receiver baud rate:

D + 1 S S 1 + D S + SF RSLOW =

, RFAST =

RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate D is the sum of character size and parity size (D = 5 to 10 bits) S is the number of samples per bit (S = 16, 8 or 3) SF is the first sample number used for majority voting (SF = 7, 3 or 2) when CTRLA.SAMPA=0. SM is the middle sample number used for majority voting (SM = 8, 4 or 2) when CTRLA.SAMPA=0. D + 2 S D + 1 S + SM The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure:

Figure 28-5. USART Rx Error Calculation SERCOM Receiver error acceptance from RSLOW and RFAST formulas

Baud Generator offset error depends on BAUD register value Clock source error

Recommended max. Rx Error (%) Error Max (%) Baud Rate Error Min (%) The recommendation values in the table above accommodate errors of the clock source and the baud generator. The following figure gives an example for a baud rate of 3 Mbps:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 638 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Figure 28-6. USART Rx Error Calculation Example SERCOM Receiver error acceptance sampling = x16 data bits = 10 parity = 0 start bit = stop bit = 1 Error Max 3.3%

No baud generator offset error Fbaud(2Mbps) = 32MHz *1(BAUD=0) /16

Error Max 3.3%

Error Max 3.0%

Accepted Receiver Error

Transmitter Error*

Baud Rate 2Mbps Error Min -4.35%

Error Min -4.35%

Error Min -4.05%

security margin

*Transmitter Error depends on the external transmitter used in the application. It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example). Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error. Recommended max. Rx Error +/-1.5%

(example) Related Links 27.6.2.3. Clock Generation Baud-Rate Generator 28.6.3 Additional Features 28.6.3.1 Parity Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). If even parity is selected (CTRLB.PMODE = 0), the Parity bit of an outgoing frame is 1 if the data contains an odd number of bits that are 1, making the total number of 1 even. If odd parity is selected (CTRLB.PMODE = 1), the Parity bit of an outgoing frame is 1 if the data contains an even number of bits that are 1, making the total number of 1 odd. When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the Parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the Status register (STATUS.PERR) is set. 28.6.3.2 Hardware Handshaking The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and CTS pins with the remote device, as shown in the figure below. Figure 28-7. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Hardware handshaking is only available in the following configuration:

USART with internal clock (CTRLA.MODE=1), Asynchronous mode (CTRLA.CMODE=0), and Flow control pinout (CTRLA.TXPO=2). When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 639 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be set immediately and the frame being received will be stored in the Shift register until the receive FIFO is no longer full. Figure 28-8. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN RTS Two-Level Rx Buffer The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting. Figure 28-9. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 28.6.3.3 IrDA Modulation and Demodulation Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration:

IrDA encoding enabled (CTRLB.ENC=1), Asynchronous mode (CTRLA.CMODE=0), and 16x sample rate (CTRLA.SAMPR[0]=0). During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as illustrated in the figure below. Figure 28-10. IrDA Transmit Encoding 1 baud clock TXD IrDA encoded TXD The reception decoder has two main functions. 3/16 baud clock The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start of each zero pulse. The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is transferred to the receiver. Note:Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit. Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20 SE clock cycles. When using BAUD=0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 640 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Figure 28-11. IrDA Receive Decoding Baud clock 0 0.5 1 1.5 2 2.5 IrDA encoded RXD RXD 20 SE clock cycles 28.6.3.4 Break Character Detection and Auto-Baud/LIN Client Break character detection and auto-baud are available in this configuration:

Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05), Asynchronous mode (CTRLA.CMODE = 0), and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a break field has been detected, the Receive Break Interrupt Flag (INTFLAG.RXBRK) is set and the USART expects the sync field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error Interrupt Flag (INTFLAG.ERROR), and the baud rate is unchanged. The auto-baud follows the LIN format. All LIN Frames start with a Break Field followed by a Sync Field. Figure 28-12. LIN Break and Sync Fields Break Field Sync Field 8 bit times After a break field is detected and the Start bit of the sync field is detected, a counter is started. The counter is then incremented for the next 8 bit times of the sync field. At the end of these 8 bit times, the counter is stopped. At this moment, the 13 Most Significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD), and the 3 Least Significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP). When the sync field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated after a synchronization delay. After the break and sync fields are received, multiple characters of data can be received. 28.6.3.5 LIN Host LIN Host is available with the following configuration:

LIN Host format (CTRLA.FORM = 0x02) Asynchronous mode (CTRLA.CMODE = 0) 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1) LIN frames start with a header transmitted by the Host. The header consists of the break, sync, and identifier fields. After the Host transmits the header, the addressed Client will respond with 1-8 bytes of data plus checksum. Figure 28-13. LIN Frame Format Header TxD Break Sync ID RxD Client response 1-8 Data bytes Checksum Using the LIN command field (CTRLB.LINCMD), the complete header can be automatically transmitted, or software can control transmission of the various header components. When CTRLB.LINCMD=0x1, software controls transmission of the LIN header. In this case, software uses the following sequence. CTRLB.LINCMD is written to 0x1. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 641 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... DATA register written to 0x00. This triggers transmission of the break field by hardware. Note that writing the DATA register with any other value will also result in the transmission of the break field by hardware. DATA register written to 0x55. The 0x55 value (sync) is transmitted. DATA register written to the identifier. The identifier is transmitted. When CTRLB.LINCMD=0x2, hardware controls transmission of the LIN header. In this case, software uses the following sequence. CTRLB.LINCMD is written to 0x2. DATA register written to the identifier. This triggers transmission of the complete header by hardware. First the break field is transmitted. Next, the sync field is transmitted, and finally the identifier is transmitted. In LIN Host mode, the length of the break field is programmable using the break length field (CTRLC.BRKLEN). When the LIN header command is used (CTRLB.LINCMD=0x2), the delay between the break and sync fields, in addition to the delay between the sync and ID fields are configurable using the header delay field (CTRLC.HDRDLY). When manual transmission is used (CTRLB.LINCMD=0x1), software controls the delay between break and sync. Figure 28-14. LIN Header Generation Configurable Break Field Length Sync Field Identifier Field LIN Header After header transmission is complete, the Client responds with 1-8 data bytes plus checksum. Configurable delay using CTRLC.HDRDLY 28.6.3.6 RS485 RS485 is available with the following configuration:

USART frame format (CTRLA.FORM = 0x00 or 0x01) RS485 pinout (CTRLA.TXPO=0x3). The RS485 feature enables control of an external line driver as shown in the figure below. While operating in RS485 mode, the transmit enable pin (TE) is driven high when the transmitter is active. Figure 28-15. RS485 Bus Connection USART RXD TXD TE Differential Bus The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows a transfer with one stop bit and CTRLC.GTIME=3. Figure 28-16. Example of TE Drive with Guard Time Start Data Stop GTIME=3 TXD TE The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and TE goes low. 28.6.3.7 ISO 7816 for Smart Card Interfacing The SERCOM USART features an ISO/IEC 7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO 7816 link. Both T = 0 and T = 1 protocols defined by the ISO 7816 specification are supported. ISO 7816 is available with the following configuration:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 642 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... ISO 7816 format (CTRLA.FORM = 0x07) Inverse transmission and reception (CTRLA.RXINV=1 and CTRLA.TXINV = 1) Single bidirectional data line (CTRLA.TXPO and CTRLA.RXPO configured to use the same data pin) Even parity (CTRLB.PMODE = 0) 8-bit character size (CTRLB.CHSIZE = 0) T=0 (CTRLA.CMODE=1) or T=1 (CTRLA.CMODE = 0) ISO 7816 is a half duplex communication on a single bidirectional line. The USART connects to a smart card as shown below. The output is only driven when the USART is transmitting. The USART is considered as the host of the communication as it generates the clock. Figure 28-17. Connection of a Smart Card to the SERCOM USART SERCOM USART SCK TXD/RXD CLK I/O Smart Card ISO 7816 characters are specified as 8 bits with even parity. The USART must be configured accordingly. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO 7816 mode may lead to unpredictable results. The ISO 7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value (CTRLA.RXINV = 1 and CTRLA.TXINV = 1). Protocol T=0 In T = 0 protocol, a character is made up of:

one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transfer is synchronous (CTRLA.CMODE = 1). The transmitter shifts out the bits and does not drive the I/O line during the guard time. Additional guard time can be added by programming the Guard Time (CTRLC.GTIME). If no parity error is detected, the I/O line remains 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in the following figure. Figure 28-18. T=0 Protocol without Parity Error SCK I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 P Guard Time1 Guard Time2 Next Start Bit If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in the next figure. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time, which lasts 1 bit time. Figure 28-19. T=0 Protocol with Parity Error SCK I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 P Error Guard Time1 Guard Time2 Start Bit D0 D1 Repetition When the USART is the receiver and it detects a parity error, the parity error bit in the Status Register

(STATUS.PERR) is set and the character is not written to the receive FIFO. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 643 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Receive Error Counter The receiver also records the total number of errors (receiver parity errors and NACKs from the remote transmitter) up to a maximum of 255. This can be read in the Receive Error Count (RXERRCNT) register. RXERRCNT is automatically cleared on read. Receive NACK Inhibit The receiver can also be configured to inhibit error generation. This can be achieved by setting the Inhibit Not Acknowledge (CTRLC.INACK) bit. If CTRLC.INACK is 1, no error signal is driven on the I/O line even if a parity error is detected. Moreover, if CTRLC.INACK is set, the erroneous received character is stored in the receive FIFO, and the STATUS.PERR bit is set. Inhibit not acknowledge (CTRLC.INACK) takes priority over disable successive receive NACK (CTRLC.DSNACK). Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next character. Repetition is enabled by writing the Maximum Iterations register (CTRLC.MAXITER) to a non-zero value. The USART repeats the character the number of times specified in CTRLC.MAXITER. When the USART repetition number reaches the programmed value in CTRLC.MAXITER, the STATUS.ITER bit is set and the internal iteration counter is reset. If the repetition of the character is acknowledged by the receiver before the maximum iteration is reached, the repetitions are stopped and the iteration counter is cleared. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the Disable Successive NACK bit (CTRLC.DSNACK). The maximum number of NACKs transmitted is programmed in the CTRLC.MAXITER field. As soon as the maximum is reached, the character is considered as correct, an acknowledge is sent on the line, the STATUS.ITER bit is set and the internal iteration counter is reset. Protocol T=1 When operating in ISO7816 protocol T=1, the transmission is asynchronous (CTRL1.CMODE=0) with one or two stop bits. After the stop bits are sent, the transmitter does not drive the I/O line. Parity is generated when transmitting and checked when receiving. Parity error detection sets the STATUS.PERR bit, and the erroneous character is written to the receive FIFO. When using T=1 protocol, the receiver does not signal errors on the I/O line and the transmitter does not retransmit. 28.6.3.8 Collision Detection When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1). Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 28-20. Collision Checking 8-bit character, single stop bit TXD RXD The next figure shows the conditions for a collision detection. In this case, the Start bit and the first Data bit are received with the same value as transmitted. The second received Data bit is found to be different than the transmitted bit at the detection point, which indicates a collision. Collision checked 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 644 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Figure 28-21. Collision Detected Collision checked and ok Tri-state TXD RXD TXEN When a collision is detected, the USART follows this sequence:

Collision detected Abort the current transfer. Flush the transmit buffer. 1. 2. 3. Disable transmitter (CTRLB.TXEN=0) This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. After disabling, the TxD pin will be tri-stated. 4. 5. Set the Collision Detected bit (STATUS.COLL) along with the Error Interrupt Flag (INTFLAG.ERROR). Set the Transmit Complete Interrupt Flag (INTFLAG.TXC), since the transmit buffer no longer contains data. After a collision, software must manually enable the transmitter again before continuing, after assuring that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set. 28.6.3.9 Loop-Back Mode For Loop-Back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally. 28.6.3.10 Start-of-Frame Detection The USART start-of-frame detector can wake up the CPU when it detects a Start bit. In Standby Sleep mode, the internal fast start-up oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8 MHz Internal Oscillator is powered up and the USART clock is enabled. After start-up, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the fast start-up internal oscillator start-up time. See Electrical Characteristics from Related Links for details. The start-up time of this oscillator varies with supply voltage and temperature. The USART start-of-frame detection works both in Asynchronous and Synchronous modes. It is enabled by writing 1 to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8 MHz internal oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the receive complete interrupt is generated. Related Links 38. Electrical Characteristics 28.6.3.11 Sample Adjustment In Asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling. 28.6.3.12 32-bit Extension For better system bus utilization, 32-bit data receive and transmit can be enabled separately by writing to the Data 32-bit bit field in the Control C register (CTRLC.DATA32B). When enabled, writes and/or reads to the DATA register are 32 bit in size. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 645 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... If frames are not multiples of 4 Bytes, the length counter (LENGTH.LEN) and length enable (LENGTH.LENEN) must be configured before data transfer begins, LENGTH.LEN must be enabled only when CTRLC.DATA32B is enabled. The figure below shows the order of transmit and receive when using 32-bit extension. Bytes are transmitted or received, and stored in order from 0 to 3. Only 8-bit and smaller character sizes are supported. If the character size is less than 8 bits, characters will still be 8-bit aligned within the 32-bit APB write or read. The unused bits within each byte will be zero for received data and unused for transmit data. Figure 28-22. 32-bit Extension Ordering APB Write/Read BYTE3 BYTE2 BYTE1 BYTE0 Bit Position 31 0 A receive transaction using 32-bit extension is in the next figure. The Receive Complete flag (INTFLAG.RXC) is raised every four received Bytes. For transmit transactions, the Data Register Empty flag (INTFLAG.DRE) is raised instead of INTFLAG.RXC. Figure 28-23. 32-bit Extension Receive Operation RXC interrupt Byte 0 Byte 1 Byte 2 Byte 3 S W Data Length Configuration When the Data Length Enable bit field in the Length register (LENGTH.LENEN) is written to 0x1 or 0x2, the Data Length bit (LENGTH.LEN) determines the number of characters to be transmitted or received from 1 to 255. Note:There is one internal length counter that can be used for either transmit (LENGTH.LENEN=0x1) or receive

(LENGTH.LENEN=0x2), but not for both simultaneously. The LENGTH register must be written before the frame begins. If LENGTH.LEN is not a multiple of 4 Bytes, the final INTFLAG.RXC/DRE interrupt will be raised when the last byte is received/sent. The internal length counter is reset when LENGTH.LEN is reached or when LENGTH.LENEN is written to 0x0. Writing the LENGTH register while a frame is in progress will produce unpredictable results. If LENGTH.LENEN is not set and a frame is not a multiple of 4 Bytes, the remainder may be lost. Attempting to use the length counter for transmit and receive at the same time will produce unpredictable results. 28.6.4 DMA, Interrupts and Events Table 28-4. Module Request for SERCOM USART Condition Data Register Empty (DRE) Receive Complete (RXC) Transmit Complete (TXC) Receive Start (RXS) Clear to Send Input Change (CTSIC) Receive Break (RXBRK) Error (ERROR) Request DMA Yes

(request cleared when data is written) Yes

(request cleared when data is read) NA NA NA NA NA Interrupt Event NA Yes Yes Yes Yes Yes Yes Yes 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 646 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Table 28-5. Module Request for SERCOM USART Condition Standard (DRE): Data Register Empty FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty Request DMA Yes

(request cleared when data is written) Interrupt Event Yes NA Standard (RXC): Receive Complete FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed. Yes

(request cleared when data is read) Yes Standard (TXC): Transmit Complete FIFO (TXC): Transmit Complete and TX FIFO is empty Receive Start (RXS) Clear to Send Input Change (CTSIC) Receive Break (RXBRK) Error (ERROR) NA NA NA NA NA Yes Yes Yes Yes Yes 28.6.4.1 DMA Operation The USART generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read. Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written. Data received (RX): The request is set when data is available in the receive FIFO or if at least RXTRHOLD data are available in the RX FIFO when FIFO operation is enabled. The request is cleared when DATA is read. Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty or if at least TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The request is cleared when DATA is written. 28.6.4.2 Interrupts The USART has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from any Sleep mode:

Data Register Empty (DRE) Receive Complete (RXC) Transmit Complete (TXC) Receive Start (RXS) Clear to Send Input Change (CTSIC) Received Break (RXBRK) Error (ERROR) Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing

'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the USART is reset. For details on clearing Interrupt flags, see INTFLAG from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 647 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 28.8.8. INTFLAG 28.6.4.3 Events Not applicable. 28.6.5 Sleep Mode Operation The behavior in Sleep mode is depending on the clock source and the Run In Standby bit in the Control A register

(CTRLA.RUNSTDBY):

Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all Sleep modes. Any interrupt can wake-up the device. External clocking, CTRLA.RUNSTDBY=1: The Receive Complete interrupt(s) can wake-up the device. Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer was completed. The Receive Complete interrupt(s) can wake-up the device. External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing transfer was completed. All reception will be dropped. 28.6.6 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST) Enable bit in the CTRLA register (CTRLA.ENABLE) Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Transmitter Enable bit in the Control B register (CTRLB.TXEN) Note:CTRLB.RXEN is write-synchronized somewhat differently. See also 28.8.2. CTRLB for details. Required write synchronization is denoted by the "Write-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 648 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.7 Register Summary See SERCOM0/SERCOM1/SERCOM2 module in the Product Memory Mapping Overview from Related Links for base address based on the SERCOM instant used. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x04 CTRLB 0x08 CTRLC 0x0C 0x0E 0x0F

... 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A BAUD RXPL Reserved INTENCLR Reserved INTENSET Reserved INTFLAG Reserved STATUS 0x1C SYNCBUSY 0x20 0x21 0x22 0x24

... 0x27 RXERRCNT Reserved LENGTH Reserved 0x28 DATA 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 23:16 31:24 7:0 7:0 15:8 7:0 15:8 23:16 31:24 0x2C

... 0x2F 0x30 0x31

... 0x33 0x34 Reserved DBGCTRL 7:0 Reserved FIFOSPACE 0x36 FIFOPTR RUNSTDBY SAMPR[2:0]

SAMPA[1:0]

RXPO[1:0]

DORD SBMODE CPOL CMODE MODE[2:0]

ENABLE SWRST RXINV TXINV IBON TXPO[1:0]

FORM[3:0]

CHSIZE[2:0]

PMODE ENC SFDE RXEN COLDEN TXEN LINCMD[1:0]

GTIME[2:0]

MAXITER[2:0]

HDRDLY[1:0]

BRKLEN[1:0]

DSNACK INACK DATA32B[1:0]

BAUD[7:0]

BAUD[15:8]

RXPL[7:0]

ERROR ERROR ERROR RXBRK CTSIC RXS RXBRK CTSIC RXS RXBRK CTSIC RXS RXC RXC RXC TXC TXC TXC DRE DRE DRE ITER TXE COLL ISF CTS BUFOVF FERR PERR LENGTH RXERRCNT CTRLB ENABLE SWRST RXERRCNT[7:0]

LEN[7:0]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

LENEN[1:0]

DBGSTOP 7:0 15:8 7:0 15:8 TXSPACE[4:0]

RXSPACE[4:0]

CPUWRPTR[3:0]

CPURDPTR[3:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 649 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Related Links 7. Product Memory Mapping Overview 28.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 650 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLA 0x00 0x00000000 Bit 31 Access Reset 30 DORD R/W 0 29 CPOL R/W 0 28 CMODE R/W 0 Bit 23 22 SAMPA[1:0]

Access Reset R/W 0 R/W 0 Bit 15 Access Reset R/W 0 14 SAMPR[2:0]

R/W 0 Bit 7 6 RUNSTDBY Access Reset R/W 0 Bit 30 DORDData Order RXPO[1:0]

21 R/W 0 13 R/W 0 5 20 R/W 0 12 4 R/W 0 27 R/W 0 19 11 3 MODE[2:0]

R/W 0 FORM[3:0]

26 R/W 0 18 25 R/W 0 17 R/W 0 TXPO[1:0]

10 RXINV R/W 0 2 R/W 0 9 TXINV R/W 0 1 ENABLE R/W 0 24 R/W 0 16 R/W 0 8 IBON R/W 0 0 SWRST R/W 0 This bit selects the data order when a character is shifted out from the Data register. This bit is not synchronized. Value 0 1 Description MSB is transmitted first. LSB is transmitted first. Bit 29 CPOLClock Polarity This bit selects the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. CPOL 0x0 0x1 TxD Change Rising XCK edge Falling XCK edge RxD Sample Falling XCK edge Rising XCK edge Bit 28 CMODECommunication Mode This bit selects asynchronous or synchronous communication. This bit is not synchronized. Value 0 1 Description Asynchronous communication. Synchronous communication. Bits 27:24 FORM[3:0]Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0]

Description 0x0 0x1 USART frame USART frame with parity 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 651 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... ..........continued FORM[3:0]

Description 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF LIN Host - Break and sync generation. See LIN Command (CTRLB.LINCMD). Reserved Auto-baud (LIN Client) - break detection and auto-baud. Auto-baud - break detection and auto-baud with parity Reserved ISO 7816 Reserved Bits 23:22 SAMPA[1:0]Sample Adjustment These bits define the sample adjustment. These bits are not synchronized. SAMPA[1:0]

16x Over-sampling (CTRLA.SAMPR=0 or 1) 8x Over-sampling (CTRLA.SAMPR=2 or 3) 0x0 0x1 0x2 0x3 7-8-9 9-10-11 11-12-13 13-14-15 3-4-5 4-5-6 5-6-7 6-7-8 Bits 21:20 RXPO[1:0]Receive Data Pinout These bits define the receive data (RxD) pin configuration. These bits are not synchronized. RXPO[1:0]

0x0 0x1 0x2 0x3 Name PAD[0]

PAD[1]

PAD[2]

PAD[3]

Description SERCOM PAD[0] is used for data reception SERCOM PAD[1] is used for data reception SERCOM PAD[2] is used for data reception SERCOM PAD[3] is used for data reception Bits 17:16 TXPO[1:0]Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. This bit is not synchronized. TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS/TE SERCOM PAD[1]

NA 0x0 0x1 0x2 0x3 SERCOM PAD[0]

Reserved SERCOM PAD[0]

SERCOM_PAD[0]

NA SERCOM_PAD[1]

SERCOM PAD[2]

SERCOM_PAD[2]

SERCOM PAD[3]

NA CTS NA Bits 15:13 SAMPR[2:0]Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0]

Description 0x0 0x1 0x2 0x3 0x4 0x5-0x7 16x over-sampling using arithmetic baud rate generation. 16x over-sampling using fractional baud rate generation. 8x over-sampling using arithmetic baud rate generation. 8x over-sampling using fractional baud rate generation. 3x over-sampling using arithmetic baud rate generation. Reserved Bit 10 RXINVReceive Data Invert This bit controls whether the receive data (RxD) is inverted or not. Note:Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data. This bit is not synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 652 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Value 0 1 Description RxD is not inverted. RxD is inverted. Bit 9 TXINVTransmit Data Invert This bit controls whether the transmit data (TxD) is inverted or not. Note:Start, parity and stop bit(s) are unchanged. When enabled, parity is calculated on the inverted data. This bit is not synchronized. Value 0 1 Description TxD is not inverted. TxD is inverted. Bit 8 IBONImmediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. This bit is not synchronized. Value 0 1 Description STATUS.BUFOVF is asserted when it occurs in the data stream. STATUS.BUFOVF is asserted immediately upon buffer overflow. Bit 7 RUNSTDBYRun In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY External Clock Internal Clock 0x0 0x1 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Wake on Receive Complete interrupt. Generic clock is disabled when ongoing transfer is finished. The device will not wake up on Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain. Generic clock is enabled in all sleep modes. Any interrupt can wake up the device. Bits 4:2 MODE[2:0]Operating Mode These bits select the USART serial communication interface of the SERCOM. These bits are not synchronized. Value 0x0 0x1 Description USART with external clock USART with internal clock Bit 1 ENABLEEnable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled or being disabled. The peripheral is enabled or being enabled. Bit 0 SWRSTSoftware Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 653 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 654 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.2 Control B Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLB 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 Access Reset Bit 15 14 Access Reset Bit 7 Access Reset 6 SBMODE R/W 0 Bits 25:24 LINCMD[1:0]LIN Command 12 11 13 PMODE R/W 0 5 4 3 10 ENC R/W 0 2 R/W 0 LINCMD[1:0]

R/W 0 17 RXEN R/W 0 9 SFDE R/W 0 R/W 0 16 TXEN R/W 0 8 COLDEN R/W 0 1 CHSIZE[2:0]

R/W 0 0 R/W 0 These bits define the LIN header transmission control. This field is only valid in LIN Host mode (CTRLA.FORM= LIN Host). These are strobe bits and will always read back as zero. These bits are not enable-protected. Value 0x0 0x1 0x2 0x3 Description Normal USART transmission. Break field is transmitted when DATA is written. Break, sync and identifier are automatically transmitted when DATA is written with the identifier. Reserved Bit 17 RXENReceiver Enable Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register. Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'. Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value 0 1 Description The receiver is disabled or being enabled. The receiver is enabled or will be enabled when the USART is enabled. Bit 16 TXENTransmitter Enable Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 655 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'. Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the transmitter is enabled, and CTRLB.TXEN will read back as '1'. This bit is not enable-protected. Value 0 1 Description The transmitter is disabled or being enabled. The transmitter is enabled or will be enabled when the USART is enabled. Bit 13 PMODEParity Mode This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set. This bit is not synchronized. Value 0 1 Description Even parity. Odd parity. Bit 10 ENCEncoding Format This bit selects the data encoding format. This bit is not synchronized. Value 0 1 Description Data is not encoded. Data is IrDA encoded. Bit 9 SFDEStart of Frame Detection Enable This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line. This bit is not synchronized. SFDE INTENSET.RXS INTENSET.RXC Description 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 Start-of-frame detection disabled. Reserved Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 COLDENCollision Detection Enable This bit enables collision detection. This bit is not synchronized. Value 0 1 Description Collision detection is not enabled. Collision detection is enabled. Bit 6 SBMODEStop Bit Mode This bit selects the number of stop bits transmitted. This bit is not synchronized. Value 0 1 Description One stop bit. Two stop bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 656 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Bits 2:0 CHSIZE[2:0]Character Size These bits select the number of bits in a character. These bits are not synchronized. CHSIZE[2:0]

0x0 0x1 0x2-0x4 0x5 0x6 0x7 Description 8 bits 9 bits Reserved 5 bits 6 bits 7 bits 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 657 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.3 Control C Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRLC 0x08 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset Bit 15 Access Reset 22 R/W 0 14 21 MAXITER[2:0]

R/W 0 13 20 R/W 0 12 Bit 7 6 5 4 Access Reset Bits 25:24 DATA32B[1:0]Data 32 Bit 19 18 DATA32B[1:0]

R/W 0 17 DSNACK R/W 0 R/W 0 16 INACK R/W 0 11 10 HDRDLY[1:0]

9 8 BRKLEN[1:0]

R/W 0 3 R/W 0 2 R/W 0 R/W 0 1 GTIME[2:0]

R/W 0 R/W 0 0 R/W 0 These bits configure 32-bit Extension for read and write transactions to the DATA register. When disabled, access is according to CTRLB.CHSIZE. Value 0x0 0x1 Description DATA reads (for received data) and writes (for transmit data) according to CTRLB.CHSIZE. DATA reads according to CTRLB.CHSIZE. 0x2 0x3 DATA writes using 32-bit Extension. DATA reads using 32-bit Extension. DATA writes according to CTRLB.CHSIZE. DATA reads and writes using 32-bit Extension. Bits 22:20 MAXITER[2:0]Maximum Iterations These bits define the maximum number of retransmit iterations. These bits also define the successive NACKs sent to the remote transmitter when CTRLC.DSNACK is set. This field is only valid when using ISO7816 T=0 mode (CTRLA.MODE=0x7 and CTRLA.CMODE=0). Bit 17 DSNACKDisable Successive Not Acknowledge This bit controls how many times NACK will be sent on parity error reception. This bit is only valid in ISO7816 T=0 mode and when CTRLC.INACK=0. Value 0 1 Description NACK is sent on the ISO line for every parity error received. Successive parity errors are counted up to the value specified in CTRLC.MAXITER. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. Bit 16 INACKInhibit Not Acknowledge This bit controls whether a NACK is transmitted when a parity error is received. This bit is only valid in ISO7816 T=0 mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 658 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Value 0 1 Description NACK is transmitted when a parity error is received. NACK is not transmitted when a parity error is received. Bits 11:10 HDRDLY[1:0]LIN Host Header Delay These bits define the delay between break and sync transmission in addition to the delay between the sync and identifier (ID) fields when in LIN Host mode (CTRLA.FORM=0x2). This field is only valid when using the LIN header command (CTRLB.LINCMD=0x2). Value 0x0 Description Delay between break and sync transmission is 1 bit time. 0x1 0x2 0x3 Delay between sync and ID transmission is 1 bit time. Delay between break and sync transmission is 4 bit time. Delay between sync and ID transmission is 4 bit time. Delay between break and sync transmission is 8 bit time. Delay between sync and ID transmission is 4 bit time. Delay between break and sync transmission is 14 bit time. Delay between sync and ID transmission is 4 bit time. Bits 9:8 BRKLEN[1:0]LIN Host Break Length These bits define the length of the break field transmitted when in LIN Host mode (CTRLA.FORM=0x2). Value 0x0 0x1 0x2 0x3 Description Break field transmission is 13 bit times Break field transmission is 17 bit times Break field transmission is 21 bit times Break field transmission is 26 bit times Bits 2:0 GTIME[2:0]Guard Time These bits define the guard time when using RS485 mode (CTRLA.FORM=0x0 or CTRLA.FORM=0x1, and CTRLA.TXPO=0x3) or ISO7816 mode (CTRLA.FORM=0x7). For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin

(TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted. For ISO7816 T=0 mode, the guard time is programmable from 2-9 bit times and defines the guard time between each transmitted byte. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 659 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.4 Baud Name:

Offset:

Reset:

Property: Enable-Protected, PAC Write-Protection BAUD 0x0C 0x0000 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 BAUD[15:8]

BAUD[7:0]

12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 BAUD[15:0]Baud Value Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0):

These bits control the clock generation, as described in the SERCOM Baud Rate section. If Fractional Baud Rate Generation (CTRLA.SAMPR=1 or =3) bit positions 15 to 13 are replaced by FP[2:0]

Fractional Part:

Bits 15:13 - FP[2:0]: Fractional Part These bits control the clock generation, as described in the SERCOM Clock Generation Baud-Rate Generator section. Bits 12:0 - BAUD[12:0]: Baud Value These bits control the clock generation, as described in the SERCOM Clock Generation Baud-Rate Generator section. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 660 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.5 Receive Pulse Length Register Name:

Offset:

Reset:

Property: Enable-Protected, PAC Write-Protection RXPL 0x0E 0x00 Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 RXPL[7:0]

3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bits 7:0 RXPL[7:0]Receive Pulse Length When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period

. PULSE RXPL + 1 SEper SEper 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 661 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.6 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x14 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit Access Reset 7 ERROR R/W 0 6 5 RXBRK R/W 0 4 CTSIC R/W 0 3 RXS R/W 0 2 RXC R/W 0 1 TXC R/W 0 0 DRE R/W 0 Bit 7 ERRORError Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 5 RXBRKReceive Break Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt. Value 0 1 Description Receive Break interrupt is disabled. Receive Break interrupt is enabled. Bit 4 CTSICClear to Send Input Change Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt. Value 0 1 Description Clear To Send Input Change interrupt is disabled. Clear To Send Input Change interrupt is enabled. Bit 3 RXSReceive Start Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. Value 0 1 Description Receive Start interrupt is disabled. Receive Start interrupt is enabled. Bit 2 RXCReceive Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 TXCTransmit Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Transmit Complete interrupt. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 662 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Value 0 1 Description Transmit Complete interrupt is disabled. Transmit Complete interrupt is enabled. Bit 0 DREData Register Empty Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 663 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.7 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x16 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit Access Reset 7 ERROR R/W 0 6 5 RXBRK R/W 0 4 CTSIC R/W 0 3 RXS R/W 0 2 RXC R/W 0 1 TXC R/W 0 0 DRE R/W 0 Bit 7 ERRORError Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 5 RXBRKReceive Break Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt. Value 0 1 Description Receive Break interrupt is disabled. Receive Break interrupt is enabled. Bit 4 CTSICClear to Send Input Change Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt. Value 0 1 Description Clear To Send Input Change interrupt is disabled. Clear To Send Input Change interrupt is enabled. Bit 3 RXSReceive Start Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. Value 0 1 Description Receive Start interrupt is disabled. Receive Start interrupt is enabled. Bit 2 RXCReceive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 TXCTransmit Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 664 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Value 0 1 Description Transmit Complete interrupt is disabled. Transmit Complete interrupt is enabled. Bit 0 DREData Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 665 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.8 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x18 0x00

Bit Access Reset 7 ERROR R/W 0 Bit 7 ERRORError 6 5 RXBRK R/W 0 4 CTSIC R/W 0 3 RXS R/W 0 2 RXC R 0 1 TXC R/W 0 0 DRE R 0 This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 5 RXBRKReceive Break This flag is cleared by writing '1' to it. This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 4 CTSICClear to Send Input Change This flag is cleared by writing a '1' to it. This flag is set when a change is detected on the CTS pin. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 3 RXSReceive Start This flag is cleared by writing '1' to it. This flag is set when a Start condition is detected on the RxD line and start-of-frame detection is enabled

(CTRLB.SFDE is '1'). Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Start Interrupt flag. Bit 2 RXCReceive Complete This flag is cleared by reading the Data register (DATA) or by disabling the receiver. This flag is set when there are unread data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 1 TXCTransmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. This flag is set when the entire frame in the Transmit Shift register has been shifted out and there are no new data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 DREData Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 666 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.9 Status Name:

Offset:

Reset:

Property:

STATUS 0x1A 0x0000

Bit 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset 7 ITER R/W 0 6 TXE R/W 0 5 COLL R/W 0 4 ISF R/W 0 3 CTS R 0 2 BUFOVF R/W 0 1 FERR R/W 0 0 PERR R/W 0 Bit 7 ITERMaximum Number of Repetitions Reached This bit is set when the maximum number of NACK repetitions or retransmissions is met in ISO7816 T=0 mode. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 6 TXETransmitter Empty When CTRLA.FORM is set to LIN Host mode, this bit is set when any ongoing transmission is complete and TxDATA is empty. When CTRLA.FORM is not set to LIN Host mode, this bit will always read back as zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 5 COLLCollision Detected This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 4 ISFInconsistent Sync Field This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 3 CTSClear to Send This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO). Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. Bit 2 BUFOVFBuffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 667 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Bit 1 FERRFrame Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if the received character had a frame error, i.e., when the first stop bit is zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. Bit 0 PERRParity Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5, or 0x7) and a parity error is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 668 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.10 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x1C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 Access Reset 4 LENGTH R 0 3 RXERRCNT R 0 2 CTRLB R 0 1 ENABLE R 0 0 SWRST R 0 Bit 4 LENGTHLENGTH Synchronization Busy Writing to the LENGTH register requires synchronization. When writing to LENGTH, SYNCBUSY.LENGTH will be set until synchronization is complete. If the LENGTH register is written to while SYNCBUSY.LENGTH is asserted, an APB error is generated. Value 0 1 Description LENGTH synchronization is not busy. LENGTH synchronization is busy. Bit 3 RXERRCNTReceive Error Count Synchronization Busy The RXERRCNT register is automatically synchronized to the APB domain upon error. When returning from sleep, this bit will be raised until the new value is available to be read. Value 0 1 Description RXERRCNT synchronization is not busy. RXERRCNT synchronization is busy. Bit 2 CTRLBCTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. Value 0 1 Description CTRLB synchronization is not busy. CTRLB synchronization is busy. Bit 1 ENABLESERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When writing to CTRLA.ENABLE, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value 0 1 Description Enable synchronization is not busy. Enable synchronization is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 669 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... Bit 0 SWRSTSoftware Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When writing to CTRLA.SWRST, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 670 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.11 Receive Error Count RXERRCNT Name:

0x20 Offset:

Reset:

0x00 Property: Read-Synchronized Bit Access Reset 7 R 0 6 R 0 5 R 0 4 3 RXERRCNT[7:0]

R R 0 0 2 R 0 1 R 0 0 R 0 Bits 7:0 RXERRCNT[7:0]Receive Error Count This register records the total number of parity errors and NACK errors combined in ISO7816 mode

(CTRLA.FORM=0x7). This register is automatically cleared on read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 671 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.12 Length Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized LENGTH 0x22 0x00 Bit 15 14 13 12 11 10 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 LEN[7:0]

3 R/W 0 2 R/W 0 LENEN[1:0]

9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 9:8 LENEN[1:0]Data Length Enable In 32-bit Extension mode, this bit field configures the length counter either for transmit or receive transactions. Value 0x0 0x1 0x2 0x3 Description Length counter disabled Length counter enabled for transmit Length counter enabled for receive Reserved Bits 7:0 LEN[7:0]Data Length In 32-bit Extension mode, this bit field configures the data length after which the flags INTFLAG.RXC or INTFLAG.DRE are raised. Description Value Reserved if LENEN=0x1 or LENEN=0x2 0x00 Data Length 0x01-0xF F 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 672 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.13 Data Name:

Offset:

Reset:

Property:

DATA 0x28 0x0000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DATA[31:0]Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order to get any corresponding error. Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Reads and writes are 32-bit or CTLB.CHSIZE based on the CTRLC.DATA32B setting. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 673 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.14 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x30 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGSTOPDebug Stop Mode DBGSTOP R/W 0 This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 674 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.15 FIFO Space Name:

Offset:

Reset:

Property:

FIFOSPACE 0x34 0x0000

This register allows the user to identify the number of bytes present in each TX and RX FIFO. Bit 15 14 13 Access Reset Bit 7 6 5 Access Reset 12 R 0 4 R 0 11 R 0 3 R 0 10 RXSPACE[4:0]

R 0 2 TXSPACE[4:0]

R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 12:8 RXSPACE[4:0]RX FIFO Filled Space These bits return the number filled locations in the RX FIFO (bytes or words, depending on CTRLC.DATA32B setting). Bits 4:0 TXSPACE[4:0]TX FIFO Empty Space These bits return the number of available locations in the TX FIFO (bytes or words, depending on CTRLC.DATA32B setting). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 675 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Synchronous and Asynchronous Receiver ... 28.8.16 FIFO CPU Pointers Name:

Offset:

Reset:

Property:

FIFOPTR 0x36 0x0000

This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 Access Reset Bit 7 6 5 4 Access Reset 11 R/W 0 3 R/W 0 9 10 CPURDPTR[3:0]

R/W 0 R/W 0 1 2 CPUWRPTR[3:0]

R/W 0 R/W 0 8 R/W 0 0 R/W 0 Bits 11:8 CPURDPTR[3:0]RX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. Reading DATA register, will return RXFIFO[CPURDPTR] location value. Bits 3:0 CPUWRPTR[3:0]TX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. When writting to DATA register, the DATA will be written to TXFIFO[CPUWRPTR] location. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 676 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29. SERCOM Serial Peripheral Interface (SERCOM SPI) 29.1 Overview The Serial Peripheral Interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 29.3. Block Diagram. Each side, host and client, depicts a separate SPI containing a Shift register, a transmit buffer and a two-level receive buffer. In addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address match logic. Labels in capital letters are synchronous to PB1_CLK and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock. 29.2 Features SERCOM SPI includes the following features:

Full-duplex, four-wire interface (MISO, MOSI, SCK, SS) One-level transmit buffer, two-level receive buffer Supports all four SPI modes of operation Single data direction operation allows alternate function on MISO or MOSI pin Selectable LSB- or MSB-first data transfer Can be used with DMA 32-bit Extension for better system bus utilization Up to 16-bytes internal FIFO Host Operation:

Serial clock speed up to half the system clock 8-bit clock generator Hardware controlled SS Optional inter-character spacing Client Operation:

Serial clock speed up to half the system clock Optional 8-bit address match operation Operation in all sleep modes Wake on SS transition Note:SERCOM2 does not have SPI functionality. 29.3 Block Diagram Figure 29-1. Full-Duplex SPI Host Client Interconnection Host Client BAUD Tx DATA Tx DATA ADDR/ADDRMASK baud rate generator shift register SCK SS MISO MOSI shift register rx buffer Rx DATA rx buffer Rx DATA

Address Match 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 677 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.4 Signal Description Table 29-1. SERCOM SPI Signals Signal Name PAD[3:0]

Type Digital I/O Description General SERCOM pins One signal can be mapped to one of several pins. For more details on pin mapping, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 29.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described in the following sections. 29.5.1 I/O Lines In order to use the SERCOMs I/O lines, the I/O pins must be configured using the System Configuration registers

(See System Configuration and Register Locking (CFG) from Related Links) (SCOM_HSEN[1:0] of CFGCON1/

DEVCFG1 register) for direct or PPS configuration. If SERCOM pins are selected through PPS, the PPS registers has to be configured (See I/O Ports and Peripheral Pin Select (PPS) from Related Links). If SCOMx_HSEN =1, SERCOM uses dedicated pins. If SCOMx_HSEN = 0, SERCOM uses PPS path, and I/O pins are multiplexed to pins groups defined in PPS section. When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the following table. If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the SPI Select line (SS) is hardware controlled when the Host SPI Select Enable bit in the Control B register

(CTRLB.MSSEN) is 1. Table 29-2. SPI Pin Configuration Pin MOSI MISO SCK SS Host SPI Output Input Output Output (CTRLB.MSSEN = 1) Client SPI Input Output Input Input The configuration of the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 18. System Configuration and Register Locking (CFG) 29.5.2 Power Management This peripheral can continue to operate in any Sleep mode where its source clock is running. The interrupts can wake-up the device from Sleep modes. 29.5.3 Clocks A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Clock and Reset Unit (CRU) and Configuration (CFG.CFGPCLKGEN1) registers before using the SPI. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 678 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... This generic clock is asynchronous to the bus clock (PB1_CLK). Therefore, writes to certain registers will require synchronization to the clock domains. 29.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). To use DMA requests with this peripheral, the DMAC must be configured first (see Direct Memory Access Controller (DMAC) from Related Links). Related Links 22. Direct Memory Access Controller (DMAC) 29.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 29.5.6 Events Not applicable. 29.5.7 Debug Operation When the CPU is halted in the Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging. For more details, see Debug Control (DBGCTRL) register. 29.5.8 Register Access Protection Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC write protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. 29.5.9 Analog Connections Not applicable. 29.6 Functional Description 29.6.1 Principle of Operation The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device and peripheral devices. The SPI can operate as host or client. As host, the SPI initiates and controls all data transactions. The SPI is single buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character. The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more characters. The character size is configurable, and can be either 8 or 9 bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 679 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Figure 29-2. SPI Transaction Format Character Transaction MOSI/MISO Character 0 Character 1 Character 2 SS The SPI host must pull the SPI Select line (SS) of the desired client low to initiate a transaction if multiple clients are connected to the bus. The SPI Select line can be wired low if there is only one SPI client on the bus. The host and client prepare data to send via their respective Shift registers, and the host generates the serial clock on the SCK line. Data is always shifted from host to client on the Host Output Client Input line (MOSI); data is shifted from client to host on the Host Input Client Output line (MISO). Each time character is shifted out from the host, a character will be shifted out from the client simultaneously. To signal the end of a transaction, the host will pull the SS line high. 29.6.2 Basic Operation 29.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled

(CTRL.ENABLE = 0):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN) Baud register (BAUD) Address register (ADDR) When the SPI is enabled or is being enabled (CTRLA.ENABLE = 1), any writing to these registers will be discarded. When the SPI is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the Enable-Protection property in the register description. Initialize the SPI by following these steps:

1. 2. Select SPI mode in host/client operation in the Operating Mode bit group in the CTRLA register

(CTRLA.MODE = 0x2 or 0x3). Select Transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL and CTRLA.CPHA) if desired. Select the Frame Format value in the CTRLA register (CTRLA.FORM). 3. 4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver. 5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the transmitter. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE). 6. 7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction. 8. If the SPI is used in Host mode:

a. b. Select the desired baud rate by writing to the Baud register (BAUD). If Hardware SS control is required, write 1 to the Host SPI Select Enable bit in CTRLB register

(CTRLB.MSSEN). 9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN = 1). 29.6.2.2 Enabling, Disabling, and Resetting This peripheral is enabled by writing 1 to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing 0 to it. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 680 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Writing 1 to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. For more details, see CTRLA register description. 29.6.2.3 Clock Generation In the SPI host operation (CTRLA.MODE = 0x3), the serial clock (SCK) is generated internally by the SERCOM Baud Rate Generator (BRG). In the SPI mode, the BRG is set to Synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK and clocking the Shift register (see Clock Generation Baud-Rate Generator from Related Links). In the SPI client operation (CTRLA.MODE = 0x2), the clock is provided by an external host on the SCK pin. This clock is used to clock the SPI Shift register. Related Links 27.6.2.3. Clock Generation Baud-Rate Generator 29.6.2.4 Data Register The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register. 29.6.2.5 SPI Transfer Modes There are four combinations of SCK phase and polarity to transfer serial data. The SPI Data Transfer modes are shown in the following table and figure. SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize. Table 29-3. SPI Transfer Modes Mode CPOL CPHA Leading Edge 0 1 2 3 0 0 1 1 0 1 0 1 Rising, sample Rising, setup Falling, sample Falling, setup Note:

Leading edge is the first clock edge in a clock cycle. Trailing edge is the second clock edge in a clock cycle. Trailing Edge Falling, setup Falling, sample Rising, setup Rising, sample 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 681 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Figure 29-3. SPI Transfer Modes Mode 0 Mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Mode 1 Mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB 29.6.2.6 Transferring Data 29.6.2.6.1 Host In Host mode (CTRLA.MODE = 0x3), when Host SPI Select Enable (CTRLB.MSSEN) is 1, hardware will control the SS line. When Host SPI Select Enable (CTRLB.MSSEN) is 0, the SS line must be configured as an output. SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line low. When writing a character to the Data register (DATA), the character will be transferred to the Shift register when the shift register is empty. Once the content of TxDATA has been transferred to the Shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA. Each time one character is shifted out from the host, another character will be shifted in from the client simultaneously. If the receiver is enabled (CTRLA.RXEN = 1), the contents of the Shift register will be transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA. When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to 0, the software must pull the SS line high. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 682 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.6.2.6.2 Client In Client mode (CTRLA.MODE = 0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set. When SS is pulled low and SCK is running, the client will sample and shift out data according to the Transaction mode set. When the content of TxDATA has been loaded into the Shift register, INTFLAG.DRE will be set, and new data can be written to DATA. Similar to the host, the client will receive one character for each character transmitted. A character will be transferred into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set. When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the Shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by using the preloading feature. For more details, see 29.6.3.2. Preloading of the Client Shift Register. When transmitting several characters in one SPI transaction, the data has to be written into DATA register with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously received character will be transmitted. Once the DATA register is empty, it takes three PB1_CLK cycles for INTFLAG.DRE to be set. 29.6.2.7 Receiver Error Bit The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register

(STATUS). Once an error happens, the bit will stay set until it is cleared by writing 1 to it. The bit is also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification, selected by the immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON):

If CTRLA.IBON = 1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receiver complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) goes low. If CTRLA.IBON = 0, the Buffer Overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero. 29.6.3 Additional Features 29.6.3.1 Address Recognition When the SPI is configured for client operation (CTRLA.MODE = 0x2) with address recognition (CTRLA.FORM =

0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in Sleep mode, an address match can wake-up the device in order to process the transaction. If there is no match, the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits of the Shift register are checked against the Address register

(ADDR). Preload must be disabled (CTRLB.PLOADEN = 0) in order to use this mode. 29.6.3.2 Preloading of the Client Shift Register When starting a transaction, the client will first transmit the contents of the shift register before loading new data from DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 683 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will be shifted out. Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins. For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as shown in the following figure. For timing details, see Electrical Characteristics from Related Links. Preloading is enabled by writing 1 to the Client Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN). Figure 29-4. Timing Using Preloading Required SS-to-SCK time using PRELOADEN SS SS synchronized to system domain SCK Synchronization to system domain MISO to SCK setup time Related Links 38. Electrical Characteristics 29.6.3.3 Host with Several Clients Host with multiple clients in parallel is only available when Host SPI Select Enable (CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI clients, a SPI host can use general purpose I/O pins to control the SS line to each of the clients on the bus, as shown in the following figure. In this configuration, the single selected SPI client will drive the tri-state MISO line. Figure 29-5. Multiple Clients in Parallel shift register SPI Host MOSI MISO SCK SS[0]

SS[n-1]

MOSI MISO SCK SS MOSI MISO SCK SS shift register SPI Client 0 shift register SPI Client n-1 Another configuration is multiple clients in series, as shown in the following figure. In this configuration, all n attached clients are connected in series. A common SS line is provided to all clients, enabling them simultaneously. The host must shift n characters for a complete transaction. Depending on the Host SPI Select Enable bit (CTRLB.MSSEN), the SS line can be controlled either by hardware or user software and normal GPIO. The SS line is controlled by a normal GPIO. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 684 Microchip Confidential Confidential Figure 29-6. Multiple Clients in Series shift register SPI Host MOSI MISO SCK SS PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... MOSI MISO SCK SS MOSI MISO SCK SS shift register SPI Client 0 shift register SPI Client n-1 29.6.3.4 Loop-Back Mode For Loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally. 29.6.3.5 Hardware Controlled SS In Host mode, a single SS chip select can be controlled by hardware by writing the Host SPI Select Enable

(CTRLB.MSSEN) bit to 1. In this mode, the SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames. In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI Transfer mode. Figure 29-7. Hardware Controlled SS T T T T T SS SCK T = 1 to 2 baud cycles When CTRLB.MSSEN = 0, the SS pin(s) is/are controlled by user software and normal GPIO. 29.6.3.6 SPI Select Low Detection In Client mode, the SPI can wake the CPU when the SPI Select (SS) goes low. When the SPI Select Low Detect is enabled (CTRLB.SSDE = 1), a high-to-low transition will set the SPI Select Low Interrupt flag (INTFLAG.SSL) and the device will wake-up if applicable. 29.6.3.7 Host Inter-Character Spacing When configured as host, inter-character spacing can be increased by writing a non-zero value to the Inter-Character Spacing bit field in the Control C register (CTRLC.ICSPACE). When non-zero, CTRLC.ICSPACE represents the minimum number of baud cycles that the SCK clock line does not toggle and the next character is stalled. The figure gives an example for CTRLC.ICSPACE = 4; In this case, the SCK is inactive for four baud cycles. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 685 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Figure 29-8. Four Cycle Inter-Character Spacing Example T T T T SCK T = 1 baud cycle 29.6.3.8 32-bit Extension For better system bus utilization, 32-bit data receive and transmit can be enabled by writing to the Data 32-bit bit field in the Control C register (CTRLC.DATA32B = 1). When enabled, write and read transactions to/from the DATA register are 32 bit in size. If frames are not multiples of 4 Bytes, the Length Counter (LENGTH.LEN) and Length Enable (LENGTH.LENEN) must be configured before data transfer begins. LENGTH.LEN must be enabled only when CTRLC.DATA32B is enabled. The following figure shows the order of transmit and receive when using 32-bit mode. Bytes are transmitted or received and stored in order from 0 to 3. Only 8-bit character size is supported. Figure 29-9. 32-bit Extension Byte Ordering APB Write/Read BYTE3 BYTE2 BYTE1 BYTE0 Bit Position 31 0 32-bit Extension Client Operation The following figure shows a transaction with 32-bit Extension enabled (CTRLC.DATA32B = 1). When address recognition is enabled (CTRLA.FORM = 0x2) and there is an address match, the address is loaded into the FIFO as Byte zero and data begins with Byte 1. INTFLAGS.RXC will then be raised for every 4 Bytes transferred. For transmit, there is a 32-bit holding buffer in the core domain. Once DATA has been registered in the core domain, INTFLAG.DRE will be raised, so that the next 32 bits can be written to the DATA register. Figure 29-10. 32-bit Extension Client Operation RXC interrupt RXC interrupt ADDRESS S W Byte 0 Byte 1 Byte 2 Byte 3 S W When utilizing the length counter, the LENGTH register must be written before the frame begins. If the frame length while SS is low is not a multiple of LENGTH.LEN Bytes, the Length Error Status bit (STATUS.LENERR) is raised. If LENGTH.LEN is not a multiple of 4 Bytes, the final INTFLAG.RXC interrupt will be raised when the last Byte is received. The length count is based on the received Bytes, or the number of clocks if the receiver is not enabled. If pre-loading is disabled and DATA is written for transmit before SCK starts, transmitted data will be delayed by one Byte, but the length counter will still increment for the first (empty) Byte transmission. When the counter reaches LENGTH.LEN, the internal length counter, Rx Byte counter, and Tx Byte counter are reset. If multiple lengths are to be transmitted, INTFLAG.TXC must go high before writing DATA for subsequent lengths. If there is a Length Error (STATUS.LENERR), the remaining Bytes in the length will be transmitted at the beginning of the next frame. If this is not desired, the SERCOM must be disabled and re-enabled in order to flush the Tx and Rx pipelines. Writing the LENGTH register while a frame is in progress will produce unpredictable results. If LENGTH.LENEN is not configured and a frame is not a multiple of 4 Bytes (while SS is low), the remainder will be transmitted in the next frame. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 686 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 32-bit Extension Host Operation When using the SPI configured as Host, the Length and the Length Enable bit fields (LENGTH.LEN and LENGTH.LENEN) must be written before the frame begins. When LENGTH.LENEN is written to 1, the value of LENGTH.LEN determines the number of data bytes in the transaction from 1 to 255. For receive data, INTFLAG.RXC is raised every 4 Bytes received. If LENGTH.LEN is not a multiple of 4 Bytes, the final INTFLAG.RXC is set when the final byte is received. For transmit, there is a holding buffer for the 32-bit data in the core domain. Once DATA has been registered in the SCK domain, INTFLAG.DRE will be raised so that the next 32 bits can be written to the DATA register. If multiple lengths are to be transmitted, INTFLAG.TXC must go high before writing DATA for subsequent lengths. 29.6.4 DMA, Interrupts, and Events Table 29-4. Module Request for SERCOM SPI Condition Data Register Empty (DRE) Receive Complete (RXC) Transmit Complete (TXC) SPI Select Low (SSL) Error (ERROR) Request DMA Yes

(request cleared when data is written) Yes

(request cleared when data is read) NA NA NA Interrupt Event NA Yes Yes Yes Yes Yes Table 29-5. Module Request for SERCOM SPI Condition Standard (DRE): Data Register Empty FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty Request DMA Yes

(request cleared when data is written) Interrupt Event Yes NA Standard (RXC): Receive Complete FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed. Yes

(request cleared when data is read) Yes Standard (TXC): Transmit Complete FIFO (TXC): Transmit Complete and TX FIFO is empty SPI Select Low (SSL) Error (ERROR) NA NA NA Yes Yes Yes 29.6.4.1 DMA Operation The SPI generates the following DMA requests:

Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read. Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written. Data received (RX): The request is set when data is available in the receive FIFO or if at least RXTRHOLD data are available in the RX FIFO when FIFO operation is enabled. The request is cleared when DATA is read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 687 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty or if at least TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The request is cleared when DATA is written. 29.6.4.2 Interrupts The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from any Sleep mode:

Data Register Empty (DRE) Receive Complete (RXC) Transmit Complete (TXC) SPI Select Low (SSL) Error (ERROR) Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing 1 to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing 1 to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SPI is reset. For details on clearing Interrupt flags, see INTFLAG register description. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 29.6.4.3 Events Not applicable. 29.6.5 Sleep Mode Operation The behavior in Sleep mode is depending on the host/client configuration and the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY):

Host operation, CTRLA.RUNSTDBY = 1: The peripheral clock GCLK_SERCOMx_CORE will continue to run in Idle Sleep mode and in Standby Sleep mode. Any interrupt can wake up the device. Host operation, CTRLA.RUNSTDBY = 0: GCLK_SERCOMx_CORE will be disabled after the ongoing transaction is finished. Any interrupt can wake up the device. Client operation, CTRLA.RUNSTDBY = 1: The Receive Complete interrupt can wake up the device. Client operation, CTRLA.RUNSTDBY = 0: All reception will be dropped, including the ongoing transaction. 29.6.6 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus error is generated. The following bits need to be synchronized when written:

Software Reset bit in the CTRLA register (CTRLA.SWRST) Enable bit in the CTRLA register (CTRLA.ENABLE) Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Note:CTRLB.RXEN is write-synchronized somewhat differently. For more details, see 29.8.2. CTRLB register. Required write synchronization is denoted by the "Write-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 688 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.7 Register Summary See SERCOM0/SERCOM1/SERCOM2 module in the Product Memory Mapping Overview from Related Links for base address based on the SERCOM instant used. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 RUNSTDBY MODE[2:0]

ENABLE SWRST DORD CPOL CPHA FORM[3:0]

DIPO[1:0]

IBON DOPO[1:0]

PLOADEN AMODE[1:0]

FIFOCLR[1:0]

MSSEN CHSIZE[2:0]

SSDE RXEN ICSPACE[5:0]

ERROR ERROR ERROR BAUD[7:0]

DATA32B SSL SSL SSL RXC RXC RXC TXC TXC TXC DRE DRE DRE BUFOVF LENERR LENGTH CTRLB ENABLE SWRST 0x00 CTRLA 0x04 CTRLB 0x08 CTRLC 0x0C 0x0D

... 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A BAUD Reserved INTENCLR Reserved INTENSET Reserved INTFLAG Reserved STATUS 0x1C SYNCBUSY 0x20

... 0x21 0x22 Reserved LENGTH 0x24 ADDR 0x28 DATA 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x2C

... 0x2F 0x30 Reserved DBGCTRL 7:0 Related Links 7. Product Memory Mapping Overview LEN[7:0]

ADDR[7:0]

ADDRMASK[7:0]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

LENEN DBGSTOP 29.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 689 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. See Peripheral Access Controller (PAC) from Related Links. Related Links 20. Peripheral Access Controller (PAC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 690 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLA 0x00 0x00000000 Bit 31 Access Reset 30 DORD R/W 0 Bit 23 22 Access Reset Bit 15 14 Access Reset 29 CPOL R/W 0 21 R/W 0 13 DIPO[1:0]

Bit 7 6 5 RUNSTDBY Access Reset R/W 0 Bit 30 DORDData Order 28 CPHA R/W 0 20 R/W 0 12 4 R/W 0 27 R/W 0 19 FORM[3:0]

26 R/W 0 18 11 10 25 R/W 0 17 R/W 0 9 24 R/W 0 16 R/W 0 DOPO[1:0]

3 MODE[2:0]

R/W 0 2 R/W 0 1 ENABLE R/W 0 8 IBON R/W 0 0 SWRST R/W 0 This bit selects the data order when a character is shifted out from the shift register. This bit is not synchronized. Value 0 1 Description MSB is transferred first. LSB is transferred first. Bit 29 CPOLClock Polarity In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode. This bit is not synchronized. Value 0 Description SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. 1 Bit 28 CPHAClock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. This bit is not synchronized. Mode CPOL CPHA 0 0 1 1 0 1 0 1 Leading Edge Rising, sample Rising, change Falling, sample Falling, change Trailing Edge Falling, change Falling, sample Rising, change Rising, sample Description The data is sampled on a leading SCK edge and changed on a trailing SCK edge. The data is sampled on a trailing SCK edge and changed on a leading SCK edge. 0x0 0x1 0x2 0x3 Value 0 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 691 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Bits 27:24 FORM[3:0]Frame Format This bit field selects the various frame formats supported by the SPI in client mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register. FORM[3:0]

0x0 0x1 0x2 0x3-0xF Name SPI

SPI_ADDR

Description SPI frame Reserved SPI frame with address Reserved Bits 21:20 DIPO[1:0]Data In Pinout These bits define the data in (DI) pad configurations. In host operation, DI is MISO. In client operation, DI is MOSI. These bits are not synchronized. DIPO[1:0]

0x0 0x1 0x2 0x3 Name PAD[0]

PAD[1]

PAD[2]

PAD[3]

Bits 17:16 DOPO[1:0]Data Out Pinout Description SERCOM PAD[0] is used as data input SERCOM PAD[1] is used as data input SERCOM PAD[2] is used as data input SERCOM PAD[3] is used as data input These bits define the available pad configurations for data out (DO), the serial clock (SCK) and the SPI Select (SS). In Client operation, the SPI Select line (SS) is controlled by DOPO. In host operation, the SPI Select line (SS) is either controlled by DOPO when CTRLB.MSSEN = 1, or by a GPIO driven by the application when CTRLB.MSSEN =

0. In host operation, DO is MOSI. In client operation, DO is MISO. These bits are not synchronized. DOPO DO SCK Client SS Host SS (MSSEN = 1) Host SS (MSSEN = 0) 0x0 0x1 0x2 0x3 PAD[0] PAD[1] PAD[2]

Reserved PAD[3] PAD[1] PAD[2]

Reserved PAD[2]

PAD[2]

Any GPIO configured by the application Any GPIO configured by the application Bit 8 IBONImmediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized. Value 0 1 Description STATUS.BUFOVF is set when it occurs in the data stream. STATUS.BUFOVF is set immediately upon buffer overflow. Bit 7 RUNSTDBYRun In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. RUNSTDBY Client Host 0x0 0x1 Disabled. All reception is dropped, including the ongoing transaction. Ongoing transaction continues, wake on Receive Complete interrupt. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device. Generic clock is enabled while in sleep modes. All interrupts can wake up the device. Bits 4:2 MODE[2:0]Operating Mode These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM. 0x2: SPI client operation 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 692 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 0x3: SPI host operation These bits are not synchronized. Bit 1 ENABLEEnable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled or being disabled. The peripheral is enabled or being enabled. Bit 0 SWRSTSoftware Reset Writing 0 to this bit has no effect. Writing 1 to this bit Resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing 1 to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing Reset will result in an APB error. Reading any register will return the Reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not enable-protected. Value 0 1 Description There is no Reset operation ongoing. The Reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 693 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.2 Control B Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLB 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 FIFOCLR[1:0]

Access Reset R/W 0 Bit 15 R/W 0 14 AMODE[1:0]

Access Reset R/W 0 R/W 0 Bit 7 Access Reset 6 PLOADEN R/W 0 12 11 10 13 MSSEN R/W 0 5 4 3 2 R/W 0 1 CHSIZE[2:0]

R/W 0 17 RXEN R/W 0 9 SSDE R/W 0 16 8 0 R/W 0 Bits 23:22 FIFOCLR[1:0]FIFO Clear When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.CTRLB = 0. These bits are not enable-protected. FIFOCLR[1:0]

0x0 0x1 0x2 0x3 Name NONE TXFIFO RXFIFO BOTH Description No action Clear TX FIFO Clear RX FIFO Clear both TX/RX FIFO Bit 17 RXENReceiver Enable Writing 0 to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared. Writing 1 to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as 1. Writing 1 to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as 1. This bit is not enable-protected. Value 0 1 Description The receiver is disabled. The receiver is enabled or it will be enabled when SPI is enabled. Bits 15:14 AMODE[1:0]Address Mode These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode. These bits are not synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 694 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... AMODE[1:0] Name Description 0x0 0x1 0x2 0x3 ADDRMASK is used as a mask to the ADDR register MASK 2_ADDRS The client responds to the two unique addresses in ADDR and ADDRMASK RANGE The client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit Reserved Bit 13 MSSENHost SPI Select Enable This bit enables hardware SPI Select (SS) control. This bit is not synchronized. Value 0 1 Description Hardware SS control is disabled. Hardware SS control is enabled. Bit 9 SSDESPI Select Low Detect Enable This bit enables wake-up when the SPI Select (SS) pin transitions from high-to-low. This bit is not synchronized. Value 0 1 Description SS low detector is disabled. SS low detector is enabled. Bit 6 PLOADENClient Data Preload Enable Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the Shift register. This bit is not synchronized. Bits 2:0 CHSIZE[2:0]Character Size These bits are not synchronized. CHSIZE[2:0]

0x0 0x1 0x2-0x7 Name 8BIT 9BIT Description 8 bits 9 bits Reserved 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 695 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.3 Control C Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRLC 0x08 0x00000000 Bit 31 30 29 28 27 26 25 Access Reset 24 DATA32B R/W 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 Access Reset 5 R/W 0 4 R/W 0 3 2 ICSPACE[5:0]

R/W 0 R/W 0 Bit 24 DATA32BData 32 Bit This bit enables 32-bit Extension for read and write transactions to the DATA register. When disabled, access is according to CTRLB.CHSIZE. Value 0 1 Description Transactions from and to DATA register are according to CTRLB.CHSIZE Transactions from and to DATA register are 32-bit 9 1 8 0 R/W 0 R/W 0 Bits 5:0 ICSPACE[5:0]Inter-Character Spacing When non-zero, CTRLC.ICSPACE selects the minimum number of baud cycles the SCK line will not toggle between characters. Value 0x00 0x01-0x3 F Description Inter-Character Spacing is disabled The minimum Inter-Character Spacing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 696 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.4 Baud Rate Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected BAUD 0x0C 0x00 Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 BAUD[7:0]

4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bits 7:0 BAUD[7:0]Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation Baud-Rate Generator. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 697 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.5 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x14 0x00 This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit Access Reset 7 ERROR R/W 0 6 5 4 3 SSL R/W 0 2 RXC R/W 0 1 TXC R/W 0 0 DRE R/W 0 Bit 7 ERRORError Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 3 SSLSPI Select Low Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the SPI Select Low Interrupt Enable bit, which disables the SPI Select Low interrupt. Value 0 1 Description SPI Select Low interrupt is disabled. SPI Select Low interrupt is enabled. Bit 2 RXCReceive Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 TXCTransmit Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Transmit Complete interrupt. Value 0 1 Description Transmit Complete interrupt is disabled. Transmit Complete interrupt is enabled. Bit 0 DREData Register Empty Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 698 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.6 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x16 0x00 This register allows the user to enable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit Access Reset 7 ERROR R/W 0 6 5 4 3 SSL R/W 0 2 RXC R/W 0 1 TXC R/W 0 0 DRE R/W 0 Bit 7 ERRORError Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 3 SSLSPI Select Low Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the SPI Select Low Interrupt Enable bit, which enables the SPI Select Low interrupt. Value 0 1 Description SPI Select Low interrupt is disabled. SPI Select Low interrupt is enabled. Bit 2 RXCReceive Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 TXCTransmit Complete Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. Value 0 1 Description Transmit Complete interrupt is disabled. Transmit Complete interrupt is enabled. Bit 0 DREData Register Empty Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 699 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.7 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x18 0x00

Bit Access Reset 7 ERROR R/W 0 Bit 7 ERRORError 6 5 4 3 SSL R/W 0 2 RXC R 0 1 TXC R/W 0 0 DRE R 0 This flag is cleared by writing 1 to it. This bit is set when any error is detected. Errors that will set this flag have corresponding Status flags in the STATUS register. The BUFOVF error and the LENERR error will set this Interrupt flag. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the flag. Bit 3 SSLSPI Select Low This flag is cleared by writing 1 to it. This bit is set when a high to low transition is detected on the SS pin in Client mode and SPI Select Low Detect

(CTRLB.SSDE) is enabled. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the flag. Bit 2 RXCReceive Complete This flag is cleared by reading the Data (DATA) register or by disabling the receiver. This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction will be an address. Writing 0 to this bit has no effect. Writing 1 to this bit has no effect. Bit 1 TXCTransmit Complete This flag is cleared by writing 1 to it or by writing new data to DATA. In Host mode, this flag is set when the data have been shifted out and there are no new data in DATA. In Client mode, this flag is set when the SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the flag. Bit 0 DREData Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing 0 to this bit has no effect. Writing 1 to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 700 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.8 Status Name:

Offset:

Reset:

Property:

STATUS 0x1A 0x0000 Bit 15 14 13 12 Access Reset 11 LENERR R/W 0 Bit 7 6 5 4 3 Access Reset Bit 11 LENERRTransaction Length Error 9 1 8 0 10 2 BUFOVF R/W 0 This bit is set in the Client mode when the length counter is enabled (LENGTH.LENEN = 1) and the transfer length while SS is low is not a multiple of LENGTH.LEN. Writing 0 to this bit has no effect. Writing 1 to this bit will clear it. Value 0 1 Description No Length Error has occurred. A Length Error has occurred. Bit 2 BUFOVFBuffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing 1 to the bit or by disabling the receiver. This bit is set when a Buffer Overflow condition is detected. When set, the corresponding RxDATA will be zero. Writing 0 to this bit has no effect. Writing 1 to this bit will clear it. Value 0 1 Description No Buffer Overflow has occurred. A Buffer Overflow has occurred. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 701 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.9 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x1C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 Access Reset 3 4 LENGTH R 0 2 CTRLB R 0 1 ENABLE R 0 0 SWRST R 0 Bit 4 LENGTHLENGTH Synchronization Busy Writing to the LENGTH register requires synchronization. When writing to LENGTH, SYNCBUSY.LENGTH will be set until synchronization is complete. If the LENGTH register is written to while SYNCBUSY.LENGTH is asserted, an APB error is generated. Note:In the Client mode, the clock is only running during data transfer, therefore, SYNCBUSY.LENGTH will remain asserted until the next data transfer begins. Value 0 1 Description LENGTH synchronization is not busy. LENGTH synchronization is busy. Bit 2 CTRLBCTRLB Synchronization Busy Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.CTRLB = 1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB = 1, an APB error will be generated. Value 0 1 Description CTRLB synchronization is not busy. CTRLB synchronization is busy. Bit 1 ENABLESERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.ENABLE = 1 until synchronization is complete. Value 0 1 Description Enable synchronization is not busy. Enable synchronization is busy. Bit 0 SWRSTSoftware Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST = 1 until synchronization is complete. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 702 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 703 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.10 Length Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized LENGTH 0x22 0x0000 Bit 15 14 13 12 11 10 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 LEN[7:0]

3 R/W 0 2 R/W 0 9 1 R/W 0 8 LENEN R/W 0 0 R/W 0 Bit 8 LENENData Length Enable In 32-bit Extension mode, this bit field enables the length counter. Value 0 1 Description Length counter disabled Length counter enabled Bits 7:0 LEN[7:0]Data Length In 32-bit Extension mode, this bit field configures the data length after which the flags INTFLAG.RCX or INTFLAG.DRE are raised. Description Value Reserved if LENEN = 0x1 0x00 Data Length 0x01-0xF F 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 704 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.11 Address Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected ADDR 0x24 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset Bit 7 Access Reset R/W 0 22 R/W 0 14 6 R/W 0 21 R/W 0 13 5 R/W 0 20 19 ADDRMASK[7:0]

R/W 0 12 4 R/W 0 ADDR[7:0]

R/W 0 11 3 R/W 0 18 R/W 0 10 2 R/W 0 17 R/W 0 9 1 16 R/W 0 8 0 R/W 0 R/W 0 Bits 23:16 ADDRMASK[7:0]Address Mask These bits hold the address mask when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). Bits 7:0 ADDR[7:0]Address These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 705 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.12 Data Name:

Offset:

Reset:

Property:

DATA 0x28 0x0000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DATA[31:0]Data Reading these bits will return the contents of the receive data buffer. The register must be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. Writing these bits will write the transmit data buffer. This register must be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Reads and writes are 32-bit or CTLB.CHSIZE based on the CTRLC.DATA32B setting. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 706 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Serial Peripheral Interface (SERCOM S... 29.8.13 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x30 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGSTOPDebug Stop Mode DBGSTOP R/W 0 This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 707 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30. SERCOM Inter-Integrated Circuit (SERCOM I2C) 30.1 Overview The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication interface

(SERCOM). The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 30-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM. A SERCOM instance can be configured to be either an I2C host or an I2C client. Both host and client have an interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C host uses the SERCOM baud-rate generator, while the I2C client uses the SERCOM address match logic. 30.2 Features SERCOM I2C includes the following features:

Host or Client Operation Can be used with DMA Philips I2C Compatible SMBus Compatible PMBus Compatible Support of 100 kHz and 400 kHz, 1 MHz I2C mode low system clock frequencies 32-bit Data Extension for better system bus utilization Up to 16-bytes internal FIFO 4-Wire Operation Supported Physical interface includes:

Slew-rate limited outputs Filtered inputs Client Operation:

Operation in all Sleep modes Wake-up on address match 7-bit and 10-bit Address match in hardware for:

Unique address and/or 7-bit general call address Address range Two unique addresses can be used with DMA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 708 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.3 Block Diagram Figure 30-1. I2C Single-Host Single-Client Interconnection Host Client BAUD TxDATA TxDATA ADDR/ADDRMASK baud rate generator SCL hold low shift register 0 0 SCL 0 SCL hold low SDA 0 shift register RxDATA RxDATA

30.4 Signal Description Signal Name PAD[0]

PAD[1]

PAD[2]

PAD[3]

Type Digital I/O Digital I/O Digital I/O Digital I/O Description SDA SCL SDA_OUT (4-wire operation) SCL_OUT (4-wire operation) I2C pins on SERCOM are fixed pins and not configurable through PPS functionality. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 30.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines In order to use the SERCOMs I/O lines, the I/O pins must be configured as direct using the System Configuration registers (See System Configuration and Register Locking (CFG) from Related Links). I2C does not operate through PPS. See DEVCFG1 configuration bits SCOMn_HSEN in Configuration Bits Fuses and also CFGCON1 SCOMn_HSEN in CFGCON1(L) register. Note:SERCOM2 has only I2C functionality and therefore, the direct configuration using System configuration register is not required. When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are still effective. In I2C mode pull-up resistors are disabled. External pull-up resistors are required for proper function. Related Links 18. System Configuration and Register Locking (CFG) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 709 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.5.2 Power Management This peripheral can continue to operate in any Sleep mode where its source clock is running. The interrupts can wake-up the device from Sleep modes. 30.5.3 Clocks Two generic clocks are used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock

(GCLK_SERCOMx_CORE) can clock the I2C when working as a host. The slow clock (GCLK_SERCOMx_SLOW) is required only for certain functions, for example, for SMBus timing 32KHz_LPCLK must be configured as this is the source for GCLK_SERCOMx_SLOW clock. These two clocks must be configured and enabled in the CRU registers before using the I2C. These generic clocks are asynchronous to the bus clock (PBx_CLK). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. 30.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). To use DMA requests with this peripheral, the DMAC must be configured first (see Direct Memory Access Controller (DMAC) from Related Links). Related Links 22. Direct Memory Access Controller (DMAC) 30.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 30.5.6 Events Not applicable. 30.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control

(DBGCTRL) register for details. 30.5.8 Register Access Protection Registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC). PAC write protection is not available for the following registers:

Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Address register (ADDR) in Host mode Optional PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. 30.5.9 Analog Connections Not applicable. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 710 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.6 Functional Description 30.6.1 Principle of Operation The I2C interface uses two physical lines for communication:

Serial Data Line (SDA) for data transfer Serial Clock Line (SCL) for the bus clock A transaction starts with the I2C host sending the Start condition, followed by a 7-bit address and a direction bit (read or write to/from the client). The addressed I2C client will then Acknowledge (ACK) the address, and data packet transactions can begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. If a data packet is Not Acknowledged (NACK), whether by the I2C client or host, the I2C host takes action by either terminating the transaction by sending the Stop condition, or by sending a repeated start to transfer more data. The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains the transaction symbols. These symbols will be used in the following descriptions. Figure 30-2. Transaction Diagram Symbols Bus Driver Special Bus Conditions Host driving bus S START condition Client driving bus Sr repeated START condition Either Host or Client driving bus P STOP condition Data Package Direction Acknowledge Host Read Host Write R

'1'

W

'0'

Acknowledge (ACK) Not Acknowledge (NACK) A

'0'

A

'1'

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 711 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Figure 30-3. Basic I2C Transaction Diagram SDA SCL 6..0 7..0 7..0 S ADDRESS R/W ACK DATA ACK DATA ACK/NACK P S ADDRESS R/W A DATA A DATA A/A P Direction Address Packet Data Packet #0 Data Packet #1 Transaction 30.6.2 Basic Operation 30.6.2.1 Initialization The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled

(CTRLA.ENABLE is 0):

Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits Baud register (BAUD) Address register (ADDR) in client operation. When the I2C is enabled or is being enabled (CTRLA.ENABLE = 1), writing to these registers will be discarded. If the I2C is being disabled, writing to these registers will be completed after the disabling. Enable-protection is denoted by the Enable-Protection property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps:

1. 2. 3. 4. 5. 6. Select I2C Host or Client mode by writing 0x4 (Client mode) or 0x5 (Host mode) to the Operating Mode bits in the CTRLA register (CTRLA.MODE). If desired, select the SDA Hold Time in the CFGCON1 register (CFGCON1.I2CDSELx). In Client mode, the minimum client setup time for the SDA can be selected in the SDA Setup Time bit group in the Control C register (CTRLC.SDASETUP). If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register

(CTRLB.SMEN). If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register

(CTRLA.LOWTOUT). In Host mode:

a. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register

(CTRLA.INACTOUT). b. Write the Baud Rate register (BAUD) to generate the desired baud rate. In Client mode:

a. Configure the address match configuration by writing the Address Mode value in the CTRLB register b.

(CTRLB.AMODE). Set the Address and Address Mask value in the Address register (ADDR.ADDR and ADDR.ADDRMASK) according to the address configuration. 30.6.2.2 Enabling, Disabling, and Resetting This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 712 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Writing 1 to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. 30.6.2.3 I2C Bus State Logic The Bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all Sleep modes with running GCLK_SERCOMx_CORE clocks. The start and stop detectors and the bit counter are all essential in the process of determining the current Bus state. The Bus state is determined according to Bus State Diagram. Software can get the current Bus state by reading the Host Bus State bits in the Status register

(STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary. Figure 30-4. Bus State Diagram RESET UNKNOWN

(0b00) Timeout or Stop Condition Start Condition IDLE

(0b01) Timeout or Stop Condition BUSY

(0b11) Stop Condition Write ADDR to generate Start Condition Lost Arbitration OWNER

(0b10) R e p e a t e d S t a r t C o n d i t i o n Write ADDR to generate Repeated Start Condition The Bus state machine is active when the I2C host is enabled. After the I2C host has been enabled, the Bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will transition to IDLE (0b01) by either:

Forcing by writing 0b01 to STATUS.BUSSTATE A Stop condition is detected on the bus If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs. Note:Once a known Bus state is established, the Bus state logic will not re-enter the UNKNOWN state. When the bus is IDLE it is ready for a new transaction. If a Start condition is issued on the bus by another I2C host in a multi-host setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a Stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be configured). If a Start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e., arbitration was not lost, the I2C host can issue a Stop condition, which will change the Bus state back to IDLE. However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the Bus state becomes BUSY until a Stop condition is detected. A repeated Start condition will change the Bus state only if arbitration is lost while issuing a repeated start. Note:Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a software Reset (CTRLA.SWRST='1'). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 713 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.6.2.4 I2C Host Operation The I2C host is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations, and a Special Smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register

(CTRLA.SMEN). The I2C host has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the Acknowledge bit . In this mode the I2C host operates according to I2C Host Behavioral Diagram (SCLSM=0) as shown in the following figure. The circles labeled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C host operation throughout the document. Figure 30-5. I2C Host Behavioral Diagram (SCLSM=0) APPLICATION HOST BUS INTERRUPT + SCL HOLD M1 M2 M3 M4 BUSY P IDLE S ADDRESS R/W BUSY SW BUSY SW Wait for IDLE R/W A W A SW SW SW P IDLE Sr M1 M2 M3 BUSY M4 DATA A/A CLIENT BUS INTERRUPT + SCL HOLD SW Software interaction SW A BUSY The host provides data on the bus A/A P IDLE Addressed client provides data on the bus A/A Sr A/A M4 M2 M3 In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Host Behavioral Diagram

(SCLSM=1) shown in the following figure. This strategy can be used when it is not necessary to check DATA before acknowledging. R A DATA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 714 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Figure 30-6. I2C Host Behavioral Diagram (SCLSM=1) APPLICATION Host Bus INTERRUPT + SCL HOLD M1 M2 M3 M4 BUSY P IDLE S ADDRESS R/W BUSY SW BUSY SW Wait for IDLE R/W A W A SW SW SW P IDLE Sr M1 M2 M3 BUSY M4 DATA A/A SW Software interaction The host provides data on the bus Addressed client provides data on the bus Client Bus INTERRUPT + SCL HOLD SW BUSY P IDLE Sr M4 M2 M3 R A DATA A/A 30.6.2.4.1 Host Clock Generation The SERCOM peripheral supports several I2C bidirectional modes:

Standard mode (Sm) up to 100 kHz Fast mode (Fm) up to 400 kHz Fast mode Plus (Fm+) up to 1 MHz The Host clock configuration for Sm, Fm and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode and Fast-Mode Plus) as follows. Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) In I2C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section:

The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 715 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Figure 30-7. SCL Timing P S TLOW Sr TRISE SCL SDA TBUF THIGH TFALL TSU;STO THD;STA TSU;STA The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW = 0, the Host Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it. TLOW Low period of SCL clock TSU;STO Set-up time for stop condition TBUF Bus free time between stop and start conditions THD;STA Hold time (repeated) start condition TSU;STA Set-up time for repeated start condition THIGH is timed using the SCL high time count from BAUD.BAUD TRISE is determined by the bus impedance; for internal pull-ups. TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. The SCL frequency is given by:

1 TLOW + THIGH + TRISE fSCL =

When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency:

fSCL =

When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:

fGCLK 10 + 2BAUD + fGCLK TRISE fSCL =

The following formulas can determine the SCL TLOW and THIGH times:

fGCLK 10 + BAUD + BAUDLOW + fGCLK TRISE TLOW =

BAUDLOW + 5 fGCLK BAUD + 5 fGCLK THIGH =

Note:The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB (PBx_CLK) cycles when the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA write and IF clear must be controlled by software. Note:When timing is controlled by user, the Smart Mode cannot be enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 716 Microchip Confidential Confidential 30.6.2.4.2 Transmitting Address Packets PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... The I2C host starts a bus transaction by writing the I2C client address to ADDR.ADDR and the direction bit, as described in 30.6.1. Principle of Operation. If the bus is busy, the I2C host will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C host will issue a start condition on the bus. The I2C host will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I2C host, one of four cases will arise according to arbitration and transfer direction. Case 1: Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C host is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly to the Arbitration Lost condition. In this case, the MB Interrupt flag and Host Bus Error bit in the Status register

(STATUS.BUSERR) are both set in addition to STATUS.ARBLOST. The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication. In this case, software will typically inform the application code of the condition and then clear the Interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared automatically the next time the ADDR.ADDR register is written. Case 2: Address packet transmit complete No ACK received If there is no I2C client device responding to the address packet, then the INTFLAG.MB Interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C client is busy with other tasks or sleeping. Therefore, it is not able to respond. In this event, the next step can be either issuing a Stop condition (recommended) or resending the address packet by a repeated Start condition. When using SMBus logic, the client must ACK the address. If there is no response, it means that the client is not available on the bus. Case 3: Address packet transmit complete Write packet, Host on Bus set If the I2C host receives an acknowledge response from the I2C client, INTFLAG.MB will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA. Transmit a new address packet by writing ADDR.ADDR. A repeated Start condition will automatically be inserted before the address packet. Issue a Stop condition, consequently terminating the transaction. Case 4: Address packet transmit complete Read packet, Client on Bus set If the I2C host receives an ACK from the I2C client, the I2C host proceeds to receive the next byte of data from the I2C client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue:

Let the I2C host continue to read data by acknowledging the data received. ACK can be sent by software, or automatically in Smart mode. Transmit a new address packet. Terminate the transaction by issuing a Stop condition. Note:An ACK or NACK will be automatically transmitted if Smart mode is enabled. The Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent. 30.6.2.4.3 Transmitting Data Packets When an address packet with direction Host Write (see Figure 30-3) was transmitted successfully , INTFLAG.MB will be set. The I2C host will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for packet collisions. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 717 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... If a collision is detected, the I2C host will lose arbitration and STATUS.ARBLOST will be set. If the transmit was successful, the I2C host will receive an ACK bit from the I2C client, and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome. It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the I2C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet arbitration. STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I2C host is not allowed to continue transmitting data packets if a NACK is received from the I2C client. 30.6.2.4.4 Receiving Data Packets (SCLSM=0) When INTFLAG.SB is set, the I2C host will already have received one data packet. The I2C host must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission. 30.6.2.4.5 Receiving Data Packets (SCLSM=1) When INTFLAG.SB is set, the I2C host will already have received one data packet and transmitted an ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in the Smart mode. 30.6.2.4.6 10-Bit Addressing When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register

(ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted, see 10-bit Address Transmission for a Read Transaction. The addressed client acknowledges the two address bytes, and the transaction continues. Regardless of whether the transaction is a read or write, the host must start by sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero. If the host receives a NACK after the first byte, the Write Interrupt flag will be raised and the STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more clients, then the host will proceed to transmit the second address byte and the host will first see the Write Interrupt flag after the second byte is transmitted. If the transaction direction is read-from-client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to '1'. Figure 30-8. 10-bit Address Transmission for a Read Transaction MB INTERRUPT S 11110 addr[9:8]

AW addr[7:0]

A This implies the following procedure for a 10-bit read operation:

S W Sr 11110 addr[9:8]

1 R A 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit

(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR). Proceed to transmit data. 3. 30.6.2.5 I2C Client Operation The I2C client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register

(CTRLA.SMEN). The I2C client has two interrupt strategies. When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this mode, the I2C client operates according to I2C Client Behavioral Diagram (SCLSM=0) as shown in the following figure. The circles labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction. This diagram is used as reference for the description of the I2C client operation throughout the document. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 718 Microchip Confidential Confidential

 

 

PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Figure 30-9. I2C Client Behavioral Diagram (SCLSM=0) AMATCH INTERRUPT DRDY INTERRUPT S1 S1 A A A A S W S W P Sr S2 S3 DATA P Sr S2 S3 DATA A/A S W S W A/A S1 S2 S3 S ADDRESS R PREC INTERRUPT W Interrupt on STOP Condition Enabled S W S W Software interaction The host provides data on the bus Addressed client provides data on the bus In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in the following figure I2C Client Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. For host reads, an address and data interrupt will be issued simultaneously after the address acknowledge. However, for host writes, the first data interrupt will be seen after the first data byte has been received by the client and the acknowledge bit has been sent to the host. Figure 30-10. I2C Client Behavioral Diagram (SCLSM=1) AMATCH INTERRUPT (+ DRDY INTERRUPT in Host Read mode) DRDY INTERRUPT P Sr S2 S3 DATA A/A S W S W P Sr S2 S3 DATA A/A S W S1 S2 S3 S ADDRESS R A/A PREC INTERRUPT W A/A Interrupt on STOP Condition Enabled S W S W Software interaction The host provides data on the bus Addressed client provides data on the bus 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 719 Microchip Confidential Confidential 30.6.2.5.1 Receiving Address Packets (SCLSM=0) PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... When CTRLA.SCLSM=0, the I2C client stretches the SCL line according to Figure 30-9. When the I2C client is properly configured, it will wait for a Start condition. When a Start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected, and the I2C client will wait for a new Start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register

(INTFLAG.AMATCH) will be set. SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL low, the software has unlimited time to respond. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register

(STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packets collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C host, one of two cases will arise based on transfer direction. Case 1: Address packet accepted Read flag set The STATUS.DIR bit is 1, indicating an I2C host read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C client will wait for a new Start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C client Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations as the command execution is dependent on the STATUS.DIR bit. Writing 1 to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Case 2: Address packet accepted Write flag set The STATUS.DIR bit is cleared, indicating an I2C host write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C client will wait for data to be received. Data, repeated start or stop can be received. If a NACK is sent, the I2C client will wait for a new Start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK. The I2C client command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR. Writing 1 to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. 30.6.2.5.2 Receiving Address Packets (SCLSM=1) When SCLSM=1, the I2C client will stretch the SCL line only after an ACK (see Figure 30-10). When the I2C client is properly configured, it will wait for a Start condition to be detected. When a Start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet will be rejected and the I2C client will wait for a new Start condition. If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register

(CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register

(STATUS.DIR). This bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packets collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C host, INTFLAG.AMATCH can be set to 1 to clear it. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 720 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.6.2.5.3 Receiving and Transmitting Data Packets After the I2C client has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C client will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY Interrupt flag is set. If NACK is received, indicated by STATUS.RXNACK=1, the I2C client must expect a stop or a repeated start to be received. The I2C client must release the data line to allow the I2C host to generate a stop or repeated start. Upon detecting a Stop condition, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C client will return to IDLE state. 30.6.2.5.4 PMBus Group Command When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used, INTFLAG.PREC will be set if the client has been addressed since the last STOP condition. When CTRLB.GCMD=0, a STOP condition without address match will not set INTFLAG.PREC. The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the clients addressed during the group command, they all begin executing the command they received. The following figure shows an example where this client, bearing ADDRESS 1, is addressed after a repeated START condition. There can be multiple clients addressed before and after this client. Eventually, at the end of the group command, a single STOP is generated by the host. At this point a STOP interrupt is asserted. Figure 30-11. PMBus Group Command Example S ADDRESS 0 W A n Bytes A Command/Data AMATCH INTERRUPT DRDY INTERRUPT Command/Data Sr ADDRESS 1

(this client) W S W A n Bytes S W A Command/Data PREC INTERRUPT Sr ADDRESS 2 W A n Bytes A P S W 30.6.3 Additional Features 30.6.3.1 SMBus The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out, host extend time-out, and client extend time-out. This allows for SMBus functionality. These time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to use a 32KHz_LPCLK. The I2C interface also allows for a SMBus compatible SDA hold time. TTIMEOUT: SCL low time of 25..35ms Measured for a single SCL low period. It is enabled by CTRLA.LOWTOUTEN. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 721 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... TLOW:SEXT: Cumulative clock low extend time of 25 ms Measured as the cumulative SCL low extend time by a client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN. TLOW:MEXT: Cumulative clock low extend time of 10 ms Measured as the cumulative SCL low extend time by the host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by CTRLA.MEXTTOEN. 30.6.3.2 Smart Mode The I2C interface has a Smart mode that simplifies application code and minimizes the user interaction needed to adhere to the I2C protocol. The Smart mode accomplishes this by automatically issuing an ACK or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read. 30.6.3.3 4-Wire Mode Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-Wire mode operation. In this mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri-state driver is needed when connecting to an I2C bus. Figure 30-12. I2C Pad Interface SCL_OUT/

SDA_OUT SCL_IN/

SDA_IN PINOUT I2C Driver PINOUT SCL_OUT/

SDA_OUT pad SCL/SDA pad 30.6.3.4 Quick Command Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding Interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the client acknowledges the address. At this point, the software can either issue a Stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR. 30.6.3.5 32-bit Extension For better system bus utilization, 32-bit data receive and transmit can be enabled by writing to the Data 32-bit bit field in the Control C register (CTRLC.DATA32B = 1). When enabled, write and read transaction to/from the DATA register are 32 bit in size. If frames are not multiples of 4 Bytes, the Length Counter (LENGTH.LEN) and Length Enable (LENGTH.LENEN) must be configured before data transfer begins. LENGTH.LEN must be enabled only when CTRLC.DATA32B is enabled. The following figure shows the order of transmit and receive when using 32-bit mode. Bytes are transmitted or received and stored in order from 0 to 3. Figure 30-13. 32-bit Extension Byte Ordering APB Write/Read BYTE3 BYTE2 BYTE1 BYTE0 Bit Position 31 0 32-bit Extension Client Operation The following figure shows a transaction with 32-bit Extension enabled (CTRLC.DATA32B=1). In client operation, the Address Match interrupt in the Interrupt Flag Status and Clear register (INTFLAG.AMATCH) is set after the address is received and available in the DATA register. The Data Ready interrupt (INTFLAG.DRDY) will then be raised for every 4 Bytes transferred. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 722 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Figure 30-14. 32-bit Extension Client Operation CLIENT ADDRESS INTERRUPT S ADDRESS W S W A Byte 0 A Byte 1 A Byte 2 A Byte 3 CLIENT DATA INTERRUPT S W The LENGTH register can be written before the frame begins, or when the AMATCH interrupt is set. If the frame size is not LENGTH.LEN Bytes, the Length Error status bit (STATUS.LENERR) is raised. If LENGTH.LEN is not a multiple of 4 Bytes, the final INTFLAG.DRDY interrupt is raised when the last Byte is received for host reads. For host writes, the last data byte will be automatically NACKed. On address recognition, the internal length counter is reset in preparation for the incoming frame. When SCL clock stretch mode is selected (CTRLA.SCLSM=1) and the transaction is a host write, the selected Acknowledge Action (CTRLB.ACKACT) will only be used to ACK/NACK each 4th byte. All other bytes are ACKed. This allows the user to write CTRLB.ACKACT=1 in the final interrupt, so that the last byte in a 32-bit word will be NACKed. Writing to the LENGTH register while a frame is in progress will produce unpredictable results. If LENGTH.LENEN is not set and a frame is not a multiple of 4 Bytes, the remainder will be lost. 32-bit Extension Host Operation When using the I2C configured as Host, the Address register must be written with the desired address

(ADDR.ADDR), and optionally, the transaction Length and transaction Length Enable bits (ADDR.LEN and ADDR.LENEN) can be written. When ADDR.LENEN is written to '1' along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. Then, the ADDR.LEN bytes are transferred, followed by an automatically generated NACK (for host reads) and a STOP. The INTFLAG.SB or INTFLAG.MB are raised for every 4 Bytes transferred. If the transaction is a host read and ADDR.LEN is not a multiple of 4 Bytes, the final INTFLAG.SB is set when the last byte is received. When SCL clock stretch mode is enabled (CTRLA.SCLSM=1) and the transaction is a host read, the selected Acknowledge Action (CTRLB.ACKACT) will only be used to ACK/NACK each 4th Byte. All other bytes are ACKed. This allows the user to set CTRLB.ACKACT=1 in the final interrupt, so that the last byte in a 32-bit word will be NACKed. If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP will be automatically generated, and the length error (STATUS.LENERR) is raised along with the INTFLAG.ERROR interrupt. 30.6.4 DMA, Interrupts and Events Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing 1 to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing 1 to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request is active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG (Client) or INTFLAG (Host) register from Related Links for details on how to clear interrupt flags. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 723 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Table 30-1. Module Request for SERCOM I2C Client Request DMA Yes

(request cleared when data is written) Yes

(request cleared when data is read) Condition Data needed for transmit (TX) (Client transmit mode) Data received (RX) (Client receive mode) Data Ready (DRDY) Address Match (AMATCH) Stop received (PREC) Error (ERROR) Table 30-2. Module Request for SERCOM I2C Host Condition Data needed for transmit (TX) (Host transmit mode) Data needed for transmit (RX) (Host transmit mode) Request DMA Yes

(request cleared when data is written) Yes

(request cleared when data is read) Interrupt Event NA Yes Yes Yes Yes Interrupt Event NA Host on Bus (MB) Stop received (SB) Error (ERROR) Related Links 30.8.6. INTFLAG 30.10.7. INTFLAG Yes Yes Yes 30.6.4.1 DMA Operation Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1. 30.6.4.1.1 Client DMA When using the I2C client with DMA, an address match will cause the address Interrupt flag

(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA. The I2C client generates the following requests:

Write data received (RX): The request is set when host write data is received. The request is cleared when DATA is read. Read data needed for transmit (TX): The request is set when data is needed for a host read operation. The request is cleared when DATA is written. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 724 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Write data received (RX): If the FIFO is disabled, the request is set when host write data is received. If the FIFO is enabled, the request is set when the RX FIFO threshold is reached (CTRLC.RXTRHOLD). The request is cleared when DATA is read. Read data needed for transmit (TX): If the FIFO is disabled, the request is set when data is needed for a host read operation. If the FIFO is enabled, the request is set when the TX FIFO threshold is reached

(CTRLC.TXTRHOLD). The request is cleared when DATA is written. 30.6.4.1.2 Host DMA When using the I2C host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for host reads) and a STOP. If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C host generates the following requests:

Read data received (RX): The request is set when host read data is received. The request is cleared when DATA is read. Write data needed for transmit (TX): The request is set when data is needed for a host write operation. The request is cleared when DATA is written. Read data received (RX): If the FIFO is disabled, the request is set when host read data is received. If the FIFO is enabled, the request is set when the RX FIFO threshold is reached. The request is cleared when DATA is read. Write data needed for transmit (TX): If the FIFO is disabled, the request is set when data is needed for a host write operation. If the FIFO is enabled, the request is set when the TX FIFO threshold is reached

(CTRLC.TXTRHOLD). The request is cleared when DATA is written. 30.6.4.2 Interrupts The I2C client has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any Sleep mode:

Error (ERROR) Data Ready (DRDY) Address Match (AMATCH) Stop Received (PREC) The I2C host has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device from any Sleep mode:

Error (ERROR) Client on Bus (SB) Host on Bus (MB) Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register

(INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing 1 to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing 1 to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled or the I2C is reset. For details on how to clear Interrupt flags, see INTFLAG register from Related Links. The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 30.8.6. INTFLAG 30.10.7. INTFLAG 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 725 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.6.4.3 Events Not applicable. 30.6.4.4 Sleep Mode Operation I2C Host Operation The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in Standby Sleep mode. Any interrupt can wake-up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any interrupt can wake-up the device. I2C Client Operation Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake-up the device. When CTRLA.RUNSTDBY=0, all receptions will be dropped. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 726 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.7 Register Summary See SERCOM0/SERCOM1/SERCOM2 module in the Product Memory Mapping Overview from Related Links for base address based on the SERCOM instant used. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 MODE[2:0]

ENABLE SWRST 0x00 CTRLA 0x04 CTRLB 0x08 CTRLC 0x0C

... 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A Reserved INTENCLR Reserved INTENSET Reserved INTFLAG Reserved STATUS 0x1C SYNCBUSY 0x20

... 0x21 0x22 Reserved LENGTH 0x24 ADDR 0x28 DATA 0x2C

... 0x33 0x34 Reserved FIFOSPACE 0x36 FIFOPTR 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 RUNSTDBY SEXTTOEN LOWTOUT SCLSM AMODE[1:0]

FIFOCLR[1:0]

PINOUT SPEED[1:0]

AACKEN ACKACT GCMD SMEN CMD[1:0]

SDASETUP[3:0]

DATA32B ERROR ERROR ERROR RXFF TXFE DRDY AMATCH PREC RXFF TXFE DRDY AMATCH PREC RXFF TXFE DRDY AMATCH PREC CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR LENERR SEXTTOUT LENGTH SYSOP ENABLE SWRST LEN[7:0]

ADDR[6:0]

ADDRMASK[6:0]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

LENEN GENCEN ADDR[9:7]

ADDRMASK[9:7]

TXSPACE[4:0]

RXSPACE[4:0]

CPUWRPTR[3:0]

CPURDPTR[3:0]

Related Links 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 727 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8 Register Description - I2C Client Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the Enable-Protected property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 728 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLA 0x00 0x00000000 Bit 31 Access Reset 30 LOWTOUT R/W 0 29 28 26 27 SCLSM R/W 0 Bit 23 22 21 20 19 18 SEXTTOEN Access Reset R/W 0 25 R/W 0 17 SPEED[1:0]

24 R/W 0 16 PINOUT R/W 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 RUNSTDBY Access Reset R/W 0 4 R/W 0 3 MODE[2:0]

R/W 0 2 R/W 0 1 ENABLE R/W 0 0 SWRST R/W 0 Bit 30 LOWTOUTSCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25 ms-35 ms, the client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. This bit is not synchronized. Value 0 1 Description Time-out disabled. Time-out enabled. Bit 27 SCLSMSCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value 0 1 Description SCL stretch according to Figure 30-9 SCL stretch only after ACK bit according to Figure 30-10 Bits 25:24 SPEED[1:0]Transfer Speed These bits define bus speed. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 Description Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz Fast-mode Plus (Fm+) up to 1 MHz Reserved Reserved Bit 23 SEXTTOENClient SCL Low Extend Time-Out This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25 ms from the initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 729 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... This bit is not synchronized. Value 0 1 Description Time-out disabled Time-out enabled Bit 16 PINOUTPin Usage This bit sets the pin usage to either two- or four-wire operation:

This bit is not synchronized. Value 0 1 Description 4-wire operation disabled 4-wire operation enabled Bit 7 RUNSTDBYRun in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value 0 1 Description Disabled All reception is dropped. Wake on address match, if enabled. Bits 4:2 MODE[2:0]Operating Mode These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 ENABLEEnable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled or being disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing 0 to this bit has no effect. Writing 1 to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 730 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.2 Control B Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRLB 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 FIFOCLR[1:0]

Access Reset R/W 0 Bit 15 R/W 0 14 AMODE[1:0]

Access Reset R/W 0 Bit 7 Access Reset R/W 0 6 13 12 11 CMD[1:0]

18 ACKACT R/W 0 10 AACKEN R/W 0 17 W 0 9 GCMD R/W 0 16 W 0 8 SMEN R/W 0 5 4 3 2 1 0 Bits 23:22 FIFOCLR[1:0]FIFO Clear When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0. These bits are not enable-protected. FIFOCLR[1:0]

0x0 0x1 0x2 0x3 Name NONE TXFIFO RXFIFO BOTH Description No action Clear TX FIFO Clear RX FIFO Clear both TX/RX FIFO Bit 18 ACKACTAcknowledge Action This bit defines the client's acknowledge behavior after an address or data byte is received from the host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled

(CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read. ACKACT shall not be updated more than once between each peripheral interrupts request. This bit is not enable-protected. Value 0 1 Description Send ACK Send NACK Bits 17:16 CMD[1:0]Command This bit field triggers the client operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 731 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Table 30-3. Command Description CMD[1:0] DIR Action 0x0 0x1 0x2 0x3

(No action)

(Reserved) X X Used to complete a transaction in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition 1 (Host read) Wait for any start (S/Sr) condition Used in response to an address interrupt (AMATCH) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Used in response to a data interrupt (DRDY) 0 (Host write) Execute acknowledge action succeeded by reception of next byte 1 (Host read) Execute a byte read operation followed by ACK/NACK reception Execute acknowledge action succeeded by client data interrupt Bits 15:14 AMODE[1:0]Address Mode These bits set the addressing mode. Value 0x0 Name MASK Description The client responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK. 0x1 0x2 0x3 2_ADDRS The client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK. RANGE The client responds to the range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK. ADDR.ADDR is the upper limit. Reserved. Bit 10 AACKENAutomatic Acknowledge Enable This bit enables the address to be automatically acknowledged if there is an address match. Value 0 1 Description Automatic acknowledge is disabled. Automatic acknowledge is enabled. Bit 9 GCMDPMBus Group Command This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the bus. Value 0 1 Description Group command is disabled. Group command is enabled. Bit 8 SMENSmart Mode Enable When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read. Value 0 1 Description Smart mode is disabled. Smart mode is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 732 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.3 Control C Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRLC 0x08 0x00000000 Bit 31 30 29 28 27 26 25 Access Reset 24 DATA32B R/W 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 Access Reset Bit 7 6 5 4 Access Reset Bit 24 DATA32BData 32 Bit 3 R/W 0 This bit enables 32-bit data writes and reads to/from the DATA register. Value 0 1 Description Data transaction to/from DATA are 8-bit in size Data transaction to/from DATA are 32-bit in size 8 0 2 1 SDASETUP[3:0]

R/W 0 R/W 0 R/W 0 Bits 3:0 SDASETUP[3:0]SDA Setup Time These bits select the minimum SDA-to-SCL setup time, measured from the release of SDA to the release of SCL:

tSU:DAT = GCLK_SERCOMx APB period PBx_CLK 6 + 16 SDASETUP 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 733 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.4 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x14 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit Access Reset 7 ERROR R/W 0 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 DRDY R/W 0 1 AMATCH R/W 0 0 PREC R/W 0 Bit 7 ERRORError Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 4 RXFFRX FIFO Full Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the RX FIFO Full bit, which disables the RX FIFO Full interrupt. Value 0 1 Description The RX FIFO Full interrupt is disabled. The RX FIFO Full interrupt is enabled. Bit 3 TXFETX FIFO Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the TX FIFO Empty bit, which disables the TX FIFO Empty interrupt. Value 0 1 Description The TX FIFO Empty interrupt is disabled. The TX FIFO Empty interrupt is enabled. Bit 2 DRDYData Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt. Value 0 1 Description The Data Ready interrupt is disabled. The Data Ready interrupt is enabled. Bit 1 AMATCHAddress Match Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. Value 0 1 Description The Address Match interrupt is disabled. The Address Match interrupt is enabled. Bit 0 PRECStop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt. Value 0 1 Description The Stop Received interrupt is disabled. The Stop Received interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 734 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.5 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x16 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit Access Reset 7 ERROR R/W 0 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 DRDY R/W 0 1 AMATCH R/W 0 0 PREC R/W 0 Bit 7 ERRORError Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 4 RXFFRX FIFO Full Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the RX FIFO Full bit, which enables the RX FIFO Full interrupt. Value 0 1 Description The RX FIFO Full interrupt is disabled. The RX FIFO Full interrupt is enabled. Bit 3 TXFETX FIFO Empty Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt. Value 0 1 Description The TX FIFO Empty interrupt is disabled. The TX FIFO Empty interrupt is enabled. Bit 2 DRDYData Ready Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Data Ready Interrupt Enable bit, which enables the Data Ready interrupt. Value 0 1 Description The Data Ready interrupt is disabled. The Data Ready interrupt is enabled. Bit 1 AMATCHAddress Match Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. Value 0 1 Description The Address Match interrupt is disabled. The Address Match interrupt is enabled. Bit 0 PRECStop Received Interrupt Enable Writing 0 to this bit has no effect. Writing 1 to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt. Value 0 1 Description The Stop Received interrupt is disabled. The Stop Received interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 735 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.6 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x18 0x00

Bit Access Reset 7 ERROR R/W 0 Bit 7 ERRORError 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 DRDY R/W 0 1 AMATCH R/W 0 0 PREC R/W 0 This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are LENERR, SEXTTOUT, LOWTOUT, COLL and BUSERR. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the flag. Bit 4 RXFFRX FIFO Full This flag is set when RX FIFO Threshold locations are fulfilled. The flag is cleared when the RX FIFO is empty. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the RX FIFO Full interrupt flag. Bit 3 TXFETX FIFO Empty This flag is set when TX FIFO Threshold locations are available. The flag is cleared when the TX FIFO is full. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the TX FIFO Empty interrupt flag. Bit 2 DRDYData Ready This flag is set when a I2C client byte transmission is successfully completed. The flag is cleared by hardware when either:

Writing to the DATA register. Reading the DATA register with Smart mode enabled. Writing a valid command to the CMD register. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Data Ready Interrupt flag. Bit 1 AMATCHAddress Match This flag is set when the I2C client address match logic detects that a valid address has been received. The flag is cleared by hardware when CTRL.CMD is written. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Address Match Interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. Bit 0 PRECStop Received This flag is set when a Stop condition is detected for a transaction being processed. A Stop condition detected between a bus host and another client will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1). This flag is cleared by hardware after a command is issued on the next address match. Writing 0 to this bit has no effect. Writing 1 to this bit will clear the Stop Received Interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 736 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.7 Status Name:

Offset:

Reset:

Property:

STATUS 0x1A 0x0000

Bit 15 14 13 12 Access Reset Bit 7 CLKHOLD Access Reset R 0 6 LOWTOUT R/W 0 5 4 SR R 0 Bit 11 LENERRTransaction Length Error 11 LENERR R/W 0 3 DIR R 0 10 8 9 SEXTTOUT R/W 0 2 RXNACK R 0 1 COLL R/W 0 0 BUSERR R/W 0 This bit is set when the length counter is enabled (LENGTH.LENEN) and a STOP or repeated START is received before or after the length in LENGTH.LEN is reached. This bit is cleared automatically when responding to a new start condition with ACK or NACK (CTRLB.CMD=0x3) or when INTFLAG.AMATCH is cleared. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Bit 11 LENERRTransaction Length Error This bit is set when the length counter is enabled (LENGTH.LENEN) and a STOP or repeated START is received before or after the length in LENGTH.LEN is reached. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Value 0 1 Description No length error has occurred. Length error has occurred. Bit 9 SEXTTOUTClient SCL Low Extend Time-Out This bit is set if a client SCL low extend time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Value 0 1 Description No SCL low extend time-out has occurred. SCL low extend time-out has occurred. Bit 7 CLKHOLDClock Hold The client Clock Hold bit (STATUS.CLKHOLD) is set when the client is holding the SCL line low, stretching the I2C clock. Software must consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. This bit is automatically cleared when the corresponding interrupt is also cleared. Bit 6 LOWTOUTSCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 737 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Value 0 1 Description No SCL low time-out has occurred. SCL low time-out has occurred. Bit 4 SRRepeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. This flag is only valid while the INTFLAG.AMATCH flag is one. Value 0 1 Description Start condition on last address match Repeated start condition on last address match Bit 3 DIRRead / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a host . Value 0 1 Description Host write operation is in progress. Host read operation is in progress. Bit 2 RXNACKReceived Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. Value 0 1 Description Host responded with ACK. Host responded with NACK. Bit 1 COLLTransmit Collision If set, the I2C client was not able to transmit a high data or NACK bit, the I2C client will immediately release the SDA and SCL lines and wait for the next packet addressed to it. This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations indicates that there has been a protocol violation, and must be treated as a bus error. Note:This status will not trigger any interrupt, and must be checked by software to verify that the data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Value 0 1 Description No collision detected on last data byte sent. Collision detected on last data byte sent. Bit 0 BUSERRBus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD) or INTFLAG.AMATCH is cleared. Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the status. Value 0 1 Description No bus error detected. Bus error detected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 738 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.8 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x1C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 Access Reset 3 4 LENGTH R 0 2 SYSOP R 0 1 ENABLE R 0 0 SWRST R 0 Bit 4 LENGTHLENGTH Synchronization Busy Writing LENGTH requires synchronization. When written, this bit will be set until synchronization is complete. If LENGTH is written while SYNCBUSY.LENGTH is asserted, an APB error will be generated. Note:In client mode, the clock is only running during data transfer, so SYNCBUSY.LENGTH will remain asserted until the next data transfer begins. Value 0 1 Description LENGTH synchronization is not busy. LENGTH synchronization is busy. Bit 2 SYSOPSystem Operation Synchronization Busy Writing CTRLB.FIFOCLR when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. Value 0 1 Description System operation synchronization is not busy. System operation synchronization is busy. Bit 1 ENABLESERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.ENABLE = 1 until synchronization is complete. Value 0 1 Description Enable synchronization is not busy. Enable synchronization is busy. Bit 0 SWRSTSoftware Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by SYNCBUSY.SWRST = 1 until synchronization is complete. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 739 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 740 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.9 Length Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized LENGTH 0x22 0x0000 Bit 15 14 13 12 11 10 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 LEN[7:0]

3 R/W 0 2 R/W 0 9 1 R/W 0 8 LENEN R/W 0 0 R/W 0 Bit 8 LENENData Length Enable In 32-bit Extension mode (CTRLC.DATA32B=1), this bit field enables the length counter. Value 0 1 Description Length counter is disabled. Length counter is enabled. Bits 7:0 LEN[7:0]Data Length In 32-bit Extension mode (CTRLC.DATA32B=1) with Data Length counting enabled (LENGTH.LENEN), this bit field configures the data length from 0 to 255 Bytes after which the flag INTFLAG.DRDY is raised. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 741 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.10 Address Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected ADDR 0x24 0x00000000 Bit 31 30 29 28 27 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset Bit 7 Access Reset R/W 0 22 R/W 0 14 6 R/W 0 21 R/W 0 13 5 R/W 0 20 ADDRMASK[6:0]

R/W 0 12 4 ADDR[6:0]

R/W 0 19 R/W 0 11 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 ADDRMASK[9:7]

R/W 0 17 R/W 0 9 ADDR[9:7]

R/W 0 1 R/W 0 24 R/W 0 16 8 R/W 0 0 GENCEN R/W 0 Bits 26:17 ADDRMASK[9:0]Address Mask These bits act as a second address match register, an address mask register or the lower limit of an address range, depending on the CTRLB.AMODE setting. Bits 10:1 ADDR[9:0]Address These bits contain the I2C client address used by the client address match logic to determine if a host has addressed the client. When using 7-bit addressing, the client address is represented by ADDR[6:0]. When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction. Bit 0 GENCENGeneral Call Address Enable A general call address is an address consisting of all-zeroes, including the direction bit (host write). Value 0 1 Description General call address recognition disabled. General call address recognition enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 742 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.11 Data Name:

Offset:

Reset:

Property: Read/Write DATA 0x28 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DATA[31:0]Data The client data register I/O location (DATA.DATA) provides access to the host transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the client

(STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been received. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). When CTRLC.DATA32B=1, read and write transactions from/to the DATA register are 32 bit in size. Otherwise, reads and writes are 8 bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 743 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.12 FIFO Space Name:

Offset:

Reset:

Property:

FIFOSPACE 0x34 0x0000

This register allows the user to identify the number of bytes present in each TX and RX FIFO. Bit 15 14 13 Access Reset Bit 7 6 5 Access Reset 12 R 0 4 R 0 11 R 0 3 R 0 10 RXSPACE[4:0]

R 0 2 TXSPACE[4:0]

R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 12:8 RXSPACE[4:0]RX FIFO Filled Space These bits return the number filled locations in the RX FIFO (bytes or words, depending on CTRLC.DATA32B setting). Bits 4:0 TXSPACE[4:0]TX FIFO Empty Space These bits return the number of available locations in the TX FIFO (bytes or words, depending on CTRLC.DATA32B setting). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 744 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.8.13 FIFO CPU Pointers Name:

Offset:

Reset:

Property:

FIFOPTR 0x36 0x0000

This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 Access Reset Bit 7 6 5 4 Access Reset 11 R/W 0 3 R/W 0 9 10 CPURDPTR[3:0]

R/W 0 R/W 0 1 2 CPUWRPTR[3:0]

R/W 0 R/W 0 8 R/W 0 0 R/W 0 Bits 11:8 CPURDPTR[3:0]RX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. Reading DATA register, will return RXFIFO[CPURDPTR] location value. Bits 3:0 CPUWRPTR[3:0]TX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. When writting to DATA register, the DATA will be written to TXFIFO[CPUWRPTR] location. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 745 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.9 Register Summary See SERCOM0/SERCOM1/SERCOM2 module in the Product Memory Mapping Overview from Related Links for base address based on the SERCOM instant used. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x04 CTRLB 0x08 CTRLC 0x0C BAUD 0x10

... 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Reserved INTENCLR Reserved INTENSET Reserved INTFLAG Reserved 0x1A STATUS 0x1C SYNCBUSY 0x20

... 0x23 Reserved 0x24 ADDR 0x28 DATA 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 7:0 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 RUNSTDBY MODE[2:0]

ENABLE SWRST SEXTTOEN MEXTTOEN LOWTOUT INACTOUT[1:0]

SCLSM PINOUT SPEED[1:0]

FIFOCLR[1:0]

QCEN SMEN ACKACT CMD[1:0]

BAUD[7:0]

BAUDLOW[7:0]

RXFF TXFE RXFF TXFE RXFF TXFE ERROR ERROR ERROR CLKHOLD LOWTOUT BUSSTATE[1:0]

DATA32B SB SB SB MB MB MB RXNACK ARBLOST BUSERR LENERR SEXTTOUT MEXTTOUT SYSOP ENABLE SWRST TENBITEN LENEN ADDR[10:8]

ADDR[7:0]

LEN[7:0]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

0x2C

... 0x2F 0x30 0x31

... 0x33 0x34 Reserved DBGCTRL 7:0 Reserved FIFOSPACE 7:0 15:8 7:0 15:8 0x36 FIFOPTR DBGSTOP TXSPACE[4:0]

RXSPACE[4:0]

CPUWRPTR[3:0]

CPURDPTR[3:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 746 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Related Links 7. Product Memory Mapping Overview 30.10 Register Description I2C Host Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the Enable-Protected property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 747 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLA 0x00 0x00000000 Bit 31 Access Reset 30 LOWTOUT R/W 0 Bit 23 SEXTTOEN Access Reset R/W 0 22 MEXTTOEN R/W 0 29 28 INACTOUT[1:0]

R/W 0 21 R/W 0 20 26 27 SCLSM R/W 0 19 18 25 R/W 0 17 SPEED[1:0]

24 R/W 0 16 PINOUT R/W 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 RUNSTDBY Access Reset R/W 0 4 R/W 0 3 MODE[2:0]

R/W 0 2 R/W 0 1 ENABLE R/W 0 0 SWRST R/W 0 Bit 30 LOWTOUTSCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the host will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted. INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set. This bit is not synchronized. Value 0 1 Description Time-out disabled. Time-out enabled. Bits 29:28 INACTOUT[1:0]Inactive Time-Out If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arise when either an I2C host or client is holding the SCL low. Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. Name Value DIS 0x0 55US 0x1 105US 0x2 205US 0x3 Description Disabled 5-6 SCL cycle time-out (50-60s) 10-11 SCL cycle time-out (100-110s) 20-21 SCL cycle time-out (200-210s) Bit 27 SCLSMSCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value 0 1 Description SCL stretch according to Figure 30-5 SCL stretch only after ACK bit, Figure 30-6 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 748 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Bits 25:24 SPEED[1:0]Transfer Speed These bits define bus speed. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 Description Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz Fast-mode Plus (Fm+) up to 1 MHz Reserved Reserved Bit 23 SEXTTOENClient SCL Low Extend Time-Out This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value 0 1 Description Time-out disabled Time-out enabled Bit 22 MEXTTOENHost SCL Low Extend Time-Out This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set. This bit is not synchronized. Value 0 1 Description Time-out disabled Time-out enabled Bit 16 PINOUTPin Usage This bit set the pin usage to either two- or four-wire operation:

This bit is not synchronized. Value 0 1 Description 4-wire operation disabled. 4-wire operation enabled. Bit 7 RUNSTDBYRun in Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Value 0 1 Description GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode. GCLK_SERCOMx_CORE is enabled in all sleep modes. Bits 4:2 MODE[2:0]Operating Mode These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM. These bits are not synchronized. Bit 1 ENABLEEnable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled or being disabled. The peripheral is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 749 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Bit 0 SWRSTSoftware Reset Writing 0 to this bit has no effect. Writing 1 to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 750 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.2 Control B Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized CTRLB 0x04 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 FIFOCLR[1:0]

Access Reset R/W 0 Bit 15 Access Reset R/W 0 14 13 12 11 10 18 ACKACT R/W 0 17 W 0 9 QCEN R/W 0 CMD[1:0]

16 W 0 8 SMEN R/W 0 Bit 7 6 5 4 3 2 1 0 Access Reset Bits 23:22 FIFOCLR[1:0]FIFO Clear When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0. These bits are not enable-protected. FIFOCLR[1:0]

0x0 0x1 0x2 0x3 Name NONE TXFIFO RXFIFO BOTH Description No action Clear TX FIFO Clear RX FIFO Clear both TX/RX FIFO Bit 18 ACKACTAcknowledge Action This bit defines the I2C Host's acknowledge behavior after a data byte is received from the I2C Client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled

(CTRLB.SMEN is written to one), when DATA.DATA is read. This bit is not enable-protected. This bit is not write-synchronized. Value 0 1 Description Send ACK. Send NACK. Bits 17:16 CMD[1:0]Command Writing these bits triggers a Host operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt flag (INTFLAG.MB) is '1'. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 751 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address. Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP). Table 30-4. Command Description CMD[1:0]

Direction Action 0x0 0x1 0x2 0x3 X X 0 (Write) 1 (Read) X

(No action) Execute acknowledge action succeeded by repeated Start No operation Execute acknowledge action succeeded by a byte read operation Execute acknowledge action succeeded by issuing a Stop condition These bits are not enable-protected. Bit 9 QCENQuick Command Enable This bit is not write-synchronized. Value 0 1 Description Quick Command is disabled. Quick Command is enabled. Bit 8 SMENSmart Mode Enable When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read. This bit is not write-synchronized. Value 0 1 Description Smart mode is disabled. Smart mode is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 752 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.3 Control C Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected CTRLC 0x08 0x00000000 Bit 31 30 29 28 27 26 25 Access Reset 24 DATA32B R/W 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 24 DATA32BData 32 Bit This bit enables 32-bit data writes and reads to/from the DATA register. Value 0 1 Description Data transactions to/from DATA are 8-bit in size Data transactions to/from DATA are 32-bit in size 9 1 8 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 753 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.4 Baud Rate Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected BAUD 0x0C 0x0000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 BAUDLOW[7:0]

R/W 0 4 R/W 0 BAUD[7:0]

R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:8 BAUDLOW[7:0]Host Baud Rate Low If this bit field is non-zero, the SCL low time will be described by the value written. For more details on how to calculate the frequency, see Clock Generation Baud-Rate Generator from Related Links. Bits 7:0 BAUD[7:0]Host Baud Rate This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. For more details on how to calculate the frequency, see Clock Generation Baud-Rate Generator from Related Links. Related Links 27.6.2.3. Clock Generation Baud-Rate Generator 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 754 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.5 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x14 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit Access Reset 7 ERROR R/W 0 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 1 SB R/W 0 0 MB R/W 0 Bit 7 ERRORError Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 4 RXFFRX FIFO Full Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the RX FIFO Full bit, which disables the RX FIFO Full interrupt. Value 0 1 Description The RX FIFO Full interrupt is disabled. The RX FIFO Full interrupt is enabled. Bit 3 TXFETX FIFO Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the TX FIFO Empty bit, which disables the TX FIFO Empty interrupt. Value 0 1 Description The TX FIFO Empty interrupt is disabled. The TX FIFO Empty interrupt is enabled. Bit 1 SBClient on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt. Value 0 1 Description The Client on Bus interrupt is disabled. The Client on Bus interrupt is enabled. Bit 0 MBHost on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt. Value 0 1 Description The Host on Bus interrupt is disabled. The Host on Bus interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 755 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.6 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x16 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit Access Reset 7 ERROR R/W 0 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 1 SB R/W 0 0 MB R/W 0 Bit 7 ERRORError Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description Error interrupt is disabled. Error interrupt is enabled. Bit 4 RXFFRX FIFO Full Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the RX FIFO Full bit, which enables the RX FIFO Full interrupt. Value 0 1 Description The RX FIFO Full interrupt is disabled. The RX FIFO Full interrupt is enabled. Bit 3 TXFETX FIFO Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt. Value 0 1 Description The TX FIFO Empty interrupt is disabled. The TX FIFO Empty interrupt is enabled. Bit 1 SBClient on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt. Value 0 1 Description The Client on Bus interrupt is disabled. The Client on Bus interrupt is enabled. Bit 0 MBHost on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt. Value 0 1 Description The Host on Bus interrupt is disabled. The Host on Bus interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 756 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.7 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x18 0x00

Bit Access Reset 7 ERROR R/W 0 Bit 7 ERRORError 6 5 4 RXFF R/W 0 3 TXFE R/W 0 2 1 SB R/W 0 0 MB R/W 0 This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 4 RXFFRX FIFO Full This flag is set when RX FIFO Threshold locations are fulfilled. The flag is cleared when the RX FIFO is empty. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the RX FIFO Full interrupt flag. Bit 3 TXFETX FIFO Empty This flag is set when TX FIFO Threshold locations are available. The flag is cleared when the TX FIFO is full. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the TX FIFO Empty interrupt flag. Bit 1 SBClient on Bus The Client on Bus flag (SB) is set when a byte is successfully received in Host Read mode, for example, no arbitration lost or bus error occurred during the operation. When this flag is set, the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions:

Writing to ADDR.ADDR Writing to DATA.DATA Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN) Writing a valid command to CTRLB.CMD Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. Bit 0 MBHost on Bus This flag is set when a byte is transmitted in Host Write mode. The flag is set regardless of the occurrence of a bus error or an Arbitration Lost condition. MB is also set when arbitration is lost during sending of NACK in Host Read mode, or when issuing a Start condition if the bus state is unknown. When this flag is set and arbitration is not lost, the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared on one of the following actions:

Writing to ADDR.ADDR Writing to DATA.DATA Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN) Writing a valid command to CTRLB.CMD 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 757 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing '0' to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 758 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.8 Status STATUS Name:

0x1A Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 Access Reset Bit 7 CLKHOLD Access Reset R 0 6 LOWTOUT R/W 0 5 4 BUSSTATE[1:0]

R/W 0 R/W 0 3 Bit 10 LENERRTransaction Length Error 10 LENERR R/W 0 2 RXNACK R 0 9 SEXTTOUT R/W 0 1 ARBLOST R/W 0 8 MEXTTOUT R/W 0 0 BUSERR R/W 0 This bit is set when automatic length is used for a DMA and/or 32-bit transaction and the client sends a NACK before ADDR.LEN bytes have been written by the host. Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 9 SEXTTOUTClient SCL Low Extend Time-Out This bit is set if a client SCL low extend time-out occurs. This bit is automatically cleared when writing to the ADDR register. Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT flag to be cleared by this method. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 8 MEXTTOUTHost SCL Low Extend Time-Out This bit is set if a Host SCL low time-out occurs. Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bit 7 CLKHOLDClock Hold This bit is set when the host is holding the SCL line low, stretching the I2C clock. Software should consider this bit when INTFLAG.SB or INTFLAG.MB is set. This bit is cleared when the corresponding Interrupt flag is cleared and the next operation is given. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Bit 6 LOWTOUTSCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect. This bit is not write-synchronized. Bits 5:4 BUSSTATE[1:0]Bus State These bits indicate the current I2C Bus state. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 759 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus state cannot be forced into any other state. Writing BUSSTATE to idle will set SYNCBUSY.SYSOP. Value 0x0 Name UNKNOWN The Bus state is unknown to the I2C host and will wait for a Stop condition to be detected Description 0x1 0x2 0x3 IDLE OWNER BUSY or wait to be forced into an Idle state by software The Bus state is waiting for a transaction to be initialized The I2C host is the current owner of the bus Some other I2C host owns the bus Bit 2 RXNACKReceived Not Acknowledge This bit indicates whether the last address or data packet sent was acknowledged or not. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Value 0 1 Description Client responded with ACK. Client responded with NACK. Bit 1 ARBLOSTArbitration Lost This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a Start or Repeated Start condition on the bus. The Host on Bus Interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set. Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. Bit 0 BUSERRBus Error This bit indicates that an illegal Bus condition has occurred on the bus, regardless of bus ownership. An illegal Bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A Start condition directly followed by a Stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR. If the I2C host is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in addition to BUSERR. Writing the ADDR.ADDR register will automatically clear the BUSERR flag. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it. This bit is not write-synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 760 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.9 Synchronization Busy Name:

Offset:

Reset:

SYNCBUSY 0x1C 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 Access Reset 2 SYSOP R 0 1 ENABLE R 0 0 SWRST R 0 Bit 2 SYSOPSystem Operation Synchronization Busy Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR or DATA when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR or DATA when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. Value 0 1 Description System operation synchronization is not busy. System operation synchronization is busy. Bit 1 ENABLESERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Value 0 1 Description Enable synchronization is not busy. Enable synchronization is busy. Bit 0 SWRSTSoftware Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 761 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.10 Address ADDR Name:

0x24 Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 TENBITEN Access Reset R/W 0 Bit 7 Access Reset R/W 0 22 R/W 0 14 6 R/W 0 21 R/W 0 13 LENEN R/W 0 5 R/W 0 LEN[7:0]

ADDR[7:0]

20 R/W 0 12 4 R/W 0 19 R/W 0 11 3 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 R/W 0 9 ADDR[10:8]

R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 23:16 LEN[7:0]Transaction Length These bits define the transaction length of a DMA and/or 32-bit transaction from 0 to 255 bytes. The Transfer Length Enable (LENEN) bit must be written to '1' in order to use DMA. Bit 15 TENBITENTen Bit Addressing Enable This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission. Value 0 1 Description 10-bit addressing disabled. 10-bit addressing enabled. Bit 13 LENENTransfer Length Enable Value 0 1 Description Automatic transfer length disabled. Automatic transfer length enabled. Bits 10:0 ADDR[10:0]Address When ADDR is written, the consecutive operation will depend on the bus state:

UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. BUSY: The I2C host will await further operation until the bus becomes IDLE. IDLE: The I2C host will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set. OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set. STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written. The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the host logic to perform any bus protocol related operations. The I2C host control logic uses bit 0 of ADDR as the bus protocols read/write flag (R/W); 0 for write and 1 for read. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 762 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.11 Data Name:

Offset:

Reset:

Property: Read/Write DATA 0x28 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DATA[31:24]

R/W 0 20 R/W 0 19 DATA[23:16]

R/W 0 12 R/W 0 4 R/W 0 DATA[15:8]

DATA[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 DATA[31:0]Data The host data register I/O location (DATA) provides access to the host transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the host

(STATUS.CLKHOLD is set). An exception is reading the last data byte after the stop condition has been sent. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). When CTRLC.DATA32B=1, read and write transactions from/to the DATA register are 32 bit in size. Otherwise, reads and writes are 8 bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 763 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.12 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x30 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGSTOPDebug Stop Mode DBGSTOP R/W 0 This bit controls functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger. The baud-rate generator is halted when the CPU is halted by an external debugger. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 764 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.13 FIFO Space Name:

Offset:

Reset:

Property:

FIFOSPACE 0x34 0x0000

This register allows the user to identify the number of bytes present in each TX and RX FIFO. Bit 15 14 13 Access Reset Bit 7 6 5 Access Reset 12 R 0 4 R 0 11 R 0 3 R 0 10 RXSPACE[4:0]

R 0 2 TXSPACE[4:0]

R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 12:8 RXSPACE[4:0]RX FIFO Filled Space These bits return the number filled locations in the RX FIFO (bytes or words, depending on CTRLC.DATA32B setting). Bits 4:0 TXSPACE[4:0]TX FIFO Empty Space These bits return the number of available locations in the TX FIFO (bytes or words, depending on CTRLC.DATA32B setting). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 765 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family SERCOM Inter-Integrated Circuit (SERCOM I2C... 30.10.14 FIFO CPU Pointers Name:

Offset:

Reset:

Property:

FIFOPTR 0x36 0x0000

This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 Access Reset Bit 7 6 5 4 Access Reset 11 R/W 0 3 R/W 0 9 10 CPURDPTR[3:0]

R/W 0 R/W 0 1 2 CPUWRPTR[3:0]

R/W 0 R/W 0 8 R/W 0 0 R/W 0 Bits 11:8 CPURDPTR[3:0]RX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. Reading DATA register, will return RXFIFO[CPURDPTR] location value. Bits 3:0 CPUWRPTR[3:0]TX FIFO Filled Space These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. When writting to DATA register, the DATA will be written to TXFIFO[CPUWRPTR] location. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 766 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31. Quad Serial Peripheral Interface (QSPI) 31.1 Overview The Quad SPI Interface (QSPI) circuit is a synchronous serial data link that provides communication with external devices in Host mode. The QSPI can be used in SPI mode to interface serial peripherals, such as ADCs, DACs, LCD controllers and sensors, or in Serial Memory Mode to interface serial Flash memories. The QSPI allows the system to execute code directly from a serial Flash memory (XIP) without code shadowing to SRAM. The serial Flash memory mapping is seen in the system as other memories (ROM, SRAM, embedded Flash memories, and so on.). XIP mode is not available for a secured or code protected device for security reasons. This is achieved by blocking off AHB accesses (only instruction) on the CPU side from QSPI. QSPI returns error on the transactions where CPU is requesting for instructions from QSPI connected external memories. With the support of the quad-SPI protocol, the QSPI allows the system to use high performance serial Flash memories which are small and inexpensive, in place of larger and more expensive parallel Flash memories. 31.2 Features Host SPI Interface:

Programmable clock phase and clock polarity Programmable transfer delays between consecutive transfers, between clock and data, between deactivation and activation of chip select (CS) SPI Mode:

To use serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers, and sensors 8-bit, 16-bit, or 32-bit programmable data length Serial Memory Mode:

To use serial Flash memories operating in single-bit SPI, Dual SPI and Quad SPI Supports execute in place (XIP). The system can execute code directly from a Serial Flash memory Flexible instruction register, to be compatible with all serial Flash memories 32-bit Address mode (default is 24-bit address) to support serial Flash memories larger than 128 Mbit Continuous Read mode Scrambling/Unscrambling On-the-Fly Double data rate support Connection to DMA Channel Capabilities Optimizes Data Transfers One channel for the receiver and one channel for the transmitter Register Write Protection 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 767 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.3 Block Diagram Figure 31-1. QSPI Block Diagram Clock Source Generator

(CLK_GEN) PB2_CLK

(CLK_QSPI_APB) SYS_CLK

(CLK_QSPI_AHB) Peripheral Bridge APB QSPI CPU DMA AHB MATRIX SCK MOSI/DATA0 MISO/DATA1 DATA2 DATA3 CS 31.4 Signal Description Table 31-1. Quad-SPI Signals Signal SCK CS Description Serial Clock Chip Select Interrupt Control QSPI Interrupt Type Output Output MOSI(DATA0) Data Output (Data Input Output 0) Output (Input/Output) MISO(DATA1) Data Input (Data Input Output 1) Input (Input/Output) DATA2 DATA3 Notes:

Data Input Output 2 Data Input Output 3 Input/Output Input/Output 1. MOSI and MISO are used for single-bit SPI operation. 2. DATA0-DATA1 are used for Dual SPI operation. 3. DATA0-DATA3 are used for Quad SPI operation. See I/O Ports and Peripheral Pin Select (PPS) from Related Links for details on the pin mapping for the QSPI peripheral. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 31.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 768 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.5.1 I/O Lines Using the QSPI I/O lines requires the I/O pins to be configured using the System Configuration registers (See System Configuration and Register Locking (CFG) from Related Links) (QSPI_HSEN of CFGCON1/DEVCFG1 register) for direct or PPS. If QSPI pins are selected through PPS, the PPS registers has to be configured (See I/O Ports and Peripheral Pin Select (PPS) from Related Links). If QSPI_HSEN =1, QSPI uses dedicated pins. If QSPI_HSEN = 0, QSPI uses PPS path, and I/O pins are multiplexed to pins groups defined in PPS section. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 18. System Configuration and Register Locking (CFG) 31.5.2 Power Management The QSPI will continue to operate in any Sleep mode where the selected source clock is running. The QSPI interrupts can be used to wake up the device from sleep modes. See Power Management Unit (PMU) from Related Links for details on the different sleep modes. Related Links 14. Power Management Unit (PMU) 31.5.3 Clocks An AHB clock (CLK_QSPI_AHB) is required to clock the QSPI. In PIC32CX-BZ3, SYS_CLK is the AHB clock and can be configured in the CRU. A FAST clock (CLK_QSPI2X_AHB) is required to clock the QSPI. This clock can be enabled and disabled in the CFGCON1 register, bit 29 (CFGCON1.QSPIDDRM). When using QSPI DDR (Double Data Rate) Mode, the System Clock (SYS_CLK) must be less than or equal to 32 MHz. PB2_CLK is CLK_QSPI_APB clock and can be configured in CRU registers. Figure 31-2. QSPI Clock Organization HS Clock Domain CLK_QSPI2X_AHB CPU Clock Domain CLK_QSPI_AHB CLK_QSPI_APB QSPI Important: The CLK_QSPI2x_AHB must be two times faster to CLK_QSPI_AHB when the QSPI is operated in the DDR mode. In Single Data Rate (SDR), the CLK_QSPI2x_AHB is not used. The CLK_QSPI_APB, CLK_QSPI_AHB, and CLK_QSPI2X_AHB, respectively, are all synchronous, but can be divided by a prescaler. 31.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). Using the QSPI DMA requests requires the DMA Controller to be configured first. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 769 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Note:DMAC write access must be 32-bit aligned. If a single byte is to be written in a 32-bit word, the rest of the word must be filled with 'ones'. 31.5.5 Interrupts The interrupt request lines are connected to the interrupt controller. Using the QSPI interrupts requires the interrupt controller to be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 31.5.6 Events Not applicable. 31.5.7 Debug Operation When the CPU is halted in debug mode the QSPI continues normal operation. If the QSPI is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 31.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers:

Control A (CTRLA) register Transmit Data (TXDATA) register Scrambling Key (SCRAMBKEY) register Interrupt Flag Status and Clear (INTFLAG) register PAC write-protection is denoted by the PAC Write-Protection property in the register description. Write-protection does not apply to accesses through an external debugger. 31.6 Functional Description 31.6.1 Principle of Operation The QSPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device and peripheral or serial memory devices. The QSPI operates as a host. It initiates and controls all data transactions. When transmitting, the TXDATA register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the RXDATA register, and the receiver is ready for a new character. 31.6.2 Basic Operation 31.6.2.1 Initialization After Power-On Reset, this peripheral is enabled . 31.6.2.2 Enabling, Disabling, and Resetting The peripheral is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is disabled by writing a '0' to CTRLA.ENABLE. The peripheral is reset by writing a '1' to the Software Reset bit (CTRLA.SWRST). 31.6.3 Transfer Data Rate By default, the QSPI module is enabled in single data rate mode. In this operating mode, the CLK_QSPI2X_AHB clock is not used and must be disabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 770 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... The dual data rate operating mode is enabled by writing a 1 to the Double Data Rate Enable bit in the CFGCON1 register (CFGCON1.QSPIDDRM). This operating mode requires the CLK_QSPI2X_AHB clock and must be enabled before writing the DDREN bit. 31.6.4 Serial Clock Baud Rate The QSPI Baud rate clock is generated by dividing the module clock (CLK_QSPI_AHB) by a value between 1 and 255. This allows a maximum operating baud rate at up to Host Clock and a minimum operating baud rate of CLK_QSPI_AHB divided by 255. At reset, BAUD = 0 and the user has to program a valid value before performing the first transfer. 31.6.5 Serial Clock Phase and Polarity Four combinations of polarity and phase are available for data transfers. Writing the Clock Polarity bit in the QSPI Baud register (BAUD.CPOL) selects the polarity. The Clock Phase bit in the BAUD register programs the clock phase

(BAUD.CPHA). These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations. Note: The polarity/phase combinations are incompatible. Thus, the interfaced client must use the same parameter values to communicate. Table 31-2. SPI Transfer Mode Clock Mode BAUD.CPOL BAUD.CPHA Shift SCK Edge Capture SCK Edge SCK Inactive Level 0 1 2 3 0 0 1 1 0 1 0 1 Falling Rising Rising Falling Rising Falling Falling Rising Low Low High High 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 771 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Figure 31-3. QSPI Transfer Modes (BAUD.CPHA = 0, 8-bit transfer) Figure 31-4. SCK Cycle (for reference) 1 2 3 4 5 6 7 8 SCK

(CPOL = 0) SCK

(CPOL = 1) MOSI

(from host) MISO

(from client) CS

(to client) MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB

QSPI Transfer Modes (BAUD.CPHA = 1, 8-bit transfer) SCK Cycle (for reference) 1 2 3 4 5 6 7 8

* Not defined, but normally MSB of previous character received SCK

(CPOL = 0) MOSI

(from host) MSB MISO

(from client)

MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB CS

(to client) 31.6.6 Transfer Delays

* Not defined, but normally LSB of previous character received The QSPI supports several consecutive transfers while the chip select is active. Three delays can be programmed to modify the transfer waveforms:

The delay between the inactivation and the activation of CS is programmed by writing the Minimum Inactive CS Delay bit field in the Control B register (CTRLB.DLYCS), allowing to tune the minimum time of CS at high level. The delay between consecutive transfers is programmed by writing the Delay Between Consecutive Transfers bit field in the Control B register (CTRLB.DLYBCT), allowing to insert a delay between two consecutive transfers. In Serial Memory mode, this delay is not programmable and DLYBCT settings are ignored. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 772 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... The delay before SCK is programmed by writing the Delay Before SCK bit field in the BAUD register

(BAUD.DLYBS), allowing to delay the start of SPCK after the chip select has been asserted. These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 31-5. Programmable Delay CS SCK DLYCS DLYBS DLYBCT DLYBCT 31.6.7 QSPI SPI Mode In this mode, the QSPI acts as a regular SPI Host. To activate this mode, the MODE bit in the Control B register must be cleared (CTRLB.MODE=0). 31.6.7.1 SPI Mode Operations The QSPI in standard SPI mode operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the client connected to the SPI bus. The QSPI drives the chip select line to the client (CS) and the serial clock signal (SCK). The QSPI features a single internal shift register and two holding registers: the Transmit Data Register (TXDATA) and the Receive Data Register (RXDATA). The holding registers maintain the data flow at a constant rate. After enabling the QSPI, a data transfer begins when the processor writes to the TXDATA. The written data is immediately transferred into the internal shift register and transfer on the SPI bus starts. While the data in the internal shift register is shifted on the MOSI line, the MISO line is sampled and shifted into the internal shift register. Receiving data cannot occur without transmitting data. If new data is written in TXDATA during the transfer, it stays in TXDATA until the current transfer is completed. Then, the received data is transferred from the internal shift register to the RXDATA, the data in TXDATA is loaded into the internal shift register, and a new transfer starts. The transfer of data written in TXDATA in the internal shift register is indicated by the Transmit Data Register Empty

(DRE) bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE). When new data is written in TXDATA, this bit is cleared. The DRE bit is used to trigger the Transmit DMA channel. The end of transfer is indicated by the Transmission Complete flag (INTFLAG.TXC). If the transfer delay for the last transfer was configured to be greater than 0 (CTRLB.DLYBCT), TXC is set after the completion of the delay. The module clock (CLK_QSPI_AHB) can be switched off at this time. Ongoing transfer of received data from the internal shift register into RXDATA is indicated by the Receive Data Register Full flag (INTFLAG.RXC). When the received data is read, the RXC bit is cleared. If the RXDATA has not been read before new data is received, the Overrun Error flag in INTFLAG register

(INTFLAG.ERROR) is set. As long as this flag is set, data is loaded in RXDATA. The SPI Mode Block Diagram shows a flow chart describing how transfers are handled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 773 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.6.7.2 SPI Mode Block Diagram Figure 31-6. SPI Mode Block Diagram BAUD BAUD Peripheral Clock Baud Rate Generator SCK Serial Clock BAUD RXDATA DATA RXC ERROR Shift Register MSB MOSI MISO CPHA CPOL LSB CTRLB DATALEN TXDATA DATA DRE Chip Select Controller CS CTRLB CSMODE 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 774 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.6.7.3 SPI Mode Flow Diagram Figure 31-7. SPI Mode Flow Diagram 1 0 QSI Enable DRE ?

0 CS = 0 Delay DLYBS Serializer = TXDATA DRE = 1 Data Transfer RXDATA = Serializer RXC = 1 Delay DLYBCT DRE ?

1 CS = 1 Delay DLYCS 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 775 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Figure 31-8. Interrupt Flags Behaviour 1 2 3 4 5 6 7 8 SCK CS MOSI

(from host) DRE Write in TXDATA RXC MISO

(from client) TXC MSB 6 5 4 3 2 1 LSB RXDATA Read MSB 6 5 4 3 2 1 LSB Shift register empty 31.6.7.4 Peripheral Deselection with DMA When the Direct Memory Access Controller is used, the Chip Select line will remain low during the whole transfer since the Transmit Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is managed by the DMA itself. The reloading of the TXDATA by the DMA is done as soon as INTFLAG.DRE flag is set. In this case, setting the Chip Select Mode bit field in the Control B register (CTRLB.CSMODE) to 0x1 is not mandatory. However, it may happen that when other DMA channels connected to other peripherals are in use as well, the QSPI DMA could be delayed by another DMA transfer with a higher priority on the bus. Having DMA buffers in slower memories like Flash memory or SDRAM (compared to fast internal SRAM), may lengthen the reload time of the TXDATA by the DMA as well. This means that TXDATA might not be reloaded in time to keep the Chip Select line low. In this case the Chip Select line may toggle between data transfer and according to some SPI Client devices, and the communication might get lost. Writing CTRLB.CSMODE = 0x1 can prevent this loss. When CTRLB.CSMODE = 0x0, the CS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the INTFLAG.DRE flag is raised as soon as the content of the TXDATA is transferred into the internal shifter. When this flag is detected the TXDATA can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same Chip Select as the current transfer, the Chip Select is not de-asserted between the two transfers. This may lead to difficulties for interfacing with some serial peripherals requiring the Chip Select to be de-asserted after each transfer. To facilitate interfacing with such devices, it is recommended to write CTRLB.CSMODE to 0x2. 31.6.7.5 Peripheral Deselection without DMA During multiple data transfers on a Chip Select without the DMA, the TXDATA is loaded by the processor, and the Transmit Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) rises as soon as the content of the RXDATA is transferred into the internal shift register. When this flag is detected high, the TXDATA can be reloaded. If this reload-by-processor occurs before the end of the current transfer and if the next transfer is performed on the same Chip Select as the current transfer, the Chip Select is not de-asserted between the two transfers. Depending on the application software handling the flags or servicing other interrupts or other tasks, the processor may not reload the TXDATA in time to keep the Chip Select active (low). A null Delay Between Consecutive Transfer bit field value in the CTRLB register (CTRLB.DLYBCT) will give even less time for the processor to reload the TXDATA. With some SPI client peripherals, requiring the Chip Select line to remain active (low) during a full set of transfers might lead to communication errors. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 776 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... To facilitate interfacing with such devices, the Chip Select Mode bit field in the CTRLB register (CTRLB.CSMODE) can be written to 0x1. This allows the Chip Select lines to remain in their current state (low = active) until the end of transfer is indicated by the Last Transfer bit in the CTRLA register (CTRLA.LASTXFER). Even if the TXDATA is not reloaded the Chip Select will remain active. To have the Chip Select line rise at the end of the last data transfer, the LASTXFER bit in the CTRLA must be set before writing the last data to transmit into the TXDATA. 31.6.8 QSPI Serial Memory Mode In this mode the QSPI acts as a serial Flash memory controller. The QSPI can be used to read data from the serial Flash memory allowing the CPU to execute code from it (XIP execute in place). The QSPI can also be used to control the serial Flash memory (Program, Erase, Lock, and so on) by sending specific commands. In this mode, the QSPI is compatible with single-bit SPI, Dual-SPI and Quad-SPI protocols. To activate this mode, the MODE bit in Control B register must be set to one (CTRLB.MODE = 1). In serial memory mode, data cannot be transferred by the TXDATA and the RXDATA, but by writing or reading the QSPI memory space (0x0400 00000x0500 0000). Caching can be enabled using the CMCC module along with configuring CFGCON1.QSCHE_EN bit. Important:QSPI memory space region can be cached to improve data transfer speed. However, external Flash devices which have command/status registers mapped in the QSPI memory space region must be managed carefully by applying any one of the following configurations:

Data cache must be disabled. If data cache is required, then cache line must be invalidated before reading the status register. 31.6.8.1 Instruction Frame In order to control serial flash memories, the QSPI is able to sent instructions by the SPI bus (ex: READ, PROGRAM, ERASE, LOCK, etc.). Because instruction set implemented in serial flash memories is memory vendor dependant, the QSPI includes a complete instruction registers, which makes it very flexible and compatible with all serial flash memories. An instruction frame includes:

An instruction code (size: 8 bits). The instruction can be optional in some cases. An address (size: 24 bits or 32 bits). The address is optional but is required by instructions such as READ, PROGRAM, ERASE, LOCK. By default the address is 24 bits long, but it can be 32 bits long to support serial flash memories larger than 128 Mbit (16 Mbyte). An option code (size: 1/2/4/8 bits). The option code is optional but is useful for activate the XIP mode or the Continuous Read Mode for READ instructions, in some serial flash memory devices. These modes allow to improve the data read latency. Dummy cycles. Dummy cycles are optional but required by some READ instructions. Data bytes are optional. Data bytes are present for data transfer instructions such as READ or PROGRAM. The instruction code, the address/option and the data can be sent with Single-bit SPI, Dual SPI or Quad SPI protocols. Figure 31-9. Instruction Frame CS SCK DATA0 DATA1 DATA2 DATA3 A20 A16 A12 A8 A4 A0 O4 O0 D4 D0 D4 D0 A21 A17 A13 A9 A5 A1 O5 O1 D5 D1 D5 D1 A22 A18 A14 A10 A6 A2 O6 O2 D6 D2 D6 D2 Instruction EBh Address Option Dummy cycles Data A23 A19 A15 A11 A7 A3 O7 O3 D7 D3 D7 D3 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 777 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.6.8.2 Instruction Frame Sending To send an instruction frame, the user must first configure the address to send by writing the field ADDR in the Instruction Address Register (INSTRADDR.ADDR). This step is required if the instruction frame includes an address and no data. When data is present, the address of the instruction is defined by the address of the data accesses in the QSPI memory space, and not by the INSTRADDR register. If the instruction frame includes the instruction code and/or the option code, the user must configure the instruction code and/or the option code to send by writing the fields INST and OPTCODE bit fields in the Instruction Control Register (INSTRCTRL.OPTCODE, INSTRCTRL.INSTR). Then, the user must write the Instruction Frame Register (INSTRFRAME) to configure the instruction frame depending on which instruction must be sent. If the instruction frame does not include data, writing in this register triggers the send of the instruction frame in the QSPI. If the instruction frame includes data, the send of the instruction frame is triggered by the first data access in the QSPI memory space. The instruction frame is configured by the following bits and fields of INSTRFRAME:

WIDTH field is used to configure which data lanes are used to send the instruction code, the address, the option code and to transfer the data. It is possible to use two unidirectional data lanes (MISO-MOSI Single-bit SPI), two bidirectional data lanes (DATA0 - DATA1 Dual SPI) or four bidirectional data lanes (DATA0 - DATA3). Table 31-3. WIDTH Encoding INSTRFRAME Instruction Address/Option Data 0 1 2 3 4 5 6 7 Single-bit SPI Single-bit SPI Single-bit SPI Single-bit SPI Single-bit SPI Dual SPI Quad SPI Reserved Single-bit SPI Single-bit SPI Single-bit SPI Dual SPI Quad SPI Dual SPI Quad SPI Single-bit SPI Dual SPI Quad SPI Dual SPI Quad SPI Dual SPI Quad SPI INSTREN bit enables sending an instruction code. ADDREN bit enables sending of an address after the instruction code. OPTCODEEN bit enables sending of an option code after the address. DATAEN bit enables the transfer of data (READ or PROGRAM instruction). OPTCODELEN field configures the option code length (0 -> 1-bit / 1 -> 2-bit / 2 -> 4-bit / 3 -> 8-bit). The value written in OPTCODELEN must be consistent with value written in the field WIDTH. For example: OPTCODELEN

= 0 (1-bit option code) is not coherent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4-bit). ADDRLEN bit configures the address length (0 -> 24 bits / 1-> 32 bits) TFRTYPE field defines which type of data transfer must be performed. DUMMYLEN field configures the number of dummy cycles when reading data from the serial flash memory. Between the address/option and the data, with some instructions, dummy cycles are inserted by the serial flash memory. If data transfer is enabled, the user can access the serial memory by reading or writing the QSPI memory space following these rules:

Reading from the serial memory, but not memory data (for example reading the JEDEC-ID or the STATUS), requires TFRTYPE to be written to 0x0. Reading from the serial memory, and particularly memory data, requires TFRTYPE to be written to '1'. Writing to the serial memory, but not memory data (for example writing the configuration or STATUS), requires TFRTYPE to be written to 0x2. Writing to the serial memory, and particularly memory data, requires TFRTYPE to be written to 0x3. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 778 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... If TFRTYP has a value other than 0x1 and CTRLB.SMEMREG=0, the address sent in the instruction frame is the address of the first system bus accesses. The addresses of the subsequent access actions are not used by the QSPI. At each system bus access, an SPI transfer is performed with the same size. For example, a half-word system bus access leads to a 16-bit SPI transfer, and a byte system bus access leads to an 8-bit SPI transfer. If CTRLB.SMEMREG=1, accesses are made via the QSPI registers and the address sent in the instruction frame is the address defined in the INSTRADDR register. Each time the INSTRFRAME or TXDATA registers are written, an SPI transfer is performed with a byte size. Another byte is read each time RXDATA register is read or written each time TXDATA register is written. The SPI transfer ends by writing the LASTXFER bit in Control A register

(CTRLA.LASTXFER). If TFRTYP=0x1, the address of the first instruction frame is the one of the first read access in the QSPI memory space. Each time the read accesses become non-sequential (addresses are not consecutive), a new instruction frame is sent with the last system bus access address. In this way, the system can read data at a random location in the serial memory. The size of the SPI transfers may differ from the size of the system bus read accesses. When data transfer is not enabled, the end of the instruction frame is indicated when the INSTREND interrupt flag in the INTFLAG register is set. When data transfer is enabled, the user must indicate when data transfer is completed in the QSPI memory space by setting the bit LASTXFR in the CTRLA. The end of the instruction frame is indicated when the INSTREND interrupt flag in the INTFLAG register is set. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 779 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Figure 31-10. Instruction Transmission Flow Diagram START No Instruction frame with address but no data

Yes Write the address in INSTRADDR No Instruction frame with instruction code and/or option code

Yes Write the instruction code and/or the option code in INSTRCTRL Configure and send instruction frame by writing INSTRFRAME No Instruction frame with data

Yes Read INSTRFRAME to synchronize APB and AHB accesses No No Instruction frame with address

Yes Read memory transfer

(TFRTYP = 1)

Yes Read DATA in the QSPI AHB memory space. If accesses are not sequential a new instruction is sent automatically. Read/Write DATA in the QSPI AHB memory space

(SMEMREG = 0) or APB register space (SMEMREG = 1). The address of the first access is sent after the instruction code. Read/Write DATA in the QSPI AHB memory space. Address of accesses are not used by the QSPI. Write CTRLA.LASTXFR to 1 when all data have been transferred. Wait for INTFLAG.INSTREND to rise by polling or interrupt. Depending on CSMODE configuration wait for INTFLAG.CSRISE to rise by polling or interrupt. END 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 780 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.6.8.3 Read Memory Transfer The user can access the data of the serial memory by sending an instruction with DATAEN=1 and TFRTYP=0x1 in the Instruction Frame register (INSTRFRAME). In this mode the QSPI is able to read data at random address into the serial flash memory, allowing the CPU to execute code directly from it (XIP execute-in-place). In order to fetch data, the user must first configure the instruction frame by writing the INSTRFRAME. Then data can be read at any address in the QSPI address space mapping. The address of the system bus read accesses match the address of the data inside the serial Flash memory. When Fetch Mode is enabled, several instruction frames can be sent before writing the bit LASTXFR in the CTRLA. Each time the system bus read accesses become non-sequential (addresses are not consecutive), a new instruction frame is sent with the corresponding address. 31.6.8.4 Continuous Read Mode The QSPI is compatible with Continuous Read Mode (CRM) which is implemented in some Serial Flash memories. The CRM allows to reduce the instruction overhead by excluding the instruction code from the instruction frame. When CRM is activated in a Serial Flash memory (by a specific option code), the instruction code is stored in the memory. For the next instruction frames, the instruction code is not required, as the memory uses the stored one. In the QSPI, CRM is used when reading data from the memory (INSTFRAME.TFRTYPE=0x1). The addresses of the system bus read accesses are often non-sequential, this leads to many instruction frames with always the same instruction code. By disabling the sending of the instruction code, the CRM reduces the access time of the data. To be functional, this mode must be enabled in both the QSPI and the Serial Flash memory. The CRM is enabled in the QSPI by setting the CRM bit in the INSTRFRAME register (INSTFRAME.CRMODE=1, INSTFRAME.TFRTYPE must be 0x1). The CRM is enabled in the Serial Flash memory by sending a specific option code. CAUTION If CRM is not supported by the Serial Flash memory or disabled, the CRMODE bit must not be set. Otherwise, data read out the Serial Flash memory is not valid. Figure 31-11. Continuous Read Mode CS SCK DATA0 DATA1 DATA2 DATA3 A20 A16 A12 A8 A4 A0 O4 O0 D4 D0 D4 D0 A20 A16 A12 A8 A4 A0 O4 O0 A21 A17 A13 A9 A5 A1 O5 O1 D5 D1 D5 D1 A21 A17 A13 A9 A5 A1 O5 O1 A22 A18 A14 A10 A6 A2 O6 O2 D6 D2 D6 D2 A22 A18 A14 A10 A6 A2 O6 O2 A23 A19 A15 A11 A7 A3 O7 O3 D7 D3 D7 D3 A23 A19 A15 A11 A7 A3 O7 O3 D4 D0 D5 D1 D6 D2 D7 D3 Instruction Address Option to activate the Continuous Read Mode in the serial flash memory Data Address Instruction code is not required Option Data 31.6.8.5 Instruction Frame Transmission Examples All waveforms in the following examples describe SPI transfers in SPI Clock mode 0 (BAUD.CPOL=0 and BAUD.CPHA=0). All system bus accesses described below refer to the system bus address phase. System bus wait cycles and system bus data phases are not shown. Example 31-1.Example 1 Instruction in Single-bit SPI, without address, without option, without data. Command: CHIP ERASE (C7h). Write 0x0000_00C7 to INSTRCTRL register. Write 0x0000_0010 to INSTRFRAME register. Wait for INTFLAG.INSTREND to rise. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 781 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Figure 31-12. Instruction Transmission Waveform 1 Write INSTRFRAME CS SCK MOSI / DATA0 INTFLAG.INSTREND Instruction C7h Example 31-2.Example 2 Instruction in Quad SPI, without address, without option, without data. Command: POWER DOWN (B9h) Write 0x0000_00B9 to INSTRCTRL register. Write 0x0000_0016 to INSTRFRAME register. Wait for INTFLAG.INSTREND to rise. Figure 31-13. Instruction Transmission Waveform 2 Write INSTRFRAME CS SCK DATA0 DATA1 DATA2 DATA3 INTFLAG.INSTREND Instruction B9h Example 31-3.Example 3 Instruction in Single-bit SPI, with address in Single-bit SPI, without option, without data. Command: BLOCK ERASE (20h) Write the address (of the block to erase) to QSPI_AR. Write 0x0000_0020 to INSTRCTRL register. Write 0x0000_0030 toINSTRFRAME register. Wait for INTFLAG.INSTREND to rise. Figure 31-14. Instruction Transmission Waveform 3 Write INSTRADDR Write INSTRFRAME CS SCK MOSI / DATA0 INTFLAG.INSTREND Instruction 20h Address A23 A22 A21 A20 A3 A2 A1 A0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 782 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Example 31-4.Example 4 Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI. Command: SET BURST (77h) Write 0x0000_0077 to INSTRCTRL register. Write 0x0000_2090 to INSTRFRAME register. Read INSTRFRAME register (dummy read) to synchronize system bus accesses. Write data to the system bus memory space (0x0400_00000x0500_0000). The address of the system bus write accesses is not used. Write the LASTXFR bit in CTRLA register to '1'. Wait for INTFLAG.INSTREND to rise. Figure 31-15. Instruction Transmission Waveform 4 Write INSTRFRAME CS SCK MOSI / DATA0 INTFLAG.INSTREND Write AHB Set CTRLA.LASTXFER Instruction 77h Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Example 31-5.Example 5 Instruction in Single-bit SPI, with address in Dual SPI, without option, with data write in Dual SPI. Command: BYTE/PAGE PROGRAM (02h) Write 0x0000_0002 to INSTRCTRL register. Write 0x0000_30B3 to INSTRFRAME register. Read INSTRFRAME register (dummy read) to synchronize system bus accesses. Write data to the QSPI system bus memory space (0x040 000000x0500_0000). The address of the first system bus write access is sent in the instruction frame. The address of the next system bus write accesses is not used. Write LASTXFR bit in CTRLA register to '1'. Wait for INTFLAG.INSTREND to rise. Figure 31-16. Instruction Transmission Waveform 5 Write INSTRFRAME CS SCK DATA0 DATA1 INTFLAG.INSTREND Write AHB Set CTRLA.LASTXFER A22 A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 D6 D4 D2 D0 D6 D4 D2 D0 Instruction 02h Address Data A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 D7 D5 D3 D1 D7 D5 D3 D1 Example 31-6.Example 6 Instruction in Single-bit SPI, with address in Single-bit SPI, without option, with data read in Quad SPI, with eight dummy cycles. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 783 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Command: QUAD_OUTPUT READ ARRAY (6Bh) Write 0x0000_006B to INSTRCTRL register. Write 0x0008_10B2 ti INSTRFRAME register. Read QSPI_IR (dummy read) to synchronize system bus accesses. Read data from the QSPI system bus memory space (0x040 000000x0500_0000). The address of the first system bus read access is sent in the instruction frame. The address of the next system bus read accesses is not used. Write the LASTXFR bit in CTRLA register to '1'. Wait for INTFLAG.INSTREND to rise. Figure 31-17. Instruction Transmission Waveform 6 Write INSTRFRAME C S SCK DATA0 DATA1 DATA2 DATA3 INTFLAG.INSTREND Read AHB Set CTRLA.LASTXFER A23 A22 A21 A20 A3 A2 A1 A0 D4 D0 D4 D0 D5 D1 D5 D1 D6 D2 D6 D2 D7 D3 D7 D3 Instruction 6Bh Address Dummy cycles Data Example 31-7.Example 7 Instruction in Single-bit SPI, with address and option in Quad SPI, with data read from Quad SPI, with four dummy cycles, with fetch and continuous read. Command: FAST READ QUAD I/O (EBh) - 8-BIT OPTION (0x30h) Write 0x0030_00EB to INSTRCTRL register. Write 0x0004_33F4 to INSTRFRAME register. Read INSTRFRAME register (dummy read) to synchronize system bus accesses. Read data from the QSPI system bus memory space (0x040 000000x0500_0000). Fetch is enabled, the address of the system bus read accesses is always used. Write LASTXFR bit in CTRLA register to '1'. Wait for INTFLAG.INSTREND to rise. Figure 31-18. Instruction Transmission Waveform 7 Write INSTRFRAME C S SCK DATA0 DATA1 DATA2 DATA3 Read AHB A20 A16 A12 A8 A4 A0 O4 O0 D4 D0 D4 D0 A20 A16 A12 A8 A4 A0 O4 O0 A21 A17 A13 A9 A5 A1 O5 O1 D5 D1 D5 D1 A21 A17 A13 A9 A5 A1 O5 O1 A22 A18 A14 A10 A6 A2 O6 O2 D6 D2 D6 D2 A22 A18 A14 A10 A6 A2 O6 O2 A23 A19 A15 A11 A7 A3 O7 O3 D7 D3 D7 D3 A23 A19 A15 A11 A7 A3 O7 O3 D4 D0 D5 D1 D6 D2 D7 D3 Instruction EBh Address Option Dummy cycles Data Address Option Dummy cycles Data Example 31-8.Example 8 Instruction in Quad SPI, with address in Quad SPI, without option, with data read from Quad SPI, with two dummy cycles, with fetch. Command: HIGH-SPEED READ (0Bh) Write 0x0000_000B to INSTRCTRL register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 784 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Write 0x0002_20B6 to INSTRFRAME register. Read INSTRFRAME register (dummy read) to synchronize system bus accesses. Read data in the QSPI system bus memory space (0x040 000000x0500_0000). Fetch is enabled, the address of the system bus read accesses is always used. Write LASTXFR bit in CTRLA register to '1'. Wait for INTFLAG.INSTREND to rise. Figure 31-19. Instruction Transmission Waveform 8 Write INSTRFRAME C S SCK DATA0 DATA1 DATA2 DATA3 R e a d A H B A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 A20 A16 A12 A8 A4 A0 D4 D0 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 A21 A17 A13 A9 A5 A1 D5 D1 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 A22 A18 A14 A10 A6 A2 D6 D2 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 A23 A19 A15 A11 A7 A3 D7 D3 Instruction 0Bh Address Dummy cycles Data Instruction 0Bh Address Dummy cycles Data 31.6.9 Scrambling/Unscrambling Function The scrambling/unscrambling function cannot be performed on devices other than memories. Data is scrambled when written to memory and unscrambled when data is read. The external data lines can be scrambled to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either the micro-controller or the QSPI client device (e.g., memory). The scrambling/unscrambling function can be enabled by writing a 1 to the ENABLE bit in the Scrambling Control register (SCRAMBCTRL.ENABLE). The scrambling and unscrambling are performed on-the-fly without impacting the throughput. The scrambling method depends on the user-configurable Scrambling User Key in the Scrambling Key register

(SCRAMBKEY.KEY). This register is only accessible in Write mode. By default, the scrambling and unscrambling algorithm includes the scrambling user key, plus a device-dependent random value. This random value is not included when the Scrambling/Unscrambling Random Value Disable bit in the Scrambling Mode register (SCRAMBCTRL.RANDOMDIS) is written to 1. The random value is neither user-configurable nor readable. If SCRAMBCTRL.RANDOMDIS=0, data scrambled by a given circuit cannot be unscrambled by a different circuit. If SCRAMBCTRL.RANDOMDIS=1, the scrambling/unscrambling algorithm includes only the scrambling user key, making it possible to manage data by different circuits. The scrambling user key must be securely stored in a reliable Non-Volatile Memory to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. 31.6.10 DMA Operation The QSPI generates the following DMA requests:

Data received (RX): The request is set when data is available in the RXDATA register, and cleared when RXDATA is read. Data transmit (TX): The request is set when the transmit buffer (TXDATA) is empty, and cleared when TXDATA is written. Note:If DMA and RX memory modes are selected, a QSPI memory space read operation is required to force the first triggering. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 785 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... If the CPU accesses the registers which are source of DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted. 31.6.11 Interrupts The QSPI has the following interrupt source:

Interrupt Request (INTREQ): Indicates that at least one bit in the Interrupt Flag Status and Clear register

(INTFLAG) is set to '1'. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear

(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the QSPI is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 786 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.7 Register Summary See QSPI module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x00 CTRLA 0x04 CTRLB 0x08 BAUD 0x0C RXDATA 0x10 TXDATA 0x14 INTENCLR 0x18 INTENSET 0x1C INTFLAG 0x20 STATUS 0x24

... 0x2F Reserved 0x30 INSTRADDR 0x34 INSTRCTRL 0x38 INSTRFRAME 0x3C

... 0x3F Reserved ENABLE SWRST LASTXFER CSMODE[1:0]

SMEMREG WDRBT LOOPEN MODE DATALEN[3:0]

CPHA CPOL DLYBCT[7:0]

DLYCS[7:0]

BAUD[7:0]

DLYBS[7:0]

DATA[7:0]

DATA[15:8]

DATA[7:0]

DATA[15:8]

ERROR TXC DRE INSTREND ERROR TXC DRE INSTREND ERROR TXC DRE INSTREND RXC CSRISE RXC CSRISE RXC CSRISE ENABLE CSSTATUS ADDR[7:0]

ADDR[15:8]

ADDR[23:16]

ADDR[31:24]

INSTR[7:0]

OPTCODE[7:0]

DATAEN OPTCODEEN ADDREN INSTREN WIDTH[2:0]

DDREN CRMODE TFRTYPE[1:0]

ADDRLEN OPTCODELEN[1:0]

DUMMYLEN[4:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 787 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... ..........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x40 SCRAMBCTRL 0x44 SCRAMBKEY 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Related Links 7. Product Memory Mapping Overview 31.8 Register Description RANDOMDIS ENABLE KEY[7:0]

KEY[15:8]

KEY[23:16]

KEY[31:24]

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. See Peripheral Access Controller (PAC) from Related Links. Some registers are enable-protected, meaning they can only be written when the QSPI is disabled. Enable-protection is denoted by the Enable-protected property in each individual register description. Related Links 20. Peripheral Access Controller (PAC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 788 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.1 Control A Name:

Offset:

Reset:

Property:

Control A CTRLA 0x00 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 Access Reset LASTXFER W 0 16 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 Access Reset 1 ENABLE W 0 0 SWRST W 0 Bit 24 LASTXFERLast Transfer 0: No effect. 1: The chip select will be de-asserted after the character written in TD has been transferred. Bit 1 ENABLEEnable Writing a '0' to this bit disables the QSPI. Writing a '1' to this bit enables the QSPI to transfer and receive data. As soon as ENABLE is reset, QSPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the QSPI is disable. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the QSPI. A software-triggered hardware reset of the QSPI interface is performed. DMAC channels are not affected by software reset. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 789 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.2 Control B Name:

Offset:

Reset:

Property: PAC Write-Protection CTRLB 0x04 0x00000000 Control B Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset 30 R/W 0 22 R/W 0 14 29 R/W 0 21 R/W 0 13 DLYCS[7:0]

28 R/W 0 20 27 R/W 0 19 DLYBCT[7:0]

R/W 0 12 R/W 0 11 R/W 0 3 SMEMREG R/W 0 26 R/W 0 18 R/W 0 10 25 R/W 0 17 R/W 0 9 DATALEN[3:0]

R/W 0 2 WDRBT R/W 0 R/W 0 1 LOOPEN R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 MODE R/W 0 Bit 7 6 5 4 Access Reset CSMODE[1:0]

R/W 0 R/W 0 Bits 31:24 DLYCS[7:0]Minimum Inactive CS Delay This bit field defines the minimum delay between the inactivation and the activation of CS. The DLYCS time guarantees the client minimum deselect time. If DLYCS is 0x00, one CLK_QSPI_AHB period will be inserted by default. Otherwise, the following equation determines the delay:

DLYCS = Minimum inactive fperipheral clock Bits 23:16 DLYBCT[7:0]Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT=0x00, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. In Serial Memory mode (MODE=1), DLYBCT is ignored and no delay is inserted. Otherwise, the following equation determines the delay:

DLYBCT = (Delay Between Consecutive Transfers fperipheral clock) / 32 Bits 11:8 DATALEN[3:0]Data Length The DATALEN field determines the number of data bits transferred. Reserved values must not be used. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Description 8-bits transfer 9-bits transfer 10-bits transfer 11-bits transfer 12-bits transfer 13-bits transfer 14-bits transfer 15-bits transfer 16-bits transfer Reserved Name 8BITS 9BITS 10BITS 11BITS 12BITS 13BITS 14BITS 15BITS 16BITS 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 790 Microchip Confidential Confidential Bits 5:4 CSMODE[1:0]Chip Select Mode PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... The CSMODE field determines how the chip select is de-asserted. Value 0x0 Name NORELOAD Description The chip select is de-asserted if TD has not been reloaded before the end of the current transfer. The chip select is de-asserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. SYSTEMATICALLY The chip select is de-asserted systematically after each transfer. LASTXFER 0x1 0x2 0x3 Reserved Bit 3 SMEMREGSerial Memory Register Mode Value 0 1 Description Serial memory registers are written via AHB access. Serial memory registers are written via APB access. Reset the QSPI. Bit 2 WDRBTWait Data Read Before Transfer This bit determines the Wait Data Read Before Transfer option. Bit 1 LOOPENLocal Loopback Enable This bit defines if the Local Loopback is enabled or disabled. LOOPEN controls the local loopback on the data serializer for testing in SPI Mode only. (MISO is internally connected on MOSI). Value 0 1 Description Local Loopback is disabled. Local Loopback is enabled. Bit 0 MODESerial Memory Mode This bit defines if the QSPI is in SPI Mode or Serial Memory Mode. Value 0 1 Description SPI operating mode Serial Memory operating mode Name SPI MEMORY 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 791 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.3 Baud Rate Name:

Offset:

Reset:

Property: PAC Write-Protection BAUD 0x08 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 22 R/W 0 14 R/W 0 6 21 R/W 0 13 R/W 0 5 DLYBS[7:0]

BAUD[7:0]

20 R/W 0 12 R/W 0 4 19 R/W 0 11 R/W 0 3 18 R/W 0 10 R/W 0 2 17 R/W 0 9 R/W 0 1 CPHA R/W 0 16 R/W 0 8 R/W 0 0 CPOL R/W 0 Bits 23:16 DLYBS[7:0]Delay Before SCK This field defines the delay from CS valid to the first valid SCK transition. When DLYBS equals zero, the CS valid to SCK transition is 1/2 the SCK clock period. Otherwise, the following equation determines the delay:

Equation 31-1.Delay Before SCK Delay Before SCK =

Bits 15:8 BAUD[7:0]Serial Clock Baud Rate DLYBS MCK The QSPI uses a modulus counter to derive the SCK baud rate from the module clock (MCK) CLK_QSPI_AHB. The Baud rate is selected by writing a value from 1 to 255 in the BAUD field. The following equation determines the SCK baud rate:

Equation 31-2.SCK Baud Rate SCK Baud Rate =

Bit 1 CPHAClock Phase MCK BAUD + 1 CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between host and client devices. Value 0 1 Description Data is captured on the leading edge of SCK and changed on the following edge of SCK. Data is changed on the leading edge of SCK and captured on the following edge of SCK. Bit 0 CPOLClock Polarity CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the required clock/data relationship between host and client devices. Value 0 Description The inactive state value of SCK is logic level zero. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 792 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Value 0 Description The inactive state value of SCK is logic level 'one'. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 793 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.4 Receive Data Name:

Offset:

Reset:

Property:

RXDATA 0x0C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 14 R 0 6 R 0 13 R 0 5 R 0 DATA[15:8]

DATA[7:0]

12 R 0 4 R 0 11 R 0 3 R 0 10 R 0 2 R 0 9 R 0 1 R 0 8 R 0 0 R 0 Bits 15:0 DATA[15:0]Receive Data Data received by the QSPI is stored in this register right-justified. Unused bits read zero. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 794 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.5 Transmit Data Name:

Offset:

Reset:

Property:

TXDATA 0x10 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset Bit Access Reset W 0 7 W 0 14 W 0 6 W 0 13 W 0 5 W 0 DATA[15:8]

DATA[7:0]

12 W 0 4 W 0 11 W 0 3 W 0 10 W 0 2 W 0 9 W 0 1 W 0 8 W 0 0 W 0 Bits 15:0 DATA[15:0]Transmit Data Data to be transmitted by the QSPI is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 795 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.6 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x14 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 Access Reset 10 INSTREND R/W 0 Bit 7 6 5 4 Access Reset 3 ERROR R/W 0 2 TXC R/W 0 9 1 DRE R/W 0 8 CSRISE R/W 0 0 RXC R/W 0 Bit 10 INSTRENDInstruction End Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The INSTREND interrupt is disabled. The INSTREND interrupt is enabled. Bit 8 CSRISEChip Select Rise Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The CSRISE interrupt is disabled. The CSRISE interrupt is enabled. Bit 3 ERROROverrun Error Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The ERROR interrupt is disabled. The ERROR interrupt is enabled. Bit 2 TXCTransmission Complete Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The TXC interrupt is disabled. The TXC interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 796 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Bit 1 DRETransmit Data Register Empty Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The DRE interrupt is disabled. The DRE interrupt is enabled. Bit 0 RXCReceive Data Register Full Interrupt Disable Writing a '0' to this bit has no effect. Writing a '1' will clear the corresponding interrupt request. Value 0 1 Description The RXC interrupt is disabled. The RXC interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 797 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.7 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x18 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 Access Reset 10 INSTREND R/W 0 Bit 7 6 5 4 Access Reset 3 ERROR R/W 0 2 TXC R/W 0 9 1 DRE R/W 0 8 CSRISE R/W 0 0 RXC R/W 0 Bit 10 INSTRENDInstruction End Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The INSTREND interrupt is disabled. The INSTREND interrupt is enabled. Bit 8 CSRISEChip Select Rise Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The CSRISE interrupt is disabled. The CSRISE interrupt is enabled. Bit 3 ERROROverrun Error Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The ERROR interrupt is disabled. The ERROR interrupt is enabled. Bit 2 TXCTransmission Complete Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The TXC interrupt is disabled. The TXC interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 798 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Bit 1 DRETransmit Data Register Empty Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The DRE interrupt is disabled. The DRE interrupt is enabled. Bit 0 RXCReceive Data Register Full Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' will set the corresponding interrupt request. Value 0 1 Description The RXC interrupt is disabled. The RXC interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 799 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.8 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x1C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 Access Reset 10 INSTREND R/W 0 Bit 7 6 5 4 Access Reset 3 ERROR R/W 0 2 TXC R/W 0 9 1 DRE R/W 0 8 CSRISE R/W 0 0 RXC R/W 0 Bit 10 INSTRENDInstruction End This bit is set when an Instruction End has been detected. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the flag. Bit 8 CSRISEChip Select Rise The bit is set when a Chip Select Rise has been detected. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the flag. Bit 3 ERROROverrun Error This bit is set when an ERROR has occurred. An ERROR occurs when RXDATA is loaded at least twice from the serializer. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the flag. Bit 2 TXCTransmission Complete 0: As soon as data is written in TXDATA. 1: TXDATA and internal shifter are empty. If a transfer delay has been defined, TXC is set after the completion of such delay. Bit 1 DRETransmit Data Register Empty 0: Data has been written to TXDATA and not yet transferred to the serializer. 1: The last data written in the TXDATA has been transferred to the serializer. This bit is '0' when the QSPI is disabled or at reset. The bit is set as soon as ENABLE bit is set. Bit 0 RXCReceive Data Register Full 0: No data has been received since the last read of RXDATA. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 800 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 1: Data has been received and the received data has been transferred from the serializer to RXDATA since the last read of RXDATA. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 801 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.9 Status Name:

Offset:

Reset:

Property:

STATUS 0x20 0x00000200

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 3 2 Access Reset Bit 9 CSSTATUSChip Select Value 0 1 Description Chip Select is asserted. Chip Select is not asserted. Bit 1 ENABLEEnable Value 0 1 Description QSPI is disabled. QSPI is enabled. 8 0 9 CSSTATUS R 1 1 ENABLE R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 802 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.10 Instruction Address Name:

Offset:

Reset:

Property:

INSTRADDR 0x30 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 ADDR[31:24]

R/W 0 20 R/W 0 19 ADDR[23:16]

R/W 0 12 R/W 0 4 R/W 0 ADDR[15:8]

ADDR[7:0]

R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 ADDR[31:0]Instruction Address Address to send to the serial flash memory in the instruction frame. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 803 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.11 Instruction Code Name:

Offset:

Reset:

Property:

INSTRCTRL 0x34 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset Bit 7 Access Reset R/W 0 22 R/W 0 14 6 R/W 0 21 R/W 0 13 5 R/W 0 20 19 OPTCODE[7:0]

R/W 0 12 4 R/W 0 INSTR[7:0]

R/W 0 11 3 R/W 0 18 R/W 0 10 2 R/W 0 17 R/W 0 9 1 16 R/W 0 8 0 R/W 0 R/W 0 Bits 23:16 OPTCODE[7:0]Option Code These bits define the option code to send to the serial flash memory. Bits 7:0 INSTR[7:0]Instruction Code Instruction code to send to the serial flash memory. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 804 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.12 Instruction Frame Name:

Offset:

Reset:

Property:

INSTRFRAME 0x38 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 R/W 0 12 Access Reset Bit Access Reset Bit Access Reset 15 DDREN R/W 0 7 DATAEN R/W 0 14 CRMODE R/W 0 13 TFRTYPE[1:0]

R/W 0 R/W 0 6 OPTCODEEN R/W 0 5 ADDREN R/W 0 4 INSTREN R/W 0 19 R/W 0 11 3 18 DUMMYLEN[4:0]

R/W 0 17 R/W 0 16 R/W 0 10 ADDRLEN R/W 0 8 9 OPTCODELEN[1:0]

R/W R/W 0 0 2 R/W 0 1 WIDTH[2:0]

R/W 0 0 R/W 0 Bits 20:16 DUMMYLEN[4:0]Dummy Cycles Length The DUMMYLEN field defines the number of dummy cycles required by the serial Flash memory before data transfer. Bit 15 DDRENDouble Data Rate Enable Note:Double Data Rate operating is only supported in Read. Value 0 1 Description Double Data Rate operating mode is disabled. Double Data Rate operating mode is enabled. Bit 14 CRMODEContinuous Read Mode This bit defines if the Continuous Read Mode is enabled or disabled. Value 0 1 Description Continuous Read Mode is disabled. Continuous Read Mode is enabled. Bits 13:12 TFRTYPE[1:0]Data Transfer Type These bits define the data type transfer. Value 0x0 Name READ Description Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. 0x1 0x2 0x3 READMEMORY Read data transfer from the serial memory.If enabled, scrambling is WRITE WRITEMEMORY Write data transfer into the serial memory. If enabled, scrambling is performed. performed.Read at random location (fetch) in the serial flash memory is possible. Write transfer into the serial memory.Scrambling is not performed. Bit 10 ADDRLENAddress Length The ADDRLEN bit determines the length of the address. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 805 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... Value 0x0 0x1 Name 24BITS 32BITS Description 24-bits address length 32-bits address length Bits 9:8 OPTCODELEN[1:0]Option Code Length The OPTCODELEN field determines the length of the option code. The value written in OPTCODELEN must be coherent with value written in the field WIDTH. For example: OPTCODELEN=0 (1-bit option code) is not coherent with WIDTH=6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4-bit). Value 0x0 0x1 0x2 0x3 Description 1-bit length option code 2-bits length option code 4-bits length option code 8-bits length option code Name 1BIT 2BITS 4BITS 8BITS Bit 7 DATAENData Enable Value 0 1 Description No data is sent/received to/from the serial flash memory. Data is sent/received to/from the serial flash memory. Bit 6 OPTCODEENOption Enable Description The option is not sent to the serial flash memory The option is sent to the serial flash memory. Value 0 1 Bit 5 ADDRENAddress Enable Value 0 1 Description The transfer address is not sent to the serial flash memory. The transfer address is sent to the serial flash memory. Bit 4 INSTRENInstruction Enable Description The instruction is not sent to the serial flash memory. The instruction is sent to the serial flash memory. Value 0 1 Bits 2:0 WIDTH[2:0]Instruction Code, Address, Option Code and Data Width This field defines the width of the instruction code, the address, the option and the data. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Reserved Name SINGLE_BIT_SPI DUAL_OUTPUT QUAD_OUTPUT DUAL_IO QUAD_IO DUAL_CMD QUAD_CMD 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 806 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 31.8.13 Scrambling Mode Name:

Offset:

Reset:

Property: PAC Write-Protection SCRAMBCTRL 0x40 0x00000000 Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 Access Reset 1 RANDOMDIS R/W 0 0 ENABLE R/W 0 Bit 1 RANDOMDISScrambling/Unscrambling Random Value Disable Value 0 1 Description The scrambling/unscrambling algorithm includes the scrambling user key plus a random value that may differ from chip to chip. The scrambling/unscrambling algorithm includes only the scrambling user key. Bit 0 ENABLEScrambling/Unscrambling Enable This bit defines if the scrambling/unscrambling is enabled or disabled. Value 0 1 Description Scrambling/unscrambling is disabled. Scrambling/unscrambling is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 807 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quad Serial Peripheral Interface (... 28 W 0 20 W 0 12 W 0 4 W 0 KEY[31:24]

KEY[23:16]

KEY[15:8]

KEY[7:0]

27 W 0 19 W 0 11 W 0 3 W 0 26 W 0 18 W 0 10 W 0 2 W 0 25 W 0 17 W 0 9 W 0 1 W 0 24 W 0 16 W 0 8 W 0 0 W 0 31.8.14 Scrambling Key Name:

Offset:

Reset:

Property: PAC Write-Protection SCRAMBKEY 0x44 0x00000000 Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 W 0 23 W 0 15 W 0 7 W 0 30 W 0 22 W 0 14 W 0 6 W 0 29 W 0 21 W 0 13 W 0 5 W 0 Bits 31:0 KEY[31:0]Scrambling User Key This field defines the user key value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 808 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32. Analog-to-Digital Converter (ADC) 32.1 Overview The PIC32CX-BZ3 has one shared ADC module. This ADC module incorporates a multiplexer on the input to facilitate a group of inputs and provides a flexible automated scanning option through the input scan logic. For the ADC module, the analog inputs are connected to the Sample and Hold (S&H) capacitor. The ADC module performs the conversion of the input analog signal based on the configurations set in the registers. When the conversion is complete, the final result is stored in the result buffer for the specific analog input and is passed to the digital filter and digital comparator if configured to use data from this particular sample. 32.2 Features The PIC32CX-BZ3 12-bit High Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes the following features:

12-bit resolution One ADC module, up to 2 Msps conversion rate Single-ended and/or differential input Supported in Standby Sleep mode Two digital comparators Two digital filters supporting two modes:

Oversampling mode Averaging mode Designed for motor control, power conversion and general purpose applications 32.3 Block Diagram A block diagram of the ADC module is illustrated in the following figure. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 809 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Figure 32-1. ADC Block Diagram K L C _ 1 B P 3 K L C F E R AVDD AVSS

(ADCCON3) [1:0]

00 01 10 11 TCLK CONCLKDIV [5:0]

(ADCCON3) TAD7 ADCDIV [6:0]

(ADCCON2 [6:0] )

(ADCCON3)

(ADINSEL[5:0]) BG_VREF (AN8) CP_1V2 (AN9) VDD_1V2 (AN10) VDD33/2 (AN11) ANN0 1

(ADCIMCON1) VREFSEL[2:0]

(ADCCON3) AN1 AN6 AN7 CVD Capacitors ADC7 ADCDATA0

... ADCDATA11 Triggers, Scan Control Logic Trigger Digital Filter Data Digital Comparator Interrupt/Event Capacitive Voltage Divider (CVD) Interrupt/Event Status and Control Registers Interrupt S U B M E T S Y S 32.4 ADC Operation The High Speed Successive Approximation Register (SAR) ADC is designed to support power conversion and motor control applications and consists of one shared ADC module. The shared ADC module has multiple analog inputs connected to its S&H circuit through a multiplexer. Multiple analog inputs share this ADC; therefore, it is termed the shared ADC module. The shared ADC module is used to measure analog signals of lower frequencies and signals that are static in nature (in other words, do not change significantly with time). However, this ADC module is capable of up to 2 Msps sample rate. The analog inputs connected to the shared ADC module are Class 2 and Class 3 inputs. The number of inputs designated for each class depends on the specific device. For the PIC32CX-BZ3, the following arrangement is provided. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 810 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Class 2 = AN0 to AN7 Class 3 = AN8 to AN11 The property of each class of analog input is described in the following table. Table 32-1. Analog Input Class ADC Module Analog Input Class Trigger Trigger Action Shared ADC module Class 2 Individual trigger source or scan trigger Starts sampling sequence or begins scan sequence Shared ADC module with input scan Class 3 Scan trigger Starts scan sequence Class 2 and Class 3 analog input properties:

Class 2 inputs are used on the shared ADC module, either individually triggered or as part of a scan list. When used individually, they are triggered by their unique trigger selected by the ADCTRGx register. The analog inputs on the shared ADC have a natural order of priority (for example, AN6 has a higher priority than AN7). Class 3 inputs are used exclusively for scanning and share a common trigger source (scan trigger). Class 3 analog inputs share both the ADC module and the trigger source; therefore, the only method possible to convert them is to scan them sequentially for each incoming scan trigger event, where scanning occurs in the natural order of priority. The arrival of a trigger in the shared ADC module only starts the sampling. When the trigger arrives, the ADC module goes into sampling mode for the sampling time decided by the SAMC[9:0] bits (ADCCON2[25:16]). At the end of sampling, the ADC starts conversion. Upon completion of conversion, the ADC module is used to convert the next in line Class 2 or Class 3 inputs according to the natural order of priority. When a shared analog input (Class 2 or Class 3) has completed all conversion and no trigger is pending, the ADC module is disconnected from all analog inputs Figure 32-2. Sample and Conversion Sequence for Shared ADC Modules 32.4.1 Class 2 Triggering When a single Class 2 input is triggered, it is sampled and converted by the shared S&H using the sequence illustrated in Sample and Conversion Sequence for the Shared ADC Modules figure; see Sample and Conversion Sequence for Shared ADC Modules figure in the ADC Operation from Related Links. When multiple Class 2 inputs are triggered, it is important to understand the consequences of trigger timing. If a conversion is underway and 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 811 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) another Class 2 trigger occurs, then the sample-hold-conversion for the new trigger is stalled until the in-process, sample-hold cycle is complete, as shown in the following figure. Figure 32-3. Multiple Independent Class 2 Trigger Conversion Sequence AN1 AN1 AN2 AN2 AN1 AN1 AN2 AN2 AN1 AN2 When multiple inputs to the shared S&H are triggered simultaneously, the processing order is determined by their natural priority (the lowest numbered input has the highest priority). As an example, if AN1, AN2 and AN3 are triggered simultaneously, AN1 is sampled and converted first, followed by AN2 and finally, AN3. When using the independent Class 2 triggering on the shared S&H, the SAMC[9:0] bits (ADCCON2[25:16]) determine the sample time for all inputs while the appropriate TRGSRC[4:0] bits in the ADCTRGx Register (see ADCTRG1 register from Related Links) determine the trigger source for each input. 32.4.2 Input Scan Input scanning is a feature that allows an automated scanning sequence of multiple Class 2 or Class 3 inputs. All Class 2 and Class 3 inputs are scanned using the single shared S&H. The selection of analog inputs for scanning is done with the CSSx bits of the ADCCSS1 registers. Class 2 inputs are triggered using STRIG selection in the ADCTRGx register, and Class 3 inputs are triggered using the STRGSRC[4:0] of the ADCCON1[20:16] register. When a trigger occurs for Class 2 or Class 3 inputs, the sampling and conversion occur in the natural input order is used; lower number inputs are sampled before higher number inputs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 812 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Figure 32-4. Input Scan Conversion Sequence for Three Class 2 Inputs AN1 AN1 AN2 AN2 AN3 AN3 AN1 AN2 AN3 When using the shared analog inputs in scan mode, the SAMC[9:0] bits in the ADC Control Register 2

(ADCCON2[25:16]) determine the sample time for all inputs, while the Scan Trigger Source Selection bits

(STRGSRC[4:0]) in the ADC Control Register 1 (ADCCON1[20:16]) determine the trigger source. To ensure predictable results, a scan must not be retriggered until a sampling of all inputs is complete. Ensure system design to preclude retriggering a scan while a scan is in progress. Individual Class 2 triggers that occur during a scan preempts the scan sequence if they are a higher priority than the sample currently being processed. In the following figure, a scan of AN5, AN6 and AN7 is underway when an independent trigger of Class 2 input AN2 takes place. The scan is interrupted for the sampling and conversion of AN2. Figure 32-5. Scan Conversion Pre-empted by Class 2 Input Trigger AN5 AN6 AN2 AN7 AN2 AN7 AN2 AN2 AN6 AN6 AN5 AN5 AN6 AN6 AN2 AN2 AN7 AN7 AN5 AN6 AN2 AN7 32.5 ADC Module Configuration Operation of the ADC module is directed through bit settings in the specific registers. The following instructions summarize the actions and the settings. The options and details for each configuration step are provided in the subsequent sections. To configure the ADC module, perform the following steps:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 813 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Select the analog inputs to the ADC multiplexers as described in Select the format of the ADC result as described in Select the conversion trigger source as described in Select the voltage reference source as described in Select the scanned inputs as described in Select the analog-to-digital conversion clock source and prescaler as described in Specify any additional acquisition time (if required) as described in Turn on the ADC module as described in 1. Configure the analog port pins as described in 2. 3. 4. 5. 6. 7. 8. 9. 10. Poll (or wait for the interrupt) for the voltage reference to be ready as described in 11. Enable the analog and bias circuit for the required ADC modules, and, after the ADC module wakes up, enable the digital circuit as described in 12. Configure the ADC interrupts (if required) as described in 32.5.1 Configuring the Analog Port Pins The ANSELx registers for the I/O ports associated with the analog inputs are used to configure the corresponding pin as an analog or a digital pin. A pin is configured as an analog input when the corresponding ANSELx bit = 1. When the ANSELx bit = 0, the pin is set to digital control. The ANSELx registers are set when the device comes out of Reset, causing the ADC input pins to be configured as analog inputs by default. The TRISx registers control the digital function of the port pins. The port pins that are required as analog inputs must have their corresponding bit set in the specific TRISx register, configuring the pin as an input. If the I/O pin associated with an ADC input is configured as an output by clearing the TRISx bit, the ports digital output level (VOH or VOL) is converted. After a device Reset, all of the TRISx bits are set. For more information on port pin configuration, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. Note:When reading a PORT register that shares pins with the ADC, any pin configured as an analog input reads as 0 when the PORT latch is read. Analog levels on any pin that is defined as a digital input but not configured as an analog input, may cause the input buffer to consume the current that exceeds the device specification. 32.5.2 Selecting the ADC Multiplexer Analog Inputs The ADC module has two inputs, referred to as the positive and negative inputs. Input selection options vary as described in the following sections. 32.5.2.1 Selection of Positive Inputs For the shared ADC module, the positive input is shared among all Class 2 and Class 3 inputs. Input connection of the analog input ANx to the shared ADC is automatic for either the Class 2 input trigger or during a scan of Class 2 and or Class 3 inputs. Selecting inputs for scanning is described in Selecting the Scanned Inputs from Related Links. Related Links 32.5.6. Selecting the Scanned Inputs 32.5.2.2 Selection of Negative Inputs Negative input selection is determined by the setting of the DIFFx bit of the ADCIMCON1 register. The DIFFx bit allows the inputs to be rail-to-rail and either single-ended or differential. The SIGNx and DIFFx bits in the ADCIMCON1 register scale the internal ADC analog inputs and reference voltages and configure the digital result to align with the expected full-scale output range. For the shared ADC module, the analog inputs have individual settings for the DIFFx bit. Therefore, the user has the ability to select certain inputs as single-ended and others as differential while being connected to the same shared ADC module. While sampling, the signal changes on-the-fly as single-ended or differential according to its corresponding DIFFx bit setting. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 814 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Table 32-2. Negative Input Selection ADCIMCON1 Input Configuration Input Voltage DIFFx SIGNx 1 1 0 0 1 0 1 0 Differential 2s complement Minimum input VINP - VINN = -VREF Maximum input VINP - VINN = VREF Differential unipolar Minimum input VINP - VINN = -VREF 0 Single-ended 2s complement Maximum input VINP - VINN = VREF Minimum input VINP = VREF Maximum input VINP - VINN = VREF Single-ended unipolar Minimum input VINP = VREF

+4095

-2048

+2047 0 Maximum input VINP - VINN = VREF

+4095 Output

-2048

+2047 Legend:

VINP = Positive S&H input VINN = Negative S&H input VREF = VREFH - VREFL Note:For proper operation and to prevent device damage, input voltage levels must not exceed the limits listed in the Electrical Specifications. 32.5.3 Selecting the Format of the ADC Result The data in the ADC Result register can be read in any of the four supported data formats. The user can select from unsigned integer, signed integer, unsigned fractional or signed fractional. Integer data is right-justified and fractional data is left-justified. The integer or fractional data format selection is specified globally for all analog inputs using the Fractional Data Output Format bit, FRACT (ADCCON1[23]). The signed or unsigned data format selection can be independently specified for each individual analog input using the SIGNx bits in the ADCIMCONx registers

. The following table provides how a result is formatted. Table 32-3. ADC Result Format FRACT SIGNx Description 32-bit Output Data Format 0 0 1 1 0 1 0 1 Unsigned integer Signed integer Fractional Signed fractional 0000 0000 ssss ssss dddd 0000 sddd 0000 0000 dddd ssss sddd dddd 0000 dddd 0000 0000 dddd ssss dddd dddd 0000 dddd 0000 0000 dddd ssss dddd 0000 0000 dddd 0000 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 815 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) The following code is an example for ADC Class 2 configuration and fractional format. int main(int argc, char** argv) {

int result[3];

/* Configure ADCCON1 */

ADCCON1bits.FRACT = 1; // use Fractional output format ADCCON1bits.SELRES = 3; // ADC resolution is 12 bits ADCCON1bits.STRGSRC = 0; // No scan trigger.

/* Configure ADCCON2 */

ADCCON2bits.SAMC = 5; // ADC sampling time = 5 * TAD7 ADCCON2bits.ADCDIV = 1; // ADC clock freq is half of control clock = TAD7

/* Initialize warm up time register */ ADCANCON = 0;

ADCANCONbits.WKUPCLKCNT = 5; // Wakeup exponent = 32 * TAD7

/* Clock setting */ ADCCON3 = 0;

ADCCON3bits.ADCSEL = 0; // Select input clock source ADCCON3bits.CONCLKDIV = 1; // Control clock frequency is half of input clock ADCCON3bits.VREFSEL = 0; // Select AVDD and AVSS as reference source

/* Select ADC input mode */

ADCIMCON1bits.SIGN7 = 0; // unsigned data format ADCIMCON1bits.DIFF7 = 0;

/* Configure ADCGIRQENx */

ADCGIRQEN1 = 0; // No interrupts are used ADCGIRQEN2 = 0;

/* Configure ADCCSSx */

ADCCSS1 = 0; // No scanning is used

/* Configure ADCCMPCONx */

ADCCMPCON1 = 0; // No digital comparators are used. Setting the ADCCMPCONx ADCCMPCON2 = 0; // register to '0' ensures that the comparator is disabled.

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // No oversampling filters are used. ADCFLTR2 = 0;

/* Set up the trigger sources */

ADCTRGSNSbits.LVL7 = 0;

ADC1TRG2bits.TRGSRC7 = 1; // Set AN7 to trigger from software

/* Turn the ADC on */

ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN7 = 1; // Enable the clock to analog bias

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY7); // Wait until ADC7 is ready

/* Enable the ADC module */ ADCCON3bits.DIGEN7 = 1; // Enable ADC7 while (1) {

/* Trigger a conversion */ ADCCON3bits.GSWTRG = 1;

/* Wait the conversions to complete */

while (ADCDSTAT1bits.ARDY7 == 0);

/* fetch the result */

result[0] = ADCDATA7;

* Process results here

* Note 1: Loop time determines the sampling time since all inputs are Class 2.

* If the loop time happens is small and the next trigger happens before the

* completion of set sample time, the conversion will happen only after the

* sample time has elapsed.

* Note 2: Results are in fractional format

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 816 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC)

return (1);

32.5.4 Selecting the Conversion Trigger Source Class 2 inputs to the ADC module can be triggered for conversion either individually or as part of a scan sequence. Class 3 inputs can only be triggered as part of a scan sequence. Individual or scan triggers can originate from an event system (EVSYS), from external digital circuits connected to INT0, from external analog circuits connected to an analog comparator or through software by setting a trigger bit in an SFR. Note:When conversion triggers for multiple Class 2 analog inputs occur simultaneously, they are prioritized according to a natural order priority scheme based on the analog input used. AN6 has the highest priority, AN7 has the next highest priority and so on. 32.5.4.1 Trigger Selection Class 2 Inputs For each one of the Class 2 inputs, the user application can independently specify a conversion trigger source. The individual trigger source for an analog input x is specified by the TRGSRC[4:0] bits located in registers ADCTRG1 through ADCTRG2. For example, these trigger sources may include:

Event System (EVSYS): The event system is tied with many peripherals. The peripheral can be an event generator and ADC can be an event user to trigger the ADC conversion. See Event User m from Related Links. External INT0 Pin Trigger: In this mode, the ADC module starts a conversion on an active transition on the INT0 pin. The INT0 pin may be programmed for either a rising edge input or a falling edge input to trigger the conversion process. Global Software Trigger: The ADC module can be configured for manually triggering a conversion for all inputs that have selected this trigger option. The user can manually trigger a conversion by setting the Global Software Trigger bit, GSWTRG (ADCCON3[6]). Related Links 26.8.13. USERm 32.5.4.2 Conversion Trigger Sources and Control The following are the possible sources for each trigger signal:

External trigger selection through the TRGSRCx[4:0] bits in the ADCTRGx registers. This capability is supported only for Class 2 analog inputs. Typically, the user specifies a particular trigger source to initiate a conversion for specific input. All of the analog inputs may select the same trigger source if desired. In such an event, the result resembles a scanned conversion, which has its order of completion enforced by the priority of the inputs associated with the same trigger source. The first trigger selection is 00000 (no trigger), which amounts to temporarily disabling that particular trigger and, consequently, temporarily disabling that analog input from being converted. The next two selections for trigger source (GSWTRG and GLSWTRG) are software-generated trigger sources. The second software-generated trigger selection is the Global Software Trigger (GSWTRG). This trigger links to the GSWTRG bit in the ADCCON3 register, which may be used to enable the user application to initiate a single conversion. GSWTRG is a self-clearing bit; therefore, it clears itself on the next ADC clock cycle after being set by the user application. The third software-generated trigger selection is the Global Level Software Trigger (GLSWTRG), which is linked to the GLSWTRG bit in the ADCCON3 register. This trigger may be used by the user application to initiate a burst of consecutive samples as the GLSWTRG bit is not self-clearing. The fourth trigger selection is a special selection, the Scan Trigger selection, which allows the Class 2 analog inputs to be included as members of a global scan of all inputs. Scanned trigger selection via the STRGSRC[4:0] bits in the ADCCON1 register and select bits in the ADCCSS1 registers. This mode is typically used to initiate the conversion of a group of analog inputs. This capability works for 2 and 3 analog inputs but is typically used for Class 3 inputs because they do not have individual associated TRGSRC bits. One of the trigger selections is the GSWTRG bit in the ADCCON3 register, which may be used to enable the user software to initiate a conversion. User initiated trigger via the ADINSEL[5:0] bits and the RQCNVRT bit in the ADCCON3 register. This mode enables the user application to create an individual conversion trigger request for a specified analog input. Using this mode enables the user application to trigger the conversion of an input without changing the trigger source configuration of the ADC. This is useful in handling error situations where another software module wants ADC 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 817 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) information without disrupting the normal operation of the ADC. This is also the preferred method to generate the initial trigger to start a digital filter sequence. User-controlled sampling of Class 2 and Class 3 inputs via the ADINSEL[5:0] bits and the SAMP bit in the ADCCON3 register. Setting the SAMP bit causes the Class 2 and Class 3 inputs to be in Sampling mode while ignoring the selection of the SAMC[9:0] bits. This mode is also useful in software conversion of ADC with software-selectable sample time. 32.5.4.3 User-Requested Individual Conversion Trigger (Software ADC Conversion) The user can explicitly request a single conversion (by software) of any selected analog input at any time during program execution without changing the trigger source configuration of the ADC. The steps to be followed for conversion are as follows:

The analog input ID to be converted is specified by the ADC Input Select bits, ADINSEL[5:0] (ADCCON3[5:0]). The sampling of analog input is started by setting the SAMP bit (ADCCON3[9]). After the required sampling time (time delay), the SAMP bit is cleared. The conversion of sampled signal is started by setting the RQCNVRT bit (ADCCON3[8]). 1. 2. 3. 4. 5. Once the conversion is complete, the ARDYx bit of the ADCDSTATx register is set. The data can be read from the ADCDATAx register. The following figure illustrates the conversion process in graphical form. Figure 32-6. Individual Conversion Trigger Process AN6 AN7 AN6 AN6 AN7 AN7 AN6 AN7 32.5.5 Selecting the Voltage Reference Source The user application can select the voltage reference for the ADC module, which can be internal or external. The Voltage Reference Input Selection bits, VREFSEL[2:0] (ADCCON3[15:13]), select the voltage reference for analog-to-digital conversions. The upper voltage reference (VREFH) and the lower voltage reference (VREFL) may be the internal AVDD and AVSS voltage rails or the band gap reference generator or the external VREFH+ and VREF-

input pins. When the voltage reference and band gap reference are ready, the BGVRRDY (ADCCON2[31]) bit is set. If a Fault occurs in the voltage reference (such as a brown-out), the REFFLT bit (ADCCON2[30]) is set. The 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 818 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) BGVRRDY and REFFLT bits can also generate interrupts if the BGVRIEN bit (ADCCON2[15]) and REFFLTIEN bit

(ADCCON2[14]) are set, respectively. The voltages applied to the external reference pins must comply with certain specifications. See Electrical Characteristics from Related Links. The Analog Input Charge Pump Enable bit, AICPMPEN (ADCCON1[12]), must be set when the difference between the selected reference voltages (VREFH - VREFL) is less than 0.65 * (AVDD - AVSS). Setting this bit does not increase the magnitude of the reference voltage; however, setting this bit reduces the series source resistance to the sampling capacitors. This maximizes the SNR for analog-to-digital conversions using small reference voltage rails. Related Links 38. Electrical Characteristics 32.5.6 Selecting the Scanned Inputs All available analog inputs can be configured for scanning. Class 2 and Class 3 inputs are sampled using the shared ADC module. A single conversion trigger source is selected for all of the inputs selected for scanning using the STRGSRC[4:0] bits (ADCCON1[20:16]). On each conversion trigger, the ADC module starts converting (in the natural priority) all inputs specified in the user-specified scan list (ADCCSS1). For Class 2 and Class 3 inputs, the trigger initiates a sequential sample/conversion process in the natural priority order. An analog input belongs to the scan if it is:

A Class 3 input. For Class 3 inputs, scan is the only mechanism for conversion. A Class 2 input that has the scan trigger selected as the trigger source by selecting the STRIG option in the TRGSRCx[4:0] bits located in the ADCTRG1 and ADCTRG2 registers. The trigger options available for scan are identical to those available for independent triggering of Class 2 inputs. Any Class 2 inputs that are part of the scan must have the STRIG option selected as their trigger source in the TRGSRCx[4:0] bits. Note:The end-of-scan (EOS) is generated only if the last shared input conversion has completed. Until this condition is met, the scan sequence is still in effect. Therefore, the EOS Interrupt can be used for any scan sequence with any combination of input types. The following code is an example for ADC scanning multiple inputs. int main(int argc, char** argv) {

int result[3];

/* Configure ADCCON1 */

ADCCON1 = 0;

// CVD mode, Fractional mode and scan trigger source. ADCCON1bits.SELRES = 3; // ADC7 resolution is 12 bits ADCCON1bits.STRGSRC = 1; // Select scan trigger.

// No ADCCON1 features are enabled including: Stop-in-Idle, turbo,

/* Configure ADCCON2 */

ADCCON2bits.SAMC = 5; // ADC7 sampling time = 5 * TAD7 ADCCON2bits.ADCDIV = 1; // ADC7 clock freq is half of control clock = TAD7

/* Initialize warm up time register */ ADCANCON = 0;

ADCANCONbits.WKUPCLKCNT = 5; // Wakeup exponent = 32 * TAD7

/* Clock setting */

ADCCON3bits.ADCSEL = 0;

ADCCON3bits.CONCLKDIV = 1;

ADCCON3bits.VREFSEL = 0;

// Select input clock source

// Control clock frequency is half of input clock

// Select AVDD and AVSS as reference source ADC0TIMEbits.ADCDIV = 1;

ADC0TIMEbits.SAMC = 5;

ADC0TIMEbits.SELRES = 3;

// ADC0 clock frequency is half of control clock = TAD7

// ADC0 sampling time = 5 * TAD7

// ADC0 resolution is 12 bits

/* Select ADC input mode */

ADCIMCON1bits.SIGN0 = 0;

ADCIMCON1bits.DIFF0 = 0;

ADCIMCON1bits.SIGN7 = 0;

ADCIMCON1bits.DIFF7 = 0;

/* Configure ADCGIRQENx */

ADCGIRQEN1 = 0;

// unsigned data format

// Single ended mode

// unsigned data format

// Single ended mode

// No interrupts are used. ADCGIRQEN2 = 0;

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 819 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC)

/* Configure ADCCSSx */

ADCCSS1 = 0; // Clear all bits ADCCSS1bits.CSS0 = 1; // AN0 set for scan ADCCSS1bits.CSS7 = 1; // AN7 (Class 2) set for scan

/* Configure ADCCMPCONx */

ADCCMPCON1 = 0; // No digital comparators are used. Setting the ADCCMPCONx ADCCMPCON2 = 0; // register to '0' ensures that the comparator is disabled.

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // No oversampling filters are used. ADCFLTR2 = 0;

/* Set up the trigger sources */

ADCTRG1bits.TRGSRC0 = 3; // Set AN0 (Class 2) to trigger from scan source ADCTRG2bits.TRGSRC7 = 3; // Set AN7 (Class 2) to trigger from scan source

/* Turn the ADC on */ ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN7 = 1; // Enable, ADC7

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY0); // Wait until ADC0 is ready while(!

ADCANCONbits.WKRDY7); // Wait until ADC7 is ready

/* Enable the ADC module */

ADCCON3bits.DIGEN7 = 1; // Enable ADC7 while (1) {

/* Trigger a conversion */ ADCCON3bits.GSWTRG = 1;

/* Wait the conversions to complete */

while (ADCDSTAT1bits.ARDY0 == 0);

/* fetch the result */

result[0] = ADCDATA0;

while (ADCDSTAT1bits.ARDY7 == 0);

/* fetch the result */

result[1] = ADCDATA7;

* Process results here

return (1);

32.5.7 Selecting the Analog-to-Digital Conversion Clock Source and Prescaler The ADC module can use the internal Fast RC (FRC) oscillator output, system clock (SYS_CLK), reference clock

(REFO3) or peripheral bus clock (PB1_CLK) as the conversion clock source (TQ). See ADCCON3 register from Related Links. When the ADCSEL[1:0] bits (ADCCON2[31:30]) = 01, the internal FRC oscillator is used as the ADC clock source. When using the internal FRC oscillator, the ADC module can continue to function in Sleep and Idle modes. Note:It is recommended that applications that require precise timing of ADC acquisitions use SYS_CLK as the clock source for the ADC. For correct analog-to-digital conversions, the conversion clock limits must not be exceeded. Clock frequencies from 1 MHz to 32 MHz are supported by the ADC module. The maximum rate that analog-to-digital conversions may be completed by the ADC module (effective conversion throughput) is 2 Msps. However, the maximum rate that a single input can be converted is dependent on the sampling time requirements. In addition, the sampling time depends on the output impedance of the analog signal source. For more information on sampling time, see ADC Sampling Requirements from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 820 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) The input clock source for the ADC is selected using the ADCSEL[1:0] bits (ADCCON3[31:30]). The input clock is further divided by the control clock divider CONCLKDIV[5:0] bits (ADCCON3[29:24]). The output clock is called the ADC control clock with a time period of TQ. The ADC control clock is divided before it is used for the shared ADC by the ADCDIV[6:0] bits (ADCCON2[6:0]). The time period for this clock is denoted as TAD7. Figure 32-7. Clock Derivation for Shared ADC Modules Equation 32-1.Sample Time for the Shared ADC Module tSAMC = ADCCON2 < 25: 16 > TAD7 Equation 32-2.ADC Throughput Rate tconversion = 2 + ADCCON2 < 22: 21 > TAD7 Where, FTP = TAD7/ TSAMC + TCONV TAD7 = The frequency of the individual ADC module. 32.5.8 Turning ON the ADC Turning ON the ADC module involves the following procedure. When the ADC module enable bit, ON (ADCCON1[15]), is set to 1, the module is in Active mode and is fully powered and functional. When the ON bit is 0, the ADC module is disabled. Once disabled, the digital and analog portions of the ADC are turned off for maximum current savings. In addition to setting the ON bit, the analog and digital circuits of ADC must be turned ON. See Low-power Mode from Related Links. Note:Writing to the ADC control bits that control the ADC clock, input assignments, scanning, voltage reference selection, S&H circuit operating modes and interrupt configuration is not recommended while the ADC module is enabled. Related Links 32.8.3. Low-Power Mode 32.5.9 ADC Status Bits The ADC module includes the WKRDY7 status bit in the ADCANCON register, which indicates the current state of ADC Analog and bias circuit. The user application must not perform any ADC operations until this bit is set. 32.6 Additional ADC Functions This section describes some additional features of the ADC module, which includes:

Digital comparator Oversampling filter 32.6.1 Digital Comparator The ADC module features digital comparators that can be used to monitor selected analog input conversion results and generate interrupts when a conversion result is within the user-specified limits. Conversion triggers are still required to initiate conversions. The comparison occurs automatically once the conversion is complete. This feature is enabled by setting the Digital Comparator Module Enable bit, ENDCMP (ADCCMPCONx[7]). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 821 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) The user application makes use of an interrupt that is generated when the analog-to-digital conversion result is higher or lower than the specified high and low limit values in the ADCCMPx register. The high and low limit values are specified in the DCMPHI[15:0] bits (ADCCMPx[31:16]) and the DCMPLO[15:0] bits (ADCCMPx[15:0]). The CMPEx bits (x = 0 through 11) in the ADCCMPENx registers are used to specify which analog inputs are monitored by the digital comparator (for 12 analog inputs, ANx, where x = 0 through 11). The ADCCMPCONx register specifies the comparison conditions that generates an interrupt, as follows:

When IEBTWN = 1, an interrupt is generated when DCMPLO ADCDATA < DCMPHI When IEHIHI = 1, an interrupt is generated when DCMPHI ADCDATA When IEHILO = 1, an interrupt is generated when ADCDATA < DCMPHI When IELOHI = 1, an interrupt is generated when DCMPLO ADCDATA When IELOLO = 1, an interrupt is generated when ADCDATA < DCMPLO The comparator event generation is illustrated in the following figure. When the ADC module generates a conversion result, the conversion result is provided to the comparator. The comparator uses the DIFFx and SIGNx bits of the ADCIMCONx register (depending on the analog input used) to determine the data format used and to appropriately select whether the comparison must be signed or unsigned. The global ADC setting, which is specified by the FRACT bit (ADCCON1[23]), is also used to set the fractional or integer format. The digital comparator compares the ADC result with the high and low limit values (depending on the selected comparison criteria) in the ADCCMPx register. Depending on the comparator results, a digital comparator interrupt event may be generated. If a comparator event occurs, the Digital Comparator Interrupt Event Detected status bit, DCMPED (ADCCMPCONx[5]), is set, and the Analog Input Identification (ID) bits, AINID[4:0] (ADCCMPCONx[12:8]), are automatically updated so that the user application knows which analog input generated the interrupt event. Note:The user software must format the values contained in the ADCCMPx registers to match converted data format as either signed or unsigned, and fractional or integer. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 822 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Figure 32-8. Digital Comparator The following code is an example for ADC digital comparator. int main(int argc, char** argv) {

int result = 0, eventFlag = 0;

/* Configure ADCCON1 */

ADCCON1 = 0; // No ADCCON1 features are enabled including: Stop-in-Idle,

// turbo, CVD mode, Fractional mode and scan trigger source. ADCCON1bits.SELRES = 3; //

ADC resolution is 12 bits ADCCON1bits.STRGSRC = 0; // No scan trigger.

/* Configure ADCCON2 */

ADCCON2bits.SAMC = 5; // ADC7 sampling time = 5 * TAD7 ADCCON2bits.ADCDIV = 1; // ADC7 clock freq = TAD7

/* Initialize warm up time register */ ADCANCON = 0;

/* Select ADC input mode */

ADCIMCON1bits.SIGN7 = 0; // unsigned data format ADCIMCON1bits.DIFF7 = 0; // Single ended mode

/* Configure ADCGIRQENx */

ADCGIRQEN1 = 0; // No interrupts are used ADCGIRQEN2 = 0;

/* Configure ADCCSSx */

ADCCSS1 = 0; // No scanning is used 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 823 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC)

/* Configure ADCCMPCONx */

ADCCMP1 = 0; // Clear the register ADCCMP1bits.DCMPHI = 0xC00; // High limit is a 3072 result. ADCCMP1bits.DCMPLO = 0x500; // Low limit is a 1280 result. ADCCMPCON1bits.IEBTWN = 1; // Create an event when the measured result is

// >= low limits and < high limit. ADCCMPEN1 = 0; // Clear all enable bits ADCCMPEN1bits.CMPE8 = 1; // set the bit corresponding to AN8 ADCCMPCON1bits.ENDCMP = 1; // enable comparator

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // No oversampling filters are used. ADCFLTR2 = 0;

/* Set up the trigger sources */

ADCTRG2bits.TRGSRC7 = 3; // Set AN7 (Class 2) to trigger from scan source

/* Turn the ADC on */ ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN7 = 1; // Enable the clock to analog bias

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY7); // Wait until ADC7 is ready

/* Enable the ADC module */

ADCCON3bits.DIGEN7 = 1; // Enable ADC7 while (1) {

/* Trigger a conversion */ ADCCON3bits.GSWTRG = 1;

while (ADCDSTAT1bits.ARDY7 == 0);

/* fetch the result */

result = ADCDATA7;

/* Note: It is not necessary to fetch the result for the digital

* comparator to work. In this example we are triggering from

* software so we are using the ARDY8 to gate our loop. Reading the

* data clears the ARDY bit.

/* See if we have a comparator event*/

if (ADCCMPCON1bits.DCMPED == 1) {

eventFlag = 1;

* Process results here

return (1);

32.6.2 Oversampling Digital Filter The ADC module supports two oversampling digital filters. The oversampling digital filter consists of an accumulator and a decimator (down-sampler), which function together as a low-pass filter. By sampling an analog input at a higher-than-required sample rate, then processing the data through the oversampling digital filter, the effective resolution of the ADC module can be increased at the expense of decreased conversion throughput. To obtain x bits of extra resolution, the number of samples required (over and above the Nyquist rate) = (2x)2:

4x oversampling yields one extra bit of resolution (total 13 bits resolution) 16x oversampling yields two extra bits of resolution (total 14 bits resolution) 64x oversampling provides three extra bits of resolution (total 15 bits resolution) 256x oversampling provides four extra bits of resolution (total 16 bits resolution) The digital filter also has an averaging mode, where it accumulates the samples and divides it by the number of samples. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 824 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Note:

1. Only Class 2 analog inputs can engage the digital filter. Therefore, the CHNLID[2:0] bits are 3 bits wide (0 to 7). 2. During the burst conversion process (repeated trigger until all required data for oversampling is obtained), in the case of filtering Class 2 input using the shared ADC module, higher priority ADC inputs may still process conversions; lower priority ADC conversion requests are held waiting until the filter burst sequence is completed. If higher priority requests occur during the digital filter sequence, they delay the completion of the filtering process. This delay may affect the accuracy of the result because the multiple samples cannot be contiguous. The user must arrange the initiation trigger for the oversampling filters to occur while there are no expected interruptions from higher priority ADC conversion requests. 3. The user application must configure the following bits to perform an oversampling conversion:

Select the amount of oversampling through the Oversampling Filter Oversampling Ratio (OVRSAM[2:0]) bits in the ADC Filter register (ADCFLTRx[28:26]). Set the filter mode to either Oversampling mode or Averaging mode using the DFMODE bit(ADCFLTRx[29]). If the filter is set to Averaging mode and the data format is set to fractional (FRACT bit), set or clear the DATA16EN bit (ADCFLTRx[30]) to set the output resolution. Set the sample time for subsequent samples:

If using Class 2 inputs, select the sample time using the SAMC[9:0] bits (ADCCON2[25:16]). Select the specific analog input to be oversampled by configuring the Analog Input ID Selection bits, CHNLID[4:0] (ADCFLTRx[20:16]). If needed, include the oversampling filter interrupt event in the global ADC interrupt by setting the Accumulator Filter Global Interrupt Enable bit, AFGIEN (ADCFLTRx[25]). Enable the oversampling filter by setting the Oversampling Filter Accumulator Enable bit, AFEN

(ADCFLTRx[31]). When the digital filter module is configured, the filters control logic waits for an external trigger to initiate the process. The trigger signal for the analog input to be oversampled causes the accumulator to be cleared and initiates the first conversion. The trigger also forces the trigger sensitivity into level mode and forces the trigger itself to 1 as long as the filter needs to acquire the user-specified number of samples via the OVRSAM[2:0] bits (ADCFLTRx[28:26]). The time delay between each acquired sample is decided by the set sample time in the SAMC[9:0] bits in the ADCCON2 register for Class 2 and the time for conversion. When the required number set by OVRSAM[2:0] are received and processed, the data stored in the FLTRDATA[15:0] bit (ADCFLTRx[15:0]) and the AFRDY bit (ADCFLTRx[24]) is set and the interrupt is generated (if enabled). The following figure illustrates 4x oversampling using a Class 2 input. Triggering a Class 2 input initiates sampling for the length of time defined by the SAMC[9:0] bits. Retriggers generated by the oversampling logic use the SAMC[9:0]

bits to set the sample time. Class 2 inputs use the shared S&H; therefore, oversampling blocks lower priority Class 2 and Class 3 triggers. Higher priority Class 2 triggers completely disrupt the oversampling process; therefore, they must be avoided completely. The same priority rule applies to two Class 2 inputs that use two digital filters. In such a case, the higher priority input also uses the shared ADC module in Burst mode and prevents the lower priority input from using the shared ADC. Only after all required samples are obtained by the higher priority input can the lower priority input use the shared ADC to acquire samples for its own digital filtering. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 825 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Figure 32-9. 4x Oversampling of a Class 2 Input AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 The following code is an example for ADC digital oversampling filter. int main(int argc, char** argv) {

int result;

/* Configure ADCCON1 */

ADCCON1 = 0; // No ADCCON1 features are enabled including: Stop-in-Idle, turbo,

// CVD mode, Fractional mode and scan trigger source.

/* Initialize warm up time register */ ADCANCON = 0;

ADCANCONbits.WKUPCLKCNT = 5; // Wake-up exponent = 32 * TAD7

/* Clock setting */ ADCCON3 = 0;

ADCCON3bits.ADCSEL = 0; // Select input clock source ADCCON3bits.CONCLKDIV = 1; // Control clock frequency is half of input clock ADCCON3bits.VREFSEL = 0; // Select AVDD and AVSS as reference source ADCCON2bits.ADCDIV = 1; // ADC7 clock frequency is half of control clock = TAD7 ADCCON2bits.SAMC = 5; // ADC7 sampling time = 5 * TAD7 ADCCON1bits.SELRES = 3; // ADC7 resolution is 12 bits

/* Select ADC input mode */

ADCIMCON1bits.SIGN0 = 0; // unsigned data format ADCIMCON1bits.DIFF0 = 0; // Single ended mode

/* Configure ADCGIRQENx */

ADCGIRQEN1 = 0; // No interrupts are used ADCGIRQEN2 = 0;

/* Configure ADCCSSx */

ADCCSS1 = 0; // No scanning is used

/* Configure ADCCMPCONx */

ADCCMPCON1 = 0; // No digital comparators are used. Setting the ADCCMPCONx

/* Configure ADCFLTRx */

ADCFLTR1 = 0; // Clear all bits ADCFLTR1bits.CHNLID = 0; // Use AN0 as the source ADCFLTR1bits.OVRSAM = 3; // 16x oversampling ADCFLTR1bits.DFMODE = 0; //

Oversampling mode ADCFLTR1bits.AFEN = 1; // Enable filter 1 ADCFLTR2 = 0; // Clear all bits

/* Set up the trigger sources */ ADCTRGSNSbits.LVL0 = 0; // Edge trigger ADCTRG1bits.TRGSRC0 = 1; // Set AN0 to trigger from software.

/* Turn the ADC on */

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 826 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) ADCCON1bits.ON = 1;

/* Wait for voltage reference to be stable */

while(!ADCCON2bits.BGVRRDY); // Wait until the reference voltage is ready while(ADCCON2bits.REFFLT); // Wait if there is a fault with the reference voltage

/* Enable clock to analog circuit */

ADCANCONbits.ANEN0 = 1; // Enable the clock to analog bias and digital control

/* Wait for ADC to be ready */

while(!ADCANCONbits.WKRDY7); // Wait until ADC7 is ready

/* Enable the ADC module */ ADCCON3bits.DIGEN7 = 1; // Enable ADC7 while (1) {

/* Trigger a conversion */ ADCCON3bits.GSWTRG = 1;

/* Wait for the oversampling process to complete */

while (ADCFLTR1bits.AFRDY == 0);

/* fetch the result */

result = ADCFLTR1bits.FLTRDATA;

* Process result Here

* Note 1: Loop time determines the sampling time for the first sample.

* remaining samples sample time is determined by set sampling + conversion time.

* Note 2: The first 5 samples may have reduced accuracy.

return (1);

Figure 32-10. ADC Filter Comparisons Example 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 827 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.7 Interrupts The ADC module supports interrupts triggered from a variety of sources that can be processed individually or globally. An early interrupt feature is also available to compensate for interrupt servicing latency. After an enabled interrupt is generated, the CPU jumps to the vector assigned to that interrupt. The CPU begins executing code at the vector address. The user software at this vector address must perform the required operations, such as processing the data results, clearing the interrupt flag, then exiting. See Nested Vector Interrupt Controller

(NVIC) from Related Links for more information on interrupts and the vector address table details. 32.7.1 Interrupt Sources The ADC is capable of generating interrupts from the events listed in the following table. Table 32-4. ADC Interrupt Sources Interrupt Event Description Interrupt Enable Bit Interrupt Status Bit ANx Data Ready Event

(ADC_GIRQ) Digital Comparator Event

(ADC_DIRQ) Oversampling Filter Data Ready Event (ADC_AIRQ) Both Band Gap Voltage and ADC Reference Voltage Ready Event

(ADC_BGVR_RDY) Interrupt is generated upon a completion of a conversion from an analog input source (ANx). Each of the ARDYx bits is capable of generating a unique interrupt when set using the ADCBASE register. When an conversion's comparison criteria are met by a configured and enabled digital comparator. Each of the digital comparators is capable of generating a unique interrupt when its DCMPED bit is set. When an oversampling filter has completed the accumulation/

decimation process and has stored the result. Interrupt is generated when both band gap voltage and ADC reference voltage are ready. AGIENx of ADCGIRQEN1 ARDYx of ADCDSTAT1 register DCMPGIEN of ADCCMPCONx register DCMPED of ADCCMPCONx register AFGIEN of ADCFLTRx register AFRDY of ADCFLTRx register BGVRIEN of ADCCON2 register BGVRRDY of ADCCON2 register Band Gap Fault/Reference Voltage Fault/AVDD Brown-

out Fault Event (ADC_FLT) Interrupt is generated when Band Gap Fault/Reference Voltage Fault/

AVDD Brown-out occurs. REFFLTIEN of ADCCON2 register REFFLT of ADCCON2 register End of Scan Event

(ADC_FCC) Interrupt is generated when all the selected inputs have completed scan EOSIEN of ADCCON2 register EOSRDY of ADCCON2 register ADC Module Wake-up Event Interrupt is generated when ADC wakes up after being enabled. WKIEN7 of ADCANCON register WKRDY7 of ADCANCON register Update Ready Event Interrupt is generated when ADC SFRs are ready to be (and can be safely) updated with new values. UPDIEN of ADCCON3 register UPDRDY of ADCCON3 register 32.7.2 ADC Base Register (ADCBASE) Usage After conversion of ADC is complete, if the interrupt is vectored to a function that is common to all analog inputs, it takes some significant time to find the ADC input by evaluating the ARDYx bits in the ADCDSTATx. To avoid this time spent, the ADCBASE register is provided, which contains the base address of the users ADC ISR jump table. When read, the ADCBASE register provides a sum of the contents of the ADCBASE register plus an encoding of the 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 828 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) ARDYx bits set in the ADCDSTATx registers. This use of the ADCBASE register supports the creation of an interrupt vector address that can be used to improve the performance of an ISR. The ARDYx bits are binary priority encoded with ARDY0 being the highest priority and ARDY11 being the lowest priority. The encoded priority result is, then, shifted left the amount specified by the number of bit positions specified by the IRQVS[2:0] bits in the ADCCON1 register, then added to the contents of the ADCBASE register. If there are no ARDYx bits set, then reading the ADCBASE register equals the value written into the ADCBASE register. The ADCBASE register is typically loaded with the base address of a jump table that contains the address of the appropriate ISR. The kth interrupt request is enabled via the AGIENx bit (0-11) in ADCGIRQEN1. The following codes are examples for the ADCBASE register usage. Case 1:

ADCBASE = 0x1234; // Set the address ADCCON1bits.IRQVS = 2; // left shift by 2 ADCGIRQEN1bits.AGIEN0 = 1; // enable interrupt when AN0 completion is done. When the ADC conversion for AN0 is complete, bit 0 of ADCDSTAT1 = ARDY0 is set. Read value of ADCBASE = 0x1234 + (0 << 2) = 0x1234. Therefore, the ISR must be placed at address 0x1234 for AN0. Case 2:

ADCBASE = 0x1234; // Set the address ADCCON1bits.IRQVS = 2; // left shift by 2 ADCGIRQEN1bits.AGIEN0 = 2; // enable interrupt when AN2 completion is done. When the ADC conversion for AN2 is complete, bit 2 of ADCDSTAT1 = ARDY2 is set. Read value of ADCBASE = 0x1234 + (2 << 2) = 0x123C. Therefore, the ISR must be placed at address 0x123C for AN2. 32.7.3 32.7.4 Note:The contents of the ADCBASE register are not altered. Summation is performed when the ADCBASE register is read and the summation result is the returned read value from the ADCBASE SFR. Interrupt Enabling, Priority and Vectoring Each of the ADC events previously mentioned generates an interrupt when its associate Interrupt Enable bit. Each of the ADC events previously listed also has an associated interrupt vector. See Nested Vector Interrupt Controller from Related Links for more information on the vector location and control/status bits associated with each individual interrupt. Individual and Global Interrupts The use of the individual interrupts previously listed can significantly optimize the servicing of multiple ADC events by keeping each ISR focused on efficiently handling a specific event. In addition, different ISRs can be easily segregated according to the tasks performed, thereby making user software easier to implement and maintain. There may be cases where it is desirable to have a single ISR service multiple interrupt events. To facilitate this, each ADC event can be logically ORed to create a single global ADC interrupt. When an ADC event is enabled for a global interrupt, it vectors to a single interrupt routine. It is the responsibility of this single global ISR to determine the source of the interrupt through polling and process it accordingly. Use of the Global Interrupt requires configuration of its own unique ISER, IPR0, INTFLAG and configuration of its interrupt vector as described in Interrupt Enabling, Priority and Vectoring. See Nested Vector Interrupt Controller

(NVIC) from Related Links. Interrupts for the ADC can be configured as individual or global, or utilized as both where some are processed individually and others in the global ISR. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 829 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.8 Power-Saving Modes of Operation The Power-Saving, Standby Sleep and Idle modes are useful for reducing the conversion noise by minimizing the digital activity of the CPU, buses and other peripherals. 32.8.1 Standby Sleep Mode When the device enters Standby Sleep mode, the system clock (SYS_CLK) is halted. If an ADC module selects SYS_CLK as its clock source or selects REFO3 as its clock source (REFO3 is generated from SYS-CLK) and Standby Sleep mode occurs during a conversion, the conversion is aborted. The converter cannot resume a partially completed conversion on exiting from Sleep mode. The ADC register contents are not affected by the device entering or leaving Sleep mode. The ADC module can operate during Sleep mode if the ADC clock source is derived from a source other than SYS_CLK that is active during Sleep mode. The FRC clock source is a logical choice for operation during Sleep; however, the REFO3 clock source can also be used, provided it has an input clock that is operational during Sleep mode. ADC operation during Sleep mode reduces the digital switching noise from the conversion. When the conversion is completed, the ARDYx status bit for that analog input is set and the result is loaded into the corresponding ADC Result register (ADCDATAx). If any of the ADC interrupts are enabled, the device is woken up from Sleep mode when the ADC interrupt occurs. The program execution resumes at the ADC ISR if the ADC interrupt is greater than the current CPU priority. Otherwise, execution continues from the instruction after the WFI instruction that placed the device in Sleep mode. To minimize the effects of digital noise on the ADC module operation, the user must select a conversion trigger source that ensures that the analog-to-digital conversion take places in Sleep mode. For example, the external interrupt pin (INT0) conversion trigger option (TRGSRC[4:0] = 00100) can be used for performing sampling and conversion while the device is in Sleep mode. Note:For the ADC module to operate in Sleep mode, the ADC clock source must be set to Internal FRC

(ADCSEL[1:0] bits (ADCCON2[31:30]) = 01). Alternately, the REFO3 source can be used; however, the clock source used for REFO3 must operate during Sleep mode. Any changes to the ADC clock configuration require that the ADC be disabled. 32.8.2 Operation During Idle Mode For the ADC, the stop in Idle Mode bit, SIDL (ADCCON1[13]), specifies whether the ADC module stops on Idle or continues on Idle. If SIDL = 0, the ADC module continues normal operation when the device enters Idle mode. If any of the ADC interrupts are enabled, the device wakes up from Idle mode when the ADC interrupt occurs. The program execution resumes at the ADC ISR if the ADC interrupt is greater than the current CPU priority. Otherwise, execution continues from the instruction after the WAIT instruction that placed the device in Idle mode. If SIDL = 1, the ADC module stops in Idle mode. If the device enters Idle mode during a conversion, the conversion is aborted. The converter cannot resume a partially completed conversion on exiting from Idle mode. 32.8.3 Low-Power Mode The ADC module can be placed in a low-power state by disabling the digital circuit for individual ADC modules that are not running. This is possible by clearing the DIGEN7 bit in the ADCCON3 register. (See ADCCON3 register from Related Links.) An even lower power state is possible by disabling the analog and bias circuit for ADC module that is not running. This is possible by clearing the ANEN7 bit in the ADCANCON register. (See ADCANCON register from Related Links.) Disabling the digital circuit to achieve Low-Power mode provides a significantly faster module restart compared to disabling and re-enabling the analog and bias circuit of the ADC module. This is because disabling and re-enabling the analog and bias circuit using the ANEN7 bit requires a wake-up time (typical minimum wake-up time of 20 s) for the ADC module before it can be used. See Electrical Characteristics from Related Links for more information on the stabilization time. When the analog and bias circuit for an ADC module is enabled, the wake-up must be polled (or through an interrupt) using the wake-up ready bits, WKRDY7, which must be equal to 1. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 830 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Related Links 32.13.3. ADCCON3 32.13.20. ADCANCON 38. Electrical Characteristics 32.9 Effects of Reset Following any Reset event, all the ADC control and status registers are reset to their default values with control bits in a non-active state. This disables the ADC module and sets the analog input pins to Analog Input mode. Any conversion that was in progress terminates, and the result cannot be written to the result buffer. The values in the ADCDATAx registers are initialized to 0x00000000 during a device Reset. The bias circuits are also turned off, so the ADC resuming operations wait for the bias circuits to stabilize by polling (or requesting to be interrupted by) the BGVRRDY bit (ADCCON2 register). 32.10 Transfer Function A typical transfer function of the 12-bit ADC is illustrated in the following figure. The difference of the input voltages

(VINH - VINL) is compared with the reference (VREFH - VREFL). The first code transition (A) occurs when the input voltage is (VREFH - VREFL/8192) or 0.5 LSb. The 0000 0000 0001 code is centered at (VREFH - VREFL/4096) or 1.0 LSb (B). The 1000 0000 0000 code is centered at (2048 * (VREFH - VREFL)/4096) (C). An input voltage less than (1 * (VREFH - VREFL)/8192) converts as 0000 0000 0000 (D). An input greater than (8192 * (VREFH - VREFL)/8192) converts as 1111 1111 1111 (E). Figure 32-11. Analog-to-Digital Transfer Function 32.11 ADC Sampling Requirements The analog input model of the 12-bit ADC is illustrated in the following figure. The total acquisition time for the analog-to-digital conversion is a function of the internal circuit settling time and the holding capacitor charge time. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 831 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) For the ADC module to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The analog output source impedance (RS), the interconnect impedance (RIC) and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the CHOLD. The combined impedance of the analog sources must, therefore, be small enough to fully charge

(to within one-fourth LSB of the desired voltage) the holding capacitor within the selected sample time. The internal holding capacitor is in the discharged state prior to each sample operation. At least 1 TAD7 time period must be allowed between conversions for the acquisition time. See Electrical Characteristics from Related Links. Figure 32-12. 12-bit ADC Analog Input Model Note:The CPIN value depends on the device package and is not tested. The effect of the CPIN is negligible if Rs 5 k. Legend:

CPIN = Input capacitance RSS = Sampling switch resistance RS = Source resistance VT = Threshold voltage RIC = Interconnect resistance CHOLD = Sample/hold capacitance ILEAKAGE = Leakage current at the pin due to various junctions 32.11.1 Connection Considerations Because the analog inputs employ Electrostatic Discharge (ESD) protection, they have diodes to VDD and VSS;

therefore, the analog input must be between VDD and VSS. The presence of diodes is the reason why the analog pins cannot be 5V tolerant. If the input voltage exceeds this range by greater than 0.3V (either direction), one of the diodes becomes forward biased, and it may damage the device if the input current specification is exceeded. An external RC filter is sometimes added for antialiasing of the input signal. The R (resistive) component must be selected to ensure that the acquisition time is met. Any external components connected (through high-impedance) to an analog input pin (capacitor, Zener diode and so on) must have very little leakage current at the pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 832 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.12 Register Summary The register offsets shown below are with respect to Base Address = 0x4400_0000. The PIC32CX-BZ3 12-bit High Speed SAR ADC module has the following Special Function Registers (SFRs):

Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved Offset 0x00

... 0x13FF 0x1400 ADCCON1 0x1404

... 0x140F Reserved 0x1410 ADCCON2 0x1414

... 0x141F Reserved 0x1420 ADCCON3 0x1424

... 0x143F Reserved 0x1440 ADCIMCON1 0x1444

... 0x147F Reserved 0x1480 ADCGIRQEN1 0x1484

... 0x149F Reserved 0x14A0 ADCCSS1 0x14A4

... 0x14BF Reserved 0x14C0 ADCDSTAT1 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 IRQVS[2:0]

STRGLVL ON FRACT FRZ SIDL AIPMPEN CVD_EN FSYUPB SCANEN SELRES[1:0]

STRGSRC[4:0]

BGVRIEN REFFLTIEN EOSIEN ADCDIV[6:0]

SAMC[7:0]

BGVRRDY REFFLT EOSRDY CVD_CPL[2:0]

SAMC[9:8]

GLSWTRG GSWTRG ADINSEL[5:0]

VREFSEL[2:0]

TRGSUSP UPDIEN UPDRDY SAMP RQCNVRT DIGEN7 ADCSEL[1:0]

CONCLKDIV[5:0]

DIFF3 DIFF7 DIFF11 SIGN3 SIGN7 SIGN11 DIFF2 DIFF6 DIFF10 SIGN2 SIGN6 SIGN10 DIFF1 DIFF5 DIFF9 SIGN1 SIGN5 SIGN9 DIFF0 DIFF4 DIFF8 SIGN0 SIGN4 SIGN8 AGIEN7 AGIEN6 AGIEN5 AGIEN4 AGIEN3 AGIEN2 AGIEN11 AGIEN10 AGIEN1 AGIEN9 AGIEN0 AGIEN8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS11 CSS2 CSS10 CSS1 CSS9 CSS0 CSS8 ARDY7 ARDY6 ARDY5 ARDY4 ARDY3 ARDY11 ARDY2 ARDY10 ARDY1 ARDY9 ARDY0 ARDY8 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 833 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC)

...........continued Offset 0x14C4

... 0x14DF Name Bit Pos. 7 6 5 4 3 2 1 0 Reserved 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x14E0 ADCCMPEN1 0x14E4

... 0x14EF Reserved 0x14F0 ADCCMP1 0x14F4

... 0x14FF Reserved 0x1500 ADCCMPEN2 0x1504

... 0x150F Reserved 0x1510 ADCCMP2 0x1514

... 0x159F Reserved 0x15A0 ADCFLTR1 0x15A4

... 0x15AF Reserved 0x15B0 ADCFLTR2 0x15B4

... 0x15FF Reserved 0x1600 ADCTRG1 0x1604

... 0x160F Reserved 0x1610 ADCTRG2 0x1614

... 0x167F Reserved CMPEx[7:0]

CMPEx[11:8]

CMPEx[11:8]

DCMPLO[7:0]

DCMPLO[15:8]

DCMPHI[7:0]

DCMPHI[15:8]

CMPEx[7:0]

DCMPLO[7:0]

DCMPLO[15:8]

DCMPHI[7:0]

DCMPHI[15:8]

FLTRDATA[7:0]

FLTRDATA[15:8]

AFEN DATA16EN DFMODE OVRSAM[2:0]

AFGIEN AFRDY CHNLID[4:0]

AFEN DATA16EN DFMODE OVRSAM[2:0]

AFGIEN AFRDY FLTRDATA[7:0]

FLTRDATA[15:8]

CHNLID[4:0]

TRGSRC0[4:0]

TRGSRC1[4:0]

TRGSRC2[4:0]

TRGSRC3[4:0]

TRGSRC4[4:0]

TRGSRC5[4:0]

TRGSRC6[4:0]

TRGSRC7[4:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 834 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x1680 ADCCMPCON1 0x1684

... 0x168F Reserved 0x1690 ADCCMPCON2 0x1694

... 0x16FF Reserved 0x1700 ADCBASE 0x1704

... 0x173F Reserved 0x1740 ADCTRGSNS 0x1744

... 0x17FF Reserved 0x1800 ADCANCON 0x1804

... 0x1AFF Reserved 0x1B00 ADCSYSCFG0 0x1B04

... 0x1DFF Reserved 0x1E00 ADCDATA0

... 0x1E2C ADCDATA11 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO AINID[4:0]

CVD_DATA[7:0]

CVD_DATA[15:8]

ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO AINID[4:0]

ADCBASE[7:0]

ADCBASE[15:8]

LVL7 LVL6 LVL5 LVL4 LVL3 LVL2 LVL1 LVL0 ANEN7 WKRDY7 WKIEN7 WKUPCLKCNT[3:0]

AN[7:0]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

DATA[7:0]

DATA[15:8]

DATA[23:16]

DATA[31:24]

Related Links 5.4.1.9. CLR, SET and INV Registers 32.13 Register Description Following conventions are used in the register description:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 835 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 836 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.1 ADCCON1 ADC Control Register 1 Name:

Offset:

Reset:

Property:

ADCCON1 0x1400 0x00601000

This register controls the basic operation of the ADC module, including behavior in Sleep and Idle modes, and data formatting. This register also specifies the vector shift amounts for the Interrupt Controller. Bit 31 30 29 28 27 26 25 24 Access Reset Bit Access Reset Bit Access Reset 23 FRACT R/W 0 15 ON R/W 0 Bit 7 Access Reset 22 21 SELRES[1:0]

20 R/W 0 12 AIPMPEN R/W 0 R/W 1 13 SIDL R/W 0 5 IRQVS[2:0]

R/W 0 4 R/W 0 19 R/W 0 18 STRGSRC[4:0]

R/W 0 17 R/W 0 16 R/W 0 10 9 FSYUPB R/W 0 8 SCANEN R/W 0 2 1 0 11 CVD_EN R/W 0 3 STRGLVL R/W 0 R/W 0 14 FRZ R/W 0 6 R/W 0 Bit 23 FRACTFractional Data Output Format bit Value 0 1 Description Integer Fractional Bits 22:21 SELRES[1:0]Shared ADC Resolution bits Note:Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx register. The result occupies 12 bits, with the corresponding lower unused bits set to 0. For example, a resolution of 6 bits results in ADCDATAx[5:0] being set to 0 and ADCDATAx[11:6] holding the result. Value 11 10 01 00 Description 12 bits (default) 10 bits 8 bits 6 bits Bits 20:16 STRGSRC[4:0]ScanTrigger Source Select bits Value 10001 - 11111 10000 01111 01110 01101 01100 01011 01010 01001 Description Reserved EVSYS_51 EVSYS_50 EVSYS_49 EVSYS_48 EVSYS_47 EVSYS_46 EVSYS_45 EVSYS_44 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 837 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description EVSYS_43 EVSYS_42 EVSYS_41 EVSYS_40 INT0 External interrupt Reserved Global level software trigger (GLSWTRG) Global software edge trigger (GSWTRG) No Trigger Bit 15 ONADC Module Enable bit Note:The ON bit must be set only after the ADC module is configured. Value 0 1 Description ADC module is disabled ADC module is enabled Bit 14 FRZ Freeze in Debug Mode Value 0 1 Description Do not freeze in Debug mode Freeze in Debug mode Bit 13 SIDLStop in Idle Mode bit Description Continue module operation in Idle mode Discontinue module operation when device enters Idle mode Value 0 1 Bit 12 AIPMPENAnalog Input charge Pump Enable Note:The power-up/reset default value is 1b0. Bit 11 CVD_ENCVD Enable (Capacitive Voltage Division Enable) is the bit which enables and starts the CVD operation. The software must ensure that prior to enable CVD_EN. Notes:

1. 2. 3. 4. The shared ADC core is enabled and ready for conversions, i.e.ADCANCON.ANENx = 1b1 and ADCANCON.WKRDYx = 1b1 and ADCCON3.CHN_EN_SHR = 1b1. The software must disable all external triggers for all second class channels by setting the corresponding ADCTRGx.TRGSRCx[4:0] = 5h00 and also the third class scan trigger by setting ADCCONx.STRGSRC[4:0] =

5h00. The software must enable the ADCCSS1.CSSx channel scan select bits of all the channels to be included in the CVD scan. The software must set up the Digital Comparator 1 with the necessary comparison values in ADCCMP1 and the required setup in ADCCMPCON1 (enabling the comparator itself as well as its interrupt if desired). The register ADCCMPEN1 is irrelevant for the CVD operation. The Digital Comparator 1 will update its status field ADCCMPCON1.AINID[5:0] with the channel ID just finished for CVD only upon issuing an ADCCMPCON1.DCMPED interrupt signifying a detected touch event. When the CVD has accomplished its purpose (usually after an interrupt request from the Digital Comparator 1 signaling a touch event), the software must clear first the ADCCON3.DIGEN7 bit before clearing CVD_EN. After that, the software may set again ADCCON3.DIGEN7 and start normal A/D conversions on the shared ADC core for all second and third class channels. Bit 9 FSYUPBFast Synchronous UPB Clock bit Value 0 1 Description Fast synchronous UPB clock is disabled Fast synchronous UPB clock is enabled Bit 8 SCANENSCAN Enable bit 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 838 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 0 1 Description When this bit is cleared, the scan cycle is re-triggerable, which means that if an edge-sensitive scan trigger arrives in the middle of a current scan cycle, the current conversion completes but the rest of the current scan is aborted, the EOSRDY status bit is asserted and the scan cycle starts again from the beginning with the first channel included in the scan cycle. By setting this bit, the user disallows the scan trigger to re-start the current scan cycle and the current scan cycle will complete with its last included channel before getting re-started. Bits 6:4 IRQVS[2:0]Interrupt Vector Shift bits To determine the interrupt vector address, this bit specifies the amount of left-shift done to the ARDYx status bits in the ADCDSTAT1 and ADCDSTAT2 registers prior to adding with the ADCBASE register. Interrupt Vector Address = Read Value of ADCBASE, and Read Value of ADCBASE = Value written to ADCBASE +

x << IRQVS[2:0], where x is the smallest active input ID from the ADCDSTAT1 or ADCDSTAT2 registers (which has highest priority). Value 111 110 101 100 011 010 001 000 Description Shift x left 7 bit position Shift x left 6 bit position Shift x left 5 bit position Shift x left 4 bit position Shift x left 3 bit position Shift x left 2 bit position Shift x left 1 bit position Shift x left 0 bit position Bit 3 STRGLVLScanTrigger High Level/Positive Edge Sensitivity bit Value 0 1 Description Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), only a single scan trigger is generated, which completes the scan of all selected analog inputs. Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), the scan trigger continues for all selected analog inputs, until the STRIG option is removed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 839 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.2 ADCCON2 ADC Control Register 2 Name:

Offset:

Reset:

Property:

ADCCON2 0x1410 0x00000000

This register controls the reference selection for the ADC module, the sample time for the shared ADC module, interrupt enable for reference, early interrupt selection and clock division selection for the shared ADC. Bit 31 BGVRRDY R/HS/HC 0 Access Reset 30 REFFLT R/HS/HC 0 29 EOSRDY R/HS/HC 0 Bit 23 Access Reset R/W 0 22 R/W 0 21 R/W 0 Bit Access Reset 15 BGVRIEN R/W 0 14 REFFLTIEN R/W 0 13 EOSIEN R/W 0 Bit 7 Access Reset 6 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 4 R/W 0 27 CVD_CPL[2:0]

R/W 0 SAMC[7:0]

19 R/W 0 11 3 ADCDIV[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 2 R/W 0 SAMC[9:8]

25 R/W 0 17 R/W 0 9 1 24 R/W 0 16 R/W 0 8 0 R/W 0 R/W 0 Bit 31 BGVRRDYBand Gap Voltage/ADC Reference Voltage Status bit Data processing is valid only after BGVRRDY is set by hardware, so the application code must check that the BGVRRDY bit is set to ensure data validity. This bit set to 0 when ON (ADCCON1[15]) = 0. Value 0 1 Description Either or both band gap voltage and ADC reference voltages (VREF) are not ready Both band gap voltage and ADC reference voltages (VREF) are ready Bit 30 REFFLTBand Gap/VREF/AVDD BOR Fault Status bit This bit is cleared when the ON bit (ADCCON1[15]) = 0 and the BGVRRDY bit = 1. Value 0 1 Description Band gap and VREF voltage are working properly Fault in band gap or the VREF voltage while the ON bit (ADCCON1[15]) was set. Most likely a band gap or VREF fault is caused by a BOR of the analog VDDsupply. Bit 29 EOSRDYEnd of Scan Interrupt Status bit This bit is cleared when ADCCON2[31:24] are read in software. Value 0 1 Description Scanning has not completed All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 register) have completed scanning Bits 28:26 CVD_CPL[2:0]CVD Partly Line Capacitor Setting; Cpline = CVD_CPL[2:0] * 2.5 pF = 0 to 17.5 pF Bits 25:16 SAMC[9:0]SampleTime for the Shared ADC bits Where TAD7 = Period of the ADC conversion clock for the Shared ADC controlled by the ADCCON2.ADCDIV[6:0]

bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 840 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 11111111 11

... 00000000 01 00000000 00 Description 1025 TAD7 3 TAD7 2 TAD7 Bit 15 BGVRIENBand Gap/VREF Voltage Ready Interrupt Enable bit Value 0 1 Description No interrupt is generated when the BGVRRDY bit is set Interrupt is generated when the BGVRDDY bit is set Bit 14 REFFLTIENBand Gap/VREF Voltage Fault Interrupt Enable bit Value 0 1 Description No interrupt is generated when the REFFLT bit is set Interrupt is generated when the REFFLT bit is set Bit 13 EOSIENEnd of Scan Interrupt Enable bit Value 0 1 Description No interrupt is generated when the EOSRDY bit is set Interrupt is generated when the EOSRDY bit is set Bits 6:0 ADCDIV[6:0]Division Ratio for the Shared SAR ADC Core Clock bits Description 254 * TQ = TAD7 The ADCDIV[6:0] bits divide the ADC control clock (TQ) to generate the clock for the shared SAR ADC. Value 1111111

... 0000011 0000010 0000001 0000000 Reserved 6 * TQ = TAD7 4 * TQ = TAD7 2 * TQ = TAD7 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 841 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.3 ADCCON3 ADC Control Register 3 Name:

Offset:

Reset:

Property:

ADCCON3 0x1420 0x00000000

This register enables ADC clock selection, enables/disables the digital feature for the shared ADC module and controls the manual (software) sampling and conversion. Note:

1. The SAMP bit has the highest priority and setting this bit keeps the S&H circuit in Sample mode until the bit is cleared. Also, usage of the SAMP bit causes settings of SAMC[9:0] bits (ADCCON2[25:16]) to be ignored. The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and, only after setting the RQCNVRT bit, to start the analog-to-digital conversion. 2. 3. 4. Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx[4:0] bits and STRGSRC[4:0] bits must be set to 00000 to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal SAMP and with the software-controlled trigger RQCNVRT. Bit 31 30 ADCSEL[1:0]

Access Reset R/W 0 Bit Access Reset 23 DIGEN7 R/W 0 R/W 0 22 Bit 15 Access Reset R/W 0 14 VREFSEL[2:0]

R/W 0 Bit 7 GLSWTRG Access Reset R/W 0 6 GSWTRG R/W, HC 0 29 R/W 0 21 13 R/W 0 5 R/W 0 28 R/W 0 20 27 26 CONCLKDIV[5:0]

R/W 0 19 R/W 0 18 12 TRGSUSP R/W 0 11 UPDIEN R/W 0 10 UPDRDY R/HS/HC 0 4 R/W 0 3 2 ADINSEL[5:0]

R/W 0 R/W 0 25 R/W 0 17 9 SAMP R/W 0 1 R/W 0 24 R/W 0 16 8 RQCNVRT R/HS/HC 0 0 R/W 0 Bits 31:30 ADCSEL[1:0]Analog-to-Digital Clock Source (TCLK) bits Value 00 01 10 11 Description Peripheral Bus Clock (PB1_CLK) FRC Clock REFO3 Clock Output System Clock (SYS_CLK) Bits 29:24 CONCLKDIV[5:0]Analog-to-Digital Control Clock (TQ) Divider bits Value 111111

... 000011 000010 000001 000000 Description 64 * TCLK= TQ 4 * TCLK= TQ 3 * TCLK= TQ 2 * TCLK= TQ TCLK= TQ 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 842 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Bit 23 DIGEN7Shared ADC Digital Enable bit Value 1 0 Description ADC is digital enabled ADC is digital disabled Bits 15:13 VREFSEL[2:0]Voltage Reference (VREF) Input Selection bits Table 32-5. VREFSEL[2:0]

000 001-111 ADREF+

AVDD RESERVED FOR FUTURE USE ADREF-

AVSS Bit 12 TRGSUSPTrigger Suspend bit Value 1 0 Description Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled Triggers are not blocked Bit 11 UPDIENUpdate Ready Interrupt Enable bit Value 1 0 Description Interrupt is generated when the UPDRDY bit is set by hardware No interrupt is generated Bit 10 UPDRDYADC Update Ready Status bit Note:This bit is only active while the TRGSUSP bit is set and there are no more running conversions of any ADC modules. Value 1 0 Description ADC SFRs can be updated ADC SFRs cannot be updated Bit 9 SAMPClass 2 and Class 3 Analog Input Sampling Enable bit(1,2,3,4) Value 1 0 Description The ADC S&H amplifier is sampling The ADC S&H amplifier is holding Bit 8 RQCNVRTIndividual ADC Input Conversion Request bit This bit and its associated ADINSEL[5:0] bits enable the user to individually request an analog-to-digital conversion of an analog input through software. Note:This bit is automatically cleared in the next ADC clock cycle. Value 1 0 Description Trigger the conversion of the selected ADC input as specified by the ADINSEL[5:0] bits Do not trigger the conversion Bit 7 GLSWTRGGlobal Level Software Trigger bit Value 1 0 Description Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either through the associated TRGSRC[4:0] bits in the ADCTRGx registers or through the STRGSRC[4:0]bits in the ADCCON1 register Do not trigger an analog-to-digital conversion Bit 6 GSWTRGGlobal Software Trigger bit This bit is automatically cleared in the next ADC clock cycle. Value 0 Description Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either through the associated TRGSRC[4:0] bits in the ADCTRGx registers or through the STRGSRC[4:0]bits in the ADCCON1 register 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 843 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 1 Description Do not trigger an analog-to-digital conversion Bits 5:0 ADINSEL[5:0]Analog Input Select bits Description Reserved These bits select the analog input to be converted when the RQCNVRT bit is set. Value 111111

... 001011 001010 001001 001000 000111

... 000001 000000 VDD33/2(AN11) (Internal) VDD 1.2V(VDD_1V2(AN10)) (Internal) ADC Charge-pump 1.2V(CP_1V2(AN9)) (Internal) BandGap Reference (BG_VREF (AN8)) (Internal) AN7 is being monitored AN1 is being monitored AN0 is being monitored 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 844 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.4 ADCIMCON1 ADC Input Mode Control Register 1 Name:

Offset:

Reset:

Property:

ADCIMCON1 0x1440 0x00000000

This register enables the user to select between single-ended and differential operation as well as select between signed and unsigned data format. Bit 31 30 29 28 27 26 25 24 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 23 DIFF11 R/W 0 15 DIFF7 R/W 0 7 DIFF3 R/W 0 22 SIGN11 R/W 0 14 SIGN7 R/W 0 6 SIGN3 R/W 0 21 DIFF10 R/W 0 13 DIFF6 R/W 0 5 DIFF2 R/W 0 20 SIGN10 R/W 0 12 SIGN6 R/W 0 4 SIGN2 R/W 0 19 DIFF9 R/W 0 11 DIFF5 R/W 0 3 DIFF1 R/W 0 18 SIGN9 R/W 0 10 SIGN5 R/W 0 2 SIGN1 R/W 0 17 DIFF8 R/W 0 9 DIFF4 R/W 0 1 DIFF0 R/W 0 16 SIGN8 R/W 0 8 SIGN4 R/W 0 0 SIGN0 R/W 0 Bit 23 DIFF11AN11 Mode bit Value 1 0 Description AN11 is using Differential mode AN11 is using Single-ended mode Bit 22 SIGN11AN11 Signed Data Mode bit Value 1 0 Description AN11 is using Signed Data mode AN11 is using Unsigned Data mode Bit 21 DIFF10AN10 Mode bit Value 1 0 Description AN10 is using Differential mode AN10 is using Single-ended mode Bit 20 SIGN10AN10 Signed Data Mode bit Value 1 0 Description AN10 is using Signed Data mode AN10 is using Unsigned Data mode Bit 19 DIFF9AN9 Mode bit Value 1 0 Description AN9 is using Differential mode AN9 is using Single-ended mode Bit 18 SIGN9AN9 Signed Data Mode bit 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 845 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 1 0 Description AN9 is using Signed Data mode AN9 is using Unsigned Data mode Bit 17 DIFF8AN8 Mode bit Value 1 0 Description AN8 is using Differential mode AN8 is using Single-ended mode Bit 16 SIGN8AN8 Signed Data Mode bit Value 1 0 Description AN8 is using Signed Data mode AN8 is using Unsigned Data mode Bit 15 DIFF7AN7 Mode bit Value 1 0 Description AN7 is using Differential mode AN7 is using Single-ended mode Bit 14 SIGN7AN7 Signed Data Mode bit Value 1 0 Description AN7 is using Signed Data mode AN7 is using Unsigned Data mode Bit 13 DIFF6AN6 Mode bit Value 1 0 Description AN6 is using Differential mode AN6 is using Single-ended mode Bit 12 SIGN6AN6 Signed Data Mode bit Value 1 0 Description AN6 is using Signed Data mode AN6 is using Unsigned Data mode Bit 11 DIFF5AN5 Mode bit Value 1 0 Description AN5 is using Differential mode AN5 is using Single-ended mode Bit 10 SIGN5AN5 Signed Data Mode bit Value 1 0 Description AN5 is using Signed Data mode AN5 is using Unsigned Data mode Bit 9 DIFF4AN4 Mode bit Value 1 0 Description AN4 is using Differential mode AN4 is using Single-ended mode Bit 8 SIGN4AN4 Signed Data Mode bit Value 1 0 Description AN4 is using Signed Data mode AN4 is using Unsigned Data mode Bit 7 DIFF3AN3 Mode bit 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 846 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 1 0 Description AN3 is using Differential mode AN3 is using Single-ended mode Bit 6 SIGN3AN3 Signed Data Mode bit Value 1 0 Description AN3 is using Signed Data mode AN3 is using Unsigned Data mode Bit 5 DIFF2AN2 Mode bit Value 1 0 Description AN2 is using Differential mode AN2 is using Single-ended mode Bit 4 SIGN2AN2 Signed Data Mode bit Value 1 0 Description AN2 is using Signed Data mode AN2 is using Unsigned Data mode Bit 3 DIFF1AN1 Mode bit Value 1 0 Description AN1 is using Differential mode AN1 is using Single-ended mode Bit 2 SIGN1AN1 Signed Data Mode bit Value 1 0 Description AN1 is using Signed Data mode AN1 is using Unsigned Data mode Bit 1 DIFF0AN0 Mode bit Value 1 0 Description AN0 is using Differential mode AN0 is using Single-ended mode Bit 0 SIGN0AN0 Signed Data Mode bit Value 1 0 Description AN0 is using Signed Data mode AN0 is using Unsigned Data mode 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 847 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.5 ADCGIRQEN1 ADC Global Interrupt Enable Register 1 Name:

Offset:

Reset:

Property:

ADCGIRQEN1 0x1480 0x00000000

This register specifies which of the individual input conversion interrupts can generate the global ADC interrupt. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit Access Reset 7 AGIEN7 R/W 0 6 AGIEN6 R/W 0 5 AGIEN5 R/W 0 4 AGIEN4 R/W 0 11 AGIEN11 R/W 0 3 AGIEN3 R/W 0 10 AGIEN10 R/W 0 2 AGIEN2 R/W 0 9 AGIEN9 R/W 0 1 AGIEN1 R/W 0 8 AGIEN8 R/W 0 0 AGIEN0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 AGIENADC Global Interrupt Enable bits Value 1 0 Description Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (x = 8-1) of the ADCDSTAT1 register) Interrupts are disabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 848 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.6 ADCCSS1 ADC Common Scan Select Register 1 Name:

Offset:

Reset:

Property:

ADCCSS1 0x14A0 0x00000000

This register specifies the analog inputs to be scanned by the common scan trigger. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit Access Reset 7 CSS7 R/W 0 6 CSS6 R/W 0 5 CSS5 R/W 0 4 CSS4 R/W 0 11 CSS11 R/W 0 3 CSS3 R/W 0 10 CSS10 R/W 0 2 CSS2 R/W 0 9 CSS9 R/W 0 1 CSS1 R/W 0 8 CSS8 R/W 0 0 CSS0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 CSSAnalog Common Scan Select bits Notes:

1. 2. In addition to setting the appropriate bits in this register, Class 2 analog inputs must select the STRIG input as the trigger source if they are to be scanned through the CSSx bits. Refer to the bit descriptions in the ADCTRGx registers for selecting the STRIG option. If a Class 2 input is included in the scan by setting the CSSx bit to 1 and by setting the TRGSRCx[4:0] bits to STRIG mode (0b11), the user application must ensure that no other triggers are generated for that input using the RQCNVRT bit in the ADCCON3 register or the hardware input or any digital filter. Otherwise, the scan behavior is unpredictable. Value 1 0 Description Select ANx for input scan Skip ANx for input scan 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 849 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.7 ADCDSTAT1 ADC Data Ready Status Register 1 Name:

Offset:

Reset:

Property:

ADCDSTAT1 0x14C0 0x00000000

This register contains the interrupt status of the individual analog input conversions. Each bit represents the data-

ready status for its associated conversion result. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit Access Reset 7 ARDY7 R/HS/HC 0 6 ARDY6 R/HS/HC 0 5 ARDY5 R/HS/HC 0 4 ARDY4 R/HS/HC 0 11 ARDY11 R/HS/HC 0 3 ARDY3 R/HS/HC 0 10 ARDY10 R/HS/HC 0 2 ARDY2 R/HS/HC 0 9 ARDY9 R/HS/HC 0 1 ARDY1 R/HS/HC 0 8 ARDY8 R/HS/HC 0 0 ARDY0 R/HS/HC 0 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ARDYConversion Data Ready for Corresponding Analog Input Ready bits Value 1 0 Description This bit is set when converted data is ready in the data register This bit is cleared when the associated data register is read 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 850 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.8 ADCCMPEN1 ADC Digital Comparator 1 Enable Register Name:

Offset:

Reset:

Property:

ADCCMPEN1 0x14E0 0x00000000

These registers select which analog input conversion results is processed by the digital comparator. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 CMPEx[7:0]

4 R/W 0 Bits 11:0 CMPEx[11:0]ADC Digital Comparator x Enable bits Note:CMPEx = where "x" stands for bit value from 0 to 11. 11 R/W 0 3 R/W 0 10 9 CMPEx[11:8]

R/W 0 2 R/W 0 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 These bits enable conversion results corresponding to the analog input to be processed by the digital comparator. CMPE0 enables AN0, CMPE1 enables AN1 and so on. Notes:

1. CMPEx = ANx, where x = 0-11 (Digital Comparator inputs are limited to AN0 through AN11). 2. Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable behavior. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 851 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.9 ADCCMPEN2 ADC Digital Comparator 2 Enable Register Name:

Offset:

Reset:

Property:

ADCCMPEN2 0x1500 0x00000000

These registers select which analog input conversion results is processed by the digital comparator. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 Access Reset Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 CMPEx[7:0]

4 R/W 0 Bits 11:0 CMPEx[11:0]ADC Digital Comparator x Enable bits Note:CMPEx = where x stands for bit value from 0 to 11. 11 R/W 0 3 R/W 0 10 9 CMPEx[11:8]

R/W 0 2 R/W 0 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 These bits enable conversion results corresponding to the analog input to be processed by the digital comparator. CMPE0 enables AN0, CMPE1 enables AN1 and so on. Notes:

1. CMPEx = ANx, where x = 0-11 (Digital Comparator inputs are limited to AN0 through AN11). 2. Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable behavior. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 852 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.10 ADCCMP1 ADC Digital Comparator 1 Limit Value Register Name:

Offset:

Reset:

Property:

ADCCMP1 0x14F0 0x00000000

These registers contain the high and low digital comparison values for use by the digital comparator. Notes:

1. Changing theses bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable 2. 3. behavior. The format of the limit values must match the format of the ADC converted value in terms of sign and fractional settings. For Digital Comparator 1 used in CVD mode, the DCMPHI[15:0] and DCMPLO[15:0] bits must always be specified in signed format as the CVD output data is differential and is always signed. Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DCMPHI[15:8]

R/W 0 20 R/W 0 19 DCMPHI[7:0]

R/W 0 12 R/W 0 11 DCMPLO[15:8]

R/W 0 4 R/W 0 3 DCMPLO[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:16 DCMPHI[15:0]Digital Comparator x High Limit Value bits(1,2,3) These bits store the high limit value, which is used by digital comparator for comparisons with ADC converted data. Bits 15:0 DCMPLO[15:0]Digital Comparator x Low Limit Value bits(1,2,3) These bits store the low limit value, which is used by digital comparator for comparisons with ADC converted data. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 853 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.11 ADCCMP2 ADC Digital Comparator 2 Limit Value Register Name:

Offset:

Reset:

Property:

ADCCMP2 0x1510 0x00000000

These registers contain the high and low digital comparison values for use by the digital comparator. Notes:

1. Changing theses bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable 2. behavior. The format of the limit values must match the format of the ADC converted value in terms of sign and fractional settings. Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 DCMPHI[15:8]

R/W 0 20 R/W 0 19 DCMPHI[7:0]

R/W 0 12 R/W 0 11 DCMPLO[15:8]

R/W 0 4 R/W 0 3 DCMPLO[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:16 DCMPHI[15:0]Digital Comparator x High Limit Value bits(1,2,3) These bits store the high limit value, which is used by digital comparator for comparisons with ADC converted data. Bits 15:0 DCMPLO[15:0]Digital Comparator x Low Limit Value bits(1,2,3) These bits store the low limit value, which is used by digital comparator for comparisons with ADC converted data. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 854 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.12 ADCFLTR1 ADC Digital Filter 1 Register Name:

Offset:

Reset:

Property:

ADCFLTR1 0x15A0 0x00000000

These registers provide control and status bits for the oversampling filter accumulator, and also includes the 16-bit filter output data. Bit Access Reset 31 AFEN R/W 0 30 DATA16EN R/W 0 29 DFMODE R/W 0 Bit 23 22 21 Access Reset 28 R/W 0 20 R/W 0 27 OVRSAM[2:0]

R/W 0 26 R/W 0 19 R/W 0 18 CHNLID[4:0]

R/W 0 10 25 AFGIEN R/W 0 17 R/W 0 9 24 AFRDY R/W 0 16 R/W 0 8 Bit 15 14 13 12 11 FLTRDATA[15:8]

Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 7 6 5 4 3 FLTRDATA[7:0]

2 1 0 Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 31 AFENDigital Filter x Enable bit Value 1 0 Description Digital filter is enabled Digital filter is disabled and the AFRDY status bit is cleared Bit 30 DATA16ENFilter Significant Data Length bit Note:This bit is significant only if DFMODE = 1 (Averaging Mode) and FRACT (ADCCON1[23]) = 1 (Fractional Output Mode). Value 1 0 Description All 16 bits of the filter output data are significant Only the first 12 bits are significant, followed by four zeros Bit 29 DFMODEADC Filter Mode bit Value 1 0 Description Filter x works in Averaging mode Filter x works in Oversampling Filter mode (default) Value Bits 28:26 OVRSAM[2:0]Oversampling Filter Ratio bits Description If DFMODE is 0 128 samples (shift sum 3 bits to right, output data is in 15.1 format) 32 samples (shift sum 2 bits to right, output data is in 14.1 format) 8 samples (shift sum 1 bit to right, output data is in 13.1 format) 2 samples (shift sum 0 bits to right, output data is in 12.1 format) 256 samples (shift sum 4 bits to right, output data is 16 bits) 64 samples (shift sum 3 bits to right, output data is 15 bits) 111 110 101 100 011 010 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 855 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 001 000 111 110 101 100 011 010 001 000 Description 16 samples (shift sum 2 bits to right, output data is 14 bits) 4 samples (shift sum 1 bit to right, output data is 13 bits) If DFMODE is 1 256 samples (256 samples to be averaged) 128 samples (128 samples to be averaged) 64 samples (64 samples to be averaged) 32 samples (32 samples to be averaged) 16 samples (16 samples to be averaged) 8 samples (8 samples to be averaged) 4 samples (4 samples to be averaged) 2 samples (2 samples to be averaged) Bit 25 AFGIENDigital Filter x Interrupt Enable bit Value 1 0 Description Digital filter interrupt is enabled and is generated by the AFRDY status bit Digital filter is disabled Bit 24 AFRDYDigital Filter x Data Ready Status bit Note:This bit is cleared by reading the FLTRDATA[15:0] bits or by disabling the Digital Filter module (by setting AFEN to 0). Value 1 0 Description Data is ready in the FLTRDATA[15:0] bits Data is not ready Bits 20:16 CHNLID[4:0]Digital Filter Analog Input Selection bits Note:Only the first 8 analog inputs, Class 2 (AN0 -AN7), can use a digital filter. Description Reserved These bits specify the analog input to be used as the oversampling filter data source. Value 11111

... .. .. 00111

... .. .. 00010 00001 00000 AN2 AN1 AN0 AN7 Bits 15:0 FLTRDATA[15:0]Digital Filter x Data Output Value bits The filter output data is as per the fractional format set in the FRACT bit (ADCCON1[23]). The FRACT bit must not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation of the filter ended must not update the value of the FLTRDATA[15:0] bits to reflect the new format. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 856 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.13 ADCFLTR2 ADC Digital Filter 2 Register Name:

Offset:

Reset:

Property:

ADCFLTR2 0x15B0 0x00000000

These registers provide control and status bits for the oversampling filter accumulator, and also include the 16-bit filter output data. Bit Access Reset 31 AFEN R/W 0 30 DATA16EN R/W 0 29 DFMODE R/W 0 Bit 23 22 21 Access Reset 28 R/W 0 20 R/W 0 27 OVRSAM[2:0]

R/W 0 26 R/W 0 19 R/W 0 18 CHNLID[4:0]

R/W 0 10 25 AFGIEN R/W 0 17 R/W 0 9 24 AFRDY R/W 0 16 R/W 0 8 Bit 15 14 13 12 11 FLTRDATA[15:8]

Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 7 6 5 4 3 FLTRDATA[7:0]

2 1 0 Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 31 AFENDigital Filter x Enable bit Value 1 0 Description Digital filter is enabled Digital filter is disabled and the AFRDY status bit is cleared Bit 30 DATA16ENFilter Significant Data Length bit Note:This bit is significant only if DFMODE = 1 (Averaging Mode) and FRACT (ADCCON1[23]) = 1 (Fractional Output Mode). Value 1 0 Description All 16 bits of the filter output data are significant Only the first 12 bits are significant, followed by four zeros Bit 29 DFMODEADC Filter Mode bit Value 1 0 Description Filter x works in Averaging mode Filter x works in Oversampling Filter mode (default) Value Bits 28:26 OVRSAM[2:0]Oversampling Filter Ratio bits Description If DFMODE is 0 128 samples (shift sum 3 bits to right, output data is in 15.1 format) 32 samples (shift sum 2 bits to right, output data is in 14.1 format) 8 samples (shift sum 1 bit to right, output data is in 13.1 format) 2 samples (shift sum 0 bits to right, output data is in 12.1 format) 256 samples (shift sum 4 bits to right, output data is 16 bits) 64 samples (shift sum 3 bits to right, output data is 15 bits) 111 110 101 100 011 010 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 857 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 001 000 111 110 101 100 011 010 001 000 Description 16 samples (shift sum 2 bits to right, output data is 14 bits) 4 samples (shift sum 1 bit to right, output data is 13 bits) If DFMODE is 1 256 samples (256 samples to be averaged) 128 samples (128 samples to be averaged) 64 samples (64 samples to be averaged) 32 samples (32 samples to be averaged) 16 samples (16 samples to be averaged) 8 samples (8 samples to be averaged) 4 samples (4 samples to be averaged) 2 samples (2 samples to be averaged) Bit 25 AFGIENDigital Filter x Interrupt Enable bit Value 1 0 Description Digital filter interrupt is enabled and is generated by the AFRDY status bit Digital filter is disabled Bit 24 AFRDYDigital Filter x Data Ready Status bit Note:This bit is cleared by reading the FLTRDATA[15:0] bits or by disabling the Digital Filter module (by setting AFEN to 0). Value 1 0 Description Data is ready in the FLTRDATA[15:0] bits Data is not ready Bits 20:16 CHNLID[4:0]Digital Filter Analog Input Selection bits Note:Only the first 8 analog inputs, Class 2 (AN0-AN7), can use a digital filter. Description Reserved These bits specify the analog input to be used as the oversampling filter data source. Value 11111

... .. .. 01100 0111

... .. .. 00010 00001 00000 Reserved AN7 AN2 AN1 AN0 Bits 15:0 FLTRDATA[15:0]Digital Filter x Data Output Value bits The filter output data is as per the fractional format set in the FRACT bit (ADCCON1[23]). The FRACT bit must not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation of the filter ended must not update the value of the FLTRDATA[15:0] bits to reflect the new format. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 858 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.14 ADCTRG1 ADC Trigger Source 1 Register Name:

Offset:

Reset:

Property:

ADCTRG1 0x1600 0x00000000

This register controls the trigger source selection for AN0 through AN3 analog inputs. Bit 31 30 29 Access Reset Bit 23 22 21 Access Reset Bit 15 14 13 Access Reset Bit 7 6 5 Access Reset 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 TRGSRC3[4:0]

R/W 0 18 TRGSRC2[4:0]

R/W 0 10 TRGSRC1[4:0]

R/W 0 2 TRGSRC0[4:0]

R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 28:24 TRGSRC3[4:0]Trigger Source for Conversion of Analog Input AN3 Select bits Note:For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC[4:0] bits

(ADCCON1[20:16]) to select the trigger source, and requires the appropriate CSS bits to be set in the ADCCSSx registers. Value 10001 -

11111 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description Reserved EVSYS_51 EVSYS_50 EVSYS_49 EVSYS_48 EVSYS_47 EVSYS_46 EVSYS_45 EVSYS_44 EVSYS_43 EVSYS_42 EVSYS_41 EVSYS_40 INT0 External interrupt STRIG Global level software trigger (GLSWTRG) Global software edge trigger (GSWTRG) No Trigger Bits 20:16 TRGSRC2[4:0]Trigger Source for Conversion of Analog Input AN2 Select bits Note:See bits 28-24 for bit value definitions. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 859 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Bits 12:8 TRGSRC1[4:0]Trigger Source for Conversion of Analog Input AN1 Select bits Note:See bits 28-24 for bit value definitions. Bits 4:0 TRGSRC0[4:0]Trigger Source for Conversion of Analog Input AN0 Select bits Note:See bits 28-24 for bit value definitions. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 860 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.15 ADCTRG2 ADC Trigger Source 2 Register Name:

Offset:

Reset:

Property:

ADCTRG2 0x1610 0x00000000

This register controls the trigger source selection for AN4 through AN7 analog inputs. Bit 31 30 29 Access Reset Bit 23 22 21 Access Reset Bit 15 14 13 Access Reset Bit 7 6 5 Access Reset 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 TRGSRC7[4:0]

R/W 0 18 TRGSRC6[4:0]

R/W 0 10 TRGSRC5[4:0]

R/W 0 2 TRGSRC4[4:0]

R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 28:24 TRGSRC7[4:0]Trigger Source for Conversion of Analog Input AN7 Select bits Note:For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC[4:0] bits

(ADCCON1[20:16]) to select the trigger source, and requires the appropriate CSS bits to be set in the ADCCSSx registers. Value 10001 -

11111 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Description Reserved EVSYS_51 EVSYS_50 EVSYS_49 EVSYS_48 EVSYS_47 EVSYS_46 EVSYS_45 EVSYS_44 EVSYS_43 EVSYS_42 EVSYS_41 EVSYS_40 INT0 External interrupt STRIG Global level software trigger (GLSWTRG) Global software edge trigger (GSWTRG) No Trigger Bits 20:16 TRGSRC6[4:0]Trigger Source for Conversion of Analog Input AN6 Select bits Note:See bits 28-24 for bit value definitions. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 861 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Bits 12:8 TRGSRC5[4:0]Trigger Source for Conversion of Analog Input AN5 Select bits Note:See bits 28-24 for bit value definitions. Bits 4:0 TRGSRC4[4:0]Trigger Source for Conversion of Analog Input AN4 Select bits Note:See bits 28-24 for bit value definitions. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 862 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.16 ADCCMPCON1 ADC Digital Comparator 1 Control Register Name:

Offset:

Reset:

Property:

ADCCMPCON1 0x1680 0x00000000

This register controls the operation of Digital Comparator 1, including the generation of interrupts, comparison criteria to be used and provides status when a comparator event occurs. Bit 31 30 29 27 28 CVD_DATA[15:8]

26 25 24 Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 23 22 21 20 19 18 17 16 CVD_DATA[7:0]

Access Reset R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 R/HS/HC 0 Bit 15 14 13 12 11 Access Reset Bit Access Reset R/HS/HC 0 R/HS/HC 0 7 ENDCMP R/W 0 6 DCMPGIEN R/W 0 5 DCMPED R/HS/HC 0 4 IEBTWN R/W 0 3 IEHIHI R/W 0 10 AINID[4:0]

R/HS/HC 0 2 IEHILO R/W 0 9 8 R/HS/HC 0 R/HS/HC 0 1 IELOHI R/W 0 0 IELOLO R/W 0 Bits 31:16 CVD_DATA[15:0]CVD Differential Output Data In CVD mode this 16-bit field gets the CVD differential output data whenever a DCMPED interrupt is generated. The value in this field is ADCCON1.FRACT-compliant and ALWAYS signed, because it is the result of the subtraction between the CVD positive and negative measurements. Bits 12:8 AINID[4:0]Digital Comparator 1 Analog Input Identification (ID) bits Description Reserved When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being monitored by digital comparator 1. Value 11111

... .. .. 01011

... 01000 00111

... 00001 00000 AN8 is being monitored AN7 is being monitored AN1 is being monitored AN0 is being monitored AN11 is being monitored Bit 7 ENDCMPDigital Comparator 1 Enable bit Value 1 0 Description Digital comparator 1 is enabled Digital comparator 1 is not enabled, and the DCMPED status bit (ADCCMPCON[5]) is cleared Bit 6 DCMPGIENDigital Comparator 1 Global Interrupt Enable bit 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 863 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Value 1 0 Description A Digital comparator 1 interrupt is generated when the DCMPED status bit (ADCCMPCON[5]) is set A Digital comparator 1 interrupt is disabled Bit 5 DCMPEDDigital Comparator 1 Output True Event Status bit The logical conditions under which the digital comparator becomes True are defined by the IEBTWN, IEHIHI, IEHILO, IELOHI and IELOLO bits. Note:This bit is cleared by reading the AINID[4:0] bits or by disabling the Digital Comparator module (by setting ENDCMP to 0). Value 1 0 Description Digital comparator 1 output true event has occurred (output of comparator is 1) Digital comparator 1 output is false (output of comparator is 0) Bit 4 IEBTWNBetween Low/High Digital Comparator 1 Event bit Value 1 0 Description Generate a digital comparator event when DATA[31:0] is less than DCMPHI[15:0] AND greater than DCMPLO[15:0]

Do not generate a digital comparator event Bit 3 IEHIHIHigh/High Digital Comparator 1 Event bit Value 1 0 Description Generate a digital comparator 1 event when DCMPHI[15:0] bits are less than or equal to DATA[31:0]

bits Do not generate an event Bit 2 IEHILOHigh/Low Digital Comparator 1 Event bit Value 1 0 Description Generate a digital comparator 1 event when DATA[31:0] bits are less than DCMPHI[15:0] bits Do not generate an event Bit 1 IELOHILow/High Digital Comparator 1 Event bit Value 1 0 Description Generate a digital comparator 1 event when DCMPLO[15:0] bits are less than or equal to DATA[31:0]

bits Do not generate an event Bit 0 IELOLOLow/Low Digital Comparator 1 Event bit Value 1 0 Description Generate a digital comparator 1 event when DATA[31:0] bits are less than DCMPLO[15:0] bits Do not generate an event 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 864 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.17 ADCCMPCON2 ADC Digital Comparator 2 Control Register Name:

Offset:

Reset:

Property:

ADCCMPCON2 0x1690 0x00000000

These registers control the operation of Digital Comparator 2, including the generation of interrupts and the comparison criteria to be used. This register also provides the status when a comparator event occurs. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 Access Reset Bit Access Reset R/HS/HC 0 R/HS/HC 0 7 ENDCMP R/W 0 6 DCMPGIEN R/W 0 5 DCMPED R/HS/HC 0 4 IEBTWN R/W 0 3 IEHIHI R/W 0 10 AINID[4:0]

R/HS/HC 0 2 IEHILO R/W 0 9 8 R/HS/HC 0 R/HS/HC 0 1 IELOHI R/W 0 0 IELOLO R/W 0 Bits 12:8 AINID[4:0]Digital Comparator 2 Analog Input Identification (ID) bits Description Reserved AN11 is being monitored When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being monitored by the digital comparator. Value 11111 01011

... .. .. 00111

... 00001 00000 AN1 is being monitored AN0 is being monitored AN7 is being monitored Bit 7 ENDCMPDigital Comparator 2 Enable bit Value 1 0 Description Digital comparator 2 is enabled Digital comparator 2 is not enabled, and the DCMPED status bit is cleared Bit 6 DCMPGIENDigital Comparator 2 Global Interrupt Enable bit Value 1 0 Description Digital comparator 2 interrupt is generated when the DCMPED status bit is set Digital comparator 2 interrupt is disabled Bit 5 DCMPEDDigital Comparator 2 Output True Event Status bit The logical conditions where the digital comparator gets True are defined by the IEBTWN, IEHIHI, IEHILO, IELOHI and IELOLO bits. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 865 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Note:This bit is cleared by reading the AINID[4:0] bits or by disabling the Digital Comparator module (by setting ENDCMP to 0). Value 1 0 Description Digital comparator 2 output true event has occurred (output of comparator is 1) Digital comparator 2 output is false (output of comparator is 0) Bit 4 IEBTWNBetween Low/High Digital Comparator 2 Event bit Value 1 0 Description Generate a digital comparator event when DCMPLO[15:0] bits DATA[31:0] bits [DCMPHI[15:0] bits Do not generate a digital comparator event Bit 3 IEHIHIHigh/High Digital Comparator 2 Event bit Value 1 0 Description Generate a digital comparator 2 event when DCMPHI[15:0] bits are less than or equal to DATA[31:0]

bits Do not generate an event Bit 2 IEHILOHigh/Low Digital Comparator 2 Event bit Value 1 0 Description Generate a digital comparator 2 event when DATA[31:0] bits are less than DCMPHI[15:0] bits Do not generate an event Bit 1 IELOHILow/High Digital Comparator 2 Event bit Value 1 0 Description Generate a digital comparator 2 event when DCMPLO[15:0] bits are less than or equal to DATA[31:0]

bits Do not generate an event Bit 0 IELOLOLow/Low Digital Comparator 2 Event bit Value 1 0 Description Generate a digital comparator 2 event when DATA[31:0] bits are less than DCMPLO[15:0] bits Do not generate an event 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 866 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.18 ADCBASE ADC Base Register Name:

Offset:

Reset:

Property:

ADCBASE 0x1700 0x00000000

This register specifies the base address of the user ADC Interrupt Service Routine (ISR) jump table. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 ADCBASE[15:8]

R/W 0 4 R/W 0 3 ADCBASE[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 ADCBASE[15:0]ADCISR Base Address bits This register, when read, contains the base address of the user's ADC ISR jump table. The interrupt vector address is determined by the IRQVS[2:0] bits of the ADCCON1 register specifying the amount of left shift done to the ARDYx status bits in the ADCDSTAT1 register, prior to adding with ADCBASE register. Interrupt vector address = Read value of ADCBASE Read value of ADCBASE = Value written to ADCBASE + x << ADCCON1.IRQVS[2:0], where x is the smallest active analog input ID from the ADCDSTAT1 register (which has the highest priority). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 867 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.19 ADCTRGSNS ADC Trigger Level/Edge Sensitivity Register Name:

Offset:

Reset:

Property:

ADCTRGSNS 0x1740 0x00000000

This register contains the setting for trigger level for each ADC analog input. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset 7 LVL7 R/W 0 6 LVL6 R/W 0 5 LVL5 R/W 0 4 LVL4 R/W 0 3 LVL3 R/W 0 2 LVL2 R/W 0 1 LVL1 R/W 0 0 LVL0 R/W 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 LVLTrigger Level and Edge Sensitivity bits Notes:

1. 2. This register specifies the trigger level for analog inputs 0 to 7. The higher analog input ID belongs to Class 3, and, therefore, is only scan triggered. All Class 3 analog inputs use the scan trigger, for which the level/edge is defined by the STRGLVL bit (ADCCON1[3]). Value 1 0 Description Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high) Analog input is sensitive to the positive edge of its trigger (this is the value after a reset) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 868 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.20 ADCANCON ADC Analog Warm-up Control Register Name:

Offset:

Reset:

Property:

ADCANCON 0x1800 0x00000000

This register contains the warm-up control settings for the analog and bias circuit of the ADC module. Bit 31 30 29 28 Access Reset Bit 23 WKIEN7 Access Reset R/W 0 22 21 20 27 R/W 0 19 26 25 WKUPCLKCNT[3:0]

R/W R/W 0 0 18 17 Bit 15 14 13 12 11 10 WKRDY7 R/HS/HC 0 Access Reset Bit Access Reset 7 ANEN7 R/W 0 6 5 4 3 2 9 1 Bits 27:24 WKUPCLKCNT[3:0]Wake-up Clock Count bits 24 R/W 0 16 8 0 Description 215= 32,768 clocks These bits represent the number of ADC clocks required to warm-up the ADC module before it can perform conversion. Although the clocks are specific to each ADC, the WKUPCLKCNT bit is common to all ADC modules. Value 1111

... .. .. 0110 0101 0100 0011 0010 0001 0000 26= 64 clocks 25= 32 clocks 24= 16 clocks 24= 16 clocks 24= 16 clocks 24= 16 clocks 24= 16 clocks Bit 23 WKIEN7Shared ADC Wake-up Interrupt Enable bit Description Enable interrupt and generate interrupt when the WKRDY7 status bit is set Disable interrupt Value 1 0 Bit 15 WKRDY7Shared ADC Wake-up Status bit Note:This bit is cleared by hardware when the ANEN7 bit is cleared. Value 1 0 Description ADC Analog and bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting ANEN2 to 1 ADC Analog and bias circuitry is not ready 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 869 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) Bit 7 ANEN7Shared ADC Analog and Bias Circuitry Enable bit Value 1 0 Description Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs a warm-up time, as defined by the ADCANCON.WKUPCLKCNT[3:0] bits. Analog and bias circuitry disabled 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 870 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.21 ADCSYSCFG0 ADC System Configuration Register 0 Name:

Offset:

Reset:

Property:

ADCSYSCFG0 0x1B00 0x00000000

This register contains read-only bits corresponding to the analog input. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit Access Reset 7 R 0 6 R 0 5 R 0 4 R 0 AN[7:0]

3 R 0 2 R 0 9 1 R 0 8 0 R 0 Bits 7:0 AN[7:0]ADC Analog Input bits These bits reflect the system configuration and are updated during boot-up time. By reading these read-only bits, the user application can determine whether or not an analog input in the device is available. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 871 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog-to-Digital Converter (ADC) 32.13.22 ADCDATAx ADC Output Data Register (x = 0 to 11) Name:

Offset:

Reset:

Property:

ADCDATAx 0x1E00 + x*0x04 [x=0..11]

0x00000000

These registers are the analog-to-digital conversion output data registers. The ADCDATAx register is associated with each external analog input, 0-7, plus internal analog inputs 8-11. Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 R 0 21 R 0 13 R 0 5 R 0 DATA[31:24]

DATA[23:16]

DATA[15:8]

DATA[7:0]

28 R 0 20 R 0 12 R 0 4 R 0 27 R 0 19 R 0 11 R 0 3 R 0 26 R 0 18 R 0 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:0 DATA[31:0]ADC Converted Data Output bits Note:

1. Reading the ADCDATAx register value after changing the ADCCON1.FRACT bit converts the data into the format specified by the ADCCON1.FRACT bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 872 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33. Capacitive Voltage Divider (CVD) Controller 33.1 Overview The PIC32CX-BZ3 device family supports a hardware CVD controller, which supports enhanced CVD self, and self and mutual measurements. The enhanced CVD controller offloads the CPU by performing CVD scans with programmable phase timing and oversampling. Also, the enhanced CVD controller calculates the measurement deltas and detects the touches based on thresholds. 33.2 Features The key features of the Capacitive Voltage Divider (CVD) Controller module are:

Self measurement for basic touch detection. Supports upto eight RX/TX channels for touch measurements. AddCap control to optimize sensitivity on systems with small sample capacitors. Support for busing of multiple RX inputs and/or TX outputs for detecting touch over larger areas and algorithmically searching for touch location. Four Scan Descriptors control the scan settings to enable software controlled search algorithms by loading the next scan parameters while one is in progress. Oversampling of measurements to increase the signal-to-noise ratio. Ability to control the sequencing order of RX and TX scanning. Programmable thresholding to limit the data to the CPU to only those that exceed the set threshold. Supported in Standby Sleep and Idle mode. 33.3 Block Diagram Figure 33-1. Capacitive Voltage Divider (CVD) Controller Block Diagram Enhanced CVD Trigger Timer ADC Results ADC Core AddCap Pins with RX Function Pins with TX Function Pins with TX Function 33.4 CVD Module Operation The enhanced CVD uses the shared ADC SARCORE (See Analog-to-Digital Converter (ADC) from Related Links) for its operations. The enhanced CVD controller controls the shared ADC SARCORE in a simplified mode that supports only the needs of CVD, performing the full sequence of an oversampled CVD touch scan and associated math for self, and combination of self and mutual mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 873 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... The controller also controls pin functions needed for the CVD operations. Some of these pins provide RX functionality by having an analog. Some pins may have both RX and TX functions. The RX and TX pins connect to a matrix of button electrodes, a touch screen, or touch pad electrode grid with horizontal and vertical structures. To determine a touch or an approach, measure the capacitance of these electrodes. An AddCap module connects to the analog input net to augment the internal capacitance of the chip to match the base capacitance of the touch panel. A timer module provides the trigger signals. Related Links 32. Analog-to-Digital Converter (ADC) 33.4.1 Theory of Operation This section describes the full sequence of an oversampled CVD touch scan and associated math for self, and combination of self and mutual mode. 33.4.1.1 CVD Self Sensing Connect a capacitive sensor to one of the PIC32CX-BZ3 devices analog pins and then perform the sampling exclusively by manipulating the input or output ports, and the ADC. The following figure shows the waveform of CVD self sensing configuration. Figure 33-2. CVD Self Sensing Waveform ADC S&H Cap V DD Drive High Drive High Drive High Sample A e r a h S e g r a h C Sample B e r a h S e g r a h C e r a h S e g r a h C Sample A

... Drive Low Drive Low Drive Low GND Rx Pin Step 1: Precharge the Capacitors Charge the two capacitors to opposite voltages. First time charging of these capacitors are shown in the Sample A

(see, Figure 33-2) and the second time (described in Steps 4-6) is Sample B (see, Figure 33-2). Configurations of these samples are:

Sample A:

CVD Rx pin discharged to GND. ADC S and H capacitor charged to VDD. Sample B:

CVD Rx pin charged to VDD. ADC S and H capacitor discharged to GND. Step 2: Connect the Capacitors and Settle Connect the two capacitors in parallel and allow the charges to settle. As the external capacitance (CVD Rx Pin) increases, its initial charge (see, following equation) also increases. The internal capacitance (ADC S and H capacitor) does not change, therefore its charge remains constant. Equation 33-1.Precharge Stage Qbase = CbaseVbase Qold = ColdVold 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 874 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Where, Qbase is the total external charge. Qhold is the total internal charge. Vbase is the voltage provided to the external sensor during the precharge stage. Vhold is the voltage provided to the internal ADC hold capacitance during precharge. Cbase is the base external capacitance in the released state. Chold is the internal ADC capacitance for the sensor. Step 3: ADC Conversion Determine the final voltage on Choldby the size of the external capacitance (CVD Rx pin) in relation to the size of the internal capacitance (ADC S and H capacitor) (see following equation). Equation 33-2.Acquisition Stage Vsettle =

ColdVold + CbaseVbase Cold + Cbase Ctotal = Cold Cbase = Cold + Cbase Where, Qtotal = ColdVold + CbaseVbase Qtotal is the total charge on both capacitors when connected during the Acquisition stage. Ctotal is the total capacitance of the circuit during the Acquisition stage when both internal and external capacitors are connected and sharing charge. Vsettle is the final settling voltage during the Acquisition stage of a normal CVD waveform. Steps 4-6: Reverse the Precharge Voltages and Repeat Charge the capacitors, but during this time the precharge voltages are reversed. Use the difference between the two results as the current sensor reading. 33.4.1.2 CVD Self and Mutual Sensing The mutual drive signal (Tx pin) is a square wave that is driven high during all of Sample A, and low during all of Sample B. This signal aligns in-phase with the external sensors starting voltage for each sample. The following figure shows the waveform of CVD self and mutual sensing configuration. Figure 33-3. CVD Self and Mutual Sensing Waveform ADC S&H CapV V DD Drive High Drive High Drive High Sample A e r a h S e g r a h C Sample B e r a h S e g r a h C e r a h S e g g r a h C Sample A

... GND Tx Pin Rx Pin Drive Low Drive Low Drive Low Using the capacitive sensor measure the two effects when generating the CVD waveform:

Measure the capacitance of the sensor as normal due to the typical CVD waveform physics. Sample A increases in value when the ADC S and H capacitance decreases. Sample B decrease in value when the ADC S and H capacitance increases. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 875 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.4.2 Channel Sets The enhanced CVD module can control up to eight RX inputs and eight TX inputs. It enables the user to map up to eight specific CVDRx pins sequential RX indexes, and up to eight specific CVDTx pins to sequential TX indexes via Special Function Registers (SFRs). The actual pins used can therefore be in any order and with any gaps required. This enables the PCB designer to map I/O pins to panel RX/TX functions with greater ease. Each scan can span multiple RX/TX indexes via the STRIDE setting, enabling the user to scan multiple RX inputs in parallel, or drive multiple TX outputs in parallel. This is useful for doing full-panel touch detection or for performing a touch search algorithm. 33.4.2.1 RX/TX Striding The enhanced CVD employs the RX/TX striding to achieve the busing of multiple RX and/or TX pins together for a single measurement sequence. After programming the RX and TX indexes, user can configure a scan to run by simultaneously utilizing multiples of these indexes per measurement. For example, if the user has eight RX and four TX pins, and needs to scan four RX and two TX simultaneously. Performing a scan for the panel in groups, programs the RX stride to indicate four per measurement and programs the TX stride to indicate two per measurement. The scan then measures as mentioned in the following steps:

1. RX0-3/TX0-1 2. RX4-7/TX0-1 3. RX0-3/TX2-3, and so on. 33.4.2.2 Scan Descriptors The enhanced CVD module includes four scan descriptors to off-load the intervention requirements and timing dependencies of the CPU. Each scan descriptor includes the RX and TX indexes to be scanned and the strides for each, as well as the time for each measurement phase, the amount of oversampling, and a threshold at which to act on the data. Each descriptor indicates:

RX indexes to be scanned. TX indexes to be driven. Number of RX indexes to scan at one time. Number of TX indexes to scan at one time. Channel timing control. Oversampling or threshold support. Provision to enable an interrupt when complete or when threshold exceeds. The Enable mode settings to enable the single, continuous, or continuous until threshold scanning. Independent enable for Self (RX-drive), and combination of Self and Mutual modes. The scan descriptors can be set up to run just one time, run continuously until software intervention, or run continuously until the threshold is met. The four Scan Descriptors enables the software to maintain different scan settings for different regions or resolutions of the panel without having to swap previous description settings. For example: An application can set up Scan Descriptor Zero (SD0) to scan the panel in very large groups 16 RX and 16 TX (PIC32CX-BZ3 family of devices supports maximum 8) at a time. User can configure this Scan Descriptor (SD0) to scan continuously upon each external trigger until its threshold is met, then move on to the next enabled Scan Descriptor. The next scan descriptor can provide a higher resolution scan of only four RX and four TX at a time, with a different oversampling and different threshold. When the application code examines the result of the higher resolution scan, it can program third Scan Descriptor to scan at full resolution and oversampling a small area of the panel to zero-in on exactly where the touch was. Because it can zero-in with the third descriptor, it need not save the settings for the first and second ones, and does not need to re-load them later. The fourth descriptor enables the above to be done for a second simultaneous touch point. The Application code can ping-pong between SD2 and SD3 for as many simultaneous touch points as it supports. These four descriptors are part of the SFR register:

CVDSDnC1: CVD Scan Descriptor n Control 1, n = 0-3 CVDSDnC2: CVD Scan Descriptor n Control 2, n = 0-3 CVDSDnC3: CVD Scan Descriptor n Control 3, n = 0-3 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 876 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... CVDSDnT2: CVD Scan Descriptor n Time 2, n = 0-3 33.4.3 Oversampling A scan descriptor can program each measurement for any amount of oversampling from 0 to 127 additional samples. This accumulates all the samples into a 19-bit result. Do not perform division or averaging to prevent data loss and to enable non-power-of-two oversampling. 33.4.4 Phase Timing The user can tune the timing of the main 6-phases of the CVD measurement as per application needs. The Scan Descriptor holds time values for each of the following phases of the measurement cycle. Charge Acquire Conversion Spacing between polarity measurements Spacing between oversampling of same point(s) Spacing between channels 33.4.5 Thresholds Each Scan Descriptor specifies a threshold value. If the application wishes to receive all the accumulated oversample data, it can set the threshold to zero. Otherwise, the Scan Descriptor can be set to only store data that exceeds the requested threshold, or to store all data and assert an interrupt only when the threshold is met. 33.4.6 Interrupts Configure the enhanced CVD to cause an interrupt when the FIFO exceeds a programmed threshold and/or when a scan descriptor exceeds a threshold and/or completes its function. Note:FIFO threshold interrupt is not supported in the Standby Sleep mode. 33.4.7 Triggers The enhanced CVD can be set to start the enabled Scan Descriptors upon two possible trigger events. One is a software trigger SFR bit and another trigger is from any of EVSYS generators. See Event System (EVSYS) from Related Links. If a scan descriptor is set to run in the continuous mode, it runs when it receives a trigger and stays enabled. The CVD module then waits for the next trigger to run the next enabled scan descriptor. Alternatively, the scan descriptor may instruct the CVD module to continue scanning the one descriptor on every trigger until a threshold is met. These modes allow the CVD module to run autonomously being triggered by a system timer while the CPU sleeps (Idle, Standby Sleep), and interrupt the CPU to wake it if a tough threshold is reached. The first mode is useful for scanning various portions of the panel at regular intervals. The second mode is useful for scanning a low-resolution scan on every trigger, then moving to a higher resolution scan descriptor if a threshold is met. Related Links 26. Event System (EVSYS) 33.4.8 FIFO Results are stored in a FIFO with a depth of 8 word. The FIFO contains the accumulated result data and the TX and RX indexes for that data. The user can configure the CVD module to store all accumulated results into the FIFO, or only results that exceed the threshold specified in the scan descriptor. In either case, user can generate an interrupt when the FIFO exceeds a watermark value. The application has the choice of reading out, Only a single 32-bit word that contains the RX and TX indexes and the delta of the positive and negative accumulated CVD measurements. A total of three 32-bit words to read the actual positive and negative CVD measurement along with delta. The FIFO uses following registers:

33.6.4. CVDRESH: CVD Results POS FIFO Read Register 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 877 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.5. CVDRESL: CVD Results NEG FIFO Read Register 33.6.6. CVDRESD: CVD Results Descriptor FIFO Read Register 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 878 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.5 Register Summary See CVD module in the Product Memory Mapping Overview from Related Links for base address. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 0x00 CVDCON 0x04 CVDADC 0x08 CVDSTAT 0x0C

... 0x0F Reserved 0x10 CVDRESH 0x14 CVDRESL 0x18 CVDRESD 0x1C

... 0x7F Reserved 0x80 CVDRX0 0x84 CVDRX1 0x88

... 0xBF Reserved 0xC0 CVDTX0 0xC4 CVDTX1 0xC8

... 0xFF Reserved THSTR ON CLKSEL[1:0]

TRIGSEL[3:0]

FIFOTH[7:0]

CVDIEN FIFOIEN FIFOTH[9:8]

FRZ SIDL ORDER SDWREN ABORT SWTRIG DIGEN DIFFPEN SELRES[1:0]

SD2INT SD4INT SD2DONE SD2BUSY SD4DONE SD4BUSY SD1INT SD3INT SD1DONE SD1BUSY SD3DONE SD3BUSY FIFOCNT[7:0]

FIFOFULL FIFOWM FIFOMT FIFOCNT[9:8]

POS[7:0]

POS[15:8]

NEG[7:0]

NEG[15:8]

DELTA[7:0]

DELTA[15:8]

POS[18:16]

NEG[18:16]

RXINDEX[4:0]

TXINDEX[4:0]

DELTA[17:16]

SDNUM[1:0]

RXAN0[5:0]

RXAN1[5:0]

RXAN2[5:0]

RXAN3[5:0]

RXAN4[5:0]

RXAN5[5:0]

RXAN6[5:0]

RXAN7[5:0]

TXAN0[5:0]

TXAN1[5:0]

TXAN2[5:0]

TXAN3[5:0]

TXAN4[5:0]

TXAN5[5:0]

TXAN6[5:0]

TXAN7[5:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 879 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... ..........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x0100 CVDSD0C1 0x0104 CVDSD0C2 0x0108 CVDSD0C3 0x010C CVDSD0T2 0x0110 CVDSD1C1 0x0114 CVDSD1C2 0x0118 CVDSD1C3 0x011C CVDSD1T2 0x0120 CVDSD2C1 0x0124 CVDSD2C2 0x0128 CVDSD2C3 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 SD0RXSTRID E SD0RXSTRID E SD0RXSTRID E SD0RXSTRID E SD0TXSTRID E SD0TXSTRID E SD0TXSTRID E SD0TXSTRID E SD0OVRSAMP[6:0]

SD0TH[7:0]

SD0TH[15:8]

SD0TH[23:16]

SD0RXBEG[5:0]

SD0RXEND[5:0]

SD0TXBEG[5:0]

SD0TXEND[5:0]

SD0CHGTIME[6:0]

SD0ACQTIME[6:0]

SD0EN[1:0]

CVDEN CVDCPL[2:0]

SD0BUF SD0INTEN SD0SELF SD0MUT SD0CONTIME[6:0]

SD0POLTIME[6:0]

SD0OVRTIME[6:0]

SD0CHNTIME[6:0]

SD1OVRSAMP[6:0]

SD1TH[7:0]

SD1TH[15:8]

SD1TH[23:16]

SD1RXBEG[5:0]

SD1RXEND[5:0]

SD1TXBEG[5:0]

SD1TXEND[5:0]

SD1CHGTIME[6:0]

SD1ACQTIME[6:0]

SD1RXSTRID E SD1RXSTRID E SD1RXSTRID E SD1RXSTRID E SD1TXSTRID E SD1TXSTRID E SD1TXSTRID E SD1TXSTRID E SD1EN[1:0]

CVDEN CVDCPL[2:0]

SD1BUF SD1INTEN SD1SELF SD1MUT SD1CONTIME[6:0]

SD1POLTIME[6:0]

SD1OVRTIME[6:0]

SD1CHNTIME[6:0]

SD2OVRSAMP[6:0]

SD2TH[7:0]

SD2TH[15:8]

SD2TH[23:16]

SD2RXBEG[5:0]

SD2RXEND[5:0]

SD2TXBEG[5:0]

SD2TXEND[5:0]

SD2CHGTIME[6:0]

SD2ACQTIME[6:0]

SD2RXSTRID E SD2RXSTRID E SD2RXSTRID E SD2RXSTRID E SD2TXSTRID E SD2TXSTRID E SD2TXSTRID E SD2TXSTRID E SD2EN[1:0]

CVDEN CVDCPL[2:0]

SD2BUF SD2INTEN SD2SELF SD2MUT 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 880 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... ..........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x012C CVDSD2T2 0x0130 CVDSD3C1 0x0134 CVDSD3C2 0x0138 CVDSD3C3 0x013C CVDSD3T2 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 SD2CONTIME[6:0]

SD2POLTIME[6:0]

SD2OVRTIME[6:0]

SD2CHNTIME[6:0]

SD3OVRSAMP[6:0]

SD3TH[7:0]

SD3TH[15:8]

SD3TH[23:16]

SD3RXBEG[5:0]

SD3RXEND[5:0]

SD3TXBEG[5:0]

SD3TXEND[5:0]

SD3CHGTIME[6:0]

SD3ACQTIME[6:0]

SD3RXSTRID E SD3RXSTRID E SD3RXSTRID E SD3RXSTRID E SD3TXSTRID E SD3TXSTRID E SD3TXSTRID E SD3TXSTRID E SD3EN[1:0]

CVDEN CVDCPL[2:0]

SD3BUF SD3INTEN SD3SELF SD3MUT SD3CONTIME[6:0]

SD3POLTIME[6:0]

SD3OVRTIME[6:0]

SD3CHNTIME[6:0]

Related Links 7. Product Memory Mapping Overview 33.6 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. See Peripheral Access Controller (PAC) from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the Enable-protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared Related Links 20. Peripheral Access Controller (PAC) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 881 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.1 CVDCON - CVD Control Register Name:

Offset:

Reset:

Property:

CVDCON 0x00 0x00020000

25 ABORT W/HC 0 24 SWTRIG W/HC 0 17 16 FIFOTH[9:8]

Bit Access Reset Bit Access Reset 31 ON R/W 0 23 THSTR R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 30 FRZ R/W 0 22 14 R/W 0 6 29 SIDL R/W 0 21 13 R/W 0 5 28 ORDER R/W 0 20 27 SDWREN R/W 0 19 CVDIEN R/W 0 12 11 FIFOTH[7:0]

R/W 0 4 CLKSEL[1:0]

R/W 0 R/W 0 R/W 0 3 R/W 0 26 18 FIFOIEN R/W 0 10 R/W 0 2 R/W 1 9 R/W 0 1 TRIGSEL[3:0]

R/W 0 R/W 0 R/W 0 8 R/W 0 0 R/W 0 Bit 31 ONEnables the State Machine to scan the enabled Scan Descriptors upon next trigger Before turning ON bit from 1b1 to 1b0, the Scan Enable bits of all descriptors must be cleared and the CVD controller must either be allowed to finish any scan in progress, or must be instructed to abort the scan with the ABORT bit. Bit 30 FRZFreeze Mode Value 1 0 Description CVD controller stops in the debugger mode CVD controller runs in debugger mode Bit 29 SIDLStop in Idle Mode bit Description CVD controller stops when device enters Idle mode CVD controller continues running in Idle mode Value 1 0 Bit 28 ORDERRX/TX Loop Order Description Scans all the requested TX indexes, then increments RX index and continues operation Scans all the requested RX indexes, then increments TX index and continues operation Value 1 0 Bit 27 SDWRENScan Descriptor Write Enable Value 1 0 Description Enables writes to the scan descriptors Prevents writes to the scan descriptors Bit 25 ABORTAbort Current Scan Note:The controller moves on to the next enabled Scan Descriptor if there is one, else it goes to idle state. Hardware clears this bit. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 882 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Value 1 0 Description Aborts the current scan CVD controller continues with the current scan Bit 24 SWTRIGSoftware Trigger control. Starts scan manually Note:Hardware clears this bit. Value 1 0 Description Starts scan manually Continues without the scan Bit 23 THSTRThreshold Store Mode Value 1 0 Description Stores only the results which exceed the programmed threshold for the Scan Descriptor Stores all the results in FIFO Bit 19 CVDIENGlobal Interrupt Enable Value 1 0 Description Enables the FIFO and scan descriptor interrupts Disables the FIFO and scan descriptor interrupts Bit 18 FIFOIENFIFO Threshold Interrupt Enable Value 1 0 Description Controller asserts an interrupt when the FIFO threshold is met Controller does not assert an interrupt when the FIFO threshold is met Bits 17:8 FIFOTH[9:0]Threshold for the results FIFO These bits contain threshold for the results FIFO that causes an interrupt and watermark FIFOWM status bit assertion. Bits 5:4 CLKSEL[1:0]Clock Select for CVD Value 00 01 02 03 Description PB1_CLK POSC LPRC Reserved Bits 3:0 TRIGSEL[3:0]Trigger select for starting the scan Description SFR controlled software trigger EVSYS event. See Event System (EVSYS) from Related Links. Value 0000 0001

... .. .. 1111 Reserved Related Links 26. Event System (EVSYS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 883 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.2 CVD ADC Configuration Register Name:

Offset:

Reset:

Property:

CVDADC 0x04 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 Access Reset Bit 7 6 5 4 Access Reset Bit 3 DIGEN 3 DIGEN R/W 0 2 DIFFPEN R/W 0 Shared ADC Digital Enable bit (Differential Mode Select from ADC controller) Value 1 0 Description Shared ADC is digital enabled Shared ADC is digital disabled 9 1 8 0 SELRES[1:0]

R/W 0 R/W 0 Bit 2 DIFFPEN Controls differential mode operation of ANN0. Value 1 0 Description ANN0 (Differential) enabled ANN0 (Differential) disabled Bits 1:0 SELRES[1:0]Shared ADC Resolution bits Read as 0. Note:Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx register. The result will still occupy 12 bits, with the corresponding lower unused bits set to 0. For example, a resolution of 6 bits will result in ADCDATAx[5:0] being set to 0, and ADCDATAx[11:6] holding the result. Value 00 01 10 11 Description 6 bits 8 bits 10 bits 12 bits (default) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 884 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 28 27 26 25 24 FIFOCNT[9:8]

R 0 17 R 0 9 SD3DONE R 0 1 SD1DONE R 0 R 0 16 R 0 8 SD3BUSY R 0 0 SD1BUSY R 0 18 R 0 10 SD3INT R/W/HS 0 2 SD1INT R/W/HS 0 33.6.3 CVD Status Register Name:

Offset:

Reset:

Property:

CVDSTAT 0x08 0x20000000

Bit Access Reset 31 FIFOFULL R 0 30 FIFOWM R 0 29 FIFOMT R 1 23 R 0 15 Bit Access Reset Bit Access Reset Bit 7 Access Reset 22 R 0 14 SD4INT R/W/HS 0 6 SD2INT R/W/HS 0 21 R 0 13 SD4DONE R 0 5 SD2DONE R 0 20 19 FIFOCNT[7:0]

R 0 11 3 R 0 12 SD4BUSY R 0 4 SD2BUSY R 0 Bit 31 FIFOFULLResults FIFO is full Value 1 0 Description FIFO is full Not full Bit 30 FIFOWM Value 1 0 Bit 29 FIFOMT Value 1 0 Description FIFO has reached the programmed FIFOTHRESH threshold FIFO has not reached the programmed FIFOTHRESH threshold Description FIFO is empty FIFO is not empty Bits 25:16 FIFOCNT[9:0]

These bits indicate the number of words in the Results FIFO. Bit 14 SD4INT Value 1 0 Bit 13 SD4DONE Description Scan Descriptor 4 has caused an interrupt Scan Descriptor 4 has not caused an interrupt Note:The hardware will clear this bit upon receiving next trigger for Scan Descriptor 4. Value 1 0 Description Scan Descriptor 4 has completed at least once Scan Descriptor 4 has not completed 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 885 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Bit 12 SD4BUSY Value 1 0 Description Scan Descriptor 4 is in progress Scan Descriptor 4 is not in progress Bit 10 SD3INT Value 1 0 Bit 9 SD3DONE Description Scan Descriptor 3 has caused an interrupt Scan Descriptor 3 has not caused an interrupt The controller sets this bit if Scan Descriptor 3 completes at least once. Core clears this bit upon receiving next trigger for Scan Descriptor 3. Bit 8 SD3BUSY Value 1 0 Bit 6 SD2INT Description Scan Descriptor 3 is in progress Scan Descriptor 3 is not in progress Value 1 0 Description Scan Descriptor 2 has caused an interrupt Scan Descriptor 2 has not caused an interrupt Bit 5 SD2DONEThe controller sets this bit if Scan Descriptor 2 completes at least once. Core clears this bit upon receiving next trigger for Scan Descriptor 2. Bit 4 SD2BUSY Value 1 0 Description Scan Descriptor 2 has caused an interrupt Scan Descriptor 2 has not caused an interrupt Bit 2 SD1INTScan Descriptor 1 has caused an interrupt Description Scan Descriptor 1 has caused an interrupt Scan Descriptor 1 has not caused an interrupt Value 1 0 Bit 1 SD1DONEThe controller sets this bit if Scan Descriptor 1 has completed at least once. Core clears this bit upon receiving next trigger for Scan Descriptor 1. Bit 0 SD1BUSYScan Descriptor 1 is in progress Value 1 0 Description Scan Descriptor 1 is in progress Scan Descriptor 1 is not in progress 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 886 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.4 CVD Results POS FIFO Read Register Name:

Offset:

Reset:

Property:

CVDRESH 0x010 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 Bits 18:0 POS[18:0]

14 R 0 6 R 0 13 R 0 5 R 0 POS[15:8]

POS[7:0]

12 R 0 4 R 0 11 R 0 3 R 0 18 R 0 10 R 0 2 R 0 17 POS[18:16]

R 0 9 R 0 1 R 0 16 R 0 8 R 0 0 R 0 The accumulated result of the positive-side measurements since the controller supports up to 128x oversampling, each polarity can accumulate up to 19 bits when using 12-bit ADC (Actual number of bits = ADCBITS + 7). The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, the software will need to account for the left-shift of the result returned. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 887 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.5 CVD Results NEG FIFO Read Register Name:

Offset:

Reset:

Property:

CVDRESL 0x014 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 Access Reset Bit 15 Access Reset Bit Access Reset R 0 7 R 0 Bits 18:0 NEG[18:0]

14 R 0 6 R 0 13 R 0 5 R 0 NEG[15:8]

NEG[7:0]

12 R 0 4 R 0 11 R 0 3 R 0 18 R 0 10 R 0 2 R 0 17 NEG[18:16]

R 0 9 R 0 1 R 0 16 R 0 8 R 0 0 R 0 The accumulated result of the negative-side measurements since the controller supports up to 128x oversampling, each polarity can accumulate up to 18 bits when using 12-bit ADC (Actual number of bits = ADCBITS + 7). The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, the software will need to account for the left-shift of the result returned. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 888 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.6 CVD Results Descriptor FIFO Read Register Name:

Offset:

Reset:

Property:

CVDRESD 0x018 0x00000000

Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 31 R 0 23 R 0 15 R 0 7 R 0 30 R 0 22 R 0 14 R 0 6 R 0 29 TXINDEX[4:0]

R 0 21 RXINDEX[4:0]

R 0 13 R 0 5 R 0 28 R 0 20 R 0 12 R 0 4 R 0 DELTA[15:8]

DELTA[7:0]

27 R 0 19 R 0 11 R 0 3 R 0 26 18 10 R 0 2 R 0 25 R 0 17 R 0 9 R 0 1 R 0 SDNUM[1:0]

DELTA[17:16]

24 R 0 16 R 0 8 R 0 0 R 0 Bits 31:27 TXINDEX[4:0]Transmit Index of the result If the Stride of the Scan Descriptor is more than one, the Transmit Index indicates the first one of the group. Bits 25:24 SDNUM[1:0]Scan Descriptor Number These bits has the Scan Descriptor Number that generated the result. Bits 23:19 RXINDEX[4:0]Receive Index of the result If the Stride of the Scan Descriptor is more than one, the Receive Index indicates the first one of the group. Bits 17:0 DELTA[17:0]Delta of the accumulated results of the negative-side and positive-side measurements Since the controller supports up to 128x oversampling, each polarity can accumulate up to 19 bits when using 12-bit ADC. The accumulation is not shifted back down to create an average. Therefore, if oversampling was requested, the software will need to account for the results returned. The DELTA presented is the 18 MSBs (including sign bit) of a signed subtraction of the two accumulators. The data will be in 2s complement form if the delta is negative. Width Needed: ADCBITS + 7 + 1 (sign) Width available: 18 delta_pre[ADCBITS+7:0] = signed( {1b0, POS[ADCBITS+7-1:0]} - {1b0, NEG[ADCBITS+7-1:0]} ) DELTA[17:0] = delta_pre[ADC_BITS+7:ADC_BITS+7-17]

Note:Reading this register increments the FIFO read pointer, destroying the data in the previous two registers for NEG and POS absolute values. If the NEG and POS values are desired, those registers must be read before this register. If the absolute values are not required, bandwidth can be saved by reading only this descriptor register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 889 Microchip Confidential Confidential 33.6.7 CVD Receive Index 0 Configuration PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Name:

Offset:

Reset:

Property:

CVDRX0 0x080 0x00000000

Bit 31 30 Access Reset Bit 23 22 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 RXAN3[5:0]

RXAN2[5:0]

RXAN1[5:0]

RXAN0[5:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 RXAN3[5:0]ANx/CVDR channel to use for RX Index 3 Bits 21:16 RXAN2[5:0]ANx/CVDR channel to use for RX Index 2 Bits 13:8 RXAN1[5:0]ANx/CVDR channel to use for RX Index 1 Bits 5:0 RXAN0[5:0]ANx/CVDR channel to use for RX Index 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 890 Microchip Confidential Confidential 33.6.8 CVD Receive Index 1 Configuration PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Name:

Offset:

Reset:

Property:

CVDRX1 0x084 0x00000000

Bit 31 30 Access Reset Bit 23 22 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 RXAN7[5:0]

RXAN6[5:0]

RXAN5[5:0]

RXAN4[5:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 RXAN7[5:0]ANx/CVDR channel to use for RX Index 7 Bits 21:16 RXAN6[5:0]ANx/CVDR channel to use for RX Index 6 Bits 13:8 RXAN5[5:0]ANx/CVDR channel to use for RX Index 5 Bits 5:0 RXAN4[5:0]ANx/CVDR channel to use for RX Index 4 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 891 Microchip Confidential Confidential 33.6.9 CVD Transmit Index 0 Configuration PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Name:

Offset:

Reset:

Property:

CVDTX0 0x0C0 0x00000000

Bit 31 30 Access Reset Bit 23 22 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 TXAN3[5:0]

TXAN2[5:0]

TXAN1[5:0]

TXAN0[5:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 TXAN3[5:0]ANx/CVDR channel to use for TX Index 3 Bits 21:16 TXAN2[5:0]ANx/CVDR channel to use for TX Index 2 Bits 13:8 TXAN1[5:0]ANx/CVDR channel to use for TX Index 1 Bits 5:0 TXAN0[5:0]ANx/CVDR channel to use for TX Index 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 892 Microchip Confidential Confidential 33.6.10 CVD Transmit Index 1 Configuration PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Name:

Offset:

Reset:

Property:

CVDTX1 0x0C4 0x00000000

Bit 31 30 Access Reset Bit 23 22 Access Reset Bit 15 14 Access Reset Bit 7 6 Access Reset 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 TXAN7[5:0]

TXAN6[5:0]

TXAN5[5:0]

TXAN4[5:0]

27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 TXAN7[5:0]ANx/CVDR channel to use for TX Index 7 Bits 21:16 TXAN6[5:0]ANx/CVDR channel to use for TX Index 6 Bits 13:8 TXAN5[5:0]ANx/CVDR channel to use for TX Index 5 Bits 5:0 TXAN4[5:0]ANx/CVDR channel to use for TX Index 4 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 893 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.11 CVD Scan Descriptor 0 Control 1 Name:

Offset:

Reset:

Property:

CVDSD0C1 0x100 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 SD0TH[23:16]

R/W 0 20 R/W 0 19 SD0TH[15:8]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 SD0TH[7:0]

3 SD0OVRSAMP[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:8 SD0TH[23:0]Scan Descriptor Threshold The controller subtracts the accumulators after all oversampling is complete. The controller compares the result of subtraction to this threshold to determine if threshold exceed asserts internally, which is used to generate an interrupt and/or store data to the FIFO, depending on settings of other control bits. Bits 6:0 SD0OVRSAMP[6:0]Scan Descriptor Over Sampling Determines the amount of oversampling done on each measurement. Value 0 1

... 127 Description Accumulates one measurement Accumulates two measurements Accumulates 128 measurements 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 894 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.12 CVD Scan Descriptor 0 Control 2 Name:

Offset:

Reset:

Property:

CVDSD0C2 0x104 0x00000000

Bit 31 30 SD0TXSTRIDE SD0TXSTRIDE Access Reset R/W 0 Bit 23 R/W 0 22 SD0TXSTRIDE SD0TXSTRIDE Access Reset R/W 0 Bit 15 R/W 0 14 SD0RXSTRIDE SD0RXSTRIDE Access Reset R/W 0 Bit 7 R/W 0 6 SD0RXSTRIDE SD0RXSTRIDE Access Reset R/W 0 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 26 SD0TXEND[5:0]

R/W 0 19 R/W 0 18 SD0TXBEG[5:0]

R/W 0 R/W 0 11 SD0RXEND[5:0]

10 R/W 0 R/W 0 3 2 SD0RXBEG[5:0]

R/W 0 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 SD0TXEND[5:0]Scan Descriptor TX Index End Determines the last TX index to include in a scan. The SD0TXSTRIDE+1 value increments the TX index pointer, meets or exceeds this value, the TX loop of the scan is complete. Bits 22,23,30,31 SD0TXSTRIDEScan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. Value 4b0 4bF Description One TX Index 16 TX Indexes Bits 21:16 SD0TXBEG[5:0]Scan Descriptor TX Index Start Determines the first TX index to include in a scan. Bits 13:8 SD0RXEND[5:0]Scan Descriptor RX Index End Determines the last RX index to include in a scan. The SD0RXSTRIDE+1 value increments the RX index pointer, meets or exceeds this value, the RX loop of the scan is complete. Bits 6,7,14,15 SD0RXSTRIDEScan Descriptor RX Index Stride Determines the number of RX indexes included in a single measurement. Value 4b0 4bF Description One RX Index 16 RX Indexes Bits 5:0 SD0RXBEG[5:0]Scan Descriptor RX Index Start Determines the first RX index to include in a scan. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 895 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.13 CVD Scan Descriptor 0 Control 3 Name:

Offset:

Reset:

Property:

CVDSD0C3 0x108 0x00000000

Bit 31 30 29 28 SD0EN[1:0]

Access Reset R/W/HC 0 R/W/HC 0 Bit 23 22 21 20 Access Reset Bit 15 Access Reset Bit 7 Access Reset 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 R/W 0 4 R/W 0 11 SD0ACQTIME[6:0]

R/W 0 3 SD0CHGTIME[6:0]

R/W 0 27 SD0BUF R/W 0 19 CVDEN R/W 0 26 SD0INTEN R/W 0 25 SD0SELF R/W 0 24 SD0MUT R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 CVDCPL[2:0]

R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:30 SD0EN[1:0]Scan Descriptor Enable Mode Value 00 01 10 11 Description Disables the Scan Descriptor. Executes the Scan Descriptor one time only, then clears the enable. Executes the Scan Descriptor, and keeps it enabled. Then, moves on to the next enabled descriptors. Executes the Scan Descriptor in a loop until a threshold match is detected, then clears the enable mode and moves on to next enabled descriptors. Bit 27 SD0BUFScan Descriptor CVD Buffer Enable Value 1 0 Description Uses CVD buffer output as shared ADC input. Does not use CVD buffer output as shared ADC input. Bit 26 SD0INTENScan Descriptor Interrupt Enable Value 1 0 Description Scan Descriptor creates an interrupt if the accumulator threshold is met. Scan descriptor does not create an interrupt. Bit 25 SD0SELFScan Descriptor Self Measurement Mode Description Enables the Self Measurement mode; RX outputs are part of CVD measurement and are driven. Disables the Self Measurement mode; RX outputs are not part of CVD measurements. Value 1 0 Bit 24 SD0MUTScan Descriptor Mutual Mode Value 1 0 Description Enables the Mutual Measurement mode; TX outputs are part of CVD measurement and are driven. Disables the Mutual Measurement mode; TX outputs are not part of CVD measurements. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 896 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Bit 19 CVDENCapacitive Voltage Division Enable bit Value 1 0 Description CVD operation is enabled CVD operation is disabled Bits 18:16 CVDCPL[2:0]Capacitor Voltage Divider (CVD) Setting bits Value 111 110 101 100 011 010 001 000 Description 7 * 2.5 pF = 17.5 pF 6 * 2.5 pF = 15 pF 5 * 2.5 pF = 12.5 pF 4 * 2.5 pF = 10 pF 3 * 2.5 pF = 7.5 pF 2 * 2.5 pF = 5 pF 1 * 2.5 pF = 2.5 pF 0 * 2.5 pF = 0 pF Bits 14:8 SD0ACQTIME[6:0]Scan Descriptor Acquire Time Specifies the time for which CVD waits for ADC voltage to settle. Bits 6:0 SD0CHGTIME[6:0]Scan Descriptor Charge Time Specifies the time for which CVD remains in the charging state for internal or external capacitors, and for TX outputs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 897 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.14 CVD Scan Descriptor 0 Time 2 Name:

Offset:

Reset:

Property:

CVDSD0T2 0x10C 0x00000000

Bit 31 Access Reset Bit 23 Access Reset Bit 15 Access Reset Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 SD0CHNTIME[6:0]

R/W 0 19 SD0OVRTIME[6:0]

R/W 0 11 SD0POLTIME[6:0]

R/W 0 3 SD0CONTIME[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 30:24 SD0CHNTIME[6:0]Scan Descriptor Channel Time Controls the number of cycles the state machine waits in the RXCHAN or TXCHAN state before moving to the next RX/TX pair. Bits 22:16 SD0OVRTIME[6:0]Scan Descriptor Oversample Time Controls the number of cycles the state machine waits in the OVERSAMP state before taking the next oversampling measurement of an RX/TX pair. Bits 14:8 SD0POLTIME[6:0]Scan Descriptor Polarity Time Controls the number of cycles the state machine waits in the POLARITY state before taking the second polarity measurement of an RX/TX pair. Bits 6:0 SD0CONTIME[6:0]Scan Descriptor Convert Time Controls the number of cycles the state machine waits in the CONVERT state for the ADC sample data. User must ensure that the ADC asserts End-Of-Convert (EOC) before the CONVERT state timer expires. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 898 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.15 CVD Scan Descriptor 1 Control 1 Name:

Offset:

Reset:

Property:

CVDSD1C1 0x110 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 SD1TH[23:16]

R/W 0 20 R/W 0 19 SD1TH[15:8]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 SD1TH[7:0]

3 SD1OVRSAMP[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:8 SD1TH[23:0]Scan Descriptor Threshold The controller subtracts the accumulators after all oversampling is complete. The controller compares the result of subtraction to this threshold to determine if threshold exceed asserts internally, which is used to generate an interrupt and/or store data to the FIFO, depending on settings of other control bits. Bits 6:0 SD1OVRSAMP[6:0]Scan Descriptor Over Sampling Determines the amount of oversampling done on each measurement. Value 0 1

... 127 Description Accumulates one measurement Accumulates two measurements Accumulates 128 measurements 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 899 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.16 CVD Scan Descriptor 1 Control 2 Name:

Offset:

Reset:

Property:

CVDSD1C2 0x114 0x00000000

Bit 31 30 SD1TXSTRIDE SD1TXSTRIDE Access Reset R/W 0 Bit 23 R/W 0 22 SD1TXSTRIDE SD1TXSTRIDE Access Reset R/W 0 Bit 15 R/W 0 14 SD1RXSTRIDE SD1RXSTRIDE Access Reset R/W 0 Bit 7 R/W 0 6 SD1RXSTRIDE SD1RXSTRIDE Access Reset R/W 0 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 26 SD1TXEND[5:0]

R/W 0 19 R/W 0 18 SD1TXBEG[5:0]

R/W 0 R/W 0 11 SD1RXEND[5:0]

10 R/W 0 R/W 0 3 2 SD1RXBEG[5:0]

R/W 0 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 SD1TXEND[5:0]Scan Descriptor TX Index End Determines the last TX index to include in a scan. The SD1TXSTRIDE+1 value increments the TX index pointer, meets or exceeds this value, the TX loop of the scan is complete. Bits 22,23,30,31 SD1TXSTRIDEScan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. Value 4b0 4bF Description One TX Index 16 TX Indexes Bits 21:16 SD1TXBEG[5:0]Scan Descriptor TX Index Start Determines the first TX index to include in a scan. Bits 13:8 SD1RXEND[5:0]Scan Descriptor RX Index End Determines the last RX index to include in a scan. The SD1RXSTRIDE+1 value increments the RX index pointer, meets or exceeds this value, the RX loop of the scan is complete. Bits 6,7,14,15 SD1RXSTRIDEScan Descriptor RX Index Stride Determines the number of RX indexes included in a single measurement. Value 4b0 4bF Description One RX Index 16 RX Indexes Bits 5:0 SD1RXBEG[5:0]Scan Descriptor RX Index Start Determines the first RX index to include in a scan. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 900 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.17 CVD Scan Descriptor 1 Control 3 Name:

Offset:

Reset:

Property:

CVDSD1C3 0x118 0x00000000

Bit 31 30 29 28 SD1EN[1:0]

Access Reset R/W/HC 0 R/W/HC 0 Bit 23 22 21 20 Access Reset Bit 15 Access Reset Bit 7 Access Reset 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 R/W 0 4 R/W 0 11 SD1ACQTIME[6:0]

R/W 0 3 SD1CHGTIME[6:0]

R/W 0 27 SD1BUF R/W 0 19 CVDEN R/W 0 26 SD1INTEN R/W 0 25 SD1SELF R/W 0 24 SD1MUT R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 CVDCPL[2:0]

R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:30 SD1EN[1:0]Scan Descriptor Enable Mode Value 00 01 10 11 Description Disables the Scan Descriptor. Executes the Scan Descriptor one time only, then clears the enable. Executes the Scan Descriptor, and keeps it enabled. Then, moves on to the next enabled descriptors. Executes the Scan Descriptor in a loop until a threshold match is detected, then clears the enable mode and moves on to next enabled descriptors. Bit 27 SD1BUFScan Descriptor CVD Buffer Enable Value 1 0 Description Uses CVD buffer output as shared ADC (ADC2) input. Does not use CVD buffer output as shared ADC (ADC2) input. Bit 26 SD1INTENScan Descriptor Interrupt Enable Value 1 0 Description Scan Descriptor creates an interrupt if the accumulator threshold is met. Scan descriptor does not create an interrupt. Bit 25 SD1SELFScan Descriptor Self Measurement Mode Description Enables the Self Measurement mode; RX outputs are part of CVD measurement and are driven. Disables the Self Measurement mode; RX outputs are not part of CVD measurements. Value 1 0 Bit 24 SD1MUTScan Descriptor Mutual Mode Value 1 0 Description Enables the Mutual Measurement mode; TX outputs are part of CVD measurement and are driven. Disables the Mutual Measurement mode; TX outputs are not part of CVD measurements. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 901 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Bit 19 CVDENCapacitive Voltage Division Enable bit Value 1 0 Description CVD operation is enabled CVD operation is disabled Bits 18:16 CVDCPL[2:0]Capacitor Voltage Divider (CVD) Setting bits Value 111 110 101 100 011 010 001 000 Description 7 * 2.5 pF = 17.5 pF 6 * 2.5 pF = 15 pF 5 * 2.5 pF = 12.5 pF 4 * 2.5 pF = 10 pF 3 * 2.5 pF = 7.5 pF 2 * 2.5 pF = 5 pF 1 * 2.5 pF = 2.5 pF 0 * 2.5 pF = 0 pF Bits 14:8 SD1ACQTIME[6:0]Scan Descriptor Acquire Time Specifies the time for which CVD waits for ADC voltage to settle. Bits 6:0 SD1CHGTIME[6:0]Scan Descriptor Charge Time Specifies the time for which CVD remains in the charging state for internal or external capacitors, and for TX outputs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 902 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.18 CVD Scan Descriptor 1 Time 2 Name:

Offset:

Reset:

Property:

CVDSD1T2 0x11C 0x00000000

Bit 31 Access Reset Bit 23 Access Reset Bit 15 Access Reset Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 SD1CHNTIME[6:0]

R/W 0 19 SD1OVRTIME[6:0]

R/W 0 11 SD1POLTIME[6:0]

R/W 0 3 SD1CONTIME[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 30:24 SD1CHNTIME[6:0]Scan Descriptor Channel Time Controls the number of cycles the state machine waits in the RXCHAN or TXCHAN state before moving to the next RX/TX pair. Bits 22:16 SD1OVRTIME[6:0]Scan Descriptor Oversample Time Controls the number of cycles the state machine waits in the OVERSAMP state before taking the next oversampling measurement of an RX/TX pair. Bits 14:8 SD1POLTIME[6:0]Scan Descriptor Polarity Time Controls the number of cycles the state machine waits in the POLARITY state before taking the second polarity measurement of an RX/TX pair. Bits 6:0 SD1CONTIME[6:0]Scan Descriptor Convert Time Controls the number of cycles the state machine waits in the CONVERT state for the ADC sample data. User must ensure that the ADC asserts End-Of-Convert (EOC) before the CONVERT state timer expires. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 903 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.19 CVD Scan Descriptor 2 Control 1 Name:

Offset:

Reset:

Property:

CVDSD2C1 0x120 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 SD2TH[23:16]

R/W 0 20 R/W 0 19 SD2TH[15:8]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 SD2TH[7:0]

3 SD2OVRSAMP[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:8 SD2TH[23:0]Scan Descriptor Threshold The controller subtracts the accumulators after all oversampling is complete. The controller compares the result of subtraction to this threshold to determine if threshold exceed asserts internally, which is used to generate an interrupt and/or store data to the FIFO, depending on settings of other control bits. Bits 6:0 SD2OVRSAMP[6:0]Scan Descriptor Over Sampling Determines the amount of oversampling done on each measurement. Value 0 1

... 127 Description Accumulates one measurement Accumulates two measurements Accumulates 128 measurements 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 904 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.20 CVD Scan Descriptor 2 Control 2 Name:

Offset:

Reset:

Property:

CVDSD2C2 0x124 0x00000000

Bit 31 30 SD2TXSTRIDE SD2TXSTRIDE Access Reset R/W 0 Bit 23 R/W 0 22 SD2TXSTRIDE SD2TXSTRIDE Access Reset R/W 0 Bit 15 R/W 0 14 SD2RXSTRIDE SD2RXSTRIDE Access Reset R/W 0 Bit 7 R/W 0 6 SD2RXSTRIDE SD2RXSTRIDE Access Reset R/W 0 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 26 SD2TXEND[5:0]

R/W 0 19 R/W 0 18 SD2TXBEG[5:0]

R/W 0 R/W 0 11 SD2RXEND[5:0]

10 R/W 0 R/W 0 3 2 SD2RXBEG[5:0]

R/W 0 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 SD2TXEND[5:0]Scan Descriptor TX Index End Determines the last TX index to include in a scan. The SD2TXSTRIDE+1 value increments the TX index pointer, meets or exceeds this value, the TX loop of the scan is complete. Bits 22,23,30,31 SD2TXSTRIDEScan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. Value 4b0 4bF Description One TX Index 16 TX Indexes Bits 21:16 SD2TXBEG[5:0]Scan Descriptor TX Index Start Determines the first TX index to include in a scan. Bits 13:8 SD2RXEND[5:0]Scan Descriptor RX Index End Determines the last RX index to include in a scan. The SD2RXSTRIDE+1 value increments the RX index pointer, meets or exceeds this value, the RX loop of the scan is complete. Bits 6,7,14,15 SD2RXSTRIDEScan Descriptor RX Index Stride Determines the number of RX indexes included in a single measurement. Value 4b0 4bF Description One RX Index 16 RX Indexes Bits 5:0 SD2RXBEG[5:0]Scan Descriptor RX Index Start Determines the first RX index to include in a scan. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 905 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.21 CVD Scan Descriptor 2 Control 3 Name:

Offset:

Reset:

Property:

CVDSD2C3 0x128 0x00000000

Bit 31 30 29 28 SD2EN[1:0]

Access Reset R/W/HC 0 R/W/HC 0 Bit 23 22 21 20 Access Reset Bit 15 Access Reset Bit 7 Access Reset 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 R/W 0 4 R/W 0 11 SD2ACQTIME[6:0]

R/W 0 3 SD2CHGTIME[6:0]

R/W 0 27 SD2BUF R/W 0 19 CVDEN R/W 0 26 SD2INTEN R/W 0 25 SD2SELF R/W 0 24 SD2MUT R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 CVDCPL[2:0]

R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:30 SD2EN[1:0]Scan Descriptor Enable Mode Value 00 01 10 11 Description Disables the Scan Descriptor. Executes the Scan Descriptor one time only, then clears the enable. Executes the Scan Descriptor, and keeps it enabled. Then, moves on to the next enabled descriptors. Executes the Scan Descriptor in a loop until a threshold match is detected, then clears the enable mode and moves on to next enabled descriptors. Bit 27 SD2BUFScan Descriptor CVD Buffer Enable Value 1 0 Description Uses CVD buffer output as shared ADC (ADC2) input. Does not use CVD buffer output as shared ADC (ADC2) input. Bit 26 SD2INTENScan Descriptor Interrupt Enable Value 1 0 Description Scan Descriptor creates an interrupt if the accumulator threshold is met. Scan descriptor does not create an interrupt. Bit 25 SD2SELFScan Descriptor Self Measurement Mode Description Enables the Self Measurement mode; RX outputs are part of CVD measurement and are driven. Disables the Self Measurement mode; RX outputs are not part of CVD measurements. Value 1 0 Bit 24 SD2MUTScan Descriptor Mutual Mode Value 1 0 Description Enables the Mutual Measurement mode; TX outputs are part of CVD measurement and are driven. Disables the Mutual Measurement mode; TX outputs are not part of CVD measurements. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 906 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Bit 19 CVDENCapacitive Voltage Division Enable bit Value 1 0 Description CVD operation is enabled CVD operation is disabled Bits 18:16 CVDCPL[2:0]Capacitor Voltage Divider (CVD) Setting bits Value 111 110 101 100 011 010 001 000 Description 7 * 2.5 pF = 17.5 pF 6 * 2.5 pF = 15 pF 5 * 2.5 pF = 12.5 pF 4 * 2.5 pF = 10 pF 3 * 2.5 pF = 7.5 pF 2 * 2.5 pF = 5 pF 1 * 2.5 pF = 2.5 pF 0 * 2.5 pF = 0 pF Bits 14:8 SD2ACQTIME[6:0]Scan Descriptor Acquire Time Specifies the time for which CVD waits for ADC voltage to settle. Bits 6:0 SD2CHGTIME[6:0]Scan Descriptor Charge Time Specifies the time for which CVD remains in the charging state for internal or external capacitors, and for TX outputs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 907 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.22 CVD Scan Descriptor 2 Time 2 Name:

Offset:

Reset:

Property:

CVDSD2T2 0x12C 0x00000000

Bit 31 Access Reset Bit 23 Access Reset Bit 15 Access Reset Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 SD2CHNTIME[6:0]

R/W 0 19 SD2OVRTIME[6:0]

R/W 0 11 SD2POLTIME[6:0]

R/W 0 3 SD2CONTIME[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 30:24 SD2CHNTIME[6:0]Scan Descriptor Channel Time Controls the number of cycles the state machine waits in the RXCHAN or TXCHAN state before moving to the next RX/TX pair. Bits 22:16 SD2OVRTIME[6:0]Scan Descriptor Oversample Time Controls the number of cycles the state machine waits in the OVERSAMP state before taking the next oversampling measurement of an RX/TX pair. Bits 14:8 SD2POLTIME[6:0]Scan Descriptor Polarity Time Controls the number of cycles the state machine waits in the POLARITY state before taking the second polarity measurement of an RX/TX pair. Bits 6:0 SD2CONTIME[6:0]Scan Descriptor Convert Time Controls the number of cycles the state machine waits in the CONVERT state for the ADC sample data. User must ensure that the ADC asserts End-Of-Convert (EOC) before the CONVERT state timer expires. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 908 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.23 CVD Scan Descriptor 3 Control 1 Name:

Offset:

Reset:

Property:

CVDSD3C1 0x130 0x00000000

Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 SD3TH[23:16]

R/W 0 20 R/W 0 19 SD3TH[15:8]

R/W 0 12 R/W 0 4 R/W 0 R/W 0 11 R/W 0 SD3TH[7:0]

3 SD3OVRSAMP[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:8 SD3TH[23:0]Scan Descriptor Threshold The controller subtracts the accumulators after all oversampling is complete. The controller compares the result of subtraction to this threshold to determine if threshold exceed asserts internally, which is used to generate an interrupt and/or store data to the FIFO, depending on settings of other control bits. Bits 6:0 SD3OVRSAMP[6:0]Scan Descriptor Over Sampling Determines the amount of oversampling done on each measurement. Value 0 1

... 127 Description Accumulates one measurement Accumulates two measurements Accumulates 128 measurements 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 909 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.24 CVD Scan Descriptor 3 Control 2 Name:

Offset:

Reset:

Property:

CVDSD3C2 0x134 0x00000000

Bit 31 30 SD3TXSTRIDE SD3TXSTRIDE Access Reset R/W 0 Bit 23 R/W 0 22 SD3TXSTRIDE SD3TXSTRIDE Access Reset R/W 0 Bit 15 R/W 0 14 SD3RXSTRIDE SD3RXSTRIDE Access Reset R/W 0 Bit 7 R/W 0 6 SD3RXSTRIDE SD3RXSTRIDE Access Reset R/W 0 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 26 SD3TXEND[5:0]

R/W 0 19 R/W 0 18 SD3TXBEG[5:0]

R/W 0 R/W 0 11 SD3RXEND[5:0]

10 R/W 0 R/W 0 3 2 SD3RXBEG[5:0]

R/W 0 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 29:24 SD3TXEND[5:0]Scan Descriptor TX Index End Determines the last TX index to include in a scan. The SD3TXSTRIDE+1 value increments the TX index pointer, meets or exceeds this value, the TX loop of the scan is complete. Bits 22,23,30,31 SD3TXSTRIDEScan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. Value 4b0 4bF Description One TX Index 16 TX Indexes Bits 21:16 SD3TXBEG[5:0]Scan Descriptor TX Index Start Determines the first TX index to include in a scan. Bits 13:8 SD3RXEND[5:0]Scan Descriptor RX Index End Determines the last RX index to include in a scan. The SD3RXSTRIDE+1 value increments the RX index pointer, meets or exceeds this value, the RX loop of the scan is complete. Bits 6,7,14,15 SD3RXSTRIDEScan Descriptor RX Index Stride Determines the number of RX indexes included in a single measurement. Value 4b0 4bF Description One RX Index 16 RX Indexes Bits 5:0 SD3RXBEG[5:0]Scan Descriptor RX Index Start Determines the first RX index to include in a scan. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 910 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.25 CVD Scan Descriptor 3 Control 3 Name:

Offset:

Reset:

Property:

CVDSD3C3 0x138 0x00000000

Bit 31 30 29 28 SD3EN[1:0]

Access Reset R/W/HC 0 R/W/HC 0 Bit 23 22 21 20 Access Reset Bit 15 Access Reset Bit 7 Access Reset 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 R/W 0 4 R/W 0 11 SD3ACQTIME[6:0]

R/W 0 3 SD3CHGTIME[6:0]

R/W 0 27 SD3BUF R/W 0 19 CVDEN R/W 0 26 SD3INTEN R/W 0 25 SD3SELF R/W 0 24 SD3MUT R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 CVDCPL[2:0]

R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:30 SD3EN[1:0]Scan Descriptor Enable Mode Value 00 01 10 11 Description Disables the Scan Descriptor. Executes the Scan Descriptor one time only, then clears the enable. Executes the Scan Descriptor, and keeps it enabled. Then, moves on to the next enabled descriptors. Executes the Scan Descriptor in a loop until a threshold match is detected, then clears the enable mode and moves on to next enabled descriptors. Bit 27 SD3BUFScan Descriptor CVD Buffer Enable Value 1 0 Description Uses CVD buffer output as shared ADC (ADC2) input. Does not use CVD buffer output as shared ADC (ADC2) input. Bit 26 SD3INTENScan Descriptor Interrupt Enable Value 1 0 Description Scan Descriptor creates an interrupt if the accumulator threshold is met. Scan descriptor does not create an interrupt. Bit 25 SD3SELFScan Descriptor Self Measurement Mode Description Enables the Self Measurement mode; RX outputs are part of CVD measurement and are driven. Disables the Self Measurement mode; RX outputs are not part of CVD measurements. Value 1 0 Bit 24 SD3MUTScan Descriptor Mutual Mode Value 1 0 Description Enables the Mutual Measurement mode; TX outputs are part of CVD measurement and are driven. Disables the Mutual Measurement mode; TX outputs are not part of CVD measurements. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 911 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... Bit 19 CVDENCapacitive Voltage Division Enable bit Value 1 0 Description CVD operation is enabled CVD operation is disabled Bits 18:16 CVDCPL[2:0]Capacitor Voltage Divider (CVD) Setting bits Value 111 110 101 100 011 010 001 000 Description 7 * 2.5 pF = 17.5 pF 6 * 2.5 pF = 15 pF 5 * 2.5 pF = 12.5 pF 4 * 2.5 pF = 10 pF 3 * 2.5 pF = 7.5 pF 2 * 2.5 pF = 5 pF 1 * 2.5 pF = 2.5 pF 0 * 2.5 pF = 0 pF Bits 14:8 SD3ACQTIME[6:0]Scan Descriptor Acquire Time Specifies the time for which CVD waits for ADC voltage to settle. Bits 6:0 SD3CHGTIME[6:0]Scan Descriptor Charge Time Specifies the time for which CVD remains in the charging state for internal or external capacitors, and for TX outputs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 912 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Capacitive Voltage Divider (CVD) Controlle... 33.6.26 CVD Scan Descriptor 3 Time 2 Name:

Offset:

Reset:

Property:

CVDSD3T2 0x13C 0x00000000

Bit 31 Access Reset Bit 23 Access Reset Bit 15 Access Reset Bit 7 Access Reset 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 SD3CHNTIME[6:0]

R/W 0 19 SD3OVRTIME[6:0]

R/W 0 11 SD3POLTIME[6:0]

R/W 0 3 SD3CONTIME[6:0]

R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 30:24 SD3CHNTIME[6:0]Scan Descriptor Channel Time Controls the number of cycles the state machine waits in the RXCHAN or TXCHAN state before moving to the next RX/TX pair. Bits 22:16 SD3OVRTIME[6:0]Scan Descriptor Oversample Time Controls the number of cycles the state machine waits in the OVERSAMP state before taking the next oversampling measurement of an RX/TX pair. Bits 14:8 SD3POLTIME[6:0]Scan Descriptor Polarity Time Controls the number of cycles the state machine waits in the POLARITY state before taking the second polarity measurement of an RX/TX pair. Bits 6:0 SD3CONTIME[6:0]Scan Descriptor Convert Time Controls the number of cycles the state machine waits in the CONVERT state for the ADC sample data. User must ensure that the ADC asserts End-Of-Convert (EOC) before the CONVERT state timer expires. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 913 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34. Analog Comparators (AC) 34.1 Overview The Analog Comparator (AC) supports two individual comparators; one shared (with built-in supply voltage monitor

(MVREF)) AC_CMP1, and one dedicated AC_CMP0. Each comparator (COMP) compares the voltage levels on two inputs, and provides a digital output based on the comparison. Each comparator may be configured to generate interrupt requests and/or peripheral events upon several different combinations of input change. The input selection includes up to four shared analog port pins and several internal signals. Each Comparator Output state can also be output on a pin for use by external devices. The comparators are grouped in pairs on each port. The AC peripheral implements pairtwo pairs of comparators . These are called Comparator 0 (COMP0) and Comparator 1 (COMP1) . for the first pair and Comparator 2 (COMP2) and Comparator 3 (COMP3) for the second pair. They have identical behaviors, but separate Control registers. TheEach pair can be set in Window mode to compare a signal to a voltage range instead of a single voltage level. 34.2 Features Two individual comparators (Single pair configuration) Analog comparator outputs available on pins Asynchronous or synchronous Flexible input selection:

Up to four pins selectable for positive or negative inputs Ground (for zero crossing) Bandgap reference voltage Programmable VDD scaler for AC_CMP1 (Shared with Programmable Low Voltage Detector (PLVD)) and fixed VDD/2 for AC_CMP0 DAC output Interrupt generation on:

Rising or falling edge Toggle End of comparison Window function interrupt generation on:

Signal above window Signal inside window Signal below window Signal outside window Event generation on:

Comparator output Window function inside/outside window Optional digital filter on comparator output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 914 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.3 Block Diagram Figure 34-1. Analog Comparator Block Diagram AIN0 AIN1 VDD SCALER

(VDD/2) PLVD SCALER BANDGAP AIN2 AIN3 DAC COMP0

HYSTERESIS ENABLE INTERRUPT MODE COMPCTRLn WINCTRL ENABLE HYSTERESIS COMP1

INTERRUPT SENSITIVITY CONTROL

WINDOW FUNCTION CMP0 INTERRUPTS EVENTS GCLK_AC CMP1 34.4 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 34.4.1 I/O Lines Using the ACs I/O lines requires the I/O pins to be configured as analog pins for AC_AINx inputs. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Table 34-1. I/O LINES Signal AC_AIN0 AC_AIN1 AC_AIN2 AC_AIN3 AC_CMP0 AC_CMP1 Peripheral Function Comparator input Comparator input Comparator input Comparator input Comparator output Comparator output Note:

1. To get the analog comparator output on I/O line, CFGCON1.CMP0_OE/CFGCON1.CMP1_OE needs to be set/enabled. See System Configuration and Register Locking (CFG) from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 915 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 18. System Configuration and Register Locking (CFG) 34.4.2 Power Management The AC will continue to operate in any Sleep mode (Idle, Standby Sleep) where the selected source clock is running. The ACs interrupts can be used to wake-up the device from Sleep modes. Events connected to the Event System can trigger other operations in the system without exiting Standby Sleep mode. 34.4.3 Clocks The AC bus clock (PB2_CLK) can be enabled and disabled in the Main Clock module, CRU (see Clock and Reset Unit (CRU) from Related Links), and the Analog Comparator module can be enabled or disabled via the PMD1 register. See Peripheral Module Disable Register (PMD) from Related Links. A generic clock (GCLK_AC) is required to clock the AC. This clock must be configured and enabled in the generic clock controller before using the AC. This generic clock is asynchronous to the bus clock (PB2_CLK). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. See Synchronization from Related Links. Related Links 13. Clock and Reset Unit (CRU) 34.5.13. Synchronization 34.4.4 DMA Not applicable. 34.4.5 Interrupts The interrupt request lines are connected to the interrupt controller. Using the AC interrupts requires the interrupt controller to be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 34.4.6 Events The events are connected to the Event System. See Event System (EVSYS) from Related Links for details on how to configure the Event System. Related Links 26. Event System (EVSYS) 34.4.7 Debug Operation When the CPU is halted in debug mode, the AC will halt normal operation after any ongoing comparison is completed. The AC can be forced to continue normal operation during debugging. See DBGCTRL register from Related Links. If the AC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. Related Links 34.7.9. DBGCTRL 34.4.8 Register Access Protection All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Control B register (CTRLB) Interrupt Flag register (INTFLAG) Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 916 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) PAC write protection does not apply to accesses through an external debugger. 34.4.9 Analog Connections Each comparator has up to four I/O pins that can be used as analog inputs. The pair of comparators shares the same four pins. These pins must be configured for analog operation before using them as comparator inputs. Any internal reference source, such as a bandgap voltage reference, DAC must be configured and enabled prior to its use as a comparator input. 34.5 Functional Description 34.5.1 Principle of Operation Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection of analog input pins. Each negative input may be chosen from a selection of both analog input pins and internal inputs, such as bandgap voltage reference. The digital output from the comparator is 1 when the difference between the positive and the negative input voltage is positive, and 0otherwise. The individual comparators can be used independently (Normal mode) or paired to form a window comparison

(Window mode). 34.5.2 Basic Operation 34.5.2.1 Initialization Some registers are enable-protected, meaning they can only be written when the module is disabled. The following register is enable-protected:

Event Control register (EVCTRL) Enable-protection is denoted by the "Enable-Protected" property in each individual register description. 34.5.2.2 Enabling, Disabling and Resetting The AC is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The AC is disabled writing a 0 to CTRLA.ENABLE. In addition to this AC module enable configuration, AC must also be enabled in the PMD module. The AC is reset by writing a 1 to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the AC will be reset to their initial state, and the AC will be disabled. See CTRLA register from Related Links. Related Links 34.7.1. CTRLA 34.5.2.3 Comparator Configuration Each individual comparator must be configured by its respective Comparator Control register (COMPCTRLx) before that comparator is enabled. These settings cannot be changed while the comparator is enabled. Select the desired measurement mode with COMPCTRLx.SINGLE. See Starting a Comparison from Related Links. Fixed hysteresis does not support programmable Hysteresis. Fixed speed of operation Select the interrupt source with COMPCTRLx.INTSEL. Select the positive and negative input sources with the COMPCTRLx.MUXPOS and COMPCTRLx.MUXNEG bits. See Selecting Comparator Inputs from Related Links. Select the filtering option with COMPCTRLx.FLEN. Select the standby operation with the Run in Standby bit (COMPCTRLx.RUNSTDBY). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 917 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) The individual comparators are enabled by writing a 1 to the Enable bit in the Comparator x Control registers

(COMPCTRLx.ENABLE). The individual comparators are disabled by writing a 0 to COMPCTRLx.ENABLE. Writing a 0 to CTRLA.ENABLE will also disable all the comparators but will not clear their COMPCTRLx.ENABLE bits. Related Links 34.5.2.4. Starting a Comparison 34.5.3. Selecting Comparator Inputs 34.5.2.4 Starting a Comparison Each comparator channel can be in one of two different measurement modes, which is determined by the COMPCTRLx.SINGLE bit:

Continuous measurement Single-shot After being enabled, a start-up delay is required before the result of the comparison is ready. This start-up time is measured automatically to account for environmental changes, such as temperature or voltage supply level, and is specified in the Electrical Specifications. During the start-up time, the COMP output is not available. The comparator can be configured to generate interrupts when the output toggles, when the output changes from 0 to 1 (rising edge), when the output changes from 1 to 0 (falling edge) or at the end of the comparison. An end-of-comparison interrupt can be used with the Single-Shot mode to chain further events in the system, regardless of the state of the comparator outputs. The Interrupt mode is set by the Interrupt Selection bit group in the Comparator Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state regardless of whether the interrupt is enabled or not. 34.5.2.4.1 Continuous Measurement Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always available in the Current State bit in the Status A register (STATUSA.STATEx). After the start-up time has passed, a comparison is done and STATUSA is updated. The Comparator x Ready bit in the Status B register (STATUSB.READYx) is set, and the appropriate peripheral events and interrupts are also generated. New comparisons are performed continuously until the COMPCTRLx.ENABLE bit is written to zero. The start-up time applies only to the first comparison. In the continuous operation, edge detection of the comparator output for interrupts is done by comparing the current and previous sample. The sampling rate is the GCLK_AC frequency. An example of continuous measurement is shown in the following figure. Figure 34-2. Continuous Measurement Example GCLK_AC_DIG Write 1 COMPCTRLx.ENABLE 2-3 cycles tSTARTUP STATUSB.READYx Sampled Comparator Output For low-power operation, comparisons can be performed during sleep mode without a clock. The comparator is enabled continuously, and changes of the comparator state are detected asynchronously. When a toggle occurs, the CRU will start GCLK_AC to register the appropriate peripheral events and interrupts. The GCLK_AC clock is, then, disabled again automatically unless configured to wake up the system from sleep. 34.5.2.4.2 Single-Shot Single-shot operation is selected by writing COMPCTRLx.SINGLE to 1. During single-shot operation, the comparator is normally idle. The user starts a single comparison by writing 1 to the respective Start Comparison bit in the write-only Control B register (CTRLB.STARTx). The comparator is enabled and, after the start-up time has passed, a single comparison is done and STATUSA is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. Writing 1 to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx). STATUSB.READYx is set automatically by hardware when the single comparison has completed. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 918 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) A single-shot measurement can also be triggered by the Event System. Setting the Comparator x Event Input bit in the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation;

the difference is that a peripheral event from another hardware module causes the hardware to automatically start the comparison and will not clear STATUSB.READYx. To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the current measurement is compared with the result of the previous measurement (one sampling period earlier). An example of single-shot operation is shown in the following figure. Figure 34-3. Single-Shot Example GCLK_AC Write 1 Write 1 CTRLB.STARTx 2-3 cycles 2-3 cycles tSTARTUP tSTARTUP STATUSB.READYx Sampled Comparator Output For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the CRU will start GCLK_AC. The comparator is enabled and, after the start-up time has passed, a comparison is done and appropriate peripheral events and interrupts are also generated. The comparator and GCLK_AC are, then, disabled again automatically unless configured to wake up the system from sleep. 34.5.3 Selecting Comparator Inputs Each comparator has one positive and one negative input. The positive input is one of the external input pins (AINx). The negative input can be fed either from an external input pin (AINx) or from one of the internal reference voltage sources common to all comparators. The user selects the input source as follows:

The positive input is selected by the Positive Input MUX Select bit group in the Comparator Control register

(COMPCTRLx.MUXPOS). The negative input is selected by the Negative Input MUX Select bit group in the Comparator Control register

(COMPCTRLx.MUXNEG). In the case of using an external I/O pin, the selected pin must be configured for analog use in the GPIO by disabling the digital input and output. The switching of the analog input multiplexers is controlled to minimize crosstalk between the channels. The input selection must be changed only while the individual comparator is disabled. Note:For internal use of the comparison results by the CCL module (see Configurable Custom Logic (CCL) from Related Links), COMPCTRLx.OUT must be 0x1 or 0x2. Related Links 24. Configurable Custom Logic (CCL) 34.5.4 Window Operation The comparator pair can be configured to work together in Window mode. In this mode, a voltage range is defined, and the comparators give information about whether an input signal is within this range or not. Window mode is enabled by the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators must have the same measurement mode setting in their respective Comparator Control Registers (COMPCTRLx.SINGLE). Notes:

1. Both comparators must be enabled (COMPCTRLx.ENABLE = 1) before the Window mode is enabled

(WINCTRL.WEN0 = 1). 2. Window mode must be first disabled (WINCTRL.WEN0 = 0) before both comparators are disabled

(COMPCTRLx.ENABLE = 0). To physically configure the comparators for Window mode, the same I/O pin must be chosen as positive input for each comparator, providing a shared input signal. The negative inputs define the range for the window. In the figure below, COMP0 defines the upper limit and COMP1 defines the lower limit of the window, as shown but the window will also work in the opposite configuration with COMP0 lower and COMP1 higher. The current state of the window function is available in the Window x State bit group of the Status register (STATUS.WSTATEx). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 919 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Window mode can be configured to generate interrupts when the input voltage changes to below the window, when the input voltage changes to above the window, when the input voltage changes into the window or when the input voltage changes outside the window. The interrupt selections are set by the Window Interrupt Selection bit field in the Window Control register (WINCTRL.WINTSEL). Events are generated using the inside/outside state of the window, regardless of whether the interrupt is enabled or not. Note that the individual comparator outputs, interrupts and events continue to function normally during Window mode. When the comparators are configured for Window mode and Single-shot mode, measurements are performed simultaneously on both comparators. Writing 1 to either Start Comparison bit in the Control B register

(CTRLB.STARTx) will start a measurement. Likewise either peripheral event can start a measurement. STATUSA.WSTATE bit field must be read only after STATUSB.READY bits of both the related comparators are set. Figure 34-4. Comparators in Window Mode

COMP0 COMP1 INTERRUPT SENSITIVITY CONTROL

WINDOW FUNCTION STATE0 WSTATE[1:0]

INTERRUPTS EVENTS STATE1 UPPER LIMIT OF WINDOW INPUT SIGNAL LOWER LIMIT OF WINDOW 34.5.5 VDD Scaler The VDD scaler generates a reference voltage that is a fraction of the devices supply voltage with 16 levels. The programmable VDD scaler (PLVD Scaler) is available for AC_CMP1 only. AC_CMP0 uses a fixed VDD/2 reference. The scaler of a comparator is enabled when the Negative Input Mux bit field or the Positive Input Mux in the respective Comparator Control register (COMPCTRLx.MUXNEG) is set to 0x5 and the comparator is enabled. The voltage of each channel is selected by the Value bit field in the SCALER1 registers (SCALER1.VALUE) using the VDD resistor ladder. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 920 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Figure 34-5. PLVD Scaler COMPCTRLx.MUXNEG == 5 SCALER1.. VALUE 4 to COMP1 34.5.6 Filtering The output of the comparators can be filtered digitally to reduce noise. The filtering is determined by the Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the GCLK_AC frequency. Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the comparator output is validated. For Continuous mode, the first valid output will occur when the required number of filter samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the previous N-1 samples, as shown in Figure 34-6. For Single-shot mode, the comparison completes after the Nth filter sample, as shown in Figure 34-7. Figure 34-6. Continuous Mode Filtering Sampling Clock Sampled Comparator Output 3-bit Majority Filter Output 5-bit Majority Filter Output Figure 34-7. Single-Shot Filtering tSTARTUP Sampling Clock Start 3-bit Sampled Comparator Output 3-bit Majority Filter Output 5-bit Sampled Comparator Output 5-bit Majority Filter Output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 921 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) During Sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous measurements will be done during Sleep modes, or the resulting interrupt/event may be generated incorrectly. 34.5.7 Comparator Output The output of each comparator can be routed to an I/O pin by setting the Output bit group in the Comparator Control x register (COMPCTRLx.OUT). To get the analog comparator output on the I/O line, CFGCON1.CMP0_OE/

CFGCON1.CMP1_OE also needs to be set or enabled. This allows the comparator to be used by external circuitry. Either the raw, non-synchronized output of the comparator or the GCLK_AC-synchronized version, including filtering, can be used as the I/O signal source. The output appears on the corresponding AC_CMPx pin. The AC_CMP1 can be output on an alternate pin by configuring the CFGCON0.ACCMP1_ALTEN configuration. 34.5.8 Offset Compensation The Swap bit in the Comparator Control registers (COMPCTRLx.SWAP) controls switching of the input signals to a comparator's positive and negative terminals. When the comparator terminals are swapped, the output signal from the comparator is also inverted, as shown in Figure 34-8. This allows the user to measure or compensate for the comparator input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the comparator is disabled. Figure 34-8. Input Swapping for Offset Compensation MUXPOS

COMPx CMPx HYSTERESIS ENABLE SWAP MUXNEG COMPCTRLx SWAP 34.5.9 DMA Operation Not applicable. 34.5.10 Interrupts The AC has the following interrupt sources:

Comparator (COMP0, COMP1, COMP2, COMP3): Indicates a change in comparator status Window (WIN0, WIN1): Indicates a change in the window status Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSELx[1:0]). Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear

(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the AC is Reset. See INTFLAG register from Related Links for details on how to clear interrupt flags. All interrupt requests from the peripheral are OR'ed together on the system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. See Nested Vector Interrupt Controller (NVIC) from Related Links. Note:Interrupts must be globally enabled for interrupt requests to be generated. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 922 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 34.7.6. INTFLAG 34.5.11 Events The AC can generate the following output events:

Comparator (COMP0, COMP1, COMP2, COMP3): Generated as a copy of the comparator status Window (WIN0, WIN1): Generated as a copy of the window inside/outside status Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. See Event System (EVSYS) from Related Links for details on how to configure the Event System. The AC can take the following action on an input event:

Start comparison (START0, START1): Start a comparison Writing a one to an Event Input bit into the Event Control register (EVCTRL.COMPEIx) enables the corresponding action on an input event. Writing a zero to this bit disables the corresponding action on an input event. Note that if several events are connected to the AC, the enabled action will be taken on any of the incoming events. See Event System (EVSYS) from Related Links for details on how to configure the Event System. When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In normal mode, each comparator responds to its corresponding input event independently. For a pair of comparators in window mode, either comparator event will trigger a comparison on both comparators simultaneously. Related Links 26. Event System (EVSYS) 34.5.12 Sleep Mode Operation The Run in Standby bits in the Comparator x Control registers (COMPCTRLx.RUNSTDBY) control the behavior of the AC during standby sleep mode. Each RUNSTDBY bit controls one comparator. When the bit is zero, the comparator is disabled during sleep, but maintains its current configuration. When the bit is one, the comparator continues to operate during sleep. Note that when RUNSTDBY is zero, the analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep. For Window Mode operation, both comparators in a pair must have the same RUNSTDBY configuration. When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. The AC can also be used during sleep modes where the clock used by the AC is disabled, provided that the AC is still powered (not in shutdown). In this case, the behavior is slightly different and depends on the measurement mode, as listed in Table 34-2. Table 34-2. Sleep Mode Operation COMPCTRLx.MODE RUNSTDBY=0 RUNSTDBY=1 0 (Continuous) COMPx disabled GCLK_AC stopped, COMPx enabled 1 (Single-shot) COMPx disabled GCLK_AC stopped, COMPx enabled only when triggered by an input event 34.5.12.1 Continuous Measurement during Sleep When a comparator is enabled in continuous measurement mode and GCLK_AC is disabled during sleep, the comparator will remain continuously enabled and will function asynchronously. The current state of the comparator is asynchronously monitored for changes. If an edge matching the interrupt condition is found, GCLK_AC is started to register the interrupt condition and generate events. If the interrupt is enabled in the Interrupt Enable registers

(INTENCLR/SET), the AC can wake up the device; otherwise GCLK_AC is disabled until the next edge detection. Filtering is not possible with this configuration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 923 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Figure 34-9. Continuous Mode SleepWalking GCLK_AC Write 1 COMPCTRLx.ENABLE 2-3 cycles tSTARTUP STATUSB.READYx Sampled Comparator Output 34.5.12.2 Single-Shot Measurement during Sleep For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the CRU will start GCLK_AC. The comparator is enabled and, after the start-up time has passed, a comparison is done, with filtering if desired, and the appropriate peripheral events and interrupts are also generated as shown in the following figure. The comparator and GCLK_AC are, then, disabled again automatically unless configured to wake the system from sleep. Filtering is allowed with this configuration. Figure 34-10. Single-Shot SleepWalking GCLK_AC Input Event Comparator Output or Event tSTARTUP tSTARTUP 34.5.13 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset bit in Control register (CTRLA.SWRST) Enable bit in Control register (CTRLA.ENABLE) Enable bit in Comparator Control register (COMPCTRLn.ENABLE) The following registers are synchronized when written:

Window Control register (WINCTRL) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 924 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.6 Register Summary See AC module in the Product Memory Mapping Overview from Related Links for base address. Offset 0x00 0x01 0x02 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B

... 0x0C 0x0D 0x0E

... 0x0F Bit Pos. 7 6 5 4 3 2 1 0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 START3 START2 ENABLE START1 SWRST START0 INVEI3 INVEI2 INVEI1 INVEI0 COMPEI3 COMPEI2 COMPEI1 COMPEI0 WINEO1 WINEO0 COMPEO3 COMPEO2 COMPEO1 COMPEO0 WIN1 WIN1 WIN1 WIN0 WIN0 WIN0 WSTATE1[1:0]

WSTATE0[1:0]

COMP3 COMP3 COMP3 STATEx COMP2 COMP2 COMP2 STATEx COMP1 COMP1 COMP1 STATE1 READY1 WINTSEL1[1:0]

WEN1 WINTSEL0[1:0]

COMP0 COMP0 COMP0 STATE0 READY0 DBGRUN WEN0 Name CTRLA CTRLB EVCTRL INTENCLR INTENSET INTFLAG STATUSA STATUSB DBGCTRL WINCTRL Reserved SCALER1 7:0 Reserved VALUE[3:0]

0x10 COMPCTRL0 0x14 COMPCTRL1 0x18

... 0x1F Reserved 0x20 SYNCBUSY 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 RUNSTDBY INTSEL[1:0]

SINGLE ENABLE SWAP MUXPOS[2:0]

RUNSTDBY INTSEL[1:0]

SINGLE SWAP MUXPOS[2:0]

OUT[1:0]

OUT[1:0]

MUXNEG[2:0]

FLEN[2:0]

ENABLE MUXNEG[2:0]

FLEN[2:0]

COMPCTRL3 COMPCTRL2 COMPCTRL1 COMPCTRL0 WINCTRL ENABLE SWRST Related Links 7. Product Memory Mapping Overview 34.7 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-

protection is denoted by the PAC Write-Protection property in each individual register description. See Register Access Protection from Related Links. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. See Synchronization from Related Links. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-

protection is denoted by the "Enable-Protected" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 925 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Related Links 34.4.8. Register Access Protection 34.5.13. Synchronization 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 926 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized CTRLA 0x00 0x00 Bit 7 6 5 4 3 2 Access Reset Bit 1 ENABLEEnable 1 ENABLE R/W 0 0 SWRST W 0 Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the corresponding bit in the Synchronization Busy register

(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the peripheral is enabled/disabled. Note:To avoid spurious interrupts from multiple enable/disable cycles of AC, use the SWRST bit to reset the comparator module. Value 0 1 Description The AC is disabled. The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator Control register (COMPCTRLn.ENABLE). Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the AC to their initial state, and the AC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 927 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.2 Control B Name:

Offset:

Reset:

Property:

CTRLB 0x01 0x00

Bit 7 6 5 4 Access Reset 3 START3 R/W 0 2 START2 R/W 0 1 START1 R/W 0 0 START0 R/W 0 Bits 0, 1 STARTxComparator x Start Comparison Writing a '0' to this field has no effect. Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is not implemented, or if it is not enabled in single-shot mode, Writing a '1' has no effect. This bit always reads as zero. Bits 0, 1, 2, 3 STARTxComparator x Start Comparison Writing a '0' to this field has no effect. Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is not enabled in single-shot mode, writing a '1' has no effect. This bit always reads as zero. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 928 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.3 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x02 0x0000 Bit Access Reset 15 INVEI3 R/W 0 14 INVEI2 R/W 0 Bit 7 6 Access Reset 13 INVEI1 R/W 0 5 WINEO1 R/W 0 12 INVEI0 R/W 0 4 WINEO0 R/W 0 11 COMPEI3 R/W 0 3 COMPEO3 R/W 0 10 COMPEI2 R/W 0 2 COMPEO2 R/W 0 9 COMPEI1 R/W 0 1 COMPEO1 R/W 0 8 COMPEI0 R/W 0 0 COMPEO0 R/W 0 Bits 12, 13 INVEIxInverted Event Input Enable x Value 0 1 Description Incoming event is not inverted for comparator x. Incoming event is inverted for comparator x. Bits 12, 13, 14, 15 INVEIxInverted Event Input Enable x Description Incoming event is not inverted for comparator x. Incoming event is inverted for comparator x. Value 0 1 Bits 8, 9 COMPEIxComparator x Event Input Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, the enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming events caused the action. These bits indicate whether a comparison will start or not on any incoming event. Value 0 1 Description Comparison will not start on any incoming event. Comparison will start on any incoming event. Bits 8, 9, 10, 11 COMPEIxComparator x Event Input Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, the enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming events caused the action. These bits indicate whether a comparison will start or not on any incoming event. Value 0 1 Description Comparison will not start on any incoming event. Comparison will start on any incoming event. Bit 4 WINEO0Window 0 Event Output Enable These bits indicate whether the window 0 function can generate a peripheral event or not. Value 0 1 Description Window 0 Event is disabled. Window 0 Event is enabled. Bits 4, 5 WINEOxWindow x Event Output Enable These bits indicate whether the window x function can generate a peripheral event or not. Value 0 1 Description Window x Event is disabled. Window x Event is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 929 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Bits 0, 1 COMPEOxComparator x Event Output Enable These bits indicate whether the comparator x output can generate a peripheral event or not. Value 0 1 Description COMPx event generation is disabled. COMPx event generation is enabled. Bits 0, 1, 2, 3 COMPEOxComparator x Event Output Enable These bits indicate whether the comparator x output can generate a peripheral event or not. Value 0 1 Description COMPx event generation is disabled. COMPx event generation is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 930 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.4 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x04 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 Access Reset 5 WIN1 R/W 0 4 WIN0 R/W 0 3 COMP3 R/W 0 2 COMP2 R/W 0 1 COMP1 R/W 0 0 COMP0 R/W 0 Bit 4 WIN0Window 0 Interrupt Enable Reading this bit returns the state of the Window 0 interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit disables the Window 0 interrupt. Value 0 1 Description The Window 0 interrupt is disabled. The Window 0 interrupt is enabled. Bits 4, 5 WINxWindow x Interrupt Enable Reading this bit returns the state of the Window x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit disables the Window x interrupt. Value 0 1 Description The Window x interrupt is disabled. The Window x interrupt is enabled. Bits 0, 1 COMPxComparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit disables the Comparator x interrupt. Value 0 1 Description The Comparator x interrupt is disabled. The Comparator x interrupt is enabled. Bits 0, 1, 2, 3 COMPxComparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit disables the Comparator x interrupt. Value 0 1 Description The Comparator x interrupt is disabled. The Comparator x interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 931 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.5 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x05 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 Access Reset 5 WIN1 R/W 0 4 WIN0 R/W 0 3 COMP3 R/W 0 2 COMP2 R/W 0 1 COMP1 R/W 0 0 COMP0 R/W 0 Bit 4 WIN0Window 0 Interrupt Enable Reading this bit returns the state of the Window 0 interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit enables the Window 0 interrupt. Value 0 1 Description The Window 0 interrupt is disabled. The Window 0 interrupt is enabled. Bits 4, 5 WINxWindow x Interrupt Enable Reading this bit returns the state of the Window x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit enables the Window x interrupt. Value 0 1 Description The Window x interrupt is disabled. The Window x interrupt is enabled. Bits 0, 1 COMPxComparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt. Value 0 1 Description The Comparator x interrupt is disabled. The Comparator x interrupt is enabled. Bits 0, 1, 2, 3 COMPxComparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt. Value 0 1 Description The Comparator x interrupt is disabled. The Comparator x interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 932 Microchip Confidential Confidential 34.7.6 Interrupt Flag Status and Clear PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Name:

Offset:

Reset:

Property:

INTFLAG 0x06 0x00 Bit 7 6 Access Reset Bit 4 WIN0Window 0 5 WIN1 R/W 0 4 WIN0 R/W 0 3 COMP3 R/W 0 2 COMP2 R/W 0 1 COMP1 R/W 0 0 COMP0 R/W 0 This flag is set according to the Window 0 Interrupt Selection bit group in the WINCTRL register

(WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Window 0 interrupt flag. Bits 4, 5 WINxWindow x This flag is set according to the Window x Interrupt Selection bit group in the WINCTRL register

(WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Window x interrupt flag. Bits 0, 1 COMPxComparator x Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx always reads as zero. This flag is set according to the Interrupt Selection bit group in the Comparator x Control register

(COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Comparator x interrupt flag. Bits 0, 1, 2, 3 COMPxComparator x Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx always reads as zero. This flag is set according to the Interrupt Selection bit group in the Comparator x Control register

(COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Comparator x interrupt flag. Bit 0 SWRSTSoftware Reset Writing a 0 to this bit has no effect. Writing a 1 to this bit resets all registers in the AC to their initial state, and the AC will be disabled. Writing a 1 to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 933 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.7 Status A Name:

Offset:

Reset:

Property:

STATUSA 0x07 0x00

Bit Access Reset 7 R 0 WSTATE1[1:0]

6 R 0 5 R 0 WSTATE0[1:0]

4 R 0 3 STATEx R 0 2 STATEx R 0 1 STATE1 R 0 0 STATE0 R 0 Bits 7:6 WSTATE1[1:0]Window 1 Current State These bits show the current state of the signal if the window 1 mode is enabled. Value 0x0 0x1 0x2 0x3 Description Signal is above window Signal is inside window Signal is below window Reserved Name ABOVE INSIDE BELOW Bits 5:4 WSTATE0[1:0]Window 0 Current State These bits show the current state of the signal if the window 0 mode is enabled. These values may change in during startup and measurement cycles. When polling for sample completion use both the STATUSB.READYx bits to signal completion. Value 0x0 0x1 0x2 0x3 Description Signal is above window Signal is inside window Signal is below window Reserved Name ABOVE INSIDE BELOW

Bits 3,2,1,0 STATExComparator x Current State This bit shows the current state of the output signal from COMPx. STATEx is valid only when the STATUSB.READYx bit is one. Bits 0, 1 STATExComparator x Current State This bit shows the current state of the output signal from COMPx. STATEx is valid only when the STATUSB.READYx bit is one. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 934 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.8 Status B Name:

Offset:

Reset:

Property:

STATUSB 0x08 0x00

Bit 7 6 5 4 3 2 Access Reset Bits 0, 1 READYxComparator x Ready Value 0 1 Description This bit is cleared when the comparator x output is not ready. This bit is set when the comparator x output is ready. 1 READY1 R 0 0 READY0 R 0 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 935 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.9 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x09 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNDebug Run DBGRUN R/W 0 This bit is not reset by a software reset. This bits controls the functionality when the CPU is halted by an external debugger. Value 0 Description The AC is halted when the CPU is halted by an external debugger. Any on-going comparison will complete before AC is halted. The AC continues normal operation when the CPU is halted by an external debugger. 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 936 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.10 Window Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized WINCTRL 0x0A 0x00 Bit 7 Access Reset 6 5 WINTSEL1[1:0]

R/W 0 R/W 0 4 WEN1 R/W 0 3 2 1 WINTSEL0[1:0]

R/W 0 R/W 0 0 WEN0 R/W 0 Bits 6:5 WINTSEL1[1:0]Window 1 Interrupt Selection These bits configure the interrupt mode for the comparator window 1 mode. Value 0x0 0x1 0x2 0x3 Description Interrupt on signal above window Interrupt on signal inside window Interrupt on signal below window Interrupt on signal outside window Name ABOVE INSIDE BELOW OUTSIDE Bit 4 WEN1Window 1 Mode Enable Value 0 1 Description Window mode is disabled for comparators 2 and 3. Window mode is enabled for comparators 2 and 3. Bits 2:1 WINTSEL0[1:0]Window 0 Interrupt Selection These bits configure the interrupt mode for the comparator window 0 mode. Value 0x0 0x1 0x2 0x3 Description Interrupt on signal above window Interrupt on signal inside window Interrupt on signal below window Interrupt on signal outside window Name ABOVE INSIDE BELOW OUTSIDE Bit 0 WEN0Window 0 Mode Enable Value 0 1 Description Window mode is disabled. Window mode is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 937 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.11 Scaler 1 Name:

Offset:

Reset:

Property: PAC Write-Protection SCALER1 0x0D 0x00 Bit 7 6 5 4 Access Reset 3 R/W 0 VALUE[3:0]

2 R/W 0 1 R/W 0 0 R/W 0 Bits 3:0 VALUE[3:0]Scaler Value These bits define the scaling factor for channel 1 of the VDD voltage scaler. The output voltage, VSCALE, is:

R_Bottom R_Total VSCALE = VDD Where, R_Total = 900. Refer to the following table for R_Bottom for different VALUE[3:0]

For example, VSCALE for VALUE[3:0] = 0x02 at VDD = 3.3V VSCALE = 3.3 598.5 Table 34-3. Scaler Value 900

= 2.1945V Value[3:0]

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF R_Bottom Reserved Reserved 598.5 634.5 306 324 328.5 360 387 400.5 432 450 468 490.5 481.5 External Reference on LVDIN pin 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 938 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.12 Comparator Control n Name:

Offset:

Reset:

Property: PAC Write-Protection COMPCTRL 0x10 + n*0x04 [n=0..1]

0x00000000 Bit 31 30 Access Reset Bit 23 22 OUT[1:0]

29 R/W 0 21 Access Reset Bit Access Reset 15 SWAP R/W 0 14 R/W 0 13 MUXPOS[2:0]

R/W 0 Bit 7 Access Reset 5 6 RUNSTDBY R/W 0 Bits 29:28 OUT[1:0]Output 28 R/W 0 20 12 R/W 0 4 27 19 11 3 INTSEL[1:0]

R/W 0 R/W 0 26 R/W 0 18 10 R/W 0 25 FLEN[2:0]

R/W 0 17 9 MUXNEG[2:0]

R/W 0 2 SINGLE R/W 0 1 ENABLE R/W 0 24 R/W 0 16 8 R/W 0 0 These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero. Note:For internal use of the comparison results by the CCL, this must be 0x1 or 0x2. These bits are not synchronized. Description Name Value OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC 0x2 N/A 0x3 The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Reserved Bits 26:24 FLEN[2:0]Filter Length These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Name Value OFF 0x0 MAJ3 0x1 MAJ5 0x2 0x3-0x7 N/A Description No filtering 3-bit majority function (2 of 3) 5-bit majority function (3 of 5) Reserved Bit 15 SWAPSwap Inputs and Invert This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Value 0 Description The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 939 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Value 1 Description The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input. Bits 14:12 MUXPOS[2:0]Positive Input Mux Selection These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Name Value PIN0 0x0 PIN1 0x1 PIN2 0x2 PIN3 0x3 VSCALE 0x4

0x50x7 Description AC_AIN0 AC_AIN1 AC_AIN2 AC_AIN3 VDD scaler Reserved Bits 10:8 MUXNEG[2:0]Negative Input Mux Selection These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Name Value PIN0 0x0 PIN1 0x1 PIN2 0x2 PIN3 0x3 GND 0x4 VSCALE 0x5 BANDGAP 0x6 DAC 0x7 Description I/O pin 0 I/O pin 1 I/O pin 2 I/O pin 3 Ground VDD scaler Internal bandgap voltage DAC output Bit 6 RUNSTDBYRun in Standby This bit controls the behavior of the comparator during standby sleep mode. This bit is not synchronized Value 0 1 Description The comparator is disabled during sleep. The comparator continues to operate during sleep. Bits 4:3 INTSEL[1:0]Interrupt Selection These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Name Value TOGGLE 0x0 RISING 0x1 FALLING 0x2 EOC 0x3 Description Interrupt on comparator output toggle Interrupt on comparator output rising Interrupt on comparator output falling Interrupt on end of comparison (single-shot mode only) Bit 2 SINGLESingle-Shot Mode This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Value 0 1 Description Comparator n operates in continuous measurement mode. Comparator n operates in single-shot mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 940 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) Bit 1 ENABLEEnable Writing a zero to this bit disables comparator n. Writing a one to this bit enables comparator n. Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set. SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled. Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 941 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Analog Comparators (AC) 34.7.13 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x20 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 Access Reset COMPCTRL3 COMPCTRL2 COMPCTRL1 COMPCTRL0 R 0 R 0 R 0 R 0 2 WINCTRL R 0 1 ENABLE R 0 0 SWRST R 0 Bits 3, 4 COMPCTRLxCOMPCTRLx Synchronization Busy This bit is cleared when the synchronization of the COMPCTRLx register between the clock domains is complete. This bit is set when the synchronization of the COMPCTRLx register between clock domains is started. Bits 3, 4, 5, 6 COMPCTRLxCOMPCTRLx Synchronization Busy This bit is cleared when the synchronization of the COMPCTRLx register between the clock domains is complete. This bit is set when the synchronization of the COMPCTRLx register between clock domains is started. Bit 2 WINCTRLWINCTRL Synchronization Busy This bit is cleared when the synchronization of the WINCTRL register between the clock domains is complete. This bit is set when the synchronization of the WINCTRL register between clock domains is started. Bit 1 ENABLEEnable Synchronization Busy This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete. This bit is set when the synchronization of the CTRLA.ENABLE bit between clock domains is started. Bit 0 SWRSTSoftware Reset Synchronization Busy This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST bit between clock domains is started. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 942 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35. Timer/Counter (TC) 35.1 Overview There are up to eight TC peripheral instances. Up to four TCs (TC[3:0]) are in PD1, whereas TC4, present in all device configurations, is always located in power domain PD0. Each TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events or IO pin edges, allowing for capturing of frequency and/or pulse width. A TC can also perform waveform generation, such as frequency generation and pulse-width modulation. 35.2 Features Selectable configuration 8-, 16- or 32-bit TC operation, with compare/capture channels 2 compare/capture channels (CC) with:

Double buffered timer period setting (in 8-bit mode only) Double buffered compare channel Waveform generation Frequency generation Single-slope pulse-width modulation Input capture Event / IO pin edge capture Frequency capture Pulse-width capture Time-stamp capture Minimum and maximum capture (only available on SAM C20/C21 N variants) One input event Interrupts/output events on:

Counter overflow/underflow Compare match or capture Internal prescaler DMA support 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 943 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.3 Block Diagram Figure 35-1. Timer/Counter Block Diagram Base Counter BUFV PERBUF Counter PER COUNT Prescaler

"count"

"clear"

"load"

"direction"

OVF (INT/Event/DMA Req.) ERR (INT Req.) Control Logic TC Input Event Event System

= 0 TOP BOTTOM

t n e v e

E T A D P U Compare/Capture

(Unit x = {0,1}

BUFV CCBUFx

"capture"

Control Logic CCx

Waveform Generation WO[1]

WO[0]

"match"

MCx (INT/Event/DMA Req.) 35.4 Signal Description Table 35-1. Signal Description for TC Signal Name WO[1:0]

Type Digital output Digital input Description Waveform output Capture input For details on the pin mapping for this peripheral, see I/O Ports and Peripheral Pin Select (PPS) from Related Links. One signal can be mapped on several pins 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 944 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 35.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 35.5.1 I/O Lines In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT), see Port Register Summary from Related Links. Related Links 5.10. Port Register Summary 35.5.2 Power Management This peripheral can continue to operate in any Sleep mode (Idle, Standby sleep) where its source clock is running. The interrupts can wake-up the device from Sleep modes. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. 35.5.3 Clocks The TC bus clocks (CLK_TCx_APB) can be enabled and disabled in the Clock and Reset Unit (CRU). The generic clocks (GCLK_TCx) are asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Note:Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to different clock frequencies. See Clock and Reset Unit (CRU) from Related Links. Related Links 13. Clock and Reset Unit (CRU) 35.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral, the DMAC must be configured first (see Direct Memory Access Controller (DMAC) from Related Links). Related Links 22. Direct Memory Access Controller (DMAC) 35.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 35.5.6 Events The events of this peripheral are connected to the Event System. Related Links 26. Event System (EVSYS) 35.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to continue operation during debugging. For more details, see DBGCTRL from Related Links. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 945 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Related Links 35.8.11. DBGCTRL 35.5.8 Register Access Protection Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag Status and Clear register (INTFLAG) Status register (STATUS) Count register (COUNT) Count register (COUNT) Period and Period Buffer registers (PER, PERBUF) Compare/Capture Value registers and Compare/Capture Value Buffer registers (CCx, CCBUFx) Note:Optional write protection is indicated by the "PAC Write Protection" property in the register description. Write protection does not apply for accesses through an external debugger. 35.5.9 Analog Connections Not applicable. 35.6 Functional Description 35.6.1 Principle of Operation The following definitions are used throughout the documentation:

Table 35-2. Timer/Counter Definitions Name TOP ZERO MAX UPDATE Timer Counter CC Description The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the waveform generator mode in Waveform Output Operations. See Waveform Output Operations from Related Links. The counter is ZERO when it contains all zeros. The counter reaches MAX when it contains all ones. The timer/counter signals an update when it reaches ZERO or TOP, depending on the direction settings. The timer/counter clock control is handled by an internal source. The clock control is handled externally (e.g., counting external events). For compare operations, the CC are referred to as compare channels. For capture operations, the CC are referred to as capture channels. Each TC instance has up to two compare/capture channels (CC0 and CC1). The counter in the TC can either count events from the Event System or clock ticks of the GCLK_TCx clock, which may be divided by the prescaler. The counter value is passed to the CCx where it can be either compared to user-defined values or captured. For optimized timing, the CCx and CCBUFx registers share a common resource. When writing into CCBUFx, lock the access to the corresponding CCx register (SYNCBUSY.CCX = 1) until the CCBUFx register value is not loaded into the CCx register (BUFVx == 1). Each buffer register has a buffer valid (BUFV) flag that indicates when the buffer contains a new value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 946 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) The Counter register (COUNT) and the Compare and Capture registers with buffers (CCx and CCBUFx) can be configured as 8-, 16- or 32-bit registers, with corresponding MAX values. Mode settings (CTRLA.MODE) determine the maximum range of the Counter register. In 8-bit mode, a Period Value (PER) register and its Period Buffer Value (PERBUF) register are also available. The counter range and the operating frequency determine the maximum time resolution achievable with the TC peripheral. The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the TOP or ZERO value to determine whether the counter has reached that value. On a comparison match, the TC can request DMA transactions, or generate interrupts or events for the Event System. In a compare operation, the counter value is continuously compared to the values in the CCx registers. In the case of a match, the TC can request DMA transactions, or generate interrupts or events for the Event System. In waveform generator mode, these comparisons are used to set the waveform period or pulse width. Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture selectable edges from an IO pin or internal event from Event System. Related Links 35.6.2.6.1. Waveform Output Operations 35.6.2 Basic Operation 35.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the TC is disabled

(CTRLA.ENABLE =0):

Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits Drive Control register (DRVCTRL) Wave register (WAVE) Event Control register (EVCTRL) Writing to Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of the CTRLA register. Writing to Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a single 32-bit access. Before enabling the TC, the peripheral must be configured by the following steps:

1. 2. 3. 4. 5. 6. 7. 8. Enable the TC bus clock if not already enabled by default (CLK_TCx_APB). Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16-bit. Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register

(WAVE.WAVEGEN). If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register

(CTRLA.PRESCALER). If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC). If desired, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register

(CTRLBSET.ONESHOT). If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter Direction bit in the Control B register (CTRLBSET.DIR). For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control A register (CTRLA.CAPTEN). If desired, enable inversion of the waveform output or IO pin input signal for individual channels via the Invert Enable bit group in the Drive Control register (DRVCTRL.INVEN). 35.6.2.2 Enabling, Disabling, and Resetting The TC is enabled by writing a 1 to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by writing a zero to CTRLA.ENABLE. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 947 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) The TC is reset by writing a 1 to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TC, except DBGCTRL, will be reset to their initial state. See CTRLA from Related Links. The TC should be disabled before the TC is reset in order to avoid undefined behavior. Related Links 35.8.1. CTRLA 35.6.2.3 Prescaler Selection The GCLK_TCx is fed into the internal prescaler. The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the prescaler toggles. If the prescaler value is higher than one, the Counter Update condition can be optionally executed on the next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler

(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description. Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). Note:When counting events, the prescaler is bypassed. The joint stream of prescaler ticks and event action ticks is called CLK_TCx_CNT. Figure 35-2. Prescaler PRESCALER EVACT GCLK_TCx Prescaler GCLK_TCx /

{1,2,4,8,64,256,1024}

EVENT CLK_TCx_CNT COUNT 35.6.2.4 Counter Mode The counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default, the counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:

COUNT8: The 8-bit TC has its own Period Value and Period Buffer Value registers (PER and PERBUF). COUNT16: 16-bit is the default counter mode. There is no dedicated period register in this mode. COUNT32: 32-bit mode is achieved by pairing two 16-bit TC peripherals. TC(2n) is paired with TC(n+1). When paired, the TC peripherals are configured using the registers of the even-numbered TC (TC0 or TC2 respectively). The TC bus clocks (CLK_TCx_APB) for both master and slave TCs need to be enabled. The odd-numbered partner (TC1 or TC3 respectively) will act as a slave, and the Slave bit in the Status register

(STATUS.SLAVE) will be set. The register values of a slave will not reflect the registers of the 32-bit counter. Writing to any of the slave registers will not affect the 32-bit counter. Normal access to the slave COUNT and CCx registers is not allowed. 35.6.2.5 Counter Operations Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TC clock input (CLK_TCx_CNT). A counter clear or reload marks the end of the current counter cycle and the start of a new one. The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero the counter is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it is counting up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. When it is counting down, the counter is reloaded with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set. INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow occurrence

(i.e., a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B register is set

(CTRLBSET.ONESHOT). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 948 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) It is possible to change the counter value (by writing directly in the COUNT register) even when the counter is running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on the counting direction set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been written to it, or the TC has been stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the counter can also be changed when the counter is running. See also the following figure. Figure 35-3. Counter Operation Period (T) Direction Change COUNT written COUNT MAX TOP ZERO DIR

"reload" update

"clear" update Due to asynchronous clock domains, the internal counter settings are written when the synchronization is complete. Normal operation must be used when using the counter as timer base for the capture channels. 35.6.2.5.1 Stop Command and Event Action A Stop command can be issued from software by using Command bits in the Control B Set register

(CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will not retain its current value. All waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP). 35.6.2.5.2 Re-Trigger Command and Event Action A re-trigger command can be issued from software by writing the Command bits in the Control B Set register

(CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event Control register (EVCTRL.EVACT = 0x1, RETRIGGER). When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command is detected while the counter is stopped, the counter will resume counting from the current value in the COUNT register. Note:When a re-trigger event action is configured in the Event Action bits in the Event Control register

(EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event. 35.6.2.5.3 Count Event Action The TC can count events. When an event is received, the counter increases or decreases the value, depending on direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be selected by the Event Action bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT). Note:If this operation mode is selected, PWM generation is not supported. 35.6.2.5.4 Start Event Action The TC can start counting operation on an event when previously stopped. In this configuration, the event has no effect if the counter is already counting. When the peripheral is enabled, the counter operation starts when the event is received or when a re-trigger software command is applied. The Start TC on Event action can be selected by the Event Action bit group in the Event Control register

(EVCTRL.EVACT=0x3, START). 35.6.2.6 Compare Operations By default, the Compare/Capture channel is configured for compare operations. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 949 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation. The Channel x Compare Buffer (CCBUFx) registers provide double buffer capability. The double buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a forced update command (CTRLBSET.CMD=UPDATE). See Double Buffering from Related Links. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output. Related Links 35.6.2.7. Double Buffering 35.6.2.6.1 Waveform Output Operations The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled:

1. Choose a Waveform Generation mode in the Waveform Generation Operation bit in Waveform register

(WAVE.WAVEGEN). 2. Optionally invert the waveform output WO[x] by writing the corresponding Output Waveform x Invert Enable bit in the Driver Control register (DRVCTRL.INVENx). 3. Configure the pins with the I/O Peripheral Pin Select (PPS). See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Note:Event must not be used when the compare channel is set in waveform output operating mode. The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TC_CNT (see Normal Frequency Operation). An interrupt/and or event can be generated on comparison match if enabled. The same condition generates a DMA request. There are four waveform configurations for the Waveform Generation Operation bit group in the Waveform register

(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The configurations are:

Normal frequency (NFRQ) Match frequency (MFRQ) Normal pulse-width modulation (NPWM) Match pulse-width modulation (MPWM) When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit Counter mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16-

and 32-bit Counter mode, TOP is fixed to the maximum (MAX) value of the counter. Normal Frequency Generation (NFRQ) For Normal Frequency Generation, the period time (T) is controlled by the period register (PER) for 8-bit Counter mode and MAX for 16- and 32-bit mode. The waveform generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (INTFLAG.MCx) will be set. Figure 35-4. Normal Frequency Operation Period (T) Direction Change COUNT Written COUNT MAX TOP CCx ZERO WO[x]

"reload" update

"clear" update

"match"

Match Frequency Generation (MFRQ) For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0]

toggles on each Update condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 950 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-5. Match Frequency Operation Period (T) Direction Change COUNT Written COUNT MAX CC0 ZERO WO[0]

"reload" update

"clear" update Normal Pulse-Width Modulation Operation (NPWM) NPWM uses single-slope PWM generation. For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match between COUNT and CCx register values. The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:

log(TOP+1) RPWM_SS =

The PWM frequency (fPWM_SS) depends on TOP value and the peripheral clock frequency (fGCLK_TC), and can be log(2) calculated by the following equation:

fPWM_SS =

Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). fGCLK_TC N(TOP+1) Match Pulse-Width Modulation Operation (MPWM) In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On every overflow/underflow, a one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure). Figure 35-6. Match PWM Operation Period (T) CCx= Zero CCx= TOP MAX CC0 COUNT CC1 ZERO WO[1]

" clear" update

" match"

The following table shows the Update Counter and Overflow Event/Interrupt Generation conditions in different operation modes. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 951 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Table 35-3. Counter Update and Overflow Event/interrupt Conditions in TC Name Operation TOP Update Output Waveform OVFIF/Event On Match On Update Up Down NFRQ Normal Frequency PER TOP/ ZERO Toggle MFRQ Match Frequency CC0 TOP/ ZERO Toggle Stable Stable TOP ZERO TOP ZERO NPWM Single-slope PWM PER TOP/ ZERO See description above. TOP ZERO MPWM Single-slope PWM CC0 TOP/ ZERO Toggle Toggle TOP ZERO Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 35.6.2.7 Double Buffering The Compare Channels (CCx) registers, and the Period (PER) register in 8-bit mode are double buffered. Each buffer register has a buffer valid bit (CCBUFVx or PERBUFV) in the STATUS register, which indicates that the buffer register contains a new valid value that can be copied into the corresponding register. As long as the respective buffer valid status flag (PERBUFV or CCBUFVx) are set to 1, related syncbusy bits are set (SYNCBUSY.PER or SYNCBUSY.CCx), a write to the respective PER/PERBUF or CCx/CCBUFx registers will generate a PAC error, and access to the respective PER or CCx register is invalid. When the buffer valid flag bit in the STATUS register is 1 and the Lock Update bit in the CTRLB register is set to 0, (writing CTRLBCLR.LUPD to 1), double buffering is enabled: the data from buffer registers will be copied into the corresponding register under hardware UPDATE conditions, then the buffer valid flags bit in the STATUS register are automatically cleared by hardware. Note:The software update command (CTRLBSET.CMD=0x3) is acting independently of the LUPD value. A compare register is double buffered as in the following figure. Figure 35-7. Compare Channel Double Buffering

"write enable"

"data write"

CCBUFVx EN CCBUFx UPDATE EN CCx COUNT

"match"

Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a 1 to CTRLBSET.LUPD. Note:In NFRQ, MFRQ or PWM, down-counting counter mode (CTRLBSET.DIR=1), when double buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continuously copied into the PER independently of update conditions. Changing the Period 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 952 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on the waveform generation mode), which is available in 8-bit mode. Any period update on registers (PER or CCx) is effective after the synchronization delay. A counter wraparound can occur in any operation mode when up-counting without buffering (see the following figure). Figure 35-8. Unbuffered Single-Slope Up-Counting Operation Counter Wraparound

"clear" update

"write"

COUNT MAX ZERO New TOP written to PER that is higher than current COUNT New TOP written to PER that is lower than current COUNT COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written to TOP, COUNT will wrap before a compare match. Figure 35-9. Unbuffered Single-Slope Down-Counting Operation COUNT MAX ZERO

"reload" update

"write"

New TOP written to PER that is higher than current COUNT New TOP written to PER that is lower than current COUNT When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in the following figure. This prevents wraparound and the generation of odd waveforms. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 953 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-10. Changing the Period Using Buffering COUNT MAX ZERO 35.6.2.8 Capture Operations

" clear" update

" write"

New TOP written to PER that is higher than current COUNT New TOP written to PER that is lower than current COUNT To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control A register

(CTRLA.CAPTENx) must be written to '1'. A capture trigger can be provided by input event line TC_EV or by asynchronous I/O pin WO[x] for each capture channel or by a TC event. To enable the capture from input event line, Event Input Enable bit in the Event Control register (EVCTRL.TCEI) must be written to '1'. To enable the capture from the I/O pin, the Capture On Pin x Enable bit in the CTRLA register (CTRLA.COPENx) must be written to '1'. Notes:

1. Capture on I/Os is only possible in 'Event' and 'Time-Stamp' capture action modes. Other modes can only use internal events. (If I/Os toggling is needed in other modes, then the I/Os edge must be configured for generating internal events). 2. Capture on an event from the Event System is possible in 'Event', 'PPW/PWP/PW', and 'Time-Stamp' capture action modes. In this case, the event system channels must be configured to operate in asynchronous mode of operation. 3. Depending on CTRLA.COPENx, channel x can be configured for I/Os or internal event capture (both are mutually exclusive). One channel can be configured for I/Os capture while the other uses internal event capture. By default, a capture operation is done when a rising edge is detected on the input signal. Capture on falling edge is available, its activation is depending on the input source:

When the channel is used with a I/O pin, write a '1' to the corresponding Invert Enable bit in the Drive Control register (DRVCTRL.INVENx). When the channel is counting events from the Event System, write a '1' to the TC Event Input Invert Enable bit in Event Control register (EVCTRL.TCINV). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 954 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-11. Capture Double Buffering

"capture"

COUNT BV EN CCBx IF EN CCx

"INT/DMA request"

data read For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional interrupt, event or DMA request. The CCBUFx register value can't be read, all captured data must be read from CCx register. Note:

When up-counting (CTRLBSET.DIR = 0), counter values lower than 1 cannot be captured. To capture the full range including value 0, the TC must be in down-counting mode (CTRLBSET.DIR = 0). 35.6.2.8.1 Event Capture Action on Events or I/Os The compare and capture channels can be used as input capture channels to capture events from the Event System or I/O pins and give them a timestamp. This mode is selected when EVTCTRL.EVACT is configured either as OFF, RETRIGGER, COUNT or START. The following figure shows four capture events for one capture channel. Figure 35-12. Input Capture Timing Events COUNT TOP ZERO Capture 0 Capture 1 Capture 2 Capture 3 The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. 35.6.2.8.2 Period and Pulse-Width (PPW/PWP) Capture Action on Events The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the pulse width and period and to characterize the frequency f and duty cycle of an input signal:

f =

1 T dutyCycle =

tp T 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 955 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-13. PWP Capture Input signal Pulsewitdh (tp) Period (T) events COUNT MAX ZERO

"capture"

CC0 CC1 CC0 CC1 Selecting PWP in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the TC to perform one capture action on the rising edge and another one on the falling edge. The period T will be captured into CC1 and the pulse width tp in CC0. EVCTRL.EVACT = PPW (period and pulse-width) offers identical functionality, but will capture T into CC0 and tp into CC1. The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select whether the wraparound must occur on the rising edge or the falling edge. If EVCTRL.TCINV = 1, the wraparound will happen on the falling edge. In case pin capture is enabled, this can also be achieved by modifying the value of the DRVCTRL.INVENx bit. The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. Note:The corresponding capture is working only if the channel is enabled in capture mode (CTRLA.CAPTENx = 1). Consequently, both channels must be enabled to fully characterize the input. 35.6.2.8.3 Pulse-Width (PW) Capture Action on Events The TC performs the input capture on the falling edge of the input signal. When the edge is detected, the counter value is cleared and the TC stops counting. When a rising edge is detected on the input signal, the counter restarts the counting operation. To enable the operation on opposite edges, the input signal to capture must be inverted (refer to EVCTRL.TCEINV). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 956 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-14. Pulse-Width Capture on Channel 0 Input signal Pulsewidth (tp) events COUNT MAX ZERO

"capture"

"restart"

The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. CC0 CC0 35.6.3 Additional Features 35.6.3.1 One-Shot Operation When one-shot is enabled, the counter automatically stops on the next Counter Overflow or Underflow condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is automatically set and the waveform outputs are set to zero. One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register

(CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC will count until an overflow or underflow occurs and stops counting operation. The one-shot operation can be restarted by a re-trigger software command, a re-trigger event, or a start event. When the counter restarts its operation, STATUS.STOP is automatically cleared. 35.6.3.2 Time-Stamp Capture on Events or I/Os This feature is enabled when the Capture Time Stamp (STAMP) Event Action in Event Control register

(EVCTRL.EVACT) is selected. The counter TOP value must be smaller than MAX. When a capture event from the Event System or the I/O pin is detected, the COUNT value is copied into the corresponding Channel x Compare/Capture Value (CCx) register. In case of an overflow, the MAX value is copied into the corresponding CCx register. When a valid captured value is present in the capture channel register, the corresponding Capture Channel x Interrupt Flag (INTFLAG.MCx) is set. The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and INTFLAG.ERR will be set. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 957 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Figure 35-15. Time Stamp 35.6.3.3 Minimum Capture (SAM C20/C21 N only) The minimum capture is enabled by writing the CAPTMIN mode in the Channel n Capture Mode bits in the Control A register (CTRLA.CAPTMODEn = CAPTMIN). CCx Content:

In CAPTMIN operations, CCx keeps the Minimum captured values. Before enabling this mode of capture, the user must initialize the corresponding CCx register value to a value different from zero. If the CCx register initial value is zero, no captures will be performed using the corresponding channel. MCx Behaviour:

In CAPTMIN operation, capture is performed only when on capture event time, the counter value is lower than the last captured value. The MCx interrupt flag is set only when on capture event time, the counter value is upper or equal to the value captured on the previous event. So interrupt flag is set when a new absolute local Minimum value has been detected. 35.6.3.4 Maximum Capture (SAM C20/C21 N only) The maximum capture is enabled by writing the CAPTMAX mode in the Channel n Capture Mode bits in the Control A register (CTRLA.CAPTMODEn = CAPTMAX). CCx Content:

In CAPTMAX operations, CCx keeps the Maximum captured values. Before enabling this mode of capture, the user must initialize the corresponding CCx register value to a value different from TOP. If the CCx register initial value is TOP, no captures will be performed using the corresponding channel. MCx Behaviour:

In CAPTMAX operation, capture is performed only when on capture event time, the counter value is upper than the last captured value. The MCx interrupt flag is set only when on capture event time, the counter value is lower or equal to the value captured on the previous event. So interrupt flag is set when a new absolute local Maximum value has been detected. Figure 35-16. Maximum Capture Operation with CC0 Initialized with ZERO Value COUNT TOP CC0 ZERO Input event CC0 Event/

Interrupt 35.6.4 DMA Operation The TC can generate the following DMA requests:

"clear" update

"match"

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 958 Microchip Confidential MAXZEROCOUNTTOP"capture""overflow"EventsCCx ValueCOUNTCOUNTTOPMAXCOUNTConfidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Overflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is detected, the request is cleared by hardware on DMA acknowledge. Match or Capture Channel x (MCx): for a compare channel, the request is set on each compare match detection, the request is cleared by hardware on DMA acknowledge. For a capture channel, the request is set when valid data is present in the CCx register, and cleared when CCx register is read. 35.6.5 Interrupts The TC has the following interrupt sources:

Overflow/Underflow (OVF) Match or Capture Channel x (MCx) Capture Overflow Error (ERR) Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a 1 to the corresponding bit in the Interrupt Enable Set register

(INTENSET), and disabled by writing a 1 to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset. See INTFLAG from Related Links for more details on how to clear the interrupt flags. The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 35.8.7. INTFLAG 35.6.6 Events The TC can generate the following output events:

Overflow/Underflow (OVF) Match or Capture Channel x (MCX0-1) Writing a 1 to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output event. The output event is disabled by writing EVCTRL.MCEOx=0. One of the following event actions can be selected by the Event Action bit group in the Event Control register

(EVCTRL.EVACT):

Disable event action (OFF) Start TC (START) Re-trigger TC (RETRIGGER) Count on event (COUNT) Capture time stamp (STAMP) Capture Period (PPW and PWP) Capture Pulse Width (PW) Writing a 1 to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events (EVU0-2) to the TC. Writing a 0 to this bit disables input events to the TC. The TC requires only asynchronous event inputs. See Event System (EVSYS) from Related Links for additional information on configuring the asynchronous events. Related Links 26. Event System (EVSYS) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 959 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.6.7 Sleep Mode Operation The TC can be configured to operate in any sleep mode (Idle, Standby Sleep). To be able to run in standby sleep mode, the RUNSTDBY bit in the Control A register (CTRLA.RUNSTDBY) must be '1'. This peripheral can wake up the device from any sleep mode using interrupts or perform actions through the Event System. If the On Demand bit in the Control A register (CTRLA.ONDEMAND) is written to '1', the module stops requesting its peripheral clock when the STOP bit in STATUS register (STATUS.STOP) is set to '1'. When a re-trigger or start condition is detected, the TC requests the clock before the operation starts. 35.6.8 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE) Capture Channel Buffer Valid bit in STATUS register (STATUS.CCBUFVx) The following registers are synchronized when written:

Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) Count Value register (COUNT) Period Value and Period Buffer Value registers (PER and PERBUF) Channel x Compare/Capture Value and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx) The following registers are synchronized when read:

Count Value register (COUNT): synchronization is done on demand through READSYNC command

(CTRLBSET.CMD) Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) Channel x Compare/Capture Value (CCx) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 960 Microchip Confidential Confidential 0x00 CTRLA CTRLBCLR CTRLBSET EVCTRL INTENCLR INTENSET INTFLAG STATUS WAVE DRVCTRL Reserved DBGCTRL SYNCBUSY Reserved 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11

... 0x13 0x14 0x15

... 0x1A 0x1B 0x1C 0x1D 0x1E

... 0x2E 0x2F 0x30 0x31 PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.7 Register Summary See TCx (x = 0 to 7) module in the Product Memory Mapping Overview from Related Links for base address based on the TC instant used. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ONDEMAND RUNSTDBY PRESCSYNC[1:0]

MODE[1:0]

ENABLE SWRST DMAOS ALOCK PRESCALER[2:0]

COPEN1 COPEN0 CAPTMODE1[1:0]

CAPTEN1 CAPTEN0 CAPTMODE0[1:0]

CMD[2:0]

CMD[2:0]

TCEI MCEO1 MC1 MC1 MC1 TCINV MCEO0 MC0 MC0 MC0 CCBUFV1 CCBUFV0 PERBUFV ONESHOT ONESHOT LUPD LUPD DIR DIR EVACT[2:0]

ERR ERR ERR OVFEO OVF OVF OVF SLAVE STOP WAVEGEN[1:0]

INVEN1 INVEN0 DBGRUN CC1 CC0 PER COUNT STATUS CTRLB ENABLE SWRST COUNT 7:0 COUNT[7:0]

Reserved PER CC0 CC1 Reserved PERBUF CCBUF0 CCBUF1 7:0 7:0 7:0 7:0 7:0 7:0 PER[7:0]

CC[7:0]

CC[7:0]

PERBUF[7:0]

CCBUF[7:0]

CCBUF[7:0]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 35.8 Register Description - 8-bit Mode Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 961 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 962 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Enable-Protected CTRLA 0x00 0x00000000 Bit 31 30 29 28 27 CAPTMODE1[1:0]

Access Reset Bit 23 22 Access Reset Bit Access Reset 15 DMAOS R/W 0 R/W 0 20 COPEN0 R/W 0 21 COPEN1 R/W 0 14 13 12 R/W 0 19 11 ALOCK R/W 0 Bit 7 ONDEMAND Access Reset R/W 0 6 RUNSTDBY R/W 0 5 4 PRESCSYNC[1:0]

R/W 0 R/W 0 MODE[1:0]

3 R/W 0 Bits 28:27 CAPTMODE1[1:0]Capture mode Channel 1 These bits select the channel 1 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 25:24 CAPTMODE0[1:0]Capture mode Channel 0 These bits select the channel 0 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 20, 21 COPENxCapture On Pin x Enable [x=1..0]

Description Default capture Minimum capture Maximum capture Reserved Description Default capture Minimum capture Maximum capture Reserved 26 18 10 R/W 0 2 R/W 0 25 24 CAPTMODE0[1:0]

R/W 0 R/W 0 17 CAPTEN1 R/W 0 16 CAPTEN0 R/W 0 9 PRESCALER[2:0]

R/W 0 8 R/W 0 1 ENABLE R/W 0 0 SWRST W 0 Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input. This bit is not synchronized. Value 0 1 Description Event from Event System is selected as trigger source for capture operation on channel x. I/O pin is selected as trigger source for capture operation on channel x. Bits 16, 17 CAPTENxCapture Channel x Enable [x=1..0]

Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value 0 1 Description CAPTEN disables capture on channel x. CAPTEN enables capture on channel x. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 963 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Bit 15 DMAOSDMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command. Writing a '0' to this bit will generate DMA triggers on each TC cycle. This bit is not synchronized. Bit 11 ALOCKAuto Lock When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event. This bit is not synchronized. Value 0 1 Description The LUPD bit is not affected on overflow/underflow, and re-trigger event. The LUPD bit is set on each overflow/underflow or re-trigger event. Bits 10:8 PRESCALER[2:0]Prescaler These bits select the counter prescaler factor. These bits are not synchronized. Name Value DIV1 0x0 DIV2 0x1 DIV4 0x2 DIV8 0x3 DIV16 0x4 DIV64 0x5 DIV256 0x6 DIV1024 0x7 Description Prescaler: GCLK_TC Prescaler: GCLK_TC/2 Prescaler: GCLK_TC/4 Prescaler: GCLK_TC/8 Prescaler: GCLK_TC/16 Prescaler: GCLK_TC/64 Prescaler: GCLK_TC/256 Prescaler: GCLK_TC/1024 Bit 7 ONDEMANDClock On Demand This bit selects the clock requirements when the TC is stopped. In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'. This bit is not synchronized. Value 0 Description The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when its operation is stopped (STATUS.STOP=1). The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the clock. The clock is requested when a software re-trigger command is applied or when an event with start/re-trigger action is detected. 1 Bit 6 RUNSTDBYRun in Standby This bit is used to keep the TC running in standby mode. This bit is not synchronized. Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 PRESCSYNC[1:0]Prescaler and Counter Synchronization These bits select whether the counter must wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized. Name Value GCLK 0x0 PRESC 0x1 RESYNC 0x2

0x3 Description Reload or reset the counter on next generic clock Reload or reset the counter on next prescaler clock Reload or reset the counter on next generic clock. Reset the prescaler counter Reserved Bits 3:2 MODE[1:0]Timer Counter Mode These bits select the counter mode. These bits are not synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 964 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Value 0x0 0x1 0x2 0x3 Name COUNT16 COUNT8 COUNT32

Bit 1 ENABLEEnable Description Counter in 16-bit mode Counter in 8-bit mode Counter in 32-bit mode Reserved Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. This bit is not enable-protected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 965 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.2 Control B Clear Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized CTRLBCLR 0x04 0x00 This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. This bit has no effect when input capture operation is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the LUPD bit. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 966 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.3 Control B Set Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-synchronized, Write-Synchronized CTRLBSET 0x05 0x00 This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a value different from 0x0 to these bits will issue a command for execution. Value 0x0 0x1 0x2 0x3 0x4 Description No action Force a start, restart or retrigger Force a stop Force update of double buffered registers Force a read synchronization of COUNT Name NONE RETRIGGER STOP UPDATE READSYNC Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect. Writing a '1' to this bit will enable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the LUPD bit. This bit has no effect when input capture operation is enabled. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 967 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.4 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x06 0x0000 Bit 15 14 Access Reset Bit 7 6 Access Reset 13 MCEO1 R/W 0 5 TCEI R/W 0 12 MCEO0 R/W 0 4 TCINV R/W 0 11 10 9 3 2 R/W 0 1 EVACT[2:0]

R/W 0 8 OVFEO R/W 0 0 R/W 0 Bits 12, 13 MCEOxMatch or Capture Channel x Event Output Enable [x = 1..0]

These bits enable the generation of an event for every match or capture on channel x. Value 0 1 Description Match/Capture event on channel x is disabled and will not be generated. Match/Capture event on channel x is enabled and will be generated for every compare/capture. Bit 8 OVFEOOverflow/Underflow Event Output Enable This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter overflows/underflows. Value 0 1 Description Overflow/Underflow event is disabled and will not be generated. Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. Bit 5 TCEITC Event Enable This bit is used to enable asynchronous input events to the TC. Value 0 1 Description Incoming events are disabled. Incoming events are enabled. Bit 4 TCINVTC Inverted Event Input Polarity This bit inverts the asynchronous input event source. Value 0 1 Description Input event source is not inverted. Input event source is inverted. Bits 2:0 EVACT[2:0]Event Action These bits define the event action the TC will perform on an event. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Event action disabled Start, restart or retrigger TC on event Count on event Start TC on event Time stamp capture Period captured in CC0, pulse width in CC1 Period captured in CC1, pulse width in CC0 Pulse width capture Name OFF RETRIGGER COUNT START STAMP PPW PWP PW 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 968 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.5 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x08 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 969 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.6 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x09 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 970 Microchip Confidential Confidential 35.8.7 Interrupt Flag Status and Clear PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Name:

Offset:

Reset:

Property:

INTFLAG 0x0A 0x00

Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x [x = 1..0]

This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is 1. Writing a 0 to these bits has no effect. Writing a 1 to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In capture operation, this flag is automatically cleared when CCx register is read. Bit 1 ERRError Interrupt Flag This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is set, in which case there is no place to store the new capture. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Error interrupt flag. Bit 0 OVFOverflow Interrupt Flag This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or INTENSET.OVF is 1. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Overflow interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 971 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.8 Status STATUS Name:

0x0B Offset:

Reset:

0x01 Property: Read-Synchronized Bit 7 6 Access Reset 5 CCBUFV1 R/W 0 4 CCBUFV0 R/W 0 3 PERBUFV R/W 0 2 1 SLAVE R 0 0 STOP R 1 Bits 4, 5 CCBUFVxChannel x Compare or Capture Buffer Valid [x = 1..0]

For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a 1 to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on UPDATE condition. For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is cleared automatically when the CCx register is read. Bit 3 PERBUFVPeriod Buffer Valid This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing 1 to the corresponding location when CTRLB.LUPD is set, or automatically cleared by hardware on UPDATE condition. This bit is available only in 8-bit mode and will always read zero in 16- and 32-bit modes. Bit 1 SLAVEClient Status Flag This bit is only available in 32-bit mode on the Client TC (i.e., TC1, TC3, TC5 and/or TC7). The bit is set when the associated Host TC (TC0, TC2, TC4 and/or TC6, respectively) is set to run in 32-bit mode. Bit 0 STOPStop Status Flag This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is 1. Value 0 1 Description Counter is running. Counter is stopped. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 972 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.9 Waveform Generation Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected WAVE 0x0C 0x00 Bit 7 6 5 4 3 2 Access Reset Bits 1:0 WAVEGEN[1:0]Waveform Generation Mode 1 0 WAVEGEN[1:0]

R/W 0 R/W 0 These bits select the waveform generation operation. They affect the top value, as shown in Waveform Output Operations. They also control whether frequency or PWM waveform generation must be used. The waveform generation operations are explained in Waveform Output Operations. See Waveform Output Operations from Related Links. These bits are not synchronized. Value Name Operation Top Value Output Waveform on Match Output Waveform on Wraparound 0x0 0x1 0x2 0x3 1. NFRQ MFRQ NPWM MPWM Normal frequency Match frequency Normal PWM Match PWM PER1 / Max CC0 PER1 / Max CC0 Toggle Toggle Set Set No action No action Clear Clear This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode, it is the respective MAX value. Related Links 35.6.2.6.1. Waveform Output Operations 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 973 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.10 Driver Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DRVCTRL 0x0D 0x00 Bit 7 6 5 4 3 2 Access Reset 1 INVEN1 R/W 0 0 INVEN0 R/W 0 Bits 0, 1 INVENxOutput Waveform x Invert Enable [x=1..0]

Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value 0 1 Description Disable inversion of the WO[x] output and IO input pin. Enable inversion of the WO[x] output and IO input pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 974 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.11 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x0F 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNRun in Debug Mode DBGRUN R/W 0 This bit is not affected by a software Reset, and must not be changed by software while the TC is enabled. Value 0 1 Description The TC is halted when the device is halted in debug mode. The TC continues normal operation when the device is halted in debug mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 975 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.12 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x10 0x00

Bit Access Reset 7 CC1 R 0 6 CC0 R 0 5 PER R 0 4 COUNT R 0 3 STATUS R 0 2 CTRLB R 0 1 ENABLE R 0 0 SWRST R 0 Bits 6, 7 CCxCompare/Capture Channel x Synchronization Busy [x=0..1]

For details on CC channels number, refer to each TC feature list. This bit is set when the synchronization of CCx between clock domains is started. This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared when the STATUS.CCBUFx bit is cleared. Bit 5 PERPER Synchronization Busy This bit is cleared when the synchronization of PER between the clock domains is complete. This bit is set when the synchronization of PER between clock domains is started. This bit is also set when the PER is written, and cleared on update condition. The bit is automatically cleared when the STATUS.PERBUF bit is cleared. Bit 4 COUNTCOUNT Synchronization Busy This bit is cleared when the synchronization of COUNT between the clock domains is complete. This bit is set when the synchronization of COUNT between clock domains is started. Bit 3 STATUSSTATUS Synchronization Busy This bit is cleared when the synchronization of STATUS between the clock domains is complete. This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the synchronization of STATUS between clock domains is started. Bit 2 CTRLBCTRLB Synchronization Busy This bit is cleared when the synchronization of CTRLB between the clock domains is complete. This bit is set when the synchronization of CTRLB between clock domains is started. Bit 1 ENABLEENABLE Synchronization Busy This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete. This bit is set when the synchronization of ENABLE bit between clock domains is started. Bit 0 SWRSTSWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 976 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.13 Counter Value, 8-bit Mode Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized COUNT 0x14 0x00 Note:Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC). Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 3 COUNT[7:0]

R/W 0 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bits 7:0 COUNT[7:0] Counter Value These bits contain the current counter value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 977 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.14 Period Value, 8-bit Mode PER Name:

0x1B Offset:

Reset:

0xFF Property: Write-Synchronized Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 PER[7:0]

3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 1 Bits 7:0 PER[7:0]Period Value These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 978 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.15 Channel x Compare/Capture Value, 8-bit Mode CCx Name:

0x1C + x*0x01 [x=0..1]

Offset:

Reset:

0x00 Property: Write-Synchronized Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 CC[7:0]

4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bits 7:0 CC[7:0]Channel x Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM

(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 979 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.16 Period Buffer Value, 8-bit Mode PERBUF Name:

0x2F Offset:

Reset:

0xFF Property: Write-Synchronized Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 3 PERBUF[7:0]

R/W 0 R/W 0 2 R/W 0 1 R/W 0 0 R/W 1 Bits 7:0 PERBUF[7:0]Period Buffer Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 980 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.8.17 Channel x Compare Buffer Value, 8-bit Mode CCBUFx Name:

0x30 + x*0x01 [x=0..1]

Offset:

Reset:

0x00 Property: Write-Synchronized Bit 7 Access Reset R/W 0 6 R/W 0 5 R/W 0 4 3 CCBUF[7:0]

R/W 0 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bits 7:0 CCBUF[7:0]Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 981 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.9 Register Summary See TCx (x = 0 to 7) module in the Product Memory Mapping Overview from Related Links for base address based on the TC instant used. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11

... 0x13 0x14 0x16

... 0x19 0x1A 0x1C 0x1E 0x20

... 0x2D 0x2E CTRLBCLR CTRLBSET EVCTRL INTENCLR INTENSET INTFLAG STATUS WAVE DRVCTRL Reserved DBGCTRL SYNCBUSY Reserved COUNT Reserved PER CC0 CC1 Reserved PERBUF 0x30 CCBUF0 0x32 CCBUF1 7:0 15:8 23:16 31:24 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 ONDEMAND RUNSTDBY PRESCSYNC[1:0]

MODE[1:0]

ENABLE SWRST DMAOS ALOCK PRESCALER[2:0]

COPEN1 COPEN0 CAPTMODE1[1:0]

CAPTEN1 CAPTEN0 CAPTMODE0[1:0]

CMD[2:0]

CMD[2:0]

TCEI MCEO1 MC1 MC1 MC1 TCINV MCEO0 MC0 MC0 MC0 CCBUFV1 CCBUFV0 PERBUFV ONESHOT ONESHOT LUPD LUPD DIR DIR EVACT[2:0]

ERR ERR ERR OVFEO OVF OVF OVF SLAVE STOP WAVEGEN[1:0]

INVEN1 INVEN0 DBGRUN CC1 CC0 PER COUNT STATUS CTRLB ENABLE SWRST COUNT[7:0]

COUNT[15:8]

PER[7:0]

PER[15:8]

CC[7:0]

CC[15:8]

CC[7:0]

CC[15:8]

PERBUF[7:0]

PERBUF[15:8]

CCBUF[7:0]

CCBUF[15:8]

CCBUF[7:0]

CCBUF[15:8]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 35.10 Register Description - 16-bit Mode Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 982 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 983 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Enable-Protected CTRLA 0x00 0x00000000 Bit 31 30 29 28 27 CAPTMODE1[1:0]

Access Reset Bit 23 22 Access Reset Bit Access Reset 15 DMAOS R/W 0 R/W 0 20 COPEN0 R/W 0 21 COPEN1 R/W 0 14 13 12 R/W 0 19 11 ALOCK R/W 0 Bit 7 ONDEMAND Access Reset R/W 0 6 RUNSTDBY R/W 0 5 4 PRESCSYNC[1:0]

R/W 0 R/W 0 MODE[1:0]

3 R/W 0 Bits 28:27 CAPTMODE1[1:0]Capture mode Channel 1 These bits select the channel 1 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 25:24 CAPTMODE0[1:0]Capture mode Channel 0 These bits select the channel 0 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 20, 21 COPENxCapture On Pin x Enable [x=1..0]

Description Default capture Minimum capture Maximum capture Reserved Description Default capture Minimum capture Maximum capture Reserved 26 18 10 R/W 0 2 R/W 0 25 24 CAPTMODE0[1:0]

R/W 0 R/W 0 17 CAPTEN1 R/W 0 16 CAPTEN0 R/W 0 9 PRESCALER[2:0]

R/W 0 8 R/W 0 1 ENABLE R/W 0 0 SWRST W 0 Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input. This bit is not synchronized. Value 0 1 Description Event from Event System is selected as trigger source for capture operation on channel x. I/O pin is selected as trigger source for capture operation on channel x. Bits 16, 17 CAPTENxCapture Channel x Enable [x=1..0]

Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value 0 1 Description CAPTEN disables capture on channel x. CAPTEN enables capture on channel x. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 984 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Bit 15 DMAOSDMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command. Writing a '0' to this bit will generate DMA triggers on each TC cycle. This bit is not synchronized. Bit 11 ALOCKAuto Lock When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event. This bit is not synchronized. Value 0 1 Description The LUPD bit is not affected on overflow/underflow, and re-trigger event. The LUPD bit is set on each overflow/underflow or re-trigger event. Bits 10:8 PRESCALER[2:0]Prescaler These bits select the counter prescaler factor. These bits are not synchronized. Name Value DIV1 0x0 DIV2 0x1 DIV4 0x2 DIV8 0x3 DIV16 0x4 DIV64 0x5 DIV256 0x6 DIV1024 0x7 Description Prescaler: GCLK_TC Prescaler: GCLK_TC/2 Prescaler: GCLK_TC/4 Prescaler: GCLK_TC/8 Prescaler: GCLK_TC/16 Prescaler: GCLK_TC/64 Prescaler: GCLK_TC/256 Prescaler: GCLK_TC/1024 Bit 7 ONDEMANDClock On Demand This bit selects the clock requirements when the TC is stopped. In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'. This bit is not synchronized. Value 0 Description The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when its operation is stopped (STATUS.STOP=1). The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the clock. The clock is requested when a software re-trigger command is applied or when an event with start/re-trigger action is detected. 1 Bit 6 RUNSTDBYRun in Standby This bit is used to keep the TC running in standby mode. This bit is not synchronized. Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 PRESCSYNC[1:0]Prescaler and Counter Synchronization These bits select whether the counter must wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized. Name Value GCLK 0x0 PRESC 0x1 RESYNC 0x2

0x3 Description Reload or reset the counter on next generic clock Reload or reset the counter on next prescaler clock Reload or reset the counter on next generic clock. Reset the prescaler counter Reserved Bits 3:2 MODE[1:0]Timer Counter Mode These bits select the counter mode. These bits are not synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 985 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Value 0x0 0x1 0x2 0x3 Name COUNT16 COUNT8 COUNT32

Bit 1 ENABLEEnable Description Counter in 16-bit mode Counter in 8-bit mode Counter in 32-bit mode Reserved Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. This bit is not enable-protected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 986 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.2 Control B Clear Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized CTRLBCLR 0x04 0x00 This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. This bit has no effect when input capture operation is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the LUPD bit. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 987 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.3 Control B Set Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-synchronized, Write-Synchronized CTRLBSET 0x05 0x00 This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a value different from 0x0 to these bits will issue a command for execution. Value 0x0 0x1 0x2 0x3 0x4 Description No action Force a start, restart or retrigger Force a stop Force update of double buffered registers Force a read synchronization of COUNT Name NONE RETRIGGER STOP UPDATE READSYNC Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect. Writing a '1' to this bit will enable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the LUPD bit. This bit has no effect when input capture operation is enabled. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 988 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.4 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x06 0x0000 Bit 15 14 Access Reset Bit 7 6 Access Reset 13 MCEO1 R/W 0 5 TCEI R/W 0 12 MCEO0 R/W 0 4 TCINV R/W 0 11 10 9 3 2 R/W 0 1 EVACT[2:0]

R/W 0 8 OVFEO R/W 0 0 R/W 0 Bits 12, 13 MCEOxMatch or Capture Channel x Event Output Enable [x = 1..0]

These bits enable the generation of an event for every match or capture on channel x. Value 0 1 Description Match/Capture event on channel x is disabled and will not be generated. Match/Capture event on channel x is enabled and will be generated for every compare/capture. Bit 8 OVFEOOverflow/Underflow Event Output Enable This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter overflows/underflows. Value 0 1 Description Overflow/Underflow event is disabled and will not be generated. Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. Bit 5 TCEITC Event Enable This bit is used to enable asynchronous input events to the TC. Value 0 1 Description Incoming events are disabled. Incoming events are enabled. Bit 4 TCINVTC Inverted Event Input Polarity This bit inverts the asynchronous input event source. Value 0 1 Description Input event source is not inverted. Input event source is inverted. Bits 2:0 EVACT[2:0]Event Action These bits define the event action the TC will perform on an event. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Event action disabled Start, restart or retrigger TC on event Count on event Start TC on event Time stamp capture Period captured in CC0, pulse width in CC1 Period captured in CC1, pulse width in CC0 Pulse width capture Name OFF RETRIGGER COUNT START STAMP PPW PWP PW 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 989 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.5 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x08 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 990 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.6 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x09 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 991 Microchip Confidential Confidential 35.10.7 Interrupt Flag Status and Clear PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Name:

Offset:

Reset:

Property:

INTFLAG 0x0A 0x00

Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x [x = 1..0]

This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is 1. Writing a 0 to these bits has no effect. Writing a 1 to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In capture operation, this flag is automatically cleared when CCx register is read. Bit 1 ERRError Interrupt Flag This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is set, in which case there is no place to store the new capture. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Error interrupt flag. Bit 0 OVFOverflow Interrupt Flag This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or INTENSET.OVF is 1. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Overflow interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 992 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.8 Status STATUS Name:

0x0B Offset:

Reset:

0x01 Property: Read-Synchronized Bit 7 6 Access Reset 5 CCBUFV1 R/W 0 4 CCBUFV0 R/W 0 3 PERBUFV R/W 0 2 1 SLAVE R 0 0 STOP R 1 Bits 4, 5 CCBUFVxChannel x Compare or Capture Buffer Valid [x = 1..0]

For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a 1 to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on UPDATE condition. For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is cleared automatically when the CCx register is read. Bit 3 PERBUFVPeriod Buffer Valid This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing 1 to the corresponding location when CTRLB.LUPD is set, or automatically cleared by hardware on UPDATE condition. This bit is available only in 8-bit mode and will always read zero in 16- and 32-bit modes. Bit 1 SLAVEClient Status Flag This bit is only available in 32-bit mode on the Client TC (i.e., TC1, TC3, TC5 and/or TC7). The bit is set when the associated Host TC (TC0, TC2, TC4 and/or TC6, respectively) is set to run in 32-bit mode. Bit 0 STOPStop Status Flag This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is 1. Value 0 1 Description Counter is running. Counter is stopped. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 993 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.9 Waveform Generation Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected WAVE 0x0C 0x00 Bit 7 6 5 4 3 2 Access Reset Bits 1:0 WAVEGEN[1:0]Waveform Generation Mode 1 0 WAVEGEN[1:0]

R/W 0 R/W 0 These bits select the waveform generation operation. They affect the top value, as shown in Waveform Output Operations. They also control whether frequency or PWM waveform generation must be used. The waveform generation operations are explained in Waveform Output Operations. See Waveform Output Operations from Related Links. These bits are not synchronized. Value Name Operation Top Value Output Waveform on Match Output Waveform on Wraparound 0x0 0x1 0x2 0x3 1. NFRQ MFRQ NPWM MPWM Normal frequency Match frequency Normal PWM Match PWM PER1 / Max CC0 PER1 / Max CC0 Toggle Toggle Set Set No action No action Clear Clear This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode, it is the respective MAX value. Related Links 35.6.2.6.1. Waveform Output Operations 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 994 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.10 Driver Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DRVCTRL 0x0D 0x00 Bit 7 6 5 4 3 2 Access Reset 1 INVEN1 R/W 0 0 INVEN0 R/W 0 Bits 0, 1 INVENxOutput Waveform x Invert Enable [x=1..0]

Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value 0 1 Description Disable inversion of the WO[x] output and IO input pin. Enable inversion of the WO[x] output and IO input pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 995 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.11 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x0F 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNRun in Debug Mode DBGRUN R/W 0 This bit is not affected by a software Reset, and must not be changed by software while the TC is enabled. Value 0 1 Description The TC is halted when the device is halted in debug mode. The TC continues normal operation when the device is halted in debug mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 996 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.12 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x10 0x00

Bit Access Reset 7 CC1 R 0 6 CC0 R 0 5 PER R 0 4 COUNT R 0 3 STATUS R 0 2 CTRLB R 0 1 ENABLE R 0 0 SWRST R 0 Bits 6, 7 CCxCompare/Capture Channel x Synchronization Busy [x=0..1]

For details on CC channels number, refer to each TC feature list. This bit is set when the synchronization of CCx between clock domains is started. This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared when the STATUS.CCBUFx bit is cleared. Bit 5 PERPER Synchronization Busy This bit is cleared when the synchronization of PER between the clock domains is complete. This bit is set when the synchronization of PER between clock domains is started. This bit is also set when the PER is written, and cleared on update condition. The bit is automatically cleared when the STATUS.PERBUF bit is cleared. Bit 4 COUNTCOUNT Synchronization Busy This bit is cleared when the synchronization of COUNT between the clock domains is complete. This bit is set when the synchronization of COUNT between clock domains is started. Bit 3 STATUSSTATUS Synchronization Busy This bit is cleared when the synchronization of STATUS between the clock domains is complete. This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the synchronization of STATUS between clock domains is started. Bit 2 CTRLBCTRLB Synchronization Busy This bit is cleared when the synchronization of CTRLB between the clock domains is complete. This bit is set when the synchronization of CTRLB between clock domains is started. Bit 1 ENABLEENABLE Synchronization Busy This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete. This bit is set when the synchronization of ENABLE bit between clock domains is started. Bit 0 SWRSTSWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 997 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.13 Counter Value, 16-bit Mode Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized COUNT 0x14 0x00 Note:Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC). Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 COUNT[15:8]

R/W 0 4 R/W 0 3 COUNT[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 COUNT[15:0] Counter Value These bits contain the current counter value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 998 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.14 Period Value, 16-bit Mode Name:

Offset:

Reset:

Property: Write-Synchronized PER 0x1A 0xFFFF Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 PER[15:8]

PER[7:0]

12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 1 Bits 15:0 PER[15:0]Period Value These bits hold the value of the TC period count. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 999 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.15 Channel x Compare/Capture Value, 16-bit Mode CCx Name:

0x1C + x*0x02 [x=0..1]

Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 CC[15:8]

CC[7:0]

12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 CC[15:0]Channel x Compare/Capture Value These bits contain the compare/capture value in 16-bit TC mode. In Match frequency (MFRQ) or Match PWM

(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1000 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.16 Period Buffer Value, 16-bit Mode Name:

Offset:

Reset:

Property: Write-Synchronized PERBUF 0x2E 0xFFFF Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 PERBUF[15:8]

R/W 0 4 R/W 0 3 PERBUF[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 1 Bits 15:0 PERBUF[15:0]Period Buffer Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1001 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.10.17 Channel x Compare Buffer Value, 16-bit Mode CCBUFx Name:

0x30 + x*0x02 [x=0..1]

Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 14 R/W 0 6 R/W 0 13 R/W 0 5 R/W 0 12 11 CCBUF[15:8]

R/W 0 4 R/W 0 3 CCBUF[7:0]

R/W 0 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 Bits 15:0 CCBUF[15:0]Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1002 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.11 Register Summary See TCx (x = 0 to 7) module in the Product Memory Mapping Overview from Related Links for base address based on the TC instant used. Note:All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11

... 0x13 CTRLBCLR CTRLBSET EVCTRL INTENCLR INTENSET INTFLAG STATUS WAVE DRVCTRL Reserved DBGCTRL SYNCBUSY Reserved 0x14 COUNT 0x18

... 0x1B Reserved 0x1C CC0 0x20 CC1 0x24

... 0x2F Reserved 0x30 CCBUF0 0x34 CCBUF1 7:0 15:8 23:16 31:24 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 ONDEMAND RUNSTDBY PRESCSYNC[1:0]

MODE[1:0]

ENABLE SWRST DMAOS ALOCK PRESCALER[2:0]

COPEN1 COPEN0 CAPTMODE1[1:0]

CAPTEN1 CAPTEN0 CAPTMODE0[1:0]

CMD[2:0]

CMD[2:0]

TCEI MCEO1 MC1 MC1 MC1 TCINV MCEO0 MC0 MC0 MC0 CCBUFV1 CCBUFV0 PERBUFV ONESHOT ONESHOT LUPD LUPD DIR DIR EVACT[2:0]

ERR ERR ERR OVFEO OVF OVF OVF SLAVE STOP WAVEGEN[1:0]

INVEN1 INVEN0 DBGRUN CC1 CC0 PER COUNT STATUS CTRLB ENABLE SWRST COUNT[7:0]

COUNT[15:8]

COUNT[23:16]

COUNT[31:24]

CC[7:0]

CC[15:8]

CC[23:16]

CC[31:24]

CC[7:0]

CC[15:8]

CC[23:16]

CC[31:24]

CCBUF[7:0]

CCBUF[15:8]

CCBUF[23:16]

CCBUF[31:24]

CCBUF[7:0]

CCBUF[15:8]

CCBUF[23:16]

CCBUF[31:24]

Related Links 5.4.1.9. CLR, SET and INV Registers 7. Product Memory Mapping Overview 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1003 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12 Register Description - 32-bit Mode Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write protection is denoted by the PAC Write-Protection property in each individual register description. Some registers are synchronized when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable protection is denoted by the Enable-Protected property in each individual register description. Following conventions are used in the register description:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown HS = Hardware Set HC = Hardware Cleared 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1004 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Enable-Protected CTRLA 0x00 0x00000000 Bit 31 30 29 28 27 CAPTMODE1[1:0]

Access Reset Bit 23 22 Access Reset Bit Access Reset 15 DMAOS R/W 0 R/W 0 20 COPEN0 R/W 0 21 COPEN1 R/W 0 14 13 12 R/W 0 19 11 ALOCK R/W 0 Bit 7 ONDEMAND Access Reset R/W 0 6 RUNSTDBY R/W 0 5 4 PRESCSYNC[1:0]

R/W 0 R/W 0 MODE[1:0]

3 R/W 0 Bits 28:27 CAPTMODE1[1:0]Capture mode Channel 1 These bits select the channel 1 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 25:24 CAPTMODE0[1:0]Capture mode Channel 0 These bits select the channel 0 capture mode. Value 0x0 0x1 0x2 0x3 Name DEFAULT CAPTMIN CAPTMAX Bits 20, 21 COPENxCapture On Pin x Enable [x=1..0]

Description Default capture Minimum capture Maximum capture Reserved Description Default capture Minimum capture Maximum capture Reserved 26 18 10 R/W 0 2 R/W 0 25 24 CAPTMODE0[1:0]

R/W 0 R/W 0 17 CAPTEN1 R/W 0 16 CAPTEN0 R/W 0 9 PRESCALER[2:0]

R/W 0 8 R/W 0 1 ENABLE R/W 0 0 SWRST W 0 Bit x of COPEN[1:0] selects the trigger source for capture operation, either events or I/O pin input. This bit is not synchronized. Value 0 1 Description Event from Event System is selected as trigger source for capture operation on channel x. I/O pin is selected as trigger source for capture operation on channel x. Bits 16, 17 CAPTENxCapture Channel x Enable [x=1..0]

Bit x of CAPTEN[1:0] selects whether channel x is a capture or a compare channel. These bits are not synchronized. Value 0 1 Description CAPTEN disables capture on channel x. CAPTEN enables capture on channel x. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1005 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Bit 15 DMAOSDMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TC cycle following a TC_CTRLBSET_CMD_DMAOS command. Writing a '0' to this bit will generate DMA triggers on each TC cycle. This bit is not synchronized. Bit 11 ALOCKAuto Lock When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event. This bit is not synchronized. Value 0 1 Description The LUPD bit is not affected on overflow/underflow, and re-trigger event. The LUPD bit is set on each overflow/underflow or re-trigger event. Bits 10:8 PRESCALER[2:0]Prescaler These bits select the counter prescaler factor. These bits are not synchronized. Name Value DIV1 0x0 DIV2 0x1 DIV4 0x2 DIV8 0x3 DIV16 0x4 DIV64 0x5 DIV256 0x6 DIV1024 0x7 Description Prescaler: GCLK_TC Prescaler: GCLK_TC/2 Prescaler: GCLK_TC/4 Prescaler: GCLK_TC/8 Prescaler: GCLK_TC/16 Prescaler: GCLK_TC/64 Prescaler: GCLK_TC/256 Prescaler: GCLK_TC/1024 Bit 7 ONDEMANDClock On Demand This bit selects the clock requirements when the TC is stopped. In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'. This bit is not synchronized. Value 0 Description The On Demand is disabled. If On Demand is disabled, the TC will continue to request the clock when its operation is stopped (STATUS.STOP=1). The On Demand is enabled. When On Demand is enabled, the stopped TC will not request the clock. The clock is requested when a software re-trigger command is applied or when an event with start/re-trigger action is detected. 1 Bit 6 RUNSTDBYRun in Standby This bit is used to keep the TC running in standby mode. This bit is not synchronized. Value 0 1 Description The TC is halted in standby. The TC continues to run in standby. Bits 5:4 PRESCSYNC[1:0]Prescaler and Counter Synchronization These bits select whether the counter must wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler. These bits are not synchronized. Name Value GCLK 0x0 PRESC 0x1 RESYNC 0x2

0x3 Description Reload or reset the counter on next generic clock Reload or reset the counter on next prescaler clock Reload or reset the counter on next generic clock. Reset the prescaler counter Reserved Bits 3:2 MODE[1:0]Timer Counter Mode These bits select the counter mode. These bits are not synchronized. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1006 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Value 0x0 0x1 0x2 0x3 Name COUNT16 COUNT8 COUNT32

Bit 1 ENABLEEnable Description Counter in 16-bit mode Counter in 8-bit mode Counter in 32-bit mode Reserved Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. This bit is not enable-protected. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1007 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.2 Control B Clear Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized CTRLBCLR 0x04 0x00 This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. This bit has no effect when input capture operation is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the LUPD bit. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1008 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.3 Control B Set Name:

Offset:

Reset:

Property: PAC Write-Protection, Read-synchronized, Write-Synchronized CTRLBSET 0x05 0x00 This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR). Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]Command These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero. Writing 0x0 to these bits has no effect. Writing a value different from 0x0 to these bits will issue a command for execution. Value 0x0 0x1 0x2 0x3 0x4 Description No action Force a start, restart or retrigger Force a stop Force update of double buffered registers Force a read synchronization of COUNT Name NONE RETRIGGER STOP UPDATE READSYNC Bit 2 ONESHOTOne-Shot on Counter This bit controls one-shot operation of the TC. Writing a '0' to this bit has no effect. Writing a '1' to this bit will enable one-shot operation. Value 0 1 Description The TC will wrap around and continue counting on an overflow/underflow condition. The TC will wrap around and stop on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TC buffered registers. When CTRLB.LUPD is set, no update of the registers with value of its buffered register is performed on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the LUPD bit. This bit has no effect when input capture operation is enabled. Value 0 Description The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition. The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1009 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.4 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x06 0x0000 Bit 15 14 Access Reset Bit 7 6 Access Reset 13 MCEO1 R/W 0 5 TCEI R/W 0 12 MCEO0 R/W 0 4 TCINV R/W 0 11 10 9 3 2 R/W 0 1 EVACT[2:0]

R/W 0 8 OVFEO R/W 0 0 R/W 0 Bits 12, 13 MCEOxMatch or Capture Channel x Event Output Enable [x = 1..0]

These bits enable the generation of an event for every match or capture on channel x. Value 0 1 Description Match/Capture event on channel x is disabled and will not be generated. Match/Capture event on channel x is enabled and will be generated for every compare/capture. Bit 8 OVFEOOverflow/Underflow Event Output Enable This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter overflows/underflows. Value 0 1 Description Overflow/Underflow event is disabled and will not be generated. Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. Bit 5 TCEITC Event Enable This bit is used to enable asynchronous input events to the TC. Value 0 1 Description Incoming events are disabled. Incoming events are enabled. Bit 4 TCINVTC Inverted Event Input Polarity This bit inverts the asynchronous input event source. Value 0 1 Description Input event source is not inverted. Input event source is inverted. Bits 2:0 EVACT[2:0]Event Action These bits define the event action the TC will perform on an event. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Event action disabled Start, restart or retrigger TC on event Count on event Start TC on event Time stamp capture Period captured in CC0, pulse width in CC1 Period captured in CC1, pulse width in CC0 Pulse width capture Name OFF RETRIGGER COUNT START STAMP PPW PWP PW 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1010 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.5 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x08 0x00 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Disable Writing a 0 to these bits has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1011 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.6 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x09 0x00 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x Interrupt Enable [x = 1..0]

Writing a 0 to these bits has no effect. Writing a 1 to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt. Description Value The Match or Capture Channel x interrupt is disabled. 0 The Match or Capture Channel x interrupt is enabled. 1 Bit 1 ERRError Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 0 OVFOverflow Interrupt Enable Writing a 0 to these bits has no effect. Writing a 1 to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request. Value 0 1 Description The Overflow interrupt is disabled. The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1012 Microchip Confidential Confidential 35.12.7 Interrupt Flag Status and Clear PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) Name:

Offset:

Reset:

Property:

INTFLAG 0x0A 0x00

Bit 7 6 Access Reset 5 MC1 R/W 0 4 MC0 R/W 0 3 2 1 ERR R/W 0 0 OVF R/W 0 Bits 4, 5 MCxMatch or Capture Channel x [x = 1..0]

This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is 1. Writing a 0 to these bits has no effect. Writing a 1 to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In capture operation, this flag is automatically cleared when CCx register is read. Bit 1 ERRError Interrupt Flag This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is set, in which case there is no place to store the new capture. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Error interrupt flag. Bit 0 OVFOverflow Interrupt Flag This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt request if INTENCLR.OVF or INTENSET.OVF is 1. Writing a 0 to these bits has no effect. Writing a 1 to this bit clears the Overflow interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1013 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.8 Status STATUS Name:

0x0B Offset:

Reset:

0x01 Property: Read-Synchronized Bit 7 6 Access Reset 5 CCBUFV1 R/W 0 4 CCBUFV0 R/W 0 3 PERBUFV R/W 0 2 1 SLAVE R 0 0 STOP R 1 Bits 4, 5 CCBUFVxChannel x Compare or Capture Buffer Valid [x = 1..0]

For a compare channel x, the bit x is set when a new value is written to the corresponding CCBUFx register. The bit x is cleared by writing a 1 to it when CTRLB.LUPD is set, or it is cleared automatically by hardware on UPDATE condition. For a capture channel x, the bit x is set when a valid capture value is stored in the CCBUFx register. The bit x is cleared automatically when the CCx register is read. Bit 3 PERBUFVPeriod Buffer Valid This bit is set when a new value is written to the PERBUF register. The bit is cleared by writing 1 to the corresponding location when CTRLB.LUPD is set, or automatically cleared by hardware on UPDATE condition. This bit is available only in 8-bit mode and will always read zero in 16- and 32-bit modes. Bit 1 SLAVEClient Status Flag This bit is only available in 32-bit mode on the Client TC (i.e., TC1, TC3, TC5 and/or TC7). The bit is set when the associated Host TC (TC0, TC2, TC4 and/or TC6, respectively) is set to run in 32-bit mode. Bit 0 STOPStop Status Flag This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is 1. Value 0 1 Description Counter is running. Counter is stopped. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1014 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.9 Waveform Generation Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected WAVE 0x0C 0x00 Bit 7 6 5 4 3 2 Access Reset Bits 1:0 WAVEGEN[1:0]Waveform Generation Mode 1 0 WAVEGEN[1:0]

R/W 0 R/W 0 These bits select the waveform generation operation. They affect the top value, as shown in Waveform Output Operations. They also control whether frequency or PWM waveform generation must be used. The waveform generation operations are explained in Waveform Output Operations. See Waveform Output Operations from Related Links. These bits are not synchronized. Value Name Operation Top Value Output Waveform on Match Output Waveform on Wraparound 0x0 0x1 0x2 0x3 1. NFRQ MFRQ NPWM MPWM Normal frequency Match frequency Normal PWM Match PWM PER1 / Max CC0 PER1 / Max CC0 Toggle Toggle Set Set No action No action Clear Clear This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode, it is the respective MAX value. Related Links 35.6.2.6.1. Waveform Output Operations 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1015 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.10 Driver Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DRVCTRL 0x0D 0x00 Bit 7 6 5 4 3 2 Access Reset 1 INVEN1 R/W 0 0 INVEN0 R/W 0 Bits 0, 1 INVENxOutput Waveform x Invert Enable [x=1..0]

Bit x of INVEN[1:0] selects inversion of the output or capture trigger input of channel x. Value 0 1 Description Disable inversion of the WO[x] output and IO input pin. Enable inversion of the WO[x] output and IO input pin. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1016 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.11 Debug Control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x0F 0x00 Bit 7 6 5 4 3 2 1 0 Access Reset Bit 0 DBGRUNRun in Debug Mode DBGRUN R/W 0 This bit is not affected by a software Reset, and must not be changed by software while the TC is enabled. Value 0 1 Description The TC is halted when the device is halted in debug mode. The TC continues normal operation when the device is halted in debug mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1017 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.12 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x10 0x00

Bit Access Reset 7 CC1 R 0 6 CC0 R 0 5 PER R 0 4 COUNT R 0 3 STATUS R 0 2 CTRLB R 0 1 ENABLE R 0 0 SWRST R 0 Bits 6, 7 CCxCompare/Capture Channel x Synchronization Busy [x=0..1]

For details on CC channels number, refer to each TC feature list. This bit is set when the synchronization of CCx between clock domains is started. This bit is also set when the CCBUFx is written, and cleared on update condition. The bit is automatically cleared when the STATUS.CCBUFx bit is cleared. Bit 5 PERPER Synchronization Busy This bit is cleared when the synchronization of PER between the clock domains is complete. This bit is set when the synchronization of PER between clock domains is started. This bit is also set when the PER is written, and cleared on update condition. The bit is automatically cleared when the STATUS.PERBUF bit is cleared. Bit 4 COUNTCOUNT Synchronization Busy This bit is cleared when the synchronization of COUNT between the clock domains is complete. This bit is set when the synchronization of COUNT between clock domains is started. Bit 3 STATUSSTATUS Synchronization Busy This bit is cleared when the synchronization of STATUS between the clock domains is complete. This bit is set when a '1' is written to the Capture Channel Buffer Valid status flags (STATUS.CCBUFVx) and the synchronization of STATUS between clock domains is started. Bit 2 CTRLBCTRLB Synchronization Busy This bit is cleared when the synchronization of CTRLB between the clock domains is complete. This bit is set when the synchronization of CTRLB between clock domains is started. Bit 1 ENABLEENABLE Synchronization Busy This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete. This bit is set when the synchronization of ENABLE bit between clock domains is started. Bit 0 SWRSTSWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. Note:During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST cleared by hardware. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1018 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.13 Counter Value, 32-bit Mode Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized COUNT 0x14 0x00 Note:Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC). Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 COUNT[31:24]

R/W 0 20 R/W 0 19 COUNT[23:16]

R/W 0 12 R/W 0 11 COUNT[15:8]

R/W 0 4 R/W 0 3 COUNT[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 COUNT[31:0] Counter Value These bits contain the current counter value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1019 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.14 Channel x Compare/Capture Value, 32-bit Mode Name:

Offset:

Reset:

Property: Write-Synchronized CCx 0x1C + x*0x04 [x=0..1]

0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 CC[31:24]

CC[23:16]

CC[15:8]

CC[7:0]

28 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 27 R/W 0 19 R/W 0 11 R/W 0 3 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 CC[31:0]Channel x Compare/Capture Value These bits contain the compare/capture value in 32-bit TC mode. In Match frequency (MFRQ) or Match PWM

(MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1020 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter (TC) 35.12.15 Channel x Compare Buffer Value, 32-bit Mode Name:

Offset:

Reset:

Property: Write-Synchronized CCBUFx 0x30 + x*0x04 [x=0..1]

0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 30 R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 29 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 28 27 CCBUF[31:24]

R/W 0 20 R/W 0 19 CCBUF[23:16]

R/W 0 12 R/W 0 11 CCBUF[15:8]

R/W 0 4 R/W 0 3 CCBUF[7:0]

R/W 0 R/W 0 26 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 25 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 31:0 CCBUF[31:0]Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value. When the buffer valid flag is '1' and double buffering is enabled (CTRLBCLR.LUPD=1), the data from buffer registers will be copied into the corresponding CCx register under UPDATE condition (CTRLBSET.CMD=0x3), including the software update command. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1021 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36. Timer/Counter for Control Applications (TCC) 36.1 Overview The device provides three instances of the Timer/Counter for Control Applications (TCC). Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events or clock pulses. The counter together with the compare/capture channels can be configured to time stamp input events, allowing capture of frequency and pulse-width. It can also perform waveform generation, such as frequency generation and pulse-width modulation. Waveform extensions are featured for motor control, ballast, LED, H-bridge, power converters and other types of power control applications. They allow for low-side and high-side output with optional dead-time insertion. Waveform extensions can also generate a synchronized bit pattern across the waveform output pins. The fault options enable fault protection for safe and deterministic handling, disabling and/or shut-down of external drivers. Note:The TCC configurations, such as channel numbers and features, may be reduced for some of the TCC instances. Table 36-1. TCC Specific Configuration TCC No. Counter Size (SIZE) Link Role (Host_Client_MODE) (0 = NA, 1 = Host, 2 =

Client) Channels (CC_NUM) Pins WO_NUM (OW_NUM) 0 1 2 24 24 16 1 2 0 6 6 2 6 6 2 Note:Traditional Timer/Counter for Control Applications (TCC) documentation uses the terminology Master and Slave. The equivalent Microchip terminology used in this document is Host and Client, respectively. 36.2 Features Up to six Compare/Capture Channels (CC) with:

Double buffered period setting Double buffered compare or capture channel Circular buffer on period and compare channel registers Waveform Generation:

Frequency generation Single-slope pulse-width modulation (PWM) Dual-slope PWM with half-cycle reload capability Input Capture:

Event capture Frequency capture Pulse-width capture Waveform Extensions:

Configurable distribution of compare channels outputs across port pins Low-side and high-side output with programmable dead-time insertion Waveform swap option with double buffer support Pattern generation with double buffer support Dithering support Fault Protection for Safe Disabling of Drivers:

Two recoverable fault sources 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1022 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Two non-recoverable fault sources Debugger can be a source of non-recoverable fault Input Events:

Two input events (EVx) for counter One input event (MCx) for each channel Output Events:

Three output events (Count, re-trigger and overflow) are available for counter One compare match/input capture event output for each channel Interrupts:

Overflow and re-trigger interrupt Compare match/input capture interrupt Interrupt on fault detection 36.3 Block Diagram Figure 36-1. Timer/Counter for Control Applications - Block Diagram Base Counter BV PERBUFx PER Prescaler Counter COUNT

"count"

"clear"

"load"

"direction"

Control Logic OVF (INT/Event/DMA Req.) ERR (INT Req.)

"TCCx_EV0" (TCE0)

"TCCx_EV1" (TCE1)

TOP BOTTOM E T A D P U nt"

e v e

= 0

"TCCx_MCx"

Event System Compare/Capture

(Unit x = {0,1,...,5}) BV CCBUFx

"capture"

Control Logic CCx

Waveform Generation

"match"

t u p t u O x i r t a M i e m T

d a e D n o i t r e s n I l e b a r e v o c e R s t l u a F P A W S n r e t t a P n o i t a r e n e G e l b a r e v o c e r

n o N s t l u a F WO[5]

WO[4]

WO[3]

WO[2]

WO[1]

WO[0]

MCx (INT/Event/DMA Req.) 36.4 Signal Description Table 36-2. Signal Description Pin Name TCCx/WO[0]

TCCx/WO[1]

Type Description Digital output Compare channel 0 waveform output Digital output Compare channel 1 waveform output

... .. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1023 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC)

...........continued Pin Name Type Description TCCx/WO[WO_NUM-1]

Digital output Compare channel n waveform output See I/O Ports and Peripheral Pin Select (PPS) from Related Links for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 36.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 36.5.1 I/O Lines In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Peripheral Pin Select

(PPS). 36.5.2 Power Management This peripheral can continue to operate in any Sleep mode (Idle, Standby sleep) where its source clock is running. The interrupts can wake-up the device from Sleep modes. Events connected to the event system can trigger other operations in the system without exiting Sleep modes. 36.5.3 Clocks A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the generic clock controller before using the TCC. Note that TCC1 and TCC2 share a single peripheral clock generator. The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (PB1_CLK). Due to this asynchronicity, writing certain registers will require synchronization between the clock domains. 36.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral, the DMAC must be configured first (see Direct Memory Access Controller (DMAC) from Related Links). Related Links 22. Direct Memory Access Controller (DMAC) 36.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Interrupt Controller (NVIC) must be configured first. See Nested Vector Interrupt Controller (NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 36.5.6 Events The events of this peripheral are connected to the Event System. Related Links 26. Event System (EVSYS) 36.5.7 Debug Operation When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details. Refer to 36.8.8. DBGCTRL register for details. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1024 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.5.8 Register Access Protection Registers with write access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following:

Interrupt Flag register (INTFLAG) Status register (STATUS) Period and Period Buffer registers (PER, PERBUF) Compare/Capture and Compare/Capture Buffer registers (CCx, CCBUFx) Control Waveform register (WAVE) Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTBUF) Note:Optional write protection is indicated by the "PAC Write Protection" property in the register description. Write protection does not apply for accesses through an external debugger. 36.5.9 Analog Connections Not applicable. 36.6 Functional Description 36.6.1 Principle of Operation The following definitions are used throughout the documentation:

Table 36-3. Timer/Counter for Control Applications Definitions Name TOP ZERO MAX UPDATE Timer Counter CC Description The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the Waveform Generator mode in Waveform Output Operations. See Waveform Output Generation Operations from Related Links. The counter reaches ZERO when it contains all zeros. The counter reaches maximum when it contains all ones. The timer/counter signals an update when it reaches ZERO or TOP, depending on the direction settings. The timer/counter clock control is handled by an internal source. The clock control is handled externally (e.g., counting external events). For compare operations, the CC are referred to as "compare channels."

For capture operations, the CC are referred to as "capture channels."

Each TCC instance has up to six compare/capture channels (CCx). The Counter register (COUNT), Period registers with Buffer (PER and PERBUF), and Compare and Capture registers with buffers (CCx and CCBUFx) are 16- or 24-bit registers, depending on each TCC instance. Each Buffer register has a Buffer Valid (BUFV) flag that indicates when the buffer contains a new value. Under normal operation, the counter value is continuously compared to the TOP or ZERO value to determine whether the counter has reached TOP or ZERO. In either case, the TCC can generate interrupt requests or generate events for the Event System. In Waveform Generator mode, these comparisons are used to set the waveform period or pulse width. A prescaled generic clock (GCLK_TCCx) and events from the event system can be used to control the counter. The event system is also used as a source to the input capture. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1025 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) The Recoverable Fault Unit enables event-controlled waveforms by acting directly on the generated waveforms of the TCC compare channels output. These events can restart, halt the timer/counter period, shorten the output pulse active time, or disable waveform output as long as the fault condition is present. This can typically be used for current sensing regulation, and zero-crossing and demagnetization re-triggering. The MCE0 and MCE1 asynchronous event sources are shared with the recoverable fault unit. Only asynchronous events are used internally when fault unit extension is enabled. See Event System (EVSYS) from Related Links for further details on how to configure asynchronous events routing. Recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches, by using digital filtering, input blanking and qualification options. See Recoverable Faults from Related Links. In order to support applications with different types of motor control, ballast, LED, H-bridge, power converter and other types of power switching applications, the following independent units are implemented in some of the TCC instances as optional and successive units:

Recoverable faults and non-recoverable faults Output matrix Dead-time insertion Swap Pattern generation See Timer/Counter for Control Applications - Block Diagram in the Block Diagram from Related Links. The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different configurations, each optimized for different application types. The Dead-Time Insertion (DTI) unit splits the four lower OTMX outputs into two non-overlapping signals: the non-inverted Low Side (LS) and inverted High Side (HS) of the waveform output with optional dead-time insertion between LS and HS switching. The SWAP unit can swap the LS and HS pin outputs and can be used for fast decay motor control. The pattern generation unit can be used to generate synchronized waveforms with constant logic level on TCC UPDATE conditions. This is useful for easy stepper motor and full bridge control. The non-recoverable fault module enables event-controlled fault protection by acting directly on the generated waveforms of the timer/counter compare channel outputs. When a non-recoverable fault condition is detected, the output waveforms are forced to a preconfigured value that is safe for the application. This is typically used for instant and predictable shut-down and disabling high current or voltage drives. The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The events can be optionally filtered. If the filter options are not used, the non-recoverable faults provide an immediate asynchronous action on waveform output, even for cases where the clock is not present. See Event System (EVSYS) from Related Links for further details on how to configure asynchronous events routing. Related Links 26. Event System (EVSYS) 36.3. Block Diagram 36.6.3.5. Recoverable Faults 36.6.2.5.1. Waveform Output Generation Operations 36.6.2 Basic Operation 36.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the TCC is disabled

(CTRLA.ENABLE=0):

Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset

(SWRST) bits Recoverable Fault n Control registers (FCTRLA and FCTRLB) Waveform Extension Control register (WEXCTRL) Drive Control register (DRVCTRL) Event Control register (EVCTRL) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1026 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to 1, but not at the same time as CTRLA.ENABLE is written to 0. Enable-protection is denoted by the Enable-Protected property in the register description. Before the TCC is enabled, it must be configured as outlined by the following steps:

Enable the TCC bus clock if not already enabled by default (PB1_CLK). If Capture mode is required, enable the channel in Capture mode by writing a 1 to the Capture Enable bit in the Control A register (CTRLA.CPTEN). 1. 2. Optionally, the following configurations can be set before enabling TCC:

1. 2. 3. 4. 5. 6. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER). Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC). If down-counting operation is desired, write the Counter Direction bit in the Control B Set register

(CTRLBSET.DIR) to 1. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN). Select the Waveform Output Polarity in the WAVE register (WAVE.POL). The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit group in the Driver register (DRVCTRL.INVEN). 36.6.2.2 Enabling, Disabling, and Resetting The TCC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled by writing a zero to CTRLA.ENABLE. The TCC is reset by writing '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. See CTRLA register from Related Links. The TCC should be disabled before the TCC is reset to avoid undefined behavior. 36.6.2.3 Prescaler Selection The GCLK_TCCx clock is fed into the internal prescaler. The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the prescaler toggles. If the prescaler value is higher than one, the Counter Update condition can be optionally executed on the next GCLK_TCCx clock pulse or the next prescaled clock pulse. For further details, refer to the Prescaler

(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) descriptions. Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). Note:When counting events, the prescaler is bypassed. The joint stream of prescaler ticks and event action ticks is called CLK_TCCx_COUNT. Figure 36-2. Prescaler PRESCALER EVACT 0/1 GCLK_TCCx PRESCALER GCLK_TCCx /

{1,2,4,8,64,256,1024 }

TCCx EV0/1 CLK_TCCx_COUNT COUNT 36.6.2.4 Counter Operation Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC clock input (CLK_TCCx_COUNT). A counter clear or reload mark the end of current counter cycle and the start of a new one. The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If the bit is zero, it's counting up and if one it's counting down. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1027 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it's counting up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. When down-counting, the counter is reloaded with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set. INTFLAG.OVF can be used to trigger an interrupt, or an event. An overflow/underflow occurrence (i.e. a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B register is set (CTRLBSET.ONESHOT). The One-Shot feature is explained in the Additional Features section. Figure 36-3. Counter Operation Direction Change COUNT written

"reload" update

"clear" update COUNT MAX TOP ZERO DIR It is possible to change the counter value (by writing directly in the COUNT register) even when the counter is running. The COUNT value will always be ZERO or TOP, depending on direction set by CTRLBSET.DIR or CTRLBCLR.DIR, when starting the TCC, unless a different value has been written to it, or the TCC has been stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the counter can also be changed during normal operation. See also Figure 36-3. Stop Command A stop command can be issued from software by using TCC Command bits in Control B Set register

(CTRLBSET.CMD=0x2, STOP). When a Stop is detected while the counter is running, the counter will not retain its current value. If the waveform generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and Non- Recoverable State x Output Value bit in the Driver Control register (DRVCTRL.NREx and DRVCTRL.NRVx), and the Stop bit in the Status register is set (STATUS.STOP). Pause Event Action A pause command can be issued when the stop event action is configured in the Input Event Action 1 bits in Event Control register (EVCTRL.EVACT1=0x3, STOP). When a pause is detected, the counter can stop immediatly maintaining its current value and all waveforms keep their current state, until a start event action is detected: Input Event Action 0 bits in Event Control register

(EVCTRL.EVACT0=0x3, START). Re-Trigger Command and Event Action A re-trigger command can be issued from software by using TCC Command bits in Control B Set register

(CTRLBSET.CMD=0x1, RETRIGGER), or from event when the re-trigger event action is configured in the Input Event 0/1 Action bits in Event Control register (EVCTRL.EVACTn=0x1, RETRIGGER). When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). The Re-Trigger bit in the Interrupt Flag Status and Clear register will be set (INTFLAG.TRG). It is also possible to generate an event by writing a '1' to the Re-Trigger Event Output Enable bit in the Event Control register (EVCTRL.TRGEO).If a re-trigger command is detected when the counter is stopped, the value in COUNT will be not be retained and will start either from ZERO or TOP depending on the direction set by CTRLBSET.DIR or CTRLBCLR.DIR. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1028 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Note:

When a re-trigger event action is configured in the Event Action bits in the Event Control register

(EVCTRL.EVACTn=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event. Start Event Action The start action can be selected in the Event Control register (EVCTRL.EVACT0=0x3, START) and can start the counting operation when previously stopped. The event has no effect if the counter is already counting. When the module is enabled, the counter operation starts when the event is received or when a re-trigger software command is applied. Note:

When a start event action is configured in the Event Action bits in the Event Control register (EVCTRL.EVACT0=0x3, START), enabling the counter will not start the counter. The counter will start on the next incoming event, but it will not restart on subsequent events. Count Event Action The TCC can count events. When an event is received, the counter increases or decreases the value, depending on direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action is selected by the Event Action 0 bit group in the Event Control register

(EVCTRL.EVACT0=0x5, COUNT). Direction Event Action The direction event action can be selected in the Event Control register (EVCTRL.EVACT1=0x2, DIR). When this event is used, the asynchronous event path specified in the event system must be configured or selected. The direction event action can be used to control the direction of the counter operation, depending on external events level. When received, the event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the direction bit value is updated accordingly. Increment Event Action The increment event action can be selected in the Event Control register (EVCTRL.EVACT0=0x4, INC) and can change the Counter state when an event is received. When the TCE0 event (TCCx_EV0) is received, the counter increments, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is. Decrement Event Action The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1=0x4, DEC) and can change the Counter state when an event is received. When the TCE1 (TCCx_EV1) event is received, the counter decrements, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is. Non-recoverable Fault Event Action Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACTn=0x7, FAULT). When received, the counter will be stopped and the output of the compare channels is overridden according to the Driver Control register settings (DRVCTRL.NREx and DRVCTRL.NRVx). TCE0 and TCE1 must be configured as asynchronous events. Event Action Off If the event action is disabled (EVCTRL.EVACTn=0x0, OFF), enabling the counter will also start the counter. 36.6.2.5 Compare Operations By default, the Compare/Capture channel is configured for compare operations. To perform capture operations, it must be re-configured. When using the TCC with the Compare/Capture Value registers (CCx) for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation. The Channel x Compare/Capture Buffer Value (CCBUFx) registers provide double buffer capability. The double buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force update command (CTRLBSET.CMD=0x3, UPDATE). For further details, refer to 36.6.2.6. Double Buffering. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1029 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.6.2.5.1 Waveform Output Generation Operations The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled:

1. Choose a Waveform Generation mode in the Waveform Generation Operation bit in Waveform register

(WAVE.WAVEGEN). 2. Optionally, invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in the Driver Control register (DRVCTRL.INVENx). 3. Configure the pins with the I/O Pin Controller. See I/O Ports and Peripheral Pin Select (PPS) from Related Links. Note:Event must not be used when the compare channel is set in waveform output operating mode. The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on the same condition if Match/Capture occurs, i.e., INTENSET.MCx and/or EVCTRL.MCEOx is 1. Both interrupt and event can be generated simultaneously. There are seven waveform configurations for the Waveform Generation Operation bit group in the Waveform register

(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The configurations are:

Normal Frequency (NFRQ) Match Frequency (MFRQ) Normal Pulse-Width Modulation (NPWM) Dual-slope, interrupt/event at TOP (DSTOP) Dual-slope, interrupt/event at ZERO (DSBOTTOM) Dual-slope, interrupt/event at Top and ZERO (DSBOTH) Dual-slope, critical interrupt/event at ZERO (DSCRITICAL) When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value. For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other Waveforms Generation modes, the update time occurs on counter wraparound, on overflow, underflow or re-trigger. The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes. Table 36-4. Counter Update and Overflow Event/interrupt Conditions Name Operation TOP Update Output Waveform OVFIF/Event NFRQ MFRQ NPWM DSCRITICAL DSBOTTOM DSBOTH DSTOP Normal Frequency Match Frequency Single-slope PWM Dual-slope PWM Dual-slope PWM Dual-slope PWM Dual-slope PWM PER TOP/ ZERO Toggle Stable TOP On Match On Update Up Down ZERO CC0 TOP/ ZERO Toggle Stable TOP ZERO PER TOP/ ZERO See section 'Output Polarity'

TOP ZERO below PER ZERO PER ZERO PER TOP(1) &

ZERO PER ZERO ZERO ZERO TOP ZERO TOP 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1030 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 1. The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel. Related Links 5. I/O Ports and Peripheral Pin Select (PPS) 36.6.2.5.2 Normal Frequency (NFRQ) For Normal Frequency generation, the period time (T) is controlled by the period register (PER). The waveform generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (EVCTRL.MCEOx) will be set. Figure 36-4. Normal Frequency Operation Period (T) Direction Change COUNT Written COUNT MAX TOP CCx ZERO WO[x]

"reload" update

"clear" update

"match"

36.6.2.5.3 Match Frequency (MFRQ) For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on each update condition. Figure 36-5. Match Frequency Operation Direction Change COUNT Written COUNT MAX CC0 ZERO WO[0]

"reload" update

"clear" update 36.6.2.5.4 Normal Pulse-Width Modulation (NPWM) NPWM uses single-slope PWM generation. 36.6.2.5.5 Single-Slope PWM Operation For single-slope PWM generation, the period time (T) is controlled by Top value, and CCx controls the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match between COUNT and CCx register values. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1031 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-6. Single-Slope PWM Operation CCx=ZERO CCx=TOP MAX TOP COUNT CCx ZERO WO[x]

"clear" update

"match"

The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:

RPWM_SS =

The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCCx), and can be calculated by the following equation:

log(TOP+1) log(2) fPWM_SS =

Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). fGCLK_TCCx N(TOP+1) 36.6.2.5.6 Dual-Slope PWM Generation For dual-slope PWM generation, the period setting (TOP) is controlled by PER, while CCx control the duty cycle of the generated waveform output. The figure below shows how the counter repeatedly counts from ZERO to PER and then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared on compare match when down-counting. An interrupt and/or event is generated on TOP (when counting upwards) and/or ZERO (when counting up or down). In DSBOTH operation, the circular buffer must be enabled to enable the update condition on TOP. Figure 36-7. Dual-Slope Pulse Width Modulation CCx=ZERO CCx=TOP

"update"

"match"

CCx COUNT MAX TOP ZERO WO[x]

Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation. The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001). The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):

. RPWM_DS =

The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCCx, and can be calculated by the following equation:

log(PER+1) log(2) fPWM_DS =

fGCLK_TCCx 2N PER 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1032 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC clock frequency (fGCLK_TCCx) when TOP is set to 0x00000001 and no prescaling is used. The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency

(fGCLK_TCCx), and can be calculated by the following equation:

2N TOP CCx PPWM_DS =

N represents the prescaler divider used. fGCLK_TCCx Note:In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB bit defines the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0, falling if CCx[MSB] = 1.) Related Links 36.6.3.2. Circular Buffer 36.6.2.5.7 Dual-Slope Critical PWM Generation Critical mode generation allows generation of non-aligned centered pulses. In this mode, the period time is controlled by PER while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2) control the generated waveform output edge during down-counting. Figure 36-8. Dual-Slope Critical Pulse Width Modulation (N=CC_NUM) CCx CC(x+N/2) CCx CC(x+N/2) CCx CC(x+N/2)

"reload" update

"match"

COUNT MAX TOP ZERO WO[x]

36.6.2.5.8 Output Polarity The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM operation, it is possible to invert the pulse edge alignment individually on start or end of a PWM cycle for each compare channels. The table below shows the waveform output set/clear conditions, depending on the settings of timer/counter, direction, and polarity. Table 36-5. Waveform Generation Set/Clear Conditions Waveform Generation Operation Single-Slope PWM Dual-Slope PWM DIR POLx Waveform Generation Output Update Set Clear 0 1 x 0 1 0 1 0 1 Timer/counter matches TOP Timer/counter matches CCx Timer/counter matches CC Timer/counter matches TOP Timer/counter matches CC Timer/counter matches ZERO Timer/counter matches ZERO Timer/counter matches CC Timer/counter matches CC when counting up Timer/counter matches CC when counting down Timer/counter matches CC when counting down Timer/counter matches CC when counting up 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1033 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output. 36.6.2.6 Double Buffering The Pattern (PATT), Period (PER) and Compare Channels (CCx) registers are all double buffered. Each buffer register has a buffer valid (PATTBUFV, PERBUFV and CCBUFVx) bit in the STATUS register, which indicates that the Buffer register contains a valid value that can be copied into the corresponding register. When the Buffer Valid Flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register is set to

'0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers will be copied into the corresponding register under hardware UPDATE conditions, then the Buffer Valid flags bit in the STATUS register are automatically cleared by hardware. Note:Software update command (CTRLBSET.CMD=0x3) act independently of LUPD value. A compare register is double buffered as in the following figure. Figure 36-9. Compare Channel Double Buffering

"APB write enable"

"data write"

UPDATE BV EN CCBUFx EN CCx COUNT

"match"

Both the registers (PATT/PER/CCx) and corresponding Buffer registers (PATTBUFPERBUF/CCBUFx) are available in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a '1' to CTRLSET.LUPD. Note:In NFRQ, MFRQ or PWM Down-Counting Counter mode (CTRLBSET.DIR=1), when double buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continuously copied into the PER independently of update conditions. Changing the Period The counter period can be changed by writing a new Top value to the Period register (PER or CC0, depending on the Waveform Generation mode), any period update on registers (PER or CCx) is effective after the synchronization delay, whatever double buffering enabling is. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1034 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-10. Unbuffered Single-Slope Up-Counting Operation Counter Wraparound COUNT MAX ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT Figure 36-11. Unbuffered Single-Slope Down-Counting Operation COUNT MAX ZERO

"clear" update

"write"

"reload" update

"write"

New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT A counter wraparound can occur in any operation mode when up-counting without buffering, see Figure 36-10. COUNT and TOP are continuously compared, so when a new value that is lower than the current COUNT is written to TOP, COUNT will wrap before a compare match. Figure 36-12. Unbuffered Dual-Slope Operation Counter Wraparound COUNT MAX ZERO

"reload" update

"write"

New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown in Figure 36-13. This prevents wraparound and the generation of odd waveforms. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1035 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-13. Changing the Period Using Buffering COUNT MAX ZERO

"reload" update

"write"

New value written to PERBUF that is higher than current COUNT New value written to PERBUF that is lower than current COUNT PER is updated with PERBUF value 36.6.2.7 Capture Operations To enable and use capture operations, the Match or Capture Channel x Event Input Enable bit in the Event Control register (EVCTRL.MCEIx) must be written to 1. The capture channels to be used must also be enabled in the Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx) before capturing can be performed. Event Capture Action The compare/capture channels can be used as input capture channels to capture events from the Event System, and give them a timestamp. The following figure shows four capture events for one capture channel. Event system channels must be configured to operate in asynchronous mode when used for capture operations. Figure 36-14. Input Capture Timing events MAX ZERO COUNT Capture 0 Capture 1 Capture 2 Capture 3 For input capture, the Buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any content in CCBUFx is transferred to CCx. The Buffer Valid flag is passed to set the CCx Interrupt flag (IF) and generate the optional interrupt, event, or DMA request. The CCBUFx register value cannot be read, all captured data must be read from the CCx register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1036 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-15. Capture Double Buffering

"capture"

COUNT BUFV EN CCBUFx IF EN CCx

"INT/DMA request"

data read The TCC can detect capture overflow of the input capture channels. When a new capture event is detected while the Capture Buffer Valid flag (STATUS.CCBUFV) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. Period and Pulse-Width (PPW) Capture Action The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to measure the pulse-width and period and to characterize the frequency f and dutyCycle of an input signal, as shown below:

tp T Period (T)

"capture"

f =

dutyCycle =

Figure 36-16. PWP Capture

, 1 T external signal /event capture times COUNT MAX ZERO CC0 CC1 CC0 CC1 Selecting PWP or PPW in the Timer/Counter Event Input 1 Action bit group in the Event Control register

(EVCTRL.EVACT1) enables the TCC to perform one capture action on the rising edge and the other one on the falling edge. When using PPW event action, period T will be captured into CC0 and the pulse-width tp into CC1. The PWP (Pulse-width and Period) event action offers the same functionality, but T will be captured into CC1 and tp into CC0. The Timer/Counter Event x Invert Enable bit in Event Control register (EVCTRL.TCEINVx) is used for event source x to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCEINVx = 1, the wraparound will happen on the falling edge. The corresponding capture is done only if the channel is enabled in Capture mode (CTRLA.CPTENx = 1). If not, the capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these channels is required, the other channel can be used for other purposes. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1037 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) The TCC can detect capture overflow of the input capture channels. When a new capture event is detected while the INTFLAG.MCx is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. Note:When up-counting (CTRLBSET.DIR = 0), counter values lower than 1 cannot be captured in Capture Minimum mode (FCTRLn.CAPTURE = CAPTMIN). To capture the full range including value 0, the TCC must be configured in Down-counting mode (CTRLBSET.DIR = 0). Note:In dual-slope PWM operation, and when TOP is lower than MAX/2, the CCx MSB captures the CTRLB.DIR state to identify the ramp on which the capture has been done. For rising ramps CCx[MSB] is zero, for falling ramps CCx[MSB] = 1. 36.6.3 Additional Features 36.6.3.1 One-Shot Operation When one-shot is enabled, the counter automatically stops on the next Counter Overflow or Underflow condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is set and the waveform outputs are set to the value defined by DRVCTRL.NREx and DRVCTRL.NRVx. One-shot operation can be enabled by writing a '1' to the One-Shot bit in the Control B Set register

(CTRLBSET.ONESHOT) and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TCC will count until an overflow or underflow occurs and stop counting. The one-shot operation can be restarted by a re-trigger software command, a re-trigger event or a start event. When the counter restarts its operation, STATUS.STOP is automatically cleared. 36.6.3.2 Circular Buffer The Period register (PER) and the Compare Channels register (CC0 toCC5) support circular buffer operation. When circular buffer operation is enabled, the PER or CCx values are copied into the corresponding buffer registers at each update condition. Circular buffering is dedicated to RAMP2, RAMP2A, and DSBOTH operations. Figure 36-17. Circular Buffer on Channel 0

"write enable"

"data write"

BUFV EN CCBUF0 UPDATE CIRCC0EN UPDATE EN CC0 COUNT

"ma tch"

36.6.3.3 Dithering Operation The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns. Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register

(CTRLA.RESOLUTION):

DITH4 enable dithering every 16 PWM frames DITH5 enable dithering every 32 PWM frames DITH6 enable dithering every 64 PWM frames 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1038 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) The DITHERCY bits of COUNT, PER and CCx define the number of extra cycles to add into the frame (DITHERCY bits from the respective COUNT, PER or CCx registers). The remaining bits of COUNT, PER, CCx define the compare value itself. The pseudo code, giving the extra cycles insertion regarding the cycle is:

int extra_cycle(resolution, dithercy, cycle){

int MASK;

int value switch (resolution){

DITH4: MASK = 0x0f;

DITH5: MASK = 0x1f;

DITH6: MASK = 0x3f;

value = cycle * dithercy;

if (((MASK & value) + dithercy) > MASK) return 1;

return 0;

Dithering on Period Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas. DITH4 mode:

PwmPeriod =

Note:If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register correspond to the DITHERCY value, rest of the bits corresponds to PER/CCx or COUNT value.

+ PER DITHERCY 16 1 fGCLK_TCCx DITH5 mode:

PwmPeriod =

DITH6 mode:

DITHERCY 32

+ PER 1 fGCLK_TCCx DITHERCY PwmPeriod =

Dithering on Pulse-Width 64

+ PER 1 fGCLK_TCCx Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula. DITH4 mode:

PwmPulseWidt = DITHERCY DITH5 mode:

16

+ CCx 1 fGCLK_TCCx PwmPulseWidt =

DITH6 mode:

DITHERCY 32

+ CCx 1 fGCLK_TCCx DITHERCY PwmPulseWidt =

Note:The PWM period will remain static in this case. 64 1 fGCLK_TCCx

+ CCx 36.6.3.4 Ramp Operations Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM generation. The Ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register

(WAVE.RAMP). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1039 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) RAMP1 Operation This is the default PWM operation, described in Single-Slope PWM Generation. RAMP2 Operation These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull SMPS topologies, where two consecutive timer/counter cycles are interleaved, see Figure 36-18. In cycle A, odd channel output is disabled, and in cycle B, even channel output is disabled. The ramp index changes after each update, but can be software modified using the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD). Standard RAMP2 (RAMP2) Operation Ramp A and B periods are controlled by the PER register value. The PER value can be different on each ramp by the Circular Period buffer option in the Wave register (WAVE.CIPEREN=1). This mode uses a two-channel TCC to generate two output signals, or one output signal with another CC channel enabled in Capture mode. Figure 36-18. RAMP2 Standard Operation Ramp A B A B TOP(A) TOP(B) Retrigger on FaultA TOP(B) COUNT CC0 CC1 CC1 CC0

"clear" update

"match"

CIPEREN = 1 ZERO WO[0]

WO[1]

FaultA input FaultB input POL0 = 1 Keep on FaultB POL1 = 1 Alternate RAMP2 (RAMP2A) Operation Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs. Channel 1 can be used in capture mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1040 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-19. RAMP2 Alternate Operation Ramp A B A B COUNT TOP(A) TOP(B) Retrigger on FaultA TOP(B) CC0(B) CC0(B) CC0(A) CC0(A)

"clear" update

"match"

CIPEREN = 1 CICCEN0 = 1 ZERO WO[0]

WO[1]

FaultA input FaultB input Keep on FaultB POL0 = 1 Critical RAMP2 (RAMP2C) Operation Critical RAMP2 operation provides a way to cover RAMP2 operation requirements without the update constraint associated with the use of circular buffers. In this mode, CC0 is controlling the period of ramp A and PER is controlling the period of ramp B. When using more than two channels, WO[0] output is controlled by CC2 (HIGH) and CC0 (LOW). On TCC with 2 channels, a pulse on WO[0] will last the entire period of ramp A, if WAVE.POL0=0. Figure 36-20. RAMP2 Critical Operation With More Than 2 Channels Ramp A B A B

"clear" update

"match"

CC0 TOP Retrigger on FaultA TOP COUNT CC2 CC2 CC1 CC1 ZERO WO[0]

WO[1]

FaultA input FaultB input POL2 = 1 Keep on FaultB POL1 = 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1041 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-21. RAMP2 Critical Operation With 2 Channels Ramp A B A B

"clear" update

"match"

CC0 TOP Retrigger on FaultA TOP CC1 CC1 POL0 = 0 Keep on FaultB POL1 = 1 COUNT ZERO WO[0]

WO[1]

FaultA input FaultB input 36.6.3.5 Recoverable Faults Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable fault actions on the compare channels CC0 and CC1 of the TCC. The compare channels' outputs can be clamped to inactive state either as long as the fault condition is present, or from the first valid fault condition detection on until the end of the timer/counter cycle. Fault Inputs The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs, respectively. Event system channels connected to these fault inputs must be configured as asynchronous. The TCC must work in a PWM mode. Fault Filtering There are three filters available for each input Fault A and Fault B. They are configured by the corresponding Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can either be used independently or in any combination. Input Filtering Fault Blanking By default, the event detection is asynchronous. When the event occurs, the fault system will immediately and asynchronously perform the selected fault action on the compare channel output, also in device power modes where the clock is not available. To avoid false fault detection on external events (e.g. due to a glitch on an I/O port) a digital filter can be enabled and configured by the Fault B Filter Value bits in the Fault n Configuration registers (FCTRLn.FILTERVAL). If the event width is less than FILTERVAL (in clock cycles), the event will be discarded. A valid event will be delayed by FILTERVAL clock cycles. This ignores any fault input for a certain time just after a selected waveform output edge. This can be used to prevent false fault triggering due to signal bouncing, as shown in the figure below. Blanking can be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the Recoverable Fault n Configuration register (FCTRLn.BLANK). The desired duration of the blanking must be written to the Fault n Blanking Time bits (FCTRLn.BLANKVAL). The blanking time tbis calculated by Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx. tb =

1 + BLANKVAL fGCLK_TCCx_PRESC The prescaler is enabled by writing '1' to the Fault n Blanking Prescaler bit (FCTRLn.BLANKPRESC). When disabled, fGCLK_TCCx_PRESC=fGCLK_TCCx. When enabled, fGCLK_TCCx_PRESC=fGCLK_TCCx/64. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1042 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) The maximum blanking time (FCTRLn.BLANKVAL =

255) at fGCLK_TCCx= 64 MHz is 4 s (no prescaler) or 256 s (prescaling). For fGCLK_TCCx=1 MHz, the maximum blanking time is either 256 s (no prescaling) or 16.4 ms (prescaling enabled). Figure 36-22. Fault Blanking in RAMP1 Operation with Inverted Polarity COUNT TOP CC0 ZERO CMP0

"clear" update

"match"

"Fault input enabled"

"Fault input disabled"

x

"Fault discarded"

FCTRLA.BLANKVAL = 0 FCTRLA.BLANKVAL > 0 FCTRLA.BLANKVAL > 0 FaultA Blanking

x

x x x FaultA Input WO[0]

Fault Qualification This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled

(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output has an inactive level, as shown in the figures below. Figure 36-23. Fault Qualification in RAMP1 Operation COUNT MAX TOP CC0 CC1 ZERO

"clear" update

"match"

"Fault input enabled"

"Fault input disabled"

x

"Fault discarded"

Fault A Input Qual

x x x

x x x x x x Fault Input A Fault B Input Qual

x x x

x x x x x

x x x x x x x

x x x x

Fault Input B 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1043 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-24. Fault Qualification in RAMP2 Operation with Inverted Polarity COUNT Cycle MAX TOP CC0 CC1 ZERO

"clear" update

"match"

"Fault input enabled"

"Fault input disabled"

x

"Fault discarded"

Fault A Input Qual

x x x

x x x x x x x x x Fault Input A Fault B Input Qual

x x x x x

x x x x x x x x x x

Fault Input B Fault Actions Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually exclusive; hence two or more actions can be enabled at the same time to achieve a result that is a combination of fault actions. Keep Action This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register

(FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as long as the fault condition is present. The clamp will be released on the start of the first cycle after the fault condition is no longer present, see next Figure. Figure 36-25. Waveform Generation with Fault Qualification and Keep Action MAX TOP COUNT CC0 ZERO

"clear" update

"match"

"Fault input enabled"

"Fault input disabled"

x

"Fault discarded"

Fault A Input Qual

x x x

x Fault Input A WO[0]

KEEP KEEP Restart Action This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register

(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a new cycle, see Waveform Generation in RAMP1 mode with Restart Action figure. In Ramp 1 mode, when the new cycle starts, the compare outputs will be clamped to inactive level as long as the fault condition is present. Note:For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change automatically, see Waveform Generation in RAMP2 mode with Restart Action figure. Fault A and Fault B are qualified only during the cycle A and cycle B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1044 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-26. Waveform Generation in RAMP1 mode with Restart Action COUNT MAX TOP CC0 CC1 ZERO Fault Input A WO[0]

WO[1]

"clear" update

"match"

Restart Restart Figure 36-27. Waveform Generation in RAMP2 mode with Restart Action Cycle MAX TOP CC0/CC1 ZERO COUNT Fault Input A WO[0]

WO[1]

CCx=ZERO CCx=TOP

"clear" update

"match"

No fault A action in cycle B Restart Capture Action Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is captured when the fault occurs. These capture operations are available:

CAPT - the equivalent to a standard capture operation, see Capture Operations from Related Links. CAPTMIN - gets the minimum time stamped value: on each new local minimum captured value, an event or interrupt is issued. CAPTMAX - gets the maximum time stamped value: on each new local maximum captured value, an event or interrupt (IT) is issued, see Capture Action CAPTMAX figure. LOCMIN - notifies by event or interrupt when a local minimum captured value is detected. LOCMAX - notifies by event or interrupt when a local maximum captured value is detected. DERIV0 - notifies by event or interrupt when a local extreme captured value is detected, see Capture Action DERIV0 figure. CCx Content:

In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see Capture Action CAPTMAX figure. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time, see Capture Action DERIV0 figure. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1045 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding CCx register value to a value different from zero (for CAPTMIN) or top (for CAPTMAX). If the CCx register initial value is zero (for CAPTMIN) or top (for CAPTMAX), no captures will be performed using the corresponding channel. MCx Behaviour:

In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt flag is set only when the captured value is above or equal (for LOCMIN) or below or equal (for LOCMAX) to the previous captured value. So interrupt flag is set when a new relative local Minimum

(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR function of (LOCMIN, LOCMAX). In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each new capture. In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the counter value is lower (for CAPTMIN) or higher (for CAPMAX) than the last captured value. The MCx interrupt flag is set only when on capture event time, the counter value is higher or equal (for CAPTMIN) or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is set when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. Interrupt Generation In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel capture counter value. In other modes, an interrupt is only generated on an extreme captured value. Figure 36-28. Capture Action CAPTMAX COUNT TOP CC0 ZERO FaultA Input CC0 Event/

Interrupt Figure 36-29. Capture Action DERIV0 COUNT TOP CC0 ZERO WO[0]

FaultA Input CC0 Event/

Interrupt

"clear" update

"update"

"match"

Hardware Halt Action This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is extended as long as the corresponding fault is present. The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where both restart action and hardware halt action are enabled for Fault A. The compare channel 0 output 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1046 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the counting operation as soon as the fault condition is no longer present. As the restart action is enabled in this example, the timer/counter is restarted after the fault condition is no longer present. The figure after that ('Waveform Generation with Fault Qualification, and Halt) shows a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the fault condition is no longer present. Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index will automatically change. Figure 36-30. Waveform Generation with Halt

"clear" update

"match"

"update"

"match"

COUNT MAX TOP CC0 ZERO Fault Input A WO[0]

HALT Restart Restart Figure 36-31. Waveform Generation with Fault Qualification and Halt MAX TOP COUNT CC0 ZERO HALT Resume Fault A Input Qual

x x x

Fault Input A WO[0]

KEEP Software Halt Action This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but in order to restart the timer/counter, the corresponding fault condition must not be present anymore, and the corresponding FAULT n bit in the STATUS register must be cleared by software. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1047 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-32. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions MAX TOP COUNT CC0 ZERO HALT

"update"

"match"

Fault A Input Qual

Restart Restart

x x

Fault Input A Software Clear WO[0]

KEEP NO KEEP FCTRLA.KEEP = 1 FCTRLA.KEEP = 0 Related Links 36.6.2.7. Capture Operations 36.6.3.6 Non-Recoverable Faults The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0 and EV1) actions are enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using Non-Recoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). Therefore, the event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles. When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug operation. In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the respective interrupt (UFS) are generated. 36.6.3.7 Time-Stamp Capture on Events or I/Os This feature is enabled when the Capture Time Stamp (STAMP) Event Action in Event Control register

(EVCTRL.EVACT) is selected. The counter TOP value must be smaller than MAX. When a capture event from the Event System or the I/O pin is detected, the COUNT value is copied into the corresponding Channel x Compare/Capture Value (CCx) register. In case of an overflow, the MAX value is copied into the corresponding CCx register. When a valid captured value is present in the capture channel register, the corresponding Capture Channel x Interrupt Flag (INTFLAG.MCx) is set. The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and INTFLAG.ERR will be set. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1048 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-33. Time Stamp 36.6.3.8 Waveform Extension Waveform Extension Stage Details displays the schematic diagram of actions of the four optional units that follow the recoverable fault stage on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern Generation. The DTI and SWAP units can be seen as a four port pair slices:

Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0]) Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1]) And generally:

Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x]) Figure 36-34. Waveform Extension Stage Details OTMX WEX DTI PORTS SWAP PATTERN OTMX[x+WO_NUM/2]

PGV[x+WO_NUM/2]

LS PGO[x+WO_NUM/2]

INV[x+WO_NUM/2]

WO[x+WO_NUM/2]

OTMX DTIx DTIxEN HS OTMX[x]

SWAPx PGO[x]

PGV[x]

INV[x]

WO[x]

The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in the following table. Table 36-6. Output Matrix Channel Pin Routing Configuration WEXCTRL.OTMX OTMX[5]

OTMX[4]

OTMX[3]

OTMX[2]

OTMX[1]

OTMX[0]

0x0 0x1 0x2 0x3 CC5 CC2 CC0 CC1 CC4 CC1 CC0 CC1 CC3 CC0 CC0 CC1 CC2 CC2 CC0 CC1 CC1 CC1 CC0 CC1 CC0 CC0 CC0 CC0 Configuration 0x0 is the default configuration. The channel location is the default one and channels are distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on. Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the number of output locations to the lower channels than the default configuration. This can be used, for example, to control the four transistors of a full bridge using only two compare channels. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1049 Microchip Confidential MAXZEROCOUNTTOP"capture""overflow"EventsCCx ValueCOUNTCOUNTTOPMAXCOUNTConfidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible drive of a full bridge in all quadrant configurations. Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this configuration can control a stepper motor. Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED strings, with a boost stage. The table below is an example showing four compare channels on four outputs. Table 36-7. Four Compare Channels on Four Outputs WEXCTRL.OTMX OTMX[3]

OTMX[2]

OTMX[1]

OTMX[0]

0x0 0x1 0x2 0x3 CC3 CC1 CC0 CC1 CC2 CC0 CC0 CC1 CC1 CC1 CC0 CC1 CC0 CC0 CC0 CC0 The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side

(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures that the LS and HS will never switch simultaneously. The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels. The following figure shows the block diagram of one DTI generator. The four channels have a common register which controls the dead time, which is independent of high side and low side setting. Figure 36-35. Dead-Time Generator Block Diagram DTLS DTHS Dead Time Generator OTMX output D Q Edge Detect LOAD EN Counter

= 0

"DTLS"

(To PORT)

"DTHS"

(To PORT) As shown in the following figure, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input. When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the output changes from high to low (negative edge) it reloads the DTHS register. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1050 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-36. Dead-Time Generator Timing Diagram

"dti_cnt"

"OTMX output"

"DTLS"

"DTHS"

tP tDTILS T tDTIHS The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC), stepper motors, and full bridge control. For more information, refer to the following figure. Figure 36-37. Pattern Generator Block Diagram COUNT UPDATE BV PGEB[5:0]

BV PGVB[5:0]

SWAP output EN PGE[5:0]

EN PGV[5:0]

As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition set by the timer/counter waveform generation operation. If synchronization is not required by the application, the software can simply access directly the PATT.PGE, PATT.PGV bits registers. 36.6.4 Host/Client Operation Two TCC instances sharing the same GCLK_TCC clock, can be linked to provide more synchronized CC channels. The operation is enabled by setting the Host Synchronization bit in Control A register (CTRLA.MSYNC) in the Client instance. When the bit is set, the Client TCC instance will synchronize the CC channels to the Host counter. WOx[5:0]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1051 Microchip Confidential Confidential 36.6.5 DMA, Interrupts, and Events Table 36-8. Module Requests for TCC Condition Interrupt request Yes Yes Yes Yes Yes Yes Yes Yes Overflow / Underflow Channel Compare Match or Capture Retrigger Count Capture Overflow Error Debug Fault State Recoverable Faults Non-Recoverable Faults TCCx Event 0 input TCCx Event 1 input Notes:

PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Event input DMA DMA request is cleared request Yes(1) Yes(3) Yes(2) On DMA acknowledge For circular buffering: on DMA acknowledge For capture channel:

when CCx register is read Event output Yes Yes Yes Yes Yes(4) Yes(5) 1. DMA request set on Overflow, Underflow or Re-trigger conditions. 2. Can perform capture or generate recoverable fault on an event input. 3. 4. On event input, either action can be executed:

In Capture or Circular modes. re-trigger counter control counter direction stop the counter decrement the counter perform period and pulse width capture generate non-recoverable fault 5. On event input, either action can be executed:

re-trigger counter increment or decrement counter depending on direction start the counter increment or decrement counter based on direction increment counter regardless of direction generate non-recoverable fault 36.6.5.1 DMA Operation The TCC can generate the following DMA requests:

Counter overflow

(OVF) If the One-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the The TCC generates a DMA request on each cycle when an update condition (Overflow, Underflow or Re-trigger) is detected. When an update condition (Overflow, Underflow or Re-trigger) is detected while CTRLA.DMAOS=1, the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to the Control B register (CTRLBSET.CMD=DMAOS). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1052 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) In both cases, the request is cleared by hardware on DMA acknowledge. Channel Match (MCx) A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is cleared by hardware on DMA acknowledge. When CTRLA.DMAOS=1, the DMA requests are not generated. Channel Capture

(MCx) For a capture channel, the request is set when valid data is present in the CCx register, and cleared once the CCx register is read. In this operation mode, the CTRLA.DMAOS bit value is ignored. DMA Operation with Circular Buffer When circular buffer operation is enabled, the Buffer registers must be written in a correct order and synchronized to the update times of the timer. The DMA triggers of the TCC provide a way to ensure a safe and correct update of circular buffers. Note:Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only. DMA Operation with Circular Buffer in RAMP2 and RAMP2A Mode When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match detection, but on start of ramp B. If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A with an effective DMA transfer on previous ramp B (DMA acknowledge). The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC trigger. The update of all circular buffer values for ramp B, can be done through a second DMA channel triggered by the overflow DMA request. Figure 36-38. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled Ramp A B A B A B Cycle N-2 N-1 N COUNT ZERO STATUS.IDX DMA_CCx_req DMA_OVF_req

"update"

DMA Channel i Update ramp A DMA Channel j Update ramp B DMA Operation with Circular Buffer in DSBOTH Mode When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match detection, but on start of down-counting phase. If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase with an effective DMA transfer on previous down-counting phase (DMA acknowledge). When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA request. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1053 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Figure 36-39. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled Cycle N-2 N-1 N Old Parameter Set New Parameter Set COUNT ZERO CTRLB.DIR DMA_CCx_req DMA_OVF_req

"update"

DMA Channel i Update Rising DMA Channel j Update Rising 36.6.5.2 Interrupts The TCC has the following interrupt sources:

Overflow/Underflow (OVF) Retrigger (TRG) Count (CNT) Refer also to the description of EVCTRL.CNTSEL Capture Overflow Error (ERR) Non-Recoverable Update Fault (UFS) Debug Fault State (DFS) Recoverable Faults (FAULTn) Non-recoverable Faults (FAULTx) Compare Match or Capture Channels (MCx) These interrupts are asynchronous wake-up sources. Each interrupt source has an Interrupt flag associated with it. The Interrupt flag in the Interrupt Flag Status and Clear

(INTFLAG) register is set when the Interrupt condition occurs. Each interrupt can be individually enabled by writing a 1 to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a 1 to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the Interrupt flag is cleared, the interrupt is disabled or the TCC is reset. See INTFLAG from Related Links for details on how to clear Interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which Interrupt condition is present. Interrupts must be globally enabled for interrupt requests to be generated. See Nested Vector Interrupt Controller

(NVIC) from Related Links. Related Links 8.2. Nested Vector Interrupt Controller (NVIC) 36.8.12. INTFLAG 36.6.5.3 Events The TCC can generate the following output events:

Overflow/Underflow (OVF) Trigger (TRG) Counter (CNT) (For further details, refer to the EVCTRL.CNTSEL description.) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1054 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Compare Match or Capture on compare/capture channels: MCx Writing a 1 (0) to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the corresponding output event. See Event System (EVSYS) from Related Links. The TCC can take the following actions on a channel input event (MCx):

Capture event Generate a recoverable or non-recoverable fault The TCC can take the following actions on counter Event 1 (TCCx EV1):

Counter re-trigger Counter direction control Stop the counter Decrement the counter on event Period and pulse width capture Non-recoverable fault The TCC can take the following actions on counter Event 0 (TCCx EV0):

Counter re-trigger Count on event (increment or decrement, depending on counter direction) Counter start Start counting on the event rising edge. Further events will not restart the counter; the counter will keep counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction. Counter increment on event. This will increment the counter, irrespective of the counter direction. Count during active state of an asynchronous event (increment or decrement, depending on counter direction). In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as the event is active. Non-recoverable fault The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and EVCTRL.EVACT1). See EVCTRL from Related Links. Writing a 1 (0) to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables

(disables) the corresponding action on input event. Note:When several events are connected to the TCC, the enabled action will apply for each of the incoming events. See Event System (EVSYS) from Related Links for details on how to configure the Event System. Related Links 26. Event System (EVSYS) 36.8.9. EVCTRL 36.6.6 Sleep Mode Operation The TCC can be configured to operate in any sleep mode (Standby Sleep, Idle). To be able to run in standby sleep mode, the RUNSTDBY bit in the Control A register (CTRLA.RUNSTDBY) must be '1'. This peripheral can wake up the device from any sleep mode using interrupts or perform actions through the Event System. 36.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written:

Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE) The following registers are synchronized when written:

Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) Status register (STATUS) Pattern and Pattern Buffer registers (PATT and PATTBUF) Waveform register (WAVE) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1055 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Count Value register (COUNT) Period Value and Period Buffer Value registers (PER and PERBUF) Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx) The following registers are synchronized when read:

Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) Count Value register (COUNT): synchronization is done on demand through READSYNC command

(CTRLBSET.CMD) Pattern and Pattern Buffer registers (PATT and PATTBUF) Waveform register (WAVE) Period Value and Period Buffer Value registers (PER and PERBUF) Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx) Required write synchronization is denoted by the "Write-Synchronized" property in the register description. Required read synchronization is denoted by the "Read-Synchronized" property in the register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1056 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.7 Register Summary See TCCx (x = 0 to 2) module in the Product Memory Mapping Overview from Related Links for base address based on the TCC instant used. Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x00 CTRLA 0x04 0x05 0x06

... 0x07 CTRLBCLR CTRLBSET Reserved 0x08 SYNCBUSY 0x0C FCTRLA 0x10 FCTRLB 0x14 WEXCTRL 0x18 DRVCTRL 0x1C

... 0x1D 0x1E 0x1F Reserved DBGCTRL Reserved 0x20 EVCTRL 0x24 INTENCLR 0x28 INTENSET 0x2C INTFLAG RESOLUTION[1:0]

ENABLE SWRST ALOCK PRESCYNC[1:0]

RUNSTDBY PRESCALER[2:0]

MSYNC DMAOS CPTEN5 CPTEN4 CPTEN3 CPTEN2 CPTEN1 CPTEN0 CMD[2:0]

CMD[2:0]

IDXCMD[1:0]

IDXCMD[1:0]

ONESHOT ONESHOT LUPD LUPD DIR DIR PER WAVE PATT CC5 COUNT STATUS CC4 CC3 CTRLB CC2 ENABLE SWRST CC1 CC0 RESTART BLANKPRES C RESTART BLANKPRES C BLANK[1:0]

QUAL KEEP CAPTURE[2:0]

CHSEL[1:0]

BLANKVAL[7:0]

FILTERVAL[3:0]

BLANK[1:0]

QUAL KEEP CAPTURE[2:0]

CHSEL[1:0]

BLANKVAL[7:0]

SRC[1:0]

HALT[1:0]

SRC[1:0]

HALT[1:0]

FILTERVAL[3:0]

OTMX[1:0]

DTIEN3 DTIEN2 DTIEN1 DTIEN0 DTLS[7:0]

DTHS[7:0]

NRE5 NRV5 NRE4 NRV4 NRE3 NRV3 NRE2 NRV2 NRE1 NRV1 NRE0 NRV0 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0 FILTERVAL1[3:0]

FILTERVAL0[3:0]

FDDBD DBGRUN CNTSEL[1:0]

TCEI1 TCEI0 TCINV1 MCEI5 MCEO5 EVACT1[2:0]

TCINV0 MCEI4 MCEO4 MCEI3 MCEO3 CNTEO MCEI2 MCEO2 FAULT1 FAULT0 FAULTB FAULTA MC5 MC4 FAULT1 FAULT0 FAULTB FAULTA MC5 MC4 FAULT1 FAULT0 FAULTB FAULTA MC5 MC4 ERR DFS MC3 ERR DFS MC3 ERR DFS MC3 CNT UFS MC2 CNT UFS MC2 CNT UFS MC2 EVACT0[2:0]

TRGEO MCEI1 MCEO1 TRG OVFEO MCEI0 MCEO0 OVF MC1 TRG MC1 TRG MC1 MC0 OVF MC0 OVF MC0 7:0 15:8 23:16 31:24 7:0 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1057 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC)

...........continued Offset Name Bit Pos. 7 6 5 4 0x30 STATUS 0x34 COUNT 0x38 0x3A

... 0x3B PATT Reserved 0x3C WAVE 0x40 PER 0x44 CCx0 0x48 CCx1 0x4C CCx2 0x50 CCx3 0x54 CCx4 0x58 CCx5 0x5C

... 0x63 0x64 0x66

... 0x6B Reserved PATTBUF Reserved 0x6C PERBUF 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 7:0 15:8 23:16 31:24 PERBUFV PATTBUFV FAULT1 FAULT0 FAULTB SLAVE FAULTA 3 DFS 2 UFS 1 IDX 0 STOP FAULT1IN FAULT0IN FAULTBIN FAULTAIN CCBUFV5 CCBUFV4 CCBUFV3 CCBUFV2 CCBUFV1 CCBUFV0 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 COUNT[7:0]

COUNT[15:8]

COUNT[23:16]

PGE5 PGV5 PGE4 PGV4 PGE3 PGV3 PGE2 PGV2 PGE1 PGV1 PGE0 PGV0 CIPEREN RAMP[1:0]

WAVEGEN[2:0]

POL5 POL4 CICCEN3 CICCEN2 CICCEN1 CICCEN0 POL3 SWAP3 POL2 SWAP2 POL1 SWAP1 POL0 SWAP0 PER[1:0]

DITHER[5:0]

CC[1:0]

CC[1:0]

CC[1:0]

CC[1:0]

CC[1:0]

CC[1:0]

PER[9:2]

PER[17:10]

CC[9:2]

CC[17:10]

CC[9:2]

CC[17:10]

CC[9:2]

CC[17:10]

CC[9:2]

CC[17:10]

CC[9:2]

CC[17:10]

CC[9:2]

CC[17:10]

DITHER[5:0]

DITHER[5:0]

DITHER[5:0]

DITHER[5:0]

DITHER[5:0]

DITHER[5:0]

PGEB5 PGVB5 PGEB4 PGVB4 PGEB3 PGVB3 PGEB2 PGVB2 PGEB1 PGVB1 PGEB0 PGVB0 PERBUF[1:0]

DITHERBUF[5:0]

PERBUF[9:2]

PERBUF[17:10]

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1058 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC)

...........continued Offset Name Bit Pos. 7 6 5 4 3 2 1 0 0x70 CCBUFx0 0x74 CCBUFx1 0x78 CCBUFx2 0x7C CCBUFx3 0x80 CCBUFx4 0x84 CCBUFx5 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

CCBUF[1:0]

DITHERBUF[5:0]

CCBUF[9:2]

CCBUF[17:10]

Related Links 7. Product Memory Mapping Overview 36.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-

Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable protection is denoted by the "Enable-Protected" property in each individual register description. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1059 Microchip Confidential Confidential Access Reset Bit Access Reset Bit Access Reset 23 DMAOS R/W 0 15 MSYNC R/W 0 PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.1 Control A Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST) CTRLA 0x00 0x00000000 Bit 31 30 29 CPTEN5 R/W 0 28 CPTEN4 R/W 0 27 CPTEN3 R/W 0 26 CPTEN2 R/W 0 25 CPTEN1 R/W 0 24 CPTEN0 R/W 0 22 21 20 19 18 17 16 14 ALOCK R/W 0 12 13 PRESCYNC[1:0]

R/W 0 R/W 0 4 Bit 7 Access Reset 6 5 RESOLUTION[1:0]

R/W R/W 0 0 11 RUNSTDBY R/W 0 3 10 R/W 0 2 9 PRESCALER[2:0]

R/W 0 8 R/W 0 1 ENABLE R/W 0 0 SWRST R/W 0 Bits 24, 25, 26, 27, 28, 29 CPTENCapture Channel x Enable These bits are used to select the capture or compare operation on channel x. Writing a '1' to CPTENx enables capture on channel x. Writing a '0' to CPTENx disables capture on channel x. Bit 23 DMAOSDMA One-Shot Trigger Mode This bit enables the DMA One-shot Trigger Mode. Writing a '1' to this bit will generate a DMA trigger on TCC cycle following a TCC_CTRLBSET_CMD_DMAOS command. Writing a '0' to this bit will generate DMA triggers on each TCC cycle. This bit is not synchronized. Bit 15 MSYNCHost Synchronization (only for TCC client instance) This bit must be set if the TCC counting operation must be synchronized on its Host TCC. This bit is not synchronized. Value 0 1 Description The TCC controls its own counter. The counter is controlled by its Host TCC. Bit 14 ALOCKAuto Lock This bit is not synchronized. Value 0 Description The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow, and re-trigger events CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event. 1 Bits 13:12 PRESCYNC[1:0]Prescaler and Counter Synchronization These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1060 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) These bits are not synchronized. Value Name Description 0x0 0x1 0x2 0x3 GCLK PRESC RESYNC Reserved Counter Reloaded Prescaler Reload or reset Counter on next GCLK Reload or reset Counter on next prescaler clock Reload or reset Counter on next GCLK Reset prescaler counter

Bit 11 RUNSTDBYRun in Standby This bit is used to keep the TCC running in Standby mode. This bit is not synchronized. Value 0 1 Description The TCC is halted in standby. The TCC continues to run in standby. Bits 10:8 PRESCALER[2:0]Prescaler These bits select the Counter prescaler factor. These bits are not synchronized. Name Value DIV1 0x0 DIV2 0x1 DIV4 0x2 DIV8 0x3 DIV16 0x4 DIV64 0x5 DIV256 0x6 DIV1024 0x7 Description Prescaler: GCLK_TCC Prescaler: GCLK_TCC/2 Prescaler: GCLK_TCC/4 Prescaler: GCLK_TCC/8 Prescaler: GCLK_TCC/16 Prescaler: GCLK_TCC/64 Prescaler: GCLK_TCC/256 Prescaler: GCLK_TCC/1024 Bits 6:5 RESOLUTION[1:0]Dithering Resolution These bits increase the TCC resolution by enabling the dithering options. These bits are not synchronized. Table 36-9. Dithering Value 0x0 0x1 0x2 0x3 Name NONE DITH4 DITH5 DITH6 Description The dithering is disabled. Dithering is done every 16 PWM frames. PER[3:0] and CCx[3:0] contain dithering pattern selection. Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection. Bit 1 ENABLEEnable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register

(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 SWRSTSoftware Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be disabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1061 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value 0 1 Description There is no Reset operation ongoing. The Reset operation is ongoing. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1062 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.2 Control B Clear Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized CTRLBCLR 0x04 0x00 This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register. Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 IDXCMD[1:0]

R/W 0 R/W 0 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]TCC Command Writing a 0 to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Value 0x0 0x1 0x2 0x3 0x4 0x5 Description No action Clear start, restart or retrigger Force stop Force update of double buffered registers Force COUNT read synchronization One-shot DMA trigger Name NONE RETRIGGER STOP UPDATE READSYNC DMAOS Bits 4:3 IDXCMD[1:0]Ramp Index Command These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared. Writing zero to these bits has no effect. Writing a '1' to any of these bits will clear the pending command. Value 0x0 0x1 0x2 0x3 Description DISABLE Command disabled: IDX toggles between cycles A and B Set IDX: cycle B will be forced in the next cycle Clear IDX: cycle A will be forced in next cycle Hold IDX: the next cycle will be the same as the current cycle. Name DISABLE SET CLEAR HOLD Bit 2 ONESHOTOne-Shot This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on the next overflow/underflow condition or on a stop command. Writing a '0' to this bit has no effect Writing a '1' to this bit will disable the one-shot operation. Value 0 1 Description The TCC will update the counter value on overflow/underflow condition and continue operation. The TCC will stop counting on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is enabled. This bit has no effect when input capture operation is enabled. Writing a '0' to this bit has no effect. Writing a '1' to this bit will enable the registers updates on hardware UPDATE condition. Value 0 Description The CCBx, PERB, PGVB, and PGEB buffer registers values are copied into the corresponding CCx, PER, PGV, and PGE registers on hardware update condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1063 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Value 1 Description The CCBx, PERB, PGVB, and PGEB buffer registers values are not copied into the corresponding CCx, PER, PGV, and PGE registers on hardware update condition. Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a '0' to this bit has no effect Writing a '1' to this bit will clear the bit and make the counter count up. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1064 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.3 Control B Set Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized CTRLBSET 0x05 0x00 This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear (CTRLBCLR) register. Bit 7 Access Reset R/W 0 6 CMD[2:0]

R/W 0 5 R/W 0 4 3 IDXCMD[1:0]

R/W 0 R/W 0 2 ONESHOT R/W 0 1 LUPD R/W 0 0 DIR R/W 0 Bits 7:5 CMD[2:0]TCC Command These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled GCLK_TCCx clock cycle. Writing a 0 to this bit has no effect Writing a valid value to this bit group, as shown in the following table, will set the associated command. Value 0x0 0x1 0x2 0x3 0x4 0x5 Description No action Force start, restart or retrigger Force stop Force update of double buffered registers Force a read synchronization of COUNT One-shot DMA trigger Name NONE RETRIGGER STOP UPDATE READSYNC DMAOS Bits 4:3 IDXCMD[1:0]Ramp Index Command These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared. Writing a 0 to this bit has no effect Writing a valid value to these bits will set a command. Value 0x0 0x1 0x2 0x3 Description Command disabled: IDX toggles between cycles A and B Set IDX: cycle B will be forced in the next cycle Clear IDX: cycle A will be forced in next cycle Hold IDX: the next cycle will be the same as the current cycle. Name DISABLE SET CLEAR HOLD Bit 2 ONESHOTOne-Shot This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next overflow/underflow condition or a stop command. Writing a 0 to this bit has no effect Writing a 1 to this bit will enable the one-shot operation. Value 0 1 Description The TCC will count continuously. The TCC will stop counting on the next underflow/overflow condition. Bit 1 LUPDLock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled. Disabling the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. This bit has no effect when input capture operation is enabled. Writing a 0 to this bit has no effect 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1065 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Writing a 1 to this bit will disable the registers updates on hardware UPDATE condition. Value 0 Description The CCBx, PERB, PGVB, and PGEB buffer registers values are copied into the corresponding CCx, PER, PGV, and PGE registers on hardware update condition. The CCBx, PERB, PGVB, and PGEB buffer registers values are not copied into CCx, PER, PGV, and PGE registers on hardware update condition. 1 Bit 0 DIRCounter Direction This bit is used to change the direction of the counter. Writing a 0 to this bit has no effect Writing a 1 to this bit will set the bit and make the counter count down. Value 0 1 Description The timer/counter is counting up (incrementing). The timer/counter is counting down (decrementing). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1066 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.4 Synchronization Busy Name:

Offset:

Reset:

Property:

SYNCBUSY 0x08 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 Access Reset Bit Access Reset 7 PER R 0 6 WAVE R 0 13 CC5 R 0 5 PATT R 0 12 CC4 R 0 4 COUNT R 0 11 CC3 R 0 3 STATUS R 0 10 CC2 R 0 2 CTRLB R 0 9 CC1 R 0 1 ENABLE R 0 8 CC0 R 0 0 SWRST R 0 Bits 8, 9, 10, 11, 12, 13 CCCompare/Capture Channel x Synchronization Busy This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is complete. This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started. CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each TCC feature list. This bit is set when the synchronization of CCx register between clock domains is started. Bit 7 PERPER Synchronization Busy This bit is cleared when the synchronization of PER register between the clock domains is complete. This bit is set when the synchronization of PER register between clock domains is started. Bit 6 WAVEWAVE Synchronization Busy This bit is cleared when the synchronization of WAVE register between the clock domains is complete. This bit is set when the synchronization of WAVE register between clock domains is started. Bit 5 PATTPATT Synchronization Busy This bit is cleared when the synchronization of PATTERN register between the clock domains is complete. This bit is set when the synchronization of PATTERN register between clock domains is started. Bit 4 COUNTCOUNT Synchronization Busy This bit is cleared when the synchronization of COUNT register between the clock domains is complete. This bit is set when the synchronization of COUNT register between clock domains is started. Bit 3 STATUSSTATUS Synchronization Busy This bit is cleared when the synchronization of STATUS register between the clock domains is complete. This bit is set when the synchronization of STATUS register between clock domains is started. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1067 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Bit 2 CTRLBCTRLB Synchronization Busy This bit is cleared when the synchronization of CTRLB register between the clock domains is complete. This bit is set when the synchronization of CTRLB register between clock domains is started. Bit 1 ENABLEENABLE Synchronization Busy This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete. This bit is set when the synchronization of ENABLE bit between clock domains is started. Bit 0 SWRSTSWRST Synchronization Busy This bit is cleared when the synchronization of SWRST bit between the clock domains is complete. This bit is set when the synchronization of SWRST bit between clock domains is started. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1068 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.5 Fault Control A and B Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected FCTRLn 0x0C + n*0x04 [n=0..1]

0x00000000 Bit 31 30 29 28 Access Reset Bit 23 Access Reset R/W 0 Bit 15 BLANKPRESC R/W 0 Access Reset Bit 7 RESTART Access Reset R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 21 R/W 0 13 CAPTURE[2:0]

R/W 0 BLANK[1:0]

5 R/W 0 27 R/W 0 19 20 BLANKVAL[7:0]

R/W 0 12 R/W 0 4 QUAL R/W 0 R/W 0 11 R/W 0 CHSEL[1:0]

3 KEEP R/W 0 26 25 FILTERVAL[3:0]

R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 HALT[1:0]

SRC[1:0]

24 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 27:24 FILTERVAL[3:0]Recoverable Fault n Filter Value These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx event is used as synchronous event. Bits 23:16 BLANKVAL[7:0]Recoverable Fault n Blanking Value These bits determine the duration of the blanking of the fault input source. Activation and edge selection of the blank filtering are done by the BLANK bits (FCTRLn.BLANK). When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCCx periods after the detection of the waveform edge. Bit 15 BLANKPRESCRecoverable Fault n Blanking Value Prescaler This bit enables a factor 64 prescaler factor on used as base frequency of the BLANKVAL value. Value 0 1 Description Blank time is BLANKVAL* prescaled GCLK_TCCx. Blank time is BLANKVAL* 64 * prescaled GCLK_TCCx. Bits 14:12 CAPTURE[2:0]Recoverable Fault n Capture Action These bits select the capture and Fault n interrupt/event conditions. Table 36-10. Fault n Capture Action Value Name Description 0x0 0x1 DISABLE Capture on valid recoverable Fault n is disabled CAPT On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value. 0x2 CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC). INTFLAG.FAULTn flag rises on each local minimum detection. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1069 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC)

...........continued Value Name Description 0x3 CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC). INTFLAG.FAULTn flag rises on each local maximun detection. 0x4 LOCMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection. 0x5 LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by 0x6 DERIV0 CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection. On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection. 0x7 CAPTMARK Capture with ramp index as MSB value. Bits 11:10 CHSEL[1:0]Recoverable Fault n Capture Channel These bits select the channel for capture operation triggered by recoverable Fault n. Value 0x0 0x1 0x2 0x3 Description Capture value stored into CC0 Capture value stored into CC1 Capture value stored into CC2 Capture value stored into CC3 Name CC0 CC1 CC2 CC3 Bits 9:8 HALT[1:0]Recoverable Fault n Halt Operation These bits select the halt action for recoverable Fault n. Value 0x0 0x1 0x2 0x3 Name DISABLE HW SW NR Description Halt action disabled Hardware halt action Software halt action Non-recoverable fault Bit 7 RESTARTRecoverable Fault n Restart Setting this bit enables restart action for Fault n. Value 0 1 Description Fault n restart action is disabled. Fault n restart action is enabled. Bits 6:5 BLANK[1:0]Recoverable Fault n Blanking Operation These bits, select the blanking start point for recoverable Fault n. Description Value Blanking applied from start of the Ramp period 0x0 Blanking applied from rising edge of the waveform output 0x1 Blanking applied from falling edge of the waveform output 0x2 Blanking applied from each toggle of the waveform output 0x3 Name START RISE FALL BOTH Bit 4 QUALRecoverable Fault n Qualification Setting this bit enables the recoverable Fault n input qualification. Value 0 1 Description The recoverable Fault n input is not disabled on CMPx value condition. The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0). Bit 3 KEEPRecoverable Fault n Keep Setting this bit enables the Fault n keep action. Value 0 1 Description The Fault n state is released as soon as the recoverable Fault n is released. The Fault n state is released at the end of TCC cycle. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1070 Microchip Confidential Confidential Bits 1:0 SRC[1:0]Recoverable Fault n Source PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) These bits select the TCC event input for recoverable Fault n. Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when used as a recoverable Fault n input. Value 0x0 0x1 0x2 0x3 Description Fault input disabled MCEx (x=0,1) event input Inverted MCEx (x=0,1) event input Alternate fault (A or B) state at the end of the previous period. Name DISABLE ENABLE INVERT ALTFAULT 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1071 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.6 Waveform Extension Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected WEXCTRL 0x14 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset R/W 0 Bit 15 Access Reset 30 R/W 0 22 R/W 0 14 29 R/W 0 21 R/W 0 13 28 R/W 0 20 R/W 0 12 DTHS[7:0]

DTLS[7:0]

27 R/W 0 19 R/W 0 26 R/W 0 18 R/W 0 25 R/W 0 17 R/W 0 24 R/W 0 16 R/W 0 11 DTIEN3 R/W 0 10 DTIEN2 R/W 0 9 DTIEN1 R/W 0 8 DTIEN0 R/W 0 Bit 7 6 5 4 3 2 Access Reset OTMX[1:0]

1 R/W 0 0 R/W 0 Bits 31:24 DTHS[7:0]Dead-Time High Side Outputs Value This register holds the number of GCLK_TCCx clock cycles for the dead-time high side. Bits 23:16 DTLS[7:0]Dead-time Low Side Outputs Value This register holds the number of GCLK_TCCx clock cycles for the dead-time low side. Bits 8, 9, 10, 11 DTIENxDead-time Insertion Generator x Enable [x=0..3]

Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively. Value 0 1 Description No dead-time insertion override. Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal. Bits 1:0 OTMX[1:0]Output Matrix These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Waveform Extension. See Waveform Extension from Related Links. Related Links 36.6.3.8. Waveform Extension 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1072 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.7 Driver Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected DRVCTRL 0x18 0x00000000 Bit 31 Access Reset R/W 0 Bit 23 Access Reset 30 29 FILTERVAL1[3:0]

R/W 0 22 Bit 15 14 Access Reset Bit 7 6 Access Reset 28 R/W 0 20 INVEN4 R/W 0 12 NRV4 R/W 0 4 NRE4 R/W 0 27 R/W 0 19 INVEN3 R/W 0 11 NRV3 R/W 0 3 NRE3 R/W 0 26 25 FILTERVAL0[3:0]

R/W 0 18 INVEN2 R/W 0 10 NRV2 R/W 0 2 NRE2 R/W 0 R/W 0 17 INVEN1 R/W 0 9 NRV1 R/W 0 1 NRE1 R/W 0 24 R/W 0 16 INVEN0 R/W 0 8 NRV0 R/W 0 0 NRE0 R/W 0 R/W 0 21 INVEN5 R/W 0 13 NRV5 R/W 0 5 NRE5 R/W 0 Bits 31:28 FILTERVAL1[3:0]Non-Recoverable Fault Input 1 Filter Value These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a synchronous event, this value must be 0x0. Bits 27:24 FILTERVAL0[3:0]Non-Recoverable Fault Input 0 Filter Value These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is configured as a synchronous event, this value must be 0x0. Bits 16, 17, 18, 19, 20, 21 INVENxWaveform Output x Inversion [x=0..5]

These bits are used to select inversion on the output of channel x. Writing a '1' to INVENx inverts output from WO[x]. Writing a '0' to INVENx disables inversion of output from WO[x]. Bits 8, 9, 10, 11, 12, 13 NRVxNRVx Non-Recoverable State x Output Value [x=0..5]

These bits define the value of the enabled override outputs, under non-recoverable fault condition. Bits 0, 1, 2, 3, 4, 5 NRExNon-Recoverable State x Output Enable [x=0..5]

These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition. Value 0 1 Description Non-recoverable fault tri-state the output. Non-recoverable faults set the output to NRVx level. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1073 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.8 Debug control Name:

Offset:

Reset:

Property: PAC Write-Protection DBGCTRL 0x1E 0x00 Bit 7 6 5 4 3 Access Reset 2 FDDBD R/W 0 1 0 DBGRUN R/W 0 Bit 2 FDDBDFault Detection on Debug Break Detection This bit is not affected by software Reset and should not be changed by software while the TCC is enabled. By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled. When this bit is written to 1, OCD break request from the OCD system will trigger non-recoverable fault. When this bit is set, OCD fault protection is enabled and OCD break request from the OCD system will trigger a non-recoverable fault. Value 0 1 Description No faults are generated when TCC is halted in Debug mode. A non recoverable fault is generated and FAULTD flag is set when TCC is halted in Debug mode. Bit 0 DBGRUNDebug Running State This bit is not affected by software Reset and should not be changed by software while the TCC is enabled. Value 0 1 Description The TCC is halted when the device is halted in Debug mode. The TCC continues normal operation when the device is halted in Debug mode. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1074 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.9 Event Control Name:

Offset:

Reset:

Property: PAC Write-Protection, Enable-Protected EVCTRL 0x20 0x00000000 Bit 31 30 Access Reset Bit 23 22 Access Reset Bit Access Reset 15 TCEI1 R/W 0 14 TCEI0 R/W 0 Bit 7 6 CNTSEL[1:0]

Access Reset R/W 0 R/W 0 29 MCEO5 R/W 0 21 MCEI5 R/W 0 13 TCINV1 R/W 0 5 R/W 0 27 MCEO3 R/W 0 19 MCEI3 R/W 0 11 28 MCEO4 R/W 0 20 MCEI4 R/W 0 12 TCINV0 R/W 0 4 EVACT1[2:0]

R/W 0 3 R/W 0 26 MCEO2 R/W 0 18 MCEI2 R/W 0 10 CNTEO R/W 0 2 R/W 0 25 MCEO1 R/W 0 17 MCEI1 R/W 0 9 TRGEO R/W 0 1 EVACT0[2:0]

R/W 0 24 MCEO0 R/W 0 16 MCEI0 R/W 0 8 OVFEO R/W 0 0 R/W 0 Bits 24, 25, 26, 27, 28, 29 MCEOxMatch or Capture Channel x Event Output Enable [x=0..5]

These bits control if the match/capture event on channel x is enabled and will be generated for every match or capture. Value 0 1 Description Match/capture x event is disabled and will not be generated. Match/capture x event is enabled and will be generated for every compare/capture on channel x. Bits 16, 17, 18, 19, 20, 21 MCEIxMatch or Capture Channel x Event Input Enable [x=0..3]

These bits indicate if the match/capture x incoming event is enabled These bits are used to enable match or capture input events to the CCx channel of TCC. Value 0 1 Description Incoming events are disabled. Incoming events are enabled. Bits 14, 15 TCEIxTimer/Counter Event Input x Enable [x=0..1]

This bit is used to enable input event x to the TCC. Value 0 1 Description Incoming event x is disabled. Incoming event x is enabled. Bits 12, 13 TCINVxTimer/Counter Event x Invert Enable [x=0..1]

This bit inverts the event x input. Value 0 1 Description Input event source x is not inverted. Input event source x is inverted. Bit 10 CNTEOTimer/Counter Event Output Enable This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending on CNTSEL[1:0] settings. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1075 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Value 0 1 Description Counter cycle output event is disabled and will not be generated. Counter cycle output event is enabled and will be generated depending on CNTSEL[1:0] value. Bit 9 TRGEORetrigger Event Output Enable This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter retriggers operation. Value 0 1 Description Counter retrigger event is disabled and will not be generated. Counter retrigger event is enabled and will be generated for every counter retrigger. Bit 8 OVFEOOverflow/Underflow Event Output Enable This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter reaches the TOP or the ZERO value. Description Value Overflow/underflow counter event is disabled and will not be generated. 0 Overflow/underflow counter event is enabled and will be generated for every counter overflow/

1 underflow. Bits 7:6 CNTSEL[1:0]Timer/Counter Interrupt and Event Output Selection These bits define on which part of the counter cycle the counter event output is generated. Value 0x0 0x1 0x2 0x3 Description Name An interrupt/event is generated at begin of each counter cycle BEGIN END An interrupt/event is generated at end of each counter cycle BETWEEN An interrupt/event is generated between each counter cycle. BOUNDARY An interrupt/event is generated at begin of first counter cycle, and end of last counter cycle. Bits 5:3 EVACT1[2:0]Timer/Counter Event Input 1 Action These bits define the action the TCC will perform on TCE1 event input. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Event action disabled. Start, restart or re-trigger TC on event Direction control Stop TC on event Decrement TC on event Period captured into CC0 Pulse Width on CC1 Period captured into CC1 Pulse Width on CC0 Non-recoverable Fault Name OFF RETRIGGER DIR (asynch) STOP DEC PPW PWP FAULT Bits 2:0 EVACT0[2:0]Timer/Counter Event Input 0 Action These bits define the action the TCC will perform on TCE0 event input. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Description Event action disabled. Start, restart or re-trigger TC on event Count on event. Start TC on event Increment TC on EVENT Count on active state of asynchronous event Capture overflow times (Max value) Non-recoverable Fault Name OFF RETRIGGER COUNTEV START INC COUNT (async) STAMP FAULT 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1076 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.10 Interrupt Enable Clear Name:

Offset:

Reset:

Property: PAC Write-Protection INTENCLR 0x24 0x00000000 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 Access Reset Bit Access Reset 15 FAULT1 R/W 0 14 FAULT0 R/W 0 21 MC5 R/W 0 13 FAULTB R/W 0 20 MC4 R/W 0 12 FAULTA R/W 0 Bit 7 6 5 4 Access Reset 19 MC3 R/W 0 11 DFS R/W 0 3 ERR R/W 0 18 MC2 R/W 0 10 UFS R/W 0 2 CNT R/W 0 17 MC1 R/W 0 9 1 TRG R/W 0 16 MC0 R/W 0 8 0 OVF R/W 0 Bits 16, 17, 18, 19, 20, 21 MCxMatch or Capture Channel x Interrupt Disable [x=0..5]

Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which disables the Match or Capture Channel x interrupt. Value 0 1 Description The Match or Capture Channel x interrupt is disabled. The Match or Capture Channel x interrupt is enabled. Bit 15 FAULT1Non-Recoverable Fault 1 Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 1 interrupt. Value 0 1 Description The Non-Recoverable Fault 1 interrupt is disabled. The Non-Recoverable Fault 1 interrupt is enabled. Bit 14 FAULT0Non-Recoverable Fault 0 Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 0 interrupt. Value 0 1 Description The Non-Recoverable Fault 0 interrupt is disabled. The Non-Recoverable Fault 0 interrupt is enabled. Bit 13 FAULTBRecoverable Fault B Interrupt Disable Writing a 0 to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1077 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Writing a 1 to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable Fault B interrupt. Value 0 1 Description The Recoverable Fault B interrupt is disabled. The Recoverable Fault B interrupt is enabled. Bit 12 FAULTARecoverable Fault A Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable Fault A interrupt. Value 0 1 Description The Recoverable Fault A interrupt is disabled. The Recoverable Fault A interrupt is enabled. Bit 11 DFSNon-Recoverable Debug Fault State Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault State interrupt. Value 0 1 Description The Debug Fault State interrupt is disabled. The Debug Fault State interrupt is enabled. Bit 10 UFSNon-Recoverable Update Fault Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the Non-Recoverable Update Fault interrupt. Description Value The Non-Recoverable Update Fault interrupt is disabled. 0 The Non-Recoverable Update Fault interrupt is enabled. 1 Bit 3 ERRError Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 2 CNTCounter Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt. Value 0 1 Description The Counter interrupt is disabled. The Counter interrupt is enabled. Bit 1 TRGRetrigger Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt. Value 0 1 Description The Retrigger interrupt is disabled. The Retrigger interrupt is enabled. Bit 0 OVFOverflow Interrupt Disable Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt. Value 0 Description The Overflow interrupt is disabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1078 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Value 1 Description The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1079 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.11 Interrupt Enable Set Name:

Offset:

Reset:

Property: PAC Write-Protection INTENSET 0x28 0x00000000 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 Access Reset Bit Access Reset 15 FAULT1 R/W 0 14 FAULT0 R/W 0 21 MC5 R/W 0 13 FAULTB R/W 0 20 MC4 R/W 0 12 FAULTA R/W 0 Bit 7 6 5 4 Access Reset 19 MC3 R/W 0 11 DFS R/W 0 3 ERR R/W 0 18 MC2 R/W 0 10 UFS R/W 0 2 CNT R/W 0 17 MC1 R/W 0 9 1 TRG R/W 0 16 MC0 R/W 0 8 0 OVF R/W 0 Bits 16, 17, 18, 19, 20, 21 MCMatch or Capture Channel x Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which enables the Match or Capture Channel x interrupt. Value 0 1 Description The Match or Capture Channel x interrupt is disabled. The Match or Capture Channel x interrupt is enabled. Bit 15 FAULT1Non-Recoverable Fault 1 Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which enables the Non-

Recoverable Fault 1 interrupt. Value 0 1 Description The Non-Recoverable Fault 1 interrupt is disabled. The Non-Recoverable Fault 1 interrupt is enabled. Bit 14 FAULT0Non-Recoverable Fault 0 Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which enables the Non-

Recoverable Fault 0 interrupt. Value 0 1 Description The Non-Recoverable Fault 0 interrupt is disabled. The Non-Recoverable Fault 0 interrupt is enabled. Bit 13 FAULTBRecoverable Fault B Interrupt Enable Writing a 0 to this bit has no effect. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1080 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Writing a 1 to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable Fault B interrupt. Value 0 1 Description The Recoverable Fault B interrupt is disabled. The Recoverable Fault B interrupt is enabled. Bit 12 FAULTARecoverable Fault A Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable Fault A interrupt. Value 0 1 Description The Recoverable Fault A interrupt is disabled. The Recoverable Fault A interrupt is enabled. Bit 11 DFSNon-Recoverable Debug Fault State Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault State interrupt. Value 0 1 Description The Debug Fault State interrupt is disabled. The Debug Fault State interrupt is enabled. Bit 10 UFSNon-Recoverable Update Fault Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which enables the Non-Recoverable Update Fault interrupt. Description Value The Non-Recoverable Update Fault interrupt is disabled. 0 The Non-Recoverable Update Fault interrupt is enabled. 1 Bit 3 ERRError Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 2 CNTCounter Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Counter Interrupt Disable/Enable bit, which enables the Counter interrupt. Value 0 1 Description The Counter interrupt is disabled. The Counter interrupt is enabled. Bit 1 TRGRetrigger Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt. Value 0 1 Description The Retrigger interrupt is disabled. The Retrigger interrupt is enabled. Bit 0 OVFOverflow Interrupt Enable Writing a 0 to this bit has no effect. Writing a 1 to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt. Value 0 Description The Overflow interrupt is disabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1081 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Value 1 Description The Overflow interrupt is enabled. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1082 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.12 Interrupt Flag Status and Clear Name:

Offset:

Reset:

Property:

INTFLAG 0x2C 0x00000000

Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 Access Reset Bit Access Reset 15 FAULT1 R/W 0 14 FAULT0 R/W 0 21 MC5 R/W 0 13 FAULTB R/W 0 20 MC4 R/W 0 12 FAULTA R/W 0 Bit 7 6 5 4 Access Reset 19 MC3 R/W 0 11 DFS R/W 0 3 ERR R/W 0 18 MC2 R/W 0 10 UFS R/W 0 2 CNT R/W 0 17 MC1 R/W 0 9 1 TRG R/W 0 16 MC0 R/W 0 8 0 OVF R/W 0 Bits 16, 17, 18, 19, 20, 21 MCxMatch or Capture Channel x Interrupt Flag [x=0..5]

This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once the CCx register contains a valid capture value. Writing a 0 to one of these bits has no effect. Writing a 1 to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag. In the Capture operation, this flag is automatically cleared when the CCx register is read. Bit 15 FAULT1Non-Recoverable Fault 1 Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Non-Recoverable Fault 1 interrupt flag. Bit 14 FAULT0Non-Recoverable Fault 0 Interrupt Flag Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Non-Recoverable Fault 0 interrupt flag. Bit 13 FAULTBRecoverable Fault B Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Recoverable Fault B interrupt flag. Bit 12 FAULTARecoverable Fault A Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Recoverable Fault A interrupt flag. Bit 11 DFSNon-Recoverable Debug Fault State Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Debug Fault State occurs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1083 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Debug Fault State interrupt flag. Bit 10 UFSNon-Recoverable Update Fault Interrupt Flag This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). Writing a 0 to this bit has no effect. Writing a 1 to this bit will clear the Non-Recoverable Update Fault Interrupt Flag. Bit 3 ERRError Interrupt Flag This flag is set if a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is one. In which case, there is no place to store the new capture. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Error interrupt flag. Bit 2 CNTCounter Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the CNT interrupt flag. Bit 1 TRGRetrigger Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Retrigger interrupt flag. Bit 0 OVFOverflow Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs. Writing a 0 to this bit has no effect. Writing a 1 to this bit clears the Overflow interrupt flag. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1084 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.13 Status Name:

Offset:

Reset:

Property:

STATUS 0x30 0x00000001

Note:Clear STATUS register bits by 32-bits write access only. Bit 31 30 Access Reset Bit 23 22 Access Reset Bit Access Reset 15 FAULT1 R/W 0 Bit 7 PERBUFV Access Reset R/W 0 14 FAULT0 R/W 0 6 29 CMP5 R/W 0 21 CCBUFV5 R/W 0 13 FAULTB R/W 0 5 PATTBUFV R/W 0 28 CMP4 R/W 0 20 CCBUFV4 R/W 0 12 FAULTA R/W 0 4 SLAVE R 0 27 CMP3 R/W 0 19 CCBUFV3 R/W 0 11 FAULT1IN R 0 3 DFS R/W 0 26 CMP2 R/W 0 18 CCBUFV2 R/W 0 10 FAULT0IN R 0 2 UFS R/W 0 25 CMP1 R/W 0 17 CCBUFV1 R/W 0 9 FAULTBIN R 0 1 IDX R 0 24 CMP0 R/W 0 16 CCBUFV0 R/W 0 8 FAULTAIN R 0 0 STOP R 1 Bits 24, 25, 26, 27, 28, 29 CMPxChannel x Compare Value [x=0..5]

This bit reflects the channel x output compare value. Value 0 1 Description Channel compare output value is 0. Channel compare output value is 1. Bits 16, 17, 18, 19, 20, 21 CCBUFVxChannel x Compare or Capture Buffer Valid [x=0..5]

For a compare channel, this bit is set when a new value is written to the corresponding CCBUFx register. The bit is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or automatically on an UPDATE condition. For a capture channel, the bit is set when a valid capture value is stored in the CCBUFx register. The bit is automatically cleared when the CCx register is read. Bits 14, 15 FAULTxNon-recoverable Fault x State [x=0..1]

This bit is set by hardware as soon as non-recoverable Fault x condition occurs. This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low. Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULTx bit. For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD). Bit 13 FAULTBRecoverable Fault B State This bit is set by hardware as soon as recoverable Fault B condition occurs. This bit can be cleared by hardware when Fault B action is resumed, or by writing a '1' to this bit when the corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will release the timer/counter. Bit 12 FAULTARecoverable Fault A State This bit is set by hardware as soon as recoverable Fault A condition occurs. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1085 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) This bit can be cleared by hardware when Fault A action is resumed, or by writing a '1' to this bit when the corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing this bit will release the timer/counter. Bit 11 FAULT1INNon-Recoverable Fault 1 Input This bit is set while an active Non-Recoverable Fault 1 input is present. Bit 10 FAULT0INNon-Recoverable Fault 0 Input This bit is set while an active Non-Recoverable Fault 0 input is present. Bit 9 FAULTBINRecoverable Fault B Input This bit is set while an active Recoverable Fault B input is present. Bit 8 FAULTAINRecoverable Fault A Input This bit is set while an active Recoverable Fault A input is present. Bit 7 PERBUFVPeriod Buffer Valid This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared by hardware on UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit. Bit 5 PATTBUFVPattern Generator Value Buffer Valid This bit is set when a new value is written to the PATTBUF register. This bit is automatically cleared by hardware on UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit. Bit 4 SLAVEClient Mode Enable This bit is set when TCC is set in Client mode. This bit follows the CTRLA.MSYNC bit state. Bit 3 DFSDebug Fault State This bit is set by hardware in Debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by writing a '1' to this bit and when the TCC is not in Debug mode. When the bit is set, the counter is halted and the Waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers. Bit 2 UFSNon-recoverable Update Fault State This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit is cleared by writing a one to this bit. When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers. Bit 1 IDXRamp Index In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1 operation, the bit always reads zero. See Ramp Operations from Related Links. Bit 0 STOPStop This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot operation mode is enabled (CTRLBSET.ONESHOT=1). This bit is cleared on the next incoming counter increment or decrement. Value 0 1 Description Counter is running. Counter is stopped. Related Links 36.6.3.4. Ramp Operations 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1086 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.14 Counter Value Name:

Offset:

Reset:

Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized COUNT 0x34 0x00000000 Note:Prior to any read access, this register must be synchronized by user by writing the according TCC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 Access Reset R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 20 19 COUNT[23:16]

R/W 0 12 R/W 0 11 COUNT[15:8]

R/W 0 4 R/W 0 3 COUNT[7:0]

R/W 0 R/W 0 18 R/W 0 10 R/W 0 2 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 23:0 COUNT[23:0]Counter Value These bits hold the value of the Counter register. Note:When the TCC is configured as 16-bit timer/counter, the excess bits are read zero. Note:This bit field occupies the MSBs of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [23:m]

23:0 (depicted) 23:4 23:5 23:6 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1087 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.15 Pattern PATT Name:

0x38 Offset:

Reset:

0x0000 Property: Write-Synchronized Bit 15 14 Access Reset Bit 7 6 Access Reset 13 PGV5 R/W 0 5 PGE5 R/W 0 12 PGV4 R/W 0 4 PGE4 R/W 0 11 PGV3 R/W 0 3 PGE3 R/W 0 10 PGV2 R/W 0 2 PGE2 R/W 0 9 PGV1 R/W 0 1 PGE1 R/W 0 8 PGV0 R/W 0 0 PGE0 R/W 0 Bits 8, 9, 10, 11, 12, 13 PGVxPattern Generation Output Value [x=0..5]

This register holds the values of pattern for each waveform output. Bits 0, 1, 2, 3, 4, 5 PGExPattern Generation Output Enable [x=0..5]

This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override the corresponding SWAP output with the corresponding PGVx value. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1088 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.16 Waveform Name:

Offset:

Reset:

Property: Write-Synchronized WAVE 0x3C 0x00000000 Bit 31 30 29 28 Access Reset Bit 23 22 Access Reset 21 POL5 R/W 0 20 POL4 R/W 0 Bit 15 14 13 12 Access Reset Bit Access Reset 6 7 CIPEREN R/W 0 RAMP[1:0]

5 R/W 0 4 R/W 0 27 SWAP3 R/W 0 19 POL3 R/W 0 11 CICCEN3 R/W 0 3 26 SWAP2 R/W 0 18 POL2 R/W 0 25 SWAP1 R/W 0 17 POL1 R/W 0 24 SWAP0 R/W 0 16 POL0 R/W 0 10 CICCEN2 R/W 0 9 CICCEN1 R/W 0 8 CICCEN0 R/W 0 2 R/W 0 1 WAVEGEN[2:0]

R/W 0 0 R/W 0 Bits 24, 25, 26, 27 SWAPxSwap DTI Output Pair x [x=0..3]

Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not affect the swap operation. Bits 16, 17, 18, 19, 20, 21 POLxChannel Polarity x [x=0..5]

Setting these bits enables the output polarity in single-slope and dual-slope PWM operations. Value 0 Name

(single-slope PWM waveform generation)

(single-slope PWM waveform generation)

(dual-slope PWM waveform generation)

(dual-slope PWM waveform generation) Description Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value. Compare output is set to ~DIR when TCC counter matches CCx value Compare output is set to DIR when TCC counter matches CCx value. 1 0 1 Bits 8, 9, 10, 11 CICCENxCircular CC Enable x [x=0..3]

Setting these bits enables the compare circular buffer option on the first four Compare/Capture channels. When the bit is set, CCx register value is copied-back into the CCBUFx register on UPDATE condition. Bit 7 CIPERENCircular Period Enable Setting this bit enables the period circular buffer option. When the bit is set, the PER register value is copied-back into the PERBUF register on UPDATE condition. Bits 5:4 RAMP[1:0]Ramp Operation These bits select Ramp operation (RAMP). These bits are not synchronized. Value 0x0 0x1 Description RAMP1 operation Alternative RAMP2 operation Name RAMP1 RAMP2A 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1089 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Value 0x2 0x3 Name RAMP2 RAMP2C Description RAMP2 operation Critical RAMP2 operation Bits 2:0 WAVEGEN[2:0]Waveform Generation Operation These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation should be used. These bits are not synchronized. Value Name Description Operation Top Update Waveform Output On Match Waveform Output On Update OVFIF/Event Up Down 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 NFRQ MFRQ NPWM Normal Frequency Match Frequency Normal PWM Reserved

DSCRITICAL Dual-slope PWM DSBOTTOM Dual-slope PWM DSBOTH DSTOP Dual-slope PWM Dual-slope PWM PER CC0 PER

PER PER PER PER TOP/Zero TOP/Zero TOP/Zero

Zero Zero TOP & Zero Zero Toggle Toggle Set

~DIR

~DIR

~DIR

~DIR Stable Stable Clear

Stable Stable Stable Stable TOP TOP TOP

TOP TOP Zero Zero Zero

Zero Zero Zero 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1090 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.17 Period Value Name:

Offset:

Reset:

Property: Write-Synchronized PER 0x40 0x00FFFFFF Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 1 Bit 15 Access Reset R/W 1 Bit 7 PER[1:0]

Access Reset R/W 1 22 R/W 1 14 R/W 1 6 R/W 1 Bits 23:6 PER[17:0]Period Value 21 R/W 1 13 R/W 1 5 R/W 1 20 R/W 1 12 R/W 1 4 R/W 1 PER[17:10]

PER[9:2]

19 R/W 1 11 R/W 1 3 18 R/W 1 10 R/W 1 2 DITHER[5:0]

R/W 1 R/W 1 17 R/W 1 9 R/W 1 1 R/W 1 16 R/W 1 8 R/W 1 0 R/W 1 These bits hold the value of the TCC period count. The number of bits in this field corresponds to the size of the counter. Note:When the TCC is configured as 16-bit timer/counter, the excess bits are read zero. Note:This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [23:m]

23:0 23:4 23:5 23:6 (depicted) Bits 5:0 DITHER[5:0]Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames. Note:This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [n:0]

3:0 4:0 5:0 (depicted) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1091 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.18 Compare/Capture Channel x Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized CCx 0x44 + x*0x04 [x=0..5]

0x00000000 The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of operation. For capture operation, this register represents the second buffer level and access point for the CPU and DMA. For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms. CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition occurs. In addition, in match frequency operation, the CC0 register controls the counter period. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 CC[1:0]

Access Reset R/W 0 22 R/W 0 14 R/W 0 6 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 20 R/W 0 12 R/W 0 4 R/W 0 CC[17:10]

CC[9:2]

19 R/W 0 11 R/W 0 3 18 R/W 0 10 R/W 0 2 DITHER[5:0]

R/W 0 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 23:6 CC[17:0]Channel x Compare/Capture Value These bits hold the value of the Channel x compare/capture register. Notes:

1. When the TCC is configured as a 16-bit timer/counter, the excess bits are read as zero. 2. This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [23:m]

23:0 23:4 23:5 23:6 (depicted) Bits 5:0 DITHER[5:0]Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1092 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) Note:This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [n:0]

3:0 4:0 5:0 (depicted) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1093 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.19 Pattern Buffer Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized PATTBUF 0x64 0x0000 Bit 15 14 Access Reset Bit 7 6 Access Reset 13 PGVB5 R/W 0 5 PGEB5 R/W 0 12 PGVB4 R/W 0 4 PGEB4 R/W 0 11 PGVB3 R/W 0 3 PGEB3 R/W 0 10 PGVB2 R/W 0 2 PGEB2 R/W 0 9 PGVB1 R/W 0 1 PGEB1 R/W 0 8 PGVB0 R/W 0 0 PGEB0 R/W 0 Bits 8, 9, 10, 11, 12, 13 PGVBxPattern Generation Output Value Buffer [x=0..5]

This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the PGVx register on an UPDATE condition. Bits 0, 1, 2, 3, 4, 5 PGEBxPattern Generation Output Enable Buffer [x=0..5]

This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into the PGEx register at an UPDATE condition. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1094 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.20 Period Buffer Value Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized PERBUF 0x6C 0x00FFFFFF Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 1 Bit 15 Access Reset R/W 1 Bit 7 22 R/W 1 14 R/W 1 6 PERBUF[1:0]

Access Reset R/W 1 R/W 1 21 R/W 1 13 R/W 1 5 R/W 1 18 R/W 1 10 R/W 1 20 19 PERBUF[17:10]

R/W 1 12 R/W 1 11 PERBUF[9:2]

R/W 1 R/W 1 4 R/W 1 3 2 DITHERBUF[5:0]

R/W 1 R/W 1 17 R/W 1 9 R/W 1 1 R/W 1 16 R/W 1 8 R/W 1 0 R/W 1 Bits 23:6 PERBUF[17:0]Period Buffer Value These bits hold the value of the Period Buffer register. The value is copied to PER register on UPDATE condition. Note:When the TCC is configured as 16-bit timer/counter, the excess bits are read zero. Note:This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [23:m]

23:0 23:4 23:5 23:6 (depicted) Bits 5:0 DITHERBUF[5:0]Dithering Buffer Cycle Number These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is copied to the PER.DITHER bits on an UPDATE condition. Note:This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [n:0]

3:0 4:0 5:0 (depicted) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1095 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Timer/Counter for Control Applications (TCC) 36.8.21 Channel x Compare/Capture Buffer Value Name:

Offset:

Reset:

Property: Write-Synchronized, Read-Synchronized CCBUFx 0x70 + x*0x04 [x=0..5]

0x00000000 CCBUFx is copied into CCx at TCC update time Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 Access Reset R/W 0 Bit 15 Access Reset R/W 0 Bit 7 22 R/W 0 14 R/W 0 6 CCBUF[1:0]

Access Reset R/W 0 R/W 0 21 R/W 0 13 R/W 0 5 R/W 0 18 R/W 0 10 R/W 0 20 19 CCBUF[17:10]

R/W 0 12 R/W 0 11 CCBUF[9:2]

R/W 0 R/W 0 4 R/W 0 3 2 DITHERBUF[5:0]

R/W 0 R/W 0 17 R/W 0 9 R/W 0 1 R/W 0 16 R/W 0 8 R/W 0 0 R/W 0 Bits 23:6 CCBUF[17:0]Channel x Compare/Capture Buffer Value [x=0..5]

These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corresponding CCBUFVx status bit. Notes:

1. When the TCC is configured as a 16-bit timer/counter, the excess bits are read as zero. 2. This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [23:m]

23:0 23:4 23:5 23:6 (depicted) Bits 5:0 DITHERBUF[5:0]Dithering Buffer Cycle Number These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits value is copied to the CCx.DITHER bits on an UPDATE condition. Note:This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):

CTRLA.RESOLUTION 0x0 - NONE 0x1 - DITH4 0x2 - DITH5 0x3 - DITH6 Bits [n:0]

3:0 4:0 5:0 (depicted) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1096 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Zigbee Bluetooth Radio Subsystem (ZBT) 37. Zigbee Bluetooth Radio Subsystem (ZBT) 37.1 Overview The PIC32CX-BZ3 and the WBZ35x provides an on-chip IEEE 802.15.4 and 802.15.3 compliant Zigbee, Bluetooth Low Energy 5.2 interface with integrated transceivers. The Wireless Subsystem block comprises of the following modules:

Single ultra-low power 2.4 GHz ISM band RF transceiver Radio arbiter Bluetooth modem Bluetooth link layer ZigBee modem ZigBee MAC The radio arbiter hardware allows to establish simultaneous Bluetooth and ZigBee links with dynamic switching and programmable QoS. The RF transceiver includes a switching power amplifier architecture, and a transmit/receive switch. Therefore, medium to high power application use cases are supported without an external front-end module

(FEM). With integrated Ultra Low Power 2.4 GHz ISM band single transceiver, dual modem, and dual MAC, the Radio supports dual Zigbee and Bluetooth 5.2 link protocols. An on board intelligent Radio Arbiter hardware module establishes both the links simultaneously using single Radio Transmit/Receive with programmable QoS. The RF transceiver includes Switching Power Amplifiers architecture, and TR Switch. Therefore medium to high power application use cases are supported without external FEM. The RTOS which is running on the Cortex M4F CPU handles the arbitration between the application, the Bluetooth link stack, the ZigBee link stack, and miscellaneous maintenance tasks. 37.2 Features 2.4 GHz RF Transceiver Integrated 2.4 GHz Ultra-low Power RF Transceiver Shared between Bluetooth and Zigbee Modems and Link

(MAC) Controllers Integrated Crystal Oscillator with Support for 16 MHz Crystal Internal Parallel PA Paths, which may be Shut Down to Control Pout as well as Current Consumption to Improve TX Power Efficiency Low BOM Single-ended TRX RFFE Architecture Integrated balun (single ended RF output) and TRX switch Hardware Radio Arbiter with Programmable QoS:

Resolution: up to per packet level Time-division coexistence between Bluetooth and 802.15.4 Based on shared transceiver and antenna Bluetooth Bluetooth Low Energy 5.2 Certified Up to +10 dBm Programmable Transmit Output Power Typical Receiver Power Sensitivity:

-97 dBm for Bluetooth low energy 1 Mbps

-95 dBm for Bluetooth low energy 2 Mbps

-108 dBm for Bluetooth low energy 125 Kbps

-102 dBm for Bluetooth low energy 500 Kbps Wideband RSSI 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1097 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Zigbee Bluetooth Radio Subsystem (ZBT) Enables Interference Robustness and Higher Tolerance to Out-of-Band Blockers Bluetooth Supported Features:

2M uncoded PHY Long range (Coded PHY) Channel selection algorithm #2 Advertising extensions, offloads CPU with hardware based scheduler High duty cycle non-connectible advertising Data length extensions Secure connections Privacy upgrades (with hardware white-list support) ECDH P256 Hardware Engine for Link Key Generation When Bluetooth Pairing AES128 Hardware Module for Real-Time Bluetooth Payload Data Encryption HCI Interface via UART LE Power Control Bluetooth Low Energy Profiles/Services:

Bluetooth Low Energy peripheral and central roles Bluetooth Low Energy APIs for application layer to implement standard or customize GATT based profiles/

services Alert notification service Proximity reporter (PXP) Time information Zigbee PSDU Data Rate: 250 Kbps Programmable RX Mode

-103 dBm RX sensitivity (typical) in the Continuous mode

-96 dBm sensitivity in the RPC mode RPC mode provides lower power consumption in the RX mode to support California Green Energy Specification at the system level Proprietary Modulation Schemes Typical sensitivity level for the proprietary data rates:

500 Kbps: -98 dBm 1 Mbps: -96 dBm 2 Mbps: -90 dBm TX Output Power up to +10 dBm Hardware Assisted MAC Auto acknowledge Auto retry Channel access back-off SFD Detection; Spreading; De-spreading; Framing; CRC-16 Computation Independent TX/RX Buffers for Improved CPU Offloading while Handling Zigbee Data 128-byte TX and 128-byte RX frame buffer Hardware Security Advanced Encryption Standard (AES) True Random Number Generator (TRNG) Zigbee Stack Support Zigbee 3.0 ready Zigbee Pro 2017 Zigbee green power support (proxy, sink, and multi sensor) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1098 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Zigbee Bluetooth Radio Subsystem (ZBT) 37.3 Wireless Subsystem Top Level Diagram Figure 37-1. Wireless Subsystem Top Level Diagram 37.4 Analog RF Front-end The analog front-end contains the following:

RF antenna switch XTO, connecting to a 16 MHz crystal oscillator RF synthesizer Analog RX path (LNA, Mixer, IF amplifier) ADC Analog TX path (Power amplifier) System clock PLL RF-related power management (RF-LDOs) Analog control logic 37.5 Digital Front-end The digital front-end (DFE) connects to the analog front-end on one side and the Bluetooth or Zigbee baseband on the other side. In the receive path, the I/Q data from the ADC are filtered and down-converted. Automatic gain control is also implemented in the DFE. In the transmit path, the Zigbee power control is done in the DFE. 37.6 Bluetooth Low-Energy Link Controller The Bluetooth Low-Energy Link Controller consists of the TX/RX modem and the link layer. The modem is responsible for modulation and demodulation of the digital IF data for both, Bluetooth classic and Bluetooth Low-

Energy. The baseband link layer carries out all Bluetooth operations as transmit or receive tasks. There are several task masters:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1099 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Zigbee Bluetooth Radio Subsystem (ZBT) Firmware Firmware can trigger tasks by writing the task controller registers 1. 2. Hardware Schedule Controller This is Bluetooth low-energy advertisement scheduler controller (Advertiser role) 3. Hardware Scanner This is Bluetooth LE advertisement scanner (Central role) 4. Bluetooth Low-Energy advertisement controller: This is Bluetooth 4.2 advertisement controller (Advertiser role) The requests from the task masters are arbitrated and carried out by the task controller. The RX and TX data are written to common memory via DMA over an AHB interface. 37.7 Zigbee Subsystem The Zigbee Subsystem deals with the physical/modem layer and the MAC layer of the Zigbee transceiver. A digital baseband processor down-converts and demodulates the received IF data, the subsequent modules implement basic MAC functionality and hardware accelerators for features, such as automatic acknowledgment, CSMA_CA and retransmission or automatic FCS check. The flow control is done by a Finite State Machine (FSM). The data is stored in integrated 128-bytes RX and TX frame buffers. 37.8 Radio Arbiter The Radio Arbiter provides a low-level arbitration for using the single RF frontend for both, Zigbee and Bluetooth links. The arbiter supports the following modes:

BT static Radio ownership is with the Bluetooth link controller. ZB static Radio ownership is with the Zigbee subysystem. Dynamic Radio ownership is decided dynamically at every arbitration event. In the static modes, either the Bluetooth link controller or the Zigbee subsystem continuously own the radio. No arbitration is done. Every firmware command or transaction which is issued to the Bluetooth link layer or the ZigBee MAC results in a radio request from the corresponding controller to the arbiter hardware. The firmware stack must accompany each request by the following three main attributes:

Base priority (4-bit) Time sensitivity (transaction is timing critical) Atomic nature (burst mode) In the dynamic mode, the ownership of the radio is decided at every arbitration event. In between events the radio is retained by the current owner. 37.9 Register Banks The ZBT subsystem contains various register banks to configure and control the digital baseband hardware and state machines. The firmware accesses the registers by the ARM APB bus. 37.10 Coexistence Interface Bluetooth and Wi-Fi partly operate in the same 2.4 GHz band. Therefore, transmissions can interfere with each other and impact the performance and reliability of the wireless systems. The Coexistence interface is built of a 3-wire bus that allows to mutually signalize RF activity when Bluetooth and Wi-Fi chips are available in the same hardware module. Interference can thus be avoided. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1100 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics 38. Electrical Characteristics This chapter provides the Electrical Specification and Characteristic of PIC32CX-BZ3 and WBZ35x Module across the operating temperature range of the product. 38.1 Absolute Maximum Electrical Characteristics Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Table 38-1. Absolute Maximum Ratings Parameter Ambient temperature under bias(Note) Storage temperature Voltage on VDD / VDDIO with respect to GND Value

-40C to +125C

-65C to +150C

-0.3V to +4.0V Voltage on any tolerant pins, with respect to GND

-0.3V to (VDD + 0.3V) Maximum current out of GND pins Maximum current into VDD pins(2) Maximum output current sourced/sunk by any Low Current Mode I/O pin (4x drive strength) Maximum output current sourced/sunk by any High Current Mode I/O pin (8x drive strength) Maximum current sink by all ports Maximum current sourced by all ports(2) ESD Qualification Human Body Model (HBM) per JESD22-A114 300 mA 300 mA 10 mA 15 mA 120 mA 120 mA 2000V Charged Device Model (CDM) (ANSI/ESD STM 5.3.1)(All pins / Corner pins)

+500V/- 500V Notes:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. Maximum allowable current is a function of device maximum power dissipation (See the Thermal Operating Conditions table in the Thermal Specifications from Related Links). Related Links 38.3. Thermal Specifications 38.2 DC Electrical Characteristics Table 38-2. Operating Frequency VS. Voltage Param. No. VDDIO, VDDANA Range Temp. Range (in C) Max. MCU Frequency Comments DC_5 1.9V to 3.6V

-40C to +85C 64 MHz Industrial 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1101 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics

...........continued Param. No. VDDIO, VDDANA Range Temp. Range (in C) Max. MCU Frequency Comments DC_7 1.9V to 3.6V

-40C to +125C 64 MHz Extended Note:The same voltage must be applied to VDDIN and VDDANA. 38.3 Thermal Specifications Table 38-3. Thermal Operating Conditions Rating Symbol Min. Typ Max. Unit Industrial Temperature Devices:

Operating ambient temperature range Operating junction temperature range V-Temp Temperature Devices:

Operating ambient temperature range Operating junction temperature range Extended Temperature Range:

Operating ambient temperature range Operating junction temperature range TA TJ TA TJ TA TJ

-40

-40

-40

-40

-40

-40 Maximum allowed power dissipation PDMAX

(TJ TA)/JA

+85

+105

+105

+125

+125

+135 C C C C C C W 38.4 Active Current Consumption DC Electrical Specifications Table 38-4. Active Current Consumption DC Electrical Specifications DC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Clock/Freq Typ (1) APWR_1 APWR_2 IDD_ACTIVE

(2,3) APWR_3 APWR_4 MCU IDD in Active mode w/LDO mode selected MCU IDD in Active mode w/

BUCK mode selected PLL 64 MHz 131 FRC 8 MHz 443 PLL 64 MHz 76.8 FRC 8 MHz 300 Max. Units Conditions A/MHz VDD =

VDDANA =

3.3V 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1102 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-1. Run Mode Current Consumption in Buck Mode at PLL 64 MHz

) A m

n o i t p m u s n o C t n e r r u C 8 7 6 5 4 3 2 1 0

-40 0 25 60 85 105 125 Temperature (in degree Celcius) Figure 38-2. Run Mode Current Consumption in MLDO Mode at PLL 64 MHz 12 10

) A m

n o i t p m u s n o C t n e r r u C 8 6 4 2 0

-40 0 25 60 85 105 125 Temperature (in degree Celcius) 2.4V 2.7V 3.3V 3.6V 1.9V 2.4V 2.7V 3.3V 3.6V 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1103 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

1. 2. Typical value measured at 3.3V and 25. The test conditions are as follows:

All GPIO except RPA3 pulled up. RPA3 is pulled down. RF system in IDLE state. Not transmitting or receiving packets. All peripherals are disabled. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. PMU 1 MHz clock is derived from FRC. FRC is divided by 8. Cache is enabled and configured to wait states PFMWS[3:0] as 0xF. Backup RAM in the Retention mode. DSU is disconnected. 3. MCU running while(1) loop with 50 NOP instructions. 38.5 Idle Current Consumption DC Electrical Specifications Table 38-5. Idle Current Consumption DC Electrical Specifications DC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Clock/Freq Typ(1) Max. Units IPWR_1 IDD_IDLE (2) MCU IDD in IDLE IPWR_2 IPWR_3 IPWR_4 mode w/LDO mode selected MCU IDD in IDLE mode w/BUCK mode selected A/MHz PLL 64 MHz 83 FRC 8 MHz 336 PLL 64 MHz 52.8 FRC 8 MHz 282 Conditions

(3) VDDIO =

VDDANA =

3.3V 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1104 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-3. Idle Mode Current Consumption in Buck Mode at PLL 64 MHz A m n i t n e r r u C 6 5 4 3 2 1 0

-40 0 25 60 Temperature in Degree C 85 105 125 Figure 38-4. Idle Mode Current Consumption in MLDO Mode at PLL 64 MHz A m n i t n e r r u C 9 8 7 6 5 4 3 2 1 0

-40 0 25 60 Temperature in Degree C 85 105 125 2.4 - 64 2.7 - 64 3.3 - 64 3.6 - 64 1.9 - 64 2.4 - 64 2.7 - 64 3.3 - 64 3.6 - 64 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1105 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

1. 2. Typical value measured during characterization at 3.3V and 25. The test conditions are as follows:

All GPIO except RPA3 are pulled up. RPA3 is pulled down. All peripherals are disabled. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. PMU 1 MHz clock is derived from FRC. FRC is divided by 8. Cache is enabled and configured to wait states PFMWS[3:0] as 0xF. Backup RAM in the Retention mode. DSU is disconnected. RF system clock is gated. Entry to the Sleep mode is disabled and WFI instruction is executed. No active RF transmission or reception during current measurement. 38.6 Sleep Current Consumption DC Electrical Specifications Table 38-6. Sleep Current Consumption DC Electrical Specifications DC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics VDDIO Typ(1) Max. Units Conditions SPWR_1 IDD_SLEEP SPWR_29 MCU IDD in Sleep mode w/LDO mode selected MCU IDD in Sleep mode w/

BUCK mode selected 3.3V 3.3V 3.3V 3.3V 950 620 470 450 A A A A XTAL ON XTAL OFF XTAL ON XTAL OFF Figure 38-5. Sleep Current with XTAL_OFF_MLDO

) A m

t n e r r u C _ a t o T _ D D l I 5 4 3 2 1 0

-40 0 25 Temperature (Degree C) 60 85 105 125 1.9 2.4 2.7 3.3 3.6 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1106 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-6. Sleep Current with XTAL_OFF_DC_DC

) A m

t n e r r u C _ a t o T _ D D l I 5 4 3 2 1 0

-40 0 25 60 Temperature (Degree C) 85 105 125 Figure 38-7. Sleep Current with XTAL_ON_MLDO 3

) A m

t n e r r u C _ a t o T _ D D l I 2.5 2 1.5 1 0.5 0

-40 0 25 60 Temperature (Degree C) 85 105 125 Figure 38-8. Sleep Current with XTAL_ON_DC_DC

) A m

t n e r r u C _ a t o T _ D D l I 5 4 3 2 1 0

-40 0 25 60 Temperature (Degree C) 85 105 125 2.4 2.7 3.3 3.6 1.9 2.4 2.7 3.3 3.6 2.4 2.7 3.3 3.6 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1107 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

1. 2. Typical value measured during characterization at 3.3V and 25. The test conditions are as follows:

All GPIO except RPA3 are pulled up. RPA3 is pulled down. All peripherals are disabled (except EIC). All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. CLDO is configured at lowest possible voltage (VREG Trim = 0x07). PMU is configured to the Buck PSM mode on the Sleep Mode Entry with current sense is disabled. Cache is enabled and configured to wait states PFMWS[3:0] as 0xF. Backup RAM in the Retention mode. DSU is disconnected. RF system is in low power configuration. Entry to the Sleep mode is enabled and WFI instruction is executed. In XTAL ON mode - PMU Buck clock is derived from POSC 16 MHz and scaled to 1 MHz. FRC is OFF. In XTAL OFF mode - PMU is clocked from FRC and XTAL 16 MHz clock is disabled and clock configuration in CRU changed to FRC. 38.7 Deep Sleep Current Consumption DC Electrical Specifications Table 38-7. Deep Sleep Current Consumption DC Electrical Specifications DC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics VDDIO Typ(1) Max. Units Conditions BPWR_1 IDD_BACKUP

(2) MCU IDD in BPWR_2 Deep Sleep mode powered from VDDIO 3.3V 3.3V 1.2 1.5 A A No backup RAM retained 8 KB backup RAM retained Figure 38-9. Deep Sleep Current RAM ON A n i t n e r r u C 6 5 4 3 2 1 0 1.9 2.4 2.7 3.3 3.6

-40 0 25 60 Temperature ( C) 85 105 125 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1108 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-10. Deep Sleep Current RAM OFF 4 3.5 3 2.5 2 1.5 1 0.5 0 A n i t n e r r u C Notes:

1.9 2.4 2.7 3.3 3.6

-40 0 25 60 Temperature ( C) 85 105 125 1. 2. Typical value measured during characterization at 3.3V and 25. The test conditions are as follows:

All GPIO except RPA3 are pulled up. RPA3 is pulled down. All peripherals are disabled. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC and POSC is disabled. DSU is disconnected. RF system is in low power configuration. DSWDT is enabled and configured for wake-up. Deep sleep entry is configured and WFI instruction is executed. 38.8 XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications Table 38-8. XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications DC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics VDDIO Typ(1) Max. Units Conditions OPWR_1 IDD_OFF

(2) MCU IDD in OFF mode powered from VDDIOx 3.3V 0.12 A In OFF mode, the device is entirely powered-off. Note:This mode is left by pulling the RESET pin low, or when a power Reset is done. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1109 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-11. Extreme Deep Sleep Current 2.5 2 1.5 1 A n i t n e r r u C 0.5 0 Notes:

1.9 2.4 2.7 3.3 3.6

-40 0 25 60 85 105 125 Temperature ( C) 1. 2. Typical value measured during characterization at 3.3V and 25. The test conditions are as follows:

All GPIO except RPA3 are pulled up. RPA3 is pulled down. All peripherals are disabled. DSU is disconnected. RF system is in low power configuration. DSWDT is disabled. RTCC and POSC is disabled. Deep sleep entry is configured and WFI instruction is executed. 38.9 External XTAL and Clock AC Electrical Specifications Table 38-9. External XTAL and Clock AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Symbol Characteristics Min. Typ Max. Units Conditions(1) Param. No. XOSC_1 FOSC_XOS C XOSC crystal frequency XOSC_1A TOSC TOSC = 1/

FOSC_XOSC XOSC_2 XOSC_ST(2) XOSC crystal start-up time 16 0.0625 MHz ns 2.5 ms See parameter XOSC1 for FOSC_XOSC value Crystal stabilization time only not oscillator ready 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1110 Microchip Confidential Confidential

...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ Max. Units Conditions(1) XOSC_3 CXIN XOSC_5 CXOUT XOSC_11 CLOAD(3) XOSC_21 ESR XOSC_33 DLEVEL XOSC XIN parasitic pin capacitance XOSC XOUT parasitic pin capacitance XOSC crystal FOSC = 16 MHz XOSC crystal FOSC = 16 MHz MCU crystal oscillator power drive level XOSC_34 FREQ ERROR Center frequency error

-30 Figure 38-12. External XTAL and Clock Diagram 0.35 0.35 9 100 100 pF pF pF W With default crystal trim settings(2) With default crystal trim settings

+30 ppm Across temperature C1 XTAL N X I T U O X 2 C RS 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1111 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

VDDIO = VDDANA = 3.3V. 1. 2. Refer RDP for information related to crystal trimming. 3. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitic that are outside the scope of this specification. The test conditions for crystal load capacitor calculation are as follows:

4. Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (in other words, PCB STD TRACE W

= 0.175 mm, H = 36 m, T = 113 m). Xtal PCB capacitance typical; therefore, ~= 2.5 pF for a tight PCB xtal layout For CXIN and CXOUT within 4 pF of each other, assume CXTAL_EFF = ((CXIN+CXOUT) / 2). Note:Averaging CXIN and CXOUT will affect the final calculated CLOAD value by less than 0.25 pF. Equation 38-1.Equation 1:

MFG CLOAD Spec =

Assuming C1 = C2 and CXin ~= CXout, the formula can be further simplified and restated to solve for C1 and oscillator PCB stray capacitance C2 by:

CXIN + C1 * CXOUT + C2 / CXIN + C1 + C2 + CXOUT + estimated Equation 38-2.Equation 2 (In other words: Simplified Equation 1) Example:

C1 = C2 =

2 * MFG CLOAD Spec CXTAL_EFF 2 * PCB capacitance XTAL Mfg CLOAD Data Sheet Spec = 12 pF PCB XTAL trace Capacitance = 2.5 pF CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF; therefore, CXTAL_EFF = ((CXIN+CXOUT) / 2) CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF C1 = C2 = ((2 * MFG Cload spec) - CXTAL_EFF - (2 * PCB capacitance)) C1 = C2 = (24 - 5.5 - (2 * 2.5)) C1 = C2 = 13.5 pF (Always rounded down) C1 = C2 = 13 pF (in other words, for hypothetical example crystal external load capacitors) User C1 = C2 = 13 pF CLOAD (max) spec 38.10 XOSC32 AC Electrical Specifications Table 38-10. XOSC32 AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature:

-40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions(1) XOSC32_1 FOSC_XOSC32 XOSC32 oscillator XOSC32_3 CXIN32 XOSC32_5 CXOUT32 crystal frequency XOSC32 XIN32 parasitic pin capacitance XOSC32 XOUT32 parasitic pin capacitance on PIC32CX-BZ2 32.768 kHz XIN32, XOUT32 secondary oscillator 0.4 2.4 0.4 2.4 pF At the SOC pins on the Module pF At the SOC pins on the Module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1112 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature:

-40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions(1) XOSC32_11 CLOAD_X32(3) XOSC32_13 ESR_X32 XOSC32_15 TOSC32 32.768 kHz crystal load capacitance 32.768 kHz crystal ESR TOSC32 = 1/

FOSC_XOSC32 11 75 pF K 30.518 s See parameter XOSC32_1 for FOSC_XOSC32 value This includes system delay and cannot be considered as the exact start-up time of SOSC clock as it is brought out on REFOx XOSC32_17 XOSC32_ST(2) XOSC32 crystal start-

23 ms up time Figure 38-13. XOSC32 Block Diagram C1 XTAL 2 C RS N X I T U O X 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1113 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

1. 2. 3. VDDIO = VDDANA = 3.3V. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitic that is outside the scope of this specification. If this is a major concern, the customer might need to characterize this based on their design choices. The test conditions for crystal load capacitor calculation are as follows:

Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (in other words, PCB STD TRACE W

= 0.175 mm, H = 36 m, T = 113 m) Xtal PCB capacitance typical; therefore, ~= 2.5 pF for a tight PCB xtal layout For CXIN and CXOUT within 4 pF of each other, assume CXTAL_EFF = ((CXIN / 2) Note:Averaging CXIN and CXOUT will affect the final calculated CLOAD value by less than the tolerance of the capacitor selection. 4. Equation 38-3.Equation 1:

MFG CLOAD Spec =

Assuming C1 = C2 and CXin ~= CXout, the formula can be further simplified and restated to solve for C1 and oscillator PCB stray capacitance C2 by:

CXIN + C1 * CXOUT + C2 / CXIN + C1 + C2 + CXOUT + estimated Equation 38-4.Equation 2 (In other words: Simplified Equation 1) Example:

C1 = C2 =

2 * MFG CLOAD Spec CXTAL_EFF 2 * PCB capacitance XTAL Mfg CLOAD Data Sheet Spec = 12 pF PCB XTAL trace Capacitance = 2.5 pF CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF therefore CXTAL_EFF = ((CXIN / 2) CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF C1 = C2 = ((2 * MFG Cload spec) - CXTAL_EFF - (2 * PCB capacitance)) C1 = C2 = (24 - 5.5 - (2 * 2.5)) C1 = C2 = (24 - 5.5 - 5) C1 = C2 = 13.5 pF (Always rounded down) C1 = C2 = 13 pF (in other words, for hypothetical example crystal external load capacitors) User C1 = C2 = 13 pF CLOAD_X32 (max.) spec 38.11 Low Power Internal 32 kHz RC Oscillator AC Electrical Specifications Table 38-11. Low Power Internal 32 kHz RC Oscillator AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions LP32K_1 FOSC_LPRC32K Output frequency LP32K_3 LPRC32K_ACC Accuracy LP32K_9 RC32K_Duty LPRC32K OSC duty cycle 32.7 50 kHz kHz

Factory default calibration 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1114 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics 38.12 FRC AC Electrical Specifications Table 38-12. FRC AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature:

-40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions FRC1 FINTFREQ FRC2 TSUFRC Internal FRC frequency Start-up time of internal FRC FRC3 FACCU FRC accuracy FRC5 DUTY_CYCLE FRC duty cycle FRC6 C_USE FRC user tune frequency drift 8 15 50

MHz Factory calibrated and user trim bits set to zero s Not characterized FRC7 C_USER_STEP_SIZE FRC user tune

step size 38.13 Frequency AC Electrical Specifications Table 38-13. Frequency AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions MCU_1 FCY MCU frequency of operation 64 MHz VDDIO(min) to VDDIO(max) MCU_3 TCY MCU clock period 1/FCY s PLL ( Phase Locked Loop) AC Electrical Specifications 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1115 Microchip Confidential Frequency drift =

[ (Maximum frequency measured - Minimum frequency measured)/

(Default frequency of 8 MHz) ] * 100;

Maximum frequency drift possible by using the frequency trim bits Step size = (% Drift across Osc tune)/(Total number of trim bit combinations); Change in frequency with incremental trim bit Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Table 38-14. PLL MHz (Phase Locked Loop) AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions PLL_1 PLL_FIN PLL_3 PLL_FOUT PLL input frequency PLL output clock frequency PLL_4 PLL_VCO_FREQ PLL VCO frequency (Fixed) 16 96 480 MHz MHz MHz Note:

1. PLL input clock is 16 MHz XOSC. 38.14 QSPI Module Electrical Specifications Table 38-15. QSPI Module Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1) Max. Units Conditions QSPI_1 FCLK QSPI_2 FCLK QSPI_3 TSCKH QSPI_5 TSCKL QSPI_7 TSCKR QSPI_9 TSCKF QSPI_11 TCSS QSPI_13 TCSH SQI serial clock frequency SDR Host mode 0 and 2 SQI serial clock frequency SDR Host mode 1 and 3 Serial clock high time Serial clock low time Serial clock rise time Serial clock fall time CS active setup time CS active hold time QSPI_19 TDIS Data in setup time 32 MHz 32 MHz 8.9 7.8 6.9 7.6 7.3 10.4 7.4 ns ns ns ns ns ns ns 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1116 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1) Max. Units Conditions QSPI_21 TDIH Data in hold time QSPI_23 TDOH Data out hold QSPI_25 TDOV Data out valid 19.8 18 2.4 ns ns ns Note:

1. VDDIO = 3.3V, CLOAD = 30 pF (Typ.). 38.15 Power Supply DC Module Electrical Specifications Table 38-16. Power Supply DC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions REG_1 VDDCORE _CIN VDDCORE

(CLDO_OUT) input bypass parallel capacitor pair(5) 1 F REG_5 VDD33 VDD33 input bypass parallel capacitor pair(5) REG_6 PMU_VDDI O Input bypass parallel capacitor pair for the PMU power section(5) REG_7 PMU_VDD P Input bypass parallel capacitor pair for the PMU power section(5) 100 nF 10 F 100 nF 4.7 F nF 1 F nF Bulk ceramic or solid tantalum with ESR

<0.5. Min and max represent absolute values including cap tolerances Ceramic XR7/X5R with ESR <0.5 depending on temperature Bulk ceramic or solid tantalum with ESR

<0.5(6) Ceramic XR7/X5R with ESR <0.5 depending on temperature on all VDDIO pins(6) Bulk Ceramic or solid Tantalum with ESR

<0.5(6) Ceramic XR7/X5R with ESR <0.5 depending on temperature on all VDDIO pins(6) Bulk ceramic or solid tantalum with ESR

<0.5(6) Ceramic XR7/X5R with ESR <0.5 depending on temperature on all VDDIN pins(6) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1117 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Max. Units Conditions REG_9 VDDFLASH _CIN VDD_FLASH bypass parallel capacitor pair(5) REG_17 VDDANA_ CIN VDDANA input bypass parallel capacitor pair(5) VDDANA_L EXT VDDANA series ferrite bead DCR

(DC resistance) REG_18 REG_19 REG_20 BUCK_PLL _CIN REG_21 BUCK_BB_ CIN REG_22 BUCK_MP A_CIN REG_23 BUCK_LPA _CIN REG_24 BUCK_CLD O_CIN REG_25 R_EXT Ferrite bead current Rating 100 VDD bypass capacitor on the BUCK_PLL input VDD bypass capacitor on the BUCK_BB input VDD bypass capacitor on the BUCK_LPA input VDD bypass capacitor on the BUCK_MPA input VDD bypass capacitor on the BUCK_CLDO input Bias for the reference current generation Typ. 10 F 100 nF 10 F 0.1 nF Bulk ceramic or solid tantalum with ESR

<0.5(6) Ceramic XR7/X5R with ESR <0.5 depending on temperature on all VDDFLASH pins(6) Bulk ceramic or solid tantalum with ESR

<0.5(6) Ceramic XR7/X5R with ESR <0.5 1 1 1 1 1 0.1 600 at 100 MHz mA F Ceramic XR7/X5R with ESR <0.5 F Ceramic XR7 with ESR

<0.5 F Ceramic XR7 with ESR

<0.5 F Ceramic XR7 with ESR

<0.5 F Ceramic XR7 with ESR

<0.5 30 k 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1118 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. REG_27

VSW_LEXT 2,3) Buck Switch mode regulator inductor inductance Inductor DCR (DC resistance) REG_29 REG_31 REG_32 REG_32A 250 10 VSW_CAP EXT Inductor ISAT Rating(2) Buck Switch mode regulator bulk capacitor capacitance Buck Switch mode regulator filtering capacitor capacitance Typ. 4.7 Max. Units Conditions H Shielded inductor only 0.22 mA F

(7) 100 nF REG_36 VDDCORE VDDCORE 1.2 REG_37 VDD33(4) voltage range VDD33 input voltage range REG_39 VDDANA(4) VDDANA input voltage range REG_40 VDDREG VDDREG input voltage range 1.9 1.9 REG_43 SVDDIO_R VDDIO rise ramp rate to ensure internal Power-on Reset signal 3.3 3.3 1.35 0.1 3.6 3.6 V V V V V/s REG_44 SVDDIO_F VDDIO falling V/s ramp rate to ensure internal Power-on Reset signal REG_45 VP0R+

Power-on Reset 1.5 REG_45_A VP0R-

Power-on Reset 1.5 REG_47 VBOR33(4) VDDIO BOD (All 1.7 modes)(4) V V V MCU Active, cache and prefetch disabled while executing from Flash(1) PMU output voltage Failure to meet this specification may lead to start-up or unexpected behaviors Failure to meet this specification may cause the device to not detect reset VDDIO power up/Down

(See Param REG43, VDDIO Ramp Rate) VDDIO Power up/Down

(See Param REG43, VDDIO Ramp Rate) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1119 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. REG_48 VBOR12 BOR of the 1.2V regulator REG_48A VZBPOR33 Zero power BOR REG_53 TRST(6) External RESET valid active pulse width REG_54 MLDO_DE LAY REG_55 SYS_DELA Y PMU MLDO and CLDO power-up delay System delay before fetching first instruction REG_56 CLK_DELA Y Crystal start-up delay REG_57 REG_58 POWER_O N_DELAY Power-up period BOR_DELA Y Width of the BOR event Max. Units Conditions Typ. 1.0 1.8 11 V V s Minimum Reset active time to guarantee MCU Reset for the module. Reset filter circuit inside Module Minimum Reset active time to guarantee MCU Reset for SoC with no Reset filter circuit 2.5 s 260 s s XOSC_2 s 488 s s Refer to XOSC_2 parameter from the crystal oscillator section Includes system delay since this is measured with a CPU event 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1120 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-14. Power-On Reset Timing Characteristics Internal Clock Sources External Clock Sources REG54 REG55 REG57 REG54 REG55 REG57 REG56 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1121 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-15. External Reset Timing Characteristics Internal Clock Sources External Clock Sources REG53 REG58 REG57 REG55 REG57 REG55 REG56 Notes:

1. 2. Ferrite Bead ISAT(min) (IDDANA(max) * 1.15). Buck Inductor ISAT(min) ((ICAPACITOR + IVDDCORE_MAX) * 1.2) when the BUCK mode is enabled

(shielded inductor only). 3. User must select either LDO or BUCK Mode. The modes are exclusive to each other. 4. 5. VDD33 and VDDANA must be at the same voltage level. All bypass caps must be located immediately adjacent to pin(s) and on the same side of the PCB as the MCU. Each primary power supply group VDDIO, VDDANA, VDDCORE must have one bulk capacitor and all power pins with a 100 nF bypass cap. The RESET pulse width is the minimum pulse width required on the I/O pin after any filtering on the NMCLR pin. Keep the DCR as low as possible to improve efficiency. 6. 7. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1122 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics 38.16 I/O PIN AC/DC Electrical Specifications Table 38-17. I/O PIN AC/DC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1) Max. Units Conditions DI_1 VOL DI_2 VOL DI_3 VOL DI_4 VOH DI_5 VOH DI_6 VOH DI_7 VIL Output voltage low (Drive strength, 8x) Output voltage low (Drive strength, 4x) Output voltage low (Drive strength, 8x) Output voltage low (Drive strength, 4x) Output voltage low (Drive strength, 8x) Output voltage low (Drive strength, 8x) Output voltage low (Drive strength, 4x) Output voltage low (Drive strength, 8x) Output voltage low (Drive strength, 4x) Output voltage High (Drive strength, 8x) Input voltage low

(Drive strength, 8x) Input voltage low

(Drive strength, 4x) 0.1 V VDDIO = 3.3V at IOL= 10 mA 0.2 VDDIO = 3.3V at IOL= 10 mA 0.2 V 0.3 0.2 2.3 2.1 V V VDDIO = 3.3V at IOL= 13 mA VDDIO = 3.3V at IOL= 13 mA VDDIO = 3.3V at IOL= 15 mA VDDIO = 3.3V at IOH= 5 mA VDDIO = 3.3V at IOH= 5 mA 2.2 V VDDIO = 3.3V at IOH= 7 mA 2.0 VDDIO = 3.3V at IOH= 7 mA 2.1 0.7 V V VDDIO = 3.3V at IOH=

10 mA VDDIO = 3.3V 0.5 VDDIO = 3.3V 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1123 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1) Max. Units Conditions DI_8 VIH DI_13 IIL DI_15(5) RPDWN DI_17 RPUP DI_25 TRISE Input voltage high

(Drive strength, 8x) Input voltage high

(Drive strength, 4x) Input pin leakage current Internal pull-down

(Drive strength, 8x) Internal pull-down

(Drive strength, 4x) Internal pull-up

(Drive strength, 8x) Internal pull-up

(Drive strength, 4x) I/O pin rise time (High drive strength, high load) I/O pin rise time (Low drive strength, high load) I/O pin rise time (High drive strength, standard load) I/O pin rise time (Low drive strength, standard load) 2.9 V VDDIO = 3.3V 2.9 VDDIO = 3.3V 71.8 21.4 nA k VDDIO = 3.3V 3.9 k 18.6 k 3.3 k 1.97 ns VDDIO = 3.3V 10.7 ns 2.0 ns 7.6 ns 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1124 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1) Max. Units Conditions DI_27 TFALL I/O pin fall time (High drive strength, high load) I/O pin fall time (Low drive strength, high load) I/O pin fall time (High drive strength, standard load) I/O pin fall time (Low drive strength, standard load) 1.6 ns 8.1 ns 1.6 ns 5.1 ns Notes:

1. 2. 3. All measurements done at 3.3V at 25. VIL source < (GND 0.3). Characterized but not tested. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the absolute instantaneous sum of the input injection currents from all pins do not exceed the specified IICT limit. To limit the injection current, the user must insert a resistor in series RSERIES (in other words, RS), between the input source voltage and device pin. The resistor value is calculated according to:

For negative Input voltages less than (GND 0.3): RS absolute value of | ((VIL source (GND 0.3)) /

IICL) |

For positive input voltages greater than (VDDIO + 0.3): RS ((VIH source (VDDIO +0.3))/ IICH) For Vpin voltages greater than VDDIO + 0.3 and less than GND 0.3: RS = the larger of the values calculated above 4. High load = 50 pF and Standard load = 30 pF. The drive strength of pads are as follows:

5. 8x pads - PA0, PA1, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA13, PA14, PB10, PB11, PB12, PB13 4x pads - PA2, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9 38.17 I2C Module Electrical Specifications Note:Traditional Serial Communication Interface documentation uses the terminology Master and Slave. The equivalent Microchip terminology used in this document is Host and Client, respectively. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1125 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Table 38-18. I2C Module Host Mode Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions I2CM_1 TL0:SCL Host clock low time 100 kHz mode 400 kHz mode 1 MHz mode I2CM_5 TF:SCL SDAx and SCLx fall time 100 kHz mode 400 kHz mode 1 MHz mode I2CM_7 TR:SCL SDAx and SCLx rise time 100 kHz mode 400 kHz mode 1 MHz mode I2CM_9 TSU:DAT Data input setup time 100 kHz mode 400 kHz mode 1 MHz mode I2CM_11 THD:DAT Data input hold time 100 kHz mode 400 kHz mode 1 MHz mode 5020 1280 712 19 5 5 166 154 154 4900 1200 592 159 93 140 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDDIOx = 3.3V, VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pf VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1126 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions I2CM_13 TSU:STA Start condition setup time I2CM_15 THD:STA Start condition hold time I2CM_21 TAA:SCL Output valid from clock I2CM_23 TBF:SDA Bus free time(1) 100 kHz mode 400 kHz mode 1 MHz mode 100 kHz mode 400 kHz mode 1 MHz mode 100 kHz mode 400 kHz mode 1 MHz mode 100 kHz mode 400 kHz mode 1 MHz mode 5180 1450 867 4990 1250 666 TL0:SC L TL0:SC L TL0:SC L s ns ns s s s ns ns ns ns ns ns VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF Note:

1. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1127 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-16. I2C Start/Stop Bits Host Mode AC Timing Diagram Figure 38-17. I2C Bus Data Host Mode AC Timing Diagram Table 38-19. I2C Module Client Mode Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions I2CS_5 TF:SCL SDAx and SCLx fall time 100 kHz mode 400 kHz mode 1 MHz mode I2CS_7 TR:SCL SDAx and SCLx rise time 100 kHz mode 400 kHz mode 1 MHz mode 19 5 5 166 154 154 ns ns ns ns ns ns VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1128 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions I2CS_9 TSU:DAT Data input setup time 100 kHz mode 400 kHz mode 1 MHz mode I2CS_11 THD:DAT Data input hold time 100 kHz mode 400 kHz mode 1 MHz mode 5580 1470 490 490 ns ns ns ns ns s VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF VDDIOx = 3.3V, IPULL-

UP = 3 mA, CLOAD =

400 pF VDDIOx = 3.3V, IPULL-

UP = 20 mA, CLOAD =

550 pF Note:

1. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition). Figure 38-18. I2C Start/Stop Bits Client Mode AC Timing Diagram 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1129 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-19. I2C Bus Data Client Mode AC Timing Diagram 38.18 SPI Module Electrical Specifications Note:Traditional Serial Communication Interface documentation uses the terminology Master and Slave. The equivalent Microchip terminology used in this document is Host and Client, respectively. Table 38-20. SPI Module Host Mode Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions MSP_1 FSCK SCK frequency MSP_3 TSCL MSP_5 TSCH MSP_7 TSCF MSP_9 TSCR MSP_11 TMOV MSP_13 TMOH MSP_15 TMIS SCK output low time SCK output high time SCK and MOSI output fall time SCK and MOSI output rise time MOSI Data output valid after SCK MOSI hold after SCK MISO setup time of data input to SCK 32 24 31.2 31.2 1.8 1.8 11 15 23 MHz Fixed pins Remappable pins See parameter DI27 I/O spec See parameter DI25 I/O spec VDDIOx (Min.), CLOAD =

30 pF (Typ.) ns ns ns ns ns ns ns MSP_17 TMIH MISO hold time of data input to SCK 8 ns 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1130 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-20. SPI Host Module CPHA=0 Timing Diagrams SCK CPOL=0 SCK CPOL=1 MISO

(Mstr Data In MOSI

(Mstr Data Out SP1 SP5 SP9 SP7 SP13 SP17 SP15 MSB SP11 SP3 LSB MSB LSB Figure 38-21. SPI Host Module CPHA=1 Timing Diagrams SP1 SP5 SP9 SP7 SCK CPOL=0 SCK CPOL=1 MISO

(Mstr Data In MOSI

(Mstr Data Out SP15 SP17 SP3 MSB MSB SP11 SP13 LSB LSB Note:

1. Assumes VDDIOx(min) and 30 pF external load on all SPIx pins unless otherwise noted. Table 38-21. SPI Module Client Mode Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. SSP_1 FSCK SCK frequency Typ 16 Max. Units Conditions 16 MHz VDDIOx = 1.9V or VDDIO(min) whichever is greater, CLOAD = 30 pF

(Min) fixed pins Remappable pins SSP_3 TSCL SCK output low time 12 62.5 12 ns 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1131 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. SSP_5 TSCH SSP_7 TSCF SSP_9 TSCR SSP_11 TSOV SSP_15 TSIS SCK output high time SCK and MOSI output fall time SCK and MOSI output rise time MOSI data output valid after SCK MISO setup time of data input to SCK Typ 62.5 3 26 21 23 Max. Units Conditions ns ns ns ns ns See parameter DI27 I/O spec See parameter DI25 I/O spec VDDIOx = 3.3V, CLOAD

= 30 pF (Min) SSP_17 TSIH MISO hold time of data input to SCK 22 ns Figure 38-22. SPI Client Module CPHA=0 Timing Diagrams SP1 SP5 SP9 SP7 SCK CPOL=0 SCK CPOL=1 MISO

(Mstr Data In MOSI

(Mstr Data Out SP19 __ SS SP15 MSB SP17 SP11 SP3 LSB MSB LSB SP13 SP21 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1132 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-23. SPI Client Module CPHA=1 Timing Diagrams SP1 SP5 SP9 SP7 SCK CPOL=0 SCK CPOL=1 MISO

(Mstr Data In MOSI

(Mstr Data Out SP11 __ SS SP15 SP17 SP3 MSB MSB SP19 SP13 LSB LSB SP21 38.19 ADC Electrical Specifications Table 38-22. ADC AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions Device Supply ADC_1 VDDANA ADC supply VDDANA(min) Reference Inputs ADC_3 VREF

(6) ADC reference voltage(4) Analog Input Range ADC_7 AFS ADC_9 Full-scale analog input signal range

(Single-ended) Full-scale analog input signal range

(Differential) 0 VDDANA/2 VDDANA(max) VDDANA VDDANA VDDANA/2 V V V V VDDIO = VDDANA External reference voltage VREF =

VDDANA(max) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1133 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Table 38-23. ADC Single-Ended Mode AC Electrical Specifications AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions Single-Ended Mode ADC Accuracy SADC_11 Res Resolution 6 12 bits SADC_13 EN0B(3) Effective number of bits 9.3 bits SADC_19 INL(3) Integral non linearity

-5.2 LSb SADC_25 DNL(3) Differential non linearity -1 LSb 2.7 SADC_31 GERR(3) Gain error

-0.7 LSb 1.8 SADC_37 E0FF(3) Offset error 3.2 LSb Single-Ended Mode ADC Dynamic Performance SADC_49 SINAD(1,2,3) Signal to noise and 57.8 dB distortion SADC_51 SNR(1,2,3)) Signal to noise ratio 58.2 SADC_53 SFDR(1,2,3) Spurious free dynamic 66.2 range SADC_55 THD(1,2,3,5) Total harmonic

-71.3 distortion Selectable 6, 8, 10, 12 bit resolution ranges 1.6 Msps, Internal VREF, VDDANA =

VDDIO = 3.3V 1.6 Msps, Internal VREF, VDDANA =

VDDIO = 3.3V 1.6 Msps, Internal VREF, VDDANA =

VDDIO = 3.3V 1.6 Msps, Internal VREF, VDDANA =

VDDIO = 3.3V Internal VREF, VDDANA = VDDIO =

3.3V VREF = VDDANA = VDDIO = 3.3V at 12-bit resolution, max sampling rate(1,2) Notes:

1. Characterized with an analog input sine wave = (FTP(maximum)/100). Example: FTP(maxium) = 1 Msps/100 2. 3.

= 10 KHz sine wave. Sinewave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution. Spec values collected under the following additional conditions:

a. b. ADC Measurements done with 3.3V VREF Voltage. 4. 5. Value taken over 7 harmonics. 6. Referred to as AVDD in the pinout. 12-bit resolution mode. All registers at reset default value otherwise not mentioned. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1134 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Table 38-24. ADC Conversion AC Electrical Requirements AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V

(unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ. Max. Units Conditions ADC_ Clock Requirements ADC_57 TAD ADC clock period 20.8 ns ADC Single-Ended Throughput Rates ADC_59 FTPR

(Single-

ended Mode) Throughput rate(2)

(Single-ended) 2 0.7 Msps VREF = VDDANA =

3.3V 12-bit resolution, DIV_SHR = 2 12-bit resolution, DIV_SHR = 4 Notes:

1. Conversion_time = (SAMC_SHR+15)*TAD. 2. FTPR = 1/(( SAMC_SHR + Resolution + 1 ) * ( 1/( ControlClk/DIV_SHR ))). Table 38-25. ADC Sample AC Electrical Requirements AC Characteristics Param. No. Symbol ADC_65 TCNV ADC_67 Characteristic s Conversion time(1) (Single-

ended Mode) Conversion time(1)

(Differential Mode) Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Min. Typ. Max. Units Conditions 14 12 10 14 12 10 TAD 12-bit resolution 10-bit resolution 8-bit resolution TAD 12-bit resolution 10-bit resolution 8-bit resolution ADC_69 CSAMPLE ADC internal sample cap ADC_71 RSAMPLE ADC internal 5 200 pf impedance Note:

1. ADC Throughput Rate FTP = ((1/((TSAMP + TCNV) * TAD))/(# of user active analog inputs in use on specific target ADC module)). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1135 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics 38.20 Bluetooth Low Energy RF Characteristics Table 38-26. Bluetooth Low Energy RF Characteristics AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ(1) Max. Units Conditions 2400 2480 MHz BTG1 FREQ BTTX1 TXPWR:MPA BTTX2 TXPWR:LPA BTX3 TXIB:1MBPS BTX4 TXIB:2MBPS BTRX1 RXSENSE BTRX2 MAXINSIG Frequency range of operation Bluetooth transmit power MPA Bluetooth transmit power LPA In-band emission for FTX -2 MHz In-band emission for FTX -(3+N) MHz In-band emission for FTX -4 MHz In-band emission for FTX -5 MHz In-band emission for FTX -(6+N) MHz Receiver sensitivity at 1 Mbps Receiver sensitivity at 2 Mbps Receiver sensitivity at 500 kbps Receiver sensitivity at 125 kbps Maximum input signal level at 1 Mbps Maximum input signal level at 2 Mbps Maximum input signal level at 500 kbps Maximum input signal level at 125 kbps

(1)

(5)

(5)

(5) 11.5 4.0

-32

-45

-43

-48

-51 dBm dBm dBm dBm dBm dBm dBm

-95.5 dBm

-92.5 dBm

-98.5 dBm

-102 0 0 0 0 dBm dBm dBm dBm dBm 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1136 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ(1) Max. Units Conditions BTRX3(4) CI1M:COCH CI1M: -1 MHz CI1M: -2 MHz CI1M:ADJ(3+n) CI1M:IMG C/I Co channel rejection C/I adjacent channel rejection C/I adjacent channel rejection C/I alternate channel rejection C/I image frequency rejection CI1M:IMG -1 MHz C/I adjacent channel to image freq rejection BTRX4(4) CIS2:COCH CIS2: -1 MHz CIS2: -2 MHz CIS2:ADJ(3+n) CIS2:IMG C/I Co channel rejection C/I adjacent channel rejection C/I adjacent channel rejection C/I alternate channel rejection C/I image frequency rejection CIS2:IMG -1 MHz C/I adjacent channel to image freq rejection BTRX5(4) CIS8:COCH CIS8: -1 MHz CIS8: -2 MHz CIS8:ADJ(3+n) CIS8:IMG C/I Co channel rejection C/I adjacent channel rejection C/I adjacent channel rejection C/I alternate channel rejection C/I image frequency rejection CIS2:IMG -1 MHz C/I adjacent channel to image freq rejection 13 13 13 15 15 14 11 17 18 17 14 18 6 13 13 14 8 16 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1137 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ(1) Max. Units Conditions BTRX6(4) CI2M:COCH CI2M: -2 MHz CI2M: -4 MHz CI2M:ADJ(6+2n) CI2M:IMG CI2M:IMG -2 MHz BTRX7(4) BLOCK1M:<2 GHZ C/I Co channel rejection C/I adjacent channel rejection C/I adjacent channel rejection C/I alternate channel rejection C/I image frequency rejection C/I adjacent channel to image freq rejection Blocking performance from 30-2 GHz BLOCK1M:2 GHZ<SIG<2399 MHz Blocking performance from 2003-2399 MHz BLOCK1M:2484 MHZ<SIG<2977 MHz Blocking performance between 2484-2997 MHz BLOCK1M:3 GHZ<SIG<12.75 GHz Blocking performance between 3-12.5 GHz BTRX8(4) BLE1M:INTERMOD BLE2M:INTERMOD Inter modulation performance for BLEM Inter modulation performance for BLEM 13 16 19 16 13 19 20 14 20 20 13.5 19.5 dB dB dB dB dB dB dB dB dB dB dB dB Notes:

1. Measured at 25, averaged across all voltages and channels. 2. Measured on a board with the reference schematic. 3. 4. 5. All measurement across voltage based on the SIG specifications. The specified value is the limit above the SIG specifications. PDU length = 37, channels = 2402/2426/2440/2480 MHz. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1138 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Table 38-27. Bluetooth Low Energy RF Current Characteristics AC Characteristics Param. No. Symbol Characteristics RF Power CPU Frequency Standard Operating Conditions: VDDIO

= VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Min. Typ. Max. Units Conditions IBLETX1 IDDTXMPA IBLETX2 IBLETX3 IBLETX4 IBLETX5 IBLETX6 IBLETX7 IDDTXLPA IBLETX8 IBLETX9 IBLETX10 IBLETX11 IBLETX12 IBLETX7 IDDTXLPA0 IBLETX8 IBLETX9 IBLETX10 IBLETX11 IBLETX12 Current consumption with output power in DC-

DC mode 1 Mbps Current consumption at +12 dBm output power in MLDO mode

+12 dBm

+12 dBm

+12 dBm

+12 dBm

+12 dBm

+12 dBm 64 MHz 42.8 mA 32 MHz 40.5 mA 8 MHz 39.0 mA 64 MHz 96.7 mA 32 MHz 91.8 mA 8 MHz 88.1 mA Current consumption at +4 dBm output power in DC-DC mode 1 Mbps Current consumption at +4 dBm output power in MLDO mode Current consumption at +0 dBm output power in DC-DC mode 1 Mbps Current consumption at 0 dBm output power in MLDO mode 4 dBm 64 MHz 4 dBm 32 MHz 4 dBm 8 MHz 4 dBm 64 MHz 4 dBm 32 MHz 4 dBm 8 MHz 0 dBm 64 MHz 0 dBm 32 MHz 0 dBm 8 MHz 0 dBm 64 MHz 0 dBm 32 MHz 0 dBm 8 MHz 24.9 22.9 21.1 55.5 48.7 45.8 22.7 20.9 18.2 47.6 43.0 39.7 mA mA mA mA mA mA mA mA mA mA mA mA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1139 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics

...........continued AC Characteristics Param. No. Symbol Characteristics RF Power CPU Frequency Standard Operating Conditions: VDDIO

= VDDANA 1.9-3.6V (unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Min. Typ. Max. Units Conditions IBLERX1 IDDRXBLE1M Current consumption at RX signal level -80 dBm in DC-DC mode Current consumption at RX signal level -80 dBm in MLDO mode IBLERX2 IBLERX3 IBLERX4 IBLERX5 IBLERX6 Notes:

-80 dBm

-80 dBm

-80 dBm

-80 dBm

-80 dBm

-80 dBm 64 MHz 20.6 mA 32 MHz 18.2 mA 8 MHz 16.5 mA 64 MHz 40.6 mA 32 MHz 35.1 mA 8 MHz 30.9 mA Current consumption is measured on a board based upon the Microchip Technology Reference Design. Current consumption is for the entire SoC (including the MCU), measured at the input power rail. Current consumption is measured using HUT code. Current reported is the average of the current during the transmit or receive burst (exclude off cycle of the transmit/receive operation). Figure 38-24. Module Bluetooth Low Energy Receive Sensitivity vs Temperature

) m B d

l e v e l y t i v i t i s n e S

-50

-60

-70

-80

-90

-100

-110

-40 25 Temperature (C) 85 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1140 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

Bluetooth Low Energy receive sensitivity is measured across temperature at 3.6V, 2440 MHz, uncoded data at 1 Ms/s. PDU length = 37. Sensitivity is measured according to the SIG specifications. Figure 38-25. Module Bluetooth Low Energy Receive Sensitivity vs Frequency

-50

-60

-70

-80

-90

-100

) m B d

l e v e l y t i v i t i s n e S

-110 Notes:

2 0 4 2 6 0 4 2 0 1 4 2 4 1 4 2 8 1 4 2 2 2 4 2 6 2 4 2 0 3 4 2 4 3 4 2 8 3 4 2 2 4 4 2 6 4 4 2 0 5 4 2 4 5 4 2 8 5 4 2 2 6 4 2 6 6 4 2 0 7 4 2 4 7 4 2 8 7 4 2 Frequency (MHz) Bluetooth Low Energy sensitivity is measured across channels at 3.6V at 25, uncoded data at 1 Ms/s. PDU length = 37. Sensitivity is measured according to the SIG specifications. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1141 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-26. Bluetooth Low Energy 1M CI Margin 25 20 15 10 5 0

) B d

n i g r a M Notes:

0 0 4 2 4 0 4 2 8 0 4 2 2 1 4 2 6 1 4 2 0 2 4 2 4 2 4 2 8 2 4 2 2 3 4 2 6 3 4 2 0 4 4 2 4 4 4 2 8 4 4 2 2 5 4 2 6 5 4 2 0 6 4 2 4 6 4 2 8 6 4 2 2 7 4 2 6 7 4 2 0 8 4 2 Frequency (MHz) Bluetooth Low Energy 1M C/I Margin is measured at 2440 MHz at 25, 3.6V, uncoded data at 1 Ms/s. C/I test is done with HUT code based on the SIG specifications. Reported C/I margin is the margin above the C/I specifications from SIG. Figure 38-27. Bluetooth Low Energy Receive Sensitivity vs Voltage

) m B d

l e v e l y t i v i t i s n e S

-50

-60

-70

-80

-90

-100

-110 1.9 2.3 2.6 3.6 Supply Voltage (V) Notes:

Bluetooth Low Energy receive sensitivity is measured at 2440 MHz at 25, uncoded data at 1 Ms/s. PDU length = 37. Sensitivity is measured according to the SIG specifications. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1142 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-28. Bluetooth Low Energy Receive Sensitivity vs Temperature

) m B d

l e v e L y t i v i t i s n e S

-50

-60

-70

-80

-90

-100

-110 Notes:

-40 25 Temperature (C) 125 U Bluetooth Low Energy receive sensitivity is measured across channels at 3.6V, 2440 MHz, uncoded data at 1 Ms/s. PDU length = 37. Sensitivity is measured according to the SIG specifications. Figure 38-29. Bluetooth Low Energy Receive Sensitivity vs Frequency

-50

-60

-70

-80

-90

) m B d

l e v e l y t i v i t i s n e S

-100

-110 2 0 4 2 6 0 4 2 0 1 4 2 4 1 4 2 8 1 4 2 2 2 4 2 6 2 4 2 0 3 4 2 4 3 4 2 8 3 4 2 2 4 4 2 6 4 4 2 0 5 4 2 4 5 4 2 8 5 4 2 2 6 4 2 6 6 4 2 0 7 4 2 4 7 4 2 8 7 4 2 Frequency (MHz) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1143 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

Bluetooth Low Energy receiver sensitivity is measured across channels at 3.6V at 25, uncoded data at 1 Ms/s. PDU length = 37. Sensitivity is measured according to the SIG specifications. Figure 38-30. Bluetooth Low Energy Receive Current vs Temperature A m n i t n e r r u C 30 25 20 15 10 5 0 Notes:

0 4

5 3

5 2

5 1

5 5

5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 0 1 5 1 1 5 2 1 Temperature (C) Bluetooth Low Energy receive current is measured at 3.3V (Buck mode), uncoded data at 1 Ms/s with LNA configured at maximum gain. PDU length = 37. Current is measured on input power rail to SoC (includes processor current as well). Current is measured with HUT code. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1144 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-31. Bluetooth Low Energy Transmit Power vs Frequency

) m B d

l e v e L r e w o P 14 12 10 8 6 4 2 0 Notes:

2 0 4 2 6 0 4 2 0 1 4 2 4 1 4 2 8 1 4 2 2 2 4 2 6 2 4 2 0 3 4 2 4 3 4 2 8 3 4 2 2 4 4 2 6 4 4 2 0 5 4 2 4 5 4 2 8 5 4 2 2 6 4 2 6 6 4 2 0 7 4 2 4 7 4 2 8 7 4 2 Frequency (MHz) Bluetooth Low Energy transmit power is measured across frequency after transmit power calibration at 3.3V

(Buck mode). Transmit power is measured with HUT code. Transmit power is measured after the PA matching and LPF. Figure 38-32. Bluetooth Low Energy Transmit Power vs Transmit Power Level 14 10 6 2

-2

-6

-10

-14

-18

-22

-26

-30

-34

) m B d

r e w o p x T 12 11 10 9 8 7 6 5 4 2 0

-5 -10 -16 -22 -29 BLE Tx Power Level 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1145 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

Bluetooth Low Energy transmit power is measured at 2440 MHz after transmit power calibration. Transmit power is measured on board based on Microchip Technology Reference Design. Transmit power is measured after PA match and LPF. Transmit power is measured with HUT code. Transmit power is controlled by transmit power settings on HUT code for measurement. Figure 38-33. Bluetooth Low Energy Transmit Power vs VDD Supply Voltage 14 12 10 8 6 4 2 0

) m B d

r e w o p x T Notes:

1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 Voltage (V) n Bluetooth Low Energy transmit power is measured across voltage after transmit power calibration. Transmit power is measured after calibration at +12 dBm ( 0.5 dBm). Transmit power is measured on board based on the Microchip Reference Design. Transmit power is measured after the LPA and PA match section. Transmit power is measured with HUT code. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1146 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-34. Bluetooth Low Energy Transmit Power vs. Temperature 10

) m B d

r e w o p x T 5 0 Notes:

0 4

5 3

5 2

5 1

5 5

5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 Temperature (C) 5 0 1 5 1 1 5 2 1 Bluetooth Low Energy transmit power is measured across temperature after transmit power calibration at 3.6V and 2440 MHz. Transmit power is measured with HUT code. Temperature power compensation is triggered before power measurement. Transmit power is measured after the PA matching and LPF. Figure 38-35. Bluetooth Low Energy Transmit Current vs Temperature 100 90 80 70 60 50 40 30 20 10 0 A m n i t n e r r u C 0 4

5 3

5 2

5 1

5 5

5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 Temperature (C) 5 0 1 5 1 1 5 2 1 Notes:

Bluetooth Low Energy transmit current is measured at 3.3V (Buck mode) at 2440 MHz across temperature. Transmit current is measured after calibration at +12 dBm ( 0.5 dBm). Current is measured on input power rail to SoC. Current is measured with HUT code. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1147 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics 38.21 Zigbee RF Characteristics Table 38-28. Zigbee RF Characteristics AC Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature:

-40C TA +85C for Industrial Temp Symbol Characteristics Min. Typ.(1,2) Max. Units Conditions Param. No. ZBG1 ZBG2 ZBG3 FREQ FCH PSDU ZBT1 TXOPMPA ZBT2 TXOPLPA Frequency range 2405 Channel spacing Bit rate Transmit output power MPA Transmit output power LPA ZBT3 POWERRANGE Output power range ZBT4 EVM ZBRX1 SENS250 SENS500 SENS1M SENS2M Error vector magnitude Receiver sensitivity in 250 kbps Receiver sensitivity in 500 kbps Receiver sensitivity in 1 Mbps Receiver sensitivity in 2 Mbps ZBRX2 PMAX Maximum input level ZBRX3(3) PACRP ZBRX4(3) PACRN ZBRX5(3) PALRP ZBRX6(3) PALRN ZBRX7 LOLEAKLPA ZBRX7A LOLEAKMPA Adjacent channel rejection +5 MHz Adjacent channel rejection -5 MHz Alternate channel rejection +10 MHz Alternate channel rejection -10 MHz LO leakage on LPA mode LO leakage on MPA mode 5 250, 500, 1000, 2000 11.5 4.0 26 10

-99

-96

-94

-88 0 35 31 17 17

-34

-28 2480 MHz MHz kbps dBm dBm dB

%RMS dBm dBm dBm dBm dBm dB dB dB dB dB dB

(4)

(4) TX power on ZB power levels from (-14 to 12 dBm)

(6)

(5)

(5) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1148 Microchip Confidential Confidential...........continued AC Characteristics PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Standard Operating Conditions: VDDIO = VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature:

-40C TA +85C for Industrial Temp Param. No. Symbol Characteristics Min. Typ.(1,2) Max. Units Conditions ZBRX8 RSSIRANGE Dynamic range of RSSI 40 dB Notes:

Specified value is the margin above the 802.15.4 standard limits. 1. Measured on a board based on the Microchip Technology reference design. 2. Measured across channels at 3.3V and according to the 802.15.4 standard specifications. 3. 4. Measured across channels and voltages. 5. 6. LO leakage on LPA mode, measured across voltage. All results are based on measurement conditions as per the 802.15.4 standards. Table 38-29. Zigbee RF Current Characteristics AC Characteristics Param. No. Symbol Characteristics CPU Frequency IZBTX1 IDDTXMPA IZBTX2 IBLETX3 IZBTX4 IZBTX5 IZBTX6 IZBTX7 IDDTXLPA IZBTX8 IZBTX9 IZBTX10 IZBTX11 IZBTX12 IZBRX1 IDDRXZB IZBRX2 IZBRX3 IZBRX4 IZBRX5 IZBRX6 Current consumption at

+12 dBm output power in DC-DC mode 250 kbps Current consumption at

+12 dBm output power in MLDO mode Current consumption at

+4 dBm output power in DC-DC mode 250 kbps Current consumption at

+4 dBm output power in MLDO mode Current consumption at RX signal level -95 dBm in DC-DC mode Current consumption at RX signal level -95 dBm in MLDO mode 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz Standard Operating Conditions: VDDIO =

VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Min. Typ. Max. Units Conditions 43.3 41.3 39.9 96.4 92.1 89.0 27.3 24.9 22.7 51.7 47.6 45.0 19.4 17.4 15 38.5 33.5 30.3 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1149 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics

...........continued AC Characteristics Symbol Characteristics IDDRXZBRPC Current consumption at RX signal level -95 dBm in DC-DC mode Current consumption at RX signal level -95 dBm in MLDO mode CPU Frequency 64 MHz 32 MHz 8 MHz 64 MHz 32 MHz 8 MHz Param. No. IZBRX1 IZBRX2 IZBRX3 IZBRX4 IZBRX5 IZBRX6 Notes:

Standard Operating Conditions: VDDIO =

VDDANA 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40C TA

+85C for Industrial Temp Min. Typ. Max. Units Conditions 13.6 11.3 9.8 29 24.2 20.7 mA mA mA mA mA mA Current consumption is measured on a board based upon the Microchip Technology Reference Design. Current consumption is for the entire SoC (including the MCU). Current consumption is measured using the HUT code. Current reported is the average of the current during the transmit burst (exclude off cycle of the transmission). Figure 38-36. Module Zigbee Receive Sensitivity vs. Temperature

-50

-60

-70

-80

-90

) m B d

l e v e l y t i v i t i s n e S

-100

-110 Notes:

-40 25 Temperature (C) 85 Receiver sensitivity is measured based on the 802.15.4 specifications. Receiver sensitivity is measured at 2440 MHz at 3.6V, 250 kbps. Measured after receiver calibration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1150 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-37. Module Zigbee Receive Sensitivity vs. Frequency

-50

-60

-70

-80

-90

) m B d

l e v e l y t i v i t i s n e S

-100

-110 5 0 4 2 0 1 4 2 5 1 4 2 0 2 4 2 5 2 4 2 0 3 4 2 5 0 3 4 4 4 2 2 Frequency (MHz) 5 4 4 2 0 5 4 2 5 5 4 2 0 6 4 2 5 6 4 2 0 7 4 2 5 7 4 2 0 8 4 2 Notes:

RX sensitivity across channels is measured at 3.6V at 25, 250 kbps. Sensitivity is measured according to the 802.15.4 specifications. Figure 38-38. Zigbee TX Setting vs. Measurement Power 14 10 6 2

-2

-6

-10

-14

) m B d

r e w o P t n e m e r u s a e M

-18 Notes:

0 1 2 3 5 4 6 Zigbee Tx Power Level 8 7 9 10 11 12 13 14 15 Transmit power is measured after calibration. Transmit power is measured across power levels at 2440 MHz at 3.6V, 25. Transmit power is measured after the PA matching and LPF. Transmit power is configured using the transmit power setting in HUT code. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1151 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-39. Zigbee ACR +-5M Margin 40 35 30 25 20 15 10 5 0

) B d

n i g r a M Notes:

2420 2470 2420 2470

-5 5

-freq offset/+freq offset (MHz)/co-channel Adjacent channel rejection is measured at 3.6V at 25, 250 kbps. Measured based on the 802.15.4 adjacent channel relative jamming specification. Margin specified is the margin above the 802.15.4 specifications. Measured after receiver calibration. Figure 38-40. Zigbee ACR +-10M Margin 40 35 30 25 20 15 10 5 0

) B d

n i g r a M Notes:

2420 2470 2420 2470

-5 5

-freq offset/+freq offset (MHz)/co-channel Adjacent channel rejection is measured at 3.6V at 25, 250 kbps. Measured based on the 802.15.4 adjacent channel relative jamming specification. Margin specified is the margin above the 802.15.4 specifications. Measured after receiver calibration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1152 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-41. Zigbee Receive Sensitivity vs. Temperature

-50

-60

-70

-80

-90

-100

) m B d

l e v e l y t i v i t i s n e S

-110 Notes:

-40 25 125 Temperature (C) Receiver sensitivity is measured based on the 802.15.4 specifications. Sensitivity measured at 3.6V, 25 on 2440 MHz across temperature, 250 kbps. Measured after receiver calibration. Figure 38-42. Zigbee Receive Sensitivity vs. Frequency

-50

-60

-70

-80

-90

) m B d

l e v e l y t i v i t i s n e S

-100

-110 Notes:

5 0 4 2 0 1 4 2 5 1 4 2 0 2 4 2 5 2 4 2 0 3 4 2 5 3 4 2 0 4 4 2 5 4 4 2 0 5 4 2 5 5 4 2 0 6 4 2 5 6 4 2 0 7 4 2 5 7 4 2 0 8 4 2 Frequency (MHz) RX sensitivity is measured across channels at 3.6V at 25, 250 kbps. Sensitivity is measured according to the 802.15.4 specifications. Sensitivity is measured after RX calibration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1153 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-43. Zigbee Receive Sensitivity vs. VDD Supply Voltage

-50

-60

-70

-80

-90

-100

) m B d

l e v e l y t i v i t i s n e S

-110 Notes:

1.9 2.3 Supply Voltage (V) 2.6 3.6 RX sensitivity is measured at 2440 MHz at 25 across voltage, 250 kbps. Sensitivity is measured according to the 802.15.4 specifications. Sensitivity is measured after RX calibration. Figure 38-44. Zigbee Receive Current vs. Temperature A m n i t n e r r u C 50 45 40 35 30 25 20 15 10 5 0 Notes:

0 4

5 3

5 2

5 1

5 5

5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 Temperature (C) 5 0 1 5 1 1 5 2 1 Receiver operating at 2440 MHz, 3.3V, 25 at maximum LNA gain. Measured after receiver calibration. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1154 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Figure 38-45. Zigbee Transmit Power vs Frequency

) m B d

r e w o P t i m s n a r T 14 12 10 8 6 4 2 0 Notes:

5 0 4 2 0 1 4 2 5 1 4 2 0 2 4 2 5 2 4 2 0 3 4 2 5 4 4 2 0 4 4 2 5 3 4 2 Frequency (MHz) 0 5 4 2 5 5 4 2 0 6 4 2 5 6 4 2 0 7 4 2 5 7 4 2 0 8 4 2 Transmit power is measured after calibration. Transmit power is measured across the channels at 3.6V at 25. Transmit power is measured after the PA matching and LPF. Figure 38-46. Zigbee Transmit Power vs Temperature 14 12 10

) m B d

r e w o P x T 8 6 4 2 0

-40 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (C) 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1155 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

Transmit power is measured after calibration. Transmit power is measured at 2440 MHz at 3.6V across temperature. Transmit power is measured after the PA matching and LPF. Transmit power compensation is triggered before measurement across temperature. Figure 38-47. Zigbee Transmit Power vs. VDD Supply Voltage 14 12 10 8 6 4 2 0

) m B d

r e w o P x T Notes:

1.9 2.1 2.3 2.5 2.7 Voltage (V) 2.9 3.1 3.3 3.5 Transmit power is measured after calibration. Transmit power is measured across voltage at 2440 MHz and 25. Transmit power is measured on reference board after the PA matching and LPF. Transmit power is configured using transmit power setting in HUT code. Figure 38-48. Zigbee Transmit Current vs. Temperature A m n i t n e r r u C 100 90 80 70 60 50 40 30 20 10 0 0 4

5 3

5 2

5 1

5 5

5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 Temperature (C) 5 0 1 5 1 1 5 2 1 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1156 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Electrical Characteristics Notes:

Transmit current is measured at input to SoC (includes SoC power consumption). Transmit current is measured at 2440 MHz at 3.3V (Buck mode). Transmit power is calibrated to +12 dBm ( 0.5 dBm on MPA mode). 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1157 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 39. Packaging Information This chapter provides information on package markings, dimension and footprint of the PIC32CX-BZ3 and the WBZ35x family. 39.1 PIC32CX-BZ3 SoC Packaging Information For the most current package drawings, see the Microchip Packaging Specification located at www.microchip.com/

en-us/support/package-drawings. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1158 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1159 Microchip Confidential BA0.10C0.10C0.10CAB0.05CC2XTOP VIEWSIDE VIEWBOTTOM VIEW12N0.10CAB0.10CAB0.10C0.08CSheet 1 of 22X48XNote:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging48-Lead Very Thin Plastic Quad Flat, No Lead Package (ZWX) - 6x6x0.9 mm Body [VQFN]With 4.20 mm Exposed Pad and Stepped Wettable Flanks 2021 Microchip Technology Inc.Microchip Technology Drawing C04-531 Rev BSECTION AAAANOTE1(DATUM B)(DATUM A)NOTE 1SEATINGPLANEDED2E2(K)e48X bLe2A(A3)AD3A412NSEEDETAIL BConfidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1160 Microchip Confidential For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: 2021 Microchip Technology Inc.REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.Notes:1.2.3.Pin 1 visual index feature may vary, but must be located within the hatched area.Package is saw singulatedDimensioning and tolerancing per ASME Y14.5MSheet 2 of 2Wettable Flank Step Cut LengthD3A4Wettable Flank Step Cut HeightNumber of TerminalsOverall HeightTerminal WidthOverall WidthTerminal LengthExposed Pad WidthTerminal ThicknessPitchStandoffUnitsDimension LimitsA1AbE2A3eLEN0.40 BSC0.203 REF0.350.150.800.000.200.400.850.026.00 BSCMILLIMETERSMINNOM480.450.250.900.05MAXK0.50 REFTerminal-to-Exposed-PadOverall LengthExposed Pad LengthDD24.106.00 BSC4.204.304.104.204.30--0.085-0.100.1948-Lead Very Thin Plastic Quad Flat, No Lead Package (ZWX) - 6x6x0.9 mm Body [VQFN]With 4.20 mm Exposed Pad and Stepped Wettable FlanksMicrochip Technology Drawing C04-531 Rev BDETAIL BALTERNATE TERMINALCONFIGURATION48X bLConfidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1161 Microchip Confidential RECOMMENDED LAND PATTERNDimension LimitsUnitsC2Center Pad WidthContact Pad SpacingCenter Pad LengthContact PitchY2X24.304.30MILLIMETERS0.40 BSCMINEMAX5.90Contact Pad Length (Xnn)Contact Pad Width (Xnn)Y1X10.850.20NOM1248C1Contact Pad Spacing5.90Contact Pad to Contact Pad (Xnn)G20.20Thermal Via DiameterVThermal Via PitchEV0.331.20BSC: Basic Dimension. Theoretically exact value shown without tolerances.Notes:Dimensioning and tolerancing per ASME Y14.5MFor best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss duringreflow process1.2.For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: 2021 Microchip Technology Inc.Contact Pad to Center Pad (Xnn)G10.38Microchip Technology Drawing C04-2531 Rev BC1EVC2EVY2X2X1Y1G1G2VSILK SCREENE48-Lead Very Thin Plastic Quad Flat, No Lead Package (ZWX) - 6x6x0.9 mm Body [VQFN]With 4.20 mm Exposed Pad and Stepped Wettable FlanksConfidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1162 Microchip Confidential BA0.10C0.10C0.10CAB0.05C(DATUM B)(DATUM A)CSEATINGPLANENOTE 112N2XTOP VIEWSIDE VIEWBOTTOM VIEWNOTE 112N0.10CAB0.10CAB0.10C0.08CMicrochip Technology Drawing C04-21391 Rev G Sheet 1 of 22X32XFor the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote:32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN] 2022 Microchip Technology Inc.DEe32X bE2D2e2LAA1With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS(A3)AADETAIL AA4D3SECTION AAPARTIALLYPLATEDKConfidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1163 Microchip Confidential Microchip Technology Drawing C04-21391 Rev G Sheet 2 of 2REF: Reference Dimension, usually without tolerance, for information purposes only.BSC: Basic Dimension. Theoretically exact value shown without tolerances.1.2.3.Notes:Pin 1 visual index feature may vary, but must be located within the hatched area.Package is saw singulatedDimensioning and tolerancing per ASME Y14.5M32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: 2022 Microchip Technology Inc.With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBSNumber of TerminalsOverall HeightTerminal WidthOverall WidthTerminal LengthExposed Pad WidthTerminal ThicknessPitchStandoffUnitsDimension LimitsA1AbE2A3eLEN0.50 BSC0.203 REF3.500.350.200.800.000.250.403.600.900.0355.00 BSCMILLIMETERSMINNOM323.700.450.301.000.05MAXK-0.20-Terminal-to-Exposed-PadOverall LengthExposed Pad LengthDD23.505.00 BSC3.603.70Wettable Flank Step Cut DepthA40.10-0.19D3--0.085Wettable Flank Step Cut WidthWettable Flank Step LengthD30.0350.060.085A4-0.100.19Wettable Flank Step HeightDimensions D3 and A4 above apply to all new products released afterNovember 1, and all products shipped after January 1, 2019, and supersededimensions D3 and A4 below.No physical changes are being made to any package; this update is to aligncosmetic and tolerance variations from existing suppliers.DETAIL 1ALTERNATE TERMINALCONFIGURATIONSConfidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1164 Microchip Confidential RECOMMENDED LAND PATTERNDimension LimitsUnitsC2Optional Center Pad WidthContact Pad SpacingOptional Center Pad LengthContact PitchY2X23.703.70MILLIMETERS0.50 BSCMINEMAX5.00Contact Pad Length (X32)Contact Pad Width (X32)Y1X10.800.30NOM1232C1Contact Pad Spacing5.00Contact Pad to Center Pad (X32)G10.25Thermal Via DiameterVThermal Via PitchEV0.301.00BSC: Basic Dimension. Theoretically exact value shown without tolerances.Notes:Dimensioning and tolerancing per ASME Y14.5MFor best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss duringreflow process1.2.For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: 2022 Microchip Technology Inc.Microchip Technology Drawing C04-23391 Rev G32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBSC1C2EVEVX2CHY2G2Y1X1ESILK SCREENVCHExposed Pad 45 Corner Chamfer0.25Contact Pad to Contact Pad (X28)G20.20G1Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information 39.2 WBZ35x Module Packaging Information The following images illustrate the packaging information of the WBZ351, which is a 39-lead PCB 15.5 mm x 20.7 mm x 2.8 mm with a metal shield and coaxial connector. Figure 39-1. Dimensions and Top, Bottom and Side Views of WBZ351 Module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1165 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information Figure 39-2. WBZ351 Module Package Outline Drawing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1166 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information Figure 39-3. Recommended Land Pattern of WBZ351 Module The following images illustrate the packaging information of the WBZ350, which is 30-lead PCB -13.4 mm x 18.7 mm x 2.8 mm with a metal shield and coaxial connector. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1167 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information Figure 39-4. Top, Bottom, End and Side Views of WBZ350 Module 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1168 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Packaging Information Figure 39-5. WBZ350 Module Package Outline Drawing 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1169 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Document Revision History 40. Document Revision History Revision A Date 11/2022 Section Document Description Initial revision 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1170 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Microchip Information The Microchip Website Microchip provides online support via our website at www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes:

Product Support Data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software General Technical Support Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Product Change Notification Service Microchips product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, go to www.microchip.com/pcn and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels:

Distributor or Representative Local Sales Office Embedded Solutions Engineer (ESE) Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip products:

Microchip products meet the specifications contained in their particular Microchip Data Sheet. Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is unbreakable. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. Legal Notice This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1171 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/

design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-

ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. 2022, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN:

2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1172 Microchip Confidential Confidential PIC32CX-BZ3 and WBZ35x Family Quality Management System For information regarding Microchips Quality Management Systems, please visit www.microchip.com/quality. 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1173 Microchip Confidential Confidential Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support:

www.microchip.com/support Web Address:

www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel: 91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea - Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel: 60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel: 86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China - Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China - Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel: 86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Raanana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 2022 Microchip Technology Inc. and its subsidiaries Draft Advance Information Data Sheet A-page 1174 Confidential