FCC ID: TE6-DRWLS1271L DR-WLS1271L-102

 

Preliminary and RFM Confidential DR-WLS1271L-102 FCC/IC Certified WLAN/Bluetooth Multifunction Module Data Sheet www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 1 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Scope This specification applies to the IEEE802.11b/g/n WLAN and Bluetooth 4.0 standards. Interfaces SDIO UART and PCM WLAN/BT BB/MAC IC:

Front-end IC for WL1271L:

TI WL1271L (PG 3.1) TriQuint TQM679002A (E 2.6) WLAN:

Bluetooth:

IC and Firmware Clocks and Compliance Sleep Clock:

RoHS:

Bluetooth:

Certifications:

External 32.768 kHz oscillator required This module is compliant with the RoHS directive Qualified Design Listing: B017989 FCC, and Industry Canada (IC) For mobile operating conditions (greater than 20 cm to the body) - This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator and your body. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. For portable operating conditions (less than 20 cm to the body) - This equipment complies with FCC radi-

ation exposure limits set forth for an uncontrolled environment. This equipment may operate in direct con-

tact with the body of the user under normal operating conditions. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Certification testing conducted with Antenna Factor ANT-RAF-RPS 2.4/5 GHz antenna, RSMA connector. Part Numbers DR-WLS1271L-102 Module:

www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 2 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Block Diagram DR-WLS1271L-102 WLAN Features WLAN MAC baseband processor and RF transceiver which are IEEE802.11b/g and IEEE802.11n PICS compliant Optimized for ultra-low current consumption in all operating modes Accepts 19.2, 26, 38.4, 52 MHz reference clock inputs for easy integration into cellular handsets, etc. IEEE Standard 802.11d, e, h, i, k, r, PICS compliant Support for Cisco Client eXtensions (CCX) standard Serial debug interface Secure Digital Input/Output (SDIO) host interface Medium Access Controller (MAC) Embedded ARM central processing unit (CPU) Hardware-based encryption/decryption using 64-, 128- or 256-bit WEP, TKIP or AES keys Supports Wi-Fi protected access (WPA and WPA2.0) and IEEE Standard 802.11i, including hardware accelerated Advanced Encryption Standard (AES)]

Designed to work with IEEE Std 802.1x for Virtual Private Network (VPN) solutions Baseband Processor IEEE Std 802.11n single-stream data rates (MCS0-7) and SGI support 2.4 GHz Radio Digital Radio Processor (DRP) implementation Integrated LNA Supports IEEE Std 802.11b, g, b/g and 802.11n www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 3 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12

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4 A C Preliminary and RFM Confidential DR-WLS1271L-102 Bluetooth Features V4.0 + EDR, Power Class 1.5 + BLE Bluetooth Qualified Design Listing: B017988 BT Enhanced Data Rates - 2 and 3 Mbps Enhanced UART host interface Very low power consumption On-chip Embedded radio Integrated 2.4 GHz RF transceiver All digital PLL transmitter with digitally controlled oscillator Near-zero IF architecture On-chip TX/RX switch Support for Class-1.5 applications Embedded ARM microprocessor system High rate four wire UART HCI (H4) and three wire UART HCI (H5) Automatic clock-detection mechanism Flexible PCM interface - full flexibility for data order, sampling and positioning Temperature detection and compensation mechanism ensures minimal variation in the RF performance over the entire operating temperature range Low-power scan achieves paging and inquiry scans at 1/3 normal power Digital Radio Processor (DRP) single-ended 50 ohm I/O for easy RF interfacing Patch trap mechanism and reserved RAM enables easy bug fixes www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 4 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Advance Audio Interfaces and capabilities A2DP support A2DP internal loopback Wide-band speech support On board SBC encoder/decoder - offloads host for A2DP and wide-band speech processing Full support for Bluetooth low energy (BLE) standard. BLE can operate in parallel with standard Bluetooth function. WLAN Functional Blocks The DR-WLS1271L-102 WLAN architecture includes a digital radio processor and a point-to-multipoint baseband core function. The architecture is based on a single-processor ARM core. The device includes on-chip peripherals to enable easy communication between a host system and the WLAN core function. WLAN SDIO Transport Layer SDIO is the WLAN host interface in the DR-WLS1271L-102. This interface is a standard SDIO interface

(SDIO Version 2.0), supporting a maximum clock rate of 26 MHz. The DR-WLS1271L-102 SDIO also supports the following features:

4-bit data bus Functions number 0 and 2 Multi-Block data transfer The SDIO interface is used for WLAN. The WLAN block uses function 2. Function 0 is used for the common I/O area. WLAN MAC The DR-WLS1271L-102 MAC implements the IEEE standard 802.11 MAC sub-layer using both dedicated hardware and embedded firmware. The MAC hardware implements real-time functions, including access protocol management, encryption and decryption. WLAN Baseband Processor The DR-WLS1271L-102 baseband processor sits between the on-chip MAC and the radio. The DR-

WLS1271L-102 baseband processor implements the IEEE 802.11b/g/n PHY sub-layers and has been optimized to perform well in conditions of high multipath and noise. WLAN RF Radio The DR-WLS1271L-102 radio is a highly integrated Digital Radio Processor (DRP) designed for 802.11b/g/n applications. The DR-WLS1271L-102 RF interface is a single-band RF front end for 2.4 GHz 802.11b/g/n applications. BT Functional Blocks The DR-WLS1271L-102 BT architecture comprises a digital radio processor and a point-to-multipoint baseband core function. The architecture is based on a single-processor ARM core. The device includes on-chip peripherals to enable easy communication between a host system and the Bluetooth core func-

tion. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 5 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential BT HCI UART Transport Layers The DR-WLS1271L-102 incorporates one UART module dedicated to the Host Controller Interface (HCI) transport layer. The HCI interface is used to transport commands, events, ACL and data between the Bluetooth device and its host using HCI data packets. The DR-WLS1271L-102 supports the following HCI transport layers, detected automatically when communication starts:

UART transport layer - HCI four-wire (H4) and HCI three-wire (H5) HCI interface has a 256 byte receive buffer The HCI UART supports most baud rates (including all PC rates) up to a maximum of 4 Mbps. After pow-

er-up, the baud rate is set for 115.2 kbps. The maximum baud rate deviation supported is -2.5%, +1.5%. The baud rate can thereafter be changed with a VS command. The DR-WLS1271L-102 responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. The only parameter needed is the desired baud rate. HCI hardware includes the following features:

Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions Transmitter underflow detection CTR/RTS hardware flow control BT UART 4-Wire Interface - H4 The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and the DR-WLS1271L-102 is byte-wise by hardware. Flow control is obtained by the following:

When the UART RX buffer of the DR-WLS1271L-102 passes the flow control threshold, it sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the DR-WLS1271L-102 stops transmitting on the interface. In case HCI_CTS is set high in the middle of transmitting a byte, the DR-WLS1271L-102 finishes transmitting the byte and stops the transmission. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 6 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 0

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Preliminary and RFM Confidential BT UART 3-Wire Interface - H5 This interface consists of three signals: TXD, RXD and GND:

HCI_RX Receive Data on the UART Interface HCI_TX Transmit Data on the UART Interface GND Ground XON/XOFF software flow control is normally used. The DR-WLS1271L-102 also supports a four-wire mode for H5, with RTS/CTS hardware flow control. Since the same UART module is used for the 3- and 4-wire HCI UART interface, all features supported by the 4-wire interface are also supported for the 3-wire interface. H5 features:

Flow control configured with HCI_VS command, software XON/XOFF, hardware (RTS/CTS), or none Power management Configurable timers for re-transmission management CRC BT Audio CODEC Interface The CODEC interface is a fully dedicated programmable serial port that provides the logic to interface to several kinds of PCM codecs. The interface supports:

Two voice channels Master/slave modes Coding schemes: -Law, A-Law, Linear, Transparent Long & short frames Different data widths, orders and positions UDI profile High rate PCM interface for EDR Enlarged interface options to support a wider variety of codecs PCM bus sharing PCM Hardware Interface The PCM interface is one implementation of the codec interface. It contains the following four lines:

Clock - configurable direction (input or output) Frame Sync - configurable direction (input or output) Data In - Input Data Out - Output/Hi-Z The DR-WLS1271L-102 device can be either the master of the interface where it generates the clock and the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured by means of a VS command. For slave mode, clock input frequencies of up to 16 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the DR-WLS1271L-

102 can generate any clock frequency between 64 kHz and 4.096 MHz. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 7 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Data Format The data format is fully configurable:

The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to 640 bits when using 1 channel. The data length can be set independently for each channel. The data position within a frame is also configurable with 1-clock (bit) resolution, and can be set inde-

pendently (relative to the edge of the Frame Sync signal) for each channel. The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order

(i.e. LSB first) is supported only for sample sizes up to 24 bits. The data in and data out size do not necessarily have to be the same length. The Data_Out line is configured as a high-Z output between data words. Data_Out can also be set for permanent high-Z, irrespective of data out. This allows the DR-WLS1271L-102 to be a bus slave in a mul-

ti-slave PCM environment. At power up, Data_Out is configured as high-Z. Frame-Idle Period The CODEC interface has the capability for frame-idle periods, where the PCM clock can take a break and become 0 at the end of the PCM frame, after all data has been transferred. The DR-WLS1271L-102 supports frame-idle periods both as master and slave of the PCM bus. When DR-WLS1271L-102 is the master of the interface, the frame-idle period is configurable. There are 2 configurable parameters:

Clk_Idle_Start - indicates the number of PCM clock cycles from the beginning of the frame till the begin-

ning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0. Clk_Idle_End - indicates the time from the beginning of the frame till the end of the idle period. This time is given in multiples of PCM clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period, e.g., for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. Between each two-frame sync there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame and lasts 90-60=30 clock cycles. This means that the idle period ends 100-90=10 clock cycles before the end of the frame. The data transmis-

sion must end prior to the beginning of the idle period. Audio Encoding The DR-WLS1271L-102 CODEC interface can use one of four audio coding patterns:

A-Law (8-bit) m-Law (8-bit) Linear (8 or 16-bit) Transparent www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 8 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Mechanical www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 9 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 6

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Preliminary and RFM Confidential Module Terminal Descriptions Num Terminal Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PCM SYNC PCM CLK PCM OUT PCM IN HOST WAKE NOT USED BT ENABLE WLAN IRQ GND NOT USED NOT USED NOT USED NOT USED WLAN TX WLAN RX WLAN EN SDIO D2 SDIO D1 SDIO CMD NOT USED GND SDIO CLK UART DBG SDIO D0 NOT USED SDIO D3 BT UART DBG NOT USED NOT USED SLEEP CLOCK BT WAKE NOT USED NOT USED NOT USED WLAN BT BT BT BT BT BT Type System I/O I/O I/O I/O I/O I O I/O I/O I I/O I/O I/O I I/O I/O I/O WLAN WLAN WLAN WLAN WLAN WLAN WLAN WLAN WLAN WLAN I/O I I/O BT BT IC Terminal Connection Description WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L WL1271L AUD_FSYNC AUD_CLK AUD_OUT AUD_IN BT_FUNC5 BT_EN WLAN_IRQ WL_RS232_TX WL_RS232_RX WL_EN SDIO_D2 SDIO_D1 SDIO_CMD SDIO_CLK WL_UART_DBG SDIO_D0 SDIO_D3 BT_UART_DBG WL1271L WL1271L SLOWCLK BT_FUNC2 PCM I/F PCM I/F PCM I/F PCM I/F Host Wake Up Mechanical Connection BT Enable/Reset WLAN interrupt request SOC Ground Mechanical Connection Mechanical Connection Mechanical Connection Mechanical Connection RS232_RX RS232_TX WLAN Enable/Reset SDIO DATA 2 SDIO DATA 1 SDIO CMD Mechanical Connection SOC Ground SDIO CLK WL_UART_DBG SDIO DATA 0 Mechanical Connection SDIO DATA 3 BT_UART_DBG, connect to TP for software debug Mechanical Connection Mechanical Connection SLEEP_CLK Input BT_WU/BT Mechanical Connection Mechanical Connection Mechanical Connection www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 10 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential IC Terminal Connection HCI_CTS WL1271L WL1271L HCI_RTS Num 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Terminal Name BT CTS NOT USED BT RTS NOT USED BT TX NOT USED BT RX GND GND GND GND VBAT IN GND GND Type System I/O I/O I/O I/O BT BT BT BT SOC P 2.4 GHZ ANT I/O WLAN GND GND GND WL1271L WL1271L WL1271L, TPS62601 Description BT UART CTS Mechanical Connection BT UART RTS Mechanical Connection BT UART TX Mechanical Connection BT UART RX SOC Ground SOC Ground SOC Ground SOC Ground HCI_TX HCI_RX PMS_VBAT, VIN Power supply input SOC Ground SOC Ground RF receiver input RF transmitter output SOC Ground SOC Ground SOC Ground www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 11 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Absolute Maximum Ratings Ratings Storage Temperature Supply Voltage Operating Conditions Specifications Temperature1, 2 Supply Voltage VBAT VIO VBAT VIO3 Digital I/O Terminal Specifications Specifications Logic High Input Voltage (VDD_IO = IO supply for ring) Logic Low Input Voltage Logic High Output Voltage Logic Low Output Voltage Notes:

Minimum Maximum

-40

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+2.1 Units C V V Minimum Typical Maximum

-40 2.7 1.70

+25 3.6 1.80

+85 4.8 1.90 Units C V V Minimum 0.70 * VIO VIO Maximum Units Condition Default Default 4 mA 1 mA 0.3 mA 4 mA 1 mA 0.09 mA 0 0.35 * VIO VIO - 0.450 VIO - 0.112 VIO - 0.033 0 0 0 VIO VIO VIO 0.450 0.112 0.010 V V V V 1. 2. The device can be reliably operated for 5,000 active WLAN hours cumulative at T ambient of 85 C. BIP (calibration) must be run to achieve full power output when temperatures changes more than 20 C from the last BIP. 3. VIO voltage derived from regulator on module. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 12 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential External Slow Clock Requirements Specifications Slow Clock Frequency Slow Clock Accuracy Clock Transition Time, Tr/Tf 10 to 90%

Clock Duty Cycle Input Voltage Limits Input Impedance Input Capacitance Rise and Fall Time Phase Noise Condition Minimum WLAN Tr/Tf Square Wave, DC-coupled

30 0.65 * VIO 0 1

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Maximum 150 100 70 VIO 0.35 * VIO

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-125 Units kHz ppm ns

V M pF ns dBc/Hz www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 13 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential WLAN Power-up Sequence The following sequence describes device power up from shutdown. Only the WLAN core is enabled; the BT core is disabled. 1. No signals are allowed on the IO pins if no IO power supplied, because the IOs are not fail-safe. Exceptions are CLQ_REQ, SLEEP_CLK (SLOWCLK), and XTALP, which are fail-safe and can tolerate external voltages with no VIO and DC2DC. 2. VBAT,VIO and SLEEP_CLK must be available before WLAN_EN (WL_EN). 3. TWAKE-UP = T1+T2. The duration of T1 is the time from WLAN_EN high until FREF is valid for DR-WLS1271L-102 (55 ms typical). The duration of T2 depends on:

- Operating system

- Host enumeration for the SDIO

- PLL configuration

- Firmware download

- Releasing the core from reset

- Firmware initialization www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 14 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 8 1

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. Preliminary and RFM Confidential WLAN Power-down Sequence 1. DC_REQ of DR-WLS1271L-102 will go low only if WLAN is the only core working. If BT is working, it will stay high. 2. CLK_REQ will go low only if WLAN is the only core working. If BT is working it will stay high. 3. WLAN_EN must remain de-asserted for at least 64 ms before it is re-asserted. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 15 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 8

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1 4 3 Preliminary and RFM Confidential Bluetooth Power-up Sequence The following sequence describes device power-up from shutdown. Only the BT core is enabled; the WLAN core is disabled. 1. No signals are allowed on the IO pins if no IO power supplied, because the IOs are not failsafe. Exceptions are CLK_REQ, SLEEP_CLK, XTALP and AUD_xxx, which are failsafe and can tolerate external voltages with no VIO and DC2DC. 2. VIO and SLEEP_CLK must be stable before releasing BT_EN. 3. Fast clock must be stable a maximum 55 ms after BT_EN goes HIGH. 4. The duration of T1 is defined as the time from BT_EN = high until Fref is valid (55 ms typical). 5. The duration of TWAKE-UP is defined as the time from the rising edge of BT_EN to the falling edge of HCI_RTS (70 ms typical). 6. The DR-WLS1271L-102 indicates completion of BT power up sequence by asserting HCI_RTS low. This occurs up to 100 ms after BT_EN goes high. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 16 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 8

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4 6 5 Preliminary and RFM Confidential Bluetooth Power-down Sequence www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 17 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 5

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8 Preliminary and RFM Confidential Host Interface Combination WLAN SDIO BT UART Remarks All core functions support automatic host-interface recognition. The user does not need to configure it in advance. SDIO Interface Clock Switching Characteristics, 25 pF Load Capacitance 25 60 Minimum Maximum Units MHz

ns ns ns ns ns ns ns ns 0 40 10 10 5 5 0 0 14 14 4.3 3.5 Symbol FCLOCK DC tWL tWH tTLH tTHL tISU tIH tODLY1 tODLY2 SDIO Timing Parameter Clock Frequency Low/High Duty Cycle Pulse Duration, Clock Low Pulse Duration, Clock High Clock Rise Time Clock Fall Time Set-up Time, Input Valid before Clock Hold Time, Input Valid after Clock Delay Time, Clock Falling Edge to Output Valid Delay Time, Clock Falling Edge to Output Invalid 0.7 0.2 www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 18 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12

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Preliminary and RFM Confidential SDIO Interface Read Symbol tCR tCC tRC tAC SDIO Interface Write Parameter Delay Time, Assign Relative Address or Data Transfer Mode; Read command CMD invalid to card response CMD valid Delay Time, CMD command invalid to CMD command valid Delay Time, CMD response invalid to CMD command valid Access Time, CMD command invalid to SD0-SD3 read data valid Minimum Maximum Units 2 8 8 8 64 Clock Cycles

Clock Cycles Clock Cycles Clock Cycles Symbol Td1 Td2 Parameter Delay Time, CMD Card Response Invalid to SD0-SD3 Write Data Valid Delay Time, SD0-SD3 Write Data Invalid to CRC Status Valid Minimum Maximum Units 2 2

2 Clock Cycles Clock Cycles www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 19 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 4 A

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Preliminary and RFM Confidential BT Audio CODEC/PCM Interface Switching Characteristics PCM Master Symbol TCLK TW tis tih top top PCM Slave Symbol TCLK TW tis tih tis tih top Parameter Clock Period High/Low Pulse Width AUD_IN Setup Time AUD_IN Hold Time AUD_OUT Propagation Time, 40 pF Load FSYNC_OUT Propagation Time, 40 pF Load Minimum Maximum Units 166.7 (6 MHz) 50% of TCLK 25 0 0 0 15625 (64 kHz) 10 10 ns ns Parameter Clock Period High/Low Pulse Width AUD_IN Setup Time AUD_IN Hold Time FSYNC_IN Setup Time FSYNC_IN Hold Time AUD_OUT Propagation Time, 40 pF Load Minimum Maximum Units 62.5 (16 MHz) 40% of TCLK 8 0 8 0 0 21 ns ns www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 20 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 6

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7 6 Preliminary and RFM Confidential UART Interface Timing Symbol Parameter Baud Rate Baud Rate Accuracy CTS Low to TX_DATA CTS High to TX_DATA CTS High Pulse Width RTS Low to RX_DATA ON RTS High to RX_DATA OFF BR t5, t7 t3 t4 t6 t1 t2 Condition Minimum Typical Maximum Most Standard Rates Receive/Transmit Hardware Flow Control Interrupt set to 1/4 FIFO 37.5

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s byte bit s byte DR-WLS1271L-102 IRQ Operation 1. The default state of the WLAN_IRQ prior to firmware initialization is 0. 2. During firmware initialization, the WLAN_IRQ is configured by the SDIO module; a WLAN_IRQ changes its state to 1 3. A WLAN firmware interrupt is handled as follows:

(a) The WLAN firmware creates an Interrupt-to-Host, indicated by a 1-to-0 transition on the WLAN_IRQ line (host must be configured as active-low or falling-edge detect).

(b) After the host is available, depending on the interrupt priority and other host tasks, it masks the firmware interrupt. The WLAN_IRQ line returns to 1 (0-to-1 transition on the WLAN_IRQ line).

(c) The host reads the internal register status to determine the interrupt sources - the register is cleared after the read

(d) The host processes in sequence all the interrupts read from this register

(e) The host unmasks the firmware interrupts. 4. The host is ready to receive another interrupt from the WLAN device. DR-WLS1271L-102 BT function Low Power Mode Protocols The DR-WLS1271L-102 device includes a mechanism that handles the transition between operating mode and deep sleep low-power mode. The protocol is done via the UART and is known as eHCILL (en-

hanced HCI Low Level) power management protocol. This protocol is backward compatible with the BRF6150/ BRF6300/BRF6350/WL1273 HCILL Protocol, so a Host that implements the HCILL for BRF6150/ BRF6350 does not need to change anything in order to work with the DR-WLS1271L-102. The

"Enhanced" portion of the HCILL introduces changes that allow a simpler host implementation of this pro-

tocol. See BT-SW-0024 (BRF Enhanced HCILL 4 wire Power Management Protocol). In addition to the HCILL protocol, the WL1273 also supports the power management schemes inherent in the UART H5 transport layers. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 21 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 0

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Preliminary and RFM Confidential DC and RF Characteristics for IEEE 802.11b, 11 Mbps Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source System Specifications Standard Mode Frequency Data Rate DC Specifications DC Current:

TX Mode RX Mode Sleep Mode Transmitter Specifications RF Output Power Spectrum Mask:

1st Sidelobes 2nd Sidelobes Power-on and Power-off Ramp RF Carrier Suppression Modulation Accuracy (EVM) Spurious Emissions:

0.03 to 1.00 GHz 1.00 to 12.75 GHz 1.80 to 1.90 GHz 5.15 to 5.30 GHz Receiver Specifications Sensitivity:

Minimum Input Level, 11 Mbps, FER 8%

Maximum Input Level, FER 8%

Data IEEE802.11b DSSS/CCK 2412 to 2462 MHz 1, 2, 5.5, 11 Mbps Minimum Typical Maximum

250 100 100 320 150 200 Minimum Typical Maximum 14

15

16

-40

-55 0.1 37 10

-80

-60

-80

-80 18

-30

-50 2.0

35

-36

-30

-47

-47 Minimum Typical Maximum

-10

-87 0

-76

Units mA mA A Units dBm dBr dBr s dB

dBm dBm dBm dBm Units dBm dBm www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 22 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential DC and RF Characteristics for IEEE 802.11g Operation, 54 Mbps Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source System Specifications Standard Mode Frequency Data Rate DC Specifications DC Current:

TX Mode RX Mode Sleep Mode Transmitter Specifications RF Output Power Spectrum Mask:

at fC 11 MHz at fC 20 MHz at fC 30 MHz Spurious Emissions:

0.03 to 1.00 GHz 1.00 to 12.75 GHz 1.80 to 1.90 GHz 5.15 to 5.30 GHz Constellation Error (EVM) Receiver Specifications Sensitivity:

Minimum Input Level, 54 Mbps, PER 10%

Maximum Input Level, PER 10%

Data IEEE802.11g OFDM 2412 to 2462 MHz 6, 9, 12, 18, 24, 36, 48, 54 Mbps Minimum Typical Maximum

180 100 100 245 150 200 Minimum Typical Maximum 11

13

-30

-33

-45

-80

-65

-80

-80

-30 15

-20

-28

-40

-36

-30

-47

-47

-25 Minimum Typical Maximum

-20

-73

-4

-65

Units mA mA A Units dBm dBr dBr dBr dBm dBm dBm dBm dB Units dBm dBm www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 23 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential DC and RF Characteristics for IEEE 802.11n Operation, 65 Mbps (MCS7) Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source System Specifications Standard Mode Frequency Data Rate DC Specifications DC Current:

TX Mode RX Mode Sleep Mode Transmitter Specifications RF Output Power Spectrum Mask:

at fC 11 MHz at fC 20 MHz at fC 30 MHz Constellation Error (EVM) Spurious Emissions:

0.03 to 1.00 GHz 1.00 to 12.75 GHz 1.80 to 1.90 GHz 5.15 to 5.30 GHz Receiver Specifications Sensitivity:

Minimum Input Level, 65 Mbps, PER 10%

Maximum Input Level, PER 10%

Data IEEE802.11n-2.4G OFDM 2412 to 2462 MHz 6.5, 13, 19.5, 26, 39, 52, 58.5, 65 Mbps Minimum Typical Maximum

180 100 100 245 150 200 Minimum Typical Maximum 10

12

-30

-35

-50

-80

-80

-65

-80

-80 14

-20

-28

-45

-28

-36

-30

-47

-47 Minimum Typical Maximum

-20

-67

-5

-64

Units mA mA A Units dBm dBr dBr dBr dB dBm dBm dBm dBm Units dBm dBm www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 24 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential DC and RF Characteristics for Bluetooth Operation Conditions: 25 C, VBAT=3.6 V, VDDIO=1.8 V, TCXO Fast Clock Source System Specifications Bluetooth Standard Channel Spacing Number of RF Channels Power Class Operating Mode DC Specifications DC Current:

DH1 Packet, 50% RX/TX Slot Duty Cycle DH3 Packet, 50% RX/TX Slot Duty Cycle DH5 Packet, 50% RX/TX Slot Duty Cycle Transmitter Specifications RF Output Power Frequency Range, RX/TX

-20 dB Bandwidth Adjacent Channel Power1:

M - N = 2 M - N 3 Modulation Characteristics:

Modulation f1 average Modulation f2 maximum Modulation f2 average / f1 average Carrier Frequency Drift:

1 Slot 3 Slots 5 Slots Maximum Frequency Drift Rate Spurious Emissions:

0.03 to 1.00 GHz 1.00 to 12.75 GHz 1.80 to 1.90 GHz 5.15 to 5.30 GHz ERD Relative Power, /4-DPQSK and 8DPSK EDR Carrier Frequency Stability and Modulation Accuracy:

/4-DPQSK and 8DPSK

/4-DPQSK and 8DPSK

/4-DPQSK and 8DPSK RMS DEVM, /4-DPQSK 99% DEVM, /4-DPQSK Peak DEVM, /4-DPQSK Data Version 4.0 1 MHz 79 1 Frequency hopping spread spectrum, pseudorandom hopping pattern, time division multiple access on transmit or receive, frequency hop after each RX/TX cycle Minimum Typical Maximum

37 46 48 60 60 60 Minimum Typical Maximum 4.5 8.0 2400 to 2483.5

140 115 0.8

-25

-40

-40

-20

-4

-75

-10

-75

0.8

-45

-46 158 132 0.9

-58

-40 80 80

-0.2

6 10 14

1.0

-20

-40 175

+25

+40

+40

+20

-36

-30

-47

-47 1

+75

+10

+75 20 30 35 Units mA mA mA Units dBm MHz MHz dBm dBm kHz kHz

kHz kHz kHz kHz/50 s dBm dBm dBm dBm dB kHz kHz kHz

www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 25 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Transmitter Specifications (continued) RMS DEVM, 8DPSK 99% DEVM, 8DPSK Peak DEVM, 8DPSK Receiver Specifications Sensitivity, BER 0.1%:

2402 MHz 2441 MHz 2480 MHz C/I Performance, BER 0.1%2:

Co-channel ratio, -60 dBm Input 1 MHz ratio, -60 dBm Input 2 MHz ratio, -60 dBm Input 3 MHz ratio, -67 dBm Input Image 1 MHz ratio, -67 dBm input Blocking Performance, BER 0.1%3:

30 to 2000 MHz 2000 to 2400 MHz 2500 to 3000 MHz 3000 to 12750 MHz Intermodulation Performance, -64 dBm Input, BER 0.1%

Maximum Input Level EDR Sensitivity, BER 0.01%:

/4-DQPSK 8DPSK Minimum Typical Maximum Units

6 10 15 13 20 25 Minimum Typical Maximum

-10

-27

-27

-10

-39

-20

-90

-90

-90 7

-9

-46

-48

-30

-8 0 0

-5

-30 10

-90

-84

-70

-70

-70 11 0

-30

-40

-20

-70

-70

Units dBm dBm dBm dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm 1. Up to three spurious responses within Bluetooth limits are allowed. 2. Up to five spurious responses within Bluetooth limits are allowed. 3. Up to twenty-four spurious responses within Bluetooth limits are allowed. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 26 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Storage Conditions This product should be stored without opening the packing in an ambient temperature range of 5 to 35 C and humidity range from 20 to 70% RH, and be used within six months of receipt. Packing materials can be deformed at temperatures above 40 C. If the product is not used six months or more after receipt, its solderbility should be tested before being used. The product should be stored in non-corrosive gas. Any excess mechanical shock such as sticking the packing materials with a sharp object or dropping the product, etc., must be avoided in order not to damage the packing materials. This product is applicable to MSL3, based on JEDEC Standard J-STD-020. After the packing is opened, the product should be stored at an ambient temperature below 30 C and at humidity level less than 60% RH. The product should be used within 168 hours. If the color of the indica-

tor in the packing has changed, the product should be baked before soldering at 125 to 130 C for 24 hours. The products should be baked on the heat-resistant tray, as the tape and reel materials are not heat-resistant. Handling Conditions Use care in handling or transporting this product as excessive stress or mechanical shock can crack or break the product. Do not touch this product with bare hands as this can result in poor solderability. Standard PCB Design (Land Pattern and Dimensions) All the ground terminals should be connected to the ground patterns, and unconnected terminals should be soldered to unconnected PCB pads for mechanical strength. The best land pattern depends on the pattern generation method, grounding method, land dimensions, land forming method of the unconnected terminals and the PCB material and thickness. Contact RFM technical support if you have any questions about adapting the recommend land pattern to your application specifics or before using non-standard land dimensions, etc. Module PCB Placement This product can be broken by uneven forces from a worn-out chucking locating claw or a suction nozzle. To prevent damage, be sure to follow the specifications for the maintenance of the chip placer being used. Be aware that mechanical chucking can damage this product when used for mounting it on a PCB. Module Soldering Preheat so that the temperature difference T between the solder and module surface is less than 130 C. If the module is immersed in solvent after mounting, care should be taken to limit the temperature difference to 100 C. These provisions are necessary to prevent damage due to excessive differential ex-

pansion. Contact RFM technical support if you have any questions about soldering methods or are con-

sidering other soldering conditions. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 27 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Using a Soldering Iron A soldering iron of 18 W or less, using a ceramic heater is recommended. The soldering iron tip diameter should be 3 mm maximum, and the tip temperature should be 350 C or less. The iron contact time at each terminal should be limited to 3 seconds. The soldering iron should be applied to the land pattern next to the module terminal, not directly on the module ceramic substrate. Example Reflow Soldering Profile Use rosin flux or a weakly active flux with a chlorine content of 0.2% or less by weight. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 28 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12 Preliminary and RFM Confidential Solder Paste Amount and Assembly Standards Ensure that solder is applied smoothly to a minimum height of 0.2 to 0.5 mm at the end surface of the modules external pads. If too much or little solder is applied, the mechanical strength can be insufficient. Cleaning This product is moisture sensitive and not suitable for water-based cleaning. Operational Conditions This product is designed to work under normal environmental conditions - ambient temperature, humidity and pressure. If this product is used under the following circumstances, erratic operation or complete fail-

ure can occur:

Atmosphere containing a corrosive gas (Cl2, NH3, SOx, NOx, etc.) Atmosphere containing a combustible or volatile gas Dusty location Location with direct sunlight Location subject to water splashes, high humidity or condensation If the customers application could subject a module to one or more of the above conditions, consult with RFM technical support before use. Avoid static electricity or excessive voltage while assembling this module on a PCB or testing it. Power Supply Voltages Power supply voltages applied to this product must conform to the specifications for the module. Contact RFM technical support if you have any questions about power supply requirements. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 29 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12

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Preliminary and RFM Confidential Labeling Requirements FCC Certification - The WLS1271L-102 hardware has been certified for operation under FCC Part 15 Rules, Section 15.247. FCC Notice - This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any inter-

ference received, including interference that may cause undesired operation. A clearly visible label is required on the outside of the users (OEM) enclosure stating the following text:

Contains FCC ID: HSW-WLS1271L-102 Contains IC: 4492A-WLS1271L-102 This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. WARNING: This device operates under Part 15 of the FCC rules. Any modification to this device, not expressly authorized by RFM, Inc., may void the users authority to operate this device. This apparatus complies with Health Canadas Safety Code 6 / IC RSS 210. IC RSS-210 Notice - Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause un-

desired operation of the device. ICES-003 This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus as set out in the radio interference regulations of Industry Canada. Le present appareil numerique nemet pas de bruits radioelectriques depassant les limites applicables aux appareils numeriques de Classe B prescrites dans le reglement sur le brouillage radioelectrique edicte par Industrie Canada. www.RFM.com 2012 by RF Monolithics, Inc. Technical support +1.972.448.3700 E-mail: tech_sup@rfm.com Page 30 of 30 DR-WSL1271L-102 Data Sheet - 12/13/12