Technical Description The Equipment Under Test (EUT) is Bluetooth Cube. The EUT has Bluetooth BLE feature. It is powered by a 3.7V internal rechargeable battery. 2.4GHz Bluetooth portion:
Modulation Type: GFSK Antenna Type: Integral, Internal Antenna gain: 0dBi RF conducted power range: -8dBm to +2dBm Frequency Range: 2402MHz - 2480MHz The main components are described as below:
1. U4 BK3231S is 2.4GHz Bluetooth BLE core 2. 16MHz crystal is master clock for U4 BK3231S 3. U5, U6, U7 are motor drivers 4. U2 is 3.3VDC LDO BK3231S Datasheet V1.5 BK3231S Bluetooth SoC Datasheet Preliminary Specification Building 41, Capital of Tech Leaders, 1387 Zhangdong Road, Zhangjiang High-Tech Park, Pudong New District, Shanghai, China Beken Corporation Tel: (86)21 51086811 Fax: (86)21 60871277 This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The contents of this document should not be disclosed outside the companies without specific written permission. Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware implementation may differ. 2015 Beken Corporation Proprietary and Confidential Page 1 of 24 Revision History BK3231S Datasheet V1.5 Date Author(s) Remark 2015-1-7 Yiming and Guofei 2016-02-26 mingsheng Rev. 1.0 1.1 1.2 2016.04.08 Mingsheng.ao 1.3 2016.04.11 Mingsheng.ao Draft version based on BK3231 datasheet Add the 32PIN SIP package inf Modified the SIP package removed P22,P23,VPP, added P35,P36,P37 ,which is based on the SIP package Modified the Description 2015 Beken Corporation Proprietary and Confidential Page 2 of 24 BK3231S Datasheet V1.5 Table of Contens General Description ............................................................................................................................ 6 1.1 Overview ....................................................................................................................................... 6 Block Diagram ............................................................................................................................. 6 1.2 Features ........................................................................................................................................ 7 1.3 1.4 Application ................................................................................................................................... 7 Pin Information ................................................................................................................................... 9 Function Description ........................................................................................................................ 16 3.1 Memory Address Mapping ....................................................................................................... 16 3.2 Interrupt and Clock Unit .......................................................................................................... 17 3.3 GPIO ........................................................................................................................................... 17 ADC ............................................................................................................................................. 17 3.4 UART .......................................................................................................................................... 18 3.5 I2C-SMBus ................................................................................................................................. 18 3.6 3.7 SPI ............................................................................................................................................... 19 3.8 PWM Timer ............................................................................................................................... 20 3.9 Watch dog ................................................................................................................................... 20 Electrical Specifications .................................................................................................................... 20 4.1 General Specification ................................................................................................................. 20 BR mode ..................................................................................................................................... 21 4.2 Package Information ........................................................................................................................ 22 5.1 QFN 7X7 56PIN: ........................................................................................................................ 22 5.2 QFN4X4 32PIN: ......................................................................................................................... 23 Application Schematic ...................................................................................................................... 24 6.1 QFN7X7 56PIN: ......................................................................................................................... 24 6.2 QFN4X4 32PIN: ......................................................................................................................... 24 Order Information ............................................................................................................................ 24 Contact Information ......................................................................................................................... 24 1 2 3 4 5 6 7 8 2015 Beken Corporation Proprietary and Confidential Page 3 of 24 BK3231S Datasheet V1.5 List of Figures FIGURE 1 BLOCK DIAGRAM ............................................................................................................................ 6 FIGURE 2 BK3231S QFN56PIN ASSIGNMENT .................................................................................................. 9 FIGURE 3 BK3231S QFN32PIN ASSIGNMENT ................................................................................................ 12 FIGURE 4 BK3231S QFN56PIN PACKAGE INFORMATION ............................................................................. 22 FIGURE 5 BK3231S QFN32PIN PACKAGE INFORMATION ............................................................................. 23 2015 Beken Corporation Proprietary and Confidential Page 4 of 24 BK3231S Datasheet V1.5 List of tables TABLE 1 BK3231S QFN56 PIN DESCRIPTION ................................................................................................. 10 TABLE 2 BK3231S QFN32 PIN DESCRIPTION ................................................................................................. 13 TABLE 3 THE MEMORY MAPPING ................................................................................................................. 16 TABLE 4 GENERAL CHARACTERISTICS ........................................................................................................... 20 TABLE 5 BR MODE RF CHARACTERISTICS ..................................................................................................... 21 TABLE 6 BLE MODE RF CHARACTERISTICS ..................................................................... TABLE 7 BEKEN PROPRIETORY 2.4GHZ MODE RF CHARACTERISTICS ............................ TABLE 8 ORDER INFORMATION .................................................................................................................... 24 2015 Beken Corporation Proprietary and Confidential Page 5 of 24 BK3231S Datasheet V1.5 1 General Description 1.1 Overview The BK3231S chip is a highly integrated SoC, and it supports two wireless protocols, which are Blueetooth Basic Rate (BR), and Bluetooth Low Energy (BLE). It integrates a high-performance 2.4GHz RF transceiver, rich features baseband, ARM-core MCU and various peripheral IOs. It uses up-to-4Mbit external Flash to excute the programmable protocol and profile to support customized applications such as HID, Bluetooth 3D Glasses shutter, Remote controllers. 1.2 Block Diagram 16 KB Program Cache 2.4 GHz Radio Flash Controller Data Memory
(24 KB) Bluetooth Baseband JTAG AHB AHB2APB APB MCU ARM968E-S 16 MHz DPLL 16MHz Clock 32KHz Clock Power Managerment DPLL
(96 MHz) 16 MHz external Crystal 32 KHz external Crystal 32 KHz on-chip ROSC ICU OTP 32 Byte) BIST Reset Figure 1 Block Diagram 3DS UART SPI I2C GPIO PWM WDT ADC RTC Timer 2015 Beken Corporation Proprietary and Confidential Page 6 of 24 BK3231S Datasheet V1.5 1.3 Features Bluetooth SIG Bluetooth Dual-Mode compliant Bluetooth 3.0 Basic Rate (BR) Bluetooth 4.0 Low Energy (BLE) ARM968 Core MCU integrated External Flash up-to-4Mbytes for Program and 24KB RAM for Data Low-power 2.4GHz Transceiver Operation voltage from 1.8V to 3.6 V
-89 dBm sensitivity at 1 Mbps data rate and +4dBm transmit power for BLE application
-86dBm sensitivity for 1 Mbps mode and 2 dBm transmit power for BR application External power-amplifier supporting Clock 16 MHz crystal reference clock 96MHz optional clock provided by internal DPLL Internal 32kHz low-power oscillator with auto-calibration (200ppm) External 32kHz crystal oscillator as optional low-power clock source Interface and peripheral units FLASH programming, JTAG, Dual I2Cs, SPI and UART interface Integrated OTP for customization On-chip high accurate temperature sensor On-chip 7-channel 10bit general ADC 6-outputs PWM 4-outputs 3D Glasses shutter Real-time counter Package Type 56-pin QFN 7mmx7mm package 32-pin QFN 4mmx4mm package 1.4 Application Wireless Self-Timer Wireless Keyboards 2015 Beken Corporation Proprietary and Confidential Page 7 of 24 BK3231S Datasheet V1.5 Wireless Mouse Wireless Gamepad LED Lighting Remote Control Bluetooth 3D Glasses 2015 Beken Corporation Proprietary and Confidential Page 8 of 24 BK3231S Datasheet V1.5 2 Pin Information The QFN56 package format for the full functions usage.It can be used as keyboard TX part and total 34 GPIO available. The pin assignment for QFN56 package is shown in Figure 2. Other package type such as QFN32 is also available by request with less GPIO. K 2 3 L A T X 6 5 5 0 P 5 5 7 1 P 4 5 P W _ S L F O S _ S L F N S C _ S L F O L A T X L A T X C C V I L A T X 3 5 2 5 1 5 0 5 9 4 8 4 3 2 P 7 4 2 2 P 6 4 1 2 P 5 4 F E R V C D A 4 4 I F C C V 3 4 P27 P35 P36 VDDSPI VCCMCU BOOST_CP1 BOOST_CP2 VOUTBOOST 1 2 3 4 5 6 7 8 9 VPP P37 10 P34 11 P16 12 P33 13 P31 1414 BK3231S QFN 7mmx7mm 56-Pin 42 VDDPA15 41 ANT 40 VCCRF 39 TSTEN 38 P24 37 P00 36 P01 35 P30 34 P14 33 P15 32 P26 31 P40 30 P41 29 P04 5 1 2 3 P 6 1 I S _ S L F 7 1 8 1 K C S _ S L F D L O H _ S L F 9 1 0 2 P 0 2 3 0 P 1 2 2 0 P 2 2 5 2 P 3 2 3 1 P 4 2 2 1 P 5 2 7 0 P 6 2 6 0 P 7 2 1 1 P 8 2 0 1 P Figure 2 BK3231S QFN56Pin Assignment 2015 Beken Corporation Proprietary and Confidential Page 9 of 24 BK3231S Datasheet V1.5 Table 1 BK3231S QFN56 Pin Description Name P27 P35 P36 VDDSPI VCCMCU boost_cp1 boost_cp2 voutboost VPP P37 P34 P16 P33 P31 P32 FLS_SI FLS_SCK FLS_HOLD P20 P03 P02 P25 P13 P12 P07 P06 P11 P10 P04 P41 P40 P26 P15 P14 P30 P01 P00 Description General I/O General I/Oor input of ADC5 General I/Oor input of ADC6 The output of digital LDO 3V power supply The function PIN of boost,add 100nF cap between boost_cp1 and boost_cp2 The function PIN of boost,add 100nF cap between boost_cp1 and boost_cp2 The output of boost The 6V power supply of OTP,it can be used when download General I/Oor input of ADC7 General I/Oor input of ADC4 General I/Oor clock for I2C1 General I/Oor input of ADC3 General I/Oor input of ADC1 General I/Oor input of ADC2 The function PIN of flash The function PIN of flash The function PIN of flash General I/O, or UART TX General I/O, or 3DS_PWM[3]
General I/O, or 3DS_PWM[2]
General I/Oor enable for TIMER1 General I/Oor enable for PWM3 General I/Oor enable for PWM2 General I/O, or chip select for SPI General I/O,or MISO for SPI General I/Oor enable for PWM1 General I/O, or enable for PWM0 General I/O, or SCK for SPI General I/O, or PLL enable General I/O, or PA enable General I/Oor enable for TIMER2 General I/Oor enable for PWM5 General I/Oor enable for PWM4 General I/Oor input of ADC0 General I/O, or 3DS_PWM[1]
General I/O, or 3DS_PWM[0]
NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 2015 Beken Corporation Proprietary and Confidential Page 10 of 24 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 P24 TSTEN VCCRF ANT VDDPA15 VCCIF ADCVREF P21 P22 P23 VCCXTAL XTALI XTALO FLS_CSN FLS_SO FLS_WP P17 P05 XTAL32K BK3231S Datasheet V1.5 General I/Oor enable for TIMER0 Enable the testting function of memory 3V power supply The input of RF The output of PA ldo 3V power supply The output of reference voltage of ADC,it can be connected to a cap on the board General I/O, or UART RX General I/Oor clock for I2C0 General I/Oor data I/O for I2C0 3V power supply The input of 16M crystal oscillator The input of 16M crystal oscillator The function PIN of flash The function PIN of flash The function PIN of flash General I/Oor data I/O for I2C1 General I/O, or MOSI for SPI The input of 32K crystal oscillator 2015 Beken Corporation Proprietary and Confidential Page 11 of 24 BK3231S Datasheet V1.5 The pin assignment for QFN32 package is shown in Figure 3. XTAL32K VDDSPI VCCMCU BOOST_CP1 BOOST_CP2 VOUTBOOST VPP P31 1 2 3 4 5 6 7 8 P W _ S L F 2 3 O S _ S L F 1 3 N S C _ S L F 0 3 I L A T X O L A T X 9 2 L A T X C C V F E R V C D A 8 2 7 2 6 2 I F C C V 5 2 BK3231S QFN 4mmx4mm 32-Pin 9 2 3 P 0 1 I S _ S L F 1 1 K C S _ S L F 2 1 D L O H _ S L F 3 1 0 2 P 4 1 5 1 3 2 P 2 2 P 6 1 1 2 P 24 VDDPA15 23 ANT 22 VCCRF 21 TSTEN 20 P00 19 P01 18 P30 17 P14 Figure 3 BK3231S QFN32Pin Assignment 2015 Beken Corporation Proprietary and Confidential Page 12 of 24 BK3231S Datasheet V1.5 Table 2 BK3231S QFN32 Pin Description NO Name 1 2 3 XTAL32K VDDSPI VCCMCU Description The input of 32K crystal oscillator The output of digital LDO 3V power supply boost_cp1 boost_cp2 Boost function PIN. Add 100nF cap between boost_cp1 and boost_cp2 Boost function PIN. Add 100nF cap between boost_cp1 and boost_cp2 voutboost VPP The output of boost The 6V power supply of OTP,it can be used when download General I/Oor input of ADC1 General I/Oor input of ADC2 FLS_SI FLS_SCK FLS_HOLD P20 The function PIN of flash The function PIN of flash The function PIN of flash General I/O, or UART TX 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P31 P32 P23 P22 P21 P14 P30 P01 P00 TSTEN VCCRF ANT VDDPA15 VCCIF ADCVREF VCCXTAL XTALI XTALO FLS_CSN FLS_SO FLS_WP General I/Oor data I/O for I2C0 General I/Oor clock for I2C0 General I/O, or UART RX General I/Oor enable for PWM4 General I/Oor input of ADC0 General I/O, or 3DS_PWM[1]
General I/O, or 3DS_PWM[0]
Enable the testting function of memory 3V power supply The input of RF The output of PA ldo 3V power supply The output of reference voltage of ADC. It can be connected to a cap on the board 3V power supply The input of 16M crystal oscillator The input of 16M crystal oscillator The function PIN of flash The function PIN of flash The function PIN of flash 2015 Beken Corporation Proprietary and Confidential Page 13 of 24 BK3231S Datasheet V1.5 The pin assignment for QFN32 package(SIP with flash) is shown in Figure 4 P35 P36 VDDSPI VCCMCU boost_cp1 boost_cp2 voutboost P37 1 2 3 4 5 6 7 8 K 2 3 L A T X 2 3 5 0 P 1 3 L A T X C C V O L A T X I L A T X 0 3 9 2 8 2 1 2 P 7 2 F E R V C D A 6 2 I F C C V 5 2 BK3231S QFN 4mmx4mm 32-Pin 9 1 3 P 0 1 2 3 P 1 1 0 2 P 2 1 3 0 P 3 1 2 0 P 4 1 5 1 7 0 P 6 0 P 6 1 4 0 P 24 VDDPA15 23 ANT 22 VCCRF 21 TSTEN 20 P00 19 P01 18 P30 17 P14 Figure 4 BK3231S QFN32Pin Assignment(SIP with flash) Table 3 BK3231S QFN32 Pin Description(SIP with flash) 5 6 7 8 9 10 11 NO Name 1 2 3 4 P35 P36 VDDSPI VCCMCU Description General I/Oor input of ADC1 General I/Oor input of ADC1 The output of digital LDO 3V power supply boost_cp1 boost_cp2 Boost function PIN. Add 100nF cap between boost_cp1 and boost_cp2 Boost function PIN. Add 100nF cap between boost_cp1 and boost_cp2 voutboost The output of boost P37 P31 P32 P20 General I/Oor input of ADC1 General I/Oor input of ADC1 General I/Oor input of ADC2 General I/O, or UART TX 2015 Beken Corporation Proprietary and Confidential Page 14 of 24 BK3231S Datasheet V1.5 General I/O, or 3DS_PWM[3], I2C1.SDA, WP_FLA General I/O, or 3DS_PWM[2], I2C1.SCL, HOLD_FLA General I/O, or SPI_NSS, CSN_FLA General I/O,or MISO for SPI, SCK_FLA General I/O, or SPI_SCK, SI_FLA P03 P02 P07 P06 P04 P14 P30 P01 P00 TSTEN VCCRF ANT VDDPA15 VCCIF ADCVREF P21 VCCXTAL XTALI XTALO P05 XTAL32K 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 General I/Oor enable for PWM4 General I/Oor input of ADC0 General I/O, or 3DS_PWM[1]
General I/O, or 3DS_PWM[0]
Enable the testting function of memory 3V power supply The input of RF The output of PA ldo 3V power supply The output of reference voltage of ADC. It can be connected to a cap on the board General I/O, or UART RX 3V power supply The input of 16M crystal oscillator The input of 16M crystal oscillator General I/O, or MOSI for SPI, SO_FLA The input of 32K crystal oscillator 2015 Beken Corporation Proprietary and Confidential Page 15 of 24 BK3231S Datasheet V1.5 3 Function Description 3.1 Memory Address Mapping Table 3 The Memory Mapping Start Address End Address Total (Bytes) Flash space 0x00000000 0x0003FFFF 4M maximum SRAM 0x00400000 0x00405FFF 24K Program Memory Data Memory AHB Peripheral ICU 0x00800000 BK24_BB 0x00810000 FLASH CONTROL 0x00820000 AHB2APB 0x00F00000 APB Peripheral WDT 0x00F00000 PWM 0x00F00100 SPI 0x00F00200 UART 0x00F00300 I2C0 0x00F00400 GPIO 0x00F00500 RTC 0x00F00600 ADC 0x00F00700 BT 3DS 0x00F00800 I2C1 0x00F00900 Timer 0x00F00A00 XVR 0x00F10000 CEVA DM IP 0x00F20000 0x0080FFFF 0x0081FFFF 0x0082FFFF 0x00FFFFFF 0x00F000FF 0x00F001FF 0x00F002FF 0x00F003FF 0x00F004FF 0x00F005FF 0x00F006FF 0x00F007FF 0x00F008FF 0x00F009FF 0x00F00AFF 0x00F1FFFF 0x00F2FFFF 64K 64K 64K 1M 256B 256B 256B 256B 256B 256B 256B 256B 256B 256B 256B 64K 64K 2015 Beken Corporation Proprietary and Confidential Page 16 of 24 BK3231S Datasheet V1.5 3.2 Interrupt and Clock Unit The MCU core clock can be selected from three clock sources: 32KHz clock, 16 MHz clock and 96 MHz DPLL. The ARM968E-S supports two interrupt level. The FIRQ has higher priority than nIRQ. In the BK3231S, all peripheral interrupts are nIRQ except the Bluetooth transceiver. All interrupt can be enabled, disabled, and cleared. There are two low power modes: MCU stop and deep sleep, and any interrupt can be configured to be a wake up source to let MCU exit low power mode. 3.3 GPIO There are totally 40 general purpose input/output ports (GPIO). All the 40 ports can be used for general I/O with selectable direction for each bit, or these lines can be used for specialized functions. 3.4 ADC An 8bits SAR-ADC is integrated in the BK3231S. Total 8 channels can be selected used for ADC transfer. The ADC supports continue mode and single transfer mode, and the sample rate can be 1 KHz to 32KHz. In single transfer mode, it will generate interrupt every time after transform. The ADC has four work modes they are sleep mode, single mode, and software mode and continue mode. IDLE mode(mode==00): ADC is in idle state. Single mode(mode==01): The ADC will enter idle mode when transfer is done and waiting MCU to read the result. You should write mode=1 again for another transfer. Controlled by software (mode==10): In this mode, interrupt will be triggered after transfer and wait MCU to read. The interrupt will be cleared after MCU read, and then the transfer will start again. Continue mode(mode==11):The ADC will work at the sample rate set by register. The sample rate can be calculated by the next formula:
F_sample = input ADC clock/(2^(ADC_CLK_RATE+2) / 36(or 18)) The highest sample rate is 32k 2015 Beken Corporation Proprietary and Confidential Page 17 of 24 BK3231S Datasheet V1.5 The local interrupt flag of ADC need not be cleared by software; it will be set after transform and be cleared after the result has been read out. But the ADC INTstored ICU should be cleared after the ADC INT service finished. The range of input voltage is from 0v to 1.5V. If the input voltage more than 1.5V, a resistor can be added to decrease the input voltage like the next diagram. Test_point R1 BK3231 PA D ADC On/off R2 100k Note: There are eight GPIO can be ADC input. When used as this:
Voltage=data [9:0]/448; the saturate voltage is 1.5 volt. 3.5 UART The UART interface has 128 bytes FIFO for both TX and RX. It will generate interrupt request when there is risk or event of FIFO underflow or overflow. For the RX, it will generate interrupt if found parity bit check error or stop bit check error. When the UART RX line goes from idle state (HIGH) to active state (LOW) for a set UART clock cycle, it will generate wake up interrupt to activate MCU clock. 3.6 I2C-SMBus The I2C I/O interface is a two-wire, bi-directional serial bus. The I2C is compliant with the System Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to the interface by the system controller are byte oriented with the I2C interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/10th of the system clock as a master or slave
(this can be faster than allowed by the I2C specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. 2015 Beken Corporation Proprietary and Confidential Page 18 of 24 BK3231S Datasheet V1.5 The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL
(serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. It is assumed the reader is familiar with the I2C-Bus Specification -- Version 2.0 and system Management Bus Specification -- Version 1.1. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-
collector output for both the SCL and SDA lines, so that both are pulled high
(recessive state) when the bus is free. 3.7 SPI The Enhanced Serial Peripheral Interface (SPI) provides access to a flexible, full-
duplex synchronous serial bus. SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-
select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slaves. There are four pins for SPI interface. The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI is operating as a master and an input when SPI is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI is operating as a master and an output when SPI is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 2015 Beken Corporation Proprietary and Confidential Page 19 of 24 BK3231S Datasheet V1.5 In slave mode, the data on MOSI are sampled at the middle of period of every bit. In master mode, the data on MISO are sampled at the last clock period to acquire the maximal setup time. 3.8 PWM Timer There are three timers, two of which is 16 bit and can be works as PWM waveform generator, while the other one is 20bit timer. The PWM waveform can be output to GPIO to drive external device such as LED. 3.9 Watch dog The watch dog is used to reset the whole chip when the firmware runs out of order. 4 Electrical Specifications 4.1 General Specification Table 4 General Characteristics Name Parameter (Condition) Min Max Typi cal Unit Com ment VCC TEMP VIH VIL VOH VOL Operating Condition Voltage Temperature Digital input Pin High level Low level Digital output Pin High level (IOH=-0.25mA) Low level(IOL=0.25mA) 4.2 BLE mode 1.8
-20 3.0
+27 3.6
+80 V C VCC-0.3 VSS VCC+0.3 V VSS+0.3 V VCC- 0.3 VSS V VCC VSS+0.3 V Table 5 BLE mode RF Characteristics Name Parameter (Condition) Min Max Normal condition Deep sleep Active RX Active TX @ 2 dBm output power Transmitter Output power Modulation 20 dB bandwidth Receiver IVDD IVDD IVDD PRF PBW Max Input 1 E-3 BER RXSENS IIP3 1 E-3 BER sensitivity IIP3, Pin=-63 dBm; Punwant=-39 dBm; f0=2f1-f2, f2-f1=3 MHz or 4 MHz or 5 MHz 0 Typi cal TBD TBD TBD 4 1
-89 TBD 5 Unit Com ment uA mA mA dBm MHz dBm dBm dBm 2015 Beken Corporation Proprietary and Confidential Page 20 of 24 BK3231S Datasheet V1.5 Table 6 BR mode RF Characteristics Name Parameter (Condition) Min Max Unit Com ment C/ICO C/I1ST C/I2ND C/I3RD C/I1STI C/I2NDI Co-channel C/I ACS C/I 1MHz ACS C/I 2MHz ACS C/I 3MHz ACS C/I Image channel ACS C/I 1 MHz adjacnet to image channel 4.3 BR mode Normal condition Deep sleep Active RX Active TX @ 2 dBm output power Transmitter Output power Modulation 20 dB bandwidth Receiver IVDD IVDD IVDD PRF PBW Max Input 1 E-3 BER RXSENS IIP3 1 E-3 BER sensitivity IIP3, Pin=-63 dBm; Punwant=-39 dBm; f0=2f1-f2, f2-f1=3 MHz or 4 MHz or 5 MHz Co-channel C/I ACS C/I 1MHz ACS C/I 2MHz ACS C/I 3MHz ACS C/I Image channel ACS C/I 1 MHz adjacnet to image channel C/ICO C/I1ST C/I2ND C/I3RD C/I1STI C/I2NDI 0 Typi cal TBD TBD TBD 2 1
-86 TBD TBD TBD TBD TBD TBD TBD dB dB dB dB dB dB 5 11 0
-30
-40
-9
-20 uA mA mA dBm MHz dBm dBm dBm dB dB dB dB dB dB 2015 Beken Corporation Proprietary and Confidential Page 21 of 24 BK3231S Datasheet V1.5 5 Package Information 5.1 QFN 7X7 56PIN:
Figure 4 BK3231S QFN56Pin Package Information 2015 Beken Corporation Proprietary and Confidential Page 22 of 24 5.2 QFN4X4 32PIN:
BK3231S Datasheet V1.5 Figure 5 BK3231S QFN32Pin Package Information 2015 Beken Corporation Proprietary and Confidential Page 23 of 24 BK3231S Datasheet V1.5 6 Application Schematic 6.1 QFN7X7 56PIN:
TBD 6.2 QFN4X4 32PIN:
TBD 7 Order Information Table 6 Order Information Part number Package Packing BK3231SQB BK3231SQ32 QFN 4mmx4mm 32-Pin QFN7x7-56Pin Tape Reel Tape Reel 3000 10K Minimum Order Quantity 8 Contact Information Beken Corporation Technical Support Center Shanghai office Building 41, 1387 Zhangdong Road, Zhangjiang High-Tech Park, Pudong New District, Shanghai, China Phone: 86-21-51086811 Fax: 86-21-60871089 Postal Code: 201203 Email: info@bekencorp.com Website: www.bekencorp.com 2015 Beken Corporation Proprietary and Confidential Page 24 of 24