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Antenna Info 1 | Users Manual | 113.17 KiB | ||||
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Antenna Info 2 | Users Manual | 127.25 KiB | ||||
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Antenna Info 3 | Users Manual | 352.86 KiB | ||||
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Antenna Info 4 | Users Manual | 252.88 KiB | ||||
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Antenna Info 5 | Users Manual | 368.72 KiB | ||||
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Antenna Info 6 | Users Manual | 249.40 KiB | ||||
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Antenna Info 7 | Users Manual | 463.91 KiB | ||||
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Antenna Info 8 | Users Manual | 189.12 KiB | ||||
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Antenna Info 9 | Users Manual | 480.49 KiB | ||||
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Manual | Users Manual | 3.17 MiB | ||||
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User Manual | Users Manual | 254.36 KiB | ||||
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1 2 | Antenna Info 1 | Users Manual | 113.17 KiB |
ANT-2.4-CW-RCL DATA SHEETS Product Dimensions Description 0.24
(6.0) The RCL Series is useful in products where additional height above the products case is needed or a slightly wider operational bandwidth is desired. The 2.45GHz version has a center-fed 1/2-wave element with an internal ground reference. Features Right-angle mount Excellent performance Omni-directional pattern Fully weatherized Rugged & damage-resistant Part 15 compliant RP-SMA connector Available in black or custom colors Use with plastic or metal enclosures Electrical Specifications Center Freq. Bandwidth Wavelength VSWR Impedance Gain Connector 2.45GHz 120MHz 1/2-wave
<1.7 typ. at center 50 ohms 2.90dBi RP-SMA Electrical specifications and plots measured on 4.00 x 4.00 reference ground plane Ordering Information ANT-2.4-CW-RCL S11 SWR 1.470 3.46
(88.0) 0.31
(8.0) 0.42
(10.6) Polar Plots and VSWR Graph 0.0
-10.0
-20.0
-30.0
-40.0
-50.0 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 Azimuth Elevation Typical VSWR CENTER 2 450.000MHz SPAN 1 000.000MHz Antenna Factor 575 S.E. Ashley Place Grants Pass, OR 97526-3237 www.antennafactor.com 541-956-0931 (phone) 541-471-6251 (fax) Rev 04-27-06 ANT-2.4-CW-RCL DATA SHEETS 180 Absolute Gain of AUT Azimuth Radiation Pattern Measurement Antenna Polarity: Vertical Test Antenna Polarity: Vertical Maximum Absolute Gain: -0.50dBi 270 0 Antenna Elevation Radiation Pattern Measurement Antenna Polarity: Horizontal Test Antenna Polarity: Horizontal Maximum Absolute Gain: 2.90dBi 180 270 0 Antenna Antenna Test Fixture ABOUT THIS TEST FIXTURE The adjoining diagram shows the dimensions of the fixture on which the stated pattern and gain measurements were made. This does not mean that your product must conform to this size or antenna orientation, although it should be recognized that the gain, pattern, and performance may increase or decrease accordingly. Antenna Factor recognizes that our antennas are often used in compact applications with less than ideal ground planes. In some cases, the reference jig is smaller than optimum, particularly with lower-frequency antennas. This is, in part, to more accurately reflect the performance of the antenna in typical real-world applications. 90 270 90 270 0 0.0
-10.0
-20.0
-30.0
-40.0
-50.0 180 Absolute Gain of AUT 0 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 180 4.00
(101.6) 90 90 4.00
(101.6) GROUND PLANE ON BOTTOM LAYER Antenna Factor 575 S.E. Ashley Place Grants Pass, OR 97526-3237 www.antennafactor.com 541-956-0931 (phone) 541-471-6251 (fax)
1 2 | Antenna Info 2 | Users Manual | 127.25 KiB |
ANT-2.4-CW-RCT-xx DATA SHEETS Product Dimensions Description 0.39
(10.0) The RCT 1/2-wave 2.4GHz antenna delivers outstanding performance and orientation flexibility in a compact physical package. The antennas innovative articulating base allows it to tilt and swivel for optimum orientation. The RCT mounts quickly via an SMA or FCC Part 15 compliant RP-SMA connector. 4.44
(113.0) 3.76
(95.6) 0.33
(8.4) 0.35
(9.0) 0.20
(5.1) 1.10
(28.0) Polar Plots and VSWR Graph 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 9 Features Tilts and rotates Very low VSWR Excellent performance Omni-directional pattern Fully weatherized Rugged and damage-resistant RP-SMA or SMA connector Electrical Specifications Center Freq. Bandwidth Wavelength VSWR Impedance Gain Connector 2.45GHz 120MHz 1/2-wave
<1.9 typ. at center 50 ohms 2.20dBi RP-SMA or SMA Electrical specifications and plots measured on 4.00x 4.00 reference ground plane Ordering Information ANT-2.4-CW-RCT-RP (with RP-SMA connector) ANT-2.4-CW-RCT-SS (with SMA connector) S11 SWR 1.033 Azimuth Elevation Typical VSWR CENTER 2 450.000MHz SPAN 200.000MHz Antenna Factor 575 S.E. Ashley Place Grants Pass, OR 97526-3237 www.antennafactor.com 541-956-0931 (phone) 541-471-6251 (fax) Rev 05-01-06 ANT-2.4-CW-RCT-xx DATA SHEETS 180 Absolute Gain of AUT Azimuth Radiation Pattern Measurement Antenna Polarity: Vertical Test Antenna Polarity: Vertical Maximum Absolute Gain: 0.40dBi 270 0 Antenna Elevation Radiation Pattern Measurement Antenna Polarity: Horizontal Test Antenna Polarity: Horizontal Maximum Absolute Gain: 2.20dBi 180 270 0 Antenna Antenna Test Fixture ABOUT THIS TEST FIXTURE The adjoining diagram shows the dimensions of the fixture on which the stated pattern and gain measurements were made. This does not mean that your product must conform to this size or antenna orientation, although it should be recognized that the gain, pattern, and performance may increase or decrease accordingly. Antenna Factor recognizes that our antennas are often used in compact applications with less than ideal ground planes. In some cases, the reference jig is smaller than optimum, particularly with lower-frequency antennas. This is, in part, to more accurately reflect the performance of the antenna in typical real-world applications. 90 270 90 270 0 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 180 Absolute Gain of AUT 0 5.0
-5.0
-15.0
-25.0
-35.0
-45.0 180 4.00
(101.6) 90 90 4.00
(101.6) GROUND PLANE ON BOTTOM LAYER Antenna Factor 575 S.E. Ashley Place Grants Pass, OR 97526-3237 www.antennafactor.com 541-956-0931 (phone) 541-471-6251 (fax)
1 2 | Antenna Info 3 | Users Manual | 352.86 KiB |
WCR External Antenna Connector Mount Specifications:
wave coaxial dipole
Clutch allows 360 rotation
Flexible element
FCC Part 15 compliant polarized connector Frequency Polarization Gain Nominal Impedance VSWR RF Power Handling Size (Length) Temperature Range Drop Test Connectors:
Model #
WCR2400-MMCX WCR2400-SMA WCR2400-SMRP 1.0 dBi 2.0 dBi 1.0 dBi 2.4 2.5 GHz Vertical MMCX SMA SMRP 50 ohms 1.5:1 max at resonance 50 watts 8cm
-40 to +80C 1M Part #
WCR2400MMCX WCR2400SMA WCR2400SMRP Connector MMCX Straight SMA-Male RP-SMA-Male (gold) Azimuth WCR2400MMCX Elevation WCR2400MMCX Specifications subject to change without notice. 3425 N.44th Street, LINCOLN, NE 68504 USA SALES PHONE: 800.228.4563 PHONE: 402.467.4491 FAX: 402.467.4528 www.centurion.com sales@centurion.com Copyright 2004 Centurion Wireless Technologies, Inc. All Rights Reserved m c 0 1 m c 8 Model Number:
WCR2400 WCRb 1/17/05
1 2 | Antenna Info 4 | Users Manual | 252.88 KiB |
WRR - RPSMA External Antenna Connector Mount Specifications:
Covers 802.11b for all U.S., European & Japanese WLAN applications
Center fed coaxial dipole Frequency Gain Polarization Nominal Impedance VSWR Size (Length) Connectors:
Model #
WRR2400-RPSMA-B WRR2400-RPSMA-G 2.4 2.5 GHz 1.3 dBi (2.45 GHz) Vertical, Omnidirectional 50 ohms 2:1 max across all bands 10.9 cm (180) or 8.8 cm (90) Part #
MAF94028 MAF94046 Color Black Gray Connector RP-SMA RP-SMA Azimuth Plane 2.45 GHz Elevation Plane Elevation Plane phi = 0 2.45 GHz Specifications subject to change without notice. 3425 N.44th Street, LINCOLN, NE 68504 USA phi = 90 2.45 GHz SALES PHONE: 800.228.4563 PHONE: 402.467.4491 FAX: 402.467.4528 www.centurion.com sales@centurion.com Copyright 2004 Centurion Wireless Technologies, Inc. All Rights Reserved Model Number:
WRR2400-RPSMA m c 8
. 8 m c 8
. 8 WRR RPSMAa 5/18/04
1 2 | Antenna Info 5 | Users Manual | 368.72 KiB |
Product Specification Titanis 2.4 GHz Swivel SMA Antenna P r o d u c t S p e c i f i c a t i o n Titanis 2.4 GHz Swivel SMA Antenna TABLE OF CONTENT 1. Features .........................................................................................................................................................................2 2. Description .....................................................................................................................................................................2 3. Application ......................................................................................................................................................................2 4. General data ...................................................................................................................................................................3 5. Model names ..................................................................................................................................................................3 6. Electrical characteristics .................................................................................................................................................3 7. Electrical performance ....................................................................................................................................................4 7.1 Voltage Standing Wave Ratio ...............................................................................................................................4 7.2 Radiation patterns ................................................................................................................................................4 7.3 3D-Radiation ........................................................................................................................................................4 8. Antenna Dimensions .......................................................................................................................................................5 9. Electrical interface ..........................................................................................................................................................5 9.1 Connection ...........................................................................................................................................................5 9.2 Electrical performance test set-up........................................................................................................................5 10. Reliability ......................................................................................................................................................................6 10.1 Temperature and Humidity .................................................................................................................................6 10.2 Judgement standard ..........................................................................................................................................6 11. Hazardous Material Reguration Conformance ..............................................................................................................6 12. Packaging .....................................................................................................................................................................7 12.1 Shelf storage recommendation ..........................................................................................................................7 12.2 Packaging characteristics ..................................................................................................................................7 12.3 Bag label information .........................................................................................................................................7 13. Contact information ......................................................................................................................................................7 1. FEATURES
-Designed for 2.4 GHz applications [BluetoothTM, WiFiTM (802.11b/g), ZigbeeTM, WiMediaTM etc.]
- Also available as reversed thread (left) to meet FCC regulation part 15
- Intended for SMA mounting
- Supplied in bulk 2. DESCRIPTION The Titanis antenna is intended for use with all 2.4 GHz applications. The antenna is fitted with an SMA male connector and a blade, made of a flexible material that can be rotated 360 degrees. No external matching net is required. Titanis is available as standard SMA and reversed thread SMA. 3. APPLICATION
- Development tools
- Test equipment
- Instruments
- Access points and gateways
- Printers Subject to changes without prior notice 2 (7) Rev : AE030054-B / April 18 2005 Titanis 2.4 GHz Swivel SMA Antenna Drawing No. Technology
-Metal Antenna Family
-External 4. MODEL NAMES 20 10 Bxxxx - 01 5. GENERAL DATA emaNtcudorP
.oNelcitrA ycneuqerF noitaziraloP erutarepmetgnitarepO ecnadepmI thgieW epytannetnA 6. ELECTRICAL CHARACTERISTICS scitsiretcarahC niM pyT xaM iBd0.4 iBd1.4 iBd4.4
%08 1:1.1
%58 1:2.1
%09 1:3.1 niaGkaeP ycneiciffE RWSV zHG4.2sinatiT
)dradnatS(10-4484B0102
)daerhtesreveR(10-0906B0102 zHG5.2-4.2 raeniL Cged58+ot04-
mhO05 marg4.7 leviwS
*snoitidnoC
)dleifraen(rebmahcD3niderusaeM,zHG5.2-4.2ycneuqerF rezylanAkrowteNniderusaeM,zHG5.2-4.2ycneuqerF draobecnerefertnAagigehtnodesaberaelbatsihtnidedivorpatadllaetoN*
Subject to changes without prior notice 3 (7) Rev : AE030054-B / April 18 2005 Titanis 2.4 GHz Swivel SMA Antenna 7. ELECTRICAL PERFORMANCE 7.1 Voltage Standing Wave Ratio 7.2 3D-Radiation 7.3 Radiation patterns XY- Plane XZ- Plane YZ- Plane Total polarization Vertical polarization Horizontal polarization Subject to changes without prior notice 4 (7) Rev : AE030054-B / April 18 2005 Titanis 2.4 GHz Swivel SMA Antenna 8. ANTENNA DIMENSIONS A H 2 H 1 H 3 B W 1 A B 2.07 5.05.21 retemillimnisnoisnemiD 1H thgieH 5.05.26 9. ELECTRICAL INTERFACE 9.1 Connection Titanis is fitted with an internal matching net. Connect the antenna directly to an SMA Female connector. W 2 2H thgieH 5.03.84 3H thgieH 5.05.9 1W htdiW 3.002 2W htdiW 3.05.91 9.2 Electrical performance test set-up RF Transmitted Network Analyzer SMA FEMALE RF Absorbed Anechoic chamber set-up Network analyzer set-up Subject to changes without prior notice 5 (7) Rev : AE030054-B / April 18 2005 Titanis 2.4 GHz Swivel SMA Antenna 10. RELIABILITY 10.1 Temperature and Humidity metI dradnatS woL hgiH noitaruD gnitarepO erutarepmet erutarepmeT gnilcyc efilegarotS ytidimuH efilegarotS erutarepmetwoL efilegarotS erutarepmethgiH Cged03-
Cged09+
Cged04-
Cged09+
nim01/selcyc005 yrD:dBtseT,2-2-86006CEI/NE taeh
:aNtseT,41-2-86006CEI/NE erutarepmetfoegnahC pmaD:aCtseT,1-2-86006CEI/NE taeh HR%09/Cged06+
h005 h005 dloC:dAtseT,1-2-86006CEI/NE Cged55-
yrD:bBtseT,2-2-86006CEI/NE taeh
Cged521+
h005 10.2 Judgement standard The judgement of the above tests should be made as follows:
1. Visual inspection - Normal apperance with no obvious cracking, peeling-off. 2. Electrical inspection - The antenna satisfies the VSWR specification throughout the 2.4-2.5 GHz band 11. HAZARDOUS MATERIAL REGURATION CONFORMANCE Cadmium and cadmium compound. Organic brominated compound (PBB, PBDE) Polychlorinated biphenyl (PCB) Polychlorinated naphthalene (PCN) Organic tin compound Asbestos Azo compound Lead and lead compound Mercury and mercury compound Sexivalent chrome compound Chlorinated paraffin (CP) Mirex Formaldehyde Tetra-bromo-bisphenol-A-bis (TBBP-A-bis) Subject to changes without prior notice 6 (7) Rev : AE030054-B / April 18 2005 Titanis 2.4 GHz Swivel SMA Antenna 12. PACKAGING 12.1 Shelf storage recommendation erutarepmeT ytidimuH efiLflehS ecalpegarotS Ceerged04+ot01-
HR%57nahtsseL shtnoM84 thgilnustceriddnasagevisorrocmorfyawA 12.2 Packaging characteristics sgabcitsalpnidesolcneklubniderevilederasannetnaehT 12.3 Bag label information 13. CONTACT INFORMATION www.gigaAnt.com Europe & Africa e-mail: info.EU@gigaAnt.com Tel: +46 46 286 4177 Or your local gigaAnt representative America e-mail: info.US@gigaAnt.com Tel: +1 817 430 7291 Asia and Pacific e-mail: info.ASIA@gigaAnt.com Tel: +656 890 6200 Subject to changes without prior notice 7 (7) Rev : AE030054-B / April 18 2005
1 2 | Antenna Info 6 | Users Manual | 249.40 KiB |
2.4 GHz 2.2 dBi Reverse Polarity SMA "Rubber Duck" Wireless LAN Antenna Features Compact size, only 4.7" long RP-SMA Connector Tilt and swivel design 802.11b, 802.11g and Bluetooth compatible Description Model: HG2402RD-RSF This compact 2.4GHz omnidirectional "rubber-duck" WiFi antenna provides broad coverage and 2.2 dBi gain. It is a coaxial sleeve design with an omni-directional pattern. It is ideally suited for IEEE 802.11b and 802.11g wireless LANs, Bluetooth and other WLAN applications. Only 4.7" long, this flexible antenna features a tilt-and-swivel reverse-polarity SMA plug connector, allowing them to be used vertically, at a right angle, or any angle in-between. It is suitable as a replacement antenna for many access points and radios that are equipped with reverse-polarity SMA connectors including D-Link, Linksys WET11 and others (Note: This RF antenna is used as a "replacement" antenna rather than a "range extender"
antenna. It should yield similar range to most radio's stock antennas). Application Note: This antenna is not for use with U.S.Robotics RP-SMA equipped devices. Specifications Electrical Specifications Frequency Gain Impedance VSWR Mechanical Specifications Weight Length Diameter Finish Connector 2400-2500 MHz 2.2 dBi 50 Ohm
< 2.0 0.52 oz. (15 g) 4.7" (105 mm) 0.4" (10 mm) Matte Black Reverse Polarity SMA Plug Operating Temperature
-40 C to to 85 C (-40 F to 185 F) Polarization RoHS Compliant Vertical Yes e-mail: sales@hyperlinktech.com tel: 561-995-2256 fax: 561-995-2432 web: www.hyperlinktech.com 1201 Clint Moore Road Boca Raton FL 33487 Antenna Gain Pattern e-mail: sales@hyperlinktech.com tel: 561-995-2256 fax: 561-995-2432 web: www.hyperlinktech.com 1201 Clint Moore Road Boca Raton FL 33487
1 2 | Antenna Info 8 | Users Manual | 189.12 KiB |
Series Part Numbers Con nector Code Description P/N E-Plane Pattern @ 2.45GHz AM SMA Plug S141AM-2450 AH SMA Plug Reverse Polarity | $141AH-2450 AT SMA Plug Reverse Thread | $141AT-2450 |
Electrical Properties: @0.31(8) Frequency Range: 2.4~2.5 GHz Impedance: 50Q nominal VSWR: <2.0:1 Gain: 2 CBi Radiation: Omni Polarization: Vertical =>
Wave: Half Wave Dipole =
oO wt Mechanical Properties:
Connector: SMA type Material:
Whip: Polyurethene(Black) Operation Temp.: = -20C to +65C Storage Temp.: -30C to +75C
*Connector is covered by the overmold. This is a ROHS compliant product.
@0.39(10) |--|
Connector Interface TITLE 2.4GHz Straight Antenna Rev. Date |_ SHEET
-141 Model 01/08/06| 1 of 1 UNIT_|pwe. No. | $141XX-2450 SMA Plug SMA Plug Reverse Polarity | SMA Plug Reverse Thread in.(mm) i 5 z =| NEARSON none All rights reserved NEARSON INC. Specification is subject to change without notice. http://www.nearson.com
1 2 | Manual | Users Manual | 3.17 MiB |
Data Sheet JN513x IEEE802.15.4 and ZigBee Wireless Microcontrollers Overview The JN513x are a family of low power, low cost wireless microcontrollers suitable for IEEE802.15.4 and ZigBee applications. Each device integrates a 32-bit RISC processor, with a fully compliant 2.4GHz IEEE802.15.4 transceiver, 192kB of ROM, a selection of RAM sizes from 8kB to 96kB, and a rich mixture of analogue and digital peripherals. The cost sensitive ROM/RAM architecture supports the storage of system software, tables and application code/data. Each device has hardware MAC and AES encryption accelerators, power saving and timed sleep modes, and mechanisms for security key and program code encryption. These features all make for a highly efficient, low power, single chip wireless microcontroller for battery-powered applications. Block Diagram including protocol stacks, routing RAM 8kB - 96kB ROM 192kB 32-bit RISC CPU 48-byte OTP eFuse Bootloader Flash Optional SPI 2-wire serial Timers UARTs 12-bit ADC, comparators 11-bit DACs, temp sensor Applications Robust and secure low power wireless applications Wireless sensor networks, particularly IEEE802.15.4 and ZigBee systems Home and commercial building automation Remote Control Telemetry and utilities Toys and gaming peripherals Industrial systems
(e.g. AMR) 2.4GHz Radio O-QPSK Modem XTAL IEEE802.15.4 MAC Accelerator Power Management 128-bit AES Encryption Accelerator Benefits Single chip integrates transceiver and microcontroller for wireless sensor networks Cost sensitive ROM/RAM architecture, meets needs for volume application System BOM is low in component count and cost Hardware MAC ensures low power consumption and low processor overhead Extensive user peripherals Pin compatible with JN5121 for easy migration Features: Transceiver MAC accelerator with packet 2.4GHz IEEE802.15.4 compliant 128-bit AES security processor formatting, CRCs, address check, auto-acks, timers Integrated power management and sleep oscillator for low power On-chip power regulation for 2.2V to 3.6V battery operation Deep sleep current 0.2A Sleep current with active sleep timer 1.3A Needs minimum of external components (< US$1 cost) Rx current 34mA Tx current 34mA Receiver sensitivity -97dBm Features: Microcontroller Transmit power +3dBm 32-bit RISC processor sustains 32MIPs with low power 192kB ROM stores system code, including protocol stack 8kB, 16kB, 32kB or 96kB RAM stores system data and optionally bootloaded program code 48-byte OTP eFuse, stores MAC ID on-chip, offers AES based code encryption feature 4-input 12-bit ADC, 2 11-bit DACs, 2 comparators 2 Application timer/counters, 3 system timers 2 UARTs (one for debug) SPI port with 5 selects 2-wire serial interface Up to 21 GPIO Industrial temperature range
(-40C to +85C) 8x8mm 56-lead QFN Lead-free and RoHS compliant Jennic 2007 JN-DS-JN513x v1.4 Preliminary 1 Pin Assignment Pin Descriptions RISC CPU and Memory Peripherals Block Diagram ROM RAM OTP eFuse Memory External Memory Power Supplies Reset 16MHz System Clock Radio Analogue Peripherals Digital Input/Output Jennic 1 Introduction 1.1 Wireless Microcontroller 1.2 Wireless Transceiver 1.3 1.4 1.5 2 Pin Configurations 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 3 CPU 4 Memory Organisation 4.1 4.2 4.3 4.4 4.4.1 4.5 4.6 5 System Clocks 5.1 5.2 6 Reset 6.1 Internal Power-on Reset 6.2 External Reset 6.3 Software Reset 6.4 Brown-out Detect 7 Interrupt System 7.1 7.2 7.2.1 Bus Error 7.2.2 Alignment 7.2.3 Illegal Instruction 7.3 Hardware Interrupts 8 Wireless Transceiver 8.1 8.1.1 8.1.2 8.2 Modem System Calls Processor Exceptions 16MHz Oscillator 32kHz Oscillator Radio Radio External components Antenna Diversity Secure External Memory Encryption Peripherals Unused Memory Addresses 6 6 6 6 7 8 9 10 11 11 11 11 11 11 12 13 14 15 15 15 15 16 16 16 17 17 17 18 18 19 19 20 21 21 21 21 21 21 22 23 23 24 24 25 2 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Baseband Processor JN513x Initiated Data Transfer Transmit Reception Auto Acknowledge Beacon Generation Security Pulse Width Modulation Mode Capture Mode Counter / Timer Mode Delta-Sigma Mode Timer / Counter Application 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 Security Coprocessor 9 Digital Input/Output 10 Serial Peripheral Interface 10.1 Programming Example 11 Intelligent Peripheral Interface 11.1 Data Transfer Format 11.2 11.3 Remote Processor Initiated Data Transfer 12 Timers 12.1 Peripheral Timer / Counters 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.2 Tick Timer 12.3 Wakeup Timers 12.3.1 12.3.2 13 Serial Communications 13.1 13.2 UART Application 13.3 Programming Example 14 Two-Wire Serial interface 14.1 Connecting Devices 14.2 Multi-Master Operation 14.3 Clock Stretching 14.4 Programming Example 15 Analogue Peripherals 15.1 Analogue to Digital Converter 15.1.1 15.1.2 15.1.3 15.1.4 15.2 Digital to Analogue Converter 15.2.1 15.2.2 15.3 Comparators 16 Power Management and Sleep Modes Operation Supply Monitor Temperature Sensor Programming Example RC Oscillator Calibration External 32kHz Clock Source Operation Programming Example Interrupts Jennic 25 26 26 27 27 27 27 28 29 32 34 34 35 35 36 36 37 37 38 38 39 40 41 41 42 43 44 44 45 46 47 47 48 48 50 51 51 51 52 52 52 52 53 53 55 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 3 CPU Doze Power Domains DIO Event Comparator Event Operating Conditions DC Current Consumption I/O Characteristics Reset Brown-out Detect SPI Timing Two-wire serial interface Power Down and Wake-Up timings 32kHz Oscillator 16MHz Crystal Oscillator Analogue to Digital Converters Digital to Analogue Converters Jennic 16.1 Operating Modes 16.1.1 16.2 Active Processing Mode 16.2.1 16.3 Sleep Mode 16.3.1 Wakeup Timer Event 16.3.2 16.3.3 16.4 Deep Sleep Mode 17 Electrical Characteristics 17.1 Maximum ratings 17.2 DC Electrical Characteristics 17.2.1 17.2.2 17.2.3 17.3 AC Characteristics 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 17.3.8 17.3.9 17.3.10 Comparators 17.3.11 17.3.12 Radio Transceiver Appendix A Mechanical and Ordering Information A.1 A.2 A.3 Ordering Information A.4 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.6 Appendix B Development Support B.1 B.1.1 B.1.2 B.1.3 B.2 B.3 B.3.1 B.3.2 B.3.3 Crystal Equivalent Circuit Crystal Load Capacitance Crystal ESR and Required Transconductance Tape Orientation and Dimensions Reel Information: 7 Reel Reel Information: 13 Reel Dry Pack Requirement for Moisture Sensitive Material Typical Application Schematic PCB Requirements Supply Decoupling 56pin QFN Package Drawing PCB Decal Device Package Marking Tape and Reel Information 16MHz Oscillator Applications Information PCB Design and Reflow Profile Temperature Sensor Crystal Oscillator 55 55 55 55 55 56 56 56 56 57 57 57 57 58 59 59 59 60 61 61 62 63 63 63 64 65 66 66 70 70 71 72 73 74 74 75 76 76 77 78 78 78 79 79 81 82 82 83 84 4 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Reference Oscillator Requirements B.3.4 Reference Oscillator Layout Considerations B.3.5 VCO Tune Circuit Component Specifications B.3.6 VCO Tune Circuit Layout Considerations B.3.7 Radio Front-End B.3.8 Antennae B.3.9 Ground Planes B.3.10 Manufacturing Considerations B.3.11 Bespoke Solutions - PCB Layout Suggestions B.3.12 Using a Balun B.3.13 Decoupling Capacitors B.3.14 Internal Regulator Smoothing Capacitors B.3.15 VREF B.3.16 IBIAS B.3.17 B.3.18 EMC Appendix C Related Documents RoHS Compliance Status Information Disclaimers Version Control Contact Details Jennic 84 84 84 85 85 85 85 86 87 88 88 88 89 89 89 90 90 90 90 91 91 92 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 5 Jennic 1 Introduction The JN513x is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including ZigBee. It includes all of the functionality required to meet the IEEE802.15.4 specification and has additional processor capability to run a wide range of applications including but not limited to Remote Control, Home and Building Automation, Toys and Gaming. The device includes a Wireless Transceiver, RISC CPU, on-chip memory and an extensive range of peripherals. 1.1 Wireless Microcontroller Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimise this complexity, Jennic provides a series of software libraries that control the transceiver and peripherals of the JN513x. These libraries, with functions called by an Application Programming Interface (API) remove the need for the developer to understand wireless protocols and greatly simplify the programming complexities of power modes, interrupts and hardware functionality. In addition, the JN513x is expected to be programmed in the C high-level language and debugged using the JN5 series software developer kit. In view of the above, the register details of the JN513x are not provided in the datasheet and access to all peripherals is gained using API calls to the peripheral library. Extensive reference to such calls is made throughout the datasheet and the convention used is to format the function call in the courier font e.g. vAHI_Init(). Full details of these function calls can be found in the JN-RM-2001 Integrated Peripherals API [2]. An IEEE802.15.4 compliant wireless network can be developed using the IEEE802.15.4 MAC library described in JN-
RM-2002 802.15.4 Stack [3]. Applications over simple (point-point, star or tree) wireless networks can use this library directly or more complex wireless mesh networks such as ZigBee or IPv6 can be built on top of the IEEE802.15.4 library. 1.2 Wireless Transceiver The Wireless Transceiver is highly integrated and, together with the IEEE802.15.4 MAC library requires little knowledge of RF or wireless design. The Wireless Transceiver comprises a low-IF 2.45GHz radio, an O-QPSK modem, a baseband controller and a security coprocessor. The radio has a 200 resistive differential antenna port that includes all the required matching components on-chip, allowing a differential antenna to be connected directly to the port, minimising the system BOM costs. Connection to a single ported antenna can be achieved using a 200/50 2.45GHz balun. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realised very easily. The Security coprocessor provides hardware-based 128-bit AES-CCM, CBC(1), CTR and CCM* processing as specified by the 802.15.4b standard. It does this in-band on packets during transmission and reception, requiring minimal intervention from the CPU. It is also available for off-line use under software control for encrypting and decrypting packets generated by software layers such as Zigbee and user applications. This means that these algorithms can be off-loaded by the CPU, increasing the processor bandwidth available for user applications. The transceiver elements (radio, modem and baseband) work together to provide 802.15.4 Medium Access Control under the control of a protocol stack supplied with the device as a software library. Applications incorporating IEEE802.15.4 functionality can be rapidly developed by combining user-developed application software with this library. The facilities provided by this library to applications together with examples of their use are described in more detail in [3].
(1) AES-CBC processing is only available off-line for use under software control. 1.3 RISC CPU and Memory A 32-bit RISC CPU allows software to be run on-chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN513x has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organized within the same linear address space. The device contains 192kBytes of ROM, a choice of 8k, 16k, 32k or 96kBytes of RAM and a 48-byte OTP eFuse memory. 6 JN-DS-JN513x v1.4 Preliminary Jennic 2007 1.4 Peripherals The following peripherals are available on-chip:
Jennic Master SPI port with five select outputs Two UARTs Two programmable Timer/Counters with capture/compare facility Two programmable Sleep Timers and a Tick Timer Two-wire serial interface (compatible with SMbus and I2C) Slave SPI port (shared with digital I/O) Twenty-one digital I/O lines (multiplexed with UARTs, timers and SPI selects) Four-channel, 12-bit, 100ksps Analogue-to-Digital converter Two 11-bit Digital-to-Analogue converters Two programmable analogue comparators Internal temperature sensor and battery monitor User applications access the peripherals using the Hardware Peripheral Library with a simple API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. The JN-RM-2001 Integrated Peripherals API [2] describes this interface in more detail. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 7 Jennic 1.5 Block Diagram Tick Timer Programmable Interrupt Controller From Peripherals 32-bit RISC CPU RAM 8k - 96kB ROM 192kB OTP eFuse 48-byte VB_xx VDD1 VDD2 RESETN XTALIN XTALOUT COMP1M COMP1P COMP2M COMP2P DAC1 DAC2 ADC1 ADC2 ADC3 ADC4 M U X Voltage Regulators 1.8V 32kHz Osc Reset Wakeup WT1 WT0 Clock Generator 2 x Clock Comparator1 Comparator2 DAC1 DAC2 Supply Monitor ADC Temperature Sensor SPI UART0 UART1 Timer0 Timer1 2-wire interface Intelligent Peripheral Wireless Transceiver Security Coprocessor Baseband Controller Modem Radio SPICLK SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO1/SPISEL2 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX DIO4/CTS0 DIO5/RTS0 DIO6/TXD0 DIO7/RXD0 DIO17/CTS1/IP_SEL DIO18/RTS1/IP_INT DIO19/TXD1 DIO20/RXD1 DIO8/TIM0CK_GT DIO9/TIM0CAP/CLK32K DIO10/TIM0OUT DIO11/TIM1CK_GT DIO12/TIM1CAP DIO13/TIM1OUT DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO DIO16/IP_DI M U X RFM RFP VCOTUNE IBAIS Figure 1: JN513x Block Diagram 8 JN-DS-JN513x v1.4 Preliminary Jennic 2007 2 Pin Configurations Jennic K L C _ P I
I K L C _ F S 4 1 O D I
T G _ K C 1 M T 1 1 O D I
I I T U O 0 M T 0 1 O D I
I T U O 1 M T 3 1 O D I
I P A C 1 M T 2 1 O D I
K 2 3 K L C P A C 0 M T 9 O D I
I T G _ K C 0 M T 8 O D I
I 2 D D V 0 D X R 7 O D I
0 D X T 6 O D I
0 S T R 5 O D I
0 S T C 4 O D I
X T F R 4 L E S P S 3 O D I
I O D _ P I
I
D _ F S 5 1 O D I DIO16/IP_DI DIO17/CTS1/IP_SEL VB_DIG2 DIO18/RTS1/IP_INT DIO19/TXD1 DIO20/RXD1 VSS2 RESETN VSS3 VSSS XTALOUT XTALIN VB_SYN VCOTUNE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 5 5 4 5 3 5 2 5 1 5 0 5 9 4 8 4 7 4 6 4 5 4 4 4 3 4 PADDLE 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 1 D D V O C V _ B V M 1 P M O C P 1 P M O C S A B I I P F R F R _ B V M F R F E R V 1 C D A 2 C D A 3 C D A 4 C D A A _ B V Figure 2: 56-pin QFN Configuration (top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DIO2/SPISEL3/RFRX DIO1/SPISEL2 VB_MEM VSS1 DIO0/SPISEL1 SPISEL0 SPIMOSI VB_DIG1 SPIMISO SPICLK COMP2M COMP2P DAC2 DAC1
Note: Please refer to Appendix B.3.11 for important applications information regarding the connection of the PADDLE to the PCB. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 9 Power supplies VB_DIG2, VB_SYN, VB_VCO, VB_RF, VB_A, VB_DIG1, VB_MEM VDD1, VDD2 VSS2, VSS3, VSSS, VSS1, VSSA Description Regulated supply voltage Analogue Peripheral I/O ADC1, ADC2, ADC3, ADC4 VREF DAC1, DAC2 COMP1M, COMP1P, COMP2P, COMP2M Comparator inputs Digital I/O General Radio RESETN XTALOUT, XTALIN Jennic 2.1 Pin Assignment Pin No 3, 13, 15, 21 28, 35, 40 16, 49 7,9,10,39, PADDLE 8 11, 12 14 19 20, 22 24, 25, 26, 27 23 29, 30 17, 18, 31, 32 33 36 34 37 38 41 42 Primary Function SPICLK SPIMOSI SPIMISO SPISEL0 DIO0 DIO1 DIO2 VCOTUNE IBIAS RFP, RFM DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 DIO20 43 44 45 46 47 48 50 51 52 53 54 55 56 1 2 4 5 6 10 Device supplies: VDD1 for analogue, VDD2 for digital Device grounds Reset output/input System crystal oscillator VCO tuning RC network Bias current control Differential antenna port ADC inputs Analogue peripheral reference voltage DAC outputs SPI Clock SPI Master Out Slave In SPI Master In Slave Out SPI Slave Select Output 0 DIO0 or SPI Slave Select Output 1 DIO1 or SPI Slave Select Output 2 DIO2 or SPI Slave Select Output 3 or Radio Receive Control Output DIO3 or SPI Slave Select Output 4 or Radio Transmit Control Output DIO4 or UART 0 Clear To Send Input DIO5 or UART 0 Request To Send Output DIO6 or UART 0 Transmit Data Output DIO7 or UART 0 Receive Data Input DIO8 or Timer0 Clock/Gate Input DIO9 or Timer0 Capture Input or CLK32K DIO10 or Timer0 PWM Output DIO11 or Timer1 Clock/Gate Input DIO12 or Timer1 Capture Input or Antenna Diversity DIO13 or Timer1 PWM Output or Antenna Diversity DIO14 or Serial Interface Clock or Intelligent Peripheral Clock Input DIO15 or Serial Interface Data or Intelligent Peripheral Data Out DIO16 or Intelligent Peripheral Data In DIO17 or UART 1 Clear To Send Input or Intelligent Peripheral Device Select Input DIO18 or UART 1 Request To Send Output or Intelligent Peripheral Interrupt Output DIO19 or UART 1 Transmit Data Output DIO20 or UART 1 Receive Data Input Alternate Function SPISEL1 SPISEL2 SPISEL3, RFRX SPISEL4, RFTX CTS0 RTS0 TXD0 RXD0 TIM0CK_GT TIM0CAP,CLK32K TIM0OUT TIM1CK_GT TIM1CAP TIM1OUT SIF_CLK, IP_CLK SIF_D, IP_DO IP_DI CTS1, IP_SEL RTS1, IP_INT TXD1 RXD1 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 2.2 Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to analogue ground. VDD2 is the power supply for the digital circuitry; it should be decoupled to digital ground. A 10uF tantalum capacitor is required at the common ground star point of analogue and digital supplies. Decoupling pins for the internal 1.8V regulators are provided which require a 100nF capacitor located as close to the device as practical. VB_VCO, VB_RF, VB_A and VB_SYN should be decoupled to analogue ground, while VB_MEM, VB_DIG1 and VB_DIG2 should be decoupled to digital ground. See also Appendix B for connection details. VSSA is the analogue ground, connected to the paddle of the device, while VSSS, VSS1, VSS2, VSS3 are digital ground pins. 2.2.2 Reset RESETN is a bi-directional active low reset pin that is connected to a 45k internal pull-up resistor. It may be pulled low by an external circuit, or can be driven low by the JN513x if an internal reset is generated. Typically, it will be used to provide a system reset signal. Refer to section 6.2, External Reset, for more details. 2.2.3 16MHz System Clock A crystal connected between XTALIN and XTALOUT drives the system clock. A capacitor to analogue ground is required on each of these pins. Refer to section 5.1 16MHz Oscillator for more details. 2.2.4 Radio A 200 balanced antenna (such as a printed circuit antenna) can be connected directly to the radio interface pins RFM and RFP. A single-ended 50 antenna such as a ceramic type or SMA connector for an external antenna requires the addition of a 200/50 2.45GHz balun transformer connected to the antenna pins. The balun differential port should be connected to the antenna port with 200 balanced controlled impedance track. A 50 controlled impedance track should be used to connect the unbalanced port of the balun to the antenna to ensure good impedance matching and reduce losses and reflections. A simple external loop filter circuit consisting of two capacitors and a resistor is connected to VCOTUNE. Refer to section 8.1 Radio for more details. An external resistor (43k) is required between IBIAS and analogue ground to set various bias currents and references within the radio. 2.2.5 Analogue Peripherals Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference. There are four ADC inputs, two comparator inputs and two DAC outputs. The analogue I/O pins on the JN513x can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3 Analogue I/O Cell. In reset and deep sleep the analogue peripherals are all off and the DAC outputs are in a high impedance state. During sleep the ADC and DACs are off, with the DAC outputs in a high impedance state and the comparator may optionally be used as a wakeup. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 11 Jennic VDD1 Analogue I/O Pin Analogue Peripheral VSSA Figure 3 Analogue I/O Cell 2.2.6 Digital Input/Output Digital I/O pins on the JN513x can have signals applied up to 2V higher than VDD2 and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these pins see section 17.2.3 I/O Characteristics. When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal pull up resistors (45k nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled) then their direction is fixed by the function, although the pull up resistors will remain enabled or disabled dependent upon how they were set. A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic. VDD2 Pu OE RPU O I RPROT IE DIO[x] Pin VSS Figure 4: DIO Pin Equivalent Schematic Each DIO pin configuration is programmed by functions in Hardware Peripheral Library. The pin direction is set by calling the vAHI_DioSetDirection() function that enables OE and IE as required, or by enabling a peripheral which uses the cell as part of its I/O. The use of the pull-up resistor Rpu for each pin is controlled through the vAHI_DioSetPullup() routine in the peripheral library, the default state from reset is enabled. In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled these pins may be used to wake up the JN513x from sleep. 12 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 3 CPU The CPU of the JN513x is a 32-bit load and store RISC processor. It has been architected for three key requirements:
Low power consumption for battery powered applications High performance to implement a wireless protocol at the same time as complex applications Efficient coding of high-level languages such as C/C++ provided with the Jennic Software Developers Kit It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are also mapped into this space. The CPU contains a block of 32 32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle (16/32MHz) while those that access memory require a further cycle to allow the memory to respond. The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications. The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects on the stack. The recommended programming method for the JN513x is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger. The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in a RTOS environment. Embedded applications require efficient handling of external hardware events. Exception processing (including reset and interrupt handling) is enhanced by the inclusion of a number of special-purpose registers into which the PC and status register contents are copied as part of the operation of the exception hardware. This means that the essential registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler to start executing in the next cycle. To improve power consumption a number of power-saving modes are implemented in the JN513x, described more fully in section 16 - Power Management and Sleep Modes. One of these modes is the CPU doze mode, under software control, the processor can be shut down and on an interrupt it will wake up to service the request. The CPU clock may be optionally doubled using a 2x clock input. Using the 2x clock mode enables the CPU to clocked at 32MHz and therefore able to sustain 32 MIPs. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 13 Jennic 4 Memory Organisation This section describes the different memories found within the JN513x. The device contains ROM, RAM, OTP memory, the wireless transceiver and peripherals all within the same linear address space. 0xFFFFFFFF 0xF0018000 0xF0008000 0xF0004000 0xF0002000 0xF0000000 RAM
(96kB)
(32kB)
(16kB)
(8kB) Unpopulated Peripherals 0x10000000 0x04000000 RAM Echo 0x00030000 0x00000000 ROM
(192kB) Intelligent Peripheral Memory Block Intelligent Peripheral SPI 2-Wire Interface Timer1 Timer0 UART1 UART0 GPIO Analogue Peripherals PHY Controller Security Coprocessor Baseband Controller System Controller 0xEFFFFFFF 0x980001FF 0x98000000 0x90000013 0x90000000 0x80000017 0x80000000 0x70000013 0x70000000 0x6000001B 0x60000000 0x5000001B 0x50000000 0x4000007F 0x40000000 0x3000007F 0x30000000 0x2000000B 0x20000000 0x10000F23 0x10000F00 0x10000E57 0x10000E00 0x10000DFF 0x10000C00 0x100009FF 0x10000400 0x100000FF 0x10000000 Figure 5: JN513x Memory Map 14 JN-DS-JN513x v1.4 Preliminary Jennic 2007 4.1 ROM The ROM is 192K bytes in size, organized as 48k x 32-bit words and can be accessed by the CPU in a single clock cycle. The ROM contents change for different versions of the device to support differing protocol stacks and applications, all versions carry a default interrupt vector table and interrupt manager. Variants that can be used for application or protocol development carry a boot loader, to allow code from external Flash memory to be bootloaded into RAM at runtime. The operation of the boot loader is described in detail in Application Note JN-AN-1003 Boot Loader Operation [4]. For development variants the interrupt manager routes interrupt calls to the applications soft interrupt vector table contained within RAM. Section 7 contains further information regarding the handling of interrupts. Typical ROM contents for a development variant containing a ZigBee protocol stack is shown in Figure 6. Jennic 0x0002FFFF Unused ZigBee Stack IEEE802.15.4 Stack Boot Loader Interrupt Manager Interrupt Vectors 0x00000F00 0x00000000 Figure 6: Typical ROM contents 4.2 RAM The JN513x contains 8k, 16k, 32k or 96k bytes of high speed RAM organized as 2k, 4k, 8k or 24k x 32-bit words respectively. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered. 4.3 OTP eFuse Memory The JN513x contains 48-bytes of eFuse memory; this is one time programmable memory that is organised as 12 x 32-bit words, 4 words are reserved by Jennic, 2 of which support on-chip MAC ID. The remaining 8 words are fully user programmable, designed to allow the storage of configuration and product information. If secure external memory encryption is enabled then 4 words of the user eFuse are used for this (see section 4.4.1) At a low level, programming of the eFuse requires a sequence of carefully controlled steps, therefore to simplify the procedure, a simple API function call through software is provided that handles the various sequences required, this is described in JN-RM-2001 Integrated Peripherals API [2]. For reliable programming operation, a minimum system supply voltage VDD2 of 3.6V must be provided. If this condition is not satisfied, then programming reliability cannot be guaranteed. 4.4 External Memory An external memory with an SPI interface may be used to provide storage for program code and data for the device when external power is removed. The memory is connected to the SPI interface using select line SPISEL0; this Jennic 2007 JN-DS-JN513x v1.4 Preliminary 15 Jennic select line is dedicated to the external memory interface and is not available for use with other external devices. See Figure 7 for connection details. JN513x SPISEL0 SPIMISO SPIMOSI SPICLK Serial Memory SS SDO SDI CLK Figure 7: Connecting External Serial Memory At reset, the contents of this memory are copied into RAM by the software boot loader. A number of types of memory device may be used with the JN513x boot loader so long as they conform to the format of read instructions issued by the boot loader over the SPI interface. See application note [4] JN-AN-1003 Boot Loader Operation for details on the format of the read command and other details of the boot loader. 4.4.1 Secure External Memory Encryption The contents of the external serial memory may be securely encrypted to protect against system cloning or intrusion. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in eFuse and is programmed through software control. Initially after programming, the encryption feature is not active; this allows the system to continue to operate in an unsecured mode. Enabling of the encryption feature is through software control, once enabled all programming operations require authentication. Full details of the eFuse software functions may be found in JN-RM-2001 Integrated Peripherals API [2]. When bootloading program code from external serial memory, the JN513x automatically accesses the encryption key to execute the decryption process. User program code, does not need to handle any of the decryption process, it is a transparent process. 4.5 Peripherals All peripherals have their registers mapped into the memory space. Access to these registers requires 3 clock cycles. Applications have access to the peripherals through the peripherals library, which presents a high-level view of the peripherals functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and operation of power and interrupts with the IEEE802.15.4 software protocol stack allowing bug-free application code to be developed more rapidly. See JN-RM-2001 Integrated Peripherals API [2] for more details. 4.6 Unused Memory Addresses Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated. 16 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 5 System Clocks Two separate oscillators are used to provide system clocks: a crystal controlled 16MHz oscillator, using an external crystal and an internal, RC based 32kHz oscillator. 5.1 16MHz Oscillator The JN513x contains the necessary on-chip components to build a 16 MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic and layout of these components are shown in Figure 8. The two capacitors, C1 and C2, should be 15pF 5% and use a COG dielectric. Due to the small size of these capacitors, it is important to keep the traces to the external components as short as possible. The on-chip transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal resistor R1. The electrical specification of the oscillator can be found in section 17.3.6. For detailed application support and specification of the crystal required see Appendix B.1. JN513x XTALIN R1 XTALOUT C1 C2 Figure 8: Crystal oscillator connections The clock generated by this oscillator provides the reference for most of the JN513x subsystems, including the transceiver, processor, memory and digital and analogue peripherals. The clock for the processor, RAM and ROM may be optionally driven by a 2x clock that effectively clocks these at 32MHz. 5.2 32kHz Oscillator The internal 32kHz RC oscillator requires no external components. It provides a low speed clock for use in sleep mode. The clock is used for timing the length of a sleep period (see section 16 Power Management and Sleep Modes) and also to generate the system clock used internally during reset. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz 30%. To make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the more accurate 16MHz oscillator may be applied. The calibration factor is derived through software, details can be found in section 12.3.1. For detailed electrical specifications, see section 17.3.5. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 17 Jennic 6 Reset A system reset initialises the device to a predefined state and forces the CPU to start program execution from the reset vector. The reset process that the JN513x goes through is as follows. When power is applied, the 32kHz oscillator starts up and stabilises, which takes approximately 100sec. At this point, the 16MHz crystal oscillator is enabled and power is applied to processor and peripheral logic. The logic blocks are held in reset until the 16MHz crystal oscillator stabilises, typically this takes 2.5ms. Once the oscillator is up and running the internal reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector, consisting of initialisation code and then optionally the resident Boot Loader (described in reference [4]). Section 17.3.1 provides detailed electrical data and timing. The JN513x has four sources of reset:
Internal Power-on Reset External Reset Software Reset Brown-Out-Detect
Note: When the device exits a reset condition, device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, then the device must be held in reset until the operating conditions are met. 6.1 Internal Power-on Reset For the majority of applications the internal power-on reset is capable of generating the required reset signal. When power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD reaches the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN pin. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal reset signal is then removed and the CPU is allowed to run. VDD Internal RESET RESETN Pin Figure 9: Internal Power-on Reset 18 JN-DS-JN513x v1.4 Preliminary Jennic 2007 If the application requires a power supply reset to be used, i.e. removing and then applying VDD, it is important that the device decoupling capacitors are completely discharged before the VDD is re-applied. Failure to do so may inhibit the operation of the internal power-on reset circuit. If complete discharge is difficult to achieve then it is recommended that the external reset circuit, as shown in Figure 10, be used. Jennic VDD R1 10k C1 100nF JN513x RESETN Figure 10: External Reset Generation The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin. 6.2 External Reset An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN513x is held in reset while the RESETN pin is low and when the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the internal reset process starts. Multiple devices may connect to the RESETN pin in an open-collector mode. The JN513x has an internal pull-up resistor although an external pull-up resistor is recommended when multiple devices connect to the RESETN pin. The pin is an input for an external reset, an output during the power-on reset and may optionally be an output during a software reset. No devices should drive the RESETN pin high. RESETN pin Reset Internal Reset Figure 11: External Reset 6.3 Software Reset A system reset can be triggered at any time by calling the Software Reset function, vAHI_SwReset() from the peripheral library. This function can be executed within a users application, upon detection of a system failure for example. The RESETN line can be driven low by the JN513x to provide a reset to other devices in the system (e.g. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 19 Jennic external sensors). The reset output feature can be enabled or disabled for the software generated reset using the function vAHI_DriveResetOut()within the peripheral library (the default state is disabled). 6.4 Brown-out Detect A brown-out detect module is used to monitor the supply voltage to the JN513x; this can be used whilst the device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN513x to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it. Hysteresis is built into the brown out detect module this is nominally 100mV. The threshold voltage is selectable at levels of 2.1V, 2.4V, 2.5V or 2.6V through software control, this is described in JN-RM-2001 Integrated Peripherals API [2]. 20 JN-DS-JN513x v1.4 Preliminary Jennic 2007 7 Interrupt System The interrupt system on JN513x is a hardware-vectored interrupt system. The JN513x provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor mode. Interrupt sources and their vector locations are listed in Table 1 below:
Jennic Vector Location Interrupt Source 0x100 Reset 0x200 Bus Error 0x500 Tick Timer 0x600 Alignment Illegal Instruction 0x700 Hardware Interrupts 0x800 0xC00 System Call Trap 0xE00 Interrupt Definition Software or hardware reset Bus error or attempt to access invalid physical address Tick Timer expiry Load/Store to naturally not aligned location Illegal instruction in instruction stream Hardware Interrupt System Call Initiated by software (l.sys instruction) Caused by l.trap instruction Table 1: Interrupt Vectors 7.1 System Calls Executing the l.sys instruction causes a system call interrupt to be generated. The purpose of this interrupt is to allow a task to switch into supervisor mode when a real time operating system is in use, see section 3 for further details. It also allows a software interrupt to be issued, as does execution of the l.trap instruction. 7.2 Processor Exceptions 7.2.1 Bus Error A bus error exception is generated when software attempts to access a memory address that does not exist, or is not populated with memory or peripheral registers. 7.2.2 Alignment Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc. 7.2.3 Illegal Instruction If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal instruction exception. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 21 Jennic 7.3 Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library. Further details of interrupts are provided for the functions in their respective sections in this datasheet. Interrupts are used to wake the JN513x from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the wake-up timers and analogue comparator interrupts remain powered to bring the JN513x out of sleep. Wake-up Timers Baseband Controller Security Coprocessor DIO Pins UART0 UART1 Timer0 Timer1 2-wire Serial Interface SPI Controller Intelligent Peripheral Analogue Peripheral Programmable Interrupt Controller Hardware Interrupt Figure 12: Programmable Interrupt Controller 22 JN-DS-JN513x v1.4 Preliminary Jennic 2007 8 Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, an O-QPSK modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standards-based wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band. IEEE802.15.4 wireless functionality is provided with the transceiver and the protocol software described in JN-RM-2002 802.15.4 Stack [3]. Applications interface to the protocol software via an API interface that corresponds to the SAP interfaces defined in the IEEE Std 802.15.4-2006 [1]
Jennic 8.1 Radio LOI LOQ PA PA Power TX RX Calibration DAC IDATA DAC QDATA VGA PA (I) Trim VGA PA (Q) Trim LNA LOI LOQ VGA1 VGA2 IF DATA ADC LOQ 90 LOI 0 PLL Calibration Reference
& BIAS VCO AGC Figure 13: Radio Architecture The radio comprises a low-IF receive path and a direct up-conversion transmit path, which converge at the TX/RX switch. This switch includes the necessary matching components such that a 200 differential antenna may be directly connected without external components. Alternatively, a balun can be used for single ended antennas. The 16MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Lock Loop (PLL) that has a loop filter comprising 3 external components. A programmable charge pump is also used to tune the loop characteristic. Finally, quadrature (I and Q) local oscillator signals for the mixer drives are derived. The receiver chain starts with the low noise amplifier / mixer combination whose outputs are passed to the polyphase bandpass filter. This filter provides the channel definition as well as image frequency rejection. The signal is then passed to two variable gain amplifier blocks. The gain control for these stages, and the bandpass filter, is derived in the automatic gain control (AGC) block within the Modem. The signal is conditioned with the anti-alias low pass filter, before being converted to a digital signal with a flash ADC. In the transmit direction, the digital I and Q streams from the Modem are passed to I and Q quadrature DAC blocks which are buffered and low-pass filtered, before being applied to the modulator mixers. The summed 2.4 GHz signal is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of six settings. The output of the PA drives the antenna via the RX/TX switch. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 23 Jennic 8.1.1 Radio External components The VCO loop filter requires three external components and the IBIAS pin requires one external component as shown in Figure 14. These components should be placed close to the JN513x pins and analogue ground. VCOTUNE 4k7 1%
15 19 3n3F VB_VCO 100nF 330pF VSSA IBIAS 43k 1%
VSSA Figure 14: VCO Loop Filter and IBIAS The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN513x and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for internal regulators is required as described in section 2.2.1, Power Supplies. 8.1.2 Antenna Diversity Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an antenna system. It allows the radio to switch between two antennas that have very low correlation between their received signals. Typically, this is achieved by spacing two antennas around 0.25 wavelengths apart or by using two orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can switch to the other antenna for the retry, with a different probability of success. The JN513x provides two outputs that can be used to control an antenna switch; this enables antenna diversity to be implemented easily. DIO12 is asserted on odd numbered retires and DIO13 is asserted on the first transmit and even numbered retries. 24 JN-DS-JN513x v1.4 Preliminary Jennic 2007 8.2 Modem The Modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. Jennic RX O-QPSK Demodulation AGC Symbol Detection
(Despreading) RX Data Interface TX O-QPSK Modulation I Q I Q Pulse Shaping Spreading TX Data Interface Gain IF Signal I Q Figure 15: Modem Architecture The transmitter receives symbols from the baseband processor and uses the spreading function to map each unique 4-bit symbol to a 32-chip Pseudo-random Noise (PN) sequence. Offset-QPSK modulation and half-sine pulse shaping is applied to the resultant spreading sequence to produce two independent quadrature phase signals (I and Q), which are subsequently converted to analogue voltages in the radio transmit path. The Automatic Gain Control (AGC) monitors the received signal level and adjusts the gain of the amplifiers in the radio receiver to ensure that the optimum signal amplitude is maintained during reception. The demodulator performs digital IF down-conversion and matched filtering and is extremely tolerant to carrier frequency offsets in excess of 80ppm without suffering any significant degradation in performance. Symbol detection and synchronization is performed using direct sequence correlation techniques in conjunction with searches for the Preamble and Start-of-Frame Delimiter (SFD) fields contained in the transmitted IEEE 802.15.4 Synchronization Header (SHR). Features are provided to support network channel selection algorithms include Energy Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel Assessment (CCA). The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the IEEE 802.15.4 ED function. The LQI is defined in the IEEE 802.15.4 standard as a characterization of the strength and/or data quality of a received packet. The Modem produces a signal quality metric based upon correlation magnitudes, which may be used in conjunction with the ED value to formulate the LQI. The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. 8.3 Baseband Processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to Jennic 2007 JN-DS-JN513x v1.4 Preliminary 25 Jennic implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint and coordinator nodes, using the services provided by the baseband processor. Tx Bitstream Append Checksum Serialiser Status Supervisor Radio Protocol Timing Engine CSMA CCA Backoff Control Rx Bitstream Verify Checksum Control Deserialiser Encrypt Port AES AES Codec Codec Inline Security Decrypt Port Tx/Rx Frame Buffer Protocol Timers Figure 16: Baseband Processor Processor Bus 8.3.1 Transmit A transmission is performed by software writing the data to be transferred into the Tx/Rx Frame Buffer, together with parameters such as the destination address and the number of retries allowed, and programming one of the protocol timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor controls the sequencing of the radio and modem to perform the type of transmission required. It can perform all the algorithms required by IEEE802.15.4 such as CSMA/CA, GTS without processor intervention including retries and random backoffs. When the transmission begins, the header of the frame is constructed from the parameters programmed by the software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared for transmission. During the passage of the bitstream to the modem, it passes through a CRC checksum generator that calculates the checksum on-the-fly, and appends it to the end of the frame. If using slotted access, it is possible for a transmission to overrun the time in its allocated slot; the Baseband Processor handles this situation autonomously and notifies the protocol software via interrupt, rather than requiring it to handle the overrun explicitly. 8.3.2 Reception In a reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is directed into the Tx/Rx Frame Buffer where both header and frame data can be read by the protocol software. An interrupt may be provided on receipt of the frame header. As the frame data is being received from the modem it is passed through a checksum generator; at the end of the reception the checksum result is compared with the checksum at the end of the message to ensure that the data has been received correctly. During reception, the modem determines the Link Quality, which is made is made available at the end of the reception as part of the requirements of IEEE802.15.4. 26 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 8.3.3 Auto Acknowledge Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN513x baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence. The JN513x baseband processor can also request an acknowledge for packets being transmitted and handle the reception of acknowledged packets without processor intervention. 8.3.4 Beacon Generation In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU intervention. 8.3.5 Security The baseband processor supports the transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm transparently to the CPU. This is done by passing incoming and outgoing data through an in-line security engine that is able to perform encryption and decryption operations on-the-fly, resulting in minimal processor intervention. The CPU must provide the appropriate encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same time as the rest of the frame data and setup information. During reception, the CPU must look up the key and provide it from information held in the header of the incoming frame. However, the hardware of the security engine can process data much faster than the incoming frame data rate. This means that it is possible to allow the CPU to receive the interrupt from the header of an incoming packet, read where the frame originated, look up the key and program it to the security hardware before the end of the frame has arrived. By providing a small amount of buffering to store incoming data while the lookup process is taking place, the security engine can catch up processing the frame so that when the frame arrives in the receive frame buffer it is fully decrypted. 8.4 Security Coprocessor As well as being used during in-line encryption/decryption operations over a streaming interface and in external memory encryption, it is also possible to use the AES core as a coprocessor to the CPU of the JN513x. To allow the hardware to be shared between the two interfaces an arbiter ensures that the streaming interface to the AES core always has priority, to ensure that in-line processing can take place at any time. Some protocols (for example ZigBee) require that security operations can be performed on buffered data rather than in-line. A hardware implementation of the encryption engine significantly speeds up the processing of the contents of these buffers. The AES library for the JN513x provides two operations vAHI_SecurityEncode() and vAHI_SecurityDecode() which utilise the encryption engine in the device and allow the contents of memory buffers to be transformed. Information such as the type of security operation to be performed and the encrypt/decrypt key to be used must also be provided. Processor Interface In-line Interface r e t i b r A AES Block Encrpytion Controller AES Encoder Figure 17: Security Coprocessor Architecture n o i t a r e n e G y e K Jennic 2007 JN-DS-JN513x v1.4 Preliminary 27 Jennic 9 Digital Input/Output There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual module sections for a full description of the alternate peripherals functions. From reset, all peripherals are off and the DIO pins are configured as inputs with the internals pull-ups turned on. SPICLK, MOSI, MISO SPISEL<0>
DIO<20:0>
MUX Chip Pins SPI Port UART 0 UART 1 Counter/Timer 0 Counter/Timer 1 2-Wire Serial Interface Intelligent Peripheral RFTX SPISEL<4:0>
TxD RxD RTS CTS TxD RxD RTS CTS TIM0CK_GT TIM0CAP TIM0OUT TIM1CK_GT TIM1CAP TIM1OUT SIF_CLK SIF_D IP_CLK IP_DI IP_DO IP_SEL IP_INT RFTX Processor Bus
(Address, Data, Interrupts) GPIO Data / Direction Registers DIO<20:0>
Figure 18: DIO Block Diagram When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin can be controlled individually with the direction being set using the vAHI_DioSetDirection() function. Reading and writing to the pins is controlled using the vAHI_DioSetOutput() and u32AHI_DioReadInput() functions. The individual pull-up resistors, RPU, are selected using the vAHI_DioSetPullup() function. When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is sleeping, these interrupts become events that can be used to wake the device up. Selection of the interrupt transition is done using vAHI_DioInterruptEdge(). Enabling and masking of DIO interrupts is done using vAHI_DioInterruptEnable() while the status of a DIO interrupt is given by u32AHI_DioInterruptStatus(). See section 16 Power Management and Sleep Modes for further details on sleep and wakeup. 28 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 10 Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN513x and peripheral devices. The JN513x operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN513x CPU. The SPI includes the following features:
Full-duplex, three-wire synchronous data transfer Programmable bit rates up to 16Mbps Programmable transaction size of 8,16 or 32 bits Supports standard SPI modes 0, 1, 2, 3 to allow control over the relationship between clock and transmit /
receive data Automatic slave select generation (up to 5 slaves) Maskable transaction complete interrupt LSB First or MSB First Data Transfer 16 MHz Clock Divider 31 15 7 Data Buffer 0 e g d E k c o C l t c e e S l I V D a t a D SPI Bus Cycle Controller N E L _ R A H C B S L Select Latch SPICLK SPIMISO SPIMOSI SPISEL [4..0]
Figure 19: SPI Block Diagram The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously. There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. Master-
Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN513x. The JN513x provides five slave selects, SPISEL0 to SPISEL4 to allow five SPI peripherals on the bus. SPISEL0 is a dedicated pin and SPISEL1 to 4, are alternate functions of pins DIO0 to 3 respectively. This allows a serial flash memory to be connected to SPISEL0 and download to internal RAM via software from reset. The interface can transfer 8, 16 or 32 bits without software intervention and can keep the slave select lines asserted between transfers when required, to enable longer transfers to be performed. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 29 Jennic Slave 0 S S Flash Memory I S C O S Slave 1 S S User Defined I S C O S Slave 2 S S User Defined I S C O S Slave 3 S S User Defined I S C O S Slave 4 S S User Defined I S C O S SPISEL1 SPISEL2 SPISEL0 SPISEL3 SPISEL4 7 3 8 3 1 4 2 4 3 4 JN513x SPIMOSI SPICLK SPIMISO 36 33 34 Figure 20: Typical JN513x SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN513x supports transfers at selectable data rates from 16MHz to 250kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable. The clock polarity controls if SCLK is high or low between transfers (and hence the polarity of the first clock edge in a transfer). The clock phase and polarity determines which edge of SPICLK is used by the JN513x to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. These options are specified using the vAHI_SpiConfigure() function. SPICLK Polarity Phase Mode Description 0 0 1 1 0 1 0 1 0 1 2 3 SPICLK is low when idle the first edge is positive. Valid data it output on SPIMOSI before the first clock and changes every negative edge. SPIMISO is sampled every positive edge. SPICLK is low when idle the first edge is positive. Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every negative edge. SPICLK is high when idle the first edge is negative. Valid data is output on SPIMOSI before the first clock edge and is changed every positive edge. SPIMISO is sampled every negative edge. SPICLK is high when idle the first edge is negative. Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled every positive edge. The slave select outputs, SPISELn, are controlled using the vAHI_SpiSelect() function. If more than one SPISEL line is to be used in a system they must be used in numerical order, for instance if 3 SPI select lines are to be used, they must be SPISEL0, 1 and 2. The number of SPISEL lines to be used in a system is controlled using vAHI_SpiConfigure(). A SPISEL line can be automatically deasserted between transactions if required, or it may stay asserted over a number of transactions until removed by a call to vAHI_SpiSelect(). For devices such as 30 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic memories where a large amount of data can be received by the master by continually providing SPICLK transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the whole of the transfer. A transaction commences with the SPI bus being set to the correct configuration using vAHI_SpiConfigure(), and then the slave device being selected using vAHI_SpiSelect(). Transmit commences using the vAHI_SpiStartTransferxx() function (where xx is either 8, 16 or 32 bits). This will cause data to be placed in the FIFO data buffer and be clocked out, at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of data bits is being received from the slave as it transmits. The data that is received during this transmission can be read using u32AHI_SpiReadTransferxx() (again xx is either 8, 16 or 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be sent from a slave, it can perform a vAHI_SpiStartTransferxx() using dummy transmit data. An interrupt can be generated when the transaction has completed when enabled by vAHI_SpiConfigure(). Alternatively the interface can be polled using the bAHI_SpiPollBusy() or vAHI_SpiWaitBusy() functions. If a slave device wishes to signal the JN513x indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 31 Jennic 10.1 Programming Example The following code example shows how to initialise the SPI and perform a simple read from a slave device. The device being read requires 40 clocks to send an 8-bit instruction, a 24-bit address and retrieve the 8-bit data. This cannot be achieved by a single transfer, so multiple transfers are combined without the automatic de-assertion of the selects. The waveforms generated by the example code are illustrated in Figure 21. Programming Example PRIVATE void vReadFromFlash(uint32 u32Addr, uint32 u32NumWords, uint32 *pau32Buffer )
#define FLASHREADCMD 0x03
#define SPI_SLCT_NONE 0x00 uint32 u32Temp;
uint32 i;
vAHI_SpiConfigure( 1, /* number of slave select lines in use */
E_AHI_SPIM_MSB_FIRST, /* send data MSB first */
E_AHI_SPIM_TXNEG_EDGE, /* TX data to change on negative edge */
E_AHI_SPIM_RXNEG_EDGE, /* RX data to change on negative edge */
0, /* Generate 16MHz SPI clock */
E_AHI_SPIM_INT_DISABLE, /* Disable SPI interrupt */
E_AHI_SPIM_AUTOSLAVE_DSABL); /* Disable auto slave select
/* combine read cmd & addr into single value to be sent over SPI */
u32Temp = (u32Addr & 0x00FFFFFF) | (FLASHREADCMD << 24);
/* select spi device */
vAHI_SpiSelect(E_AHI_SPIM_SLAVE_ENBLE_0);
/* send read cmd and address location */
vAHI_SpiStartTransfer32(u32Temp);
vAHI_SpiWaitBusy();
for (i=0; i<=u32NumWords; i++)
/* read data 4 bytes at a time */
vAHI_SpiStartTransfer32(u32Addr);
vAHI_SpiWaitBusy();
/* copy into temp variable */
u32Temp = u32AHI_SpiReadTransfer32();
/* copy to buffer */
memcpy( (pau32Buffer+i), &u32Temp, sizeof(u32Temp) );
/* deselect select spi device */
vAHI_SpiSelect(SPI_SLCT_NONE);
32 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Instruction Transaction Jennic SPISEL SPICLK SPIMOSI SPIMISO SPISEL SPICLK SPIMOSI SPIMISO 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction (0x03) 24-Bit Address 22 21 3 2 1 0 23 MSB Read Data Bytes Transaction(s) 1-N 0 1 2 3 4 5 7 8 9 10 28 29 30 31 Changes every spi clk but value is unused by peripheral 6 5 4 3 2 1 0 7 MSB 6 5 3 2 1 7 MSB Octet 0 Octet 4N-3 Octet 4N-1 0 LSB Figure 21: SPI Transaction Waveforms (Mode = 0) Jennic 2007 JN-DS-JN513x v1.4 Preliminary 33 Jennic 11 Intelligent Peripheral Interface The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor that requires a wireless peripheral. As an example, the JN513x may provide a complete IEEE802.15.4, ZigBee or other wireless network to a phone, computer, PDA, set-top box or games console. No resources are required from the main processor compared to a transceiver as the complete wireless protocol may be run on the internal JN513x CPU. The wireless peripheral may be controlled via one of the UARTs but the IP interface is intended to provide a high-speed, low-processor-overhead interface. The intelligent peripheral interface is a SPI slave interface and uses pins shared with other DIO signals. The interface is designed to allow message passing and data transfer. Data received and transmitted on the IP interface is copied directly to and from a dedicated area of memory without intervention from the CPU. This memory area, the intelligent peripheral memory block, contains 64 32-bit word receive and transmit buffers. JN513x Intelligent Peripheral Interface IP_INT IP_DO IP_DI IP_SEL IP_CLK SPIINT SPIMISO SPIMOSI SPISEL SPICLK System Processor
(e.g. in cellphone, computer) SPI MASTER CPU Figure 22: Intelligent Peripheral Connection The interface conforms to the SPI protocol as described in section 10. It is possible to select the clock edge of IP_CLK on which data on the IP_DIN line of the interface is sampled, and the state of data output IP_DOUT is changed. The order of transmission is MSB first. The IP_DO data output is tri-stated when the device is inactive, i.e. the device is not selected via IP_SEL. An interrupt output line IP_INT is available so that the JN513x can indicate to an external master that it has data to transfer. The IP interface signals IP_CLK, IP_DO, IP_DI, IP_SEL, IP_INT are alternate functions of pins DIO14 to 18 respectively. 11.1 Data Transfer Format Transfers are started by the remote processor asserting the IPSEL line and terminated by the remote processor de-
asserting IP_SEL. Data transfers are bi-directional and traffic in both directions has a format of status byte, data length byte (of the number of 32-bit words to transfer) and data packet (from the receive and transmit buffers). The first byte transferred in either direction is a status byte with the following format:
Bit Field Description 7:2 1 0 RSVD TXQ RXRDY Reserved, set to 0. 1: Data queued for transmission 1: Buffer ready to receive data Table 2: IP Status Byte Format If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status byte was 1), the next byte to be transmitted is the data length in words. If either the JN513x or the remote processor 34 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic has no data to transfer, then the data length should set to zero. The transaction can be terminated by the master after the status byte has been sent if it is not possible to send data in either direction. This may be because neither party has data to send or because the receiver does not have a buffer available. If the data length is non-zero, the data in the JN513x transmit memory buffer is sent, beginning at the start of the buffer. At the same time that data bytes are being sent from the transmit buffer, the JN513x receive buffer is being filled with incoming data, beginning from the start of the buffer. The remote processor, acting as the master must determine the larger of its incoming or outgoing data transfers and deassert IP_SEL when all of the transmit and receive data has been transferred. The data is transferred into or out of the buffers starting from the lowest address in the buffer, and each word is assembled with the MSB first on the serial data lines. IP_SEL IP_CLK IP_DI IP_DO Status (8 bit) padding (8 bit) padding (8 bit) data length or 0s (8 bit) Status (8 bit) data length or 0s (8 bit) N words of data N words of data Figure 23: Intelligent Peripheral Data Transfer Waveforms 11.2 JN513x Initiated Data Transfer To send data, the data is written into either buffer 0 or 1 of the intelligent peripheral memory area. Then the buffer number is written together with the data length using bAHI_IpSendData(). If the call is successful, the interrupt line IP_INT will signal to the remote processor that there is a message ready to be sent from the JN513x. When a remote processor starts a transfer to the JN513x by deasserting IP_SEL, then IP_INT is deasserted. If the transfer is unsuccessful and the data is not output then IP_INT is reasserted after the transfer to indicate that data is still waiting to be sent. The interface can be configured to generate an internal interrupt whenever a transaction completes (for example IP_SEL becomes inactive after a transfer starts). It is also possible to mask the interrupt. The end of the transmission can be signalled by an interrupt, or the interface can be polled using the function bAHI_IpTxDone() To receive data the interface must first be initialised using vAHI_IpEnable(). When this is done, the bit RXRDY sent in the status byte from the IP block will show that data can be received by the JN513x. Successful data arrival can be indicated by an interrupt, or the interface can be polled using bAHI_IpRxDataAvailable(). Data is then retrieved using bAHI_IpReadData(). To send and receive at the same time, the transmit and the receive buffers must be set to be different. 11.3 Remote Processor Initiated Data Transfer The remote processor (master) may initiate a transfer to send data to the JN513x by asserting the slave select pin, IP_SEL, and generating its status byte on IP_DI with TXRDY set. After receiving the status byte from the JN513x, it should check that the JN513x has a buffer ready by reading the RXRDY bit. If the RXRDY bit is 0 indicating that the JN513x cannot accept data, it should terminate the transfer by deasserting IP_SEL unless it is receiving data from the JN513x. If the RXRDY bit is 1, indicating that the JN513x can accept data, then the master should generate a further 8 clocks on IP_CLK in order to transfer its own message length on IP_DI. The master should continue clocking the interface until sufficient clocks have been generated to send all the data specified in the length field to the JN513x. The master should then deassert IP_SEL to show the transfer is complete. The master may initiate a transfer to read data from the JN513x by asserting the slave select pin, IP_SEL, and generating its status byte on IP_DI with RXRDY set. After receiving the status byte from the JN513x, it should check that the JN513x has a buffer ready by reading the TXRDY bit. If the TXRDY bit is 0, indicating that the JN513x does not have data to send, it should terminate the transfer by deasserting IP_SEL unless it is transmitting data to the JN513x. If the TXRDY bit is 1, indicating that the JN513x can send data, then the master should generate a further 8 clocks on IP_CLK in order to receive the message length on IP_DO. The master should continue clocking the interface until sufficient clocks have been generated to receive all the data specified in the length field from the JN513x. The master should then deassert IP_SEL to show the transfer is complete. Data can be sent in both directions at once and the master must ensure both transfers have completed before deasserting IP_SEL. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 35 Jennic 12 Timers 12.1 Peripheral Timer / Counters Two general-purpose timer / counter units are available that can be independently configured to operate in one of five modes. The timers have the following features:
16-bit prescaler, divides system clock by of 2 prescale value as the clock to the timer Clocked from internal system clock 16-bit counter, 16-bit Rise and Fall (period) registers Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal Counter: counts number of transitions on external event signal. Can use low-high, high-low or both transitions PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse. Can set period and mark-space ratio Capture: measures times between transitions of an applied signal. Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes Int Enable INT Interrupt Generator
S R PWM/Delta-
Sigma OE TIMxOUT TIMxCAP Capture Generator Capture Enable Sys Clk Prescaler Rise Fall Delta-Sigma PWM/
Gate Counter PWM/
Reset Gate TIMxCK_GT Reset Generator Edge Select S/w Reset System Reset Single Shot Figure 24: Timer Unit Block Diagram The clock source for the timer unit is fed from the 16MHz system clock. This clock passes to a 16-bit prescaler where a value of 0 leaves the clock unmodified and other values divide it by 2 prescale value. For example, a prescale value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The value of the prescaler is set using the vAHI_TimerEnable() function. 36 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic The counter is optionally gated by a signal on the clock / gate input (TIMxCK_GT). If the gate function is selected
(using vAHI_TimerClockSelect()) the counter is frozen when the clock/gate input is high. If enabled using the vAHI_TimerEnable() function, an interrupt is generated whenever counter is equal to the value stored in either of the High or Low registers. The internal Output Enable (OE) signal enables or disables the timer output. The Timer 0 signals CK_GT, CAP and OUT are alternate functions of pins DIO8, 9 and 10 respectively and Timer 1 signals CK_GT, CAP and OUT are alternate functions of pins DIO11, 12, and 13 respectively. Selection of either the Timer or DIOx functionality is through software, in either case the timer still functions internally. 12.1.1 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode allows the user to specify an overall cycle time and pulse length within the cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by the cycle time. In this mode, the cycletime and low periods of the PWM output signal can be set by the values of two independent 16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset and the cycle repeats. Depending upon the mode of operation either the vAHI_TimerStartRepeat() function or the vAHI_TimerStartSingleShot() is used to set the values of the High and Low registers. The PWM waveform is available on TIMxOUT when the output driver is enabled using vAHI_TimerEnable(). Rise Fall Figure 25: PWM Output Timings 12.1.2 Capture Mode The capture mode can be used to measure the time between transitions of a signal applied to the capture input
(TIMxCAP). The mode is selected and the counter started by vAHI_TimerStartCapture(). On the next low-to-
high transition of the captured signal, the count value is stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register. The pulse width is the difference in counts in the two registers multiplied by the driving clock (in all cases this must be the 16MHz clock and so the prescaler must be set to 0). The counter is stopped and Low and High registers read with vAHI_TimerReadCapture(). The values in the High and Low registers will be updated whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the mode was started. Therefore, if multiple pulses are seen on TIMxCAP before the counter is stopped only the last pulse width will be stored. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 37 Jennic CLK CAPT Rise Fall 9 tRISE 5 3 4 tRISE tFALL tFALL Capture Mode Enabled x 9 3 x 14 7 Figure 26: Capture Mode 12.1.3 Counter / Timer Mode The counter/timer can be used to generate timing or count interrupts for software to use. As a timer the clock source is from the system clock, prescaled if required. The timer period is programmed into the Fall register and the Fall register match interrupt enabled. The timer is started either as a single-shot or repeating timer
(vAHI_TimerStartSingleShot() or vAHI_TimerStartRepeat()), and generates an interrupt when the counter reaches the Fall register value. When used to count external events on TIMxCK_GT the clock source is selected from the input pin and the number of events programmed into the Fall register. The Fall register match interrupt is enabled and the counter started, usually in single shot mode. An interrupt is generated when the programmed number of low-to-high transitions is seen on the input pin. 12.1.4 Delta-Sigma Mode A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be implemented with up to 16-bit resolution. This requires that a resistor-capacitor network is placed between the output DIO pin and digital ground. A stream of pulses with digital voltage levels is generated which is integrated by the RC network to give an analogue voltage. A conversion time is defined in terms of a number of clock cycles. The width of the pulses generated is the period of a clock cycle. The number of pulses output in the cycle, together with the integrator RC values will determine the resulting analogue voltage. For example, generating approximately half the number of pulses that make up a complete conversion period will produce a voltage on the RC output of VDD1/2, provided the RC time constant is chosen correctly. During a conversion, the pulses will be pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on the output of the RC network. The output signal is asserted for the number of clock periods defined in the High register set by vAHI_TimerStartDeltaSigma(), with the total period being 216 cycles. For the same value in the High register the pattern of pulses on subsequent cycles is different, due to the pseudo-random distribution. The delta-sigma convertor output can operate in a Return-To-Zero (RTZ) or a Non-Return-to-Zero (NRZ) mode. The NRZ mode will allow several pulses to be output next to each other. The RTZ mode ensures that each pulse is separated from the next by at least one period. This improves linearity if the rise and fall times of the output are different to one another. Essentially, the output signal is low on every other output clock period, and the conversion cycle time is twice the NRZ cycle time ie 217 clocks. The integrated output will only reach half VDD2 in RTZ mode, since even at full scale only half the cycle contains pulses. Figure 27 and Figure 28 illustrate the difference between RTZ and NRZ for the same programmed number of pulses. 38 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 1 2 3 N 1 2 3 N 217 Conversion cycle 1 Conversion cycle 2 Figure 27: Return To Zero Mode in Operation 1 2 3 N 1 2 3 N Conversion cycle 1 216 Conversion cycle 2 Figure 28: Non-Return to Zero Mode 12.1.5 Timer / Counter Application Figure 29 shows an application of the JN513x timers to provide closed loop speed control. Timer 0 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls the power in the DC motor. Timer 1 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application software executing the control algorithm.
+12V JN513x 1N4007 M Tacho Timer 0 Timer 1 CLK/GATE CAPTURE PWM CLK/GATE CAPTURE PWM 48 50 51 52 53 54 IRF521 1 pulse/rev Figure 29: Closed Loop PWM Speed Control Using JN513x Timers Jennic 2007 JN-DS-JN513x v1.4 Preliminary 39 Jennic 12.2 Tick Timer The JN513x contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system, as a high-precision timing reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include:
32-bit counter 28-bit match value Maskable timer interrupt Single-shot, Restartable or Continuous modes of operation SysClk
Run Match Value Counter Reset Mode Control Mode Match
Tick Timer Interrupt
Int Enable Figure 30: Tick Timer The Tick Timer is clocked from the CPU clock (16 or 32MHz), which is fed to a 32-bit wide resettable up-counter, gated by a signal from the mode control block. A match register allows comparison between the counter and a programmed value. The match value, measured in 16 or 32MHz clock cycles can be programmed using vAHI_TickTimerInterval(), in the range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is enabled and used in controlling the counter in the different modes. The mode is programmed using vAHI_TickTimerConfigure(), which also resets the counter to zero. The interrupt is enabled by vAHI_TickTimerIntEnable(). The interrupt state is returned by bAHI_TickTimerIntStatus() and if an interrupt is generated it can be cleared by vAHI_TickTimerIntPndClr(). If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached. The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The counter can be restarted by reprogramming the mode using vAHI_TickTimerConfigure(). If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode, except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be generated when the match value is reached if it is enabled. Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not reset but continues to count. An interrupt will be generated when the match value is reached if enabled. 40 JN-DS-JN513x v1.4 Preliminary Jennic 2007 12.3 Wakeup Timers Two 32-bit wakeup timers are available in the JN513x driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt, if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 16 for further details on how they are used during sleep periods. Features include:
Jennic 32-bit down-counter Optionally runs during sleep periods Clocked from 32 kHz RC oscillator A wakeup timer consists of a 32-bit down counter clocked from the 32 kHz internal clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event is required, the timer interrupt should be enabled using vAHI_WakeTimerEnable() before loading the count value for the period. The count value is loaded using vAHI_WakeTimerStart() and causes the counter to begin to count down to zero; the counter can be stopped at any time using vAHI_WakeTimerStop(). The counter will remain at the value it contained when the timer was stopped and no interrupt will be generated. The status of the timers can be checked using the u8AHI_WakeTimerStatus() function, which indicates if the timers are running. The timers can be checked to see if they have expired using u8AHI_WakeTimerFiredStatus() which is useful when the timer interrupts are masked. If a timer has expired then the fired status will be reset by the function. 12.3.1 RC Oscillator Calibration The RC oscillator used to time sleep periods is designed to require very little power to operate and be self-contained, requiring no external timing components and hence is lower cost. As a consequence of using on-chip resistors and capacitors, the inherent absolute accuracy and temperature coefficient is lower than that of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal oscillator. Sleep time periods should be as close to the desired time as possible in order to allow the device to wake up in time for important events, for example beacon transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can be programmed to wake up very close to the calculated time of the event and so keep current consumption to a minimum. If the sleep time is less accurate, it will be necessary to wake up earlier in order to be certain the event will be captured. If the device wakes earlier, it will be awake for longer and so reduce battery life. In order to allow sleep time periods to be as close to the desired length as possible, the true frequency of the RC oscillator needs to be determined to better than the initial 30% accuracy. The calibration factor can then be used to calculate the true number of nominal 32kHz periods needed to make up a particular sleep time. A calibration reference timer, clocked from the crystal oscillator, is provided to allow comparisons to be made between the RC clock and the 16MHz crystal oscillator when the JN513x is awake. Operation is as follows:
Wakeup timer0 is disabled and programmed with a number of 32kHz ticks Calibration mode is enabled which causes the Calibration Reference counter to be zeroed. Both counters start counting, the wakeup timer decrementing and the calibration counter incrementing When the wakeup timer reaches zero the Reference Counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer. The true period of the 32kHz clock can thus be determined and used when programming a wakeup timer to achieve a better accuracy and hence more accurate sleep periods The RC oscillator has a good temperature coefficient for an oscillator of its class (see section 17.3.5) however this should be taken into account for any given application, when planning the wake up events and the time interval between calibrations. A calibration can be performed by calling u32AHI_WakeTimerCalibrate(), which calibrates over twenty 32kHz ticks and returns the number of 16MHz ticks recorded. For a RC oscillator running at exactly 32kHz the value returned should be 10000. If the oscillator is running faster than 32kHz the count will be less than 10000, if running slower the value will be higher. For a calibration count of 9000, indicating that the RC oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with 71,112 ((10000/9000) *
(32000*2)) rather than 64000. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 41 Jennic 12.3.2 External 32kHz Clock Source It is possible to change the source of 32kHz clock used for the sleep timers, to an externally supplied 32kHz reference clock on the CLK32K input (DIO9). This mode could allow the timer clock to be sourced from a very stable oscillator model, allowing more accurate sleep cycle timings. 42 JN-DS-JN513x v1.4 Preliminary Jennic 2007 13 Serial Communications The JN513x has two independent Universal Asynchronous Receiver / Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. Each interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a 16-byte deep FIFO buffer allows the CPU to read and write multiple characters on each transaction. This means that the CPU is freed from handling data on a character-by-character basis, with the associated high processor overhead. The UARTs have the following features:
Jennic 16 byte transmit and receive FIFO buffers reduce interrupts to CPU, with direct access to fill levels of each Emulates behaviour of industry standard NS16450 and NS16550 UARTs Adds / deletes standard start, stop and parity communication bits to or from the serial data Optional modem flow control signals CTS and RTS Independently controlled transmit, receive, status and data sent interrupts Fully programmable data formats: baud rate, start, stop and parity settings False start bit detection Internal diagnostic capabilities: loop-back controls for communications link fault isolation Flow control by software or automatically by hardware Internal Interrupt Interrupt Logic RTS CTS Modem Signals Logic Interrupt ID Register s u B r o s s e c o r P Interrupt Enable Register Modem Status Register Modem Control Register Divisor Latch Register s Line Status Register Line Control Register FIFO Control Register Baud Generator Logic Receiver Logic Receiver FIFO Receiver Shift Register RXD Transmitter Logic Transmitter FIFO Transmitter Shift Register TXD Figure 31 UART Block Diagram The serial interface characteristics are programmed using the peripheral library call vAHI_UartSetControl(). This sets the number of data bits (5, 6,7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation and single or multiple stop bit generation (for 5 bit data, multiple is 1.5 stop bits; for 6, 7 or 8 data bits, multiple is 2 bits). The baud rate is programmable between 4800, 9600, 19.2k, 38.4k, 76.8k and 115.2 kbaud via the vAHI_UartSetClockDivisor() function. For higher or non-standard baud rates, the registers of the UART may be accessed directly to achieve the desired programming. Two hardware flow control signals are provided: Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data. RTS is an indication sent by the UART to the external device that it is ready to receive data. Both signals are active low. RTS is controlled from software using the vAHI_UartSetControl() function, while the value of CTS can be read using u8AHI_UartReadModemStatus(). The result of this routine also indicates if the state of CTS has changed, Jennic 2007 JN-DS-JN513x v1.4 Preliminary 43 Jennic indicating that the connected device has signalled the UART that it can begin transmitting. Monitoring and control of CTS and RTS is a software activity, normally performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate to software the state of the UART external interface. Alternatively, the software can set the Automatic Flow Control mode where the hardware controls the value of the generated RTS
(negated if the receive FIFO fill level is 15 and another character starts to be received, and asserted when the receive FIFO is read), and only transmits data when the incoming CTS is asserted. Characters are read one byte at a time from the Receive FIFO using the u8AHI_UartReadData() routine and are written to the Transmit FIFO using vAHI_UartWriteData(). The Transmit and Receive FIFOs can be cleared and reset independently of each other using vAHI_UartReset(). The status of the transmitter can be checked using u8AHI_UartReadLineStatus(), which indicates if the transmit FIFO is empty, and if there is a character being transmitted. The status of the receiver is also checked using this call, which can indicate if conditions such as parity error, framing error or break indication have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if there is data held in the receive FIFO. UART 0 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO4, 5, 6 and 7 respectively and UART 1 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO17, 18, 19 and 20 respectively. If CTS and RTS are not required on the devices external pins, then they may be disabled through software control, this allows the alternate DIOx to be used instead 13.1 Interrupts Interrupt generation is controlled for the UART block using the vAHI_UartSetInterrupt() routine, and are divided into four categories:
Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times. Transmit FIFO Empty: Is set when the last character from the TX FIFO is read and starts to be transmitted. Receiver Line Status: Is set when one of the following occur (1) Parity Error - the character at the head of the receive FIFO has been received with a parity error, (2) Overrun Error - the FIFO is full and another character has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive FIFO does not have a valid stop bit and (4) Break Interrupt occurs when the RxD line has been held low for an entire character. The source of the interrupt is determined using u8AHI_UartReadLineStatus() Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART connected to a 9-pin connector compatible with a PC. The software developer kit uses such an interface as the debugger interface between the JN513x and a PC. As the JN513x device pins do not provide the RS232 line voltage a level shifter is used. 44 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic PC COM Port 1 6 5 9 Pin 1 2 3 4 5 6 7 8 9 Signal CD RD TD DTR SG DSR RTS CTS RI JN513x UART0 RXD RTS TXD CTS 47 45 46 44 RS232 Level Shifter Figure 32 JN513x Serial Communication Link 13.3 Programming Example The following code shows the peripheral library calls to configure UART0 and output the message Hello World Programming Example
/* Set up uart0 */
vAHI_UartEnable(E_AHI_UART_0);
/* set baud rate */
vAHI_UartSetClockDivisor(0, E_AHI_UART_RATE_38400);
/* set parity, start bits, number data bits */
vAHI_UartSetControl(E_AHI_UART_0, E_AHI_UART_EVEN_PARITY, E_AHI_UART_PARITY_DISABLE, E_AHI_UART_WORD_LEN_8, E_AHI_UART_1_STOP_BIT, E_AHI_UART_RTS_HIGH);
/* output message */
char acstring[] = Hello World;
char *pcstring = acstring;
while (*pcstring)
vAHI_UartWriteData(E_AHI_UART_0, *pcstring);
pcstring++;
Jennic 2007 JN-DS-JN513x v1.4 Preliminary 45 Jennic 14 Two-Wire Serial interface The JN513x includes an industry standard two-wire synchronous serial interface (SIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following features:
Compatible with both I2C and SMbus peripherals Multi-master operation Software programmable clock frequency Clock stretching and wait state generation Software programmable acknowledge bit Bus busy detection Support for 7 and 10 bit addressing modes Interrupt or bit-polling driven byte-by-byte data-transfers P r o c e s s o r B u s Prescale Register Command Register Status Register Transmit Register Receive Register Clock Generator Byte Command Controller Bit Command Controller SIF_CLK SIF_D Data I/O Shift Register Figure 33: SIF Block Diagram The prescale register, set using the vAHI_SiConfigure() function, allows the interface to be configured to operate at up to 400kbit/s. The clock generator handles the clock stretching required by some slave devices. The Byte Command Controller handles traffic at the byte level. It takes data from the Command Register and translates it into sequences based on the transmission of a single byte. By setting the start, stop, read, write and acknowledge control bits in the command register using the vAHI_SiSetCmdReg() function it is possible to generate read or write sequences on the bus. The data I/O shift register contains the data associated with the current transfer. During a read operation, data is shifted into this register from the SIF_D line. When the read is complete the byte is copied into the receive register and can be accessed using the u8AHI_SiReadData8() function. During a write operation the contents of the transmit register are copied into the shift register and then onto the SIF_D line. The transmit register can be accessed using the vAHI_SiWriteData8() function. It is possible to generate an interrupt upon the completion of a byte transmission or reception. If required this interrupt can be enabled by using the vAHI_SiConfigure() function. 46 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic If interrupt-driven communication is not desired it is possible to poll the status of the interface by using the bAHI_SiPollBusy() and bAHI_SiPollTransferInProgress() functions. The first byte of data transferred by the device after a start bit is the slave address. The JN513x supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit. The slave address to be used is set using the vAHI_SiWriteSlaveAddr() function. The SIF signals SIF_CLK, SIF_D are alternate functions of pins DIO14 and 15 respectively. 14.1 Connecting Devices The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO lines 14 and 15 respectively. The serial interface function of these pins is selected when the interface is enabled using the vAHI_SiConfigure() function. They are both bi-directional lines, connected internally to the positive supply voltage via weak (45k) programmable pull-up resistors. However, it is recommended that external 4.7k pull-ups be used for reliable operation at high bus speeds, as shown in Figure 34. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is solely dependent on the bus capacitance limit of 400pF. JN513x SIF_CLK SIF_D SIF 55 56 RP RP Vdd Pullup Resistors D1_IN CLK1_IN D2_IN CLK2_IN CLK1_OUT D2_OUT CLK2_OUT D1_OUT DEVICE 1 Figure 34: Connection Details DEVICE 2 14.2 Multi-Master Operation The interface provides a true multi-master bus including collision detection and arbitration that prevents data corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices to count off their low period. Once a devices clock input has gone low, it will hold the SIF_CLK line in that state until the clock high state is reached. Due to the wired-AND connection, the SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the shortest high period. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 47 Jennic Start counting low period Start counting high period Wait State SIF_CLK1 SIF_CLK2 SIF_CLK Master1 SIF_CLK Master2 SIF_CLK Wired-AND SIF_CLK Figure 35: Multi-Master Clock Synchronization 14.3 Clock Stretching Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it. If the slaves SIF_CLK low period is greater than the masters low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait states. Clock held low by Slave SIF_CLK SIF_CLK SIF_CLK Master SIF_CLK Slave SIF_CLK Wired-AND SIF_CLK Figure 36: Clock Stretching 14.4 Programming Example The two-wire serial interface protocol is implemented by a combination of hardware and software. Normally, a standard communication cycle consists of four parts:
Start signal generation Slave address transfer Data transfer Stop signal generation The hardware API supports several calls to support the protocol on the interface. All bit-level timing is implemented by dedicated hardware within the JN513x. The following code example shows how to read a set of values for a slave device into a buffer. A typical application would be data logging from a sensor. Note that bAHI_SiPollTransferInProgress() function is used to block execution until a byte has been transferred. Higher performance applications should use interrupts to detect end of transfer, running the two-wire interface as a background task outside the main program thread. The waveforms below illustrate the operation of the bSIFRead() function listed on the following page. Slave Address Transfer Slave Data Transfer Repeated x u32Length SIF_CLK SIF_D S 7-bit address 0x4E Rd Ack D7 D6 D5 D4 D3 D2 D1 D0 NAck P Figure 37: Read From Slave Device 48 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic Programming Example PRIVATE bool_t bSIFRead(uint8 u8SlaveAddress, uint8 *pau8ReadBuffer, uint32 u32Length)
int i;
for (i=0; i<u32Length; i++)
/* set slave address */
vAHI_SiWriteSlaveAddr(u8SlaveAddress, E_AHI_SI_SLAVE_RW_SET);
/* send read command */
vAHI_SiSetCmdReg(E_AHI_SI_START_BIT, E_AHI_SI_NO_STOP_BIT, E_AHI_SI_NO_SLAVE_READ, E_AHI_SI_SLAVE_WRITE, E_AHI_SI_SEND_ACK, E_AHI_SI_NO_IRQ_ACK);
while(bAHI_SiPollTransferInProgress()); /* busy wait */
if (bAHI_SiPollArbitrationLost() | bAHI_SiPollRxNack())
/* release bus & abort */
vAHI_SiSetCmdReg(E_AHI_SI_NO_START_BIT, E_AHI_SI_STOP_BIT, E_AHI_SI_NO_SLAVE_READ, E_AHI_SI_SLAVE_WRITE, E_AHI_SI_SEND_ACK, E_AHI_SI_NO_IRQ_ACK);
return FALSE;
if (i < u32Length - 1)
/* read and ack */
vAHI_SiSetCmdReg(E_AHI_SI_NO_START_BIT, E_AHI_SI_NO_STOP_BIT, E_AHI_SI_SLAVE_READ, E_AHI_SI_NO_SLAVE_WRITE, E_AHI_SI_SEND_ACK, E_AHI_SI_NO_IRQ_ACK);
else /* last byte */
/* read, stop, nack */
vAHI_SiSetCmdReg(E_AHI_SI_NO_START_BIT, E_AHI_SI_STOP_BIT, E_AHI_SI_SLAVE_READ, E_AHI_SI_NO_SLAVE_WRITE, E_AHI_SI_SEND_NACK, E_AHI_SI_NO_IRQ_ACK);
while(bAHI_SiPollTransferInProgress()); /* busy wait */
if (bAHI_SiPollArbitrationLost())
/* release bus & abort */
vAHI_SiSetCmdReg(E_AHI_SI_NO_START_BIT, E_AHI_SI_STOP_BIT, E_AHI_SI_NO_SLAVE_READ, E_AHI_SI_NO_SLAVE_WRITE, E_AHI_SI_SEND_ACK, E_AHI_SI_NO_IRQ_ACK);
return FALSE;
/* Store data read from device */
pau8ReadBuffer[i] = u8AHI_SiReadData8();
/* transfer complete */
vAHI_SiSetCmdReg(E_AHI_SI_NO_START_BIT, E_AHI_SI_STOP_BIT, E_AHI_SI_NO_SLAVE_READ, E_AHI_SI_NO_SLAVE_WRITE, E_AHI_SI_SEND_ACK, E_AHI_SI_NO_IRQ_ACK);
return TRUE;
Jennic 2007 JN-DS-JN513x v1.4 Preliminary 49 Jennic 15 Analogue Peripherals The JN513x contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors, switches and actuators. Vref Supply Voltage
(VDD1) Internal Reference Vref select Chip Boundary VREF ADC1 ADC2 ADC3 ADC4 COMP1P COMP1M COMP2P COMP2M DAC1 DAC2 ADC Temp Sensor Comparator 1 Comparator 2 DAC1 DAC2 Processor Bus Figure 38: On-chip Analogue Peripherals In order to provide good isolation from digital noise, the analogue peripherals are powered by a separate regulator, supplied from the analogue supply VDD1 and referenced to analogue ground VSSA. The ADC and DAC reference Vref can be selected by vAHI_ApConfigure() between an internal bandgap reference or an external voltage reference supplied to the VREF pin. 50 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 15.1 Analogue to Digital Converter The 12-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, one connected to an internal temperature sensor, and one connected to an internal supply monitoring circuit. 15.1.1 Operation The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage. The reference can be either taken from the internal voltage reference or from the external voltage applied to the VREF pin. For example, an external reference of 1.2V supplied to VREF may be used to set the ADC range between 0V and 2.4V. VREF 1.2V 1.6V 1.2V 1.6V Gain Setting Maximum Input Range Supply Voltage Range (VDD) 0 0 1 1 1.2V 1.6V 2.4V 3.2V 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V The input clock to the ADC is 16MHz and is divided down to 500kHz. During an ADC conversion the selected input channel is sampled for a fixed period and then held. This sampling period is defined as a number of ADC clock periods and can be programmed to 2, 4, 6 or 8. The conversion rate is (2 x sampling interval) + (14 x Clock periods), for example if the sampling period is set to 2 clock periods, with the 500kHz clock the conversion rate will be 2 x 2 +
14 = 18 clock periods, 36secs or 27.7kHz. If the source resistance of the input voltage is 1k or less, then the default sampling time of 2 clocks should be used. The input to the ADC can be modelled as a resistor of 5k to represent the on-resistance of the switches and the sampling capacitor 8pF. The sampling time required can then be calculated, by adding the sensor source resistance to the switch resistance, multiplying by the capacitance giving a time constant. Assuming normal exponential RC charging, the number of time constants required to give an acceptable error can be calculated, 7 time constants gives an error of 0.1%, so for 12-bit accuracy 10 time constants should be the target. For a source with zero resistance, 10 time constants is 800 nsecs, hence the smallest sampling window of 2 clock periods can be used. The ADC sampling period is set with vAHI_ApConfigure(). The ADC input range and input is selected and the in either single shot mode with vAHI_AdcStartSample() or continuous mode using ADC enabled vAHI_AdcEnable(). When the ADC conversion is complete, an interrupt is generated. This is enabled using vAHI_ApConfigure(). Alternatively the conversion status can be monitored using bAHI_AdcPoll(). When operating in continuous mode, it is recommended that the interrupt is used to signal the end of a conversion, since conversion times may range from 36 to 60 secs. Polling over this period would be wasteful of processor bandwidth. The result of a conversion can be read using u16AHI_AdcRead() function. The ADC also has an accumulation feature that allows the results of several samples to be accumulated with no CPU intervention and once completed an interrupt generated. For detailed electrical specifications, see section 17.3.7. 15.1.2 Supply Monitor The internal supply monitor allows the voltage on the analogue supply pin VDD1 to be measured. This is achieved with a potential divider that reduces the voltage by a factor of 0.666, allowing it to fall inside the input range of the ADC when set with an input range twice the internal voltage reference. The resistor chain that performs the voltage reduction is disabled until the measurement is made to avoid a continuous drain on the supply. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 51 Jennic 15.1.3 Temperature Sensor The on-chip temperature sensor can be used either to provide an absolute measure of the device temperature or to detect changes in the ambient temperature. In common with most on-chip temperature sensors, it is not trimmed and so the absolute accuracy variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces a constant current through a forward biased diode to provide a voltage output proportional to the chip die temperature which can then be measured using the ADC. The measured voltage has a linear relationship to temperature as described in section 17.3.11. Because this sensor is on-chip, any measurements taken must account for the thermal time constants. For example if the device just came out of sleep mode the user application should wait until the temperature has stabilized before taking a measurement. 15.1.4 Programming Example The following example illustrates data logging using the ADC1 input channel. E_AHI_AP_REGULATOR_ENABLE, E_AHI_AP_INT_DISABLE, E_AHI_AP_SAMPLE_2, E_AHI_AP_CLOCKDIV_500KHZ, E_AHI_AP_INTREF);
Programming Example PRIVATE void vAdcDataLogger(uint16 *pau16DataBuffer, uint32 u32Length)
int i;
/* configure Analogue Peripheral timings, interrupt & ref voltage */
vAHI_ApConfigure(
while (!bAHI_APRegulatorEnabled);
/* configure & enable DAC */
vAHI_AdcEnable(E_AHI_ADC_CONVERT_ENABLE, while(TRUE)
vAHI_AdcStartSample();
/* start capture */
while(bAHI_AdcPoll());
/* busy wait until capture complete */
pau16DataBuffer[i] = u16AHI_AdcRead();
/* store in buffer */
for (i=0;i<u32Length;i++)
E_AHI_AP_INPUT_RANGE_1, E_AHI_ADC_SRC_ADC_1);
15.2 Digital to Analogue Converter The Digital to Analogue Converter (DAC) provides two output channels and is capable of producing voltages of 0 to Vref or 0 to 2Vref where Vref is selected between the internal reference and the VREF pin, with a resolution of 11 bits and a minimum conversion time of 9secs (2MHz clock). 15.2.1 Operation The output range of each DAC can be set independently to swing between 0V to either the reference voltage or twice the reference voltage. The reference voltage is selected from the internal reference or the VREF pin. For example, an external reference of 0.8V supplied to VREF may be used to set DAC1 maximum output of 0.8V and DAC2 maximum output of 1.6V. 52 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic The DAC output amplifier is capable of driving a capacitive load up to that specified in section 17.3.9. Programmable clock periods set with vAHI_ApConfigure() allow a trade-off between conversion speed and resolution. The full 11-bit resolution is achieved with the 250kHz clock rate. See section 17.3.7, electrical characteristics, for more details. The conversion period of the DACs are given by the same formula as the ADC conversion time and so can vary between 9 and 120uS. The DAC values may be updated at the same time as the ADC is active. The clock divider ratio, interrupt enable and reference voltage select are all controlled by the vAHI_ApConfigure() function which is for options common to both the ADC and DAC. The DAC output range and value is set with vAHI_DacEnable() and subsequent updates may use vAHI_DacOutput(), which only requires the new DAC value. The call bAHI_DacPoll() can be used to determine if a DAC channel is busy performing a conversionThe vAHI_DacDisable() function is used to power down a DAC cell. 15.2.2 Programming Example The following code example illustrates how to generate a sawtooth waveform on pin 29 (DAC1) E_AHI_AP_REGULATOR_ENABLE, E_AHI_AP_INT_DISABLE, E_AHI_AP_SAMPLE_2, E_AHI_AP_CLOCKDIV_2MHZ, E_AHI_AP_INTREF);
Programming Example PRIVATE void vDacSawtooth(void)
uint16 u16InitalValue = 0;
int i;
/* configure Analogue Peripheral timings, interrupt & ref voltage */
vAHI_ApConfigure(
while (!bAHI_APRegulatorEnabled);
/* configure & enable DAC */
vAHI_DacEnable(E_AHI_AP_DAC_1, while(TRUE)
/* value to output */
vAHI_DacOutput(E_AHI_DAC_1, i);
/* wait until conversion completes */
while(bAHI_DacPoll());
for (i=0;i<2048;i++)
E_AHI_AP_INPUT_RANGE_1, E_AHI_DAC_RETAIN_DISABLE, u16InitalValue);
15.3 Comparators The JN513x contains two analogue comparators COMP1 and COMP2 that are designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level (common to both comparators) can be set to a nominal value of 0mV, 10mV, 20mV or 40mV using the vAHI_ComparatorEnable() function. In addition, the source of the negative input signal for each comparator (COMP1M and COMP2M) can be set to one of the internal voltage reference, the output of DAC1 or DAC2 (COMP1 or COMP2 respectively) or the external pin, using vAHI_ComparatorEnable(). The comparator outputs are routed to internal registers and can be polled using the u8AHI_ComparatorStatus() function, or can be used to generate interrupts controlled by Jennic 2007 JN-DS-JN513x v1.4 Preliminary 53 Jennic vAHI_ComparatorIntEnable(). The comparators can be disabled using the vAHI_ComparatorDisable() function to reduce power consumption. The comparators have a low power mode where the response time of the comparator is slower than normal and is specified in section 17.3.10. This mode may be used during non-sleep operation however it is particularly useful in sleep mode to wake up the JN513x from sleep where low current consumption is important. The function vAHI_ComparatorIntEnable() enables the wakeup action and sets which edge of the comparator output will be active. In sleep mode the negative input signal source defaults to the external pins. 54 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 16 Power Management and Sleep Modes 16.1 Operating Modes Three operating modes are provided in the JN513x that enable the system power consumption to be controlled carefully to maximise battery life. Active Processing Mode Sleep Mode Deep Sleep Mode The variation in power consumption of the three modes is a result of having a series of power domains within the chip that may be controllably powered on or off. 16.1.1 Power Domains The JN513x has the following power domains:
VDD Supply Domain: supplies the wake-up timers and controller, DIO blocks, Comparators and 32kHz RC oscillator. This domain is driven from the external supply (battery) and is always powered. The wake-up timers and controller, and the 32kHz RC oscillator may be powered on or off in sleep mode through software control. Digital Logic Domain: supplies the SPI interface, CPU, ROM, Baseband controller, Modem and Encryption processor. It is powered off during sleep mode. Analogue Domain: supplies the ADC, DACs and the temperature sensor. It is powered off during sleep mode and may be powered on or off in active processing mode through software control. RAM Domain: supplies the RAM during sleep mode to retain the memory contents. It may be powered on or off for sleep mode through software control. Radio Domain: supplies the radio interface. It is powered during transmit and receive and controlled by the baseband processor. 16.2 Active Processing Mode Active processing mode in the JN513x is where all of the application processing takes place. By default, the CPU will execute in full speed mode allowing 16/32MIPs performance to be achieved. All of the peripherals are available to the application as are options to actively enable or disable them to control power consumption; see specific peripheral sections for details. Whilst in Active processing mode there is the option to doze the CPU but keep the rest of the chip active, this is particularly useful for radio transmit and receive operations, where the CPU operation is not required. 16.2.1 CPU Doze Whilst in doze mode, CPU operation is stopped but the chip remains powered and the digital peripherals continue to run. Doze mode is entered by executing the vAHI_CpuDoze() function and is terminated by any interrupt request. Once the interrupt service routine has been executed, the vAHI_CpuDoze() function returns and normal program execution resumes. Doze mode uses more power than sleep and deep sleep modes but requires less time to restart and can therefore be used as a low power alternative to an idle loop. 16.3 Sleep Mode The JN513x enters sleep mode under control of the CPU using the vAHI_PowerDown() function. In this mode many of the internal chip functions are shutdown to save power, however the state of DIO pins are retained, including Jennic 2007 JN-DS-JN513x v1.4 Preliminary 55 Jennic the output values, and this therefore preserves any interface to the outside world. The DAC outputs are placed into a high impedance state. When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period, this is determined by vAHI_MemoryHold(). If wakeup timers or comparator event are not to be used for a wakeup event, then power can be saved by switching off the 32kHz oscillator through software control. Whilst in sleep mode one of three possible events can cause a wakeup to occur, transitions on DIO inputs, expiry of wakeup timers or comparator events. If any of these events occur, an interrupt is generated that will cause a wakeup from sleep. It is possible for multiple wakeup sources to trigger an event at the same instant and only one of them will be accountable for the wakeup period. It is therefore necessary in software to remove all other pending wakeup events prior to requesting entry back into sleep mode; otherwise, the device will re-awaken immediately. When wakeup occurs, a similar sequence of events to the reset process described in section 6.1 happens. The 16MHz oscillator is started up, once stable the power to CPU system is enabled and the reset is removed. Software determines that this is a reset from sleep and so commences with the wakeup process. 16.3.1 Wakeup Timer Event The JN513x contains two 32-bit wakeup timers that are counters clocked from the 32kHz oscillator, and can be programmed to generate a wake-up event. Following a wakeup event, the timers continue to run. These timers are described in section 12.3. Timer events can be generated from both of the two timers; one is intended for use by the 802.15.4 protocol, the other being available for use by the Application running on the CPU. These timers are available to run at any time, even during sleep mode, and are controlled by API calls as detailed in the Jennic document JN513x JN-RM-2001 Integrated Peripherals API [2]. 16.3.2 DIO Event Any DIO pin when used as an input has the capability, by detecting a transition, to generate a wake-up event. Once this feature has been enabled using the vAHI_DioInterruptEnable() function the type of transition can be specified (rising or falling edge) by using the vAHI_DioInterruptEdge() function. Even when groups of DIO lines are configured as alternative functions such as the UARTs or Timers etc, any input line in the group can still be used to provide a wakeup event. This means that an external device communicating over the UART can wakeup a sleeping device by asserting its RTS signal pin. 16.3.3 Comparator Event The comparator can generate a wakeup interrupt when a change in the relative levels of the positive and negative inputs occurs, the negative input being selectable between the external pin COMPxN or the internal voltage reference. The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power applications. The JN513x can remain in sleep mode until the voltage drops below a threshold and then be woken up to deal with the alarm condition. 16.4 Deep Sleep Mode Deep sleep mode gives the lowest power consumption. All switchable power domains are off and certain functions in the VDD supply power domain, including the 32kHz oscillator are stopped. It is entered by executing the vAHI_PowerDown() function. This mode can be exited by a power down, a hardware reset on the RESETN pin, or a DIO event. The DIO event in this mode causes a chip reset to occur. 56 JN-DS-JN513x v1.4 Preliminary Jennic 2007 17 Electrical Characteristics 17.1 Maximum ratings Exceeding these conditions may result in damage to the device. Parameter Device supply voltage VDD1, VDD2 Supply voltage at voltage regulator bypass pins VB_xxx Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RFP, RFM, Voltage on analogue pins VREF, ADC1-4, DAC1-2, COMP1M, COMP1P, COMP2M, COMP2P, IBIAS, GPIO9, GPIO10 Voltage on 5v tolerant digital pins SPICLK, SPIMOSI, SPIMISO, SPISEL0, GPIO0-GPIO8, GPIO11-GPIO20, RESETN Storage temperature Reflow soldering temperature according to IPC/JEDEC J-STD-020C ESD rating (see note 1) Human Body Model Machine Model Min
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-40C Jennic Max 3.6V 1.98V VB_xxx + 0.3V VDD1 + 0.3V Lower of (VDD2 + 2V) and 5.5V 150C 260C 1.5kV 150V Note 1: The Human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. (MIL-
STD-883 3015.7) The machine model is a 200pF capacitor discharged directly into each pin. 17.2 DC Electrical Characteristics 17.2.1 Operating Conditions Supply VDD1, VDD2 Ambient temperature range Min 2.2V
-40C Max 3.6V 85C Jennic 2007 JN-DS-JN513x v1.4 Preliminary 57 Jennic 17.2.2 DC Current Consumption VDD = 2.2 to 3.6V, -40 to +85 C 17.2.2.1 Active Processing Mode:
Min Typ Max Unit Notes CPU processing CPU processing (2 x clock) Radio transmit
[boost mode]
Radio receive
[boost mode]
2.7 +
0.325/MHz 2.7 +
0.325/MHz 34
[38]
34
[37]
mA SPI, GPIOs enabled mA mA mA SPI, GPIOs enabled CPU in software doze radio transmitting CPU in software doze radio in receive mode The following current figures should be added to those above if the feature is being used ADC DAC Comparator UART Timer 2-wire serial interface 17.2.2.2 Sleep Mode Mode:
Sleep mode with I/O wakeup Sleep mode with I/O and timer wakeup Min 580 220 / 250 67 / 1.2 110 65 86 Typ 0.2 1.3 A A A A A A Temperature sensor and battery measurements require ADC One / both Fast response time / low-power For each UART For each Timer Max Unit Notes A A Waiting on I/O event. As above, but also waiting on timer event. If both wakeup timers are enabled then add another 0.3A The following current figures should be added to those above if the feature is being used RAM retention Comparator (low-power mode) 17.2.2.3 Deep Sleep Mode Mode:
Deep sleep mode Min 2.0 1.2 Typ 0.2 A A For full 96kB retained. Reduced response time. Max 0.4 Unit A Notes Waiting on chip RESET or I/O event. 58 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic Typ 35 42 59 4 3 Max 53 63 92 Lower of (VDD2 + 2V) and 5.5V VDD x 0.27 0.4V VDD2 0.4V VDD2 0.4V Unit k V V V V V V V mA Notes VDD2 = 3.6V, 25C VDD2 = 3.0V, 25C VDD2 = 2.2V, 25C 5V Tolerant With 4mA load With 4mA load With 3mA load With 3mA load VDD2 = 2.7V to 3.6V VDD2 = 2.2V to 2.7V 17.2.3 I/O Characteristics VDD = 2.2 to 3.6V, -40 to +85 C Parameter Internal DIO pull up resistors Min 24 27 38 Digital I/O High Input VDD2 x 0.7 Digital I/O low Input Digital I/O input hysteresis DIO High O/P (2.7-3.6V) DIO Low O/P (2.7-3.6V) DIO High O/P (2.2-2.7V) DIO Low O/P (2.2-2.7V) Current sink capability
-0.3 0.175 VDD2 x 0.8 0 VDD2 x 0.8 0 17.3 AC Characteristics 17.3.1 Reset VDD Internal RESET RESETN RESETN Internal RESET VPOT tSTAB Figure 39: Power-on Reset tRST VRST tSTAB Figure 40: External Reset Jennic 2007 JN-DS-JN513x v1.4 Preliminary 59 Jennic Parameter External Reset pulse width External Reset threshold voltage Internal Power-on Reset threshold voltage (VPOT) Reset stabilisation time
(tSTAB) Min 1 VDD2 x 0.7 1 VDD rise time of 1ms. 17.3.2 Brown-out Detect VTH + VHYS VTH Typ Max 1.90 1.95 2.00 2.5 DVDD Unit s V V ms Notes Assumes internal pullup resistor value of 100K worst case and ~5pF external capacitance. VDD2 = 2.2V VDD2 = 3.0V VDD2 = 3.6V Note 1 Internal BOR Figure 41: Brown-out Detect Internal BOR Parameter Brown-out Threshold Voltage
(VTH) Brown-out Hysteresis (VHYS) Min Typ 2.1 2.4 2.5 2.6 100 Max Unit V Notes Configurable threshold with 4 levels mV 60 JN-DS-JN513x v1.4 Preliminary Jennic 2007 17.3.3 SPI Timing SS CLK MISO
(mode=0,3) MISO
(mode=1,2) MOSI
(mode=1,2) MOSI
(mode=0,3) tCK tHI tSSS tSI tVO tHI tSI tVO Parameter Clock period Data setup time Data hold time Data invalid period Select set-up period Select hold period Figure 42: SPI Timing (Master) Symbol tCK tSI tHI tVO tSSS tSSH Min 62.5 15.3 @ 2.7-3.6V 30.5 @ 2.2-3.6V 0
10 10 Max
15
17.3.4 Two-wire serial interface Jennic tSSH Unit ns ns ns ns ns ns SIF_D tF SIF_CLK tLOW tR tSU;DAT tHD;STA tSP tR tBUF S tHD;STA tHD;DAT tHIGH tF tSU;STA Sr tSU;STO P S Figure 43: Two-wire serial Interface Timing Parameter Symbol Min SIF_CLK clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SIF_CLK clock HIGH period of the SIF_CLK clock Set-up time for repeated START condition Data hold time SIF_D fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT 0 0.6 1.3 0.6 0.6 0 Max 400
0.9 Unit kHz s s s s s Jennic 2007 JN-DS-JN513x v1.4 Preliminary 61 Jennic Data setup time SIF_D Rise Time SIF_D and SIF_CLK Fall Time SIF_D and SIF_CLK Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device
(including hysteresis) Noise margin at the HIGH level for each connected device
(including hysteresis) Pulse width of spikes which must be suppressed by input filter 17.3.5 Power Down and Wake-Up timings tSU:DAT 0.1 tR tF tSU:STO tBUF Cb Vnl Vnh tSP 20+0.1Cb 20+0.1Cb 0.6 1.3
0.1VDD 0.2VDD N/a 0 300 300
400
50 s ns ns s s pF V V ns Parameter Min Wake up from Deep Sleep Wake up from Sleep
(memory not held) Wake up from Sleep
(Memory held) Wake up from CPU Doze mode Max Typ 2.5 + 0.5*
program size in kBytes 2.5 + 0.5*
program size in kBytes 2.5 0.2 Unit ms ms ms s Notes Assumes SPI clock to external Flash is16MHz Assumes SPI clock to external Flash is16MHz 62 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic 17.3.6 32kHz Oscillator VDD = 2.2 to 3.6V, -40 to +85 C Parameter Current consumption of cell and counter logic Min Typ 1.2 1.0 0.8 Max Unit A Notes 3.6V 3.0V 2.2v 32kHz clock native accuracy Calibrated 32kHz accuracy Variation with temperature Variation with VDD2
-30%
32kHz
+30%
At 3.0V 25C 65
-0.02
-4 ppm
%/C
%/V 17.3.7 16MHz Crystal Oscillator VDD = 2.2 to 3.6V, -40 to +85C Parameter Min Current consumption Start up time Input capacitance Transconductance DC voltages, XTALIN, XTALOUT External Capacitors Typ 150 2.5 1.4 1.16 400 15 Max 17.3.8 Analogue to Digital Converters VDD = 3.0V, VREF = 1.2V, -40 to +85C Unit A ms Notes Excluding bandgap ref. Assuming xtal with ESR of 40ohms and CL= 9pF External caps = 15pF
(150mV pk-pk) pF Bondpad and package mA/V mV pF Total external capacitance needs to be 2*CL, allowing for stray capacitance from chip, package and PCB Parameter Resolution Current consumption Integral nonlinearity Differential nonlinearity Min Typ 580 2 Max 12 1 Unit bits A LSB LSB Notes 500kHz Clock Guaranteed monotonic Jennic 2007 JN-DS-JN513x v1.4 Preliminary 63 Jennic Parameter Offset error Gain error Internal clock No. internal clock periods to sample input Conversion time Input voltage range Vref (Internal) Vref (External) Input capacitance Min 36 1.15 1.15 Typ 20 20 500 2, 4, 6 or 8 1.2 1.2 8 Max Unit Notes 0 to Vref or 0 to 2*Vref 1.25 1.6 mV mV kHz s V V V 16MHz input clock, 32 Programmable 500KHz Clock with sample period of 2 Switchable Bandgap voltage Allowable range into VREF pin pF In series with 5K ohms 17.3.9 Digital to Analogue Converters VDD = 3.0V, VREF = 1.2V, -40 to +85C Parameter Min Resolution Current consumption Integral nonlinearity Differential nonlinearity Offset error Gain error Internal clock Output settling time to 0.5LSB Minimum Update time Output voltage swing 9 Typ 11 220 (single) 250 (both) 2
-56 15 2MHz, 1MHz, 500kHz, 250kHz 5 0 to VREF or 0 to 2xVREF Max 1 Vref (Internal) 1.15 1.2 1.25 Unit bits A LSB LSB mV mV s s V V Notes Guaranteed monotonic 16MHz input clock, programmable prescaler With 10k ohms & 20pF load 2MHz Clock with sample period of 8 Switchable Bandgap voltage 64 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Parameter VREF (External) Resistive load Capacitive load Digital input coding Min 0.8 10k Typ 1.2 Binary Max 1.6 20 17.3.10 VDD = 2.2 to 3.6V -40 to +85C Comparators Parameter Min Analogue response time
(normal) Total response time
(normal) including delay to Interrupt controller Analogue response time
(low power) Hysteresis Vref (Internal) Common Mode input range Current (normal mode) Current (low power mode) 1.15 0 Typ 105 Max 140 140 + 125 2.4 10 20 40 1.18 67 1.2 1.25 Vdd Jennic Unit Notes V pF Unit ns ns s mV V V A A Allowable range into VREF pin To ground Notes
+/- 250mV overdrive 10pF load Digital delay can be up to a max. of two 16MHz clock periods
+/- 250mV overdrive No digital delay Programmable in 3 steps and zero. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 65 Jennic 17.3.11 Temperature Sensor Parameter Operating Range Sensor Gain Accuracy Non-linearity Output Voltage Range Resolution Min
-40
-1.55
620 0.756 Typ
-1.6
750 0.733 Max 85
-1.63 10 2.5 860 0.719 Unit C mV/C C C mV C/LSB Notes 0 to Vref ADC I/P Range Radio Transceiver 17.3.12 This JN513x meets all the requirements of the IEEE802.15.4 standard over 2.2 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended and include the losses of a ceramic balun. Parameter Min Typical Max Notes Type Impedance RF Port Characteristics 200ohm Differential 2.4-2.5GHz Frequency range 2.4 GHz 2.4835GHz 66 JN-DS-JN513x v1.4 Preliminary Jennic 2007 17.3.12.1 Radio parameters: 2.2-3.6V, +25C Parameter Min Typical Max Unit Notes Receiver Characteristics Jennic Receive sensitivity Receive sensitivity
(boost) Maximum input signal Adjacent channel rejection
-1 channel / +1 channel
[CW Interferer]
Alternate channel rejection
[CW Interferer]
Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels Out of band rejection Spurious emissions
(RX) Intermodulation protection
-95.5
-96.5 31 / 33
[35 / 38]
41
[45]
46
>45 40 0 dBm dBm dBm dB dB dB Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 For 1% PER, measured as sensitivity For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4
(modulated interferer) For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4
(modulated interferer) For 1% PER with wanted signal 3dB above sensitivity, measured as per 802.15.4 section 6.5.3.4 dB
-57
-47 dBm dB 30MHz to 1GHz 1GHz to 12GHz For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation
-95 to -10dBm. Available through Hardware API RSSI linearity
-3
+3 dB Transmitter Characteristics Transmit power Transmit power (boost) Output power control range Spurious emissions
(TX) EVM Transmit Power Spectral Density 0.5
+2.5
-30 15
-48 dBm dBm Nominal dB in 5 6dB steps
-36
-43
-47 25
-20 dBm
dBc 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz At maximum output power At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 67 Jennic 17.3.12.2 Radio parameters: 2.2-3.6V, -40C Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity Maximum input signal Adjacent channel rejection
-1 channel / +1 channel Alternate channel rejection Other in band rejection Out of band rejection Spurious emissions
(RX) Intermodulation protection
-97 31 / 35 41 45 TBA 35 0 dBm dBm Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 For 1% PER, measured as sensitivity dB dB dB For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 2.4 to 2.4835 GHz, excluding adjacent channels For 1% PER with wanted signal 3dB above sensitivity, measured as per 802.15.4 section 6.5.3.4
-57
-47 dBm dB 30MHz to 1GHz 1 to 12GHz For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation
-95 to -10dBm. Available through Hardware API RSSI linearity
-3
+3 dB Transmitter Characteristics Transmit power Transmit power (boost) Output power control range Spurious emissions
(TX) EVM Transmit Power Spectral Density 68 dBm dBm Nominal dB in 5 6dB steps 1.8
+3.0
-30 dBm
-36
-43
-47 20
-50 25
-20
dBc 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz &
5.15 to 5.3GHz At maximum output power At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN513x v1.4 Preliminary Jennic 2007 17.3.12.3 Radio parameters: 2.2-3.6V, +85C Parameter Min Typical Max Unit Notes Receiver Characteristics Jennic Receive sensitivity Maximum input signal Adjacent channel rejection
-1 channel / +1 channel Alternate channel rejection Other in band rejection Out of band rejection Spurious emissions
(RX) Intermodulation protection
-92 27 / 35 41 43 TBA 35 0 dBm dBm dB dB dB Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 For 1% PER, measured as sensitivity For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 For 1% PER with wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 2.4 to 2.4835 GHz, excluding adjacent channels For 1% PER with wanted signal 3dB above sensitivity, measured as per 802.15.4 section 6.5.3.4
-57
-47 dBm dB RSSI linearity
-3
+3 dB Transmitter Characteristics Transmit power Transmit power (boost) Output power control range Spurious emissions
(TX) EVM Transmit Power Spectral Density
-3.0 0
-30 12
-46 dBm dBm dB dBm
-36
-43
-47 25
-20
dBc 30MHz to 1GHz 1GHz to 12GHz For 1% PER at with wanted signal 3dB above sensitivity. Modulated Interferers at 2 & 4 channel separation
-95 to -10dBm. Available through Hardware API Nominal in 5 steps of 6dB 30MHz to 1GHz, 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz &
5.15 to 5.3GHz At maximum output power At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 69 Jennic Appendix A Mechanical and Ordering Information A.1 56pin QFN Package Drawing Controlling Dimension: mm Symbol millimetres Min.
0.00
0.25 0.20 Ref. 0.2 8.00 bsc 7.75 bsc Nom. Max.
0.9 0.05 0.01 0.7 0.65 0.3 6.60 6.60 0.50 12
Tolerances of Form and Position A A1 A2 A3 b D D1 D2 E E1 E2 L e 1 R 8.00 bsc 7.75 bsc 0 0.09
6.20 0.30 6.40 0.40 0.50 bsc 6.20 6.40 aaa bbb ccc 0.10 0.10 0.05 JN-DS-JN513x v1.4 Preliminary Jennic 2007 70 A.2 PCB Decal The following PCB decal is recommended; all dimensions are in millimetres (mm). Jennic 71 Jennic 2007 JN-DS-JN513x v1.4 Preliminary Jennic A.3 Ordering Information Ordering Format:
JN513x - XXX - Y1Y2Y3 Part Numbers:
XXX: ROM Variant:
JN5131 JN5132 JN5133 JN5139 Wireless microcontroller - 8kB RAM Wireless microcontroller - 16kB RAM Wireless microcontroller - 32kB RAM Wireless microcontroller - 96kB RAM 001 Z01 IEEE802.15.4 stack ZigBee stack Y1:
Y2:
Y3:
Punched 56 lead, 0.5mm pitch 8x8mm Quad Flat No Leads (QFN)
-40C to +85C - Industrial Temperature Range Package Variant:
A Temperature Range / Device Status:
I Shipping:
R T V X Y Trays (up to 260 devices) Tape mounted 2500 devices on a 13 reel Tape mounted 1000 devices on a 7 reel Tape mounted 500 devices on a 7 reel Tape mounted upto 100 devices (no reel) Ordering Examples:
Part Number JN5131-001-AIR JN5133-Z01-AIV Description JN5131 IEEE802.15.4 Wireless Microcontroller up to 260 devices in a tray JN5133 ZigBee Wireless Microcontroller - 1000 devices on a 7 reel 72 JN-DS-JN513x v1.4 Preliminary Jennic 2007 A.4 Device Package Marking The diagram below shows the package markings for JN513x devices. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific markings for a JN5139-Z01 device, that came from assembly build number 1000004 and was manufactured week 4 of 2007. Jennic Jennic JNXXXX-SSS FFFFFFF YYWW Jennic JN5139-Z01 1000004 0704 JN XXXX SSS FFFFFFF YY WW Jennic 4 digit part number, for example 5139, 5132 3 digit software ROM identifier 7 digit assembly build number 2 digit year number 2 digit week number Legend:
Where this Data Sheet is denoted as Advanced or Preliminary, devices will be either Engineering or Prototype Samples. Devices of this status have an R suffix after the software ROM identifier, for example JN5139-Z01R. Devices may also have an additional digit immediately after the R suffix, for example R1, R2, R3 etc. This additional digit is use to identify different revisions of engineering or prototype silicon during these product phases. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 73 Jennic A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 56QFN package in the tape is as shown in Figure 42. Figure 44: Tape and Reel orientation Figure 43 shows the detailed dimensions of the tape used for 8x8mm 56QFN devices. 74 Reference Ao Bo Ko P T W Dimensions (mm) 8.30 0.10 8.30 0.10 1.10 0.10 12.00 0.10 0.30 0.10 16.00 +0.30/-0.10 Figure 45: Tape Dimensions JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic A.5.2 Reel Information: 7 Reel Surface Resistivity Material Between 10e9 10e11 Ohms Square High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space. Tape Width 16 A 180 B (min) 1.5min C 13 0.2 N 60 +0.1 0.0 Figure 46: Reel Dimensions W (min) 16.40 W (max) 17.90 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 75 Jennic A.5.3 Reel Information: 13 Reel Surface Resistivity Material Between 10e9 10e11 Ohms Square High Impact Polystyrene with Antistatic Additive All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Tape Width 16 A 330 B (min) C 1.5 13 +0.5 -0.2 D (min) 20.2 N (min) W (min) W (max) 19.40 15.90 100 Figure 47: Reel Dimensions A.5.4 Dry Pack Requirement for Moisture Sensitive Material Moisture sensitive material, as classified by JEDEC standard J-STD-033, must be dry packed. The 56 lead QFN package is MSL2A/260C, and is dried before sealing in a moisture barrier bag (MBB) with desiccant bag weighing at 67.5 grams of activated clay and a 6 spot humidity indicator card (HIC) meeting MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices. 76 JN-DS-JN513x v1.4 Preliminary Jennic 2007 A.6 PCB Design and Reflow Profile PCB and land pattern designs are key to board level reliability, and Jennic strongly recommends that users follow the design rules listed in IPC-SM-782. For reflow profiles, it is recommended to follow the reflow profile in Figure 48 as a guide, as well as the paste manufacturers guidelines on peak flow temperature, soak times, time above liquidus and ramp rates. Jennic Figure 48: Reflow Profile Jennic 2007 JN-DS-JN513x v1.4 Preliminary 77 Jennic Appendix B Development Support B.1 Crystal Oscillator 16MHz Crystal Requirements Parameter Crystal Frequency Crystal Tolerance Crystal ESR (Rm) 1 Crystal Load Capacitance (CL) External Capacitors (C1 & C2) Min 20 Typ 16MHz 9pF 15pF B.1.1 Crystal Equivalent Circuit Cs Max Notes 40ppm Including temperature and aging 60 See below for more details See below for more details Total external capacitance needs to be 2*CL. , allowing for stray capacitance from chip, package and PCB Lm Rm Cm C1 C2 mC is the motional capacitance mL is the motional inductance. This together with mC defines the oscillation frequency (series) mR is the equivalent series resistance ( ESR ). SC is the shunt or package capacitance and this is a parasitic JN-DS-JN513x v1.4 Preliminary Jennic 2007 Where 78 B.1.2 Crystal Load Capacitance The crystal load capacitance is the total capacitance seen at the crystal pins, from all sources. As the load capacitance (CL) affects the oscillation frequency by a process known as pulling, crystal manufacturers specify the frequency for a given load capacitance only. A typical pulling coefficient is 15ppm/pF, to put this into context the maximum frequency error in the IEEE802.15.4 specification is +/-40ppm for the transmitted signal. Therefore, it is important for resonance at 16MHz exactly, that the specified load capacitance is provided. The load capacitance can be calculated using:
Jennic CL =
T C C T CC
1 C
1 1 C T C T 2 2
C 1 1 T P in 1 is the on-chip parasitic capacitance and is about 1.4pF typically. 2TC Total capacitance 1C is the capacitor component Where PC1 is the PCB parasitic capacitance. With the recommended layout this is about 1.6pF inC1 Similarly for Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent circuit represents the energy lost. To maintain oscillation, power must be supplied by the amplifier, but how much? Firstly, the Pi connected capacitors C1 and C2 with CS from the crystal, apply an impedance transformation to Rm, when viewed from the amplifier. This new value is given by:
R m
CCR
S C L m L 2 The amplifier is a transconductance amplifier, which takes a voltage and produces an output current. The amplifier together with the capacitors C1 and C2, form a circuit, which provides a negative resistance, when viewed from the crystal. The value of which is given by:
R NEG
g m C T 2 C T 1 2 Where mg is the transconductance is the frequency in rad/s Derivations of these formulas can be easily found in textbooks. In order to give quick and reliable oscillator start-up, a common rule of thumb is to set the amplifier negative resistance to be a minimum of 4 times the effective crystal resistance. This gives g m C T 2 C T 1 2 4 CCR
S m C L L 2 Jennic 2007 JN-DS-JN513x v1.4 Preliminary 79 Jennic This can be used to give an equation for the required transconductance. 4 R 2 m g m S
CCC
T T 1 CC T T 1
) CC
1 T T
22 2 2 1TC =
2TC =18pF ( for a load capacitance of 9pF), the SC =1pF and Example: Using typical parameters of mR =40, equation above gives the required transconductance ( mg ) as 647uA/V. The JN513x has a typical value for transconductance of 1.25mA/V The example and equation illustrate the trade-off that exists between the load capacitance and crystal ESR. For example, a crystal with a higher load capacitance can be used, but the value of max. ESR that can be tolerated is reduced. Also note, that the circuit sensitivity to external capacitance [ C1 , C2 ] is a square law. Below is measurement data showing the variation of the crystal oscillator amplifier transconductance with temperature and supply voltage, notice how small the variation is. Circuit techniques have been used to apply compensation, such that the user need only design for nominal conditions. Crystal Oscillator Transconductance Versus Temperature
(VDD=3V)
V A m
e c n a t c u d n o c s n a r T 1.285 1.28 1.275 1.27 1.265 1.26 1.255 1.25 1.245
-40
-20 0 20 40 60 80 100 Temperature (C) Crystal Oscillator Transconductance Versus Supply Voltage
(Temp=25C)
V A m
e c n a t c u d n o c s n a r T 1.32 1.3 1.28 1.26 1.24 1.22 1.2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Supply Voltage (VDD) 80 JN-DS-JN513x v1.4 Preliminary Jennic 2007 B.2 16MHz Oscillator The JN513x contains the necessary on-chip components to build a 16 MHz reference oscillator with the addition of an external crystal resonator and two tuning capacitors. The schematic of these components are shown in Figure 49. The two capacitors, C1 and C2, should be 15pF 5% and use a COG dielectric. For a detailed specification of the crystal required see Appendix B.1. Jennic JN513x XTALIN R1 XTALOUT C1 C2 Figure 49: Crystal oscillator connections The clock generated by this oscillator provides the reference for most of the JN513x subsystems, including the transceiver, processor, memory and digital and analogue peripherals. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 81 Jennic B.3 Applications Information B.3.1 Typical Application Schematic UART 1 RESET C10 Y1 C11 Two Wire Serial Port Vcc Timers C13 UART 0 K L C _ F S I T U O 1 M T I P A C 1 M T I D _ F S I T G _ K C 1 M T I T U O 0 M T I P A C 0 M T I 2 D D V T G _ K C 0 M T I 0 D X R 0 D X T 0 S T R 0 S T C 4 L E S P S I 43 SPI Selects 1 I/O Line CTS1 VB_PROT RTS1 C7 TXD1 RXD1 VSS2 RESETN VSS3 VSSS XTALOUT XTALIN VB_SYN VCOTUNE C9 R4 Vcc 15 O C V _ B V C2 C12 C15 C8 Jennic IC1: JN513x C6 C5 IC2 Serial Flash Memory Vcc 1 2 3 4 SS Vcc SDO HOLD WP Vss CLK SDI 8 7 6 5 SPISEL3 SPISEL2 VB_MEM VSS1 SPISEL1 SPISEL0 MOSI VB_APP MISO SPICLK COMP2M COMP2P DAC2 DAC1 29 1 D D V M 1 P M O C S A B I I P 1 P M O C P F R F R _ B V M F R F E R V 1 C D A 2 C D A 3 C D A 4 C D A A _ B V C1 C3 R9 C4 Printed Antenna Figure 50: Application Schematic Analogue IO Components C1, C2, C3, C4, C5, C6, C7, C12, C13, C15 C10, C11 C9 C8 R4 R9 Y1 IC1 IC2 Values 100nF 15pF (COG) 3n3F 330pF (COG) 4k7 43k TSX-10A 16MHz Crystal TN4-25820 JN513x 128kB Serial Flash Table 3: Bill of Materials 82 JN-DS-JN513x v1.4 Preliminary Jennic 2007 B.3.2 PCB Requirements Jennic recommend that a standard 4layer printed circuit board be used for design, with the individual layers organised as shown below in Figure 51. Jennic Copper (0.5 oz 17 m) Dielectric FR4 pre-preg 0.009 x 1 Copper (0.5 oz 17 m) Dielectric FR4 0.02 x 1 Copper (0.5 oz 17 m) Dielectric FR4 pre-preg 0.009 x 1 Copper (0.5 oz 17 m) A B A Top Metal Dielectric 1 Mid 1 metal Dielectric 2 Mid 2 metal Dielectric 3 Bottom metal Total Dim (mm) Description Dimension Tolerance 0.017 0.5 oz copper 0.2286 Er = TBD 0.017 0.5 oz copper 0.508 Er = TBD 0.017 0.5 oz copper 0.2286 Er = TBD 0.017 0.5 oz copper 1.0332 mm Dimension A TBD Dimension B TBD Dimension A TBD NOT TO SCALE Figure 51: PCB Cross-Section From top to bottom, the layers are:
Component Ground Digital tracks Power and tracks The material is standard FR4. While no special measures are required for the board design, it is recommended that Class 1 tolerances be used.
Note: The Jennic PCB layout assumes the layers defined above. If a different PCB thickness is used then the RF track thickness and layout will need to be re-assessed. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 83 Jennic B.3.3 Supply Decoupling C12 is the decoupling capacitor for the analogue areas of IC1. It is placed as close as possible to the IC1 pin VDD1. C13 is the decoupling capacitor for the digital areas of IC1. It is also used to decouple the supply on the Flash memory due to:
placement of the Flash memory power pin (IC2 Pin 8) next to the IC1 Pin VDD2 the fact that the Flash memory is only used during booting (unless reprogramming), so the RF areas of the device are not active. B.3.4 Reference Oscillator Requirements The device contains the necessary on-chip components to build a 16-MHz reference oscillator with the addition of an external crystal resonator. The schematic in Figure 50: Application Schematic shows the crystal circuit in the form of capacitors C10 and C11, together with a crystal resonator Y1. The reference crystal serves many purposes, including the provision of a reference for the 32-bit RISC processor, PHY controller, radio synthesiser and analogue peripherals. In addition, the crystal also provides timing references for external I/O (e.g. on-chip UARTs) and timer counters. Thus, it is important that the crystal reference is specified and built correctly to ensure that the system functions properly. The external crystal resonator, Y1, is connected to IC1 via two coupling capacitors, C10 and C11, that 15 pF 5%
and use a C0G dielectric the 15 pF will need to vary for alternate crystals. This is important, in order to ensure that the oscillator Q-factor is maximised and the temperature co-efficient is minimised. The choice of crystal resonator is important for the following reasons:
Resonator tolerance: A number of parameters, ranging from on-chip timings to radio centre-frequency, are derived directly from the tolerance of the crystal. As indicated in the component list, we recommend that a total tolerance of less than 35 ppm is used, as the maximum permissible offset specified in IEEE 802.15.4 is 40 ppm. Also note that this tolerance should include both temperature and ageing effects imparted on the resonator. Resonator load capacitance: The active oscillator components on the JN5121 and JN513x series devices are designed for a crystal resonator with load capacitance of 9 pF. This is a standard loading, and resonators of this type are widely available. B.3.5 Reference Oscillator Layout Considerations The layout of the oscillator circuit is such that the components are close together. This improves the performance of the oscillator by reducing parasitic impedance and the likelihood of cross-talk. We also recommend that the symmetry of layout be maximised in order to avoid uneven loading of the crystal resonator. B.3.6 VCO Tune Circuit Component Specifications Jennic wireless microcontroller devices employ an RF Phase Locked Loop (PLL). With respect to the schematic in Figure 50: Application SchematicError! Reference source not found., the only external components required on the printed circuit board are two capacitors, C8 and C9, together with the resistor R4.
! Caution: It is essential that the component values advised here are followed, since their substitution could lead to failure in the PLL. 84 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic B.3.7 VCO Tune Circuit Layout Considerations The layout of these components is such that all three components are close together, and close to the VCO_TUNE and VB_VCO pins on the wireless microcontroller IC. This improves the performance of the PLL by reducing parasitic impedance and the likelihood of cross-talk. B.3.8 Radio Front-End The radio part of the wireless microcontroller device has an internal transmit-receive switch connected to the external pins on the chip (RF- and RF+). The PHY controller configures the switch between transmit and receive. In both configurations, the connection to the device is a differential 200-ohm configuration. As an example of how this may be used, the 200-ohm differential antenna connection (RF- and RF+) can be fed to a miniature balun to convert to a single-ended 50-ohm microstrip line which, in turn, can be connected to a small ceramic antenna.
Note: The PCB layout is very important for all of the external radio connections and associated power supplies. In this respect, the tolerances indicated in Figure 51 are particularly important. B.3.9 Antennae There are many different antenna configurations that could function for a 2.4-GHz transceiver. The free-space wavelength at 2.4 GHz is approximately 12 cm, which means that a standard half-wave dipole would be approximately 6 cm. When advising on antenna design, it is dangerous to generalise. However, designers of any low-power radio device must strive to ensure that as little power as possible is wasted in producing a radio signal transmission. This involves careful consideration of the terms antenna efficiency, antenna directivity and antenna gain:
Antenna Efficiency: This is a measure of how much energy fed into the antenna feed is actually retained in the radio transmission. For example, a small antenna may exhibit an efficiency of approximately 50%, which means that half the power fed into or out of the antenna is wasted. Clearly, it is important to keep efficiency as high as possible. However, small antennae exhibit lower efficiency than large antennae. Antenna Directivity: An antenna radiation pattern indicates in which direction the power fed into an antenna actually radiates. In situations where antennae can be aligned to see each other, this can be advantageous. However, many situations do not allow this, since a path from one device to another may occur in any direction. In general, larger antennae have a greater ability to radiate in a specific direction. In antenna terminology, this is called the directivity. For instance, an antenna with a directivity of 3 dBi has the ability to radiate twice as much power in one direction when compared with a theoretical omni-directional antenna. This is fine if both antennae are aligned in this direction, but it is not good if they are misaligned. Antenna Gain: Often, the term gain is used when discussing antennae. This term should be treated with some caution since it is the product of efficiency and directivity. A poor-efficiency antenna with a high directivity can still exhibit a reasonable gain; however, power is still being wasted somewhere!
A list of antennae and suppliers can be found in the Application Note Antennae for use with JN51xx (JN-AN-1030), available on the Jennic web site. B.3.10 Ground Planes The recommendation for a four-layer design allows the best use of the ground planes, with this in mind the following restrictions should be placed on the layout:
All RF signals are confined to the top layer. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 85 Jennic The second layer is Ground and has no tracks on it. This allows the best return path for all RF signals and will reduce noise effects. The bottom layer contains all other signals and the Vcc power supply for the module. The ground planes on all layers stop BEFORE the antenna, so that the performance of the antenna is not affected. The recommended antenna clearance for a surface-mounted ceramic antenna is shown below. 20 CLEARANCE
(no ground plane) 50 transmission line ANTENNA CHIP 20 20 CLEARANCE
(no ground plane) Dimensions in mm Figure 52: Antenna Clearance Recommendations B.3.11 Manufacturing Considerations The TQFN package must be considered carefully when using reflow solder techniques. The following are recommendations:
The decal is shown in Figure 53. The pad stacks used are 0.25 mm by 1 mm for the smaller pads, and a 6.4-
mm square pad for the paddle. Figure 53: Recommended PCB Decal for 56QFN Package The solder mask used is shown in Figure 54. The pad stacks used are 0.25 mm by 1 mm for the smaller pads, and two 2-mm square pads to apply paste to the paddle. The solder paste mask has a thickness of 6 thou (0.152 mm). JN-DS-JN513x v1.4 Preliminary Jennic 2007 86 Jennic Figure 54: Recommended Solder Paste Mask for 56QFN Package Nine vias are applied to the paddle. These allow excess solder paste and heated air to be vented away from the device, preventing the device from being lifted during soldering. Figure 55: Vias on the Paddle of the 56QFN Package B.3.12 Bespoke Solutions - PCB Layout Suggestions The list presented below provides some key suggestions when using a wireless microcontroller on a bespoke, multi-
layer PCB. Clearly, the list is not exhaustive and you may have more detailed considerations in using mixed-signal integrated circuits. Shared vias: Often in layout, it is convenient for a number of components to share a return to Analog Ground. Examples include bypass capacitors and reference setting resistors. We recommend that all components are given a separate via to ground. This avoids noise feed-through and poor isolation issues that often occur if a via is shared. Oscillator circuit: We recommend that tracks from the oscillator pins are kept to the same length and, ideally, on the top layer. This avoids asymmetrical loading of the crystal resonator. The placement of the two capacitors should be symmetrical to the crystal. This also avoids asymmetrical loading of the reference oscillator. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 87 Jennic VCOTune circuit: The components defined in the schematic should be used in order to set the PLL bandwidth correctly. It is also essential to keep these components close to the chip, with minimum track lengths. B.3.13 Using a Balun When using a single ended antenna, the wireless microcontroller will use a balun and should be connected as indicated in Figure 56. The tracks between IC1 pins RF+ and RF-, and the balanced side of the balun, are on the top layer. These are impedance-controlled tracks, designed to provide the 200-ohm differential matched impedance required by the device at its RF port. With the exception of the via connected to the VB_RF pin, other nearby tracks should be placed such that there is at least three times the track width of unbroken ground on either side and underneath the tracks. The other side of the balun should be connected to the antenna. This track is an unbalanced microstrip RF track operating at 2.4 GHz. It should be impedance controlled to 50 ohms for a good RF input match. GND plane to be cut underneath differential tracks Top View To wireless microcontroller Track widths to give 200 ohm differential line Track width to give 50 ohm line GND BALUN GND Figure 56: Connecting the Balun B.3.14 Decoupling Capacitors Three capacitors should be used:
Two ceramic 100-nF capacitors - one should be placed close to pin VDD1, the other should be placed close to pin VDD2 One 10-F electrolytic capacitor connected to ground - if the PCB is a module then place this capacitor close to the point where the power enters the module. B.3.15 Internal Regulator Smoothing Capacitors A ceramic 100-nF capacitor should be connected to each of the following pins. Place these capacitors close to the device and make the tracks as thick as possible to improve RF bypass/decoupling. Some pins require an additional 47-pF capacitor. Details are given below. 88 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Pin Name VP_PROT VB_SYN VB_VCO VB_RF VB_A VB_APP VB_MEM 47-pF Capacitor Required Jennic
B.3.16 VREF A ceramic 100-nF capacitor should be placed as close as possible to the VREF pin. B.3.17 IBIAS A 43-k resistor should be connected as close as possible to the IBIAS pin. B.3.18 EMC For good EMC performance, it is necessary to minimise any ground loops when laying out the PCB. Jennic 2007 JN-DS-JN513x v1.4 Preliminary 89 Jennic Appendix C Related Documents
[1] IEEE Std 802.15.4-2003 IEEE Standard for Information technology Part 15.4 Wireless Medium Access Control
(MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs)
[2] JN-RM-2001 Integrated Peripherals API
[3] JN-RM-2002 802.15.4 Stack API
[4] JN-AN-1003 Boot Loader Operation RoHS Compliance JN513x devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). Status Information The status of this Data Sheet is Preliminary. Jennic products progress according to the following format:
Advanced The Data Sheet shows the specification of a product in planning or in development. The functionality and electrical performance specifications are target values and may be used as a guide to the final specification. Integrated circuits are identified with an R suffix, for example JN5139-Z01R. Jennic reserves the right to make changes to the product specification at anytime without notice. Preliminary The Data Sheet shows the specification of a product that is in production, but is not yet fully qualified. The functionality of the product is final. The electrical performance specifications are target values and may used as a guide to the final specification. Integrated circuits are identified with an R suffix, for example JN5139-Z01R. Jennic reserves the right to make changes to the product specification at anytime without notice. Production This is the final Data Sheet for the product. All functional and electrical performance specifications, including minimum and maximum values are final. This Data Sheet supersedes all previous document versions. Jennic reserves the right to make changes to the product specification at anytime to improve its performance. 90 JN-DS-JN513x v1.4 Preliminary Jennic 2007 Jennic Disclaimers The contents of this document are subject to change without notice. Jennic reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained herein in order to improve design and/or performance. Information contained in this document regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Jennic warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Jennics standard warranty. Testing and other quality control techniques are used to the extent Jennic deems necessary to support this warranty. Except where mandatory by government requirements, testing of all parameters of each product is not necessarily performed. Jennic assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work infringement, unless otherwise specified. Jennic products are not intended for use in life support systems, appliances or systems where malfunction of these products can reasonably be expected to result in personal injury, death or severe property or environmental damage. Jennic customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Jennic for any damages resulting from such use. All trademarks are the property of their respective owners. Version Control Version 1.0 1.1 1.2 1.3 1.4 Notes 22rd December 2006 - First Release 9th February 2007 Added solder reflow profile 16th July 2007 uplifted to Preliminary status, typical specification updates, internal reset modifications 31st July 2007 updates to DC current consumptions 26th October 2007 updated applications information, added PCB decal including paddle details Jennic 2007 JN-DS-JN513x v1.4 Preliminary 91 Jennic Contact Details Corporate Headquarters Jennic Ltd, Furnival Street Sheffield S1 4QT, UK Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 info@jennic.com www.jennic.com Jennic Ltd Japan Osakaya building 4F 1-11-8 Higashigotanda Shinagawa-ku Tokyo 141-0022, Japan Tel: +81 3 5449 7501 Fax: +81 3 5449 0741 info@jp.jennic.com www.jennic.com Jennic Ltd Taiwan 19F-1, 182, Sec.2 Tun Hwa S. Road. Taipei 106, Taiwan Tel: +886 2 2735 7357 Fax: +886 2 2739 5687 info@tw.jennic.com www.jennic.com Jennic America Inc - West Coast Office 1322 Scott Street, Suite 203 Point Loma, CA 92106, USA Tel: +619 223 2215 Fax: +619 223 2081 info@us.jennic.com www.jennic.com Jennic America Inc - East Coast Office 1060 First Avenue, Suite 400 King of Prussia, PA 19406, USA Tel: +1 484 868 0222 Fax: +1 484 971 5015 info@us.jennic.com www.jennic.com Jennic Ltd Korea 701, 7th Floor, Kunam Bldg., 831-37, Yeoksam-Dong, Kangnam-ku Seoul 135-080 Korea Tel: +82 2 552 5325 Fax: +82 2 3453 8802 info@kr.jennic.com www.jennic.com 92 JN-DS-JN513x v1.4 Preliminary Jennic 2007
1 2 | User Manual | Users Manual | 254.36 KiB |
Advanced Information Advanced Data Sheet JN5139-xxx-Myy IEEE802.15.4/ZigBee Module Family Overview The JN5139-xxx-Myy family is a range of surface mount modules that enable users to implement IEEE802.15.4 or ZigBee compliant systems with minimum time to market and at the lowest cost. They remove the need for expensive and lengthy development of custom RF board designs and test suites. The modules use Jennics JN5139 wireless microcontroller to provide a comprehensive solution with high radio performance and all RF components included. All that is required to develop and manufacture wireless control or sensing products is to connect a power supply and peripherals such as switches, actuators and sensors, considerably simplifying product development. Three basic hardware module variants are available: JN5139-xxx-M00 with an integrated antenna, JN5139-xxx-M01/M03 with an antenna connector and JN5139-
xxx-M02/M04 with a power amplifier and LNA for extended range. Each variant can be provided pre-programmed with a ZigBee network stack (JN5139-Z01-Myy). Module Block Diagram External Antenna Ceramic Antenna Balun M00 Option Connector Balun M01/03 Option Connector Balun PA / LNA M02/04 Option XTAL JN5139 chip RAM 96kB ROM 192kB 2.4GHz Radio O-QPSK Modem RISC CPU IEEE802.15.4 MAC Accelerator Power Management 128-bit AES Encryption Accelerator 128kB Serial Flash Memory SPI 2-wire serial Timers UARTs 12-bit ADC, comparators 11-bit DACs, temp sensor Power Benefits Microminiature module solutions Ready to use in products Minimises product development time No RF test required for systems Compliant with FCC part 15 rules, ETSI ETS 300-328 and Japan ARIB STD-T66 Production volumes supplied pre-programmed with application software Applications Robust and secure low power wireless applications Wireless sensor networks, particularly IEEE802.15.4 /
ZigBee systems Home and commercial building automation Home networks Toys and gaming peripherals Telemetry and utilities Industrial systems
(e.g. AMR) Features: Module 2.4GHz IEEE802.15.4 & ZigBee compliant 2.7-3.6V operation Sleep current (with active sleep timer) 2A JN5139-xxx-M00/01/03
> 1km range M00 has on board antenna M01 has SMA connector M03 has uFl connector o Receiver sensitivity -97dBm o TX power +3dBm o TX current < 39mA o RX current < 39mA o 18x30mm JN5139-xxx-M02/04
> 4km range M02 has SMA connector M04 has uFl connector o Receiver sensitivity -100dBm o 19dBm TX power o TX current < 120mA o RX current < 45mA o 18x40.5mm Features: Microcontroller 16MHz 32-bit RISC CPU 96kB RAM, 192kB ROM 4-input 12-bit ADC, 2 11-bit DACs, 2 comparators, temperature sensor 2 Application timer/counters, 3 system timers 2 UARTs (one for in-system debug) SPI port with 5 selects 2-wire serial interface 21 GPIO Evaluation kits available with full, unlimited, Software Development Kit Industrial temperature range
(-20C to +70C) Lead-free and RoHS compliant Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 JN5139 Single Chip Wireless Microcontroller Jennic Contents 1. Introduction 1.1. Variants 1.2. Regulatory Approvals 2. Specifications 3. Product Development 3.1. 4. Pin Configurations 4.1. Pin Assignment 4.2. Pin Descriptions 4.3. Power Supplies 4.4. SPI Memory Connections 5. Electrical Characteristics 5.1. Maximum Ratings 5.2. Operating Conditions Appendix A Additional Information A.1 Outline Drawing A.2 Module PCB Footprint A.3 Ordering Information A.4 Tape and Reel Information:
A.4.1 Tape Orientation and dimensions A.4.2 Cover tape details A.4.3 Leader and Trailer A.4.4 Reel Dimensions:
A.5 Related Documents A.6 Federal Communication Commission Interference Statement A.7 RoHS Compliance A.8 Status Information A.9 Disclaimers A.10 Version Control A.11 Contact Details 3 3 3 4 5 5 6 7 8 8 8 9 9 9 10 10 15 16 17 17 17 18 18 19 19 20 20 21 21 22 ii Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 Jennic 1. Introduction The JN5139-xxx-Myy module family provides designers with a ready made component which allows IEEE802.15.4 [1]
wireless applications, including ZigBee, to be quickly and easily included in product designs. The modules integrate all of the RF components, removing the need to perform expensive RF design and test. Products can be designed by simply connecting sensors and switches to the module IO pins. The modules use Jennics single chip IEEE802.15.4 Wireless Microcontroller, allowing designers to make use of the extensive chip development support material. Hence, this range of modules allows designers to bring wireless applications to market in the minimum time with significantly reduced development effort and cost. Three basic module hardware variants are available: JN5139-xxx-M00 (standard module with on board ceramic antenna), JN5139-xxx-M01 (standard module with SMA connector for use with external antennae) and JN5139-xxx-
M02 (high RF power, improved sensitivity module for extended range applications). uFL connector variants are provided (-M03 standard power and M04 high power) for FCC approved products and for applications where a small connector size is required. Each of these modules can be supplied with a range of protocol stacks, including a simple IEEE802.15.4 protocol for point to point and star applications and a ZigBee mesh networking stack. The variants available are described below. 1.1. Variants Variant JN5139-001-M00 JN5139-Z01-M00 JN5139-001-M01 JN5139-Z01-M01 JN5139-001-M02 JN5139-Z01-M02 JN5139-001-M03 JN5139-Z01-M03 JN5139-001-M04 JN5139-Z01-M04 Description JN5139 Module (IEEE802.15.4 stack, ceramic antenna) JN5139 Module (ZigBee stack, ceramic antenna) JN5139 Module (IEEE802.15.4 stack, SMA connector) JN5139 Module (ZigBee stack, SMA connector) JN5139 Module (High Power (18.5dBm), IEEE802.15.4 stack, SMA connector) JN5139 Module (High Power (18.5dBm), ZigBee stack, SMA connector) JN5139 Module (IEEE802.15.4 stack, uFl connector) JN5139 Module (ZigBee stack, uFl connector) JN5139 Module (High Power (18.5dBm), IEEE802.15.4 stack, uFl connector) JN5139 Module (High Power (18.5dBm), ZigBee stack, uFl connector) 1.2. Regulatory Approvals All module types have been tested against the requirements of European standard ETS 300 328 and a certificate of compliance to this standard is available on request. The High Power modules with M02 suffix are approved for use in Europe with reduced output power. They must not be used with PHY_PIB_ATTR_TX_POWER set above 3 See [4]. Additionally, modules with M00, M03 and M04 suffixes have received FCC Modular Approvals, in compliance with CFR 47 FCC part 15 regulations and in accordance to FCC Public notice DA00-1407. The modules are approved for use with the following half wave dipole antenna families: EAD BKR2400 series, Antenna Factor RCT and RCL series, Centurion WCR2400 & WRR2400, GigaAnt Titanis and Nearson Models 131, 141 & 145. See Appendix A.6 for details on the conditions applying to this modular approval. The high power module variant is classified as mobile device pursuant with FCC 2.1091 and must not be used at a distance of < 20 cm (8) from any nearby people. Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 3 Jennic 2. Specifications Most specification parameters for the modules are specified in JN-DS-JN513x Datasheet for JN5139 single chip wireless microcontroller, [2]. Where there are differences, the parameters are defined here. VDD=3.0V @ +25C Typical DC Characteristics Deep sleep current Sleep current Radio transmit current Radio receive current JN5139-xxx-
M00/01/03
<1uA
<2uA 40mA 40mA JN5139-xxx-
M02/04
<1uA
<2uA 120mA 45mA Centre frequency accuracy
+/-25ppm
+/-25ppm Typical RF Characteristics Receive sensitivity Max. Transmit power Transmit power at 3.6V Maximum input signal RSSI range RF Port impedance SMA/uFl connector VSWR (max) Peripherals Master SPI port with five select outputs Slave SPI port Two UARTs Two-wire serial I/F (compatible with SMbus & I2C) Two programmable Timer/Counters with capture/compare facility, Tick timer Two programmable Sleep Timers Twenty-one digital IO lines (multiplexed with UARTs, timers and SPI selects) Four-channel, 12-bit, Analogue-to-Digital converter Two 11-bit Digital-to-Analogue converters Two programmable analogue comparators Internal temperature sensor and battery monitor
-96.5dBm
-100dBm
+2.5dBm
-10dBm
-95 to -10 dBm 50 ohm 2:1 18dBm 19dBm
-15dBm
-115 to -20 dBm 50 ohm 2:1 Notes With active sleep timer CPU in doze, radio transmitting CPU in doze, radio receiving Additional +/-15ppm allowance for temperature and aging Notes Nominal for 1% PER, as per 802.15.4 section 6.5.3.3 Nominal With Vdd=3.6V For 1% PER, measured as sensitivity 2.4 - 2.5GHz 2.4 - 2.5GHz Notes 250kHz - 16MHz 250kHz - 16MHz 16550 compatible Up to 400kHz 16MHz clock 32kHz clock Up to 100ks/s Up to 100ks/s Ultra low power mode for sleep 4 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 Jennic 3. Product Development Jennic supplies all the development tools and networking stacks needed to enable end product development to occur quickly and efficiently. These are all freely available from Jennics support website: http://www.jennic.com/support/ . A range of evaluation/developer kits is also available, allowing products to be quickly breadboarded. Efficient development of software applications is enabled by the provision of a complete, unlimited, software developer kit. Together with the available libraries for the IEEE802.15.4 MAC and the ZigBee network stack, this package provides everything required to develop application code and to trial it with hardware representative of the final module. The modules can be programmed by the user, for both development and production, using Jennic supplied software. They can also be supplied ready loaded with customer defined software if required. The JN-UG-3007 Flash Loader User Guide [5], describes how to put the module into programming mode, download software onto it and to load individual MAC addresses. Access to the on-chip peripherals, MAC and ZigBee stack software is provided through specific APIs. These are described in the JN-RM-2001 Hardware Peripheral Library Reference Manual [3], JN-RM-
2002 Stack Software Reference Manual [4] and JN-RM-2014 ZigBee Application Development API Reference Manual [6]. Additional information is available on the Jennic support website. 3.1. JN5139 Single Chip Wireless Microcontroller The JN5139-xxx-Myy series is constructed around the JN5139 single chip wireless microcontroller, which includes the radio system, a 32-bit RISC CPU, ROM and RAM memory and a range of analogue and digital peripherals. The chip is described fully in JN-DS-JN513x Datasheet for JN5139 single chip wireless microcontroller [2]. Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 5 Jennic 4. Pin Configurations a J1 n n e t n A ADC4 DAC1 DAC2 COMP2+
COMP2-
SPICLK SPIMISO SPIMOSI SPISSZ DIO0/SPISEL1 DIO1/SPISEL2 DIO2/SPISEL3 SPISSM SPISWP DIO3/SPISEL4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 D D V D N G A S S V 0 S T C 4 O D I
0 S T R 5 O D I
0 D X T 6 O D I
0 D X R 7 O D I
I T G 0 M T 8 O D I
P A C _ 0 M T 9 O D I
I I T G 1 M T 1 1 O D I
T U O _ 0 M T
0 1 O D I I 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 ADC3 ADC2 ADC1 COMP1+
COMP1-
DIO20/RXD1 DIO19/TXD1 DIO18/RTS1 DIO17/CTS1 DIO16 DIO15/SIF_D DIO14/SIF_CLK RESETN DIO13/TIM1_OUT DIO12/TIM1_CAP Figure 1: Pin Configuration (top view) Note that the same basic pin configuration applies for all module designs. However, DIO3/SPISEL4 and DIO2/SPISEL3 are not available with high power modules. 6 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 4.1. Pin Assignment Function Pin Signal Jennic Alternative Function ADC4 DAC1 DAC2 COMP2+
COMP2-
SPICLK Analogue to Digital input Digital to Analogue output Digital to Analogue output Comparator 2 inputs SPI master clock out SPIMISO SPI Master In/Slave Out SPIMOSI SPI Master Out/Slave In SPISSZ SPI select from module - SS0 (output) SPISEL1 SPI Slave Select1 (output) SPISEL2 SPI Slave Select2 (output) General Purpose Digital I/O DIO0 General Purpose Digital I/O DIO1 SPISEL3*
SPI Slave Select3 (output) General Purpose Digital I/O DIO2 *
SPISSM SPI select to FLASH (input) SPISWP FLASH write protect (input) SPI Slave Select4 (output) General Purpose Digital I/O DIO3*
UART0 Clear To Send (input) General Purpose Digital I/O DIO4 UART0 Request To Send (output) General Purpose Digital I/O DIO5 UART0 Transmit Data (output) General Purpose Digital I/O DIO6 SPISEL4*
Hi CTS0 t RTS0 TXD0 RXD0 UART0 Receive Data (input) TIM0GT Timer0 clock/gate (input) TIM0_CAP Timer0 capture (input) TIM0_OUT Timer0 PWM (output) TIM1GT Timer1 clock/gate (input) VDD GND VSSA 3V power Digital ground Analogue ground TIM1_CAP Timer1 capture (input) TIM1_OUT Timer1 PWM (output) RESETN Active low reset General Purpose Digital I/O DIO7 General Purpose Digital I/O DIO8 General Purpose Digital I/O DIO9 General Purpose Digital I/O DIO10 General Purpose Digital I/O DIO11 General Purpose Digital I/O DIO12 General Purpose Digital I/O DIO13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SIF_CLK Serial Interface clock / Intelligent peripheral clock General Purpose Digital I/O DIO14 Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 7 Jennic Pin Signal Function 31 32 33 34 35 36 37 38 39 40 41 SIF_D DIO 16 CTS1 RTS1 TXD1 RXD1 COMP1-
COMP1+
ADC1 ADC2 ADC3 Serial Interface data / Intelligent peripheral data t Intelligent peripheral device select Alternative Function General Purpose Digital I/O DIO15 General Purpose Digital I/O UART1 Clear To Send (input) General Purpose Digital I/O DIO17 UART1 Request To Send (output) General Purpose Digital I/O DIO18 UART1 Transmit Data (output) General Purpose Digital I/O DIO19 UART1 Receive Data (input) General Purpose Digital I/O DIO20 Comparator 1 inputs Analogue to Digital input Analogue to Digital input Analogue to Digital input
*: These two pins are not connected for High power modules 4.2. Pin Descriptions All pins behave as described in the JN513x datasheet [2], with the exception of the following:
4.3. Power Supplies A single power supply pin, VDD is provided. Separate analogue (VSSA) and digital (GND) grounds are provided. These should be connected together at the module pins. 4.4. SPI Memory Connections SPISWP is a write protect pin for the serial flash memory. This should be held low to inhibit writes to the flash device. SPISSZ is connected to SPI Slave Select 0 on the JN5139. SPISSM is connected to the Slave Select pin on the memory. This configuration allows the flash memory device to be programmed using an external SPI programmer if required. For programming in this mode, the JN5139 should be held in reset by taking RESETN low. The memory can also be programmed over the UART by using the programming mode described in JN-UG-3007 Flash Loader User Guide [5]. For normal operation of the module and programming over the UART, SPISSZ should be connected to SPISSM. 8 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 5. Electrical Characteristics In most cases, the Electrical Characteristics are the same for both module and chip. They are described in detail in the chip datasheet. Where there are differences, they are detailed below. Jennic 5.1. Maximum Ratings Exceeding these conditions will result in damage to the device. Parameter Device supply voltage VDD Voltage on analogue pins ADC1-4, DAC1-2, COMP1+, COMP1-, COMP2+, COMP2-, SPICLK, SPIMOSI, SPIMISO, SPISSM, SPISWP Voltage on 5V tolerant digital pins DIO-DIO20, RESETN, SPISSZ Storage temperature Solder reflow temperature (According to IPC/JEDEC J-STD-020C) Min
-0.3V
-0.3V
-0.3V
-40C Max 3.6V VDD + 0.3V VDD + 2V or 5.5V, whichever is the lesser 150C 260 C This device is sensitive to ESD and should only be handled using ESD precautions. 5.2. Operating Conditions Supply VDD Ambient temperature range Min 2.7V
-20C Max 3.6V 70C Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 9 Jennic Appendix A Additional Information A.1 Outline Drawing 18mm J1 a n n e t n A 30mm Thickness: 3.5mm 10 1.27 mm 2.54 mm 2.54 mm 2.79 mm JN5139-xxx-M00 Outline Drawing Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 Jennic 18mm 9.74mm 4.59mm 30mm 1.27 mm 2.54 mm 2.54 mm 2.79 mm Thickness: 3.5mm over can, 10.6mm at SMA connector JN5139-xxx-M01 Outline Drawing Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 11 Jennic 30mm 18mm 9.76mm 6.58mm 1.27 mm 2.54 mm 2.54 mm Thickness: 3.5mm 2.79 mm JN5139-xxx-M03 Outline Drawing 12 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 Jennic 18mm 7.2mm 4.05mm 40.5mm
. 2.54 mm 1.27 mm 2.54 mm 2.79 mm Thickness: 3.5mm over can, 10.6mm at SMA connector. Note that early versions of this board will be 40mm long but the SMA connector will remain in the same location with respect to the pcb pads. JN5139-xxx-M02 Outline Drawing Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 13 Jennic 40.5mm
. 2.54 mm Thickness: 3.5mm 18mm 7.2mm 3.99mm 1.27 mm 2.54 mm 2.79 mm JN5139-xxx-M04 Outline Drawing 14 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 A.2 Module PCB Footprint 18mm Jennic 1.27 mm 2.54 mm 2.54mm All Pads are 0.9mm square on 1.27mm pitch Note: All modules have the same footprint. RF note for M00 modules with ceramic antenna: No components, ground plane or tracks on any layer of the mother board should be placed within 20mm of the 3 free sides of the antenna. Tracks etc may be placed adjacent to the can, but should not extend past the can towards the antenna end of the module for 20mm from the antenna. Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 15 Jennic A.3 Ordering Information Part Numbering:
JN5139 - XXX - MY1Y2 Y3 Y4 Shipping R T V Box (10 modules per pack) Tape Mounted 500pcs (00 module only) Tape Mounted 200pcs (01,02,03,04 modules only) Temp Range / Device Status D
-20C to +70C, Qualified Module Type 00 01 02 03 04 Standard Power, Ceramic antenna Standard Power, SMA connector High Power, SMA connector Standard Power, uFl connector High power, uFl connector Software Variant 001 Z01 ZigBee Stack IEEE802.15.4 Stack 16 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 A.4 Tape and Reel Information:
A.4.1 Tape Orientation and dimensions Jennic Module type:
A B JN5139-xxx-M00/03 18.4 30.4 JN5139-xxx-M01 18.4 30.4 JN5139-xxx-M02 18.5 40.5 JN5139-xxx-M04 18.5 40.9 W 44 56 56 56 F E P0 P1 P2 T Cover Tape width (W) 20.2 1.75 20.2 1.75 20.2 1.75 20.2 1.75 4.0 4.0 4.0 4.0 2.0 2.0 2.0 2.0 24.0 3.4 37.5 24.0 11.4 49.5 24.0 11.4 49.5 24.0 3.4 49.5 Tolerance 0.1 0.1 0.3 0.1
+0.1 0.1 0.1 0.1 0.1 0.1 A.4.2 Cover tape details Thickness (T) 0.061mm Surface resistivity (component side) 104 to 107 Ohms/sq Surface resistivity (component side) Non-conductive Backing type:
Adhesive type:
Sealing:
Polyester PSA Room ambient Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 17 Jennic A.4.3 Leader and Trailer 300 MM A.4.4 Reel Dimensions:
300 MM Module type:
JN5139-xxx-M00 JN5139-xxx-
M01/02/03/04 A 330 1.0 330 1.0 B 2.20.5 2.20.5 C 13 0.2 13 0.2 N 100 +0.1 100 +0.1 W (min) 44.5 0.3 56.5 0.3 18 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 A.5 Related Documents
[1] IEEE Std 802.15.4-2003 IEEE Standard for Information Technology Part 15.4 Wireless Medium Access Control
(MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) Jennic
[2] JN-DS-JN513x Datasheet for JN5139 single chip wireless microcontroller
[3] JN-RM-2001 Hardware Peripheral Library Reference Manual
[4] JN-RM-2002 Stack Software Reference Manual
[5] JN-UG-3007 Flash Loader User Guide
[6] JN-RM-2014 ZigBee Application Development API Reference Manual A.6 Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. WARNING!
FCC Radiation Exposure Statement:
This portable equipment with its antenna complies with FCCs RF radiation exposure limits set forth for an uncontrolled environment. To maintain compliance follow the instructions below;
1. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. 2. Avoid direct contact to the antenna, or keep it to a minimum while using this equipment. This transmitter module is authorized to be used in other devices only by OEM integrators under the following condition:
The transmitter module must not be co-located with any other antenna or transmitter. Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 19 Jennic As long as the above condition is met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). High Power Module usage limitation The high power module variants are classified as mobile device pursuant with FCC 2.1091 and must not be used at a distance of < 20 cm (8) from any nearby people. IMPORTANT NOTE: In the event that these conditions can not be met (for certain configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product
(including the transmitter) and obtaining a separate FCC authorization. The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user manual of the end product. The user manual for the end product must include the following information in a prominent location;
To comply with FCCs RF radiation exposure requirements, the antenna(s) used for this transmitter must not be co-
located or operating in conjunction with any other antenna or transmitter. A.7 RoHS Compliance JN5139-xxx-Myy devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). A.8 Status Information The status of this Data Sheet is Advanced. Jennic products progress according to the following format:
Advanced The Data Sheet shows the specification of a product in planning or in development. The functionality and electrical performance specifications are target values and may be used as a guide to the final specification. Jennic reserves the right to make changes to the product specification at anytime without notice. Preliminary The Data Sheet shows the specification of a product that is in production, but is not yet fully qualified. The functionality of the product is final. The electrical performance specifications are target values and may used as a guide to the final specification. Modules are identified with an R suffix, for example JN5139-Z01-M00R. Jennic reserves the right to make changes to the product specification at anytime without notice. Production This is the final Data Sheet for the product. 20 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007 Jennic All functional and electrical performance specifications, including minimum and maximum values are final. This Data Sheet supersedes all previous document versions. Jennic reserves the right to make changes to the product specification at anytime to improve its performance. A.9 Disclaimers The contents of this document are subject to change without notice. Jennic reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained herein in order to improve design and/or performance. Information contained in this document regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Jennic assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work infringement, unless otherwise specified. Jennic products are not intended for use in life support systems, appliances or systems where malfunction of these products can reasonably be expected to result in personal injury, death or severe property or environmental damage. Jennic customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Jennic for any damages resulting from such use. All trademarks are the property of their respective owners. A.10 Version Control Version Notes 1st Issue of Advanced Datasheet Update to correct connector positions on drawings and typo on module numbering. 000 modules now read 001. 1.0 1.1 Jennic 2007 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 21 Jennic A.11 Contact Details Corporate Headquarters Jennic Ltd, Furnival Street Sheffield S1 4QT, UK Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 info@jennic.com www.jennic.com Jennic Ltd Japan Osakaya building 4F 1-11-8 Higashigotanda Shinagawa-ku Tokyo 141-0022, Japan Tel: +81 3 5449 7501 Fax: +81 3 5449 0741 info@jp.jennic.com www.jennic.com Jennic Ltd Taiwan 19F-1, 182, Sec.2 Tun Hwa S. Road. Taipei 106, Taiwan Tel: +886 2 2735 7357 Fax: +886 2 2739 5687 info@tw.jennic.com www.jennic.com Jennic America Inc - East Coast Office 1322 Scott Street, Suite 203 Point Loma, CA 92106, USA Tel: +619 223 2215 Fax: +619 223 2081 info@us.jennic.com www.jennic.com Jennic America Inc - West Coast Office 1060 First Avenue, Suite 400 King of Prussia, PA 19406, USA Tel: +1 484 868 0222 Fax: +1 484 971 5015 info@us.jennic.com www.jennic.com Jennic Ltd Korea 701, 7th Floor, Kunam Bldg., 831-37, Yeoksam-Dong, Kangnam-ku Seoul 135-080 Korea Tel: +82 2 552 5325 Fax: +82 2 3453 8802 info@kr.jennic.com www.jennic.com 22 Preliminary - JN-DS-JN5139-xxx-Myy v1.1 Jennic 2007
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2008-04-25 | 2400 ~ 2483.5 | DTS - Digital Transmission System | Class II permissive change or modification of presently authorized equipment |
2 | 2007-04-19 | 2400 ~ 2483.5 | DTS - Digital Transmission System | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 | Effective |
2008-04-25
|
||||
1 2 |
2007-04-19
|
|||||
1 2 | Applicant's complete, legal business name |
NXP Laboratories UK Ltd
|
||||
1 2 | FCC Registration Number (FRN) |
0014596860
|
||||
1 2 | Physical Address |
Furnival St
|
||||
1 2 |
Sheffield, N/A S1 4QT
|
|||||
1 2 |
United Kingdom
|
|||||
app s | TCB Information | |||||
1 2 | TCB Application Email Address |
p******@trac-trl.com
|
||||
1 2 |
M******@trlcompliance.com
|
|||||
1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 | Grantee Code |
TYO
|
||||
1 2 | Equipment Product Code |
JN5139M4
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 | Name |
C**** F****
|
||||
1 2 | Telephone Number |
+44 1********
|
||||
1 2 | Fax Number |
+44 1********
|
||||
1 2 |
c******@nxp.com
|
|||||
app s | Technical Contact | |||||
1 2 | Firm Name |
Jennic Ltd.
|
||||
1 2 | Name |
C****** F******
|
||||
1 2 | Physical Address |
Furnival Street
|
||||
1 2 |
S1 4QT
|
|||||
1 2 |
United Kingdom
|
|||||
1 2 | Telephone Number |
+4411********
|
||||
1 2 | Fax Number |
+4411********
|
||||
1 2 |
c******@jennic.com
|
|||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 | Equipment Class | DTS - Digital Transmission System | ||||
1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | JN5139-000-M04 Wireless Microcontroller | ||||
1 2 | JN5139-000-M04 IEEE802.15.4 Wireless Transmitter | |||||
1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 | Modular Equipment Type | Single Modular Approval | ||||
1 2 | Purpose / Application is for | Class II permissive change or modification of presently authorized equipment | ||||
1 2 | Original Equipment | |||||
1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 | Grant Comments | Single Modular | ||||
1 2 | Output power listed is conducted. Modular Approval for mobile RF Exposure conditions, the antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Approval is limited to OEM installation only. OEM integrators must be provided with antenna installation instructions. OEM integrators and end-users must be provided with transmitter operating conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no instructions to remove or install the device. The only antennas approved for use with this module are those documented in the filings under this FCC ID. | |||||
1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 | Firm Name |
Element Materials Technology Warwick Ltd
|
||||
1 2 |
R.N. Electronics Ltd.
|
|||||
1 2 | Name |
S******** B****
|
||||
1 2 |
R**** R******
|
|||||
1 2 | Telephone Number |
01684********
|
||||
1 2 |
44-12********
|
|||||
1 2 | Fax Number |
01684********
|
||||
1 2 |
44-12********
|
|||||
1 2 |
s******@element.com
|
|||||
1 2 |
r******@RNelectronics.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2400.00000000 | 2483.50000000 | 0.1000000 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | 2400.00000000 | 2483.50000000 | 0.1000000 | JN5139 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC