FCC ID: XXMJN5189M16 ZigBee Modular Transmitter

JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Rev. 1.6 April 15, 2019 Reference manual dDocument information Info Content Keywords JN5189, 89T, 88, 88T, module Abstract Reference Manual for JN5189, 89T, 88, 88T modules and platform design. SECURITY STATUS NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Revision history Rev Date Description 1.0 1.1 1.2 1.3 1.4 1.5 20180201 Creation 20180307 Added picture of the JN5189-001-M16 module 20180525 Manufacturer address added 20180528 Update of IC chapter 20181004 Update of FCCID / IC ID 20180321 JN5188/88T added Temperature range explained O-QPSK modulation frequency band added 1.6 20190415 Add comments in chapter 8.2 SECURITY STATUS Contact information For more information, please visit: http://www.nxp.com JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 2 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 1. Introduction This manual describes the hardware for the reference designs for modules based around the NXP JN5189 family of wireless microcontrollers. This family is composed by JN5189, 89T, 88, 88T modules. In this manual, JN5189 name can stand also for JN5189T, JN5188 and JN5188T. The NXP JN5189 modules are small, low-power and cost-effective evaluation and development board or application prototyping and demonstration of the JN5189 device. The JN5189 is an ultra-low-power, highly integrated single-chip device that enables Standard IEEE 802.15.4 RF connectivity for portable, extremely low-power embedded systems. The JN5189 SoC integrates a radio transceiver operating in the 2.4 GHz ISM band supporting O-QPSK modulation (2400MHz to 2483.5MHz), an ARM Cortex-M4 processor, up to 640 kB flash,152 kB SRAM and 128 kB ROM, 802.15.4 processor hardware and peripherals optimized to meet the requirements of the target applications. The design considerations presented in this manual are equally valid for bespoke solutions where the JN5189 device is placed directly onto the product PCB. Three modules models are available:

JN5189-001-M10 SECURITY JN5189-001-M13 JN5189-001-M16 The models available are described in Table 1. STATUS In order to complete a successful PCB design by your own the hardware guidelines described in this reference manual must be followed as strictly as possible. Further information on the JN5189 characteristics are available in the JN5189 IEEE802.15.4 Wireless Microcontroller datasheet. 1.1 Audience This guide is intended for systems designers 1.2 Manufacturer address NXP Semiconductors Campus EffiScience, Esplanade Anton Philips 14906 Caen France 1.3 Regulatory approvals The JN5189-001-M10 and M13 are compliant with:

RED 2014/53/UE CFR 47 FCC part 15 Industry Canada requirements JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 3 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual The high power JN5189-001-M16 is not approved for use in Europe. It is compliant with:

CFR 47 FCC part 15 Industry Canada requirements 2. Reference Design The reference design package includes the following information for each module variant:

Reference manual: JN-RM-2078 Schematics Layout Bill-of-Materials Full design databases including schematics and layout source files are available on request. The following table provides a summary of the JN5189 Module Reference Design that is available from the Wireless Connectivity area of the NXP web site. Part number Description Table 1. Modules references SECURITY Content JN-RD-6054 Reference Manual JN5189-001-M10 JN-RM-2078 OM15069 Standard Power PCB Antenna JN5189 Module Reference Design Package STATUS OM15069 Standard Power Fl connector JN5189-001-M13 OM15072 High Power Antenna diversity (PCB antenna and Fl connector) JN5189-001-M16 Note: These reference designs are approved for the operating temperature range of 40 C to +105 C for JN5189T/JN5188T where NTAG is embedded and -40C to

+125C without embedded NTAG, as JN5188 and JN5189 modules. As reference, below are the operating conditions from the datasheet. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 4 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Table 2. Operating conditions 3. Block diagram SECURITY Fig 1. JN5189-001-M10 & M13 block diagrams STATUS Fig 2. JN5189-001-M16 block diagram JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 5 of 33 JN5189MatchingFlconnectorJN5189-001-M10JN5189MatchingPrintedantennaJN5189-001-M13JN5189SKY66403MatchingJN5189-001-M16PrintedantennaFlconnector NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 4. Marking The label is fixed on the bottom face of the modules 5. Design considerations To have successful wireless hardware development, the proper device footprint, RF layout, circuit matching, antenna design, and RF measurement capability are essential. RF circuit design, layout, and antenna design are specialties requiring investment in tools and experience. With available hardware reference designs from NXP, RF design considerations, and the guidelines contained in this application note, hardware engineers can successfully design IEEE 802.15.4 radio boards with good performance levels. The following figures show the JN5189 M10 & M13 reference modules. They contain the JN5189 device and all necessary I/O connections. SECURITY JN-RM-2078 Reference manual STATUS Fig 3. JN5189-001-M10 & M13 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 6 of 33 32 MHz XTALDCDC externalcomponentsIF PrintedantennaFlconnector0 ohm resistorusedto configure the module in M10 or M13 variantRFIO & MatchingNetwork32 kHz XTAL NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 4. JN5189-001-M16 SECURITY The device footprint and layout are critical and the RF performance is affected by the design implementation. For these reasons, use of the NXP recommended RF hardware reference designs are important for successful board performance. Additionally, the reference platforms have been optimized for radio performance. Even small changes in the location of components can mistune the circuit. If the recommended footprint and design are followed exactly in the RF region of the board, sensitivity, output power, harmonic and spurious radiation, and range will have a high likelihood of first time success. STATUS The following subsections describe important considerations when implementing a wireless hardware design starting with the device footprint, PCB stack-up, RF circuit implementation, and antenna selection. The following figure shows an example of a typical layout with the critical RF section which must be copied exactly for optimal radio performance. The less critical layout area can be modified without reducing radio performance. NOTE Exact dimensions are not given in this document, but can be found in the manufacturing files for the JN5189 modules 5.1 JN5189 device footprint The performance of the wireless link is largely influenced by the devices footprint. As a result, a great deal of care has been put into creating a footprint so that receiver sensitivity and output power are optimized to enable board matching and minimal component count. NXP highly recommends copying the die flag exactly as it is shown in the following figure; this includes via locations as well. Deviation from these parameters can cause performance degradation. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 7 of 33 DCDC externalcomponents32 kHz XTAL32 MHz XTALRFIO & MatchingNetworkIF PrintedantennaFlconnectorFEM SKY66403 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 5. Critical Layout of die flag area Figure 5 shows the critical areas of the device die flag. These are the following:

SECURITY Ground vias and locations RF output and ground traces 5.2 PCB Stack-Up Die flag shape STATUS Complexity is the main factor that will determine whether the design of an application board can be two-layer, four-layer, or more. From an RF point of view a 4 layers PCB is preferred to a two layers PCB.Nevertheless in a very simple application it should be possible to use a 2 layers PCB. The recommended board stack-up for either a four-layer or two-layer board design is as follows:

4-layer stack-up:

Top: RF routing of transmission lines L2: RF reference ground L3: DC power Bottom: signal routing Two-layer stack-up:

Top: RF routing of transmission lines, signals, and ground Bottom: RF reference ground, signal routing, and general ground JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 8 of 33 RFIOGND viasDie flag NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual The JN5789-001-M10 and JN5189-001-M13 (OM15069) and JN5189-001-M16

(OM15062) modules are built on a standard 4layer printed circuit board (PCB) with the individual layers organized as shown in Figure 6. Fig 6. PCB stack-up Note: The NXP PCB layouts assume use of the layers defined above. If a different PCB stack-up is used then NXP does not guarantee performance. NXP strongly recommends the use of the above stack-up. SECURITY As shown in Figure 6, regarding transmission lines, it is important to copy not just the physical layout of the circuit, but also the PCB stackup. Any small change in the thickness of the dielectric substrate under the transmission line will have a significant change in impedance; all this information can be found on the fabrication notes for each board design. As an illustration, consider a 50 ohm microstrip trace that is 18 mils wide over 10 mils of FR4. If that thickness of FR4 is changed from 10 to 6 mils, the impedance will only be about 36 ohms. STATUS In any case the width of the RF lines must be re-calculated according to the PCB characteristics in order to ensure a 50 ohm characteristic impedance. When the top layer dielectric becomes too thin, the layers will not act as a true transmission line, even though all the dimensions are correct. There is not universal industry agreement on which thickness at which this occurs, but NXP prefers to use a top layer dielectric thickness of no less than 8-10 mils. There is also a limit to the ability of PCB fabricators to control the minimum width of a PCB trace and the minimum thickness of a dielectric layer. +/- 1 mil will have less impact on an 18 mils wide trace and a 10 mil thick dielectric layer, than it will on a much narrower trace and thinner top layer. This can be an especially insidious problem. The design will appear to be optimized with the limited quantity of prototype and initial production boards, in which the bare PCB's were all fabricated in the same lot. However, when the product goes into mass production there can be variations in PCB fabrication from lot-to-lot which can degrade performance. The use of a correct substrate like the FR4 with a dielectric constant of 4.4 will assist you in achieving a good RF design. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 9 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual While no special measures are required for the board design, it is recommended that Class 1 tolerances be used. 5.3 RF circuit topology and matching NXP always recommends that designers start by copying the existing NXP reference design. This applies to both the circuit portion (schematic) of the design, and the PCB layout. For all RF designs, particularly for designs at frequencies as high as 2.4 GHz, the PCB traces are a part of the design itself. Even a very short trace has a small amount of parasitic impedance (usually inductive), which has to be compensated for in the remainder of the circuit. What may seem like a minor change to the layout, or what would certainly be a minor change at a lower frequency of operation, can actually be a significant change at 2.4 GHz. For example, we may consider that a metal trace on a PCB such as the JN5189-

001M1x modules is approximately 0.8 nH per mm. At lower frequencies, this would have no impact, but at 2.4 GHz this would have a significant impact in any matching circuits. The circuits used on the NXP reference designs are all tuned and optimized on the actual layout of the reference design, such that the final component values take into account the effects of the circuit board traces, and other parasitic effects introduced by the PCB. This includes such issues as parasitic capacitance between components, traces, and/or board copper layers, inductance of traces and ground vias, the non-ideal effects of components, and nearby physical objects. SECURITY The layout of the RF portions of JN5189 based modules is critical. It is important that the reference designs are strictly adhered to, otherwise the following may occur:

Reduction in RF output STATUS Excessive spurious RF outputs leading to RF compliance issues Unacceptable power slope across the full channel range Poor range Reduced Rx sensitivity 5.4 Transmission lines Transmission lines have several shapes such as microstrip, coplanar waveguide, and strip-line. For 802.15.4 applications built on FR4 substrates, the types of transmission lines typically take the form of microstrip or coplanar waveguide

(CPW). These two structures are defined by the dielectric constant of the board material, trace width, and the board thickness between the trace and the ground. Additionally, for CPW, the transmission line is defined by the gap between the trace and the top edge ground plane. These parameters are used to define the characteristic impedance of the transmission line (trace) that is used to convey the RF energy between the radio and the antenna. JN5189 has a single ended RF output with a 3 components matching network composed of a shunt capacitor, a series inductor then another shunt capacitor. In addition a 0 ohm resistor has been placed between the RFIO port of the chip and JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 10 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual the first shunt capacitor. These elements transform the device impedance to 50 ohms. The value of these components may vary depending on your specific board layout. The recommended RF matching network is shown in Figure 7. Avoid routing traces near or parallel to RF transmission lines or crystal signals. Maintaining a continuous ground under an RF trace is critical to maintaining the characteristic impedance of that trace. Avoid any routing on the ground layer that will result in disrupting the ground under the RF traces. Keep the RF trace as short as possible. SECURITY STATUS Fig 7. RF Matching Network 5.5 Components All electronic components have parasitic characteristics that cause the part to act in a non-ideal way. Typically, these effects become worse as the frequency of operation is increased. For most component suppliers, this quality is expressed by the Self Resonant Frequency (SRF) specification. For example, a capacitor has parasitic inductance introduced by the metal leads of the components. As frequency increases, at some point the impedance due to the parasitic inductance is greater than the impedance of the capacitor, and at that frequency and higher, the component no longer acts as a capacitor and now acts as an inductor. At the point at which the impedance from both inductive and capacitive components is the same, the part will resonate as a LC parallel resonant circuit, and this is called the Self Resonant frequency. Figure 8 shows some typical response curve. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 11 of 33 Controlledimpedancetrace(50 ohm microstrip)RF MatchPrintedantennaFlconnector NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 8. RF Plots for 3pF ceramic capacitor Murata GRM1555 type SECURITY The same is true of inductors. There is parasitic capacitance in an inductor, mainly due to capacitive coupling between the turns of wire. At some point in frequency, this capacitance will have a higher impedance than the inductance of the part. From this frequency and higher the part acts as a capacitor and not as an inductor. STATUS The Bill of Materials (BOM) is available for all NXP reference designs. The BOM shows the specific vendors and part numbers used on NXP designs. It is certainly possible to substitute another vendor's parts, but it may impact the performance of the circuit, therefore, it may be necessary to use different component values when parts from another vendor are used. If there is a performance issue on a new design, and part substitutions were made on that design, then it is strongly recommended that components identical to those used in the NXP reference design be placed on the new design for test purposes. Once the design is working properly with components that are identical to those used by NXP, then it will be possible to substitute components from other vendors one at a time, and test for any impact on circuit performance. 5.6 GND planes It is recommended to use a solid (continuous) ground plane on Layer 2, assuming Layer 1 (top) is used for the RF components and transmission lines; avoid cut-outs or slots in that area. Keep top ground continuous as possible. This also applies for the other layers. Connect ground on the components layer to the ground plane beneath with a large quantity of vias. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 12 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Ground pours or fingers can act as antennas that unintentionally radiate. To avoid this, eliminate any finger that is not connected to the ground reference with a via; put a via in any trace that doesnt go anywhere. 5.7 Layers interconnections Avoid vias in the RF traces.Typically for a 1.6mm thickness PCB material, a single via can add 1.2nH of inductance and 0.5pF of capacitance, depending upon the via dimensions and PCB dielectric material. Provide multiple vias for high current and/or low impedance traces. Connect carefully all the ground areas of any layer to the reference GND plane 5.8 DCDC components Be sure that the smallest values capacitors C12 and C10 are placed close to the VBAT pin. The impedance of the GND connection between C10/C12 and C19 must be as low as possible: connect them directly on the component layer (see the red path below) SECURITY STATUS Fig 9. GND path between C10/C12 and C19 5.9 Reference Oscillator The NXP JN5189 device contains the necessary on-chip components to build a 32-MHz reference oscillator with the addition of an external crystal resonator. There is no need to use external capacitors because the JN5189 includes a bank of switchable capacitors that can be tuned to adjust the load capacitance (CL) that needs to be seen by the XTAL. The reference crystal serves many purposes, including the provision of a reference for the 32-bit ARM processor, PHY controller, radio synthesizer and analogue peripherals. In addition, the crystal provides timing references for external I/O (e.g. on-chip UARTs) and JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 13 of 33 C10C12C 19 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual timer counters. Thus, it is important that the crystal reference is specified and built correctly to ensure that the system functions properly. The choice of crystal resonator is important for the following reasons:

Resonator tolerance: A number of parameters, ranging from on-chip timings to radio centre-frequency, are derived directly from the tolerance of the crystal. As indicated in the component list, we recommend that a total tolerance of less than 25 ppm is used, as the maximum permissible offset specified in IEEE802.15.4 is 40 ppm. Also, note that this tolerance should include both temperature and ageing effects imparted on the resonator. Resonator load capacitance: The active oscillator components on the JN5189 devices are designed for a crystal resonator with load capacitance (CL) of 6 pF. This is a standard load and resonators of this type are widely available. Lay-out recommendations:

Route the connections from the 32 MHz XTAL to the chip oscillator pins with traces as short as possible. The layout of the oscillator circuit is such that tracks between components are as short as possible. This improves the performance of the oscillator by reducing stray capacitance which can introduce frequency errors. The XTAL should be placed away from high frequency devices and traces in order to reduce the capacitive coupling between XTAL pins and PCB traces. Keep other digital signal lines, especially clock lines and frequently switching signal lines, as far away from the crystal connections as possible. SECURITY Caution: Adherence to NXPs recommendations will ensure that the module performs correctly. The substitution of components is not recommended, as this may lead to both oscillator start-up and frequency tolerance issues. STATUS 5.10 Decoupling 5.10.1 General considerations Decouple the power supplies or regulated voltages as close as possible to the supply pin of the IC. The decoupling capacitors must be connected to a localized ground pad on the top layer that is connected to the main ground plane layer through multiple vias. Ensure that each decoupling capacitor has its own via connection to ground. When possible use 2 vias to connect the capacitor to the ground layer. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 14 of 33 Best configurationWrongconfiguration:There are not enoughviasThe viasare toofar fromthe decouplingcapacitors NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 10. GND vias placement The capacitor with a smaller capacitance must be placed nearer to the IC. The decoupling capacitor must be placed between the main supply line and the supply pin as shown below:

Fig 11. Decoupling capacitors placement 5.10.2 VDD(RADIO), FB, VDD_PMU, VDDE and VBAT decoupling SECURITY Copy as much as possible the placement of the decoupling capacitors of all the supply pins as shown below. STATUS Fig 12. VDD(Radio) decoupling JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 15 of 33 VDDMain supplytrace on layer 3VDDGndGndMain supplytrace on layer 3capbest configurationviaviaviaviaWrongconfiguration:The decouplingcapacitorisnot placedbetweenthe main line and the VDD pin C13C14VDD(Radio) NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 13. FB and VDD_PMU decoupling SECURITY Fig 14. VDDE decoupling STATUS Fig 15. VBAT decoupling 5.11 Traces Isolation When PCB traces are in close proximity, they can talk to each other through the capacitor created by these traces. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 16 of 33 C100VDDEC10C12C 1 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual In order to mimimize the effect of this parasitic coupling, identify the most sensitive traces or areas (RF trace, oscillator, power lines, ...) and separate them from any signal that is likely to couple with them through parasitics. Separation between 2 lines can be achieved by increasing the distance from one to the other. 5.12 GPIOs The GPIOs traces are generally long lines that can cover long distances. They can carry undesirable signals that are likely to radiate in any direction. It is recommended to avoid routing these signals 5.13 Screening can The JN5189 doesnt radiate high spurs and it is very robust to EMC interferers so there is in principle no need for a screening can (or shielding can). Nevertheless a footprint for a can has been added on the NXP modules and NXP recommends to add this footprint to any PCB. In very specific cases under a very noisy environment it could be helpful to add a can. SECURITY STATUS JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 17 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 6. Optimal PCB placement of a module In case the JN5189 is mounted on a module similar to the NXP JN5189-001-M10 care must be taken when mounting this module onto another PCB. The area around the antenna must be kept clear of conductors or other metal objects for an absolute minimum of 20 mm. This is true for all layers of the PCB and not just the top layer. Any conductive objects close to the antenna could severely disrupt the antenna pattern resulting in deep nulls and high directivity in some directions. The diagrams below show various possible scenarios. The top 3 scenarios are correct;

groundplane may be placed beneath JN5168-001-M00 module as long as it does not protrude beyond the edge of the top layer ground plane on the module PCB. The bottom 3 scenarios are incorrect; the left-hand side example because there is groundplane underneath the antenna, the middle example because there is insufficient clearance around the antenna (it is best to have no conductors anywhere near the antenna), finally the right hand example has a batterys metal casing in the recommended keep out area. SECURITY STATUS Fig 16. PCB placement of a JN5189 module with a printed antenna 7. Manufacturing considerations The HVQFN package must be considered carefully when using reflow solder techniques. Package footprint information can be found in the JN5189 data sheet. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 18 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual The decal is shown in Fig 17. The pad stacks used are 0.25 mm by 1 mm for the smaller pads, and a 6.4 mm square pad for the paddle. JN-RM-2078 Reference manual SECURITY Fig 17. Recommended PCB decal for HVQFN40 40-pin QFN STATUS The solder mask used is shown in Fig 18. The pad stacks used are 0.25 mm by 1 mm for the smaller pads, and four 1.6 mm square pads to apply paste to the paddle. The solder paste mask has a thickness of 6-thou (0.152 mm). If the paste thickness needs to deviate from that used NXP then it may be necessary to change the number of pads that the paste is applied to. Paste thickness may be dictated by additional components used in a design. All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 19 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual Fig 18. Solder paste mask for HVQFN40 40-pin QFN SECURITY STATUS Fig 19. Vias on the paddle of the HVQFN40 40-pin QFN 25 vias are applied to the paddle. These allow excess solder paste and heated air to be vented away from the device, preventing the device from being lifted during soldering. In addition, these vias ensure that a low impedance ground is maintained, which is vital for optimum RF performance. All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 20 of 33 JN-RM-2078 Reference manual NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 8. Regulations 8.1 Federal Communication Commission Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules see Ref. 4. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio/TV technician for help OEM integrators instructions SECURITY The OEM integrators are responsible for ensuring that the end-user has no manual instructions to remove or install module The module is limited to installation in mobile or fixed applications, according to CFR 47 Part 2.1091(b) STATUS Separate approval is required for all other operating configurations, including portable configurations with respect to CFR 47 Part 2.1093 and different antenna configurations User guide mandatory statements User's instructions of the host device must contain the following statements in addition to operation instructions:

* This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and

(2) This device must accept any interference received, including interference that may cause undesired operation

* Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment FCC RF Exposure requirements User's instructions of the host device must contain the following instructions in addition to operation instructions:

Avoid direct contact to the antenna, or keep it to a 20 cm minimum distance while using this equipment. This device must not be collocated or operating in conjunction with another antenna or transmitter. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 21 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual This module has been designed to operate with antennas having a maximum gain of 2 dBi. Antennas having a gain greater than 2 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. 8.1.1 FCC end product labelling The final end product should be labelled in a visible area with the following:

Contains TX FCC ID: XXMJN5189M1013 and XXMJN5189M16 to reflect the version of the module being used inside the product. 8.2 Industry Canada statement Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power

(e.i.r.p.) is not more than that necessary for successful communication. SECURITY Conformment la rglementation d'Industrie Canada, le prsent metteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou infrieur) approuv pour l'metteur par Industrie Canada. Dans le but de rduire les risques de brouillage radiolectrique l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonne quivalente

(p.i.r.e.) ne dpasse pas l'intensit ncessaire l'tablissement d'une communication satisfaisante. STATUS This radio transmitter (8764A-JN5189M1013 and 8764A-JN5189M16) has been approved by Industry Canada to operate with the antenna types listed below with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Le prsent metteur radio (8764A-

JN5189M1013 and 8764A-JN5189M16) a t approuv par Industrie Canada pour fonctionner avec les types d'antenne numrs ci-dessous et ayant un gain admissible maximal et l'impdance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est suprieur au gain maximal indiqu, sont strictement interdits pour l'exploitation de l'metteur. This module has been designed to operate with antennas having a maximum gain of 2 dBi. Antennas having a gain greater than 2 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. As long as the above condition is met, further transmitter testing will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc). The host equipment (including JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 22 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual power supply system) still needs to re-confirm that the whole system complies with both intentional and unintentional emission requirements. This device complies with Industry Canada RF radiation exposure limits set forth for general population. This device must be installed to provide a separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. This device complies with Industry Canada radiation exposure limits set forth for general population. This device must not be co-located or operating in conjunction with any other antenna or transmitter. Le prsent appareil est conforme aux niveaux limites dexigences dexposition RF aux personnes dfinies par Industrie Canada. Lappareil doit tre install afin doffrir une distance de sparation dau moins 20cm avec lutilisateur, et ne doit pas tre install proximit ou tre utilis en conjonction avec une autre antenne ou un autre metteur. Le prsent appareil est conforme aux niveaux limites dexigences dexposition RF pour la population globale dfinies par Industrie Canada. Lappareil ne doit pas tre install proximit ou tre utilis en conjonction avec une autre antenne ou un autre metteur. This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device SECURITY Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes: (1) il ne doit pas produire de brouillage, et (2) lutilisateur du dispositif doit tre prt a accepter tout brouillage radiolectrique reu, mme si ce brouillage est susceptible de compromettre le fonctionnement du dispositif. STATUS 8.2.1 Industry Canada end product labelling For Industry Canada purposes the following should be used: Contains Industry Canada ID IC: 8764A-JN5189M1013 and 8764A-JN5189M16 8.3 European Radio Equipment Directive 2014/53/EU statement JN5189-001-M10 and JN5189-001-M13 are compliant with ETSI EN 300 328 V2.1.1, EMC, EN 301 489-17 v3.2.0 and the Basic Safety Assessment (BSA) EN 60950-1:2006

(2006-06) and are subject to a Notified Body Opinion. The JN5189-001-M16 module is not approved for use in Europe. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 23 of 33 9. Check list schematic Table 3. Schematic design-in check list Check number SCHEMATICS DESIGN-IN REVIEW CHECK-LIST

/

A N N Y

/

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.1 2.2 2.3 3 3.1 3.2 GENERAL Have the schematics been checked versus NXP reference schematics & Application Notes?

Have the schematics been reviewed by several people?

Does the application use non standard components?

(e.g. components that had not previously used for such applications) Have the non standard components been qualified so that they can be used in the application?

Are recommendations for layout/form factor written on the schematics?

Are the components sized for the wanted current drive capability?

Has the JN5189 symbol pinning been checked and does it include the exposed pad?

RF IO Is the characteristic impedance of the RF_IO input/output line 50 ohm over the full RF range?

Have components with the correct type and value been connected to the RF port of the JN5189?

For modules with external FEM is extra filtering needed for harmonics rejection ?

32 MHz crystal reference Oscillator Is the oscillator external configuration in accordance with the Application Note?

Has XTAL model been recommended by NXP?

R e f e r e n c e m a n u a l R e v

. 1

. 6 A p r i l 1 5

, 2 0 1 9

-

J N R M

-

2 0 7 8 A l l i f n o r m a t i o n p r o v d e d i i n t i h s d o c u m e n t i s s u b e c t t j o l e g a l i l i d s c a m e r s

. N X P B V

. 2 0 1 6

. A l l r i g h t s r e s e r v e d

. 2 4 o f 3 3 Customer comments and/or E C U RI T Y S T A T U actions Check done by NXP Feedback i N X P S e m c o n d u c t o r s J N 5 1 8 9

, 8 9 T

, 8 8

, l l 8 8 T m o d u e s d e v e o p m e n t r e f e r e n c e m a n u a l

-

J N R M

-

2 0 7 8 R e f e r e n c e m a n u a l R e v

. 1

. 6 A p r i l 1 5

, 2 0 1 9

-

J N R M

-

2 0 7 8 A l l i f n o r m a t i o n p r o v d e d i i n t i h s d o c u m e n t i s s u b e c t t j o l e g a l i l i d s c a m e r s

. N X P B V

. 2 0 1 6

. A l l r i g h t s r e s e r v e d

. 2 5 o f 3 3 3.3 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 5.5 5.6 6 6.1 6.2 7 7.1 In case the XTAL model has not been recommended by NXP have all the parameters been checked in order they fulfill NXP, standard and application requirements (load capacitance,pulling sensitivity, equivalent resistance, frequency tolerance, temperature range, frequency drift versus temperature, ageing) ?

32 kHz crystal Oscillator Has the need of a 32 kHz XTAL been discussed ? (

Zigbee specifications can be met without an external XTAL) In case the 32 kHz XTAL oscillator has been implemented has the XTAL model been recommended by NXP ?

In case the XTAL model has not been recommended by NXP have all the parameters been checked in order they fulfill NXP, standard and application requirements (load capacitance,pulling sensitivity, equivalent resistance, frequency tolerance, temperature range, frequency drift versus temperature, ageing) ?

Power Supply Have all the VDD pins been connected according to NXP recommendations?

Are the power supply regulators well sized?

Has the decoupling of the supply regulators output been implemented?

Have the power supply pins of the IC been properly decoupled (according to the Application Note and Reference Design schematics?) Have the recommendations for the values and models of the components of the DCDC converter been taken into account?

Has the exposed die pad been connected to GND?

PIOs Has the compatibility of the logic levels with other components been checked?

Does the max source/sink current fit the application?

Does the ADC characteristics fit the application?

ADC E C U RI T Y S T A T U i N X P S e m c o n d u c t o r s J N 5 1 8 9

, 8 9 T

, 8 8

, l l 8 8 T m o d u e s d e v e o p m e n t r e f e r e n c e m a n u a l

-

J N R M

-

2 0 7 8 R e f e r e n c e m a n u a l R e v

. 1

. 6 A p r i l 1 5

, 2 0 1 9

-

J N R M

-

2 0 7 8 A l l i f n o r m a t i o n p r o v d e d i i n t i h s d o c u m e n t i s s u b e c t t j o l e g a l i l i d s c a m e r s

. N X P B V

. 2 0 1 6

. A l l r i g h t s r e s e r v e d

. 2 6 o f 3 3 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 Programming and Debug Has the flash programming connector been connected to the correct I/O on the microcontroler?

Has a connector for debug been added that allows the microcontroler to be put into programming mode?

(RSTN & SPIMISO pins) Is the reset pin RSTN properly connected?

Add a test point at an unused DIO in order a trigger signal can be output from the pin for sensitivity measurements For printed and chip antenna: Is the RF line implemented in such a way that the HW can be easily modified in order to do conducted measurements on one hand and measure the antenna characteristics on the other hand ? For instance a 0 ohm resistor can be used to connect the JN5189 RF port to the antenna for the real application and a SMA or FL connector footprint can be added for debug; the SMA or Fl connector will be connected/disconnected to/from the JN5189 RF port or the antenna with 0 ohm resistors. If I2C used, are the I2C lines pulled up?

External Memory In case an external flash memory is used has the correct type of memory been used and is it connected to the microcontroller correctly?

Has the flash memory symbol pinning been checked?

E C U RI T Y S T A T U i N X P S e m c o n d u c t o r s J N 5 1 8 9

, 8 9 T

, 8 8

, l l 8 8 T m o d u e s d e v e o p m e n t r e f e r e n c e m a n u a l

-

J N R M

-

2 0 7 8 10. Check list layout Table 4. Layout design-in check list Check number LAYOUT DESIGN-IN REVIEW CHECK-LIST

/

A N N Y

/

1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.3 2.4 3 3.1 3.2 4 4.1 4.2 GENERAL Has the number of layers been clearly discussed?

Has the layout been checked versus NXP reference board ? (i.e OM15069-2_JN5189_ANTENNA_MODULE) Have the HW recommendations of the JN-RM-2078 reference manual been followed?

Has the correct PCB material been specified?

Have the correct PCB thicknesses been specified?

RF IO Is the RF_IO input/output line well sized for 50 ohm?

The line width must be calculated according to the board thickness and PCB material. Are the RF wires as short as possible (wires behave as antenna so shortening them help to increase EMI immunity) Have vias been avoided in the RF line?

Has the placement of the RFIO matching network been strictly copied from the NXP reference module?

Crystal reference Oscillator Has the 32 MHz XTAL been placed close to the IC?

Are there GND vias around the 32 MHz XTAL ?

Power Supply Have all the VDD capacitors been placed as close as possible to the power pins and voltage regulators outputs?

Provide multiple vias in the power lines when power is routed on several layers R e f e r e n c e m a n u a l R e v

. 1

. 6 A p r i l 1 5

, 2 0 1 9

-

J N R M

-

2 0 7 8 A l l i f n o r m a t i o n p r o v d e d i i n t i h s d o c u m e n t i s s u b e c t t j o l e g a l i l i d s c a m e r s

. N X P B V

. 2 0 1 6

. A l l r i g h t s r e s e r v e d

. 2 7 o f 3 3 Customer comments and/or E C U RI T Y S T A T U actions Check done by NXP feedback i N X P S e m c o n d u c t o r s J N 5 1 8 9

, 8 9 T

, 8 8

, l l 8 8 T m o d u e s d e v e o p m e n t r e f e r e n c e m a n u a l

-

J N R M

-

2 0 7 8 R e f e r e n c e m a n u a l R e v

. 1

. 6 A p r i l 1 5

, 2 0 1 9

-

J N R M

-

2 0 7 8 A l l i f n o r m a t i o n p r o v d e d i i n t i h s d o c u m e n t i s s u b e c t t j o l e g a l i l i d s c a m e r s

. N X P B V

. 2 0 1 6

. A l l r i g h t s r e s e r v e d

. 2 8 o f 3 3 For low supply voltage application close to 2.0V, please ensure that the supply track is well dimensioned so as to avoid IR drop and hence falsely trigger the brown-out.

(IR drop is the voltage drop due to the supply current flowing into the supply track resistance). Have the VDD lines been isolated from potential interferences?

Is GND plane continuous around and near all signals?

Has the die pad been properly connected to GND?

Are vias implemented in the die pad?

EMC and Misc In case more than 2 layers are used, does one layer act as a continuous ground plane (GND reference plane)?

Are numerous vias added near capacitor, near fingers,?

Remove small GND areas and isolated fingers that cannot be connected to the reference GND plane with a via. Have silk screens been added with relevant information? (components ref, logo, board name) Are all silkscreen texts readable when the board is populated?

Have traces been avoided below noisy or sensitive components?

Check that traces do not cut across power or ground planes unnecessarily. Is the JN5189 footprint strictly similar to the NXP reference?

If more than 2 layers are used, the inner layers must be left empty below the RF components and the antenna 4.3 4.4 4.5 4.6 4.7 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Each connection between a component and GND must be doubled with a via to the GND plane. Have the soldering/non soldering areas been respected?

Is solder resist layer check in the empty area?

If sold unit is a module is a CAN/shield implemented?

E C U RI T Y S T A T U i N X P S e m c o n d u c t o r s J N 5 1 8 9

, 8 9 T

, 8 8

, l l 8 8 T m o d u e s d e v e o p m e n t r e f e r e n c e m a n u a l

-

J N R M

-

2 0 7 8 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 11. Abbreviations Table 5. Abbreviations Acronym Description EMC ETSI FCC PAN PCB RF SPI-bus TQFN WPAN Electro Magnetic Compatibility European Telecommunications Standards Institute Federal Communications Commission Personal Area Network Printed Circuit Board Radio Frequency Serial Peripheral Interface-bus Thin Quad Flat No-lead Wireless Personal Area Network 12. References JN5189 Datasheet IEEE802.15.4 Wireless Microcontroller SECURITY STATUS JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP B.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 29 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 13. Legal information 13.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 13.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). Customer is responsible for doing all necessary testing for the customers applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customers third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-

infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. SECURITY In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. STATUS Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customers exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customers sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customers applications and products planned, as well as for the planned application and use of customers third party customer(s). Customers should 13.3 Patents Notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 30 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 14. List of figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. JN5189-001-M10 & M13 block diagrams .......... 5 JN5189-001-M16 block diagram ....................... 5 JN5189-001-M10 & M13 ................................... 6 JN5189-001-M16 .............................................. 7 Critical Layout of die flag area ........................... 8 PCB stack-up .................................................... 9 RF Matching Network ..................................... 11 RF Plots for 3pF ceramic capacitor Murata GRM1555 type ................................................ 12 GND path between C10/C12 and C19 ............ 13 GND vias placement ....................................... 15 Decoupling capacitors placement ................... 15 VDD(Radio) decoupling .................................. 15 FB and VDD_PMU decoupling ........................ 16 VDDE decoupling ............................................ 16 VBAT decoupling ............................................ 16 PCB placement of a JN5189 module with a printed antenna ............................................... 18 Recommended PCB decal for HVQFN40 40-pin QFN ................................................................ 19 Solder paste mask for HVQFN40 40-pin QFN 20 Vias on the paddle of the HVQFN40 40-pin QFN

........................................................................ 20 SECURITY STATUS Fig 18. Fig 19. JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 31 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual 15. List of tables Table 1. Modules references .......................................... 4 Table 2. Schematic design-in check list ........................ 24 Table 3. Layout design-in check list .............................. 27 Table 4. Abbreviations .................................................. 29 SECURITY STATUS JN-RM-2078 Reference manual All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2016. All rights reserved. Rev. 1.6 April 15, 2019 32 of 33 NXP Semiconductors JN-RM-2078 JN5189, 89T, 88, 88T modules development reference manual List of tables ...................................................... 32 Contents ............................................................. 33 15. 16. 16. Contents 1. 1.1 1.2 1.3 2. 3. 4. 5. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.10.1 5.10.2 Introduction ......................................................... 3 Audience ............................................................ 3 Manufacturer address ........................................ 3 Regulatory approvals ......................................... 3 Reference Design ................................................ 4 Block diagram ...................................................... 5 Marking ................................................................ 6 Design considerations ........................................ 6 JN5189 device footprint ..................................... 7 PCB Stack-Up .................................................... 8 RF circuit topology and matching ..................... 10 Transmission lines ........................................... 10 Components ..................................................... 11 GND planes...................................................... 12 Layers interconnections ................................... 13 DCDC components .......................................... 13 Reference Oscillator ......................................... 13 Decoupling ....................................................... 14 General considerations .................................... 14 VDD(RADIO), FB, VDD_PMU, VDDE and SECURITY STATUS VBAT decoupling ............................................. 15 Traces Isolation .......................................... 16 GPIOs .............................................................. 17 Screening can .................................................. 17 Optimal PCB placement of a module ............... 18 Manufacturing considerations ......................... 18 Regulations ........................................................ 21 Federal Communication Commission Statement

......................................................................... 21 FCC end product labelling ................................ 22 Industry Canada statement .............................. 22 Industry Canada end product labelling ............. 23 European Radio Equipment Directive 2014/53/EU statement ..................................... 23 Check list schematic ......................................... 24 Check list layout ................................................ 27 Abbreviations .................................................... 29 References ......................................................... 29 Legal information .............................................. 30 Definitions ........................................................ 30 Disclaimers....................................................... 30 Patents ............................................................. 30 Trademarks ...................................................... 30 List of figures ..................................................... 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: April 15, 2019 Document identifier: JN-RM-2078 5.11 5.12 5.13 6. 7. 8. 8.1 8.1.1 8.2 8.2.1 8.3 9. 10. 11. 12. 13. 13.1 13.2 13.3 13.4 14.