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15 PAN1320 UserMan Rev1.2 | Users Manual | 1.60 MiB | January 29 2016 | |||
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UserMan | Users Manual | 2.94 MiB | April 16 2014 | |||
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09 PAN1320 IntPho | Internal Photos | 59.11 KiB | January 29 2016 | |||
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08 PAN1320 ExtPho | External Photos | 95.56 KiB | January 29 2016 | |||
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06 07 LabelSampel Location | ID Label/Location Info | 71.25 KiB | January 29 2016 | |||
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04 PAN1320 AuthLet | Attestation Statements | 323.71 KiB | January 29 2016 | |||
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05 PAN1320 ConReq | Cover Letter(s) | 412.52 KiB | January 29 2016 | |||
1 2 3 4 5 | Test Setup Photos | January 29 2016 | ||||||
1 2 3 4 5 | 11 PAN1320 OpDes | Operational Description | January 29 2016 | confidential | ||||
1 2 3 4 5 | 12 PAN1320 BlkDia | Block Diagram | January 29 2016 | confidential | ||||
1 2 3 4 5 | 13 PAN1320 Schem | Schematics | January 29 2016 | confidential | ||||
1 2 3 4 5 | Test Report | January 29 2016 | ||||||
1 2 3 4 5 | Test Report | January 29 2016 | ||||||
1 2 3 4 5 | 16 PAN1320 PartsLst | Parts List/Tune Up Info | January 29 2016 | confidential | ||||
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17a PAN1320 AntSpec | Operational Description | 358.70 KiB | January 29 2016 | |||
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17b PAN1320 Antenna Description | Operational Description | 522.69 KiB | January 29 2016 | |||
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30 PAN1320 ChLet Rev01 | Cover Letter(s) | 312.22 KiB | January 29 2016 | |||
1 2 3 4 5 | AntSpec | Operational Description | April 16 2014 | confidential | ||||
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AutLet | Cover Letter(s) | 317.56 KiB | April 16 2014 | |||
1 2 3 4 5 | BlkDia | Block Diagram | April 16 2014 | confidential | ||||
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CIIPChLetter | Cover Letter(s) | 305.01 KiB | April 16 2014 | |||
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ConReq | Cover Letter(s) | 396.61 KiB | April 16 2014 | |||
1 2 3 4 5 | OpDes | Operational Description | April 16 2014 | confidential | ||||
1 2 3 4 5 | PartsLst | Parts List/Tune Up Info | April 16 2014 | confidential | ||||
1 2 3 4 5 | RF Exposure Info | April 16 2014 | ||||||
1 2 3 4 5 | Schem | Schematics | April 16 2014 | confidential | ||||
1 2 3 4 5 | Test Report | April 16 2014 | ||||||
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1 2 3 4 5 | 15 PAN1320 UserMan Rev1.2 | Users Manual | 1.60 MiB | January 29 2016 |
A u g u s t 2 0 1 0 E N W 8 9 8 1 4 A 2 M F B l u e t o o t h Q D ID : B0 1 4 9 9 9 ( B T V 2 . 1 + ED R ) B l u e t o o t h Q D ID : B0 1 4 9 4 0 ( B T V 2 . 0 + ED R ) B l u e t o o t h Q D I D : B 0 1 4 9 3 6 ( B T V 1 . 2 ) P A N 1 3 2 0 - H C I - B T 2 . 1 I n f i n e o n s B l u e M o o n U n i v e r s a l P l a t f o r m W i r e l e s s M o d u l e s P r o d u c t O v e r v i e w R e v i s i o n 1 . 2 , 2010-08-18 Edition 2010-08-18 Published by Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 D-21337 Lneburg, Germany 2010 Panasonic Industrial Devices Europe GmbH All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Panasonic Office in Germany or one of our Distributor or write an e-mail to wireless@eu.panasonic.com. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Panasonic Office. Panasonic Electronic Devices may only be used in life-support devices or systems with the express written approval of Panasonic Devices, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF ENW89814A2MF 12/01 BlueMoonTM Universal Platform CONFIDENTIAL Revision History: 2010-08-18, Revision 1.2 Previous Version: no former version where published Page Rev1.2 Subjects (major changes since last revision) Initial version Trademarks of Infineon Technologies AG ABM, BlueMoon, CONVERGATE, COSIC, C166, FALC, GEMINAX, GOLDMOS, ISAC, OMNITUNE, OMNIVIA, PROSOC, SEROCCO, SICOFI, SIEGET, SMARTi, SMINT, SOCRATES, VINAX, VINETIC, VOIPRO, X-GOLD, XMM, X-PMU, XWAY Other Trademarks Microsoft, Visio, Windows, Windows Vista, Visual Studio, Win32 of Microsoft Corporation. Linux of Linus Torvalds. FrameMaker, Adobe Reader, Adobe Audition of Adobe Systems Incorporated. APOXI, COMNEON of Comneon GmbH & Co. OHG. PrimeCell, RealView, ARM, ARM Developer Suite (ADS), Multi-ICE, ARM1176JZ-S, CoreSight, Embedded Trace Macrocell (ETM), Thumb, ETM9, AMBA, ARM7, ARM9, ARM7TDMI-S, ARM926EJ-S of ARM Limited. OakDSPCore, TeakLite DSP Core, OCEM of ParthusCeva Inc. IndoorGPS, GL-20000, GL-LN-22 of Global Locate. mipi of MIPI Alliance. CAT-iq of DECT Forum. MIPS, MIPS II, 24KEc, MIPS32, 24KEc of MIPS Technologies, Inc. Texas Instruments, PowerPAD, C62x, C55x, VLYNQ, Telogy Software, TMS320C62x, Code Composer Studio, SSI of Texas Instruments Incorporated. Bluetooth of Bluetooth SIG, Inc. IrDA of the Infrared Data Association. Java, SunOS, Solaris of Sun Microsystems, Inc. Philips, I2C-Bus of Koninklijke Philips Electronics N.V. Epson of Seiko Epson Corporation. Seiko of Kabushiki Kaisha Hattori Seiko Corporation. Panasonic of Matsushita Electric Industrial Co., Ltd. Murata of Murata Manufacturing Company. Taiyo Yuden of Taiyo Yuden Co., Ltd. TDK of TDK Electronics Company, Ltd. Motorola of Motorola, Inc. National Semiconductor, MICROWIRE of National Semiconductor Corporation. IEEE of The Institute of Electrical and Electronics Engineers, Inc. Samsung, OneNAND, UtRAM of Samsung Corporation. Toshiba of Toshiba Corporation. Dallas Semiconductor, 1-Wire of Dallas Semiconductor Corp. ISO of the International Organization for Standardization. IEC of the International Engineering Consortium. EMV of EMVCo, LLC. Zetex of Zetex Semiconductors. Microtec of Microtec Research, Inc. Verilog of Cadence Design Systems, Inc. ANSI of the American National Standards Institute, Inc. WindRiver and VxWorks of Wind River Systems, Inc. Nucleus of Mentor Graphics Corporation. OmniVision of OmniVision Technologies, Inc. Sharp of Sharp Corporation. Symbian OS of Symbian Software Ltd. Openwave of Openwave Systems, Inc. Maxim of Maxim Integrated Products, Inc. Spansion of Spansion LLC. Micron, CellularRAM of Micron Technology, Inc. RFMD of RF Micro Devices, Inc. EPCOS of EPCOS AG. UNIX of The Open Group. Tektronix of Tektronix, Inc. Intel of Intel Corporation. Qimonda of Qimonda AG. 1GOneNAND of Samsung Corporation. HyperTerminal of Hilgraeve, Inc. MATLAB of The MathWorks, Inc. Red Hat of Red Hat, Inc. Palladium of Cadence Design Systems, Inc. SIRIUS Satellite Radio of SIRIUS Satellite Radio Inc. TOKO of TOKO Inc. The information in this document is subject to change without notice. Last Trademarks Update 2008-11-17 Product Overview 3 Revision 1.2, 2010-08-18 CONFIDENTIAL Table of Contents PAN1320-HCI-BT2.1 ENW89814A2MF Table of Contents Table of Contents . 4 List of Figures . 6 List of Tables . 7 General Device Overview . 8 Features . 8 Block Diagram . 9 Pin Configuration LGA . 9 Pin Description . 10 System Integration . 12 FW version . 13 Basic Operating Information . 14 Power Supply . 14 Clocking . 14 Interfaces . 15 HCI / UART Interface . 15 Supported Transport Layers . 15 UART . 15 Baud Rates . 15 PCM Interface . 17 Overview . 17 WLAN Coexistence Interface . 19 General Device Capabilities . 20 HCI+ and Bluetooth Device Data (BD_DATA) . 20 Manufacturer Mode . 20 Firmware ROM Patching . 20 Patch Support . 20 Bluetooth Capabilities . 21 Supported Features . 21 Not-supported Features . 21 PAN1320-HCI Specifics and Extensions . 21 During Connection . 21 Scatternet and Piconet Capabilities . 21 Role Switch . 22 Dynamic Polling Strategy . 22 Adaptive Frequency Hopping (AFH) . 22 Channel Quality Driven Data Rate Change (CQDDR) . 22 Synchronous Links . 22 Interface . 22 Voice Coding . 24 RSSI and Output Power Control . 24 Received Signal Strength Indication (RSSI) . 24 Output Power Control . 24 Ultra Low Transmit Power . 24 Electrical Characteristics . 25 Absolute Maximum Ratings . 25 Operating Conditions . 25 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 3 3.1 3.1.1 3.1.2 3.1.2.1 3.2 3.2.1 3.3 4 4.1 4.2 4.3 4.3.1 5 5.1 5.2 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.1.3 5.3.1.4 5.3.1.5 5.3.2 5.3.2.1 5.3.2.2 5.3.3 5.3.3.1 5.3.3.2 5.3.3.3 6 6.1 6.2 Product Overview 4 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Table of Contents 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.4.1 6.5 6.5.1 6.5.1.1 DC Characteristics . 26 Pad Driver and Input Stages . 26 Pull-ups and Pull-downs . 28 Protection Circuits . 28 System Power Consumption . 29 AC Characteristics . 29 Characteristics of 32.768 kHz Clock Signal . 30 RF Part . 30 Characteristics RF Part . 30 Bluetooth Related Specifications . 30 7 7.1 7.2 7.2.1 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.6.2.1 9.6.2.2 9.7 9.8 9.9 9.9.1 9.9.2 Package Information . 34 Package Marking . 34 Production Package . 34 Pin Mark . 35 Important Application Information . 36 Reference Design . 36 FCC Class B Digital Devices Regulatory Notice . 37 FCC Wireless Notice . 37 FCC Interference Statement . 38 FCC Identifier . 38 European R&TTE Declaration of Conformity . 38 Bluetooth Qualified Design ID . 40 Industry Canada Certification . 40 Label Design of the Host Product . 40 Regulatory Test House . 40 Assembly Guidelines . 41 General Description of the Module . 41 Printed Circuit Board Design . 41 Solder Paste Printing . 42 Assembly . 42 Component Placement . 42 Pin Mark . 42 Package . 43 Soldering Profile . 44 Rework . 45 Removal Procedure . 45 Replacement Procedure . 45 Alternative 1: Dispensing Solder . 45 Alternative 2: Printing Solder . 46 Inspection . 46 Component Salvage . 46 Voids in the Solder Joints . 47 Expected Void Content and Reliability . 47 Parameters with an Impact on Voiding . 47 References . 49 Terminology . 50 Product Overview 5 Revision 1.2, 2010-08-18 CONFIDENTIAL List of Figures PAN1320-HCI-BT2.1 ENW89814A2MF List of Figures Simplified Block Diagram of PAN1320-HCI . 9 Figure 1 Pin Configuration for PAN1320-HCI in Top View (footprint) . 9 Figure 2 Example of a Bluetooth System . 12 Figure 3 HCI/UART Interface . 15 Figure 4 Figure 5 PCM_Signals_Overview . 17 Figure 6 WLAN Coexistence Interface . 19 Figure 7 Package Marking . 34 Production Package . 34 Figure 8 Figure 9 Top View and Bottom View. 35 Figure 10 Reference Design Schematics . 36 Figure 11 Equipment Label. 38 Figure 12 Declaration of Conformity . 39 Figure 13 Pad Layout on the Module (Top View) . 41 Figure 14 Pin Marking. 42 Figure 15 Tape on Reel . 43 Figure 16 Eutectic Lead-Solder Profile . 44 Figure 17 Eutectic Leadfree-Solder Profile . 44 Figure 18 Solder Printing . 46 Figure 19 X-ray Picture Showing Voids Conforming to IPC-A-610D . 47 Product Overview 6 Revision 1.2, 2010-08-18 CONFIDENTIAL List of Tables PAN1320-HCI-BT2.1 ENW89814A2MF List of Tables Pin Description . 10 Table 1 UART Baud Rates . 15 Table 2 Supported Voice Settings . 24 Table 3 Absolute Maximum Ratings . 25 Table 4 Operating Conditions . 25 Table 5 Internal1 (1.5 V) Supplied Pins . 26 Table 6 Internal2 (2.5 V) Supplied Pins . 26 Table 7 VDDUART Supplied Pins . 26 Table 8 Table 9 VDDPCM Supplied Pins . 27 Table 10 ONOFF PIN . 27 Table 11 Pull-up and Pull-down Currents . 28 Table 12 Current Consumption in Different Operating Modes . 29 Table 13 Max. Load at the Different Supply Voltages . 29 PCM Interface Timing . 29 Table 14 Table 15 Timing Characteristics of PCM Interface for the First Bit . 30 BDR - Transmitter Part . 30 Table 16 BDR -Receiver Part . 31 Table 17 EDR - Transmitter Part . 32 Table 18 Table 19 EDR -Receiver Part . 33 Antennas. 37 Table 20 Product Overview 7 Revision 1.2, 2010-08-18 CONFIDENTIAL 1 General Device Overview 1.1 Features General PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview Complete Bluetooth 2.1 + EDR solution Integrates ARM7TDMI, RAM and patchable ROM Configurable for BT 1.2 and 2.0 + EDR Ultra low power design in 0.13 m CMOS Temperature range from -40C to 85C On-module voltage regulators. External supply 2.9 - 4.1 V On-module EEPROM with configuration data Reference clock included Low power clock from internal oscillator or external low power clock (e.g. 32.768 kHz) Dynamic low power mode switching Interfaces 3.25 MBaud UART with transport layer detection (HCI UART, HCI Three-Wire UART) PCM/I2S interface for digital audio WLAN coexistence interface General purpose I/Os with interrupt capabilities. JTAG for boundary scan and debug RF Transmit power programmable from -45 dBm to 4.5 dBm Transmit power typ. 2.5 dBm (default settings) Receiver sensitivity typ. -86 dBm No external components except antenna Digital demodulation for optimum sensitivity and co-/adjacent channel performance Integrated antenna switch, balun and antenna filter Integrated LNA with excellent blocking and intermodulation performance Bluetooth Piconet with seven slaves. Scatternet with two slave roles while still being discoverable SCO and eSCO with hardware accelerated audio signal processing Audio error correction algorithm (PLC) improving speech quality Power control and RSSI. Hold and Sniff. Adaptive Frequency Hopping, Quality of Service, Channel Quality Driven Data Rate Bluetooth security features: Authentication, Pairing, Encryption and Secure Simple Pairing Bluetooth test mode Sniff Subrating for lower Sniff power consumption Product Overview 8 Revision 1.2, 2010-08-18 PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview Ceramic Antenna Balun Filter CONFIDENTIAL 1.2 Block Diagram PAN1320 -HCI-BT2.1 VDD_PCM VDD_UART UART - HCI PCM1 Vsupply Low Power Clock
(Optional) 32.768 kHz Voltage Regulator EEPROM I2C PMB8763 BlueMoon UniCellular Crystal 26 MHz Figure 1 Simplified Block Diagram of PAN1320-HCI 1.3 Pin Configuration LGA F2 P1 .2 TDI RF_ ACTIVE F3 P0.1 1 F4 P0. 1 4 F5 P0.7 TX _CONF TX _CONF UARTCTS F6 VDDUART F7 P0 .4 F8 P0. 6 UARTTXD UARTRTS F1 VSS E1 P0. 1 2 SDAO D1 P0 .1 0 C1 VREG E2 P0. 1 3 SCL O D2 P0 .8 E3 P1.3 TDO SL OT_STATE E4 P0 .0 E5 P0 .1 PCMFR1 PCMCL K E6 P0 .5 UARTRXD D3 P1. 1 TCK D4 P0 .3 PCMOUT D5 P0.2 PCMIN C2 P0 .9 C3 JTAG #
C4 TRST#
C5 VDDPCM B1 P1.7 B2 P1 .8 WAKEUP _ BT WAKEUP _ HOST A1 VSS A2 P1.8 B3 P1 .0 TMS B4 P1.4 RTCK B5 ONOFF A3 A4 A5 A6 RESET #
VSUPPL Y VSUPPLY VSUPPL Y F9 VSS E9 VSS D9 NC E8 VSS D8 VSS C8 VSS C9 VSS B8 NC A8 P1. 5 CL K3 2 B9 SL EEPX A9 VSS D6 NC C6 NC B6 NC E7 NC D7 VSS C7 NC B7 NC A7 VSS Figure 2 Pin Configuration for PAN1320-HCI in Top View (footprint) Product Overview 9 Revision 1.2, 2010-08-18 CONFIDENTIAL 1.4 Pin Description PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might be removed/changed in future variants. All pins not listed below shall be not connected. Table 1 Pin Description Supply Voltage During Symbol P1.6 Input /
Output I/O/OD RESET#
AI Internal1 Internal1 P1.5/
CLK32 I/O/OD Internal1 P1.7/
WAKEUP_BT P1.8/
WAKEUP_HOST I/O/OD Internal1 I/O/OD Internal1 Reset Z Input Input PD/
Input PD After Reset Z Input Input Function Port 1.6 Hardware Reset Port 1.5 or LPM clock input (e.g. 32.768 kHz) PD/ Input Port 1.7 or Bluetooth wake-up signal PD Port 1.8 or Host wake-up signal P1.0/
TMS P1.4/
RTCK ONOFF SLEEPX P0.9 JTAG#
TRST#
P0.10 P0.8 P1.1/
TCK P0.3/
PCMOUT P0.2/
PCMIN P0.12/
SDA0 P0.13/
SCL0 P1.3/ TDO/
SLOT_STATE P0.0/
PCMFR1 I/O/OD Internal2 PU1) PU1) I/O/OD Internal2 I I/O VDDUART I/O/OD Internal2 I I I/O/OD I/O/OD I/O/OD Internal2 Internal2 Internal2 Internal2 Internal2 Z
-
PD Z PU PD Z PD PU1) Z
-
H Z PU PD Z PD PU1) Port 1.0 or JTAG interface Port 1.4 or JTAG interface Turns off module completely Sleep indication signal Port 0.9 Mode selection Port 1:
0: JTAG 1: Port JTAG interface Port 0.10 Port 0.8 Port 1.1 or JTAG interface I/O/OD VDDPCM Conf. PD def. Conf. PD def. Port 0.3 or PCM data out I/O/OD VDDPCM Z Z I/O/OD Internal2 PU PU I/O/OD Internal2 PU PU I/O/OD Internal2 Z Z I/O/OD VDDPCM PD PD Port 0.2 or PCM data in Port 0.12 or I2C data signal Port 0.13 or I2C clock signal Port 1.3 or JTAG interface or WLAN coexistence interface Port 0.0 or PCM frame signal 1 Pin No. A2 A3 A8 B1 B2 B3 B4 B5 B9 C2 C3 C4 D1 D2 D3 D4 D5 E1 E2 E3 E4 Product Overview 10 Revision 1.2, 2010-08-18 CONFIDENTIAL Table 1 Pin Description PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview Supply Voltage During Reset After Reset Function VDDPCM PD PD Input /
Output I/O/OD I/O/OD VDDUART Z Z I/O/OD Internal2 PU1) PU1) I/O/OD Internal2 I/O VDDUART I/O/OD VDDUART Z Z Z Z Z Z I/O/OD VDDUART PU PU I/O/OD VDDUART PU PU VSUPPLY SI VREG VDDUART VDDPCM VSS SO SI SI
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-
-
-
-
-
-
-
-
-
Port 0.1 or PCM clock Port 0.5 or UART receive data Port 1.2 or JTAG interface or WLAN coexistence interface Port 0.11or WLAN coexistence interface Port 0.14 or WLAN coexistence interface Port 0.7 or UART CTS flow control Port 0.4 or UART transmit data Port 0.6 or UART RTS flow control Power supply Regulated Power supply UART interface Power supply PCM interface Power supply Ground Symbol P0.1/
PCMCLK P0.5/
UARTRXD P1.2/ TDI/
RF_ACTIVE P0.11/
TX_CONF P0.14/
TX_CONF P0.7/
UARTCTS P0.4/
UARTTXD P0.6/
UARTRTS Pin No. E5 E6 F2 F3 F4 F5 F7 F8 A4, A5, A6 C1 F6 C5 A1, A7, A9, C8, C9, D7, D8, E8, E9, F1, F9 1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset. If JTAG interface is not selected the port is tristate. Product Overview 11 Revision 1.2, 2010-08-18 PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview CONFIDENTIAL Descriptions of acronyms used in the pin list:
Acronym Description I O OD Z PU PD A S Input Output Output with open drain capability Tristate Pull-up Pull-down Analog (e.g. AI means analog input) Supply (e.g. SO means supply output) 1.5 System Integration PAN1320-HCI is optimized for a low bill of material (BOM) and a small PCB size. Figure 3 shows a typical application example. T R A U S 2 I
/
M C P HOST UARTRTS UARTTXD UARTRXD UARTCTS PCMCLK PCMFR1 PCMIN PCMOUT W AKEUP _HOST W AKEUP _BT RESET #
CLK32 ANTENNA PAN 1320-
HCI-BT2.1 TX_CONF RF_ ACTIVE SLOT _STATE WLAN Subsystem P U S D D V T R A U D D V M C P D D V Power Supply Bluet oot h_Syst em _Example. vsd Optional Figure 3 Example of a Bluetooth System The UART interface is used for Bluetooth HCI communication between the host and PAN1320-HCI. When the HCI UART transport layer is used, four interface lines are needed: two for data (UARTTXD and UARTRXD) and two for hardware flow control (UARTRTS and UARTCTS). When the HCI Three-Wire UART transport layer is used the hardware flow control lines are optional. In addition to the standard Bluetooth HCI commands, PAN1320-HCI supports a set of Infineon specific commands called HCI+. Digital audio can either be sent over the HCI interface or over the dedicated PCM/I2S interface. The PCM/I2S interface is highly configurable. Product Overview 12 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF General Device Overview Low power mode control of PAN1320-HCI and the host can be implemented in different ways, either using the dedicated WAKEUP_HOST and WAKEUP_BT signals or using signaling over the HCI interface. The host can reset PAN1320-HCI via the RESET# signal. A low power clock can be connected to CLK32 or generated internally by a low power oscillator. Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages. The UART and the PCM interfaces have separate supply voltages so that they can comply with host signaling. If a WLAN subsystem is collocated with PAN1320-HCI the WLAN coexistence interface should be used to enhance Bluetooth and WLAN performance. To coexist with external WLAN devices PAN1320-HCI supports adaptive frequency hopping. 1.6 FW version PAN1320-HCI is available in different versions. Please check corresponding release documents for latest information. Product Overview 13 Revision 1.2, 2010-08-18 CONFIDENTIAL 2 Basic Operating Information PAN1320-HCI-BT2.1 ENW89814A2MF Basic Operating Information 2.1 Power Supply PAN1320-HCI is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The PAN1320-HCI chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces. The PCM interface and the UART interface are supplied with dedicated, independent, reference levels via the VDDPCM and VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5 V(Internal1). Section 1.4 provides a mapping between pins and supply voltages. The I/O power domains (VDDPCM and VDDUART) are completely separated from the other power domains and can stay present also in low power modes. 2.2 Clocking PAN1320-HCI has one clock input CLK32 that is optional. If used this 32.768 kHz clock must always be present to assist PAN1320-HCI to keep the time in low power modes. The low power clock can be generated internally by the crystal oscillator and/or the low power oscillator or provided externally. Product Overview 14 Revision 1.2, 2010-08-18 CONFIDENTIAL 3 Interfaces PAN1320-HCI-BT2.1 ENW89814A2MF Interfaces 3.1 HCI / UART Interface The HCI/UART interface is the main communication interface between the host and PAN1320-HCI. The standard HCI commands are supported together with an Infineon-specific set of commands called HCI+. The interface consists of four UART signals and two wake-up signals as shown in Figure 4. Depending on which HCI transport layer that is used, some or all of the signals are needed. UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP_BT WAKEUP_HOST UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP_BT WAKEUP_HOST HCI_UART_Interface.vsd Figure 4 HCI/UART Interface 3.1.1 Supported Transport Layers PAN1320-HCI supports the HCI Three-Wire UART transport layer and two derivatives of the HCI UART transport layer (HCI UART-4W and HCI UART-6W) where the only difference is how low power modes are handled. PAN1320-HCI automatically detects which transport layer that is used by the host. 3.1.2 UART The on-chip UART (Universal Asynchronous Receiver and Transmitter) is compatible with standard UARTs and is optimized for Bluetooth communication. Hardware support for SLIP1) framing and 16-bit CRC calculation enhances performance with the HCI Three-Wire UART transport layer. A separate supply voltage, VDDUART, makes it easy to connect the UART interface to any system. 3.1.2.1 Baud Rates The supported baud rates are listed in Table 2 together with the small deviation error that results from the internal clock generation. The default baud rate is 115200 Baud. Table 2 UART Baud Rates Wanted Baud Rate Real Baud Rate Deviation Error (%) 9600 19200 9615 19230 0.16 0.16 1) See http://www.ietf.org/rfc/rfc1055.txt for information about SLIP. Product Overview 15 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Interfaces Table 2 UART Baud Rates (contd) Wanted Baud Rate Real Baud Rate Deviation Error (%) 38400 57600 115200 230400 460800 921600 1843200 3250000 38461 57522 115044 230088 464285 928571 1857142 3250000 0.16
-0.14
-0.14
-0.14 0.76 0.76 0.76 0 Product Overview 16 Revision 1.2, 2010-08-18 CONFIDENTIAL 3.2 PCM Interface PAN1320-HCI-BT2.1 ENW89814A2MF The PCM interface is used to exchange synchronous data (usually audio) between PAN1320-HCI and the host as well as to connect e.g. an external audio codec or an external DSP to PAN1320-HCI. It can be configured as an industry standard PCM interface supporting long and short frame synchronization, as an I2S interface or as an IOM-2 interface in terminal mode with reduced capabilities. The main features of the PCM interface are:
Two bidirectional PCM channels Separate supply voltage (VDDPCM) for easy interfacing to other systems Support of 16-bit linear samples and 8-bit A-law/-law compressed samples as defined in the Bluetooth specification 8 x 32-bit FIFOs for each channel Programmable frame length Programmable frame signal length Programmable channel start positions Programmable idle level on PCMOUT Programmable low-power/inactive levels on all PCM pins Data word LSB justified or MSB justified with respect to frame signal Clock master/slave mode Frame master/slave mode Fractional divider for PCM clock generation 3.2.1 Overview The PCM interface consists of five signals as shown in Figure 5 below. PCMCLK PCMOUT 1 1 1 1 1 M S B 4 3 2 1 0 L 9 8 7 6 5 4 3 2 1 S B IDLE M 1 1 1 1 1 S B 4 3 2 1 0 L 9 8 7 6 5 4 3 2 1 S B PCMIN PCMFR 1 M 1 1 1 1 1 S B 4 3 2 1 0 L 9 8 7 6 5 4 3 2 1 S B Dont Care M 1 1 1 1 1 S B 4 3 2 1 0 L 9 8 7 6 5 4 3 2 1 S B F rame Signal Length Channel 2 Start Position Data W ord Length F rame Length IDLE Dont Care M 1 1 1 S B 4 3 2 M 1 1 1 S B 4 3 2 PCM_Interface_ PCM_ Signals_Overview.vsd Figure 5 PCM_Signals_Overview The clock signal PCMCLK is the timing base for the other signals in the PCM interface. In clock master mode, PAN1320-HCI generates PCMCLK from the internal system clock using a fractional divider. In clock slave mode PCMCLK is an input to PAN1320-HCI and has to be supplied by an external source. The maximum PCMCLK frequency (in both modes) is 1/8 of the internal system clock frequency. The PCM interface supports up to two bidirectional channels. Data is transmitted on PCMOUT and received on PCMIN, always with the most significant bit first. 16-bit linear audio samples and 8-bit A-law or -law compressed audio samples are supported. The samples are organized in frames such that each frame contains one sample in each direction of each active channel. The frame rate (i.e. sample rate) is controlled by the PCMCLK frequency and the programmable Frame Length. In the firmware the sample rate has been fixed to 8 kHz. This means that the PCMCLK frequency can be calculated from Frame Length and does not have to be specified. Product Overview 17 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Each channel has its own frame signal (PCMFR1/PCMFR2) that indicates where in the frame the channel starts. The Frame Signal Length is programmable. The start position of PCMFR2 in the frame is also programmable
(Channel 2 Start Position). PCMFR1 always starts at the beginning of the frame. In frame master mode, PAN1320-HCI generates PCMFR1 and PCMFR2. In frame slave mode the signal PCMFR1 is an input to PAN1320-HCI and has to be supplied externally. PCMFR2 is still generated by PAN1320-
HCI. When only one channel the HCI command HCI_Infineon_Write_PCM_Mode. is used PCMFR2 can be switched off with In PAN1320-HCI the second PCM channel cannot be used. The on-module bluetooth controller can handle two PCM channels but due to restrictions in the controller pinout the second PCM channel cannot be supported when using EEPROM. Product Overview 18 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF 3.3 WLAN Coexistence Interface PAN1320-HCI has a WLAN coexistence interface that is based on the IEEE 802.15.2 Packet Traffic Arbitration
(PTA) scheme2). The interface prevents interference between collocated WLAN and Bluetooth devices by not letting the two devices transmit and/or receive at the same time. WLAN packets and Bluetooth packets are assigned priorities, and a control unit decides on a per-packet basis which of the devices that should be allowed to operate. The interface uses three wires as shown in Figure 6. Host PAN1320-HCI-BT2.1 l o r t n o C t i n U TX_CONF SLOT_STATE RF_ACTIVE Host W LAN_Coexistence_Interface_2 .1.vsd Figure 6 WLAN Coexistence Interface 2) 802.15.2: Coexistence of Wireless Personal Area Networks with other Wireless Devices Operating in Unlicensed Frequency Bands, IEEE, 28 August 2003 Product Overview 19 Revision 1.2, 2010-08-18 CONFIDENTIAL 4 General Device Capabilities PAN1320-HCI-BT2.1 ENW89814A2MF General Device Capabilities 4.1 HCI+ and Bluetooth Device Data (BD_DATA) In addition to the standard Bluetooth HCI commands and events, PAN1320-HCI supports a set of Infineon-specific commands and events called HCI+. All Infineon-specific features are accessed using HCI+. All configuration information that is critical for correct operation of PAN1320-HCI is called Bluetooth Device Data
(BD_DATA). This data is stored in the modules EEPROM and is initialized during module manufacturing. BD_DATA can be Infineon_Read_BD_Data and Infineon_Write_BD_Data. read and written with the HCI+ commands Note: Each PAN1320-HCI module is delivered with a unique Bluetooth device address in its BD_DATA. This information should not be changed!
4.2 Manufacturer Mode HCI+ commands that modify critical information are not available during normal operation. To access these commands the Infineon_Manufacturer_Mode command. to enter manufacturer mode with tell PAN1320-HCI the host must first Operations that are only allowed in manufacturer mode are for example:
Changing the Baud rate with Infineon_Set_UART_Baudrate. Accessing Bluetooth Device Data (BD_DATA) with any of the following commands:
Infineon_Write_BD_Data, Infineon_Read_BD_Data, Infineon_Write_Ext_EEPROM_Data, Infineon_Read_Ext_EEPROM_Data. Accessing internal memory and registers with Infineon_Memory_Write and Infineon_Memory_Read. It is necessary to leave manufacturer mode before start of normal operation. Leaving manufacturer mode is done with the Infineon_Manufacturer_Mode command. 4.3 Firmware ROM Patching 4.3.1 Patch Support PAN1320-HCI contains dedicated hardware that makes it possible to apply patches to any code and data in the firmware ROM. The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content. In addition to this, an 8 kByte area of the firmware RAM has been reserved for patches. This area can be filled with any combination of code and data. Product Overview 20 Revision 1.2, 2010-08-18 CONFIDENTIAL 5 Bluetooth Capabilities PAN1320-HCI-BT2.1 ENW89814A2MF Bluetooth Capabilities 5.1 Supported Features PAN1320-HCI supports all new core features in the Bluetooth 2.1 + EDR specification, including:
Enhanced Data Rate up to 3 Mbit/s Adaptive Frequency Hopping (AFH) All packet types All LMP features except those related to the features listed in Chapter 5.2 Authentication, Pairing and Encryption Secure Simple Pairing Sniff Subrating Extended Inquiry Response Quality of Service Channel Quality Driven Data Rate change Sniff, Hold Role Switch RSSI and Power Control Power class 2 and 3 7 point-to-multipoint connections Scatternet with two slave roles while still being discoverable 2 synchronous links (SCO/eSCO) A-law, -law, CVSD and transparent synchronous data Dual SCO/eSCO channels in scatternet 5.2 Not-supported Features Park State Master Link Key Broadcast 5.3 PAN1320-HCI Specifics and Extensions 5.3.1 During Connection 5.3.1.1 Scatternet and Piconet Capabilities PAN1320-HCI supports point-to-multipoint and scatternet scenarios:
Up to 7 links Up to 2 simultaneous slave roles Always capable of responding to inquiry and remote name request Always capable of Inquiry Product Overview 21 Revision 1.2, 2010-08-18 CONFIDENTIAL 5.3.1.2 Role Switch PAN1320-HCI-BT2.1 ENW89814A2MF Bluetooth Capabilities Only one role switch can be performed at a time. If a role switch request is pending, other role switch requests on the same or other links are rejected. If a role switch fails, PAN1320-HCI will automatically try again a maximum of three times. Encryption (if present) is stopped in the old piconet before a role switch is performed and re-enabled when the role switch has succeeded or failed. If the Bluetooth 2.1 introduced feature pause encryption is enabled in PAN1320-HCI and supported in the remote device, the the encryption will instead be paused before the role switch and resumed after the role switch which leads to an atomic encryption of data throughout the role switch. If the physical link is in Sniff Mode or Hold Mode, or has any synchronous logical transports, a role switch will not be performed. 5.3.1.3 Dynamic Polling Strategy In addition to the regular polling scheme, PAN1320-HCI dynamically assigns unused slots to links where data is exchanged. This adapts very well to bursty traffic and improves throughput and latency on the links. 5.3.1.4 Adaptive Frequency Hopping (AFH) PAN1320-HCI supports adaptive frequency hopping according to the Bluetooth 2.1 + EDR specification. AFH switch and channel classification are supported both as master and slave. Channel classification from the host is also supported. A number of HCI+ commands and events are available to provide information about AFH operation. The commands Infineon_Enable_AFH_Info_Sending and Infineon_Disable_AFH_Info_Sending turn on and off the Infineon_AFH_Info events that provide detailed information about channel classification, channel maps, interferers, etc. If enabled by the Infineon_Enable_Infineon_Events command, the Infineon_AFH_Extraordinary_RSSI event informs the host whenever extraordinary RSSI measurements in unused slots have been started. This is done when the number of known good channels has decreased below a critical limit and periodically after a defined time. The Infineon_Set_AFH_Measurement_Period command can be used to configure the duration of the AFH measurement period. 5.3.1.5 Channel Quality Driven Data Rate Change (CQDDR) PAN1320-HCI supports channel quality driven data rate change according to the Bluetooth 2.1 + EDR specification. A device that receives an LMP_preferred_rate message is not required to follow all recommendations. PAN1320-HCI normally at least follows the recommendation whether to use forward error correction (FEC) or not. If possible, recommendations about packet size and modulation scheme will be taken into account. When PAN1320-HCI sends an LMP_preferred_rate to another device the proposal always includes preferences for all parameters. The HCI+ commands Infineon_Enable_CQDDR_Info_Sending and Infineon_Disable_CQDDR_Info_Sending turn on and off sending of the Infineon_CQDDR_Info event. This event provides information to the host every time a new CQDDR proposal is sent to a remote device. The link keys are stored in the modules EEPROM. 5.3.2 Synchronous Links PAN1320-HCI supports up to two simultaneous synchronous links (SCO/eSCO). 5.3.2.1 Interface The interface for synchronous data is either the HCI transport layer or the dedicated PCM/I2S interface. The choice of interface for a synchronous connection is done with the HCI+ command Product Overview 22 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Bluetooth Capabilities Infineon_Config_Synchronous_Interface and must be done before the connection is established. The default interface is configurable via the bit Default_SCO_interface in the BD_DATA parameter BB_Conf. All details about the PCM/I2S interface are described in Section 3.2. Product Overview 23 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Bluetooth Capabilities 5.3.2.2 Voice Coding Table 3 shows the supported values of the Bluetooth parameter Voice_Settings. Table 3 Supported Voice Settings Parameter Input Coding Input Data Format Input Sample Size Air Coding Format Linear_PCM_Bit_Pos Supported Values Linear (PCM/I2S only), -law, A-law 2s complement 16-bit (only relevant for linear input coding) CVSD, -law, A-law, Transparent Data Not used. Please see the parameter Channel_Pos in the Infineon_Write_PCM_Mode command for similar functionality. PAN1320-HCI supports transcoding between any combination of linear, -law and A-law. If the air coding format is Transparent Data and the synchronous interface is the transport layer, the input coding is ignored. If transparent data is sent through the PCM/I2S interface, the input coding determines if 8-bit or 16-bit samples are used. Transparent Data is the only setting for which data rates other than 64 kbit/s can be used. 5.3.3 RSSI and Output Power Control 5.3.3.1 Received Signal Strength Indication (RSSI) PAN1320-HCI supports received signal strength measurements and uses LMP signaling to keep the output power of a remote device within the golden receive power range. The range is set with the BD_DATA parameters RSSI_Min and RSSI_Max. 5.3.3.2 Output Power Control PAN1320-HCI supports power control according to the Bluetooth 2.1+EDR specification. The output power can be controlled in up to 4 configurable steps. PAN1320-HCI can work as a class 2 or 3 device, depending on the settings. Fine tuning can be used on the power steps. A default sub-state power step can be set The power step configuration is set through BD_DATA parameters. The Inquiry output power can be programmed with the Write Inquiry Transmit Power Level command introduced in the 2.1 Bluetooth Core specification. 5.3.3.3 Ultra Low Transmit Power For high security devices the output power can be reduced to a value that reduces the communication range to a few inches. This mode is enabled with the HCI+ command Infineon_TX_Power_Config. Product Overview 24 Revision 1.2, 2010-08-18 CONFIDENTIAL 6 Electrical Characteristics 6.1 Absolute Maximum Ratings PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 4 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Storage temperature VSUPPLY supply voltage VDDUART supply voltage VDDPCM supply voltage VREG VREG ONOFF Input voltage range Output voltage range ESD Min. Typ. Max.
-40
-0.3
-0.9
-0.9
-0.3
-0.3
-0.3
-0.9
-0.9 125 6.0 4.0 4.0 4.0 VSUPPLY C V V V V V VSUPPLY+0.3 V 4.0 4.0 1.0 V V kV VSUPPLY > 4 V VSUPPLY < 4 V
-9 According to MIL-STD883D method 3015.7 Note: Stresses above those listed here are likely to cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Maximum ratings are not operating conditions. 6.2 Operating Conditions Table 5 Operating Conditions Parameter Symbol Values Unit Note / Test Condition Operating temperature Main supply voltage (Vsupply) VDDUART VDDPCM Min. Typ. Max.
-40 2.9 1.35 1.35 85 4.1 3.6 3.6 C V V V Product Overview 25 Revision 1.2, 2010-08-18 CONFIDENTIAL 6.3 DC Characteristics 6.3.1 Pad Driver and Input Stages For more information, see Chapter 1.4. Table 6 Internal1 (1.5 V) Supplied Pins PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Parameter Symbol Values Unit Note / Test Condition Input low voltage Input high voltage Output low voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min. Typ. Max.
-0.3 1.15 1.1 0.27 3.6 0.25 1 10 0.01 1 V V V V mA pF A IOL = 1 mA IOH = -1 mA Input and output drivers disabled 1) The totaled continuous load for all Internal1 supplied pins shall not exceed 2mA at the same time Table 7 Internal2 (2.5 V) Supplied Pins Parameter Symbol Values Unit Note / Test Condition Input low voltage Input high voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min. Typ. Max.
-0.3 1.93 1.93 2.0 2.1 0.45 2.8 3.6 0.25 0.15 5 10 0.01 1 V V V V V V V mA pF A P0.10 Other pins IOL = 5 mA IOL = 2 mA IOH = -5 mA IOH = -2 mA Input and output drivers disabled 1) The totaled continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time Table 8 VDDUART Supplied Pins Parameter Symbol Input low voltage Input high voltage Input high voltage Min.
-0.3 Values Typ. Max. Unit Note / Test Condition 0.2*VDDUART V 0.7*VDDUART VDDUART+0.3 V P0.5/UARTRXD 0.7*VDDUART 3.6 V Other pins Product Overview 26 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 8 VDDUART Supplied Pins (contd) Parameter Symbol Values Unit Note / Test Condition Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min. Typ. Max. VDDUART
-0.25 VDDUART
-0.15 0.25 0.15 5 10 0.01 1 V V V V mA pF A IOL = 5 mA VDDUART = 2.5 V IOL = 2 mA VDDUART = 2.5 V IOH = -5 mA VDDUART = 2.5 V IOH = -2 mA VDDUART = 2.5 V Input and output drivers disabled 1) The totaled continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 9 VDDPCM Supplied Pins Parameter Symbol Input low voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min.
-0.3 0.7*VDDPCM VDDPCM
-0.25 VDDPCM
-0.15 Values Typ. Max. Unit Note / Test Condition 0.2*VDDPCM 3.6 0.25 0.15 5 10 0.01 1 V V V V V V mA pF A IOL = 5 mA VDDPCM = 2.5 V IOL = 2 mA VDDPCM = 2.5 V IOH = -5 mA VDDPCM = 2.5 V IOH = -2 mA VDDPCM = 2.5 V Input and output drivers disabled 1) The totaled continuous load for all VDDPCM supplied pins shall not exceed 35 mA at the same time Table 10 ONOFF PIN Parameter Symbol Values Unit Note / Test Condition Min. Typ. Input low voltage Input high voltage Input current 1.7
-1 Max. 0.7 VSUPPLY V V 0.01 1 A ONOFF = 0 V Product Overview 27 Revision 1.2, 2010-08-18 CONFIDENTIAL 6.3.2 Pull-ups and Pull-downs PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 11 Pull-up and Pull-down Currents Pin Pull Up Current Pull Down Current Unit Conditions Min. Typ. Max. Min. Typ. Max. 260 740 1300 N/A N/A N/A A 22 130 350 23 150 380 A 4.2 24 68 3.0 20 55 A 1.1 6.0 17 0.75 5.0 14 A Pull-up current measured with pin voltage = 0 V Pull-down current measured with pin voltage =
supply voltage Min measured at 125C with supply = 1.35 V Typ. measured at 27C with supply = 2.5V Max measured at
-40C with supply = 3.63 V P0.12/SDA0, P0.13/SCL0 TRST#, JTAG#, P0.0/PCMFR1, P0.1/PCMCLK, P0.2/PCMIN, P0.3/PCMOUT P0.4/UARTTXD, P0.5/UARTRXD, P0.6/UARTRTS, P0.7/UARTCTS, P0.10/PSEL1, P0.8/PAON, P0.9/PSEL0, P0.11/RXON, P0.14/TX_CONF, P0.15/SLEEPX P1.0/TMS, P1.1/TCK, P1.2/TDI, P1.3/TDO, P1.4/RTCK, P1.5/CLK32, P1.6, P1.7/WAKEUP_BT, P1.8/WAKEUP_HOST, 6.3.3 Protection Circuits All pins have an inverse protection diode against VSS. P0.10 has an inverse diode against Internal2. P0.5/UARTRXD has an inverse diode against VDDUART. All other pins have no diode against their supply. Product Overview 28 Revision 1.2, 2010-08-18 CONFIDENTIAL 6.3.4 System Power Consumption PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics The following table shows the Vsupply current consumption. All I/O currents are neglected since they depend mainly on the external load. T = 25C, Output Power = 0 dBm Table 12 Current Consumption in Different Operating Modes Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Ultra Low Power Mode Page & Inquiry Scan (1.28 s) Sniff (1.28 s) ACL (Transmit DH1) ACL (Receive DH1) ACL (Transmit 2-DH1) ACL (Receive 2-DH1) ACL (Transmit 3-DH1) ACL (Receive 3-DH1) 170 1.1 0.35 A mA mA 38 35 40 37 40 37 mA Basic Rate, 179.2 kbit/s1) mA Basic Rate, 179.2 kbit/s mA Enhanced Data Rate, 358.4 kbit/s1) mA Enhanced Data Rate, 358.4 kbit/s1) mA Enhanced Data Rate, 544.0 kbit/s1) mA Enhanced Data Rate, 544.0 kbit/s1) 19 SCO (HV3) eSCO (Symmetric 64 kbit/s, EV3) eSCO (Symmetric 64 kbit/s, 2-EV3) eSCO (Symmetric 64 kbit/s, 3-EV3) eSCO (Symmetric 64 kbit/s, EV5) eSCO (Symmetric 64 kbit/s, 2-EV5) eSCO (Symmetric 64 kbit/s, 3-EV5) 1) Figure indicates maximum possible data rate with this packet type 8.7 20 13 11 14 10 mA mA mA Enhanced Data Rate mA Enhanced Data Rate mA mA Enhanced Data Rate mA Enhanced Data Rate I/O currents are not included since they depend mainly on external loads. Table 13 Max. Load at the Different Supply Voltages Parameter Symbol Values Unit Note / Test Condition Vsupply 100 mA Peak current Min. Typ. Max. 6.4 AC Characteristics Table 14 PCM Interface Timing Parameter Symbol Values Unit Note / Test Condition PCMOUT delay from rising clock edge PCMFRy setup time to falling clock edge PCMFRy hold time from falling clock edge td1 ts1 th1 Min. Typ. Max. 100 1001) 1001) ns ns ns Product Overview 29 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 14 PCM Interface Timing (contd) Parameter Symbol Values Unit Note / Test Condition PCMIN setup time to falling clock edge PCMIN hold time from falling clock edge ts2 th2 1) In frame slave mode Min. Typ. Max. 50 50 ns ns Table 15 Timing Characteristics of PCM Interface for the First Bit Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition PCMOUT delay from PCMCLK or PCMFR1 PCMFR1 delay from PCMCLK 1) T is the PCMCLK period time td1 td2
-0.25 T1) 100 ns
+0.25 T ns 6.4.1 Characteristics of 32.768 kHz Clock Signal The 32.768 kHz clock signal applied to CLK32 must be a rectangular waveform with a duty cycle of between 10%
and 90%. The frequency accuracy must be better than 250 ppm. The rise and fall time of the signal must be less than 10 s. 6.5 RF Part 6.5.1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range. Typical characteristics are the median of the production. All values refers to Infineon reference design. All values will be updated after verification/Characterisation. 6.5.1.1 Bluetooth Related Specifications Table 16 BDR - Transmitter Part Parameter Symbol Values Unit Note / Test Condition Output power (high gain) Output power (highest gain) Power control step size Frequency range fL Frequency range fH 20 dB bandwidth 2nd adjacent channel power 3rd adjacent channel power Min. Typ. Max. 0.5 4 2.5 4.5 6 4.5 8 2400 2401.3 dBm dBm dB MHz 2480.7 2483.5 MHz 0.930 1
-40
-60
-20
-40 MHz dBm dBm Default settings Maximum settings Product Overview 30 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 16 BDR - Transmitter Part (contd) Parameter Symbol Values Unit Note / Test Condition
>3rd adjacent channel power Average modulation deviation for 00001111 sequence Minimum modulation deviation for 01010101 sequence Ratio Deviation 01010101 /
Deviation 00001111 Initial carrier frequency tolerance |foffset|
Carrier frequency drift
(one slot) |fdrift|
Carrier frequency drift
(three slots) |fdrift|
Carrier frequency drift
(five slots) |fdrift|
Carrier frequency driftrate
(one slot) |fdriftrate|
Carrier frequency driftrate
(three slots) |fdriftrate|
Carrier frequency driftrate
(five slots) |fdriftrate|
0.8 Min. Typ. Max.
-64
-40 dBm 140 156 175 kHz 115 145 kHz 75 kHz 1 10 25 kHz 10 40 kHz 10 40 kHz Max. 2 of 3 exceptions @
52 MHz offset might be used 5 5 5 20 20 20 kHz/50 ms kHz/50 ms kHz/50 ms Table 17 BDR -Receiver Part Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Sensitivity C/I-performance:
-4th adjacent channel C/I-performance:
-3rd adjacent channel
(1st adj. of image) C/I-performance:
-2nd adjacent channel (image) C/I-performance:
-1st adjacent channel C/I-performance: co. channel C/I-performance:
+1st adjacent channel C/I-performance:
+2nd adjacent channel dBm Ideal wanted signal
-86
-51
-81
-40 dB
-46
-20 dB
-35
-9 dB
-4 0 dB 9
-4 11 0 dB dB
-40
-30 dB Product Overview 31 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 17 BDR -Receiver Part (contd) Parameter Symbol Values Unit Note / Test Condition C/I-performance:
+3rd adjacent channel Blocking performance 30 MHz - 2 GHz Blocking performance 2 GHz - 2.4 GHz Blocking performance 2.5 GHz - 3 GHz Blocking performance 3 GHz - 12.75 GHz Intermodulation performance Maximum input level Min. Typ. Max.
-50
-40 dB 10
-27
-27 10
-39
-34
-20 dBm Some spurious responses, but according to BT-specification dBm dBm dBm Some spurious responses, but according to BT-specification dBm Valid for all intermodulation tests dBm Table 18 EDR - Transmitter Part Parameter Symbol Values Unit Note / Test Condition Output power (high gain) Relative transmit power:
PxPSK - PGFSK Carrier frequency stability |i|
Carrier frequency stability |i+0|
Carrier frequency stability |0|
DPSK - RMS DEVM 8DPSK - RMS DEVM DPSK - Peak DEVM 8DPSK - Peak DEVM DPSK - 99% DEVM 8DPSK - 99% DEVM Differential phase encoding 1st adjacent channel power 2nd adjacent channel power 3rd adjacent channel power Min. Typ. Max.
-2.5
-4
-0.6 2 10 10 20 20 2 1 75 75 10 20 13 35 25 30 20 99 100
-26
-20
-40 dBm dB kHz kHz kHz
%
%
%
%
%
%
%
dBc dBm Carrier power measured at basic rate
-40 dBm Carrier power measured at basic rate Product Overview 32 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Electrical Characteristics Table 19 EDR -Receiver Part Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DQPSK-Sensitivity 8DPSK-Sensitivityl DQPSK - BER Floor Sensitivity 8DPSK - BER Floor Sensitivity DQPSK - C/I-performance:
-4th adjacent channel DQPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) DQPSK - C/I-performance:
-2nd adjacent channel (image) DQPSK - C/I-performance:
-1st adjacent channel DQPSK - C/I-performance:
co. channel DQPSK - C/I-performance:
+1st adjacent channel DQPSK - C/I-performance:
+2nd adjacent channel DQPSK - C/I-performance:
+3rd adjacent channel 8DPSK - C/I-performance:
-4th adjacent channel 8DPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) 8DPSK - C/I-performance:
-2nd adjacent channel (image) 8DPSK - C/I-performance:
-1st adjacent channel 8DPSK - C/I-performance:
co. channel 8DPSK - C/I-performance:
+1st adjacent channel 8DPSK - C/I-performance:
+2nd adjacent channel 8DPSK - C/I-performance:
+3rd adjacent channel Maximum input level dBm Ideal wanted signal dBm Ideal wanted signal
-88
-83
-84
-79
-53
-83
-77
-60
-60
-40 dBm dBm dB
-47
-20 dB
-31
-7 dB
-7 0 dB 11 13 dB
-9 0 dB
-44
-30 dB
-50
-40 dB
-48
-33 dB
-44
-13 dB
-25 0 dB
-5 5 dB 17 21 dB
-5 5 dB
-36
-25 dB
-46
-33 dB
-20 dBm Product Overview 33 Revision 1.2, 2010-08-18 CONFIDENTIAL 7 Package Information 7.1 Package Marking PAN1320-HCI-BT2.1 ENW89814A2MF Package Information Ordering Code Date Code FCC ID PAN1320 HW/SW ENW89814A2MF YYWWDLL FCC ID:T7VEBMU Version HW Hardware Version SW Software Version Machine readable 2D bar code Panasonic usage only , could be changed without any notice Case PCB Figure 7 Package Marking 7.2 Production Package Figure 8 Production Package All dimensions are in mm. Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm. Production _Package.vsd Product Overview 34 Revision 1.2, 2010-08-18 CONFIDENTIAL 7.2.1 Pin Mark PAN1320-HCI-BT2.1 ENW89814A2MF Package Information Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 9. Diameter of pin 1 mark on the shield is 0.40 mm. PAN 1320 12/01 ENW89814A2MF 0902401 FCC ID:T7VEBMU F9 E9 D9 F8 F7 E 8 E7 D8 D7 F6 E6 D6 F5 F4 E 5 E4 D 5 D4 F3 E3 D3 F2 F1 E 2 E1 D 2 D1 C9 C8 C7 C6 C 5 C4 C3 C 2 C1 B9 B 8 B7 B6 B 5 B4 B3 B 2 B1 A9 A 8 A7 A6 A 5 A4 A3 A 2 A1 Pin 1 marking top side Pin 1 marking bottom side Top_and _Bottom_Views.vsd Figure 9 Top View and Bottom View Product Overview 35 Revision 1.2, 2010-08-18 c:
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LL CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Important Application Information ENW89814A2MF 12/01 is intended to be installed inside end user equipment. ENW89814A2MF 12/01 is Bluetoooth-qualified and also FCC-certified and Industry Canada approved, and conforms to R&TTE (European) requirements and directives with the reference design described in Figure 10. FCC certification is valid together with the following antennas, having in mind, that this module has the Johansson antenna included:
Table 20 Antennas Manufacturer GigAnt Model Titanis Type Swivel Tyco Electronics P/N 1513151-1 Module Murata Infineon reference design LDA312G7313F-237 Ceramic chip Printed inverted F Antenna
(PIFA) Johansson Inwave 2450AT43A100 Ceramic chip antenna BST-2450 Dipole antenna Peak antenna gain Impedance 4 dBi 4 dBi 0 dBi 4 dBi 2 dBi 2 dBi 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm When using any of the above antennas, installed in the appropriate manner, it is possible to re-use the approvals for the end-product. It is, however, required to have a written consent from Infineon Technologies AG to re-use the regulatory approvals for the FCC, Canada and Europe. Manufacturers of mobile, fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete product tested and approved for compliance (FCC or other when applicable). When using other antennas, a class II permissive change is required for FCC approval. The normal procedure is to first provide a technical test report showing that 4 dBi is not exceeded and to continue working with a regulatory test house to finalize the approval for a new antenna implementation. There are no parts in ENW89814A2MF 12/01 that can be modified by the user except modifications of the device BD data and loading of SW patches. Any changes or modifications made to this device that are not expressly approved by Infineon, may void the users authority to operate the equipment. 8.2 FCC Class B Digital Devices Regulatory Notice This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by 1 or more of the following measures:
Reorient or relocate the antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio or television technician for help 8.3 FCC Wireless Notice This product emits radio frequency energy, but the radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized. To meet the FCC's RF exposure rules and regulations:
The system antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Product Overview 37 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Important Application Information The system antenna used for this module must not exceed 4 dBi. Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance. 8.4 FCC Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1. This device may not cause harmful interference 2. This device must accept any interference received, including interference that may cause undesired operation. The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label (laser marking) on the outside of the OEM enclosure specifying the appropriate Panasonic FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: T7V-EBMU. 8.5 FCC ID: T7VEBMU FCC Identifier 8.6 European R&TTE Declaration of Conformity Hereby, Panasonic Electronic Devices Europe GmbH, declares that the Bluetooth module ENW89814A2MF 12/01 is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-
customer equipment should be labelled as follows:
Figure 11 Equipment Label PAN1320 in the specified reference design can be used in the following countries:
Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Product Overview 38 Revision 1.2, 2010-08-18 Panasonic CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Important Application Information Declaration of Conformity (DoC) 1999/5/EC We, Panasonic Electronic Devices Europe GmbH High Frequency Products Business Group Zeppelinstrasse 19, 21337 Lueneburg, Germany declare under our sole responsibility that the product:
Type of equipment:
Brand name:
Bluetooth 2.0+EDR Module PAN1320 Model name:
ENW89814A2MF to which this declaration relates, is in compliance with all the applicable essential requirements, and other provisions of the European Council Directive:
1999/5/EC Radio and Telecommunications Terminal Equipment Directive (R&TTE) The conformity assessment procedure used for this declaration is Annex IV of this Directive. Product compliance has been demonstrated on the basis of:
- IEC 60950-1 (2006)
-EN 301 489-1 Vl.8.1
-EN 301 489-17 V2.1.1
-EN 300 328 Vl.6.1 (2004-11)
-EN 300 328 Vl.7.1 (2006-10) For article 3.1 (a): Health and Safety of the User For article 3.1 (b): Electromagnetic Compatibility For article 3.2 : Effective use of spectrum allocated The technical contruction file is kept available at:
Panasonic Electronic Devices Europe GmbH, Zeppelinstrasse 19, 21337 Lueneburg, Germany Issued on:
31st ofMarch 2010 Signed by the manufacturer:
(Company name) Panasonic Electronic Devices Europe GmbH
(Signature)
(Printed name) Heino Kaehler
(Title) Manager Wireless Modules Parmsonft.;. Electronic n',vl c,::es rr&rte t"iirl"t-}'H r-e:r:hr r)k):;Jy C e tf.er -- tv1<J.(1tl f e Bt ZesJ.f::J-t !lfr1str 1.i3e 1 )
!;_l ; 1!i<ii L.\J lett Jrg reL -t-L}- )- {"t)).4- 131 I 8$:..J) - 30 Figure 12 Declaration of Conformity Product Overview 39 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Important Application Information 8.7 Bluetooth Qualified Design ID Manufacturers of Bluetooth devices incorporating this product can reference the following QD ID numbers according to the version of the BT core specification that their application complies with. Standard configuration BT 2.1 + ED R B014999 PAN1320 2.01 (BT v2.1 +
EDR) Configured for BE 2.0 + EDR B014940 PAN1320 2.01 (BT v2.0 +
EDR) Configured for BT 1.2 + EDR B014936 PAN1320 2.01 (BT v1.2) LMP_features =
8379FF9BFE0FFEFFH LMP_features =
8000F99BFE0FFEFFH LMP_features =
8000181BF80FFEFFH 8.8 Industry Canada Certification PAN1320 complies with the regulatory requirements of Industry Canada (IC), license: IC: 216Q-EBMU The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Panasonic IC identifier for this product as well as the IC Notice above. The IC identifiers are:
IC: 216Q-EBMU This IC identifiers are valid for all PAN1320 modules, for details, see the Chapter 29. Ordering Information. In any case the end product must be labelled exterior with
"Contient IC: 216Q-EBMU Obligations dtiquetage Les fabricants dquipements (OEM) doivent sassurer que les obligations dtiquetage du produit final sont remplies. Ces obligations incluent une tiquette clairement visible lextrieur de lemballage externe, comportant lidentifiant IC du module Panasonic inclus, ainsi que la notification ci-dessus. Les identifiants IC sont:
IC: 216Q-EBMU Ces identifiants sont valides pour tous les modules PAN1320 (Chapter 29. Ordering Information). Dans tous les cas les produits finaux doivent indiquer sur leur emballage externe une des mentions suivantes:
"Contient IC: 216Q-EBMU 8.9 Label Design of the Host Product It is recommended to include the following information on the host product label:
Contains transmitter Module FCC ID: T7VEBMU / IC: 216QEBMU 8.10 Regulatory Test House The test house used by Panasonic in the Bluetooth and Regulatory approvals for the module PAN1320:
Eurofins Product Service GmbH Storkower Str. 38c D-15526 Reichenwalde b. Berlin GERMANY Tel.: +49 33631 888 0 Fax: +49 33631 888 650 www.eurofins.com Product Overview 40 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Assembly Guidelines 9 Assembly Guidelines The target of this document is to provide guidelines for customers to successfully introduce the PAN1320-HCI module in production. This includes general description, PCB-design, solder printing process, assembly, soldering process, rework and inspection. 9.1 General Description of the Module PAN1320-HCI is a Land Grid Array (LGA 6x9) module made for surface mounting. The pad diameter is 0.6 mm and the pitch 1.2 mm. All solder joints on the module will reflow during soldering on the mother board. All components and shield will stay in place due to wetting force. Wave soldering is not possible. Surface treatment on the module pads is Nickel (5-8 m)/Gold (0.04 - 0.10 m). Figure 13 shows the pad layout on the module, seen from the component side. 15,6 1,0 0,6 1,2 F1 F2 F3 F4 F5 F6 F7 F8 F9 E1 E2 E3 E4 E5 E6 E7 E8 E9 D1 D2 D3 D4 D5 D6 D7 D8 D9 C1 C2 C3 C4 C5 C6 C7 C8 C9 B1 B2 B3 B4 B5 B6 B7 B8 B9 A2 A3 A4 A5 A6 A7 A8 A9 A1 0,6 5,0 1,35 1,2 1,35 8,7 Figure 13 Pad Layout on the Module (Top View) 9.2 Printed Circuit Board Design The land pattern on the PCB shall be according to the land pattern on the module, which means that the diameter of the LGA pads on the PCB shall be 0.6 mm. It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 m to avoid overlapping solder mask and pad. Product Overview 41 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Assembly Guidelines 9.3 Solder Paste Printing The solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree / lead composition. A no-clean solder paste is preferred, since cleaning of the solder joints is difficult because of the small gap between the module and the PCB. Preferred thickness of the solder paste stencil is 100 - 127 m (4 - 5 mils). The apertures on the solder paste stencil shall be of the same size as the pads, 0.6 mm. 9.4 Assembly 9.4.1 Component Placement In order to assure a high yield, good placement on the PCB is necessary. As a rule of thumb the tolerable misplacement is 150 m. This means that the Unistone module can be assembled with a variety of placement systems. It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package (in contrast to outline centring). This eliminates the pad to package edge tolerance. The recommendation is to pick and place the module with a nozzle in the centre of the shield. The nozzle diameter shall not be bigger than 4 mm. 9.4.2 Pin Mark Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 14. Diameter of pin 1 mark on the shield is 0.40 mm. Even if this figure below shows PAN1310, which is the type without the antenna, it is marked on PAN1320-HCI in the same style. P i n 1 0.9 2 0 .9 2 m m Fi g u re 2 a : To p V i e w Fi g u re 2 b : B o tto m V i e w P in 1 P in _ M a rk in g . v s d Figure 14 Pin Marking Product Overview 42 Revision 1.2, 2010-08-18 1
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+/- 0.3 SECTION X-X For ming f orm at : Fl at bed E st imated m ax. length : 64 met er /22B 3 reel
(I) Meas ured f rom c ent reli ne of s proc k et hole to centreline of pock et.
(II ) C umulativ e t ol erance of 10 spr ock et holes is 0 . 20 .
(II I) Meas ured f rom c ent reli ne of s proc k et hole t o cent reline of poc ket. Other m at eri al avail able.
(IV ) ALL D IM EN SI ONS I N MILLIM ETR ES U N LESS OTH E RWI SE STA TED . l e e R n o e p a T 5 1 e r u g F i
. i 1 n o s v e R i 3 4 i w e v r e v O t c u d o r P 9.5 Soldering Profile Generally all standard reflow soldering processes (vapour phase, convection, infrared) and typical temperature profiles used for surface mount devices are suitable for the Unistone module. Wave soldering is not possible. Figure 16 and Figure 17 shows example of a suitable solder reflow profile. One for leaded and one for leadfree solder. Recommended temp. profile for reflow soldering Temp.[C]
235C max. 220 5C 200C 150 10C 10 1s 30 +20/-10s 90 30s Time [s]
30 sec max 60 ~ 150 sec Figure 16 Eutectic Lead-Solder Profile Recommended temp. profile for reflow soldering (J-STD-020C) Temp.[C]
260C 255C 217C 200C 150C 25C 60 ~ 120 sec @ 3C/sec max 8 minutes max 6C/sec max Figure 17 Eutectic Leadfree-Solder Profile L ea dF ree _S old er _P rof ile .v s d Time [s]
Product Overview 44 Revision 1.2, 2010-08-18 At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality, whereas overheating the board with its components has to be avoided. Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for all solder joints on the PCB (especially on large, complex boards with different thermal masses of the components). The most recommended types are therefore forced convection or vapour phase reflow. Nitrogen atmosphere can generally improve solder joint quality, but is normally not necessary. The reflow profiles and other reflow parameters are dependent on the used solder paste. The paste manufacturer provides a reflow profile recommendation for this product. Additionally it is important not to overheat the Unistone module by a too large reflow peak temperature. Unistone contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly. Overheating in combination with excessive moisture content could result in package delaminations or cracks
(popcorn effect). The heating rate should not exceed 3C/s and max sloping rate should not exceed 4C/s. Unistone shall be handled according to MSL3, which means a floor life of 168 h in 30C/60% r.h. The Unistone module can be soldered according to max. J-STD-020C curve, assuming that all other conditions are followed stated in Product Specification, Qualification Report and in Application Note. Restriction is that PBA 31308 can be soldered two times, since one time is already consumed when soldering devices on Module. 9.6 Rework 9.6.1 Removal Procedure 1. Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a hot plate (about 225C dependent on the board). Hot plate can only be used if the board is single side assembled. The temperature of the module shall be 200-220C. 2. Use grippers or a pair of tweezers to remove the module. The module has to be gripped on two opposite edges of the module (not on the shield). 3. Remove excess solder by using solder sucker, suction soldering irons or solder wick. 9.6.2 Replacement Procedure Replacement can be done in two ways, dependent of how the solder is applied. Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module. 9.6.2.1 Alternative 1: Dispensing Solder A dispenser with controlled volume must be used to assure the same volume on every pad. The volume on each pad shall be about 0.04 mm3. 1. Dispense 0.04 mm3 on each LGA pad 2. Pick the module by a nozzle and place in the right position on the board 3. Reflow the solder. Product Overview 45 Revision 1.2, 2010-08-18 9.6.2.2 Alternative 2: Printing Solder To print solder on the module a fixture must be used. The purpose of the fixture is to get a flat surface and fix the stencil and module for printing. An example of how this fixture can be designed is shown in Figure 18. S o ld e r p a ste sten cil C a vity of th e m odu le Va c u u m h o l e s B o tto m T o o lin g p in s F ix ture S o ld e r _ P rin t in g . v s d Figure 18 Solder Printing 1. Assemble the fixture to the bottom 2. Place the module in the cavity with the LGA pads upwards 3. Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module 4. Apply vacuum to fix the solder paste stencil 5. Apply solder paste on the stencil and print by using a blade 6. Turn everything (bottom, fixture and stencil) upside down. 7. Separate carefully the bottom from the fixture 8. Pick the module by a nozzle and place in the right position on the board 9. Reflow the solder. 9.7 Inspection Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability. 9.8 Component Salvage If it is intended to send a defect Unistone module back to the supplier for failure analysis, please note that during the removal of this component no further defects must be introduced to the device, because this may hinder the failure analysis at the supplier. This includes ESD precautions, not to apply high mechanical force for component removal, and to prevent excess moisture content in the package during salvage (risk of pop corning failures). Therefore if the maximum storage time out of the dry pack (see label on packing material) is exceeded after board assembly, the PCB has to be dried 24h at 125C before soldering off the defect component, because otherwise too much moisture may have been accumulated. Product Overview 46 Revision 1.2, 2010-08-18 9.9 Voids in the Solder Joints 9.9.1 Expected Void Content and Reliability The content of voids is larger on LGA modules than for modules with BGA or leads. At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air. The void content of the UniStone module conforms to IPC-A-610D (25% or less voiding area/area). Figure 19 shows an example of void-content at a module assembled at production site. Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly. Figure 19 X-ray Picture Showing Voids Conforming to IPC-A-610D 9.9.2 Parameters with an Impact on Voiding If the void content has to be reduced following parameters have an impact. V o id s _ I P C _ A _ 6 1 0 D .v s d Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding. Flux will get entrapped on oxidized surfaces. In general, Ni/Au pads show fewer voids than HASL and OSP. Solder paste Higher activity of the flux will remove oxide rapidly and less flux will get entrapped. Voiding increases with increasing solder paste exposure time, since long exposure time will result in more oxidation and moisture pickup. Pad size A large soldering pad means that the outgassing flux has a longer way to the surface of the solder, and will thereby create more voids. Product Overview 47 Revision 1.2, 2010-08-18 Solder paste Smaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding. Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder. Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder. Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids. Too long reflow time gives larger voids Too short reflow time gives a fraction of voids Product Overview 48 Revision 1.2, 2010-08-18 CONFIDENTIAL References PAN1320-HCI-BT2.1 ENW89814A2MF References
[1] Panasonics Users Manual - Firmware Description (BMU_PBA31308_V2.01_UM_FD_Rev1.2.pdf) This document is CONFIDENTIAL and can only distributed with NDA.
[2] Panasonic Users Manual - Hardware Description (PAN1320_V12.01_UM_HD_Rev1.4.pdf) This document is CONFIDENTIAL and can only distributed with NDA.
[3]
Infineon Generic Quality Specification for Mobile Phones
(Generic Quality Specification for Mobile Phones V2.0_2007-08-16.pdf) Product Overview 49 Revision 1.2, 2010-08-18 PAN1320-HCI-BT2.1 ENW89814A2MF Terminology CONFIDENTIAL Terminology A ACK ACL AFH AHS ARQ B b B Acknowledgement Asynchronous Connection-oriented (logical transport) Adaptive Frequency Hopping Adaptive Hop Sequence Automatic Repeat reQuest bit/bits (e.g. kb/s) Byte/Bytes (e.g. kB/s) BALUN BALanced UNbalanced BD_ADDR Bluetooth Device Address BER BMU BOM BT BW C CDCT CMOS COD Bit Error Rate BlueMoon Universal Bill Of Material Bluetooth Bandwidth Clock Drift Compensation Task Complementary Metal Oxide Semiconductor Class Of Device CODEC COder/DECoder CPU Central Processing Unit CQDDR Channel Quality Driven Data Rate CRC CTS CVSD D DC DDC DH DM DMA DPSK Cyclic Redundancy Check Clear To Send (UART flow control signal) Continuous Variable Slope Delta (modulation) Direct Current Device Data Control Data High-Rate (packet type) Data Medium-Rate (packet type) Direct Memory Access Differential Phase Shift Keying (modulation) DQPSK Differential Quaternary Phase Shift Keying (modulation) DSP DUT E EDR Digital Signal Processor Device Under Test Enhanced Data Rate Product Overview 50 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Terminology EEPROM Electrically Erasable Programmable Read Only Memory eSCO Extended Synchronous Connection-Oriented (logical transport) EV F FEC FHS FIFO FM FW G GFSK GPIO GSM H HCI HCI+
HEC HV HW I I2C I2S IAC ID IEEE IF ISM J JTAG L Extended Voice (packet type) Forward Error Correction Frequency Hop Synchronization (packet) First In First Out (buffer) Frequency Modulation Firmware Gaussian Frequency Shift Keying (modulation) General Purpose Input/Output Global System for Mobile communication Host Controller Interface Infineon Specific HCI command set Header Error Check High quality Voice (packet type) Hardware Inter-IC Control (bus) Inter-IC Sound (bus) Inquiry Access Code IDentifier Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific & Medical (frequency band) Joint Test Action Group LAN Local Area Network LAP Lower Address Part LM Link Manager LMP LNA LO LPM LSB Link Manager Protocol Low Noise Amplifier Local Oscillator Low Power Mode(s) LPO Low Power Oscillator Least Significant Bit/Byte LT_ADDR Logical Transport Address Product Overview 51 Revision 1.2, 2010-08-18 CONFIDENTIAL PAN1320-HCI-BT2.1 ENW89814A2MF Terminology M MSB MSRS N NC NOP NVM O OCF OGF P PA PCB PCM PDU PER PIN PLC PLL PMU POR PTA PTT Q QoS R RAM RF ROM RSSI RTS RX RXD S SCO SIG SW SYRI T TBD Most Significant Bit/Byte Master-Slave Role Switch No Connection No OPeration Non-Volatile Memory Opcode Command Field Opcode Group Field Power Amplifier Printed Circuit Board Pulse Coded Modulation Protocol Data Unit Packet Error Rate Personal Identification Number Packet Loss Concealment Phase Locked Loop Power Management Unit Power-On Reset Packet Traffic Arbitration Packet Type Table Quality Of Service Random Access Memory Radio Frequency Read Only Memory Received Signal Strength Indication Request To Send (UART flow control signal) Receive Receive Data (UART signal) Synchronous Connection-Oriented (logical transport) Special Interest Group (Bluetooth SIG) Software Synthesizer Reference Input To Be Determined Product Overview 52 Revision 1.2, 2010-08-18 PAN1320-HCI-BT2.1 ENW89814A2MF Terminology CONFIDENTIAL TCK TDO TL TMS TX TXD U UART ULPM V VCO W Test Clock (JTAG signal) TDI Test Data In (JTAG signal) Test Data Out (JTAG signal) Transport Layer Test Mode Select (JTAG signal) Transmit Transmit Data (UART signal) Universal Asynchronous Receiver & Transmitter Ultra Low Power Mode Voltage Controlled Oscillator WLAN Wireless LAN (Local Area Network) Product Overview 53 Revision 1.2, 2010-08-18 w w w . p i d e u . p a n a s o n i c . d e Published by Panasonic Industrial Devices Europe GmbH
1 2 3 4 5 | UserMan | Users Manual | 2.94 MiB | April 16 2014 |
August 2013 ENW89841A3KF Bluetooth QD ID:B021246 (End Product Listing) FCC ID: T7VEBMU IC ID: 216QEBMU PAN1322-SPP Intels BlueMoonUniversal Platform Wireless Modules Users Manual Hardware Description Revision 1.3 Edition 2013-08-14 Published by Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 D-21337 Lneburg, Germany 2013 Panasonic Industrial Devices Europe GmbH All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Panasonic Industrial Devices Europe GmbH hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Panasonic Office in Germany or one of our Distributor or write an e-mail to wireless@eu.panasonic.com. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Panasonic Office. Panasonic Electronic Devices may only be used in life-support devices or systems with the express written approval of Panasonic Devices, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
PAN1322-SPP ENW89841A3KF ENW89841A3KF - Intels BlueMoonTM Universal Platform Revision History: 2013-08-14, Revision 1.3 Previous Version: 1.2 Revision Subjects (major changes since last revision) Rev1.0 Rev1.1 Initial Version from 2013-02-01 Delete chapter 4.3, Update module picture on page 8, delete antenna reference list in chapter 9.1, update chapter 9.8 Refer in chapter 1.7 FW Version to Appendix [2]
Update QD ID Rev1.2 Rev1.3 Trademark Information:
BlueMoon is a trademark of Intel Mobile Communications GmbH. IPhone, iPad, iPad and Apple are trademarks of Apple Inc. Users Manual Hardware Description 3 Revision 1.3, 2013-08-14
Table of Contents PAN1322-SPP ENW89841A3KF Table of Contents Table of Contents . 4 List of Figures . 6 List of Tables . 7 General Device Overview . 8 Features . 8 Block Diagram . 9 Pin Configuration LGA . 9 Pin Description . 10 System Integration . 13 SW Patch in EEPROM . 14 FW Version . 14 Basic Operating Information . 15 Power Supply . 15 Clocking . 15 Low Power Modes . 15 Low Power Mode . 15 Complete Power Down . 15 ON/OFF . 15 PAN1322-SPP Interfaces . 16 UART Interface . 16 UART . 16 Baud Rates . 16 Detailed UART Behavior . 17 UARTCTS Response Time . 17 Low Power Control . 17 General Device Capabilities . 18 RF Test Application . 18 Firmware ROM Patching . 18 Patch Support . 18 Ordering Information . 18 Bluetooth Capabilities . 19 Supported Features . 19 PAN1322-SPP Bluetooth Features . 19 Secure Simple Pairing . 19 Role Switch . 19 Sniff Mode . 19 Sniff Subrating . 19 Enhanced Power Control . 19 Encryption Pause and Resume . 20 Electrical Characteristics . 21 Absolute Maximum Ratings . 21 Operating Conditions . 21 DC Characteristics . 22 Pad Driver and Input Stages . 22 Pull-ups and Pull-downs . 24 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 3 3.1 3.1.1 3.1.1.1 3.1.1.2 3.1.1.3 3.2 4 4.1 4.2 4.2.1 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 7 7.1 7.2 7.3 7.3.1 7.3.2 Users Manual Hardware Description 4 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Table of Contents 7.3.3 7.3.4 7.4 7.4.1 7.4.1.1 8 8.1 8.2 8.2.1 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.5 10.6 10.6.1 10.6.2 10.6.2.1 10.6.2.2 10.7 10.8 10.9 10.9.1 10.9.2 11 12 Protection Circuits . 24 System Power Consumption . 25 RF Part . 25 Characteristics RF Part . 25 Bluetooth Related Specifications . 25 Package Information . 29 Package Marking . 29 Production Package . 29 Pin Mark . 30 Bluetooth Qualification and Regulatory Certification . 31 Reference Design . 31 FCC Class B Digital Devices Regulatory Notice . 32 FCC Wireless Notice . 32 FCC Interference Statement . 33 FCC Identifier . 34 European R&TTE Declaration of Conformity . 34 Bluetooth Qualified Design ID . 36 Industry Canada Certification . 36 Label Design of the Host Product . 36 Regulatory Test House . 36 Assembly Guidelines . 37 General Description of the Module . 37 Printed Circuit Board Design . 37 Solder Paste Printing . 39 Assembly . 39 Component Placement . 39 Pin Mark . 39 Package . 40 Soldering Profile . 41 Rework . 42 Removal Procedure . 42 Replacement Procedure . 42 Alternative 1: Dispensing Solder . 42 Alternative 2: Printing Solder . 43 Inspection . 43 Component Salvage . 43 Voids in the Solder Joints . 44 Expected Void Content and Reliability . 44 Parameters with an Impact on Voiding . 44 Terminology . 46 References . 50 Users Manual Hardware Description 5 Revision 1.3, 2013-08-14
List of Figures PAN1322-SPP ENW89841A3KF List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Simplified Block Diagram of PAN1322-SPP. 9 Pin Configuration for PAN1322-SPP in Top View (footprint) . 9 System Architecture Example of a Bluetooth System using eUniStone. 13 UART Interface. 16 UARTCTS Response Time. 17 Package Marking . 29 Production Package . 29 Top View and Bottom View. 30 Reference Design Schematics . 31 Cutout Drawing. 33 Equipment Label. 34 Declaration of Conformity . 35 Pad Layout on the Module (top view) . 37 Cutout Drawing. 38 Pin Marking. 39 Tape on Reel . 40 Eutectic Lead-Solder Profile . 41 Eutectic Leadfree-Solder Profile. 41 Solder Printing . 43 X-ray Picture Showing Voids Conforming to IPC-A-610D . 44 Users Manual Hardware Description 6 Revision 1.3, 2013-08-14
List of Tables PAN1322-SPP ENW89841A3KF List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Pin Description . 10 UART Baud Rates . 16 Default (non-inverted) behavior of UART signals . 17 Order Code as of 2013-05-14. 18 Absolute Maximum Ratings . 21 Operating Conditions . 21 Internal1 (1.5 V) Supplied Pins . 22 Internal2 (2.5 V) Supplied Pins . 22 VDDUART Supplied Pins . 22 VDD1 Supplied Pins . 23 ONOFF PIN . 23 Pull-up and Pull-down Currents . 24 Max. Load at the Different Supply Voltages . 25 BDR - Transmitter Part . 25 BDR - Receiver Part . 26 EDR - Transmitter Part . 27 EDR -Receiver Part . 27 Users Manual Hardware Description 7 Revision 1.3, 2013-08-14
1 General Device Overview 1.1 Features General PAN1322-SPP ENW89841A3KF General Device Overview Complete Bluetooth 2.1 + EDR solution Implements a single point-to-point data link to other SPP capable Bluetooth devices Integrates ARM7TDMI, RAM and patchable ROM Ultra low power design in 0.13 m CMOS Temperature range from -40C to 85C On-module voltage regulators. External supply 2.9 - 4.1 V On-module EEPROM with configuration data On-module tuned reference clock Module can enter low power mode in idle state and during sniff intervals Interfaces AT command interface over UART with HW flow control Default UART baudrate 115200 bit/s Module configuration reprogrammable for 9600 bit/s up to 3.25 Mbit/s UART baudrate JTAG for boundary scan in production test RF Class 2 device up to +4 dBm Receiver sensitivity typ. -86 dBm Digital demodulation for optimum sensitivity and co-/adjacent channel performance Integrated antenna, balun and ISM band filter Integrated LNA with excellent blocking and intermodulation performance Bluetooth Bluetooth V2.1 + EDR compliant Secure Simple Pairing Device A (initiating link) or Device B (accepting link) role supported Single point-to-point data link, role switch supported Packet data mode and stream data mode supported Sniff mode and Sniff Subrating is supported with above capabilities SW version available to configure specific RF certification tests 5 trusted devices stored in EEPROM Users Manual Hardware Description 8 Revision 1.3, 2013-08-14
1.2 Block Diagram PAN1322-SPP PAN1322-SPP ENW89841A3KF General Device Overview VDD1 VDD_UART UART GPIO Vsupply EEPROM I2C Ceramic Antenna PMB8754 BlueMoon UniCellular Balun Filter /
Matching Voltage Regulator Crystal 26 MHz Figure 1 Simplified Block Diagram of PAN1322-SPP 1.3 Pin Configuration LGA F4 LPMin P0.14 F5 UARTCTS F6 VDDUART F7 UARTTXD F8 UARTRTS F9 VSS F11 VSS F12 VSS F1 VSS E1 P0.12 SDA0 D1 P0.10 C1 VREG B1 P1.7 A1 VSS F2 P1.2 TDI E2 P0.13 SCL0 D2 P0.8 C2 P0.9 B2 P1.8 A2 P1.6 F3 P0.11 E3 P1.3 TDO D3 P1.1 TCK E4 LPMout P0.0 D4 P0.3 E5 P0.1 D5 P0.2 C3 JTAG#
C4 TRST#
C5 VDD1 B3 P1.0 TMS B4 P1.4 RTCK B5 ONOFF E6 UARTRXD D6
(NC) C6
(NC) B6
(NC) A3 RESET#
A4 VSUPPLY A5 VSUPPLY A6 VSUPPLY E7
(NC) D7 VSS C7
(NC) B7
(NC) A7 VSS E8 VSS D8 VSS C8 VSS B8
(NC) A8 P1.5 E9 VSS D9
(NC) C9 VSS B9 P0.15 A9 VSS Top View A11 VSS A12 VSS Figure 2 Pin Configuration for PAN1322-SPP in Top View (footprint) Users Manual Hardware Description 9 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF General Device Overview Pin Description 1.4 The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might be removed/changed in future variants. Pins not listed below shall not be connected. Pin Description Supply Voltage During Function Input /
Output I/O/OD AI I/O/OD I/O/OD I/O/OD I/O/OD Internal1 Internal1 Internal1 Internal1 Internal1 Internal2 I/O/OD Internal2 I I/O I/O/OD I I I/O/OD I/O/OD I/O/OD VDDUART Internal2 Internal2 Internal2 Internal2 Internal2 Internal2 I/O/OD VDD1 I/O/OD I/O/OD I/O/OD I/O/OD VDD1 Internal2 Internal2 Internal2 I/O/OD VDD1 I/O/OD I/O/OD VDD1 VDDUART Table 1 Pin No. A2 A3 A8 B1 B2 B3 Symbol P1.6 RESET#
P1.5 P1.7 P1.8 P1.0 /
TMS P1.4 /
RTCK ONOFF B4 B5 B9 C2 C3 C4 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 E6 F2 F3 SLEEPX P0.9 JTAG#
TRST#
P0.10 P0.8 P1.1 /
TCK P0.3 P0.2 P0.12 / SDA0 P0.13 / SCL0 P1.3 /
TDO P0.0 P0.1 P0.5 /
UARTRXD P1.2 /
TDI P0.11 After Reset Z Input Input
-
-
Z Z PD PU1) Reset Port 1.6 Z Hardware Reset, active low Input Input Port 1.5 PD/ Input PD/ Input Port 1.7 Port 1.8 PD PU1) Port 1.0 or JTAG interface Port 1.4 or JTAG interface Connect to VDD1 and refer to chapter 12 item [3]. Sleep indication signal Port 0.9 Mode selection Port 1:
0: JTAG 1: Port JTAG interface Port 0.10 Port 0.8 Port 1.1 or JTAG interface Port 0.3 PD Z PD PU1) PD Z PD PU1) PD Z PU H Z PU Conf. PD def. Z PU PU Z Conf. PD def. Z PU PU Z PD PD Z PD PD Z Port 0.2 I2C data signal I2C clock signal Port 1.3 or JTAG interface Port 0.0 LPM wakeup output Port 0.1 Port 0.5 or UART receive data Port 1.2 or JTAG interface Port 0.11 I/O/OD Internal2 PU1) PU1) I/O/OD Internal2 Z Z Users Manual Hardware Description 10 Revision 1.3, 2013-08-14
Table 1 Pin No. F4 Pin Description Symbol Input /
Output I/O Supply Voltage During Reset Z P0.14 LPmin VDDUART I/O/OD VDDUART I/O/OD VDDUART I/O/OD VDDUART Z PU PU P0.7 /
UARTCTS P0.4 /
UARTTXD P0.6 /
UARTRTS VSUPPLY VREG VDDUART VDD1 VSS SI SO SI SI PAN1322-SPP ENW89841A3KF General Device Overview Function Port 0.14 LPM wakup input Port 0.7 or UART CTS flow control Port 0.4 or UART transmit data Port 0.6 or UART RTS flow control Power supply Regulated Power supply UART interface Power supply Power supply Ground No connection After Reset Z Z PU PU
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
-
F5 F7 F8 A4, A5, A6 C1 F6 C5 A1, A7, A9, A11, A12, C8, C9, D7, D8, E8, E9, F1, F9 F11, F12 B6, B7, B8, C6, C7, D6, D9, E7 1) Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset. If JTAG interface is not selected the port is tristate. Users Manual Hardware Description 11 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF General Device Overview
Descriptions of acronyms used in the pin list:
Acronym I O OD Z PU PD A S Description Input Output Output with open drain capability Tristate Pull-up Pull-down Analog (e.g. AI means analog input) Supply (e.g. SO means supply output) Users Manual Hardware Description 12 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF General Device Overview System Integration 1.5 PAN1322-SPP is optimized for a low bill of material (BOM) and a small PCB size. Figure 3 shows a typical application example. Keys, Leds HOST UART RESET AT command interface GPIO SPP(Serial Port Profile) Loaded from EEPROM Oscillator EEPROM I2C Voltage Regulator API RFCOMM BT Stack BT Baseband BT RF BALUN VSUPPLY Antenna Example_Application_PAN1311.vsd Figure 3 System Architecture Example of a Bluetooth System using eUniStone Users Manual Hardware Description 13 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF General Device Overview The UART interface is used for communication between the host and PAN1322-SPP. The lines UARTTXD and UARTRXD are used for commands, events and data. The lines UARTRTS and UARTCTS are used for hardware flow control. Low power mode control of PAN1322-SPP and the host can be implemented in by using the pins P0.14 and P0.0. P0.14 is used by the host to allow PAN1322-SPP to enter low power mode and P0.0 is used by PAN1322-SPP to wake-up the host when attention is required. Additionally, the host could hardware reset PAN1322-SPP using the RESET# pin. Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages. The UART and the GPIOs interfaces have separate supply voltages so that they can comply with host signaling. SW Patch in EEPROM 1.6 Bug fixes for the SW in ROM are downloaded from the EEPROM. Panasonic may include new bug fixes in EEPROM during product lifetime. FW Version 1.7 PAN1322-SPP is available in different firmware (FW) versions. Please check corresponding release documents for latest information in item [2]. The identifier about the software version will be visible on the module, please refer to Figure 6, here it is the identifier SW (Software). For example SW01 match with FW3.1. Users Manual Hardware Description 14 Revision 1.3, 2013-08-14
2 Basic Operating Information PAN1322-SPP ENW89841A3KF Basic Operating Information Power Supply 2.1 PAN1322-SPP is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The PAN1322-SPP chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces. The GPIOs and the UART interface are supplied with dedicated, independent, reference levels via the VDD1 and VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5 V (Internal1). Section 1.4 provides a mapping between pins and supply voltages. The I/O power domains (VDD1 and VDDUART) are completely separated from the other power domains and can stay present also in low power modes. Clocking 2.2 PAN1322-SPP contains a crystal from which the internal 26 MHz system clock is generated. Also, the low power mode clock of 32,768 kHz is generated internally, which means that no external clock is needed. Low Power Modes 2.3 To minimize current consumption, eUniStone automatically switches between different low power modes. The major modes are described below. Low Power Mode 2.3.1 In Low Power Mode (LPM) most parts of eUniStone are powered down. This is done automatically in idle mode or if the link is in Sniff mode and the host allows LPM with the pin P0.14. Complete Power Down 2.3.2 If Bluetooth functionality is not needed at all, VSUPPLY should be grounded to minimize power consumption. In this state there is no activity in eUniStone and the Bluetooth state (native clock, etc.) is not updated. ON/OFF 2.3.3 PAN1322-SPP provides an alternative way to power down using the ONOFF logic input. When the ONOFF is low, the internal regulator on the module is turned OFF. The intention with the signal is to have the possibility to turn off the module without having to turn off the supply voltage. In the OFF state, the module will consume less than 1mA excluding the interface currents that is mainly set by the external load. If this signal isnt used then it should be connected to VSUPPLY on the host PCB. Users Manual Hardware Description 15 Revision 1.3, 2013-08-14
3 PAN1322-SPP Interfaces PAN1322-SPP ENW89841A3KF PAN1322-SPP Interfaces UART Interface 3.1 The UART interface is the main communication interface between the host and PAN1322-SPP. AT commands are desribed in detail in the AT Commands specification [1]. The interface consists of four UART signals and two LPM control signals as shown in Figure 4. Host UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP_BT WAKEUP_HOST Figure 4 UART Interface PAN1322 UARTTXD UARTRXD UARTRTS UARTCTS P0.14 input P0.0 output UART 3.1.1 The lines UARTTXD and UARTRXD are used for commands, responses and data. The lines UARTRTS and UARTCTS are used for hardware flow control. A separate supply voltage, VDDUART, defines the UART reference levels to fit any system requirements. Baud Rates 3.1.1.1 The UART baud rate can be configured with the BD_DATA parameter UART_Baudrate. The module is programmed for a default baudrate of 115200 baud. Reprogramming of the EEPROM configuration is possible by AT commands at manufacturing time of the end product. The baudrate written to EEPROM will be used each time PAN1322-SPP starts or, HW or SW reset is done. The host is also able to change the baudrate temporarily with an AT command. This baudrate is used by PAN1322-SPP until a HW or SW reset is done, when it will change back to the baudrate stored in the EEPROM. The supported baud rates are listed in Table 3 together with the small deviation error that results from the internal clock generation. UART Baud Rates Table 2 Wanted Baud Rate 9600 19200 38400 57600 115200 230400 460800 921600 Real Baud Rate 9615 19230 38461 57522 115044 230088 464285 928571 Deviation Error (%) 0.16 0.16 0.16
-0.14
-0.14
-0.14 0.76 0.76 Users Manual Hardware Description 16 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF PAN1322-SPP Interfaces UART Baud Rates (contd) Table 2 Wanted Baud Rate 1843200 3250000 Real Baud Rate 1857142 3250000 Deviation Error (%) 0.76 0 Detailed UART Behavior 3.1.1.2 After reset the UART interface is configured with one start bit, eight data bits, no parity bit and one stop bit. The least significant bit is transmitted first. The polarity of the UART signals can be changed with the BD_DATA parameter UART_Invert. The default (non-
nverted) behavior is shown in Table 4. Default (non-inverted) behavior of UART signals Table 3 Signal UARTTXD / UARTRXD UARTRTS / UARTCTS Level 0 1 0 1 Meaning Start bit, 0 bit in character. Idle level, stop bit Flow on Flow stopped UARTCTS Response Time 3.1.1.3 Figure 5 shows the UARTCTS response time. Assuming non-inverted UART signals, the data flow stops within the flow off response time after UARTCTS has been set to high. If UARTCTS goes high during the transmission of a byte (phase 1 in the figure) this byte will be completely transmitted. While UARTCTS is high, no data will be transmitted (phase 2). When UARTCTS goes low again, data transmission will continue (phase 3). The maximum flow off response time is 10 UART bits (including start and stop bits). As an example, if the UART baud rate is 115200 Baud, the maximum flow off response time is 10 x 1/115200 s = 87 s. max. flow off response time UARTCTS flow off response time UARTTXD art st t 0 bi t 1 bi t 2 bi t 3 bi t 4 bi t 5 bi t 6 bi t 7 bi p o st art st t 0 bi
... phase 1 phase 2 phase 3 HCI_UARTCTS_Response_Time.vsd Figure 5 UARTCTS Response Time Low Power Control 3.2 Pin P0.14 and P0.0 are optional, but strongly recommended to be used. P0.14 is used to allow PAN1322-SPP to enter Low Power Mode (LPM). P0.0 is used by PAN1322-SPP when in LPM to wake up the host. Users Manual Hardware Description 17 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF General Device Capabilities General Device Capabilities 4 This chapter describes features available in the PAN1322 (ENW89841A3KF) core. Actual feature set and how to access the features can be found in the AT Command document [1]. Release specific performance characteristics, like data speed, is related in the SW Release Notes [2]. RF Test Application 4.1 The PAN1322 module can be programmed over UART with a specific application for RF test purposes, e.g. TX continuous or TX burst mode. This test application is controlled over the UART through Intel specific HCI commands. The commands supported by this test application are described in the document T8753-2-
Infineon_Specific_HCI_Commands-7600.pdf. Firmware ROM Patching 4.2 In any chip with complex firmware in ROM it is wise to support patching. The risk of project delay is significantly reduced when problems can be solved without hardware changes. Enhancements, adaptations and bug fixes can be handled very late during design-in, even after the PAN1322 has been soldered in the final product. The well-proven patch concept used in PAN1322 is described below. Patch Support 4.2.1 PAN1322-SPP contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM. The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content. This area can be filled with any combination of code and data. The firmware patch is stored in EEPROM and automatically loaded after startup. This provides a flexible bugfix solution for the ROM part of the firmware. Ordering Information 5 This chapter shows the different order codes for the PAN1322-SPP. In case, there is no specific software version mentioned in the order, we will always deliver the latest official software release, which is downwards compatible. Please refer also to Table 2 Firmware Releases as of 2013-05-14 on Page 14. 1) Order Code as of 2013-08-14 Table 4 Order Code ENW89841A3KF Description PAN1322-SPP Bluetoth 2.1 Module with integrated Antenna and a standard SPP software. MOQ 1) 1500 1) Abbreviation for Minimum Order Quantity (MOQ). The standard MOQ for mass production are 1500 pieces, fewer only on customer demand. Samples for evaluation can be delivered at any quantity. Users Manual Hardware Description 18 Revision 1.3, 2013-08-14
6 6.1 Bluetooth Capabilities Supported Features PAN1322-SPP ENW89841A3KF Bluetooth Capabilities Bluetooth V2.1 + EDR compliant Enhanced Data Rate 2 and 3 Mbit/s symbol rate on the air Secure Simple Pairing Device A (initiating link) or Device B (accepting link) role supported Single point-to-point data link, role switch supported Packet data mode and stream data mode supported Sniff Subrating Connection to a Bluetooth Tester 5 trusted devices stored in EEPROM Link in sniff mode supported. Device enters Low Power Mode in sniff intervals if permitted by the host. 6.2 PAN1322-SPP Bluetooth Features Secure Simple Pairing 6.2.1 The device implements Secure Simple Pairing with the following association models according to BT2.1 core specification:
Numeric Comparisoon Passkey Entry Also pairing with legacy (BT2.0 and older) devices is supported. Just Works Role Switch 6.2.2 The initiating device (devA) starts as Bluetooth master of the link, the accepting device starts as Bluetooth slave of the link. The remote device can request a role change to accomodate with other Bluetooth links. If that happens, the module will send an event to the host. Also if the PAN1322-SPP start as slave, (Device B), the other device can change it's own role making PAN1322-SPP master. The host controlling PAN1322-SPP will be notified with the same event. Sniff Mode 6.2.3 The local host or the remote device can request sniff mode for the link. During sniff mode, the devices synchronize on sniff instants only. The module will enter low power mode in the sniff intervals, if allowed by the host LPM control signals. Data packets can be exchanged at the sniff instants only, so the data rate is reduced in sniff mode. The module will wake up the host when data is received or other responses need to be transmitted. Sniff Subrating 6.2.4 The local host or the remote device can request Sniff Subrating for the link. When in sniff mode, the device will automatically switch between Sniff Mode and Sniff Subrating Mode making it possible to stay longer in Low Power Mode when there is no data transmitted or received. Enhanced Power Control 6.2.5 PAN1322-SPP support Enhanced Power Control according to Bluetooth specification 3.0. The Enhanced Power Control is handled automatically to make different modulations modes transmit on optimal levels. Users Manual Hardware Description 19 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Capabilities Encryption Pause and Resume 6.2.6 Encryption Pause Resume is supported making it possible to change connection link key on an encrypted link, pause the encryption and resume it with the new link key. This is handled automatically by PAN1322-SPP to make the link more secure. Users Manual Hardware Description 20 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Electrical Characteristics
7 7.1 Table 5 Parameter Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings Storage temperature VSUPPLY supply voltage VDDUART supply voltage VDD1 supply voltage VREG VREG ONOFF Input voltage range Output voltage range ESD Symbol Values Unit Note / Test Condition Min.
-40
-0.3
-0.9
-0.9
-0.3
-0.3
-0.3
-0.9
-0.9 Typ. Max. C 125 V 6.0 V 4.0 V 4.0 V 4.0 VSUPPLY V VSUPPLY+0.3 V V 4.0 V 4.0 1.0 kV VSUPPLY > 4 V VSUPPLY < 4 V
-9 According to MIL-STD883D method 3015.7 Note: Stresses above those listed here are likely to cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Maximum ratings are not operating conditions. 7.2 Operating Conditions Table 6 Parameter Operating Conditions Symbol Operating temperature Main supply voltage (Vsupply) VDDUART VDD1 1) At ambient temperatures above 65C the maximum allowed power dissipation in the module is limited to 200 mW C V V V Values Typ. Max. 85 4.11) 3.6 3.6 Min.
-40 2.9 1.35 1.35 Unit Note / Test Condition Users Manual Hardware Description 21 Revision 1.3, 2013-08-14
7.3 DC Characteristics 7.3.1 For more information, see Chapter 1.4. Pad Driver and Input Stages Table 7 Parameter Internal1 (1.5 V) Supplied Pins Symbol Input low voltage Input high voltage Output low voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage PAN1322-SPP ENW89841A3KF Electrical Characteristics Values Typ. Max. 0.27 3.6 0.25 1 10 0.01 1 Min.
-0.3 1.15 1.1 Unit Note / Test Condition V V V V mA pF A IOL = 1 mA IOH = -1 mA Input and output drivers disabled 1) The totaled continuous load for all Internal1 supplied pins shall not exceed 2mA at the same time Table 8 Parameter Internal2 (2.5 V) Supplied Pins Symbol Unit Note / Test Condition Input low voltage Input high voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage P0.10 Other pins IOL = 5 mA IOL = 2 mA IOH = -5 mA IOH = -2 mA Input and output drivers disabled 1) The totaled continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time V V V V V V V mA pF A Values Typ. Max. 0.45 2.8 3.6 0.25 0.15 5 10 0.01 1 Min.
-0.3 1.93 1.93 2.0 2.1 Table 9 Parameter VDDUART Supplied Pins Symbol Input low voltage Input high voltage Input high voltage Users Manual Hardware Description Unit Note / Test Condition Values Min. Typ. Max.
-0.3 0.7*VDDUART 0.7*VDDUART 0.2*VDDUART V VDDUART+0.3 V 3.6 V P0.5/UARTRXD Other pins 22 Revision 1.3, 2013-08-14
Table 9 Parameter VDDUART Supplied Pins (contd) Symbol Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min. VDDUART
-0.25 VDDUART
-0.15 Values Typ. Max. 0.25 0.01 0.15 5 10 1 PAN1322-SPP ENW89841A3KF Electrical Characteristics Unit Note / Test Condition V V V V mA pF A IOL = 5 mA VDDUART = 2.5 V IOL = 2 mA VDDUART = 2.5 V IOH = -5 mA VDDUART = 2.5 V IOH = -2 mA VDDUART = 2.5 V Input and output drivers disabled 1) The totaled continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 10 Parameter VDD1 Supplied Pins Symbol Input low voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1) Pin Capacitance Magnitude Pin Leakage Min.
-0.3 0.7*VDD1 VDD1
-0.25 VDD1
-0.15 Values Typ. Max. 0.2*VDD1 3.6 0.25 0.01 0.15 5 10 1 Unit Note / Test Condition V V V V V V mA pF A IOL = 5 mA VDD1 = 2.5 V IOL = 2 mA VDD1 = 2.5 V IOH = -5 mA VDD1 = 2.5 V IOH = -2 mA VDD1 = 2.5 V Input and output drivers disabled 1) The totaled continuous load for all VDD1 supplied pins shall not exceed 35 mA at the same time Table 11 Parameter ONOFF PIN Symbol Input low voltage Input high voltage Input current Users Manual Hardware Description Values Unit Note / Test Condition Min. 1.7
-1 Typ. 0.01 Max. 0.7 VSUPPLY 1 V V A ONOFF = 0 V 23 Revision 1.3, 2013-08-14
7.3.2 Pull-ups and Pull-downs Table 12 Pin Pull-up and Pull-down Currents Pull Up Current PAN1322-SPP ENW89841A3KF Electrical Characteristics Unit Conditions A A Pull-up current measured with pin voltage = 0 V Min. 260 Typ. Max. Min. 740 1300 N/A Pull Down Current Max. N/A Typ. N/A 22 130 350 23 150 380 4.2 24 68 3.0 20 55 A 1.1 6.0 17 0.75 5.0 14 A Pull-down current measured with pin voltage =
supply voltage Min measured at 125C with supply = 1.35 V Typ. measured at 27C with supply = 2.5V Max measured at
-40C with supply = 3.63 V P0.12 P0.13 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.10 P0.8 P0.9 P0.11 P0.14 P0.15 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 Protection Circuits 7.3.3 All pins have an inverse protection diode against VSS. P0.10 has an inverse diode against Internal2. P0.5/UARTRXD has an inverse diode against VDDUART. All other pins have no diode against their supply. Users Manual Hardware Description 24 Revision 1.3, 2013-08-14
7.3.4 System Power Consumption Max. Load at the Different Supply Voltages Table 13 Parameter Vsupply Symbol Min. Values Typ. Max. 100 mA Peak current PAN1322-SPP ENW89841A3KF Electrical Characteristics Unit Note / Test Condition Note: I/O currents are not included since they depend mainly on external loads. For more details see [2]. 7.4 RF Part Characteristics RF Part 7.4.1 The characteristics involve the spread of values to be within the specific temperature range. Typical characteristics are the median of the production. All values refers to Panasonic reference design. 7.4.1.1 Bluetooth Related Specifications Table 14 Parameter BDR - Transmitter Part Symbol Output power (high gain) Output power (highest gain) Power control step size Frequency range fL Frequency range fH 20 dB bandwidth 2nd adjacent channel power 3rd adjacent channel power
>3rd adjacent channel power Average modulation deviation for 00001111 sequence Minimum modulation deviation for 01010101 sequence Ratio Deviation 01010101 /
Deviation 00001111 Initial carrier frequency tolerance |foffset|
Carrier frequency drift
(one slot) |fdrift|
Carrier frequency drift
(three slots) |fdrift|
Users Manual Hardware Description Unit Values Max. Typ. 4.5 2.5 dBm 4.5 dBm 6 8 dB 2401.3 MHz 2480.7 2483.5 MHz MHz 0.930
-40 dBm dBm
-60
-64 dBm 1
-20
-40
-40 Min. 0.5 4 2400 140 156 175 115 145 0.8 1 10 10 75 25 40 kHz kHz kHz kHz kHz Note / Test Condition Default settings Maximum settings Max. 2 of 3 exceptions @
52 MHz offset might be used 25 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Electrical Characteristics
BDR - Transmitter Part (contd) Table 14 Parameter Carrier frequency drift
(five slots) |fdrift|
Carrier frequency driftrate
(one slot) |fdriftrate|
Carrier frequency driftrate
(three slots) |fdriftrate|
Carrier frequency driftrate
(five slots) |fdriftrate|
Symbol Values Typ. 10 Max. 40 Min. Unit kHz Note / Test Condition 5 5 5 20 20 20 kHz/50 ms kHz/50 ms kHz/50 ms Table 15 Parameter BDR - Receiver Part Symbol Values Unit Note / Test Condition Min. Typ. Max.
-86
-51
-81
-40 dBm dB Ideal wanted signal
-46
-20 dB Sensitivity C/I-performance:
-4th adjacent channel C/I-performance:
-3rd adjacent channel
(1st adj. of image) C/I-performance:
-2nd adjacent channel (image) C/I-performance:
-1st adjacent channel C/I-performance: co. channel C/I-performance:
+1st adjacent channel C/I-performance:
+2nd adjacent channel C/I-performance:
+3rd adjacent channel Blocking performance 30 MHz - 2 GHz Blocking performance 2 GHz - 2.4 GHz Blocking performance 2.5 GHz - 3 GHz Blocking performance 3 GHz - 12.75 GHz Intermodulation performance Maximum input level Users Manual Hardware Description dB dB dB dB dB dB 10
-27
-27 10
-39
-20
-35
-4 9
-4
-40
-50
-34
-9 0 11 0
-30
-40 26 dBm dBm Some spurious responses, but according to BT-specification dBm dBm dBm dBm Some spurious responses, but according to BT-specification Valid for all intermodulation tests Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Electrical Characteristics
Table 16 Parameter EDR - Transmitter Part Output power (high gain) Relative transmit power:
PxPSK - PGFSK Carrier frequency stability |i|
Carrier frequency stability |i+0|
Carrier frequency stability |0|
DPSK - RMS DEVM 8DPSK - RMS DEVM DPSK - Peak DEVM 8DPSK - Peak DEVM DPSK - 99% DEVM 8DPSK - 99% DEVM Differential phase encoding 1st adjacent channel power 2nd adjacent channel power 3rd adjacent channel power Symbol Values Typ. Max.
-0.6 2 1 Min.
-2.5
-4 Unit Note / Test Condition dBm dB 99 2 10 10 20 20 100
-40 75 75 10 20 13 35 25 30 20
-26
-20
-40 kHz kHz kHz
%
%
%
%
%
%
%
dBc dBm Carrier power measured at basic rate dBm Carrier power measured at basic rate Table 17 Parameter EDR -Receiver Part DQPSK-Sensitivity 8DPSK-Sensitivityl DQPSK - BER Floor Sensitivity 8DPSK - BER Floor Sensitivity DQPSK - C/I-performance:
-4th adjacent channel DQPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) DQPSK - C/I-performance:
-2nd adjacent channel (image) DQPSK - C/I-performance:
-1st adjacent channel DQPSK - C/I-performance:
co. channel DQPSK - C/I-performance:
+1st adjacent channel Symbol Values Unit Note / Test Condition Min. Typ. Max.
-88
-83
-84
-79
-53
-83
-77
-60
-60
-40
-47
-31
-7 11
-9
-20
-7 0 13 0 dBm dBm dBm dBm dB dB dB dB dB dB Ideal wanted signal Ideal wanted signal Users Manual Hardware Description 27 Revision 1.3, 2013-08-14
Table 17 Parameter EDR -Receiver Part (contd) DQPSK - C/I-performance:
+2nd adjacent channel DQPSK - C/I-performance:
+3rd adjacent channel 8DPSK - C/I-performance:
-4th adjacent channel 8DPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) 8DPSK - C/I-performance:
-2nd adjacent channel (image) 8DPSK - C/I-performance:
-1st adjacent channel 8DPSK - C/I-performance:
co. channel 8DPSK - C/I-performance:
+1st adjacent channel 8DPSK - C/I-performance:
+2nd adjacent channel 8DPSK - C/I-performance:
+3rd adjacent channel Maximum input level PAN1322-SPP ENW89841A3KF Electrical Characteristics Symbol Values Unit Note / Test Condition Min. Typ. Max.
-44
-30
-50
-48
-44
-25
-5 17
-5
-36
-46
-20
-40
-33
-13 0 5 21 5
-25
-33 dB dB dB dB dB dB dB dB dB dB dBm Users Manual Hardware Description 28 Revision 1.3, 2013-08-14
8 Package Information 8.1 Please refer to Ordering Information on Page 18 Package Marking Ordering Code Date Code FCC ID HW/SW PAN1322 ENW89841A3KF YYWWDLL FCC ID:T7VEBMU Case PCB Figure 6 Package Marking 8.2 Production Package PAN1322-SPP ENW89841A3KF Package Information Version HW Hardware Version SW Software Version Machine readable 2D bar code Panasonic usage only, could be changed without any notice
Production Package Figure 7 All dimensions are in mm. Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm. Users Manual Hardware Description 29 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Package Information Pin Mark 8.2.1 Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 8. Diameter of pin 1 mark on the shield is 0.40mm. PAN1322 01/01 ENW89841A3KF 1302401 FCC ID:T7VEBMU F9 E9 D9 C9 B9 A9 F8 E8 D8 C8 B8 A8 F7 E7 D7 C7 B7 A7 F6 E6 D6 C6 B6 A6 F5 E5 D5 C5 B5 A5 F4 E4 D4 C4 B4 A4 F3 E3 D3 C3 B3 A3 F2 E2 D2 C2 B2 A2 F1 E1 D1 C1 B1 A1 Pin 1 marking top side Pin 1 marking bottom side Figure 8 Top View and Bottom View Users Manual Hardware Description 30 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 9 9.1 Bluetooth Qualification and Regulatory Certification Reference Design Figure 9 Reference Design Schematics Users Manual Hardware Description 31 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification ENW89841A3KF is intended to be installed inside end user equipment. ENW89841A3KF is Bluetoooth-qualified and also FCC-certified and Industry Canada approved, and conforms to R&TTE (European) requirements and directives with the reference design described in Figure 9. Manufacturers of mobile, fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete product tested and approved for compliance (FCC or other when applicable). When using other antennas, a class II permissive change is required for FCC approval. The normal procedure is to first provide a technical test report showing that 4 dBi is not exceeded and to continue working with a regulatory test house to finalize the approval for a new antenna implementation. There are no parts in ENW89841A3KF that can be modified by the user except modifications of the device BD data and loading of SW patches. Any changes or modifications made to this device that are not expressly approved by Panasonic, may void the users authority to operate the equipment. FCC Class B Digital Devices Regulatory Notice 9.2 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by 1 or more of the following measures:
Reorient or relocate the antenna Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio or television technician for help Increase the separation between the equipment and receiver FCC Wireless Notice 9.3 This product emits radio frequency energy, but the radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized. To meet the FCC's RF exposure rules and regulations:
The system antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. The system antenna used for this module must not exceed 4 dBi. Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance, please refer to Figure 10. Users Manual Hardware Description 32 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification If possible place PAN1322 in the center of main PCB. min. 15mm 8.7 5.00 min. 15mm 0 0
. 3 Restricted Area No copper any layer m m 0 4
. i n m Top View PAN1322 6
. 5 1 All dimensions are in mm. Use a Ground plane in the area surrounding the PAN1322 module wherever possible. l P a c e P A N 1 3 2 2 m o t h e r P C B
. a t t h e e d g e o f Figure 10 Cutout Drawing Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance. FCC Interference Statement 9.4 This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1. This device may not cause harmful interference Users Manual Hardware Description 33 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 2. This device must accept any interference received, including interference that may cause undesired operation. 9.5 FCC ID: T7VEBMU FCC Identifier European R&TTE Declaration of Conformity 9.6 Hereby, Panasonic Industrial Devices Europe GmbH, declares that the Bluetooth module ENW89841A3KF is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-
customer equipment should be labelled as follows:
Figure 11 Equipment Label PAN1322 in the specified reference design can be used in the following countries:
Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Users Manual Hardware Description 34 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification Figure 12 Declaration of Conformity Users Manual Hardware Description 35 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification Bluetooth Qualified Design ID 9.7 Panasonic has submitted End Product Listing (EPL) for PAN1322, based on Intel eBMU plattform, in the Qualified Product List of the Bluetooth SIG. These EPL are referring the Bluetooth qualfication of the SPP-AT application running on the eBMU chip under QD ID B021246. Manufacturers of Bluetooth devices incorporating PAN1322 can reference the same QD ID number. Bluetooth QD ID: B021246 (PAN1322 SPP BT2.1). Industry Canada Certification 9.8 PAN1322 complies with the regulatory requirements of Industry Canada (IC), license: IC: 216Q-EBMU Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the built in antenna. It is not allowed to alter the antenna or connecting an external antenna to the module. The built in antenna used for this transmitter must not be collocated or operating in conjunction with any other antenna or transmitter. Label Design of the Host Product 9.9 It is recommended to include the following information on the host product label:
Contains transmitter Module FCC ID: T7VEBMU / IC: 216QEBMU 9.10 The test house used by Panasonic in the Bluetooth and Regulatory approvals for the module PAN1322:
Regulatory Test House Eurofins Product Service GmbH Storkower Str. 38c D-15526 Reichenwalde b. Berlin GERMANY Tel.: +49 33631 888 0 Fax: +49 33631 888 650 www.eurofins.com Users Manual Hardware Description 36 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines Assembly Guidelines 10 The target of this chapter is to provide guidelines for customers to successfully introduce the PAN1322-SPP module in production. This includes general description, PCB-design, solder printing process, assembly, soldering process, rework and inspection. General Description of the Module 10.1 PAN1322-SPP is a Land Grid Array (LGA 8.7mm x 15.6mm) module made for surface mounting. The pad diameter is 0.6 mm and the pitch 1.2 mm. All solder joints on the module will reflow during soldering on the mother board. All components and shield will stay in place due to wetting force. Wave soldering is not possible. Surface treatment on the module pads is Nickel (5 - 8 m)/Gold (0.04 - 0.10 m). Figure 13 shows the pad layout on the module, seen from the component side. 15.6 mm 1.0 0.6 1.2 2.4 F1 E1 D1 C1 B1 A1 F3 E3 D3 C3 B3 A3 F2 E2 D2 C2 B2 A2 0.6 F4 E4 D4 C4 B4 A4 F5 E5 D5 C5 B5 A5 F6 E6 D6 C6 B6 A6 F7 E7 D7 C7 B7 A7 F8 E8 D8 C8 B8 A8 F9 E9 D9 C9 B9 A9 5 3
. 1 2
. 1 5 3 1
. 5.0 F11 F12 A11 A12 m m 0 7
. 8 Figure 13 Pad Layout on the Module (top view) Printed Circuit Board Design 10.2 The land pattern on the PCB shall be according to the land pattern on the module, which means that the diameter of the LGA pads on the PCB shall be 0.6 mm. It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 m to avoid overlapping solder mask and pad. Users Manual Hardware Description 37 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines If possible place PAN1322 in the center of main PCB. min. 15mm 8.7 5.00 min. 15mm 0 0
. 3 Restricted Area No copper any layer m m 0 4
. i n m Top View PAN1322 6
. 5 1 All dimensions are in mm. Use a Ground plane in the area surrounding the PAN1322 module wherever possible. l P a c e P A N 1 3 2 2 m o t h e r P C B
. a t t h e e d g e o f Figure 14 Cutout Drawing In order to preserve the characteristics of the embedded antenna, a cutout must be respected under the antenna through all metal layers of the PCB, as shown in drawing Figure 14. Placing the module inside a metal housing or close to metal parts like fasteners, shielding cages, washers, etc. can significantly affect the antenna characteristics. Users Manual Hardware Description 38 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines Solder Paste Printing 10.3 The solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree / lead composition. A no-clean solder paste is preferred, since cleaning of the solder joints is difficult because of the small gap between the module and the PCB. Preferred thickness of the solder paste stencil is 100 - 127 m (4 - 5 mils). The apertures on the solder paste stencil shall be of the same size as the pads, 0.6 mm. 10.4 Assembly Component Placement 10.4.1 In order to assure a high yield, good placement on the PCB is necessary. As a rule of thumb the tolerable misplacement is 150 m. This means that the PAN1322 module can be assembled with a variety of placement systems. It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package (in contrast to outline centring). This eliminates the pad to package edge tolerance. The recommendation is to pick and place the module with a nozzle in the centre of the shield. The nozzle diameter shall not be bigger than 4 mm. Pin Mark 10.4.2 Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 15. Diameter of pin 1 mark on the shield is 0.40 mm. PAN1322 01/01 ENW89841A3KF 1302401 FCC ID:T7VEBMU F9 E9 D9 C9 B9 A9 F8 E8 D8 C8 B8 A8 F7 E7 D7 C7 B7 A7 F6 E6 D6 C6 B6 A6 F5 E5 D5 C5 B5 A5 F4 E4 D4 C4 B4 A4 F3 E3 D3 C3 B3 A3 F2 E2 D2 C2 B2 A2 F1 E1 D1 C1 B1 A1 Pin 1 marking top side Pin 1 marking bottom side Figure 15 Pin Marking Users Manual Hardware Description 39 Revision 1.3, 2013-08-14
10.4.3 PAN1322 is packed in tape on reel according to Figure 16. Package PAN1322-SPP ENW89841A3KF Assembly Guidelines Figure 16 Tape on Reel Users Manual Hardware Description 40 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines Soldering Profile 10.5 Generally all standard reflow soldering processes (vapour phase, convection, infrared) and typical temperature profiles used for surface mount devices are suitable for the PAN1322 module. Wave soldering is not possible. Figure 17 and Figure 18 shows example of a suitable solder reflow profile. One for leaded and one for leadfree solder. 10 1s 30 +20/-10s 90 30s Time [s]
Lead _Solder _Profile .v s d 30 sec max 60 ~ 150 sec 235C max. Temp.[C]
Recommended temp. profile for reflow soldering 150 10C 220 5C 200C Figure 17 Eutectic Lead-Solder Profile Recommended temp. profile for reflow soldering (J-STD-020C) Temp.[ C]
260C 255C 217C 200C 150C 25C 60 ~ 120 sec @ 3C/sec max 8 minutes max 6C/sec max Time [s]
LeadF ree _Solder _Profile .v s d Figure 18 Eutectic Leadfree-Solder Profile Users Manual Hardware Description 41 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality, whereas overheating the board with its components has to be avoided. Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for all solder joints on the PCB (especially on large, complex boards with different thermal masses of the components). The most recommended types are therefore forced convection or vapour phase reflow. Nitrogen atmosphere can generally improve solder joint quality, but is normally not necessary. The reflow profiles and other reflow parameters are dependent on the used solder paste. The paste manufacturer provides a reflow profile recommendation for this product. Additionally it is important not to overheat the PAN1322 module by a too large reflow peak temperature. PAN1322 contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly. Overheating in combination with excessive moisture content could result in package delaminations or cracks
(popcorn effect). The heating rate should not exceed 3C/s and max sloping rate should not exceed 4C/s. PAN1322 shall be handled according to MSL3, which means a floor life of 168h in 30C/60% r.h. The PAN1322 module can be soldered according to max. J-STD-020C curve, assuming that all other conditions are followed stated in Product Specification, Qualification Report and in Application Note. Restriction is that PAN1322 can be soldered two times, since one time is already consumed when soldering devices on Module. 10.6 Rework 10.6.1 Removal Procedure 1. Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a hot plate (about 225C dependent on the board). Hot plate can only be used if the board is single side assembled. The temperature of the module shall be 200-220C. 2. Use grippers or a pair of tweezers to remove the module. The module has to be gripped on two opposite edges of the module (not on the shield). 3. Remove excess solder by using solder sucker, suction soldering irons or solder wick. Replacement Procedure 10.6.2 Replacement can be done in two ways, dependent of how the solder is applied. Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module. 10.6.2.1 Alternative 1: Dispensing Solder A dispenser with controlled volume must be used to assure the same volume on every pad. The volume on each pad shall be about 0.04 mm3. 1. Dispense 0.04 mm3 on each LGA pad 2. Pick the module by a nozzle and place in the right position on the board 3. Reflow the solder. Users Manual Hardware Description 42 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.6.2.2 Alternative 2: Printing Solder To print solder on the module a fixture must be used. The purpose of the fixture is to get a flat surface and fix the stencil and module for printing. An example of how this fixture can be designed is shown in Figure 19. Solder paste stencil C avity of the module Vacuum hol es B ottom Tooling pins Fixture Solder _Printing .v s d Figure 19 Solder Printing 1. Assemble the fixture to the bottom 2. Place the module in the cavity with the LGA pads upwards 3. Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module 4. Apply vacuum to fix the solder paste stencil 5. Apply solder paste on the stencil and print by using a blade 6. Turn everything (bottom, fixture and stencil) upside down. 7. Separate carefully the bottom from the fixture 8. Pick the module by a nozzle and place in the right position on the board 9. Reflow the solder. Inspection 10.7 Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability. Component Salvage 10.8 If it is intended to send a defect PAN1322 module back to the supplier for failure analysis, please note that during the removal of this component no further defects must be introduced to the device, because this may hinder the failure analysis at the supplier. This includes ESD precautions, not to apply high mechanical force for component removal, and to prevent excess moisture content in the package during salvage (risk of pop corning failures). Therefore if the maximum storage time out of the dry pack (see label on packing material) is exceeded after board assembly, the PCB has to be dried 24h at 125C before soldering off the defect component, because otherwise too much moisture may have been accumulated. Users Manual Hardware Description 43 Revision 1.3, 2013-08-14
10.9 Voids in the Solder Joints PAN1322-SPP ENW89841A3KF Assembly Guidelines Expected Void Content and Reliability 10.9.1 The content of voids is larger on LGA modules than for modules with BGA or leads. At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air. The void content of the PAN1322 module conforms to IPC-A-610D (25% or less voiding area/area). Figure 20 shows an example of void-content at a module assembled at production site. Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly. Figure 20 X-ray Picture Showing Voids Conforming to IPC-A-610D Voids _IPC _A_ 610D .v s d 10.9.2 If the void content has to be reduced following parameters have an impact. Parameters with an Impact on Voiding Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding. Flux will get entrapped on oxidized surfaces. In general, Ni/Au pads show fewer voids than HASL and OSP. Solder paste Higher activity of the flux will remove oxide rapidly and less flux will get entrapped. Voiding increases with increasing solder paste exposure time, since long exposure time will result in more oxidation and moisture pickup. Pad size A large soldering pad means that the outgassing flux has a longer way to the surface of the solder, and will thereby create more voids. Solder paste Smaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding. Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder. Users Manual Hardware Description 44 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF Assembly Guidelines Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder. Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids. Too long reflow time gives larger voids Too short reflow time gives a fraction of voids Users Manual Hardware Description 45 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Terminology
11 A ACK ACL AFH AHS ARQ B b B BALUN BD_ADDR BER BMU BOM BT BW C CMOS COD CODEC CPU CQDDR CRC CTS CVSD CDCT CQDDR D DC DDC DM DMA DH DPSK DQPSK DSP DUT Terminology Acknowledgement Asynchronous Connection-oriented (logical transport) Adaptive Frequency Hopping Adaptive Hop Sequence Automatic Repeat reQuest bit/bits (e.g. kb/s) Byte/Bytes (e.g. kB/s) BALanced UNbalanced Bluetooth Device Address Bit Error Rate BlueMoon Universal Bill Of Material Bluetooth Bandwidth Complementary Metal Oxide Semiconductor Class Of Device COder/DECoder Central Processing Unit Channel Quality Driven Data Rate Cyclic Redundancy Check Clear To Send (UART flow control signal) Continuous Variable Slope Delta (modulation) Clock Drift Compensation Task Channel Quality Driven Data Rate Direct Current Device Data Control Data Medium-Rate (packet type) Direct Memory Access Data High-Rate (packet type) Differential Phase Shift Keying (modulation) Differential Quaternary Phase Shift Keying (modulation) Digital Signal Processor Device Under Test Users Manual Hardware Description 46 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Terminology
E EDR EEPROM eSCO EV F FEC FHS FIFO FM FW G GFSK GPIO GSM H HCI HCI+
HEC HV HW I I2C I2S IAC ID IEEE IF ISM J JTAG L LAN LAP LM LMP LNA LO LPM LPO Enhanced Data Rate Electrically Erasable Programmable Read Only Memory Extended Synchronous Connection-Oriented (logical transport) Extended Voice (packet type) Forward Error Correction Frequency Hop Synchronization (packet) First In First Out (buffer) Frequency Modulation Firmware Gaussian Frequency Shift Keying (modulation) General Purpose Input/Output Global System for Mobile communication Host Controller Interface Infineon Specific HCI command set Header Error Check High quality Voice (packet type) Hardware Inter-IC Control (bus) Inter-IC Sound (bus) Inquiry Access Code IDentifier Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific & Medical (frequency band) Joint Test Action Group Local Area Network Lower Address Part Link Manager Link Manager Protocol Low Noise Amplifier Local Oscillator Low Power Mode(s) Low Power Oscillator Users Manual Hardware Description 47 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Terminology
LSB LT_ADDR M MSB MSRS N NC NOP NVM O OCF OGF P PA PCB PCM PDU PER PIN PLC PLL PMU POR PTA PTT Q QoS R RAM RF ROM RSSI RTS RX RXD S SCO SIG SW SYRI Least Significant Bit/Byte Logical Transport Address Most Significant Bit/Byte Master-Slave Role Switch No Connection No OPeration Non-Volatile Memory Opcode Command Field Opcode Group Field Power Amplifier Printed Circuit Board Pulse Coded Modulation Protocol Data Unit Packet Error Rate Personal Identification Number Packet Loss Concealment Phase Locked Loop Power Management Unit Power-On Reset Packet Traffic Arbitration Packet Type Table Quality Of Service Random Access Memory Radio Frequency Read Only Memory Received Signal Strength Indication Request To Send (UART flow control signal) Receive Receive Data (UART signal) Synchronous Connection-Oriented (logical transport) Special Interest Group (Bluetooth SIG) Software Synthesizer Reference Input Users Manual Hardware Description 48 Revision 1.3, 2013-08-14 PAN1322-SPP ENW89841A3KF Terminology
T TBD TCK TDI TDO TL TMS TX TXD U UART ULPM V VCO W WLAN To Be Determined Test Clock (JTAG signal) Test Data In (JTAG signal) Test Data Out (JTAG signal) Transport Layer Test Mode Select (JTAG signal) Transmit Transmit Data (UART signal) Universal Asynchronous Receiver & Transmitter Ultra Low Power Mode Voltage Controlled Oscillator Wireless LAN (Local Area Network) Users Manual Hardware Description 49 Revision 1.3, 2013-08-14
12
[1]
References Intel AT Command Specification
(eUniStone_1.00_UM_SD.pdf) Always the latest revisionwill be available under the link below
(SPP-AT Users Manual) PAN1322-SPP ENW89841A3KF References
[2] Release Notes for SPP AT application Software (SW)
(eUniStone_1.00_SW_3.1_RN.pdf) Always the latest revision will be available under the link below, please refer also to Table 2 Firmware Releases as of 2013-05-14 on Page 14.
(SPP-AT Release Notes)
[3] PAN1322 Application Note Design Guide Always the latest revision, as a pdf file, will be available under the link below
(PAN1322 Application Note Design Guide)
[4] PAN1322-SPP Users Manual (Data Sheet) It is this document. Always the latest revision, as a pdf file, will be available under the link below
(PAN1322-SPP Data Sheet) Users Manual Hardware Description 50 Revision 1.3, 2013-08-14
PAN1322-SPP ENW89841A3KF References Users Manual Hardware Description 51 Revision 1.3, 2013-08-14 w w w . p i d e u . p a n a s o n i c . d e Published by Panasonic Industrial Devices Europe GmbH
1 2 3 4 5 | IntPho | Internal Photos | 51.87 KiB | April 16 2014 |
Internal Photos Model No.:PAN1322 FCC ID: T7VEBMU page 1 Test Report No.: G0M-1311-3395-TFC247BT-V01 Eurofins Product Service GmbH Storkower Str. 38C, D-15526 Reichenwalde, Germany
1 2 3 4 5 | ExtPho | External Photos | 78.60 KiB | April 16 2014 |
External Photos Model No.:PAN1322 FCC ID: T7VEBMU page 1 Test Report No.: G0M-1311-3395-TFC247BT-V01 Eurofins Product Service GmbH Storkower Str. 38C, D-15526 Reichenwalde, Germany
1 2 3 4 5 | 06 07 LabelSampel Location | ID Label/Location Info | 71.25 KiB | January 29 2016 |
Label Sample - Location Model No.: PAN1320 FCC ID: T7VEBMU IC: 216Q-EBMU page 1 Project No.: G0M-1506-4866
1 2 3 4 5 | LabelSmpl | ID Label/Location Info | 346.32 KiB | April 16 2014 |
m m 0 7 8
, 15,60mm Original Module Size The above picture shows the full module with the case, the laser marking is made moreless on the hole case.
1 2 3 4 5 | 04 PAN1320 AuthLet | Attestation Statements | 323.71 KiB | January 29 2016 |
Panasonic PANASONIC INDUSTRIAL DEVICES EUROPE GmbH Telefon +49 (0) 4131 899-0 ZeppelinstraRe 19, 21337 Luiineburg Telefax +49 (0) 4131 899-120 E-Mail: pideu@eu.panasonic.com www.pideu.panasonic.de Federal Communications Commission Authorization and Evaluation Division Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 11/10/2015 To whom it may concern:
We, the undersigned, hereby authorize Eurofins Product Service GmbH to act on our behalf in all matters relating to applications for equipment authorization FCC ID: T7VEBMU including the signing of all documents related to these matters. Any and all acts carried out by Eurofins Product Service GmbH on our behalf shall have the same effect as acts of our own. We also hereby certify that no party to this application is subject to a denial of benefits, including FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 862. Sincerely, Yo) CW a Signature Name Olaf Knoth Title Product Safety Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 21337 Lueneburg
1 2 3 4 5 | 05 PAN1320 ConReq | Cover Letter(s) | 412.52 KiB | January 29 2016 |
Panasonic PANASONIC INDUSTRIAL DEVICES EUROPE GmbH Telefon +49 (0) 4131 899-0 ZeppelinstraRe 19, 21337 Luneburg Telefax +49 (0) 4131 899-120 E-Mail: pideu@eu.panasonic.com www.pideu.panasonic.de Federal Communications Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 11/10/2015 Request for Confidentiality Company name: Panasonic Industrial Devices Europe GmbH FCC ID: T7VEBMU FCC Part 15 Certification Gentlemen, In accordance with CFR 47 0.457 and CFR 47 0.459 Panasonic Industrial Devices Europe GmbH hereby requests confidentiality of following attachments:
(1) schematic diagrams,
(2) detailed block diagrams,
(3) detailed operational descriptions,
(4) parts lists. These documents contain detailed system and equipment description and related information about the product which Panasonic Industrial Devices Europe GmbH considers to be proprietary, confidential and a custom design and otherwise would not release to the general public. Since the design is a basis from which future technological products will evolve, Panasonic Industrial Devices Europe GmbH considers that this information would be of benefit to its competitors and that the disclosure of the information in these documents would give competitors an unfair advantage in the market. Sincerely,
Signature Name Olaf Knoth Title Product Safety Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 21337 Lueneburg
1 2 3 4 5 | 17a PAN1320 AntSpec | Operational Description | 358.70 KiB | January 29 2016 |
Service GmbH v.0.2 Provided by Eurofins Product Panasonic PANASONIC INDUSTRIAL DEVICES EUROPE GmbH Telefon +49 (0) 4131 899-0 ZeppelinstraRe 19, 21337 Luneburg Telefax +49 (0) 4131 899-120 E-Mail: pideu@eu.panasonic.com www.pideu.panasonic.de Declaration concerning Antenna Specification It is hereby declared that the product Model No.: PAN1320 FCC ID: T/7VEBMU fulfils the requirement in FCC test relating to the antenna type. The device specified above confirms to the FCC recommendations for internal antenna type described below:
Model No. of antenna: 2450AT43B100 Type of antenna: SMD Gain of the antenna: 1.3 dBi Frequency range: 2.4 - 2.5 MHz How to mount the external antenna type together with the PAN1320 are described in the user manual description, in other words the customer has to follow the tested reference design. Any other antenna with the same type and less or equal maximum antenna gain of 1.3 dBi are allowed to use. Company name: Panasonic Industrial Devices Europe GmbH Address: Zeppelinstrasse 19 City: Lueneburg ZIP / Postal code: 21337 Country: Germany Place: Lueneburg Date: 11/10/2015 Signature: C Sitz Luneburg I Registergericht: Amtsgericht Luneburg, Abt. B Nr. 839 1 Geschaftsftihrer: Udo Bachsmann
1 2 3 4 5 | 17b PAN1320 Antenna Description | Operational Description | 522.69 KiB | January 29 2016 |
"High Frequency Ceramic Solutions"
2.4 GHz WLAN, Home RF, Bluetooth Antenna NEW with Ground Clearance Requirements Minimized Detail Specification: 09/04/08 P/N 2450AT43B100 Page 1 of 4 General Specifications Part Number Frequency Range Peak Gain Average Gain Return Loss 2450AT43B100 2400 - 2500 Mhz 1.3 dBi typ. (XZ-V)
-0.5 dBi typ. (XZ-V) 9.5 dB min. Input Power Impedance Reel Quanity Operating Temperature Storage Temperature 2W max. 50 1,000
-40 to +85C
+5 to +35C, Humidity:
45-75%RH, 12 mos. Max Packaging Style P/N Suffix Termination Style Bulk T & R 100% Tin Tin / Lead Eg. 2450AT43B100S Eg. 2450AT43B100E Suffix = S Suffix = E Suffix = None Eg. 2450AT43B100(E or S) Please consult Factory Function Feed Point Terminal Configuration No. 1 2 3 4 NC NC NC Mechanical Dimensions L W L1 W1 T a 0.276 0.079 0.102 0.020 0.079 0.020 0.008 0.008 0.008 0.008 In
+.004/-.008 0.012 7.00 2.00 2.60 0.50 2.00 0.50 0.20 0.20 0.20 0.20 mm
+0.1/-0.2 0.30 2 3 4 1 L L1 W1 W a T Johanson Technology, Inc. reserves the right to make design changes without notice. All sales are subject to Johanson Technology, Inc. terms and conditions. www.johansontechnology.com 4001 Calle Tecate Camarillo, CA 93012 TEL 805.389.1166 FAX 805.389.1821 2008 Johanson Technology, Inc. All Rights Reserved
"High Frequency Ceramic Solutions"
2.4 GHz WLAN, Home RF, Bluetooth Antenna Detail Specification: 09/04/08 P/N 2450AT43B100 Page 2 of 4 Mounting Considerations Mount these devices with brown mark facing up. Units: mm Line width should be designed to provide 50 impedance matching characteristics.
* Note: Pins 3 & 4, although "NC", must be soldered to its PCB pads for proper electrical operation With Matching Circuits 1 1.6 2 4.87 1.6 1 1 2.2 2.7 nH 2 2 2.8 0.8 0.83 0.8 1.8 3 10
(Matching circuit and component values will be different, depending on PCB layout) JTI P/N for Matching Circuit:
Inductor (2.2nH): L-07C2N2SV6T Inductor (2.7nH): L-07C2N7SV6T
) www.johansontechnology.com 4001 Calle Tecate Camarillo, CA 93012 TEL 805.389.1166 FAX 805.389.1821 2008 Johanson Technology, Inc. All Rights Reserved
"High Frequency Ceramic Solutions"
2.4 GHz WLAN, Home RF, Bluetooth Antenna Detail Specification: 09/04/08 P/N 2450AT43B100 Page 3 of 4 Typical Electrical Characteristics (T=25oC) Test Board:
) 20 Return Loss With Matching Circuit
) Ground 10 4.87 Antenna No Ground 40
) Johanson Technology, Inc. reserves the right to make design changes without notice. All sales are subject to Johanson Technology, Inc. terms and conditions. www.johansontechnology.com 4001 Calle Tecate Camarillo, CA 93012 TEL 805.389.1166 FAX 805.389.1821 2008 Johanson Technology, Inc. All Rights Reserved
"High Frequency Ceramic Solutions"
2.4 GHz WLAN, Home RF, Bluetooth Antenna Detail Specification: 09/04/08 P/N 2450AT43B100 Page 4 of 4 Typical Radiation Patterns
) XY-V/XY-H
) Z XY cut @2.45GHz Vertical Horizontal
) 180
) 90 90 90 X 270 Y 0 XY-cut scanning direction XZ-V/XZ-H Y 180 XZ cut @2.45GHz Vertical Horizontal X 270 Z 0 XZ-cut scanning direction YZ-V/YZ-H X 180
) YZ cut @2.45GHz Vertical Horizontal Y 270 Z 0 YZ-cut scanning direction Johanson Technology, Inc. reserves the right to make design changes without notice. All sales are subject to Johanson Technology, Inc. terms and conditions. www.johansontechnology.com 4001 Calle Tecate Camarillo, CA 93012 TEL 805.389.1166 FAX 805.389.1821 2008 Johanson Technology, Inc. All Rights Reserved
1 2 3 4 5 | 30 PAN1320 ChLet Rev01 | Cover Letter(s) | 312.22 KiB | January 29 2016 |
Panasonic PANASONIC INDUSTRIAL DEVICES EUROPE GmbH Telefon +49 (0) 4131 899-0 ZeppelinstraRe 19, 21337 Liineburg Telefax +49 (0) 4131 899-120 E-Mail: pideu@eu.panasonic.com www.pideu.panasonic.de Date 10/05/2015 Federal Communications Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 Request of Class II Permissive Change Company name: Panasonic Industrial Devices Europe GmbH FCC ID: T7VEBMU FCC Part 15 Certification Gentlemen, This is to request a Class II Permissive Change for FCC ID: T7VEBMU originally granted on 01/10/2010 The major change filed under application is:
Change 1: EEPROM Change 2: PCB (Footprint of the EEPROM) If you have any questions regarding this application, please feel free to contact Contactname Olaf Knoth Company name Panasonic Industrial Devices Europe GmbH Phone No.: 04131899257 Sincerely, 7 hom aes, Signature Olaf Knoth Product Safety Panasonic Industrial Devices Europe GmbH
1 2 3 4 5 | AutLet | Cover Letter(s) | 317.56 KiB | April 16 2014 |
Panasonic Federal Communications Commission Authorization and Evaluation Division Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 3/24/2014 To whom it may concern:
We, the undersigned, hereby authorize Eurofins Product Service GmbH to act on our behalf in all matters relating to applications for equipment authorization FCC ID: T7VEBMU including the signing of all documents related to these matters. Any and all acts carried out by Eurofins Product Service GmbH on our behalf shall have the same effect as acts of our own. We also hereby certify that no party to this application is subject to a denial of benefits, including FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 862. Sincerely, Signature
[Olaf Knoth]
[Product Safety]
[Panasonic Industrial Devices Europe GmbH]
Sitz Lineburg - Registergericht: Amtsgericht Luneburg, Abt. B Nr. 839 - Geschaftsfilhrer: Udo Bachsmann
1 2 3 4 5 | CIIPChLetter | Cover Letter(s) | 305.01 KiB | April 16 2014 |
Panasonic Date 21.03.2014 Federal Communications Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 Request of Class II Permissive Change Company name Panasonic Industrial Devices Europe GmbH FCC ID: T7VEBMU FCC Part 15 Certification Gentlemen, This is to request a Class II Permissive Change for FCC ID: T7VEBMU originally granted on Panasonic Electronic Devices Europe GmbH The major change filed under application is:
Change 1: Antenna Change 2: Matching Change 3 :Component supplier If you have any questions regarding this application, please feel free to contact Contact name _ Olaf Knoth Company name Panasonic Industrial Devices Europe GmbH Phone No.:: +49 4131 899 257 Sincerely, or . a Zi _ Oo Signature Olaf Knoth Product Safety Panasonic Industrial Devices Europe GmbH Sitz Luneburg - Registergericht: Amtsgericht Luneburg, Abt. B Nr. 839 - Geschaftsfiihrer: Udo Bachsmann
1 2 3 4 5 | ConReq | Cover Letter(s) | 396.61 KiB | April 16 2014 |
Panasonic Federal Communications Commission Equipment Authorization Branch 7435 Oakland Mills Road Columbia, MD 21046 3/24/2014 Request for Confidentiality Company name: Panasonic Industrial Devices Europe GmbH FCC ID: T7VEBMU FCC Part 15 Certification Gentlemen, In accordance with CFR 47 0.457 and CFR 47 0.459 Panasonic Industrial Devices Europe GmbH hereby requests confidentiality of following attachments:
(1) schematic diagrams,
(2) detailed block diagrams,
(3) detailed operational descriptions,
(4) parts lists. These documents contain detailed system and equipment description and related information about the product which Panasonic Industrial Devices Europe GmbH considers to be proprietary, confidential and a custom design and otherwise would not release to the general public. Since the design is a basis from which future technological products will evolve, Panasonic Industrial Devices Europe GmbH considers that this information would be of benefit to its competitors and that the disclosure of the information in these documents would give competitors an unfair advantage in the market. Sincerely, Signature
[Olaf Knoth]
[Product Safety]
Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 21337 Lueneburg Sitz Luneburg - Registergericht: Amtsgericht Liineburg, Abt. B Nr. 839 - Geschaftsfilhrer: Udo Bachsmann
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2016-01-29 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Class II Permissive Change |
2 | 2014-04-16 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | |
3 | 2009-10-16 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | |
4 | 2009-02-26 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | |
5 | 2009-02-23 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Change in Identification |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 3 4 5 | Effective |
2016-01-29
|
||||
1 2 3 4 5 |
2014-04-16
|
|||||
1 2 3 4 5 |
2009-10-16
|
|||||
1 2 3 4 5 |
2009-02-26
|
|||||
1 2 3 4 5 |
2009-02-23
|
|||||
1 2 3 4 5 | Applicant's complete, legal business name |
Panasonic Industrial Devices Europe GmbH
|
||||
1 2 3 4 5 | FCC Registration Number (FRN) |
0014980072
|
||||
1 2 3 4 5 | Physical Address |
Zeppelinstrasse 19
|
||||
1 2 3 4 5 |
Lueneburg
|
|||||
1 2 3 4 5 |
Lueneburg, N/A
|
|||||
1 2 3 4 5 |
Germany
|
|||||
app s | TCB Information | |||||
1 2 3 4 5 | TCB Application Email Address |
j******@eurofins.de
|
||||
1 2 3 4 5 |
j******@eurofins.de
|
|||||
1 2 3 4 5 |
J******@eurofins.de
|
|||||
1 2 3 4 5 |
T******@Intertek.com
|
|||||
1 2 3 4 5 |
T******@intertek.com
|
|||||
1 2 3 4 5 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 3 4 5 | Grantee Code |
T7V
|
||||
1 2 3 4 5 | Equipment Product Code |
EBMU
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 3 4 5 | Name |
O**** K******
|
||||
1 2 3 4 5 | Title |
Product Safety
|
||||
1 2 3 4 5 | Telephone Number |
+49-4******** Extension:
|
||||
1 2 3 4 5 | Fax Number |
+49-4********
|
||||
1 2 3 4 5 |
o******@eu.panasonic.com
|
|||||
app s | Technical Contact | |||||
1 2 3 4 5 | Firm Name |
Panasonic Industrial Devices Europe GmbH
|
||||
1 2 3 4 5 |
Panasonic Electronic Devices Europe GmbH
|
|||||
1 2 3 4 5 | Name |
I**** K****
|
||||
1 2 3 4 5 |
H****** K****
|
|||||
1 2 3 4 5 | Physical Address |
Zeppelinstrasse 19
|
||||
1 2 3 4 5 |
Lueneburg, 21337
|
|||||
1 2 3 4 5 |
Germany
|
|||||
1 2 3 4 5 | Telephone Number |
00413******** Extension:
|
||||
1 2 3 4 5 |
+49 4********
|
|||||
1 2 3 4 5 |
49 41********
|
|||||
1 2 3 4 5 | Fax Number |
+49 4********
|
||||
1 2 3 4 5 |
49 41********
|
|||||
1 2 3 4 5 |
I******@eu.panasonic.com
|
|||||
1 2 3 4 5 |
H******@eu.panasonic.com
|
|||||
app s | Non Technical Contact | |||||
1 2 3 4 5 | Firm Name |
Panasonic Electronic Devices Europe GmbH
|
||||
1 2 3 4 5 | Name |
H****** K******
|
||||
1 2 3 4 5 | Physical Address |
Zeppelinstrasse 19
|
||||
1 2 3 4 5 |
Lueneburg, 21337
|
|||||
1 2 3 4 5 |
Germany
|
|||||
1 2 3 4 5 | Telephone Number |
+49 4********
|
||||
1 2 3 4 5 |
49 41********
|
|||||
1 2 3 4 5 | Fax Number |
+49 4********
|
||||
1 2 3 4 5 |
49 41********
|
|||||
1 2 3 4 5 |
H******@eu.panasonic.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 2 3 4 5 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 3 4 5 | No | |||||
1 2 3 4 5 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 3 4 5 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 3 4 5 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
1 2 3 4 5 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Bluetooth Module | ||||
1 2 3 4 5 | Bluetooth EDR Module | |||||
1 2 3 4 5 | PAN1321 Bluetooth module | |||||
1 2 3 4 5 | PAN1311 Bluetooth module | |||||
1 2 3 4 5 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 3 4 5 | Modular Equipment Type | Does not apply | ||||
1 2 3 4 5 | Single Modular Approval | |||||
1 2 3 4 5 | Purpose / Application is for | Class II Permissive Change | ||||
1 2 3 4 5 | Change in Identification | |||||
1 2 3 4 5 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 2 3 4 5 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 3 4 5 | Grant Comments | Power Output listed is conducted. Single Modular Approval. The antenna(s) used for this device must be used in accordance with FCC multi-transmitter product procedures. This module is approved in mobile/portable configurations. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. Grantee must coordinate with OEM integrator to determine applicable host configurations to ensure RF exposure compliance, including simultaneous transmission SAR requirements according to published KDB 616217 or KDB 447498. When all conditions of this filing cannot be met installation of this device into specific final products may require the submission of a permissive change application, containing appropriate data demonstrating compliance, or a new application. OEM/Host integrator must be provided with antenna installation instructions and transmitter operating conditions to satisfy RF exposure compliance. OEM/Host integrator is responsible for complying with the instructions and requirements for each transmitter they choose to integrate into a host product. | ||||
1 2 3 4 5 | Modular Approval. Power Output is Conducted. Approval is limited to OEM installation only. The antenna used for this transmitter must not be co-located with any other antenna or transmitter within a host device, except in accordance with FCC multi-transmitter product procedures. OEM integrators and End-Users must be provided with transmitter operation conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device. | |||||
1 2 3 4 5 | Modular Approval. Power Output is Conducted. Measured EIRP is 2.4 mW with antenna as documented in this Permissive Change. Approval is limited to OEM installation only. The antenna used for this transmitter must not be co-located with any other antenna or transmitter within a host device, except in accordance with FCC multi-transmitter product procedures. OEM integrators and End-Users must be provided with transmitter operation conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device. | |||||
1 2 3 4 5 | Modular Approval. Power Output is Conducted. Measured EIRP is 0.35 mW with antenna as documented in this Permissive Change. Approval is limited to OEM installation only. The antenna used for this transmitter must not be co-located with any other antenna or transmitter within a host device, except in accordance with FCC multi-transmitter product procedures. OEM integrators and End-Users must be provided with transmitter operation conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device. | |||||
1 2 3 4 5 | Modular Approval. Power Output is Conducted. Approval is limited to OEM installation only. The only antenna approved for use with this module is documented in the filing, and must be installed in the manner specified therein. The antenna(s) must not be co-located or operating in conjunction with any other antenna or transmitter. OEM integrators must be provided with antenna installation instructions. OEM integrators and End-Users must be provided with transmitter operation conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device. | |||||
1 2 3 4 5 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 3 4 5 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 3 4 5 | Firm Name |
Eurofins Product Service GmbH
|
||||
1 2 3 4 5 |
DEKRA Testing and Certification, S.A.U.
|
|||||
1 2 3 4 5 | Name |
R**** K******
|
||||
1 2 3 4 5 |
J****** K********
|
|||||
1 2 3 4 5 |
F**** C********
|
|||||
1 2 3 4 5 | Telephone Number |
49-33********
|
||||
1 2 3 4 5 |
49-33********
|
|||||
1 2 3 4 5 |
34-95********
|
|||||
1 2 3 4 5 | Fax Number |
49-33********
|
||||
1 2 3 4 5 |
49-33********
|
|||||
1 2 3 4 5 |
34-95********
|
|||||
1 2 3 4 5 |
r******@eurofins.de
|
|||||
1 2 3 4 5 |
j******@eurofins.de
|
|||||
1 2 3 4 5 |
f******@dekra.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0020000 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0012200 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
3 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0012200 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
4 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0012200 | ||||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
5 | 1 | 15C | 2402.00000000 | 2480.00000000 | 0.0012200 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC