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Users Guide 1709411, 1709412 Wireless Retro Handset For Your Smartphone Outfitting your mobile life. 1709411_412_UG_EN.indd 1-6 Package Contents Wireless Retro Handset Micro USB Charging Cable Neck and Wrist Lanyards Users Guide Features Miniature size and retro-styling meet the convenience of modern technology Wireless Bluetooth connection means you can leave your smartphone in your purse or pocket Go ahead and multitaskyour other phone functions are still accessible during a call Attaching a Lanyard (Optional) You can use either of the supplied lanyards to carry your handset. Charging Your Handset Use the supplied charging cable to connect the handset to a USB port or a USB charger (not included). LED Pairing Your Handset 1. Press and hold the Multifunction button for 2 seconds to turn on the handset. While searching for Bluetooth devices, the LED flashes blue and red. When the battery is low, the LED flashes red and the handset beeps every 20 seconds. While charging, the LED lights red, but may flash blue to indicate the Bluetooth status. Multifunction Button 2. Activate your phones Bluetooth function
(refer to the phone users guide). 3. When PointMobl Mini Phone appear, select it. When paired, the LED flashes blue every three seconds. n Note:
If prompted for a PIN, enter 0000. The handset automatically turns off if no phone is connected for 10 minutes. Using Your Handset To use the Multifunction button:
Power on Press and hold for 2 seconds. Answer or end a call Press once. Reject a call Press and hold for 2 seconds. Answer a second call Press and hold for 2 seconds to place the current call on hold and answer the second call. Redial Press twice quickly. This redials the last call dialed from the phone. Turn off the handset Press and hold for 5 seconds. When turned on, the handset automatically connects to the most recently paired phone. If that phone is not available, it will search for other phones. If the connected phone moves too far away from the handset, the handset disconnects from the device but resumes connection when the device is detected within 5 minutes. Changing Phones To change phones, you must first disconnect the first phone. X 1. Press and hold the Multifunction button for 5 seconds to turn off the handset. 2. Press and hold the Multifunction again until the LED flashes red and blue. If you release the button before the LED flashes red and blue, the handset will automatically connect to the first smartphone. 3. When PointMobl Mini Phone appears in the list of devices on the second phone, select it. When paired, the LED flashes blue every three seconds. n Note: If the handset malfunctions, reset it by pressing the Multifunction button twice quickly when the LED flashes blue and red. 2 3 4 5 6 10/7/2013 5:16:00 PM Specifications Power Input ......................................5V DC, 500mA Charging Time ..........................................1.5 hours Operating Time ............................................5 hours Bluetooth Protocol ........................................... V3.0 Operating Distance .............................. 33 ft. (10m) Handset Weight .................................. 0.88 oz (25g) Specifications are subject to change and improvement without notice. Actual product may vary from the images found in this document. FCC Information This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Limited Warranty Ignition L.P. warrants this product against defects in materials and workmanship under normal use by the original purchaser for ninety (90) days after the date of purchase. IGNITION L.P. MAKES NO OTHER EXPRESS WARRANTIES. This warranty does not cover: (a) damage or failure caused by or attributable to abuse, misuse, failure to follow instructions, improper installation or maintenance, alteration, accident, Acts of God
(such as floods or lightning), or excess voltage or current; (b) improper or incorrectly performed repairs by persons who are not a Ignition L.P. Authorized Service Facility; (c) consumables such as fuses or batteries; (d) ordinary wear and tear or cosmetic damage; (e) transportation, shipping or insurance costs; (f) costs of product removal, installation, set-up service, adjustment or reinstallation; and (g) claims by persons other than the original purchaser. Should a problem occur that is covered by this warranty, take the product and the sales receipt as proof of purchase date to the place of purchase. Ignition L.P. will, at its option, unless otherwise provided by law: (a) repair the product without charge for parts and labor; (b) replace the product with the same or a comparable product; or (c) refund the purchase price. All replaced parts and products, and products on which a refund is made, become the property of Ignition L.P. New or reconditioned parts and products may be used in the performance of warranty service. Repaired or replaced parts and products are warranted for the remainder of the original warranty period. You will be charged for repair or replacement of the product made after the expiration of the warranty period. IGNITION L.P. EXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS NOT STATED IN THIS LIMITED WARRANTY. ANY IMPLIED WARRANTIES THAT MAY BE IMPOSED BY LAW, INCLUDING THE IMPLIED WARRANTY OF MERCHANTABILITY AND, IF APPLICABLE, THE IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE, SHALL EXPIRE ON THE EXPIRATION OF THE STATED WARRANTY PERIOD. EXCEPT AS DESCRIBED ABOVE, IGNITION L.P. SHALL HAVE NO LIABILITY OR RESPONSIBILITY TO THE PURCHASER OF THE PRODUCT OR ANY OTHER PERSON OR ENTITY WITH RESPECT TO ANY LIABILITY, LOSS OR DAMAGE CAUSED DIRECTLY OR INDIRECTLY BY USE OR PERFORMANCE OF THE PRODUCT OR ARISING OUT OF ANY BREACH OF THIS WARRANTY, INCLUDING, BUT NOT LIMITED TO, ANY DAMAGES RESULTING FROM INCONVENIENCE AND ANY LOSS OF TIME, DATA, PROPERTY, REVENUE, OR PROFIT AND ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, EVEN IF IGNITION L.P. HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Some states do not allow limitations on how long an implied warranty lasts or the exclusion or limitation of incidental or consequential damages, so the above limitations or exclusions may not apply to you. This warranty gives you specific legal rights, and you may also have other rights which vary from state to state. You may contact Ignition L.P. at: Ignition L.P., 3102 Maple Ave., Suite 450, Dallas, TX 75201 02/09 For product support, call 1-866-315-0426 Complies with the European Unions Restriction of Hazardous Substances Directive, which protects the environment by restricting specific hazardous materials and products. The Bluetooth word mark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by Ignition L.P. is under license. Other trademarks and trade names are those of their respective owners. 2013. Ignition L.P. All rights reserved. PointMobl is a registered trademark used by Ignition L.P. 10A13 1709411, 1709412 Printed in China 7 8 9 10 11 12 1709411_412_UG_EN.indd 7-12 10/7/2013 5:16:00 PM
1 | Label Artwork and Location | ID Label/Location Info | 367.76 KiB |
1709411 China 10A13 1709411 White China 10A13 100%
TITLE:
P/N:
1709411 printing Protop International Inc. A UNLESS OTHERWISE SPECIFICATION TOLERANCES ARE:
APPROVAL DATE DWN. JACK 2013/09/23 DRAW NO:
1709411_printing_A0_20130923 SCALE:
1: 1 UNIT:
mm
. 0.5
.x 0.2
.xx 0.1
.xxx 0.05 ANGLES 0.5 A0 REV.:
RDD-P-001-6A MATERIAL:
THIRD ANGLE PROJECTION 3 CHK. APP. 4
1 | Letter of Agency | Cover Letter(s) | 25.81 KiB |
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1 | Technical Description | Operational Description | 1.67 MiB |
Technical Description:
The brief circuit description is listed as follows:
U4 and associated circuit act as Bluetooth module
-U1 acts as Bluetooth Transceiver
-U2 acts as Multilayer Balanced Band Pass Filter
-U3 act as 2-Wire Serial EEPROM An internal, integral antenna has been used. Antenna Gain: 0dBi Nominal rated field strength: 100.9dBV/m at 3m Maximum allowed field strength of production tolerance: +/- 3dB F-3098 Module Specification Module Description Using the latest CSR BC6 chip, sound quality and overall RF performance improved significantly Supports two phones simultaneously connected Comply with Bluetooth V3.0 Bluetooth headsets, speakers, car accessories, low-cost solution Module size: L23.5 x W15.5 x H1.8 mm Transmit power up to 8.5dB,-91dB Receiver Sensitivity High quality audio processor A2DP V1.2 Supports HSP V1.2, HFP V1.5 Applications High-quality Bluetooth headset Car Hands free Bluetooth High quality Bluetooth audio Module size and pin diagram Performance Parameters Model F-3098 Bluetooth Specification Bluetooth V3.0 Modulation Mode Supply voltage GFSK, 1Mbps, 0.5BT Gaussian Battery voltage VDD:3.3Vdc supply Supply Bluetooth Agreement Operating current Standby Current Temperature Range A2DP,HSP,HFP 30mA
<0.4mA
-40 to +80 Wireless transmission range 10 meter Transmission power CLASS 24dBm Sensitivity Frequency Range External Interface Audio Performance Audio SNR Distortion
-91 dBm @ 0.1% BER 2.4GHz-2.48GHz PIO, SPI, Speaker , microphone High acoustic fidelity sound 75dB 0.01%
Pin Function Description:
PIN NO. NAME TYPE FUNCTION 1 2 3 4 5 6 GND2 AIO1 AIO1 GND Ground connections Bidirectional Programmable input/output line Bidirectional Programmable input/output line PIO20/RX Bidirectional with UART data input, active high. weak PIO[20] is internal pull-down clock for SPI flash interface PIO23/TX Bidirectional with UART data output, active high. weak PIO[23] is internal pull-up data output for SPI flash interface PIO3 Bidirectional with Programmable input/output line programmable PIO[3] is chip select for SPI flash strength interface internal pull-up/down 7 PIO2 Bidirectional with Programmable input/output line 8 PIO1 Bidirectional with Programmable input/output line 9 PIO0 Bidirectional with Programmable input/output line programmable strength internal pull-up/down programmable strength internal pull-up/down programmable strength internal pull-up/down 10 RST Input with weak Reset if low. Input debounced so internal pull-up reset must be low for >5ms to cause a 11 PIO11 Bidirectional with Programmable input/output line. programmable PIO[11] is data input for SPI flash strength internal pull-up/down interface 12 LED1 Open drain output LED driver 13 14 15 16 17 20 21 22 23 24 25 Open drain output LED driver LED0 GND3 GND GND GND Ground connections Ground connections 1V8 Power Positive supply for bluecore POWER_EN Take high to enable both 18 BAT 19 CHG high-voltage regulator and switch-mode regulator Lithium ion/polymer battery positive terminal. Battery charger output and input to switch-mode regulator Lithium ion/polymer battery charger input MIC_BIAS Analogue Microphone bias MIC_P MIC_N Analogue Analogue Microphone input, positive Microphone input, negative SPKR_N Analogue Speaker output, negative SPKR_P Analogue Speaker output, positive MOSI with weak internal SPI data input 26 CLK Bidirectional with SPI clock pull-down weak internal pull-down weak internal pull-down internal pull-down weak GND RF GND 28 MISO Bidirectional with SPI data output 29 30 31 GND1 RF GND0 Ground connections RF GND 27 CSB Bidirectional with Chip select for SPI, active low Note:
large box can not be shielded next to the antenna can not have metal Common end-to-noise inhibition, you need to increase the amplifier or main to be placed near the power modules PAD electrolytic capacitors. front part of the op amp to eliminate interference amplifier module must be grounded well, allowed to exist island or in closed loop, the module grounding Point with the master and the potential difference between the amplifier ground shall not be greater than 1mV. Application Circuit:
Solder reflow temperature Features 6th generation 1-mic CVC audio enhancements A2DP v1.2 for high-quality mono music streaming Supports mSBC wideband speech codec Programmable audio prompts: available from either EEPROM or a low-cost SPI flash Bidirectional noise reduction: Hear and Be Heard Long-tail echo cancellation for low-cost speakerphones and car-kits Low power consumption: over 11 hours talk time from a 120mAhr battery Advanced multipoint support: enables a headset
(HFP) connection to 2 phones for voice Multipoint A2DP streaming: enables a mono headset (A2DP) connection to 2 A2DP source devices for music playback Secure simple pairing, CSR's proximity pairing and CSR's proximity connection 64MIPS Kalimba DSP coprocessor HFP v1.5 and HSP v1.2. Integrated linear and switch-mode regulators 150mA lithium battery charger, with fast charge and external boost charge for a total 240mA High-quality mono codec with 95dB SNR DAC 48-lead 7 x 7 x 0.9mm, 0.5mm pitch QFN, pin compatible with BC6140 QFN and BC6130 QFN Green (RoHS compliant and no antimony or halogenated flame retardants) General Description BlueCore BC6145 QFN is a low-cost fully-featured ROM IC solution for Bluetooth mono headsets with extremely low power consumption. The BC6145 QFN ensures increased speech clarity and improves intelligibility through spectral enhancement, with the bidirectional noise reduction Hear and Be Heard feature. BC6145 QFN reduces the number of external components required, minimising production costs. It includes a Bluetooth radio, baseband, Kalimba DSP, DAC/ADC, switch-mode power supply and battery charger in a QFN package for low-cost designs. The Kalimba DSP coprocessor supports enhanced audio applications. A2DP streaming enables music playback on a mono headset. _`=_`SNQR=nck 1-mic CVC Mono Headset Solution Advanced Echo and Noise Cancellation Fully Qualified Single-chip Bluetooth v3.0 System Production Information BC6145A04 Issue 2 _
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t D a a S h e e t Applications BC6145 QFN DSP mono headset solution Low-cost speakerphones and car-kits BC6145 QFN includes CVC single-microphone echo and noise reduction, which reduces headset echo enabling the headset-user to be heard more clearly. A low-power wind noise reduction feature improves intelligibility in windy environments. BC6145 QFN supports secure simple pairing which simplifies the pairing process and makes it easier to use a Bluetooth headset. The device includes auto-calibration and BIST routines to simplify development, type approval and production test. See CSR Glossary at www.csrsupport.com. XTAL RF IN RF OUT Speaker 1 1 Microphone ROM MCU Kalimba DSP 2.4GHz Radio I/O I2C EEPROM UART PIO SPI Flash RAM Battery Charger CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 1 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Device Details Radio Kalimba DSP Common TX/RX terminal simplifies external matching; eliminates external antenna switch Bluetooth v3.0 specification compliant Transmitter Receiver 8.5dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range typically
>30dB Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch Audio Codec Receiver sensitivity of -91dBm Integrated channel filters Digital demodulator for improved sensitivity and co-
channel rejection Real-time digitised RSSI available on HCI interface Fast AGC for enhanced dynamic range Synthesiser Fully integrated synthesiser requires no external VCO, varactor diode, resonator or loop filter Compatible with crystals 16MHz to 26MHz Baseband and Software Support for Bluetooth v3.0 specification when using updated configuration as described in the BC6145 QFN software release note, see www.csrsupport.com Internal ROM 48KB of internal RAM, enables full-speed data transfer, mixed voice/data and full piconet support Logic for FEC, HEC, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping Transcoders for A-law, -law and linear voice from host and A-law, -law and CVSD voice over air Configurable mono headset ROM software to set-
up headset features and user interface HFP v1.5 and HSP v1.2 Secure simple pairing CSR's proximity pairing (headset-initiated pairing) Supports mSBC wideband speech decoder Advanced multipoint support, enables a headset to connect to 2 mobile phones or 1 mobile phone and a VoIP dongle DSP-based 6th generation 1-mic CVC echo and noise cancellation for effective noise cancellation under all conditions Bidirectional noise reduction ensures increased speech clarity in preparation for improving intelligibility through spectral enhancement for the user and the person they are speaking to Device Details Very low-power Kalimba DSP coprocessor, 64MIPS, 24-bit fixed point core Single-cycle MAC; 24 x 24-bit multiply and 56-bit accumulator Separate program memory and dual data memory Program memory cache when executing from ROM 16-bit resolution mono codec Integrated amplifiers for driving a 16 speaker; no need for external components Support for single-ended speaker termination and line output Integrated low-noise microphone bias Digital enhancements to add bass cut and side tone Analogue enhancements to support single-ended speaker drive capability and reference availability Physical Interfaces Synchronous serial interface for system debugging IC compatible interface communicates with an external EEPROM which contains all of the device configuration (PS Keys) Synchronous serial interface communicates with an external SPI flash device, which can store programmable audio prompts UART interface with data rates up to 3Mbits/s Auxiliary Features BIST minimises production test time Crystal oscillator with built-in digital trimming Device can run in low power modes from an external 32.768kHz clock signal Programmable audio prompts Power management includes digital shutdown, and wake up commands with an integrated low power oscillator for ultra low power Park/Sniff/Hold mode Integrated regulators: 1.5V output from 1.7V to 2.8V input and 1.9V output from 2.7V to 5.5V input Integrated high-efficiency switch-mode regulator;
1.5V output from 2.2V to 4.4V input Power-on-reset cell detects low supply voltage Arbitrary sequencing of power supplies permitted 10-bit ADC Battery charger with programmable current, 20mA to 150mA for lithium ion/polymer battery. Supports external boost charge for up to a total of 240mA fast charge current. 2 LED drivers with faders Package Option 48-lead 7 x 7 x 0.9mm, 0.5mm pitch QFN CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 2 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Functional Block Diagram Bluetooth v3.0 Radio Baseband Basic Rate Modem Enhanced Rate Modem Radio Control Clock Generation Battery Charger IN OUT IN IN Switch-mode Regulator OUT SENSE EN EN High-voltage Regulator OUT SENSE IN EN Low-voltage Regulator OUT SENSE RF_N RF_P VDD_CORE VDD_LO LO_REF XTAL_OUT XTAL_IN VDD_CHG BAT_P VREGENABLE_H LX SMP_SENSE VREGIN_H VREGOUT_H VREGENABLE_L VREGIN_L VDD_ANA VDD_RADIO Bluetooth Modem Memory Management Unit Microcontroller Interrupt Controller System RAM DSP Interrupt Controller Timers MCU Timers Kalimba DSP Data Memory Data Memory DM1 DM2 Program Memory PM Programmable I/O Internal Memory Interface LED Driver AIO GPIO ROM Power Control and Regulation L E D 0
L E D 1
I A O 0
I A O 1
I P O 2 0
Figure : Functional Block Diagram Production Information Cambridge Silicon Radio Limited 2010 This Material is Subject to CSR's Non-disclosure Agreement CS-204118-DSP2 Page 3 of 69 Functional Block Diagram I2C bus interface can only connect to a serial EEPROM SDA SCL PIO[8]
PIO[7]
PIO[6]
S e r i a l I t n e r f a c e s I 2 C I t n e r f a c e U A R T I t n e r f a c e S P I l F a s h I t n e r f a c e S P I I t n e r f a c e i A u d o C o d e c UART_TX/PIO[23]
UART_RX/PIO[20]
SPI_DEBUG_EN PIO[11]
PIO[3]
SPI_MOSI SPI_MISO SPI_CS#
SPI_CLK SPKR_N SPKR_P MIC_BIAS MIC_N MIC_P AU_REF VDD_AUDIO VDD_PADS[0]
VDD_PADS[1]
RST#
TEST_EN 1 1
. 9 9 3 6 0 0 0
W T
G _
S N Q R n c k
t D a a S h e e t Document History Document History Revision Date Change Reason 1 2 04 AUG 10 16 NOV 10 Original publication of this document. Production information added. Ordering information and ROM code updated. ESD information and power consumption updated. Clarification of boost charge current definition and update to example application schematic. Added input decoupling capacitor requirement to high-voltage linear regulator. Minor editorial changes. If you have any comments about this document, email comments@csr.com giving the number, title and section with your feedback. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 4 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Status Information Status Information The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:
Advance Information Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-production Information Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. All electrical specifications may be changed by CSR without notice. Production Information Production Data Sheets supersede all previous document versions. Life Support Policy and Use in Safety-critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. CSR Green Semiconductor Products and RoHS Compliance BC6145 QFN devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). BC6145 QFN devices are also free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products. Trademarks, Patents and Licences Unless otherwise stated, words and logos marked with or are trademarks registered or owned by CSR plc or its affiliates. Bluetooth and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. Refer to www.csrsupport.com for compliance and conformance to standards information. No statements or representations in this document are to be construed as advertising, marketing, or offering for sale in the United States imported covered products subject to the Cease and Desist Order issued by the U.S. International Trade Commission in its Investigation No. 337-TA-602. Such products include SiRFstarIII chips that operate with SiRF software that supports SiRFInstantFix, and/or SiRFLoc servers, or contains SyncFreeNav functionality. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 5 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Contents Contents 1 2 3 4 5 6 7 8 2.1.1 2.2.1 2.2.2 2.5.1 2.5.2 2.3.1 2.3.2 Device Details ................................................................................................................................................. 2 Functional Block Diagram .............................................................................................................................. 3 Package Information ..................................................................................................................................... 10 1.1 Pinout Diagram .................................................................................................................................... 10 1.2 Device Terminal Functions .................................................................................................................. 11 1.3 Package Dimensions ........................................................................................................................... 14 1.4 PCB Design and Assembly Considerations ......................................................................................... 15 1.5 Typical Solder Reflow Profile ............................................................................................................... 15 Bluetooth Modem .......................................................................................................................................... 16 2.1 RF Ports ............................................................................................................................................... 16 RF_N and RF_P ..................................................................................................................... 16 2.2 RF Receiver ......................................................................................................................................... 16 Low Noise Amplifier ............................................................................................................... 16 RSSI Analogue to Digital Converter ....................................................................................... 16 2.3 RF Transmitter ..................................................................................................................................... 17 IQ Modulator .......................................................................................................................... 17 Power Amplifier ...................................................................................................................... 17 2.4 Bluetooth Radio Synthesiser ............................................................................................................... 17 2.5 Baseband ............................................................................................................................................. 17 Burst Mode Controller ............................................................................................................ 17 Physical Layer Hardware Engine ........................................................................................... 17 Clock Generation .......................................................................................................................................... 18 3.1 Clock Architecture ................................................................................................................................ 18 3.2 Input Frequencies and PS Key Settings .............................................................................................. 18 3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT ....................................................................................... 18 Crystal PS Key Settings ......................................................................................................... 19 3.4 External 32kHz Clock .......................................................................................................................... 19 Bluetooth Stack Microcontroller .................................................................................................................... 20 4.1 Programmable I/O Ports ...................................................................................................................... 20 Kalimba DSP ................................................................................................................................................ 21 Memory Interface and Management ............................................................................................................. 22 6.1 Memory Management Unit .................................................................................................................. 22 6.2 System RAM ........................................................................................................................................ 22 6.3 Kalimba DSP RAM .............................................................................................................................. 22 6.4 Internal ROM ....................................................................................................................................... 22 Serial Interfaces ............................................................................................................................................ 23 7.1 UART Interface .................................................................................................................................... 23 UART Configuration While Reset is Active ............................................................................ 24 7.2 Programming and Debug Interface ...................................................................................................... 24 7.2.1 Instruction Cycle ..................................................................................................................... 24 7.2.2 Multi-slave Operation ............................................................................................................. 25 7.3 IC Interface ......................................................................................................................................... 25 7.4 SPI Flash Interface .............................................................................................................................. 25 Audio Interface .............................................................................................................................................. 27 8.1 Audio Input and Output ........................................................................................................................ 27 8.2 Mono Audio Codec Block Diagram ...................................................................................................... 27 8.3 ADC ..................................................................................................................................................... 27 ADC Digital Gain .................................................................................................................... 27 ADC Analogue Gain ............................................................................................................... 28 8.4 DAC ..................................................................................................................................................... 28 8.3.1 8.3.2 3.3.1 7.1.1 CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 6 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Contents 9 10 11 9.9.1 9.9.2 8.4.1 8.4.2 DAC Digital Gain .................................................................................................................... 29 DAC Analogue Gain ............................................................................................................... 29 8.5 Microphone Input ................................................................................................................................. 30 8.6 Line Input ............................................................................................................................................. 31 8.7 Output Stage ........................................................................................................................................ 32 Integrated Digital IIR Filter ................................................................................................................... 32 8.8 8.8.1 Integrated Digital Filter Configuration ..................................................................................... 33 8.9 Side Tone ............................................................................................................................................ 34 Power Control and Regulation ...................................................................................................................... 35 9.1 Power Sequencing ............................................................................................................................... 35 9.2 External Voltage Source ...................................................................................................................... 35 9.3 Switch-mode Regulator ....................................................................................................................... 36 9.4 High-voltage Linear Regulator ............................................................................................................. 36 9.5 Low-voltage Linear Regulator .............................................................................................................. 36 9.6 Voltage Regulator Enable Pins ............................................................................................................ 37 9.7 Battery Charger ................................................................................................................................... 37 9.8 LED Drivers ......................................................................................................................................... 38 9.9 Reset, RST# ........................................................................................................................................ 38 Digital Pin States on Reset .................................................................................................... 39 Status after Reset .................................................................................................................. 39 Example Application Schematic ................................................................................................................... 40 Electrical Characteristics .............................................................................................................................. 41 11.1 Absolute Maximum Ratings ................................................................................................................. 41 11.2 Recommended Operating Conditions .................................................................................................. 41 11.3 Input/Output Terminal Characteristics ................................................................................................. 42 11.3.1 High-voltage Linear Regulator ............................................................................................... 42 11.3.2 Switch-mode Regulator .......................................................................................................... 43 11.3.3 Low-voltage Linear Regulator ................................................................................................ 44 11.3.4 Battery Charger ...................................................................................................................... 45 11.3.5 Reset ...................................................................................................................................... 46 11.3.6 Regulator Enable ................................................................................................................... 46 11.3.7 Digital Terminals .................................................................................................................... 47 11.3.8 LED Driver Pads .................................................................................................................... 48 11.3.9 Auxiliary ADC ......................................................................................................................... 48 11.3.10 Mono Codec: Analogue to Digital Converter .......................................................................... 49 11.3.11 Mono Codec: Digital to Analogue Converter .......................................................................... 50 11.3.12 Clocks .................................................................................................................................... 51 11.4 ESD Protection .................................................................................................................................... 51 Power Consumption ..................................................................................................................................... 52 12 13 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 54 Software ........................................................................................................................................................ 56 14 14.1 BC6145 QFN DSP Mono Headset Solution ........................................................................................ 56 14.1.1 Hear and Be Heard ................................................................................................................ 56 14.1.2 A2DP Streaming on a Mono Headset .................................................................................... 56 14.1.3 Advanced Multipoint Support ................................................................................................. 56 14.1.4 A2DP Multipoint Support ........................................................................................................ 57 14.1.5 Programmable Audio Prompts ............................................................................................... 57 14.1.6 CSRs Intelligent Power Management ................................................................................... 58 14.1.7 Proximity Pairing .................................................................................................................... 58 14.1.8 Proximity Connection ............................................................................................................. 58 14.2 6th Generation 1-mic CVC Audio Enhancements ................................................................................ 59 14.2.1 Noise Suppression ................................................................................................................. 59 14.2.2 Wind Noise Reduction ............................................................................................................ 59 CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 7 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Contents 14.2.3 Acoustic Echo Cancellation .................................................................................................... 60 14.2.4 Comfort Noise Generator ....................................................................................................... 60 14.2.5 Equalisation ............................................................................................................................ 60 14.2.6 Automatic Gain Control .......................................................................................................... 60 14.2.7 Packet Loss Concealment ..................................................................................................... 60 14.2.8 Adaptive Equalisation ............................................................................................................. 60 14.2.9 Auxiliary Stream Mix .............................................................................................................. 60 14.2.10 Clipper .................................................................................................................................... 60 14.2.11 Noise Dependent Volume Control .......................................................................................... 61 14.2.12 Fixed Gains ............................................................................................................................ 61 14.2.13 Frequency Enhanced Speech Intelligibility ............................................................................ 61 14.3 BC6145 QFN DSP Mono Headset Solution Development Kit ............................................................. 61 15 Ordering Information ..................................................................................................................................... 62 15.1 Development Kit Ordering Information ................................................................................................ 62 Tape and Reel Information ........................................................................................................................... 63 16.1 Tape Orientation .................................................................................................................................. 63 16.2 Tape Dimensions ................................................................................................................................. 64 16.3 Reel Information .................................................................................................................................. 65 16.4 Moisture Sensitivity Level .................................................................................................................... 65 17 Document References .................................................................................................................................. 66 Terms and Definitions ............................................................................................................................................ 67 16 List of Figures Device Pinout .................................................................................................................................. 10 Figure 1.1 Simplified Circuit RF_N and RF_P .................................................................................................. 16 Figure 2.1 Clock Architecture ........................................................................................................................... 18 Figure 3.1 Crystal Driver Circuit ....................................................................................................................... 18 Figure 3.2 Crystal Equivalent Circuit ................................................................................................................ 19 Figure 3.3 Kalimba DSP Interface to Internal Functions .................................................................................. 21 Figure 5.1 Break Signal .................................................................................................................................... 23 Figure 7.1 Example EEPROM Connection ...................................................................................................... 25 Figure 7.2 Example SPI Flash Interface ........................................................................................................... 26 Figure 7.3 Mono Codec Audio Input and Output Stages .................................................................................. 27 Figure 8.1 ADC Analogue Amplifier Block Diagram ......................................................................................... 28 Figure 8.2 Microphone Biasing ......................................................................................................................... 30 Figure 8.3 Differential Input .............................................................................................................................. 32 Figure 8.4 Single-ended Input .......................................................................................................................... 32 Figure 8.5 Speaker Output ............................................................................................................................... 32 Figure 8.6 Voltage Regulator Configuration ..................................................................................................... 35 Figure 9.1 Figure 9.2 LED Equivalent Circuit .................................................................................................................... 38 Figure 10.1 Example Application Schematic ...................................................................................................... 40 Figure 14.1 Programmable Audio Prompts in External IC EEPROM ................................................................ 57 Figure 14.2 Programmable Audio Prompts in External SPI Flash with External IC EEPROM for PS Keys ................................................................................................................................................ 58 1-mic CVC Block Diagram .............................................................................................................. 59 Figure 14.3 Tape Orientation ............................................................................................................................. 63 Figure 16.1 Figure 16.2 Tape Dimensions ............................................................................................................................ 64 Figure 16.3 Reel Dimensions ............................................................................................................................. 65 _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 8 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Contents List of Tables Crystal Specification ......................................................................................................................... 19 Table 3.1 Possible UART Settings ................................................................................................................... 23 Table 7.1 Standard Baud Rates ....................................................................................................................... 24 Table 7.2 Instruction Cycle for a SPI Transaction ............................................................................................ 25 Table 7.3 ADC Digital Gain Rate Selection ...................................................................................................... 28 Table 8.1 DAC Digital Gain Rate Selection ...................................................................................................... 29 Table 8.2 DAC Analogue Gain Rate Selection ................................................................................................. 29 Table 8.3 Voltage Output Steps ....................................................................................................................... 31 Table 8.4 Current Output Steps ....................................................................................................................... 31 Table 8.5 BC6145 QFN Voltage Regulator Enable Pins .................................................................................. 37 Table 9.1 Table 9.2 Pin States on Reset .......................................................................................................................... 39 Table 11.1 ESD Handling Ratings ...................................................................................................................... 51 Table 13.1 Chemical Limits for Green Semiconductor Products ........................................................................ 54 List of Equations Equation 7.1 Baud Rate ....................................................................................................................................... 23 Equation 8.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 33 Equation 8.2 IIR Filter plus DC Blocking Transfer Function, HDC(z) .................................................................... 33 Equation 9.1 LED Current .................................................................................................................................... 38 Equation 9.2 LED PAD Voltage ............................................................................................................................ 38 _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 9 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Package Information 1 Package Information 1.1 Pinout Diagram Orientation from Top of Device 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1.1: Device Pinout 36 35 34 33 32 31 30 29 28 27 26 25 _
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G CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 10 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Package Information 1.2 Device Terminal Functions Bluetooth Radio Lead Pad Type Supply Domain Description RF_N RF_P 8 7 RF RF VDD_RADIO Transmitter output/switched receiver VDD_RADIO Complement of RF_N Synthesiser and Oscillator XTAL_IN XTAL_OUT Lead Pad Type Supply Domain Description 13 14 Analogue Analogue VDD_ANA For crystal or external clock input VDD_ANA Drive for crystal LO_REF 15 Analogue VDD_ANA Reference voltage to decouple the synthesiser SPI Interface Lead Pad Type Supply Domain Description Input, with weak internal pull-down VDD_PADS[1]
SPI data input Bidirectional with weak internal pull-down Bidirectional with weak internal pull-down Bidirectional with weak internal pull-down VDD_PADS[1]
Chip select for SPI, active low VDD_PADS[1]
SPI clock VDD_PADS[1]
SPI data output SPI_DEBUG_EN 42 Input with strong internal pull-down VDD_PADS[1]
Debug interface input, not required for production / debug SPI access on BC6145 QFN UART Interface Lead Pad Type Supply Domain Description SPI_MOSI SPI_CS#
SPI_CLK SPI_MISO UART_TX /
PIO[23]
UART_RX /
PIO[20]
38 40 39 41 19 18 Bidirectional with weak internal pull-up VDD_PADS[0]
Bidirectional with weak internal pull-down VDD_PADS[0]
UART data output, active high. PIO[23] is data output for SPI flash interface (BC6145 QFN is master). UART data input, active high. PIO[20] is clock for SPI flash interface (BC6145 QFN is master). _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 11 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information PIO Port Lead Pad Type Supply Domain Description Package Information Bidirectional with programmable strength internal pull-up/down VDD_PADS[0]
Programmable input/output line. PIO[11] is data input for SPI flash interface (BC6145 QFN is master). Bidirectional with programmable strength internal pull-up/down VDD_PADS[1]
Programmable input/output line Bidirectional with programmable strength internal pull-up/down VDD_PADS[0]
Programmable input/output line PIO[3] is chip select for SPI flash interface (BC6145 QFN is master). Bidirectional with programmable strength internal pull-up/down VDD_PADS[0]
Programmable input/output line Bidirectional VDD_ANA Programmable input/output line Lead Pad Type Supply Domain Description Analogue Analogue Analogue Analogue VDD_AUDIO Speaker output, negative VDD_AUDIO Speaker output, positive VDD_AUDIO Microphone input, negative VDD_AUDIO Microphone input, positive MIC_BIAS 47 Analogue VDD_AUDIO, BAT_P Microphone bias AU_REF 5 Analogue VDD_AUDIO Decoupling of audio reference
(for high quality audio) LED Drivers Lead Pad Type Supply Domain Description LED[1]
LED[0]
Open drain output Open drain LED driver Open drain output Open drain LED driver PIO[11]
PIO[8]
PIO[7]
PIO[6]
PIO[3]
PIO[2]
PIO[1]
PIO[0]
AIO[0]
AIO[1]
Audio SPKR_N SPKR_P MIC_N MIC_P 27 44 45 46 21 22 23 24 17 16 3 4 2 1 28 29 _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 12 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Package Information Test and Debug Lead Pad Type Supply Domain Description RST#
TEST_EN 26 25 Input with weak internal pull-up VDD_PADS[0]
Reset if low. Input debounced so must be low for >5ms to cause a reset Input with strong internal pull-down VDD_PADS[0]
For test purposes only (leave unconnected) Power Supplies Control Lead Description VREGENABLE_L VREGENABLE_H VREGIN_L VREGIN_H LX VREGOUT_H VDD_PADS[1]
VDD_PADS[0]
VDD_CORE VDD_RADIO VDD_ANA VDD_LO VDD_AUDIO BAT_P VDD_CHG SMP_SENSE VSS 10 33 11 32 35 31 43 20 30 6 12 9 48 36 37 34 Take high to enable low-voltage regulator Take high to enable both high-voltage regulator and switch-mode regulator Input to internal low-voltage regulator Input to internal high-voltage regulator Switch-mode power regulator output High-voltage regulator output Positive supply for digital input/output ports including PIO[8:6] and SPI interface Positive supply for digital input/output ports including PIO[11,3:0]
Positive supply for internal digital circuitry Positive supply for RF circuitry Positive supply for analogue circuitry, AIO[1:0]. Output from internal 1.5V regulator Positive supply for local oscillator circuitry Positive supply for audio Lithium ion/polymer battery positive terminal. Battery charger output and input to switch-mode regulator Lithium ion/polymer battery charger input Positive supply for switch-mode control circuitry _
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t D a a S h e e t Exposed Pad Ground connections CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 13 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 1.3 Package Dimensions Package Information Dimension Min Typ Max Dimension Min Typ Max A A1 A2 A3 b D E e 0.8 0.85 0.9 J K L 0.035 0.05 0.65 0.67 0.203
bbb 0.25 0.3 ccc 7 7 7.05 ddd 7.05 eee 5.2 5.2 0.35
5.3 5.3 0.4 0.1 0.08 0.1 0.1 5.4 5.4 0.45
0.5
P 0.3
Notes 1. Coplanarity applies to leads, corner leads and die attach pad. 2. Exposed die attach pad smaller than BlueVox2 QFN. Dimensions have been reduced to enhance solderability. Backward pin-for-pin compatibility with BlueVox2 QFN is maintained 0
0.2 6.9 6.9 _
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G Size Pitch Description 48-lead Quad Flat No-lead Package 7 x 7 x 0.9mm JEDEC MO-220 0.5 Units mm CS-204118-DSP2 Page 14 of 69 Production Information Cambridge Silicon Radio Limited 2010 This Material is Subject to CSR's Non-disclosure Agreement Package Information 1.4 PCB Design and Assembly Considerations This section lists recommendations to achieve maximum board-level reliability of the 7 x 7 x 0.9mm QFN 48-lead package:
NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. CSR recommends that the PCB land pattern to be in accordance with IPC standard IPC-7351. Solder paste must be used during the assembly process. 1.5 Typical Solder Reflow Profile See Typical Solder Reflow Profile for Lead-free Devices for information. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 15 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Bluetooth Modem 2 Bluetooth Modem 2.1 RF Ports 2.1.1 RF_N and RF_P RF_N and RF_P form a complementary balanced pair and are available for both transmit and receive. On transmit their outputs are combined using an external balun into the single-ended output required for the antenna. Similarly, on receive their input signals are combined internally. Both terminals present similar complex impedances that may require matching networks between them and the balun. Viewed from the chip, the outputs can each be modelled as an ideal current source in parallel with a lossy capacitor. An equivalent series inductance can represent the package parasitics. _ PA
LNA _ RF Switch RF Switch RF_N RF_P _
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G RF_N and RF_P require an external DC bias. The DC level must be set at VDD_RADIO. Figure 2.1: Simplified Circuit RF_N and RF_P 2.2 RF Receiver The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die. A digital FSK discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise enables BC6145 QFN to exceed the Bluetooth requirements for co-channel and adjacent channel rejection. For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed to the EDR modem. 2.2.1 Low Noise Amplifier The LNA operates in differential mode and takes its input from the shared RF port. 2.2.2 RSSI Analogue to Digital Converter The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference limited environments. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 16 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Bluetooth Modem 2.3 RF Transmitter 2.3.1 IQ Modulator 2.3.2 Power Amplifier The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping. The internal PA on the BC6145 QFN has a maximum output power that enables it to operate as a Class 2 and Class 3 Bluetooth radio without requiring an external RF PA. 2.4 Bluetooth Radio Synthesiser The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v3.0 specification. 2.5 Baseband 2.5.1 Burst Mode Controller During transmission the BMC constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception. 2.5.2 Physical Layer Hardware Engine Dedicated logic performs the following:
Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding Firmware performs the following voice data translations and operations:
A-law/-law/linear voice data (from host) A-law/-law/CVSD (over the air) Voice interpolation for lost packets Rate mismatch correction The hardware supports all optional and mandatory features of the Bluetooth v3.0 specification including AFH and eSCO. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 17 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Clock Generation 3 Clock Generation BC6145 QFN requires a Bluetooth reference clock frequency, derived from an externally connected crystal in the range 16MHz to 26MHz. All BC6145 QFN internal digital clocks are generated by a phase locked loop, locked to the frequency of the external reference clock. The Bluetooth operation determines the watchdog clock operation in low-power modes. 3.1 Clock Architecture Reference Clock Bluetooth Radio Auxiliary PLL Digital Circuitry 3.2 Input Frequencies and PS Key Settings Figure 3.1: Clock Architecture BC6145 QFN is configured to operate with a chosen reference frequency. PSKEY_ANA_FREQ sets this reference frequency for all frequencies using an integer multiple of 250kHz. The input frequency default setting for BC6145 QFN is 26MHz depending on the software build. Full details are in the software release note for the specific build from www.csrsupport.com. 3.3 Crystal Oscillator: XTAL_IN and XTAL_OUT BC6145 QFN contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator. Figure 3.2 shows the external crystal is connected to pins XTAL_IN, XTAL_OUT. g m
C trim Cint N I _ L A T X Ct2 T U O _ L A T X C t1 Figure 3.3 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors. Figure 3.2: Crystal Driver Circuit CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 18 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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. 4 4 5 4 2 0 0 0 0
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G Cm Lm Rm CO Min 16
Figure 3.3: Crystal Equivalent Circuit The resonant frequency can be trimmed with the crystal load capacitance. BC6145 QFN contains variable internal capacitors to provide a fine trim. Table 3.1 shows the specification for an external crystal. Parameter Frequency Initial Tolerance Pullability Typ 26 25 20 Max 26
Unit MHz ppm ppm/pF The BC6145 QFN driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and can be set for optimum performance. Table 3.1: Crystal Specification 3.3.1 Crystal PS Key Settings The BC6145 QFN firmware automatically controls the drive level on the crystal circuit to achieve optimum input swing. The firmware uses PSKEY_XTAL_TARGET_AMPLITUDE to servo the required amplitude of crystal oscillation. For more information see the software build release note. Configure the BC6145 QFN to operate with the chosen reference frequency. 3.4 External 32kHz Clock Apply a 32kHz clock to AIO[0] by setting DEEP_SLEEP_EXTERNAL_CLOCK_SOURCE. If the external clock is applied to the analogue pad AIO[0], drive the digital signal with a maximum 1.5V. Note:
If the 32kHz clock is accurate and stable to within 200ppm, then further power saving features are available. See the relevant software release note for more information. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 19 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Bluetooth Stack Microcontroller 4 Bluetooth Stack Microcontroller BC6145 QFN uses a 16-bit RISC MCU for low power consumption and efficient use of memory. The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host interfaces. 4.1 Programmable I/O Ports BC6145 QFN provides 8 lines of programmable bidirectional I/O. PIO[11,3:0] are powered from VDD_PADS[0] and PIO[8:6] are powered from VDD_PADS[1]. AIO[1:0] are powered from VDD_ANA. Any of the PIO lines are configurable as button inputs or control outputs. Certain PIOs also have dedicated functions that are accessed using appropriate PS Keys. PSKEY_CLOCK_REQUEST_ENABLE configures PIO[6] or PIO[2]
as a request line for an external clock source. This is useful for detecting when BC6145 QFN is entering or leaving deep sleep. Note:
Note:
See the relevant software release note for the implementation of these PIO lines, as they are firmware build-
specific. BC6145 QFN has 2 general-purpose analogue interface pins, AIO[1:0], to access internal circuitry and control signals. Auxiliary functions available on the analogue interface include a 10-bit ADC. Signals selectable on this interface include the band gap reference voltage and a variety of clock signals: 64, 48, 32, 24, 16, 12, 8, 6 and 2MHz
(output from AIO[0] only) and the XTAL and XTAL/2 clock frequency (output from AIO[1] and AIO[0]). When operating with analogue signals the voltage range is constrained by the analogue supply voltage. When configured to drive out digital level signals (clocks) generated from within the analogue part of the device, VDD_ANA determines the output voltage level. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 20 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Kalimba DSP 5 Kalimba DSP The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over-air data or codec data to enhance audio applications. The Kalimba DSP is dedicated to processing the audio enhancement algorithms, which are hard-coded into the ROM. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks within BC6145 QFN. Kalimba DSP Core Memory Management Unit MCU Register Interface (including Debug) DSP MMU Port DSP, MCU and Memory Window Control Programmable Clock = 64MHz DSP RAMs l o r t n o C m a r g o r P P S D DM2 DM1 PM DSP Data Memory 2 Interface (DM2) DSP Data Memory 1 Interface (DM1) DSP Program Memory Interface (PM) Data Memory Inteface Address Generators Instruction Decode ALU s r e t s g e R i Program Flow DEBUG Clock Select PIO Internal Control Register MMU Interface Interrupt Controller Timer MCU Window Flash Window PIO In/Out IRQ to Subsystem IRQ from Subsystem 1s Timer Clock The key features of the DSP include:
Figure 5.1: Kalimba DSP Interface to Internal Functions 64MIPS performance, 24-bit fixed point DSP core Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate 32-bit instruction word Separate program memory and dual data memory, enabling an ALU operation and up to 2 memory accesses in a single cycle Zero overhead looping Zero overhead circular buffer indexing Single cycle barrel shifter with up to 56-bit input and 24-bit output Multiple cycle divide (performed in the background) Orthogonal instruction set Bit reversed addressing Low overhead interrupt _
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G CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 21 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Memory Interface and Management 6 Memory Interface and Management 6.1 Memory Management Unit The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers. 6.2 System RAM 48KB of integrated RAM supports the RISC MCU and is shared between the ring buffers for holding voice/data for each active connection and the general-purpose memory required by the Bluetooth stack. 6.3 Kalimba DSP RAM Additional integrated RAM provides support for the Kalimba DSP:
8K x 24-bit for data memory 1 (DM1) 4K x 24-bit for data memory 2 (DM2) 4K x 32-bit for program memory (PM) Note:
6.4 Internal ROM Internal ROM is provided for system firmware implementation. The Kalimba DSP can also execute directly from internal ROM, using a 64-instruction on-chip cache. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 22 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Serial Interfaces 7 Serial Interfaces 7.1 UART Interface BC6145 QFN has a standard UART serial interface that provides a simple communications channel for test and debug using RS232 protocol. 2 signals implement the UART function, UART_TX and UART_RX. When BC6145 QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. UART configuration parameters, such as baud rate and packet format, are set using BC6145 QFN firmware. To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated serial port adapter card. Minimum Maximum Possible Values 1200 baud (2%Error) 9600 baud (1%Error) 4Mbaud (1%Error) None, Odd or Even None 1 or 2 8 Table 7.1: Possible UART Settings The UART interface resets BC6145 QFN on reception of a break signal. A break is identified by a continuous logic low (0V) on the UART_RX terminal, as Figure 7.1 shows. If tBRK is longer than the value, defined by the HOSTIO_UART_RESET_TIMEOUT, a reset occurs. This feature enables a host to initialise the system to a known state. Also, BC6145 QFN can issue a break character for waking the host. Table 7.2 shows a list of common baud rates and their associated values for PSKEY_UART_BAUDRATE. There is no requirement to use these standard values. Any baud rate within the supported range is set in the PS Key according to the formula in Equation 7.1. tBRK Figure 7.1: Break Signal Baud Rate =
PSKEY_UART_BAUDRATE 0.004096 Equation 7.1: Baud Rate Note:
Parameter Baud rate Flow control Parity Number of stop bits Bits per byte UART_TX _
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G CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 23 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Baud Rate Persistent Store Value 1200 2400 4800 9600 19200 38400 57600 76800 115200 230400 460800 921600 1382400 1843200 2764800 3686400 Hex 0x0005 0x000a 0x0014 0x0027 0x004f 0x009d 0x00ec 0x013b 0x01d8 0x03b0 0x075f 0x0ebf 0x161e 0x1d7e 0x2c3d 0x3afb Dec 5 10 20 39 79 157 236 315 472 944 1887 3775 5662 7550 11325 15099 Serial Interfaces Error 1.73%
1.73%
1.73%
-0.82%
0.45%
-0.18%
0.03%
0.14%
0.03%
0.03%
-0.02%
0.00%
-0.01%
0.00%
0.00%
0.00%
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t D a a S h e e t 7.1.1 UART Configuration While Reset is Active Table 7.2: Standard Baud Rates The UART interface is tristate while BC6145 QFN is being held in reset. This enables the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tristate when BC6145 QFN reset is de-asserted and the firmware begins to run. 7.2 Programming and Debug Interface Important Note:
The SPI is for programming, configuring (PS Keys) and debugging the BC6145 QFN. It is required in production. Ensure the 4 SPI signals are brought out to either test points or a header. CSR provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required. All are available from CSR. BC6145 QFN uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when the internal processor is running or is stopped. Data is written or read one word at a time, or the auto-increment feature is available for block access. 7.2.1 Instruction Cycle The BC6145 QFN is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 7.3 shows the instruction cycle for a SPI transaction. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 24 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Serial Interfaces 1 2 3 4 5 Reset the SPI interface Hold SPI_CS# high for two SPI_CLK cycles Write the command word Take SPI_CS# low and clock in the 8-bit command Write the address Clock in the 16-bit address word Write or read data words Clock in or out 16-bit data word(s) Termination Take SPI_CS# high Table 7.3: Instruction Cycle for a SPI Transaction With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into the BC6145 QFN on the rising edge of the clock line SPI_CLK. When reading, BC6145 QFN replies to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. Taking SPI_CS# high terminates the transaction. Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when transferring large amounts of data. To overcome this BC6145 QFN offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read. 7.2.2 Multi-slave Operation Avoid connecting BC6145 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines. When BC6145 QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, BC6145 QFN outputs 0 if the processor is running or 1 if it is stopped. 7.3 IC Interface Note:
PIO[8:6] are available to form a master IC interface. The interface is formed using software to drive these lines. The program memory for the BC6145 QFN is internal ROM so the IC interface only connects to a serial EEPROM, Figure 7.2 shows an example. The EEPROM stores programmable audio prompts, see Section 14.1.5, as well as PS Keys and configuration information. The programmable audio prompts option requires a larger EEPROM than Figure 7.2 shows, up to 512Kb. When a SPI flash is used to store programmable audio prompts, see Section 7.4, an EEPROM is still required to store the PS Keys and configuration information. The EEPROM Supply in Figure 7.2 is 1.9V. _
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t D a a S h e e t EEPROM Supply Decoupling Capacitor 1 2 3 4 8 7 6 5 VCC WP SCL A0 A1 A2 SDA GND Serial EEPROM
(24AA32) PIO[8]
PIO[6]
PIO[7]
. 3 5 7 0 2 0 0 0 0
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G 7.4 SPI Flash Interface Figure 7.2: Example EEPROM Connection PIO[23, 20, 11, 3] form a software-driven master SPI flash interface, Figure 7.3 shows an example connection to a serial SPI flash IC. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 25 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information The SPI flash is only for programmable audio prompts storage, see Section 14.1.5. SPI Flash Supply R 100k PIO[3]
PIO[20]
VDD CE#
WP#/SIO2 SCK HOLD#/SIO3 SI/SIO0 VSS SO/SIO1 C 100nF PIO[23]
PIO[11]
Figure 7.3: Example SPI Flash Interface Note:
The SPI Flash Supply in Figure 7.3 is 1.9V. For more information on supported SPI flash ICs contact CSR. Serial Interfaces 1
. 1
. 3 8 6 6 0 0 0
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G _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 26 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Audio Interface 8 Audio Interface The audio interface circuit consists of:
Mono audio codec Audio inputs and outputs 8.1 Audio Input and Output The audio input circuitry consists of:
1 channel of microphone input:
The microphone input is configurable to be either single-ended or fully differential The input has an analogue and digital programmable gain stage for optimisation of different microphones The audio output circuitry consists of a single differential class AB output stage. 8.2 Mono Audio Codec Block Diagram MIC_P MIC_N SPKR_P SPKR_N Input Amplifier
- ADC LP Filter Output Amplifier
- DAC Figure 8.1: Mono Codec Audio Input and Output Stages The mono audio codec uses a fully differential architecture in the analogue signal path, which results in low noise-
sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a single power-supply of 1.5V and uses a minimum of external components. 8.3 ADC The ADC consists of:
8.3.1 ADC Digital Gain A second-order Sigma-Delta converter, as Figure 8.1 shows. 2 gain stages; one of which is an analogue gain stage and the other is a digital gain stage. The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain settings summarised in Table 8.1. There is also a high resolution digital gain mode, which enables gain changes in 1/32 steps. Contact CSR for more information. Digital Circuitry
. 2 3 0 2 4 1 0 0 0
W T
G _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 27 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Audio Interface
(dB)
-24
-20.5
-18
-14.5
-12
-8.5
-6
-2.5 _
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t D a a S h e e t P N 2
. 4 0 0 4 1 0 0 0
W T
G Gain Selection Value ADC Digital Gain Setting ADC Digital Gain Setting Gain Selection Value
(dB) 3.5 0 6 9.5 12 15.5 18 21.5 8 9 10 11 12 13 14 15 8.3.2 ADC Analogue Gain Table 8.1: ADC Digital Gain Rate Selection Figure 8.2 shows the equivalent block diagram for the ADC analogue amplifier. It is a two-stage amplifier:
The first stage amplifier has a selectable gain of either bypass for line input mode or gain of 24dB gain for the microphone mode. The second stage has a programmable gain with 7 individual 3dB steps. By combining the 24dB gain selection of the microphone input with the 7 individual 3dB gain steps, the overall range of the analogue amplifier is approximately -3dB to 42dB in 3dB steps. The BC6145 QFN controls all the gain control of the ADC. Bypass or 24dB gain
-3dB to 18dB gain 0 1 2 3 4 5 6 7 P N Line Mode / Mic Mode Gain 0:7 Switches shown for line mode Microphone mode input impedance = 6k Line mode input impedance = 6k to 30k Figure 8.2: ADC Analogue Amplifier Block Diagram 8.4 DAC The DAC consists of:
A second-order Sigma-Delta converter, as Figure 8.1 shows. 2 gain stages; one of which is an analogue gain stage and the other is a digital gain stage. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 28 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Audio Interface 8.4.1 DAC Digital Gain The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings, summarised in Table 8.2. There is also a high resolution digital gain mode, which enables gain changes in 1/32 steps. Contact CSR for more information. The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and analogue amplifier settings. Digital Gain Selection DAC Digital Gain Setting Digital Gain Selection DAC Digital Gain Setting Value Value
(dB) 3.5 0 6 9.5 12 15.5 18 21.5 3 0
-3
-6 8 9 10 11 12 13 14 15 3 2 1 0
(dB)
-24
-20.5
-18
-14.5
-12
-8.5
-6
-2.5
-9
-12
-15
-18 _
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t D a a S h e e t 8.4.2 DAC Analogue Gain Table 8.2: DAC Digital Gain Rate Selection Table 8.3 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB steps. The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue amplifier settings. Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain Value Setting (dB) Value Setting (dB) 0 1 2 3 4 5 6 7 7 6 5 4 Table 8.3: DAC Analogue Gain Rate Selection CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 29 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 8.5 Microphone Input Figure 8.3 shows recommended biasing for each microphone. The microphone bias, MIC_BIAS, derives its power from the BAT_P and requires a 1F capacitor on its output. Microphone Bias R2 R1 C1 C2
MIC1 C3 C4 MIC_P MIC_N Input Amplifier Audio Interface 2
. 2
. 9 8 1 1 0 0 0
W T
G Figure 8.3: Microphone Biasing The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS maintains regulation within the limits 0.200mA to 1.230mA. If the microphone sits below these limits, then the microphone output must be pre-loaded with a large value resistor to ground. The audio input range is from 1A to 10A at 94dB SPL. With biasing resistors R1 and R2 equal to 1k, this requires microphones with sensitivity between about 40dBV and 60dBV. The input impedance at MIC_N and MIC_P is typically 6.0k. C1 and C2 are 150nF if low frequency roll-off is required to limit wind noise on the microphone. R1 sets the microphone load impedance and is normally in the range of 1k to 2k. R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Select the values as required. R2 can connect to a convenient supply, in which case the bias network is permanently enabled, or to the MIC_BIAS output (which is ground referenced and provides good rejection of the supply), which is configurable to provide bias only when the microphone is required. Table 8.4 shows the 4-bit programmable output voltage that the microphone bias provides, and Table 8.5 shows the 4-bit programmable output current. The characteristics of the microphone bias include:
BC6145 QFN microphone supply is BAT_P Power supply:
Minimum input voltage = Output voltage + drop-out voltage Maximum input voltage is 4.4V Drop-out voltage:
Guaranteed for configuration of voltage or current output shown in Table 8.4 and Table 8.5 Typically the microphone bias is between 2V and 2.5V, or as specified by the microphone vendor 300mV minimum _
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t D a a S h e e t Output voltage:
4-bit programmable from 1.7V to 3.6V Tolerance 90% to 110%
Output current:
4-bit programmable from 200A to 1.230mA Maximum current guaranteed >1mA Load capacitance:
Unconditionally stable for 1F 20% and 2.2F 20% pure C CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 30 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Output Step VOL_SET[3:0]
Typ Units VOL_SET[3:0]
Typ Units Output Step 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0000 0001 0010 0011 0100 0101 0110 0111 0000 0001 0010 0011 0100 0101 0110 0111 1.71 1.76 1.82 1.87 1.95 2.02 2.10 2.18 0.200 0.280 0.340 0.420 0.480 0.530 0.610 0.670 V V V V V V V V mA mA mA mA mA mA mA mA 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 1000 1001 1010 1011 1100 1101 1110 1111 1000 1001 1010 1011 1100 1101 1110 1111 Table 8.4: Voltage Output Steps Output Step CUR_SET[3:0]
Typ Units CUR_SET[3:0]
Typ Units Output Step Audio Interface 2.32 2.43 2.56 2.69 2.90 3.08 3.33 3.57 0.750 0.810 0.860 0.950 1.000 1.090 1.140 1.230 V V V V V V V V mA mA mA mA mA mA mA mA _
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t D a a S h e e t Note:
Table 8.5: Current Output Steps For BAT_P, the PSRR at 100Hz to 22kHz, with >300mV supply headroom, decoupling capacitor of 1.1F, is typically 58.9dB and worst case 53.4dB. For VDD_AUDIO, the PSRR at 100Hz to 22kHz, decoupling capacitor of 1.1F, is typically 88dB and worst case 60dB. 8.6 Line Input If the input analogue gain is set to less than 24dB, BC6145 QFN automatically selects line input mode. In line input mode the first stage of the amplifier is automatically disabled, providing additional power saving. In line input mode the input impedance varies from 6k to 30k, depending on the volume setting. Figure 8.4 and Figure 8.5 show 2 circuits for line input operation and show connections for either differential or single-ended inputs. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 31 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information C1 C2 C1 C2 MIC_P MIC_N MIC_P MIC_N Figure 8.4: Differential Input Audio Interface 3
. 2
. 1 9 1 1 0 0 0
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G 2 3
. 0 9 1 1 0 0 0
W T
G 2
. 2
. 4 1 6 0 0 0 0
W T
G _
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t D a a S h e e t 8.7 Output Stage Figure 8.5: Single-ended Input The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. The output stage circuit comprises a DAC with gain setting and class AB output stage amplifier. The output is available as a differential signal between SPKR_N and SPKR_P, as Figure 8.6 shows. The output stage is capable of driving a speaker directly when its impedance is at least 8. SPKR_P SPKR_N A 3-bit programmable resistive divider controls the analogue gain of the output stage, which sets the gain in steps of approximately 3dB. Figure 8.6: Speaker Output 8.8 Integrated Digital IIR Filter BC6145 QFN has a programmable digital filter integrated into the ADC channel of the codec. The filter is a 2-stage, second order IIR and is for functions such as custom wind noise reduction. The filter also has optional DC blocking. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 32 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Audio Interface The filter has 10 configuration words:
1 for gain value 8 for coefficient values 1 for enabling and disabling the DC blocking The gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN. Note:
The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit. For example:
01.1111111111 01.0000000000 00.0000000000 11.0000000000 10.0000000000
most positive number, close to 2 1 0
-1
-2, most negative number Equation 8.1 shows the equation for the IIR filter. Equation 8.2 shows the equation for when the DC blocking is enabled. The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in the following order:
0 1 2 3 4 5 6 7 8 9
Gain b01 b02 a01 a02 b11 b12 a11 a12 DC Block (1 = enable, 0 = disable) _
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t D a a S h e e t Filter, H(z) = Gain
( 1 + b01 z
( 1 + a z 01 1 1
+ b02 z
+ a 02 2 ) 2 ) z
( 1 + b11 z
( 1 + a z 11 1 1
+ b12 z
+ a 12 2 ) 2 ) z Equation 8.1: IIR Filter Transfer Function, H(z) Filter with DC Blocking, HDC (z) = H(z) ( 1 z1 ) Equation 8.2: IIR Filter plus DC Blocking Transfer Function, HDC(z) 8.8.1 Integrated Digital Filter Configuration The behaviour of the integrated digital IIR filter described in Section 8.8, is configurable through 12 values stored in PSKEY_USR29:
10-words for the IIR filter parameters in Section 8.8 1-word for the audio energy estimation threshold 1-word for the gain applied when the audio energy estimation is above the threshold Adjusting these values configures the IIR filter for different functions. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 33 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Audio Interface Note:
The IIR filter is switched off at initialisation. 8.9 Side Tone PSKEY_SIDE_TONE_ENABLE PSKEY_SIDE_TONE_GAIN PSKEY_SIDE_TONE_AFTER_ADC PSKEY_SIDE_TONE_AFTER_DAC In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the microphone signal to the earpiece. The BC6145 QFN codec contains side tone circuitry to do this. The side tone hardware is configured through the following PS Keys:
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 34 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Power Control and Regulation 9 Power Control and Regulation BC6145 QFN contains 3 regulators:
A switch-mode regulator, which generates a 1.5V rail A low-voltage regulator, which generates an optional 1.5V rail A high-voltage linear regulator, which generates a 1.9V rail for powering the EEPROM Various configurations for power control and regulation with BC6145 QFN are available, but Figure 9.1 shows a typical configuration. This configuration shows the switch-mode regulator generating a 1.5V supply rail, and the high-
voltage linear regulator generating a 1.9V supply rail. VDD_LO VDD_ANA VDD_RADIO VDD_AUDIO VREGIN_L VDD_CORE LX SMP_SENSE Battery Supply IN OUT Battery Charger LX Switch-mode Regulator EN SENSE VDD_CHG BAT_P VSS VREGENABLE_H VREGIN_H EN OUT High-voltage Linear Regulator IN SENSE VREGOUT_H VDD_PADS[1:0]
VREGENABLE_L 1.5 V Rail 1.9 V Rail
. 2 4 2 5 9 0 0 0 0
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G _
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t D a a S h e e t 9.1 Power Sequencing Figure 9.1: Voltage Regulator Configuration The 1.5V supply rails are VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO. CSR recommends that these supply rails are all powered at the same time. The digital I/O supply rails are VDD_PADS[1:0]. The sequence of powering the 1.5V supply rails relative to the digital I/O supply rails is not important. If the digital I/O supply rails are powered before the 1.5V supply rails, all digital I/Os have a weak pull-down irrespective of the reset state. VDD_ANA, VDD_AUDIO, VDD_LO and VDD_RADIO can connect directly to a 1.5V supply. A simple RC filter is recommended for VDD_CORE to reduce transients fed back onto the power supply rails. The digital I/O supply rails are connected either together or independently to an appropriate voltage rail. CSR recommends decoupling of the digital I/O supply rails. 9.2 External Voltage Source If supplying any of the power rails for BC6145 QFN from an external voltage source, rather than one of the internal voltage regulators, CSR recommends that VDD_AUDIO, VDD_LO and VDD_RADIO have less than 10mV rms noise level between 0 and 10MHz. Also avoid single tone frequencies. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 35 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Power Control and Regulation The transient response of any external regulator should match or better the internal regulator available on BC6145 QFN. For more information, see the regulator characteristics in Section 11. It is essential that the power rail recovers quickly at the start of a packet, where the power consumption jumps to high levels. 9.3 Switch-mode Regulator CSR recommends the on-chip switch-mode regulator to power the 1.5V supply rail. An external LC filter circuit of a low-resistance series inductor, L1 (22H), followed by a low ESR shunt capacitor, C1 (4.7F), is required between the LX terminal and the 1.5V supply rail. A connection between the 1.5V supply rail and the SMP_SENSE pin is required. A 2.2F decoupling capacitor is required between BAT_P and VSS. To maintain high-efficiency power conversion and low supply ripple, it is essential that the series resistance of tracks between the BAT_P and VSS terminals, the filter and decoupling components, and the external voltage source are minimised. The switch-mode regulator is enabled by any of the following:
VREGENABLE_H pin BC6145 QFN device firmware BC6145 QFN battery charger The switch-mode regulator switches into a low-power pulse skipping mode when the device is sent into deep sleep mode, or in reset. When the switch-mode regulator is not required, either ground the terminals BAT_P and LX, or leave them unconnected. 9.4 High-voltage Linear Regulator The 1.9V high-voltage linear regulator provides power for an external EEPROM. The external EEPROM stores PS Key and configuration information, see Section 7.3. CSR does not recommend using the high-voltage linear regulator to power any additional circuitry. Connect a decoupling capacitor of at least 100nF (preferably 470nF) to the input of the high-voltage linear regulator to maintain stability. Connect a smoothing circuit using a low ESR 2.2F capacitor and a 2.2 resistor to ground, to the output of the high-voltage linear regulator, VREGOUT_H. Alternatively use a 2.2F capacitor with an ESR of at least 2. The high-voltage linear regulator is enabled by any of the following:
VREGENABLE_H pin BC6145 QFN device firmware BC6145 QFN battery charger The regulator is switched into a low-power mode when the device is in deep sleep mode, or in reset. 9.5 Low-voltage Linear Regulator The low-voltage linear regulator is available to power a 1.5V supply rail. Its output is connected internally to VDD_ANA, and can connect externally to the other 1.5V power inputs. Connect a smoothing circuit using a low ESR 2.2F capacitor and a 2.2 resistor to ground to the output of the low-
voltage linear regulator, VDD_ANA. Alternatively use a 2.2F capacitor with an ESR of at least 2. The low-voltage linear regulator is enabled by any of the following:
VREGENABLE_L pin BC6145 QFN device firmware BC6145 QFN battery charger The low-voltage linear regulator switches into a low power mode when the device is in deep sleep mode, or in reset. When the low-voltage linear regulator is not required, either leave the terminal VREGIN_L unconnected, or tie it to VDD_ANA. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 36 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Power Control and Regulation 9.6 Voltage Regulator Enable Pins VREGENABLE_H and VREGENABLE_L enable the BC6145 QFN if the integrated regulators are used. Table 9.1 shows the appropriate enable pin responsible for each voltage regulator. Enable Pin Regulator VREGENABLE_H High-voltage Linear Regulator and Switch-mode Regulator VREGENABLE_L Low-voltage Linear Regulator The voltage regulator enable pins are active high, with weak pull-downs. Table 9.1: BC6145 QFN Voltage Regulator Enable Pins BC6145 QFN boots-up when the voltage regulator enable pins are pulled high, enabling the appropriate regulators. The firmware then latches the regulators on, release of the voltage regulator enable pins is then permitted. The status of the VREGENABLE_H pin is available to firmware through an internal connection. VREGENABLE_H also works as an input line. 9.7 Battery Charger The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer batteries only. It shares a connection to the battery terminal, BAT_P, with the switch-mode regulator. Although it operates in conjunction with either of the high-voltage regulators on the BC6145 QFN. The constant current level is varied to enable charging of different capacity batteries. The charger enters various states of operation as it charges a battery, as listed below. A full operational description is in BlueCore5 Charger Description and Calibration Procedure Application Note:
Off: entered when charger is disconnected. Trickle charge: entered when battery is below 2.9V. The battery is charged at a nominal 4.5mA. This mode is for the safe charge of deeply discharged cells. Fast charge constant current: entered when battery is above 2.9V. The charger enters the main fast charge mode. This mode charges the battery at the selected constant current, Ichgset. Fast charge constant voltage: entered when battery has reached a selected voltage, Vfloat. The charger switches mode to maintain the cell voltage at the Vfloat voltage by adjusting the charge current. Standby: this is the state when the battery is fully charged and no charging takes place. The battery voltage is continuously monitored and if it drops by more than 150mV below the Vfloat voltage the charger will re-
enter the fast charge constant current mode to keep the battery fully charged. When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger operates and an LED connected to the terminal LED[0] illuminates. By default, until the firmware is running, the LED pulses at a low duty cycle to minimise current consumption. The battery charger circuitry auto-detects the presence of a power source, enabling the firmware to detect, via an internal status bit, when the charger is powered. Therefore, when the charger supply is not connected to VDD_CHG, leave the terminal open-circuit. When not connected, the VDD_CHG pin must float, so do not pull to a power rail. When the battery charger is not enabled this pin may float to a low undefined voltage. Any DC connection increases current consumption of the device. Connection to capacitive components such as diodes, FETs and ESD protection are permitted. The battery charger is designed to operate with a permanently connected battery. If the application enables the charger input connection while the battery is disconnected, then the BAT_P pin voltage could become unstable and cause damage to the internal switch-mode regulator. Connecting a 470F capacitor to BAT_P limits these oscillations and prevents damage. The BC6145 QFN supports an external boost charge feature to provide up to 240mA fast charge current. For more information contact CSR. Note:
Support for the external boost charge feature is available when using updated configuration as described in the BC6145 QFN software release note, see www.csrsupport.com. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 37 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Power Control and Regulation 9.8 LED Drivers BC6145 QFN includes 2 pads dedicated to driving LED indicators. Firmware controls both terminals, while the battery charger can also set LED[0]. The terminals are open-drain outputs. Connect the LED from a positive supply rail to the pad in series with a current-
limiting resistor. CSR recommends that the 2 pads, LED[0] or LED[1] pins, operate with a pad voltage below 0.5V. In this case, the pad is like a resistor, RON. The resistance together with the external series resistor sets the current, ILED, in the LED. The current also depends on the external voltage, VDD, as Figure 9.2 shows. VDD D E L I LED Forward Voltage, VF LED[0] or LED[1]
RLED Resistor Voltage Drop, VR Pad Voltage, VPAD; RON = 20 From Figure 9.2 it is possible to derive Equation 9.1 to calculate ILED. If a known value of current is required through the LED to give a specific luminous intensity, then calculate the value of RLED. Figure 9.2: LED Equivalent Circuit ILED =
VDD V F R LED
+ R ON Equation 9.1: LED Current VDD = VF + VR + VPAD Equation 9.2: LED PAD Voltage For the LED[0] or LED[1] pad to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across it, VR, keeps VPAD below 0.5V. Equation 9.2 also applies. The LED current adds to the overall current. Conservative LED selection extends battery life. Note:
9.9 Reset, RST#
BC6145 QFN is reset from several sources:
CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 38 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t
. 2 3 5 5 2 0 0 0 0
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G Power Control and Regulation RST# pin Power-on reset UART break character Software configured watchdog timer The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset is performed between 1.5ms and 4.0ms following RST# being active. CSR recommends applying RST# for a period greater than 5ms. The power-on reset occurs when the VDD_CORE supply falls below typically 1.25V and is released when VDD_CORE rises above typically 1.30V. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate. Following a reset, BC6145 QFN assumes the maximum XTAL_IN frequency, which ensures that the internal clocks run at a safe (low) frequency until BC6145 QFN is configured for the actual XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BC6145 QFN free runs, again at a safe frequency. 9.9.1 Digital Pin States on Reset Table 9.2 shows the pin states of BC6145 QFN on reset. PU and PD default to weak values unless specified otherwise. Pin Name / Group I/O Type No Core Voltage Reset Full Chip Reset UART_RX UART_TX SPI_MOSI SPI_CLK SPI_CS#
SPI_MISO RST#
TEST_EN PIO[11,3:0]
PIO[8:6]
Digital input with PD Digital bidirectional with PU Digital input with PD Digital bidirectional with PD Digital bidirectional with PD Digital tristate output with PD Digital input with PU Digital input with strong PD Digital bidirectional with PU/
PD PD PD PD PD PD PD PD PU PD PD SPI_DEBUG_EN Digital input with PD Table 9.2: Pin States on Reset 9.9.2 Status after Reset The status of BC6145 QFN after a reset is:
Warm reset: data rate and RAM data remain available Cold reset: data rate and RAM data not available _
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t D a a S h e e t PD PD PD PD PD PD PD PU PD PD CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 39 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Example Application Schematic 10 Example Application Schematic EEPROM 1V8 EEPROM_WP EEPROM_SCL EEPROM_SDA U1 8 7 6 5 VCC WP SCL SDA 1 2 3 4 A0 A1 A2 VSS M24C32-FMB DFN-8 1V5 0603 C3 4u7 L1 22u 0402 C2 15p 0402 C4 22n 0402 C7 15p C8 47n 0402 R6 2R2 0 2 0 4 C9 2u2 0402 VBATT 1V8 1V8 1 2 1 2 1 2 1 2 F1 F2 VOL+
VOL-
VBATT VBATT S1 S2 S3 S4 3 4 3 4 3 4 3 4 2 R2 10k 0 4 0 2 R3 10k 0 4 0 2 R4 10k 0 4 0 D E R D1 E U L B D2 2 R7 1k0 0 4 0 2 R8 0 4 0 470R 0402 C1 100n C5 0402 100n D L H _ R W P 2 R1 0 4 0 2R2 0402 C6 2u2 0 3 9 6 2 1 5 3 0 1 1 1 0 2 3 4 O L _ D D V E R O C _ D D V A N A _ D D V I O D A R _ D D V 8 4 I O D U A _ D D V 4 3 E S N E S _ P M S S D A P _ D D V S D A P _ D D V X L I L _ N G E R V L _ E L B A N E G E R V 1 3 H _ T U O G E R V 3 3 H _ E L B A N E G E R V 4 2
0 O P I 3 2
1 O P I 2 2
2 O P I 9 2 0 D E L 8 2 1 D E L U2 1V5 L2 15nH 0402 C10 15p N U L A B _ 5 V 1 T1 DBF81F107-CSR ANT1 0402 C11 NF DC BAL RF_P ANT UNBAL 2 1 3 6 4 7 8 NC BAL RF_N D N G D N G D N G 5 8 7 Optional Thermistor Configuration 0402 R9 100k Place thermistor close to battery outline 1V8 V_CHARGE R10 0402 100k (1%) AIO1 37 VDD_CHG 0805 C12 4u7 BC6145 QFN BAT_P1 BAT_N1 VBATT 0603 C13 4u7 32 36 VREGIN_H BAT_P 26 RST#
1V8 2 R11 10k 0 4 0 V_CHARGE C20 D Q1 Si1032R-T1-E3 2 0 4 0 220n 2 R13 220k 0 4 0 G S D A P _ R T N C _ S S V 9 4 SPKR_P1 SPKR_N1 MIC_P1 MIC_N1 P _ R K P S 4 P _ R K P S N _ R K P S 3 N _ R K P S N _ C M I 2 N _ C M I P _ C M I 1 P _ C M I I 1 N _ C M I 0402 C23 15p 0402 C24 15p MIC_IN L3 15nH R14 0402 2k2 0402 C26 15p I S A B _ C M I 7 4 I S A B _ C M I 2 R12 1k0 0 4 0 0402 C25 2u2 0402 C21 150n 0402 C22 150n 0402 C18 2u2 F E R _ U A 5 F E R _ O L 5 1 0402 0402 C14 47n C15 22n T U O _ L A T X 4 1 XT1 26MHz I N _ L A T X 3 1 C16 18p 0402 0402 C17 6p8 Serial Flash PIO_3 PIO_20 1V8 0402 C19 100n PIO_23 PIO_11 1V8 U3 VDD 1 6 4 CE SCK SI/SIO0 SO/SIO1 WP/SIO2 HOLD/SIO3 VSS 8 5 2 3 7 SST25WF080 2 R15 NF0 0 4 0402 C27 NF SPI_CLK SPI_CS#
SPI_MISO SPI_MOSI 39 40 41 38 SPI_CLK SPI_CSB SPI_MISO SPI_MOSI SPI_DEBUG_EN 42 SPI_DEBUG_EN PIO[3]
PIO[6]
PIO[7]
PIO[8]
PIO[11]
PIO_3 EEPROM_SCL EEPROM_SDA EEPROM_WP PIO_11 PIO_23/UART_TX PIO_20/UART_RX PIO_23 PIO_20 TEST_EN AIO[1]
AIO[0]
AIO1 AIO0 21 46 45 44 27 19 18 25 16 17 _
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t D a a S h e e t CS-204118-DSP2 Figure 10.1: Example Application Schematic Production Information Cambridge Silicon Radio Limited 2010 This Material is Subject to CSR's Non-disclosure Agreement 3 4
. 9 4 6 5 0 0 0
W T
G Page 40 of 69 11 Electrical Characteristics 11.1 Absolute Maximum Ratings Rating Storage Temperature Core Supply Voltage VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO I/O Voltage VDD_PADS[1:0]
VREGIN_H, VREGENABLE_H and VREGENABLE_L Supply Voltage VREGIN_L BAT_P LED[1:0]
VDD_CHG Other Terminal Voltages VSS - 0.4 VDD + 0.4 11.2 Recommended Operating Conditions Operating Condition Operating Temperature Range(a) Min
-20 VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO Core Supply Voltage I/O Supply Voltage VDD_PADS[1:0]
1.7 3.3 3.6
(a) For radio performance over temperature refer to BC6145 QFN Performance Specification. 1.42 1.50 1.57 Electrical Characteristics Min
-40
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4 Typ 20 Max 105 1.65 3.6 2.7 4.9 4.4 4.4 6.5 Max 70 Unit C V V V V V V V V V V Unit C _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 41 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Electrical Characteristics 11.3 Input/Output Terminal Characteristics Note:
For all I/O terminal characteristics:
VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO at 1.5V unless shown otherwise. VDD_PADS[1:0] at 3.3V unless shown otherwise. Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative. 11.3.1 High-voltage Linear Regulator Output voltage (Iload = 25mA / VREGIN_H = 3.0V) Load regulation (100A < Iload < 25mA ), Vout Normal Operation Input voltage Temperature coefficient Output noise(a) (b) Settling time(a) (c) Output current Minimum load current Low-power Mode (d) Quiescent current (excluding load, Iload < 1mA) 300 ppm/C mV rms Max 4.9 2.05 1 5 50 25
60 Unit V V mV s mA A A Min 2.7 1.80
-300
5 30 11 Typ 1.90 0
50 15 Quiescent current (excluding load, Iload < 100A) 21 A
(a) The regulator output is connected to 47nF pure and 4.7F 2.2 ESR capacitors
(b) Frequency range 100Hz to 100kHz
(c) 1mA to 25mA pulsed load
(d) The regulator is in low-power mode when the IC is in deep sleep mode, or in reset _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 42 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.2 Switch-mode Regulator Switch-mode Regulator Input voltage Output voltage (Iload = 70mA) Temperature coefficient Normal Operation Output ripple Transient settling time(a) Maximum load current Conversion efficiency (Iload = 70mA ) Switching frequency(b) Start-up current limit(c) Low-power Mode (d) Output ripple Transient settling time(e) Maximum load current Minimum load current Electrical Characteristics 250 ppm/C mV rms Max 4.4 1.57 10 50 80
1
700 Unit V V s mA
MHz mA s mA A
mV rms Typ 1.50 1.333 90 50
Min 2.7 1.42
-250 200 30
5 1
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t D a a S h e e t Conversion efficiency (Iload = 1mA ) 80 Switching frequency(f) 50 150 kHz
(a) For step changes in load of 30 to 80mA and 80 to 30mA
(b) Locked to crystal frequency
(c) The current is limited on start-up to prevent excessive stored energy in the filter inductor.
(d) The regulator is in low-power mode when the IC is in deep sleep mode, or in reset.
(e) 100A to 1mA pulsed load
(f) Defines the minimum period between pulses. Pulses are skipped at low current loads. Note:
The external inductor connected to the switch-mode regulator must have an ESR in the range 0.3 to 0.7:
Low ESR < 0.3 causes instability. High ESR > 0.7 derates the maximum current. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 43 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.3 Low-voltage Linear Regulator Output voltage (Iload = 70mA / VREGIN_L = 1.7V) Load regulation (100A < Iload < 90mA ), Vout Load regulation (100A < Iload < 115mA ), Vout Normal Operation Input voltage Temperature coefficient Output noise(a) (b) Settling time(a) (c) Output current Minimum load current Low-power Mode (d) Quiescent current (excluding load, Iload < 1mA) Electrical Characteristics 300 ppm/C mV rms Max 2.70 1.57 1 5 25 50 115 100 150 Unit V V mV mV s mA A A Min 1.80 1.42
-300
5 50 5 Typ 2.00 1.50 0
8 90 Quiescent current (excluding load, Iload < 100A) 15 A
(a) The regulator output is connected to 47nF pure and 4.7F 2.2 ESR capacitors
(b) Frequency range 100Hz to 100kHz
(c) 1mA to 115mA pulsed load
(d) The regulator is in low-power mode when the IC is in deep sleep mode, or in reset _
S N Q R n c k
t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 44 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.4 Battery Charger Battery Charger Input voltage Charging Mode (BAT_P rising to 4.2V) Supply current(a) Battery trickle charge current(b) (c) Maximum battery fast charge current (I-CTRL = 15)(c) (d) Minimum battery fast charge current (I-CTRL = 0)(c) (d) Fast charge step size
(I-CTRL = 0 to 15) Trickle charge voltage threshold Headroom(e) > 0.7V Headroom = 0.3V Headroom > 0.7V Headroom = 0.3V Spread 17%
Float voltage (with correct trim value set), VFLOAT (f) 4.17 Float voltage trim step size(f) Battery charge termination current, % of fast charge current
(a) Current into VDD_CHG; does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) BAT_P < Float voltage
(c) The charge current is set in 16 equally spaced steps
(d) Trickle charge threshold < BAT_P < Float voltage
(e) Where headroom = VDD_CHG - BAT_P firmware during the boot-up sequence. Supply current(a) Battery current Battery recharge hysteresis(b)
(a) Current into VDD_CHG; does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) Hysteresis of (VFLOAT - BAT_P) for charging to restart Min 4.5 Min
5 Min
100 Electrical Characteristics Max 6.5 Max 6
4.23 20 Unit V Unit mA mA mA mA mA mA mA V V mV
2
200 mA A mV Typ
Typ 4.5 4 150 120 40 35 6.3 2.9 4.2 50 10 Typ 1.5
-5
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t D a a S h e e t
(f) The float voltage is adjusted in 15 steps. The trim setting is determined in production test and must be loaded into the battery charger by Standby Mode (BAT_P falling from 4.2V) Max Unit CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 45 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Shutdown Mode (VDD_CHG too low or disabled by firmware) Min Max Unit VDD_CHG under-voltage threshold VDD_CHG - BAT_P lockout threshold VDD_CHG rising VDD_CHG falling VDD_CHG rising VDD_CHG falling Electrical Characteristics
2 0 Max 1.30 1.35 0.15 0.95 0.80 0.28 0.95 0.80 0.28 mA A Unit V V V V V V V V V V V V V Typ 3.90 3.70 0.22 0.17 1.5
Typ 1.25 1.30 0.10
-1 Min 1.13 1.20 0.05 0.50 0.35 0.14 0.50 0.35 0.14 Min Typ Max Unit _
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t D a a S h e e t Supply current Battery current 11.3.5 Reset Power-on Reset VDD_CORE falling threshold VDD_CORE rising threshold Hysteresis 11.3.6 Regulator Enable Switching Threshold VREGENABLE_H Rising threshold Falling threshold Hysteresis VREGENABLE_L Rising threshold Falling threshold Hysteresis CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 46 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.7 Digital Terminals Supply Voltage Levels VDDPRE Pre-driver supply voltage VDD I/O supply voltage (post-driver) Full specification Reduced specification Input Voltage Levels VIL input logic level low VIH input logic level high VSCHMITT Schmitt voltage Typ Max Unit 0.25 x VDD 0.625 x VDD VDD + 0.3 0.25 x VDD 0.625 x VDD Output Voltage Levels Typ Max Unit VOL output logic level low, lOL = 4.0mA VOH output logic level high, lOH = -4.0mA 0.75 x VDD Electrical Characteristics Max Unit 1.6 3.6 3.0 0.125 VDD Max 100 100
-10 100
-0.2 5.0 5.0 2 2 50 50 V V V V V V V V Unit nA nA A A A A pF Unit M M k k Typ 1.5 3.3 Typ 0 0
-40 40
-1.0 1.0
Typ Max Min 1.4 3.0 1.7 Min
-0.3 Min 0 Min
-100
-100
-100 10
-5
-0.2 1.0 Min 0.5 0.5 10 10 _
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t D a a S h e e t Input and Tristate Currents Ii input leakage current at Vin = VDD or 0V Ioz tristate output leakage current at Vo = VDD or 0V With strong pull-up With strong pull-down With weak pull-up With weak pull-down CI input capacitance Resistive Strength Rpuw weak pull-up strength at VDD - 0.2V Rpdw weak pull-down strength at 0.2V Rpus strong pull-up strength at VDD - 0.2V Rpds strong pull-down strength at 0.2V CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 47 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.8 LED Driver Pads LED Driver Pads Off current On resistance VPAD < 0.5V On resistance, pad enabled by battery charger VPAD < 0.5V 11.3.9 Auxiliary ADC Auxiliary ADC Resolution Input voltage range(a) Accuracy
(Guaranteed monotonic) Offset Gain error Input bandwidth Conversion time Sample rate(b) Min Typ Max Electrical Characteristics Unit A Unit Bits LSB LSB LSB
kHz s 2 33 50 Max 10 1 1 1
0.8 700 Samples/
s 1 20 20
100 2.5
0
-1 0
-1
-0.8 Min Typ VDD_ANA V INL DNL
(a) LSB size = VDD_ANA/1023
(b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 48 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Parameter Conditions Min Typ Max 11.3.10 Mono Codec: Analogue to Digital Converter Analogue to Digital Converter Resolution Input Sample Rate, Fsample
Signal to Noise Ratio, SNR fin = 1kHz B/W = 20Hz20kHz A-Weighted THD+N < 1%
150mVpk-pk input Fsample 8kHz 11.025kHz 16kHz 22.050kHz 32kHz Digital Gain Digital Gain Resolution = 1/32 Analogue Gain Analogue Gain Resolution = 3dB Input full scale at maximum gain (differential) Input full scale at minimum gain (differential) 3dB Bandwidth Microphone mode input impedance THD+N (microphone input) @ 30mV rms input
8
-24
-3 Electrical Characteristics
79 77 76 76 75
-3 4 800 20 6.0 0.04 16 32
21.5 42 Unit Bits kHz dB dB dB dB dB dB dB mV rms mV rms kHz k
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 49 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.11 Mono Codec: Digital to Analogue Converter Parameter Conditions Min Typ Max Digital to Analogue Converter Resolution Output Sample Rate, Fsample
Signal to Noise Ratio, SNR fin = 1kHz B/W = 20Hz20kHz A-Weighted THD+N < 0.01%
0dBFS signal Load = 100k Fsample 8kHz 11.025kHz 16kHz 22.050kHz 32kHz Digital Gain Digital Gain Resolution = 1/32
-24 Analogue Gain Analogue Gain Resolution = 3dB Electrical Characteristics 95 95 95 95 95
16 32
21.5
-21 500 0.01 0.1
Unit Bits kHz dB dB dB dB dB dB dB pF
dB _
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t D a a S h e e t
8
0
Output voltage full-scale swing (differential) 750 mV rms Resistive 16(8) O.C.(a) Capacitive Allowed Load THD+N 100k load THD+N 16 load SNR (Load = 16, 0dBFS input relative to digital silence) 95
(a) CSR recommends 100 as a practical maximum allowed load CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 50 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 11.3.12 Clocks Clock Source Crystal Oscillator Crystal frequency(a) Digital trim range(b) Trim step size(b) Transconductance Negative resistance(c)
(a) Integer multiple of 250kHz Electrical Characteristics Min Typ Max Unit 16 5.0
2.0 870 26 6.2 0.1
26 8.0
1500 2400 MHz pF pF mS
(b) The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.
(c) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF. 11.4 ESD Protection Apply ESD static handling precautions during manufacturing. Table 11.1 shows the ESD handling maximum ratings. Condition Note Class Max Rating Human Body Model Contact Discharge per JEDEC EIA/JESD22A114 Machine Model Contact Discharge per JEDEC EIA/JESD22A115 Charged Device Model Contact Discharge per JEDEC EIA/JESD22C101 ESD_HAND_HBM 2000V (all pins) ESD_HAND_MM 200V (all pins) ESD_HAND_CDM 200V (all pins) 2 B II Table 11.1: ESD Handling Ratings _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 51 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information DUT Role Connection Packet Type Packet Size Unit Average Current 12 Power Consumption Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave SCO eSCO eSCO eSCO SCO 1-mic CVC eSCO 1-mic CVC eSCO 1-mic CVC ACL ACL ACL Sniff = 100ms Sniff = 500ms Sniff = 1280ms SBC low quality, no sniff SBC low quality, sniff = 62.5ms SBC high quality, no sniff SBC high quality, sniff = 62.5ms Master SCO Master eSCO Master eSCO Master eSCO Master SCO 1-mic CVC Master eSCO 1-mic CVC Master eSCO 1-mic CVC Master ACL Sniff = 100ms HV3 EV3 2EV3 2EV3 HV3 2EV3 2EV3
HV3 EV3 2EV3 2EV3 HV3 2EV3 2EV3
30 30 60 30 30 60 30
30 30 60 30 30 60 30
Power Consumption 9.8 11.3 7.9 11 12.3 10.4 13.6 0.59 0.25 0.16 11.4 7.9 13 10 9.9 10.2 7.5 9.7 12.5 10 12.2 0.71 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 52 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Power Consumption Average Current 0.26 0.16 10 8 12.8 10.1 Unit mA mA mA mA mA mA DUT Role Connection Packet Type Packet Size Master Master ACL ACL Sniff = 500ms Sniff = 1280ms Master SBC low quality, no sniff Master SBC low quality, sniff = 62.5ms Master SBC high quality, no sniff Master SBC high quality, sniff = 62.5ms Note:
Current consumption values are taken with:
BAT_P pin for switch-mode regulator = 3.7V RF TX power set to 0dBm No RF retransmissions in case of eSCO Microphones and speakers disconnected, with internal microphone bias circuit set to minimum current level Audio gateway transmits silence when SCO/eSCO channel is open LEDs disconnected _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 53 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information CSR Green Semiconductor Products and RoHS Compliance 13 CSR Green Semiconductor Products and RoHS Compliance CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:
Restriction on Hazardous Substances directive guidelines in the EU RoHS Directive 2002/95/EC. This includes compliance with the requirements for Deca BDE, as per removal of exemption, implementation date 01-Jul-08 EU REACH, Regulation (EC) No 1907/2006:
List of substances subject to authorisation (Annex XIV) Restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (Annex XVII). This Annex now includes requirements that were contained within EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not limited to, the control of use of Perfluorooctane sulfonates (PFOS). Substances identified on candidate list as Substances of Very High Concern (SVHC), 38 substances as per update published 18 June 2010. EU Commission Decision 2009/251/EC EU Packaging and Packaging Waste, Directive 94/62/EC Montreal Protocol on substances that deplete the ozone layer Products containing dimethylfumarate (DMF) are not placed or made available on the market. Additionally, as shown in Table 13.1, CSR Green semiconductor products are free from bromine, chlorine or antimony trioxide and other hazardous chemicals. Material Cadmium (Cd) Lead (Pb) Mercury (Hg) Hexavalent-Chromium (Cr VI) Polybrominated biphenyls (PBB) Bromine, Chlorine Antimony Trioxide (Sb2O3) Red phosphorous Beryllium Oxide Polychlorinated napthalenes (PCN) Polychlorinated terphenyls (PCT) Polychlorinated biphenyls (PCB) Polybrominated diphenyl ethers (PBDE) - including Decabromodiphenyl ether (Deca BDE) 1000ppm Chlorinated paraffin (including short chain chlorinated paraffins carbon chain length 10-13 and medium chain chlorinated paraffins carbon chain length 14-17) _
S N Q R n c k
t D a a S h e e t Maximum Allowable Amount 100ppm 1000ppm (solder), 100pm (plastic) 900ppm, <1500ppm combined 1000ppm 1000ppm 1000ppm 900ppm 1000ppm Banned Banned Banned Banned Banned CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 54 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information CSR Green Semiconductor Products and RoHS Compliance Material Polyvinyl Chloride (PVC) Formaldehyde Asbestos Phthalates Radioactive substances Tributyl tin (TBT) / Triphenyl tin (TPT) / Tributyl Tin Oxide (TBTO) Table 13.1: Chemical Limits for Green Semiconductor Products Products and shipment packaging are marked and labelled with applicable environmental marking symbols in accordance with relevant regulatory requirements. CSR has defined this Green standard based on current regulatory and customer requirements. For more information contact product.compliance@csr.com. Maximum Allowable Amount Banned Banned in wooden products Not intentionally introduced Not intentionally introduced Not intentionally introduced -
reportable Not intentionally introduced _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 55 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Software 14 Software BC6145 QFN:
Is supplied with on-chip Bluetooth v3.0 specification qualified HCI stack firmware Is supplied with on-chip BC6145 QFN DSP Mono Headset Solution, which includes 6th generation 1-mic CVC audio enhancements Can be shipped with CSRs BC6145 QFN DSP mono headset solution development kit for BC6145 QFN, order code DKBC6145100371A The BC6145 QFN software architecture enables Bluetooth processing and the application program to run on the internal RISC MCU, and the audio enhancements on the Kalimba DSP. 14.1 BC6145 QFN DSP Mono Headset Solution The CSR mono headset ROM software supports:
6th generation 1-mic CVC audio enhancements CSR's Hear and Be Heard bidirectional noise reduction feature mSBC wideband speech codec A2DP v1.2 HFP v1.5 and HSP v1.2 Bluetooth v3.0 specification is supported in the ROM software Secure simple pairing Proximity pairing (headset-initiated pairing) for greatly simplifying the out-of-box pairing process, for more information see Section 14.1.7 For connection to more than 1 mobile phone, advanced multipoint is supported. This enables a user to take calls from a work and personal phone or a work phone and a VoIP dongle for Skype users. This has minimal impact on power consumption and is easy to configure. Most of the CSR mono headset ROM software features are configured on the BC6145 QFN using the Headset Configurator tool available from www.csrsupport.com/MonoHeadsetSolutions. The tool reads and writes headset configurations directly to the EEPROM or alternatively to a PSR file. Configurable headset features include:
Bluetooth v3.0 specification features Reconnection policies, e.g. reconnect on power-on Audio features, including default volumes Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1] for last number redial LED indications for states, e.g. headset connected, and events, e.g. power on Indication tones for events and ringtones HFP v1.5 supported features Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc. Advanced Multipoint settings The BC6145 QFN DSP mono headset solution has undergone extensive interoperability testing to ensure it works with the majority of phones on the market 14.1.1 Hear and Be Heard CSR's Hear and Be Heard is a bidirectional noise reduction feature that ensures increased speech clarity in preparation for improving intelligibility through spectral enhancement for the user and the person they are speaking to. 14.1.2 A2DP Streaming on a Mono Headset BC6145 QFN enables an A2DP v1.2 stream connection to the headset while a call is not in progress. This enables high-quality mono music streaming where the left and right stereo streams are mixed. Advanced Multipoint enables the connection of 2 devices to BC6145 QFN at the same time, examples include:
14.1.3 Advanced Multipoint Support 2 phones connected to a BC6145 QFN headset Phone and a VoIP dongle connected to a headset CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 56 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
S N Q R n c k
t D a a S h e e t Software The BC6145 QFN DSP mono headset solution:
Supports a maximum of 2 connections (either HFP or HSP) Enables multiple-call handling from both devices at the same time Treats all headset buttons:
During a call from 1 device, as if there is 1 device connected During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (three-
way calling) 14.1.4 A2DP Multipoint Support A2DP multipoint support enables the connection of 2 A2DP source devices to BC6145 QFN at the same time, examples include:
2 A2DP-capable phones connected to a BC6145 QFN headset A2DP-capable phone and an A2DP-only source device, e.g. a PC or an iPod touch The BC6145 QFN DSP mono headset solution enables:
Music streaming from either of the connected A2DP source devices where the music player is controlled on the source device Advanced HFP multipoint functions to interrupt music streaming for calls, and resumes music streaming on the completion of the calls 14.1.5 Programmable Audio Prompts BC6145 QFN enables a user to configure and load pre-programmed audio prompts from:
An external EEPROM, in this implementation the prompts are stored in the same EEPROM as the PS Keys, see Figure 14.1. A larger EEPROM is necessary for programmable audio prompts. This implementation supports EEPROMs up to 512Kb. An EEPROM of 512Kb enables approximately 15 seconds of audio storage. An external SPI flash, in this implementation the prompts are stored in SPI flash and the EEPROM is for PS Keys, see Figure 14.2. The programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone indications. A programmable audio prompt is assigned to any user event in place of a standard tone. Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-
defined higher quality ring tones/indications, e.g. custom power on/off tones. The Headset Configurator tool can generate the content for the programmable audio prompts from standard WAV audio files. The tool also enables the user to configure which prompts are assigned to which user events. Section 7.3 describes the IC interface to the external EEPROM and Section 7.4 describes the SPI flash interface. BC6145 I2C EEPROM PS Keys Configuration Patches Programmable Audio Prompts Figure 14.1: Programmable Audio Prompts in External IC EEPROM _
S N Q R n c k
t D a a S h e e t 1
. 1
. 0 5 6 5 0 0 0
W T
G CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 57 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information EEPROM PS Keys Configuration I2C Patches BC6145 SPI Flash SPI Programmable Audio Prompts Software 2
. 1
. 5 1 4 6 0 0 0
W T
G Figure 14.2: Programmable Audio Prompts in External SPI Flash with External IC EEPROM for PS Keys 14.1.6 CSRs Intelligent Power Management IPM extends the available talk time of a BC6145 QFN-based headset, by automatically reducing the audio processing performed by CVC at a series of low battery capacity thresholds. The Headset Configurator tool configures the following IPM features:
IPM enable/disable The battery capacity that engages IPM A user-action to enable or disable the IPM is also configurable. If engaged, CVC processing reduces automatically on reaching the preset battery capacity. Once the audio is terminated, the DSP shuts down to achieve maximum power savings before the next call. IPM resets when recharging the headset. The talk time extension depends on:
The battery size The battery condition The threshold capacity configured for the IPM to engage 14.1.7 Proximity Pairing Proximity pairing is headset-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables the headset to find the closest discoverable phone. The headset then initiates the pairing activity and the user simply has to accept the incoming pairing invitation on the phone. This means that the phone-user does not have to hunt through phone menus to pair with the new headset. Depending on the phone UI:
For a Bluetooth v2.0 phone the headset pairing is with a PIN code For a Bluetooth v2.1 (or above) phone the headset pairing is without a PIN code Proximity pairing is based on finding and pairing with the closest phone. To do this, the headset finds the loudest phone by carrying out RSSI power threshold measurements. The loudest phone is the one with the largest RSSI power threshold measurement, and it is defined as the closest device. The headset then attempts to pair with and connect to this device. Proximity pairing is configurable using the Headset Configurator tool available from www.csrsupport.com/
MonoHeadsetSolutions. 14.1.8 Proximity Connection Proximity connection is an extension to proximity pairing, see Section 14.1.7. It enables the headsetuser to take advantage of the proximity of devices each time the headset powers up and not just during a first time pairing event. Proximity connection enables a user with multiple handsets to easily connect to the closest discoverable phone by comparing the proximity of devices to the headset at power-on to the list of previously paired devices. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 58 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Software Proximity connection speeds up the headset connection process. It requires the headset to initiate a SLC connection to the nearest device first and combines this with the headset's storage of the last 8 paired/connected devices. Using proximity connection means functions like power on into an incoming call operate equally well for the most recently paired or connected device, as well as the least recently paired or connected device. 14.2 6th Generation 1-mic CVC Audio Enhancements 1-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms developed to ensure easy design and build of echo and noisecancelling headset products. CVC enables greater acoustic design flexibility by incorporating software to compensate for cost-optimised microphonetospeaker coupling and placement. CVC-enabled headsets operate in a wide variety of acoustic environments. Sophisticated noise suppression technology reduces the impact of noise in the transmission channel. Using intelligent volume control and intelligibility improvements, the receive channel is also enhanced based on the acoustic noise in the listener's environment. The 6th generation CVC provides 3 new major features:
A high performance Wind Noise Reduction module provides significant reduction of both front and side wind noise. This uses a very low-power algorithm which automatically cuts in only on the detection of wind noise. A 16kHz sample rate for full compliance across the suite of DSP algorithms Frequency enhanced speech intelligibility 1-mic CVC includes a tuning tool enabling the developer to easily adapt CVC with different audio configurations and tuning parameters. The tool provides real-time system statistics with immediate feedback enabling designers to quickly investigate the effect of changes. Figure 14.3 shows the functional block diagram of CSRs proprietary 1-mic CVC DSP solution for a single-
microphone headset product. Mic Gain Wind Noise Reduction Noise Suppression Acoustic Echo Canceller Comfort Noise Equaliser AGC Side Tone NDVC Auxiliary Stream Mix DAC Clipper AGC Equaliser Adaptive Equaliser Noise Suppression Packet Loss Concealment Section 14.2.1 to Section 14.2.12 describe the audio processing functions provided within CVC. Figure 14.3: 1-mic CVC Block Diagram 14.2.1 Noise Suppression The noise suppression block is implemented in both signal paths. It is completely independent and is individually tuned. Noise suppression is a sub-band stationary / quasi-stationary noise suppression algorithm that uses the temporal characteristics of speech and noise to remove the noise from the composite signal while maximising speech quality. The current implementation has the capability to improve the SNR by > 20dB. 14.2.2 Wind Noise Reduction The wind noise algorithm achieves excellent wind noise reduction with very low power overhead, which has a negligible impact on battery life. The wind noise capability operates in the noise suppression block in the transmit path and dynamically detects and engages when wind noise is present. SNR improvements depend on wind direction, speech and microphone placement. Improvements of up to 32dB are achievable using the DSP module. CVC wind noise performance is further improved by suitable mechanical baffling of the microphone which is optimised during the tuning process. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 59 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t l B u e t o o t h v 3
. 0 R a d o i 1
. 1
. 1 5 6 5 0 0 0
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G Software 14.2.3 Acoustic Echo Cancellation The AEC includes:
A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to the microphone input A non-linear processing function that applies narrowband and wideband attenuation adaptively as a result of residual echo present after the linear filter Creates a spectrally and temporally consistent noise floor for the far-end listener Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when attenuation is applied by the non-linear processing of the AEC Have independent equalisation modules provided in the send and receive signal paths:
Each module comprises of 5 bands of equalisation using cascaded 2nd order IIR filters Are fully configurable using a graphical tuning tool Provide static compensation for the frequency response of transducers in the system 14.2.4 Comfort Noise Generator The CNG:
14.2.5 Equalisation The equalisation filters:
14.2.6 Automatic Gain Control The AGC block attempts to:
Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness Reduce distortion due to clipping Reduce amplitude variance observed from different users, phones, and networks Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also provides the subsequent processing block a larger amplitude signal to process. The behaviour of the AGC differs from a dynamic range audio compressor. The convergence time for the AGC is much slower to reduce the non-
linear distortion. 14.2.7 Packet Loss Concealment Bit errors and packet loss can occur in the Bluetooth transmission due to a variety of reasons, e.g. Wi-Fi interference or RF signal degradation due to distance or physical objects. As a result of these errors, the user hears glitches referred to as pops and clicks in the audio stream. The PLC block improves the receive path audio quality in the presence of bit and packet errors within the Bluetooth link by using a variety of techniques such as pitch-based waveform substitution. The PLC significantly improves dealing with bit errors, using the BFI output from the firmware. The DSP calculates an average BER and selectively applies the PLC to the incoming data. This optimises audio quality for a variety of bit errors and packet loss conditions. The PLC is enabled in all modes. 14.2.8 Adaptive Equalisation The adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of nearend noise by altering the spectral shape of the receive path signal while maintaining the overall power level. The adaptive equaliser can also compensate for variations in voice transmission channels. 14.2.9 Auxiliary Stream Mix The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice prompts with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents any speech from being lost. 14.2.10 Clipper The clipper block intentionally limits the amplitude of the receive signal prior to the reference input of the AEC to more accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier, and the loudspeaker. This processing block can significantly improve the echo performance in cost-optimised loudspeakers. CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 60 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Software 14.2.11 Noise Dependent Volume Control The NDVC block improves the intelligibility of the receive path signal by increasing the analogue DAC gain value based on the send noise estimate from the send path noise suppression block. As the send noise estimate increases, the NDVC algorithm increases the analogue DAC gain value. The NDVC uses hysteresis to minimise the artefacts generated by rapidly adjusting the DAC gain due to the fluctuation in the environmental noise. 14.2.12 Fixed Gains There are fixed gain controls at all inputs and outputs to the system so that levels are set according to hardware constraints and industry standards. 14.2.13 Frequency Enhanced Speech Intelligibility Frequency enhanced speech intelligibility on the BC6145 QFN works with the adaptive equalisation module, see Section 14.2.8, and the NDVC module, see Section 14.2.11, to enhance intelligibility in the presence of noise. This combination of functions creates higher frequency information, which in the presence of noise, makes it much easier for the listener to differentiate between consonant pairs, therefore improving intelligibility. This also reduces listener fatigue as it requires less concentration effort from the user. This can lead to improved dual-tasking performance. 14.3 BC6145 QFN DSP Mono Headset Solution Development Kit The development kit includes an evaluation board, music and voice dongle, and necessary interface adapters and cables. In conjunction with other supporting utilities, the development kit provides support for the evaluation and development of a BC6145 QFN mono headset solution. _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 61 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Ordering Information 15 Ordering Information Package Type Size Shipment Method Order Number BC6145 QFN DSP Mono Headset Solution QFN 48-lead 7 x 7 x 0.9mm,
(Green) 0.5mm pitch Tape and reel BC6145A04IQQBR Device Note:
BC6145 QFN is a ROM-based device where the product code has the form BC6145Axx. Axx is the specific ROM-variant, A04 is the ROM-variant for BC6145 QFN DSP Mono Headset Solution. Minimum order quantity is 2kpcs taped and reeled. Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative. To contact a CSR representative, email sales@csr.com or go to www.csr.com/contacts. 15.1 Development Kit Ordering Information Description Order Number BC6145 QFN DSP Mono Headset Solution Development Kit DKBC6145100371A _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 62 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Tape and Reel Information 16 Tape and Reel Information For tape and reel packing and labelling see IC Packing and Labelling Specification. 16.1 Tape Orientation Figure 16.1 shows the BC6145 QFN packing tape orientation. Pin 1 _
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t D a a S h e e t
. 2 2 2 1 8 2 0 0 0
W T
G User Direction of Feed Figure 16.1: Tape Orientation CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 63 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Tape and Reel Information 16.2 Tape Dimensions Figure 16.2 shows the dimensions of the tape for the BC6145 QFN. 4.0 See Note 1 0.25 0.30 0.05 R0.3 MAX 2.0 See Note 6 Bo R0.25 1.75 A 7.5 See Note 6 Ko Ao A Section A-A 12.0 Figure 16.2: Tape Dimensions A0 B0 K0 Unit Notes 7.25 7.25 1.10 mm 10 sprocket hole pitch cumulative tolerance 0.2 1. 2. Camber not to exceed 1mm in 100mm 3. Material: PS + C 4. A0 and B0 measured as indicated 5. K0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole
. 2 4 1 1 8 2 0 0 0
W T
G _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 64 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information 16.3 Reel Information Tape and Reel Information ATTENTION Electrostatic Sensitive Devices Safe Handling Required
"A"
a(rim height) 102.0 2.0 Detail "A"
330.0 2.0 88 REF M I N
"b" REF 2.0 0.5 6 PS Detail "B"
6 PS
(MEASURED AT HUB)
(MEASURED AT HUB) W1 W2 Figure 16.3: Reel Dimensions Package Type a b W1 W2 Max Units Nominal Hub Width
(Tape Width) 7 x 7 x 0.9mm QFN 16 4.5 98.0 19.1 mm 16.4
(3.0/-0.2) 16.4 Moisture Sensitivity Level BC6145 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020. 20.2 13.0 +0.5
-0.2 2
. 4 2 9 7 2 0 0 0
W T
G _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 65 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Document References Bluetooth Specification Version 3.0 + HS Version 3.0 + HS [Vol 0 to Vol 5], 21 April 2009 17 Document References Document Reference, Date BC6145 QFN Performance Specification CS-204120-SP BCSW-CVC-HS-4-5-x Product Data Sheet CS-128313-DS BlueCore5 Charger Description and Calibration Procedure Application Note CS-113282-AN Enhancing Microphone Bias Performance in Headset Designs using BlueVox2 Application Note CS-121678-AN Environmental Compliance Statement for CSR Green Semiconductor Products CB-001036-ST IC Packing and Labelling Specification CS-112584-SP Selection of IC EEPROMS for Use with BlueCore CS-101518-AN Typical Solder Reflow Profile for Lead-free Device CS-116434-AN _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 66 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Terms and Definitions Terms and Definitions Bluetooth Set of technologies providing audio and data transfer over short-range radio connections Term
-law A-law A2DP AC ACL ADC AEC AFH AG AGC AIO ALU B/W BER BFI BIST BMC CNG codec CRC CSR CVC CVSD DAC DC DNL DSP DUT e.g. EDR EIA eSCO ESD ESR FEC FET FSK HCI HEC Definition Audio companding standard (G.711) Audio companding standard (G.711) Advanced Audio Distribution Profile Alternating Current Asynchronous Connection-oriented Analogue to Digital Converter Acoustic Echo Cancellation Adaptive Frequency Hopping Audio Gateway Automatic Gain Control Analogue Input/Output Arithmetic logic unit BandWidth Bit Error Rate Bad Frame Indicator Built-In Self-Test Burst Mode Controller Comfort Noise Generation Coder decoder Cyclic Redundancy Check Cambridge Silicon Radio Clear Voice Capture Digital Signal Processor Device Under Test exempli gratia, for example Enhanced Data Rate Electronic Industries Alliance Extended SCO Electrostatic Discharge Equivalent Series Resistance Forward Error Correction Field Effect Transistor Frequency Shift Keying Host Controller Interface Header Error Check Correction Continuous Variable Slope Delta Modulation Digital to Analogue Converter Direct Current Differential Non Linearity (ADC accuracy parameter) EEPROM Electrically Erasable Programmable Read Only Memory CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 67 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information _
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t D a a S h e e t Terms and Definitions Definition Hands-Free Profile HeadSet Profile Input/Output Integrated Circuit Inter-Integrated Circuit Interface Intermediate Frequency Infinite Impulse Response (filter) Integral Non Linearity (ADC accuracy parameter) See www.ipc.org Intelligent Power Management In-Phase and Quadrature Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association) An open platform DSP co-processor, enabling support of enhanced audio applications, such as echo and noise suppression, and file compression / decompression Kilobit An inductor (L) and capacitor (C) network Light-Emitting Diode Low Noise Amplifier Least-Significant Bit (or Byte) Medium Access Control Multiplier and ACcumulator MicroController Unit Million Instructions Per Second Master In Slave Out Memory Management Unit modified Sub-Band Coding Noise Dependent Volume Control Non Solder Mask Defined Power Amplifier Personal Computer Printed Circuit Board Pulse Code Modulation Pull-down Packet Loss Concealment Public Limited Company parts per million Persistent Store Key Power Supply Rejection Ratio Pull-up Quad-Flat No-lead Random Access Memory Personal Identification Number Programmable Input/Output, also known as general purpose I/O _
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t D a a S h e e t Term HFP HSP IC I/O IC IF IIR INL IPC IPM IQ JEDEC Kalimba Kb LC LED LNA LSB MAC MAC MCU MIPS MISO MMU mSBC NDVC NSMD PA PC PCB PCM PD PIN PIO PLC plc ppm PS Key PSRR PU QFN RAM CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 68 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information Terms and Definitions Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/EC) Term RC RF RISC RoHS ROM RSSI RX SCO SIG SLC SNR SPI SPL THD+N TX UART UI VCO VM VoIP Wi-Fi XTAL Definition Resistor Capacitor Radio Frequency Reduced Instruction Set Computer Read Only Memory Received Signal Strength Indication Receive or Receiver Synchronous Connection-Oriented
(Bluetooth) Special Interest Group Service Level Connection Signal-to-Noise Ratio Serial Peripheral Interface Sound Pressure Level Total Harmonic Distortion and Noise Transmit or Transmitter Universal Asynchronous Receiver Transmitter User Interface Voltage Controlled Oscillator Virtual Machine Voice over Internet Protocol Wireless Fidelity (IEEE 802.11 wireless networking) Crystal _
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t D a a S h e e t CS-204118-DSP2 Cambridge Silicon Radio Limited 2010 Page 69 of 69 This Material is Subject to CSR's Non-disclosure Agreement Production Information
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2013-10-17 | 2402 ~ 2480 | DXX - Part 15 Low Power Communication Device Transmitter | Original Equipment |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 | Effective |
2013-10-17
|
||||
1 | Applicant's complete, legal business name |
Protop International Inc.
|
||||
1 | FCC Registration Number (FRN) |
0022960918
|
||||
1 | Physical Address |
10F-8, NO.237, Sec. 1, Datong Rd., Xizhi Dist.
|
||||
1 |
New Taipei City
|
|||||
1 |
Taiwan
|
|||||
app s | TCB Information | |||||
1 | TCB Application Email Address |
T******@intertek.com
|
||||
1 | TCB Scope |
A2: Low Power Transmitters (except Spread Spectrum) and radar detectors operating above 1 GHz
|
||||
app s | FCC ID | |||||
1 | Grantee Code |
2AAYX
|
||||
1 | Equipment Product Code |
9411
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 | Name |
Y**** D******
|
||||
1 | Title |
Vice President
|
||||
1 | Telephone Number |
886-2********
|
||||
1 | Fax Number |
886-2********
|
||||
1 |
y******@protop4me.com.tw
|
|||||
app s | Technical Contact | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
T******** C********
|
||||
1 | Physical Address |
2/F., Garment Centre
|
||||
1 |
Kowloon
|
|||||
1 |
Hong Kong
|
|||||
1 | Telephone Number |
(852)********
|
||||
1 | Fax Number |
(852)********
|
||||
1 |
t******@intertek.com
|
|||||
app s | Non Technical Contact | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
T******** C****
|
||||
1 | Physical Address |
2/F., Garment Centre
|
||||
1 |
Kowloon
|
|||||
1 |
Hong Kong
|
|||||
1 | Telephone Number |
(852)********
|
||||
1 | Fax Number |
(852)********
|
||||
1 |
t******@intertek.com
|
|||||
app s | Confidentiality (long or short term) | |||||
1 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
1 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | No | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 | Equipment Class | DXX - Part 15 Low Power Communication Device Transmitter | ||||
1 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Mini Bluetooth Retro Phone | ||||
1 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 | Modular Equipment Type | Does not apply | ||||
1 | Purpose / Application is for | Original Equipment | ||||
1 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | No | ||||
1 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 | Firm Name |
Intertek Testing Services Hong Kong Ltd.
|
||||
1 | Name |
J****** H********
|
||||
1 | Telephone Number |
85221********
|
||||
1 | Fax Number |
85278********
|
||||
1 |
j******@intertek.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | 2402.00000000 | 2480.00000000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC