FCC ID: 2ASEO-HM-BT4531 Bluetooth Module

CMT4531 CMT453x Bluetooth Low Energy wireless SoC Family Datasheet CMT453x series use 32-bit ARM Cortex-M0 core, support BLE 5.1 and SIG Mesh, and feature a frequency up to 64 MHz, 4.2 mA radio transmit current, 3.8 mA radio receive current, +6 dBm maximum transmitting power, and -96 dBm @BLE 1 Mbps RX sensitivity. Key Features CPU Core LSE: 32.768 KHz low speed external crystal 32-bit ARM Cortex-M0 core HSI: high speed internal RC 64 MHz Frequency up to 64 MHz Storage 256 KB Flash 48 KB SRAM LSI: low speed internal RC 32 KHz Support one clock output; different clock output can be configured; clock can be output after divided by four. Power Dissipation Reset Radio receive current: 3.8 mA@3.3 V Power-on/off/external pin reset Radio transmit current: 4.2 mA @0 dBm/3.3 V Watchdog reset Sleep mode (48 KB RAM retention): 1.4 Communications Interface A@3 V 2 USART interfaces, with rate up to 4 Mbps PD mode: 130 nA

(configurable as ISO7816, IrDA, LIN) RF Specification 1 LPUART interface, featuring low-power RX sensitivity: -96 dBm @BLE 1 Mbps dissipation, supporting communication rate up RX sensitivity: -93 dBm @BLE 2 Mbps to 9,600 bps and low-power wakeup in Sleep Power of programmable transmitter: up to +6 mode dBm 2 SPI interfaces, with rate up to 16 MHz, Single end antenna master/slave configurable, supporting I2S Clock 1 I2C interface, with rate up to 1 MHz, HSE: 32 MHz high speed external crystal master/slave configurable 1 / 57 www.hoperf.com CMT4531 Counter 1 16-bit advanced counter, supporting functions like input capture, output compare, 21 GPIO, supporting multiplexing 1 high speed 5-channel DMA controller 1 IR transmission controller, supporting all PWM output, and quadrature encoder input; 4 infrared remote control protocols independent channels, 3 of which support 6 1 KEYSCAN module, where 8/10/13 GPIOs complementary PWM outputs support 44/65/104 key functions respectively 1 16-bit general-purpose counter, supporting RTC real-time clock, supporting perpetual functions like input capture, output compare, calendar (that can identify leap years), alarm PWM output, and monopulse output, with 4 events, and periodic wakeup independent channels Support hardware CRC16 and CRC32 1 16-bit basic counter operations 1 24-bit system timer Operating Conditions 1 7-bit window watchdog (WWDG) Operating voltage: 1.8 V~3.6 V 1 12-bit independent watchdog (IWDG) Operating temperature: -40C~85C Analog Interface ESD: 2 KV (HBM) 1 10-bit 1.33 Msps ADC (configurable as 16-

Package bit 16 Ksps), supporting 5 external single-

QFN32 (4 mm 4 mm) ended channels, 1 differential MIC channel, 2 Ordering information internal channels Built-in PGA up to 128x MIC BIAS voltage, adjustable between 1.6 V and 2.3 V Series Part Number CMT453x CMT4531KCQ6-1 2 / 57 www.hoperf.com CMT4531 Liability Disclaimer Shenzhen Hope Microelectronics Co., Ltd reserves the right to make changes without further notice to the product to improve reliability, function or design. Shenzhen Hope Microelectronics Co., Ltd does not assume any liability arising out of the application or use of any product or circuits described herein. Life Support Applications Shenzhen Hope Microelectronics Co., Ltds products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Shenzhen Hope Microelectronics Co., Ltd customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Shenzhen Hope Microelectronics Co., Ltd for any damages resulting from such improper use or sale. Contact Information Shenzhen Hope Microelectronics Co., Ltd. Address: 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan, Shenzhen, GD, P.R. China Tel: +86-755-82973805 Post Code: 518055 Email: sales@hoperf.com Website: www.hoperf.com 2 / 57 www.hoperf.com CMT4531 Contents 1 OVERVIEW ........................................................................................................................................................ 8 NAMING RULE ...................................................................................................................................................... 9 DEVICE SCHEDULE ............................................................................................................................................... 9 2 PRODUCTION FEATURES ............................................................................................................................ 11 PROCESSOR CORE ............................................................................................................................................... 11 MEMORY ............................................................................................................................................................. 11 Flash ............................................................................................................................................................... 11 SRAM ............................................................................................................................................................ 11 LOW POWER MODES ........................................................................................................................................... 11 CLOCK SYSTEM .................................................................................................................................................. 12 GENERAL PURPOSE INPUT/OUTPUT (GPIO) ........................................................................................................ 13 EXTI .................................................................................................................................................................. 14 DMA .................................................................................................................................................................. 14 CRC ................................................................................................................................................................... 14 TIMER AND WATCHDOG ...................................................................................................................................... 15 Basic Timer (TIM6) ....................................................................................................................................... 15 General-purpose Timer (TIM3) ..................................................................................................................... 15 Advanced Timer (TIM1) ................................................................................................................................ 16 System Tick Timer (Systick) .......................................................................................................................... 17 Watchdog Timer (WDG) ................................................................................................................................ 17 ADC ................................................................................................................................................................... 17 I2C BUS INTERFACE (I2C) .................................................................................................................................. 18 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER/TRANSMITTER (USART) ........................................... 20 SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................................................ 22 SERIAL AUDIO PORT (I2S) .................................................................................................................................. 23 REAL TIME CLOCK (RTC) ................................................................................................................................... 23 INFRARED CONTROLLER (IRC) ........................................................................................................................... 24 AUTOMATIC KEY SCANNING (KEYSCAN) ......................................................................................................... 24 SERIAL SWD DEBUGGING INTERFACE (SWD) .................................................................................................... 24 3 DEFINITION AND DESCRIPTION ................................................................................................................ 25 DEVICE PINOUT .................................................................................................................................................. 25 QFN32 ........................................................................................................................................................... 25 DEFINITION OF PIN MULTIPLEXING ..................................................................................................................... 26 4 ELECTRICAL CHARACTERISTICS ............................................................................................................ 29 TEST CONDITION ................................................................................................................................................ 29 Minimum and Maximum ............................................................................................................................... 29 Typical Values ................................................................................................................................................ 29 Typical Curve ................................................................................................................................................. 29 Load Capacitance ........................................................................................................................................... 29 Input Voltage of Pin ....................................................................................................................................... 29 Power Supply Plan ......................................................................................................................................... 30 Current Consumption Measurement .............................................................................................................. 31 ABSOLUTE MAXIMUM RATING ........................................................................................................................... 32 3 / 57 www.hoperf.com CMT4531 OPERATING CONDITIONS .................................................................................................................................... 33 General Operating Conditions ....................................................................................................................... 33 Power-on and Power-off Operating Conditions ............................................................................................. 33 Characteristics of Built-in Reset and Power Control Module ........................................................................ 33 Characteristics of DCDC ............................................................................................................................... 34 Characteristics of Supply Current .................................................................................................................. 35 Characteristics of External Clock Source ...................................................................................................... 36 Characteristics of Internal Clock Source ....................................................................................................... 38 Time Required to Wake Up from Low Power Modes .................................................................................... 39 Characteristics of FLASH Memory ............................................................................................................... 39 Absolute Maximum (Electrical Sensitivity) .............................................................................................. 40 I/O port characteristics ............................................................................................................................... 41 Characteristics of NRST Pins .................................................................................................................... 43 Characteristics of TIM Timer .................................................................................................................... 44 Characteristics of I2C Interface ................................................................................................................. 45 Characteristics of SPI ................................................................................................................................ 47 Characteristics of Temperature Sensor (TS) .............................................................................................. 50 Characteristics of ADC .............................................................................................................................. 50 Characteristics of PGA .............................................................................................................................. 51 Characteristics of KEYSCAN ................................................................................................................... 52 Characteristics of BLE ............................................................................................................................... 52 5 PACKAGE SIZE ............................................................................................................................................... 55 QFN32 ............................................................................................................................................................... 55 6 VERSION HISTORY ........................................................................................................................................ 56 4 / 57 www.hoperf.com CMT4531 List of Tables Table 1-1 Resource Configuration of CMT453x Series ...................................................................................... 9 Table 3-1 Definition of Pin ................................................................................................................................ 26 Table 4-1 Voltage Characteristics ...................................................................................................................... 32 Table 4-2 Current Characteristics ...................................................................................................................... 32 Table 4-3 Temperature Characteristics .............................................................................................................. 33 Table 4-4 General Operating Conditions ........................................................................................................... 33 Table 4-5 Power-on and Power-off Operating Conditions................................................................................. 33 Table 4-6 Characteristics of Built-in Reset and Power Control Module(1) ........................................................ 34 Table 4-7 Built-in DCDC Power Management Module Characteristics (1) ........................................................ 34 Table 4-8 Typical Current Consumption in Sleep Mode(1) ................................................................................ 35 Table 4-9 Typical Current Consumption in Operating Mode ............................................................................ 35 Table 4-10 BLE Power Dissipation ................................................................................................................... 35 Table 4-11 Characteristics of HSE 32 MHz Oscillator(1)(2) ................................................................................ 36 Table 4-12 Characteristics of LSE Oscillator (fLSE=32.768kHz)(1) .................................................................... 37 Table 4-13 Characteristics of HSI Oscillator(1)(2) ............................................................................................... 38 Table 4-14 Characteristics of LSI Oscillator(1) .................................................................................................. 39 Table 4-15 Time Required to Wake Up from Low Power Modes ..................................................................... 39 Table 4-16 Characteristics of Memory .............................................................................................................. 39 Table 4-17 Flash Memory Life and Data Retention Period ............................................................................... 40 Table 4-18 Absolute Maximum of ESD ............................................................................................................ 40 Table 4-19 Electrical Sensitivity ........................................................................................................................ 41 Table 4-20 Static Characteristics of I/O(1)(2)....................................................................................................... 41 Table 4-21 I/O Output Voltage ........................................................................................................................... 42 Table 4-22 Input and Output AC Characteristics(1) ............................................................................................ 42 Table 4-23 Characteristics of NRST Pins .......................................................................................................... 43 Table 4-24 Characteristics of TIMx(1)(2) ............................................................................................................. 44 Table 4-25 Characteristics of I2C Interface(1) .................................................................................................... 46 Table 4-26 Characteristics of SPI(1) ................................................................................................................... 47 Table 4-27 Characteristics of Temperature Sensor ............................................................................................ 50 Table 4-28 Characteristics of ADC .................................................................................................................... 51 Table 4-29 Characteristics of PGA .................................................................................................................... 52 5 / 57 www.hoperf.com CMT4531 Table 4-30 Characteristics of KEYSCAN ......................................................................................................... 52 Table 4-31 BLE Receiving Characteristics(1) ..................................................................................................... 53 Table 4-32 BLE Transmitting Characteristics(1) ................................................................................................ 53 6 / 57 www.hoperf.com CMT4531 List of Figures Figure 1-1 Block Diagram of CMT453x Series .................................................................................................. 8 Figure 1-2 Structure of CMT453x Series Ordering Code ................................................................................... 9 Figure 2-1 Memory Mapping ............................................................................................................................ 11 Figure 2-2 Clock Tree ........................................................................................................................................ 13 Figure 3-1 QFN32 Pin Distribution of CMT453x Series .................................................................................. 25 Figure 4-1 Load Conditions for Pins ................................................................................................................. 29 Figure 4-2 Input Voltage of Pin ......................................................................................................................... 30 Figure 4-3 Power Supply Plan ........................................................................................................................... 30 Figure 4-4 Current Consumption Measurement Plan ........................................................................................ 31 Figure 4-5 Typical Application with a 32 MHz Crystal ..................................................................................... 37 Figure 4-6 Typical Application with a 32.768 kH Crystal ................................................................................. 38 Figure 4-7 Definition of Input and Output AC Characteristics .......................................................................... 43 Figure 4-8 Recommended NRST Pin Protection ............................................................................................... 44 Figure 4-9 AC Waveform and Measuring Circuit of I2C Bus(1) ........................................................................ 47 Figure 4-10 SPI Sequence DiagramSlave Mode and CPHA=0 ....................................................................... 49 Figure 4-11 SPI Sequence DiagramSlave Mode and CPHA=1(1) .................................................................... 49 Figure 4-12 SPI Sequence DiagramMaster Mode(1) ........................................................................................ 50 Figure 5-1 QFN32 Package Size ....................................................................................................................... 55 7 / 57 www.hoperf.com CMT4531 1 Overview CMT453x Bluetooth Low Energy wireless SoC Family is high performance, ultra-low power dissipation chips that support BLE 5.1. Equipped with 32-bit ARM Cortex-M0 core, it features a frequency up to 64 MHz, 48 KB SRAM integrated on the chip, and 256 KB Flash. Integrated with an advanced BLE 5.1 RF transceiver, it is compliant with the BLE 5.1 standard and provided with multiple modes including standard 1 Mbps BLE mode, enhanced 2 Mbps BLE mode, 125 kbps BLE remote mode

(S8), and 500 kbps BLE remote mode (S2). In the 1 Mbps or 2 Mbps BLE mode, it supports AOA and AOD, RSSI, master/slave role, multi-connection, packet length expansion, KEYSCAN, IRC, 10-bit 1.33 Msps ADC (configurable as 16-bit 16 Ksps), analog MIC input, PGA, basic, universal and advanced timers, RTC, WWDG, IWDG, LPUART, USART, SPI, I2C, and other peripherals. It is applicable to many application scenarios including Bluetooth KEY, OBU, data transmission module, Bluetooth voice remote controller, and smart home. Figure 1-1 shows the block diagram of CMT453x series. Figure 1-1 Block Diagram of CMT453x Series 8 / 57 www.hoperf.com CoreCortex-M0Fmax:64MHzFLASH256/512KBSystem BusDMASWDNVICADCCRCEXTIGPIOAGPIOBSPI1/I2S1SPI2/I2S2KEY SCANTIM1AFIOPWRRTCIWDGWWDGTIM6TIM3LPUARTUSART2I2CAHB System Bus2MODEMRadioBLE Subsystem BLEBASEBANDDMAIRCAFIOAFIOUSART1SRAM48KBAPB2 Max:64MHzAPB1 Max:32MHz CMT4531 Naming Rule Figure 1-2 Structure of CMT453x Series Ordering Code Device Schedule Table 1-1 Resource Configuration of CMT453x Series Model Bluetooth Protocol Flash Capacity (KB) SRAM Capacity (KB) CPU Frequency Operating Environment Timer Communication Interface Universal Advanced Basic RTC SPI I2S I2C USART LPUART GPIO DMA (channels) 10-bit ADC (channels) KEYSCAN CMT4531KCQ6-1 BLE5.1 256 48 ARM Cortex-M0 @64MHz 1.8 V~3.6 V/-40~85C 1 pc (TIM3) 1 pc (TIM1) 1 pc (TIM6) 1 pcs (RTC) 2 pcs (SPI1, SPI2) 2 pcs (I2S1, I2S2) 1 pc (I2C) 2 pcs (USART1, USART2) 1 pc (LPUART) 21 1(5) 1(8) 8/10/13 GPIOs support 44/65/104 keys respectively 9 / 57 www.hoperf.com CMT4531KCQ6- 1AbbreviationProduct seriesBluetoothProduct Number31 = Value lineNumber of pinsK = 32 PinsPower supply1 = 1.8~3.6VTemperature range6 = -40~85 7 = -40~105 PackageQ = QFNCapacityC = 256K E = 512K CMT4531 IRC CRC Package 1 pc CRC16/CRC32 QFN32 (4 mm 4 mm) 10 / 57 www.hoperf.com CMT4531 2 Production Features Processor Core CMT453x series are integrated with ARM Cortex-M0 processors. Memory Figure 2-1 Memory Mapping Flash 256 KB Flash, with up to 256 KB for program storage and the remaining space for data storage. SRAM 48 KB SRAM, full retention in the Sleep mode Low Power Modes CMT453x series support four low power modes. Idle Mode Only the CPU stops running. All peripherals are working and can wake up the CPU in the event of any interrupt/event. 11 / 57 www.hoperf.com Vendor Specific 511MBCortex-M0 Peripheral 1MBPeripheral 0.5GBSRAM 0.5GBFLASHReservedSRAM0x0100_0000 0x010F_FFFF0x2000_C000 0x3FFF_FFFF0x2000_0000 0x2000_BFFFCODE 0.5GBNVIC/SCSBPUDWT0xE000_E000 0xE000_EFFF0xE000_2000 0xE000_2FFF0xE000_1000 0xE000_1FFFReserved0xE010_0000 0xFFFF_FFFFTIM6TIM30x4000_1000 0x4000_13FF0x4000_0400 0x4000_07FFLPUARTUSART2IWDGWWDGRTC0x4000_4800 0x4000_4BFF0x4000_4400 0x4000_47FF0x4000_3000 0x4000_33FF0x4000_2C00 0x4000_2FFF0x4000_2800 0x4000_2BFFPWRI2C0x4000_7000 0x4000_73FF0x4000_5400 0x4000_57FFSPI1_I2S1GPIOBGPIOAEXTIAFIO0x4001_2000 0x4001_23FF0x4001_0C00 0x4001_0FFF0x4001_0800 0x4001_0BFF0x4001_0400 0x4001_07FF0x4001_0000 0x4001_03FFSPI2_I2S2USART1TIM10x4001_4400 0x4001_47FF0x4001_3800 0x4001_3BFF0x4001_2C00 0x4001_2FFFIRCRCCADCDMA0x4002_1C00 0x4002_1FFF0x4002_1000 0x4002_13FF0x4002_0800 0x4002_0BFF0x4002_0000 0x4002_03FFCRC0x4002_3000 0x4002_33FFAPB1AHBReserved 2GBAPB2ReservedAHB Peripheral ReservedAPB2 Peripheral ReservedAPB1 Peripheral 0x4003_2000 0x5FFF_FFFF0x4002_0000 0x4003_1FFF0x4001_5800 0x4001_FFFF0x4001_0000 0x4001_57FF0x4000_7800 0x4000_FFFF0x4000_0000 0x4000_77FFReservedBLE baseband0x4002_C000 0x4002_FFFF0x4002_8000 0x4002_BFFFMODEM0x4002_2400 0x4002_2FFFKEYSCAN0x4001_1400 0x4001_17FF CMT4531 Standby Mode The power supply works as usual. The CORE power domain is turned off. The BLE is available. Sleep Mode The high speed clock is switched off. The power supply runs in the low power mode. The CORE power domain and BLE are turned off. PD Mode All systems are shut down. Only WAKEUP IO and NRST can be woken up. Clock System Two high speed clocks:

HSI oscillator clock (64 MHz) HSE oscillator clock (32 MHz) Two secondary clock sources:

LSI oscillator clock (32 KHz) LSE oscillator clock (32.768 KHz) After the system is powered on and reset, HSI and HSE are enabled and the system clock is set to HSI by default. LSI can be used to drive the IWDG. Both LSI and LSE can selectively drive RTC, KEYSCAN and LPUART through a program. Moreover, LSI/LSE can automatically wake up the system in the Idle /Standby/Sleep/PD mode. If not in use, either clock source can be turned on or off independently to optimize system power dissipation. 12 / 57 www.hoperf.com CMT4531 Figure 2-2 Clock Tree General Purpose Input/Output (GPIO) GPIO stands for general purpose input/output. AFIO stands for alternate-function input/output. A chip supports up to 21 GPIOs, which are divided into 2 groups (GPIOA/GPIOB). GPIOA has 7 ports and GPIOB has 14 ports. GPIO ports share pins with other multiplexed peripherals and can be flexibly configured as required. Each GPIO pin can be independently configured as an output, input, or multiplexed peripheral functional port, and configured with heavy current through capability. Main features:

GPIO ports can be configured through software to the following modes:

Input floating Input pull-up Input pull-down Analog function Output open-drain Output push-pull 13 / 57 www.hoperf.com HSE/64/64SYSCLK64MHz MAXHCLKADC1MSELHSEI2S_CLKADC1_CLKFCLK CPU AHB BUSHCLK/8SysTickDMA_CLK/CRC_CLKAPB1Prescaler/1/2/4/8/1632MHz MAXPCLK1 to APB1 peripherals64MHz MAXPCLK2 to APB2 peripheralsTIM 3/6If(APB1 Prescaler = 1) x1else x2TIM3/6_CLKTIM1_CLKLSXSELRTC_CLKSYSCLKLSELSISYSCLKHSEHSIMCOClock TreeMCOXO32MP_INXO32MM_OUTXO32KP_INXO32KM_OUTLegend:HSE = High-speed external clock signalHSI = High-speed internal clock signalLSE = Low-speed external clock signalLSI = Low-speed internal clock signalTIMCLKSELSCLKSWHSE OSC32MHzHSI RC64MHzLSE OSC32.768KHzLSI RC32KHzAHBPrescaler/1/2/4APB2Prescaler/1/2/4/8/16TIM 1If(APB2 Prescaler = 1) x1else x2SYSCLKLSILSEHSILPUART_CLKLPUART_PCLK1PWR_LSX_CLKBLE_LSX_CLKKEYSCAN_LSX_CLKHCLK/8PLL/4/4ADC_CLK_64KADC_CLK_16K/2BLE_CLK/4/44.096M CMT4531 Alternate function push-pull Alternate function open-drain Separate bit setting or bit clearing function All I/O supports external interrupt All I/Os can be woken up from low power modes, with configurable rising or falling edge Eight EXTIs can wake up the Sleep mode and all I/O can be multiplexed as EXTI PB3 can wake up I/O from the PD mode Support remapping of AFIO through software Support GPIO locking mechanism and removal of locking status through resetting Each I/O port register bit is freely programmable, but it must be accessed as 32-bit words (16-bit half-word or 8-bit byte access is not allowed). EXTI The EXTI consists of 14 edge detectors for generating interrupt/event requests. Each interrupt line can be independently configured as an event or interrupt and the corresponding trigger event (rising edge or falling edge or both). Each line can also be masked independently. A pending register maintains the status line of the interrupt request. This request can be cleared by writing a '1' in the corresponding bit of the pending register. DMA DMA is integrated with one universal 5-channel DMA controller to manage data transfer from memory to memory, from peripheral to memory and from memory to peripheral;

Each channel has a dedicated hardware DMA request logic, and can be triggered by software. The transmission length, source address and destination address of each channel can be set separately by software. DMA is applicable to main peripherals including SPI, I2S, I2C, USART, ADC, and basic, universal and advanced control TIMx. CRC CRC is integrated with CRC32 and CRC16 to get any CRC calculation based on a fixed polynomial. Among numerous applications, CRC-based technologies are used to verify the consistency of data transmission or storage. Within the scope specified in EN/IEC 60335-1, CRC provides a means of detecting flash memory errors, and can be used to compute software signatures in real time and compare them with the signatures generated when linking and generating the software. Main features:

CRC16: supports the polynomial X16+X15+X2+X0 CRC16 computing time: one AHB clock period (HCLK) CRC32: supports the polynomial X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X +1 14 / 57 www.hoperf.com CMT4531 CRC32 computing time: four AHB clock periods (HCLK) Configurable initial value of cyclic redundancy computation DMA available Timer and Watchdog 1 advanced timer, 1 general-purpose timer, 1 basic timer, 2 watchdog timer, and 1 system tick timer. Basic Timer (TIM6) TIM6 contains a 16-bit auto-loading counter driven by a programmable prescaler. It provides a time baseline for general-purpose timers. Main features:

16-bit automatic reloading accumulating counter 16-bit programmable (can be modified in real time) prescaler, used for frequency demultiplication of the input clock by a coefficient ranging from 1 to 65536 Generate an interrupt/DMA request when an event is updated (counter overflow) General-purpose Timer (TIM3) A general-purpose timer consists of one 16-bit countup/countdown auto-loading counter, one 16-bit prescaler, and 4 independent channels, each for input capture (pulse width measurement), output compare, PWM, and monopulse output;

Main features:

16-bit countup, countdown, or countup/countdown auto-loading counter 16-bit programmable (can be modified in real time) prescaler; the frequency demultiplication coefficient of counter's clock frequency can be any numerical value ranging from 1 to 65536 Four independent channels:

Input capture Output compare PWM generation (edge or middle alignment) Monopulse output A synchronous circuit that uses an external signal control timer and allows interconnection of multiple timers Generate interrupt/DMA in the case of the following events:

Update: up/down counter overflow, counter initialization (software-based trigger or internal trigger) Trigger events (startup, shutdown, and initialization of counter, or internally triggered counting) Input capture Output compare 15 / 57 www.hoperf.com CMT4531 Support the incremental (quadrature) encoders for positioning and Hall sensor circuits Use trigger input signal as the input of external clock, or perform periodic current management Advanced Timer (TIM1) TIM1 consists of a 16-bit auto-loading counter driven by a programmable prescaler. It provides multiple functions, including measuring the pulse width of the input signal (input capture) or generating output waveform (such as output compare, PWM, and complementary PWM outputs with dead time in between). Using the timer's prescaler and RCC clock control prescaler can adjust the pulse width and waveform period from several microseconds to several milliseconds. Main features:

16-bit countup, countdown, or countup/countdown auto-loading counter 16-bit programmable (can be modified in real time) prescaler; the frequency demultiplication coefficient of counter's clock frequency can be any numerical value ranging from 1 to 65536 Use up to 64 MHz as timer's input clock Up to four independent channels:

Input capture Output compare PWM generation (edge or middle alignment) Monopulse output Trigger time points can be configured by software in the entire PWM cycle Complementary output with programmable dead time A synchronous circuit that uses an external signal control timer or allows interconnection of multiple timers A repetitive counter to update the timer registers only after a given number of cycles of the counter Break input signal can put the timer's output signals in a reset state or in a known state Generate interrupt/DMA in the case of the following events:

Update: up/down counter overflow, counter initialization (software-based trigger or internal/external trigger);

Trigger events (startup, shutdown, and initialization of counter, or internally/externally triggered counting);

Input capture;

Output compare;

Break signal input;

Support the incremental (quadrature) encoders for positioning and Hall sensor circuits;

Use trigger input signal as the input of external clock, or perform periodic current management In the debug mode, a counter can be frozen and PWM outputs are disabled, cutting off the switches controlled by those outputs. The advanced timer has many functions similar to and the same internal structure as that of the standard 16 / 57 www.hoperf.com CMT4531 TIM timer. Therefore, it can work with the TIM timer through the timer's link function to provide synchronization or event link function. System Tick Timer (Systick) This timer is tailored to a real-time operating system and can also be used as a standard downcounter. It has the following features:

24-bit downcounter Automatic re-loading function Generate a maskable system interrupt when the counter reaches zero Programmable clock source Watchdog Timer (WDG) It supports both independent watchdog (IWDG) and window watchdog (WWDG). Two watchdogs ensure higher security, time accuracy, and flexibility in use. Independent Watchdog (IWDG) The IWDG is based on a 12-bit downcounter and an 8-bit prescaler, and is driven by a separate, low speed RC oscillator. It still can work even if the master clock fails and operate in the Sleep mode. Once activated, the IWDG will generate a reset signal when the counter reaches 0x000 if the watchdog's counter is not cleared within a given time period. Moreover, it can also be used to reset the entire system in the event of an application error, or as a free timer to provide timeout management for applications. Window Watchdog (WWDG) The WWDG is typically used to monitor software failures caused by deviation of an application from the normal running sequence due to external disturbances or unforeseen logical conditions. Unless the value of a downcounter is refreshed before the T6 bit reaches zero, the watchdog circuit will generate a chip reset when the preset time cycle is reached. A chip reset is also generated if the value of a 7-bit downcounter (in the control register) is refreshed before the downcounter reaches the value of the window register. This indicates that the downcounter needs to be refreshed in a finite time window. Main features:

WWDG is driven by the clock obtained after frequency demultiplication of APB1 clock Programmable free-running downcounter Conditional reset A reset occurs when the value of the downcounter is less than 0x40 if the watchdog is enabled;

A reset occurs when the downcounter is reloaded outside the window if the watchdog is enabled;

If the watchdog is enabled and interrupt is allowed, an EWI is generated when the value of the downcounter reaches 0x40, and it can be used to reload the counter to avoid resetting WWDG. ADC Support 10-bit 1.33 Msps ADC (configurable as 16-bit 16 Ksps), single-ended or differential AMIC, and built-in 17 / 57 www.hoperf.com CMT4531 PGA with a gain up to 42 dB. Provide adjustable (1.62.3 V) MIC BIAS voltage for MIC. Up to 8 channels, including 5 external single-ended channels, 1 differential MIC channel, and 2 internal channels. Two internal channels are VCC detection channel and temperature sensor channel. For 5 external channels, the detection range of channels 1 (PB10) and 2 (PB9) is 0V-1V, and that of channels 3 (PB8), 4 (PB7), and 5 (PB6) is 0V-3.6V. the input voltage of channels 3 (PB8), 4 (PB7), and 5 (PB6) <=VCC+300 mV. In the audio mode, using the built-in PGA and microphone bias, MIC signals are amplified by the PGA, and then converted to digital signals by an ADC. After the audio input control (low-pass decimation filter and optional energy and zero-cross detection), the audio data is stored in the system RAM through DMA. Finally, 16-bit 16 kHz audio signal format data is output. Main features:

Support AMIC input, with adjustable microphone bias PGA supports single-ended or differential input and adjustable gain Support one ADC, which can measure 5 external single-ended channels, 1 differential MIC channel, and 2 internal channels (input channels are optional) Support two internal channels, including TempSensor and VCC 10-bit 1.33 Msps ADC (configurable as 16-bit 16 Ksps) Support digital decimation filter to 16-bit and noise filter Support single and continuous conversion modes A DMA request can be generated during channel switching The analog watchdog feature allows an application to detect whether the input PB10 voltage exceeds a user-

defined high/low threshold An interrupt occurs at the end of switching or in the case of an analog watchdog event In the audio mode, the filter's output data is stored in a 16-bit data register, and in the general mode, the data is right-aligned and stored in a 16-bit data register In the audio mode, data is output in 16-bit 16 Ksps signed mono PCM format, and in the general mode, data is output in 10-bit 1.33 Msps unsigned format I2C Bus Interface (I2C) The I2C bus interface provides multi-master function that controls all the I2C bus specific sequences, protocol, arbitration and timing. It supports multiple communication rate modes (up to 1 MHz), DMA operations, and SMBus 2.0. The I2C module suits multiple purposes, including CRC code generation and verification, SMBus (System Management Bus), and PMBus (Power Management Bus). Main features:

Multi-master function: The module can be either a master device or a slave device Functions of I2C master device 18 / 57 www.hoperf.com CMT4531 Generate a clock Generate start and stop signals Functions of I2C slave device Programmable address detection The I2C interface supports 7-bit or 10-bit addressing, and dual-slave address responsiveness in 7-bit slave mode Stop bit detection Generation and detection of 7-bit/10-bit addresses; broadcast call Support different communication rates Standard rate (up to 100 kHz) Rapid (up to 400 kHz) Rapid+(up to 1 MHz) Support multiple status flags Transmitter/receiver mode flag End of byte transmission flag I2C bus busy flag Support multiple error flags Arbitration is lost in the master mode Acknowledgement (ACK) error after address/data transmission Detection of a start or stop condition of misplacement Overflow or underflow when the clock stretching function is disabled One interrupt vector:

Event interrupt and error interrupt share an interrupt vector Optional clock stretching function DMA with single-byte cache Generation or verification of configurable PEC The PEC value can be transmitted as the last byte in the transmitter mode PEC for the last received byte Compatible with SMBus 2.0 25 ms clock low timeout delay 10 ms cumulative time for low clock extension for master device 19 / 57 www.hoperf.com CMT4531 25 ms cumulative time for low clock extension for slave device Generation or verification of hardware PEC with ACK control Support address resolution protocol (ARP) Compatible with SMBus Universal Synchronous/Asynchronous Receiver/Transmitter

(USART) The USART is integrated with 3 serial receiver/transmitter interfaces, including USART1, USART2, and LPUART. USART1 and USART2 interfaces support synchronous/asynchronous communication, IrDA SIR ENDEC transmission coding and decoding, multiprocessor communication mode, single-wire half-duplex communication mode, and LIN master/slave function. USART1 and USART2 interfaces also support the CTS and RTS hardware flow control, and the single-wire mode such as the ISO7816 smart card standard. DMA is available to both interfaces. Main features:

Full-duplex asynchronous communication Single-wire half-duplex communication NRZ standard format Fractional baud rate generator system a common programmable transmitting and receiving baud rate up to 4 Mbits/s Programmable data word length (8 or 9 bits) Configurable stop bits support for 1 or 2 stop bits LIN master is capable of sending synchronous break and LIN slave is capable of detecting the break: 13-bit break is generated and 10/11-bit break is detected when USART hardware is configured to LIN Transmitter clock output for synchronous transmission IRDA SIR encoder-decoder: Support for 3/16 bit duration in normal mode Smart card emulation capability The smart card interface supports the asynchronous smart card protocol as defined in the ISO7816-3 standard 0.5 and 1.5 stop bits for smart card Single-wire half-duplex communication Configurable multi-buffer communication using DMA buffering of received/transmitted bytes in SRAM using centralized DMA Separate enable bits for transmitter and receiver Detection flags 20 / 57 www.hoperf.com CMT4531 Receive buffer full Transmit buffer empty End of transmission flags Checking control Send check bits Check the received data Four error detection flags Overflow error Noise error Frame error Checking error Ten USART interrupt sources with flags CTS change LIN break detection Transmit data register empty Transmission completed Receive data register full Detected idle bus Overflow error Frame error Noise error Checking error Multiprocessor communication If addresses do not match, enable the silent mode Wake up from silent mode (by detecting idle bus or address flag) Two ways to wake up the receiver: address bit (MSB, 9th bit), bus idle Mode configuration:

Communication mode USART1 USART2 LPUART Asynchronous mode Supported Supported Supported Hardware flow control Supported Supported Supported 21 / 57 www.hoperf.com CMT4531 Multi-buffer communication (DMA) Multiprocessor communication Supported Supported Supported Supported Supported Not supported Synchronous Supported Supported Not supported Single-wire half-duplex Supported Supported Not supported Smart card Supported Supported Not supported IrDA LIN Supported Supported Not supported Supported Supported Not supported Serial Peripheral Interface (SPI) Two SPIs are provided, allowing half-duplex/full-duplex, synchronous, and serial communication between chips and peripherals. SPI can be configured to operate in the master mode and provide a communication clock (SCK) for the external slave device. Moreover, SPI can also work in the multi-master mode and use the CRC based reliable communication. Main features:

Full-duplex synchronous transmission Double-wire simplex synchronous transmission with/without the third two-way data cable 8-bit or 16-bit transmission frame format Support master or slave mode Support multi-master mode Rapid communication between master and slave modes NSS management can be performed by software or hardware in the master or slave mode: dynamic switching of master/slave mode Programmable clock polarity and phase Programmable data sequence, with MSB or LSB in the first order Dedicated transmit and receive flags to trigger interrupt SPI bus busy flag Support reliable communication based on hardware CRC The CRC value can be transmitted as the last byte in the transmitter mode Automatic CRC for the last received byte in the full-duplex mode Master mode failure, overload, and CRC error flags that trigger interrupt Single-byte transmitting and receiving buffers with DMA feature: Generate transmission and receiving 22 / 57 www.hoperf.com CMT4531 requests Maximum interface rate: 16 Mbps Serial Audio Port (I2S) I2S, a 3-pin synchronous serial interface communication protocol, operates in master or slave mode, supports an audio sample frequencies ranging from 8 kHz to 96 kHz, and can be configured as 16/24/32-bit transmission or as input or output channel. It is compatible with four audio standards, namely, the Philips' I2S standard, the MSB and LSB alignment standards, and the PCM standard. It works in both master and slave modes in half-duplex communication. When it works as the master device, it provides clock signals to external slave devices through the interface. Main features:

Half-duplex communication (either transmitting or receiving only at a time) Master or slave operation 8-bit linear programmable prescaler, helping obtain an accurate audio sample frequency (8 kHz~96 kHz) 16/24/32-bit data format 16-bit (16-bit data frame) or 32-bit (16/24/32-bit data frame) fixed packet frame for audio channel Programmable clock polarity (stable state) Underflow flag bit in the slave transmitter mode and overflow flag bit in the master/slave receiving mode 16-bit data register to transmit and receive, one in each end of the channel Supported I2S protocols Philips' I2S standard MSB alignment standard (left-justified) LSB alignment standard (right-justified) PCM standard (a 16-bit channel frame with long or short frame synchronization; or extension from a 16-

bit data frame to a 32-bit channel frame) Data sequence: MSB is always in the first order DMA is available to both transmitter and receiver Real Time Clock (RTC) RTC has a set of BCD timers/counters that count independently continuously. In the corresponding software configuration, RTC can provide the calendar function. RTC also has a programmable alarm clock interrupt. The two 32-bit registers contain the subsecond, second, minute, hour (in 12- or 24-hour format), day of the week, day (day of the month), month, and year data in decimal format (BCD). The subsecond value is provided by a separate 32-bit register in binary format. The other 32-bit register contains programmable second, minute, hour, day of the week, day, month, and year data. 23 / 57 www.hoperf.com CMT4531 RTC has the feature of automatic wakeup in the low power mode. Infrared Controller (IRC) The infrared controller can generate different infrared protocol signals by configuring different types of coding through software, and supports the software-based infrared self-learning function. Main features:

Carrier frequency range: 30 kHz~60 kHz Support pulse width coding and pulse spacing coding Support Manchester coding Support carrier-free mode Support any combination of Mark code and Space code Provide 16 (depth) 21-bit (width) Code FIFO for storing coded commands Support repeatedly sending commands Generate interrupt upon the end of transmission Automatic Key Scanning (KEYSCAN) Support 8/10/13 IO ports that support 44/65/104 keys respectively. Support configurable key jitter elimination. Support automatic scanning, software scanning, low-power dissipation scanning modes. Automatic mode: Scanning performs at the configured fixed time interval Low power mode: A round of scanning (three times) is performed after the detection key is pressed Software mode: Scanning is triggered by the software Serial SWD Debugging Interface (SWD) A SWJ-DP interface with built-in ARM, it integrates JTAG and serial single-wire debugging interfaces, and supports connecting to the serial single-wire debugging interface or JTAG interface. The TMS and TCK signals of JTAG share pins with SWDIO and SWCLK respectively. 24 / 57 www.hoperf.com CMT4531 3 Definition and Description Device Pinout QFN32 Figure 3-1 QFN32 Pin Distribution of CMT453x Series 25 / 57 www.hoperf.com QFN32PA2PA3RESETPB0PA4PA5PA6VDD_FLASHPB6PB5PB4PB3PB2PB1PB9PB8VDCDCSWITCHVCCPB13PB11PB12PB10PB7RFIOPVDD_PAVDCDCRFVCCRFXO32MM_OUTXO32MP_INPA0PA11234567824232221201918179101112131415163231302928272625GND CMT4531 Definition of Pin Multiplexing Table 3-1 Definition of Pin Pin No. Pin Name

(QFN32)

(Default Function) Type Alternate Function Function Description 1 2 3 4 5 6 7 8 9 PA2 PA3 RESET I/O I/O AIO PB0 I/O SPI1_MOSI(I2S1_SD) KEY3 SPI1_MISO(I2S1_MCK) KEY4 TIM1_CH1 SPI2_NSS(I2S2_WS) USART1_RTS LPUART_RTS KEY11 TIM1_CH3N PA4

(SWDCLK) PA5

(SWDIO) I/O USART1_TXD(7816_TX1) KEY9 TIM1_ETR I/O USART1_RXD(7816_RST1) PA6 I/O VDD_FLASH S PB8

(XO32KP_IN) I/O I/O 10 PB9

(XO32KM_OUT) 11 PB1 I/O 12 PB2 I/O External 2.2 uF capacitor ADC3 ADC2 KEY10 TIM1_BKIN USART2_TXD USART1_CK(7816_CLK1) KEY5 TIM1_CH1 IIC_SDA USART1_RTS KEY7 TIM1_CH2 IIC_SCL USART1_CTS KEY8 TIM1_CH2 SPI2_CLK(I2S2_CLK) USART1_CTS LPUART_TXD KEY12 ANT_SW4 TIM1_CH3 SPI2_MOSI 26 / 57 www.hoperf.com CMT4531 13 PB3 I/O 14 PB4 I/O LPUART_RXD KEY13 ANT_SW5 TIM1_CH4 SPI2_MISO(I2S_MCK) LPUART_CTS PA_LDO_EN ANT_SW1 SPI2_CLK(I2S2_CLK) TIM3_CH1(IRC_TX) USART2_TXD(7816_TX2) ANT_SW6 SPI2_MISO(I2S2_MCK) TIM3_CH2(IRC_RX) 15 PB5 I/O USART2_RXD(7816_RST2) 16 PB6 I/O 17 PB7 I/O 18 PB10 I/O 19 PB12 I/O 20 PB11 I/O 21 PB13 I/O RCC_MCO ANT_SW7 SPI2_MOSI(I2S2_SD) TIM3_CH3 IIC_SDA USART1_TXD SWDCLK ANT_SW2 SPI2_NSS(I2S2_WS) TIM3_CH4 IIC_SCL USART1_RXD SWDIO ANT_SW3 TIM1_CH3 LPUART_RTS USART2_RXD IIC_SMBA KEY6 TIM1_CH1N LPUART_TXD USART2_CTS TIM1_CH4 LPUART_RXD USART2_RTS IIC_SMBA TIM1_CH2N LPUART_CTS USART2_CK WAKEUP ADC5 ADC4 ADC1 AMIC_BIAS AMIC_N AMIC_P 27 / 57 www.hoperf.com CMT4531 22 23 24 25 26 27 28 29 30 31 32 33 VCC SWITCH VDCDC RFIOP VDD_PA VDCDCRF VCCRF S S S AIO S S S XO32MM_OUT AIO XO32MP_IN AIO PA0 PA1 GND I/O I/O S Power supply for chip DCDC external Interface DCDC output Antenna port PA power supply DCDC output, connecting to VDCDC Power supply for chip External 32 MHz crystal External 32 MHz crystal Ground SPI1_NSS(I2S1_WS) KEY1 SPI1_CLK(I2S1_CLK) KEY 2 I = input, O = output, S = power supply, AIO = analog IO Upon resetting, the I/O port is configured to the analog input mode. But the following signals are not applicable:

Input pull-up mode for NRST by default PA4: SWCLK under the input pull-down mode PA5: SWDIO under the input pull-up mode 28 / 57 www.hoperf.com CMT4531 4 Electrical Characteristics Test Condition All voltages are based on VSS unless otherwise specified. Minimum and Maximum Unless otherwise specified, all minimums and maximums will be guaranteed under the worst ambient temperature, supply voltage and clock frequency conditions by testing 100% of the product at ambient temperature TA=25C and TA=TAmax (TAmax matches the specified temperature range) on the production line. The annotations listed below each table are the data obtained through laboratory tests, design simulations and/or process characteristics, and will not be tested on the production line. On the basis of laboratory tests, the minimums and maximums are obtained by taking the average of the samples tested and adding to or subtracting from it three times the standard deviation (average 3). Typical Values Unless otherwise specified, the typical data is based on TA=25C and VCC=3.3 V (1.8VVCC3.6 V). Such data is used for guiding the design only and is not tested. Typical Curve Unless otherwise specified, the typical curve is used for guiding the design only and is not tested. Load Capacitance Figure 4-1 shows the load conditions for measuring pin parameters. Figure 4-1 Load Conditions for Pins Input Voltage of Pin Figure 4-2 shows how to measure the input voltage of a pin. 29 / 57 www.hoperf.com CL<=30pFPIN CMT4531 Figure 4-2 Input Voltage of Pin Power Supply Plan Figure 4-3 Power Supply Plan

(a) VDCDC/VDCDCRF uses the internal DCDC power supply 30 / 57 www.hoperf.com PINVINSWITCH32MHzVDCDCVDCDCRFRFIOP1uF2.2uHVCCGNDXO32MMX032MPVCCRFVDD_PACMT453x0NCNC47pFNC1uF12pF(1)12pF(1)10uF0.1uF1.6nHVDD_FLASH2.2uF3V0.1uF1uF(2) CMT4531

(b) VDCDC/VDCDCRF uses the external power supply

(1)The load capacitance CL required by different crystals or resonators is usually different,refer to section 4.3.6 for details.

(2)In the case of low ripple requirements, the 1uF capacitor can be used without soldering. Current Consumption Measurement Figure 4-4 Current Consumption Measurement Plan 31 / 57 www.hoperf.com SWITCH32MHzVDCDCVDCDCRFRFIOP1uFVCCGNDXO32MMX032MPVCCRFVDD_PACMT453x0NCNC47pFNC12pF(1)12pF(1)10uF0.1uF1.6nHVDD_FLASH2.2uF3V0.1uF1uF1uF(2)VCCVCCRFVSSICC CMT4531 Absolute Maximum Rating The load applied to the device in excess of the value given in the "absolute maximum rating" tables (Tables 4-1, 4-2, and 4-3) may cause permanent damage to the device. The maximum allowable load is given here, but it does not mean that the functions of the device work well under these conditions. The device reliability will be affected if the device works at the maximum conditions for a long time. Table 4-1 Voltage Characteristics Symbol Description Minimum Maximum Unit VCC-VSS External main supply voltage (including VCCRF and VCC)(1)

-0.3 3.6 V VIN Input voltage on other pins(2) VSS-0.3 VCC+0.3 VESD(HBM) Electrostatic discharge (ESD) voltage (human body model) See Section 4.3.10

(1) All power supply (VCC, VCCRF) and ground (VSS) pins must be connected to an external power supply system within the permissible range.

(2) IINJ(PIN) must not exceed its limit (see Table 4-2), ensuring that VIN does not exceed its maximum. If impossible, you need to guarantee that the external limit IINJ(PIN) does not exceed its maximum. When VIN<VSS, there is a reverse injection current. Table 4-2 Current Characteristics Symbol Description Maximum (1) Unit Total current (supply current) passing through VCC/VCCRF power cable(1) 150 IVCC IVSS IIO Total current (output current) passing through VSS ground wire(1) Output sink current of any I/O and control pins Output current of any I/O and control pins Injection current of NRST pin IINJ(PIN)

(2)(3) Injection current of HSE's OSC_IN pin and LSE's OSC_IN pin Injection current of other pins(4) IINJ(PIN)

(2) Total injection current of all I/O and control pins(4) mA 150 12

-12

+/-5

+/-5

+/-12

+/-150

(1) All power supply (VCC, VCCRF) and ground (VSS) pins must be connected to an external power supply system within the permissible range.

(2) IINJ(PIN) must not exceed its limit, ensuring that VIN does not exceed its maximum. If impossible, you need to guarantee that the external limit IINJ(PIN) does not exceed its maximum. 32 / 57 www.hoperf.com CMT4531

(3) When several I/O ports have injection current simultaneously, the maximum IINJ(PIN) is the sum of immediate absolute values of forward injection current and reverse injection current. Table 4-3 Temperature Characteristics Symbol Description Value TSTG TJ Storage temperature range

-40 to + 125 Maximum junction temperature 105 Unit C C Operating Conditions General Operating Conditions Table 4-4 General Operating Conditions Symbol Parameter Condition Minimum Maximum Unit fHCLK Internal AHB clock frequency fPCLK1 Internal APB1 clock frequency fPCLK2 Internal APB2 clock frequency VCC Standard operating voltage VCCRF Analog operating voltage TA Ambient temperature TJ Junction temperature range 64 32 64 3.6 3.6 85 105 MHz V V C C 1.8 1.8

-40

-40 Power-on and Power-off Operating Conditions The parameters in the following table are obtained by testing at the ambient temperature listed in Table 4-4. Table 4-5 Power-on and Power-off Operating Conditions Symbol Parameter Condition Minimum Maximum Unit TVCC VCC rising speed VCC lowering speed VCC=3.3 V 20 100 s/V Characteristics of Built-in Reset and Power Control Module The parameters given in the following table are obtained by testing at the ambient temperature and VCC supply 33 / 57 www.hoperf.com CMT4531 voltage listed in Table 4-4. Table 4-6 Characteristics of Built-in Reset and Power Control Module(1) Symbol Parameter Condition Minimum Typical Value Maximum Unit VBOR VCC threshold power-on voltage VCC threshold power-off voltage TA=25C TA=25C VBORhyst BOR delay TA=25C

(1) They are guaranteed by the design and are not tested in production. Characteristics of DCDC 1.65 1.60 20 V mV DCDC is an internal voltage generation module. The parameters given in the following table are obtained by testing at the ambient temperature and VCC supply voltage listed in Table 4-4. Table 4-7 Built-in DCDC Power Management Module Characteristics (1) Symbol Parameter Condition Minimum Typical Value 3.3 1.15 Maximum Unit V V VCC Supply voltage VDCDC DCDC output voltage Iload DCDC current carrying capacity DCDC conversion efficiency(2) VRPL DCDC output voltage fluctuation L DCDC load inductance COUT DCDC load capacitance tSTAR DCDC output voltage setup time Output current@ VDCDC=1.15 V 20 mA 82.5 10 2.2 2 90

mV H F uS 10 10 1 0.5

(1) They are guaranteed by the design and are not tested in production.

(2) The FDK MIPSDZ1608G2R2PA inductor is used in test. Different inductor models may vary in DCDC efficiency. 34 / 57 www.hoperf.com CMT4531 Characteristics of Supply Current Current consumption is a composite indicator evaluated based on multiple parameters and factors, including operating voltage, ambient temperature, I/O pin load, software configuration, operating frequency, I/O pin switching rate, position of a program in memory, and code executed. For the detailed method to measure current consumption, see Figure 4-4. Typical Current Consumption Table 4-8 Typical Current Consumption in Sleep Mode(1) Symbol Parameter Condition Minimum Typical Value(1) Maximum(1) Unit Current in Sleep mode Low speed clock: ON; 48 KB SRAM retention; I/O state unchanged 1.6 3.8 uA ICC Current in PD mode VCC is maintained; WAKEUP IO and NRST can be woken up 0.13 1.0 uA

(1) The test condition is TA=25C, VCC=3.3 V. Typical Current Consumption in Operating Mode The chip is under the following conditions:

All I/O pins are reset. All peripherals are turned off unless otherwise specified. Ambient temperature and VCC supply voltage conditions are listed in Table 4-4. Table 4-9 Typical Current Consumption in Operating Mode Symbol Parameter Condition Typical Value(1) Maximum Unit ICC Supply current in operating High speed internal RC oscillator mode

(HSI)(2) 2.0 mA

(1) The typical value is measured at TA=25C and VCC=3.3 V.

(2) High speed internal clock is 64 MHz. Table 4-10 BLE Power Dissipation Symbol Parameter Condition Typical Value(1) Maximum Unit 0 dbm transmitting power, VCC 4.2 ICC Supply current in operating current mode Minimum RX sensitivity, VCC 3.8 current mA mA 35 / 57 www.hoperf.com CMT4531 1 s broadcast interval, VCC average 13 current 100 ms broadcast interval, VCC 109 average current 100 ms connection interval, 70 VCC average current uA uA uA

(1) The typical value is measured at TA=25C and VCC=3.3 V. Characteristics of External Clock Source High Speed External Clock Generated Using a Crystal/Ceramic Resonator The high speed external clock (HSE) can be generated by an oscillator consisting of a 32 MHz crystal/ceramic resonator. The data presented in this section is obtained from the overall characteristic evaluation using the typical external components listed in the table below. In applications, the resonator and load capacitor must be as close to the pin of the oscillator as possible to reduce output distortion and stabilization time at startup. For more parameters

(such as frequency, package, and precision) of a crystal resonator, please contact the manufacturer. (The crystal resonator mentioned here usually means the passive crystal oscillator.) Table 4-11 Characteristics of HSE 32 MHz Oscillator(1)(2) Symbol Parameter Condition Minimum Typical Value Maximum Unit fOSC_IN Oscillator frequency CL1 CL2

(3) Recommended load capacitance and corresponding crystal serial impedance RS = 100(4)

(RS)(4) ID HSE drive current VCC=3.3 V, 12 pF load tSU(HSE)

(5) Startup time 32 12 0.2 0.2

(1) Resonator's characteristic parameters are given by the manufacturers of crystal/ceramic resonators.

(2) They are obtained from laboratory tests and are not tested in production. MHz pF mA ms

(3)(4) For CL1 and CL2, it is recommended to use high-quality ceramic dielectric capacitors designed for high frequency applications and select suitable crystals or resonators. CL1 and CL2 usually share same parameters. Crystal manufacturers usually give the parameter of load capacitance as a serial combination of CL1 and CL2. When selecting CL1 and CL2, you should consider the capacitive reactance of PCB and chip pins.

(5) tSU(HSE) is the startup time, which is measured from the moment when the software enables HSE until a stable 32 MHz oscillation is obtained. This value is measured on a standard crystal resonator and may vary greatly depending on the crystal manufacturer. 36 / 57 www.hoperf.com CMT4531 Figure 4-5 Typical Application with a 32 MHz Crystal

(1) The value of REXT depends on the characteristics of the crystal. Low Speed External Clock Generated Using a Crystal/Ceramic Resonator The low speed external clock (LSE) can be generated by an oscillator consisting of a 32.768 kHz crystal/ceramic resonator. The data presented in this section is obtained from the overall characteristic evaluation using the typical external components listed in the table below. In applications, the resonator and load capacitor must be as close to the pin of the oscillator as possible to reduce output distortion and stabilization time at startup. For more parameters

(such as frequency, package, and precision) of a crystal resonator, please contact the manufacturer. (The crystal resonator mentioned here usually means the passive crystal oscillator.) Notes: For CL1 and CL2, it is recommended to use ceramic dielectric capacitors between 8 pF and 20 pF and select suitable crystals or resonators. CL1 and CL2 usually share same parameters. Crystal manufacturers usually give the parameter of load capacitance as a serial combination of CL1 and CL2. Different crystals or resonators usually require different load capacitance (CL). The selected CL1 and CL2 must match the crystal or resonator used. The load capacitance CL is calculated by the formula: CL = CL1 CL2 / (CL1 + CL2) + Cstray, where, Cstray is the capacitance of the pin and the capacitance associated with the PCB or PCB, typically between 2 pF and 7 pF. Table 4-12 Characteristics of LSE Oscillator (fLSE=32.768kHz)(1) Symbol Parameter Condition Minimum Typical Value Maximum Unit CL1 CL2

(2) Recommended load capacitance and corresponding crystal serial impedance (RS)(3) I2 LSE drive current tSU(LSE)

(4) Startup time RS: 30K~90K 10 pF VCC=3.3 V, CL1=CL2=10 Pf, RS=30 K 0.2 0.84 A s

(1) They are obtained from laboratory tests and are not tested in production. 37 / 57 www.hoperf.com 32 MHz resonatorfHSEGain controlRrXO32MP_INXO32MM_OUTCL1CL2REXT(1)Resonator integrated with capacitor CMT4531

(2) See the "Notes" at the top of this table.

(3) Using a high quality oscillator with a small RS value can optimize the current consumption. For more details, please contact the crystal manufacturer.

(4) tSU(LSE) is the startup time, which is measured from the moment when the software enables LSE until a stable 32.768 KHz oscillation is obtained. This value is measured on a standard crystal resonator and may vary greatly depending on the crystal manufacturer. Figure 4-6 Typical Application with a 32.768 kH Crystal Characteristics of Internal Clock Source The characteristic parameters given in the following table are obtained by testing at the ambient temperature and supply voltage listed in Table 4-4. High Speed Internal (HSI) RC Oscillator Table 4-13 Characteristics of HSI Oscillator(1)(2) Symbol Parameter Condition Minimum Typical Value Maximum Unit fHSI Frequency TA = 25C 63.36 64 64.64 MHz TA = -40~105C, temperature drift ACCHSI Temperature drift of HSI oscillator TA = -10~85C, temperature drift TA = 0~70C, temperature drift

-3

-2

-1 tSU(HSI) ICC(HSI) Startup time of HSI oscillator Power dissipation of HSI oscillator

(1) VCC = 3.3 V, TA = -40~105C.

(2) They are guaranteed by the design and are not tested in production. 3 2 1

0.3 s 180 260 A 38 / 57 www.hoperf.com 32.768 kHz resonatorfLSEGain controlRrXO32KP _INXO32KM_OUTCL1CL2Resonator integrated with capacitor CMT4531 Low Speed Internal (LSI) RC Oscillator Table 4-14 Characteristics of LSI Oscillator(1) Symbol Parameter Condition Minimum Typical Value Maximum Unit Calibrated at 25C 31.9 32 32.2 KHz fLSI

(2) Output frequency TA = -40~85C, temperature drift

-1 tSU(LSI) (3) Startup time of LSI oscillator ICC(LSI)

(3) Power dissipation of LSI oscillator

(1) VCC = 3.3 V, TA = -40~85C. 1 200

s A 0.23

(2) They are obtained from laboratory tests and are not tested in production.

(3) They are guaranteed by the design and are not tested in production. Time Required to Wake Up from Low Power Modes The wakeup time listed in Table 4-15 is measured during the wakeup phase of a 64 MHz HSI RC oscillator. The clock source used in wakeup depends on the current operating mode:

Sleep or PD mode: The clock source is a RC oscillator All the time is measured under the ambient temperature and supply voltage listed in Table 4-4. Table 4-15 Time Required to Wake Up from Low Power Modes Symbol Parameter Minimum Typical Value Maximum Unit tWUSLEEP

(1) Wake up from Sleep mode tWUPD

(1) Wake up from PD mode 0.2 42 ms

(1) The wakeup time is measured from the start of the wakeup event to the reading of the first command by the user program. Characteristics of FLASH Memory Unless otherwise specified, all characteristic parameters below are obtained at TA = -40~85C. Table 4-16 Characteristics of Memory Symbol Parameter Condition Minimum Typical Value(1) Maximum(1) Unit tPP Page (256 bytes) programming TA = -40~85C 2 3 ms 39 / 57 www.hoperf.com CMT4531 time tPE Page (256 bytes) erasing time TA = -40~85C tSE Sector (4K byte) erase TA = -40~85C tCE Chip erasing time TA = -40~85C 16 16 16 30 30 30 ms ms ms

(1) They are guaranteed by the design and are not tested in production. Table 4-17 Flash Memory Life and Data Retention Period Symbol Parameter Condition Minimum(1) Unit NEND Life (note: erasure times) TA = -40~85C TA = -40~105C tRET Data retention period TA = 105 10 1 20 Ten thousand times Ten thousand times Year

(1) They are obtained from laboratory tests and are not tested in production. Absolute Maximum (Electrical Sensitivity) The electrical sensitivity is determined by testing the chip strength using specified measurement methods based on three different tests (ESD, LU). Electrostatic Discharge (ESD) Electrostatic discharge (one positive pulse followed by one negative pulse after one second) is applied to all pins of all samples, and the sample size depends on the number of power supply pins on the chip (3 (n+1) power supply pins). This test complies with the MIL-STD-883K and ESDA/JEDEC JS -002-2018 standards. Table 4-18 Absolute Maximum of ESD Symbol Parameter Condition Type Minimum(1) Unit VESD(HBM) ESD voltage (human body model) II 2000 TA = +25C, MIL-STD-883K compliant TA = +25C, V VESD(CDM) ESD voltage (charging device model) ESDA/JEDEC JS -002-2018 II 1000 compliant

(1) They are obtained from laboratory tests and are not tested in production. Static Latch-Up Provide a supply voltage exceeding the limit for each power supply pin. Inject current into each input, output and configurable I/O pin. 40 / 57 www.hoperf.com CMT4531 This test complies with JEDEC78E integrated circuit latch-up standard. Table 4-19 Electrical Sensitivity Symbol Parameter Condition Type LU Static latch-up TA = +25/+85C, JEDEC78E compliant Class II A I/O port characteristics Characteristics of General Purpose Input/Output Unless otherwise specified, the parameters given in the following table are obtained by measuring under the conditions listed in Table 4-4. All I/O ports are compatible with CMOS and TTL. Table 4-20 Static Characteristics of I/O(1)(2) Symbol Parameter Condition Minimum Maximum Unit VIL Input low level voltage VIH Input high level voltage VCC=3.3 V VCC=2.5 V VCC=3.3 V VCC=2.5 V VSS VSS 2 1.7 0.8 0.7 VCC VCC V Vhys Hysteresis voltage of Schmitt trigger(1) VCC=3.3 V/2.5 V 200 mV Ilkg Input leakage current(3) VPAD=0 VPAD=VCC RPU RPD Weak pull-up equivalent VCC=3.3 V resistance(4) VIN= VIL Weak pull-down equivalent VCC=3.3 V resistance(4) VIN= VIH

-1 1 A 120 140 k 120 140 k CIO Capacitance of I/O pin 0.1 pF

(1)(2) Hysteresis voltage of Schmitt trigger's switching level. They are obtained from laboratory tests and are not tested in production.

(3) The leakage current may exceed the maximum if there is reverse sink current on adjacent pins. Output Drive Current GPIO (general purpose input/output port) can absorb or output up to +/-12 mA current. Output Voltage 41 / 57 www.hoperf.com CMT4531 Table 4-21 I/O Output Voltage Symbol Parameter Condition Minimum Maximum Unit VOL Output low level VOH Output high level VCC=3.3, IOH=2 mA, 4 mA, 8 mA, 12 mA VCC=2.5, IOH=2 mA, 4 mA, 8 mA, 12 mA VCC =3.3 V, IOH = -2 mA,

-4 mA, -8 mA, -12 mA VCC =2.5 V, IOH = -2 mA,

-4 mA, -8 mA, -12 mA VSS 0.4 VSS 0.4 2.4 VCC 2 VCC V Input and Output AC Characteristics The definitions and values of input and output AC characteristics are given in Table 4-22. Unless otherwise specified, the parameters given in the following table are obtained by measuring at the ambient temperature and supply voltage listed in Table 4-4. Table 4-22 Input and Output AC Characteristics(1) Register Configuration Symbol Parameter Condition Minimum Maximum Unit fmax(IO)out Maximum frequency 00

(2 mA) t(IO)out Output delay t(IO)in Input delay fmax(IO)out Maximum frequency t(IO)out Output delay 01

(4 mA) CL=5 pF, VCC =3.3 V CL=5 pF, VCC =2.5 V CL=5 pF, VCC =3.3 V CL=5 pF, VCC =2.5 V CL=50 fF, VCC =2.97 V VCC=2.5 V CL=10 pF, VCC =3.3 V CL=10 pF, VCC =2.5 V CL=10 pF, VCC =3.3 V CL=10 pF, VCC =2.5 V 64 50 3.66 4.72 MHz ns 1.2 ns 64 60 3.5 4.5 MHz ns 42 / 57 www.hoperf.com CMT4531 t(IO)in Input delay fmax(IO)out Maximum frequency 10

(8 mA) t(IO)out Output delay t(IO)in Input delay fmax(IO)out Maximum frequency 11 (12 mA) t(IO)out Output delay t(IO)in Input delay CL=50 fF, VCC =2.97 V CL=50 fF, VCC=2.5 V CL=20 pF, VCC =3.3 V CL=20 pF, VCC =2.5 V CL=20 pF, VCC =3.3 V CL=20 pF, VCC =2.5 V CL=50 fF, VCC =2.97 V CL=50 fF, VCC = 2.5 V CL=30 pF, VCC =3.3 V CL=30 pF, VCC =2.5 V CL=30 pF, VCC =3.3 V CL=30 pF, VCC =2.5 V CL=50 fF, VCC =2.97 V CL=50 fF, VCC=2.5 V

(1) They are guaranteed by the design and are not tested in production. Figure 4-7 Definition of Input and Output AC Characteristics 1.2 ns 64 50 3.42 4.73 MHz ns 1.2 ns 64 50 3.34 4.26 MHz ns 1.2 ns Characteristics of NRST Pins The NRST pin's input drive uses the CMOS process and is connected with a pull-up resistor RPU that cannot be disconnected. Unless otherwise specified, the parameters given in Table 4-23 are obtained by measuring at the ambient temperature and supply voltage listed in Table 4-4. Table 4-23 Characteristics of NRST Pins Symbol Parameter Condition Minimum Typical Maximum Unit 43 / 57 www.hoperf.com 90%V110%V190%V110%V1trtf50%V150%V1tdrtdf50%V150%V1 CMT4531 VIL(NRST)

(1) NRST input low level voltage VCC = 3.3 V Vss VIH(NRST)

(1) NRST input high level voltage VCC = 3.3 V Vhys(NRST)

(1) Hysteresis voltage of NRST Schmitt trigger

2

Value

0.8 VCC V 200

mV RPU Weak pull-up equivalent resistance VCC = 3.3 V 40 50 60 k VF(NRST)

(1) NRST input filter pulse VNF(NRST)

(1) NRST input unfiltered pulse

5

500

ns us

(1) They are guaranteed by the design and are not tested in production. Figure 4-8 Recommended NRST Pin Protection

(1) The external reset network is to avoid a parasitic reset.

(2) Users must ensure that the potential of the NRST pin is below the maximum VIL(NRST) listed in Table 4-23. Otherwise, the chip cannot be reset. Characteristics of TIM Timer The parameters given in Table 4-24 are obtained by measuring at the ambient temperature and supply voltage listed in Table 4-4. Table 4-24 Characteristics of TIMx(1)(2) Symbol Parameter Condition Minimum Maximum Unit tres(TIM) Timer resolution time 1 fTIMxCLK= 64 MHz 15.625 tTIMxCLK ns fEXT Timer's external clock frequency 0 fTIMxCLK/2 MHz 44 / 57 www.hoperf.com FilterInternal resetExternal reset network(1)NRST2 CMT4531

(CH1~CH4) ResTIM Timer resolution tCOUNTER Clock period of a 16-bit counter when an internal clock is selected tMAX_COUNT Maximum possible count

(1) TIMx is a generic name that represents TIM1/TIM3/TIM6.

(2) Parameters are guaranteed by the design. Characteristics of I2C Interface 0 1 32 16 MHz Bit 65536 tTIMxCLK 0.015625 1024 s 65536x65536 tTIMxCLK 67.1 s Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature, fPCLK1 frequency, and VCC supply voltage listed in Table 4-4. The I2C interface conforms to the standard I2C communication protocol, but is subject to the following limitations:

SDA and SCL are not "real" open-drain pins, and when they are configured as output open-drain, the PMOS transistor between the lead-out pin and VCC is turned off, but still exists. The characteristics of I2C interface are shown in the table below. For more details on the characteristics of the input/output alternate function pins (SDA and SCL), see Section 4.3.11. 45 / 57 www.hoperf.com CMT4531 Table 4-25 Characteristics of I2C Interface(1) Symbol Parameter Unit Minimum Maximum Minimum Maximum Standard Mode Fast Mode I2C Interface Frequency 100 1000 KHz Start condition holding time tw(SCLL) SCL clock low time tw(SCLH) SCL clock high time Setup time for a repeated start condition 4.0 4.7 4.0 4.7 0.6 1.3 0.6 0.6 s s s s s ns SDA data hold time 3.4 0.9 SDA setup time 250.0 100 SDA and SCL rise time 1000 20 300 ns SDA and SCL fall time 300 300 ns fSCL th(STA) tsu(STA) th(SDA) tsu(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(STO) Setup time for a stop condition 4.0 tw(STO:STA) Time from stop condition to start condition (bus idle) 4.7 0.6 1.3 Cb Capacitive load per bus 400 100 tv(SDA) tv (ACK) Data validity time 3.45 Valid time of acknowledgement 3.45 0.9 0.9 s s pf s s

(1) They are guaranteed by the design and are not tested in production.

(2) To reach the maximum frequency of standard mode I2C, fPCLK1 must be greater than 2 MHz. To reach the maximum frequency of fast mode I2C, fPCLK1 must be greater than 4 MHz. 46 / 57 www.hoperf.com CMT4531 Figure 4-9 AC Waveform and Measuring Circuit of I2C Bus(1)

(1) The measuring points are set at CMOS levels: 0.3 VCC and 0.7 VCC. Characteristics of SPI Unless otherwise specified, the SPI parameters are obtained by measuring at the ambient temperature, fPCLK2 frequency, and VCC supply voltage listed in Table 4-4. For more details on the characteristics of the input/output alternate function pins (NSS, SCLK, MOSI, MISO), see Section 4.3.11. Table 4-26 Characteristics of SPI(1) Symbol Parameter Condition Minimum Maximum Unit fSCLK 1/tc(SCLK) SPI clock frequency Master mode Slave mode tr(SCLK)tf(SCLK) SPI's clock rise and fall time Load capacitance: C = 30 pF DuCy(SCK) Duty cycle of SPI's slave input clock SPI slave mode tsu(NSS) (1) NSS setup time Slave mode th(NSS)

(1) NSS hold time Slave mode

30 4tPCLK 2tPCLK 16 16 8 70

MHz ns

ns ns tw(SCLKH)

(1) SCLK high and low time Master mode tPCLK - 2 tPCLK + 2 ns 47 / 57 www.hoperf.com SDASCL100 100 VCCVCC4.7 K4.7 K(2)(2){I2C bustw(SCKL)tw(SCKH)tr(SCK)tf(SCK)1/fSCL1st clock cycle9th clocktf(SDA)tr(SDA)tv(SDA)tsu(SDA)th(SDA)tv(ACK){tsu(STA)tsu(STO)tw(STA:STO)Start conditionRepeated start conditionStop conditionStart conditionth(STA)SDASCL CMT4531 tw(SCLKL)

(1) tsu(MI )

(1) Master mode Data input setup time tsu(SI)

(1) th(MI)

(1) th(SI)

(1) Data input hold time Slave mode Master mode Slave mode SPI1 SPI2 SPI1 SPI2 ta(SO)

(1)(2) Data output access time Slave mode, fPCLK = 32 MHz tdis(SO)

(1)(3) Data output disabled time Slave mode tv(SO)

(1) tv(MO)

(1) th(SO)

(1) th(MO)

(1) Data output valid time Data output hold time Slave mode (after enabled edge) SPI1 SPI2 Master mode SPI1

(after enabled edge) SPI2 Slave mode (after enabled edge) Master mode (after enabled edge) 5 6 5 6 4 3 0 2 2 0

3tPCLK 10 16 20 8 10 ns ns ns ns ns ns

(1) They are obtained from laboratory tests and are not tested in production.

(2) The minimum represents the minimum time to drive the output, and the maximum represents the maximum time to obtain the data correctly.

(3) The minimum represents the minimum time to turn off the output, and the maximum represents the maximum time to put the data line in a high impedance state. 48 / 57 www.hoperf.com CMT4531 Figure 4-10 SPI Sequence DiagramSlave Mode and CPHA=0 Figure 4-11 SPI Sequence DiagramSlave Mode and CPHA=1(1)

(1) The measuring points are set at CMOS levels: 0.3 VCC and 0.7 VCC. 49 / 57 www.hoperf.com tc(SCLK)Output MSBOutput bits 6~1Input MSBInput bits 6~1Output LSBInput LSBNSS inputCLKPHA=0CLKPOL=0MISO outputMOSI inputCLKPHA=0CLKPOL=1ta(SO)tdls(SO)th(NSS)tsu(NSS)tw(SCLKH)tw(SCLKL)tr(SCLK)tf(SCLK)th(SI)tsu(SI)tv(SO)th(SO)tc(SCLK)Output MSBOutput bits 6~1Input MSBInput bits 6~1Output LSBInput LSBNSS inputCLKPHA=1CLKPOL=0MISO outputMOSI inputCLKPHA=1CLKPOL=1ta(SO)tdls(SO)th(NSS)tsu(NSS)tw(SCLKH)tw(SCLKL)tr(SCLK)tf(SCLK)th(SI)tsu(SI)tv(SO)th(SO) CMT4531 Figure 4-12 SPI Sequence DiagramMaster Mode(1)

(1) The measuring points are set at CMOS levels: 0.3 VCC and 0.7 VCC. Characteristics of Temperature Sensor (TS) Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature, fHCLK frequency, and VCC supply voltage listed in Table 4-4. Table 4-27 Characteristics of Temperature Sensor Symbol Parameter Minimum Typical Value Maximum Unit TL

(1) VSENSE Linearity with respect to temperature Avg_Slope(1) Average slope tSTART

(1) Setup time 4 2.14(2) C mV/C 10 s

(1) They are guaranteed by the design and are not tested in production.

(2) They are obtained from laboratory tests and are not tested in production. Characteristics of ADC Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature, fHCLK frequency, and VCC supply voltage listed in Table 4-4. 50 / 57 www.hoperf.com NSS inputCLKPHA=0CLKPOL=0MISO outputMOSI inputCLKPHA=0CLKPOL=1CLKPHA=1CLKPOL=0CLKPHA=1CLKPOL=1Output MSBOutput bits 6~1Input LSBInput MSBInput bits 6~1Input LSBtr(SCLK)tf(SCLK)th(MO)tv(MO)tw(SCLKH)tw(SCLKL)tsu(MI)th(MI)tc(SCLK) CMT4531 Table 4-28 Characteristics of ADC Symbol Parameter Test Condition Minimum Typical Value Maximum Unit VREF+

Positive reference voltage 1.0 V fADC ADC sampling rate VAIN Voltage conversion range, external low voltage path Voltage conversion range, external high voltage path RADC Sampling switch resistance CADC Internal sampling and holding capacitance SNDR Ingal noise distortion ration SNDR Ingal noise distortion ration tSTAB

(1) Power-on time tCONV

(1) Conversion time Input Frequency=1.03 KHz, VCC=3.3 V, TA=25C fADC=1Msps Input Frequency=0.98 KHz, VCC=3.3 V, TA=25C fADC=16 Ksps DNL Differential linear error VCC=3.3 V, TA=25C, INL Integral linear error VCC=3.3 V, TA=25C

(1) They are obtained from laboratory tests and are not tested in production.

(2) The maximum value 3600 mV and <= VCC+ 300 mV. Characteristics of PGA 1.33 MHz 1000 mV

3600(2) mV 46 58 16 k pF dBFS dBFS us ns LSB LSB 6 2 0 0 752

-1

-8 Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature and VCC supply voltage listed in Table 4-4. 51 / 57 www.hoperf.com CMT4531 Table 4-29 Characteristics of PGA Symbol Parameter Test Condition Minimum Typical Value Maximum Unit GAIN PGA gain GAIN STEP PGA gain step THD+N(1) Gain=0dB Gain=42 dB In-band ripple(1) Gain fluctuation in 3003400 Hz band TPGA

(1) PGA setup time 0 73 73 42 85 87 dB dB dB dB dB ms 6 82 83 0.78 15 MIC_BIAS voltage MIC_BIAS Noise(1) MIC bias voltage, step=0.1 V 1.6 2.3 V 20Hz to 8kHz A-weighted with 4.7uF

-92 dBV

(1) They are obtained from laboratory tests and are not tested in production. Characteristics of KEYSCAN Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature and VCC supply voltage listed in Table 4-4. Table 4-30 Characteristics of KEYSCAN Symbol Parameter TWTS Time interval for each round of keyboard scanning Test Condition Minimum Typical Value Maximum Unit 32 224 ms TDTS Key jitter elimination time 10 640 ms Power dissipation in automatic TDTS=40 ms, TWTS=32 ms scanning mode (104 keys) VCC=3.3 V, TA=25 C Icc(1) Power dissipation in low power mode VCC=3.3 V, TA=25 C

(104 keys) 2.9 2.3 uA uA

(1) They are obtained from laboratory tests and are not tested in production. Characteristics of BLE Unless otherwise specified, the parameters below are obtained by measuring at the ambient temperature and VCC 52 / 57 www.hoperf.com CMT4531 supply voltage listed in Table 4-4. Table 4-31 BLE Receiving Characteristics(1) No. Parameter Test Condition Minimum Typical Maximu Unit Value m 1 2 3 4 5 6 7 8 9 Sensitivity, 1 Mbps VCC=3.3 V, TA=25 C Sensitivity, 2 Mbps Co-channel interference Adjacent channel interference, +-1 MHz Adjacent channel interference, +-2 MHz Adjacent channel interference, >=+-3 MHz Mirror channel interference Adjacent mirror channel interference,

+-1 MHz Maximum input power

-96

-93 8 1

-31

-40

-24

-28 6 dBm dBm dB dB dB dB dB dB dBm

(1) They are obtained from laboratory tests and are not tested in production. Table 4-32 BLE Transmitting Characteristics(1) No. Parameter Test Condition Minimum Typical Maximum Unit 1 2 3 4 5 6 7 Output power VCC=3.3 V, TA=25 C Frequency accuracy Frequency drift rate Frequency drift Initial frequency drift f1 average f2 99.9%

Value 6 7.5

-9.4

-15.1

-13.2 258 218 dBm kHz kHz/50us kHz kHz kHz kHz 53 / 57 www.hoperf.com CMT4531 8 9 f2/f1 Harmonic power, second harmonic 10 Harmonic power, third harmonic 11 Harmonic power, fourth harmonic 12 Harmonic power, quintuple harmonic

(1) They are obtained from laboratory tests and are not tested in production. 1.06

-26

-28

-54

-55

dBm dBm dBm dBm 54 / 57 www.hoperf.com CMT4531 5 Package Size QFN32 Figure 5-1 QFN32 Package Size 55 / 57 www.hoperf.com 6 Version History Date 2023/5/23 Version Modification V1.3 Initial version CMT4531 56 / 57 www.hoperf.com FCC Statement FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate this device. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Note: This device has been tested and found to comply with the limits for a Class B digital device, according to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This device generates, uses, and can radiate radio frequency energy and, if not installed and used following the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this device does cause harmful interference to radio or television reception, which can be determined by turning the device off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the device and receiver. Connect the device into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Radiation Exposure Statement This device complies with FCC radiation exposure limits set forth for an uncontrolled rolled environment. This device should be installed and operated with a minimum distance of 20cm between the radiator and your body. Important Note This radio module must not be installed to co-locate and operating simultaneously with other radios in the host system except following FCC multi-transmitter product procedures. Additional testing and device authorization may be required to operate simultaneously with other radios. The availability of some specific channels and/or operational frequency bands are country dependent and are firmware programmed at the factory to match the intended destination. The firmware setting is not accessible by the end-user. The host product manufacturer is responsible for compliance with any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. The final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. The end-user manual shall include all required regulatory information/warnings as shown in this manual, including This product must be installed and operated with a minimum distance of 20 cm between the radiator and user body. This device has got an FCC ID: 2ASEO-HM-BT4531. The end product must be labeled in a visible area with the following:

Contains Transmitter Module FCC ID: 2ASEO-HM-BT4531. This device is intended only for OEM integrators under the following conditions:

The antenna must be installed such that 20cm is maintained between the antenna and users, and the transmitter module may not be co-located with any other transmitter or antenna. As long as the 2 conditions above are met, further transmitter tests will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. ISED Statement:

This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canadas licence-exempt RSS(s). Operation is subject to the following two conditions:

1.This device may not cause interference. 2.This device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil contient des metteurs/rcepteurs exempts de licence qui sont conformes aux RSS exempts de licence d'Innovation, Sciences et Dveloppement conomique Canada. L'exploitation est soumise aux deux conditions suivantes :

1.Cet appareil ne peut pas provoquer d'interfrences. 2.Cet appareil doit accepter toute interfrence, y compris les interfrences susceptibles de provoquer un fonctionnement indsirable de l'appareil. This device has got an IC: 24999-HMBT4531. The end product must be labeled in a visible area with the following:

Contains Transmitter Module IC: 24999-HMBT4531. Cet appareil a un IC:24999-HMBT4531. Le produit final doit tre tiquet dans une zone visible avec ce qui suit?"Contient le circuit intgr du module metteur?IC: 24999-HMBT4531". Le manuel de l'utilisateur final doit inclure toutes les informations/avertissements rglementaires requis, comme indiqu dans ce manuel, y compris "Ce produit doit tre install et utilis avec une distance minimale de 20 cm entre le radiateur et le corps de l'utilisateur". 57 / 57

Shenzhen Hope Microelectronics Co.,Ltd 2023-06-05 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: LETTER OF AGENT AUTHORIZATION To Whom It May Concern:

We, the undersigned, hereby authorize DongGuan Anci Electronic Technology Co., Ltd. to act on our behalf in all matters relating to application for equipment authorization, including the signing of all documents relating to these matters. We also hereby certify that no party to the application authorized hereunder is subject to the denial of benefits, including FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C.853(a). This agreement expires one year from the current date. Sincerely, Daniel Chen Manager Shenzhen Hope Microelectronics Co., Ltd 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan

Shenzhen Hope Microelectronics Co., Ltd 2023-06-05 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: Attestation Statements Part 2.911(d)(5)(i) request for (FCC ID: 2ASEO-HM-BT4531)

[ Shenzhen Hope Microelectronics Co., Ltd.] (the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Sincerely, Daniel Chen Manager Shenzhen Hope Microelectronics Co., Ltd 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan Shenzhen Hope Microelectronics Co., Ltd 2023-06-05 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: Attestation Statements Part 2.911(d)(5)(ii) request for(FCC ID: 2ASEO-HM-BT4531)

[Shenzhen Hope Microelectronics Co., Ltd.] (the applicant) certifies that, as of the date of the filing of the application, the applicant is not identified on the Covered List as an entity producing covered equipment. Sincerely, Sincerely, Daniel Chen Manager Shenzhen Hope Microelectronics Co., Ltd 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan

Shenzhen Hope Microelectronics Co., Ltd. 2023-06-05 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: CONFIDENTIALITY REQUEST FOR (EUT Name: Nanoleaf BLE&Thread-Matter module /Model: HM-BT4531 /FCC ID: 2ASEO-HM-BT4531) To Whom It May Concern:

This letter serves as an official request for confidentiality under sections 0.457 and 0.459 of CFR 47. We have requested that the (Block Diagram ,Operational Description,Schematics) required to be submitted with this application be permanently withheld from public review. The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these materials may be harmful to the applicant and provide unjustified benefits to its competitors. Please contact me if there is any information you may need. Sincerely, Daniel Chen Manager Shenzhen Hope Microelectronics Co., Ltd 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan

Shenzhen Hope Microelectronics Co., Ltd Request for Modular/Limited Modular Approva l Date: June 5, 2023 Subject: Manufacturers Declaration for - Modular Approval

- Split Modular Approval

- Limited Modular Approval - Limited Split Modular Approval Confidentiality Request for: ______2ASEO-HM-BT4531 ______ 8 Basic Requirements FCC Part 15.212(a)(1) For Items Marked NO(*), the Limited Module Description Must be Filled Out on the Following Pages Modular Approval Requirement Requirement Met 1. The modular transmitter must have its own RF shielding. This is intended to ensure that the module does not have to rely upon the shielding provided by the device into which it is installed in order for all modular transmitter emissions to comply with FCC limits. It is also intended to prevent coupling between the RF circuitry of the module and any wires or circuits in the device into which the module is installed. Such coupling may result in non-compliant operation. The physical crystal and tuning capacitors may be located external to the shielded radio elements. 15.212(a)(1)(i)

- YES - NO(*) 2. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with FCC requirements under conditions of excessive data rates or over-modulation. 15.212(a)(1)(ii)

- YES - NO(*) 3. The modular transmitter must have its own power supply regulation on the module. This is intended to ensure that the module will comply with FCC requirements regardless of the design of the power supplying circuitry in the device into which the module is installed. 15.212(a)(1)(iii)

- YES - NO(*) 4. The modular transmitter must comply with the antenna and transmission system requirements of 15.203, 15.204(b), 15.204(c), 15.212(a), and 2.929(b). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph 15.212(b). 15.212(a)(1)(iv)

- YES - NO(*) 5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified or commercially available (see Section 15.31(i)). 15.212(a)(1)(v)

- YES - NO(*) Shenzhen Hope Microelectronics Co., Ltd Modular Approval Requirement 6. The modular transmitter must be labeled with its own FCC ID number, or use an electron display (see t Requirement Me KDB Publication 784748). If using a permanently affixed label with its own FCC ID number, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: XYZMODEL1 or Contains FCC ID:

XYZMODEL1. Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization. If the modular transmitter uses an electronic display of the FCC identification number, the information must be readily accessible and visible on the modular transmitter or on the device in which it is installed. If the module is installed inside another device, then the outside of the device into which the module is installed must display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains FCC certified transmitter module(s). Any similar wording that expresses the same meaning may be used. The user manual must include instructions on how to access the electronic display. A copy of these instructions must be included in the application for equipment authorization. 15.212(a)(1)(vi)

- YES - NO(*) 7. The modular transmitter must comply with all specific rule or operating requirements applicable to the transmitter, including all the conditions provided in the integration instructions by the grantee. A copy of these instructions must be included in the application for equipment authorization. For example, there are very strict operational and timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. 15.212(a)(1)(vii)

- YES - NO(*) 8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance in accordance with Section 15.247(b)(4). Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. 15.212(a)(1)(viii)

- YES - NO(*) Shenzhen Hope Microelectronics Co., Ltd Limited Module Description When Applicable

* If a module does NOT meet one or more of the above 8 requirements, the applicant may request Limited Modular Approval (LMA). This Limited Modular Approval (LMA) is applied with the understanding that the applicant will demonstrate and will retain control over the final installation of the device, such that compliance of the end product is always assured. The operating condition(s) for the LMA;

the module is only approved for use when installed in devices produced by grantee. A description regarding how control of the end product, into which the module will be installed, will be maintained by the applicant/manufacturer, such that full compliance of the end

. product is always ensured should be provided here Details: <example - N/A>

Software Considerations KDB 594280 / KDB 442812 (One of the following 2 items must be applied) Requirement 1. For non-Software Defined Radio transmitter modules where software is used to ensure compliance of the device, technical description must be provided about how such control is implemented to ensure prevention of third-party modification; see KDB Publication 594280. Requirement Met

- Provided in Separate Cover Letter

- N/A 2. For Software Defined Radio (SDR) devices, transmitter module applications must provide a software security description; see KDB Publication 442812.

- Provided in Separate Cover Letter

- N/A Split Modular Requirements Requirement Provided in Manual 1. For split modular transmitters, specific descriptions for secure communications between front-end and control sections, including authentication and restrictions on third-party modifications; also, instructions to third-party integrators on how control is maintained.

- Provided in Separate Cover Letter

- N/A Shenzhen Hope Microelectronics Co., Ltd OEM Integration Manual Guidance KDB 996369 D03 Section 2 Clear and Specific Instructions Describing the Conditions, Limitations, and Procedures

. for third-parties to use and/or integrate the module into a host device Requirement Is this module intended for sale to third parties?

- YES

- No, If No, and LMA applies, the applicant can optionally choose to not make the following detailed info public. However there still needs to be basic integration instructions for a users manual and the information below must still be included in the operational description. If the applicant wishes to keep this info confidential, this will require a separate statement cover letter explaining the module is not for sale to third parties and that integration instructions are internal confidential documents. Items required to be in the manual See KDB 996369 D03, Section 2 As of May 1, 2019, the FCC requires ALL the following information to be in the installation manual. Modular transmitter applicants should include information in their instructions for all these items indicating clearly when they are not applicable. For example information on trace antenna design could indicate Not Applicable. Also if a module is limited to only a grantees own products and not intended for sale to third parties, the user instructions may not need to be detailed and the following items can be placed in the operational description, but this should include a cover letter as cited above. 1. List of applicable FCC rules. KDB 996369 D03, Section 2.2 a. Only list rules related to the transmitter. 2. Summarize the specific operational use conditions. KDB 996369 D03, Section 2.3 a. Conditions such as limits on antennas, cable loss, reduction of power for point to point 3. Limited Module Procedures. KDB 996369 D03, Section 2.4 systems, professional installation info a. Describe alternative means that the grantee uses to verify the host meets the necessary limiting conditions b. When RF exposure evaluation is necessary, state how control will be maintained such that compliance is ensured, such as Class II for new hosts, etc. 4. Trace antenna designs. KDB 996369 D03, Section 2.5 a. Layout of trace design, parts list, antenna, connectors, isolation requirements, tests for design verification, and production test procedures for ensuring compliance. If confidential, the method used to keep confidential must be identified and information provided in the operational description. 5. RF exposure considerations. KDB 996369 D03, Section 2.6 a. Clearly and explicitly state conditions that allow host manufacturers to use the module. Two types of instructions are necessary: first to the host manufacturer to define conditions (mobile, portable xx cm from body) and second additional text needed to be provided to the end user in the host product manuals. 6. Antennas. KDB 996369 D03, Section 2.7 a. List of antennas included in the application and all applicable professional installer instructions when applicable. The antenna list shall also identify the antenna types

(monopole, PIFA, dipole, etc note that omni-directional is not considered a type) 7. Label and compliance information. KDB 996369 D03, Section 2.8 a. Advice to host integrators that they need to provide a physical or e-label stating Contains FCC ID: with their finished product

- All Items shown to the left are provided in the Modular Integration Guide (or UM) for Full Modular Approval (MA) or LMA.

- An LMA applies and is approved ONLY for use by the grantee in their own products, and not intended for sale to 3rd parties as provided in a separate cover letter. Therefore the information shown to the left is found in the theory of operation. a. 8. Information on test modes and additional testing requirements. KDB 996369 D03, Section 2.9 Test modes that should be taken into consideration by host integrators including clarifications necessary for stand-alone and simultaneous configurations. Provide information on how to configure test modes for evaluation 9. Additional testing, Part 15 Subpart B disclaimer. KDB 996369 D03, Section 2.10 b. Sincerely, By:

Daniel Chen_ / Manager_

(Signature/Title1) ________________________

(Print name) 1 - Must be signed by applicant contact given for applicant on the FCC site, or by the authorized agent if an appropriate Shenzhen Hope Microelectronics Co., Ltd authorized agent letter has been provided. Letters should be placed on appropriate letterhead.

Attestation Statements

(2023-05-26) TO: Federal Communications Commission Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046, USA RE: Attestation Statements Part 2.911(d)(7) request for (2ASEO-HM-BT4531}

(Shenzhen Hope Microelectronics Co., Ltd }, the undersigned, hereby authorize (Wilson Tech Service LLC) to act as our designated U.S. agent for service of process, (Shenzhen Hope Microelectronics Co., Ltd} accepts to maintain an agent for no less than one year after the grantee has terminated all marketing and importation or the conclusion of any Commission-related proceeding involving the equipment.

(Wilson Tech Service LLC} accepts the responsibility to act as designated U.S. agent for service of process. Applicant Information:

Company name: Shenzhen Hope Microelectronics Co., Ltd Contact Name: Daniel Chen Address: 30th floor of 8th Building, C Zone Vanke Cloud City, Xili Sub-district, Nanshan Telephone No: +8675582973805 Email: danielchen@hoperf.com Signature Daniel Chen

[name] Daniel Chen U.S. Agent Information:

Company Name: Wilson Tech Service LLC Address: 1312 17th Street Suite 692, Denver, CO, 80202, US Contact Name: Wilson Cheung Telephone No: 17169655112 FRN: 0033402033 Email: Wilson.Cheung.FDA@gmail.com Signature vy

[name] Wilson Cheung