FCC ID: XPY2AGQN4NNN Cellular Module

 

Smart Pill Bottle User Manual AdhereTechs User Information for FCC For a copy of the User Manual specific to a particular use-case, please email support@adheretech.com. The Smart Pill Bottle can produce helpful reminder alerts to help patients stay adherent. To start using the bottle, peel & remove the entire pull-tab pouch from the Bottle. The Bottle will then light up &

chime to show that it is activated & ready to use. With normal use, the battery in the Bottle lasts up to six months from the moment when the Bottle is first used until it needs to be recharged. Battery life will vary based on the Bottles alert settings and patient use. It takes approximately eight hours of charging for the Bottle to be fully recharged. FCC INFORMATION FOR USER This equipment has been tested and found to comply with the limits for a class B digital device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment to an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio/TV technician for help AdhereTech 11 Broadway, Suite 457 New York, NY 10004 1-800-381-9384 www.adheretech.com

 

 

SARA-R4/N4 series System Integration Manual System Integration Manual SARA-R4/N4 Abstract This document describes the features and the integration of the size-optimized SARA-R4/N4 series cellular modules. These modules are a complete, cost efficient, performance optimized, multi-mode and multi band LTE Cat M1 / NB1 and EGPRS solution in the compact SARA form factor. www.u-blox.com UBX-16029218 - R11 SARA-R4/N4 series - System Integration Manual Document Information Title Subtitle SARA-R4/N4 series System Integration Manual Document type System Integration Manual Document number UBX-16029218 Revision and date R11 20-Feb-2019 Disclosure Restriction Product status Corresponding content status Functional Sample Draft For functional testing. Revised and supplementary data will be published later. In Development /

Objective Specification Target values. Revised and supplementary data will be published later. Prototype Engineering Sample Advance Information Data based on early testing. Revised and supplementary data will be published later. Initial Production Early Production Information Data from product verification. Revised and supplementary data may be published later. Mass Production /

Production Information Document contains the final product specification. End of Life This document applies to the following products:

Product name Type number Modem version Application version PCN reference Product status SARA-R404M SARA-R404M-00B-00 K0.0.00.00.07.06 SARA-R404M-00B-01 K0.0.00.00.07.08 SARA-R410M SARA-R410M-01B-00 L0.0.00.00.02.03 UBX-17047084 End of Life UBX-18053670 Initial Production UBX-17051617 Initial Production SARA-R410M-02B-00 L0.0.00.00.05.06 A02.00 UBX-18010263 Initial Production SARA-R410M-52B-00 L0.0.00.00.06.05 A02.06 UBX-18045915 Initial Production SARA-R412M SARA-R412M-02B-00 M0.09.00 A02.11 UBX-19004091 Initial Production SARA-N410 SARA-N410-02B-00 L0.0.00.00.07.07 A02.09 UBX-18057459 Initial Production u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided as is and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. Copyright u-blox AG. UBX-16029218 - R11 Page 2 of 157 SARA-R4/N4 series - System Integration Manual Contents Document Information ............................................................................................................................ 2 Contents...................................................................................................................................................... 3 1 System description ............................................................................................................................ 7 1.1 Overview ........................................................................................................................................................................................... 7 1.2 Architecture ................................................................................................................................................................................... 11 1.3 Pin-out ............................................................................................................................................................................................. 12 1.4 Operating modes ....................................................................................................................................................................... 17 1.5 Supply interfaces ........................................................................................................................................................................ 21 1.5.1 Module supply input (VCC) ......................................................................................................................................... 21 1.5.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 28 1.6 System function interfaces ..................................................................................................................................................... 30 1.6.1 Module power-on ............................................................................................................................................................ 30 1.6.2 Module power-off ............................................................................................................................................................ 31 1.6.3 Module reset ...................................................................................................................................................................... 33 1.7 Antenna interface ....................................................................................................................................................................... 35 1.7.1 Antenna RF interface (ANT) ......................................................................................................................................... 35 1.7.2 Antenna detection interface (ANT_DET) ................................................................................................................ 36 1.8 SIM interface................................................................................................................................................................................. 36 1.8.1 SIM interface ...................................................................................................................................................................... 36 1.8.2 SIM detection interface ................................................................................................................................................. 37 1.9 Data communication interfaces ........................................................................................................................................... 38 1.9.1 UART interface ................................................................................................................................................................... 38 1.9.2 USB interface ...................................................................................................................................................................... 40 1.9.3 SPI interface ........................................................................................................................................................................ 42 1.9.4 SDIO interface .................................................................................................................................................................... 42 1.9.5 DDC (I2C) interface........................................................................................................................................................... 42 1.10 Audio ................................................................................................................................................................................................ 42 1.11 General Purpose Input/Output ............................................................................................................................................ 44 1.12 Reserved pins (RSVD) ............................................................................................................................................................... 44 1.13 System features ........................................................................................................................................................................... 45 UBX-16029218 - R11 Page 3 of 157 SARA-R4/N4 series - System Integration Manual 1.13.1 Network indication .......................................................................................................................................................... 45 1.13.2 Antenna supervisor.......................................................................................................................................................... 45 1.13.3 Dual stack IPv4/IPv6........................................................................................................................................................ 45 1.13.4 TCP/IP and UDP/IP .......................................................................................................................................................... 45 1.13.5 FTP ........................................................................................................................................................................................... 45 1.13.6 HTTP ....................................................................................................................................................................................... 46 1.13.7 Firmware update Over AT (FOAT) ............................................................................................................................ 46 1.13.8 Firmware update Over The Air (uFOTA) ................................................................................................................ 46 1.13.9 Power saving ...................................................................................................................................................................... 47 2 Design-in ........................................................................................................................................... 51 2.1 Overview ......................................................................................................................................................................................... 51 2.2 Supply interfaces ........................................................................................................................................................................ 53 2.2.1 Module supply (VCC) ..................................................................................................................................................... 53 2.2.2 Generic digital interfaces supply output (V_INT) .............................................................................................. 75 2.3 System functions interfaces ................................................................................................................................................... 76 2.3.1 Module power-on (PWR_ON)..................................................................................................................................... 76 2.3.2 Module reset (RESET_N) ................................................................................................................................................ 78 2.4 Antenna interface ....................................................................................................................................................................... 79 2.4.1 Antenna RF interface (ANT) ......................................................................................................................................... 79 2.4.2 Antenna detection interface (ANT_DET) ................................................................................................................ 88 2.5 SIM interface................................................................................................................................................................................. 92 2.5.1 Guidelines for SIM circuit design ............................................................................................................................. 92 2.5.2 Guidelines for SIM layout design ............................................................................................................................. 97 2.6 Data communication interfaces ........................................................................................................................................... 98 2.6.1 UART interface ................................................................................................................................................................... 98 2.6.2 USB interface ................................................................................................................................................................... 105 2.6.3 SPI interface ..................................................................................................................................................................... 107 2.6.4 SDIO interface ................................................................................................................................................................. 107 2.6.5 DDC (I2C) interface........................................................................................................................................................ 107 2.7 Audio ............................................................................................................................................................................................. 111 2.7.1 Guidelines for Audio circuit design ...................................................................................................................... 111 2.8 General Purpose Input/Output ......................................................................................................................................... 111 2.8.1 Guidelines for GPIO circuit design ........................................................................................................................ 111 UBX-16029218 - R11 Page 4 of 157 SARA-R4/N4 series - System Integration Manual 2.8.2 Guidelines for general purpose input/output layout design ................................................................... 112 2.9 Reserved pins (RSVD) ............................................................................................................................................................ 113 2.10 Module placement .................................................................................................................................................................. 113 2.11 Module footprint and paste mask .................................................................................................................................. 114 2.12 Thermal guidelines ................................................................................................................................................................. 115 2.13 Schematic for SARA-R4/N4 series module integration ......................................................................................... 116 2.13.1 Schematic for SARA-R4/N4 series modules ..................................................................................................... 116 2.14 Design-in checklist .................................................................................................................................................................. 118 2.14.1 Schematic checklist ...................................................................................................................................................... 118 2.14.2 Layout checklist .............................................................................................................................................................. 118 2.14.3 Antenna checklist .......................................................................................................................................................... 119 3 Handling and soldering ................................................................................................................ 120 3.1 Packaging, shipping, storage and moisture preconditioning ............................................................................. 120 3.2 Handling ...................................................................................................................................................................................... 120 3.3 Soldering ..................................................................................................................................................................................... 122 3.3.1 Soldering paste .............................................................................................................................................................. 122 3.3.2 Reflow soldering ............................................................................................................................................................ 122 3.3.3 Optical inspection ......................................................................................................................................................... 124 3.3.4 Cleaning ............................................................................................................................................................................. 124 3.3.5 Repeated reflow soldering ........................................................................................................................................ 124 3.3.6 Wave soldering .............................................................................................................................................................. 124 3.3.7 Hand soldering ............................................................................................................................................................... 125 3.3.8 Rework ................................................................................................................................................................................ 125 3.3.9 Conformal coating ........................................................................................................................................................ 125 3.3.10 Casting................................................................................................................................................................................ 125 3.3.11 Grounding metal covers ............................................................................................................................................ 125 3.3.12 Use of ultrasonic processes ...................................................................................................................................... 126 4 Approvals......................................................................................................................................... 127 4.1 Product certification approval overview ....................................................................................................................... 127 4.2 US Federal Communications Commission notice .................................................................................................... 130 4.2.1 Safety warnings review the structure .................................................................................................................. 130 4.2.2 Declaration of Conformity ........................................................................................................................................ 130 UBX-16029218 - R11 Page 5 of 157 SARA-R4/N4 series - System Integration Manual 4.2.3 Modifications ................................................................................................................................................................... 131 4.3 Innovation, Science, Economic Development Canada notice ............................................................................ 132 4.3.1 Declaration of Conformity ........................................................................................................................................ 132 4.3.2 Modifications ................................................................................................................................................................... 133 4.4 European Conformance CE mark ..................................................................................................................................... 136 4.5 Taiwanese National Communication Commission .................................................................................................. 137 5 Product testing ............................................................................................................................... 138 5.1 u-blox in-series production test ....................................................................................................................................... 138 5.2 Test parameters for OEM manufacturers ..................................................................................................................... 139 5.2.1 Go/No go tests for integrated devices ........................................................................................................... 139 5.2.2 RF functional tests ........................................................................................................................................................ 140 Appendix ................................................................................................................................................ 142 A Migration between SARA modules ............................................................................................ 142 A.1 Overview ...................................................................................................................................................................................... 142 A.2 Pin-out comparison ................................................................................................................................................................ 144 B Glossary ........................................................................................................................................... 151 Related documents ............................................................................................................................... 154 Revision history ..................................................................................................................................... 155 Contact .................................................................................................................................................... 156 UBX-16029218 - R11 Page 6 of 157 SARA-R4/N4 series - System Integration Manual 1 System description 1.1 Overview The SARA-R4/N4 series comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode modules in the miniature SARA LGA form-factor (26.0 x 16.0 mm, 96-pin), that allow easy integration in compact designs and a seamless drop-in migration from u-blox cellular module families. SARA-R4/N4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module families and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates migration from u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules, maximizes customer investments, simplifies logistics, and enables very short time-to-market. See Table 1 for a summary of the main features and interfaces. The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices that require long battery lifetimes, such as connected health, smart metering, smart cities and wearables. The modules support handover capability and delivers the technology necessary for use in applications such as vehicle, asset and people tracking where mobility is a pre-requisite. Other applications where the modules are well-suited include and are not limited to: smart home, security systems, industrial monitoring and control. The modules support data communication over an extended operating temperature range of 40 to +85 C, with extremely low power consumption, and with coverage enhancement for deeper range into buildings and basements (and underground with NB1). Model Region Bands Positioning Interfaces Audio Features Grade e n i l e s a B e s a e e R P P G 3 l y r o g e t a c E T L P P G 3 s d n a b D D F E T L SARA-R404M USA 13 M1 13 SARA-R410M-01B North America 13 M1 2,4 5,12 SARA-R410M-02B Multi Region 13 M1 NB1

*

SARA-R410M-52B North America 13 M1 2,4,5 12,13 e r a w t f o s w o N t s i s s A m e d o m a i v S S N G e t a c o L l l e C

. 0 2 B S U T R A U I P S

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UBX-16029218 - R11 System description Page 7 of 157 SARA-R4/N4 series - System Integration Manual SARA-R412M-02B Multi Region 13 M1 NB1

*

SARA-N410-02B Multi Region 13 NB1

*

* = LTE Cat M1/NB1 Bands may include 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only)

= supported by all FW versions

= supported by future FW versions Table 1: SARA-R4/N4 series main features summary SARA-R4/N4 series modules include the following variants / product versions:

SARA-R404M LTE Cat M1 module, mainly designed for operation in LTE band 13 SARA-R410M-01B LTE Cat M1 module, mainly designed for operation in LTE bands 2, 4, 5, 12 SARA-R410M-02B LTE Cat M1 / NB1 module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28 SARA-R410M-52B LTE Cat M1 module, mainly designed for operation in LTE bands 2, 4, 5, 12, 13 SARA-R412M-02B LTE Cat M1 / NB1 and 2G module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad-band SARA-N410-02B LTE Cat NB1 module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 28 Table 2 summarizes cellular radio access technologies characteristics and features of the modules. Item SARA-R404M SARA-R410M SARA-R412M SARA-N410 Protocol stack 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13 RAT LTE Cat M1 Half-Duplex LTE Cat M1 Half-Duplex LTE Cat M1 Half-Duplex LTE Cat NB1 Half-Duplex LTE Cat NB1 Half-Duplex 1 LTE Cat NB1 Half-Duplex 2G GPRS / EGPRS 1 Not supported by the 01 product version. UBX-16029218 - R11 System description Page 8 of 157 SARA-R4/N4 series - System Integration Manual Item SARA-R404M SARA-R410M SARA-R412M SARA-N410 LTE FDD bands Band 13 (750 MHz) Band 12 (700 MHz) Band 12 (700 MHz) Band 12 (700 MHz) Band 17 (700 MHz) 1, 2, 3 Band 13 (750 MHz) Band 28 (700 MHz) Band 28 (700 MHz) 1 Band 20 (800 MHz) Band 13 (750 MHz) Band 13 (750 MHz) 1 Band 5 (850 MHz) Band 20 (800 MHz) Band 20 (800 MHz) 1 Band 8 (900 MHz) Band 5 (850 MHz) Band 26 (850 MHz) 1, 2 Band 4 (1700 MHz) Band 8 (900 MHz) Band 18 (850 MHz) 1, 2 Band 3 (1800 MHz) Band 4 (1700 MHz) Band 5 (850 MHz) Band 2 (1900 MHz) Band 3 (1800 MHz) Band 19 (850 MHz) 1, 2 Band 2 (1900 MHz) Band 8 (900 MHz) 1 Band 4 (1700 MHz) Band 3 (1800 MHz) 1 Band 2 (1900 MHz) Band 25 (1900 MHz) 1, 2, 3 Band 1 (2100 MHz) 1 Band 39 (1900 MHz) 3, 4 GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz LTE TDD bands 2G bands Power class LTE Cat M1:

LTE Cat M1 / NB15:

LTE category M1 / NB1:

LTE category NB1:

Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) 2G GMSK:

Class 4 (33 dBm) for GSM/E-GSM bands Class 1 (30 dBm) for DCS/PCS bands 2G 8-PSK:

Class E2 (27 dBm) for GSM/E-GSM bands Class E2 (26 dBm) for DCS/PCS bands 2 Not supported by the 52 product version. 3 Not supported in signaling mode by the 02 product version 4 Not supported in LTE category NB1. Not supported by the 01 and 52 product versions. 5 Not supported by the 01 product version. UBX-16029218 - R11 System description Page 9 of 157 SARA-R4/N4 series - System Integration Manual Item SARA-R404M SARA-R410M SARA-R412M SARA-N410 Data rate LTE category M1:

LTE category M1:

LTE category M1:

LTE category NB1:

up to 375 kb/s UL up to 375 kb/s UL up to 375 kb/s UL up to 62.5 kb/s UL up to 300 kb/s DL up to 300 kb/s DL up to 300 kb/s DL up to 27.2 kb/s DL LTE category NB15:

LTE category NB1:

up to 62.5 kb/s UL up to 62.5 kb/s UL up to 27.2 kb/s DL up to 27.2 kb/s DL GPRS multi-slot class 336:

Up to 85.6 kb/s UL Up to 107 kb/s DL EGPRS multi-slot class 336:

Up to 236.8 kb/s UL Up to 296.0 kb/s DL Table 2: SARA-R4/N4 series modules LTE Cat M1, LTE Cat NB1, EGPRS and GPRS characteristics summary 6 GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total. UBX-16029218 - R11 System description Page 10 of 157 SARA-R4/N4 series - System Integration Manual 1.2 Architecture Figure 1 summarizes the internal architecture of SARA-R4/N4 series modules. Figure 1: SARA-R4/N4 series modules simplified block diagram SARA-R404M-00B and SARA-R410M-01B modules, i.e. the 00 and 01 product versions of the SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o DDC (I2C) interface o SDIO interface o SPI interface o Digital audio interface SARA-R410M-02B, SARA-R410M-52B, SARA-R412M-02B and SARA-N410-02B modules, i.e. the 02 and 52 product versions of the SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o SDIO interface o SPI interface o Digital audio interface UBX-16029218 - R11 System description Page 11 of 157 MemoryV_INTRF transceiverCellularBaseBandProcessorANTVCC (Supply)USBDDC (I2C)SIM card detectionSIMUARTPower-OnResetGPIOsAntenna detectionSwitchPA19.2 MHzPowerManagementFilterSDIOSPI / Digital Audio SARA-R4/N4 series - System Integration Manual 1.3 Pin-out Table 3 lists the pin-out of the SARA-R4/N4 series modules, with pins grouped by function. Function Pin Name Pin No I/O Description Remarks Power VCC 51, 52, 53 I Module supply VCC supply circuit affects the RF performance and compliance input of the device integrating the module with applicable required certification schemes. See section 1.5.1 for functional description / requirements. See section 2.2.1 for external circuit design-in. GND 1, 3, 5, 14, N/A Ground GND pins are internally connected each other. 20-22, 30, 32, 43, 50, 54, 55, 57-

61, 63-96 External ground connection affects the RF and thermal performance of the device. See section 1.5.1for functional description. See section 2.2.1 for external circuit design-in. V_INT 4 O Generic digital V_INT = 1.8 V (typical) generated by internal regulator when interfaces supply the module is switched on, outside the low power PSM deep output sleep mode. Test-Point for diagnostic access is recommended. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in. System PWR_ON 15 I Power-on input Internal 200 k pull-up resistor. Test-Point for diagnostic access is recommended. See section 1.6.1 for functional description. See section 2.3.1 for external circuit design-in. RESET_N 18 I External reset input Internal 37 k pull-up resistor. Test-Point for diagnostic access is recommended. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in. Antenna ANT 56 I/O Primary antenna Main Tx / Rx antenna interface. 50 nominal characteristic impedance. Antenna circuit affects the RF performance and application device compliance with required certification schemes. See section 1.7 for functional description / requirements. See section 2.4 for external circuit design-in. ANT_DET 62 I Antenna detection ADC for antenna presence detection function See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in. SIM VSIM 41 O SIM supply output VSIM = 1.8 V / 3 V output as per the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in. UBX-16029218 - R11 System description Page 12 of 157 SARA-R4/N4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks SIM_IO 39 I/O SIM data Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_CLK 38 O SIM clock 4.8 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_RST 40 O SIM reset Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. UART RXD 13 O UART data output 1.8 V output, Circuit 104 (RXD) in ITU-T V.24, TXD 12 I UART data input 1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT commands, data communication, FOAT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. for AT commands, data communication, FOAT. Internal pull-down to GND on 00 and R410M-02B versions Internal pull-up to V_INT on other product versions See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. CTS 11 O UART clear to send 1.8 V output, Circuit 106 (CTS) in ITU-T V.24. output Not supported by 00, 01 and R410M-02B versions. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. RTS 10 I UART ready to send 1.8 V input, Circuit 105 (RTS) in ITU-T V.24. input Internal active pull-up to V_INT. Not supported by 00, 01 and R410M-02B versions. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DSR 6 O UART data set 1.8 V, Circuit 107 in ITU-T V.24. ready output See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. RI 7 O UART ring indicator 1.8 V, Circuit 125 in ITU-T V.24. output See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DTR 9 I UART data terminal 1.8 V, Circuit 108/2 in ITU-T V.24. ready input Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DCD 8 O UART data carrier 1.8 V, Circuit 109 in ITU-T V.24. detect output See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. UBX-16029218 - R11 System description Page 13 of 157 SARA-R4/N4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks USB VUSB_DET 17 I USB detect input VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB_D-

28 I/O USB Data Line D-

USB interface for AT commands, data communication, FOAT, FW update by u-blox tool, diagnostics. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB_D+

29 I/O USB Data Line D+ USB interface for AT commands, data communication, FOAT, FW update by u-blox tool, diagnostics. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. SPI I2S_WA /

34 O SPI MOSI SPI Master Output Slave Input, alternatively configurable as I2S SPI_MOSI word alignment Not supported by 00, 01 and x2 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. I2S_RXD /

37 I SPI MISO SPI Master Input Slave Output, alternatively configurable as I2S SPI_MISO receive data Not supported by 00, 01 and x2 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. I2S_CLK /

36 O SPI clock SPI clock, alternatively configurable as I2S clock SPI_CLK Not supported by 00, 01 and x2 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. I2S_TXD /

35 O SPI Chip Select SPI Chip Select, alternatively settable as I2S transmit data SPI_CS Not supported by 00, 01 and x2 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. UBX-16029218 - R11 System description Page 14 of 157 SARA-R4/N4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks SDIO SDIO_D0 47 I/O SDIO serial data [0] Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDIO_D1 49 I/O SDIO serial data [1] Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDIO_D2 44 I/O SDIO serial data [2] Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDIO_D3 48 I/O SDIO serial data [3] Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDIO_CLK 45 O SDIO serial clock Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDIO_CMD 46 I/O SDIO command Not supported by 00, 01 and x2 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. DDC SCL 27 O I2C bus clock line 1.8 V open drain, for communication with I2C-slave devices. Internal pull-up to V_INT: external pull-up is not required. Not supported by 00 and 01 product versions. See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDA 26 I/O I2C bus data line 1.8 V open drain, for communication with I2C-slave devices. Internal pull-up to V_INT: external pull-up is not required. Not supported by 00 and 01 product versions. See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. Audio I2S_TXD /

35 O I2S transmit data I2S transmit data, alternatively configurable as SPI Chip Select SPI_CS Not supported by 00, 01 and x2 product versions. I2S_RXD /

37 I I2S receive data I2S receive data, alternatively configurable as SPI Master Input SPI_MISO Slave Output See section 1.10 for functional description. See section 2.7 for external circuit design-in. Not supported by 00, 01 and x2 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. I2S_CLK /

36 I/O I2S clock I2S clock, alternatively configurable as SPI clock SPI_CLK Not supported by 00, 01 and x2 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. UBX-16029218 - R11 System description Page 15 of 157 SARA-R4/N4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks I2S_WA /

34 I/O I2S word alignment I2S word alignment, alternatively configurable as SPI_MOSI SPI Master Output Slave Input Not supported by 00, 01 and x2 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. GPIO GPIO1 16 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO2 23 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO3 24 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO4 25 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO5 42 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO6 19 I/O GPIO 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. Reserved RSVD 33 N/A Reserved pin This pin can be connected to GND. See sections 1.12 and 2.9 RSVD 2, 31 N/A Reserved pin Leave unconnected. See sections 1.12 and 2.9 Table 3: SARA-R4/N4 series modules pin definition, grouped by function UBX-16029218 - R11 System description Page 16 of 157 SARA-R4/N4 series - System Integration Manual 1.4 Operating modes SARA-R4/N4 series modules have several operating modes. The operating modes are defined in Table 4 and described in detail in Table 5, providing general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal Operation Deep-Sleep Mode RTC runs with 32 kHz reference internally generated. Idle Mode Module processor runs with 32 kHz reference generated by the internal oscillator. Active Mode Module processor runs with 19.2 MHz reference generated by the internal oscillator. Connected Mode RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference. Table 4: SARA-R4/N4 series modules operating modes definition Mode Description Transition between operating modes Not-Powered Module is switched off. When VCC supply is removed, the modules enter not-powered Application interfaces are not accessible. mode. When in not-powered mode, the module can enter power-off mode applying VCC supply (see 1.6.1). Power-Off Module is switched off: normal shutdown by The modules enter power-off mode from active mode when the an appropriate power-off event (see 1.6.2). host processor implements a clean switch-off procedure, by sending Application interfaces are not accessible. the AT+CPWROFF command or by using the PWR_ON pin (see 1.6.2). When in power-off mode, the modules can be switched on by the host processor using the PWR_ON input pin (see 1.6.1). When in power-off mode, the modules enter not-powered mode by removing VCC supply. UBX-16029218 - R11 System description Page 17 of 157 SARA-R4/N4 series - System Integration Manual Mode Description Transition between operating modes Deep-Sleep Only the internal 32 kHz reference is active. The modules automatically switch from the active mode to low The RF section and the application interfaces power deep sleep mode whenever possible, upon expiration of the are temporarily disabled and switched off: the 6 seconds AT inactivity timer, and upon expiration of Active Timer, module is temporarily not ready to entering in the Power Saving Mode defined in 3GPP Rel.13, if power communicate with an external device by saving configuration is enabled (see 1.13.9 and the SARA-R4/N4 means of the application interfaces as series AT Commands Manual [2], AT+CPSMS command). configured to reduce the current consumption. When in low power deep sleep mode, the module switches on to The module enters the low power deep sleep the active mode upon expiration of Periodic Update Timer mode (entering the Power Saving Mode according to the Power Saving Mode defined in 3GPP Rel.13 (see defined in 3GPP Rel.13) whenever possible, if 1.13.9 and the SARA-R4/N4 series AT Commands Manual [2], power saving configuration is enabled by AT+CPSMS command), or it can be switched on to the active mode AT+CPSMS command (see the SARA-R4/N4 by the host processor using the PWR_ON input pin (see section series AT Commands Manual [2]), reducing 1.6.1). current consumption (see 1.13.9). Power saving configuration is not enabled by default; it can be enabled by AT+CPSMS (see the SARA-R4/N4 series AT Commands Manual

[2]). Idle Module is switched on with application The modules automatically switch from the active mode to low interfaces temporarily disabled: the module is power idle mode whenever possible, upon expiration of the 6 temporarily not ready to communicate with an seconds AT inactivity timer, if low power configuration is enabled external device by means of the application

(see the SARA-R4/N4 series AT Commands Manual [2], AT+UPSV interfaces as configured to reduce the current command). consumption. When in low power idle mode, the module switches to the active The module enters the low power idle mode mode upon data reception over UART serial interface. The first whenever possible, if low power configuration character received in low power idle mode wakes up the system: it is enabled by AT+UPSV command (see the is not recognized as valid communication character, and the SARA-R4/N4 series AT Commands Manual [2]), recognition of the subsequent characters is guaranteed only after reducing current consumption. the complete system wake-up. Low power configuration is not enabled by default; it can be enabled by AT+UPSV (see the SARA-R4/N4 series AT Commands Manual

[2]). UBX-16029218 - R11 System description Page 18 of 157 SARA-R4/N4 series - System Integration Manual Mode Active Description Transition between operating modes Module is switched on with application The modules enter active mode from power-off mode when the interfaces enabled or not suspended: the host processor implements a clean switch-on procedure by using module is ready to communicate with an the PWR_ON pin (see 1.6.1). external device by means of the application The modules enter active mode from low power deep sleep mode interfaces unless power saving configuration is upon expiration of Periodic Update Timer (see 1.13.9), or when the enabled by AT+CPSMS (see the SARA-R4/N4 host processor implements a clean switch-on procedure by using series AT Commands Manual [2]). the PWR_ON pin (see 1.6.1). The modules enter power-off mode from active mode when the host processor implements a clean switch-off procedure (see 1.6.2). The modules automatically switch from active to low power deep sleep mode whenever possible, if power saving is enabled (see 1.13.9). The module switches from active to connected mode when a RF Tx/Rx data connection is initiated or when RF Tx/Rx activity is required due to a connection previously initiated. The module switches from connected to active mode when a RF Tx/Rx data connection is terminated or suspended. Connected RF Tx/Rx data connection is in progress. When a data connection is initiated, the module enters connected The module is prepared to accept data signals mode from active mode. from an external device. Connected mode is suspended if Tx/Rx data is not in progress. In such cases the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+CPSMS command, the module automatically switches to low power deep sleep mode whenever possible. Vice-versa, the module wakes up from low power deep sleep mode to active mode and then connected mode if RF Tx/Rx activity is necessary. When a data connection is terminated, the module returns to the active mode. Table 5: SARA-R4/N4 series modules operating modes description UBX-16029218 - R11 System description Page 19 of 157 Figure 2 describes the transition between the different operating modes. SARA-R4/N4 series - System Integration Manual Figure 2: SARA-R4/N4 series modules operating modes transitions UBX-16029218 - R11 System description Page 20 of 157 If PSM mode is enabled, if AT Inactivity Timer and Active Timer are expired Upon expiration of the Periodic Update Timer Using PWR_ON pinIncoming/outgoing data or other dedicated device network communicationNo RF Tx/Rx in progress, Communication droppedRemove VCCSwitch ON:PWR_ONNot poweredPower offActiveConnectedDeep SleepSwitch OFF:AT+CPWROFFPWR_ONApply VCCIf low power mode is enabled, if AT Inactivity Timer is expired IdleData received over UART SARA-R4/N4 series - System Integration Manual 1.5 Supply interfaces 1.5.1 Module supply input (VCC) The modules must be supplied via the three VCC pins that represent the module power supply input. Voltage must be stable, because during operation, the current drawn by the SARA-R4/N4 series modules through the VCC pins can vary by several orders of magnitude, depending on the operating mode and state (as described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.6). It is important that the supply source is able to withstand both the maximum pulse current occurring during a transmit burst at maximum power level and the average current consumption occurring during Tx / Rx call at maximum RF power level (see the SARA-R4 Data Sheet [1]). SARA-R412M modules provide separate supply inputs over the three VCC pins:

VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding minor part of the total current drawn of the module when RF transmission is enabled during a call The 3 VCC pins of SARA-R404M, SARA-R410M, SARA-N410 modules are internally connected each other to both the internal RF Power Amplifier and the internal baseband Power Management Unit. Figure 3 provides a simplified block diagram of SARA-R4/N4 series modules internal VCC supply routing. Figure 3: Block diagram of SARA-R4/N4 series modules internal VCC supply routing UBX-16029218 - R11 System description Page 21 of 157 53VCC52VCC51VCCSARA-R404M / SARA-R410M / SARA-N410Power ManagementUnitMemoryBaseband ProcessorTransceiverPower Amplifier53VCC52VCC51VCCSARA-R412MPower ManagementUnitMemoryBaseband ProcessorTransceiverPower Amplifier SARA-R4/N4 series - System Integration Manual 1.5.1.1 VCC supply requirements Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to correctly design a VCC supply circuit compliant with the requirements listed in Table 6. The supply circuit affects the RF compliance of the device integrating SARA-R4/N4 series modules with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the requirements summarized in the Table 6 are fulfilled. Item Requirement Remark VCC nominal voltage Within VCC normal operating range:

RF performance is guaranteed when VCC voltage is SARA-R404M / SARA-R410M / SARA-N410:

inside the normal operating range limits. 3.2 V / 4.2 V RF performance may be affected when VCC voltage is SARA-R412M:

3.2 V / 4.5 V outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits. VCC voltage during Within VCC extended operating range:

VCC voltage must be above the extended operating normal operation SARA-R404M / SARA-R410M / SARA-N410:

range minimum limit to switch-on the module. 3.0 V / 4.2 V SARA-R412M:

3.0 V / 4.5 V The module may switch-off when the VCC voltage drops below the extended operating range minimum limit. Operation above VCC extended operating range is not recommended and may affect device reliability. VCC average current Support with adequate margin the highest The maximum average current consumption can be averaged VCC current consumption value in greater than the specified value according to the actual connected mode conditions specified in the SARA-

antenna mismatching, temperature and supply voltage. R4/N4 series Data Sheet [1]

Section 1.5.1.2 describes current consumption profiles in connected mode. VCC peak current Support with adequate margin the highest peak The maximum peak Tx current consumption can be VCC current consumption value in Tx connected greater than the specified value according to the actual mode conditions specified in the SARA-R4/N4 antenna mismatching, temperature and supply voltage. series Data Sheet [1]

Section 1.5.1.2 describes current consumption profiles in connected mode. VCC voltage drop Lower than 400 mV VCC voltage drop directly affects the RF compliance with during Tx slots applicable certification schemes. Figure 6 describes VCC voltage drop during 2G Tx slots. VCC voltage ripple Noise in the supply pins must be minimized High supply voltage ripple values during RF during Tx transmissions in connected mode directly affect the RF compliance with the applicable certification schemes. VCC under/over-shoot Absent or at least minimized VCC under/over-shoot directly affects the RF compliance at start/end of Tx slots with applicable certification schemes. Figure 6 describes VCC voltage under/over-shoot. UBX-16029218 - R11 System description Page 22 of 157 SARA-R4/N4 series - System Integration Manual Table 6: Summary of VCC modules supply requirements UBX-16029218 - R11 System description Page 23 of 157 SARA-R4/N4 series - System Integration Manual 1.5.1.2 VCC current consumption in LTE connected mode During an LTE connection, the SARA-R4/N4 series modules transmit and receive in half duplex mode. The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz. Figure 4 shows an example of SARA-R4/N4 series modules current consumption profile versus time in connected mode: transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-

duplex connected mode. Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1]. Figure 4: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection 1.5.1.3 VCC current consumption in 2G connected mode When a 2G call is established, the VCC consumption is determined by the current consumption profile typical of the 2G transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption. If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can reach a high peak / pulse (see the SARA-R4/N4 series Data Sheet [1]) for 576.9 s (width of the transmit UBX-16029218 - R11 System description Page 24 of 157 Time [ms]Current [mA]0300200100500400Current consumption value depends on TX power and actual antenna load1 Slot1 Resource Block (0.5 ms)1 LTE Radio Frame (10 ms)1 Slot1 Resource Block (0.5 ms)1 LTE Radio Frame (10 ms) SARA-R4/N4 series - System Integration Manual slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are much lower than during transmission in the low bands, due to the 3GPP transmitter output power specifications. During a 2G call, current consumption is not significantly high while receiving or in monitor bursts, and it is low in the bursts unused to transmit / receive. Figure 5 shows an example of the module current consumption profile versus time in 2G single-slot. Figure 5: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot) Figure 6 illustrates the VCC voltage profile versus time during a 2G single-slot call, according to the related VCC current consumption profile described in Figure 5. Figure 6: Description of the VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot) When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak UBX-16029218 - R11 System description Page 25 of 157 Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200 mA60-120 mA1900 mAPeak current depends on TX power and actual antenna loadGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.060-120 mA10-40 mATimeundershootovershootrippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) SARA-R4/N4 series - System Integration Manual current consumption. But according to GPRS specifications, the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the case of a GSM call. If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level, the consumption can reach a quite a high peak but lower than the one achievable in 2G single-slot mode. This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower than in the 850 or 900 MHz band because of the 3GPP Tx power specifications. Figure 7 illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12. Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot) In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one during GPRS connections: the current consumption profile in GPRS multi-slot class 12 connected mode illustrated in the Figure 7 is representative for the EDGE multi-slot class 12 connected mode as well. 1.5.1.4 VCC current consumption in low power deep sleep mode (PSM enabled) The power saving mode configuration is by default disabled, but it can be enabled using the AT+CPSMS command (see the SARA-R4/N4 series AT Commands Manual [2] and section 1.13.9). When power saving mode is enabled, the module automatically enters the PSM low power deep sleep mode whenever possible, reducing current consumption down to a steady value in the A range: only the RTC runs with internal 32 kHz reference clock frequency. Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1]. Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the RC oscillator, as a consequence, a very low spike in current consumption will be observed. UBX-16029218 - R11 System description Page 26 of 157 Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]60-120mAGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.060-120mA10-40mA200mAPeak current depends on TX power and actual antenna load1600 mA SARA-R4/N4 series - System Integration Manual 1.5.1.5 VCC current consumption in low power idle mode (low power enabled) The low power idle mode configuration is by default disabled, but it can be enabled using the AT+UPSV command (see the SARA-R4/N4 series AT Commands Manual [2]). When low power idle mode is enabled, the module automatically enters the low power mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active mode to enable the reception of the paging block. In between, the module switches to low power mode. This is known as discontinuous reception (DRX) or extended discontinuous reception (eDRX). Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1]. UBX-16029218 - R11 System description Page 27 of 157 SARA-R4/N4 series - System Integration Manual 1.5.1.6 VCC current consumption in active mode (PSM / low power disabled) The active mode is the state where the module is switched on and ready to communicate with an external device by means of the application interfaces (as the USB or the UART serial interface). The module processor core is active, and the 19.2 MHz reference clock frequency is used. If power saving mode and/or low power mode configurations are disabled, as it is by default (see the SARA-

R4/N4 series AT Commands Manual [2], +CPSMS, +UPSV AT commands for details), the module remains in active mode. Otherwise, if PSM mode and/or low power mode configurations are enabled, the module enters PSM mode and/or low power mode whenever possible. Figure 8 illustrates a typical example of the module current consumption profile when the module is in active mode. In such case, the module is registered with the network and, while active mode is maintained, the receiver is periodically activated to monitor the paging channel for paging block reception. Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1]. Figure 8: VCC current consumption profile with power saving disabled and module registered with the network: active mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception 1.5.2 Generic digital interfaces supply output (V_INT) The V_INT output pin of the SARA-R4/N4 series modules is generated by the module internal power management circuitry when the module is switched on and it is not in the deep sleep power saving mode. UBX-16029218 - R11 System description Page 28 of 157 ACTIVE MODEPaging periodTime [s]Current [mA]Time [ms]Current [mA]RX Enabled01000100 SARA-R4/N4 series - System Integration Manual The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4/N4 series Data Sheet [1]. The V_INT voltage domain can be used in place of an external discrete regulator as a reference voltage rail for external components. UBX-16029218 - R11 System description Page 29 of 157 SARA-R4/N4 series - System Integration Manual 1.6 System function interfaces 1.6.1 Module power-on When the SARA-R4/N4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied), they can be switched on as follows:

Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set at the PWR_ON input pin for a valid time. When the SARA-R4/N4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving Mode (PSM), with a valid VCC supply applied, they can be switched on as follows:

Low pulse on the PWR_ON pin for a valid time period The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics with voltages and timings are described in the SARA-R4/N4 series Data Sheet [1]. Figure 9 shows the module switch-on sequence from the not-powered mode, with following phases:

The external power supply is applied to the VCC module pins The PWR_ON pin is held low for a valid time All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT). The internal reset signal is held low: the baseband core and all digital pins are held in reset state. When the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to the default operational configured state. The duration of this phase differs within generic digital interfaces and USB interface due to host / device enumeration timings. The module is fully ready to operate after all interfaces are configured. Figure 9: SARA-R4/N4 series switch-on sequence description The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:

o o the V_INT pin, to sense the start of the SARA-R4/N4 series module switch-on sequence the GPIO pin configured to provide the module operating status indication (see SARA-R4/N4 series Commands Manual [2], AT+UGPIOC), to sense when the module is ready to operate UBX-16029218 - R11 System description Page 30 of 157 VCCPWR_ONRESET_NV_INTInternal ResetGPIOSystem StateBB Pads StateOperationalOFFONInternal Reset OperationalTristate / Floating Internal ResetStart of interface configurationModule interfaces are configuredStart-up event~4.5 s0 s SARA-R4/N4 series - System Integration Manual Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the module. Before the SARA-R4/N4 series module is fully ready to operate, the host application processor should not send any AT command over AT communication interfaces (USB, UART) of the module. The duration of the SARA-R4/N4 series modules switch-on routine can vary depending on the application / network settings and the concurrent module activities. An abrupt removal of the VCC supply or forcing a low level on the RESET_N input once the boot of SARA-R4/N4 series modules has been triggered may lead to an unrecoverable faulty state!

1.6.2 Module power-off SARA-R4/N4 series modules can be cleanly switched off by:

AT+CPWROFF command (see SARA-R4/N4 series AT Commands Manual [2]). Low pulse on the PWR_ON pin for a valid time period (see the SARA-R4/N4 series Data Sheet [1]). These events listed above trigger the storage of the current parameter settings in the non-volatile memory of the module, and a clean network detach procedure. An abrupt under-voltage shutdown occurs on SARA-R4/N4 series modules when the VCC module supply is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the modules non-volatile memory or to perform the clean network detach. It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series modules normal operations. An abrupt removal of the VCC supply during SARA-R4/N4 series modules normal operations may lead to an unrecoverable faulty state!

An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in SARA-R4/N4 series AT Commands Manual [2]. UBX-16029218 - R11 System description Page 31 of 157 SARA-R4/N4 series - System Integration Manual Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may lead to an unrecoverable faulty state!

Figure 10 and Figure 11 describe the SARA-R4/N4 series modules switch-off sequence started by means of the AT+CPWROFF command and by means of the PWR_ON input pin respectively, allowing storage of current parameter settings in the modules non-volatile memory and a clean network detach, with the following phases:

When the +CPWROFF AT command is sent, or when a low pulse with appropriate time duration (see the SARA-R4/N4 series Data Sheet [1]) is applied at the PWR_ON input pin, the module starts the switch-off routine. Then, if the +CPWROFF AT command has been sent, the module replies OK on the AT interface: the switch-off routine is in progress. At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned off, including the generic digital interfaces supply (V_INT). Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a low level to PWR_ON), and enters not-powered mode if the VCC supply is removed. Figure 10: SARA-R4/N4 series modules switch-off sequence by means of AT+CPWROFF command Figure 11: SARA-R4/N4 series modules switch-off sequence by means of PWR_ON pin UBX-16029218 - R11 System description Page 32 of 157 VCC PWR_ONRESET_N V_INTInternal ResetSystem StateBB Pads StateOperationalOFFTristate / FloatingONOperational TristateAT+CPWROFFsent to the moduleOKreplied by the moduleVCC can be removedVCC PWR_ONRESET_N V_INTInternal ResetSystem StateBB Pads StateOFFTristate / FloatingONOperational -> TristateOperational0 s~2.5 s~5 sThe module starts the switch-off routineVCC can be removed SARA-R4/N4 series - System Integration Manual The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor the V_INT pin to sense the end of the switch-off sequence. VCC supply can be removed only after V_INT goes low: an abrupt removal of the VCC supply during SARA-R4/N4 series modules normal operations may lead to an unrecoverable faulty state!

The duration of each phase in the SARA-R4/N4 series modules switch-off routines can largely vary depending on the application / network settings and the concurrent module activities. 1.6.3 Module reset SARA-R4/N4 series modules can be cleanly reset (rebooted) by:

AT+CFUN command (see the SARA-R4/N4 series AT Commands Manual [2]). In the case above an internal or software reset of the module is executed: the current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed. An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on RESET_N input pin for a valid time period. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. Then, the module remains in power-off mode as long as a switch on event does not occur applying an appropriate low level to the PWR_ON input. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the SARA-R4/N4 series AT Commands Manual [2]. Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may lead to an unrecoverable faulty state!

The RESET_N input pin is directly connected to the Power Management Unit IC, with an integrated pull-up to a 1.8 V supply domain, in order to perform an abrupt hardware shutdown when asserted. Detailed electrical characteristics with voltages and timings are described in the SARA-R4/N4 series Data Sheet [1]. UBX-16029218 - R11 System description Page 33 of 157 SARA-R4/N4 series - System Integration Manual Figure 12: RESET_N input description UBX-16029218 - R11 System description Page 34 of 157 18RESET_NSARA-R4/N4Power Management UnitReset Shutdown1.8V SARA-R4/N4 series - System Integration Manual 1.7 Antenna interface 1.7.1 Antenna RF interface (ANT) SARA-R4/N4 series modules provide an RF interface for connecting the external antenna. The ANT pin represents the primary RF input/output for transmission and reception of LTE RF signals. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the primary Tx /

Rx antenna through a 50 transmission line to allow clear RF transmission and reception. 1.7.1.1 Antenna RF interfaces requirements Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to correctly design antennas circuits compliant with these requirements. The antenna circuits affect the RF compliance of the device integrating SARA-R4/N4 series modules with applicable required certification schemes (for more details see section 4). Compliance is guaranteed if the antenna RF interface requirements summarized in Table 7 are fulfilled. Item Requirements Remarks Impedance 50 nominal characteristic The impedance of the antenna RF connection must match the 50 impedance impedance of the ANT port. Frequency See the SARA-R4/N4 series Data The required frequency range of the antenna connected to ANT port Range Sheet [1]

depends on the operating bands of the used cellular module and the used mobile network. Return Loss S11 < -10 dB (VSWR < 2:1) The Return loss or the S11, as the VSWR, refers to the amount of recommended reflected power, measuring how well the antenna RF connection matches S11 < -6 dB (VSWR < 3:1) acceptable the 50 characteristic impedance of the ANT port. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of the ANT port over the operating frequency range, reducing as much as possible the amount of reflected power. Efficiency

> -1.5 dB ( > 70% ) recommended The radiation efficiency is the ratio of the radiated power to the power

> -3.0 dB ( > 50% ) acceptable delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT port needs to be enough high over the operating frequency range to comply with the Over-The-Air (OTA) radiated performance requirements, as Total Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified by applicable related certification schemes. UBX-16029218 - R11 System description Page 35 of 157 SARA-R4/N4 series - System Integration Manual Item Requirements Remarks Maximum Gain According to radiation exposure The power gain of an antenna is the radiation efficiency multiplied by limits the directivity: the gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source. The maximum gain of the antenna connected to ANT port must not exceed the herein stated value to comply with regulatory agencies radiation exposure limits. For additional info see sections 4.2.2. Input Power

> 24 dBm ( > 0.25 W ) for R404M /

The antenna connected to the ANT port must support with adequate R410M / N410 margin the maximum power transmitted by the modules.

> 33 dBm ( > 2.0 W ) for R412M Table 7: Summary of Tx/Rx antenna RF interface requirements 1.7.2 Antenna detection interface (ANT_DET) The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter

(ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the SARA-

R4/N4 series AT Commands Manual [2] for more details on this feature. The ANT_DET pin generates a DC current (for detailed characteristics see the SARA-R4/N4 series Data Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So, the requirements to achieve antenna detection functionality are the following:

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.8 SIM interface 1.8.1 SIM interface SARA-R4/N4 series modules provide high-speed SIM/ME interface including automatic detection and configuration of the voltage required by the connected SIM card or chip. Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage switch from 1.8 V to 3 V are implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output provides internal short circuit protection to limit start-up current and protect the SIM to short circuits. UBX-16029218 - R11 System description Page 36 of 157 SARA-R4/N4 series - System Integration Manual The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM card or chip. 1.8.2 SIM detection interface The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if cleanly connected to the mechanical switch of a SIM card holder as described in section 2.5:

Low logic level at GPIO5 input pin is recognized as SIM card not present High logic level at GPIO5 input pin is recognized as SIM card present For more details, see the SARA-R4/N4 series AT Commands Manual [2], +UGPIOC, +CIND and +CMER AT commands. UBX-16029218 - R11 System description Page 37 of 157 SARA-R4/N4 series - System Integration Manual 1.9 Data communication interfaces SARA-R4/N4 series modules provide the following serial communication interface:

USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host application processor (AT commands, data, FW update by means of the FOAT feature), for FW update by means of the u-blox dedicated tool and for diagnostics. See section 1.9.2. SPI interface: Serial Peripheral Interface available for communication with an external compatible device. See section 1.9.3. SDIO interface: Secure Digital Input Output interface available for communication with a compatible device. See section 1.9.4. DDC interface: I2C bus compatible interface available for the communication with u-blox GNSS positioning chips or modules and with external I2C devices. See section 1.9.5. 1.9.1 UART interface 1.9.1.1 UART features The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the SARA-

R4/N4 series modules, supporting:

AT command mode7 Data mode and Online command mode7 Multiplexer protocol functionality FW upgrades by means of the FOAT feature (see 1.13.7) The UART is available only if the USB is not enabled as AT command / data communication interface:

UART and USB cannot be concurrently used for this purpose. UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for electrical characteristics see the SARA-R4/N4 series Data Sheet [1]), providing:

data lines (RXD as output, TXD as input) hardware flow control lines (CTS as output, RTS as input) modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output) 7 For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [1]

UBX-16029218 - R11 System description Page 38 of 157 SARA-R4/N4 series - System Integration Manual SARA-R4/N4 series modules are designed to operate as cellular modems, i.e. as the data circuit-

terminating equipment (DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor connected to the module UART interface represents the data terminal equipment (DTE). UART signal names of the cellular modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD line represents data transmitted by the DTE (host processor output) and received by the DCE (module input). Hardware flow control is not supported by the 00, 01 and SARA-R410M-02B product versions, but the RTS input line of the module must be set low (= ON state) to communicate over UART interface on the 00 and 01 product versions. DTR input of the module must be set low (= ON state) to have URCs presented over UART interface. SARA-R4/N4 series modules UART interface is by default configured in AT command mode, if the USB interface is not enabled as AT command / data communication interface (UART and USB cannot be concurrently used for this purpose): the module waits for AT command instructions and interprets all the characters received as commands to execute. All the functionalities supported by SARA-R4/N4 series modules can be in general set and configured by AT commands:

AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]

u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2]) The default baud rate is 115200 b/s, while the default frame format is 8N1 (8 data bits, No parity, 1 stop bit: see Figure 13). Baud rates can be configured by AT command (see the SARA-R4/N4 series AT Commands Manual [2]). Automatic baud rate detection and automatic frame format recognition are not supported. Figure 13: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit) 1.9.1.2 UART signals behavior At the end of the module boot sequence (see Figure 9), the module is by default in active mode, and the UART interface is initialized and enabled as AT commands interface only if the USB interface is not enabled as AT command / data communication interface: UART and USB cannot be concurrently used for this purpose. UBX-16029218 - R11 System description Page 39 of 157 D0D1D2D3D4D5D6D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer,8N1 SARA-R4/N4 series - System Integration Manual The configuration and the behavior of the UART signals after the boot sequence are described below:

The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module holds RXD in the OFF state until the module transmits some data. The module data input line (TXD) is assumed to be controlled by the external host once UART is initialized and if UART is used in the application. The TXD data input line has an internal active pull-

down enabled on the 00 and SARA-R410M-02B product versions, and an internal active pull-up enabled on the other product version. 1.9.1.3 UART multiplexer protocol SARA-R4/N4 series modules include multiplexer functionality as per 3GPP TS 27.010 [8], on the UART physical link. This is a data link protocol which uses HDLC-like framing and operates between the module

(DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART). The following virtual channels are defined:

Channel 0:

for Multiplexer control Channel 1:

for all AT commands, and non-Dial Up Network (non-DUN) data connections. UDP, TCP data socket / data call connections via relevant AT commands. Channel 2:

for Dial Up Network (DUN) data connection. It requires the host to have and use its own TCP/IP stack. The DUN can be initiated on modem side or terminal/host side. Channel 3:

for u-blox GNSS data tunneling (not supported by 00 and 01 product versions). 1.9.2 USB interface 1.9.2.1 USB features SARA-R4/N4 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate, representing the main interface for transferring high speed data with a host application processor, supporting:

AT command mode8 Data mode and Online command mode8 FW upgrades by means of the FOAT feature (see 1.13.7) FW upgrades by means of the u-blox EasyFlash dedicated tool Trace log capture (diagnostic purposes) 8 For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [2]

UBX-16029218 - R11 System description Page 40 of 157 SARA-R4/N4 series - System Integration Manual The module itself acts as a USB device and can be connected to a USB host such as a Personal Computer or an embedded application microprocessor equipped with compatible drivers. The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus Revision 2.0 specification [4], while the VUSB_DET input pin senses the VBUS USB supply presence

(nominally 5 V at the source) to detect the host connection and enable the interface. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input, which senses the USB supply voltage and absorbs few microamperes. The USB interface is available as AT command / data communication interface only if an external valid USB VBUS supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the switch-on of the module, and then held during normal operations. In this case, the UART will be not available. If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode defined in 3GPP Rel.13. The USB interface is controlled and operated with:

AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]

u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2]) The USB interface of SARA-R4/N4 series modules can provide the following USB functions:

AT commands and data communication Diagnostic log The USB profile of SARA-R4/N4 series modules identifies itself by the following VID (Vendor ID) and PID

(Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [4]. VID = 0x05C6 PID = 0x90B2 UBX-16029218 - R11 System description Page 41 of 157 SARA-R4/N4 series - System Integration Manual 1.9.3 SPI interface The SPI interface is not supported by 00, 01, 02 and 52 product versions: the SPI interface pins should not be driven by any external device. SARA-R4/N4 series modules include a Serial Peripheral Interface for communication with compatible external device. The SPI interface can be made available as alternative function, in mutually exclusive way, over the digital audio interface pins

(I2S_WA

/ SPI_MOSI, I2S_RXD

/ SPI_MISO, I2S_CLK

/ SPI_CLK, I2S_TXD / SPI_CS). 1.9.4 SDIO interface The SDIO interface is not supported by 00, 01, 02 and 52 product versions: the SDIO interface pins should not be driven by any external device. SARA-R4/N4 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, and SDIO_CMD) designed to communicate with external compatible SDIO devices. 1.9.5 DDC (I2C) interface The I2C interface is not supported by 00 and 01 product versions: the I2C interface pins should not be driven by any external device. SARA-R4/N4 series modules include an I2C-bus compatible DDC interface (SDA, SCL lines) available to communicate with a u-blox GNSS receiver and with external I2C devices as an audio codec: the SARA-R4/N4 series module acts as an I2C master which can communicate with I2C slaves in accordance with the I2C bus specifications [9]. The SDA and SCL pins have internal pull-up to V_INT, so there is no need of additional pull-up resistors on the external application board. 1.10 Audio Audio is not supported by 00, 01, 02 and 52 product versions: the I2S interface pins should not be driven by any external device. UBX-16029218 - R11 System description Page 42 of 157 SARA-R4/N4 series - System Integration Manual SARA-R4/N4 series modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio services. SARA-R4/N4 series modules include an I2S digital audio interface to transfer digital audio data to/from an external compatible audio device. The digital audio interface can be made available as alternative function, in mutually exclusive way, over the SPI interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS). UBX-16029218 - R11 System description Page 43 of 157 SARA-R4/N4 series - System Integration Manual 1.11 General Purpose Input/Output SARA-R4/N4 series modules include six pins (GPIO1-GPIO6) which can be configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more details see the SARA-

R4/N4 series AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized in Table 8. Function Description Default GPIO Configurable GPIOs Network status indication Network status: registered / data transmission, no service --

GNSS supply enable 9 Enable/disable the supply of a u-blox GNSS receiver

--

GPIO1 GPIO2 connected to the cellular module by the DDC (I2C) interface GNSS data ready 9 Sense when a u-blox GNSS receiver connected to the

--

GPIO3 module is ready for sending data by the DDC (I2C) interface SIM card detection SIM card physical presence detection Module status indication Module switched off or in PSM low power deep sleep mode, versus active or connected mode Last gasp 10 Input to trigger last gasp notification General purpose input Input to sense high or low digital level General purpose output Output to set the high or the low digital level

--

--

--

--

--

GPIO5 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO3, GPIO4, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO6 Pin disabled Tri-state with an internal active pull-down enabled GPIO1, GPIO2, GPIO3, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO4, GPIO5, GPIO6 Table 8: SARA-R4/N4 series modules GPIO custom functions configuration 1.12 Reserved pins (RSVD) SARA-R4/N4 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be externally connected to ground. 9 Not supported by 00 and 01 product versions 10 Not supported by 00, 01 and SARA-R410M-02B product versions UBX-16029218 - R11 System description Page 44 of 157 SARA-R4/N4 series - System Integration Manual 1.13 System features 1.13.1 Network indication GPIOs can be configured by the AT command to indicate network status (for further details see section 1.11 and the SARA-R4/N4 series AT Commands Manual [2]):

No service (no network coverage or not registered) Registered / Data call enabled (RF data transmission / reception) 1.13.2 Antenna supervisor The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional feature that can be implemented if the application requires it. The antenna supervisor is forced by the

+UANTR AT command (see the SARA-R4/N4 series AT Commands Manual [2] for more details). The requirements to achieve antenna detection functionality are the following:

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.13.3 Dual stack IPv4/IPv6 SARA-R4/N4 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel. For more details about dual stack IPv4/IPv6 see the SARA-R4/N4 series AT Commands Manual [2]. 1.13.4 TCP/IP and UDP/IP SARA-R4/N4 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured established and handled via the data connection management packet switched data commands. SARA-R4/N4 series modules provide Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interfaces (USB, UART). In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-

versa. For more details on embedded TCP/IP and UDP/IP functionalities, see SARA-R4/N4 series AT Commands Manual [2]. 1.13.5 FTP SARA-R4/N4 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in the local file system of the module. UBX-16029218 - R11 System description Page 45 of 157 SARA-R4/N4 series - System Integration Manual FTP files can also be transferred using FTP Direct Link:

FTP download: data coming from the FTP server is forwarded to the host processor via USB / UART serial interfaces (for FTP without Direct Link mode the data is always stored in the modules flash file system) FTP upload: data coming from the host processor via USB / UART serial interface is forwarded to the FTP server (for FTP without Direct Link mode the data is read from the modules flash file system) When Direct Link is used for an FTP file transfer, only the file contents passes through USB / UART serial interface, whereas all the FTP command handling is managed internally by the FTP application. For more details about embedded FTP functionalities, see the SARA-R4/N4 series AT Commands Manual

[2]. 1.13.6 HTTP SARA-R4/N4 series modules provide the embedded Hypertext Transfer Protocol (HTTP) services via AT commands for sending requests to a remote HTTP server, receiving the server response and transparently storing it in the modules flash file system. For more details, see the SARA-R4/N4 series AT Commands Manual [2]. 1.13.7 Firmware update Over AT (FOAT) This feature allows upgrading of the module firmware over the AT interface, using AT commands. The +UFWUPD AT command enables a code download to the device from the host via the Xmodem protocol. The +UFWINSTALL AT command then triggers a reboot, and upon reboot initiates a firmware installation on the device via a special boot loader on the module. The bootloader first authenticates the downloaded image, then installs it, and then reboots the module. Firmware authenticity verification is performed via a security signature. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware installation. After completing the upgrade, the module is reset again and wakes-up in normal boot. For more details about Firmware update Over AT procedure, see the SARA-R4/N4 series AT Commands Manual [2], +UFWUPD AT command. 1.13.8 Firmware update Over The Air (uFOTA) This feature allows upgrading the module firmware over the air interface, based on u-blox client/server solution (uFOTA), using LWM2M. For more details about firmware update over-the-air procedure, see the SARA-R4/N4 series AT Commands Manual [2]. UBX-16029218 - R11 System description Page 46 of 157 SARA-R4/N4 series - System Integration Manual 1.13.9 Power saving 1.13.9.1 Guidelines to optimize power consumption The LTE Cat M1 / NB1 technology is mainly intended for applications that only require a small amount of data exchange per day (i.e. a few bytes in uplink and downlink per day). Depending on the application type, the battery may be required to last for a few years. For these reasons, the whole application board should be optimized in terms of current consumption and should carefully take into account the following aspects:

Enable the low power mode configuration using the AT+UPSV command (for the complete description of the AT+UPSV command, see the SARA-R4/N4 series AT Commands Manual [2]). Enable the power saving mode configuration using the AT+CPSMS command (for the complete description of the AT+CPSMS command, see the SARA-R4/N4 series AT Commands Manual [2]). Use the UART interface instead of the USB interface as a serial communication interface, because the current consumption of the module is ~20 mA higher when the USB interface is enabled. Use an application processor with a UART interface working at the same voltage level (1.8 V) as the module. In this way it is possible to avoid voltage translators, which helps to minimize current leakage. If the USB interface is implemented in the design, remove the external USB VBUS voltage from the VUSB_DET input when serial communication is not necessary, letting the module enter the Power Saving Mode defined in 3GPP Rel.13: the module does not enter the deep sleep power saving mode if the USB interface is enabled. Minimize current leakage on the power supply line. Optimize the antenna matching, since a mismatched antenna leads to higher current consumption. Monitor V_INT level to sense when the module enters power-off mode or deep sleep power saving mode. Disconnect the VCC supply source from the module when it is switched off (see 2.2.1.9). Disconnect the VCC supply source from the module during deep sleep power saving mode (see 2.2.1.9):

using a host application processor equipped with a RTC, the module can execute a standard PSM procedure and store the NAS protocol context in non-volatile memory, and then rely on the host application processor for running its RTC and triggering wake-up upon need11. 1.13.9.2 Functionality When power saving is enabled using the AT+CPSMS command, the module automatically enters the low power deep sleep mode whenever possible, reducing current consumption (see the section 1.5.1.4 and the SARA-R4/N4 series Data Sheet [1]). 11 The use of an external RTC during deep sleep power saving mode is not supported by the 00, 01 and x2 product versions UBX-16029218 - R11 System description Page 47 of 157 SARA-R4/N4 series - System Integration Manual For the definition and the description of the SARA-R4/N4 series operating modes, including the events forcing transitions between the different operating modes, see section 1.4. The SARA-R4/N4 series modules achieve the low power deep sleep mode by powering down all the Hardware components with the exception of the 32 kHz reference internally generated. From the host application point of view, the serial port will not be available during low power deep sleep mode, as the SARA-R4/N4 series module will act as if it is in Power-Off mode. 1.13.9.3 Timers and network interaction The SARA-R4/N4 series modules goes in low power deep sleep mode entering in the Power Saving Mode

(PSM) defined in 3GPP Release 13. Two timers have been specified on the PSM Signaling: the Periodic Update Timer and Active Timer. The Active Timer is the time defined by the network where the SARA-R4/N4 series module will keep listening for any active operation, during this time the module is in Active mode. The Periodic Update Timer is the Extended Tracking Area Update (TAU) used by the SARA-R4/N4 series module to periodically notify the network of its availability. The SARA-R4/N4 series module requests the PSM by including the Active Timer with the desired value in the Attach, TAU or Routing Area Update (RAU) messages. The Active Timer is the time the module listens to the Paging Channel after having transitioned from connected to active mode. When the Active Timer expires, the module enters PSM low power deep sleep mode. SARA-R4/N4 series module can also request an extended Periodic Update Timer value to remain in PSM low power deep sleep mode for longer than the original Periodic Update Timer broadcasted by the network. The grant of PSM is a negotiation between SARA-R4/N4 series module and the attached network: the network accepts PSM by providing the actual value of the Active Timer (and Periodic Update Timer) to be used in the Attach/TAU/RAU accept procedure. The maximum duration, including the Periodic Update Timer, is about 413 days. The SARA-R4/N4 series module enters PSM low power deep sleep mode only after the Active Timer expires. UBX-16029218 - R11 System description Page 48 of 157 SARA-R4/N4 series - System Integration Manual Figure 14: Description of the PSM timing 1.13.9.4 Timers and AT interaction The SARA-R4/N4 series modules go into low power deep sleep mode and enter the Power Saving Mode

(PSM) only after the 6 s AT Inactivity Timer expires:

If the UART interface is used, when the host application stops sending AT commands for 6 s the AT Inactivity Timer expiration then the module enters deep sleep power saving mode according to Active Timer expiration. If the USB interface is enabled, the module does not enter the deep sleep power saving mode. 1.13.9.5 AT commands The module uses the +CPSMS AT command with its defined parameters to request PSM timers to the network. See the SARA-R4/N4 series AT Commands Manual [2] for details of the +CPSMS operation and features. 1.13.9.6 Host application The PSM low power deep sleep mode implementation allows the SARA-R4/N4 series module to help extend the battery life of the application. The Host Application should be aware that the SARA-R4/N4 series module is PSM-capable. The host application needs to sense the V_INT supply output of the module to get the notification when the module has entered into PSM low power deep sleep mode. If the host application receives an event that needs to be reported by the SARA-R4/N4 series module interrupting the PSM low power deep sleep mode, it can be done so by setting the module into Active mode using the appropriate power-on event (see 1.6.1). From the host application point of view, the module will look as it is in Power-Off mode. UBX-16029218 - R11 System description Page 49 of 157 PSM low power deep sleep mode(periodic update timer)Connected mode: Data Tx / RxActive mode(active timer)TimeCurrent SARA-R4/N4 series - System Integration Manual 1.13.9.7 Normal operation The Host Application can force the SARA-R4/N4 series module to transition from PSM low power deep sleep mode to Active mode by using the Power-Up procedure specified in section 1.6.1. Be aware that when the host application transitions from low power deep sleep mode to active mode, it will cause the SARA-R4/N4 series module to consume the same amount of power as in active mode, thereby shortening the battery life of the host application. UBX-16029218 - R11 System description Page 50 of 157 SARA-R4/N4 series - System Integration Manual 2 Design-in 2.1 Overview For an optimal integration of the SARA-R4/N4 series modules in the final application board, follow the design guidelines stated in this section. Every application circuit must be suitably designed to guarantee the correct functionality of the relative interface, but a number of points require particular attention during the design of the application device. The following list provides a rank of importance in the application design, starting from the highest relevance:

1. Module antenna connection: ANT and ANT_DET pins. Antenna circuit directly affects the RF compliance of the device integrating a SARA-R4/N4 series module with applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the schematic and layout design. 2. Module supply: VCC and GND pins. The supply circuit affects the RF compliance of the device integrating a SARA-R4/N4 series module with the applicable required certification schemes as well as the antenna circuit design. Very carefully follow the suggestions provided in the relative section 2.2.1 for the schematic and layout design. 3. USB interface: USB_D+, USB_D- and VUSB_DET pins. Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the suggestions provided in the relative section 2.6.2 for the schematic and layout design. 4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins. Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling. Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design. 5. System functions: RESET_N and PWR_ON pins. Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully follow the suggestions provided in relative section 2.3 for schematic and layout design. 6. Other digital interfaces: UART, SPI, SDIO, I2C, I2S, GPIOs and reserved pins. Accurate design is required to guarantee correct functionality and reduce the risk of digital data frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3, 2.6.4, 2.6.5, 2.7, 2.8 and 2.9 for the schematic and layout design. UBX-16029218 - R11 Design-in Page 51 of 157 SARA-R4/N4 series - System Integration Manual 7. Other supplies: V_INT generic digital interfaces supply. Accurate design is required to guarantee correct functionality. Follow the suggestions provided in the corresponding section 2.2.2 for the schematic and layout design. It is recommended to follow the specific design guidelines provided by each manufacturer of any external part selected for the application board integrating the u-blox cellular modules. UBX-16029218 - R11 Design-in Page 52 of 157 SARA-R4/N4 series - System Integration Manual 2.2 Supply interfaces 2.2.1 Module supply (VCC) 2.2.1.1 General guidelines for VCC supply circuit selection and design All the available VCC pins have to be connected to the external supply minimizing the power loss due to series resistance. GND pins are internally connected. Application design shall connect all the available pads to solid ground on the application board, since a good (low impedance) connection to external ground can minimize power loss and improve RF and thermal performance. SARA-R4/N4 series modules must be sourced through the VCC pins with a suitable DC power supply that should meet the following prerequisites to comply with the modules VCC requirements summarized in Table 6. The appropriate DC power supply can be selected according to the application requirements (see Figure 15) between the different possible supply sources types, which most common ones are the following:

Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery Figure 15: VCC supply concept selection The switching step-down regulator is the typical choice when primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the operating supply voltage of SARA-R4/N4 series. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source. See section 2.2.1.2 for design-in. The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage

(e.g. less or equal than 5 V). In this case, the typical 90% efficiency of the switching regulator diminishes the benefit of voltage step-down and no true advantage is gained in input current savings. On the opposite UBX-16029218 - R11 Design-in Page 53 of 157 Main Supply Available?BatteryLi-Ion 3.7 VLinear LDO RegulatorMain Supply Voltage > 5V?Switching Step-Down RegulatorNo, portable deviceNo, less than 5 VYes, greater than 5 VYes, always available SARA-R4/N4 series - System Integration Manual side, linear regulators are not recommended for high voltage step-down as they dissipate a considerable amount of energy in thermal power. See section 2.2.1.3 for design-in. If SARA-R4/N4 series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided. See sections 2.2.1.4, 2.2.1.5, 2.2.1.6 and 2.2.1.7 for specific design-in. Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger circuit, which is not included in the modules. The charger circuit needs to be designed to prevent over-

voltage on VCC pins, and it should be selected according to the application requirements. A DC/DC switching charger is the typical choice when the charging source has a high nominal voltage (e.g. ~12 V), whereas a linear charger is the typical choice when the charging source has a relatively low nominal voltage

(~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a suitable charger

/ regulator with integrated power path management function can be selected to supply the module while simultaneously and independently charging the battery. See sections 2.2.1.6 and 2.2.1.7 for specific design-

in. An appropriate primary (not rechargeable) battery can be selected taking into account the maximum current specified in the SARA-R4/N4 series Data Sheet [1] during connected mode, considering that primary cells might have weak power capability. See section 2.2.1.5 for specific design-in. The usage of more than one DC supply at the same time should be carefully evaluated: depending on the supply source characteristics, different DC supply systems can result as mutually exclusive. The selected regulator or battery must be able to support with adequate margin the highest averaged current consumption value specified in the SARA-R4/N4 series Data Sheet [1]. The following sections highlight some design aspects for each of the supplies listed above providing application circuit design-in compliant with the module VCC requirements summarized in Table 6. 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator The use of a switching regulator is suggested when the difference from the available supply rail source to the VCC value is high, since switching regulators provide good efficiency transforming a 12 V or greater voltage supply to the typical 3.8 V value of the VCC supply. The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

UBX-16029218 - R11 Design-in Page 54 of 157 SARA-R4/N4 series - System Integration Manual Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current consumption occurring during transmissions at the maximum power, as specified in the SARA-R4/N4 series Data Sheet [1]. Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile. High switching frequency: for best performance and for smaller applications it is recommended to select a switching frequency 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC profile and therefore negatively impact modulation spectrum performance. PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in connected mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM modes transitions must be avoided to reduce noise on VCC voltage profile. Switching regulators can be used that are able to switch between low ripple PWM mode and high ripple PFM mode, provided that the mode transition occurs when the module changes status from the active mode to connected mode. It is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold. Figure 16 and the components listed in Table 9 show an example of a high reliability power supply circuit for the SARA-R412M modules that support 2G radio access technology. This circuit is also suitable for the other SARA-R4/N4 series modules, where the module VCC input is supplied by a step-down switching regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. Figure 16: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 10 F Capacitor Ceramic X7R 5750 15% 50 V Generic manufacturer 10 nF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 680 pF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 22 pF Capacitor Ceramic C0G 0402 5% 25 V Generic manufacturer UBX-16029218 - R11 Design-in Page 55 of 157 SARA-R4/N412VC5R3C4R2C2C1R1VINRUNVCRTPGSYNCBDBOOSTSWFBGND671095C61238114C7C8D1R4R5L1C3U152VCC53VCC51VCCGNDC9C10C11 SARA-R4/N4 series - System Integration Manual C5 C6 C7 C8 C9 C10 C11 D1 L1 R1 R2 R3 R4 R5 U1 10 nF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 470 nF Capacitor Ceramic X7R 0603 10% 25 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor 10 H Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics 470 k Resistor 0402 5% 0.1 W Generic manufacturer 15 k Resistor 0402 5% 0.1 W Generic manufacturer 22 k Resistor 0402 5% 0.1 W Generic manufacturer 390 k Resistor 0402 1% 0.063 W Generic manufacturer 100 k Resistor 0402 5% 0.1 W Generic manufacturer Step-Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology Table 9: Components for high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. Figure 17 and the components listed in Table 10 show an example of a high reliability power supply circuit for SARA-R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access technology. In this example, the module VCC is supplied by a step-down switching regulator capable of delivering the maximum peak / pulse current specified for the LTE use-case, with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. Figure 17: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using a step-down regulator Reference Description Part Number - Manufacturer C1 10 F Capacitor Ceramic X7R 50 V Generic manufacturer UBX-16029218 - R11 Design-in Page 56 of 157 SARA-R404MSARA-R410M SARA-N41012VC2C1VCCENPGVSWGND89142D1L1U1BSTFB5R1R252VCC53VCC51VCCGND3V8C6C7C8PGNDC4C3C51110C9 SARA-R4/N4 series - System Integration Manual C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 R1 R2 U1 10 nF Capacitor Ceramic X7R 16 V Generic manufacturer 22 nF Capacitor Ceramic X7R 16 V Generic manufacturer 22 F Capacitor Ceramic X5R 25 V Generic manufacturer 22 F Capacitor Ceramic X5R 25 V Generic manufacturer 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 30 V 2 A MBR230LSFT1G - ON Semiconductor 4.7 H Inductor 20% 2 A SLF7045T-4R7M2R0-PF - TDK 470 k Resistor 0.1 W 150 k Resistor 0.1 W Generic manufacturer Generic manufacturer Step-Down Regulator 1 A 1 MHz TS30041 - Semtech Table 10: High reliability VCC supply circuit components for SARA-R404M /-R410M /-N410, using a step-down regulator See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 57 of 157 SARA-R4/N4 series - System Integration Manual Figure 18 and the components listed in Table 11 show an example of a low cost power supply circuit suitable for all the SARA-R4/N4 series modules, where the module VCC is supplied by a step-down switching regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, transforming a 12 V supply input. Figure 18: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 L1 R1 R2 R3 R4 R5 U1 22 F Capacitor Ceramic X5R 1210 10% 25 V Generic manufacturer 220 nF Capacitor Ceramic X7R 0603 10% 25 V Generic manufacturer 5.6 nF Capacitor Ceramic X7R 0402 10% 50 V Generic manufacturer 6.8 nF Capacitor Ceramic X7R 0402 10% 50 V Generic manufacturer 56 pF Capacitor Ceramic C0G 0402 5% 50 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 25V 2 A STPS2L25 STMicroelectronics 5.2 H Inductor 30% 5.28A 22 m MSS1038-522NL Coilcraft 4.7 k Resistor 0402 1% 0.063 W Generic manufacturer 910 Resistor 0402 1% 0.063 W Generic manufacturer 82 Resistor 0402 5% 0.063 W Generic manufacturer 8.2 k Resistor 0402 5% 0.063 W Generic manufacturer 39 k Resistor 0402 5% 0.063 W Generic manufacturer Step-Down Regulator 8-VFQFPN 3 A 1 MHz L5987TR ST Microelectronics Table 11: Suggested components for low cost VCC circuit for SARA-R4/N4 series modules, using a step-down regulator See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 58 of 157 SARA-R4/N412VR5C2C1VCCINHFSWSYNCOUTGND263178C3D1R1R2L1U1GNDFBCOMP54R3C4R4C552VCC53VCC51VCCC6C7C8C9C10 SARA-R4/N4 series - System Integration Manual UBX-16029218 - R11 Design-in Page 59 of 157 SARA-R4/N4 series - System Integration Manual 2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator The use of a linear regulator is suggested when the difference from the available supply rail source and the VCC value is low. The linear regulators provide high efficiency when transforming a 5 VDC supply to a voltage value within the module VCC normal operating range. The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current consumption occurring during a transmission at the maximum Tx power, as specified in the SARA-R4/N4 series Data Sheet [1]. Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the rated range (i.e. check the voltage drop from the maximum input voltage to the minimum output voltage to evaluate the power dissipation of the regulator). Figure 19 and the components listed in Table 12 show an example of a high reliability power supply circuit for the SARA-R412M modules supporting the 2G radio access technology. This example is also suitable for the other SARA-R4/N4 series modules, where the VCC module supply is provided by an LDO linear regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, with an appropriate power handling capability. The regulator described in this example supports a wide input voltage range, and it includes internal circuitry for reverse battery protection, current limiting, thermal limiting and reverse current protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 20 and Table 13). This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit. Figure 19: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 10 F Capacitor Ceramic X5R 0603 20% 6.3 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata UBX-16029218 - R11 Design-in Page 60 of 157 5VC1INOUTADJGND12453R1R2U1SHDNSARA-R4/N452VCC53VCC51VCCGNDC2C3C4C5C6 SARA-R4/N4 series - System Integration Manual C4 C5 C6 R1 R2 U1 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 9.1 k Resistor 0402 5% 0.1 W Generic manufacturer 3.9 k Resistor 0402 5% 0.1 W Generic manufacturer LDO Linear Regulator ADJ 3.0 A LT1764AEQ#PBF - Linear Technology Table 12: Suggested components for high reliability VCC circuit for SARA-R4/N4 series modules, using an LDO regulator See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. Figure 20 and the components listed in Table 13 show an example of a high reliability power supply circuit for SARA-R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access technology, where the module VCC is supplied by an LDO linear regulator capable of delivering maximum peak / pulse current specified for LTE use-case, with suitable power handling capability. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V for the VCC, as in the circuits described in Figure 20 and Table 13). This reduces the power on the linear regulator and improves the thermal design of the circuit. Figure 20: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 R1 R2 R3 1 F Capacitor Ceramic X5R 6.3 V Generic manufacturer 22 F Capacitor Ceramic X5R 25 V Generic manufacturer 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 47 k Resistor 0.1 W 41 k Resistor 0.1 W 10 k Resistor 0.1 W Generic manufacturer Generic manufacturer Generic manufacturer UBX-16029218 - R11 Design-in Page 61 of 157 5VC1R1INOUTADJGND58134C2R2R3U1ENSARA-R404MSARA-R410MSARA-N41052VCC53VCC51VCCGNDC4C3C5C6 SARA-R4/N4 series - System Integration Manual U1 LDO Linear Regulator 1.0 A AP7361 Diodes Incorporated Table 13: Components for high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. Figure 21 and the components listed in Table 14 show an example of a low cost power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak / pulse current, with an appropriate power handling capability. The regulator described in this example supports a limited input voltage range and it includes internal circuitry for current and thermal protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 21 and Table 14). This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit. Figure 21: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 R1 R2 U1 10 F Capacitor Ceramic X5R 0603 20% 6.3 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 27 k Resistor 0402 5% 0.1 W Generic manufacturer 4.7 k Resistor 0402 5% 0.1 W Generic manufacturer LDO Linear Regulator ADJ 3.0 A LP38501ATJ-ADJ/NOPB - Texas Instrument Table 14: Suggested components for low cost VCC supply circuit for SARA-R4/N4 modules, using an LDO linear regulator UBX-16029218 - R11 Design-in Page 62 of 157 5VC1INOUTADJGND12453R1R2U1ENSARA-R4/N452VCC53VCC51VCCGNDC2C3C4C5C6 SARA-R4/N4 series - System Integration Manual See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 63 of 157 SARA-R4/N4 series - System Integration Manual 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output circuit connected to the VCC pins must be capable of delivering the maximum current occurring during a transmission at maximum Tx power, as specified in the SARA-R4/N4 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts. 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Maximum pulse and DC discharge current: the non-rechargeable battery with its related output circuit connected to the VCC pins must be capable of delivering the maximum current consumption occurring during a transmission at maximum Tx power, as specified in SARA-R4/N4 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts. 2.2.1.6 Guidelines for external battery charging circuit SARA-R4/N4 series modules do not have an on-board charging circuit. Figure 22 provides an example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell. In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features the correct pulse and DC discharge current capabilities and the appropriate DC series resistance, is directly connected to the VCC supply input of the module. Battery charging is completely managed by the Battery Charger IC, which from a USB power source (5.0 V typ.), linearly charges the battery in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current. Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor. UBX-16029218 - R11 Design-in Page 64 of 157 SARA-R4/N4 series - System Integration Manual Constant voltage: when the battery voltage reaches the regulated output voltage, the Battery Charger IC starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor or when the charging timer reaches the factory set value. Using a battery pack with an internal NTC resistor, the Battery Charger IC can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. The Battery Charger IC, as linear charger, is more suitable for applications where the charging source has a relatively low nominal voltage (~5 V), so that a switching charger is suggested for applications where the charging source has a relatively high nominal voltage (e.g. ~12 V, see section 2.2.1.7 for the specific design-

in). Figure 22: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Part Number - Manufacturer B1 C1 C2 C3 C4 C5 C6 Li-Ion (or Li-Polymer) battery pack with 470 NTC Generic manufacturer 1 F Capacitor Ceramic X7R 16 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2 Low Capacitance ESD Protection CG0402MLE-18G - Bourns R1 U1 10 k Resistor 0.1 W Generic manufacturer Single Cell Li-Ion (or Li-Polymer) Battery Charger IC MCP73833 - Microchip Table 15: Suggested components for the Li-Ion (or Li-Polymer) battery charging application circuit See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 65 of 157 C5C3C6GNDSARA-R4/N452VCC53VCC51VCCUSB SupplyU1PGSTAT2STA1VDDC15V0THERMVssVbatLi-Ion/Li-Pol Battery PackD1B1C2Li-Ion/Li-Polymer Battery Charger ICD2PROGR1C4 SARA-R4/N4 series - System Integration Manual 2.2.1.7 Guidelines for external charging and power path management circuit Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as a possible supply source, should implement a suitable charger / regulator with integrated power path management function to supply the module and the whole device while simultaneously and independently charging the battery. Figure 23 reports a simplified block diagram circuit showing the working principle of a charger / regulator with integrated power path management function. This component allows the system to be powered by a permanent primary supply source (e.g. ~12 V) using the integrated regulator, which simultaneously and independently recharges the battery (e.g. 3.7 V Li-Pol) that represents the back-up supply source of the system. The power path management feature permits the battery to supplement the system current requirements when the primary supply source is not available or cannot deliver the peak system currents. A power management IC should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

High efficiency internal step down converter, with characteristics as indicated in section 2.2.1.2 Low internal resistance in the active path Vout Vbat, typically lower than 50 m High efficiency switch mode charger with separate power path control Figure 23: Charger / regulator with integrated power path management circuit block diagram Figure 24 and the parts listed in Table 16 provide an application circuit example where the MPS MP2617H switching charger / regulator with integrated power path management function provides the supply to the cellular module. At the same time it also concurrently and autonomously charges a suitable Li-Ion (or Li-

Polymer) battery with the correct pulse and DC discharge current capabilities and the appropriate DC series resistance according to the rechargeable battery recommendations described in section 2.2.1.4. The MP2617H IC constantly monitors the battery voltage and selects whether to use the external main primary supply / charging source or the battery as supply source for the module, and starts a charging phase accordingly. UBX-16029218 - R11 Design-in Page 66 of 157 GNDPower path management ICVoutVinLi-Ion/Li-Pol Battery PackGNDSystem12 V Primary SourceCharge controllerDC/DC converter and battery FET control logicVbat SARA-R4/N4 series - System Integration Manual The MP2617H IC normally provides a supply voltage to the module regulated from the external main primary source allowing immediate system operation even under missing or deeply discharged battery: the integrated switching step-down regulator is capable to provide up to 3 A output current with low output ripple and fixed 1.6 MHz switching frequency in PWM mode operation. The module load is satisfied in priority, then the integrated switching charger will take the remaining current to charge the battery. Additionally, the power path control allows an internal connection from battery to the module with a low series internal ON resistance (40 m typical), in order to supplement additional power to the module when the current demand increases over the external main primary source or when this external source is removed. Battery charging is managed in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for the application Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively reduced until the charge termination is done. The charging process ends when the charging current reaches the 10% of the fast-charge current or when the charging timer reaches the value configured by an external capacitor Using a battery pack with an internal NTC resistor, the MP2617H can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. Several parameters as the charging current, the charging timings, the input current limit, the input voltage limit, the system output voltage can be easily set according to the specific application requirements, as the actual electrical characteristics of the battery and the external supply / charging source: suitable resistors or capacitors must be accordingly connected to the related pins of the IC. UBX-16029218 - R11 Design-in Page 67 of 157 SARA-R4/N4 series - System Integration Manual Figure 24: Li-Ion (or Li-Polymer) battery charging and power path management application circuit Reference Description Part Number - Manufacturer B1 C1, C6 Li-Ion (or Li-Polymer) battery pack with 10 k NTC Various manufacturer 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata C2, C4, C10 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata C3 C5 C7, C12 C8, C13 C11 D1, D2 D3 1 F Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E105KA12 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata Low Capacitance ESD Protection CG0402MLE-18G - Bourns Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor R1, R3, R5, R7 10 k Resistor 0402 1% 1/16 W Generic manufacturer R2 R4 R6 L1 U1 1.05 k Resistor 0402 1% 0.1 W Generic manufacturer 22 k Resistor 0402 1% 1/16 W Generic manufacturer 26.5 k Resistor 0402 1% 1/16 W Generic manufacturer 2.2 H Inductor 7.4 A 13 m 20%

SRN8040-2R2Y - Bourns Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator with MP2617H - Monolithic Power Systems (MPS) integrated Power Path Management function Table 16: Suggested components for battery charging and power path management application circuit See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 68 of 157 C10C13GNDC12C11SARA-R4/N452VCC53VCC51VCC+Primary SourceR3U1ENnILIMISETTMRAGNDVINC2C112VNTCPGNDSWSYSBATC4R1R2D1Li-Ion/Li-Pol Battery PackB1C5Li-Ion/Li-Polymer Battery Charger / Regulator with Power Path ManagmentVCCC3C6L1BSTD2VLIMR4R5C7C8D3R6SYSFBR7 SARA-R4/N4 series - System Integration Manual 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R412M SARA-R412M modules have separate supply inputs over the VCC pins (see Figure 3):

VCC pins #52 and #53: supply input for the internal RF Power Amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call VCC pin #51: supply input for the internal Power Management Unit, Base-Band and Transceiver parts, demanding minor current Generally, all the VCC pins are intended to be connected to the same external power supply circuit, but separate supply sources can be implemented for specific (e.g. battery-powered) applications. The voltage at the VCC pins #52 and #53 can drop to a value lower than the one at the VCC pin #51, keeping the module still switched-on and functional. Figure 25 illustrates a possible application circuit. Figure 25: VCC circuit example with separate supply for SARA-R412M modules Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 D1 L1 R1 R2 U1 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 56 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E560JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Schottky Diode 40 V 1 A SS14 - Vishay General Semiconductor 10 H Inductor 20% 1 A 276 m SRN3015-100M - Bourns Inc. 1 M Resistor 0402 5% 0.063 W 412 k Resistor 0402 5% 0.063 W Generic manufacturer Generic manufacturer Step-up Regulator 350 mA AP3015 - Diodes Incorporated Table 17: Examples of components for the VCC circuit with separate supply for SARA-R412M modules UBX-16029218 - R11 Design-in Page 69 of 157 C1C4GNDC3C2C5SARA-R412M52VCC53VCC51VCC+Li-Ion/Li-Pol BatteryC6SWVINSHDNnGNDFBC7R1R2L1U1Step-up RegulatorD1C8 SARA-R4/N4 series - System Integration Manual See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. UBX-16029218 - R11 Design-in Page 70 of 157 SARA-R4/N4 series - System Integration Manual 2.2.1.9 Guidelines for removing VCC supply Removing the VCC power can be useful to minimize the current consumption when the SARA-R4/N4 series modules are switched off or when the modules are in deep sleep Power Saving Mode. In applications in which the module is paired to a host application processor equipped with a RTC, the module can execute standard PSM procedures, store NAS protocol context in non-volatile memory, and rely on the host application processor to run its RTC and to trigger wake-up upon need. The application processor can disconnect the VCC supply source from the module and zero out the modules PSM current. The VCC supply source can be removed using an appropriate low-leakage load switch or p-channel MOSFET controlled by the application processor as shown in Figure 26, given that the external switch has provide:

Very low leakage current (for example, less than 1 A), to minimize the current consumption Very low RDS(ON) series resistance (for example, less than 50 m), to minimize voltage drops Adequate maximum Drain current (see the SARA-R4/N4 series Data Sheet [1] for module current consumption figures) Figure 26: Example of application circuit for VCC supply removal Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata R1, R3 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp R2 T1 U1 10 k Resistor 0402 5% 0.1 W RC0402JR-0710KL - Yageo Phycomp NPN BJT Transistor BC847 - Infineon Ultra-Low Resistance Load Switch TPS22967 - Texas Instruments Table 18: Components for VCC supply removal application circuit UBX-16029218 - R11 Design-in Page 71 of 157 C3GNDC2C1C4SARA-R4/N452VCC53VCC51VCCVCC Supply SourceGNDC5U1VOUTVINVBIASONCTGND4V_INT15PWR_ONR1R2T1GPIOApplication ProcessorGPIOGPIO+SARA-R4/N4 series - System Integration Manual It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series normal operations: the VCC supply can be removed only after V_INT goes low, indicating that the module has entered Deep-Sleep Power Saving Mode or Power-Off Mode. See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the application device integrates an internal antenna. 2.2.1.10 Additional guidelines for VCC supply circuit design To reduce voltage drops, use a low impedance power source. The series resistance of the supply lines

(connected to the modules VCC and GND pins) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize losses. Three pins are allocated to VCC supply connection. Several pins are designated for GND connection. It is recommended to correctly connect all of them to supply the module minimizing series resistance. To reduce voltage ripple and noise, improving RF performance especially if the application device integrates an internal antenna, place the following bypass capacitors near the VCC pins:

68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata GRM1555C1H680J), to filter EMI in the low cellular frequency bands 15 pF capacitor with Self-Resonant Frequency in the 1800/1900 MHz range (as Murata GRM1555C1H150J), to filter EMI in the high cellular frequency bands 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise from clocks and data 100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data An additional capacitor is recommended to avoid undershoot and overshoot at the start and at the end of RF transmission:

100 F low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA-R412M supporting 2G 10 F capacitor (or greater), for the other SARA-R4/N4 series modules that do not support 2G An additional series ferrite bead is recommended for additional RF noise filtering, in particular if the application device integrates an internal antenna:

Ferrite bead specifically designed for EMI suppression in GHz band (e.g. Murata BLM18EG221SN1), placed as close as possible to the VCC pins of the module, implementing the circuit described in Figure 27, to filter out EMI in all the cellular bands UBX-16029218 - R11 Design-in Page 72 of 157 SARA-R4/N4 series - System Integration Manual Figure 27: Suggested design to reduce ripple / noise on VCC, highly recommended when using an integrated antenna Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata FB1 Chip Ferrite Bead EMI Filter for GHz Band Noise BLM18EG221SN1 - Murata 220 at 100 MHz, 260 at 1 GHz, 2000 mA Table 19: Suggested components to reduce ripple / noise on VCC The necessity of each part depends on the specific design, but it is recommended to provide all the parts described in Figure 27 / Table 19 if the application device integrates an internal antenna. ESD sensitivity rating of the VCC supply pins is 1 kV (HBM according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if accessible battery connector is directly connected to the supply pins. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point. 2.2.1.11 Guidelines for VCC supply layout design Good connection of the module VCC pins with DC supply source is required for correct RF performance. Guidelines are summarized in the following list:

All the available VCC pins must be connected to the DC source VCC connection must be as wide as possible and as short as possible Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be avoided VCC connection must be routed through a PCB area separated from RF lines / parts, sensitive analog signals and sensitive functional units: it is good practice to interpose at least one layer of PCB ground between the VCC track and other signal routing UBX-16029218 - R11 Design-in Page 73 of 157 C5GND plane VCC lineCapacitor with SRF ~900 MHzC1C3C4FB1Ferrite Bead for GHz noiseC2C1GNDC2C4SARA-R4/N452VCC53VCC51VCC3V8C5+FB1C3Capacitor with SRF ~1900 MHzSARA SARA-R4/N4 series - System Integration Manual VCC connection must be routed as far as possible from the antenna, in particular if embedded in the application device: see Figure 28 Coupling between VCC and digital lines, especially USB, must be avoided. The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.10 should be placed close to the VCC pins. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-DC output and minimize VCC track length. Otherwise consider using separate capacitors for DC-DC converter and module tank capacitor The bypass capacitors in the pF range described in Figure 27 and Table 19 should be placed as close as possible to the VCC pins, where the VCC line narrows close to the module input pins, improving the RF noise rejection in the band centered on the Self-Resonant Frequency of the pF capacitors. This is highly recommended if the application device integrates an internal antenna Since VCC input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting to the SARA-R4/N4 series modules in the worst case Shielding of switching DC-DC converter circuit, or at least the use of shielded inductors for the switching DC-DC converter, may be considered since all switching power supplies may potentially generate interfering signals as a result of high-frequency high-power switching. If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings are not exceeded, place the protecting device along the path from the DC source toward the module, preferably closer to the DC source (otherwise protection function may be compromised) Figure 28: VCC line routing guideline for designs integrating an embedded antenna 2.2.1.12 Guidelines for grounding layout design Good connection of the module GND pins with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module. Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The VCC supply current flows back to main DC source through GND as ground current: provide adequate return path with suitable uninterrupted ground plane to main DC source UBX-16029218 - R11 Design-in Page 74 of 157 SARAVCCANTAntennaNOT OKAntennaSARAVCCANTOKAntennaSARAVCCANTNOT OK SARA-R4/N4 series - System Integration Manual It is recommended to implement one layer of the application board as ground plane as wide as possible If the application board is a multilayer PCB, then all the board layers should be filled with GND plane as much as possible and each GND area should be connected together with complete via stack down to the main ground layer of the board. Use as many vias as possible to connect the ground planes Provide a dense line of vias at the edges of each ground area, in particular along RF and high speed lines If the whole application device is composed by more than one PCB, then it is required to provide a good and solid ground connection between the GND areas of all the different PCBs Good grounding of GND pads also ensures thermal heat sink. This is critical during connection, when the real network commands the module to transmit at maximum power: correct grounding helps prevent module overheating. 2.2.2 Generic digital interfaces supply output (V_INT) 2.2.2.1 Guidelines for V_INT circuit design SARA-R4/N4 series modules provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly used to:

Indicate when the module is switched on and it is not in the deep sleep power saving mode (as described in sections 1.6.1, 1.6.2) Pull-up SIM detection signal (see section 2.5 for more details) Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. see 2.6.1) Enable external voltage regulators providing supply for external devices Do not apply loads which might exceed the maximum available current from V_INT supply (see SARA-

R4/N4 series Data Sheet [1]) as this can cause malfunctions in internal circuitry. V_INT can only be used as an output: do not connect any external supply source on V_INT. ESD sensitivity rating of the V_INT supply pin is 1 kV (HBM according to JESD22-A114). Higher protection level could be required if the line is externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG) close to accessible point. It is recommended to monitor the V_INT pin to sense the end of the internal switch-off sequence of SARA-R4/N4 series modules: VCC supply can be removed only after V_INT goes low. It is recommended to provide direct access to the V_INT pin on the application board by means of an accessible test point directly connected to the V_INT pin. UBX-16029218 - R11 Design-in Page 75 of 157 SARA-R4/N4 series - System Integration Manual 2.3 System functions interfaces 2.3.1 Module power-on (PWR_ON) 2.3.1.1 Guidelines for PWR_ON circuit design SARA-R4/N4 series PWR_ON input is equipped with an internal active pull-up resistor; an external pull-up resistor is not required and should not be provided. If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection should be provided close to the accessible point, as described in Figure 29 and Table 20. ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if an accessible push button is directly connected to PWR_ON pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to the accessible point. An open drain or open collector output is suitable to drive the PWR_ON input from an application processor, as described in Figure 29. PWR_ON input pin should not be driven high by an external device, as it may cause start up issues. Figure 29: PWR_ON application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD CT0402S14AHSG - EPCOS Varistor array for ESD protection Table 20: Example ESD protection component for the PWR_ON application circuit It is recommended to provide direct access to the PWR_ON pin on the application board by means of an accessible test point directly connected to the PWR_ON pin. UBX-16029218 - R11 Design-in Page 76 of 157 SARA-R4/N415PWR_ONPower-on push buttonESDOpen Drain OutputApplication ProcessorSARA-R4/N415PWR_ONTPTP SARA-R4/N4 series - System Integration Manual 2.3.1.2 Guidelines for PWR_ON layout design The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on and switch off the SARA-R4/N4 series modules. It is required to ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request. UBX-16029218 - R11 Design-in Page 77 of 157 SARA-R4/N4 series - System Integration Manual 2.3.2 Module reset (RESET_N) 2.3.2.1 Guidelines for RESET_N circuit design SARA-R4/N4 series RESET_N is equipped with an internal pull-up; an external pull-up resistor is not required. If connecting the RESET_N input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible point on the line connected to this pin, as described in Figure 30 and Table 21. ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if an accessible push button is directly connected to the RESET_N pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point. An open drain output or open collector output is suitable to drive the RESET_N input from an application processor, as described in Figure 30. RESET_N input pin should not be driven high by an external device, as it may cause start up issues. Figure 30: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD Varistor for ESD protection CT0402S14AHSG - EPCOS Table 21: Example of ESD protection component for the RESET_N application circuits If the external reset function is not required by the customer application, the RESET_N input pin can be left unconnected to external components, but it is recommended providing direct access on the application board by means of an accessible test point directly connected to the RESET_N pin. 2.3.2.2 Guidelines for RESET_N layout design The RESET_N circuit require careful layout due to the pin function: ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious reset request. It is recommended to keep the connection line to RESET_N pin as short as possible. UBX-16029218 - R11 Design-in Page 78 of 157 SARA-R4/N418RESET_NPower-on push buttonESDOpen Drain OutputApplication ProcessorSARA-R4/N418RESET_NTPTP SARA-R4/N4 series - System Integration Manual 2.4 Antenna interface SARA-R4/N4 series modules provide an RF interface for connecting the external antenna: the ANT pin represents the RF input/output for RF signals transmission and reception. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the physical antenna through a 50 transmission line to allow clean transmission / reception of RF signals. 2.4.1 Antenna RF interface (ANT) 2.4.1.1 General guidelines for antenna selection and design The antenna is the most critical component to be evaluated. Designers must take care of the antenna from all perspective at the very start of the design phase when the physical dimensions of the application board are under analysis/decision, since the RF compliance of the device integrating SARA-R4/N4 series modules with all the applicable required certification schemes depends on antennas radiating performance. Cellular antennas are typically available as:

External antennas (e.g. linear monopole):

o External antennas basically do not imply physical restriction to the design of the PCB where the SARA-R4/N4 series module is mounted. o The radiation performance mainly depends on the antennas. It is required to select antennas with optimal radiating performance in the operating bands. o RF cables should be carefully selected to have minimum insertion losses. Additional insertion loss will be introduced by low quality or long cable. Large insertion loss reduces both transmit and receive radiation performance. o A high quality 50 RF connector provides a clean PCB-to-RF-cable transition. It is recommended to strictly follow the layout and cable termination guidelines provided by the connector manufacturer. Integrated antennas (e.g. PCB antennas such as patches or ceramic SMT elements):

o Internal integrated antennas imply physical restriction to the design of the PCB: Integrated antenna excites RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna: its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that needs to be radiated, given that the orientation of the ground plane relative to the antenna element must be considered. As numerical example, the physical restriction to the PCB design can be considered as following:

Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm o Radiation performance depends on the whole PCB and antenna system design, including product mechanical design and usage. Antennas should be selected with optimal radiating performance in the operating bands according to the mechanical specifications of the PCB and the whole product. UBX-16029218 - R11 Design-in Page 79 of 157 SARA-R4/N4 series - System Integration Manual o It is recommended to select a custom antenna designed by an antennas manufacturer if the required ground plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm wide). The antenna design process should begin at the start of the whole product design process o It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and matching circuitry o Further to the custom PCB and product restrictions, antennas may require tuning to obtain the required performance for compliance with all the applicable required certification schemes. It is recommended to consult the antenna manufacturer for the design-in guidelines for antenna matching relative to the custom application In both of cases, selecting external or internal antennas, these recommendations should be observed:

Select an antenna providing optimal return loss (or VSWR) figure over all the operating frequencies. Select an antenna providing optimal efficiency figure over all the operating frequencies. Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified in some countries (e.g. by FCC in the United States, as reported in the section 4.2.2). 2.4.1.2 Guidelines for antenna RF interface design Guidelines for ANT pin RF connection design A clean transition between the ANT pad and the application board PCB must be provided, implementing the following design-in guidelines for the layout of the application PCB close to the ANT pad:

On a multilayer board, the whole layer stack below the RF connection should be free of digital lines Increase GND keep-out (i.e. clearance, a void area) around the ANT pad, on the top layer of the application PCB, to at least 250 m up to adjacent pads metal definition and up to 400 m on the area below the module, to reduce parasitic capacitance to ground, as described in the left picture in Figure 31 Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT pad if the top-

layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground, as described in the right picture in Figure 31 UBX-16029218 - R11 Design-in Page 80 of 157 SARA-R4/N4 series - System Integration Manual Figure 31: GND keep-out area on top layer around ANT pad and on very close buried layer below ANT pad Guidelines for RF transmission line design Any RF transmission line, such as the ones from the ANT pad up to the related antenna connector or up to the related internal antenna pad, must be designed so that the characteristic impedance is as close as possible to 50 . RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is sandwiched between two parallel ground planes within a dielectric material). The micro strip, implemented as a coplanar waveguide, is the most common configuration for printed circuit board. Figure 32 and Figure 33 provide two examples of suitable 50 coplanar waveguide designs. The first example of RF transmission line can be implemented in case of 4-layer PCB stack-up herein described, and the second example of RF transmission line can be implemented in case of 2-layer PCB stack-up herein described. Figure 32: Example of 50 coplanar waveguide transmission line design for the described 4-layer board layup UBX-16029218 - R11 Design-in Page 81 of 157 Min. 250 mMin. 400 mGNDANTGND clearance on buried layer very close to top layerbelow ANT padGND clearance on top layer around ANT pad35 m35 m35 m35 m270 m270 m760 mL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric380 m500 m500 m SARA-R4/N4 series - System Integration Manual Figure 33: Example of 50 coplanar waveguide transmission line design for the described 2-layer board layup If the two examples do not match the application PCB stack-up, then the 50 characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation, or using freeware tools like Avago / Broadcom AppCAD

(https://www.broadcom.com/appcad) taking care of the approximation formulas used by the tools for the impedance computation. To achieve a 50 characteristic impedance, the width of the transmission line must be chosen depending on:

the thickness of the transmission line itself (e.g. 35 m in the example of Figure 32 and Figure 33) the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner closer layer implementing the ground plane (e.g. 270 m in Figure 32, 1510 m in Figure 33) the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 32 and Figure 33) the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g. 500 m in Figure 32, 400 m in Figure 33) If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the Coplanar Waveguide model for the 50 calculation. Additionally to the 50 impedance, the following guidelines are recommended for transmission lines design:

Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB, Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component present on the RF transmission lines, if top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground, The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible:

avoid abrupt changes of width and spacing to GND, Add GND stitching vias around transmission lines, as described in Figure 34, UBX-16029218 - R11 Design-in Page 82 of 157 35 m35 m1510 mL2 CopperL1 CopperFR-4 dielectric1200 m400 m400 m SARA-R4/N4 series - System Integration Manual Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer, providing enough vias on the adjacent metal layer, as described in Figure 34, Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive circuit (as USB), Avoid stubs on the transmission lines, Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried metal layer, Do not route microstrip lines below discrete component or other mechanics placed on top layer Two examples of a suitable RF circuit design are illustrated in Figure 34, where the antenna detection circuit is not implemented (if the antenna detection function is required by the application, follow the guidelines for circuit and layout implementation detailed in section 2.4.2):

In the first example shown on the left, the ANT pin is directly connected to an SMA connector by means of a suitable 50 transmission line, designed with the appropriate layout. In the second example shown on the right, the ANT pin is connected to an SMA connector by means of a suitable 50 transmission line, designed with the appropriate layout, with an additional high pass filter to improve the ESD immunity at the antenna port. (The filter consists of a suitable series capacitor and shunt inductor, for example the Murata GRM1555C1H150JA01 15 pF capacitor and the Murata LQG15HN39NJ02 39 nH inductor with Self-Resonant Frequency ~1 GHz.). Figure 34: Example of circuit and layout for antenna RF circuits on the application board Guidelines for RF termination design The RF termination must provide a characteristic impedance of 50 as well as the RF transmission line up to the RF termination, to match the characteristic impedance of the ANT port. UBX-16029218 - R11 Design-in Page 83 of 157 SARA moduleSMAconnectorSARA moduleSMAconnectorHigh-pass filter to improveESD immunity SARA-R4/N4 series - System Integration Manual However, real antennas do not have a perfect 50 load on all the supported frequency bands. So to reduce as much as possible any performance degradation due to antenna mismatching, the RF termination must provide optimal return loss (or VSWR) figures over all the operating frequencies, as summarized in Table 7. If an external antenna is used, the antenna connector represents the RF termination on the PCB:

Use suitable a 50 connector providing a clean PCB-to-RF-cable transition. Strictly follow the connector manufacturers recommended layout, for example:

o SMA Pin-Through-Hole connectors require a GND keep-out (i.e. clearance, a void area) on all the layers around the central pin up to the annular pads of the four GND posts, as shown in Figure 34 o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in the area below the connector between the GND land pads. Cut out the GND layer under the RF connector and close to any buried vias, to remove stray capacitance and thus keep the RF line at 50 , e.g. the active pad of UFL connector needs to have a GND keep-out

(i.e. clearance, a void area) at least on the first inner layer to reduce parasitic capacitance to ground. If an integrated antenna is used, the integrated antenna represents the RF terminations. The following guidelines should be followed:

Use an antenna designed by an antenna manufacturer providing the best possible return loss (or VSWR). Provide a ground plane large enough according to the relative integrated antenna requirements. The ground plane of the application PCB can be reduced down to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that needs to be radiated. As numerical example, Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including the PCB layout and matching circuitry. Further to the custom PCB and product restrictions, the antenna may require a tuning to comply with all the applicable required certification schemes. It is recommended to consult the antenna manufacturer for the design-in guidelines for the antenna matching relative to the custom application. Additionally, these recommendations regarding the antenna system placement must be followed:

Do not place the antenna within a closed metal case. Do not place the antenna in close vicinity to the end user since the emitted radiation in human tissue is restricted by regulatory requirements. Place the antenna as far as possible from VCC supply line and related parts (refer to Figure 28), from high speed digital lines (as USB) and from any possible noise source. Place the antenna far from sensitive analog systems or employ countermeasures to reduce EMC or EMI issues. Be aware of interaction between co-located RF systems since the LTE transmitted power may interact or disturb the performance of companion systems. UBX-16029218 - R11 Design-in Page 84 of 157 SARA-R4/N4 series - System Integration Manual UBX-16029218 - R11 Design-in Page 85 of 157 SARA-R4/N4 series - System Integration Manual Examples of antennas Table 22 lists some examples of possible internal on-board surface-mount antennas. Manufacturer Part Number Product Name Description Taoglas PA.710.A Warrior GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm Taoglas PCS.06.A Havok GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2690 MHz 42.0 x 10.0 x 3.0 mm Taoglas MCS6.A GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2690 MHz 42.0 x 10.0 x 3.0 mm Antenova SR4L002 Lucida GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz Ethertronics P822601 Ethertronics P822602 Ethertronics 1002436 35.0 x 8.5 x 3.2 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE Vertical Mount Antenna 698..960 MHz, 1710..2700 MHz 50.6 x 19.6 x 1.6 mm Pulse W3796 Domino GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz 42.0 x 10.0 x 3.0 mm GSM / WCDMA / LTE Vertical Mount Antenna 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 74.0 x 10.6 x 1.6 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1700..2700 MHz 40.0 x 5.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2700 MHz 37.0 x 5.0 x 5.0 mm TE Connectivity 2118310-1 Molex 1462000001 Cirocomm DPAN0S07 Table 22: Examples of internal surface-mount antennas UBX-16029218 - R11 Design-in Page 86 of 157 SARA-R4/N4 series - System Integration Manual Table 23 lists some examples of possible internal off-board PCB-type antennas with cable and connector. Manufacturer Part Number Product Name Description Taoglas FXUB63.07.0150C GSM / WCDMA / LTE PCB Antenna with cable and U.FL 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz 96.0 x 21.0 mm Taoglas FXUB66.07.0150C Maximus GSM / WCDMA / LTE PCB Antenna with cable and U.FL 698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz, 3400..3600 MHz, 4800..6000 MHz 120.2 x 50.4 mm Antenova SRFL029 Moseni GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm Antenova SRFL026 Mitis GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm Ethertronics 1002289 GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 698..960 MHz, 1710..2700 MHz 140.0 x 75.0 mm EAD FSQS35241-UF-10 SQ7 GSM / WCDMA / LTE PCB Antenna with cable and U.FL 690..960 MHz, 1710..2170 MHz, 2500..2700 MHz 110.0 x 21.0 mm Table 23: Examples of internal antennas with cable and connector Table 24 lists some examples of possible external antennas. Manufacturer Part Number Product Name Description Taoglas GSA.8827.A.101111 Phoenix GSM / WCDMA / LTE adhesive-mount antenna with cable and SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz 105 x 30 x 7.7 mm Taoglas TG.30.8112 GSM / WCDMA / LTE swivel dipole antenna with SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz 148.6 x 49 x 10 mm Taoglas MA241.BI.001 Genesis GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination antenna waterproof IP67 rated with cable and SMA(M) 698..960 MHz, 1710..2170 MHz, 2400..2700 MHz 205.8 x 58 x 12.4 mm Laird Tech. TRA6927M3PW-001 GSM / WCDMA / LTE screw-mount antenna with N-type(F) 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 83.8 x 36.5 mm Laird Tech. CMS69273 GSM / WCDMA / LTE ceiling-mount antenna with cable and N-type(F) 698..960 MHz, 1575.42 MHz, 1710..2700 MHz UBX-16029218 - R11 Design-in Page 87 of 157 SARA-R4/N4 series - System Integration Manual Manufacturer Part Number Product Name Description 86 x 199 mm Laird Tech. OC69271-FNM GSM / WCDMA / LTE pole-mount antenna with N-type(M) 698..960 MHz, 1710..2690 MHz 248 x 24.5 mm Pulse WA700/2700SMA GSM / WCDMA / LTE clip-mount MIMO antenna with cables and SMA(M) Electronics 698..960 MHz,1710..2700 MHz 149 x 127 x 5.1 mm Table 24: Examples of external antennas 2.4.2 Antenna detection interface (ANT_DET) 2.4.2.1 Guidelines for ANT_DET circuit design Figure 35 and Table 25 describe the recommended schematic / components for the antenna detection circuit that must be provided on the application board and for the diagnostic circuit that must be provided on the antennas assembly to achieve antenna detection functionality. Figure 35: Suggested schematic for antenna detection circuit on application PCB and diagnostic circuit on antenna assembly Reference Description Part Number - Manufacturer C1 C2 D1 L1 R1 J1 C3 L2 C4 L3 27 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H270J - Murata 33 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H330J - Murata Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HS68NJ02 - Murata 10 k Resistor 0402 1% 0.063 W RK73H1ETTP1002F - KOA Speer SMA Connector 50 Through Hole Jack SMA6251A1-3GT50G-50 - Amphenol 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150J - Murata 39 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HN39NJ02 - Murata 22 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1H220J - Murata 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HS68NJ02 - Murata UBX-16029218 - R11 Design-in Page 88 of 157 Application BoardAntenna CableSARA-R4/N456ANT62ANT_DETR1C1D1L1C2J1Z0= 50 Z0= 50 Z0= 50 ohmAntenna AssemblyR2C4L3Radiating ElementDiagnostic CircuitGNDL2C3 SARA-R4/N4 series - System Integration Manual R2 15 k Resistor for Diagnostics Various Manufacturers Table 25: Suggested parts for antenna detection circuit on application PCB and diagnostic circuit on antennas assembly The antenna detection circuit and diagnostic circuit suggested in Figure 35 and Table 25 are here explained:

When antenna detection is forced by the +UANTR AT command, the ANT_DET pin generates a DC current measuring the resistance (R2) from the antenna connector (J1) provided on the application board to GND. DC blocking capacitors are needed at the ANT pin (C2) and at the antenna radiating element (C4) to decouple the DC current generated by the ANT_DET pin. Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series at the ANT_DET pin (L1) and in series at the diagnostic resistor (L3), to avoid a reduction of the RF performance of the system, improving the RF isolation of the load resistor. Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR AT command. It also acts as an ESD protection. Additional components (C1 and D1 in Figure 35) are needed at the ANT_DET pin as ESD protection. Additional high pass filter (C3 and L2 in Figure 35) is provided at the ANT pin as ESD immunity improvement The ANT pin must be connected to the antenna connector by means of a transmission line with nominal characteristics impedance as close as possible to 50 . The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 35, the measured DC resistance is always at the limits of the measurement range (respectively open or short), and there is no mean to distinguish between a defect on antenna path with similar characteristics (respectively:

removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example:

Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports the resistance value evaluated from the antenna connector provided on the application board to GND:

UBX-16029218 - R11 Design-in Page 89 of 157 SARA-R4/N4 series - System Integration Manual Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is correctly connected. Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit over range report (see the SARA-R4/N4 series AT Commands Manual [2]) means that that the antenna is not connected or the RF cable is broken. Reported values below the measurement range minimum limit (1 k) highlights a short to GND at antenna or along the RF cable. Measurement inside the valid measurement range and outside the expected range may indicate an unclean connection, a damaged antenna or incorrect value of the antenna load resistor for diagnostics. Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method. If the antenna detection function is not required by the customer application, the ANT_DET pin can be left not connected and the ANT pin can be directly connected to the antenna connector by means of a 50 transmission line as described in Figure 34. UBX-16029218 - R11 Design-in Page 90 of 157 SARA-R4/N4 series - System Integration Manual 2.4.2.2 Guidelines for ANT_DET layout design Figure 36 describes the recommended layout for the antenna detection circuit to be provided on the application board to achieve antenna detection functionality, implementing the recommended schematic described in the previous Figure 35 and Table 25:

The ANT pin must be connected to the antenna connector by means of a 50 transmission line, implementing the design guidelines described in section 2.4.1 and the recommendations of the SMA connector manufacturer. DC blocking capacitor at ANT pin (C2) must be placed in series to the 50 RF line. The ANT_DET pin must be connected to the 50 transmission line by means of a sense line. Choke inductor in series at the ANT_DET pin (L1) must be placed so that one pad is on the 50 transmission line and the other pad represents the start of the sense line to the ANT_DET pin. The additional components (R1, C1 and D1) on the ANT_DET line must be placed as ESD protection. The additional high pass filter (C3 and L2) on the ANT line are placed as ESD immunity improvement Figure 36: Suggested layout for antenna detection circuit on application board UBX-16029218 - R11 Design-in Page 91 of 157 SARA moduleC2R1D1C1L1J1C3L2 SARA-R4/N4 series - System Integration Manual 2.5 SIM interface 2.5.1 Guidelines for SIM circuit design 2.5.1.1 Guidelines for SIM cards, SIM connectors and SIM chips selection The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical and functional characteristics of Universal Integrated Circuit Cards (UICC), which contains the Subscriber Identification Module (SIM) integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the LTE network. Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as follows:

Contact C1 = VCC (Supply) Contact C2 = RST (Reset) Contact C3 = CLK (Clock) Contact C4 = AUX1 (Auxiliary contact) Contact C5 = GND (Ground) It must be connected to VSIM It must be connected to SIM_RST It must be connected to SIM_CLK It must be left not connected It must be connected to GND Contact C6 = VPP (Programming supply) It can be left not connected Contact C7 = I/O (Data input/output) Contact C8 = AUX2 (Auxiliary contact) It must be connected to SIM_IO It must be left not connected A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the auxiliary contacts C4 and C8. Only 6 contacts are required and must be connected to the module SIM interface. Removable SIM cards are suitable for applications requiring a change of SIM card during the product lifetime. A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided. Select a SIM connector providing 6+2 or 8+2 positions if the optional SIM detection feature is required by the custom application, otherwise a connector without integrated mechanical presence switch can be selected. Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as:

Case Pin 8 = UICC Contact C1 = VCC (Supply) Case Pin 7 = UICC Contact C2 = RST (Reset) Case Pin 6 = UICC Contact C3 = CLK (Clock) It must be connected to VSIM It must be connected to SIM_RST It must be connected to SIM_CLK Case Pin 5 = UICC Contact C4 = AUX1 (Aux.contact) It must be left not connected Case Pin 1 = UICC Contact C5 = GND (Ground) It must be connected to GND Case Pin 2 = UICC Contact C6 = VPP (Progr. supply) It can be left not connected Case Pin 3 = UICC Contact C7 = I/O (Data I/O) It must be connected to SIM_IO Case Pin 4 = UICC Contact C8 = AUX2 (Aux. contact) It must be left not connected UBX-16029218 - R11 Design-in Page 92 of 157 SARA-R4/N4 series - System Integration Manual A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other uses, but only 6 contacts are required and must be connected to the module SIM card interface as described above. Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed. 2.5.1.2 Guidelines for single SIM card connection without detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of SARA-

R4/N4 series modules as described in Figure 37, where the optional SIM detection feature is not implemented. Follow these guidelines to connect the module to a SIM connector without SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the relative pad of the SIM connector, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder. Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on each externally accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity rating of the SIM interface pins is 1 kV (HBM). So that, according to EMC/ESD requirements of the custom application, higher protection level can be required if the lines are externally accessible on the application device. Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum allowed rise time on clock line, 1.0 s is the maximum allowed rise time on data and reset lines). UBX-16029218 - R11 Design-in Page 93 of 157 SARA-R4/N4 series - System Integration Manual Figure 37: Application circuits for the connection to a single removable SIM card, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2, D3, D4 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics J1 SIM Card Holder, 6 p, without card presence Various manufacturers, as C707 10M006 136 2 - Amphenol switch Table 26: Example of components for the connection to a single removable SIM card, with SIM detection not implemented UBX-16029218 - R11 Design-in Page 94 of 157 SARA-R4/N441VSIM39SIM_IO38SIM_CLK40SIM_RSTSIM CARD HOLDERC5C6C7C1C2C3SIM Card Bottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5J1C4D1D2D3D4C8C4 SARA-R4/N4 series - System Integration Manual 2.5.1.3 Guidelines for single SIM chip connection A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of the SARA-

R4/N4 series modules as described in Figure 38. Follow these guidelines to connect the module to a solderable SIM chip without SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the relative pad of the SIM chip, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM lines. Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum allowed rise time on clock line, 1.0 s is the maximum allowed rise time on data and reset lines). Figure 38: Application circuits for the connection to a single solderable SIM chip, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata SIM chip (M2M UICC Form Factor) Various Manufacturers Table 27: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented 2.5.1.4 Guidelines for single SIM card connection with detection An application circuit for the connection to a single removable SIM card placed in a SIM card holder is described in Figure 39, where the optional SIM card detection feature is implemented. UBX-16029218 - R11 Design-in Page 95 of 157 SARA-R4/N441VSIM39SIM_IO38SIM_CLK40SIM_RSTSIM CHIPSIM ChipBottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5U1C4283671C1C5C2C6C3C7C4C887651234 SARA-R4/N4 series - System Integration Manual Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Connect one pin of the normally-open mechanical switch integrated in the SIM connector (as the SW2 pin in Figure 39) to the GPIO5 input pin, providing a weak pull-down resistor (e.g. 470 k, as R2 in Figure 39). Connect the other pin of the normally-open mechanical switch integrated in the SIM connector (SW1 pin in Figure 39) to V_INT 1.8 V supply output by means of a strong pull-up resistor (e.g. 1 k, as R1 in Figure 39) Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related pad of the SIM connector, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line

(VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder. Provide a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each related pad of the SIM connector. The ESD sensitivity rating of SIM interface pins is 1 kV (HBM according to JESD22-A114), so that, according to the EMC/ESD requirements of the custom application, higher protection level can be required if the lines are externally accessible. Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface (18.7 ns = maximum rise time on SIM_CLK, 1.0 s = maximum rise time on SIM_IO and SIM_RST). Figure 39: Application circuit for the connection to a single removable SIM card, with SIM detection implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata UBX-16029218 - R11 Design-in Page 96 of 157 SARA-R4/N441VSIM39SIM_IO38SIM_CLK40SIM_RST4V_INT42GPIO5SIM CARD HOLDERC5C6C7C1C2C3SIM Card Bottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5J1C4SW1SW2D1D2D3D4D5D6R2R1C8C4TP SARA-R4/N4 series - System Integration Manual C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1 D6 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics R1 R2 J1 1 k Resistor 0402 5% 0.1 W RC0402JR-071KL - Yageo Phycomp 470 k Resistor 0402 5% 0.1 W RC0402JR-07470KL- Yageo Phycomp SIM Card Holder Various Manufacturers, 6 + 2 positions, with card presence switch CCM03-3013LFT R102 - C&K Components Table 28: Example of components for the connection to a single removable SIM card, with SIM detection implemented 2.5.2 Guidelines for SIM layout design The layout of the SIM card interface lines (VSIM, SIM_CLK, SIM_IO, SIM_RST may be critical if the SIM card is placed far away from the SARA-R4/N4 series modules or in close proximity to the RF antenna: these two cases should be avoided or at least mitigated as described below. In the first case, the long connection can cause the radiation of some harmonics of the digital data frequency as any other digital interface. It is recommended to keep the traces short and avoid coupling with RF line or sensitive analog inputs. In the second case, the same harmonics can be picked up and create self-interference that can reduce the sensitivity of LTE receiver channels whose carrier frequency is coincidental with harmonic frequencies. It is strongly recommended to place the RF bypass capacitors suggested in Figure 37 near the SIM connector. In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges. Add adequate ESD protection as suggested to protect module SIM pins near the SIM connector. Limit capacitance and series resistance on each SIM signal to match the SIM specifications. The connections should always be kept as short as possible. Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some harmonics of the digital data frequency. UBX-16029218 - R11 Design-in Page 97 of 157 SARA-R4/N4 series - System Integration Manual 2.6 Data communication interfaces 2.6.1 UART interface 2.6.1.1 Guidelines for UART circuit design Providing the full RS-232 functionality (using the complete V.24 link)12 If RS-232 compatible signal levels are needed, two different external voltage translators can be used to provide full RS-232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for the translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the translation from 3.3 V to RS-232 compatible signal level. If a 1.8 V Application Processor (DTE) is used and complete RS-232 functionality is required, then the complete 1.8 V UART of the module (DCE) should be connected to a 1.8 V DTE, as in Figure 40. Figure 40: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 41. Figure 41: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) 12 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input must be set low to have URCs presented over UART on 00, 01 and x2 product versions. UBX-16029218 - R11 Design-in Page 98 of 157 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TP0TP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2B3A3VCCBVCCAUnidirectionalVoltage TranslatorC3C43V0DIR1DIR3OEB2 A2B4A4DIR4DIR2TP0TP0TP0TP0TP SARA-R4/N4 series - System Integration Manual Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1, U2 Unidirectional Voltage Translator SN74AVC4T77413 - Texas Instruments Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Providing the TXD, RXD, RTS, CTS and DTR lines only 14 If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available:

Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to RS-232 compatible signal level. Figure 42 describes the circuit that should be implemented as if a 1.8 V Application Processor (DTE) is used, given that the DTE will behave correctly regardless of the DSR input setting. Figure 42: UART interface application circuit with partial V.24 link (6-wire) in the DTE/DCE serial communication (1.8 V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 43, given that the DTE will behave correctly regardless of the DSR input setting. 13 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply 14 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input must be set low to have URCs presented over UART on 00, 01 and x2 product versions. UBX-16029218 - R11 Design-in Page 99 of 157 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0 0 TPTP0 0 TPTP SARA-R4/N4 series - System Integration Manual Figure 43: UART interface application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1 U2 Unidirectional Voltage Translator SN74AVC4T77415 - Texas Instruments Unidirectional Voltage Translator SN74AVC2T24515 - Texas Instruments Table 30: UART application circuit components with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) Providing the TXD, RXD, RTS and CTS lines only 16 If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:

Connect the module DTR input to GND using a 0 series resistor, since it may be useful to set DTR active if not specifically handled, in particular to have URCs presented over the UART interface (see the SARA-R4/N4 series AT Commands Manual [1] for the &D, S0, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor is used, the circuit should be implemented as described in Figure 44. 15 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply 16 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input must be set low to have URCs presented over UART on 00, 01 and x2 product versions. UBX-16029218 - R11 Design-in Page 100 of 157 4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2VCCBVCCAUnidirectionalVoltage TranslatorC33V0DIR1OEB2 A2DIR2C4 SARA-R4/N4 series - System Integration Manual Figure 44: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as in Figure 45. Figure 45: UART interface application circuit with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T77417 - Texas Instruments Table 31: UART application circuit components with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) 17 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply UBX-16029218 - R11 Design-in Page 101 of 157 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TP0TP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR4TP0TP0TP0TPTP SARA-R4/N4 series - System Integration Manual Providing the TXD and RXD lines only 18 If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, then:

Connect the module RTS input line to GND or to the CTS output line of the module, since the module requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, which is the default setting) Connect the module DTR input line to GND using a 0 series resistor, because it is useful to set DTR active if not specifically handled, in particular to have URCs presented over the UART interface (see SARA-R4/N4 series AT Commands Manual [1], &D, S0, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor (DTE) is used, the circuit that should be implemented as in Figure 46. Figure 46: UART interface application circuit with a 3-wire link in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as in Figure 47. 18 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input must be set low to have URCs presented over UART on 00, 01 and x2 product versions. UBX-16029218 - R11 Design-in Page 102 of 157 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TPTP SARA-R4/N4 series - System Integration Manual Figure 47: UART interface application circuit with a partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC2T24519 - Texas Instruments Table 32: UART application circuit components with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) 19 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply UBX-16029218 - R11 Design-in Page 103 of 157 4V_INTTxDApplication Processor(3.0V DTE)RxDDTRDSRRIDCDGNDSARA-R4/N4(1.8V DCE)12TXD9DTR13RXD6DSR7RI8DCDGND1V8B1 A1GNDU1VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR1DIR2OEVCCB2 A2RTSCTS10RTS11CTSTP0TP0TP0TPTP SARA-R4/N4 series - System Integration Manual Additional considerations If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low-cost solution, by means of an appropriate voltage divider. Consider the value of the pull-down / pull-up integrated at the input of the module (DCE) for the correct selection of the voltage divider resistance values. Make sure that any DTE signal connected to the module is tri-stated or set low when the module is in power-down mode and during the module power-on sequence (at least until the activation of the V_INT supply output of the module), to avoid latch-up of circuits and allow a clean boot of the module (see the remark below). Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding 3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate low-cost non-

inverting buffer with open drain output. The non-inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for the appropriate selection of the resistance value for the external pull-up biased by the application processor supply rail. The TXD data input line has an internal active pull-down enabled on the 00 and 02 product versions, and an internal active pull-up enabled on the 01 product version. Do not apply voltage to any UART interface pin before the switch-on of the UART supply source (V_INT), o avoid latch-up of circuits and allow a clean boot of the module. If the external signals connected to the cellular module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on. ESD sensitivity rating of the UART interface pins is 1 kV (Human Body Model according to JESD22-

A114). Higher protection levels could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points. 2.6.1.2 Guidelines for UART layout design The UART serial interface requires the same consideration regarding electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. UBX-16029218 - R11 Design-in Page 104 of 157 SARA-R4/N4 series - System Integration Manual 2.6.2 USB interface 2.6.2.1 Guidelines for USB circuit design The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer. USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.0 specification [4] are part of the module USB pins driver and do not need to be externally provided. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the SARA-R4/N4 series Data Sheet [1]). Neither the USB interface nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. Routing the USB pins to a connector, they will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device with very low capacitance should be provided close to accessible point on the line connected to this pin, as described in Figure 48 and Table 33. The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points. The USB pins of the modules can be directly connected to the USB host application processor without additional ESD protections if they are not externally accessible or according to EMC/ESD requirements. Figure 48: USB Interface application circuits Reference Description Part Number - Manufacturer C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics Table 33: Components for USB application circuits UBX-16029218 - R11 Design-in Page 105 of 157 D+D-GND29USB_D+28USB_D-GNDUSB DEVICE CONNECTORVBUSD+D-GND29USB_D+28USB_D-GNDUSB HOST PROCESSORSARA-R4/N4SARA-R4/N4VBUS17VUSB_DET17VUSB_DETD1D2D3C1C10Test-Point0Test-Point0Test-Point SARA-R4/N4 series - System Integration Manual If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode defined in 3GPP Rel.13. If the USB interface pins are not used, they can be left unconnected on the application board, but it is strongly recommended to provide accessible test points directly connected to the USB interface pins

(VUSB_DET, USB_D+, USB_D-). 2.6.2.2 Guidelines for USB layout design The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to 480 Mb/s) supported by the USB serial interface. The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0 specification [4]. The most important parameter is the differential characteristic impedance applicable for the odd-mode electromagnetic field, which should be as close as possible to 90 differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Use the following general routing guidelines to minimize signal quality problems:

Route USB_D+ / USB_D- lines as a differential pair Route USB_D+ / USB_D- lines as short as possible Ensure the differential characteristic impedance (Z0) is as close as possible to 90 Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30 Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area Figure 49 and Figure 50 provide two examples of coplanar waveguide designs with differential characteristic impedance close to 90 and common mode characteristic impedance close to 30 . The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB stack-up herein described. Figure 49: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 4-layer board layup UBX-16029218 - R11 Design-in Page 106 of 157 35 m35 m35 m35 m270 m270 m760 mL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric350 m400 m400 m350 m400 m SARA-R4/N4 series - System Integration Manual Figure 50: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 2-layer board layup 2.6.3 SPI interface 2.6.3.1 Guidelines for SPI circuit design The SPI interface is not supported by 00, 01, 02 and 52 product versions: the SPI interface pins should not be driven by any external device. 2.6.4 SDIO interface 2.6.4.1 Guidelines for SDIO circuit design The SDIO interface is not supported by 00, 01, 02 and 52 product versions: the SDIO interface pins should not be driven by any external device. 2.6.5 DDC (I2C) interface 2.6.5.1 Guidelines for DDC (I2C) circuit design DDC (I2C) interface is not supported by 00 and 01 product versions: the DDC (I2C) interface pins should not be driven by any external device. The DDC I2C-bus master interface can be used to communicate with u-blox GNSS receivers and other external I2C-bus slaves as an audio codec. The SDA and SCL pins of the module are open drain output as per I2C bus specifications [9], and they have internal pull-up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of additional pull-up resistors on the external application board. UBX-16029218 - R11 Design-in Page 107 of 157 35 m35 m1510 mL2 CopperL1 CopperFR-4 dielectric740 m410 m410 m740 m410 m SARA-R4/N4 series - System Integration Manual Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 s is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. ESD sensitivity rating of the DDC (I2C) pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the pins are not used as DDC bus interface, they can be left unconnected. UBX-16029218 - R11 Design-in Page 108 of 157 SARA-R4/N4 series - System Integration Manual Connection with u-blox 1.8 V GNSS receivers Figure 51 shows an application circuit for connecting the cellular module to a u-blox 1.8 V GNSS receiver:

The SDA and SCL pins of the cellular module are directly connected to the related pins of the u-blox 1.8 V GNSS receiver. External pull-up resistors are not needed, as they are already integrated in the cellular module. The GPIO2 pin is connected to the active-high enable pin of the voltage regulator that supplies the u-

blox 1.8 V GNSS receiver providing the GNSS supply enable function. A pull-down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. The GPIO3 pin is connected to the TXD1 pin of the u-blox 1.8 V GNSS receiver providing the additional GNSS Tx data ready function. Figure 51: Application circuit for connecting SARA-R4/N4 series modules to u-blox 1.8 V GNSS receivers Reference Description Part Number - Manufacturer R1 U1 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual Table 34: Components for connecting SARA-R4/N4 series modules to u-blox 1.8 V GNSS receivers For additional guidelines regarding the design of applications with u-blox 1.8 V GNSS receivers, see the Hardware Integration Manual of the u-blox GNSS receivers. Connection with u-blox 3.0 V GNSS receivers Figure 52 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS receiver:

As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the related I2C pins of the u-blox 3.0 V GNSS receiver must be provided using a suitable I2C-bus Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down feature so that UBX-16029218 - R11 Design-in Page 109 of 157 INOUTGNDGNSS LDORegulatorSHDNu-blox GNSS1.8 V receiverSDA2SCL2VMAIN1V8U123GPIO2SDASCLC12627VCCR1GNSS supply enabledSARA-R4/N4(except 00,01 versions)TxD1GPIO324GNSS data ready SARA-R4/N4 series - System Integration Manual the GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular supply). External pull-up resistors are not needed on the cellular module side, as they are already integrated in the cellular module. The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 3.0 V GNSS receiver providing the GNSS supply enable function. A pull-down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. The GPIO3 pin is connected to the TXD1 pin of the u-blox 3.0 V GNSS receiver providing the additional GNSS Tx data ready function, using a suitable Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up before the V_INT 1.8 V cellular supply. Figure 52: Application circuit for connecting SARA-R4/N4 series modules to u-blox 3.0 V GNSS receivers Reference Description Part Number - Manufacturer R1, R2 R3 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1, C1 Voltage Regulator for GNSS receiver and related See GNSS receiver Hardware Integration Manual output bypass capacitor U2 U3 I2C-bus Bidirectional Voltage Translator TCA9406DCUR - Texas Instruments Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 35: Components for connecting SARA-R4/N4 series modules to u-blox 3.0 V GNSS receivers For additional guidelines regarding the design of applications with u-blox 3.0 V GNSS receivers see the Hardware Integration Manual of the u-blox GNSS receivers. UBX-16029218 - R11 Design-in Page 110 of 157 u-blox GNSS 3.0 V receiver24GPIO31V8B1 A1GNDU3B2A2VCCBVCCAUnidirectionalVoltage TranslatorC4C53V0TxD1R1INOUTLDO RegulatorSHDNnR2VMAIN3V0U123GPIO226SDA27SCL1V8SDA_A SDA_BGNDU2SCL_ASCL_BVCCAVCCBI2C-bus Bidirectional Voltage Translator4V_INTC1C2C3R3SDA2SCL2VCCDIR1DIR2OEnOEGNSS data readyGNSS supply enabledGNDSARA-R4/N4(except 00,01 versions) SARA-R4/N4 series - System Integration Manual 2.6.5.2 Guidelines for DDC (I2C) layout design The DDC (I2C) serial interface requires the same consideration regarding electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. 2.7 Audio 2.7.1 Guidelines for Audio circuit design Audio is not supported by 00, 01, 02 and 52 product versions: the I2S interface pins should not be driven by any external device. 2.8 General Purpose Input/Output 2.8.1 Guidelines for GPIO circuit design A typical usage of SARA-R4/N4 series modules GPIOs can be the following:

Network indication provided over GPIO1 pin (see Figure 53 / Table 36 below) GNSS supply enable function provided by the GPIO2 pin (see section 2.6.5) GNSS Tx data ready function provided by the GPIO3 pin (see section 2.6.5) Module operating status indication provided by a GPIO pin (see section 1.6.1) SIM card detection provided over GPIO5 pin (see Figure 39 / Table 28 in section 2.5) Figure 53: Application circuit for network indication provided over GPIO1 Reference Description Part Number - Manufacturer R1 R2 R3 DL1 T1 10 k Resistor 0402 5% 0.1 W Various manufacturers 47 k Resistor 0402 5% 0.1 W Various manufacturers 820 Resistor 0402 5% 0.1 W Various manufacturers LED Red SMT 0603 NPN BJT Transistor LTST-C190KRKT - Lite-on Technology Corporation BC847 - Infineon Table 36: Components for network indication application circuit UBX-16029218 - R11 Design-in Page 111 of 157 SARA-R4/N4GPIO1R1R33V8Network IndicatorR216DL1T1 SARA-R4/N4 series - System Integration Manual Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO of SARA-R4/N4 series modules. Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (V_INT), to avoid latch-up of circuits and allow a clean module boot. If the external signals connected to the module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on. ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the GPIO pins are not used, they can be left unconnected on the application board. 2.8.2 Guidelines for general purpose input/output layout design The general purpose inputs / outputs pins are generally not critical for layout. UBX-16029218 - R11 Design-in Page 112 of 157 SARA-R4/N4 series - System Integration Manual 2.9 Reserved pins (RSVD) SARA-R4/N4 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be externally connected to ground. 2.10 Module placement An optimized placement allows a minimum RF lines length and closer path from DC source for VCC. Make sure that the module, analog parts and RF circuits are clearly separated from any possible source of radiated energy. In particular, digital circuits can radiate digital frequency harmonics, which can produce Electro-Magnetic Interference that affects the module, analog parts and RF circuits performance. Implement suitable countermeasures to avoid any possible Electro-Magnetic Compatibility issue. Make sure that the module, RF and analog parts / circuits, and high speed digital circuits are clearly separated from any sensitive part / circuit which may be affected by Electro-Magnetic Interference, or employ countermeasures to avoid any possible Electro-Magnetic Compatibility issue. Make sure that the module is placed in order to keep the antenna as far as possible from VCC supply line and related parts (refer to Figure 28), from high speed digital lines (as USB) and from any possible noise source. Provide enough clearance between the module and any external part: clearance of at least 0.4 mm per side is recommended to let suitable mounting of the parts. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the SARA-R4/N4 series modules: avoid placing temperature sensitive devices close to the module. UBX-16029218 - R11 Design-in Page 113 of 157 SARA-R4/N4 series - System Integration Manual 2.11 Module footprint and paste mask Figure 54 and Table 37 describe the suggested footprint (i.e. copper mask) and paste mask layout for SARA modules: the proposed land pattern layout reflects the modules pins layout, while the proposed stencil apertures layout is slightly different (see the F, H, I, J, O parameters compared to the F, H, I, J, O ones). The Non Solder resist Mask Defined (NSMD) pad type is recommended over the Solder resist Mask Defined

(SMD) pad type, as it implements the solder resist mask opening 50 m larger per side than the corresponding copper pad. The recommended thickness of the stencil for the soldering paste is 150 m, according to application production process requirements. Figure 54: SARA-R4/N4 series modules suggested footprint and paste mask (application board top view) Parameter Value A B C D E F 26.0 mm 16.0 mm 3.00 mm 2.00 mm 2.50 mm 1.05 mm Parameter Value G H H I I J 1.10 mm 0.80 mm 0.75 mm 1.50 mm 1.55 mm 0.30 mm Parameter Value K L M1 M2 N O 2.75 mm 2.75 mm 1.80 mm 3.60 mm 2.10 mm 1.10 mm UBX-16029218 - R11 Design-in Page 114 of 157 KM1M1M2EGHJEANT pinBPin 1KGHJADDOOLNLIFFKM1M1M2EGHJEANT pinBPin 1KGHJADDOOLNLIFFStencil: 150 m SARA-R4/N4 series - System Integration Manual F 1.00 mm J 0.35 mm O 1.05 mm Table 37: SARA-R4/N4 series modules suggested footprint and paste mask dimensions These are recommendations only and not specifications. The exact copper, solder and paste mask geometries, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. 2.12 Thermal guidelines The module operating temperature range is specified in the SARA-R4/N4 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks (for example, see the Terminal Tx Power distribution for WCDMA, taken from operation on a live network, described in the GSMA TS.09 Battery Life Measurement and Current Consumption Technique [10]); however the application should be correctly designed to cope with it. During transmission at maximum RF power the SARA-R4/N4 series modules generate thermal power that may exceed 0.5 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the actual antenna return loss, the transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition. The overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. The Module-to-Ambient thermal resistance value and the relative increase of module temperature will differ according to the specific mechanical deployments of the module, e.g. application PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. The increase of the thermal dissipation, i.e. the reduction of the Module-to-Ambient thermal resistance, will decrease the temperature of the modules internal circuitry for a given operating ambient temperature. This improves the device long-term reliability in particular for applications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application:

Connect each GND pin with solid ground layer of the application PCB and connect each ground area of the multilayer application PCB with complete thermal via stacked down to main ground layer. Provide a ground plane as wide as possible on the application board. UBX-16029218 - R11 Design-in Page 115 of 157 SARA-R4/N4 series - System Integration Manual Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power. Optimize the thermal design of any high-power components included in the application, such as linear regulators and amplifiers, to optimize overall temperature distribution in the application. Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure) of the application device that integrates the module so that it provides good thermal dissipation. Beside the reduction of the Module-to-Ambient thermal resistance implemented by correct application hardware design, the increase of module temperature can be moderated by a correspondingly correct application software implementation:

Enable power saving configuration using the AT+CPSMS command Enable module connected mode for a given time period and then disable it for a time period long enough to adequately mitigate the temperature increase. 2.13 Schematic for SARA-R4/N4 series module integration 2.13.1 Schematic for SARA-R4/N4 series modules Figure 55 is an example of a schematic diagram where a SARA-R4/N4 series 00, 01 or x2 product version is integrated into an application board using all available module interfaces and functions. UBX-16029218 - R11 Design-in Page 116 of 157 SARA-R4/N4 series - System Integration Manual Figure 55: Example of schematic diagram to integrate a SARA-R4/N4 series module using all available interfaces20 20 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input must be set low to have URCs presented over UART on 00, 01 and x2 product versions. UBX-16029218 - R11 Design-in Page 117 of 157 3V8GND100uF10nFSARA-R4/N452VCC53VCC51VCC68pFRSVD18RESET_NApplication ProcessorOpen drain output15PWR_ONOpen drain outputTPTP12TXD13RXD8DCD10RTS11CTS9DTR6DSR7RITPTPTXDRXDDCDRTSCTSDTRDSRRI1.8 V DTEGNDGNDUSB 2.0 hostD-D+28USB_D-29USB_D+VBUS17VUSB_DETTPTPGNDGND000047pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF41VSIM39SIM_IO38SIM_CLK40SIM_RST47pFSW1 SW24V_INT42GPIO5470kESDESDESDESDESDESD1kTPV_INT62ANT_DET10k27pFESD68nH56ConnectorExternal antenna33pFANTTP039nH15pF15pF100nF24GPIO3V_INTB1 A1GNDB2A2VCCBVCCASN74AVC2T245 Voltage Translator100nF100nF3V0TxD14.7kINOUTLDO RegulatorSHDNn4.7k3V83V023GPIO2V_INTSDA_A SDA_BGNDSCL_ASCL_BVCCAVCCBTCA9406I2C Voltage Translator100nF100nF100nF47kSDA2SCL2VCCDIR1DIR2OEnOEGNDEXTINT0GPIO425u-blox GNSS3.0 V receiver26SDA27SCLNot supported by 00 and 01 product versionGND3V8Network Indicator16GPIO119GPIO6SDIO_CMDSDIO_D0SDIO_D3SDIO_D146474849SDIO_D2SDIO_CLK444536I2S_CLK / SPI_CLK34I2S_WA / SPI_MOSI35I2S_TXD / SPI_CS 37I2S_RXD / SPI_MISO SARA-R4/N4 series - System Integration Manual 2.14 Design-in checklist This section provides a design-in checklist. 2.14.1 Schematic checklist The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at VCC pin within the operating range limits. DC supply must be capable of supporting the highest peak / pulse current consumption values and the maximum averaged current consumption values in connected mode, as specified in the SARA-

R4/N4 series Data Sheet [1]. VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in particular if the application device integrates an internal antenna. Do not apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range. Provide accessible test points directly connected to the following pins of the SARA-R4/N4 series modules: V_INT, PWR_ON and RESET_N for diagnostic purposes. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible. Check UART signals direction, as the modules signal names follow the ITU-T V.24 Recommendation

[5]. Capacitance and series resistance must be limited on each high speed line of the USB interface. It is strongly recommended to provide accessible test points directly connected to the USB interface pins (VUSB_DET, USB_D+ and USB_D- pins). Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Provide adequate precautions for EMC / ESD immunity as required on the application board. Do not apply voltage to any generic digital interface pin of SARA-R4/N4 series modules before the switch-on of the generic digital interface supply source (V_INT). All unused pins can be left unconnected. 2.14.2 Layout checklist The following are the most important points for a simple layout check:

UBX-16029218 - R11 Design-in Page 118 of 157 SARA-R4/N4 series - System Integration Manual Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT port (antenna RF interface). Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM signals, high-speed digital lines such as USB, and other data lines). Optimize placement for minimum length of RF line. Check the footprint and paste mask designed for SARA-R4/N4 series module as illustrated in section 2.11. VCC line should be enough wide and as short as possible. Route VCC supply line away from RF line / part (refer to Figure 28) and other sensitive analog lines

/ parts. The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the VCC pins, in particular if the application device integrates an internal antenna. Ensure an optimal grounding connecting each GND pin with application board solid ground layer. Use as many vias as possible to connect the ground planes on multilayer application board, providing a dense line of vias at the edges of each ground area, in particular along RF and high speed lines. Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity. USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 differential and 30 common mode) and should not be routed close to any RF line / part. 2.14.3 Antenna checklist Antenna termination should provide 50 characteristic impedance with V.S.W.R at least less than 3:1 (recommended 2:1) on operating bands in deployment geographical area. Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB layout and matching circuitry). Ensure compliance with any regulatory agency RF radiation requirement, as reported in section 4.2.2 for United States and in section 4.3.1 for Canada. Ensure high isolation between the cellular antenna and any other antennas or transmitters present on the end device. UBX-16029218 - R11 Design-in Page 119 of 157 SARA-R4/N4 series - System Integration Manual 3 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 3.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to SARA-R4/N4 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning, see the SARA-R4/N4 series Data Sheet [1]

and the u-blox Package Information Guide [15]. 3.2 Handling The SARA-R4/N4 series modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. The term is usually used in the electronics and other industries to describe momentary unwanted currents that may cause damage to electronic equipment. The ESD sensitivity for each pin of SARA-R4/N4 series modules (as Human Body Model according to JESD22-

A114F) is specified in the SARA-R4/N4 series Data Sheet [1]. ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working station or a large manufacturing area. The main principle of an EPA is that there are no highly charging materials near ESD sensitive electronics, all conductive materials are grounded, workers are grounded, and charge build-up on ESD sensitive electronics is prevented. International standards are used to define typical EPA and can be obtained for example from the International Electrotechnical Commission

(IEC) or the American National Standards Institute (ANSI). In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the SARA-R4/N4 series modules:

Unless there is a galvanic coupling between the local GND (i.e. the work table) and the PCB GND, then the first point of contact when handling the PCB must always be between the local GND and PCB GND. Before mounting an antenna patch, connect the ground of the device. When handling the module, do not come into contact with any charged capacitors and be careful when contacting materials that can develop charges (e.g. patch antenna, coax cable, soldering iron). UBX-16029218 - R11 Handling and soldering Page 120 of 157 SARA-R4/N4 series - System Integration Manual To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If there is any risk that such exposed antenna area is touched in a non-ESD protected work area, implement adequate ESD protection measures in the design. When soldering the module and patch antennas to the RF pin, make sure to use an ESD-safe soldering iron. UBX-16029218 - R11 Handling and soldering Page 121 of 157 SARA-R4/N4 series - System Integration Manual 3.3 Soldering 3.3.1 Soldering paste

"No Clean" soldering paste is strongly recommended for SARA-R4/N4 series modules, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature:

217 C Stencil Thickness:

150 m for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.11. The quality of the solder joints should meet the appropriate IPC specification. 3.3.2 Reflow soldering A convection type-soldering oven is strongly recommended for SARA-R4/N4 series modules over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the IPC-7530A Guidelines for temperature profiling for mass soldering (reflow and wave) processes. Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device!

Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. Note that this preheat phase will not replace prior baking procedures. Temperature rise rate: max 3 C/s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping. UBX-16029218 - R11 Handling and soldering Page 122 of 157 SARA-R4/N4 series - System Integration Manual Time: 60 120 s If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. End Temperature: +150 - +200 C If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of +217 C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above +217 C liquidus temperature: 40 - 60 s Peak reflow temperature: +245 C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4 C/s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Figure 56: Recommended soldering profile UBX-16029218 - R11 Handling and soldering Page 123 of 157 PreheatHeatingCooling[C]Peak Temp. 245C[C]250250Liquidus Temperature21721720020040 - 60 sEnd Temp.max 4C/s150 - 200C150150max 3C/s60 - 120 s100Typical Leadfree100Soldering Profile5050Elapsed time [s]SARA-R4/N4 series - System Integration Manual The modules must not be soldered with a damp heat process. 3.3.3 Optical inspection After soldering the module, inspect it optically to verify that it is correctly aligned and centered. 3.3.4 Cleaning Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results, use a "no clean" soldering paste and eliminate the cleaning step after the soldering. 3.3.5 Repeated reflow soldering Repeated reflow soldering processes and soldering the module upside-down are not recommended. Boards with components on both sides may require two reflow cycles. In this case, the module should always be placed on the side of the board that is submitted into the last reflow cycle. The reason for this

(besides others) is the risk of the module falling off due to the significantly higher weight in relation to other components. u-blox gives no warranty against damages to the SARA-R4/N4 series modules caused by performing more than a total of two reflow soldering processes (one reflow soldering process to mount the SARA-

R4/N4 series module, plus one reflow soldering process to mount other parts). 3.3.6 Wave soldering SARA-R4/N4 series LGA modules must not be soldered with a wave soldering process. Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. No more than one wave soldering process is allowed for a board with a SARA-R4/N4 series module already populated on it. Performing a wave soldering process on the module can result in severe damage to the device!

UBX-16029218 - R11 Handling and soldering Page 124 of 157 SARA-R4/N4 series - System Integration Manual u-blox gives no warranty against damages to the SARA-R4/N4 series modules caused by performing more than a total of two soldering processes (one reflow soldering process to mount the SARA-R4/N4 series module, plus one wave soldering process to mount other THT parts on the application board). 3.3.7 Hand soldering Hand soldering is not recommended. 3.3.8 Rework Rework is not recommended. Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty. 3.3.9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials affect the HF properties of the cellular modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating. Conformal Coating of the module will void the warranty. 3.3.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the cellular modules before implementing this in production. Casting will void the warranty. 3.3.11 Grounding metal covers Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interference and noise. u-blox gives no warranty for damages to the cellular modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. UBX-16029218 - R11 Handling and soldering Page 125 of 157 SARA-R4/N4 series - System Integration Manual 3.3.12 Use of ultrasonic processes The cellular modules contain components which are sensitive to ultrasonic waves. Use of any ultrasonic processes (cleaning, welding etc.) may cause damage to the module. u-blox gives no warranty against damages to the cellular modules caused by any ultrasonic processes. UBX-16029218 - R11 Handling and soldering Page 126 of 157 SARA-R4/N4 series - System Integration Manual 4 Approvals 4.1 Product certification approval overview Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications, typically called certification schemes, that can be divided into:

Regulatory certifications o Country-specific approval required by local government in most regions and countries, as:

CE (Conformit Europenne) marking for European Union FCC (Federal Communications Commission) approval for the United States Industry certifications o Telecom industry-specific approval verifying interoperability between devices and networks:

GCF (Global Certification Forum) PTCRB (PCS Type Certification Review Board) Operator certifications o Operator-specific approvals required by some mobile network operator, such as:

AT&T network operator in United States Verizon Wireless network operator in United States SARA-R4/N4 series modules approvals are summarized in Table 38. Certification SARA-R404M SARA-R410M-01B SARA-R410M-02B SARA-R410M-52B SARA-R412M-02B SARA-N410-02B PTCRB CE Europe LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat NB1 Bands 2, 4, 5, 12 2, 3, 4, 5, 8, 12, 13, 20, 28 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12 LTE Cat M1, NB1 Bands LTE Cat M1, NB1 Bands 3, 8, 20 3, 8, 20 2G Bands 900, 1800 2G Bands 850, 900, 1800, 1900 FCC US LTE Cat M1 Band LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat NB1 Bands 13 2, 4, 5, 12 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2G Bands 850, 1900 FCC ID XPY2AGQN1NNN XPY2AGQN4NNN XPY2AGQN4NNN XPY2AGQN4NNN XPYUBX18ZO01 XPY2AGQN4NNN ISED Canada LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat NB1 Bands 2, 4, 5, 12 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2G Bands 850, 1900 8595A-2AGQN4NNN 8595A-2AGQN4NNN 8595A-2AGQN4NNN 8595A-UBX18ZO01 8595A-2AGQN4NNN M1 Bands 2, 4, 5, 12 LTE Cat M1 Bands 3, 5, 8, 28 LTE Cat M1, NB1 Bands 3, 8, 28 UBX-16029218 - R11 Approvals LTE Cat NB1 Bands 3, 8, 28 Page 127 of 157 ISED ID IFT Mexico RCM Australia NCC Taiwan SARA-R4/N4 series - System Integration Manual Verizon LTE Cat M1 Band LTE Cat M1 Bands 13 4, 13 AT&T T-Mobile Bell Telus Telstra LTE Cat M1 Bands LTE Cat M1 Bands LTE Cat M1 Bands LTE Cat M1 Bands 2, 4, 5, 12 2, 4, 5, 12 2, 4, 5, 12 2, 4, 5, 12 LTE Cat M1 Bands 2, 4, 5, 12 LTE Cat M1 Bands LTE Cat M1 Bands 2, 4, 5, 12 2, 4, 5, 12 LTE Cat M1 Bands 3, 5, 8, 28 LTE Cat NB1 Bands 2, 4, 5, 12 Table 38: Summary of certification approvals achieved for the SARA-R4/N4 series modules, with related RAT and bands For the complete list and specific details regarding the certification approvals available for all the different SARA-R4/N4 series modules ordering numbers, including certificates of compliancy, please contact the u-blox office or sales representative nearest you. The manufacturer of the end-device that integrates a SARA-R4/N4 series module must take care of all certification approvals required by the specific integrating device to be deployed in the market. The required certification scheme approvals and relative testing specifications applicable to the end-device that integrates a SARA-R4/N4 series module differ depending on the country or the region where the integrating device is intended to be deployed, on the relative vertical market of the device, on type, features and functionalities of the whole application device, and on the network operators where the device is intended to operate. The SARA-R4/N4 series modules from 02 product versions onwards include the capability to configure the device by selecting the operating Mobile Network Operator Profile, Radio Access Technology, and bands. In the SARA-R4/N4 series AT Commands Manual [2], see the +UMNOPROF, +URAT, and

+UBANDMASK AT commands. As these configuration decisions are made, u-blox reminds manufacturers of the end-device integrating the 02 product versions onwards of SARA-R4/N4 series modules to take care of compliance with all the certification approvals requirements applicable to the specific integrating device to be deployed in the market. Check the appropriate applicability of the SARA-R4/N4 series modules approvals while starting the certification process of the device integrating the module: the re-use of the u-blox cellular modules approval can significantly reduce the cost and time to market of the application device certification. The certification of the application device that integrates a SARA-R4/N4 series module and the compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. SARA-R4/N4 series modules are certified according to all capabilities and options stated in the Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to the 3GPP UBX-16029218 - R11 Approvals Page 128 of 157 SARA-R4/N4 series - System Integration Manual TS 36.521-2 [12] and 3GPP TS 36.523-2 [13], is a statement of the implemented and supported capabilities and options of a device. The PICS document of the application device integrating SARA-R4/N4 series modules must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see the SARA-R4/N4 series AT Commands Manual [1]. Check the specific settings required for mobile network operators approvals as they may differ from the AT commands settings defined in the module as integrated in the application device. UBX-16029218 - R11 Approvals Page 129 of 157 SARA-R4/N4 series - System Integration Manual 4.2 US Federal Communications Commission notice United States Federal Communications Commission (FCC) IDs:

u-blox SARA-R404M cellular modules:

XPY2AGQN1NNN u-blox SARA-R410M and SARA-N410 cellular modules:

XPY2AGQN4NNN u-blox SARA-R412M cellular modules:

XPYUBX18ZO01 4.2.1 Safety warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product The clearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, hygroscopic materials, or materials containing asbestos are employed 4.2.2 Declaration of Conformity This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R4/N4 series modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the value specified in the FCC Grant for mobile and fixed or mobile operating configurations:

SARA-R404M modules:

o 13 dBi in 750 MHz, i.e. LTE FDD-13 band SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band SARA-R410M-02B, SARA-R410M-52B and SARA-N410-02B modules:

UBX-16029218 - R11 Approvals Page 130 of 157 SARA-R4/N4 series - System Integration Manual o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band SARA-R412M-02B modules:

o 8.69 dBi in 700 MHz, i.e. LTE FDD-12 band o 9.15 dBi in 750 MHz, i.e. LTE FDD-13 band o 9.41 dBi in 850 MHz, i.e. GSM 850 / LTE FDD-5 band o 12.01 dBi in 1700 MHz, i.e. LTE FDD-4 band o 12.01 dBi in 1900 MHz, i.e. GSM 1900 / LTE FDD-2 band 4.2.3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the SARA-R4/N4 series modules are authorized to use the FCC Grants of the SARA-R4/N4 series modules for their own final products according to the conditions referenced in the certificates. The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o For SARA-R404M modules:

o For SARA-R410M and SARA-N410 modules:

o For SARA-R412M cellular modules:

"Contains FCC ID: XPY2AGQN1NNN"

"Contains FCC ID: XPY2AGQN4NNN"

"Contains FCC ID: XPYUBX18ZO01"

IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4/N4 series modules are required to have their final product certified and apply for their own FCC Grant related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Additional Note: as per 47CFR15.105 this equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment UBX-16029218 - R11 Approvals Page 131 of 157 SARA-R4/N4 series - System Integration Manual off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

o Reorient or relocate the receiving antenna o Increase the separation between the equipment and receiver o Connect the equipment into an outlet on a circuit different from that to which the receiver is connected o Consultant the dealer or an experienced radio/TV technician for help 4.3 Innovation, Science, Economic Development Canada notice ISED Canada (formerly known as IC - Industry Canada) Certification Numbers:

u-blox SARA-R410M and SARA-N410 cellular modules:

8595A-2AGQN4NNN u-blox SARA-R412M cellular modules:

8595A-UBX18ZO01 4.3.1 Declaration of Conformity This device complies with the ISED Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R4/N4 series modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the value stated in the ISED Canada Grant for mobile and fixed or mobile operating configurations:

SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band SARA-R410M-02B, SARA-R410M-52B and SARA-N410-02B modules:

UBX-16029218 - R11 Approvals Page 132 of 157 SARA-R4/N4 series - System Integration Manual o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band SARA-R412M-02B modules:

o 5.63 dBi in 700 MHz, i.e. LTE FDD-12 band o 5.94 dBi in 750 MHz, i.e. LTE FDD-13 band o 6.12 dBi in 850 MHz, i.e. GSM 850 / LTE FDD-5 band o 8.29 dBi in 1700 MHz, i.e. LTE FDD-4 band o 8.52 dBi in 1900 MHz, i.e. GSM 1900 / LTE FDD-2 band 4.3.2 Modifications ISED Canada requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the SARA-R4/N4 series modules are authorized to use the ISED Canada Certificates of the SARA-R4/N4 series modules for their own final products according to the conditions referenced in the certificates. The ISED Canada Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o For SARA-R410M and SARA-N410 modules:

o For SARA-R412M cellular modules:

"Contains IC: 8595A-2AGQN4NNN"

"Contains IC: 8595A-UBX18ZO01"

Innovation, Science and Economic Development Canada (ISED) Notices This Class B digital apparatus complies with Canadian CAN ICES-3(B) / NMB-3(B). Operation is subject to the following two conditions:

this device may not cause interference this device must accept any interference, including interference that may cause undesired operation of the device Radio Frequency (RF) Exposure Information The radiated output power of the u-blox Cellular Module is below the Innovation, Science and Economic Development Canada (ISED) radio frequency exposure limits. The u-blox Cellular Module should be used in a manner such that the potential for human contact during normal operation is minimized. UBX-16029218 - R11 Approvals Page 133 of 157 SARA-R4/N4 series - System Integration Manual This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20 cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canadas REL (Radio Equipment List) can be found at the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng Additional Canadian information on RF exposure also can be found at the following web address:

http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4/N4 series modules are required to have their final product certified and apply for their own Industry Canada Certificate related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Avis d'Innovation, Sciences et Dveloppement conomique Canada (ISDE) Cet appareil numrique de classe B est conforme aux normes canadiennes CAN ICES-3(B) / NMB-3(B). Son fonctionnement est soumis aux deux conditions suivantes:

o cet appareil ne doit pas causer d'interfrence o cet appareil doit accepter toute interfrence, notamment les interfrences qui peuvent affecter son fonctionnement Informations concernant l'exposition aux frquences radio (RF) La puissance de sortie mise par lappareil de sans-fil u-blox Cellular Module est infrieure la limite d'exposition aux frquences radio d'Innovation, Sciences et Dveloppement conomique Canada (ISDE). Utilisez lappareil de sans-fil u-blox Cellular Module de faon minimiser les contacts humains lors du fonctionnement normal. Ce priphrique a t valu et dmontr conforme aux limites d'exposition aux frquences radio (RF) d'IC lorsqu'il est install dans des produits htes particuliers qui fonctionnent dans des conditions d'exposition des appareils mobiles (les antennes se situent plus de 20 centimtres du corps d'une personne). Ce priphrique est homologu pour l'utilisation au Canada. Pour consulter l'entre correspondant lappareil dans la liste d'quipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplmentaires concernant l'exposition aux RF au Canada rendez-vous sur:

http://www.ic.gc.ca/eic/site/smt-gst.nsf/fra/sf08792.html UBX-16029218 - R11 Approvals Page 134 of 157 SARA-R4/N4 series - System Integration Manual IMPORTANT: les fabricants d'applications portables contenant les modules de la SARA-R4/N4 series doivent faire certifier leur produit final et dposer directement leur candidature pour une certification FCC ainsi que pour un certificat ISDE Canada dlivr par l'organisme charg de ce type d'appareil portable. Ceci est obligatoire afin d'tre en accord avec les exigences SAR pour les appareils portables. Tout changement ou modification non expressment approuv par la partie responsable de la certification peut annuler le droit d'utiliser l'quipement. UBX-16029218 - R11 Approvals Page 135 of 157 SARA-R4/N4 series - System Integration Manual 4.4 European Conformance CE mark SARA-R410M-02B and SARA-R412M-02B module product versions have been evaluated against the essential requirements of the Radio Equipment Directive 2014/53/EU. In order to satisfy the essential requirements of the 2014/53/EU RED, the modules are compliant with the following standards:

Radio Spectrum Efficiency (Article 3.2):

o EN 301 908-1 o EN 301 908-13 o EN 301 511 Electromagnetic Compatibility (Article 3.1b):

o EN 301 489-1 o EN 301 489-52 Health and Safety (Article 3.1a) o EN 62368-1 o EN 62311 Radiofrequency radiation exposure Information: this equipment complies with radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R410M-02B and SARA-R412M-02B modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the values stated in the Declaration of Conformity of the modules, for mobile and fixed or mobile operating configurations:

SARA-R410M-02B modules:

o 8.2 dBi in 800 MHz, i.e. LTE FDD-20 band o 8.4 dBi in 900 MHz, i.e. LTE FDD-8 band o 11.3 dBi in 1800 MHz, i.e. LTE FDD-3 band SARA-R412M-02B modules:

o 8.2 dBi in 800 MHz, i.e. LTE FDD-20 band o 3.21 dBi in 900 MHz, i.e. GSM 900 / LTE FDD-8 band o 9.09 dBi in 1800 MHz, i.e. GSM 1800 / LTE FDD-3 band The conformity assessment procedure for the SARA-R410M-02B and SARA-R412M-02B modules, referred to in Article 17 and detailed in Annex II of Directive 2014/53/EU, has been followed. Thus, the following marking is included in the product:

UBX-16029218 - R11 Approvals Page 136 of 157 SARA-R4/N4 series - System Integration Manual 4.5 Taiwanese National Communication Commission The SARA-R410M-02B product version has the applicable regulatory approval for Taiwan (NCC) SARA-R410M-02B modules NCC ID: CCAA18NB0010T3 UBX-16029218 - R11 Approvals Page 137 of 157 CCAA18NB0010T3 SARA-R4/N4 series - System Integration Manual 5 Product testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested automatically on the production line. Stringent quality control processes have been implemented in the production line. Defective units are analyzed in detail to improve production quality. This is achieved with automatic test equipment (ATE) in the production line, which logs all production and measurement data. A detailed test report for each unit can be generated from the system. Figure 57 illustrates the typical automatic test equipment (ATE) in a production line. The following typical tests are among the production tests. Digital self-test (firmware download, flash firmware verification, IMEI programming) Measurement of voltages and currents Adjustment of ADC measurement interfaces Functional tests (serial interface communication, SIM card communication) Digital tests (GPIOs and other interfaces) Measurement and calibration of RF characteristics in all supported bands (such as receiver S/N verification, frequency tuning of the reference clock, calibration of transmitter and receiver power levels, etc.) Verification of the RF characteristics after calibration (i.e. modulation accuracy, power levels, spectrum, etc. are checked to ensure they are all within tolerances when calibration parameters are applied) Figure 57: Automatic test equipment for module tests UBX-16029218 - R11 Product testing Page 138 of 157 SARA-R4/N4 series - System Integration Manual 5.2 Test parameters for OEM manufacturers Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat the firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. However, an OEM manufacturer should focus on:

Module assembly on the device; it should be verified that:

o The soldering and handling process did not damage the module components o All module pins are well soldered on the device board o There are no short circuits between pins Component assembly on the device; it should be verified that:

o Communication with the host controller can be established o The interfaces between the module and device are working o Overall RF performance test of the device including the antenna Dedicated tests can be implemented to check the device. For example, the measurement of the module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result. In addition, module AT commands can be used to perform functional tests on the digital interfaces

(communication with the host controller, check the SIM interface, GPIOs, etc.) or to perform RF performance tests (see the following section 5.2.2 for details). 5.2.1 Go/No go tests for integrated devices A Go/No go test is typically used to compare the signal quality with a Golden Device in a location with excellent network coverage and known signal quality. This test should be performed after the data connection has been established. AT+CSQ is the typical AT command used to check signal quality in term of RSSI. See the SARA-R4/N4 series AT Commands Manual [2] for detail usage of the AT command. These kinds of test may be useful as a go/no go test but not for RF performance measurements. This test is suitable to check the functionality of communications with the host controller, the SIM card and the power supply. It is also a means to verify if components at the antenna interface are well-soldered. UBX-16029218 - R11 Product testing Page 139 of 157 SARA-R4/N4 series - System Integration Manual 5.2.2 RF functional tests The overall RF functional test of the device including the antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator with the assistance of the AT+UTEST command over the AT command user interface. The AT+UTEST command provides a simple interface to set the module to Rx or Tx test modes ignoring the LTE signaling protocol. The command can set the module into:

transmitting mode in a specified channel and power level in all supported bands receiving mode in a specified channel to return the measured power level in all supported bands See the SARA-R4/N4 series AT Commands Manual [2] for the AT+UTEST command syntax description and detail guide of usage. This feature allows the measurement of the transmitter and receiver power levels to check the component assembly related to the module antenna interface and to check other device interfaces on which the RF performance depends. To avoid module damage during a transmitter test, a suitable antenna according to module specifications or a 50 termination must be connected to the ANT port. To avoid module damage during a receiver test, the maximum power level received at the ANT port must meet module specifications. The AT+UTEST command sets the module to emit RF power ignoring LTE signaling protocol. This emission can generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing purposes in controlled environments by qualified users and must not be used during the normal module operation. Follow the instructions suggested in the u-blox documentation. u-blox assumes no responsibilities for the inappropriate use of this feature. Figure 58 illustrates a typical test setup for such an RF functional test. UBX-16029218 - R11 Product testing Page 140 of 157 SARA-R4/N4 series - System Integration Manual Figure 58: Setup with spectrum analyzer or power meter and signal generator for SARA-R4/N4 series RF measurements UBX-16029218 - R11 Product testing Page 141 of 157 Application BoardSARA-R4/N4ANTApplication ProcessorAT commandsCellular antennaSpectrumAnalyzerorPowerMeterINWideband antennaTXApplication BoardSARA-R4/N4Application ProcessorAT commandsSignalGeneratorOUTWideband antennaRXANTCellular antenna SARA-R4/N4 series - System Integration Manual Appendix A Migration between SARA modules A.1 Overview SARA-G3 2G modules, SARA-U2 3G / 2G modules, SARA-R4/N4 LTE Cat M1/NB1 / 2G modules and SARA-

N2 LTE Cat NB1 modules have exactly the same u-blox SARA form factor (26.0 x 16.0 mm, LGA 96-pin), with compatible pin assignments, as in Figure 59. Any one of the modules can be mounted on a single application board using exactly the same copper mask, solder mask and paste mask. Figure 59: SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 modules layout and pin assignment Table 39 summarizes the interfaces provided by the SARA-G3, SARA-U2, SARA-R4/N4, SARA-N2 modules. Modules RAT Power System SIM Serial Audio Other l t u p n i y p p u s e u d o M l l O

/

I y p p u s C T R SARA-G3 2G SARA-U2 3G, 2G SARA-R4/N4 LTE M1 / NB1, 2G SARA-N2 LTE NB1 l t u p t u O y p p u s V 8 1

. t u p n i n o

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C D D i o d u a g o a n A l t u p t u o z H M 6 2

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3 1 i o d u a l a t i g D i n o i t a c i d n i k r o w t e N n o i t c e t e d a n n e t n A m e d o m a i v S S N G s O P G I

= supported by available product version

= supported by future product versions UBX-16029218 - R11 Appendix Page 142 of 157 646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTRSVDGNDGPIO6RESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDVUSB_DETGNDGNDUSB_D-USB_D+RSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDSDIO_D2SDIO_CMDSDIO_D0SDIO_D1GNDVCCVCCRSVDI2S_TXD/SPI_CSI2S_CLK/SPI_CLKSIM_CLKSIM_IOVSIMGPIO5VCCSDIO_D3SDIO_CLKSIM_RSTI2S_RXD/SPI_MISOI2S_WA/SPI_MOSIGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-R4/N4Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTV_BCKPGNDRSVDRESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDRSVDGNDGNDRXD_AUXTXD_AUXRSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDSPK_PMIC_BIASMIC_GNDMIC_PGNDVCCVCCRSVDI2S_TXDI2S_CLKSIM_CLKSIM_IOVSIMSIM_DETVCCMIC_NSPK_NSIM_RSTI2S_RXDI2S_WAGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-G3Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTV_BCKPGNDCODEC_CLKRESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDVUSB_DETGNDGNDUSB_D-USB_D+RSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDRSVDRSVDRSVDRSVDGNDVCCVCCRSVDI2S_TXDI2S_CLKSIM_CLKSIM_IOVSIMSIM_DETVCCRSVDRSVDSIM_RSTI2S_RXDI2S_WAGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-U2Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSRSVDRSVDV_INTRSVDGNDRSVDRESET_NGPIO1RSVDRXDTXD320171496242730514845403734596256GNDGNDRSVDRSVDGNDRSVDGNDGNDRSVDRSVDRSVDGNDRSVDGPIO2SDASCLRSVDGNDGNDGNDRSVDRSVDRSVDRSVDGNDVCCVCCRSVDRSVDRSVDSIM_CLKSIM_IOVSIMRSVDVCCRSVDRSVDSIM_RSTRSVDRSVDGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-N2Top ViewPin 65-96: GND SARA-R4/N4 series - System Integration Manual Table 39: Summary of SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 modules interfaces SARA modules are also form-factor compatible with the u-blox LISA, LARA and TOBY cellular module families: although each has a different form factor, the footprints for the TOBY, LISA, SARA and LARA modules have been developed to ensure layout compatibility. With the u-blox nested design solution, any TOBY, LISA, SARA or LARA module can be alternatively mounted on the same space of a single nested application board as described in Figure 60. Guidelines for implementing a nested application board, a description of the u-blox reference nested design and a comparison between the TOBY, LISA, SARA and LARA modules are provided in the Nested Design Application Note [21]. Figure 60: TOBY, LISA, SARA, LARA modules layout compatibility: all modules lodged on the same nested footprint UBX-16029218 - R11 Appendix Page 143 of 157 LISA cellular moduleLARA cellular moduleSARA cellular moduleNested application boardTOBY cellular module SARA-R4/N4 series - System Integration Manual A.2 Pin-out comparison Table 40 shows a pin-out comparison between the SARA-G3, SARA-U2, SARA-R4/N4, and SARA-N2 modules. No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 1 2 3 4 5 6 GND Ground GND Ground GND Ground GND Ground V_BCKP RTC Supply I/O V_BCKP RTC Supply I/O RSVD Reserved RSVD Reserved RTC supply vs Reserved GND Ground GND Ground GND Ground GND Ground V_INT Interfaces Supply Output:

V_INT Interfaces Supply Output:

V_INT Interfaces Supply Output:

V_INT Interfaces Supply Output:

V_INT is switched off in deep 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max sleep (R4), or if radio is off (N2). Switched-off in deep-sleep Switched-off if radio is off TestPoint always recommended GND DSR Ground UART DSR Output V_INT level (1.8 V) GND DSR Ground UART DSR Output V_INT level (1.8 V) GND DSR Ground GND Ground UART DSR Output RSVD Reserved Not supported by N2 V_INT level (1.8 V) Diverse driver strength Driver strength: 6 mA Driver strength: 1 mA Driver strength: 2 mA 7 RI UART RI Output RI UART RI Output RI UART RI Output RSVD Reserved Not supported by N2 V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse driver strength Driver strength: 6 mA Driver strength: 2 mA Driver strength: 2 mA 8 DCD UART DCD Output DCD UART DCD Output DCD UART DCD Output RSVD Reserved Not supported by N2 V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse driver strength Driver strength: 6 mA Driver strength: 2 mA Driver strength: 2 mA 9 DTR UART DTR Input DTR UART DTR Input DTR UART DTR Input RSVD Reserved Not supported by N2 V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse internal pull-up value Internal pull-up: ~33 k Internal pull-up: ~14 k Internal pull-up: ~100 k It must be set low to have It must be set low to have It must be set low to have greeting text sent over UART greeting text sent over UART URCs sent over UART UBX-16029218 - R11 Appendix Page 144 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 10 RTS UART RTS Input RTS UART RTS Input RTS UART RTS Input21 RTS UART RTS Input21 Diverse level (V_INT vs VCC);

V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) VCC level (3.6 V typ.) Diverse internal pull-up value;

Internal pull-up:~58 k Internal pull-up: ~8 k Internal pull-up: ~100 k Internal pull-up: ~78 k Diverse functions supported. It must be set low to use UART on 00, 01 product versions 11 CTS UART CTS Output CTS UART CTS Output CTS UART CTS Output21 CTS UART CTS Output21 Diverse level (V_INT vs VCC) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) VCC level (3.6 V typ.) Diverse driver strength. Driver strength: 6 mA Driver strength: 6 mA Driver strength: 2 mA Driver strength: 1 mA Diverse functions supported. Configurable as Ring Indicator or Network Indicator 12 TXD UART Data Input TXD UART Data Input TXD UART Data Input TXD UART Data Input Diverse level (V_INT vs VCC);

V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) VCC level (3.6 V typ.) Diverse pull-up / pull-down;

Internal pull-up:~18 k Internal pull-up: ~8 k Internal pull-up/-down: ~100k No internal pull-up/-down TestPoint always recommended 13 RXD UART Data Output RXD UART Data Output RXD UART Data Output RXD UART Data Output Diverse level (V_INT vs VCC);

V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) VCC level (3.6 V typ.) Diverse driver strength;

Driver strength: 6 mA Driver strength: 6 mA Driver strength: 2 mA Driver strength: 1 mA TestPoint always recommended 14 15 GND Ground GND Ground GND Ground GND Ground PWR_ON Power-on Input PWR_ON Power-on Input PWR_ON Power-on Input RSVD Reserved Not supported by N2; Internal No internal pull-up No internal pull-up 200 k internal pull-up L-level: -0.10 V 0.65 V L-level: -0.30 V 0.65 V L-level: -0.30 V 0.35 V H-level: 2.00 V 4.50 V H-level: 1.50 V 4.40 V H-level: 1.17 V 2.10 V ON L-level time:

5 ms min ON L-level pulse time:

ON L-level pulse time:

50 s min / 80 s max 0.15 s min 3.2 s max OFF L-level pulse time:

OFF L-level pulse time:

OFF L-level pulse time:

Not Available 1 s min 1.5 s min vs No internal pull-up; Diverse voltage levels; Diverse timings;

Diverse functions supported;

TestPoint recommended for R4 21 Not supported by 00, 01, SARA-R410M-02B product versions and SARA-N2 modules UBX-16029218 - R11 Appendix Page 145 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 16 GPIO1 / RSVD GPIO (G340/G350) GPIO1 GPIO GPIO1 GPIO GPIO1 GPIO Diverse driver strength Reserved (G300/G310) V_INT level (1.8 V) Default: Pin disabled Driver strength: 6 mA V_INT level (1.8 V) Default: Pin disabled Driver strength: 6 mA V_INT level (1.8 V) Default: Pin disabled Driver strength: 2 mA V_INT level (1.8 V) TestPoint recommended for N2 Configurable as secondary UART data output: TestPoint recommended for diagnostic 17 RSVD Reserved VUSB_DET 5 V, USB Supply Detect Input VUSB_DET 5 V, USB Supply Detect Input RSVD Reserved USB detection vs Reserved;

TestPoint recommended for U2/R4 18 RESET_N Reset input RESET_N Abrupt shutdown/reset input RESET_N Abrupt shutdown input RESET_N Reset input Diverse internal pull-up Internal diode & pull-up 10 k internal pull-up 37 k internal pull-up 78 k internal pull-up Diverse voltage levels. L-level: -0.30 V 0.30 V L-level: -0.30 V 0.51 V L-level: -0.30 V 0.35 V L-level: -0.30 V 0.36*VCC Diverse timings. H-level: 2.00 V 4.70 V H-level: 1.32 V 2.01 V H-level: 1.17 V 2.10 V H-level: 0.52*VCC VCC Diverse functions supported. Reset L-level pulse time:

Reset L-level pulse time:

OFF L-level pulse time:

Reset L-level pulse time:

TestPoint always recommended 50 ms min (G340/G350) 50 ms min 10 s min 500 ns min 3 s min (G300/G310) 19 RSVD Reserved CODEC_CLK 13 or 26 MHz Output GPIO6 GPIO RSVD Reserved Clock / GPIO vs Reserved V_INT level (1.8 V) Default: Pin disabled V_INT level (1.8 V) Default: Pin disabled Driver strength: 4 mA Driver strength: 2 mA 20 21 22 23 GND GND GND Ground Ground Ground GND GND GND Ground Ground Ground GND GND GND Ground Ground Ground GND GND GND Ground Ground Ground GPIO2 / RSVD GPIO (G340/G350) GPIO2 GPIO GPIO2 GPIO RSVD Reserved GPIO vs Reserved Reserved (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS supply enable Default: Pin disabled Default: GNSS supply enable Driver strength: 1 mA Driver strength: 2 mA Driver strength: 6 mA UBX-16029218 - R11 Appendix Page 146 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 24 GPIO3 /

GPIO (G340/G350) GPIO3 GPIO GPIO3 GPIO GPIO2 GPIO23 Diverse driver strength 32K_OUT 32 kHz Output (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS data ready Driver strength: 5 mA Default: GNSS data ready Default: Pin disabled Driver strength: 6 mA Driver strength: 2 mA V_INT level (1.8 V) Default: Pin disabled Driver strength: 1 mA 25 GPIO4 / RSVD GPIO (G340/G350) GPIO4 GPIO GPIO4 GPIO RSVD Reserved GPIO vs Reserved Reserved (G300/G310) V_INT level (1.8 V) Default: GNSS RTC sharing Driver strength: 6 mA V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS RTC sharing Default: Output/Low Driver strength: 6 mA Driver strength: 2 mA 26 SDA /

I2C Data I/O (G340/G350) SDA I2C Data I/O /

SDA I2C Data I/O22 SDA I2C Data I/O23 Internal vs No internal pull-up RSVD Reserved (G300/G310) AUX UART in (04 version) V_INT level (1.8 V) V_INT level (1.8 V) Open drain No internal pull-up V_INT level (1.8 V) Open drain No internal pull-up Open drain Internal 2.2 k pull-up V_INT level (1.8 V) Open drain No internal pull-up 27 SCL /

I2C Clock Out (G340/G350) SCL I2C Clock Output /

SCL I2C Clock Output22 SCL I2C Clock Output23 Internal vs No internal pull-up RSVD Reserved (G300/G310) AUX UART out (04 version) V_INT level (1.8 V) V_INT level (1.8 V) Open drain No internal pull-up V_INT level (1.8 V) Open drain No internal pull-up Open drain Internal 2.2 k pull-up V_INT level (1.8 V) Open drain No internal pull-up 28 RXD_AUX Aux UART Data Out USB_D-

USB Data I/O (D-) USB_D-

USB Data I/O (D-) RSVD Reserved USB / AUX UART vs Reserved V_INT level (1.8 V) High-Speed USB 2.0 High-Speed USB 2.0 TestPoint recommended for SARA-G3/U2/R4 modules 29 TXD_AUX Aux UART Data In USB_D+

USB Data I/O (D+) USB_D+

USB Data I/O (D+) RSVD Reserved USB / AUX UART vs Reserved V_INT level (1.8 V) High-Speed USB 2.0 High-Speed USB 2.0 TestPoint recommended for SARA-G3/U2/R4 modules 22 Not supported by 00 and 01 product versions 23 Not supported by 02 product versions UBX-16029218 - R11 Appendix Page 147 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 30 31 32 33 34 GND Ground GND Ground GND Ground GND Ground RSVD /

Reserved (G340/G350) RSVD Reserved RSVD Reserved RSVD Reserved 32 kHz Input vs Reserved EXT32K 32 kHz Input (G300/G310) GND RSVD Ground GND Ground GND Ground GND Ground It must be connected to GND RSVD It must be connected to GND RSVD It can be connected to GND RSVD It can be connected to GND I2S_WA /

I2S Word Align.(G340/G350) I2S_WA I2S Word Alignment I2S_WA /

I2S Word Alignm24 / SPI RSVD Reserved I2S vs SPI vs Reserved RSVD Reserved (G300/G310) V_INT level (1.8 V) SPI_MOSI MOSI24 V_INT level (1.8 V) Driver strength: 6 mA Driver strength: 2 mA V_INT level (1.8 V) Driver strength: 2 mA 35 I2S_TXD /

I2S Data Output (G340/G350) I2S_TXD I2S Data Output I2S_TXD /

I2S Data Out24 / SPI chip RSVD Reserved I2S vs SPI vs Reserved RSVD Reserved (G300/G310) V_INT level (1.8 V) SPI_CS select24 V_INT level (1.8 V) Driver strength: 5 mA Driver strength: 2 mA V_INT level (1.8 V) Driver strength: 2 mA 36 I2S_CLK /

I2S Clock (G340/G350) I2S_CLK I2S Clock I2S_CLK /

I2S Clock24 / SPI clock24 RSVD Reserved I2S vs SPI vs Reserved RSVD Reserved (G300/G310) V_INT level (1.8 V) SPI_CLK V_INT level (1.8 V) V_INT level (1.8 V) Driver strength: 5 mA Driver strength: 2 mA Driver strength: 2 mA 37 I2S_RXD /

I2S Data Input (G340/G350) I2S_RXD I2S Data Input I2S_RXD /

I2S Data Input24 / SPI MISO24 RSVD Reserved I2S vs SPI vs Reserved RSVD Reserved (G300/G310) V_INT level (1.8 V) SPI_MISO V_INT level (1.8 V) V_INT level (1.8 V) 38 39 40 41 SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V SIM Clock Output SIM_IO 1.8V/3V SIM Data I/O SIM_IO 1.8V/3V SIM Data I/O SIM_IO 1.8V/3V SIM Data I/O SIM_IO 1.8V SIM Data I/O Internal 4.7 k pull-up Internal 4.7 k pull-up Internal 4.7 k pull-up Internal 4.7 k pull-up SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V SIM Reset Output VSIM 1.8V/3V SIM Supply Output VSIM 1.8V/3V SIM Supply Output VSIM 1.8V/3V SIM Supply Output VSIM 1.8V SIM Supply Output 24 Not supported by 00, 01 and x2 product version UBX-16029218 - R11 Appendix Page 148 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 42 SIM_DET SIM Detection Input SIM_DET SIM Detection Input GPIO5 SIM Detection Input RSVD Reserved SIM Detection vs Reserved V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) 43 44 GND Ground GND Ground GND Ground GND Ground SPK_P / RSVD Analog Audio Out (+) /

RSVD Reserved SDIO_D2 SDIO serial data [2]24 RSVD Reserved Analog Audio vs SDIO vs RSVD Reserved 45 SPK_N / RSVD Analog Audio Out (-) /

RSVD Reserved SDIO_CLK SDIO serial clock24 RSVD Reserved Analog Audio vs SDIO vs RSVD Reserved 46 MIC_BIAS /

Microphone Supply Out /

RSVD Reserved SDIO_CMD SDIO command24 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved 47 MIC_GND /

Microphone Ground /

RSVD Reserved SDIO_D0 SDIO serial data [0]24 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved 48 MIC_N / RSVD Analog Audio In (-) /

RSVD Reserved SDIO_D3 SDIO serial data [3]24 RSVD Reserved Analog Audio vs SDIO vs RSVD Reserved 49 MIC_P / RSVD Analog Audio In (+) /

RSVD Reserved SDIO_D1 SDIO serial data [1]24 RSVD Reserved Analog Audio vs SDIO vs RSVD Reserved 50 GND Ground 51-53 VCC Module Supply Input GND VCC Normal op. range:

3.35 V 4.5 V Extended op. range:

3.00 V 4.5 V Ground Module Supply Input Normal op. range:

3.3 V 4.4 V Extended op. range:

3.1 V 4.5 V GND VCC Ground Module Supply Input Normal op. range:

3.2 V 4.2 V Extended op. range:

3.0 V 4.3 V GND VCC Ground Module Supply Input Diverse voltage levels. Normal op. range:

Diverse current consumption. 3.1 V 4.0 V Recommended external Extended op. range:

capacitors and other parts for 2.75 V 4.2 V EMI suppression may differ. Current consumption:

Current consumption:

Current consumption:

Current consumption:

Regular pF / nF recommended.

~2.0A pulse current in 2G

~2.0A pulse current in 2G

~2.0A pulse current in 2G

~0.3A LTE pulse current Diverse functions supported. Switch-on applying VCC Switch-on applying VCC

(recommended 100uF)

(recommended 100uF)

~0.5A LTE pulse current

(recommended 10uF) No turn-on applying VCC Switch-on applying VCC 54-55 GND Ground GND Ground GND Ground GND Ground UBX-16029218 - R11 Appendix Page 149 of 157 SARA-R4/N4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 56 ANT RF Antenna I/O 57-61 GND Ground ANT GND RF Antenna I/O Ground ANT GND RF Antenna I/O Ground ANT GND RF Antenna I/O Diverse bands supported Ground 62 ANT_DET /

Antenna Detection Input /

ANT_DET Antenna Detection Input ANT_DET Antenna Detection Input ANT_DET Antenna Detection Input25 Antenna Detection vs Reserved RSVD Reserved 63-96 GND Ground GND Ground GND Ground GND Ground Table 40: SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 series modules pin assignments with remarks for migration For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the SARA-G3, SARA-U2, SARA-R4/N4 and SARA-

N2 series cellular modules, see the related Data Sheet [1], [16], [17], [18], the related System Integration Manual [19], [20], and the Nested Design Application Note [21]. 25 Not supported by 02 product version UBX-16029218 - R11 Appendix Page 150 of 157 SARA-R4/N4 series - System Integration Manual B Glossary Abbreviation Definition 2G 3G 3GPP 8-PSK ADC AT Cat CE DC DCE DDC DL DTE EDGE eDRX 2nd Generation Cellular Technology (GSM, GPRS, EGPRS) 3rd Generation Cellular Technology (UMTS, HSDPA, HSUPA) 3rd Generation Partnership Project 8 Phase-Shift Keying modulation Analog to Digital Converter AT Command Interpreter Software Subsystem, or attention Category European Conformity Direct Current Data Communication Equipment Display Data Channel interface Down-Link (Reception) Data Terminal Equipment Enhanced Data rates for GSM Evolution (EGPRS) Extended Discontinuous Reception EGPRS Enhanced General Packet Radio Service (EDGE) EMC EMI ESD ESR Electro-Magnetic Compatibility Electro-Magnetic Interference Electro-Static Discharge Equivalent Series Resistance E-UTRA Evolved Universal Terrestrial Radio Access FCC FDD FOAT FOTA FTP FW GCF GMSK GND GNSS GPIO GPRS Federal Communications Commission United States Frequency Division Duplex Firmware Over AT commands Firmware Over The Air File Transfer Protocol Firmware Global Certification Forum Gaussian Minimum-Shift Keying modulation Ground Global Navigation Satellite System General Purpose Input Output General Packet Radio Service UBX-16029218 - R11 Appendix Page 151 of 157 SARA-R4/N4 series - System Integration Manual Abbreviation Definition GPS HBM HTTP HW IFT I2C I2S ISED LDO LGA LNA LPWA LTE Global Positioning System Human Body Model HyperText Transfer Protocol Hardware Federal Telecommunications Institute Mexico Inter-Integrated Circuit interface Inter IC Sound interface Innovation, Science and Economic Development Canada Low-Dropout Land Grid Array Low Noise Amplifier Low Power Wide Area Long Term Evolution LWM2M Open Mobile Alliance Lightweight Machine-to-Machine protocol M2M MQTT N/A NAS OEM OTA PA PCM PCN PFM PSM PTCRB PWM QPSK RAT RF RSE RTC SAW SDIO SIM SMS Machine-to-Machine Message Queuing Telemetry Transport Not Applicable Non Access Stratum Original Equipment Manufacturer device: an application device integrating a u-blox cellular module Over The Air Power Amplifier Pulse Code Modulation Product Change Notification / Sample Delivery Note / Information Note Pulse Frequency Modulation Power Saving Mode PCS Type Certification Review Board Pulse Width Modulation Quadrature Phase Shift Keying Radio Access Technology Radio Frequency Radiated Spurious Emission Real Time Clock Surface Acoustic Wave Secure Digital Input Output Subscriber Identification Module Short Message Service UBX-16029218 - R11 Appendix Page 152 of 157 SARA-R4/N4 series - System Integration Manual Abbreviation Definition SPI SRF SSL TBD TCP TDD Serial Peripheral Interface Self-Resonant Frequency Secure Socket Layer To Be Defined Transmission Control Protocol Time Division Duplex TDMA Time Division Multiple Access TIS TP TRP UART UDP UICC UL UMTS USB VoLTE VSWR Total Isotropic Sensitivity Test-Point Total Radiated Power Universal Asynchronous Receiver-Transmitter User Datagram Protocol Universal Integrated Circuit Card Up-Link (Transmission) Universal Mobile Telecommunications System Universal Serial Bus Voice over LTE Voltage Standing Wave Ratio Table 41: Explanation of the abbreviations and terms used UBX-16029218 - R11 Appendix Page 153 of 157 SARA-R4/N4 series - System Integration Manual Related documents

[1]

[2]

[3]

u-blox SARA-R4/N4 series Data Sheet, document number UBX-16024152 u-blox SARA-R4/N4 series AT Commands Manual, document number UBX-17003787 u-blox EVK-R4/N4 User Guide, document number UBX-16029216

[4] Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/usb20_docs/

[5]

ITU-T Recommendation V.24 - 02-2000 - List of definitions for interchange circuits between Data Terminal Equipment (DTE) and Data Circuit-terminating Equipment (DCE), http://www.itu.int/rec/T-REC-V.24-200002-I/en 3GPP TS 27.007 - AT command set for User Equipment (UE) 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE -

DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol I2C-bus specification and user manual - Rev. 5 - 9 October 2012 - NXP Semiconductors, http://www.nxp.com/documents/user_manual/UM10204.pdf

[6]

[7]

[8]

[9]

[10] GSM Association TS.09 - Battery Life Measurement and Current Consumption Technique, https://www.gsma.com/newsroom/wp-content/uploads/TS.09_v10.1.pdf

[11] 3GPP TS 36.521-1 - Evolved Universal Terrestrial Radio Access; User Equipment conformance specification; Radio transmission and reception; Part 1: Conformance Testing

[12] 3GPP TS 36.521-2 - Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment conformance specification; Radio transmission and reception; Part 2: Implementation Conformance Statement (ICS)

[13] 3GPP TS 36.523-2 - Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Packet Core

(EPC); User Equipment conformance specification; Part 2: Implementation Conformance Statement

(ICS)

[14] u-blox End user test Application Note, document number UBX-13001922

[15] u-blox Package Information Guide, document number UBX-14001652

[16] u-blox SARA-G3 series Data Sheet, document number UBX-13000993

[17] u-blox SARA-U2 series Data Sheet, document number UBX-13005287

[18] u-blox SARA-N2 series Data Sheet, document number UBX-15025564

[19] u-blox SARA-G3/SARA-U2 series System Integration Manual, document num. UBX-13000995

[20] u-blox SARA-N2 series System Integration Manual, document number UBX-17005143

[21] u-blox Nested Design Application Note, document number UBX-16007243 For regular updates to u-blox documentation and to receive product change notifications, register on our homepage (www.u-blox.com). UBX-16029218 - R11 Related documents Page 154 of 157 SARA-R4/N4 series - System Integration Manual Revision history Revision Date Name Comments R01 R02 R03 R04 R05 R06 R07 31-Jan-2017 sfal Initial release 05-May-2017 sfal / sses Updated supported features and characteristics Extended document applicability to SARA-R410M-01B product version 24-May-2017 sses Updated supported features and electrical characteristics 19-Jul-2017 sses Updated supported features and electrical characteristics Added FCC and ISED info for SARA-R410M-01B modules Extended document applicability to SARA-R410M-02B product version 17-Aug-2017 sses Updated supported features for 02 product version 30-Oct-2017 sses Updated supported features for 02 product version 04-Jan-2018 sses Updated SARA-R410M-02B product status Updated USB, Power Saving and GPIO features description Improved Power-on sequence guidelines description Added I2C design guidelines description R08 26-Feb-2018 sses Updated SARA-R410M-02B product status Extended document applicability to SARA-R412M-02B product version Corrected power-on sequence description Corrected UART MUX description R09 10-Aug-2018 sses Extended document applicability to SARA-R410M-52B and SARA-N410-02B product version Updated SARA-R410M-02B and SARA-R412M-02B product status Updated features support plan for the product versions Clarified supported bands Updated UART TXD and CTS info Updated Approvals info and related remarks Added description of AT Inactivity Timer to enter power saving mode Minor other corrections R10 20-Sep-2018 lpah / sses Extended document applicability to SARA-R404M-00B-01 type number Clarified mode supported in frequency bands Added further guidelines for VCC and Antenna circuits design R11 20-Feb-2019 sses Updated SARA-N410-02B and SARA-R412M-02B product status Revised supported bands Updated certification info Clarified VCC and RESET_N guidelines Minor other corrections and clarifications UBX-16029218 - R11 Revision history Page 155 of 157 SARA-R4/N4 series - System Integration Manual Contact For complete contact information, visit us at www.u-blox.com. u-blox Offices North, Central and South America Headquarters Asia, Australia, Pacific u-blox America, Inc. Phone: +1 703 483 3180 Europe, Middle East, Africa u-blox AG u-blox Singapore Pte. Ltd. Phone: +65 6734 3811 E-mail:

info_us@u-blox.com Phone: +41 44 722 74 44 E-mail:

info_ap@u-blox.com Regional Office West Coast:

Phone: +1 408 573 3640 E-mail:

info_us@u-blox.com Technical Support:

Phone: +1 703 483 3185 E-mail:

support@u-blox.com E-mail:

info@u-blox.com Support: support_ap@u-blox.com Support: support@u-blox.com Regional Office Australia:

Phone: +61 2 8448 2016 E-mail:

info_anz@u-blox.com Support: support_ap@u-blox.com Regional Office China (Beijing):

Phone: +86 10 68 133 545 E-mail:

info_cn@u-blox.com Support: support_cn@u-blox.com Regional Office China (Chongqing):

Phone: +86 23 6815 1588 E-mail:

info_cn@u-blox.com Support: support_cn@u-blox.com Regional Office China (Shanghai):

Phone: +86 21 6090 4832 E-mail:

info_cn@u-blox.com Support: support_cn@u-blox.com Regional Office China (Shenzhen):

Phone: +86 755 8627 1083 E-mail:

info_cn@u-blox.com Support: support_cn@u-blox.com Regional Office India:

Phone: +91 80 405 092 00 E-mail:

info_in@u-blox.com Support: support_in@u-blox.com Regional Office Japan (Osaka):

Phone: +81 6 6941 3660 E-mail:

info_jp@u-blox.com Support: support_jp@u-blox.com Regional Office Japan (Tokyo):

UBX-16029218 - R11 Contact Page 156 of 157 SARA-R4/N4 series - System Integration Manual Phone: +81 3 5775 3850 E-mail:

info_jp@u-blox.com Support: support_jp@u-blox.com Regional Office Korea:

Phone: +82 2 542 0861 E-mail:

info_kr@u-blox.com Support: support_kr@u-blox.com Regional Office Taiwan:

Phone: +886 2 2657 1090 E-mail:

info_tw@u-blox.com Support: support_tw@u-blox.com UBX-16029218 - R11 Contact Page 157 of 157

 

 

SARA-R4/N4 series LTE Cat M1 / NB1 and EGPRS modules Data Sheet SARA-

R4/N4 Abstract Technical data sheet describing the size-optimized SARA-R4/N4 series LTE Cat M1 / NB1 and EGPRS cellular modules. The modules are a complete and cost efficient solution offering multi band data transmissions for Low Power Wide Area solutions in a compact form factor. www.u-blox.com UBX-16024152 - R11 SARA-R4/N4 series - Data Sheet Document Information Title Subtitle SARA-R4/N4 series LTE Cat M1 / NB1 and EGPRS modules Document type Data Sheet Document number UBX-16024152 Revision and date R11 Disclosure Restriction Product status Corresponding content status 09-May-2018 Functional Sample Draft For functional testing. Revised and supplementary data will be published later. In Development /

Prototype Objective Specification Target values. Revised and supplementary data will be published later. Engineering Sample Advance Information Data based on early testing. Revised and supplementary data will be published later. Initial Production Early Production Information Data from product verification. Revised and supplementary data may be published later. Mass Production /

End of Life Production Information Document contains the final product specification. This document applies to the following products:

Product name Type number Modem version Application version PCN reference Product status SARA-R404M SARA-R404M-00B-00 K0.0.00.00.07.06 SARA-R410M SARA-R410M-01B-00 L0.0.00.00.02.03 UBX-17047084 Initial Production UBX-17051617 Initial Production SARA-R410M-02B-00 L0.0.00.00.05.06 A02.00 UBX-18010263 Initial Production SARA-R412M SARA-R412M-02B-00 M0.03.00 A01.03 UBX-18006467 Prototype SARA-N410 SARA-N410-02B-00 Functional Sample u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided as is and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. Copyright u-blox AG. UBX-16024152 - R11 Page 2 of 41 SARA-R4/N4 series - Data Sheet Contents Document Information ................................................................................................................................ 2 Contents .......................................................................................................................................................... 3 1 Functional description ......................................................................................................................... 5 1.1 Overview ........................................................................................................................................................ 5 1.2 Product features ......................................................................................................................................... 5 1.3 Block diagram .............................................................................................................................................. 6 1.4 Product description .................................................................................................................................... 7 1.5 AT command support ................................................................................................................................ 8 1.6 Supported features .................................................................................................................................... 9 2 Interfaces ................................................................................................................................................. 9 2.1 Power management ................................................................................................................................. 10 2.1.1 Module supply input (VCC) ............................................................................................................. 10 2.1.2 Generic digital interfaces supply output (V_INT) ....................................................................... 10 2.2 Antenna interface ..................................................................................................................................... 10 2.2.1 Antenna RF interface (ANT) ........................................................................................................... 10 2.2.2 Antenna detection (ANT_DET) ...................................................................................................... 10 2.3 System functions ....................................................................................................................................... 11 2.3.1 Module power-on ............................................................................................................................... 11 2.3.2 Module power-off ............................................................................................................................... 11 2.3.3 Module reset ....................................................................................................................................... 11 2.4 SIM ................................................................................................................................................................ 11 2.4.1 SIM interface ...................................................................................................................................... 11 2.4.2 SIM detection ..................................................................................................................................... 11 2.5 Serial communication ...............................................................................................................................12 2.5.1 UART interface ...................................................................................................................................12 2.5.2 USB interface ..................................................................................................................................... 13 2.5.3 SPI interface ...................................................................................................................................... 13 2.5.4 SDIO interface ................................................................................................................................... 14 2.5.5 DDC (I2C) interface ............................................................................................................................ 14 2.6 Audio ............................................................................................................................................................ 14 2.7 GPIO ............................................................................................................................................................. 15 3 Pin definition ......................................................................................................................................... 16 3.1 Pin assignment .......................................................................................................................................... 16 4 Electrical specifications ................................................................................................................... 20 4.1 Absolute maximum rating....................................................................................................................... 20 4.1.1 Maximum ESD ................................................................................................................................... 20 4.2 Operating conditions .................................................................................................................................21 4.2.1 Operating temperature range .........................................................................................................21 4.2.2 Thermal parameters .........................................................................................................................21 4.2.3 Supply/power pins ............................................................................................................................ 22 UBX-16024152 - R11 Page 3 of 41 SARA-R4/N4 series - Data Sheet 4.2.4 Current consumption ....................................................................................................................... 23 4.2.5 LTE RF characteristics .................................................................................................................... 24 4.2.6 2G RF characteristics ...................................................................................................................... 26 4.2.7 ANT_DET pin characteristics ......................................................................................................... 26 4.2.8 PWR_ON pin ....................................................................................................................................... 27 4.2.9 RESET_N pin ...................................................................................................................................... 27 4.2.10 SIM pins .............................................................................................................................................. 27 4.2.11 USB pins ............................................................................................................................................. 28 4.2.12 Generic Digital Interfaces pins ....................................................................................................... 28 4.2.13 DDC (I2C) pins ..................................................................................................................................... 28 5 Mechanical specifications ................................................................................................................29 6 Qualification and approvals............................................................................................................. 30 6.1 Reliability tests ..........................................................................................................................................30 6.1.1 Approvals ............................................................................................................................................30 7 Product handling & soldering ........................................................................................................... 31 7.1 Packaging ................................................................................................................................................... 31 7.1.1 Reels .................................................................................................................................................... 31 7.1.2 Tapes ................................................................................................................................................... 32 7.2 Moisture Sensitivity Levels ..................................................................................................................... 33 7.3 Reflow soldering ........................................................................................................................................ 33 7.4 ESD precautions ........................................................................................................................................ 33 8 Labeling and ordering information ............................................................................................... 34 8.1 Product labeling ......................................................................................................................................... 34 8.2 Explanation of codes ................................................................................................................................ 34 8.3 Ordering information ................................................................................................................................ 35 Appendix ....................................................................................................................................................... 36 A Glossary ................................................................................................................................................. 36 Related documents ................................................................................................................................... 39 Revision history .......................................................................................................................................... 40 Contact ........................................................................................................................................................... 41 UBX-16024152 - R11 Page 4 of 41 SARA-R4/N4 series - Data Sheet 1 Functional description 1.1 Overview SARA-R4/N4 series modules are an LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode solution in the miniature SARA LGA form factor (26.0 x 16.0 mm, 96-pin). They allow an easy integration into compact designs and a seamless drop-in migration from other u-blox cellular module families. SARA-R4/N4 series modules provide software-based multi-band configurability enabling world-wide global coverage in LTE Cat M1 / NB1 and (E)GPRS / GSM radio access technologies. Variants specifically designed to operate in LTE Cat NB1 only, or in LTE Cat M1 band 13 only, or in LTE Cat M1 bands 2, 4, 5 and 12 only are also available. SARA-R4/N4 series modules offer data communications up to 375 kbit/s over an extended operating temperature range of 40 C to +85 C, with low power consumption, and with coverage enhancement for deeper range into buildings and basements (and underground with NB1). With many interface options and an integrated IP stack, SARA-R4/N4 series modules are the optimal choice for LPWA applications with low to medium data throughput rates, as well as devices that require long battery lifetimes, such as used in smart metering, smart lighting, telematics, asset tracking, remote monitoring, alarm panels, and connected health. Customers can future-proof their solutions by means of Over-The-Air firmware updates, thanks to the uFOTA client/server solution that utilizes LWM2M, a light and compact protocol ideal for IoT applications. SARA-R4/N4 series modules will also support VoLTE over Cat M1. The flexibility extends further through dynamic mode selection as M1-only/preferred or NB1-only/preferred. 1.2 Product features Model Region Bands Positioning Interfaces Audio Features Grade e n i l e s a B e s a e e R P P G 3 l y r o g e t a c E T L P P G 3 d n a b

-

4 S R P G

) E

(

/

M S G e r a w t f o s w o N t s s s A i e t a c o L l l e C T R A U

. 0 2 B S U m e d o m a v S S N G i s d n a b D D F E T L SARA-R404M USA 13 M1 13 SARA-R410M-01B North America 13 M1 2,4 5,12 I O D S I P S i o d u a g o a n A l I s O P G

) C 2 I

(

C D D SARA-R410M-02B Global 13 SARA-R412M-02B Global 13 M1 NB1 M1 NB1

*

*

SARA-N410-02B Global 13 NB1

*

* = Bands 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only)

= supported by all FW versions = supported by future FW versions Table 1: SARA-R4/N4 series main features summary k c a t s P D U

/

P C T d e d d e b m E i r o s v r e p u s a n n e t n A P T F

, P T T H d e d d e b m E 6 v P I

/

4 v P I k c a t s l a u D

) A T O F

(

r i a e h t r e v o e t a d p u W F i e d o M g n v a S r e w o P i o d u a l a t i g D i X R D e l i a n o s s e f o r P e v i t o m o t u A d r a d n a t S UBX-16024152 - R11 Functional description Page 5 of 41 SARA-R4/N4 series - Data Sheet 1.3 Block diagram Figure 1: SARA-R4/N4 series block diagram SARA-R404M-00B and SARA-R410M-01B modules, i.e. the 00 and 01 product versions of the SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

DDC (I2C) interface SDIO interface SPI interface Digital audio interface SARA-R410M-02B, SARA-R412M-02B and SARA-N410-02B modules, i.e. the 02 product version of the SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

SDIO interface SPI interface Digital audio interface UBX-16024152 - R11 Functional description Page 6 of 41 MemoryV_INTRF transceiverCellularBaseBandProcessorANTVCC (Supply)USBDDC (I2C)SIM card detectionSIMUARTPower-OnResetGPIOsAntenna detectionSwitchPA19.2 MHzPowerManagementFilterSDIOSPI / Digital Audio SARA-R4/N4 series - Data Sheet 1.4 Product description SARA-R4/N4 series modules include the following variants / product versions:

SARA-R404M LTE Cat M1 module, mainly designed for operation in LTE band 13 SARA-R410M-01B LTE Cat M1 module, mainly designed for operation in LTE bands 2, 4, 5, 12 SARA-R410M-02B LTE Cat M1 / NB1 module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28 SARA-R412M-02B LTE Cat M1 / NB1 and 2G module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad-band SARA-N410-02B LTE Cat NB1 module, mainly designed for operation in LTE bands 2, 4, 5, 12, 13 Item SARA-R404M SARA-R410M SARA-R412M SARA-N410 Protocol stack 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13 LTE Cat M1 Half-Duplex LTE Cat M1 Half-Duplex LTE Cat NB1 Half-Duplex1 LTE Cat M1 Half-Duplex LTE Cat NB1 Half-Duplex 2G GSM / GPRS / EGPRS LTE Cat NB1 Half-Duplex RAT Bands LTE FDD bands:

Band 13 (750 MHz) LTE FDD bands:

Band 12 (700 MHz) Band 17 (700 MHz) 1 Band 28 (700 MHz) 1 Band 13 (750 MHz) 1 Band 20 (800 MHz) 1 Band 26 (850 MHz) 1 Band 18 (850 MHz) 1 Band 5 (850 MHz) Band 19 (850 MHz) 1 Band 8 (900 MHz) 1 Band 4 (1700 MHz) Band 3 (1800 MHz) 1 Band 2 (1900 MHz) Band 25 (1900 MHz) 1 Band 1 (2100 MHz) 1 LTE TDD bands:

Band 39 (1900 MHz) 2 Power class LTE Cat M1:

Class 3 (23 dBm) LTE Cat M1 / NB11:

Class 3 (23 dBm) LTE FDD bands:

Band 12 (700 MHz) Band 17 (700 MHz) Band 28 (700 MHz) Band 13 (750 MHz) Band 20 (800 MHz) Band 26 (850 MHz) Band 18 (850 MHz) Band 5 (850 MHz) Band 19 (850 MHz) Band 8 (900 MHz) Band 4 (1700 MHz) Band 3 (1800 MHz) Band 2 (1900 MHz) Band 25 (1900 MHz) Band 1 (2100 MHz) LTE category NB1:

Class 3 (23 dBm) LTE FDD bands:

Band 12 (700 MHz) Band 17 (700 MHz) Band 28 (700 MHz) Band 13 (750 MHz) Band 20 (800 MHz) Band 26 (850 MHz) Band 18 (850 MHz) Band 5 (850 MHz) Band 19 (850 MHz) Band 8 (900 MHz) Band 4 (1700 MHz) Band 3 (1800 MHz) Band 2 (1900 MHz) Band 25 (1900 MHz) Band 1 (2100 MHz) LTE TDD bands:

Band 39 (1900 MHz) 2 2G bands:

GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz LTE category M1 / NB1:

Class 3 (23 dBm) 2G GMSK:

Class 4 (33 dBm) for GSM/E-GSM bands Class 1 (30 dBm) for DCS/PCS bands 2G 8-PSK:

Class E2 (27 dBm) for GSM/E-GSM bands Class E2 (26 dBm) for DCS/PCS bands 1 Not supported by the 01 product version. 2 Supported in LTE category M1 only. Not supported by the 01 product version. UBX-16024152 - R11 Functional description Page 7 of 41 SARA-R4/N4 series - Data Sheet Item SARA-R404M SARA-R410M SARA-R412M SARA-N410 Data rate LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category NB11:

up to 62.5 kb/s UL up to 27.2 kb/s DL LTE category NB1:

up to 62.5 kb/s UL up to 27.2 kb/s DL LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category NB1:

up to 62.5 kb/s UL up to 27.2 kb/s DL GPRS multi-slot class 333:

Up to 85.6 kb/s UL Up to 107 kb/s DL EGPRS multi-slot class 333:

Up to 236.8 kb/s UL Up to 296.0 kb/s DL Table 2: SARA-R4/N4 series LTE Cat M1, LTE Cat NB1, EGPRS, GPRS and GSM characteristics 1.5 AT command support The SARA-R4/N4 series modules support AT commands according to the 3GPP standards TS 27.007 [4], TS 27.005 [5], TS 27.010 [6], and the u-blox AT command extension. For the complete list of all supported AT commands and their syntax, see the SARA-R4/N4 series AT Commands Manual [1]. 3 GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total. UBX-16024152 - R11 Functional description Page 8 of 41 SARA-R4/N4 series - Data Sheet 1.6 Supported features Table 3 lists some of the main features supported by SARA-R4/N4 series modules. For more details, see the SARA-R4/N4 series System Integration Manual [2] and the SARA-R4/N4 series AT Commands Manual [1]. Feature Description Network Indication Antenna Detection GPIO configured to indicate the network status: registered home network, registered roaming, data call enabled, no service. The feature can be enabled through the +UGPIOC AT command. The ANT_DET pin provides antenna presence detection capability, evaluating the resistance from the ANT pin to GND by means of an external antenna detection circuit implemented on the application board. The antenna supervisor (i.e. antenna detection) feature can be enabled through the +UANTR AT command. Embedded TCP and UDP stack Embedded TCP/IP and UDP/IP stack including direct link mode for TCP and UDP sockets. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via the serial interface. FTP HTTP Embedded SSL/TLS 4 MQTT 5 File Transfer Protocol functionality is supported via AT commands. Hyper-Text Transfer Protocol functionality is supported via AT commands. With the support of X.509 certificates, embedded SSL/TLS provides server and client authentication, data encryption, data signature and enables TCP/IP applications to communicate over a secured and trusted connection. The feature can be configured and enabled by the

+USECMNG and +USECPRF AT commands. Message Queuing Telemetry Transport is an ISO standard publish-subscribe messaging protocol designed for lightweight M2M communications over TCP. MQTT allows clients to communicate one-to-one, one-to-many and many-to-one over a long-lived outgoing TCP connection. Dual stack IPv4/IPv6 Capability to move between IPv4 and dual stack network infrastructures. IPv4 and IPv6 addresses can be used. Firmware update Over AT commands (FOAT) Firmware module update over AT command interface. The feature can be enabled and configured through the +UFWUPD AT command. Firmware update Over The Air (uFOTA) GNSS via modem 5 u-blox firmware module update over the LTE air interface client/server solution using LWM2M. Full access to u-blox positioning chips and modules is available through a dedicated DDC (I2C) interface. This means that from any host processor, a single serial port can control the SARA-R4/N4 series cellular module and the u-blox positioning chip or module. Power Saving Mode (PSM) The Power Saving Mode (PSM) feature, defined in 3GPP Rel.13, allows further reduction of the module current consumption maximizing the amount of time a device can remain in PSM low power deep sleep mode during periods of data inactivity. It can be activated and configured by the

+CPSMS AT command. e-I-DRX 6 Extended Idle mode DRX, based on 3GPP Rel.13, reduces the amount of signaling overhead decreasing the frequency of scheduled measurements and/or transmissions performed by the module in idle mode. This in turn leads to a reduction in the module power consumption while maintaining a perpetual connection with the base station. Coverage Enhancements Mode A Coverage Enhancements Mode A, introduced in 3GPP Rel.13, is used to improve cell signal penetration. Coverage Enhancements Mode B 7 Coverage Enhancements Mode B, introduced in 3GPP Rel.13, is used to further improve cell signal penetration. Table 3: Some of the main features supported by SARA-R4/N4 series modules 2 Interfaces 4 Not supported by 00 product version 5 Not supported by 00 and 01 product versions 6 The feature is disabled on 00 and 01 product versions due to network readiness 7 Not supported by 00, 01 and 02 product versions UBX-16024152 - R11 Interfaces Page 9 of 41 SARA-R4/N4 series - Data Sheet 2.1 Power management 2.1.1 Module supply input (VCC) SARA-R4/N4 series modules must be supplied through the VCC pins by a DC power supply. Voltage must be stable, because during operation the current drawn from VCC may vary significantly, based on the power consumption profile of the LTE Cat M1, LTE Cat NB1 and the 2G radio access technologies (described in the SARA-R4/N4 series System Integration Manual [2]). SARA-R412M modules provide separate supply inputs over the three VCC pins:

VCC pins #52 and #53 represent the supply input for the internal RF Power Amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding minor part of the total current drawn of the module when RF transmission is enabled during a call The three VCC pins of SARA-R404M, SARA-R410M and SARA-N410 modules are internally connected to both the internal Power Amplifier and the internal baseband Power Management Unit. It is important that the system power supply circuit is able to withstand the maximum pulse current during a transmit burst at maximum power level (see Table 12). 2.1.2 Generic digital interfaces supply output (V_INT) SARA-R4/N4 series modules provide a 1.8 V supply rail output on the V_INT pin, which is internally generated when the module is switched on. The same voltage domain is used internally to supply the generic digital interfaces of the module. The V_INT supply output can be used in place of an external discrete regulator. 2.2 Antenna interface 2.2.1 Antenna RF interface (ANT) The ANT pin represents the RF antenna interface of the module, with a characteristic impedance of 50 . 2.2.2 Antenna detection (ANT_DET) The ANT_DET pin is an Analog to Digital Converter (ADC) input with a current source provided by SARA-R4/N4 series modules to sense the antenna presence (as an optional feature). It evaluates the resistance from the ANT pin to GND by means of an external antenna detection circuit implemented on the application board (for more details, see the u-blox SARA-R4/N4 series System Integration Manual [2] and the SARA-R4/N4 series AT Commands Manual [1]). UBX-16024152 - R11 Interfaces Page 10 of 41 SARA-R4/N4 series - Data Sheet 2.3 System functions 2.3.1 Module power-on SARA-R4/N4 series can be switched on using the following procedure:

Low level on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time period when the applied VCC voltage is within the valid operating range (see sections 4.2.3 and 4.2.8). The PWR_ON line has to be driven by open drain, open collector or contact switch. 2.3.2 Module power-off SARA-R4/N4 series can be properly switched off, with storage of the current parameter settings and a clean network detach, in one of these ways:

AT+CPWROFF command (see the SARA-R4/N4 series AT Commands Manual [1]) Low pulse on the PWR_ON pin for a valid time period (see section 4.2.8) An abrupt shutdown occurs on SARA-R4/N4 series modules, without storage of the current parameter settings and without a clean network detach, when:

the VCC supply drops below the extended operating range minimum limit a low level is applied on the RESET_N pin, which is normally set high by an internal pull-up, for a valid time period (see section 4.2.9). RESET_N line has to be driven by open drain, open collector or contact switch. 2.3.3 Module reset SARA-R4/N4 series modules can be reset (re-booted) by:

AT+CFUN command (see the SARA-R4/N4 series AT Commands Manual [1]). This causes an internal or software reset of the module. The current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed. 2.4 SIM 2.4.1 SIM interface A SIM card interface is provided on the VSIM, SIM_IO, SIM_CLK, SIM_RST pins: the high-speed SIM/ME interface is implemented as well as the automatic detection of the required SIM supporting voltage. Both 1.8 V and 3 V SIM types are supported (1.8 V and 3 V). Activation and deactivation with an automatic voltage switch from 1.8 V to 3 V is implemented according to the ISO-IEC 7816-3 specifications. The SIM driver supports the PPS procedure for baud-rate selection, according to the values proposed by the SIM card/chip. 2.4.2 SIM detection The GPIO5 pin of SARA-R4/N4 series modules is a 1.8 V digital input which can be configured as an external interrupt to detect the SIM card presence, as intended to be properly connected to the mechanical switch of an external SIM card holder. For more details, see the SARA-R4/N4 series System Integration Manual [2] and the SARA-R4/N4 series AT Commands Manual [1]. UBX-16024152 - R11 Interfaces Page 11 of 41 SARA-R4/N4 series - Data Sheet 2.5 Serial communication The SARA-R4/N4 series provides the following serial communication interfaces:

UART interface: asynchronous serial interface available for the communication with a DTE host application processor (AT commands, data communication, FW update by means of FOAT) USB interface: High-Speed USB 2.0 compliant interface available for communications with a USB host application processor (AT commands, data communication, FW update by means of the FOAT feature), for FW update by means of the u-blox tool and for diagnostics SPI interface: Serial Peripheral Interface available for communications with an external compatible device SDIO interface: Secure Digital Input Output interface available for communications with a compatible device DDC interface: I2C bus compatible interface available for communications with external I2C devices 2.5.1 UART interface SARA-R4/N4 series modules include a 9-wire unbalanced asynchronous serial interface (UART) for communication with an application host processor (AT commands and data communication). The UART is available only if the USB is not enabled as AT command / data communication interface: UART and USB cannot be concurrently used for this purpose. UART features are:

Complete serial port with RS-232 ITU-T V.24 Recommendation [9], with CMOS compatible signal levels (0 V for low data bit or ON state and 1.8 V for high data bit or OFF state) functionality conforming to the Data lines (RXD as output, TXD as input), hardware flow control lines (CTS as output, RTS as input), modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output) are provided The default baud rate is 115200 bit/s The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Hardware flow control is not supported by the 00, 01 and SARA-R410M-02B product versions, but the RTS input line needs to be set low (= ON state) to communicate over the UART interface on the 00 and 01 product versions. The UART serial interface can be conveniently configured through AT commands. For more details, see the SARA-R4/N4 series AT Commands Manual [1] and the SARA-R4/N4 series System Integration Manual [2]. Multiplexer protocol SARA-R4/N4 series modules include multiplexer functionality as per 3GPP TS 27.010 [6] on the UART physical link. This is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE), allowing a number of simultaneous sessions over the physical link (UART). UBX-16024152 - R11 Interfaces Page 12 of 41 SARA-R4/N4 series - Data Sheet The following virtual channels are defined:

Channe for Multiplexer control l 0:

Channe l 1:

for all AT commands, and non-Dial Up Network (non-DUN) data connections. UDP, TCP data socket / data call connections through relevant AT commands. Channe l 2:

for Dial Up Network (DUN) data connection. It requires the host to have and use its own TCP/IP stack. The DUN can be initiated on the modem side or terminal/host side. Channe for u-blox GNSS data tunneling (not supported by the 00 and 01 product versions). l 3:

2.5.2 USB interface SARA-R4/N4 series modules include a high-speed USB 2.0 compliant interface with a maximum 480 Mbit/s data rate according to the USB 2.0 specification [10] representing the main interface for transferring high speed data with a host application processor. The module itself acts as a USB device and can be connected to any USB host equipped with compatible drivers. The USB is the most suitable interface for transferring high speed data between SARA-R4/N4 series and a host processor, available for AT commands, data communication, FW upgrade by means of the FOAT feature, FW upgrade by means of the u-blox dedicated tool and for diagnostic purposes. The USB_D+ / USB_D- lines carry the USB data and signaling, while the VUSB_DET pin represents the input to enable the USB interface by applying an external valid USB VBUS supply voltage (5.0 V typical). The USB interface is available as an AT command / data communication interface only if an external valid USB VBUS supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the switch-on of the module, and then held during normal operations. In this case, the UART will not be available. If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode defined in 3GPP Rel.13. SARA-R4/N4 series modules provide by default a set of two USB functions:

AT commands and data communication Diagnostic log For more details regarding USB configurations / capabilities, see the SARA-R4/N4 series System Integration Manual [2]. 2.5.3 SPI interface The SPI interface is not supported by the 00, 01 and 02 product versions. SARA-R4/N4 series modules compatible external device. include a Serial Peripheral Interface for communications with The SPI interface can be made available as an alternative function, in a mutually exclusive way, over the digital audio interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS). UBX-16024152 - R11 Interfaces Page 13 of 41 SARA-R4/N4 series - Data Sheet 2.5.4 SDIO interface The SDIO interface is not supported by the 00, 01 and 02 product versions. SARA-R4/N4 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, and SDIO_CMD) designed to communicate with external compatible SDIO devices. 2.5.5 DDC (I2C) interface The DDC (I2C) interface is not supported by the 00 and 01 product versions. SARA-R4/N4 series modules include an I2C-bus compatible DDC interface (SDA, SCL) available to communicate with a u-blox GNSS receiver and with external I2C devices as an audio codec: the SARA-R4/N4 series module acts as an I2C master that can communicate with I2C slaves in accordance with the I2C bus specifications [11]. The SDA and SCL pins have internal pull-up to V_INT, so there is no need of additional pull-up resistors on the external application board. 2.6 Audio Audio is not supported by the 00, 01 and 02 product versions. SARA-R4/N4 series modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio services. SARA-R4/N4 series modules include an I2S digital audio interface to transfer digital audio data to/from an external compatible audio device. The digital audio interface can be made available as an alternative function, in a mutually exclusive way, over the SPI interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS). UBX-16024152 - R11 Interfaces Page 14 of 41 2.7 GPIO SARA-R4/N4 series - Data Sheet SARA-R4/N4 series modules include six pins (GPIO1-GPIO6) that can be configured as general purpose input/output or to provide custom functions as summarized in Table 4 (for further details, see the SARA-R4/N4 series System Integration Manual [2] and the GPIO section of the SARA-R4/N4 series AT Commands Manual [1]). Function Description Default GPIO Configurable GPIOs Network status indication Network status: registered / data transmission, no service GNSS supply enable 8 Enable/disable the supply of a u-blox GNSS receiver GNSS data ready 8 connected to the cellular module by the DDC (I2C) interface Sense when a u-blox GNSS receiver connected to the module is ready for sending data by the DDC (I2C) interface SIM card detection SIM card physical presence detection Module status indication Module switched off or in PSM low power deep sleep mode, versus active or connected mode General purpose input General purpose output Input to sense high or low digital level Output to set the high or the low digital level Pin disabled Tri-state with an internal active pull-down enabled Table 4: GPIO custom functions configuration

--

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--

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GPIO1 GPIO2 GPIO3 GPIO5 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 8 Not supported by 00 and 01 product versions UBX-16024152 - R11 Interfaces Page 15 of 41 SARA-R4/N4 series - Data Sheet 3 Pin definition 3.1 Pin assignment Figure 2: SARA-R4/N4 series pin assignment (top view) No Name Power domain I/O Description Remarks 1 2 3 4 5 6 GND RSVD GND V_INT

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N/A N/A N/A O Ground All the GND pins must be connected to ground RESERVED pin Leave unconnected. Ground All the GND pins must be connected to ground Generic Digital Interfaces supply output V_INT = 1.8 V (typical) generated by the module when is switched on, outside low power PSM deep sleep mode. See section 4.2.3 for detailed electrical specs. Provide test point for diagnostic purposes. GND DSR

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GDI N/A Ground All the GND pins must be connected to ground O UART data set ready Circuit 107 (DSR) in ITU-T V.24. See section 4.2.12 for detailed electrical specs. UBX-16024152 - R11 Pin definition Page 16 of 41 646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTRSVDGNDGPIO6RESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDVUSB_DETGNDGNDUSB_D-USB_D+RSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDSDIO_D2SDIO_CMDSDIO_D0SDIO_D1GNDVCCVCCRSVDI2S_TXD / SPI_CSI2S_CLK / SPI_CLKSIM_CLKSIM_IOVSIMGPIO5VCCSDIO_D3SDIO_CLKSIM_RSTI2S_RXD / SPI_MISOI2S_WA / SPI_MOSIGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-R4/N4Top ViewPin 65-96: GND SARA-R4/N4 series - Data Sheet I/O Description Remarks UART ring indicator Circuit 125 (RI) in ITU-T V.24. See section 4.2.12 for detailed electrical specs. UART data carrier detect Circuit 109 (DCD) in ITU-T V.24. No Name 7 8 9 RI DCD DTR Power domain GDI GDI GDI 10 RTS GDI O O I I UART data terminal ready UART ready to send 11 CTS GDI O UART clear to send 12 TXD GDI I UART data input 13 14 15 16 17 RXD GDI O UART data output PWR_ON POS I Power-on / power-off input GPIO1 GDI I/O GPIO VUSB_DET USB 18 RESET_N ERS I I USB detect input External reset input 19 GPIO6 GDI I/O GPIO 20 21 22 23 GND GND GND

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GPIO2 GDI N/A N/A N/A I/O Ground Ground Ground GPIO 24 GPIO3 GDI I/O GPIO 25 GPIO4 GDI I/O GPIO 26 SDA DDC I/O I2C bus data line See section 4.2.12 for detailed electrical specs. Circuit 108/2 (DTR) in ITU-T V. 24. Internal active pull-up to V_INT. See section 4.2.12 for detailed electrical specs. Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. Flow control is not supported by the 00, 01 and SARA-R410M-02B product versions See section 4.2.12 for detailed electrical specs. Circuit 106 (CTS) in ITU-T V.24. Flow control is not supported by the 00, 01 and SARA-R410M-02B product versions See section 4.2.12 for detailed electrical specs. Circuit 103 (TxD) in ITU-T V.24. Internal active pull-down to GND on 00, 02 versions Internal active pull-up to V_INT on 01 versions See section 4.2.12 for detailed electrical specs. Circuit 104 (RxD) in ITU-T V.24. See section 4.2.12 for detailed electrical specs. Internal 200 k pull-up resistor. See section 4.2.8 for detailed electrical specs. Provide test point for diagnostic purposes. Configurable GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. Input for VBUS (5 V typical) USB supply sense. See section 4.2.11 for detailed electrical specs. Provide test point for diagnostic purposes. Internal 37 k pull-up resistor to V_INT. See section 4.2.9 for detailed electrical specs. Provide test point for diagnostic purposes. Configurable GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. All the GND pins must be connected to ground All the GND pins must be connected to ground All the GND pins must be connected to ground Configurable GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. Configurable GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. Configurable GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. Fixed open drain. Internal 2.2 k pull-up resistor to V_INT. Not supported by 00 and 01 product versions See section 4.2.13 for detailed electrical specs. GND

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N/A Ground All the GND pins must be connected to ground UBX-16024152 - R11 Pin definition Page 17 of 41 SARA-R4/N4 series - Data Sheet No Name Power domain I/O Description Remarks 27 SCL DDC O I2C bus clock line 28 USB_D-

USB I/O USB Data Line D-

29 USB_D+

USB I/O USB Data Line D+

Fixed open drain. Internal 2.2 k pull-up resistor to V_INT. Not supported by 00 and 01 product versions See section 4.2.13 for detailed electrical specs. 90 nominal differential impedance. Pull-up, pull-down and series resistors, as required by the USB 2.0 specifications [10], are part of the USB pin driver and shall not be provided externally. See section 4.2.11 for detailed electrical specs. Provide test point for diagnostic purposes. 90 nominal differential impedance. Pull-up, pull-down and series resistors, as required by USB 2.0 specifications [10], are part of the USB pin driver and shall not be provided externally. See section 4.2.11 for detailed electrical specs. Provide test point for diagnostic purposes. 30 31 32 33 34 35 36 37 38 39 40 41 GND RSVD GND RSVD

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I2S_WA /

SPI_MOSI GDI I2S_TXD /

SPI_CS GDI I2S_CLK /

SPI_CLK GDI I2S_RXD /

SPI_MISO GDI SIM_CLK SIM_IO SIM SIM SIM_RST SIM VSIM

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N/A N/A N/A Ground All the GND pins must be connected to ground RESERVED pin Leave unconnected. Ground All the GND pins must be connected to ground N/A RESERVED pin This pin can be connected to GND. O /

O O /

O O /

O I /

I O I/O O O I2S word alignment /

SPI Master Output Slave Input I2S transmit data /

SPI Chip Select I2S clock /

SPI clock I2S receive data /

SPI Master Input Slave Output SIM clock SIM data I2S word alignment, alternatively configurable as SPI Master Output Slave Input Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. I2S transmit data out, alternatively configurable as SPI Chip Select Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. I2S clock, alternatively configurable as SPI clock Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. I2S receive data input, alternatively configurable as SPI Master Input Slave Output Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. See section 4.2.10 for detailed electrical specs. Internal 4.7 k pull-up resistor to VSIM. See section 4.2.10 for detailed electrical specs. SIM reset See section 4.2.10 for detailed electrical specs. SIM supply output 42 GPIO5 GDI I SIM detection GND

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N/A Ground All the GND pins must be connected to ground 43 44 SDIO_D2 GDI I/O SDIO serial data [2]

45 SDIO_CLK GDI O SDIO serial clock 46 SDIO_CMD GDI I/O SDIO command VSIM = 1.80 V typical or 2.95 V typical generated by the module according to the external SIM card type. See section 4.2.3 for detailed electrical specs. SIM card presence detection input, alternatively configurable as GPIO (see section 2.7). See section 4.2.12 for detailed electrical specs. Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. UBX-16024152 - R11 Pin definition Page 18 of 41 SARA-R4/N4 series - Data Sheet No Name Power domain I/O Description Remarks 47 SDIO_D0 GDI I/O SDIO serial data [0]

48 SDIO_D3 GDI I/O SDIO serial data [3]

49 SDIO_D1 GDI I/O SDIO serial data [1]

Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. Not supported by 00, 01 and 02 product versions See section 4.2.12 for detailed electrical specs. N/A Ground All the GND pins must be connected to ground 50 51 GND VCC 52 VCC 53 VCC 54 55 56 57 58 59 60 61 62 63 64 GND GND ANT GND GND GND GND GND GND GND

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I I I N/A N/A I/O N/A N/A N/A N/A N/A Module supply input Module supply input Module supply input Ground Ground RF input/output Ground Ground Ground Ground Ground All VCC pins must be connected to external supply. SARA-R404M, SARA-R410M and SARA-N410:

supply input for all internal parts. SARA-R412M: supply input for internal BB PMU. See section 4.2.3 and 4.2.4 for detailed specs. All VCC pins must be connected to external supply. SARA-R404M, SARA-R410M and SARA-N410:

supply input for all internal parts. SARA-R412M: supply input for internal RF PA. See section 4.2.3 and 4.2.4 for detailed specs. All VCC pins must be connected to external supply. SARA-R404M, SARA-R410M and SARA-N410:

supply input for all internal parts. SARA-R412M: supply input for internal RF PA. See section 4.2.3 and 4.2.4 for detailed specs. All the GND pins must be connected to ground All the GND pins must be connected to ground 50 nominal impedance. See section 4.2.5 for detailed electrical specs. All the GND pins must be connected to ground All the GND pins must be connected to ground All the GND pins must be connected to ground All the GND pins must be connected to ground All the GND pins must be connected to ground Antenna presence detection function. See section 4.2.7 for detailed electrical specs. All the GND pins must be connected to ground All the GND pins must be connected to ground All the GND pins must be connected to ground ANT_DET ADC I Antenna detection 65-96 GND

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N/A N/A N/A Ground Ground Ground Table 5: SARA-R4/N4 series pin-out For more information about the pin-out, see the u-blox SARA-R4/N4 series System Integration Manual [2]. See Appendix A for an explanation of the abbreviations and terms used. UBX-16024152 - R11 Pin definition Page 19 of 41 SARA-R4/N4 series - Data Sheet 4 Electrical specifications Stressing the device above one or more of the ratings listed in the Absolute Maximum Rating section may cause permanent damage. These are stress ratings only. Operating the module at these or at any conditions other than those specified in the Operating Conditions sections

(section 4.2) of the specification should be avoided. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating condition ranges define those limits within which the functionality of the device is guaranteed. Electrical characteristics are defined according to the verification on a representative number of samples or according to the simulation. Where application information is given, it is advisory only and does not form part of the specification. 4.1 Absolute maximum rating Limiting values given below are in accordance with the Absolute Maximum Rating System

(IEC 134). Symbol Description Condition Min. Max. Unit VCC Module supply voltage Input DC voltage at VCC pins (SARA-R404M) Input DC voltage at VCC pins

(SARA-R404M, SARA-R410M and SARA-N410) VUSB_DET USB detection pin Input DC voltage at VUSB_DET pin USB GDI DDC SIM ERS POS ADC USB D+/D- pins Input DC voltage at USB interface pins Generic digital interfaces Input DC voltage at Generic digital interfaces pins DDC interface SIM interface Input DC voltage at DDC interface pins Input DC voltage at SIM interface pins External reset input Input DC voltage at RESET_N pin Power-on input Input DC voltage at PWR_ON pin Antenna detection input Input DC voltage at ANT_DET pin

-0.5

-0.5

-0.5

-0.3

-0.3

-0.3

-0.3

-0.5

-0.5

-0.5 Rho_ANT Antenna ruggedness Output RF load mismatch ruggedness at ANT pins Tstg Storage temperature Table 6: Absolute maximum ratings

-40 6.0 5.2 5.5 3.6 2.3 2.3 3.5 2.1 2.1 4.3 10:1

+85 V V V V V V V V V V VSWR C The product is not protected against overvoltage or reversed voltages. If necessary, voltage spikes exceeding the voltage specifications given in the table above, must be limited to values within the specified boundaries by using appropriate protection devices. 4.1.1 Maximum ESD Parameter Min Typical Max Unit Remarks ESD sensitivity for all pins 1000 V Human Body Model according to JESD22-A114 Table 7: Maximum ESD ratings u-blox cellular modules are Electrostatic Sensitive Devices and require special precautions when handling. See section 7.4 for ESD handling instructions. UBX-16024152 - R11 Electrical specifications Page 20 of 41 SARA-R4/N4 series - Data Sheet 4.2 Operating conditions Unless otherwise indicated, all operating condition specifications are at an ambient temperature of +25 C. Operation beyond the operating conditions is not recommended and extended exposure beyond them may affect device reliability. 4.2.1 Operating temperature range Parameter Min. Typical Max. Unit Remarks Normal operating temperature 20 +25

+65 C Extended operating temperature 40

+85 C Normal operating temperature range

(fully functional and meet 3GPP specifications) Extended operating temperature range

(RF performance may be affected outside normal operating range, though module is fully functional) Table 8: Environmental conditions 4.2.2 Thermal parameters Symbol Parameter Min. Typical Max. Units Remarks M-A Module-to-Ambient thermal parameter 10 M-C Module-to-Case thermal parameter 2 C/W C/W Thermal characterization parameter M-A = (TM TA) / PH proportional to the temperature difference between the internal temperature sensor of the module I and the ambient temperature (TA), produced by the module heat power dissipation (PH), with the module mounted on a 79 x 62 x 1.41 mm 4-Layer PCB with a high coverage of copper, in still air conditions Thermal characterization parameter M-C = TM - TC) / PH proportional to the temperature difference between the internal temperature sensor of the modI(TM) and the ambient temperature (TC), produced by the module heat power dissipation (PH), with the module mounted on a 79 x 62 x 1.41 mm 4-Layer PCB with a high coverage of copper, with a robust aluminum heat-sink and with forced air ventilation, i.e. reducing to a value close to 0 C/W the thermal resistance from the case of the module to the ambient Table 9: Thermal characterization parameters of the module UBX-16024152 - R11 Electrical specifications Page 21 of 41 SARA-R4/N4 series - Data Sheet 4.2.3 Supply/power pins Symbol Parameter Module Min. Typical Max. Unit VCC Module supply normal operating input voltage 9 SARA-R404M SARA-R410M SARA-N410 SARA-R412M SARA-R404M SARA-R410M SARA-N410 3.2 3.8 4.2 V 3.2 3.0 3.8 3.8 4.5 4.3 V V Module supply extended operating input voltage 10 SARA-R412M 3.0 3.8 4.5 V Table 10: Input characteristics of the Supply/Power pins Symbol Parameter Module Min. Typical Max. Unit VSIM SIM supply output voltage with 1.8 V external SIM SIM supply output voltage with 3.0 V external SIM V_INT Generic Digital Interfaces supply output voltage All All All I_INT Generic Digital Interfaces supply output current capability All Table 11: Output characteristics of the Supply/Power pins 1.80 2.95 1.80 V V V 70 mA 9 Input voltage at VCC must be above the normal operating range minimum limit to switch on the module. RF performance may be affected when the input voltage at VCC drops below the herein stated normal operating range minimum limit, though the module is still fully functional. 10 Ensure that input voltage at VCC never drops below the extended operating range minimum limit during module operation:

the cellular module may switch off when the VCC voltage value drops below the herein stated extended operating range minimum limit.11 Typical values with a matched antenna. UBX-16024152 - R11 Electrical specifications Page 22 of 41 SARA-R4/N4 series - Data Sheet 4.2.4 Current consumption Condition Tx power Min Typ11 Max12 Unit Mode Power Off Mode

(module switched off) PSM Deep Sleep Mode

(low power mode) Active Mode

(Power Saving Mode disabled, Module registered with network) LTE Cat NB1 Connected Mode

(Data Tx / Rx) LTE Cat M1 Connected Mode

(Data Tx / Rx) Averaged current value Averaged current value Averaged current value Averaged current value Minimum 0 dBm 12 dBm 18 dBm Maximum Peak current value during Tx Maximum Averaged current value Minimum 0 dBm 12 dBm 18 dBm Maximum 6 8 9 60 65 80 100 140 100 105 125 150 190 490 490 200 A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1.5 1.9 A 2G Connected Mode

(Data Tx / Rx) Peak current value during Tx Maximum Averaged current during a GMSK 1-

slot Tx call, 850/900 MHz bands Maximum Peak current during a GMSK 1-slot Tx burst, 850/900 MHz bands Maximum Table 12: Module VCC current consumption 13 11 Typical values with a matched antenna. 12 Maximum values with a mismatched antenna.13 All values with VCC = 3.8 V, with UART connected and USB disconnected. 13 All values with VCC = 3.8 V, with UART connected and USB disconnected. UBX-16024152 - R11 Electrical specifications Page 23 of 41 SARA-R4/N4 series - Data Sheet 4.2.5 LTE RF characteristics The LTE bands supported by SARA-R4/N4 series modules are defined in Table 2, while the following Table 13 describes the Transmitting and Receiving frequencies according to 3GPP TS 36.521-1 [7]. Parameter Min. Max. Frequency range FDD Band 12 (700 MHz) Frequency range FDD Band 17 (700 MHz) Frequency range FDD Band 28 (700 MHz) Frequency range FDD Band 13 (700 MHz) Frequency range FDD Band 20 (800 MHz) Frequency range FDD Band 26 (850 MHz) Frequency range FDD Band 18 (850 MHz) Frequency range FDD Band 5 (850 MHz) Frequency range FDD Band 19 (850 MHz) Frequency range FDD Band 8 (900 MHz) Frequency range FDD Band 4 (1700 MHz) Frequency range FDD Band 3 (1800 MHz) Frequency range FDD Band 2 (1900 MHz) Frequency range FDD Band 25 (1900 MHz) Frequency range TDD Band 39 (1900 MHz)14 Frequency range FDD Band 1 (2100 MHz) Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink 699 729 704 734 703 758 777 746 832 791 814 859 815 860 824 869 830 875 880 925 1710 2110 1710 1805 1850 1930 1850 1930 1880 1880 1920 2110 Table 13: LTE operating RF frequency bands 716 746 716 746 748 803 787 756 862 821 849 894 830 875 849 894 845 890 915 960 1755 2155 1785 1880 1910 1990 1915 1995 1920 1920 1980 2170 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Remarks Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive Module transmit Module receive SARA-R4/N4 series modules include a UE Power Class 3 LTE Cat M1 / NB1 transmitter (see Table 2), with output power and characteristics according to 3GPP TS 36.521-1 [7]. SARA-R4/N4 series modules LTE receiver characteristics are compliant to 3GPP TS 36.521-1 [7], with LTE conducted receiver sensitivity performance described in Table 14 and Table 15. 14 Supported in LTE category M1 only UBX-16024152 - R11 Electrical specifications Page 24 of 41 SARA-R4/N4 series - Data Sheet Parameter Min. Typical Max. Receiver input sensitivity Band 12 / 17 (700 MHz) Receiver input sensitivity Band 28 (700 MHz) Receiver input sensitivity Band 13 (700 MHz) Receiver input sensitivity Band 20 (800 MHz) Receiver input sensitivity Band 5 / 18 / 19 / 26 (850 MHz) Receiver input sensitivity Band 8 (900 MHz) Receiver input sensitivity Band 4 (1700 MHz) Receiver input sensitivity Band 3 (1800 MHz) Receiver input sensitivity Band 2 / 25 (1900 MHz) Receiver input sensitivity Band 1 (2100 MHz) 107.0 105.0 105.0 105.0 105.5 106.5 107.5 106.0 106.0 107.5 Unit dBm Remarks Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions Condition: 50 source, throughput > 95%, QPSK modulation, other settings as per 3GPP TS 36.521-1 [7]

Table 14: LTE Cat M1 receiver sensitivity performance Parameter Receiver input sensitivity Band 12 / 17 (700 MHz) Receiver input sensitivity Band 28 (700 MHz) Receiver input sensitivity Band 13 (700 MHz) Receiver input sensitivity Band 20 (800 MHz) Receiver input sensitivity Band 5 / 18 / 19 / 26 (850 MHz) Receiver input sensitivity Band 8 (900 MHz) Receiver input sensitivity Band 4 (1700 MHz) Receiver input sensitivity Band 3 (1800 MHz) Receiver input sensitivity Band 2 / 25 (1900 MHz) Receiver input sensitivity Band 1 (2100 MHz) Min. Typical Max. 113.5 112.0 112.0 112.0 112.5 113.0 114.0 113.0 113.0 114.0 Unit dBm Remarks Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions dBm Without repetitions Condition: 50 source, throughput > 95%, other settings as per 3GPP TS 36.521-1 [7]

Table 15: LTE Cat NB1 receiver sensitivity performance UBX-16024152 - R11 Electrical specifications Page 25 of 41 SARA-R4/N4 series - Data Sheet 4.2.6 2G RF characteristics The 2G bands supported by SARA-R4/N4 series modules are defined in Table 2, while the following Table 16 describes the Transmitting and Receiving frequencies according to 3GPP TS 51.010-1 [8]. Parameter Frequency range GSM 850 Frequency range E-GSM 900 Frequency range DCS 1800 Frequency range PCS 1900 Uplink Downlink Uplink Downlink Uplink Downlink Uplink Downlink Min 824 869 880 925 1710 1805 1850 1930 Max 849 894 915 960 1785 1880 1910 1990 Unit Remarks MHz Module transmit MHz Module receive MHz Module transmit MHz Module receive MHz Module transmit MHz Module receive MHz Module transmit MHz Module receive Table 16: 2G operating RF frequency bands SARA-R4/N4 series modules include a GMSK Power Class 4 transmitter for GSM 850 and E-GSM 900 bands, a GMSK Power Class 1 transmitter for DCS 1800 and PCS 1900 bands, a 8-PSK Power Class E2 transmitter for all 2G bands (see Table 2), with output power and characteristics according to 3GPP TS 51.010-1 [8]. SARA-R4/N4 series modules 2G receiver characteristics are compliant to 3GPP TS 51.010-1 [8], with conducted receiver sensitivity performance described in Table 17. Parameter Receiver input sensitivity GSM 850 Receiver input sensitivity E-GSM 900 Receiver input sensitivity DCS 1800 Receiver input sensitivity PCS 1900 Condition: 50 source Min Typical Max

-109

-109

-109

-109 Unit dBm Remarks Downlink RF level @ BER Class II < 2.4 %

dBm Downlink RF level @ BER Class II < 2.4 %

dBm Downlink RF level @ BER Class II < 2.4 %

dBm Downlink RF level @ BER Class II < 2.4 %

Table 17: 2G receiver sensitivity performance 4.2.7 ANT_DET pin characteristics Pin Name Parameter Min. Typ. Max. Unit Remarks ANT_DET Output DC current pulse value Output DC current pulse time length 35 1160 A s Table 18: ANT_DET pin characteristics UBX-16024152 - R11 Electrical specifications Page 26 of 41 SARA-R4/N4 series - Data Sheet 4.2.8 PWR_ON pin Parameter Min. Typical Max. Unit Remarks Internal supply for PWR_ON Input Signal 1.8 V The PWR_ON input is pulled up to an internal voltage rail minus a diode drop: the voltage value present at PWR_ON input pin is normally 0.8 V typical. Low-level input

-0.30 Pull-up resistance 150 200 Input leakage current

-0.20 PWR_ON low time 0.15 0.15 1.50 Table 19: PWR_ON pin characteristics 4.2.9 RESET_N pin 0.35 250 0.20 3.20 3.20 V k A s s s Internal active pull-up Low time to switch on the module from power off mode Low time to wake-up the module from PSM deep sleep Low time to switch off the module Parameter Min. Typical Max. Unit Remarks Internal supply for RESET_N Input Signal Low-level input

-0.30 Pull-up resistance Input leakage current

-0.20 RESET_N low time 10 1.8 37 Table 20: RESET_N pin characteristics 4.2.10 SIM pins 0.63 0.20 V V k A s Internal active pull-up Low time to switch off the module The SIM pins are a dedicated interface to the external SIM card/chip. The electrical characteristics fulfill the regulatory specification requirements. The values in Table 21 are for information only. Parameter Low-level input High-level input Low-level output High-level output Min.

-0.30 0.7*VSIM 0 0.8*VSIM VSIM Internal pull-up resistor on SIM_IO Input leakage current Clock frequency on SIM_CLK

-2 Table 21: SIM pin characteristics 4.7 4.8 Typ. Max. Unit Remarks 0.2*VSIM V VSIM+0.3 V 0.4 2 V V k A Max value at IOL = +2.0 mA Max value at IOL = +2.0 mA Internal pull-up to VSIM supply VIN =0 V or VIN =VSIM MHz UBX-16024152 - R11 Electrical specifications Page 27 of 41 SARA-R4/N4 series - Data Sheet 4.2.11 USB pins USB data lines (USB_D+/ USB_D) are compliant to the USB 2.0 high-speed specification. See the Universal Serial Bus Revision 2.0 specification [10] for detailed electrical characteristics. Parameter Min. Typical Max. Unit Remarks USB detection voltage on pin VUSB_DET 4.40 5.00 5.25 V High-speed squelch detection threshold

(input differential signal amplitude) High speed disconnect detection threshold

(input differential signal amplitude) High-speed data signaling input common mode voltage range High-speed idle output level High-speed data signaling output high level High-speed data signaling output low level Chirp J level (output differential voltage) Chirp K level (output differential voltage) Table 22: USB pin characteristics 100 525

-50

-10 360

-10 700

-900 150 mV 625 mV 500 mV 10 440 10 1100

-500 mV mV mV mV mV 4.2.12 Generic Digital Interfaces pins Parameter Min Typical Max Unit Remarks 1.80 0.00 1.80 0.00 1.80 0.63 2.10 0.45 1 390 V V V V V A k Digital I/O Interfaces supply (V_INT) Max value at IOL = +2.0 mA Min value at IOH = 2.0 mA VIN =0 V or VIN =1.8V Internal supply for GDI domain

-0.30 1.17 1.35

-1 55 Low-level input High-level input Low-level output High-level output Input leakage current Internal pull-up / pull-down resistance Table 23: GDI pin characteristics 4.2.13 DDC (I2C) pins DDC (I2C) lines (SCL and SDA) are compliant to the I2C-bus standard mode specification. See the I2C-Bus Specification [11] for detailed electrical characteristics. Parameter Min Typical Max Unit Remarks Internal supply for GDI domain Low-level input High-level input Low-level output Internal pull-up resistance Input/output leakage current Clock frequency on SCL

-0.30 1.17

-1 Table 24: DDC (I2C) pin characteristics 1.80 0.00 1.80 0.00 2.2 100 0.63 2.10 0.45 1 V V V V k A Digital I/O Interfaces supply (V_INT) Max value at IOL = +2.0 mA VIN =0 V or VIN =1.8V kHz UBX-16024152 - R11 Electrical specifications Page 28 of 41 SARA-R4/N4 series - Data Sheet 5 Mechanical specifications Figure 3: SARA-R4/N4 series dimensions (bottom and side views) Parameter Description Typical Tolerance A B C D E F G H1 H2 I J1 J2 K L M1 M2 N O P Q R Module Height [mm]

Module Width [mm]

Module Thickness [mm]

Horizontal Edge to Lateral Pin Pitch [mm]

Vertical Edge to Lateral Pin Pitch [mm]

Edge to Lateral Pin Pitch [mm]

Lateral Pin to Pin Pitch [mm]

Lateral Pin Height [mm]

Lateral Pin close to ANT Height [mm]

Lateral Pin Width [mm]

Lateral Pin to Pin Distance [mm]

26.0 16.0 2.53 2.0 2.5 1.05 1.1 0.8 0.9 1.5 0.3 Lateral Pin to Pin close to ANT Distance [mm] 0.2 Horizontal Edge to Central Pin Pitch [mm]

Vertical Edge to Central Pin Pitch [mm]

Central Pin to Pin Horizontal Pitch [mm]

Central Pin to Pin Horizontal Pitch [mm]

Central Pin to Pin Vertical Pitch [mm]

Central Pin Height and Width [mm]

2.75 2.75 1.8 3.6 2.1 1.1 Horizontal Edge to Pin 1 Indicator Pitch [mm] 0.9 Vertical Edge to Pin 1 Indicator Pitch [mm]

Pin 1 Indicator Height and Width [mm]

1.0 0.6

< 3

(1023.6 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

(629.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

(99.5 mil)

(78.7 mil)

(98.4 mil)

(41.3 mil)

(43.3 mil)

(31.5 mil)

(35.4 mil)

(59.1 mil)

(11.8 mil)

(7.9 mil)

(108.3 mil)

(108.3 mil)

(70.9 mil)

(141.7 mil)

(82.7 mil)

(43.3 mil)

(35.4 mil)

(39.4 mil)

(23.6 mil)

+0.25/-0.15

(+9.8/-5.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.02/-0.02

(+0.8/-0.8 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.20/-0.20

(+7.9/-7.9 mil)

+0.02/-0.02

(+0.8/-0.8 mil) Weight Module Weight [g]

Table 25: SARA-R4/N4 series dimensions The module height tolerance +/0.20 mm may be exceeded close to the corners of the PCB due to the cutting process: in the worst cases, the height could be +0.40 mm longer than the typical value. For information regarding Footprint and Paste Mask recommended for the application board integrating the cellular module, see the SARA-R4/N4 series System Integration Manual [2]. UBX-16024152 - R11 Mechanical specifications Page 29 of 41 CRRPQKM1M1M2EGH1J1H2J2J2H2EANT pinBPin 1 IndicatorKGH1J1ADDOOLNLIFF SARA-R4/N4 series - Data Sheet 6 Qualification and approvals 6.1 Reliability tests Tests for product family qualifications according to ISO 16750 Road vhicles - Environmental conditions and testing for electrical and electronic equipment, and appropriate standards. 6.1.1 Approvals Products marked with this lead-free symbol on the product label comply wth the "Directive 2002/95/EC of the European Parliament and the Council on the Restriction of Use of certain Hazardous Substances in Electrical and Electronic Euipment" (RoHS). SARA-R4/N4 series modules are RoHS compliant. No natural rubbers, hygroscopic materials, or materials containing asbestos are employed. Table 27 summarizes the main approvals for SARA-R4/N4 series modules. Certification SARA-R404M-00B SARA-R410M-01B SARA-R410M-02B SARA-R412M-02B SARA-N410-02B GCF PTCRB CE Europe FCC US FCC ID ISED Canada ISED ID IFT Mexico RCM Australia NCC Taiwan Verizon AT&T T-Mobile Bell Telus Telstra XPY2AGQN1NNN XPY2AGQN4NNN XPY2AGQN4NNN 8595A-2AGQN4NNN 8595A-2AGQN4NNN Table 26: SARA-R4/N4 series main certification approvals summary For guidelines and notices about compliance with certification approvals requirements integrating the SARA-R4/N4 series modules in the end-device, see the SARA-R4/N4 series System Integration Manual [2]. For the complete list of approvals and for specific details on all country, conformance and network operators certifications, including related certificates of compliancy, please contact the u-blox office or sales representative nearest you. UBX-16024152 - R11 Qualification and approvals Page 30 of 41 SARA-R4/N4 series - Data Sheet 7 Product handling & soldering 7.1 Packaging SARA-R4/N4 series modules are delivered as hermetically sealed, reeled tapes to enable efficient production, production lot set-up and tear-down. For more information about packaging, see the u-blox Package Information User Guide [3]. 7.1.1 Reels SARA-R4/N4 series modules are deliverable in quantities of 250 pieces on a reel. The modules are delivered using reel type B2 described in Figure 4 and in the u-blox Package Information Guide [3]. Figure 4: SARA-R4/N4 series modules reel Parameter Specification Reel Type Delivery Quantity B2 250 Table 27: Reel information for SARA-R4/N4 series modules Quantities of less than 250 pieces are also available. Contact u-blox for more information. UBX-16024152 - R11 Product handling & soldering Page 31 of 41 7.1.2 Tapes SARA-R4/N4 series - Data Sheet Figure 5 and Table 28 specify the dimensions of the tape used for the delivery of SARA-R4/N4 series modules. Figure 5: SARA-R4/N4 series modules tape Parameter Typical value Tolerance A0 B0 K0 16.8 26.8 3.2 0.2 0.2 0.2 Table 28: SARA-R4/N4 series tape dimensions (mm) Unit mm mm mm Note 1: 10 sprocket hole pitch cumulative tolerance 0.2 mm. Note 2: pocket position relative to sprocket hole is measured as true position of pocket, not pocket hole. Note 3: A0 and B0 are calculated on a plane at a distance R above the bottom of the pocket. UBX-16024152 - R11 Product handling & soldering Page 32 of 41 SARA-R4/N4 series - Data Sheet 7.2 Moisture Sensitivity Levels SARA-R4/N4 series modules are Moisture Sensitive Devices (MSD) in accordance to the IPC/JEDEC specification. The Moisture Sensitivity Level (MSL) relates to the packaging and handling precautions required. SARA-R4/N4 series modules are rated at MSL level 4. For more information regarding moisture sensitivity levels, labeling, storage and drying, see the u-blox Package Information Guide [3]. For the MSL standard, see IPC/JEDEC J-STD-020 (can be downloaded from www.jedec.org). 7.3 Reflow soldering Reflow profiles are to be selected according to u-blox recommendations (see the SARA-R4/N4 series System Integration Manual [2]). Failure to observe these recommendations can result in severe damage to the device!

7.4 ESD precautions SARA-R4/N4 series modules contain highly sensitive electronic circuitry and are Electrostatic Sensitive Devices (ESD). Handling SARA-R4/N4 series modules without proper ESD protection may destroy or damage them permanently. SARA-R4/N4 series modules are Electrostatic Sensitive Devices (ESD) and require special ESD precautions typically applied to ESD sensitive components. Table 7 details the maximum ESD ratings of the SARA-R4/N4 series modules. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the SARA-R4/N4 series module. ESD precautions should be implemented on the application board where the module is mounted, as described in the SARA-R4/N4 series System Integration Manual [2]. Failure to observe these recommendations can result in severe damage to the device!

UBX-16024152 - R11 Product handling & soldering Page 33 of 41 SARA-R4/N4 series - Data Sheet 8 Labeling and ordering information 8.1 Product labeling The labels of SARA-R4/N4 series modules include important product information as described in this section. Figure 6 illustrates the label of all the SARA-R4/N4 series modules, and includes: u-blox logo, production lot, Pb-free marking, product type number, IMEI number, certification information, and production country. Figure 6: SARA-R4/N4 series module label 8.2 Explanation of codes Three different product code formats are used. The Product Name is used in documentation such as this data sheet and identifies all the u-blox products, independent of packaging and quality grade. The Ordering Code includes options and quality, while the Type Number includes the hardware and firmware versions. Table 29 details these 3 different formats:

Format Product Name Ordering Code Type Number Structure PPPP-TGVV(L) PPPP-TGVV(L)-MMQ PPPP-TGVV(L)-MMQ-XX Table 29: Product code formats Table 30 explains the parts of the product code. Code PPPP TG VV

(L) MM Q XX Meaning Form factor Platform (Technology and Generation) Dominant technology: G: GSM; U: HSUPA; C: CDMA 1xRTT; N: NB-IoT (LTE Cat NB1);

R: LTE low data rate (Cat 1 and Cat M1); L: LTE high data rate (Cat 3 and above) Generation: 19 Variant function set based on the same platform: 0099 LTE category: 6,4,3,1,M Major product version: 0099 Product grade: B = professional, A = automotive Example SARA R4 04 M 00 B Minor product version (not relevant for certification) Default value is 00 Table 30: Part identification code UBX-16024152 - R11 Labeling and ordering information Page 34 of 41 SARA-xxxxxxxB-xxXXX: XXXXXXXXXXXXXXX: XXXXXXXXXXXX SARA-R4/N4 series - Data Sheet 8.3 Ordering information Ordering No. Product SARA-R404M-00B LTE Cat M1 module Designed for operation in LTE band 13 26.0 x 16.0 mm, 250 pieces/reel SARA-R410M-01B LTE Cat M1 module Designed for operation in LTE bands 2, 4, 5, 12 26.0 x 16.0 mm, 250 pieces/reel SARA-R410M-02B LTE Cat M1 / NB1 module Designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28 26.0 x 16.0 mm, 250 pieces/reel SARA-R412M-02B LTE Cat M1 / NB1 and 2G module Designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G bands 850, 900, 1800, 1900 26.0 x 16.0 mm, 250 pieces/reel SARA-N410-02B LTE Cat NB1 module Designed for operation in LTE bands 2, 4, 5, 12, 13 26.0 x 16.0 mm, 250 pieces/reel Table 31: Product ordering codes UBX-16024152 - R11 Labeling and ordering information Page 35 of 41 SARA-R4/N4 series - Data Sheet Appendix A Glossary Abbreviation Definition 2G 3G 3GPP 8PSK ADC AT BB BER Cat CBS CCC 2nd Generation Cellular Technology (GSM, GPRS, EGPRS) 3rd Generation Cellular Technology (UMTS, HSDPA, HSUPA) 3rd Generation Partnership Project 8-Phase Shift Keying modulation Analog to Digital Converter AT Command Interpreter Software Subsystem, or attention Baseband Bit Error Rate Category Cell Broadcast Service China Compulsory Certificate CDMA Code-Division Multiple Access CE CLK European Conformity Clock CMOS Complementary Metal-Oxide-Semiconductor CS CTS DC DCD DCS DDC DL DRX DSR DTE DTR DUN EDGE EDRX Chip Select Clear To Send Direct Current Data Carrier Detect Digital Cellular System Display Data Channel Down Link (Reception) Discontinuous Reception Data Set Ready Data Terminal Equipment Data Terminal Ready Dial-Up Networking Enhanced Data rates for GSM Evolution (EGPRS) Extended Discontinuous Reception EGPRS Enhanced General Packet Radio Service (EDGE) ERS ESD External Reset Signal Electrostatic Discharge E-UTRA Evolved Universal Terrestrial Radio Access FCC FDD FOAT FOTA FTP FW GCF GDI Federal Communications Commission United States Frequency Division Duplex Firmware (update) Over AT commands Firmware (update) Over-The-Air File Transfer Protocol Firmware Global Certification Forum Generic Digital Interface UBX-16024152 - R11 Labeling and ordering information Page 36 of 41 SARA-R4/N4 series - Data Sheet Abbreviation Definition GMSK GND GNSS GPIO GPRS GSM HDLC HSDPA HSUPA HTTP HW IEC IFT I2C I2S I/O IMEI IP ISED ISO ITU LGA LPWA LTE Gaussian Minimum-Shift Keying modulation Ground Global Navigation Satellite System General Purpose Input/Output General Packet Radio Services Global System for Mobile communications High-level Data Link Control High Speed Downlink Packet Access High Speed Uplink Packet Access HyperText Transfer Protocol Hardware International Electrotechnical Commission Federal Telecommunications Institute Mexico Inter-Integrated Circuit Inter-IC Sound Input/Output International Mobile Equipment Identity Internet Protocol Innovation, Science and Economic Development Canada International Organization for Standardization International Telecommunications Union Land Grid Array Low Power Wide Area Long-Term Evolution LWM2M Open Mobile Alliance Lightweight Machine-to-Machine protocol M2M MISO MOSI MQTT MSD MSL MUX N/A NCC PA PCB PCN PMU POS PPS PSM PTCRB QPSK RAM RAT RF Machine to Machine Multiple Input Single Output Master Output Slave Input Message Queuing Telemetry Transport Moisture Sensitive Device Moisture Sensitivity Level Multiplexer Not Applicable National Communications Commission Taiwan Power Amplifier Printed Circuit Board Product Change Notification / Sample Delivery Note / Information Note Power Management Unit Power On Signal Protocol and Parameter Selection Power Saving Mode PCS Type Certification Review Board Quadrature Phase Shift Keying modulation Random Access Memory Radio Access Technology Radio Frequency UBX-16024152 - R11 Labeling and ordering information Page 37 of 41 SARA-R4/N4 series - Data Sheet Abbreviation Definition RI RIL RTS SCL SDA SDIO SIM SMS SPI SRRC SSL TA TCP TDD TLS TS TXD Ring Indicator Radio Interface Layer Request To Send Serial Clock Serial Data Secure Digital Input Output Subscriber Identity Module Short Message Service Serial Peripheral Interface State Radio Regulation Committee China Secure Socket Layer Timing Advance Transmission Control Protocol Time Division Duplex Transport Layer Security Technical Specification Transmit Data UART Universal Asynchronous Receiver/Transmitter UBX UDP UE UL UMTS USB VoLTE VSWR WA u-blox proprietary messaging protocol User Datagram Protocol User Equipment Uplink (Transmission) Universal Mobile Telecommunications System Universal Serial Bus Voice over LTE Voltage Standing Wave Ratio Word Alignment Table 32: Explanation of the abbreviations and terms used UBX-16024152 - R11 Labeling and ordering information Page 38 of 41 SARA-R4/N4 series - Data Sheet Related documents

[1] u-blox SARA-R4/N4 series AT Commands Manual, Doc. No. UBX-17003787

[2] u-blox SARA-R4/N4 series System Integration Manual, Doc. No. UBX-16029218

[3] u-blox Package Information User Guide, Doc. No. UBX-14001652

[4] 3GPP TS 27.007 - AT command set for User Equipment (UE)

[5] 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating Equipment

(DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS)

[6] 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol

[7] 3GPP TS 36.521-1 - Evolved Universal Terrestrial Radio Access; User Equipment conformance specification; Radio transmission and reception; Part 1: Conformance Testing

[8] 3GPP TS 51.010-1 - Mobile Station conformance specification; Part 1: Conformance specification

[9] ITU-T Recommendation V24, 02-2000. List of definitions for interchange circuits between Data Terminal Equipment (DTE) and Data Connection Equipment (DCE)

[10] Universal Serial Bus Revision 2.0 specification, www.usb.org/developers/docs/usb20_docs/

[11] I2C-bus specification and user manual - Rev.5- 9 October 2012 - NXP Semiconductors, www.nxp.com/documents/user_manual/UM10204.pdf For regular updates to u-blox documentation and to receive product change notifications, register on our homepage (www.u-blox.com). UBX-16024152 - R11 Related documents Page 39 of 41 SARA-R4/N4 series - Data Sheet Revision history Revision Date Name Comments R01 R02 R03 R04 R05 R06 R07 07-Oct-2016 02-Feb-2017 sfal sfal Initial release Updated supported features and electrical characteristics 05-May-2017 sfal / sses Updated supported features and electrical characteristics Added the SARA-R410M-01B product version 24-May-2017 sses Updated supported features and electrical characteristics 19-Jul-2017 sses Updated supported features and electrical characteristics 17-Aug-2017 sses Updated supported features for 02 product version Extended document applicability to SARA-R410M-02B product version 30-Oct-2017 sses R08 04-Jan-2018 sses Updated SARA-R410M-01B product status Updated supported features for 02 product version Updated SARA-R410M-02B product status Updated USB, GPIO and other features description R09 26-Feb-2018 sses Updated SARA-R410M-02B product status Extended document applicability to SARA-R412M-02B product version Added Current consumption, Rx sensitivity and Thermal figures Updated UART MUX and Approvals info 07-Mar-2018 mbab u-blox rebranding. Updated SARA-R412M-02B modem and app version 09-May-2018 sses Updated SARA-R410M-02B product status Extended document applicability to SARA-N410-02B product version Updated UART and Approvals info R10 R11 UBX-16024152 - R11 Revision history Page 40 of 41 SARA-R4/N4 series - Data Sheet Contact For complete contact information, visit us at www.u-blox.com. u-blox Offices North, Central and South America Headquarters Asia, Australia, Pacific Europe, Middle East, Africa u-blox AG Phone: +41 44 722 74 44 E-mail:

Support: support@u-blox.com info@u-blox.com u-blox America, Inc. Phone: +1 703 483 3180 E-mail:

info_us@u-blox.com Regional Office West Coast:

Phone: +1 408 573 3640 E-mail:

info_us@u-blox.com Technical Support:

Phone: +1 703 483 3185 E-mail: support@u-blox.com u-blox Singapore Pte. Ltd. Phone: +65 6734 3811 E-mail:

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SARA-R4 series LTE Cat M1 / NB1 and EGPRS modules System Integration Manual Abstract This document describes the features and the system integration of the size-optimized SARA-R4 series cellular modules. These modules are a complete, cost efficient, performance optimized, multi-mode and multi-band LTE Cat M1 / NB1 and EGPRS solution in the compact SARA form factor. www.u-blox.com UBX-16029218 - R09 SARA-R4 series - System Integration Manual Document Information Title Subtitle SARA-R4 series LTE Cat M1 / NB1 and EGPRS modules Document type System Integration Manual Document number UBX-16029218 Revision and date R09 Disclosure restriction Product Status Corresponding content status 09-May-2018 Functional Sample Draft For functional testing. Revised and supplementary data will be published later. In Development /

Prototype Objective Specification Target values. Revised and supplementary data will be published later. Engineering Sample Advance Information Data based on early testing. Revised and supplementary data will be published later. Initial Production Early Prod. Information Data from product verification. Revised and supplementary data may be published later. Mass Production /

End of Life Production Information Final product specification. This document applies to the following products:

Name Type number Firmware version Application version PCN reference Product Status SARA-R404M SARA-R410M SARA-R404M-00B-00 K0.0.00.00.07.06 SARA-R410M-01B-00 L0.0.00.00.02.03 SARA-R410M-02B-00 L0.0.00.00.05.06 SARA-R412M SARA-R412M-02B-00 M0.03.00 N/A N/A A02.00 A01.03 UBX-17047084 Initial Production UBX-17051617 Initial Production UBX-18010263 Initial Production UBX-18017915 Prototype u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited. The information contained herein is provided as is and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com. Copyright 2018, u-blox AG u-blox is a registered trademark of u-blox Holding AG in the EU and other countries.. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners. UBX-16029218 - R09 Page 2 of 115 SARA-R4 series - System Integration Manual Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development. AT Commands Manual: This document provides the description of the AT commands supported by the u-blox cellular modules. System Integration Manual: This document provides the description of u-blox cellular modules system from the hardware and the software point of view, it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules. Application Note: These documents provide guidelines and information on specific hardware and/or software topics on u-blox cellular modules. See Related documents for a list of Application Notes related to your Cellular Module. How to use this Manual The SARA-R4 series System Integration Manual provides the necessary information to successfully design and configure the u-blox cellular modules. This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance. A warning symbol indicates actions that could negatively impact or damage the module. Questions If you have any questions about u-blox Cellular Integration:

Read this manual carefully. Contact our information service on the homepage http://www.u-blox.com/

Technical Support Worldwide Web Our website (http://www.u-blox.com/) is a rich pool of information. Product information, technical documents can be accessed 24h a day. By E-mail Contact the closest Technical Support office by email. Use our service pool email addresses rather than any personal email address of our staff. This makes sure that your request is processed as soon as possible. You will find the contact details at the end of the document. Helpful Information when Contacting Technical Support When contacting Technical Support, have the following information ready:

Module type (SARA-R404M) and firmware version Module configuration Clear description of your question or the problem A short description of the application Your complete contact details UBX-16029218 - R09 Preface Page 3 of 115 SARA-R4 series - System Integration Manual Contents Preface ................................................................................................................................ 3 Contents .............................................................................................................................. 4 1.8 1.7 1.6 1.8.1 1.8.2 1.7.1 1.7.2 1 System description ....................................................................................................... 7 1.1 Overview .............................................................................................................................................. 7 1.2 Architecture ........................................................................................................................................ 10 1.3 Pin-out ............................................................................................................................................... 11 1.4 Operating modes ................................................................................................................................ 15 Supply interfaces ................................................................................................................................ 17 1.5 1.5.1 Module supply input (VCC) ......................................................................................................... 17 Generic digital interfaces supply output (V_INT) ........................................................................... 22 1.5.2 System function interfaces .................................................................................................................. 23 1.6.1 Module power-on ....................................................................................................................... 23 1.6.2 Module power-off ....................................................................................................................... 24 1.6.3 Module reset ............................................................................................................................... 25 Antenna interface ............................................................................................................................... 26 Antenna RF interface (ANT) ......................................................................................................... 26 Antenna detection interface (ANT_DET) ...................................................................................... 27 SIM interface ...................................................................................................................................... 27 SIM interface ............................................................................................................................... 27 SIM detection interface ............................................................................................................... 27 Data communication interfaces .......................................................................................................... 28 UART interface ............................................................................................................................ 28 USB interface............................................................................................................................... 30 SPI interface ................................................................................................................................ 31 SDIO interface ............................................................................................................................. 31 DDC (I2C) interface ...................................................................................................................... 31 1.10 Audio ................................................................................................................................................. 31 1.11 General Purpose Input/Output ............................................................................................................ 32 1.12 Reserved pins (RSVD) .......................................................................................................................... 32 1.13 System features .................................................................................................................................. 33 1.13.1 Network indication ...................................................................................................................... 33 1.13.2 Antenna supervisor ..................................................................................................................... 33 1.13.3 Dual stack IPv4/IPv6 ..................................................................................................................... 33 1.13.4 TCP/IP and UDP/IP ....................................................................................................................... 33 1.13.5 FTP .............................................................................................................................................. 33 1.13.6 HTTP ........................................................................................................................................... 34 Firmware update Over AT (FOAT) ................................................................................................ 34 1.13.7 1.13.8 Firmware update Over The Air (uFOTA) ....................................................................................... 34 1.13.9 Power saving ............................................................................................................................... 34 1.9.1 1.9.2 1.9.3 1.9.4 1.9.5 1.9 UBX-16029218 - R09 Contents Page 4 of 115 SARA-R4 series - System Integration Manual 2.6 2.5 2.4 2.3 2.5.1 2.5.2 2.4.1 2.4.2 2 Design-in ..................................................................................................................... 37 2.1 Overview ............................................................................................................................................ 37 2.2 Supply interfaces ................................................................................................................................ 38 2.2.1 Module supply (VCC) .................................................................................................................. 38 2.2.2 Generic digital interfaces supply output (V_INT) ........................................................................... 54 System functions interfaces ................................................................................................................ 55 2.3.1 Module power-on (PWR_ON) ...................................................................................................... 55 2.3.2 Module reset (RESET_N) .............................................................................................................. 56 Antenna interface ............................................................................................................................... 57 Antenna RF interface (ANT) ......................................................................................................... 57 Antenna detection interface (ANT_DET) ...................................................................................... 64 SIM interface ...................................................................................................................................... 67 Guidelines for SIM circuit design.................................................................................................. 67 Guidelines for SIM layout design ................................................................................................. 71 Data communication interfaces .......................................................................................................... 72 UART interface ............................................................................................................................ 72 USB interface............................................................................................................................... 77 SPI interface ................................................................................................................................ 79 SDIO interface ............................................................................................................................. 79 DDC (I2C) interface ...................................................................................................................... 79 2.7 Audio ................................................................................................................................................. 82 2.8 General Purpose Input/Output ............................................................................................................ 82 2.9 Reserved pins (RSVD) .......................................................................................................................... 83 2.10 Module placement.............................................................................................................................. 83 2.11 Module footprint and paste mask ....................................................................................................... 84 2.12 Thermal guidelines.............................................................................................................................. 85 2.13 Schematic for SARA-R4 series module integration .............................................................................. 86 2.13.1 Schematic for SARA-R4 series modules ........................................................................................ 86 2.14 Design-in checklist .............................................................................................................................. 87 2.14.1 Schematic checklist ..................................................................................................................... 87 2.14.2 Layout checklist ........................................................................................................................... 88 2.14.3 Antenna checklist ........................................................................................................................ 88 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 3.1 3.2 3.3 3 Handling and soldering ............................................................................................. 89 Packaging, shipping, storage and moisture preconditioning ............................................................... 89 Handling ............................................................................................................................................. 89 Soldering ............................................................................................................................................ 90 Soldering paste............................................................................................................................ 90 3.3.1 Reflow soldering ......................................................................................................................... 90 3.3.2 Optical inspection ........................................................................................................................ 91 3.3.3 Cleaning ...................................................................................................................................... 91 3.3.4 3.3.5 Repeated reflow soldering ........................................................................................................... 91 3.3.6 Wave soldering............................................................................................................................ 92 Hand soldering ............................................................................................................................ 92 3.3.7 UBX-16029218 - R09 Contents Page 5 of 115 SARA-R4 series - System Integration Manual Rework ........................................................................................................................................ 92 3.3.8 3.3.9 Conformal coating ...................................................................................................................... 92 3.3.10 Casting ........................................................................................................................................ 92 3.3.11 Grounding metal covers .............................................................................................................. 92 3.3.12 Use of ultrasonic processes .......................................................................................................... 92 4.1 4.2 4 Approvals .................................................................................................................... 93 Product certification approval overview ............................................................................................... 93 US Federal Communications Commission notice ................................................................................. 95 Safety warnings review the structure ........................................................................................... 95 4.2.1 4.2.2 Declaration of Conformity ........................................................................................................... 95 4.2.3 Modifications .............................................................................................................................. 96 Innovation, Science and Economic Development Canada notice ......................................................... 97 4.3.1 Declaration of Conformity ........................................................................................................... 97 4.3.2 Modifications .............................................................................................................................. 97 European Conformance CE mark ........................................................................................................ 99 Taiwanese National Communication Commission ............................................................................. 100 4.4 4.5 4.3 5.1 5.2 5 Product testing ......................................................................................................... 101 u-blox in-series production test ......................................................................................................... 101 Test parameters for OEM manufacturers........................................................................................... 102 Go/No go tests for integrated devices .................................................................................... 102 RF functional tests ..................................................................................................................... 102 5.2.1 5.2.2 Appendix ........................................................................................................................ 104 A Migration between SARA modules ......................................................................... 104 A.1 Overview .......................................................................................................................................... 104 A.2 Pin-out comparison between the SARA-G3, SARA-U2, SARA-R4 and SARA-N2 modules .................. 106 B Glossary .................................................................................................................... 111 Related documents......................................................................................................... 113 Revision history .............................................................................................................. 114 Contact ............................................................................................................................ 115 UBX-16029218 - R09 Contents Page 6 of 115 SARA-R4 series - System Integration Manual 1 System description 1.1 Overview The SARA-R4 series comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode modules in the miniature SARA LGA form-factor (26.0 x 16.0 mm, 96-pin), that allows an easy integration in compact designs and a seamless drop-in migration from u-blox cellular module families. SARA-R4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module families and are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates migration from the u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules, maximizes customer investments, simplifies logistics, and enables very short time-to-market. The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices that require long battery lifetimes, such as connected health, smart metering, smart cities and wearables. SARA-R4 series includes the following modules:

SARA-R404M LTE Cat M1 single-band modules designed primarily to operate on Verizon network SARA-R410M-01B LTE Cat M1 quad-band modules designed primarily to operate on AT&T network SARA-R410M-02B LTE Cat M1 / LTE Cat NB1 multi-mode and multi-band modules, with software-based bands configurability for worldwide operation SARA-R412M-02B LTE Cat M1 / LTE Cat NB1 / (E)GPRS / GSM multi-mode and multi-band modules, with software-based bands configurability for worldwide operation The modules support handover capability and delivers the technology necessary for use in applications such as vehicle, asset and people tracking where mobility is a pre-requisite. Other applications where the modules are well-

suited include and are not limited to: smart home, security systems, industrial monitoring and control. The modules support data communication over an extended operating temperature range of 40 to +85 C, with extremely low power consumption, and with coverage enhancement for deeper range into buildings and basements (and underground with NB1). Table 1 summarizes the main features and interfaces of SARA-R4 series modules. Model Region Bands Positioning Interfaces Audio Features Grade e n i l e s a B e s a e e R P P G 3 l y r o g e t a c E T L P P G 3 d n a b

-

4 S R P G

) E

(

/

M S G e r a w t f o s w o N t s i s s A m e d o m a i v S S N G s d n a b D D F E T L e t a c o L l l e C 0

. 2 B S U T R A U SARA-R404M USA 13 M1 13 SARA-R410M-01B N. America 13 M1 2,4 5,12 SARA-R410M-02B Global 13 SARA-R412M-02B Global 13 M1 NB1 M1 NB1

*

*

k c a t s P D U

/

P C T d e d d e b m E r o s i v r e p u s a n n e t n A P T F

, P T T H d e d d e b m E 6 v P I

/

4 v P I k c a t s l a u D e d o M g n i v a S r e w o P X R D e

) A T O F

(

r i a e h t r e v o e t a d p u W F l a n o i s s e f o r P e v i t o m o t u A d r a d n a t S i o d u a g o a n A l i o d u a l a t i g D i

) C 2 I

(

C D D s O P G I I O D S I P S

* = Bands 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1-only) = supported by all FW versions = supported by future FW versions Table 1: SARA-R4 series main features summary UBX-16029218 - R09 System description Page 7 of 115 SARA-R4 series - System Integration Manual Table 2 reports a summary of cellular radio access technologies characteristics and features of the modules. Item SARA-R404M SARA-R410M-01B SARA-R410M-02B SARA-R412M-02B Protocol stack 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13 RAT LTE Cat M1 Half-Duplex LTE Cat M1 Half-Duplex Operating bands LTE FDD bands:

Band 13 (750 MHz) LTE FDD bands:

Band 12 (700 MHz) Band 5 (850 MHz) Band 4 (1700 MHz) Band 2 (1900 MHz) LTE Cat M1 Half-Duplex LTE Cat NB1 Half-Duplex LTE FDD bands:

Band 12 (700 MHz) Band 17 (700 MHz) Band 28 (700 MHz) Band 13 (700 MHz) Band 20 (800 MHz) Band 26 (850 MHz) Band 5 (850 MHz) Band 19 (850 MHz) Band 8 (900 MHz) Band 4 (1700 MHz) Band 3 (1800 MHz) Band 2 (1900 MHz) Band 25 (1900 MHz) Band 1 (2100 MHz) LTE TDD bands:

Band 39 (1900 MHz)1 Power class LTE Cat M1:

Class 3 (23 dBm) LTE category M1:

Class 3 (23 dBm) LTE Cat M1 / NB1:

Class 3 (23 dBm) Data rate LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category NB1:

up to 62.5 kb/s UL up to 27.2 kb/s DL LTE Cat M1 Half-Duplex LTE Cat NB1 Half-Duplex 2G GSM / GPRS / EGPRS LTE FDD bands:

Band 12 (700 MHz) Band 17 (700 MHz) Band 28 (700 MHz) Band 13 (700 MHz) Band 20 (800 MHz) Band 26 (850 MHz) Band 5 (850 MHz) Band 19 (850 MHz) Band 8 (900 MHz) Band 4 (1700 MHz) Band 3 (1800 MHz) Band 2 (1900 MHz) Band 25 (1900 MHz) Band 1 (2100 MHz) LTE TDD bands:

Band 39 (1900 MHz)1 2G bands:

GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz LTE category M1 / NB1:

Class 3 (23 dBm) 2G GMSK:

Class 4 (33 dBm) for GSM/E-GSM bands Class 1 (30 dBm) for DCS/PCS bands 2G 8-PSK:

Class E2 (27 dBm) for GSM/E-GSM bands Class E2 (26 dBm) for DCS/PCS bands LTE category M1:

up to 375 kb/s UL up to 300 kb/s DL LTE category NB1:

up to 62.5 kb/s UL up to 27.2 kb/s DL GPRS multi-slot class 332:

Up to 85.6 kb/s UL Up to 107 kb/s DL EGPRS multi-slot class 332:

Up to 236.8 kb/s UL Up to 296.0 kb/s DL Table 2: SARA-R4 series LTE Cat M1, LTE Cat NB1, EGPRS, GPRS and GSM characteristics summary 1 Supported in LTE category M1 only 2 GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in DL (reception) and 4 slots in UL (transmission) with 6 slots in total. UBX-16029218 - R09 System description Page 8 of 115 SARA-R4 series - System Integration Manual UBX-16029218 - R09 System description Page 9 of 115 SARA-R4 series - System Integration Manual 1.2 Architecture Figure 1 summarizes the internal architecture of SARA-R4 series modules. Figure 1: SARA-R4 series modules simplified block diagram SARA-R404M-00B and SARA-R410M-01B modules, i.e. the 00 and 01 product versions of the SARA-R4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o DDC (I2C) interface o SDIO interface o SPI interface o Digital audio interface SARA-R410M-02B and SARA-R412M-02B modules, i.e. the 02 product version of the SARA-R4 series modules, do not support the following interfaces, which should be left unconnected and should not be driven by external devices:

o SDIO interface o SPI interface o Digital audio interface UBX-16029218 - R09 System description Page 10 of 115 MemoryV_INTRF transceiverCellularBaseBandProcessorANTVCC (Supply)USBDDC (I2C)SIM card detectionSIMUARTPower-OnResetGPIOsAntenna detectionSwitchPA19.2 MHzPowerManagementFilterSDIOSPI / Digital Audio SARA-R4 series - System Integration Manual 1.3 Pin-out Table 3 lists the pin-out of the SARA-R4 series modules, with pins grouped by function. Function Pin Name Pin No I/O Description Remarks Power VCC 51, 52, 53 I Module supply input VCC supply circuit affects the RF performance and GND N/A Ground 1, 3, 5, 14, 20-22, 30, 32, 43, 50, 54, 55, 57-61, 63-96 V_INT 4 O Generic digital interfaces supply output Power-on input External reset input System PWR_ON 15 RESET_N 18 I I Antenna ANT 56 I/O Primary antenna ANT_DET 62 I Antenna detection SIM VSIM 41 O SIM supply output SIM_IO 39 I/O SIM data SIM_CLK 38 O SIM clock SIM_RST 40 O SIM reset compliance of the device integrating the module with applicable required certification schemes. See section 1.5.1 for functional description / requirements. See section 2.2.1 for external circuit design-in. GND pins are internally connected each other. External ground connection affects the RF and thermal performance of the device. See section 1.5.1 for functional description. See section 2.2.1 for external circuit design-in. V_INT = 1.8 V (typical) generated by internal regulator when the module is switched on, outside the low power PSM deep sleep mode. Test-Point for diagnostic access is recommended. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in. Internal 200 k pull-up resistor. Test-Point for diagnostic access is recommended. See section 1.6.1 for functional description. See section 2.3.1 for external circuit design-in. Internal 37 k pull-up resistor. Test-Point for diagnostic access is recommended. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in. Main Tx / Rx antenna interface. 50 nominal characteristic impedance. Antenna circuit affects the RF performance and application device compliance with required certification schemes. See section 1.7 for functional description / requirements. See section 2.4 for external circuit design-in. ADC for antenna presence detection function See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in. VSIM = 1.8 V / 3 V output as per the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in. Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in. 4.8 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. UBX-16029218 - R09 System description Page 11 of 115 SARA-R4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks UART RXD 13 O UART data output TXD 12 I UART data input O I O O I CTS 11 RTS 10 DSR RI DTR DCD 6 7 9 8 UART clear to send output UART ready to send input UART data terminal ready input O UART data carrier detect output USB VUSB_DET 17 I USB detect input USB_D-

28 I/O USB Data Line D-

USB_D+

29 I/O USB Data Line D+

UART data set ready output 1.8 V, Circuit 107 in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. UART ring indicator output 1.8 V, Circuit 125 in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for AT commands, data communication, FOAT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT commands, data communication, FOAT. Internal active pull-down to GND on 00, 02 versions Internal active pull-up to V_INT on 01 versions See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V output, Circuit 106 (CTS) in ITU-T V.24. Not supported by 00, 01 and R410M-02B product versions See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. Not supported by 00, 01 and R410M-02B product versions See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V, Circuit 108/2 in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. 1.8 V, Circuit 109 in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB interface for AT commands, data communication, FOAT, FW update by u-blox dedicated tool and diagnostics. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB interface for AT commands, data communication, FOAT, FW update by u-blox dedicated tool and diagnostics. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. UBX-16029218 - R09 System description Page 12 of 115 SARA-R4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks SPI I2S_WA /

SPI_MOSI 34 O SPI MOSI I2S_RXD /

SPI_MISO 37 I SPI MISO I2S_CLK /

SPI_CLK I2S_TXD /

SPI_CS 36 O SPI clock 35 O SPI Chip Select SDIO SDIO_D0 47 I/O SDIO serial data [0]

SDIO_D1 49 I/O SDIO serial data [1]

SDIO_D2 44 I/O SDIO serial data [2]

SDIO_D3 48 I/O SDIO serial data [3]

SDIO_CLK 45 O SDIO serial clock SDIO_CMD 46 I/O SDIO command DDC SCL 27 O I2C bus clock line SDA 26 I/O I2C bus data line SPI Master Output Slave Input, alternatively configurable as I2S word alignment Not supported by 00, 01 and 02 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. SPI Master Input Slave Output, alternatively configurable as I2S receive data Not supported by 00, 01 and 02 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. SPI clock, alternatively configurable as I2S clock Not supported by 00, 01 and 02 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. SPI Chip Select, alternatively configurable as I2S transmit data Not supported by 00, 01 and 02 product versions. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. Not supported by 00, 01 and 02 product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. 1.8 V open drain, for communication with I2C-slave devices. Internal pull-up to V_INT: external pull-up is not required. Not supported by 00 and 01 product versions. See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. 1.8 V open drain, for communication with I2C-slave devices. Internal pull-up to V_INT: external pull-up is not required. Not supported by 00 and 01 product versions. See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. UBX-16029218 - R09 System description Page 13 of 115 SARA-R4 series - System Integration Manual Function Pin Name Pin No I/O Description Remarks Audio I2S_TXD /

SPI_CS 35 O I2S transmit data I2S_RXD /

SPI_MISO 37 I I2S receive data I2S_CLK /

SPI_CLK 36 I/O I2S clock I2S_WA /

SPI_MOSI 34 I/O I2S word alignment GPIO GPIO1 16 I/O GPIO GPIO2 23 I/O GPIO GPIO3 24 I/O GPIO GPIO4 25 I/O GPIO GPIO5 42 I/O GPIO GPIO6 19 I/O GPIO Reserved RSVD 33 N/A Reserved pin RSVD 2, 31 N/A Reserved pin Table 3: SARA-R4 series module pin definition, grouped by function I2S transmit data, alternatively configurable as SPI Chip Select Not supported by 00, 01 and 02 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. I2S receive data, alternatively configurable as SPI Master Input Slave Output Not supported by 00, 01 and 02 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. I2S clock, alternatively configurable as SPI clock Not supported by 00, 01 and 02 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. I2S word alignment, alternatively configurable as SPI Master Output Slave Input Not supported by 00, 01 and 02 product versions. See section 1.10 for functional description. See section 2.7 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. 1.8 V GPIO with alternatively configurable functions. See section 1.11 for functional description. See section 2.8 for external circuit design-in. This pin can be connected to GND. See sections 1.12 and 2.9 Leave unconnected. See sections 1.12 and 2.9 UBX-16029218 - R09 System description Page 14 of 115 SARA-R4 series - System Integration Manual 1.4 Operating modes SARA-R4 series modules have several operating modes. The operating modes are defined in Table 4 and described in detail in Table 5, providing general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal Operation Deep-Sleep Mode RTC runs with 32 kHz reference internally generated. Active Mode Module processor core runs with 19.2 MHz reference generated by the internal oscillator Connected Mode RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference. Table 4: SARA-R4 series modules operating modes definition Mode Description Transition between operating modes Not-Powered Module is switched off. Application interfaces are not accessible. Power-Off Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible. Deep-Sleep Active Only the internal 32 kHz reference is active. The RF section and the application interfaces are temporarily disabled and switched off: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption. The module enters the low power deep sleep mode (entering the Power Saving Mode defined in 3GPP Rel.13) whenever possible, if power saving configuration is enabled by AT+CPSMS command (see the SARA-R4 series AT Commands Manual [2]), reducing current consumption (see 1.13.9). Power saving configuration is not enabled by default; it can be enabled by AT+CPSMS (see the SARA-R4 series AT Commands Manual [2]). Module is switched on with application interfaces enabled or not suspended: the module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by AT+CPSMS (see the SARA-R4 series AT Commands Manual [2]). When VCC supply is removed, the modules enter not-powered mode. When in not-powered mode, the module can enter power-off mode applying VCC supply (see 1.6.1). The modules enter power-off mode from active mode when the host processor implements a clean switch-off procedure, by sending the AT+CPWROFF command or by using the PWR_ON pin (see 1.6.2). When in power-off mode, the modules can be switched on by the host processor using the PWR_ON input pin (see 1.6.1). When in power-off mode, the modules enter not-powered mode by removing VCC supply. The modules automatically switch from the active mode to low power deep sleep mode whenever possible, upon expiration of the 6 seconds AT inactivity timer, and upon expiration of Active Timer, entering in the Power Saving Mode defined in 3GPP Rel.13, if power saving configuration is enabled (see 1.13.9 and the SARA-R4 series AT Commands Manual [2], AT+CPSMS command). When in low power deep sleep mode, the module switches on to the active mode upon expiration of Periodic Update Timer according to the Power Saving Mode defined in 3GPP Rel.13 (see 1.13.9 and the SARA-R4 series AT Commands Manual [2], AT+CPSMS command), or it can be switched on to the active mode by the host processor using the PWR_ON input pin (see section 1.6.1). The modules enter active mode from power-off mode when the host processor implements a clean switch-on procedure by using the PWR_ON pin (see 1.6.1). The modules enter active mode from low power deep sleep mode upon expiration of Periodic Update Timer (see 1.13.9), or when the host processor implements a clean switch-on procedure by using the PWR_ON pin (see 1.6.1). The modules enter power-off mode from active mode when the host processor implements a clean switch-off procedure (see 1.6.2). The modules automatically switch from active to low power deep sleep mode whenever possible, if power saving is enabled (see 1.13.9). The module switches from active to connected mode when a RF Tx/Rx data connection is initiated or when RF Tx/Rx activity is required due to a connection previously initiated. The module switches from connected to active mode when a RF Tx/Rx data connection is terminated or suspended. UBX-16029218 - R09 System description Page 15 of 115 SARA-R4 series - System Integration Manual Mode Description Transition between operating modes Connected RF Tx/Rx data connection is in progress. The module is prepared to accept data signals from an external device. When a data connection is initiated, the module enters connected mode from active mode. Connected mode is suspended if Tx/Rx data is not in progress. In such cases the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+CPSMS command, the module automatically switches to low power deep sleep mode whenever possible. Vice-versa, the module wakes up from low power deep sleep mode to active mode and then connected mode if RF Tx/Rx activity is necessary. When a data connection is terminated, the module returns to the active mode. Table 5: SARA-R4 series modules operating modes description Figure 2 describes the transition between the different operating modes. Figure 2: SARA-R4 series modules operating modes transitions UBX-16029218 - R09 System description Page 16 of 115 If power saving is enabled, if AT Inactivity Timer and Active Timer are expired Upon expiration of the Periodic Update Timer Using PWR_ON pinIncoming/outgoing data or other dedicated device network communicationNo RF Tx/Rx in progress, Communication droppedRemove VCCSwitch ON:PWR_ONNot poweredPower offActiveConnectedDeep SleepSwitch OFF:AT+CPWROFFPWR_ONApply VCC SARA-R4 series - System Integration Manual 1.5 Supply interfaces 1.5.1 Module supply input (VCC) The modules must be supplied via the three VCC pins that represent the module power supply input. Voltage must be stable, because during operation, the current drawn by the SARA-R4 series modules through the VCC pins can vary by several orders of magnitude, depending on the operating mode and state (as described in sections 1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.5). It is important that the supply source is able to withstand both the maximum pulse current occurring during a transmit burst at maximum power level and the average current consumption occurring during Tx / Rx call at maximum RF power level (see the SARA-R4 Data Sheet [1]). SARA-R412M modules provide separate supply inputs over the three VCC pins:

VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding minor part of the total current drawn of the module when RF transmission is enabled during a call The three VCC pins of SARA-R404M and SARA-R410M modules are internally connected each other to both the internal RF Power Amplifier and the internal baseband Power Management Unit. Figure 3 provide a simplified block diagram of SARA-R4 series modules internal VCC supply routing. Figure 3: Block diagram of SARA-R4 series modules internal VCC supply routing UBX-16029218 - R09 System description Page 17 of 115 53VCC52VCC51VCCSARA-R404M / SARA-R410MPower ManagementUnitMemoryBaseband ProcessorTransceiverPower Amplifier53VCC52VCC51VCCSARA-R412MPower ManagementUnitMemoryBaseband ProcessorTransceiverPower Amplifier SARA-R4 series - System Integration Manual 1.5.1.1 VCC supply requirements Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to correctly design a VCC supply circuit compliant with the requirements listed in Table 6. The supply circuit affects the RF compliance of the device integrating SARA-R4 series modules with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the requirements summarized in the Table 6 are fulfilled. Item Requirement Remark VCC nominal voltage Within VCC normal operating range:

SARA-R404M /-R410M:

SARA-R412M:

3.2 V / 4.2 V 3.2 V / 4.5 V VCC voltage during normal operation Within VCC extended operating range:

SARA-R404M /-R410M:

SARA-R412M:

3.0 V / 4.2 V 3.0 V / 4.5 V VCC average current Support with adequate margin the highest averaged VCC current consumption value in connected mode conditions specified in the SARA-R4 Data Sheet [1]

VCC peak current Support with adequate margin the highest peak VCC current consumption value in Tx connected mode conditions specified in the SARA-R4 Data Sheet [1]

VCC voltage drop during Tx slots Lower than 400 mV VCC voltage ripple during Tx Noise in the supply pins must be minimized VCC under/over-shoot at start/end of Tx slots Absent or at least minimized Table 6: Summary of VCC modules supply requirements RF performance is guaranteed when VCC voltage is inside the normal operating range limits. RF performance may be affected when VCC voltage is outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits. VCC voltage must be above the extended operating range minimum limit to switch-on the module. The module may switch-off when the VCC voltage drops below the extended operating range minimum limit. Operation above VCC extended operating range is not recommended and may affect device reliability. The maximum average current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage. Section 1.5.1.2 describes current consumption profiles in connected mode. The maximum peak Tx current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and supply voltage. Section 1.5.1.2 describes current consumption profiles in connected mode. VCC voltage drop directly affects the RF compliance with applicable certification schemes. Figure 6 describes VCC voltage drop during 2G Tx slots. High supply voltage ripple values during RF transmissions in connected mode directly affect the RF compliance with the applicable certification schemes. VCC under/over-shoot directly affects the RF compliance with applicable certification schemes. Figure 6 describes VCC voltage under/over-shoot. UBX-16029218 - R09 System description Page 18 of 115 SARA-R4 series - System Integration Manual 1.5.1.2 VCC current consumption in LTE connected mode During an LTE connection, the SARA-R4 series modules transmit and receive in half duplex mode. The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz. Figure 4 shows an example of SARA-R4 modules current consumption profile versus time in connected mode:

transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-duplex connected mode. Detailed current consumption values can be found in the SARA-R4 series Data Sheet [1]. Figure 4: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection UBX-16029218 - R09 System description Page 19 of 115 Time [ms]Current [mA]0300200100500400Current consumption value depends on TX power and actual antenna load1 Slot1 Resource Block (0.5 ms)1 LTE Radio Frame (10 ms)1 Slot1 Resource Block (0.5 ms)1 LTE Radio Frame (10 ms) SARA-R4 series - System Integration Manual 1.5.1.3 VCC current consumption in 2G connected mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption. If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can reach a high peak / pulse (see the SARA-R4 series Data Sheet [1]) for 576.9 s (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are much lower than during transmission in the low bands, due to the 3GPP transmitter output power specifications. During a GSM call, current consumption is not significantly high while receiving or in monitor bursts, and it is low in the bursts unused to transmit / receive. Figure 5 shows an example of the module current consumption profile versus time in GSM talk mode. Figure 5: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot) Figure 6 illustrates the VCC voltage profile versus time during a GSM call, according to the related VCC current consumption profile described in Figure 5 Figure 6: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot) UBX-16029218 - R09 System description Page 20 of 115 Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200 mA60-120 mA1900 mAPeak current depends on TX power and actual antenna loadGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.060-120 mA10-40 mATimeundershootovershootrippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) SARA-R4 series - System Integration Manual When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption. But according to GPRS specifications, the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the case of a GSM call. If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level, the consumption can reach a quite a high peak but lower than the one achievable in 2G single-slot mode. This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower than in the 850 or 900 MHz band because of the 3GPP Tx power specifications. Figure 7 illustrates the current consumption profiles in GPRS connected mode, in the 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12. Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot) In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one during GPRS connections: the current consumption profile in GPRS multi-slot class 12 connected mode illustrated in the Figure 7 is representative for the EDGE multi-slot class 12 connected mode as well. 1.5.1.4 VCC current consumption in low power deep sleep mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the AT+CPSMS command (see the SARA-R4 series AT Commands Manual [2] and section 1.13.9). When power saving is enabled, the module automatically enters the PSM low power deep sleep mode whenever possible, reducing current consumption down to a steady value in the A range: only the RTC runs with internal 32 kHz reference clock frequency. Detailed current consumption values can be found in the SARA-R4 series Data Sheet [1]. Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the RC oscillator, as a consequence, a very low spike in current consumption will be observed. UBX-16029218 - R09 System description Page 21 of 115 Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]60-120mAGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.060-120mA10-40mA200mAPeak current depends on TX power and actual antenna load1600 mA SARA-R4 series - System Integration Manual 1.5.1.5 VCC current consumption in active mode (power saving disabled) The active mode is the state where the module is switched on and ready to communicate with an external device by means of the application interfaces (as the USB or the UART serial interface). The module processor core is active, and the 19.2 MHz reference clock frequency is used. If power saving configuration is disabled, as it is by default (see the SARA-R4 series AT Commands Manual [2],

+CPSMS AT command for details), the module does not automatically enter the PSM low power deep sleep mode whenever possible: the module remains in active mode. Otherwise, if the power saving configuration is enabled, the module enters PSM low power deep sleep mode whenever possible (see section 1.13.9). Figure 8 illustrates a typical example of the module current consumption profile when the module is in active mode. In such case, the module is registered with the network and, while active mode is maintained, the receiver is periodically activated to monitor the paging channel for paging block reception. Detailed current consumption values can be found in the SARA-R4 series Data Sheet [1]. Figure 8: VCC current consumption profile with power saving disabled and module registered with the network: active mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception 1.5.2 Generic digital interfaces supply output (V_INT) The V_INT output pin of the SARA-R4 series modules is generated by the module internal power management circuitry when the module is switched on and it is not in the deep sleep power saving mode. The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4 series Data Sheet

[1]. The V_INT voltage domain can be used in place of an external discrete regulator as a reference voltage rail for external components. UBX-16029218 - R09 System description Page 22 of 115 ACTIVE MODEPaging periodTime [s]Current [mA]Time [ms]Current [mA]RX Enabled01000100 SARA-R4 series - System Integration Manual 1.6 System function interfaces 1.6.1 Module power-on When the SARA-R4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied), they can be switched on as follows:

Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set at the PWR_ON input pin for a valid time. When the SARA-R4 series modules are in the power-off mode (i.e. switched off) or in the PSM low power mode, with a valid VCC supply applied, they can be switched on as follows:

Low pulse on the PWR_ON pin for a valid time period The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics with voltages and timings are described in the SARA-R4 series Data Sheet [1]. Figure 9 shows the module switch-on sequence from the not-powered mode, describing the following phases:

The external power supply is applied to the VCC module pins The PWR_ON pin is held low for a valid time All the generic digital pins of the module are tri-stated until the switch-on of their supply source (V_INT). The internal reset signal is held low: the baseband core and all the digital pins are held in the reset state. When the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to the default operational configured state. The duration of this pins configuration phase differs within generic digital interfaces and the USB interface due to host / device enumeration timings (see section 1.9.2). The module is fully ready to operate after all interfaces are configured. Figure 9: SARA-R4 series switch-on sequence description The Internal Reset signal is not available on a module pin, but it is recommended to monitor:

the V_INT pin, to sense the start of the SARA-R4 series module switch-on sequence the GPIO pin configured to provide the module operating status indication (see the SARA-R4 series AT Commands Manual [2], AT+UGPIOC command), to sense when the module is ready to operate Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the module. Before the SARA-R4 series module is fully ready to operate, the host application processor should not send any AT command over the AT communication interfaces (USB, UART) of the module. The duration of the SARA-R4 series modules switch-on routine can vary depending on the application /

network settings and the concurrent module activities. UBX-16029218 - R09 System description Page 23 of 115 VCCPWR_ONRESET_NV_INTInternal ResetGPIOSystem StateBB Pads StateOperationalOFFONInternal Reset OperationalTristate / Floating Internal ResetStart of interface configurationModule interfaces are configuredStart-up event~4.5 s0 s SARA-R4 series - System Integration Manual 1.6.2 Module power-off SARA-R4 series can be cleanly switched off by:

AT+CPWROFF command (see the SARA-R4 series AT Commands Manual [2]). The current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed. Low pulse on the PWR_ON pin for a valid time period (see the SARA-R4 series Data Sheet [1]). An abrupt under-voltage shutdown occurs on SARA-R4 series modules when the VCC module supply is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the modules non-volatile memory or to perform the clean network detach. It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series modules normal operations. An abrupt hardware shutdown occurs on SARA-R4 series modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the SARA-R4 series AT Commands Manual [2]. Figure 10 describes the SARA-R4 series modules switch-off sequence started by means of the AT+CPWROFF command, allowing storage of current parameter settings in the modules non-volatile memory and a clean network detach, with the following phases:

When the +CPWROFF AT command is sent, the module starts the switch-off routine. The module replies OK on the AT interface: the switch-off routine is in progress. At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned off, including the generic digital interfaces supply (V_INT). Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a low level to PWR_ON), and enters not-powered mode if the supply is removed from the VCC pins. Figure 10: SARA-R4 series switch-off sequence by means of AT+CPWROFF command The Internal Reset signal is not available on a module pin, but it is recommended to monitor the V_INT pin to sense the end of the switch-off sequence: VCC supply can be removed only after V_INT goes low. The duration of each phase in the SARA-R4 series modules switch-off routines can largely vary depending on the application / network settings and the concurrent module activities. UBX-16029218 - R09 System description Page 24 of 115 VCC PWR_ONRESET_N V_INTInternal ResetSystem StateBB Pads StateOperationalOFFTristate / FloatingONOperational TristateAT+CPWROFFsent to the moduleOKreplied by the moduleVCC can be removed SARA-R4 series - System Integration Manual Figure 11 describes the SARA-R4 series modules switch-off sequence started by means of the PWR_ON input pin, allowing storage of current parameter settings in the modules non-volatile memory and a clean network detach, with the following phases:

A low pulse with appropriate time duration (see the SARA-R4 series Data Sheet [1]) is applied at the PWR_ON input pin. At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned off, including the generic digital interfaces supply (V_INT). Then, the module remains in power-off mode as long as a switch on event does not occur (e.g. applying an appropriate low level to the PWR_ON input), and enters not-powered mode if the VCC supply is removed. Figure 11: SARA-R4 series switch-off sequence by means of PWR_ON pin The Internal Reset signal is not available on a module pin, but it is recommended to monitor the V_INT pin to sense the end of the switch-off sequence: VCC supply can be removed only after V_INT goes low. The duration of each phase in the SARA-R4 series modules switch-off routines can largely vary depending on the application / network settings and the concurrent module activities. 1.6.3 Module reset SARA-R4 series modules can be cleanly reset (rebooted) by:

AT+CFUN command (see the SARA-R4 series AT Commands Manual [2]). In the case listed above an internal or software reset of the module is executed: the current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed. An abrupt hardware shutdown occurs on SARA-R4 series modules when a low level is applied on RESET_N input pin for a valid time period. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. Then, the module remains in power-off mode as long as a switch on event does not occur applying an appropriate low level to the PWR_ON input. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the SARA-R4 series AT Commands Manual [2]. The RESET_N input pin is equipped with an internal pull-up to a 1.8 V supply domain. Detailed electrical characteristics with voltages and timings are described in the SARA-R4 series Data Sheet [1]. UBX-16029218 - R09 System description Page 25 of 115 VCC PWR_ONRESET_N V_INTInternal ResetSystem StateBB Pads StateOFFTristate / FloatingONOperational -> TristateOperational0 s~2.5 s~5 sThe module starts the switch-off routineVCC can be removed SARA-R4 series - System Integration Manual 1.7 Antenna interface 1.7.1 Antenna RF interface (ANT) SARA-R4 series modules provide an RF interface for connecting the external antenna. The ANT pin represents the primary RF input/output for transmission and reception of LTE RF signals. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the primary Tx / Rx antenna through a 50 transmission line to allow clear RF transmission and reception. 1.7.1.1 Antenna RF interfaces requirements Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to correctly design antennas circuits compliant with these requirements. The antenna circuits affect the RF compliance of the device integrating SARA-R4 series modules with applicable required certification schemes (for more details see section 4). Compliance is guaranteed if the antenna RF interface requirements summarized in Table 7 are fulfilled. Item Requirements Remarks Impedance 50 nominal characteristic impedance Frequency Range Return Loss See the SARA-R4 series Data Sheet [1]

S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable Efficiency

> -1.5 dB ( > 70% ) recommended

> -3.0 dB ( > 50% ) acceptable Maximum Gain According to radiation exposure limits The impedance of the antenna RF connection must match the 50 impedance of the ANT port. The required frequency range of the antenna connected to ANT port depends on the operating bands of the used cellular module and the used mobile network. The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the antenna RF connection matches the 50 characteristic impedance of the ANT port. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of the ANT port over the operating frequency range, reducing as much as possible the amount of reflected power. The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT port needs to be enough high over the operating frequency range to comply with the Over-The-Air (OTA) radiated performance requirements, as Total Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified by applicable related certification schemes. The power gain of an antenna is the radiation efficiency multiplied by the directivity: the gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source. The maximum gain of the antenna connected to ANT port must not exceed the herein stated value to comply with regulatory agencies radiation exposure limits. For additional info see sections 4.2.2. Input Power

> 24 dBm ( > 0.25 W ) for R404M / R410M

> 33 dBm ( > 2.0 W ) for R412M The antenna connected to the ANT port must support with adequate margin the maximum power transmitted by the modules. Table 7: Summary of Tx/Rx antenna RF interface requirements UBX-16029218 - R09 System description Page 26 of 115 SARA-R4 series - System Integration Manual 1.7.2 Antenna detection interface (ANT_DET) The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the SARA-R4 series AT Commands Manual [2] for more details on this feature. The ANT_DET pin generates a DC current (for detailed characteristics see the SARA-R4 series Data Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So, the requirements to achieve antenna detection functionality are the following:

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.8 SIM interface 1.8.1 SIM interface SARA-R4 series modules provide high-speed SIM/ME interface including automatic detection and configuration of the voltage required by the connected SIM card or chip. Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage switch from 1.8 V to 3 V are implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output provides internal short circuit protection to limit start-up current and protect the SIM to short circuits. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM card or chip. 1.8.2 SIM detection interface The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if cleanly connected to the mechanical switch of a SIM card holder as described in section 2.5:

Low logic level at GPIO5 input pin is recognized as SIM card not present High logic level at GPIO5 input pin is recognized as SIM card present For more details, see the SARA-R4 series AT Commands Manual [2], +UGPIOC, +CIND and +CMER AT commands. UBX-16029218 - R09 System description Page 27 of 115 SARA-R4 series - System Integration Manual 1.9 Data communication interfaces SARA-R4 series modules provide the following serial communication interface:

UART interface: Universal Asynchronous Receiver/Transmitter serial interface available for the communication with a host application processor (AT commands, data, FW update by means of FOAT). See section 1.9.1. USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host application processor (AT commands, data, FW update by means of the FOAT feature), for FW update by means of the u-blox dedicated tool and for diagnostics. See section 1.9.2. SPI interface: Serial Peripheral Interface available for communication with an external compatible device. See section 1.9.3. SDIO interface: Secure Digital Input Output interface available for communication with a compatible device. See section 1.9.4. DDC interface: I2C bus compatible interface available for the communication with u-blox GNSS positioning chips or modules and with external I2C devices. See section 1.9.5. 1.9.1 UART interface 1.9.1.1 UART features The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the SARA-R4 series modules, supporting:

AT command mode3 Data mode and Online command mode3 Multiplexer protocol functionality FW upgrades by means of the FOAT feature (see 1.13.7) The UART is available only if the USB is not enabled as AT command / data communication interface: UART and USB cannot be concurrently used for this purpose. UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for detailed electrical characteristics see the SARA-R4 series Data Sheet [1]), providing:

data lines (RXD as output, TXD as input) hardware flow control lines (CTS as output, RTS as input) modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output) SARA-R4 series modules are designed to operate as cellular modems, i.e. as the data circuit-terminating equipment

(DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor connected to the module through the UART interface represents the data terminal equipment (DTE). UART signal names of the cellular modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD line represents data transmitted by the DTE (host processor output) and received by the DCE (module input). Hardware flow control is not supported by the 00, 01 and SARA-R410M-02B product versions, but the RTS input line of the module must be set low (= ON state) to communicate over UART interface on the 00 and 01 product versions. DTR input of the module must be set low (= ON state) to have URCs presented over UART interface. 3 For the definition of the interface data mode, command mode and online command mode see SARA-R4 series AT Commands Manual [1]

UBX-16029218 - R09 System description Page 28 of 115 SARA-R4 series - System Integration Manual SARA-R4 series modules UART interface is by default configured in AT command mode, if the USB interface is not enabled as AT command / data communication interface (UART and USB cannot be concurrently used for this purpose): the module waits for AT command instructions and interprets all the characters received as commands to execute. All the functionalities supported by SARA-R4 series modules can be in general set and configured by AT commands:

AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]

u-blox AT commands (for the complete list and syntax see the SARA-R4 series AT Commands Manual [2]) The default baud rate is 115200 b/s, while the default frame format is 8N1 (8 data bits, No parity, 1 stop bit: see Figure 12). Baud rates can be configured by AT command (see the SARA-R4 series AT Commands Manual [2]). The automatic baud rate detection and the automatic frame format recognition are not supported. Figure 12: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit) 1.9.1.2 UART signals behavior At the end of the module boot sequence (see Figure 9), the module is by default in active mode, and the UART interface is initialized and enabled as AT commands interface only if the USB interface is not enabled as AT command / data communication interface: UART and USB cannot be concurrently used for this purpose. The configuration and the behavior of the UART signals after the boot sequence are described below:

The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module holds RXD in the OFF state until the module transmits some data. The module data input line (TXD) is assumed to be controlled by the external host once UART is initialized and if UART is used in the application. The TXD data input line has an internal active pull-down enabled on the 00 and 02 product versions, and an internal active pull-up enabled on the 01 product version. UART multiplexer protocol SARA-R4 series modules include multiplexer functionality as per 3GPP TS 27.010 [8], on the UART physical link. This is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART). The following virtual channels are defined:

Channel 0:

Channel 1:

Channel 2:

Channel 3:

UBX-16029218 - R09 for Multiplexer control for all AT commands, and non-Dial Up Network (non-DUN) data connections. UDP, TCP data socket / data call connections via relevant AT commands. for Dial Up Network (DUN) data connection. It requires the host to have and use its own TCP/IP stack. The DUN can be initiated on the modem side or terminal/host side. for u-blox GNSS data tunneling (not supported by the 00 and 01 product versions). System description Page 29 of 115 D0D1D2D3D4D5D6D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer,8N1 SARA-R4 series - System Integration Manual 1.9.2 USB interface 1.9.2.1 USB features SARA-R4 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate, representing the main interface for transferring high speed data with a host application processor, supporting:

AT command mode4 Data mode and Online command mode4 FW upgrades by means of the FOAT feature (see 1.13.7) FW upgrades by means of the u-blox dedicated tool Trace log capture (diagnostic purposes) The module itself acts as a USB device and can be connected to a USB host such as a Personal Computer or an embedded application microprocessor equipped with compatible drivers. The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus Revision 2.0 specification [4], while the VUSB_DET input pin senses the VBUS USB supply presence (nominally 5 V at the source) to detect the host connection and enable the interface. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input, which senses the USB supply voltage and absorbs few microamperes. The USB interface is available as AT command / data communication interface only if an external valid USB VBUS supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the switch-on of the module, and then held during normal operations. In this case, the UART will be not available. If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode defined in 3GPP Rel.13. The USB interface is controlled and operated with:

AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]

u-blox AT commands (for the complete list and syntax see the SARA-R4 series AT Commands Manual [2]) The USB interface of SARA-R4 series modules can provide the following USB functions:

AT commands and data communication Diagnostic log The USB profile of SARA-R4 series modules identifies itself by the following VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [4]. VID = 0x05C6 PID = 0x90B2 4 For the definition of the interface data mode, command mode and online command mode see SARA-R4 series AT Commands Manual [2]

UBX-16029218 - R09 System description Page 30 of 115 SARA-R4 series - System Integration Manual 1.9.3 SPI interface The SPI interface is not supported by 00, 01 and 02 product versions: the SPI interface pins should not be driven by any external device. SARA-R4 series modules include a Serial Peripheral Interface for communication with compatible external device. The SPI interface can be made available as alternative function, in mutually exclusive way, over the digital audio interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS). 1.9.4 SDIO interface The SDIO interface is not supported by 00, 01 and 02 product versions: the SDIO interface pins should not be driven by any external device. SARA-R4 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with external compatible SDIO devices. 1.9.5 DDC (I2C) interface The I2C interface is not supported by 00 and 01 product versions: the I2C interface pins should not be driven by any external device. SARA-R4 series modules include an I2C-bus compatible DDC interface (SDA, SCL) available to communicate with a u-blox GNSS receiver and with external I2C devices as an audio codec: the SARA-R4 module acts as an I2C master which can communicate with I2C slaves in accordance with the I2C bus specifications [9]. The SDA and SCL pins have internal pull-up to V_INT, so there is no need of additional pull-up resistors on the external application board. 1.10 Audio Audio is not supported by 00, 01 and 02 product versions: the I2S interface pins should not be driven by any external device. SARA-R4 series modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio services. SARA-R4 series modules include an I2S digital audio interface to transfer digital audio data to/from an external compatible audio device. The digital audio interface can be made available as alternative function, in mutually exclusive way, over the SPI interface pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS). UBX-16029218 - R09 System description Page 31 of 115 SARA-R4 series - System Integration Manual 1.11 General Purpose Input/Output SARA-R4 series modules include six pins (GPIO1-GPIO6) which can be configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more details see the SARA-R4 series AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized in Table 8. Function Description Default GPIO Configurable GPIOs Network status indication Network status: registered / data transmission, no service GNSS supply enable5 GNSS data ready5 Enable/disable the supply of a u-blox GNSS receiver connected to the cellular module by the DDC (I2C) interface Sense when a u-blox GNSS receiver connected to the module is ready for sending data by the DDC (I2C) interface SIM card detection SIM card physical presence detection Module status indication Module switched off or in PSM low power deep sleep mode, versus active or connected mode General purpose input Input to sense high or low digital level General purpose output Output to set the high or the low digital level

--

--

--

--

--

--

--

GPIO1 GPIO2 GPIO3 GPIO5 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO6 Pin disabled Tri-state with an internal active pull-down enabled GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 Table 8: SARA-R4 series GPIO custom functions configuration 1.12 Reserved pins (RSVD) SARA-R4 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be externally connected to ground. 5 Not supported by 00 and 01 product versions UBX-16029218 - R09 System description Page 32 of 115 SARA-R4 series - System Integration Manual 1.13 System features 1.13.1 Network indication GPIOs can be configured by the AT command to indicate network status (for further details see section 1.11 and the SARA-R4 series AT Commands Manual [2]):

No service (no network coverage or not registered) Registered / Data call enabled (RF data transmission / reception) 1.13.2 Antenna supervisor The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional feature that can be implemented if the application requires it. The antenna supervisor is forced by the +UANTR AT command (see the SARA-R4 series AT Commands Manual [2] for more details). The requirements to achieve antenna detection functionality are the following:

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.13.3 Dual stack IPv4/IPv6 SARA-R4 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel. For more details about dual stack IPv4/IPv6 see the SARA-R4 series AT Commands Manual [2]. 1.13.4 TCP/IP and UDP/IP SARA-R4 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured established and handled via the data connection management packet switched data commands. SARA-R4 series modules provide Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interfaces (USB, UART). In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa. For more details on embedded TCP/IP and UDP/IP functionalities, see SARA-R4 series AT Commands Manual [2]. 1.13.5 FTP SARA-R4 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in the local file system of the module. FTP files can also be transferred using FTP Direct Link:

FTP download: data coming from the FTP server is forwarded to the host processor via USB / UART serial interfaces (for FTP without Direct Link mode the data is always stored in the modules flash file system) FTP upload: data coming from the host processor via USB / UART serial interface is forwarded to the FTP server (for FTP without Direct Link mode the data is read from the modules flash file system) When Direct Link is used for an FTP file transfer, only the file contents passes through USB / UART serial interface, whereas all the FTP command handling is managed internally by the FTP application. For more details about embedded FTP functionalities, see the SARA-R4 series AT Commands Manual [2]. UBX-16029218 - R09 System description Page 33 of 115 SARA-R4 series - System Integration Manual 1.13.6 HTTP SARA-R4 series modules provide the embedded Hypertext Transfer Protocol (HTTP) services via AT commands for sending requests to a remote HTTP server, receiving the server response and transparently storing it in the modules flash file system. For more details, see the SARA-R4 series AT Commands Manual [2]. Firmware update Over AT (FOAT) This feature allows upgrading of the module firmware over the AT interface, using AT commands. The +UFWUPD AT command enables a code download to the device from the host via the Xmodem protocol. The +UFWINSTALL AT command then triggers a reboot, and upon reboot initiates a firmware installation on the device via a special boot loader on the module. The bootloader first authenticates the downloaded image, then installs it, and then reboots the module. Firmware authenticity verification is performed via a security signature. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware installation. After completing the upgrade, the module is reset again and wakes-up in normal boot. For more details about Firmware update Over AT procedure, see the SARA-R4 series AT Commands Manual [2],

+UFWUPD AT command. 1.13.8 Firmware update Over The Air (uFOTA) This feature allows upgrading the module firmware over the air interface, based on u-blox client/server solution

(uFOTA), using LWM2M. For more details about firmware update over-the-air procedure, see the SARA-R4 series AT Commands Manual [2]. 1.13.9 Power saving 1.13.9.1 Guidelines to optimize power consumption The LTE Cat M1 / NB1 technology is mainly intended for applications that only require a small amount of data exchange per day (i.e. a few bytes in uplink and downlink per day). Depending on the application type, the battery may be required to last for a few years. For these reasons, the whole application board should be optimized in terms of current consumption and should carefully take into account the following aspects:

Enable the power saving mode configuration using the AT+CPSMS command (for the complete description of the AT+CPSMS command, see the SARA-R4 series AT Commands Manual [2]). Use the UART interface instead of the USB interface as a serial communication interface, because the current consumption of the module is ~20 mA higher when the USB interface is enabled. Use an application processor with a UART interface working at the same voltage level (1.8 V) as the module. In this way it is possible to avoid voltage translators, which helps to minimize current leakage. If the USB interface is implemented in the design, remove the external USB VBUS voltage from the VUSB_DET input when serial communication is not necessary, letting the module enter the Power Saving Mode defined in 3GPP Rel.13: the module does not enter the deep sleep power saving mode if the USB interface is enabled. Minimize current leakage on the power supply line. Optimize the antenna matching, since a mismatched antenna leads to higher current consumption. Monitor V_INT level to sense when the module enters power-off mode or deep sleep power saving mode. Disconnect the VCC supply source from the module when it is switched off (see 2.2.1.9). Disconnect the VCC supply source from the module during deep sleep power saving mode (see 2.2.1.9): using a host application processor equipped with a RTC, the module can execute a standard PSM procedure and UBX-16029218 - R09 System description Page 34 of 115 SARA-R4 series - System Integration Manual store the NAS protocol context in non-volatile memory, and then rely on the host application processor for running its RTC and triggering wake-up upon need6. 1.13.9.2 Functionality When power saving is enabled using the AT+CPSMS command, the module automatically enters the low power deep sleep mode whenever possible, reducing current consumption (see the section 1.5.1.4 and the SARA-R4 series Data Sheet [1]). For the definition and the description of the SARA-R4 series operating modes, including the events forcing transitions between the different operating modes, see section 1.4. The SARA-R4 series modules achieve the low power deep sleep mode by powering down all the Hardware components with the exception of the 32 kHz reference internally generated. From the host application point of view, the serial port will not be available during low power deep sleep mode, as the SARA-R4 module will act as if the SARA-R4 module is in Power-Off mode. 1.13.9.3 Timers and network interaction The SARA-R4 series modules goes in low power deep sleep mode entering in the Power Saving Mode (PSM) defined in 3GPP Release 13. Two timers have been specified on the PSM Signaling: the Periodic Update Timer and Active Timer. The Active Timer is the time defined by the network where the SARA-R4 series module will keep listening for any active operation, during this time the SARA-R4 series module is in Active mode. The Periodic Update Timer is the Extended Tracking Area Update (TAU) used by the SARA-R4 series module to periodically notify the network of its availability. The SARA-R4 series module requests the PSM by including the Active Timer with the desired value in the Attach, TAU or Routing Area Update (RAU) messages. The Active Timer is the time the module listens to the Paging Channel after having transitioned from connected to active mode. When the Active Timer expires, the module enters PSM low power deep sleep mode. SARA-R4 series module can also request an extended Periodic Update Timer value to remain in PSM low power deep sleep mode for longer than the original Periodic Update Timer broadcasted by the network. The grant of PSM is a negotiation between SARA-R4 series module and the attached network: the network accepts PSM by providing the actual value of the Active Timer (and Periodic Update Timer) to be used in the Attach/TAU/RAU accept procedure. The maximum duration, including the Periodic Update Timer, is about 413 days. The SARA-R4 series module enters PSM low power deep sleep mode only after the Active Timer expires. Figure 13: Description of the PSM timing 6 The use of an external RTC during deep sleep power saving mode is not supported by the 00, 01 and 02 product versions UBX-16029218 - R09 System description Page 35 of 115 PSM low power deep sleep mode(periodic update timer)Connected mode: Data Tx / RxActive mode(active timer)TimeCurrent SARA-R4 series - System Integration Manual 1.13.9.4 Timers and AT interaction The SARA-R4 series modules goes in low power deep sleep mode entering in the Power Saving Mode (PSM) only after the 6 s AT Inactivity Timer expires:

If the UART interface is used, the host application has to stop sending AT commands for 6 s, consisting in the AT Inactivity Timer expiration, therefore allowing the module enter deep sleep power saving mode according to Active Timer expiration If the USB interface is enabled, the module does not enter the deep sleep power saving mode 1.13.9.5 AT commands The module uses the +CPSMS AT command with its defined parameters to request PSM timers to the network. See the SARA-R4 series AT Commands Manual [2] for details of the +CPSMS operation and features. 1.13.9.6 Host application The PSM low power deep sleep mode implementation allows the SARA-R4 series module to help extend the battery life of the application. The Host Application should be aware that the SARA-R4 series module is PSM-capable. The host application needs to sense the V_INT supply output of the module to get the notification when the module has entered into PSM low power deep sleep mode. If the host application receives an event that needs to be reported by the SARA-R4 series module interrupting the PSM low power deep sleep mode, it can be done so by setting the module into Active mode using the appropriate power-on event (see 1.6.1). From the host application point of view, the SARA-R4 module will look as it is in Power-Off mode. 1.13.9.7 Normal operation The Host Application can force the SARA-R4 series module to transition from PSM low power deep sleep mode to Active mode by using the Power-Up procedure specified in section 1.6.1. Be aware that when the host application transitions from low power deep sleep mode to active mode, it will cause the SARA-R4 series module to consume the same amount of power as in active mode, thereby shortening the battery life of the host application. UBX-16029218 - R09 System description Page 36 of 115 SARA-R4 series - System Integration Manual 2 Design-in 2.1 Overview For an optimal integration of the SARA-R4 series modules in the final application board, follow the design guidelines stated in this section. Every application circuit must be suitably designed to guarantee the correct functionality of the relative interface, but a number of points require particular attention during the design of the application device. The following list provides a rank of importance in the application design, starting from the highest relevance:

1. Module antenna connection: ANT and ANT_DET pins. Antenna circuit directly affects the RF compliance of the device integrating a SARA-R4 series module with applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the schematic and layout design. 2. Module supply: VCC and GND pins. The supply circuit affects the RF compliance of the device integrating a SARA-R4 series module with the applicable required certification schemes as well as the antenna circuit design. Very carefully follow the suggestions provided in the relative section 2.2.1 for the schematic and layout design. 3. USB interface: USB_D+, USB_D- and VUSB_DET pins. Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the suggestions provided in the relative section 2.6.2 for the schematic and layout design. 4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins. Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling. Carefully follow the suggestions provided in the relative section 2.5 for the schematic and layout design. 5. System functions: RESET_N and PWR_ON pins. Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully follow the suggestions provided in the relative section 2.3 for the schematic and layout design. 6. Other digital interfaces: UART, SPI, SDIO, I2C, I2S, GPIOs and reserved pins. Accurate design is required to guarantee correct functionality and reduce the risk of digital data frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3, 2.6.4, 2.6.5, 2.7, 2.8 and 2.9 for the schematic and layout design. 7. Other supplies: V_INT generic digital interfaces supply. Accurate design is required to guarantee correct functionality. Follow the suggestions provided in the corresponding section 2.2.2 for the schematic and layout design. It is recommended to follow the specific design guidelines provided by each manufacturer of any external part selected for the application board integrating the u-blox cellular modules. UBX-16029218 - R09 Design-in Page 37 of 115 SARA-R4 series - System Integration Manual 2.2 Supply interfaces 2.2.1 Module supply (VCC) 2.2.1.1 General guidelines for VCC supply circuit selection and design All the available VCC pins have to be connected to the external supply minimizing the power loss due to series resistance. GND pins are internally connected. Application design shall connect all the available pads to solid ground on the application board, since a good (low impedance) connection to external ground can minimize power loss and improve RF and thermal performance. SARA-R4 series modules must be sourced through the VCC pins with a suitable DC power supply that should meet the following prerequisites to comply with the modules VCC requirements summarized in Table 6. The appropriate DC power supply can be selected according to the application requirements (see Figure 14) between the different possible supply sources types, which most common ones are the following:

Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery Figure 14: VCC supply concept selection The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the operating supply voltage of SARA-R4 series. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source. See section 2.2.1.2 for specific design-in. The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less or equal than 5 V). In this case, the typical 90% efficiency of the switching regulator diminishes the benefit of voltage step-down and no true advantage is gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they dissipate a considerable amount of energy in thermal power. See section 2.2.1.3 for specific design-in. If SARA-R4 series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided. See sections 2.2.1.4, 2.2.1.5, 2.2.1.6 and 2.2.1.7 for specific design-in. Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger circuit, which is not included in the modules. The charger circuit needs to be designed to prevent over-voltage on VCC pins, and it should be selected according to the application requirements. A DC/DC switching charger is the typical choice when the charging source has a high nominal voltage (e.g. ~12 V), whereas a linear charger is the typical choice when the charging source has a relatively low nominal voltage (~5 V). If both a permanent primary supply UBX-16029218 - R09 Design-in Page 38 of 115 Main Supply Available?BatteryLi-Ion 3.7 VLinear LDO RegulatorMain Supply Voltage > 5V?Switching Step-Down RegulatorNo, portable deviceNo, less than 5 VYes, greater than 5 VYes, always available SARA-R4 series - System Integration Manual

/ charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a suitable charger / regulator with integrated power path management function can be selected to supply the module while simultaneously and independently charging the battery. See sections 2.2.1.6 and 2.2.1.7 for specific design-in. An appropriate primary (not rechargeable) battery can be selected taking into account the maximum current specified in the SARA-R4 series Data Sheet [1] during connected mode, considering that primary cells might have weak power capability. See section 2.2.1.5 for specific design-in. The usage of more than one DC supply at the same time should be carefully evaluated: depending on the supply source characteristics, different DC supply systems can result as mutually exclusive. The selected regulator or battery must be able to support with adequate margin the highest averaged current consumption value specified in the SARA-R4 series Data Sheet [1]. The following sections highlight some design aspects for each of the supplies listed above providing application circuit design-in compliant with the module VCC requirements summarized in Table 6. 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator The use of a switching regulator is suggested when the difference from the available supply rail source to the VCC value is high, since switching regulators provide good efficiency transforming a 12 V or greater voltage supply to the typical 3.8 V value of the VCC supply. The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current consumption occurring during transmissions at the maximum power, as specified in the SARA-R4 series Data Sheet [1]. Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile. High switching frequency: for best performance and for smaller applications it is recommended to select a switching frequency 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact the LTE modulation spectrum performance. PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in connected mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM modes transitions must be avoided to reduce noise on VCC voltage profile. Switching regulators can be used that are able to switch between low ripple PWM mode and high ripple PFM mode, provided that the mode transition occurs when the module changes status from the active mode to connected mode. It is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold. UBX-16029218 - R09 Design-in Page 39 of 115 SARA-R4 series - System Integration Manual Figure 15 and the components listed in Table 9 show an example of a high reliability power supply circuit for the SARA-R412M modules that support 2G radio access technology. This circuit is also suitable for the other SARA-R4 series modules, where the module VCC input is supplied by a step-down switching regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. Figure 15: Example of high reliability VCC supply circuit for SARA-R4 series modules, using a step-down regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 L1 R1 R2 R3 R4 R5 U1 10 F Capacitor Ceramic X7R 5750 15% 50 V Generic manufacturer 10 nF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 680 pF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 22 pF Capacitor Ceramic C0G 0402 5% 25 V Generic manufacturer 10 nF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer 470 nF Capacitor Ceramic X7R 0603 10% 25 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor 10 H Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics 470 k Resistor 0402 5% 0.1 W 15 k Resistor 0402 5% 0.1 W 22 k Resistor 0402 5% 0.1 W 390 k Resistor 0402 1% 0.063 W 100 k Resistor 0402 5% 0.1 W Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer Step-Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology Table 9: Components for high reliability VCC supply circuit for SARA-R4 series modules, using a step-down regulator UBX-16029218 - R09 Design-in Page 40 of 115 SARA-R412VC5R3C4R2C2C1R1VINRUNVCRTPGSYNCBDBOOSTSWFBGND671095C61238114C7C8D1R4R5L1C3U152VCC53VCC51VCCGNDC9C10C11 SARA-R4 series - System Integration Manual Figure 15 and the components listed in Table 9 show an example of a high reliability power supply circuit for the SARA-R404M and the SARA-R410M modules, which do not support the 2G radio access technology. In this example, the module VCC is supplied by a step-down switching regulator capable of delivering the maximum peak

/ pulse current specified for the LTE use-case, with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. Figure 16: Example of high reliability VCC supply circuit for SARA-R404M and SARA-R410M, using a step-down regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 R1 R2 U1 10 F Capacitor Ceramic X7R 50 V 10 nF Capacitor Ceramic X7R 16 V 22 nF Capacitor Ceramic X7R 16 V 22 F Capacitor Ceramic X5R 25 V 22 F Capacitor Ceramic X5R 25 V Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 30 V 2 A 4.7 H Inductor 20% 2 A 470 k Resistor 0.1 W 150 k Resistor 0.1 W Step-Down Regulator 1 A 1 MHz MBR230LSFT1G - ON Semiconductor SLF7045T-4R7M2R0-PF - TDK Generic manufacturer Generic manufacturer TS30041 - Semtech Table 10: Components for high reliability VCC supply circuit for SARA-R404M and SARA-R410M, using a step-down regulator UBX-16029218 - R09 Design-in Page 41 of 115 SARA-R404MSARA-R410M12VC2C1VCCENPGVSWGND89142D1L1U1BSTFB5R1R252VCC53VCC51VCCGND3V8C6C7C8PGNDC4C3C51110C9 SARA-R4 series - System Integration Manual Figure 17 and the components listed in Table 11 show an example of a low cost power supply circuit suitable for all the SARA-R4 series modules, where the module VCC is supplied by a step-down switching regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, transforming a 12 V supply input. Figure 17: Example of low cost VCC supply circuit for SARA-R4 series modules, using a step-down regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 L1 R1 R2 R3 R4 R5 U1 22 F Capacitor Ceramic X5R 1210 10% 25 V Generic manufacturer 220 nF Capacitor Ceramic X7R 0603 10% 25 V Generic manufacturer 5.6 nF Capacitor Ceramic X7R 0402 10% 50 V Generic manufacturer 6.8 nF Capacitor Ceramic X7R 0402 10% 50 V Generic manufacturer 56 pF Capacitor Ceramic C0G 0402 5% 50 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata Schottky Diode 25V 2 A 5.2 H Inductor 30% 5.28A 22 m 4.7 k Resistor 0402 1% 0.063 W 910 Resistor 0402 1% 0.063 W 82 Resistor 0402 5% 0.063 W 8.2 k Resistor 0402 5% 0.063 W 39 k Resistor 0402 5% 0.063 W STPS2L25 STMicroelectronics MSS1038-522NL Coilcraft Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer Step-Down Regulator 8-VFQFPN 3 A 1 MHz L5987TR ST Microelectronics Table 11: Suggested components for low cost VCC supply circuit for SARA-R4 series modules, using a step-down regulator UBX-16029218 - R09 Design-in Page 42 of 115 SARA-R412VR5C2C1VCCINHFSWSYNCOUTGND263178C3D1R1R2L1U1GNDFBCOMP54R3C4R4C552VCC53VCC51VCCC6C7C8C9C10 SARA-R4 series - System Integration Manual 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out linear regulator The use of a linear regulator is suggested when the difference from the available supply rail source and the VCC value is low. The linear regulators provide high efficiency when transforming a 5 VDC supply to a voltage value within the module VCC normal operating range. The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current consumption occurring during a transmission at the maximum Tx power, as specified in the SARA-R4 series Data Sheet [1]. Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the maximum input voltage to the minimum output voltage to evaluate the power dissipation of the regulator). Figure 18 and the components listed in Table 12 show an example of a high reliability power supply circuit for the SARA-R412M modules supporting the 2G radio access technology. This example is also suitable for the other SARA-R4 series modules, where the VCC module supply is provided by an LDO linear regulator capable of delivering the highest peak / pulse current specified for the 2G use-case, with an appropriate power handling capability. The regulator described in this example supports a wide input voltage range, and it includes internal circuitry for reverse battery protection, current limiting, thermal limiting and reverse current protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 19 and Table 13). This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit. Figure 18: Example of high reliability VCC supply circuit for SARA-R4 series modules, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 R1 R2 U1 10 F Capacitor Ceramic X5R 0603 20% 6.3 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 9.1 k Resistor 0402 5% 0.1 W 3.9 k Resistor 0402 5% 0.1 W LDO Linear Regulator ADJ 3.0 A Generic manufacturer Generic manufacturer LT1764AEQ#PBF - Linear Technology Table 12: Suggested components for high reliability VCC supply circuit for SARA-R4 modules, using an LDO linear regulator UBX-16029218 - R09 Design-in Page 43 of 115 5VC1INOUTADJGND12453R1R2U1SHDNSARA-R452VCC53VCC51VCCGNDC2C3C4C5C6 SARA-R4 series - System Integration Manual Figure 19 and the components listed in Table 13 show an example of a high reliability power supply circuit for the SARA-R404M and the SARA-R410M modules, which do not support the 2G radio access technology, where the module VCC is supplied by an LDO linear regulator capable of delivering the maximum peak / pulse current specified for the LTE use-case, with suitable power handling capability. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V for the VCC, as in the circuits described in Figure 19 and Table 13). This reduces the power on the linear regulator and improves the thermal design of the circuit. Figure 19: Example of high reliability VCC supply circuit for SARA-R404M and SARA-R410M, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 R1 R2 R3 U1 1 F Capacitor Ceramic X5R 6.3 V 22 F Capacitor Ceramic X5R 25 V Generic manufacturer Generic manufacturer 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 47 k Resistor 0.1 W 41 k Resistor 0.1 W 10 k Resistor 0.1 W Generic manufacturer Generic manufacturer Generic manufacturer LDO Linear Regulator 1.0 A AP7361 Diodes Incorporated Table 13: Components for high reliability VCC supply circuit for SARA-R404M and SARA-R410M, using an LDO linear regulator UBX-16029218 - R09 Design-in Page 44 of 115 5VC1R1INOUTADJGND58134C2R2R3U1ENSARA-R404MSARA-R410M52VCC53VCC51VCCGNDC4C3C5C6 SARA-R4 series - System Integration Manual Figure 20 and the components listed in Table 14 show an example of a low cost power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak / pulse current, with an appropriate power handling capability. The regulator described in this example supports a limited input voltage range and it includes internal circuitry for current and thermal protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 20 and Table 14). This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit. Figure 20: Example of low cost VCC supply circuit for SARA-R4 series modules, using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 R1 R2 U1 10 F Capacitor Ceramic X5R 0603 20% 6.3 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata 27 k Resistor 0402 5% 0.1 W 4.7 k Resistor 0402 5% 0.1 W LDO Linear Regulator ADJ 3.0 A Generic manufacturer Generic manufacturer LP38501ATJ-ADJ/NOPB - Texas Instrument Table 14: Suggested components for low cost VCC supply circuit for SARA-R4 series modules, using an LDO linear regulator UBX-16029218 - R09 Design-in Page 45 of 115 5VC1INOUTADJGND12453R1R2U1ENSARA-R452VCC53VCC51VCCGNDC2C3C4C5C6 SARA-R4 series - System Integration Manual 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output circuit connected to the VCC pins must be capable of delivering the maximum current occurring during a transmission at maximum Tx power, as specified in the SARA-R4 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts. 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

Maximum pulse and DC discharge current: the non-rechargeable battery with its related output circuit connected to the VCC pins must be capable of delivering the maximum current consumption occurring during a transmission at maximum Tx power, as specified in the SARA-R4 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts. 2.2.1.6 Guidelines for external battery charging circuit SARA-R4 series modules do not have an on-board charging circuit. Figure 21 provides an example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell. In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features the correct pulse and DC discharge current capabilities and the appropriate DC series resistance, is directly connected to the VCC supply input of the module. Battery charging is completely managed by the Battery Charger IC, which from a USB power source (5.0 V typ.), linearly charges the battery in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current. Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor. Constant voltage: when the battery voltage reaches the regulated output voltage, the Battery Charger IC starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor or when the charging timer reaches the factory set value. Using a battery pack with an internal NTC resistor, the Battery Charger IC can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. The Battery Charger IC, as linear charger, is more suitable for applications where the charging source has a relatively low nominal voltage (~5 V), so that a switching charger is suggested for applications where the charging source has a relatively high nominal voltage (e.g. ~12 V, see section 2.2.1.7 for the specific design-in). UBX-16029218 - R09 Design-in Page 46 of 115 SARA-R4 series - System Integration Manual Figure 21: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Part Number - Manufacturer B1 C1 C2 C3 C4 C5 C6 D1, D2 R1 U1 Li-Ion (or Li-Polymer) battery pack with 470 NTC Generic manufacturer 1 F Capacitor Ceramic X7R 16 V Generic manufacturer 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata Low Capacitance ESD Protection 10 k Resistor 0.1 W CG0402MLE-18G - Bourns Generic manufacturer Single Cell Li-Ion (or Li-Polymer) Battery Charger IC MCP73833 - Microchip Table 15: Suggested components for the Li-Ion (or Li-Polymer) battery charging application circuit 2.2.1.7 Guidelines for external battery charging and power path management circuit Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as a possible supply source, should implement a suitable charger / regulator with integrated power path management function to supply the module and the whole device while simultaneously and independently charging the battery. Figure 22 reports a simplified block diagram circuit showing the working principle of a charger / regulator with integrated power path management function. This component allows the system to be powered by a permanent primary supply source (e.g. ~12 V) using the integrated regulator, which simultaneously and independently recharges the battery (e.g. 3.7 V Li-Pol) that represents the back-up supply source of the system. The power path management feature permits the battery to supplement the system current requirements when the primary supply source is not available or cannot deliver the peak system currents. A power management IC should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6:

High efficiency internal step down converter, compliant with the performances specified in section 2.2.1.2 Low internal resistance in the active path Vout Vbat, typically lower than 50 m High efficiency switch mode charger with separate power path control UBX-16029218 - R09 Design-in Page 47 of 115 C5C3C6GNDSARA-R4 series52VCC53VCC51VCCUSB SupplyU1PGSTAT2STA1VDDC15V0THERMVssVbatLi-Ion/Li-Pol Battery PackD1B1C2Li-Ion/Li-Polymer Battery Charger ICD2PROGR1C4 SARA-R4 series - System Integration Manual Figure 22: Charger / regulator with integrated power path management circuit block diagram Figure 23 and the parts listed in Table 16 provide an application circuit example where the MPS MP2617H switching charger / regulator with integrated power path management function provides the supply to the cellular module. At the same time it also concurrently and autonomously charges a suitable Li-Ion (or Li-Polymer) battery with the correct pulse and DC discharge current capabilities and the appropriate DC series resistance according to the rechargeable battery recommendations described in section 2.2.1.4. The MP2617H IC constantly monitors the battery voltage and selects whether to use the external main primary supply / charging source or the battery as supply source for the module, and starts a charging phase accordingly. The MP2617H IC normally provides a supply voltage to the module regulated from the external main primary source allowing immediate system operation even under missing or deeply discharged battery: the integrated switching step-down regulator is capable to provide up to 3 A output current with low output ripple and fixed 1.6 MHz switching frequency in PWM mode operation. The module load is satisfied in priority, then the integrated switching charger will take the remaining current to charge the battery. Additionally, the power path control allows an internal connection from battery to the module with a low series internal ON resistance (40 m typical), in order to supplement additional power to the module when the current demand increases over the external main primary source or when this external source is removed. Battery charging is managed in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for the application Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively reduced until the charge termination is done. The charging process ends when the charging current reaches the 10% of the fast-charge current or when the charging timer reaches the value configured by an external capacitor Using a battery pack with an internal NTC resistor, the MP2617H can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. Several parameters as the charging current, the charging timings, the input current limit, the input voltage limit, the system output voltage can be easily set according to the specific application requirements, as the actual electrical characteristics of the battery and the external supply / charging source: suitable resistors or capacitors must be accordingly connected to the related pins of the IC. UBX-16029218 - R09 Design-in Page 48 of 115 GNDPower path management ICVoutVinLi-Ion/Li-Pol Battery PackGNDSystem12 V Primary SourceCharge controllerDC/DC converter and battery FET control logicVbat SARA-R4 series - System Integration Manual Figure 23: Li-Ion (or Li-Polymer) battery charging and power path management application circuit Reference Description Part Number - Manufacturer B1 C1, C6 Li-Ion (or Li-Polymer) battery pack with 10 k NTC Various manufacturer 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata C2, C4, C10 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata C3 C5 C7, C12 C8, C13 C11 D1, D2 D3 1 F Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E105KA12 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata Low Capacitance ESD Protection CG0402MLE-18G - Bourns Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor R1, R3, R5, R7 10 k Resistor 0402 1% 1/16 W R2 R4 R6 L1 U1 1.05 k Resistor 0402 1% 0.1 W 22 k Resistor 0402 1% 1/16 W 26.5 k Resistor 0402 1% 1/16 W 2.2 H Inductor 7.4 A 13 m 20%

Generic manufacturer Generic manufacturer Generic manufacturer Generic manufacturer SRN8040-2R2Y - Bourns Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator with integrated Power Path Management function MP2617H - Monolithic Power Systems (MPS) Table 16: Suggested components for Li-Ion (or Li-Polymer) battery charging and power path management application circuit UBX-16029218 - R09 Design-in Page 49 of 115 C10C13GNDC12C11SARA-R4 series52VCC53VCC51VCC+Primary SourceR3U1ENILIMISETTMRAGNDVINC2C112VNTCPGNDSWSYSBATC4R1R2D1Li-Ion/Li-Pol Battery PackB1C5Li-Ion/Li-Polymer Battery Charger / Regulator with Power Path ManagmentVCCC3C6L1BSTD2VLIMR4R5C7C8D3R6SYSFBR7 SARA-R4 series - System Integration Manual 2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R412M modules SARA-R412M modules have separate supply inputs over the VCC pins (see Figure 3):

VCC pins #52 and #53: supply input for the internal RF Power Amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call VCC pin #51: supply input for the internal Power Management Unit, Base-Band and Transceiver parts, demanding minor current Generally, all the VCC pins are intended to be connected to the same external power supply circuit, but separate supply sources can be implemented for specific (e.g. battery-powered) applications. The voltage at the VCC pins

#52 and #53 can drop to a value lower than the one at the VCC pin #51, keeping the module still switched-on and functional. Figure 24 illustrates a possible application circuit. Figure 24: VCC circuit example with separate supply for SARA-R412M modules Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 D1 L1 R1 R2 U1 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 56 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E560JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Schottky Diode 40 V 1 A 10 H Inductor 20% 1 A 276 m 1 M Resistor 0402 5% 0.063 W 412 k Resistor 0402 5% 0.063 W Step-up Regulator 350 mA SS14 - Vishay General Semiconductor SRN3015-100M - Bourns Inc. Generic manufacturer Generic manufacturer AP3015 - Diodes Incorporated Table 17: Examples of components for the VCC circuit with separate supply for SARA-R412M modules UBX-16029218 - R09 Design-in Page 50 of 115 C1C4GNDC3C2C5SARA-R412M52VCC53VCC51VCC+Li-Ion/Li-Pol BatteryC6SWVINSHDNnGNDFBC7R1R2L1U1Step-up RegulatorD1C8 SARA-R4 series - System Integration Manual 2.2.1.9 Guidelines for removing VCC supply Removing the VCC power can be useful to minimize the current consumption when the SARA-R4 series modules are switched off or when the modules are in deep sleep Power Saving Mode. In applications in which the module is paired to a host application processor equipped with a RTC, the module can execute standard PSM procedures, store NAS protocol context in non-volatile memory, and rely on the host application processor to run its RTC and to trigger wake-up upon need. The application processor can disconnect the VCC supply source from the module and zero out the modules PSM current. The VCC supply source can be removed using an appropriate low-leakage load switch or p-channel MOSFET controlled by the application processor as shown in Figure 25, given that the external switch has provide:

Very low leakage current (for example, less than 1 A), to minimize the current consumption Very low RDS(ON) series resistance (for example, less than 50 m), to minimize voltage drops Adequate maximum Drain current (see the SARA-R4 series Data Sheet [1] for module consumption figures) Figure 25: Example of application circuit for VCC supply removal Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 R1, R3 R2 T1 U1 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata 47 k Resistor 0402 5% 0.1 W 10 k Resistor 0402 5% 0.1 W NPN BJT Transistor RC0402JR-0747KL - Yageo Phycomp RC0402JR-0710KL - Yageo Phycomp BC847 - Infineon Ultra-Low Resistance Load Switch TPS22967 - Texas Instruments Table 18: Components for VCC supply removal application circuit It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4 series normal operations: the VCC supply can be removed only after V_INT goes low, indicating that the module has entered Deep-Sleep Power Saving Mode or Power-Off Mode. UBX-16029218 - R09 Design-in Page 51 of 115 C3GNDC2C1C4SARA-R4 series52VCC53VCC51VCCVCC Supply SourceGNDC5U1VOUTVINVBIASONCTGND4V_INT15PWR_ONR1R2T1GPIOApplication ProcessorGPIOGPIO+SARA-R4 series - System Integration Manual 2.2.1.10 Additional guidelines for VCC supply circuit design To reduce voltage drops, use a low impedance power source. The series resistance of the power supply lines

(connected to the modules VCC and GND pins) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize power losses. Three pins are allocated to VCC supply. Several pins are designated for GND connection. It is recommended to correctly connect all of them to supply the module to minimize series resistance losses. To reduce voltage ripple and noise, improving RF performance especially if the application device integrates an internal antenna, place the following bypass capacitors near the VCC pins:

68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata GRM1555C1H680J), to filter EMI in the low cellular frequency bands 15 pF capacitor with Self-Resonant Frequency in the 1800/1900 MHz range (as Murata GRM1555C1H150J), to filter EMI in the high cellular frequency bands 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise from clocks and data sources 100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data sources An additional capacitor is recommended to avoid undershoot and overshoot at the start and end of RF Tx:

100 F low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA-R412M modules supporting 2G 10 F capacitor (or greater), for the other SARA-R4 series modules that do not support 2G A suitable series ferrite bead can be suitably placed on the VCC line for additional noise filtering if required by the specific application according to the whole application board design. Figure 26: Suggested schematic for the VCC bypass capacitors to reduce ripple / noise on supply voltage profile Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata Table 19: Suggested components to reduce ripple / noise on VCC The necessity of each part depends on the specific design, but it is recommended to provide all the bypass capacitors described in Figure 26 / Table 19 if the application device integrates an internal antenna. ESD sensitivity rating of the VCC supply pins is 1 kV (HBM according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if accessible battery connector is directly connected to the supply pins. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point. UBX-16029218 - R09 Design-in Page 52 of 115 C2GNDC5SARA-R4 series52VCC53VCC51VCCC13V8C3C4+SARA-R4 series - System Integration Manual 2.2.1.11 Guidelines for VCC supply layout design Good connection of the module VCC pins with DC supply source is required for correct RF performance. Guidelines are summarized in the following list:

All the available VCC pins must be connected to the DC source VCC connection must be as wide as possible and as short as possible Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be avoided VCC connection must be routed through a PCB area separated from RF lines / parts, sensitive analog signals and sensitive functional units: it is good practice to interpose at least one layer of PCB ground between the VCC track and other signal routing Coupling between VCC and digital lines, especially USB, must be avoided. The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.10 should be placed close to the VCC pins. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-DC output and minimize VCC track length. Otherwise consider using separate capacitors for DC-DC converter and module tank capacitor The bypass capacitors in the pF range described in Figure 26 and Table 19 should be placed as close as possible to the VCC pins, where the VCC line narrows close to the module input pins, improving the RF noise rejection in the band centered on the Self-Resonant Frequency of the pF capacitors. This is highly recommended if the application device integrates an internal antenna Since VCC input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting to the SARA-R4 series modules in the worst case Shielding of switching DC-DC converter circuit, or at least the use of shielded inductors for the switching DC-

DC converter, may be considered since all switching power supplies may potentially generate interfering signals as a result of high-frequency high-power switching. If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings are not exceeded, place the protecting device along the path from the DC source toward the module, preferably closer to the DC source (otherwise protection functionality may be compromised) 2.2.1.12 Guidelines for grounding layout design Good connection of the module GND pins with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module. Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The VCC supply current flows back to main DC source through GND as ground current: provide adequate return path with suitable uninterrupted ground plane to main DC source It is recommended to implement one layer of the application board as ground plane as wide as possible If the application board is a multilayer PCB, then all the board layers should be filled with GND plane as much as possible and each GND area should be connected together with complete via stack down to the main ground layer of the board. Use as many vias as possible to connect the ground planes Provide a dense line of vias at the edges of each ground area, in particular along RF and high speed lines If the whole application device is composed by more than one PCB, then it is required to provide a good and solid ground connection between the GND areas of all the different PCBs Good grounding of GND pads also ensures thermal heat sink. This is critical during connection, when the real network commands the module to transmit at maximum power: correct grounding helps prevent module overheating. UBX-16029218 - R09 Design-in Page 53 of 115 SARA-R4 series - System Integration Manual 2.2.2 Generic digital interfaces supply output (V_INT) 2.2.2.1 Guidelines for V_INT circuit design SARA-R4 series provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly used to:

Indicate when the module is switched on and it is not in the deep sleep power saving mode (as described in sections 1.6.1, 1.6.2) Pull-up SIM detection signal (see section 2.5 for more details) Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. see 2.6.1) Enable external voltage regulators providing supply for external devices Do not apply loads which might exceed the limit for maximum available current from V_INT supply (see the SARA-R4 series Data Sheet [1]) as this can cause malfunctions in internal circuitry. V_INT can only be used as an output: do not connect any external supply source on V_INT. ESD sensitivity rating of the V_INT supply pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the line is externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible point. It is recommended to monitor the V_INT pin to sense the end of the internal switch-off sequence of SARA-

R4 series modules: VCC supply can be removed only after V_INT goes low. It is recommended to provide direct access to the V_INT pin on the application board by means of an accessible test point directly connected to the V_INT pin. UBX-16029218 - R09 Design-in Page 54 of 115 SARA-R4 series - System Integration Manual 2.3 System functions interfaces 2.3.1 Module power-on (PWR_ON) 2.3.1.1 Guidelines for PWR_ON circuit design SARA-R4 series PWR_ON input is equipped with an internal active pull-up resistor; an external pull-up resistor is not required and should not be provided. If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection should be provided close to the accessible point, as described in Figure 27 and Table 20. ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if an accessible push button is directly connected to PWR_ON pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to the accessible point. An open drain or open collector output is suitable to drive the PWR_ON input from an application processor, as described in Figure 27. The PWR_ON input pin should not be driven high by an external device, as it may cause start up issues. Figure 27: PWR_ON application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD CT0402S14AHSG - EPCOS Varistor array for ESD protection Table 20: Example ESD protection component for the PWR_ON application circuit It is recommended to provide direct access to the PWR_ON pin on the application board by means of an accessible test point directly connected to the PWR_ON pin. 2.3.1.2 Guidelines for PWR_ON layout design The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on and switch off the SARA-R4 series modules. It is required to ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request. UBX-16029218 - R09 Design-in Page 55 of 115 SARA-R4 series15PWR_ONPower-on push buttonESDOpen Drain OutputApplication ProcessorSARA-R4 series15PWR_ONTPTP SARA-R4 series - System Integration Manual 2.3.2 Module reset (RESET_N) 2.3.2.1 Guidelines for RESET_N circuit design SARA-R4 series RESET_N is equipped with an internal pull-up; an external pull-up resistor is not required. If connecting the RESET_N input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device (e.g. the EPCOS CA05P4S14THSG varistor) should be provided close to accessible point on the line connected to this pin, as described in Figure 28 and Table 21. ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if an accessible push button is directly connected to the RESET_N pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point. An open drain output or open collector output is suitable to drive the RESET_N input from an application processor, as described in Figure 28. The RESET_N input pin should not be driven high by an external device, as it may cause start up issues. Figure 28: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD Varistor for ESD protection CT0402S14AHSG - EPCOS Table 21: Example of ESD protection component for the RESET_N application circuits If the external reset function is not required by the customer application, the RESET_N input pin can be left unconnected to external components, but it is recommended providing direct access on the application board by means of an accessible test point directly connected to the RESET_N pin. 2.3.2.2 Guidelines for RESET_N layout design The RESET_N circuit require careful layout due to the pin function: ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious reset request. It is recommended to keep the connection line to RESET_N pin as short as possible. UBX-16029218 - R09 Design-in Page 56 of 115 SARA-R4 series18RESET_NPower-on push buttonESDOpen Drain OutputApplication ProcessorSARA-R4 series18RESET_NTPTP SARA-R4 series - System Integration Manual 2.4 Antenna interface SARA-R4 series modules provide an RF interface for connecting the external antenna: the ANT pin represents the RF input/output for RF signals transmission and reception. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the physical antenna through a 50 transmission line to allow clean transmission / reception of RF signals. 2.4.1 Antenna RF interface (ANT) 2.4.1.1 General guidelines for antenna selection and design The antenna is the most critical component to be evaluated. Designers must take care of the antenna from all perspective at the very start of the design phase when the physical dimensions of the application board are under analysis/decision, since the RF compliance of the device integrating SARA-R4 series modules with all the applicable required certification schemes depends on antennas radiating performance. Cellular antennas are typically available as:

External antennas (e.g. linear monopole):

o External antennas basically do not imply physical restriction to the design of the PCB where the SARA-R4 series module is mounted. o The radiation performance mainly depends on the antennas. It is required to select antennas with optimal radiating performance in the operating bands. o RF cables should be carefully selected to have minimum insertion losses. Additional insertion loss will be introduced by low quality or long cable. Large insertion loss reduces both transmit and receive radiation performance. o A high quality 50 RF connector provides a clean PCB-to-RF-cable transition. It is recommended to strictly follow the layout and cable termination guidelines provided by the connector manufacturer. Integrated antennas (e.g. PCB antennas such as patches or ceramic SMT elements):

o Internal integrated antennas imply physical restriction to the design of the PCB:

Integrated antenna excites RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna: its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that needs to be radiated, given that the orientation of the ground plane relative to the antenna element must be considered. As numerical example, the physical restriction to the PCB design can be considered as following:

Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm o Radiation performance depends on the whole PCB and antenna system design, including product mechanical design and usage. Antennas should be selected with optimal radiating performance in the operating bands according to the mechanical specifications of the PCB and the whole product. o o o It is recommended to select a custom antenna designed by an antennas manufacturer if the required ground plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm wide). The antenna design process should begin at the start of the whole product design process It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and matching circuitry Further to the custom PCB and product restrictions, antennas may require tuning to obtain the required performance for compliance with all the applicable required certification schemes. It is recommended to consult the antenna manufacturer for the design-in guidelines for antenna matching relative to the custom application UBX-16029218 - R09 Design-in Page 57 of 115 SARA-R4 series - System Integration Manual In both of cases, selecting external or internal antennas, these recommendations should be observed:

Select an antenna providing optimal return loss (or VSWR) figure over all the operating frequencies. Select an antenna providing optimal efficiency figure over all the operating frequencies. Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified in some countries (e.g. by FCC in the United States, as reported in the section 4.2.2). 2.4.1.2 Guidelines for antenna RF interface design Guidelines for ANT pin RF connection design A clean transition between the ANT pad and the application board PCB must be provided, implementing the following design-in guidelines for the layout of the application PCB close to the ANT pad:

On a multilayer board, the whole layer stack below the RF connection should be free of digital lines Increase GND keep-out (i.e. clearance, a void area) around the ANT pad, on the top layer of the application PCB, to at least 250 m up to adjacent pads metal definition and up to 400 m on the area below the module, to reduce parasitic capacitance to ground, as described in the left picture in Figure 29 Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT pad if the top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground, as described in the right picture in Figure 29 Figure 29: GND keep-out area on top layer around ANT pad and on very close buried layer below ANT pad Guidelines for RF transmission line design Any RF transmission line, such as the ones from the ANT pad up to the related antenna connector or up to the related internal antenna pad, must be designed so that the characteristic impedance is as close as possible to 50 . RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is sandwiched between two parallel ground planes within a dielectric material). The micro strip, implemented as a coplanar waveguide, is the most common configuration for printed circuit board. UBX-16029218 - R09 Design-in Page 58 of 115 Min. 250 mMin. 400 mGNDANTGND clearance on very close buried layerbelow ANT padGND clearance on top layer around ANT pad SARA-R4 series - System Integration Manual Figure 30 and Figure 31 provide two examples of suitable 50 coplanar waveguide designs. The first example of RF transmission line can be implemented in case of 4-layer PCB stack-up herein described, and the second example of RF transmission line can be implemented in case of 2-layer PCB stack-up herein described. Figure 30: Example of 50 coplanar waveguide transmission line design for the described 4-layer board layup Figure 31: Example of 50 coplanar waveguide transmission line design for the described 2-layer board layup If the two examples do not match the application PCB stack-up, then the 50 characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation, or using freeware tools like AppCAD from Agilent (www.agilent.com) or TXLine from Applied Wave Research (www.mwoffice.com), taking care of the approximation formulas used by the tools for the impedance computation. To achieve a 50 characteristic impedance, the width of the transmission line must be chosen depending on:

the thickness of the transmission line itself (e.g. 35 m in the example of Figure 30 and Figure 31) the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner closer layer implementing the ground plane (e.g. 270 m in Figure 30, 1510 m in Figure 31) the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 30 and Figure 31) the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line

(e.g. 500 m in Figure 30, 400 m in Figure 31) If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the Coplanar Waveguide model for the 50 calculation. UBX-16029218 - R09 Design-in Page 59 of 115 35 m35 m35 m35 m270 m270 m760 mL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric380 m500 m500 m35 m35 m1510 mL2 CopperL1 CopperFR-4 dielectric1200 m400 m400 m SARA-R4 series - System Integration Manual Additionally to the 50 impedance, the following guidelines are recommended for transmission lines design:

Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB, Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component present on the RF transmission lines, if top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground, The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible: avoid abrupt changes of width and spacing to GND, Add GND stitching vias around transmission lines, as described in Figure 32, Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer, providing enough vias on the adjacent metal layer, as described in Figure 32, Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive circuit (as USB), Avoid stubs on the transmission lines, Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried metal layer, Do not route microstrip lines below discrete component or other mechanics placed on top layer Two examples of a suitable RF circuit design are illustrated in Figure 32, where the antenna detection circuit is not implemented (if the antenna detection function is required by the application, follow the guidelines for circuit and layout implementation detailed in section 2.4.2):

In the first example shown on the left, the ANT pin is directly connected to an SMA connector by means of a suitable 50 transmission line, designed with the appropriate layout. In the second example shown on the right, the ANT pin is connected to an SMA connector by means of a suitable 50 transmission line, designed with the appropriate layout, with an additional high pass filter to improve the ESD immunity at the antenna port. (The filter consists of a suitable series capacitor and shunt inductor, for example the Murata GRM1555C1H150JA01 15 pF capacitor and the Murata LQG15HN39NJ02 39 nH inductor with Self-Resonant Frequency ~1 GHz.). Figure 32: Example of circuit and layout for antenna RF circuits on the application board UBX-16029218 - R09 Design-in Page 60 of 115 SARA moduleSMAconnectorSARA moduleSMAconnectorHigh-pass filter toimprove ESD immunity SARA-R4 series - System Integration Manual Guidelines for RF termination design The RF termination must provide a characteristic impedance of 50 as well as the RF transmission line up to the RF termination, to match the characteristic impedance of the ANT port. However, real antennas do not have a perfect 50 load on all the supported frequency bands. So to reduce as much as possible any performance degradation due to antenna mismatching, the RF termination must provide optimal return loss (or VSWR) figures over all the operating frequencies, as summarized in Table 7. If an external antenna is used, the antenna connector represents the RF termination on the PCB:

Use suitable a 50 connector providing a clean PCB-to-RF-cable transition. Strictly follow the connector manufacturers recommended layout, for example:

o SMA Pin-Through-Hole connectors require a GND keep-out (i.e. clearance, a void area) on all the layers around the central pin up to the annular pads of the four GND posts, as shown in Figure 32 o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in the area below the connector between the GND land pads. Cut out the GND layer under the RF connector and close to any buried vias, to remove stray capacitance and thus keep the RF line at 50 , e.g. the active pad of UFL connector needs to have a GND keep-out (i.e. clearance, a void area) at least on the first inner layer to reduce parasitic capacitance to ground. If an integrated antenna is used, the integrated antenna represents the RF terminations. The following guidelines should be followed:

Use an antenna designed by an antenna manufacturer providing the best possible return loss (or VSWR). Provide a ground plane large enough according to the relative integrated antenna requirements. The ground plane of the application PCB can be reduced down to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that needs to be radiated. As numerical example, Frequency = 750 MHz Wavelength = 40 cm Minimum GND plane size = 10 cm It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including the PCB layout and matching circuitry. Further to the custom PCB and product restrictions, the antenna may require a tuning to comply with all the applicable required certification schemes. It is recommended to consult the antenna manufacturer for the design-in guidelines for the antenna matching relative to the custom application. Additionally, these recommendations regarding the antenna system placement must be followed:

Do not place the antenna within a closed metal case. Do not place the antenna in close vicinity to the end user since the emitted radiation in human tissue is restricted by regulatory requirements. Place the antenna far from sensitive analog systems or employ countermeasures to reduce EMC issues. Be aware of interaction between co-located RF systems since the LTE transmitted power may interact or disturb the performance of companion systems. UBX-16029218 - R09 Design-in Page 61 of 115 SARA-R4 series - System Integration Manual Examples of antennas Table 22 lists some examples of possible internal on-board surface-mount antennas. Manufacturer Part Number Product Name Description Taoglas PA.710.A Warrior Taoglas PCS.06.A Havok Taoglas MCS6.A Antenova SR4L002 Lucida Ethertronics P822601 Ethertronics P822602 Ethertronics 1002436 GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2690 MHz 42.0 x 10.0 x 3.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2690 MHz 42.0 x 10.0 x 3.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 35.0 x 8.5 x 3.2 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE Vertical Mount Antenna 698..960 MHz, 1710..2700 MHz 50.6 x 19.6 x 1.6 mm Pulse W3796 Domino GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz 42.0 x 10.0 x 3.0 mm TE Connectivity 2118310-1 Molex 1462000001 Cirocomm DPAN0S07 Table 22: Examples of internal surface-mount antennas GSM / WCDMA / LTE Vertical Mount Antenna 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 74.0 x 10.6 x 1.6 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1700..2700 MHz 40.0 x 5.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2700 MHz 37.0 x 5.0 x 5.0 mm UBX-16029218 - R09 Design-in Page 62 of 115 SARA-R4 series - System Integration Manual Table 23 lists some examples of possible internal off-board PCB-type antennas with cable and connector. Manufacturer Part Number Product Name Description Taoglas FXUB63.07.0150C Taoglas FXUB66.07.0150C Maximus Antenova SRFL029 Moseni Antenova SRFL026 Mitis Ethertronics 1002289 EAD FSQS35241-UF-10 SQ7 GSM / WCDMA / LTE PCB Antenna with cable and U.FL 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz 96.0 x 21.0 mm GSM / WCDMA / LTE PCB Antenna with cable and U.FL 698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz, 3400..3600 MHz, 4800..6000 MHz 120.2 x 50.4 mm GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 698..960 MHz, 1710..2700 MHz 140.0 x 75.0 mm GSM / WCDMA / LTE PCB Antenna with cable and U.FL 690..960 MHz, 1710..2170 MHz, 2500..2700 MHz 110.0 x 21.0 mm Table 23: Examples of internal antennas with cable and connector Table 24 lists some examples of possible external antennas. Manufacturer Part Number Product Name Description Taoglas GSA.8827.A.101111 Phoenix Taoglas TG.30.8112 Taoglas MA241.BI.001 Genesis Laird Tech. TRA6927M3PW-001 Laird Tech. CMS69273 Laird Tech. OC69271-FNM Pulse Electronics WA700/2700SMA Table 24: Examples of external antennas GSM / WCDMA / LTE adhesive-mount antenna with cable and SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz 105 x 30 x 7.7 mm GSM / WCDMA / LTE swivel dipole antenna with SMA(M) 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz 148.6 x 49 x 10 mm GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination antenna waterproof IP67 rated with cable and SMA(M) 698..960 MHz, 1710..2170 MHz, 2400..2700 MHz 205.8 x 58 x 12.4 mm GSM / WCDMA / LTE screw-mount antenna with N-type(F) 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 83.8 x 36.5 mm GSM / WCDMA / LTE ceiling-mount antenna with cable and N-type(F) 698..960 MHz, 1575.42 MHz, 1710..2700 MHz 86 x 199 mm GSM / WCDMA / LTE pole-mount antenna with N-type(M) 698..960 MHz, 1710..2690 MHz 248 x 24.5 mm GSM / WCDMA / LTE clip-mount MIMO antenna with cables and SMA(M) 698..960 MHz,1710..2700 MHz 149 x 127 x 5.1 mm UBX-16029218 - R09 Design-in Page 63 of 115 SARA-R4 series - System Integration Manual 2.4.2 Antenna detection interface (ANT_DET) 2.4.2.1 Guidelines for ANT_DET circuit design Figure 33 and Table 25 describe the recommended schematic / components for the antenna detection circuit that must be provided on the application board and for the diagnostic circuit that must be provided on the antennas assembly to achieve primary and secondary antenna detection functionality. Figure 33: Suggested schematic for antenna detection circuit on application board and diagnostic circuit on antenna assembly Reference Description Part Number - Manufacturer C1 C2 D1 L1 R1 J1 C3 L2 C4 L3 R2 27 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H270J - Murata 33 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H330J - Murata Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HS68NJ02 - Murata 10 k Resistor 0402 1% 0.063 W RK73H1ETTP1002F - KOA Speer SMA Connector 50 Through Hole Jack SMA6251A1-3GT50G-50 - Amphenol 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150J - Murata 39 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HN39NJ02 - Murata 22 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1H220J - Murata 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HS68NJ02 - Murata 15 k Resistor for Diagnostics Various Manufacturers Table 25: Suggested components for antenna detection circuit on application board and diagnostic circuit on antennas assembly The antenna detection circuit and diagnostic circuit suggested in Figure 33 and Table 25 are here explained:

When antenna detection is forced by the +UANTR AT command, the ANT_DET pin generates a DC current measuring the resistance (R2) from the antenna connector (J1) provided on the application board to GND. DC blocking capacitors are needed at the ANT pin (C2) and at the antenna radiating element (C4) to decouple the DC current generated by the ANT_DET pin. Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series at the ANT_DET pin (L1) and in series at the diagnostic resistor (L3), to avoid a reduction of the RF performance of the system, improving the RF isolation of the load resistor. Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR AT command. It also acts as an ESD protection. Additional components (C1 and D1 in Figure 33) are needed at the ANT_DET pin as ESD protection. Additional high pass filter (C3 and L2 in Figure 33) is provided at the ANT pin as ESD immunity improvement The ANT pin must be connected to the antenna connector by means of a transmission line with nominal characteristics impedance as close as possible to 50 . UBX-16029218 - R09 Design-in Page 64 of 115 Application BoardAntenna CableSARA-R4 series56ANT62ANT_DETR1C1D1L1C2J1Z0= 50 Z0= 50 Z0= 50 ohmAntenna AssemblyR2C4L3Radiating ElementDiagnostic CircuitGNDL2C3 SARA-R4 series - System Integration Manual The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 33, the measured DC resistance is always at the limits of the measurement range (respectively open or short), and there is no mean to distinguish between a defect on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example:

Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports the resistance value evaluated from the antenna connector provided on the application board to GND:

Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is correctly connected. Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit over range report (see the SARA-R4 series AT Commands Manual [2]) means that that the antenna is not connected or the RF cable is broken. Reported values below the measurement range minimum limit (1 k) highlights a short to GND at antenna or along the RF cable. Measurement inside the valid measurement range and outside the expected range may indicate an unclean connection, a damaged antenna or incorrect value of the antenna load resistor for diagnostics. Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method. If the antenna detection function is not required by the customer application, the ANT_DET pin can be left not connected and the ANT pin can be directly connected to the antenna connector by means of a 50 transmission line as described in Figure 32. UBX-16029218 - R09 Design-in Page 65 of 115 SARA-R4 series - System Integration Manual 2.4.2.2 Guidelines for ANT_DET layout design Figure 34 describes the recommended layout for the antenna detection circuit to be provided on the application board to achieve antenna detection functionality, implementing the recommended schematic described in the previous Figure 33 and Table 25:

The ANT pin must be connected to the antenna connector by means of a 50 transmission line, implementing the design guidelines described in section 2.4.1 and the recommendations of the SMA connector manufacturer. DC blocking capacitor at ANT pin (C2) must be placed in series to the 50 RF line. The ANT_DET pin must be connected to the 50 transmission line by means of a sense line. Choke inductor in series at the ANT_DET pin (L1) must be placed so that one pad is on the 50 transmission line and the other pad represents the start of the sense line to the ANT_DET pin. The additional components (R1, C1 and D1) on the ANT_DET line must be placed as ESD protection. The additional high pass filter (C3 and L2) on the ANT line are placed as ESD immunity improvement Figure 34: Suggested layout for antenna detection circuit on application board UBX-16029218 - R09 Design-in Page 66 of 115 SARA moduleC2R1D1C1L1J1C3L2 SARA-R4 series - System Integration Manual 2.5 SIM interface 2.5.1 Guidelines for SIM circuit design Guidelines for SIM cards, SIM connectors and SIM chips selection The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical and functional characteristics of Universal Integrated Circuit Cards (UICC), which contains the Subscriber Identification Module (SIM) integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the LTE network. Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as follows:

Contact C1 = VCC (Supply) Contact C2 = RST (Reset) Contact C3 = CLK (Clock) Contact C4 = AUX1 (Auxiliary contact) Contact C5 = GND (Ground) Contact C6 = VPP (Programming supply) Contact C7 = I/O (Data input/output) Contact C8 = AUX2 (Auxiliary contact) It must be connected to VSIM It must be connected to SIM_RST It must be connected to SIM_CLK It must be left not connected It must be connected to GND It can be left not connected It must be connected to SIM_IO It must be left not connected A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the auxiliary contacts C4 and C8. Only 6 contacts are required and must be connected to the module SIM interface. Removable SIM cards are suitable for applications requiring a change of SIM card during the product lifetime. A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided. Select a SIM connector providing 6+2 or 8+2 positions if the optional SIM detection feature is required by the custom application, otherwise a connector without integrated mechanical presence switch can be selected. Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as:

Case Pin 8 = UICC Contact C1 = VCC (Supply) It must be connected to VSIM Case Pin 7 = UICC Contact C2 = RST (Reset) It must be connected to SIM_RST Case Pin 6 = UICC Contact C3 = CLK (Clock) It must be connected to SIM_CLK Case Pin 5 = UICC Contact C4 = AUX1 (Aux.contact) It must be left not connected Case Pin 1 = UICC Contact C5 = GND (Ground) It must be connected to GND Case Pin 2 = UICC Contact C6 = VPP (Progr. supply) It can be left not connected Case Pin 3 = UICC Contact C7 = I/O (Data I/O) It must be connected to SIM_IO Case Pin 4 = UICC Contact C8 = AUX2 (Aux. contact) It must be left not connected A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other uses, but only 6 contacts are required and must be connected to the module SIM card interface as described above. Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed. UBX-16029218 - R09 Design-in Page 67 of 115 SARA-R4 series - System Integration Manual Guidelines for single SIM card connection without detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of SARA-R4 series modules as described in Figure 35, where the optional SIM detection feature is not implemented. Follow these guidelines to connect the module to a SIM connector without SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the relative pad of the SIM connector, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder. Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on each externally accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity rating of the SIM interface pins is 1 kV (HBM). So that, according to EMC/ESD requirements of the custom application, higher protection level can be required if the lines are externally accessible on the application device. Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum allowed rise time on clock line, 1.0 s is the maximum allowed rise time on data and reset lines). Figure 35: Application circuits for the connection to a single removable SIM card, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2, D3, D4 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics J1 SIM Card Holder, 6 p, without card presence switch Various manufacturers, as C707 10M006 136 2 - Amphenol Table 26: Example of components for the connection to a single removable SIM card, with SIM detection not implemented UBX-16029218 - R09 Design-in Page 68 of 115 SARA-R4 series41VSIM39SIM_IO38SIM_CLK40SIM_RSTSIM CARD HOLDERC5C6C7C1C2C3SIM Card Bottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5J1C4D1D2D3D4C8C4 SARA-R4 series - System Integration Manual Guidelines for single SIM chip connection A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of SARA-R4 series modules as described in Figure 36. Follow these guidelines to connect the module to a solderable SIM chip without SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the relative pad of the SIM chip, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM lines. Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum allowed rise time on clock line, 1.0 s is the maximum allowed rise time on data and reset lines). Figure 36: Application circuits for the connection to a single solderable SIM chip, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata SIM chip (M2M UICC Form Factor) Various Manufacturers Table 27: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented UBX-16029218 - R09 Design-in Page 69 of 115 SARA-R4 series41VSIM39SIM_IO38SIM_CLK40SIM_RSTSIM CHIPSIM ChipBottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5U1C4283671C1C5C2C6C3C7C4C887651234 SARA-R4 series - System Integration Manual Guidelines for single SIM card connection with detection An application circuit for the connection to a single removable SIM card placed in a SIM card holder is described in Figure 37, where the optional SIM card detection feature is implemented. Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module. Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module. Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module. Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. Connect the UICC / SIM contact C5 (GND) to ground. Connect one pin of the normally-open mechanical switch integrated in the SIM connector (as the SW2 pin in Figure 37) to the GPIO5 input pin, providing a weak pull-down resistor (e.g. 470 k, as R2 in Figure 37). Connect the other pin of the normally-open mechanical switch integrated in the SIM connector (SW1 pin in Figure 37) to V_INT 1.8 V supply output by means of a strong pull-up resistor (e.g. 1 k, as R1 in Figure 37) Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related pad of the SIM connector, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder. Provide a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each related pad of the SIM connector. The ESD sensitivity rating of SIM interface pins is 1 kV (HBM according to JESD22-A114), so that, according to the EMC/ESD requirements of the custom application, higher protection level can be required if the lines are externally accessible. Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface

(18.7 ns = maximum rise time on SIM_CLK, 1.0 s = maximum rise time on SIM_IO and SIM_RST). Figure 37: Application circuit for the connection to a single removable SIM card, with SIM detection implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 D1 D6 R1 R2 J1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W RC0402JR-071KL - Yageo Phycomp RC0402JR-07470KL- Yageo Phycomp SIM Card Holder 6 + 2 positions, with card presence switch Various Manufacturers, CCM03-3013LFT R102 - C&K Components Table 28: Example of components for the connection to a single removable SIM card, with SIM detection implemented UBX-16029218 - R09 Design-in Page 70 of 115 SARA-R4 series41VSIM39SIM_IO38SIM_CLK40SIM_RST4V_INT42GPIO5SIM CARD HOLDERC5C6C7C1C2C3SIM Card Bottom View (contacts side)C1VPP (C6)VCC (C1)IO (C7)CLK (C3)RST (C2)GND (C5)C2C3C5J1C4SW1SW2D1D2D3D4D5D6R2R1C8C4TP SARA-R4 series - System Integration Manual 2.5.2 Guidelines for SIM layout design The layout of the SIM card interface lines (VSIM, SIM_CLK, SIM_IO, SIM_RST may be critical if the SIM card is placed far away from the SARA-R4 series modules or in close proximity to the RF antenna: these two cases should be avoided or at least mitigated as described below. In the first case, the long connection can cause the radiation of some harmonics of the digital data frequency as any other digital interface. It is recommended to keep the traces short and avoid coupling with RF line or sensitive analog inputs. In the second case, the same harmonics can be picked up and create self-interference that can reduce the sensitivity of LTE receiver channels whose carrier frequency is coincidental with harmonic frequencies. It is strongly recommended to place the RF bypass capacitors suggested in Figure 35 near the SIM connector. In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges. Add adequate ESD protection as suggested to protect module SIM pins near the SIM connector. Limit capacitance and series resistance on each SIM signal to match the SIM specifications. The connections should always be kept as short as possible. Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some harmonics of the digital data frequency. UBX-16029218 - R09 Design-in Page 71 of 115 SARA-R4 series - System Integration Manual 2.6 Data communication interfaces 2.6.1 UART interface 2.6.1.1 Guidelines for UART circuit design Providing the full RS-232 functionality (using the complete V.24 link)7 If RS-232 compatible signal levels are needed, two different external voltage translators can be used to provide full RS-232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for the translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the translation from 3.3 V to RS-232 compatible signal level. If a 1.8 V Application Processor (DTE) is used and complete RS-232 functionality is required, then the complete 1.8 V UART interface of the module (DCE) should be connected to a 1.8 V DTE, as described in Figure 38. Figure 38: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 39. Figure 39: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Reference Description C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V U1, U2 Unidirectional Voltage Translator Part Number - Manufacturer GRM155R61A104KA01 - Murata SN74AVC4T7748 - Texas Instruments Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) 7 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input of the module must be set low to have URCs presented over UART on 00, 01 and 02 product versions. 8 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply UBX-16029218 - R09 Design-in Page 72 of 115 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TP0TP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2B3A3VCCBVCCAUnidirectionalVoltage TranslatorC3C43V0DIR1DIR3OEB2 A2B4A4DIR4DIR2TP0TP0TP0TP0TP SARA-R4 series - System Integration Manual Providing the TXD, RXD, RTS, CTS and DTR lines only (not using the complete V.24 link)9 If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available:

Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to RS-232 compatible signal level. Figure 40 describes the circuit that should be implemented as if a 1.8 V Application Processor (DTE) is used, given that the DTE will behave correctly regardless of the DSR input setting. Figure 40: UART interface application circuit with partial V.24 link (6-wire) in the DTE/DCE serial communication (1.8 V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 41, given that the DTE will behave correctly regardless of the DSR input setting. Figure 41: UART interface application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V U1 U2 Unidirectional Voltage Translator Unidirectional Voltage Translator Part Number - Manufacturer GRM155R61A104KA01 - Murata SN74AVC4T77410 - Texas Instruments SN74AVC2T24510 - Texas Instruments Table 30: Components for UART application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) 9 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input of the module must be set low to have URCs presented over UART on 00, 01 and 02 product versions. 10 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before the V_INT 1.8 V supply UBX-16029218 - R09 Design-in Page 73 of 115 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0 0 TPTP0 0 TPTP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2VCCBVCCAUnidirectionalVoltage TranslatorC33V0DIR1OEB2 A2DIR2C4 SARA-R4 series - System Integration Manual Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link)11 If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:

Connect the module DTR input to GND using a 0 series resistor, since it may be useful to set DTR active if not specifically handled, in particular to have URCs presented over the UART interface (see the SARA-R4 series AT Commands Manual [1] for the &D, S0, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor is used, the circuit should be implemented as described in Figure 42. Figure 42: UART interface application circuit with a partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 43. Figure 43: UART interface application circuit with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V Unidirectional Voltage Translator Part Number - Manufacturer GRM155R61A104KA01 - Murata SN74AVC4T77412 - Texas Instruments Table 31: Component for UART application circuit with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) 11 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input of the module must be set low to have URCs presented over UART on 00, 01 and 02 product versions. 12 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before the V_INT 1.8 V supply UBX-16029218 - R09 Design-in Page 74 of 115 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TP0TP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4 series (1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR4TP0TP0TP0TPTP SARA-R4 series - System Integration Manual Providing the TXD and RXD lines only (not using the complete V24 link) 13 If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, then:

Connect the module RTS input line to GND or to the CTS output line of the module, since the module requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, which is the default setting) Connect the module DTR input line to GND using a 0 series resistor, because it is useful to set DTR active if not specifically handled, in particular to have URCs presented over the UART interface (see the SARA-R4 series AT Commands Manual [1] for the &D, S0, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor (DTE) is used, the circuit that should be implemented as described in Figure 44 Figure 44: UART interface application circuit with a partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 45. Figure 45: UART interface application circuit with a partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V Unidirectional Voltage Translator Part Number - Manufacturer GRM155R61A104KA01 - Murata SN74AVC2T24514 - Texas Instruments Table 32: Component for UART application circuit with a partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) 13 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input of the module must be set low to have URCs presented over UART on 00, 01 and 02 product versions. 14 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before the V_INT 1.8 V supply UBX-16029218 - R09 Design-in Page 75 of 115 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD10RTS11CTS6DSR7RI8DCDGND0TP0TP0TPTP4V_INTTxDApplication Processor(3.0V DTE)RxDDTRDSRRIDCDGNDSARA-R4(1.8V DCE)12TXD9DTR13RXD6DSR7RI8DCDGND1V8B1 A1GNDU1VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR1DIR2OEVCCB2 A2RTSCTS10RTS11CTSTP0TP0TP0TPTP SARA-R4 series - System Integration Manual Additional considerations If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low-cost solution, by means of an appropriate voltage divider. Consider the value of the pull-down / pull-up integrated at the input of the module (DCE) for the correct selection of the voltage divider resistance values. Make sure that any DTE signal connected to the module is tri-stated or set low when the module is in power-down mode and during the module power-on sequence (at least until the activation of the V_INT supply output of the module), to avoid latch-up of circuits and allow a clean boot of the module (see the remark below). Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding 3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate low-cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for the appropriate selection of the resistance value for the external pull-up biased by the application processor supply rail. The TXD data input line has an internal active pull-down enabled on the 00 and 02 product versions, and an internal active pull-up enabled on the 01 product version. Do not apply voltage to any UART interface pin before the switch-on of the UART supply source (V_INT), to avoid latch-up of circuits and allow a clean boot of the module. If the external signals connected to the cellular module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on. ESD sensitivity rating of the UART interface pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection levels could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points. 2.6.1.2 Guidelines for UART layout design The UART serial interface requires the same consideration regarding electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. UBX-16029218 - R09 Design-in Page 76 of 115 SARA-R4 series - System Integration Manual 2.6.2 USB interface 2.6.2.1 Guidelines for USB circuit design The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer. USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.0 specification [4] are part of the module USB pins driver and do not need to be externally provided. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the SARA-R4 series Data Sheet [1]). Neither the USB interface nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. Routing the USB pins to a connector, they will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device with very low capacitance should be provided close to accessible point on the line connected to this pin, as described in Figure 46 and Table 33. The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-

140 ESD protection device) on the lines connected to these pins, close to accessible points. The USB pins of the modules can be directly connected to the USB host application processor without additional ESD protections if they are not externally accessible or according to EMC/ESD requirements. Figure 46: USB Interface application circuits Reference Description Part Number - Manufacturer C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics Table 33: Components for USB application circuits If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode defined in 3GPP Rel.13. If the USB interface pins are not used, they can be left unconnected on the application board, but it is strongly recommended to provide accessible test points directly connected to the USB interface pins

(VUSB_DET, USB_D+, USB_D-). UBX-16029218 - R09 Design-in Page 77 of 115 D+D-GND29USB_D+28USB_D-GNDUSB DEVICE CONNECTORVBUSD+D-GND29USB_D+28USB_D-GNDUSB HOST PROCESSORSARA-R4 series SARA-R4 series VBUS17VUSB_DET17VUSB_DETD1D2D3C1C10Test-Point0Test-Point0Test-Point SARA-R4 series - System Integration Manual 2.6.2.2 Guidelines for USB layout design The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to 480 Mb/s) supported by the USB serial interface. The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0 specification [4]. The most important parameter is the differential characteristic impedance applicable for the odd-

mode electromagnetic field, which should be as close as possible to 90 differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Use the following general routing guidelines to minimize signal quality problems:

Route USB_D+ / USB_D- lines as a differential pair Route USB_D+ / USB_D- lines as short as possible Ensure the differential characteristic impedance (Z0) is as close as possible to 90 Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30 Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area Figure 47 and Figure 48 provide two examples of coplanar waveguide designs with differential characteristic impedance close to 90 and common mode characteristic impedance close to 30 . The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB stack-up herein described. Figure 47: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 4-layer board layup Figure 48: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 2-layer board layup UBX-16029218 - R09 Design-in Page 78 of 115 35 m35 m35 m35 m270 m270 m760 mL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric350 m400 m400 m350 m400 m35 m35 m1510 mL2 CopperL1 CopperFR-4 dielectric740 m410 m410 m740 m410 m SARA-R4 series - System Integration Manual 2.6.3 SPI interface 2.6.3.1 Guidelines for SPI circuit design The SPI interface is not supported by 00, 01 and 02 product versions: the SPI interface pins should not be driven by any external device. 2.6.4 SDIO interface 2.6.4.1 Guidelines for SDIO circuit design The SDIO interface is not supported by 00, 01 and 02 product versions: the SDIO interface pins should not be driven by any external device. 2.6.5 DDC (I2C) interface 2.6.5.1 Guidelines for DDC (I2C) circuit design DDC (I2C) interface is not supported by 00 and 01 product versions: the DDC (I2C) interface pins should not be driven by any external device. The DDC I2C-bus master interface can be used to communicate with u-blox GNSS receivers and other external I2C-

bus slaves as an audio codec. The SDA and SCL pins of the module are open drain output as per I2C bus specifications [9], and they have internal pull-up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of additional pull-up resistors on the external application board. Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 s is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. ESD sensitivity rating of the DDC (I2C) pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the pins are not used as DDC bus interface, they can be left unconnected. UBX-16029218 - R09 Design-in Page 79 of 115 SARA-R4 series - System Integration Manual Connection with u-blox 1.8 V GNSS receivers Figure 49 shows an application circuit for connecting the cellular module to a u-blox 1.8 V GNSS receiver:

The SDA and SCL pins of the cellular module are directly connected to the related pins of the u-blox 1.8 V GNSS receiver. External pull-up resistors are not needed, as they are already integrated in the cellular module. The GPIO2 pin is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 1.8 V GNSS receiver providing the GNSS supply enable function. A pull-down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. The GPIO3 pin is connected to the TXD1 pin of the u-blox 1.8 V GNSS receiver providing the additional GNSS Tx data ready function. Figure 49: Application circuit for connecting SARA-R4 series modules to u-blox 1.8 V GNSS receivers Reference Description Part Number - Manufacturer R1 U1 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual Table 34: Components for connecting SARA-R4 series modules to u-blox 1.8 V GNSS receivers For additional guidelines regarding the design of applications with u-blox 1.8 V GNSS receivers, see the Hardware Integration Manual of the u-blox GNSS receivers. UBX-16029218 - R09 Design-in Page 80 of 115 INOUTGNDGNSS LDORegulatorSHDNu-blox GNSS1.8 V receiverSDA2SCL2VMAIN1V8U123GPIO2SDASCLC12627VCCR1GNSS supply enabledSARA-R4 series(except 00,01 versions)TxD1GPIO324GNSS data ready SARA-R4 series - System Integration Manual Connection with u-blox 3.0 V GNSS receivers Figure 50 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS receiver:

As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the related I2C pins of the u-blox 3.0 V GNSS receiver must be provided using a suitable I2C-bus Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down feature so that the GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular supply). External pull-up resistors are not needed on the cellular module side, as they are already integrated in the cellular module. The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 3.0 V GNSS receiver providing the GNSS supply enable function. A pull-down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. The GPIO3 pin is connected to the TXD1 pin of the u-blox 3.0 V GNSS receiver providing the additional GNSS Tx data ready function, using a suitable Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up before the V_INT 1.8 V cellular supply. Figure 50: Application circuit for connecting SARA-R4 series modules to u-blox 3.0 V GNSS receivers Reference Description R1, R2 R3 4.7 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W Part Number - Manufacturer RC0402JR-074K7L - Yageo Phycomp RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1, C1 U2 U3 Voltage Regulator for GNSS receiver and related output bypass capacitor See GNSS receiver Hardware Integration Manual I2C-bus Bidirectional Voltage Translator TCA9406DCUR - Texas Instruments Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 35: Components for connecting SARA-R4 series modules to u-blox 3.0 V GNSS receivers For additional guidelines regarding the design of applications with u-blox 3.0 V GNSS receivers see the Hardware Integration Manual of the u-blox GNSS receivers. Guidelines for DDC (I2C) layout design The DDC (I2C) serial interface requires the same consideration regarding electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. UBX-16029218 - R09 Design-in Page 81 of 115 u-blox GNSS 3.0 V receiver24GPIO31V8B1 A1GNDU3B2A2VCCBVCCAUnidirectionalVoltage TranslatorC4C53V0TxD1R1INOUTGNSS LDO RegulatorSHDNnR2VMAIN3V0U123GPIO226SDA27SCL1V8SDA_A SDA_BGNDU2SCL_ASCL_BVCCAVCCBI2C-bus Bidirectional Voltage Translator4V_INTC1C2C3R3SDA2SCL2VCCDIR1DIR2OEnOEGNSS data readyGNSS supply enabledGNDSARA-R4 series(except 00,01 versions) SARA-R4 series - System Integration Manual 2.7 Audio 2.7.1.1 Guidelines for Audio circuit design Audio is not supported by 00, 01 and 02 product versions: the I2S interface pins should not be driven by any external device. 2.8 General Purpose Input/Output 2.8.1.1 Guidelines for GPIO circuit design A typical usage of SARA-R4 series modules GPIOs can be the following:

Network indication provided over GPIO1 pin (see Figure 51 / Table 36 below) GNSS supply enable function provided by the GPIO2 pin (see section 2.6.5) GNSS Tx data ready function provided by the GPIO3 pin (see section 2.6.5) Module operating status indication provided by a GPIO pin (see section 1.6.1) SIM card detection provided over GPIO5 pin (see Figure 37 / Table 28 in section 2.5) Figure 51: Application circuit for network indication provided over GPIO1 Reference Description Part Number - Manufacturer R1 R2 R3 DL1 T1 10 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W 820 Resistor 0402 5% 0.1 W LED Red SMT 0603 NPN BJT Transistor Various manufacturers Various manufacturers Various manufacturers LTST-C190KRKT - Lite-on Technology Corporation BC847 - Infineon Table 36: Components for network indication application circuit Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO of SARA-R4 series modules. Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (V_INT), to avoid latch-up of circuits and allow a clean module boot. If the external signals connected to the module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on. ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the GPIO pins are not used, they can be left unconnected on the application board. 2.8.1.2 Guidelines for general purpose input/output layout design The general purpose inputs / outputs pins are generally not critical for layout. UBX-16029218 - R09 Design-in Page 82 of 115 SARA-R4 seriesGPIO1R1R33V8Network IndicatorR216DL1T1 SARA-R4 series - System Integration Manual 2.9 Reserved pins (RSVD) SARA-R4 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be externally connected to ground. 2.10 Module placement An optimized placement allows a minimum RF lines length and closer path from DC source for VCC. Make sure that the module, analog parts and RF circuits are clearly separated from any possible source of radiated energy. In particular, digital circuits can radiate digital frequency harmonics, which can produce Electro-Magnetic Interference that affects the module, analog parts and RF circuits performance. Implement suitable countermeasures to avoid any possible Electro-Magnetic Compatibility issue. Make sure that the module, RF and analog parts / circuits, and high speed digital circuits are clearly separated from any sensitive part / circuit which may be affected by Electro-Magnetic Interference, or employ countermeasures to avoid any possible Electro-Magnetic Compatibility issue. Provide enough clearance between the module and any external part: clearance of at least 0.4 mm per side is recommended to let suitable mounting of the parts. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the SARA-R4 series modules: avoid placing temperature sensitive devices close to the module. UBX-16029218 - R09 Design-in Page 83 of 115 SARA-R4 series - System Integration Manual 2.11 Module footprint and paste mask Figure 52 and Table 37 describe the suggested footprint (i.e. copper mask) and paste mask layout for SARA modules: the proposed land pattern layout reflects the modules pins layout, while the proposed stencil apertures layout is slightly different (see the F, H, I, J, O parameters compared to the F, H, I, J, O ones). The Non Solder Mask Defined (NSMD) pad type is recommended over the Solder Mask Defined (SMD) pad type, implementing the solder mask opening 50 m larger per side than the corresponding copper pad. The recommended solder paste thickness is 150 m, according to application production process requirements. Figure 52: SARA-R4 series modules suggested footprint and paste mask (application board top view) Parameter Value A B C D E F F 26.0 mm 16.0 mm 3.00 mm 2.00 mm 2.50 mm 1.05 mm 1.00 mm Parameter Value G H H I I J J 1.10 mm 0.80 mm 0.75 mm 1.50 mm 1.55 mm 0.30 mm 0.35 mm Parameter Value K L M1 M2 N O O 2.75 mm 2.75 mm 1.80 mm 3.60 mm 2.10 mm 1.10 mm 1.05 mm Table 37: SARA-R4 series modules suggested footprint and paste mask dimensions These are recommendations only and not specifications. The exact copper, solder and paste mask geometries, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. UBX-16029218 - R09 Design-in Page 84 of 115 KM1M1M2EGHJEANT pinBPin 1KGHJADDOOLNLIFFKM1M1M2EGHJEANT pinBPin 1KGHJADDOOLNLIFFStencil: 150 m SARA-R4 series - System Integration Manual 2.12 Thermal guidelines The module operating temperature range is specified in the SARA-R4 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power

(data upload in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks

(for example, see the Terminal Tx Power distribution for WCDMA, taken from operation on a live network, described in the GSMA TS.09 Battery Life Measurement and Current Consumption Technique [10]); however the application should be correctly designed to cope with it. During transmission at maximum RF power the SARA-R4 series modules generate thermal power that may exceed 0.5 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the actual antenna return loss, the transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition. The overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. The Module-to-Ambient thermal resistance value and the relative increase of module temperature will differ according to the specific mechanical deployments of the module, e.g. application PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. The increase of the thermal dissipation, i.e. the reduction of the Module-to-Ambient thermal resistance, will decrease the temperature of the modules internal circuitry for a given operating ambient temperature. This improves the device long-term reliability in particular for applications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application:

Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete thermal via stacked down to main ground layer. Provide a ground plane as wide as possible on the application board. Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power. Optimize the thermal design of any high-power components included in the application, such as linear regulators and amplifiers, to optimize overall temperature distribution in the application device. Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure) of the application device that integrates the module so that it provides good thermal dissipation. Beside the reduction of the Module-to-Ambient thermal resistance implemented by correct application hardware design, the increase of module temperature can be moderated by a correspondingly correct application software implementation:

Enable power saving configuration using the AT+CPSMS command Enable module connected mode for a given time period and then disable it for a time period long enough to adequately mitigate the temperature increase. UBX-16029218 - R09 Design-in Page 85 of 115 SARA-R4 series - System Integration Manual 2.13 Schematic for SARA-R4 series module integration 2.13.1 Schematic for SARA-R4 series modules Figure 53 is an example of a schematic diagram where a SARA-R4 series module 00, 01 or 02 product version is integrated into an application board, using all the available interfaces and functions of the module. Figure 53: Example of schematic diagram to integrate a SARA-R4 module using all available interfaces15 15 Flow control is not supported by 00, 01 and SARA-R410M-02B product versions, but the RTS input must be set low to use the UART on 00 and 01 versions. The DTR input of the module must be set low to have URCs presented over UART on 00, 01 and 02 product versions. UBX-16029218 - R09 Design-in Page 86 of 115 3V8GND100uF10nFSARA-R4 series52VCC53VCC51VCC68pFRSVD18RESET_NApplication ProcessorOpen drain output15PWR_ONOpen drain outputTPTP12TXD13RXD8DCD10RTS11CTS9DTR6DSR7RITPTPTXDRXDDCDRTSCTSDTRDSRRI1.8 V DTEGNDGNDUSB 2.0 hostD-D+28USB_D-29USB_D+VBUS17VUSB_DETTPTPGNDGND000047pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF41VSIM39SIM_IO38SIM_CLK40SIM_RST47pFSW1 SW24V_INT42GPIO5470kESDESDESDESDESDESD1kTPV_INT62ANT_DET10k27pFESD68nH56ConnectorExternal antenna33pFANTTP039nH15pF15pF100nF24GPIO3V_INTB1 A1GNDB2A2VCCBVCCASN74AVC2T245 Voltage Translator100nF100nF3V0TxD14.7kINOUTLDO RegulatorSHDNn4.7k3V83V023GPIO2V_INTSDA_A SDA_BGNDSCL_ASCL_BVCCAVCCBTCA9406DCURI2C Voltage Translator100nF100nF100nF47kSDA2SCL2VCCDIR1DIR2OEnOEGNDEXTINT0GPIO425u-blox GNSS3.0 V receiver26SDA27SCLNot supported by 00 and 01 product versionGND3V8Network Indicator16GPIO119GPIO6SDIO_CMDSDIO_D0SDIO_D3SDIO_D146474849SDIO_D2SDIO_CLK444536I2S_CLK / SPI_CLK34I2S_WA / SPI_MOSI35I2S_TXD / SPI_CS 37I2S_RXD / SPI_MISO SARA-R4 series - System Integration Manual 2.14 Design-in checklist This section provides a design-in checklist. 2.14.1 Schematic checklist The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at VCC pin within the operating range limits. DC supply must be capable of supporting the highest peak / pulse current consumption values and the maximum averaged current consumption values in connected mode, as specified in the SARA-R4 series Data Sheet [1]. VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in particular if the application device integrates an internal antenna. Do not apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range. Provide accessible test points directly connected to the following pins of the SARA-R4 series modules:

V_INT, PWR_ON and RESET_N for diagnostic purposes. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible. Check UART signals direction, as the modules signal names follow the ITU-T V.24 Recommendation [5]. Capacitance and series resistance must be limited on each high speed line of the USB interface. It is strongly recommended to provide accessible test points directly connected to the USB interface pins

(VUSB_DET, USB_D+ and USB_D- pins). Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Provide adequate precautions for EMC / ESD immunity as required on the application board. Do not apply voltage to any generic digital interface pin of SARA-R4 series modules before the switch-on of the generic digital interface supply source (V_INT). All unused pins can be left unconnected. UBX-16029218 - R09 Design-in Page 87 of 115 SARA-R4 series - System Integration Manual 2.14.2 Layout checklist The following are the most important points for a simple layout check:

Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT port

(antenna RF interface). Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM signals, high-speed digital lines such as USB, and other data lines). Optimize placement for minimum length of RF line. Check the footprint and paste mask designed for SARA-R4 series module as illustrated in section 2.11. VCC line should be wide and as short as possible. Route VCC supply line away from RF line / part and other sensitive analog lines / parts. The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the VCC pins, in particular if the application device integrates an internal antenna. Ensure an optimal grounding connecting each GND pin with application board solid ground layer. Use as many vias as possible to connect the ground planes on multilayer application board, providing a dense line of vias at the edges of each ground area, in particular along RF and high speed lines. Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity. USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 differential and 30 common mode) and should not be routed close to any RF line / part. 2.14.3 Antenna checklist Antenna termination should provide 50 characteristic impedance with V.S.W.R at least less than 3:1

(recommended 2:1) on operating bands in deployment geographical area. Follow the recommendations of the antenna producer for correct antenna installation and deployment

(PCB layout and matching circuitry). Ensure compliance with any regulatory agency RF radiation requirement, as reported in section 4.2.2 for United States and in section 4.3.1 for Canada. Ensure high isolation between the cellular antenna and any other antennas or transmitters present on the end device. UBX-16029218 - R09 Design-in Page 88 of 115 SARA-R4 series - System Integration Manual 3 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 3.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to SARA-R4 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning, see the SARA-R4 series Data Sheet [1] and the u-blox Package Information Guide [15]. 3.2 Handling The SARA-R4 series modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. The term is usually used in the electronics and other industries to describe momentary unwanted currents that may cause damage to electronic equipment. The ESD sensitivity for each pin of SARA-R4 series modules (as Human Body Model according to JESD22-A114F) is specified in the SARA-R4 series Data Sheet [1]. ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working station or a large manufacturing area. The main principle of an EPA is that there are no highly charging materials near ESD sensitive electronics, all conductive materials are grounded, workers are grounded, and charge build-up on ESD sensitive electronics is prevented. International standards are used to define typical EPA and can be obtained for example from the International Electrotechnical Commission (IEC) or the American National Standards Institute (ANSI). In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the SARA-R4 series modules:

Unless there is a galvanic coupling between the local GND (i.e. the work table) and the PCB GND, then the first point of contact when handling the PCB must always be between the local GND and PCB GND. Before mounting an antenna patch, connect the ground of the device. When handling the module, do not come into contact with any charged capacitors and be careful when contacting materials that can develop charges (e.g. patch antenna, coax cable, soldering iron). To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If there is any risk that such exposed antenna area is touched in a non-ESD protected work area, implement adequate ESD protection measures in the design. When soldering the module and patch antennas to the RF pin, make sure to use an ESD-safe soldering iron. UBX-16029218 - R09 Handling and soldering Page 89 of 115 SARA-R4 series - System Integration Manual 3.3 Soldering 3.3.1 Soldering paste

"No Clean" soldering paste is strongly recommended for SARA-R4 series modules, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature: 217 C Stencil Thickness:

150 m for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.11. The quality of the solder joints should meet the appropriate IPC specification. 3.3.2 Reflow soldering A convection type-soldering oven is strongly recommended for SARA-R4 series modules over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the IPC-7530A Guidelines for temperature profiling for mass soldering (reflow and wave) processes. Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device!

Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. Note that this preheat phase will not replace prior baking procedures. Temperature rise rate: max 3 C/s Time: 60 120 s End Temperature: +150 - +200 C Heating/ reflow phase If the temperature rise is too rapid in the preheat phase it may cause excessive slumping. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. The temperature rises above the liquidus temperature of +217 C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above +217 C liquidus temperature: 40 - 60 s Peak reflow temperature: +245 C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4 C/s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. UBX-16029218 - R09 Handling and soldering Page 90 of 115 SARA-R4 series - System Integration Manual The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Figure 54: Recommended soldering profile The modules must not be soldered with a damp heat process. 3.3.3 Optical inspection After soldering the module, inspect it optically to verify that the module is correctly aligned and centered. 3.3.4 Cleaning Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-

jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results, use a "no clean" soldering paste and eliminate the cleaning step after the soldering. 3.3.5 Repeated reflow soldering Repeated reflow soldering processes and soldering the module upside-down are not recommended. Boards with components on both sides may require two reflow cycles. In this case, the module should always be placed on the side of the board that is submitted into the last reflow cycle. The reason for this (besides others) is the risk of the module falling off due to the significantly higher weight in relation to other components. u-blox gives no warranty against damages to the SARA-R4 series modules caused by performing more than a total of two reflow soldering processes (one reflow soldering process to mount the SARA-R4 series module, plus one reflow soldering process to mount other parts). UBX-16029218 - R09 Handling and soldering Page 91 of 115 PreheatHeatingCooling[C]Peak Temp. 245C[C]250250Liquidus Temperature21721720020040 - 60 sEnd Temp.max 4C/s150 - 200C150150max 3C/s60 - 120 s100Typical Leadfree100Soldering Profile5050Elapsed time [s]SARA-R4 series - System Integration Manual 3.3.6 Wave soldering SARA-R4 series LGA modules must not be soldered with a wave soldering process. Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. No more than one wave soldering process is allowed for a board with a SARA-R4 series module already populated on it. Performing a wave soldering process on the module can result in severe damage to the device!

u-blox gives no warranty against damages to the SARA-R4 series modules caused by performing more than a total of two soldering processes (one reflow soldering process to mount the SARA-R4 series module, plus one wave soldering process to mount other THT parts on the application board). 3.3.7 Hand soldering Hand soldering is not recommended. 3.3.8 Rework Rework is not recommended. Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty. 3.3.9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials affect the HF properties of the cellular modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating. Conformal Coating of the module will void the warranty. 3.3.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the cellular modules before implementing this in production. Casting will void the warranty. 3.3.11 Grounding metal covers Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interference and noise. u-blox gives no warranty for damages to the cellular modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. 3.3.12 Use of ultrasonic processes The cellular modules contain components which are sensitive to ultrasonic waves. Use of any ultrasonic processes

(cleaning, welding etc.) may cause damage to the module. u-blox gives no warranty against damages to the cellular modules caused by any ultrasonic processes. UBX-16029218 - R09 Handling and soldering Page 92 of 115 SARA-R4 series - System Integration Manual 4 Approvals 4.1 Product certification approval overview Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications, typically called certification schemes, that can be divided into three distinct categories:

Regulatory certification o Country-specific approval required by local government in most regions and countries, such as:

CE (Conformit Europenne) marking for European Union FCC (Federal Communications Commission) approval for the United States Industry certification o Telecom industry-specific approval verifying the interoperability between devices and networks:

GCF (Global Certification Forum), partnership between European device manufacturers and network operators to ensure and verify global interoperability between devices and networks PTCRB (PCS Type Certification Review Board), created by United States network operators to ensure and verify interoperability between devices and North America networks Operator certification o Operator-specific approvals required by some mobile network operator, such as:

AT&T network operator in United States Verizon Wireless network operator in United States SARA-R4 series modules are approved under all major certification schemes, as summarized in Table 38. Certification scheme SARA-R404M-00B SARA-R410M-01B SARA-R410M-02B GCF conformance PTCRB conformance CE Europe regulatory FCC US regulatory FCC ID M1 Bands 3, 5, 8, 13, 20, 28 M1 Bands 2, 4, 5, 12 M1, NB1 Bands 2, 3, 4, 5, 8, 12, 13, 20, 28 M1, NB1 Bands 3, 8, 20 M1 Band 13 XPY2AGQN1NNN M1 Bands 2, 4, 5, 12 XPY2AGQN4NNN M1, NB1 Bands 2, 4, 5, 12, 13 XPY2AGQN4NNN ISED Canada regulatory ISED ID IFT Mexico regulatory RCM Australia regulatory NCC Taiwan regulatory Verizon network operator M1 Band 13 AT&T network operator Bell network operator Telus network operator Telstra network operator M1 Bands 2, 4, 5, 12 8595A-2AGQN4NNN M1, NB1 Bands 2, 4, 5, 12, 13 8595A-2AGQN4NNN M1 Bands 2, 4, 5, 12 M1 Bands 3, 5, 8, 28 M1, NB1 Bands 3, 8, 28 M1 Bands 4, 13 M1 Bands 2, 4, 5, 12 M1 Bands 2, 4, 5, 12 M1 Bands 2, 4, 5, 12 M1 Bands 2, 4, 5, 12 M1 Bands 3, 5, 8, 28 Table 38: Summary of certification approvals achieved for the SARA-R4 series modules, with related RAT and Bands For the complete list and specific details regarding the certification approvals of SARA-R4 series modules, including certificates of compliancy, please contact the u-blox office or sales representative nearest you. UBX-16029218 - R09 Approvals Page 93 of 115 SARA-R4 series - System Integration Manual The manufacturer of the end-device that integrates a SARA-R4 series module has to take care of all the certification schemes approvals required by the specific integrating device to be deployed in the market. The required certification scheme approvals and relative testing specifications applicable to the end-device that integrates a SARA-R4 series module differ depending on the country or the region where the integrating device is intended to be deployed, on the relative vertical market of the device, on type, features and functionalities of the whole application device, and on the network operators where the device is intended to operate. It has to be noted that the 02 product versions onwards of SARA-R4 series modules include the capability to configure the device selecting the operating Mobile Network Operator Profile, Radio Access Technology, and Band:

see SARA-R4 series AT Commands Manual [2], +UMNOPROF, +URAT, and +UBANDMASK AT commands. As these configuration decisions are made, u-blox reminds manufacturers of the end-device integrating the 02 product versions onwards of SARA-R4 series modules to take care of compliance with all the certification approvals requirements applicable to the specific integrating device to be deployed in the market. Check the appropriate applicability of the SARA-R4 series modules approvals while starting the certification process of the device integrating the module: the re-use of the u-blox cellular modules approval can significantly reduce the cost and time to market of the application device certification. The certification of the application device that integrates a SARA-R4 series module and the compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. SARA-R4 series modules are certified according to all capabilities and options stated in the Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to the 3GPP TS 36.521-2 [12] and 3GPP TS 36.523-2 [13], is a statement of the implemented and supported capabilities and options of a device. The PICS document of the application device integrating SARA-R4 series modules must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see the SARA-R4 series AT Commands Manual [1]. Check the specific settings required for mobile network operators approvals as they may differ from the AT commands settings defined in the module as integrated in the application device. UBX-16029218 - R09 Approvals Page 94 of 115 SARA-R4 series - System Integration Manual 4.2 US Federal Communications Commission notice United States Federal Communications Commission (FCC) IDs:

u-blox SARA-R404M cellular modules: XPY2AGQN1NNN u-blox SARA-R410M cellular modules: XPY2AGQN4NNN 4.2.1 Safety warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product The clearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, hygroscopic materials, or materials containing asbestos are employed 4.2.2 Declaration of Conformity This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R4 series modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the value specified in the FCC Grant for mobile and fixed or mobile operating configurations:

o SARA-R404M modules:

o 13 dBi in 750 MHz, i.e. LTE FDD-13 band o SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band o SARA-R410M-02B modules:

o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band UBX-16029218 - R09 Approvals Page 95 of 115 SARA-R4 series - System Integration Manual 4.2.3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the SARA-R4 series modules are authorized to use the FCC Grants of the SARA-R4 series modules for their own final products according to the conditions referenced in the certificates. The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o For SARA-R404M modules: "Contains FCC ID: XPY2AGQN1NNN"

o For SARA-R410M modules: "Contains FCC ID: XPY2AGQN4NNN"

IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4 series modules are required to have their final product certified and apply for their own FCC Grant related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Additional Note: as per 47CFR15.105 this equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

o Reorient or relocate the receiving antenna o Increase the separation between the equipment and receiver o Connect the equipment into an outlet on a circuit different from that to which the receiver is connected o Consultant the dealer or an experienced radio/TV technician for help UBX-16029218 - R09 Approvals Page 96 of 115 SARA-R4 series - System Integration Manual 4.3 Innovation, Science and Economic Development Canada notice ISED Canada (formerly known as IC - Industry Canada) Certification Numbers:

u-blox SARA-R410M cellular modules:

8595A-2AGQN4NNN 4.3.1 Declaration of Conformity This device complies with the ISED Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R4 series modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the value stated in the ISED Canada Grant for mobile and fixed or mobile operating configurations:

o SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band o SARA-R410M-02B modules:

o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band 4.3.2 Modifications ISED Canada requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the SARA-R4 series modules are authorized to use the ISED Canada Certificates of the SARA-R4 series modules for their own final products according to the conditions referenced in the certificates. The ISED Canada Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o For SARA-R410M modules: "Contains IC: 8595A-2AGQN4NNN"

UBX-16029218 - R09 Approvals Page 97 of 115 SARA-R4 series - System Integration Manual Innovation, Science and Economic Development Canada (ISED) Notices This Class B digital apparatus complies with Canadian CAN ICES-3(B) / NMB-3(B). Operation is subject to the following two conditions:

o o this device may not cause interference this device must accept any interference, including interference that may cause undesired operation of the device Radio Frequency (RF) Exposure Information The radiated output power of the u-blox Cellular Module is below the Innovation, Science and Economic Development Canada (ISED) radio frequency exposure limits. The u-blox Cellular Module should be used in a manner such that the potential for human contact during normal operation is minimized. This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20 cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canadas REL

(Radio Equipment List) can be found at the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng Additional Canadian information on RF exposure also can be found at the following web address:

http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4 series modules are required to have their final product certified and apply for their own Industry Canada Certificate related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Avis d'Innovation, Sciences et Dveloppement conomique Canada (ISDE) Cet appareil numrique de classe B est conforme aux normes canadiennes CAN ICES-3(B) /

NMB-3(B). Son fonctionnement est soumis aux deux conditions suivantes:

o o cet appareil ne doit pas causer d'interfrence cet appareil doit accepter toute interfrence, notamment les interfrences qui peuvent affecter son fonctionnement Informations concernant l'exposition aux frquences radio (RF) La puissance de sortie mise par lappareil de sans-fil u-blox Cellular Module est infrieure la limite d'exposition aux frquences radio d'Innovation, Sciences et Dveloppement conomique Canada (ISDE). Utilisez lappareil de sans-fil u-blox Cellular Module de faon minimiser les contacts humains lors du fonctionnement normal. Ce priphrique a t valu et dmontr conforme aux limites d'exposition aux frquences radio

(RF) d'IC lorsqu'il est install dans des produits htes particuliers qui fonctionnent dans des conditions d'exposition des appareils mobiles (les antennes se situent plus de 20 centimtres du corps d'une personne). Ce priphrique est homologu pour l'entre correspondant lappareil dans la liste d'quipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

l'utilisation au Canada. Pour consulter http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplmentaires concernant l'exposition aux RF au Canada rendez-vous sur: http://www.ic.gc.ca/eic/site/smt-gst.nsf/fra/sf08792.html UBX-16029218 - R09 Approvals Page 98 of 115 SARA-R4 series - System Integration Manual IMPORTANT: les fabricants d'applications portables contenant les modules de la SARA-R4 series doivent faire certifier leur produit final et dposer directement leur candidature pour une certification FCC ainsi que pour un certificat ISDE Canada dlivr par l'organisme charg de ce type d'appareil portable. Ceci est obligatoire afin d'tre en accord avec les exigences SAR pour les appareils portables. Tout changement ou modification non expressment approuv par la partie responsable de la certification peut annuler le droit d'utiliser l'quipement. 4.4 European Conformance CE mark The SARA-R410M-02B module product version has been evaluated against the essential requirements of the Radio Equipment Directive 2014/53/EU. In order to satisfy the essential requirements of the 2014/53/EU RED, the modules are compliant with the following standards:

Radio Spectrum Efficiency (Article 3.2):

o EN 301 908-1 o EN 301 908-13 Electromagnetic Compatibility (Article 3.1b):

o EN 301 489-1 o EN 301 489-52 Health and Safety (Article 3.1a) o EN 62368-1 o EN 62311 Radiofrequency radiation exposure Information: this equipment complies with radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the SARA-R410M-02B modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the values stated in the Declaration of Conformity of the modules, for mobile and fixed or mobile operating configurations:

o 8.2 dBi in 800 MHz, i.e. LTE FDD-20 band o 8.4 dBi in 900 MHz, i.e. LTE FDD-8 band o 11.3 dBi in 1800 MHz, i.e. LTE FDD-3 band The conformity assessment procedure for SARA-R410M-02B module, referred to in Article 17 and detailed in Annex II of Directive 2014/53/EU, has been followed. Thus, the following marking is included in the product:

UBX-16029218 - R09 Approvals Page 99 of 115 SARA-R4 series - System Integration Manual 4.5 Taiwanese National Communication Commission The SARA-R410M-02B module product version has the applicable regulatory approval for Taiwan (NCC) SARA-R410M-02B modules NCC ID: CCAA18NB0010T3 UBX-16029218 - R09 Approvals Page 100 of 115 CCAA18NB0010T3 SARA-R4 series - System Integration Manual 5 Product testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested automatically on the production line. Stringent quality control processes have been implemented in the production line. Defective units are analyzed in detail to improve production quality. This is achieved with automatic test equipment (ATE) in the production line, which logs all production and measurement data. A detailed test report for each unit can be generated from the system. Figure 55 illustrates the typical automatic test equipment (ATE) in a production line. The following typical tests are among the production tests. Digital self-test (firmware download, flash firmware verification, IMEI programming) Measurement of voltages and currents Adjustment of ADC measurement interfaces Functional tests (serial interface communication, SIM card communication) Digital tests (GPIOs and other interfaces) Measurement and calibration of RF characteristics in all supported bands (such as receiver S/N verification, frequency tuning of the reference clock, calibration of transmitter and receiver power levels, etc.) Verification of the RF characteristics after calibration (i.e. modulation accuracy, power levels, spectrum, etc. are checked to ensure they are all within tolerances when calibration parameters are applied) Figure 55: Automatic test equipment for module tests UBX-16029218 - R09 Product testing Page 101 of 115 SARA-R4 series - System Integration Manual 5.2 Test parameters for OEM manufacturers Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat the firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. However, an OEM manufacturer should focus on:

Module assembly on the device; it should be verified that:

o The soldering and handling process did not damage the module components o All module pins are well soldered on the device board o There are no short circuits between pins Component assembly on the device; it should be verified that:

o Communication with the host controller can be established o The interfaces between the module and device are working o Overall RF performance test of the device including the antenna Dedicated tests can be implemented to check the device. For example, the measurement of the module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result. In addition, module AT commands can be used to perform functional tests on the digital interfaces (communication with the host controller, check the SIM interface, GPIOs, etc.) or to perform RF performance tests (see the following section 5.2.2 for details). 5.2.1 Go/No go tests for integrated devices A Go/No go test is typically used to compare the signal quality with a Golden Device in a location with excellent network coverage and known signal quality. This test should be performed after the data connection has been established. These kinds of test may be useful as a go/no go test but not for RF performance measurements. This test is suitable to check the functionality of communications with the host controller, the SIM card and the power supply. It is also a means to verify if components at the antenna interface are well-soldered. 5.2.2 RF functional tests The overall RF functional test of the device including the antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator with the assistance of the AT+UTEST command over the AT command user interface. The AT+UTEST command provides a simple interface to set the module to Rx or Tx test modes ignoring the LTE signaling protocol. The command can set the module into:

transmitting mode in a specified channel and power level in all supported bands receiving mode in a specified channel to return the measured power level in all supported bands See the SARA-R4 series AT Commands Manual [2] for the AT+UTEST command syntax description and detail guide of usage. UBX-16029218 - R09 Product testing Page 102 of 115 SARA-R4 series - System Integration Manual This feature allows the measurement of the transmitter and receiver power levels to check the component assembly related to the module antenna interface and to check other device interfaces on which the RF performance depends. To avoid module damage during a transmitter test, a suitable antenna according to module specifications or a 50 termination must be connected to the ANT port. To avoid module damage during a receiver test, the maximum power level received at the ANT port must meet module specifications. The AT+UTEST command sets the module to emit RF power ignoring LTE signaling protocol. This emission can generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing purposes in controlled environments by qualified users and must not be used during the normal module operation. Follow the instructions suggested in the u-blox documentation. u-blox assumes no responsibilities for the inappropriate use of this feature. Figure 56 illustrates a typical test setup for such an RF functional test. Figure 56: Setup with spectrum analyzer or power meter and signal generator for radiated measurements UBX-16029218 - R09 Product testing Page 103 of 115 Application BoardSARA-R4 seriesANTApplication ProcessorAT commandsCellular antennaSpectrumAnalyzerorPowerMeterINWideband antennaTXApplication BoardSARA-R4 seriesApplication ProcessorAT commandsSignalGeneratorOUTWideband antennaRXANTCellular antenna SARA-R4 series - System Integration Manual Appendix A Migration between SARA modules A.1 Overview The SARA-G3 2G modules, the SARA-U2 3G / 2G modules, the SARA-R4 LTE Cat M1/NB1 / 2G modules and the SARA-N2 LTE Cat NB1 modules have exactly the same u-blox SARA form factor (26.0 x 16.0 mm, 96-pin LGA), with compatible pin assignments, as shown in Figure 57. Any one of the modules can be mounted on a single application board using exactly the same copper mask, solder mask and paste mask. Figure 57: SARA-G3, SARA-U2, SARA-R4 and SARA-R4 series modules layout and pin assignment SARA modules are also form-factor compatible with the u-blox LISA, LARA and TOBY cellular module families:

although each has a different form factor, the footprints for the TOBY, LISA, SARA and LARA modules have been developed to ensure layout compatibility. With the u-blox nested design solution, any TOBY, LISA, SARA or LARA module can be alternatively mounted on the same space of a single nested application board as described in Figure 58. Guidelines for implementing a nested application board, a description of the u-blox reference nested design and a comparison between the TOBY, LISA, SARA and LARA modules are provided in the Nested Design Application Note [21]. Figure 58: TOBY, LISA, SARA, LARA modules layout compatibility: all modules are accommodated on the same nested footprint UBX-16029218 - R09 Appendix Page 104 of 115 646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTRSVDGNDGPIO6RESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDVUSB_DETGNDGNDUSB_D-USB_D+RSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDSDIO_D2SDIO_CMDSDIO_D0SDIO_D1GNDVCCVCCRSVDI2S_TXD/SPI_CSI2S_CLK/SPI_CLKSIM_CLKSIM_IOVSIMGPIO5VCCSDIO_D3SDIO_CLKSIM_RSTI2S_RXD/SPI_MISOI2S_WA/SPI_MOSIGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-R4Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTV_BCKPGNDRSVDRESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDRSVDGNDGNDRXD_AUXTXD_AUXRSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDSPK_PMIC_BIASMIC_GNDMIC_PGNDVCCVCCRSVDI2S_TXDI2S_CLKSIM_CLKSIM_IOVSIMSIM_DETVCCMIC_NSPK_NSIM_RSTI2S_RXDI2S_WAGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-G3Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSDCDRIV_INTV_BCKPGNDCODEC_CLKRESET_NGPIO1PWR_ONRXDTXD320171496242730514845403734596256GNDGNDDSRDTRGNDVUSB_DETGNDGNDUSB_D-USB_D+RSVDGNDGPIO2GPIO3SDASCLGPIO4GNDGNDGNDRSVDRSVDRSVDRSVDGNDVCCVCCRSVDI2S_TXDI2S_CLKSIM_CLKSIM_IOVSIMSIM_DETVCCRSVDRSVDSIM_RSTI2S_RXDI2S_WAGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-U2Top ViewPin 65-96: GND646361605857555422232526282931321110875421211918161513124344464749505253333536383941426566676869707172737475767778798081828384858687888990919293949596CTSRTSRSVDRSVDV_INTRSVDGNDRSVDRESET_NGPIO1RSVDRXDTXD320171496242730514845403734596256GNDGNDRSVDRSVDGNDRSVDGNDGNDRSVDRSVDRSVDGNDRSVDGPIO2SDASCLRSVDGNDGNDGNDRSVDRSVDRSVDRSVDGNDVCCVCCRSVDRSVDRSVDSIM_CLKSIM_IOVSIMRSVDVCCRSVDRSVDSIM_RSTRSVDRSVDGNDGNDGNDGNDGNDGNDGNDGNDGNDANT_DETANTSARA-N2Top ViewPin 65-96: GNDLISA cellular moduleLARA cellular moduleSARA cellular moduleNested application boardTOBY cellular module SARA-R4 series - System Integration Manual Table 39 summarizes the interfaces provided by the SARA-G3, SARA-U2, SARA-R4 and SARA-R4 series modules, while Figure 59 summarizes the frequency ranges of the modules operating bands. Modules RAT Power System SIM Serial Audio Other t u p n i y l p p u s e u d o M l t u p t u O y l p p u s V 8

. 1 O

/

I y l p p u s C T R t u p n i n o

-

h c t i w S t u p n i f f o

-

h c t i w S e c a f r e t n i M S I n o i t c e t e d M S I t u p n i t e s e R X U A T R A U I P S T R A U B S U SARA-G3 2G SARA-U2 3G, 2G SARA-R4 LTE M1 / NB1, 2G SARA-N2 LTE NB1

) C 2 I

(

C D D I O D S t u p t u o z H M 6 2

/

3 1 i o d u a g o a n A l i o d u a l a t i g D i n o i t a c i d n i k r o w t e N n o i t c e t e d a n n e t n A m e d o m a i v S S N G s O P G I

= supported by available product version

= supported by future product versions Table 39: Summary of SARA-G3, SARA-U2, SARA-R4 and SARA-R4 series modules interfaces Figure 59: Summary of operating frequency bands supported by SARA-G3, SARA-U2, SARA-R4 and SARA-R4 series modules UBX-16029218 - R09 Appendix Page 105 of 115 880SARA-G300 SARA-G340SARA-G310 SARA-G350SARA-U260SARA-U270SARA-U280SARA-U20190080085090095090018001800170017501800185019001950200020502100215022008809601710188075085090085080085090095090018001900190018001700175018001850190019502000205021002150220082496017101990750700700800850900950VVIIII8508501900190017001750180018501900195020002050210021502200824894185019907507009008008509009509001800180017001750180018501900195020002050210021502200IIVIIIVIII96017102170750700800850900950VVIIII1700175018001850190019502000205021002150220082489418501990750700IIII850900800850900950900180019001900180017001750180018501900195020002050210021502200IIVIIIVIII82496017102170750700VXIXXIXV850SARA-R404M800850900950170017501800185019001950200020502100215022001313746787750700824894960880= 3G bands= 2G bands= LTE Cat M1 bandsLEGENDA= LTE Cat NB1 bands2020SARA-N20080085090095017001750180018501900195020002050210021502200750700SARA-N20180085090095017001750180018501900195020002050210021502200750700SARA-N21080085090095017001750180018501900195020002050210021502200791862750700SARA-N21180085090095017001750180018501900195020002050210021502200791960750700SARA-N2808008509009501700175018001850190019502000205021002150220080375070088552020882828703SARA-R410M800850900950170017501800185019001950200020502100215022006991710750700960217012442212551313283311882819191717202026262525124422125513132833118828191917172020392626252518181818SARA-R412M8008509009501700175018001850190019502000205021002150220069917107507009602170124422125513132833118828191917172020262625251244221255131328331188281919171720203926262525181818188509009001800190019001800850 A.2 Pin-out comparison between the SARA-G3, SARA-U2, SARA-R4 and SARA-N2 modules SARA-R4 series - System Integration Manual SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration No 1 2 3 4 5 6 7 8 9 GND V_INT GND DSR RI DCD DTR 10 RTS GND Ground GND Ground V_BCKP RTC Supply I/O V_BCKP RTC Supply I/O Ground Interfaces Supply Output:

1.8 V typ, 70 mA max Ground UART DSR Output V_INT level (1.8 V) Driver strength: 6 mA UART RI Output V_INT level (1.8 V) Driver strength: 6 mA UART DCD Output V_INT level (1.8 V) Driver strength: 6 mA UART DTR Input V_INT level (1.8 V) Internal pull-up: ~33 k It must be set low to have greeting text sent over UART UART RTS Input V_INT level (1.8 V) Internal pull-up:~58 k GND V_INT GND DSR RI DCD DTR RTS CTS Ground Interfaces Supply Output:

1.8 V typ, 70 mA max Ground UART DSR Output V_INT level (1.8 V) Driver strength: 1 mA UART RI Output V_INT level (1.8 V) Driver strength: 2 mA UART DCD Output V_INT level (1.8 V) Driver strength: 2 mA UART DTR Input V_INT level (1.8 V) Internal pull-up: ~14 k It must be set low to have greeting text sent over UART UART RTS Input V_INT level (1.8 V) Internal pull-up: ~8 k UART CTS Output V_INT level (1.8 V) Driver strength: 6 mA GND RSVD GND V_INT GND DSR RI DCD DTR RTS CTS Ground Reserved Ground Interfaces Supply Output:

1.8 V typ, 70 mA max Switched-off in deep-sleep Ground UART DSR Output V_INT level (1.8 V) Driver strength: 2 mA UART RI Output V_INT level (1.8 V) Driver strength: 2 mA UART DCD Output V_INT level (1.8 V) Driver strength: 2 mA UART DTR Input V_INT level (1.8 V) Internal pull-up: ~100 k It must be set low to have URCs sent over UART UART RTS Input16 V_INT level (1.8 V) Internal pull-up: ~100 k It must be set low to use UART on 00, 01 product versions UART CTS Output16 V_INT level (1.8 V) Driver strength: 2 mA 11 CTS UART CTS Output V_INT level (1.8 V) Driver strength: 6 mA GND RSVD GND V_INT GND RSVD Ground Reserved RSVD Reserved RSVD Reserved RSVD Reserved Ground Reserved Ground RTC supply vs Reserved Interfaces Supply Output:

1.8 V typ, 70 mA max Switched-off when radio is off V_INT is switched off in deep sleep (R4), or if radio is off (N2) TestPoint always recommended Not supported by SARA-N2 Diverse driver strength Not supported by SARA-N2 Diverse driver strength Not supported by SARA-N2 Diverse driver strength Not supported by SARA-N2 Diverse internal pull-up value RTS CTS UART RTS Input16 VCC level (3.6 V typ.) Internal pull-up: ~78 k Diverse level (V_INT vs VCC) Diverse internal pull-up value Diverse functions supported. UART CTS Output16 VCC level (3.6 V typ.) Driver strength: 1 mA Configurable as Ring Indicator or Network Indicator Diverse level (V_INT vs VCC) Diverse driver strength. Diverse functions supported. Appendix Page 106 of 115 16 Not supported by 00, 01, SARA-R410M-02B product versions and SARA-N2 modules UBX-16029218 - R09 SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration SARA-R4 series - System Integration Manual No 12 TXD 13 RXD 14 15 GND PWR_ON 16 GPIO1 /

RSVD UART Data Input V_INT level (1.8 V) Internal pull-up:~18 k UART Data Output V_INT level (1.8 V) Driver strength: 6 mA TXD RXD UART Data Input V_INT level (1.8 V) Internal pull-up: ~8 k UART Data Output V_INT level (1.8 V) Driver strength: 6 mA TXD RXD UART Data Input V_INT level (1.8 V) Internal pull-up/-down: ~100k UART Data Output V_INT level (1.8 V) Driver strength: 2 mA TXD RXD UART Data Input VCC level (3.6 V typ.) No internal pull-up/-down UART Data Output VCC level (3.6 V typ.) Driver strength: 1 mA Ground GND Ground GND Ground Power-on Input No internal pull-up L-level: -0.10 V 0.65 V H-level: 2.00 V 4.50 V ON L-level time:

5 ms min OFF L-level pulse time:

Not Available GPIO (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Default: Pin disabled Driver strength: 6 mA PWR_ON GPIO1 Power-on Input No internal pull-up L-level: -0.30 V 0.65 V H-level: 1.50 V 4.40 V ON L-level pulse time:

50 s min / 80 s max OFF L-level pulse time:

1 s min GPIO V_INT level (1.8 V) Default: Pin disabled Driver strength: 6 mA PWR_ON GPIO1 Power-on Input 200 k internal pull-up L-level: -0.30 V 0.35 V H-level: 1.17 V 2.10 V ON L-level pulse time:

0.15 s min 3.2 s max OFF L-level pulse time:

1.5 s min GPIO V_INT level (1.8 V) Default: Pin disabled Driver strength: 2 mA GND RSVD Ground Reserved GPIO1 GPIO V_INT level (1.8 V) Configurable as secondary UART data output: TestPoint recommended for diagnostic 17 RSVD Reserved VUSB_DET 5 V, USB Supply Detect Input VUSB_DET 5 V, USB Supply Detect Input RSVD Reserved 18 RESET_N Reset input Internal diode & pull-up L-level: -0.30 V 0.30 V H-level: 2.00 V 4.70 V Reset L-level pulse time:

50 ms min (G340/G350) 3 s min (G300/G310) RESET_N RESET_N Abrupt shutdown / reset input 10 k internal pull-up L-level: -0.30 V 0.51 V H-level: 1.32 V 2.01 V Reset L-level pulse time:

50 ms min 19 RSVD Reserved CODEC_CLK 13 or 26 MHz Output GPIO6 V_INT level (1.8 V) Default: Pin disabled Driver strength: 4 mA Abrupt shutdown input 37 k internal pull-up L-level: -0.30 V 0.35 V H-level: 1.17 V 2.10 V OFF L-level pulse time:

10 s min GPIO V_INT level (1.8 V) Default: Pin disabled Driver strength: 2 mA RESET_N Reset input 78 k internal pull-up L-level: -0.30 V 0.36*VCC H-level: 0.52*VCC VCC Reset L-level pulse time:

500 ns min RSVD Reserved Clock / GPIO vs Reserved 20-22 GND Ground GND Ground GND Ground GND Ground UBX-16029218 - R09 Appendix Page 107 of 115 Diverse level (V_INT vs VCC) Diverse pull-up / pull-down TestPoint always recommended Diverse level (V_INT vs VCC) Diverse driver strength TestPoint always recommended Not supported by SARA-N2 Internal vs No internal pull-up Diverse voltage levels. Diverse timings. Diverse functions supported. TestPoint recommended for R4 Diverse driver strength TestPoint recommended for N2 USB detection vs Reserved TestPoint recommended for U2/R4 Diverse internal pull-up Diverse voltage levels. Diverse timings. Diverse functions supported. TestPoint always recommended SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration SARA-R4 series - System Integration Manual GPIO2 GPIO3 GPIO4 SDA SCL GPIO V_INT level (1.8 V) Default: GNSS supply enable Driver strength: 1 mA GPIO V_INT level (1.8 V) Default: GNSS data ready Driver strength: 6 mA GPIO V_INT level (1.8 V) Default: GNSS RTC sharing Driver strength: 6 mA I2C Data I/O V_INT level (1.8 V) Open drain No internal pull-up I2C Clock Output V_INT level (1.8 V) Open drain No internal pull-up GPIO2 GPIO3 GPIO4 SDA SCL GPIO V_INT level (1.8 V) Default: Pin disabled Driver strength: 2 mA GPIO V_INT level (1.8 V) Default: Pin disabled Driver strength: 2 mA GPIO V_INT level (1.8 V) Default: Output/Low Driver strength: 2 mA I2C Data I/O17 V_INT level (1.8 V) Open drain Internal 2.2 k pull-up I2C Clock Output17 V_INT level (1.8 V) Open drain Internal 2.2 k pull-up RSVD Reserved GPIO vs Reserved GPIO2 GPIO18 V_INT level (1.8 V) Default: Pin disabled Driver strength: 1 mA Diverse driver strength RSVD Reserved GPIO vs Reserved SDA SCL I2C Data I/O18 V_INT level (1.8 V) Open drain No internal pull-up I2C Clock Output18 V_INT level (1.8 V) Open drain No internal pull-up USB_D-

USB Data I/O (D-) High-Speed USB 2.0 USB_D-

USB Data I/O (D-) High-Speed USB 2.0 RSVD Reserved USB_D+

USB Data I/O (D+) High-Speed USB 2.0 USB_D+

USB Data I/O (D+) High-Speed USB 2.0 RSVD Reserved GND RSVD Ground Reserved GND RSVD Ground Reserved Ground GND Ground GND Ground It must be connected to GND RSVD It must be connected to GND RSVD It can be connected to GND GND RSVD GND RSVD Ground Reserved Ground It can be connected to GND No 23 GPIO2 /

RSVD 24 GPIO3 /

32K_OUT 25 GPIO4 /

RSVD 26 SDA /

RSVD 27 SCL /

RSVD 28 RXD_AUX 29 TXD_AUX 30 31 32 33 GND RSVD /

EXT32K GND RSVD GPIO (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Default: GNSS supply enable Driver strength: 6 mA GPIO (G340/G350) 32 kHz Output (G300/G310) V_INT level (1.8 V) Default: GNSS data ready Driver strength: 5 mA GPIO (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Default: GNSS RTC sharing Driver strength: 6 mA I2C Data I/O (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Open drain No internal pull-up I2C Clock Output (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Open drain No internal pull-up Aux UART Data Out V_INT level (1.8 V) Aux UART Data In V_INT level (1.8 V) Ground Reserved (G340/G350) 32 kHz Input (G300/G310) 17 Not supported by 00 and 01 product versions 18 Not supported by 02 product versions UBX-16029218 - R09 Internal vs No internal pull-up Internal vs No internal pull-up USB / AUX UART vs Reserved TestPoint recommended for SARA-G3/U2/R4 modules USB / AUX UART vs Reserved TestPoint recommended for SARA-G3/U2/R4 modules 32 kHz Input vs Reserved Appendix Page 108 of 115 No 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name I2S_WA /

RSVD I2S_TXD /

RSVD I2S_CLK /

RSVD I2S_RXD /

RSVD Description I2S Word Align.(G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Driver strength: 6 mA I2S Data Output (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Driver strength: 5 mA I2S Clock (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) Driver strength: 5 mA I2S Data Input (G340/G350) Reserved (G300/G310) V_INT level (1.8 V) VSIM SIM_DET GND SPK_P /

RSVD SPK_N /

RSVD MIC_BIAS /

RSVD MIC_GND /

RSVD MIC_N /

RSVD MIC_P /

RSVD GND SIM Detection Input V_INT level (1.8 V) Ground Analog Audio Out (+) /

Reserved Analog Audio Out (-) /

Reserved Microphone Supply Out /

Reserved Microphone Ground /

Reserved Analog Audio In (-) /

Reserved Analog Audio In (+) /

Reserved SARA-G3 SARA-U2 SARA-R4 Pin Name I2S_WA I2S_TXD I2S_CLK Description I2S Word Alignment V_INT level (1.8 V) Driver strength: 2 mA I2S Data Output V_INT level (1.8 V) Driver strength: 2 mA I2S Clock V_INT level (1.8 V) Driver strength: 2 mA Pin Name I2S_WA /

SPI_MOSI I2S_TXD /

SPI_CS I2S_CLK /

SPI_CLK Description I2S Word Alignm19 / SPI MOSI19 V_INT level (1.8 V) Driver strength: 2 mA I2S Data Out19 / SPI chip select19 V_INT level (1.8 V) Driver strength: 2 mA I2S Clock19 / SPI clock19 V_INT level (1.8 V) Driver strength: 2 mA SARA-R4 series - System Integration Manual SARA-N2 Pin Name Description RSVD Reserved Remarks for migration I2S vs SPI vs Reserved RSVD Reserved I2S vs SPI vs Reserved RSVD Reserved I2S vs SPI vs Reserved I2S_RXD I2S Data Input V_INT level (1.8 V) I2S_RXD /

SPI_MISO I2S Data Input19 / SPI MISO19 V_INT level (1.8 V) RSVD Reserved I2S vs SPI vs Reserved SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V SIM Clock Output SIM_IO 1.8V/3V SIM Data I/O Internal 4.7 k pull-up SIM_IO 1.8V/3V SIM Data I/O Internal 4.7 k pull-up SIM_IO 1.8V/3V SIM Data I/O Internal 4.7 k pull-up SIM_IO 1.8V SIM Data I/O Internal 4.7 k pull-up SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V SIM Reset Output 1.8V/3V SIM Supply Output VSIM 1.8V/3V SIM Supply Output SIM_DET SIM Detection Input V_INT level (1.8 V) GND RSVD Ground Reserved VSIM GPIO5 GND SDIO_D2 1.8V/3V SIM Supply Output SIM Detection Input V_INT level (1.8 V) Ground SDIO serial data [2]19 VSIM RSVD GND RSVD 1.8V SIM Supply Output Reserved Ground Reserved SIM Detection vs Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_CLK SDIO serial clock19 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_CMD SDIO command19 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_D0 SDIO serial data [0]19 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_D3 SDIO serial data [3]19 RSVD Reserved Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_D1 SDIO serial data [1]19 RSVD Reserved Analog Audio vs SDIO vs RSVD Ground GND Ground GND Ground GND Ground 19 Not supported by 00, 01 and 02 product version UBX-16029218 - R09 Appendix Page 109 of 115 SARA-R4 series - System Integration Manual No SARA-G3 SARA-U2 SARA-R4 SARA-N2 Pin Name Description Pin Name Description Pin Name Description Pin Name Description Remarks for migration 51-53 VCC VCC Module Supply Input Normal op. range:

3.35 V 4.5 V Extended op. range:

3.00 V 4.5 V Current consumption:

~2.0A pulse current in 2G

(recommended 100uF cap.) Switch-on by applying VCC VCC Module Supply Input Normal op. range:

3.3 V 4.4 V Extended op. range:

3.1 V 4.5 V Current consumption:

~2.0A pulse current in 2G

(recommended 100uF cap.) Ferrite bead for GHz noise recommended for U201 Switch-on by applying VCC Module Supply Input Normal op. range:

3.2 V 4.2 V Extended op. range:

3.0 V 4.3 V Current consumption:

~2.0A pulse current in 2G

(recommended 100uF cap.)

~0.5A pulse current in LTE

(recommended 10uF cap.) No switch-on by applying VCC 54-55 GND 56 ANT Ground RF Antenna I/O GND ANT Ground RF Antenna I/O GND ANT Ground RF Antenna I/O 57-61 GND Ground GND Ground GND Ground VCC GND ANT GND 62 ANT_DET /

RSVD Antenna Detection Input /

Reserved ANT_DET Antenna Detection Input ANT_DET Antenna Detection Input ANT_DET Module Supply Input Normal op. range:

3.1 V 4.0 V Extended op. range:

2.75 V 4.2 V Current consumption:

~0.3A pulse current in NB-IoT

(recommended 100uF cap.) Switch-on by applying VCC Diverse voltage levels. Diverse current consumption. Diverse recommended external capacitors and other parts. Regular pF / nF recommended Diverse functions supported. Ground RF Antenna I/O Ground Antenna Detection Input20 Diverse bands supported

(summarized in Figure 59) Antenna Detection vs Reserved 63-96 GND Ground GND Ground GND Ground GND Ground Table 40: SARA-G3, SARA-U2, SARA-R4 and SARA-N2 series modules pin assignments with remarks for migration For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the SARA-G3, SARA-U2, SARA-R4 and SARA-N2 series cellular modules, see the related Data Sheet [1], [16], [17], [18], the related System Integration Manual [19], [20], and the Nested Design Application Note [21]. 20 Not supported by 02 product version UBX-16029218 - R09 Appendix Page 110 of 115 SARA-R4 series - System Integration Manual B Glossary 2G 3G 3GPP 8-PSK 16QAM ACM ADC AP ASIC AT Cat CCC CE DC DCE DDC DL DRX DSP DTE EDGE eDRX EGPRS EMC EMI ESD ESR E-UTRA FCC FDD FEM FOAT FOTA FTP FW GCF GMSK GND GNSS GPIO GPRS GPS HBM HTTP HW IFT I2C I2S 2nd Generation Cellular Technology (GSM, GPRS, EGPRS) 3rd Generation Cellular Technology (UMTS, HSDPA, HSUPA) 3rd Generation Partnership Project 8 Phase-Shift Keying modulation 16-state Quadrature Amplitude Modulation Abstract Control Model Analog to Digital Converter Application Processor Application-Specific Integrated Circuit AT Command Interpreter Software Subsystem, or attention Category China Compulsory Certificate European Conformity Direct Current Data Communication Equipment Display Data Channel interface Down-Link (Reception) Discontinuous Reception Digital Signal Processing Data Terminal Equipment Enhanced Data rates for GSM Evolution (EGPRS) Extended Discontinuous Reception Enhanced General Packet Radio Service (EDGE) Electro-Magnetic Compatibility Electro-Magnetic Interference Electro-Static Discharge Equivalent Series Resistance Evolved Universal Terrestrial Radio Access Federal Communications Commission United States Frequency Division Duplex Front End Module Firmware Over AT commands Firmware Over The Air File Transfer Protocol Firmware Global Certification Forum Gaussian Minimum-Shift Keying modulation Ground Global Navigation Satellite System General Purpose Input Output General Packet Radio Service Global Positioning System Human Body Model HyperText Transfer Protocol Hardware Federal Telecommunications Institute Mexico Inter-Integrated Circuit interface Inter IC Sound interface UBX-16029218 - R09 Appendix Page 111 of 115 SARA-R4 series - System Integration Manual Internet Protocol Innovation, Science and Economic Development Canada Low-Dropout Land Grid Array Low Noise Amplifier Low Power Wide Area Long Term Evolution Open Mobile Alliance Lightweight Machine-to-Machine protocol Machine-to-Machine Message Queuing Telemetry Transport Not Applicable Not Available Non Access Stratum Original Equipment Manufacturer device: an application device integrating a u-blox cellular module Over The Air Power Amplifier Pulse Code Modulation Product Change Notification / Sample Delivery Note / Information Note Pulse Frequency Modulation Power Saving Mode PCS Type Certification Review Board Pulse Width Modulation Quadrature Phase Shift Keying Radio Access Technology Radio Frequency Radiated Spurious Emission Real Time Clock Surface Acoustic Wave Secure Digital Input Output Subscriber Identification Module Short Message Service Serial Peripheral Interface Self-Resonant Frequency State Radio Regulation Committee China Secure Socket Layer To Be Defined Transmission Control Protocol Time Division Duplex Time Division Multiple Access Total Isotropic Sensitivity Test-Point Total Radiated Power Universal Asynchronous Receiver-Transmitter User Datagram Protocol Universal Integrated Circuit Card Up-Link (Transmission) Universal Mobile Telecommunications System Universal Serial Bus Voice over LTE Voltage Standing Wave Ratio IP ISED LDO LGA LNA LPWA LTE LWM2M M2M MQTT N/A N.A. NAS OEM OTA PA PCM PCN PFM PSM PTCRB PWM QPSK RAT RF RSE RTC SAW SDIO SIM SMS SPI SRF SRRC SSL TBD TCP TDD TDMA TIS TP TRP UART UDP UICC UL UMTS USB VoLTE VSWR UBX-16029218 - R09 Appendix Page 112 of 115 SARA-R4 series - System Integration Manual Related documents

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

u-blox SARA-R4 series Data Sheet, document number UBX-16024152 u-blox SARA-R4 series AT Commands Manual, document number UBX-17003787 u-blox EVK-R4 User Guide, document number UBX-16029216 Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/usb20_docs/

ITU-T Recommendation V.24 - 02-2000 - List of definitions for interchange circuits between Data Terminal Equipment (DTE) and Data Circuit-terminating Equipment (DCE), http://www.itu.int/rec/T-REC-V.24-200002-I/en 3GPP TS 27.007 - AT command set for User Equipment (UE) 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol I2C-bus specification and user manual - Rev. 5 - 9 October 2012 - NXP Semiconductors, http://www.nxp.com/documents/user_manual/UM10204.pdf

[10] GSM Association TS.09 - Battery Life Measurement and Current Consumption Technique, https://www.gsma.com/newsroom/wp-content/uploads//TS.09_v10.0.pdf

[11] 3GPP TS 36.521-1 - Evolved Universal Terrestrial Radio Access; User Equipment conformance specification;

Radio transmission and reception; Part 1: Conformance Testing

[12] 3GPP TS 36.521-2 - Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment conformance specification; Radio transmission and reception; Part 2: Implementation Conformance Statement (ICS)

[13] 3GPP TS 36.523-2 - Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Packet Core (EPC);

User Equipment conformance specification; Part 2: Implementation Conformance Statement (ICS)

[14] u-blox End user test Application Note, document number UBX-13001922

[15] u-blox Package Information Guide, document number UBX-14001652

[16] u-blox SARA-G3 series Data Sheet, document number UBX-13000993

[17] u-blox SARA-U2 series Data Sheet, document number UBX-13005287

[18] u-blox SARA-N2 series Data Sheet, document number UBX-15025564

[19] u-blox SARA-G3 / SARA-U2 series System Integration Manual, document number UBX-13000995

[20] u-blox SARA-N2 series System Integration Manual, document number UBX-17005143

[21] u-blox Nested Design Application Note, document number UBX-16007243 Some of the above documents can be downloaded from the u-blox web-site (http://www.u-blox.com/). UBX-16029218 - R09 Related documents Page 113 of 115 SARA-R4 series - System Integration Manual Revision history Revision Date Name Status / Comments 31-Jan-2017 sfal Initial release for SARA-R4 series modules 05-May-2017 sfal / sses Updated supported features and characteristics Extended document applicability to SARA-R410M-01B product version R01 R02 R03 R04 R05 R06 R07 24-May-2017 19-Jul-2017 17-Aug-2017 30-Oct-2017 04-Jan-2018 sses sses sses sses sses R08 26-Feb-2018 sses R09 09-May-2018 sses Updated supported features and electrical characteristics Updated supported features and electrical characteristics Added FCC and ISED info for SARA-R410M-01B modules Extended document applicability to SARA-R410M-02B product version Updated supported features for 02 product version Updated supported features for 02 product version Updated SARA-R410M-02B product status Updated USB, Power Saving and GPIO features description Improved Power-on sequence guidelines description Added I2C design guidelines description Updated SARA-R410M-02B product status Extended document applicability to SARA-R412M-02B product version Corrected power-on sequence description Corrected UART MUX description Updated SARA-R410M-02B and SARA-R412M-02B product status Updated features support plan for the product versions Updated UART TXD and CTS info Updated Approvals info and related remarks Added description of AT Inactivity Timer to enter deep sleep power saving mode UBX-16029218 - R09 Revision history Page 114 of 115 SARA-R4 series - System Integration Manual Contact For complete contact information, visit us at http://www.u-blox.com/

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SARA-R4/N4 series

System Integration Manual

System Integration Manual

SARA-R4/N4

Abstract

This document describes the features and the integration of the size-optimized SARA-R4/N4 series cellular modules.

These modules are a complete, cost efficient, performance optimized, multi-mode and multi band LTE Cat M1 / NB1

and EGPRS solution in the compact SARA form factor.

www.u-blox.com

UBX-16029218 - R13

SARA-R4/N4 series - System Integration Manual

Document Information

Title

Subtitle

SARA-R4/N4 series

System Integration Manual

Document type

System Integration Manual

Document number

UBX-16029218

Revision and date

Disclosure Restriction

R13

06-Aug-2019

Product status

Corresponding content status

Functional Sample

Draft

For functional testing. Revised and supplementary data will be published later.

Objective Specification

Target values. Revised and supplementary data will be published later.

Engineering Sample

Advance Information

Data based on early testing. Revised and supplementary data will be published later.

Initial Production

Early Production Information

Data from product verification. Revised and supplementary data may be published later.

Production Information

Document contains the final product specification.

In Development /

Prototype

Mass Production /

End of Life

Product name

Type number

Modem version

Application version

PCN reference

Product status

This document applies to the following products:

SARA-R404M

SARA-R404M-00B-00

K0.0.00.00.07.06

SARA-R404M-00B-01

K0.0.00.00.07.08

SARA-R410M

SARA-R410M-01B-00

L0.0.00.00.02.03

SARA-R410M-02B-00

L0.0.00.00.05.06

L0.0.00.00.05.06

SARA-R410M-02B-01

L0.0.00.00.05.08

SARA-R410M-52B-00

L0.0.00.00.06.05

SARA-R410M-52B-01

L0.0.00.00.06.08

A02.00

A02.01

A02.04

A02.06

A02.11

SARA-R410M-03B-00

SARA-R410M-63B-00

SARA-R410M-73B-00

SARA-R412M-02B-01

SARA-R412M-03B-00

SARA-R412M

SARA-R412M-02B-00

M0.09.00

M0.10.00

A02.11

A02.14

UBX-17047084

UBX-18055331

UBX-18059854

UBX-18010263

Obsolete

Obsolete

Obsolete

Obsolete

UBX-18070443

End of Life

UBX-19024506

Initial Production

UBX-18045915

End of Life

UBX-19011338

Initial Production

Functional Sample

Functional Sample

Functional Sample

UBX-19004091

End of Life

UBX-19016568

Initial Production

Functional Sample

SARA-N410

SARA-N410-02B-00

L0.0.00.00.07.07

A02.09

UBX-18057459

Initial Production

u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction,

modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox.

The information contained herein is provided “as is” and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including

but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be

revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com.

Copyright © u-blox AG.

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SARA-R4/N4 series - System Integration Manual

Contents

1

Document Information ................................................................................................................................. 2

Contents........................................................................................................................................................ 3

1.8.1

1.8.2

1.7.1

1.7.2

System description ................................................................................................................................. 6

1.1 Overview .................................................................................................................................................................. 6

1.2 Architecture ............................................................................................................................................................. 9

1.3 Pin-out ................................................................................................................................................................... 10

1.4 Operating modes ................................................................................................................................................... 14

1.5 Supply interfaces ................................................................................................................................................... 17

1.5.1 Module supply input (VCC) ........................................................................................................................... 17

1.5.2 Generic digital interfaces supply output (V_INT) .......................................................................................... 22

1.6 System function interfaces .................................................................................................................................... 23

1.6.1 Module power-on ......................................................................................................................................... 23

1.6.2 Module power-off ......................................................................................................................................... 24

1.6.3 Module reset ................................................................................................................................................. 25

1.7 Antenna interface .................................................................................................................................................. 27

Antenna RF interface (ANT) .......................................................................................................................... 27

Antenna detection interface (ANT_DET) ...................................................................................................... 27

1.8 SIM interface ......................................................................................................................................................... 28

SIM interface ................................................................................................................................................. 28

SIM detection interface ................................................................................................................................ 28

1.9 Data communication interfaces ............................................................................................................................ 29

1.9.1 UART interface .............................................................................................................................................. 29

1.9.2 USB interface ................................................................................................................................................ 30

SPI interface .................................................................................................................................................. 32

1.9.3

1.9.4

SDIO interface ............................................................................................................................................... 32

1.9.5 DDC (I2C) interface ........................................................................................................................................ 32

1.10 Audio...................................................................................................................................................................... 32

1.11 General Purpose Input/Output .............................................................................................................................. 33

1.12 Reserved pins (RSVD) ............................................................................................................................................. 33

1.13 System features ..................................................................................................................................................... 34

1.13.1 Network indication ....................................................................................................................................... 34

1.13.2 Antenna supervisor ....................................................................................................................................... 34

1.13.3 Dual stack IPv4/IPv6 ...................................................................................................................................... 34

1.13.4 TCP/IP and UDP/IP ........................................................................................................................................ 34

1.13.5 FTP ................................................................................................................................................................ 34

1.13.6 HTTP .............................................................................................................................................................. 34

1.13.7 Firmware update Over AT (FOAT) ................................................................................................................. 35

1.13.8 Firmware update Over The Air (uFOTA) ....................................................................................................... 35

1.13.9 Power saving ................................................................................................................................................. 35

2 Design-in .............................................................................................................................................. 38

2.1 Overview ................................................................................................................................................................ 38

2.2 Supply interfaces ................................................................................................................................................... 39

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2.4.1

2.4.2

2.2.1 Module supply (VCC)..................................................................................................................................... 39

2.2.2 Generic digital interfaces supply output (V_INT) .......................................................................................... 55

2.3 System functions interfaces................................................................................................................................... 56

2.3.1 Module power-on (PWR_ON) ....................................................................................................................... 56

2.3.2 Module reset (RESET_N) ............................................................................................................................... 57

2.4 Antenna interface .................................................................................................................................................. 58

Antenna RF interface (ANT) .......................................................................................................................... 58

Antenna detection interface (ANT_DET) ...................................................................................................... 65

2.5 SIM interface ......................................................................................................................................................... 68

2.5.1 Guidelines for SIM circuit design .................................................................................................................. 68

2.5.2 Guidelines for SIM layout design .................................................................................................................. 71

2.6 Data communication interfaces ............................................................................................................................ 72

2.6.1 UART interface .............................................................................................................................................. 72

2.6.2 USB interface ................................................................................................................................................ 77

SPI interface .................................................................................................................................................. 78

2.6.3

2.6.4

SDIO interface ............................................................................................................................................... 78

2.6.5 DDC (I2C) interface ........................................................................................................................................ 79

2.7 Audio...................................................................................................................................................................... 81

2.7.1 Guidelines for Audio circuit design ............................................................................................................... 81

2.8 General Purpose Input/Output .............................................................................................................................. 81

2.8.1 Guidelines for GPIO circuit design ................................................................................................................ 81

2.8.2 Guidelines for general purpose input/output layout design ........................................................................ 82

2.9 Reserved pins (RSVD) ............................................................................................................................................. 83

2.10 Module placement ................................................................................................................................................ 83

2.11 Module footprint and paste mask ......................................................................................................................... 84

2.12 Thermal guidelines ................................................................................................................................................ 85

2.13 Schematic for SARA-R4/N4 series module integration .......................................................................................... 85

2.13.1 Schematic for SARA-R4/N4 series modules .................................................................................................. 85

2.14 Design-in checklist ................................................................................................................................................. 87

2.14.1 Schematic checklist ....................................................................................................................................... 87

2.14.2 Layout checklist ............................................................................................................................................. 87

2.14.3 Antenna checklist .......................................................................................................................................... 88

3 Handling and soldering ........................................................................................................................ 89

3.1 Packaging, shipping, storage and moisture preconditioning ................................................................................. 89

3.2 Handling ................................................................................................................................................................. 89

3.3 Soldering ................................................................................................................................................................ 90

Soldering paste ............................................................................................................................................. 90

3.3.1

Reflow soldering ........................................................................................................................................... 90

3.3.2

3.3.3 Optical inspection ......................................................................................................................................... 91

Cleaning ........................................................................................................................................................ 91

3.3.4

3.3.5

Repeated reflow soldering ............................................................................................................................ 91

3.3.6 Wave soldering ............................................................................................................................................. 92

3.3.7 Hand soldering .............................................................................................................................................. 92

Rework .......................................................................................................................................................... 92

3.3.8

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Conformal coating ......................................................................................................................................... 92

3.3.9

3.3.10 Casting........................................................................................................................................................... 92

3.3.11 Grounding metal covers ................................................................................................................................ 92

3.3.12 Use of ultrasonic processes .......................................................................................................................... 92

4 Approvals ............................................................................................................................................. 94

4.1 Product certification approval overview ............................................................................................................... 94

4.2 US Federal Communications Commission notice .................................................................................................. 99

Safety warnings review the structure ........................................................................................................... 99

4.2.1

4.2.2 Declaration of Conformity ............................................................................................................................ 99

4.2.3 Modifications .............................................................................................................................................. 100

Innovation, Science, Economic Development Canada notice.............................................................................. 100

4.3.1 Declaration of Conformity .......................................................................................................................... 100

4.3.2 Modifications .............................................................................................................................................. 101

4.4 European Conformance CE mark ......................................................................................................................... 103

4.5 National Communication Commission Taiwan .................................................................................................... 104

4.6 GITEKI Japan ........................................................................................................................................................ 104

4.3

5

Product testing ....................................................................................................................................105

5.1 u-blox in-series production test ........................................................................................................................... 105

5.2 Test parameters for OEM manufacturers ............................................................................................................ 106

“Go/No go” tests for integrated devices..................................................................................................... 106

RF functional tests ...................................................................................................................................... 106

Appendix ....................................................................................................................................................108

5.2.1

5.2.2

A Migration between SARA modules .....................................................................................................108

A.1 Overview .............................................................................................................................................108

A.2 Pin-out comparison .............................................................................................................................110

B Glossary ..............................................................................................................................................115

Related documents ....................................................................................................................................117

Revision history .........................................................................................................................................118

Contact.......................................................................................................................................................119

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SARA-R4/N4 series - System Integration Manual

System description

1

1.1 Overview

The SARA-R4/N4 series comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi-mode modules in the miniature SARA LGA

form-factor (26.0 x 16.0 mm, 96-pin), that allow easy integration in compact designs and a seamless drop-in migration

from u-blox cellular module families.

SARA-R4/N4 series modules are form-factor compatible with u-blox LISA, LARA and TOBY cellular module families and

are pin-to-pin compatible with u-blox SARA-N, SARA-G and SARA-U cellular module families. This facilitates migration

from u-blox NB-IoT, GSM/GPRS, CDMA, UMTS/HSPA and other LTE modules, maximizes customer investments, simplifies

logistics, and enables very short time-to-market. See Table 1 for a summary of the main features and interfaces.

The modules are ideal for LPWA applications with low to medium data throughput rates, as well as devices that require

long battery lifetimes, such as connected health, smart metering, smart cities and wearables.

The modules support handover capability and delivers the technology necessary for use in applications such as vehicle,

asset and people tracking where mobility is a pre-requisite. Other applications where the modules are well-suited include

and are not limited to: smart home, security systems, industrial monitoring and control.

The modules support data communication over an extended operating temperature range of –40 to +85 °C, with

extremely low power consumption, and with coverage enhancement for deeper range into buildings and basements (and

underground with NB1).

Model

Region

Bands

Positioning

Interfaces

Audio

Features

Grade

SARA-R404M

13 M1

13

USA

SARA-R410M-01B

North America 13 M1

SARA-R410M-02B

Multi Region

13

SARA-R410M-52B

North America 13 M1

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○ ● ● ● ● ● ● ●

SARA-R410M-63B

Japan

13 M1 1,8,19

● ● ○ ○ ● ●

● ● ● ● ● ● ●

SARA-R410M-73B

Korea

13 M1 3,5,26

● ● ○ ○ ● ●

● ● ● ● ● ● ●

SARA-R412M-02B

Multi Region

13

● ●

● ●

● ● ● ● ● ● ●

SARA-R412M-03B

Multi Region

13

●

● ● ○ ○ ● ●

● ● ● ● ● ● ●

SARA-N410-02B

Multi Region

13 NB1

● ●

● ●

● ● ● ● ● ● ●

* = Bands may include 1, 2, 3, 4, 5, 8, 12, 13, 18, 19, 20, 25, 26, 28 ● = supported by all FW versions ○ = supported by future FW versions

Table 1: SARA-R4/N4 series main features summary

SARA-R4/N4 series modules include the following variants / product versions:

•

SARA-R404M LTE Cat M1 module,

mainly designed for operation in LTE band 13

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System description

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®

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SARA-R4/N4 series - System Integration Manual

SARA-R410M-01B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12

SARA-R410M-02B LTE Cat M1 / NB1 module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 2515, 28

SARA-R410M-52B LTE Cat M1 module,

mainly designed for operation in LTE bands 2, 4, 5, 12, 13

SARA-R410M-03B LTE Cat M1 / NB1 module,

mainly designed for operation in LTE bands 1, 2, 3, 4, 5, 8, 12, 13, 20, 25, 26, 28

SARA-R410M-63B LTE Cat M1 module,

mainly designed for operation in LTE bands 1, 8, 19

SARA-R410M-73B LTE Cat M1 module,

mainly designed for operation in LTE bands 3, 5, 26

SARA-R412M-02B LTE Cat M1 / NB1 and 2G module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad-band

SARA-R412M-03B LTE Cat M1 / NB1 and 2G module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 26, 28 and 2G Quad-band

SARA-N410-02B LTE Cat NB1 module,

mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 28

Table 2 summarizes cellular radio access technologies characteristics and features of the modules.

☞☞☞☞

See Table 38 for the detailed list of RATs and bands included in each certification approval of the SARA-R4/N4 series

modules product versions.

•

•

•

•

•

•

•

•

•

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Item

RAT

SARA-R404M

SARA-R410M

SARA-R412M

SARA-N410

Protocol stack

3GPP Release 13

3GPP Release 13

3GPP Release 13

3GPP Release 13

LTE Cat M1 Half-Duplex

LTE Cat M1 Half-Duplex

LTE Cat NB1 Half-Duplex 1, 13, 14, 7

LTE Cat NB1 Half-Duplex

LTE FDD bands

Band 13 (750 MHz)

SARA-R4/N4 series - System Integration Manual

LTE Cat M1 Half-Duplex

LTE Cat NB1 Half-Duplex

2G GPRS / EGPRS

Band 2 (1900 MHz)

Band 3 (1800 MHz)

Band 4 (1700 MHz)

Band 5 (850 MHz)

Band 8 (900 MHz)

Band 12 (700 MHz)

Band 13 (750 MHz)

Band 20 (800 MHz)

Band 26 (850 MHz) 8

Band 28 (700 MHz) 16

Band 2 (1900 MHz)

Band 3 (1800 MHz)

Band 4 (1700 MHz)

Band 5 (850 MHz)

Band 8 (900 MHz)

Band 12 (700 MHz)

Band 13 (750 MHz)

Band 20 (800 MHz)

Band 28 (700 MHz)

Band 1 (2100 MHz) 1, 14

Band 2 (1900 MHz) 7

Band 3 (1800 MHz) 1, 14

Band 4 (1700 MHz) 7

Band 5 (850 MHz)

Band 8 (900 MHz) 1, 14

Band 12 (700 MHz) 7

Band 13 (750 MHz) 1, 7

Band 18 (850 MHz) 1, 2, 13, 14, 7

Band 19 (850 MHz) 1, 2, 13, 14

Band 20 (800 MHz) 1, 14, 7

Band 25 (1900 MHz) 1, 3, 4, 5, 6, 7

Band 26 (850 MHz) 1, 13, 14

Band 28 (700 MHz) 1, 14, 7

2G bands

Power class

LTE Cat M1:

Class 3 (23 dBm)

LTE Cat M1 / NB19:

Class 3 (23 dBm)

LTE category NB1:

Class 3 (23 dBm)

GSM 850 MHz

E-GSM 900 MHz

DCS 1800 MHz

PCS 1900 MHz

LTE category M1 / NB1:

Class 3 (23 dBm)

2G GMSK:

Class 4 (33 dBm) for GSM/E-

GSM bands

Class 1 (30 dBm) for DCS/PCS

bands

2G 8-PSK:

Class E2 (27 dBm) for GSM/E-

GSM bands

Class E2 (26 dBm) for DCS/PCS

bands

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category NB1:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

GPRS multi-slot class 3310:

Up to 85.6 kb/s UL

Up to 107 kb/s DL

EGPRS multi-slot class 3318:

Up to 236.8 kb/s UL

Up to 296.0 kb/s DL

Data rate

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category M1:

up to 375 kb/s UL

up to 300 kb/s DL

LTE category NB19:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

LTE category NB1:

up to 62.5 kb/s UL

up to 27.2 kb/s DL

Table 2: SARA-R4/N4 series modules LTE Cat M1, LTE Cat NB1, EGPRS and GPRS characteristics summary

1 Not supported by the SARA-R410M-01B product version.

2 Not supported by the SARA-R410M-03B product version.

3 Not supported by the SARA-R410M-02B-00 product version.

4 Not supported by the SARA-R410M-52B-00 product version.

5 Not supported by the SARA-R410M-52B-01 product version.

6 Not supported in LTE Cat NB1 by the SARA-R410M-02B-01 product version.

7 Not supported by the SARA-R410M-63B and SARA-R410M-73B product version

8 Not supported by the SARA-R412M-02B-00 product version.

9 LTE Cat NB1 not supported by SARA-R410M-01B, SARA-R410M-52B, SARA-R410M-63B, SARA-R410M-73B product versions.

10 GPRS/EGPRS multi-slot class 33 implies a maximum of 5 slots in Down-Link and 4 slots in Up-Link with 6 slots in total.

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SARA-R4/N4 series - System Integration Manual

1.2 Architecture

Figure 1 summarizes the internal architecture of SARA-R4/N4 series modules.

ANT

Filt er

Swit ch

PA

RF

t ransceiver

SIM

SIM card det ect ion

19.2 M Hz

M emory

VCC (Supply)

V_INT

Reset

Power-On

Power

M anagement

Figure 1: SARA-R4/N4 series modules simplified block diagram

UART

USB

DDC (I2C)

SDIO

Cellular

BaseBand

Processor

SPI / Digit al Audio

GPIOs

Ant enna det ect ion

SARA-R404M-00B and SARA-R410M-01B modules,

the

i.e.

SARA-R4/N4 series modules, do not support the following interfaces, which should be left unconnected and should

not be driven by external devices:

the “00” and “01” product versions of

SARA-R410M-02B, SARA-R410M-52B, SARA-R410M-03B, SARA-R410M-63B, SARA-R410M-73B, SARA-R412M-02B,

SARA-R412M-03B, SARA-N410-02B modules, i.e. the “02”, “52”, “03”, “63”, “73” product versions of the SARA-R4/N4

series modules, do not support the following interfaces, which should be left unconnected and should not be driven

by external devices:

☞☞☞☞

☞☞☞☞

o DDC (I2C) interface

o SDIO interface

o SPI interface

o Digital audio interface

o SDIO interface

o SPI interface

o Digital audio interface

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SARA-R4/N4 series - System Integration Manual

1.3 Pin-out

Function

Table 3 lists the pin-out of the SARA-R4/N4 series modules, with pins grouped by function.

Pin Name

Pin No

I/O

Description

Remarks

Power

VCC

51, 52, 53

I

Module supply input VCC supply circuit affects the RF performance and compliance of the

device integrating the module with applicable required certification

schemes.

See section 1.5.1 for functional description / requirements.

See section 2.2.1 for external circuit design-in.

GND

N/A

Ground

1, 3, 5, 14,

20-22, 30,

32, 43, 50,

54, 55, 57-

61, 63-96

V_INT

4

O

Generic digital

interfaces supply

output

System

PWR_ON

15

Power-on input

I

I

RESET_N

18

External reset input

Antenna

ANT

56

I/O

Primary antenna

ANT_DET

62

I

Antenna detection

SIM

VSIM

41

O

SIM supply output

SIM_IO

39

I/O

SIM data

SIM_CLK

38

O

SIM clock

SIM_RST

40

O

SIM reset

UART

RXD

13

O

UART data output

GND pins are internally connected each other.

External ground connection affects the RF and thermal performance of

the device.

See section 1.5.1for functional description.

See section 2.2.1 for external circuit design-in.

V_INT = 1.8 V (typical) generated by internal regulator when the

module is switched on, outside the low power PSM deep sleep mode.

Test-Point for diagnostic access is recommended.

See section 1.5.2 for functional description.

See section 2.2.2 for external circuit design-in.

Internal 200 kΩ pull-up resistor.

Test-Point for diagnostic access is recommended.

See section 1.6.1 for functional description.

See section 2.3.1 for external circuit design-in.

Internal 37 kΩ pull-up resistor.

Test-Point for diagnostic access is recommended.

See section 1.6.3 for functional description.

See section 2.3.2 for external circuit design-in.

Main Tx / Rx antenna interface.

50 Ω nominal characteristic impedance.

Antenna circuit affects the RF performance and application device

compliance with required certification schemes.

See section 1.7 for functional description / requirements.

See section 2.4 for external circuit design-in.

ADC for antenna presence detection function

See section 1.7.2 for functional description.

See section 2.4.2 for external circuit design-in.

VSIM = 1.8 V / 3 V output as per the connected SIM type.

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

Data input/output for 1.8 V / 3 V SIM

Internal 4.7 kΩ pull-up to VSIM.

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

4.8 MHz clock output for 1.8 V / 3 V SIM

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

Reset output for 1.8 V / 3 V SIM

See section 1.8 for functional description.

See section 2.5 for external circuit design-in.

1.8 V output, Circuit 104 (RXD) in ITU-T V.24,

for AT commands, data communication, FOAT.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

TXD

12

I

UART data input

CTS

11

O

UART clear to send

output

RTS

10

I

UART ready to send

input

SARA-R4/N4 series - System Integration Manual

1.8 V input, Circuit 103 (TXD) in ITU-T V.24,

for AT commands, data communication, FOAT.

Internal pull-down to GND on “00” and R410M-02B versions

Internal pull-up to V_INT on other product versions

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

1.8 V output, Circuit 106 (CTS) in ITU-T V.24.

Not supported by ‘00’, ‘01’ and R410M-02B-00 versions.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

1.8 V input, Circuit 105 (RTS) in ITU-T V.24.

Internal active pull-up to V_INT.

Not supported by ‘00’, ‘01’ and R410M-02B-00 versions.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

DSR

RI

DTR

DCD

6

7

9

8

O

O

I

O

UART data set ready

output

UART ring indicator

output

UART data terminal

ready input

UART data carrier

detect output

1.8 V, Circuit 107 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

1.8 V, Circuit 125 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

1.8 V, Circuit 108/2 in ITU-T V.24.

Internal active pull-up to V_INT.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

1.8 V, Circuit 109 in ITU-T V.24.

See section 1.9.1 for functional description.

See section 2.6.1 for external circuit design-in.

USB

VUSB_DET

17

I

USB detect input

USB_D-

28

I/O

USB Data Line D-

USB_D+

29

I/O

USB Data Line D+

SPI

34

O

SPI MOSI

I2S_WA /

SPI_MOSI

VBUS (5 V typical) USB supply generated by the host must be connected

to this input pin to enable the USB interface.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

USB interface for AT commands, data communication, FOAT, FW

update by u-blox tool, diagnostics.

90 Ω nominal differential impedance (Z0)

30 Ω nominal common mode impedance (ZCM)

Pull-up or pull-down resistors and external series resistors as required

by the USB 2.0 specifications [4] are part of the USB pin driver and need

not be provided externally.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

USB interface for AT commands, data communication, FOAT, FW

update by u-blox tool, diagnostics.

90 Ω nominal differential impedance (Z0)

30 Ω nominal common mode impedance (ZCM)

Pull-up or pull-down resistors and external series resistors as required

by the USB 2.0 specifications [4] are part of the USB pin driver and need

not be provided externally.

Test-Point for diagnostic / FW update strongly recommended.

See section 1.9.2 for functional description.

See section 2.6.2 for external circuit design-in.

SPI Master Output Slave Input, alternatively configurable as I2S word

alignment

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

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Function

Pin Name

Pin No

I/O

Description

Remarks

37

I

SPI MISO

I2S_RXD /

SPI_MISO

I2S_CLK /

SPI_CLK

I2S_TXD /

SPI_CS

36

O

SPI clock

35

O

SPI Chip Select

SDIO

SDIO_D0

47

I/O

SDIO serial data [0]

SDIO_D1

49

I/O

SDIO serial data [1]

SDIO_D2

44

I/O

SDIO serial data [2]

SDIO_D3

48

I/O

SDIO serial data [3]

SDIO_CLK

45

O

SDIO serial clock

SDIO_CMD

46

I/O

SDIO command

SARA-R4/N4 series - System Integration Manual

SPI Master Input Slave Output, alternatively configurable as I2S receive

data

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

SPI clock, alternatively configurable as I2S clock

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

SPI Chip Select, alternatively settable as I2S transmit data

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.3 for functional description.

See section 2.6.3 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

Not supported by “00”, “01” and “x2” product versions.

See section 1.9.4 for functional description.

See section 2.6.4 for external circuit design-in.

DDC

SCL

27

O

I2C bus clock line

SDA

26

I/O

I2C bus data line

Audio

35

O

I2S transmit data

I2S_TXD /

SPI_CS

I2S_RXD /

SPI_MISO

I2S_CLK /

SPI_CLK

37

I

I2S receive data

36

I/O

I2S clock

1.8 V open drain, for communication with I2C-slave devices.

Internal pull-up to V_INT: external pull-up is not required.

Not supported by “00” and “01” product versions.

See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

1.8 V open drain, for communication with I2C-slave devices.

Internal pull-up to V_INT: external pull-up is not required.

Not supported by “00” and “01” product versions.

See section 1.9.5 for functional description.

See section 2.6.5 for external circuit design-in.

I2S transmit data, alternatively configurable as SPI Chip Select

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

I2S receive data, alternatively configurable as SPI Master Input Slave

Output

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

I2S clock, alternatively configurable as SPI clock

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

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SARA-R4/N4 series - System Integration Manual

Function

Pin Name

Pin No

Description

Remarks

34

I2S word alignment

I/O

I/O

I2S_WA /

SPI_MOSI

GPIO

GPIO1

16

I/O

GPIO

GPIO2

23

I/O

GPIO

GPIO3

24

I/O

GPIO

GPIO4

25

I/O

GPIO

GPIO5

42

I/O

GPIO

GPIO6

19

I/O

GPIO

Reserved

RSVD

33

N/A

Reserved pin

RSVD

2, 31

N/A

Reserved pin

Table 3: SARA-R4/N4 series modules pin definition, grouped by function

I2S word alignment, alternatively configurable as

SPI Master Output Slave Input

Not supported by “00”, “01” and “x2” product versions.

See section 1.10 for functional description.

See section 2.7 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

1.8 V GPIO with alternatively configurable functions.

See section 1.11 for functional description.

See section 2.8 for external circuit design-in.

This pin can be connected to GND.

See sections 1.12 and 2.9

Leave unconnected.

See sections 1.12 and 2.9

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Mode

Deep-Sleep

Idle

SARA-R4/N4 series - System Integration Manual

1.4 Operating modes

SARA-R4/N4 series modules have several operating modes. The operating modes are defined in Table 4 and described in

detail in Table 5, providing general guidelines for operation.

General Status

Operating Mode

Definition

Power-down

Not-Powered Mode

VCC supply not present or below operating range: module is switched off.

Power-Off Mode

VCC supply within operating range and module is switched off.

Normal Operation

Deep-Sleep Mode

RTC runs with 32 kHz reference internally generated.

Idle Mode

Module processor runs with 32 kHz reference generated by the internal oscillator.

Active Mode

Module processor runs with 19.2 MHz reference generated by the internal oscillator.

Connected Mode

RF Tx/Rx data connection enabled and processor core runs with 19.2 MHz reference.

Table 4: SARA-R4/N4 series modules operating modes definition

Description

Transition between operating modes

Not-Powered

Module is switched off.

Application interfaces are not accessible.

Power-Off

Module is switched off: normal shutdown by an

appropriate power-off event (see 1.6.2).

Application interfaces are not accessible.

When VCC supply is removed, the modules enter not-powered mode.

When in not-powered mode, the module can enter power-off mode applying

VCC supply (see 1.6.1).

The modules enter power-off mode from active mode when the host

processor implements a clean switch-off procedure, by sending the

AT+CPWROFF command or by using the PWR_ON pin (see 1.6.2).

When in power-off mode, the modules can be switched on by the host

processor using the PWR_ON input pin (see 1.6.1).

When in power-off mode, the modules enter not-powered mode by

removing VCC supply.

The modules automatically switch from the active mode to low power deep

sleep mode whenever possible, upon expiration of the 6 seconds AT

inactivity timer, and upon expiration of “Active Timer”, entering in the Power

Saving Mode defined in 3GPP Rel.13, if power saving configuration is enabled

(see 1.13.9 and the SARA-R4/N4 series AT Commands Manual [2], AT+CPSMS

command).

When in low power deep sleep mode, the module switches on to the active

mode upon expiration of “Periodic Update Timer” according to the Power

Saving Mode defined in 3GPP Rel.13 (see 1.13.9 and the SARA-R4/N4 series

AT Commands Manual [2], AT+CPSMS command), or it can be switched on to

the active mode by the host processor using the PWR_ON input pin (see

section 1.6.1).

The modules automatically switch from the active mode to low power idle

mode whenever possible, upon expiration of the 6 seconds AT inactivity

timer, if low power configuration is enabled (see the SARA-R4/N4 series AT

Commands Manual [2], AT+UPSV command).

When in low power idle mode, the module switches to the active mode upon

data reception over UART serial interface. The first character received in low

power idle mode wakes up the system: it is not recognized as valid

communication character, and the recognition of the subsequent characters

is guaranteed only after the complete system wake-up.

Only the internal 32 kHz reference is active.

The RF section and the application interfaces are

temporarily disabled and switched off: the module is

temporarily not ready to communicate with an

external device by means of the application

interfaces as configured to reduce the current

consumption.

The module enters the low power deep sleep mode

(entering the Power Saving Mode defined in 3GPP

Rel.13) whenever possible, if power saving

configuration is enabled by AT+CPSMS command

(see the SARA-R4/N4 series AT Commands Manual

[2]), reducing current consumption (see 1.13.9).

Power saving configuration is not enabled by default;

it can be enabled by AT+CPSMS (see the SARA-R4/N4

series AT Commands Manual [2]).

Module is switched on with application interfaces

temporarily disabled: the module is temporarily not

ready to communicate with an external device by

means of the application interfaces as configured to

reduce the current consumption.

The module enters the low power idle mode

whenever possible, if low power configuration is

enabled by AT+UPSV command (see the SARA-R4/N4

series AT Commands Manual [2]), reducing current

consumption.

Low power configuration is not enabled by default; it

can be enabled by AT+UPSV (see the SARA-R4/N4

series AT Commands Manual [2]).

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Mode

Active

Description

Transition between operating modes

Module is switched on with application interfaces

enabled or not suspended: the module is ready to

communicate with an external device by means of

the application interfaces unless power saving

configuration is enabled by AT+CPSMS (see the

SARA-R4/N4 series AT Commands Manual [2]).

SARA-R4/N4 series - System Integration Manual

The modules enter active mode from power-off mode when the host

processor implements a clean switch-on procedure by using the PWR_ON

pin (see 1.6.1).

The modules enter active mode from low power deep sleep mode upon

expiration of “Periodic Update Timer” (see 1.13.9), or when the host

processor implements a clean switch-on procedure by using the PWR_ON

pin (see 1.6.1).

The modules enter power-off mode from active mode when the host

processor implements a clean switch-off procedure (see 1.6.2).

The modules automatically switch from active to low power deep sleep

mode whenever possible, if power saving is enabled (see 1.13.9).

The module switches from active to connected mode when a RF Tx/Rx data

connection is initiated or when RF Tx/Rx activity is required due to a

connection previously initiated.

The module switches from connected to active mode when a RF Tx/Rx data

connection is terminated or suspended.

When a data connection is initiated, the module enters connected mode

from active mode.

Connected mode is suspended if Tx/Rx data is not in progress. In such cases

the module automatically switches from connected to active mode and then,

if power saving configuration is enabled by the AT+CPSMS command, the

module automatically switches to low power deep sleep mode whenever

possible. Vice-versa, the module wakes up from low power deep sleep mode

to active mode and then connected mode if RF Tx/Rx activity is necessary.

When a data connection is terminated, the module returns to the active

mode.

Connected

RF Tx/Rx data connection is in progress.

The module is prepared to accept data signals from

an external device.

Table 5: SARA-R4/N4 series modules operating modes description

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Figure 2 describes the transition between the different operating modes.

SARA-R4/N4 series - System Integration Manual

Not

powered

Apply VCC

Rem ove VCC

Power off

Swit ch ON:

• PW R_ON

Swit ch OFF:

• AT+CPW ROFF

• PW R_ON

Incom ing/out going dat a

or ot her dedicat ed device

net work com m unicat ion

If PSM m ode is enabled,

if AT Inact ivit y Tim er and

Act ive Tim er are expired

Connect ed

Act ive

Deep

Sleep

No RF Tx/Rx in progress,

Com m unicat ion dropped

• Upon expirat ion of t he

Periodic Updat e Tim er

• Using PW R_ON pin

If low power m ode is enabled,

if AT Inact ivit y Tim er is expired

Dat a received over UART

Figure 2: SARA-R4/N4 series modules operating modes transitions

Idle

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SARA-R4/N4 series - System Integration Manual

1.5 Supply interfaces

1.5.1 Module supply input (VCC)

The modules must be supplied via the three VCC pins that represent the module power supply input.

Voltage must be stable, because during operation, the current drawn by the SARA-R4/N4 series modules through the VCC

pins can vary by several orders of magnitude, depending on the operating mode and state (as described in sections

1.5.1.2, 1.5.1.3, 1.5.1.4 and 1.5.1.6).

It is important that the supply source is able to withstand both the maximum pulse current occurring during a transmit

burst at maximum power level and the average current consumption occurring during Tx / Rx call at maximum RF power

level (see the SARA-R4 Data Sheet [1]).

SARA-R412M modules provide separate supply inputs over the three VCC pins:

• VCC pins #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of the total

current drawn of the module when RF transmission is enabled during a call

• VCC pin #51 represents the supply input for the internal baseband Power Management Unit, demanding minor part

of the total current drawn of the module when RF transmission is enabled during a call

The 3 VCC pins of SARA-R404M, SARA-R410M, SARA-N410 modules are internally connected each other to both the

internal RF Power Amplifier and the internal baseband Power Management Unit.

Figure 3 provides a simplified block diagram of SARA-R4/N4 series modules’ internal VCC supply routing.

VCC

53

VCC

52

VCC

51

SARA-R40 4M / SARA-R410 M / SARA-N410

SARA-R412M

Power

M anagement

Unit

Power

Amplif ier

Transceiver

Baseband

Processor

M emory

VCC

53

VCC

52

VCC

51

Power

M anagement

Unit

Power

Amplif ier

Transceiver

Baseband

Processor

M emory

Figure 3: Block diagram of SARA-R4/N4 series modules’ internal VCC supply routing

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System description

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⚠⚠⚠⚠

Item

VCC nominal voltage

VCC voltage during

normal operation

SARA-R4/N4 series - System Integration Manual

1.5.1.1 VCC supply requirements

Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions to correctly design a

VCC supply circuit compliant with the requirements listed in Table 6.

The supply circuit affects the RF compliance of the device integrating SARA-R4/N4 series modules with applicable

required certification schemes as well as antenna circuit design. Compliance is guaranteed if the requirements

summarized in the Table 6 are fulfilled.

Requirement

Remark

Within VCC normal operating range:

SARA-R404M / SARA-R410M / SARA-N410:

SARA-R412M:

3.2 V / 4.2 V

3.2 V / 4.5 V

Within VCC extended operating range:

SARA-R404M / SARA-R410M / SARA-N410:

SARA-R412M:

3.0 V / 4.2 V

3.0 V / 4.5 V

VCC average current

Support with adequate margin the highest averaged VCC

current consumption value in connected mode conditions

specified in the SARA-R4/N4 series Data Sheet [1]

VCC peak current

Support with adequate margin the highest peak VCC

current consumption value in Tx connected mode

conditions specified in the SARA-R4/N4 series Data

Sheet [1]

VCC voltage drop during

Tx slots

Lower than 400 mV

VCC voltage ripple during

Tx

Noise in the supply pins must be minimized

VCC under/over-shoot at

start/end of Tx slots

Absent or at least minimized

Table 6: Summary of VCC modules supply requirements

RF performance is guaranteed when VCC voltage is inside the

normal operating range limits.

RF performance may be affected when VCC voltage is outside

the normal operating range limits, though the module is still

fully functional until the VCC voltage is inside the extended

operating range limits.

VCC voltage must be above the extended operating range

minimum limit to switch-on the module.

The module may switch-off when the VCC voltage drops below

the extended operating range minimum limit.

Operation above VCC extended operating range is not

recommended and may affect device reliability.

The maximum average current consumption can be greater

than the specified value according to the actual antenna

mismatching, temperature and supply voltage.

Section 1.5.1.2 describes current consumption profiles in

connected mode.

The maximum peak Tx current consumption can be greater than

the specified value according to the actual antenna

mismatching, temperature and supply voltage.

Section 1.5.1.2 describes current consumption profiles in

connected mode.

VCC voltage drop directly affects the RF compliance with

applicable certification schemes.

Figure 6 describes VCC voltage drop during 2G Tx slots.

High supply voltage ripple values during RF transmissions in

connected mode directly affect the RF compliance with the

applicable certification schemes.

VCC under/over-shoot directly affects the RF compliance with

applicable certification schemes.

Figure 6 describes VCC voltage under/over-shoot.

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SARA-R4/N4 series - System Integration Manual

1.5.1.2 VCC current consumption in LTE connected mode

During an LTE connection, the SARA-R4/N4 series modules transmit and receive in half duplex mode.

The current consumption depends on output RF power, which is always regulated by the network (the current base

station) sending power control commands to the module. These power control commands are logically divided into a slot

of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz.

Figure 4 shows an example of SARA-R4/N4 series modules’ current consumption profile versus time in connected mode:

transmission is enabled for one sub-frame (1 ms) according to LTE Category M1 half-duplex connected mode.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

Current [mA]

50 0

40 0

30 0

20 0

100

0

Current consum pt ion value

depends on TX power and

act ual ant enna load

1 Slot

1 Resource Block

(0.5 m s)

1 LTE Radio Fram e

(10 m s)

1 Slot

1 Resource Block

(0.5 m s)

1 LTE Radio Fram e

(10 m s)

Time

[ms]

Figure 4: VCC current consumption profile versus time during LTE Cat M1 half-duplex connection

1.5.1.3 VCC current consumption in 2G connected mode

When a 2G call is established, the VCC consumption is determined by the current consumption profile typical of the 2G

transmitting and receiving bursts.

The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is

regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the

average current consumption.

If the module is transmitting in 2G single-slot mode in the 850 or 900 MHz bands at the maximum RF power control level

(approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption can reach a high peak / pulse (see the

SARA-R4/N4 series Data Sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of

1 frame = 8 slots/burst), that is, with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access).

If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are

much lower than during transmission in the low bands, due to the 3GPP transmitter output power specifications.

During a 2G call, current consumption is not significantly high while receiving or in monitor bursts, and it is low in the

bursts unused to transmit / receive.

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Figure 5 shows an example of the module current consumption profile versus time in 2G single-slot.

SARA-R4/N4 series - System Integration Manual

2.0

1.5

1.0

0.5

0.0

Volt age

3.8 V

(t yp)

Current [A]

190 0 m A

Peak current depends

on TX power and

act ual ant enna load

60 -120 m A

10-40 m A

200 m A

60-120 m A

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

M ON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

M ON

slot

unused

slot

GSM f ram e

4.615 m s

(1 f ram e = 8 slot s)

GSM f ram e

4.615 m s

(1 f ram e = 8 slot s)

Time

[ms]

Figure 5: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)

Figure 6 illustrates the VCC voltage profile versus time during a 2G single-slot call, according to the related VCC current

consumption profile described in Figure 5.

overshoot

drop

ripple

undershoot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

M ON

slot

unused

slot

RX

slot

unused

slot

unused

slot

TX

slot

unused

slot

unused

slot

M ON

slot

unused

slot

GSM f ram e

4.615 m s

(1 f ram e = 8 slot s)

GSM f ram e

4.615 m s

Time

(1 f ram e = 8 slot s)

Figure 6: Description of the VCC voltage profile versus time during a 2G single-slot call (1 TX slot, 1 RX slot)

When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be

used to receive. The transmitted power depends on network conditions, which set the peak current consumption. But

according to GPRS specifications, the maximum transmitted RF power is reduced if more than one slot is used to transmit,

so the maximum peak of current is not as high as it can be in the case of a GSM call.

If the module transmits in GPRS multi-slot class 12, in 850 or 900 MHz bands, at maximum RF power level, the

consumption can reach a quite a high peak but lower than the one achievable in 2G single-slot mode. This happens for

2.308 ms (width of the 4 Tx slots/bursts) in the case of multi-slot class 12, with a periodicity of 4.615 ms (width of 1 frame

= 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA.

If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are lower than in the 850

or 900 MHz band because of the 3GPP Tx power specifications.

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Figure 7 illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz bands, with 4 slots used

to transmit and 1 slot used to receive, as for the GPRS multi-slot class 12.

SARA-R4/N4 series - System Integration Manual

Current [A]

1600 m A

1.5

1.0

0.5

0.0

Peak current depends

on T X power and

act ual ant enna load

60-120m A

10-40m A

200m A

60-120m A

RX

slot

unused

slot

TX

slot

TX

slot

TX

TX

slot

slot

M ON

slot

unused

slot

RX

slot

unused

slot

TX

slot

TX

slot

TX

M ON

TX

slot

slot

slot

unused

slot

GSM f ram e

4.615 m s

(1 f ram e = 8 slot s)

GSM f ram e

4.615 m s

(1 f ram e = 8 slot s)

Time

[ms]

Figure 7: VCC current consumption profile versus time during a GPRS multi-slot class 12 connection (4 TX slots, 1 RX slot)

In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the one during GPRS

connections: the current consumption profile in GPRS multi-slot class 12 connected mode illustrated in the Figure 7 is

representative for the EDGE multi-slot class 12 connected mode as well.

1.5.1.4 VCC current consumption in low power deep sleep mode (PSM enabled)

The power saving mode configuration is by default disabled, but it can be enabled using the AT+CPSMS command (see

the SARA-R4/N4 series AT Commands Manual [2] and section 1.13.9).

When power saving mode is enabled, the module automatically enters the PSM low power deep sleep mode whenever

possible, reducing current consumption down to a steady value in the µA range: only the RTC runs with internal 32 kHz

reference clock frequency.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

Due to RTC running during PSM mode, the Cal-RC turns on the crystal every ~10 s to calibrate the RC oscillator, as a

consequence, a very low spike in current consumption will be observed.

1.5.1.5 VCC current consumption in low power idle mode (low power enabled)

The low power idle mode configuration is by default disabled, but it can be enabled using the AT+UPSV command (see

the SARA-R4/N4 series AT Commands Manual [2]).

When low power idle mode is enabled, the module automatically enters the low power mode whenever possible, but it

must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the

2G / LTE system requirements, even if connected mode is not enabled by the application. When the module monitors the

paging channel, it wakes up to the active mode to enable the reception of the paging block. In between, the module

switches to low power mode. This is known as discontinuous reception (DRX) or extended discontinuous reception

(eDRX).

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

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1.5.1.6 VCC current consumption in active mode (PSM / low power disabled)

The active mode is the state where the module is switched on and ready to communicate with an external device by

means of the application interfaces (as the USB or the UART serial interface). The module processor core is active, and

the 19.2 MHz reference clock frequency is used.

If power saving mode and/or low power mode configurations are disabled, as it is by default (see the SARA-R4/N4 series

AT Commands Manual [2], +CPSMS, +UPSV AT commands for details), the module remains in active mode. Otherwise, if

PSM mode and/or low power mode configurations are enabled, the module enters PSM mode and/or low power mode

whenever possible.

Figure 8 illustrates a typical example of the module current consumption profile when the module is in active mode. In

such case, the module is registered with the network and, while active mode is maintained, the receiver is periodically

activated to monitor the paging channel for paging block reception.

Detailed current consumption values can be found in the SARA-R4/N4 series Data Sheet [1].

Current [mA]

10 0

10 0

0

0

Current [mA]

Paging period

Time [s]

Time [ms]

RX

Enabled

ACTIVE M ODE

Figure 8: VCC current consumption profile with power saving disabled and module registered with the network: active mode is always held and the

receiver is periodically activated to monitor the paging channel for paging block reception

1.5.2 Generic digital interfaces supply output (V_INT)

The V_INT output pin of the SARA-R4/N4 series modules is generated by the module internal power management

circuitry when the module is switched on and it is not in the deep sleep power saving mode.

The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA-R4/N4 series Data Sheet [1].

The V_INT voltage domain can be used in place of an external discrete regulator as a reference voltage rail for external

components.

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1.6 System function interfaces

1.6.1 Module power-on

When the SARA-R4/N4 series modules are in the not-powered mode (i.e. the VCC module supply is not applied), they can

be switched on as follows:

• Rising edge on the VCC input pins to a valid voltage level, and then a low logic level needs to be set at the PWR_ON

input pin for a valid time.

When the SARA-R4/N4 series modules are in the power-off mode (i.e. switched off) or in the Power Saving Mode (PSM),

with a valid VCC supply applied, they can be switched on as follows:

•

Low pulse on the PWR_ON pin for a valid time period

The PWR_ON input pin is equipped with an internal active pull-up resistor. Detailed electrical characteristics with voltages

and timings are described in the SARA-R4/N4 series Data Sheet [1].

Figure 9 shows the module switch-on sequence from the not-powered mode, with following phases:

The external power supply is applied to the VCC module pins

The PWR_ON pin is held low for a valid time

•

•

• All the generic digital pins are tri-stated until the switch-on of their supply source (V_INT).

•

The internal reset signal is held low: the baseband core and all digital pins are held in reset state. When the internal

reset signal is released, any digital pin is set in the correct sequence from the reset state to the default operational

configured state. The duration of this phase differs within generic digital interfaces and USB interface due to host /

device enumeration timings.

The module is fully ready to operate after all interfaces are configured.

•

Start-up

event

Start of interface

configuration

M odule interfaces

are configured

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

GPIO

System State

OFF

ON

BB Pads State

Tristate / Floating

Internal Reset

Internal Reset → Operational

Operational

Figure 9: SARA-R4/N4 series switch-on sequence description

0 s

~4.5 s

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The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor:

o

o

the V_INT pin, to sense the start of the SARA-R4/N4 series module switch-on sequence

the GPIO pin configured to provide the module operating status indication (see SARA-R4/N4 series Commands

Manual [2], AT+UGPIOC), to sense when the module is ready to operate

Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage driven by an external

application should be applied to any generic digital interface of the module.

Before the SARA-R4/N4 series module is fully ready to operate, the host application processor should not send any

AT command over AT communication interfaces (USB, UART) of the module.

The duration of the SARA-R4/N4 series modules’ switch-on routine can vary depending on the application / network

settings and the concurrent module activities.

An abrupt removal of the VCC supply or forcing a low level on the RESET_N input once the boot of SARA-R4/N4 series

modules has been triggered may lead to an unrecoverable faulty state!

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1.6.2 Module power-off

SARA-R4/N4 series modules can be cleanly switched off by:

• AT+CPWROFF command (see SARA-R4/N4 series AT Commands Manual [2]).

•

Low pulse on the PWR_ON pin for a valid time period (see the SARA-R4/N4 series Data Sheet [1]).

These events listed above trigger the storage of the current parameter settings in the non-volatile memory of the module,

and a clean network detach procedure.

An abrupt under-voltage shutdown occurs on SARA-R4/N4 series modules when the VCC module supply is removed. If

this occurs, it is not possible to perform the storing of the current parameter settings in the module’s non-volatile memory

or to perform the clean network detach.

It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series modules normal

operations.

An abrupt removal of the VCC supply during SARA-R4/N4 series modules normal operations may lead to an

unrecoverable faulty state!

An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on RESET_N pin. In this

case, the current parameter settings are not saved in the module’s non-volatile memory and a clean network detach is

not performed.

It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N

input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT

commands fails or if the module does not reply to a specific AT command after a time period longer than the one

defined in SARA-R4/N4 series AT Commands Manual [2].

Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may lead to an

unrecoverable faulty state!

Figure 10 and Figure 11 describe the SARA-R4/N4 series modules switch-off sequence started by means of the

AT+CPWROFF command and by means of the PWR_ON input pin respectively, allowing storage of current parameter

settings in the module’s non-volatile memory and a clean network detach, with the following phases:

• When the +CPWROFF AT command is sent, or when a low pulse with appropriate time duration (see the SARA-R4/N4

series Data Sheet [1]) is applied at the PWR_ON input pin, the module starts the switch-off routine.

Then, if the +CPWROFF AT command has been sent, the module replies OK on the AT interface: the switch-off routine

is in progress.

• At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned

off, including the generic digital interfaces supply (V_INT).

Then, the module remains in switch-off mode as long as a switch on event does not occur (e.g. applying a low level

to PWR_ON), and enters not-powered mode if the VCC supply is removed.

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•

•

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AT+CPWROFF

sent to the module

OK

replied by the module

VCC can be

removed

ON

OFF

BB Pads State Operational

Operational → Tristate

Tristate / Floating

Figure 10: SARA-R4/N4 series modules switch-off sequence by means of AT+CPWROFF command

The module starts

the switch-off routine

VCC can be

removed

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

System State

VCC

PWR_ON

RESET_N

V_INT

Internal Reset

System State

ON

OFF

BB Pads State

Operational

Operational -> Tristate

Tristate / Floating

Figure 11: SARA-R4/N4 series modules switch-off sequence by means of PWR_ON pin

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The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor the V_INT pin to

sense the end of the switch-off sequence.

VCC supply can be removed only after V_INT goes low: an abrupt removal of the VCC supply during SARA-R4/N4

series modules normal operations may lead to an unrecoverable faulty state!

The duration of each phase in the SARA-R4/N4 series modules’ switch-off routines can largely vary depending on the

application / network settings and the concurrent module activities.

1.6.3 Module reset

SARA-R4/N4 series modules can be cleanly reset (rebooted) by:

• AT+CFUN command (see the SARA-R4/N4 series AT Commands Manual [2]).

In the case above an “internal” or “software” reset of the module is executed: the current parameter settings are saved

in the module’s non-volatile memory and a clean network detach is performed.

An abrupt hardware shutdown occurs on SARA-R4/N4 series modules when a low level is applied on RESET_N input pin

for a valid time period. In this case, the current parameter settings are not saved in the module’s non-volatile memory

and a clean network detach is not performed. Then, the module remains in power-off mode as long as a switch on event

does not occur applying an appropriate low level to the PWR_ON input.

It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N

input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT

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commands fails or if the module does not provide a reply to a specific AT command after a time period longer than

the one defined in the SARA-R4/N4 series AT Commands Manual [2].

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Forcing a low level on the RESET_N input during SARA-R4/N4 series modules normal operations may lead to an

unrecoverable faulty state!

The RESET_N input pin is directly connected to the Power Management Unit IC, with an integrated pull-up to a 1.8 V

supply domain, in order to perform an abrupt hardware shutdown when asserted. Detailed electrical characteristics with

voltages and timings are described in the SARA-R4/N4 series Data Sheet [1].

SARA-R4/ N4

Power M anagement Unit

1.8 V

RESET_N

18

Reset

Shut down

Figure 12: RESET_N input description

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1.7 Antenna interface

1.7.1 Antenna RF interface (ANT)

SARA-R4/N4 series modules provide an RF interface for connecting the external antenna. The ANT pin represents the

primary RF input/output for transmission and reception of LTE RF signals.

The ANT pin has a nominal characteristic impedance of 50 Ω and must be connected to the primary Tx / Rx antenna

through a 50 Ω transmission line to allow clear RF transmission and reception.

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Item

1.7.1.1 Antenna RF interfaces requirements

Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to correctly design

antennas circuits compliant with these requirements.

The antenna circuits affect the RF compliance of the device integrating SARA-R4/N4 series modules with applicable

required certification schemes (for more details see section 0). Compliance is guaranteed if the antenna RF interface

requirements summarized in Table 7 are fulfilled.

Requirements

Remarks

Impedance

50 Ω nominal characteristic impedance

Frequency Range

See the SARA-R4/N4 series Data Sheet [1] The required frequency range of the antenna connected to ANT port depends on

Return Loss

S11 < -10 dB (VSWR < 2:1) recommended

S11 < -6 dB (VSWR < 3:1) acceptable

Efficiency

> -1.5 dB ( > 70% ) recommended

> -3.0 dB ( > 50% ) acceptable

Maximum Gain

According to radiation exposure limits

The impedance of the antenna RF connection must match the 50 Ω impedance of

the ANT port.

the operating bands of the used cellular module and the used mobile network.

The Return loss or the S11, as the VSWR, refers to the amount of reflected power,

measuring how well the antenna RF connection matches the 50 Ω characteristic

impedance of the ANT port.

The impedance of the antenna termination must match as much as possible the

50 Ω nominal impedance of the ANT port over the operating frequency range,

reducing as much as possible the amount of reflected power.

The radiation efficiency is the ratio of the radiated power to the power delivered

to antenna input: the efficiency is a measure of how well an antenna receives or

transmits.

The radiation efficiency of the antenna connected to the ANT port needs to be

enough high over the operating frequency range to comply with the Over-The-Air

(OTA) radiated performance requirements, as Total Radiated Power (TRP) and the

Total Isotropic Sensitivity (TIS), specified by applicable related certification

schemes.

The power gain of an antenna is the radiation efficiency multiplied by the

directivity: the gain describes how much power is transmitted in the direction of

peak radiation to that of an isotropic source.

The maximum gain of the antenna connected to ANT port must not exceed the

herein stated value to comply with regulatory agencies radiation exposure limits.

For additional info see sections 4.2.2.

The antenna connected to the ANT port must support with adequate margin the

maximum power transmitted by the modules.

Input Power

> 24 dBm ( > 0.25 W ) for R404M / R410M

/ N410

> 33 dBm ( > 2.0 W ) for R412M

Table 7: Summary of Tx/Rx antenna RF interface requirements

1.7.2 Antenna detection interface (ANT_DET)

The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided

to sense the antenna presence.

The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the

application requires it. The antenna detection is forced by the +UANTR AT command. See the SARA-R4/N4 series AT

Commands Manual [2] for more details on this feature.

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The ANT_DET pin generates a DC current (for detailed characteristics see the SARA-R4/N4 series Data Sheet [1]) and

measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the

application board to GND. So, the requirements to achieve antenna detection functionality are the following:

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used

an antenna detection circuit must be implemented on the application board

See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in

guidelines.

•

•

1.8 SIM interface

1.8.1 SIM interface

SARA-R4/N4 series modules provide high-speed SIM/ME interface including automatic detection and configuration of the

voltage required by the connected SIM card or chip.

Both 1.8 V and 3 V SIM types are supported. Activation and deactivation with automatic voltage switch from 1.8 V to 3 V

are implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output provides internal short circuit

protection to limit start-up current and protect the SIM to short circuits.

The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the

values determined by the SIM card or chip.

1.8.2 SIM detection interface

The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is

configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if cleanly

connected to the mechanical switch of a SIM card holder as described in section 2.5:

Low logic level at GPIO5 input pin is recognized as SIM card not present

•

• High logic level at GPIO5 input pin is recognized as SIM card present

For more details, see the SARA-R4/N4 series AT Commands Manual [2], +UGPIOC, +CIND and +CMER AT commands.

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1.9 Data communication interfaces

SARA-R4/N4 series modules provide the following serial communication interface:

• USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host application

processor (AT commands, data, FW update by means of the FOAT feature), for FW update by means of the u-blox

dedicated tool and for diagnostics. See section 1.9.2.

SPI interface: Serial Peripheral Interface available for communication with an external compatible device. See section

1.9.3.

SDIO interface: Secure Digital Input Output interface available for communication with a compatible device. See

section 1.9.4.

•

•

• DDC interface: I2C bus compatible interface available for the communication with u-blox GNSS positioning chips or

modules and with external I2C devices. See section 1.9.5.

1.9.1 UART interface

1.9.1.1 UART features

The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the SARA-R4/N4 series

modules, supporting:

• AT command mode19

• Data mode and Online command mode19

• Multiplexer protocol functionality

•

FW upgrades by means of the FOAT feature (see 1.13.7)

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The UART is available only if the USB is not enabled as AT command / data communication interface: UART and USB

cannot be concurrently used for this purpose.

UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS compatible

signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for electrical characteristics see the

SARA-R4/N4 series Data Sheet [1]), providing:

• data lines (RXD as output, TXD as input)

• hardware flow control lines (CTS as output, RTS as input)

• modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output)

SARA-R4/N4 series modules are designed to operate as cellular modems, i.e. as the data circuit-terminating equipment

(DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor connected to the module UART

interface represents the data terminal equipment (DTE).

UART signal names of the cellular modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD line represents

data transmitted by the DTE (host processor output) and received by the DCE (module input).

Hardware flow control is not supported by the “00”, “01” and the SARA-R410M-02B-00 product versions, but the RTS

input line of the module must be set low (= ON state) to communicate over UART interface on the “00” and “01”

product versions.

DTR input of the module must be set low (= ON state) to have URCs presented over UART interface.

SARA-R4/N4 series modules’ UART interface is by default configured in AT command mode, if the USB interface is not

enabled as AT command / data communication interface (UART and USB cannot be concurrently used for this purpose):

the module waits for AT command instructions and interprets all the characters received as commands to execute. All

the functionalities supported by SARA-R4/N4 series modules can be in general set and configured by AT commands:

19 For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [1]

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• AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8]

• u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2])

The default baud rate is 115200 b/s, while the default frame format is 8N1 (8 data bits, No parity, 1 stop bit: see Figure

13). Baud rates can be configured by AT command (see the SARA-R4/N4 series AT Commands Manual [2]).

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Automatic baud rate detection and automatic frame format recognition are not supported.

Normal Transfer, 8N1

Start of 1-Byte

transfer

Possible Start of

next transfer

D0 D1 D2 D3 D4 D5 D6 D7

Start Bit

(Always 0)

tbit = 1/(Baudrate)

Stop Bit

(Always 1)

Figure 13: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit)

1.9.1.2 UART signals behavior

At the end of the module boot sequence (see Figure 9), the module is by default in active mode, and the UART interface

is initialized and enabled as AT commands interface only if the USB interface is not enabled as AT command / data

communication interface: UART and USB cannot be concurrently used for this purpose.

The configuration and the behavior of the UART signals after the boot sequence are described below:

The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module

holds RXD in the OFF state until the module transmits some data.

The module data input line (TXD) is assumed to be controlled by the external host once UART is initialized and if UART

is used in the application. The TXD data input line has an internal active pull-down enabled on the “00” and SARA-

R410M-02B product versions, and an internal active pull-up enabled on the other product version.

•

•

1.9.1.3 UART multiplexer protocol

SARA-R4/N4 series modules include multiplexer functionality as per 3GPP TS 27.010 [8], on the UART physical link. This

is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and the application

processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART).

The following virtual channels are defined:

• Channel 0:

• Channel 1:

• Channel 2:

for Multiplexer control

for all AT commands, and non-Dial Up Network (non-DUN) data connections. UDP, TCP data socket /

data call connections via relevant AT commands.

for Dial Up Network (DUN) data connection. It requires the host to have and use its own TCP/IP

stack. The DUN can be initiated on modem side or terminal/host side.

for u-blox GNSS data tunneling (not supported by “00” and “01” product versions).

• Channel 3:

1.9.2 USB interface

1.9.2.1 USB features

SARA-R4/N4 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate,

representing the main interface for transferring high speed data with a host application processor, supporting:

• AT command mode20

• Data mode and Online command mode20

•

20 For the definition of the interface data mode, command mode and online command mode see SARA-R4/N4 series AT Commands Manual [2]

FW upgrades by means of the FOAT feature (see 1.13.7)

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FW upgrades by means of the u-blox EasyFlash dedicated tool

Trace log capture (diagnostic purposes)

The module itself acts as a USB device and can be connected to a USB host such as a Personal Computer or an embedded

application microprocessor equipped with compatible drivers.

The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus Revision 2.0

specification [4], while the VUSB_DET input pin senses the VBUS USB supply presence (nominally 5 V at the source) to

detect the host connection and enable the interface. Neither the USB interface, nor the whole module is supplied by the

VUSB_DET input, which senses the USB supply voltage and absorbs few microamperes.

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The USB interface is available as AT command / data communication interface only if an external valid USB VBUS

supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the switch-on of the module, and

then held during normal operations. In this case, the UART will be not available.

If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS

supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode

defined in 3GPP Rel.13.

The USB interface is controlled and operated with:

• AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7]

• u-blox AT commands (see the SARA-R4/N4 series AT Commands Manual [2])

The USB interface of SARA-R4/N4 series modules can provide the following USB functions:

• AT commands and data communication

• Diagnostic log

The USB profile of SARA-R4/N4 series modules identifies itself by the following VID (Vendor ID) and PID (Product ID)

combination, included in the USB device descriptor according to the USB 2.0 specifications [4].

• VID = 0x05C6

• PID = 0x90B2

•

•

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1.9.3 SPI interface

The SPI interface is not supported by “00”, “01”, “02” and “52” product versions: the SPI interface pins should not be

driven by any external device.

SARA-R4/N4 series modules include a Serial Peripheral Interface for communication with compatible external device.

The SPI interface can be made available as alternative function, in mutually exclusive way, over the digital audio interface

pins

SPI_CLK,

(I2S_WA

I2S_TXD / SPI_CS).

SPI_MOSI,

SPI_MISO,

I2S_RXD

I2S_CLK

/

/

/

The SDIO interface is not supported by “00”, “01”, “02” and “52” product versions: the SDIO interface pins should

not be driven by any external device.

SARA-R4/N4 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3,

SDIO_CLK, and SDIO_CMD) designed to communicate with external compatible SDIO devices.

1.9.4 SDIO interface

1.9.5 DDC (I2C) interface

The I2C interface is not supported by “00” and “01” product versions: the I2C interface pins should not be driven by

any external device.

SARA-R4/N4 series modules include an I2C-bus compatible DDC interface (SDA, SCL lines) available to communicate with

a u-blox GNSS receiver and with external I2C devices as an audio codec: the SARA-R4/N4 series module acts as an I2C

master which can communicate with I2C slaves in accordance with the I2C bus specifications [9].

The SDA and SCL pins have internal pull-up to V_INT, so there is no need of additional pull-up resistors on the external

application board.

1.10 Audio

Audio is not supported by “00”, “01”, “02” and “52” ” product versions: the I2S interface pins should not be driven by

any external device.

SARA-R4/N4 series modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio services.

SARA-R4/N4 series modules include an I2S digital audio interface to transfer digital audio data to/from an external

compatible audio device.

The digital audio interface can be made available as alternative function, in mutually exclusive way, over the SPI interface

pins (I2S_WA / SPI_MOSI, I2S_RXD / SPI_MISO, I2S_CLK / SPI_CLK, I2S_TXD / SPI_CS).

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1.11 General Purpose Input/Output

SARA-R4/N4 series modules include pins which can be configured as General Purpose Input/Output or to provide custom

functions via u-blox AT commands (for more details see the SARA-R4/N4 series AT Commands Manual [2], +UGPIOC,

+UGPIOR, +UGPIOW AT commands), as summarized in Table 8.

Function

Configurable GPIOs

Default GPIO

Description

Network status indication

Network status: registered / data transmission, no service

GNSS supply enable 21

Enable/disable the supply of a u-blox GNSS receiver connected to

the cellular module by the DDC (I2C) interface

GNSS data ready 21

Sense when a u-blox GNSS receiver connected to the module is

ready for sending data by the DDC (I2C) interface

SIM card detection

SIM card physical presence detection

Ring Indicator 22

Events indicator

Module status indication

Module switched off or in PSM low power deep sleep mode,

versus active or connected mode

Last gasp 22

Input to trigger last gasp notification

General purpose input

Input to sense high or low digital level

General purpose output

Output to set the high or the low digital level

--

--

--

--

--

--

--

--

--

GPIO1

GPIO2

GPIO3

GPIO5

RI

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

GPIO3, GPIO4, GPIO6

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO6

Pin disabled

Tri-state with an internal active pull-down enabled

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6, RI

GPIO1, GPIO2, GPIO3,

GPIO4, GPIO5, GPIO6, RI

Table 8: SARA-R4/N4 series modules GPIO custom functions configuration

1.12 Reserved pins (RSVD)

SARA-R4/N4 series modules have pins reserved for future use, marked as RSVD.

All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be

externally connected to ground.

21 Not supported by “00” and “01” product versions

22 Not supported by “00”, “01” and SARA-R410M-02B product versions

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1.13 System features

1.13.1 Network indication

GPIOs can be configured by the AT command to indicate network status (for further details see section 1.11 and the

SARA-R4/N4 series AT Commands Manual [2]):

• No service (no network coverage or not registered)

• Registered / Data call enabled (RF data transmission / reception)

1.13.2 Antenna supervisor

The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional feature that

can be implemented if the application requires it. The antenna supervisor is forced by the +UANTR AT command (see the

SARA-R4/N4 series AT Commands Manual [2] for more details).

The requirements to achieve antenna detection functionality are the following:

•

•

an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used

an antenna detection circuit must be implemented on the application board

See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for detection circuit

on application board and diagnostic circuit on antenna assembly design-in guidelines.

1.13.3 Dual stack IPv4/IPv6

SARA-R4/N4 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel.

For more details about dual stack IPv4/IPv6 see the SARA-R4/N4 series AT Commands Manual [2].

1.13.4 TCP/IP and UDP/IP

SARA-R4/N4 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured

established and handled via the data connection management packet switched data commands.

SARA-R4/N4 series modules provide Direct Link mode to establish a transparent end-to-end communication with an

already connected TCP or UDP socket via serial interfaces (USB, UART). In Direct Link mode, data sent to the serial

interface from an external application processor is forwarded to the network and vice-versa.

For more details on embedded TCP/IP and UDP/IP functionalities, see SARA-R4/N4 series AT Commands Manual [2].

1.13.5 FTP

SARA-R4/N4 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in the local file

system of the module.

FTP files can also be transferred using FTP Direct Link:

•

•

FTP download: data coming from the FTP server is forwarded to the host processor via USB / UART serial interfaces

(for FTP without Direct Link mode the data is always stored in the module’s flash file system)

FTP upload: data coming from the host processor via USB / UART serial interface is forwarded to the FTP server (for

FTP without Direct Link mode the data is read from the module’s flash file system)

When Direct Link is used for an FTP file transfer, only the file contents passes through USB / UART serial interface, whereas

all the FTP command handling is managed internally by the FTP application.

For more details about embedded FTP functionalities, see the SARA-R4/N4 series AT Commands Manual [2].

1.13.6 HTTP

SARA-R4/N4 series modules provide the embedded Hypertext Transfer Protocol (HTTP) services via AT commands for

sending requests to a remote HTTP server, receiving the server response and transparently storing it in the module’s

flash file system. For more details, see the SARA-R4/N4 series AT Commands Manual [2].

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1.13.7 Firmware update Over AT (FOAT)

This feature allows upgrading of the module firmware over the AT interface, using AT commands.

The +UFWUPD AT command enables a code download to the device from the host via the Xmodem protocol.

The +UFWINSTALL AT command then triggers a reboot, and upon reboot initiates a firmware installation on the device

via a special boot loader on the module. The bootloader first authenticates the downloaded image, then installs it, and

then reboots the module.

Firmware authenticity verification is performed via a security signature. The firmware is then installed, overwriting the

current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts

the firmware installation. After completing the upgrade, the module is reset again and wakes-up in normal boot.

For more details about Firmware update Over AT procedure, see the SARA-R4/N4 series AT Commands Manual [2],

+UFWUPD AT command.

1.13.8 Firmware update Over The Air (uFOTA)

This feature allows upgrading the module firmware over the air interface, based on u-blox client/server solution (uFOTA),

using LWM2M.

For more details about firmware update over-the-air procedure, see the SARA-R4/N4 series AT Commands Manual [2].

1.13.9 Power saving

1.13.9.1 Guidelines to optimize power consumption

The LTE Cat M1 / NB1 technology is mainly intended for applications that only require a small amount of data exchange

per day (i.e. a few bytes in uplink and downlink per day). Depending on the application type, the battery may be

required to last for a few years. For these reasons, the whole application board should be optimized in terms of current

consumption and should carefully take into account the following aspects:

•

•

•

Enable the low power mode configuration using the AT+UPSV command (for the complete description of the

AT+UPSV command, see the SARA-R4/N4 series AT Commands Manual [2]).

Enable the power saving mode configuration using the AT+CPSMS command (for the complete description of the

AT+CPSMS command, see the SARA-R4/N4 series AT Commands Manual [2]).

• Use the UART interface instead of the USB interface as a serial communication interface, because the current

consumption of the module is ~20 mA higher when the USB interface is enabled.

• Use an application processor with a UART interface working at the same voltage level (1.8 V) as the module. In this

way it is possible to avoid voltage translators, which helps to minimize current leakage.

If the USB interface is implemented in the design, remove the external USB VBUS voltage from the VUSB_DET input

when serial communication is not necessary, letting the module enter the Power Saving Mode defined in 3GPP Rel.13:

the module does not enter the deep sleep power saving mode if the USB interface is enabled.

• Minimize current leakage on the power supply line.

• Optimize the antenna matching, since a mismatched antenna leads to higher current consumption.

• Monitor V_INT level to sense when the module enters power-off mode or deep sleep power saving mode.

• Disconnect the VCC supply source from the module when it is switched off (see 2.2.1.9).

• Disconnect the VCC supply source from the module during deep sleep power saving mode (see 2.2.1.9): using a host

application processor equipped with a RTC, the module can execute a standard PSM procedure and store the NAS

protocol context in non-volatile memory, and then rely on the host application processor for running its RTC and

triggering wake-up upon need23.

23 The use of an external RTC during deep sleep power saving mode is not supported by the “00”, “01” and “x2” product versions

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1.13.9.2 Functionality

When power saving is enabled using the AT+CPSMS command, the module automatically enters the low power deep

sleep mode whenever possible, reducing current consumption (see the section 1.5.1.4 and the SARA-R4/N4 series Data

Sheet [1]).

For the definition and the description of the SARA-R4/N4 series operating modes, including the events forcing transitions

between the different operating modes, see section 1.4.

The SARA-R4/N4 series modules achieve the low power deep sleep mode by powering down all the Hardware

components with the exception of the 32 kHz reference internally generated.

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From the host application point of view, the serial port will not be available during low power deep sleep mode, as

the SARA-R4/N4 series module will act as if it is in Power-Off mode.

1.13.9.3 Timers and network interaction

The SARA-R4/N4 series modules goes in low power deep sleep mode entering in the Power Saving Mode (PSM) defined

in 3GPP Release 13.

Two timers have been specified on the PSM Signaling: the “Periodic Update Timer” and “Active Timer”.

The “Active Timer” is the time defined by the network where the SARA-R4/N4 series module will keep listening for any

active operation, during this time the module is in Active mode.

The “Periodic Update Timer” is the Extended Tracking Area Update (TAU) used by the SARA-R4/N4 series module to

periodically notify the network of its availability.

The SARA-R4/N4 series module requests the PSM by including the “Active Timer” with the desired value in the Attach,

TAU or Routing Area Update (RAU) messages. The “Active Timer” is the time the module listens to the Paging Channel

after having transitioned from connected to active mode. When the “Active Timer” expires, the module enters PSM low

power deep sleep mode.

SARA-R4/N4 series module can also request an extended “Periodic Update Timer” value to remain in PSM low power

deep sleep mode for longer than the original “Periodic Update Timer” broadcasted by the network.

The grant of PSM is a negotiation between SARA-R4/N4 series module and the attached network: the network accepts

PSM by providing the actual value of the “Active Timer” (and “Periodic Update Timer”) to be used in the Attach/TAU/RAU

accept procedure. The maximum duration, including the “Periodic Update Timer”, is about 413 days. The SARA-R4/N4

series module enters PSM low power deep sleep mode only after the “Active Timer” expires.

Current

Connected mode: Data Tx / Rx

PSM low power deep sleep mode

(periodic update timer)

Active mode

(active timer)

Time

Figure 14: Description of the PSM timing

1.13.9.4 Timers and AT interaction

The SARA-R4/N4 series modules go into low power deep sleep mode and enter the Power Saving Mode (PSM) only after

the 6 s “AT Inactivity Timer” expires:

•

If the UART interface is used, when the host application stops sending AT commands for 6 s – the “AT Inactivity Timer”

expiration – then the module enters deep sleep power saving mode according to “Active Timer” expiration.

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•

If the USB interface is enabled, the module does not enter the deep sleep power saving mode.

1.13.9.5 AT commands

The module uses the +CPSMS AT command with its defined parameters to request PSM timers to the network.

See the SARA-R4/N4 series AT Commands Manual [2] for details of the +CPSMS operation and features.

1.13.9.6 Host application

The PSM low power deep sleep mode implementation allows the SARA-R4/N4 series module to help extend the battery

life of the application.

The Host Application should be aware that the SARA-R4/N4 series module is PSM-capable.

The host application needs to sense the V_INT supply output of the module to get the notification when the module

has entered into PSM low power deep sleep mode.

If the host application receives an event that needs to be reported by the SARA-R4/N4 series module interrupting

the PSM low power deep sleep mode, it can be done so by setting the module into Active mode using the appropriate

power-on event (see 1.6.1).

From the host application point of view, the module will look as it is in Power-Off mode.

1.13.9.7 Normal operation

The Host Application can force the SARA-R4/N4 series module to transition from PSM low power deep sleep mode to

Active mode by using the Power-Up procedure specified in section 1.6.1.

Be aware that when the host application transitions from low power deep sleep mode to active mode, it will cause

the SARA-R4/N4 series module to consume the same amount of power as in active mode, thereby shortening the

battery life of the host application.

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2 Design-in

2.1 Overview

For an optimal integration of the SARA-R4/N4 series modules in the final application board, follow the design guidelines

stated in this section.

Every application circuit must be suitably designed to guarantee the correct functionality of the relative interface, but a

number of points require particular attention during the design of the application device.

The following list provides a rank of importance in the application design, starting from the highest relevance:

1. Module antenna connection: ANT and ANT_DET pins.

Antenna circuit directly affects the RF compliance of the device integrating a SARA-R4/N4 series module with

applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the schematic and

layout design.

2. Module supply: VCC and GND pins.

The supply circuit affects the RF compliance of the device integrating a SARA-R4/N4 series module with the applicable

required certification schemes as well as the antenna circuit design. Very carefully follow the suggestions provided

in the relative section 2.2.1 for the schematic and layout design.

3. USB interface: USB_D+, USB_D- and VUSB_DET pins.

Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the suggestions

provided in the relative section 2.6.2 for the schematic and layout design.

4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins.

Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling. Carefully follow the

suggestions provided in relative section 2.5 for schematic and layout design.

5. System functions: RESET_N and PWR_ON pins.

Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully follow the

suggestions provided in relative section 2.3 for schematic and layout design.

6. Other digital interfaces: UART, SPI, SDIO, I2C, I2S, GPIOs and reserved pins.

Accurate design is required to guarantee correct functionality and reduce the risk of digital data frequency harmonics

coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3, 2.6.4, 2.6.5, 2.7, 2.8 and 2.9 for the schematic

and layout design.

7. Other supplies: V_INT generic digital interfaces supply.

Accurate design is required to guarantee correct functionality. Follow the suggestions provided in the corresponding

section 2.2.2 for the schematic and layout design.

It is recommended to follow the specific design guidelines provided by each manufacturer of any external part

selected for the application board integrating the u-blox cellular modules.

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2.2 Supply interfaces

2.2.1 Module supply (VCC)

2.2.1.1 General guidelines for VCC supply circuit selection and design

All the available VCC pins have to be connected to the external supply minimizing the power loss due to series resistance.

GND pins are internally connected. Application design shall connect all the available pads to solid ground on the

application board, since a good (low impedance) connection to external ground can minimize power loss and improve RF

and thermal performance.

SARA-R4/N4 series modules must be sourced through the VCC pins with a suitable DC power supply that should meet the

following prerequisites to comply with the modules’ VCC requirements summarized in Table 6.

The appropriate DC power supply can be selected according to the application requirements (see Figure 15) between the

different possible supply sources types, which most common ones are the following:

Switching regulator

Low Drop-Out (LDO) linear regulator

•

•

• Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery

• Primary (disposable) battery

M ain Supply

Available?

No, port able device

Bat t ery

Li-Ion 3.7 V

Yes, always available

M ain Supply

Volt age > 5V?

No, less t han 5 V

Linear LDO

Regulat or

Figure 15: VCC supply concept selection

Yes, great er t han 5 V

Swit ching St ep-Down

Regulat or

The switching step-down regulator is the typical choice when primary supply source has a nominal voltage much higher

(e.g. greater than 5 V) than the operating supply voltage of SARA-R4/N4 series. The use of switching step-down provides

the best power efficiency for the overall application and minimizes current drawn from the main supply source. See

section 2.2.1.2 for design-in.

The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less or

equal than 5 V). In this case, the typical 90% efficiency of the switching regulator diminishes the benefit of voltage step-

down and no true advantage is gained in input current savings. On the opposite side, linear regulators are not

recommended for high voltage step-down as they dissipate a considerable amount of energy in thermal power. See

section 2.2.1.3 for design-in.

If SARA-R4/N4 series modules are deployed in a mobile unit where no permanent primary supply source is available, then

a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the

usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum

voltage that is above the maximum rating for VCC, and should therefore be avoided. See sections 2.2.1.4, 2.2.1.5, 2.2.1.6

and 2.2.1.7 for specific design-in.

Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger circuit, which is

not included in the modules. The charger circuit needs to be designed to prevent over-voltage on VCC pins, and it should

be selected according to the application requirements. A DC/DC switching charger is the typical choice when the charging

source has a high nominal voltage (e.g. ~12 V), whereas a linear charger is the typical choice when the charging source

has a relatively low nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a

rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a suitable

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charger / regulator with integrated power path management function can be selected to supply the module while

simultaneously and independently charging the battery. See sections 2.2.1.6 and 2.2.1.7 for specific design-in.

An appropriate primary (not rechargeable) battery can be selected taking into account the maximum current specified in

the SARA-R4/N4 series Data Sheet [1] during connected mode, considering that primary cells might have weak power

capability. See section 2.2.1.5 for specific design-in.

The usage of more than one DC supply at the same time should be carefully evaluated: depending on the supply source

characteristics, different DC supply systems can result as mutually exclusive.

The selected regulator or battery must be able to support with adequate margin the highest averaged current

consumption value specified in the SARA-R4/N4 series Data Sheet [1].

The following sections highlight some design aspects for each of the supplies listed above providing application circuit

design-in compliant with the module VCC requirements summarized in Table 6.

2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator

The use of a switching regulator is suggested when the difference from the available supply rail source to the VCC value

is high, since switching regulators provide good efficiency transforming a 12 V or greater voltage supply to the typical 3.8

V value of the VCC supply.

The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites to comply

with the module VCC requirements summarized in Table 6:

• Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the

VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current

consumption occurring during transmissions at the maximum power, as specified in the SARA-R4/N4 series Data

Sheet [1].

Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low

noise) VCC voltage profile.

•

• High switching frequency: for best performance and for smaller applications it is recommended to select a switching

frequency ≥ 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching

regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully

evaluated since this can produce noise in the VCC profile and therefore negatively impact modulation spectrum

performance.

• PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in

connected mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM modes transitions must be avoided

to reduce noise on VCC voltage profile. Switching regulators can be used that are able to switch between low ripple

PWM mode and high ripple PFM mode, provided that the mode transition occurs when the module changes status

from the active mode to connected mode. It is permissible to use a regulator that switches from the PWM mode to

the burst or PFM mode at an appropriate current threshold.

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Figure 16 and the components listed in Table 9 show an example of a high reliability power supply circuit for the SARA-

R412M modules that support 2G radio access technology. This circuit is also suitable for the other SARA-R4/N4 series

modules, where the module VCC input is supplied by a step-down switching regulator capable of delivering the highest

peak / pulse current specified for the 2G use-case, with low output ripple and with fixed switching frequency in PWM

mode operation greater than 1 MHz.

12V

R1

4

VIN

10

5

9

7

6

RUN

BD

VC

RT

PG

BOOST

SW

U1

SYNC

FB

1

2

3

8

R2

R3

C1

C2

C3

C4

C5

GND

11

C6

L1

D1

R4

C7

R5

C8

C9 C10 C11

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

GND

Figure 16: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

Reference

Description

Part Number - Manufacturer

10 µF Capacitor Ceramic X7R 5750 15% 50 V

10 nF Capacitor Ceramic X7R 0402 10% 16 V

680 pF Capacitor Ceramic X7R 0402 10% 16 V

22 pF Capacitor Ceramic C0G 0402 5% 25 V

10 nF Capacitor Ceramic X7R 0402 10% 16 V

470 nF Capacitor Ceramic X7R 0603 10% 25 V

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

Schottky Diode 40 V 3 A

MBRA340T3G - ON Semiconductor

10 µH Inductor 744066100 30% 3.6 A

744066100 - Wurth Electronics

470 kΩ Resistor 0402 5% 0.1 W

15 kΩ Resistor 0402 5% 0.1 W

22 kΩ Resistor 0402 5% 0.1 W

390 kΩ Resistor 0402 1% 0.063 W

100 kΩ Resistor 0402 5% 0.1 W

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Step-Down Regulator MSOP10 3.5 A 2.4 MHz

LT3972IMSE#PBF - Linear Technology

Table 9: Components for high reliability VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

D1

L1

R1

R2

R3

R4

R5

U1

☞☞☞☞

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SARA-R4/N4 series - System Integration Manual

Figure 17 and the components listed in Table 10 show an example of a high reliability power supply circuit for SARA-

R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access technology. In this example,

the module VCC is supplied by a step-down switching regulator capable of delivering the maximum peak / pulse current

specified for the LTE use-case, with low output ripple and with fixed switching frequency in PWM mode operation greater

than 1 MHz.

2

VCC

9

EN

1

VSW

L1

C3

D1

C1

C2

8

PG

U1 BST

10

FB 5

PGND

11

GND

4

R1

R2

C4

C5

3 V8

C6

C7

C8

C9

Figure 17: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using a step-down regulator

Reference

Description

Part Number - Manufacturer

SARA-R40 4M

SARA-R410 M

SARA-N410

51 VCC

52 VCC

5 3 VCC

GND

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

MBR230LSFT1G - ON Semiconductor

SLF7045T-4R7M2R0-PF - TDK

Generic manufacturer

Generic manufacturer

TS30041 - Semtech

10 µF Capacitor Ceramic X7R 50 V

10 nF Capacitor Ceramic X7R 16 V

22 nF Capacitor Ceramic X7R 16 V

22 µF Capacitor Ceramic X5R 25 V

22 µF Capacitor Ceramic X5R 25 V

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

Schottky Diode 30 V 2 A

4.7 µH Inductor 20% 2 A

470 kΩ Resistor 0.1 W

150 kΩ Resistor 0.1 W

Step-Down Regulator 1 A 1 MHz

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

Table 10: High reliability VCC supply circuit components for SARA-R404M /-R410M /-N410, using a step-down regulator

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

12V

C1

C2

C3

C4

C5

C6

C7

C8

C9

D1

L1

R1

R2

U1

☞☞☞☞

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SARA-R4/N4 series - System Integration Manual

Figure 18 and the components listed in Table 11 show an example of a low cost power supply circuit suitable for all the

SARA-R4/N4 series modules, where the module VCC is supplied by a step-down switching regulator capable of delivering

the highest peak / pulse current specified for the 2G use-case, transforming a 12 V supply input.

8

VCC

3

INH

OUT

1

C1

C2

6

2

FSW

U1

FB

SYNC

COM P

5

4

R5

GND

7

L1

D1

R4

C4

C5

R3

C3

R1

R2

C6

C7 C8 C9 C10

Figure 18: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using a step-down regulator

Reference

Description

Part Number - Manufacturer

SARA-R4/ N4

5 1 VCC

52 VCC

53 VCC

GND

22 µF Capacitor Ceramic X5R 1210 10% 25 V

220 nF Capacitor Ceramic X7R 0603 10% 25 V

5.6 nF Capacitor Ceramic X7R 0402 10% 50 V

6.8 nF Capacitor Ceramic X7R 0402 10% 50 V

56 pF Capacitor Ceramic C0G 0402 5% 50 V

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

Schottky Diode 25V 2 A

5.2 µH Inductor 30% 5.28A 22 mΩ

4.7 kΩ Resistor 0402 1% 0.063 W

910 Ω Resistor 0402 1% 0.063 W

82 Ω Resistor 0402 5% 0.063 W

8.2 kΩ Resistor 0402 5% 0.063 W

39 kΩ Resistor 0402 5% 0.063 W

STPS2L25 – STMicroelectronics

MSS1038-522NL – Coilcraft

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

Step-Down Regulator 8-VFQFPN 3 A 1 MHz

L5987TR – ST Microelectronics

Table 11: Suggested components for low cost VCC circuit for SARA-R4/N4 series modules, using a step-down regulator

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

12V

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

L1

R1

R2

R3

R4

R5

U1

☞☞☞☞

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2.2.1.3 Guidelines for VCC supply circuit design using low drop-out linear regulator

The use of a linear regulator is suggested when the difference from the available supply rail source and the VCC value is

low. The linear regulators provide high efficiency when transforming a 5 VDC supply to a voltage value within the module

VCC normal operating range.

The characteristics of the Low Drop-Out (LDO) linear regulator connected to VCC pins should meet the following

prerequisites to comply with the module VCC requirements summarized in Table 6:

• Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a voltage value to

the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum current

consumption occurring during a transmission at the maximum Tx power, as specified in the SARA-R4/N4 series Data

Sheet [1].

• Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction

temperature to the rated range (i.e. check the voltage drop from the maximum input voltage to the minimum output

voltage to evaluate the power dissipation of the regulator).

Figure 19 and the components listed in Table 12 show an example of a high reliability power supply circuit for the SARA-

R412M modules supporting the 2G radio access technology. This example is also suitable for the other SARA-R4/N4 series

modules, where the VCC module supply is provided by an LDO linear regulator capable of delivering the highest peak /

pulse current specified for the 2G use-case, with an appropriate power handling capability. The regulator described in

this example supports a wide input voltage range, and it includes internal circuitry for reverse battery protection, current

limiting, thermal limiting and reverse current protection.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum

limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 20 and Table 13). This

reduces the power on the linear regulator and improves the whole thermal design of the supply circuit.

2

IN

4

OUT

1

SHDN

ADJ

5

U1

GND

3

R1

R2

C2

C3 C4 C5 C6

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

GND

Figure 19: Example of high reliability VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator

Reference

Description

Part Number - Manufacturer

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

Generic manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

9.1 kΩ Resistor 0402 5% 0.1 W

3.9 kΩ Resistor 0402 5% 0.1 W

LDO Linear Regulator ADJ 3.0 A

Generic manufacturer

Generic manufacturer

LT1764AEQ#PBF - Linear Technology

5V

C1

C1

C2

C3

C4

C5

C6

R1

R2

U1

Table 12: Suggested components for high reliability VCC circuit for SARA-R4/N4 series modules, using an LDO regulator

☞☞☞☞

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

Figure 20 and the components listed in Table 13 show an example of a high reliability power supply circuit for SARA-

R404M, SARA-R410M and SARA-N410 modules, which do not support the 2G radio access technology, where the module

UBX-16029218 - R13

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SARA-R4/N4 series - System Integration Manual

VCC is supplied by an LDO linear regulator capable of delivering maximum peak / pulse current specified for LTE use-case,

with suitable power handling capability.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum

limit of the module VCC normal operating range (e.g. ~4.1 V for the VCC, as in the circuits described in Figure 20 and Table

13). This reduces the power on the linear regulator and improves the thermal design of the circuit.

R1

5

EN

ADJ

C3

C4

C5

C6

8

IN

OUT

1

3

R2

R3

C2

U1

GND

4

Figure 20: Example of high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator

SARA-R404M

SARA-R410M

SARA-N410

51 VCC

52 VCC

53 VCC

GND

Part Number - Manufacturer

Generic manufacturer

Generic manufacturer

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

Generic manufacturer

Generic manufacturer

Generic manufacturer

Description

1 µF Capacitor Ceramic X5R 6.3 V

22 µF Capacitor Ceramic X5R 25 V

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

47 kΩ Resistor 0.1 W

41 kΩ Resistor 0.1 W

10 kΩ Resistor 0.1 W

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

LDO Linear Regulator 1.0 A

AP7361 – Diodes Incorporated

Table 13: Components for high reliability VCC supply circuit for SARA-R404M /-R410M /-N410, using an LDO linear regulator

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

Reference

5V

C1

C1

C2

C3

C4

C5

C6

R1

R2

R3

U1

☞☞☞☞

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SARA-R4/N4 series - System Integration Manual

Figure 21 and the components listed in Table 14 show an example of a low cost power supply circuit, where the VCC

module supply is provided by an LDO linear regulator capable of delivering the specified highest peak / pulse current,

with an appropriate power handling capability. The regulator described in this example supports a limited input voltage

range and it includes internal circuitry for current and thermal protection.

It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum

limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 21 and Table 14). This

reduces the power on the linear regulator and improves the whole thermal design of the supply circuit.

2

IN

4

OUT

1

EN

5

ADJ

U1

GND

3

R1

R2

C2

C3 C4 C5 C6

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

GND

Figure 21: Example of low cost VCC supply circuit for SARA-R4/N4 series modules, using an LDO linear regulator

Reference

Description

Part Number - Manufacturer

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

Generic manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

100 nF Capacitor Ceramic X7R 16 V

10 nF Capacitor Ceramic X7R 16 V

GRM155R71C104KA01 - Murata

GRM155R71C103KA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1E150JA01 - Murata

27 kΩ Resistor 0402 5% 0.1 W

4.7 kΩ Resistor 0402 5% 0.1 W

LDO Linear Regulator ADJ 3.0 A

Generic manufacturer

Generic manufacturer

LP38501ATJ-ADJ/NOPB - Texas Instrument

Table 14: Suggested components for low cost VCC supply circuit for SARA-R4/N4 modules, using an LDO linear regulator

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

5V

C1

C1

C2

C3

C4

C5

C6

R1

R2

U1

☞☞☞☞

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SARA-R4/N4 series - System Integration Manual

2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery

Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following prerequisites to comply with

the module VCC requirements summarized in Table 6:

• Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output circuit connected

to the VCC pins must be capable of delivering the maximum current occurring during a transmission at maximum Tx

power, as specified in the SARA-R4/N4 series Data Sheet [1]. The maximum discharge current is not always reported

in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity

in Amp-hours divided by 1 hour.

• DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage

drop below the operating range summarized in Table 6 during transmit bursts.

2.2.1.5 Guidelines for VCC supply circuit design using a primary battery

The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following

prerequisites to comply with the module VCC requirements summarized in Table 6:

• Maximum pulse and DC discharge current: the non-rechargeable battery with its related output circuit connected

to the VCC pins must be capable of delivering the maximum current consumption occurring during a transmission at

maximum Tx power, as specified in SARA-R4/N4 series Data Sheet [1]. The maximum discharge current is not always

reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the

battery capacity in Amp-hours divided by 1 hour.

• DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage

drop below the operating range summarized in Table 6 during transmit bursts.

2.2.1.6 Guidelines for external battery charging circuit

SARA-R4/N4 series modules do not have an on-board charging circuit. Figure 22 provides an example of a battery charger

design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell.

In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features the correct pulse and DC

discharge current capabilities and the appropriate DC series resistance, is directly connected to the VCC supply input of

the module. Battery charging is completely managed by the Battery Charger IC, which from a USB power source (5.0 V

typ.), linearly charges the battery in three phases:

• Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current.

•

Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an

external resistor.

• Constant voltage: when the battery voltage reaches the regulated output voltage, the Battery Charger IC starts to

reduce the current until the charge termination is done. The charging process ends when the charging current

reaches the value configured by an external resistor or when the charging timer reaches the factory set value.

Using a battery pack with an internal NTC resistor, the Battery Charger IC can monitor the battery temperature to protect

the battery from operating under unsafe thermal conditions.

The Battery Charger IC, as linear charger, is more suitable for applications where the charging source has a relatively low

nominal voltage (~5 V), so that a switching charger is suggested for applications where the charging source has a relatively

high nominal voltage (e.g. ~12 V, see section 2.2.1.7 for the specific design-in).

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5V0

USB

Supply

Li-Ion/Li-Polym er

Bat t ery Charger IC

VDD

Vbat

PG

C1

THERM

C2

Li-Ion/Li-Pol

Bat t ery Pack

STAT2

PROG

STA1

Vss

R1

D1

D2

U1

θ

B1

C3

C4

C5

C6

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

GND

Figure 22: Li-Ion (or Li-Polymer) battery charging application circuit

Reference

Description

Li-Ion (or Li-Polymer) battery pack with 470 Ω NTC

1 µF Capacitor Ceramic X7R 16 V

Part Number - Manufacturer

Generic manufacturer

Generic manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150JA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1, D2

Low Capacitance ESD Protection

10 kΩ Resistor 0.1 W

CG0402MLE-18G - Bourns

Generic manufacturer

Single Cell Li-Ion (or Li-Polymer) Battery Charger IC

MCP73833 - Microchip

Table 15: Suggested components for the Li-Ion (or Li-Polymer) battery charging application circuit

B1

C1

C2

C3

C4

C5

C6

R1

U1

☞☞☞☞

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

2.2.1.7 Guidelines for external charging and power path management circuit

Application devices where both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up

battery (e.g. 3.7 V Li-Pol) are available at the same time as a possible supply source, should implement a suitable charger

/ regulator with integrated power path management function to supply the module and the whole device while

simultaneously and independently charging the battery.

Figure 23 reports a simplified block diagram circuit showing the working principle of a charger / regulator with integrated

power path management function. This component allows the system to be powered by a permanent primary supply

source (e.g. ~12 V) using the integrated regulator, which simultaneously and independently recharges the battery (e.g.

3.7 V Li-Pol) that represents the back-up supply source of the system. The power path management feature permits the

battery to supplement the system current requirements when the primary supply source is not available or cannot deliver

the peak system currents.

A power management IC should meet the following prerequisites to comply with the module VCC requirements

summarized in Table 6:

• High efficiency internal step down converter, with characteristics as indicated in section 2.2.1.2

•

• High efficiency switch mode charger with separate power path control

Low internal resistance in the active path Vout – Vbat, typically lower than 50 mΩ

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SARA-R4/N4 series - System Integration Manual

Power pat h management IC

Syst em

12 V

Prim ary

Source

Vin

DC/DC convert er

and bat t er y FET

cont r ol logic

Charge

cont roller

GND

Vout

Vbat

GND

Li-Ion/Li-Pol

Bat t ery Pack

θ

Figure 23: Charger / regulator with integrated power path management circuit block diagram

Figure 24 and the parts listed in Table 16 provide an application circuit example where the MPS MP2617H switching

charger / regulator with integrated power path management function provides the supply to the cellular module. At the

same time it also concurrently and autonomously charges a suitable Li-Ion (or Li-Polymer) battery with the correct pulse

and DC discharge current capabilities and the appropriate DC series resistance according to the rechargeable battery

recommendations described in section 2.2.1.4.

The MP2617H IC constantly monitors the battery voltage and selects whether to use the external main primary supply /

charging source or the battery as supply source for the module, and starts a charging phase accordingly.

The MP2617H IC normally provides a supply voltage to the module regulated from the external main primary source

allowing immediate system operation even under missing or deeply discharged battery: the integrated switching step-

down regulator is capable to provide up to 3 A output current with low output ripple and fixed 1.6 MHz switching

frequency in PWM mode operation. The module load is satisfied in priority, then the integrated switching charger will

take the remaining current to charge the battery.

Additionally, the power path control allows an internal connection from battery to the module with a low series internal

ON resistance (40 mΩ typical), in order to supplement additional power to the module when the current demand

increases over the external main primary source or when this external source is removed.

Battery charging is managed in three phases:

• Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current,

•

set to 10% of the fast-charge current

Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an

external resistor to a value suitable for the application

• Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively

reduced until the charge termination is done. The charging process ends when the charging current reaches the 10%

of the fast-charge current or when the charging timer reaches the value configured by an external capacitor

Using a battery pack with an internal NTC resistor, the MP2617H can monitor the battery temperature to protect the

battery from operating under unsafe thermal conditions.

Several parameters as the charging current, the charging timings, the input current limit, the input voltage limit, the

system output voltage can be easily set according to the specific application requirements, as the actual electrical

characteristics of the battery and the external supply / charging source: suitable resistors or capacitors must be

accordingly connected to the related pins of the IC.

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Prim ary

Source

Li-Ion/Li-Polym er Bat t ery

Charger / Regulat or wit h

Power Pat h M anagm ent

12V

BST

C4

L1

R4

R5

VIN

SW

VLIM

SYS

SYSFB

ENn

BAT

D3

R6

R7

+

C5

Li-Ion/Li-Pol

Bat t ery Pack

C10

C11

C12

C13

θ

NTC

VCC

R3

R1

R2

ILIM

ISET

TM R

U1

C1

C2

AGND

PGND

C3

C6

C7 C8

D1

D2

B1

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

GND

Figure 24: Li-Ion (or Li-Polymer) battery charging and power path management application circuit

Reference

Description

Part Number - Manufacturer

Li-Ion (or Li-Polymer) battery pack with 10 kΩ NTC

Various manufacturer

22 µF Capacitor Ceramic X5R 1210 10% 25 V

GRM32ER61E226KE15 - Murata

C2, C4, C10

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

1 µF Capacitor Ceramic X7R 0603 10% 25 V

GRM188R71E105KA12 - Murata

330 µF Capacitor Tantalum D_SIZE 6.3 V 45 mΩ

T520D337M006ATE045 - KEMET

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E150JA01 - Murata

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

Low Capacitance ESD Protection

CG0402MLE-18G - Bourns

Schottky Diode 40 V 3 A

MBRA340T3G - ON Semiconductor

R1, R3, R5, R7

10 kΩ Resistor 0402 1% 1/16 W

1.05 kΩ Resistor 0402 1% 0.1 W

22 kΩ Resistor 0402 1% 1/16 W

26.5 kΩ Resistor 0402 1% 1/16 W

2.2 µH Inductor 7.4 A 13 mΩ 20%

Generic manufacturer

Generic manufacturer

Generic manufacturer

Generic manufacturer

SRN8040-2R2Y - Bourns

Li-Ion/Li-Polymer Battery DC/DC Charger / Regulator with

integrated Power Path Management function

MP2617H - Monolithic Power Systems (MPS)

Table 16: Suggested components for battery charging and power path management application circuit

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

B1

C1, C6

C3

C5

C7, C12

C8, C13

C11

D1, D2

D3

R2

R4

R6

L1

U1

☞☞☞☞

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2.2.1.8 Guidelines for particular VCC supply circuit design for SARA-R412M

SARA-R412M modules have separate supply inputs over the VCC pins (see Figure 3):

• VCC pins #52 and #53: supply input for the internal RF Power Amplifier, demanding most of the total current drawn

of the module when RF transmission is enabled during a call

• VCC pin #51: supply input for the internal Power Management Unit, Base-Band and Transceiver parts, demanding

minor current

Generally, all the VCC pins are intended to be connected to the same external power supply circuit, but separate supply

sources can be implemented for specific (e.g. battery-powered) applications. The voltage at the VCC pins #52 and #53

can drop to a value lower than the one at the VCC pin #51, keeping the module still switched-on and functional. Figure

25 illustrates a possible application circuit.

L1

D1

St ep-up

Regulat or

SARA-R412M

VIN

SW

51 VCC

C6

SHDNn

GND

C8

C7

R1

R2

FB

U1

+

C1

C2

C3

C4

C5

52 VCC

53 VCC

GND

Li-Ion/Li-Pol

Bat t ery

Figure 25: VCC circuit example with separate supply for SARA-R412M modules

Reference

Description

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

Part Number - Manufacturer

T520B107M006ATE015 – Kemet

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

56 pF Capacitor Ceramic C0G 0402 5% 25 V

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E560JA01 - Murata

GRM1555C1E150JA01 - Murata

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

GRM188R60J106ME47 - Murata

22 µF Capacitor Ceramic X5R 1210 10% 25 V

10 pF Capacitor Ceramic C0G 0402 5% 25 V

Schottky Diode 40 V 1 A

10 µH Inductor 20% 1 A 276 mΩ

1 MΩ Resistor 0402 5% 0.063 W

412 kΩ Resistor 0402 5% 0.063 W

Step-up Regulator 350 mA

GRM32ER61E226KE15 - Murata

GRM1555C1E100JA01 - Murata

SS14 - Vishay General Semiconductor

SRN3015-100M - Bourns Inc.

Generic manufacturer

Generic manufacturer

AP3015 - Diodes Incorporated

Table 17: Examples of components for the VCC circuit with separate supply for SARA-R412M modules

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

C1

C2

C3

C4

C5

C6

C7

C8

D1

L1

R1

R2

U1

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2.2.1.9 Guidelines for removing VCC supply

Removing the VCC power can be useful to minimize the current consumption when the SARA-R4/N4 series modules are

switched off or when the modules are in deep sleep Power Saving Mode.

In applications in which the module is paired to a host application processor equipped with a RTC, the module can execute

standard PSM procedures, store NAS protocol context in non-volatile memory, and rely on the host application processor

to run its RTC and to trigger wake-up upon need. The application processor can disconnect the VCC supply source from

the module and zero out the module’s PSM current.

The VCC supply source can be removed using an appropriate low-leakage load switch or p-channel MOSFET controlled by

the application processor as shown in Figure 26, given that the external switch has provide:

• Very low leakage current (for example, less than 1 µA), to minimize the current consumption

• Very low RDS(ON) series resistance (for example, less than 50 mΩ), to minimize voltage drops

• Adequate maximum Drain current (see the SARA-R4/N4 series Data Sheet [1] for module current consumption

figures)

VCC Supply Source

Applicat ion

Processor

GPIO

GPIO

GPIO

GND

U1

VOUT

CT

GND

T1

VIN

VBIAS

ON

R2

R1

+

C1

C2

C3

C4

C5

SARA-R4/ N4

51 VCC

52 VCC

53 VCC

4 V_INT

15 PWR_ON

GND

Figure 26: Example of application circuit for VCC supply removal

Reference

Description

Part Number - Manufacturer

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1E150JA01 - Murata

47 kΩ Resistor 0402 5% 0.1 W

10 kΩ Resistor 0402 5% 0.1 W

NPN BJT Transistor

RC0402JR-0747KL - Yageo Phycomp

RC0402JR-0710KL - Yageo Phycomp

BC847 - Infineon

Ultra-Low Resistance Load Switch

TPS22967 - Texas Instruments

Table 18: Components for VCC supply removal application circuit

It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-R4/N4 series normal operations:

the VCC supply can be removed only after V_INT goes low, indicating that the module has entered Deep-Sleep Power

Saving Mode or Power-Off Mode.

See the section 2.2.1.10, and in particular Figure 27 / Table 19, for the parts recommended to be provided if the

application device integrates an internal antenna.

C1

C2

C3

C4

C5

R2

T1

U1

R1, R3

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2.2.1.10 Additional guidelines for VCC supply circuit design

To reduce voltage drops, use a low impedance power source. The series resistance of the supply lines (connected to the

modules’ VCC and GND pins) on the application board and battery pack should also be considered and minimized: cabling

and routing must be as short as possible to minimize losses.

Three pins are allocated to VCC supply connection. Several pins are designated for GND connection. It is recommended

to correctly connect all of them to supply the module minimizing series resistance.

To reduce voltage ripple and noise, improving RF performance especially if the application device integrates an internal

antenna, place the following bypass capacitors near the VCC pins:

• 68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata GRM1555C1H680J), to filter

• 15 pF capacitor with Self-Resonant Frequency in the 1800/1900 MHz range (as Murata GRM1555C1H150J), to filter

EMI in the low cellular frequency bands

EMI in the high cellular frequency bands

• 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise from clocks and data

• 100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data

An additional capacitor is recommended to avoid undershoot and overshoot at the start and at the end of RF

transmission:

• 100 µF low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA-R412M supporting 2G

• 10 µF capacitor (or greater), for the other SARA-R4/N4 series modules that do not support 2G

An additional series ferrite bead is recommended for additional RF noise filtering, in particular if the application device

integrates an internal antenna:

Ferrite bead specifically designed for EMI suppression in GHz band (e.g. Murata BLM18EG221SN1), placed as close

as possible to the VCC pins of the module, implementing the circuit described in Figure 27, to filter out EMI in all the

cellular bands

SARA-R4/ N4

VCC

VCC

VCC

51

52

53

FB1

3V8

+

C1

C2

C3

C4

C5

SARA

C1

C2

C3 C4

FB1

Capacit or wit h

SRF ~900 M Hz

Ferrit e Bead

f or GHz noise

Capacit or wit h

SRF ~1900 M Hz

C5

GND

Figure 27: Suggested design to reduce ripple / noise on VCC, highly recommended when using an integrated antenna

Reference

Description

Part Number - Manufacturer

68 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H680JA01 - Murata

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150JA01 - Murata

10 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C103KA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

100 µF Capacitor Tantalum B_SIZE 20% 6.3V 15mΩ

T520B107M006ATE015 – Kemet

10 µF Capacitor Ceramic X5R 0603 20% 6.3 V

GRM188R60J106ME47 - Murata

Chip Ferrite Bead EMI Filter for GHz Band Noise

220 Ω at 100 MHz, 260 Ω at 1 GHz, 2000 mA

BLM18EG221SN1 - Murata

GND plane

VCC line

Table 19: Suggested components to reduce ripple / noise on VCC

The necessity of each part depends on the specific design, but it is recommended to provide all the parts described

in Figure 27 / Table 19 if the application device integrates an internal antenna.

•

C1

C2

C3

C4

C5

FB1

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ESD sensitivity rating of the VCC supply pins is 1 kV (HBM according to JESD22-A114). Higher protection level can be

required if the line is externally accessible on the application board, e.g. if accessible battery connector is directly

connected to the supply pins. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS

CA05P4S14THSG varistor) close to accessible point.

2.2.1.11 Guidelines for VCC supply layout design

Good connection of the module VCC pins with DC supply source is required for correct RF performance. Guidelines are

summarized in the following list:

• All the available VCC pins must be connected to the DC source

• VCC connection must be as wide as possible and as short as possible

• Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be avoided

• VCC connection must be routed through a PCB area separated from RF lines / parts, sensitive analog signals and

sensitive functional units: it is good practice to interpose at least one layer of PCB ground between the VCC track and

other signal routing

• VCC connection must be routed as far as possible from the antenna, in particular if embedded in the application

device: see Figure 28

• Coupling between VCC and digital lines, especially USB, must be avoided.

•

The tank bypass capacitor with low ESR for current spikes smoothing described in section 2.2.1.10 should be placed

close to the VCC pins. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-

DC output and minimize VCC track length. Otherwise consider using separate capacitors for DC-DC converter and

module tank capacitor

The bypass capacitors in the pF range described in Figure 27 and Table 19 should be placed as close as possible to

the VCC pins, where the VCC line narrows close to the module input pins, improving the RF noise rejection in the

band centered on the Self-Resonant Frequency of the pF capacitors. This is highly recommended if the application

device integrates an internal antenna

Since VCC input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted

spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which

case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting

to the SARA-R4/N4 series modules in the worst case

Shielding of switching DC-DC converter circuit, or at least the use of shielded inductors for the switching DC-DC

converter, may be considered since all switching power supplies may potentially generate interfering signals as a

result of high-frequency high-power switching.

If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings are not exceeded,

place the protecting device along the path from the DC source toward the module, preferably closer to the DC source

(otherwise protection function may be compromised)

•

•

•

•

Ant enna

VCC

ANT

SARA

NOT OK

Ant enna

ANT

VCC

SARA

NOT OK

Figure 28: VCC line routing guideline for designs integrating an embedded antenna

Ant enna

SARA

ANT

VCC

OK

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2.2.1.12 Guidelines for grounding layout design

Good connection of the module GND pins with application board solid ground layer is required for correct RF

performance. It significantly reduces EMC issues and provides a thermal heat sink for the module.

• Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad

•

•

•

surrounding VCC pins have one or more dedicated via down to the application board solid ground layer

The VCC supply current flows back to main DC source through GND as ground current: provide adequate return path

with suitable uninterrupted ground plane to main DC source

It is recommended to implement one layer of the application board as ground plane as wide as possible

If the application board is a multilayer PCB, then all the board layers should be filled with GND plane as much as

possible and each GND area should be connected together with complete via stack down to the main ground layer

of the board. Use as many vias as possible to connect the ground planes

• Provide a dense line of vias at the edges of each ground area, in particular along RF and high speed lines

•

If the whole application device is composed by more than one PCB, then it is required to provide a good and solid

ground connection between the GND areas of all the different PCBs

• Good grounding of GND pads also ensures thermal heat sink. This is critical during connection, when the real network

commands the module to transmit at maximum power: correct grounding helps prevent module overheating.

2.2.2 Generic digital interfaces supply output (V_INT)

2.2.2.1 Guidelines for V_INT circuit design

SARA-R4/N4 series modules provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly used

to:

•

Indicate when the module is switched on and it is not in the deep sleep power saving mode (as described in sections

1.6.1, 1.6.2)

• Pull-up SIM detection signal (see section 2.5 for more details)

•

•

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Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. see 2.6.1)

Enable external voltage regulators providing supply for external devices

Do not apply loads which might exceed the maximum available current from V_INT supply (see SARA-R4/N4 series

Data Sheet [1]) as this can cause malfunctions in internal circuitry.

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V_INT can only be used as an output: do not connect any external supply source on V_INT.

ESD sensitivity rating of the V_INT supply pin is 1 kV (HBM according to JESD22-A114). Higher protection level could

be required if the line is externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS

CA05P4S14THSG) close to accessible point.

It is recommended to monitor the V_INT pin to sense the end of the internal switch-off sequence of SARA-R4/N4

series modules: VCC supply can be removed only after V_INT goes low.

It is recommended to provide direct access to the V_INT pin on the application board by means of an accessible test

point directly connected to the V_INT pin.

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2.3 System functions interfaces

2.3.1 Module power-on (PWR_ON)

2.3.1.1 Guidelines for PWR_ON circuit design

SARA-R4/N4 series PWR_ON input is equipped with an internal active pull-up resistor; an external pull-up resistor is not

required and should not be provided.

If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device.

According to EMC/ESD requirements of the application, an additional ESD protection should be provided close to the

accessible point, as described in Figure 29 and Table 20.

ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection

level can be required if the line is externally accessible on the application board, e.g. if an accessible push button is

directly connected to PWR_ON pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS

CA05P4S14THSG varistor) close to the accessible point.

An open drain or open collector output is suitable to drive the PWR_ON input from an application processor, as described

in Figure 29.

PWR_ON input pin should not be driven high by an external device, as it may cause start up issues.

SARA-R4/ N4

SARA-R4/ N4

Applicat ion

Processor

Power-on

push but t on

ESD

TP

15 PW R_ON

TP

15 PW R_ON

Open

Drain

Out put

Figure 29: PWR_ON application circuits using a push button and an open drain output of an application processor

Reference

Description

Remarks

ESD

CT0402S14AHSG - EPCOS

Varistor array for ESD protection

Table 20: Example ESD protection component for the PWR_ON application circuit

It is recommended to provide direct access to the PWR_ON pin on the application board by means of an accessible

test point directly connected to the PWR_ON pin.

2.3.1.2 Guidelines for PWR_ON layout design

The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on and switch off

the SARA-R4/N4 series modules. It is required to ensure that the voltage level is well defined during operation and no

transient noise is coupled on this line, otherwise the module might detect a spurious power-on request.

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2.3.2 Module reset (RESET_N)

2.3.2.1 Guidelines for RESET_N circuit design

SARA-R4/N4 series RESET_N is equipped with an internal pull-up; an external pull-up resistor is not required.

If connecting the RESET_N input to a push button, the pin will be externally accessible on the application device.

According to EMC/ESD requirements of the application, an additional ESD protection device (e.g. the EPCOS

CA05P4S14THSG varistor) should be provided close to accessible point on the line connected to this pin, as described in

Figure 30 and Table 21.

ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). Higher protection level can be

required if the line is externally accessible on the application board, e.g. if an accessible push button is directly

connected to the RESET_N pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG

varistor) close to accessible point.

An open drain output or open collector output is suitable to drive the RESET_N input from an application processor, as

described in Figure 30.

RESET_N input pin should not be driven high by an external device, as it may cause start up issues.

SARA-R4/ N4

SARA-R4/ N4

Applicat ion

Processor

Power-on

push but t on

ESD

TP

18 RESET_N

TP

18 RESET_N

Open

Drain

Out put

Figure 30: RESET_N application circuits using a push button and an open drain output of an application processor

Reference

Description

Remarks

ESD

Varistor for ESD protection

CT0402S14AHSG - EPCOS

Table 21: Example of ESD protection component for the RESET_N application circuits

If the external reset function is not required by the customer application, the RESET_N input pin can be left

unconnected to external components, but it is recommended providing direct access on the application board by

means of an accessible test point directly connected to the RESET_N pin.

2.3.2.2 Guidelines for RESET_N layout design

The RESET_N circuit require careful layout due to the pin function: ensure that the voltage level is well defined during

operation and no transient noise is coupled on this line, otherwise the module might detect a spurious reset request. It

is recommended to keep the connection line to RESET_N pin as short as possible.

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2.4 Antenna interface

SARA-R4/N4 series modules provide an RF interface for connecting the external antenna: the ANT pin represents the RF

input/output for RF signals transmission and reception.

The ANT pin has a nominal characteristic impedance of 50 Ω and must be connected to the physical antenna through a

50 Ω transmission line to allow clean transmission / reception of RF signals.

2.4.1 Antenna RF interface (ANT)

2.4.1.1 General guidelines for antenna selection and design

The antenna is the most critical component to be evaluated. Designers must take care of the antenna from all perspective

at the very start of the design phase when the physical dimensions of the application board are under analysis/decision,

since the RF compliance of the device integrating SARA-R4/N4 series modules with all the applicable required certification

schemes depends on antenna’s radiating performance.

Cellular antennas are typically available as:

•

•

External antennas (e.g. linear monopole):

o External antennas basically do not imply physical restriction to the design of the PCB where the SARA-R4/N4

series module is mounted.

o The radiation performance mainly depends on the antennas. It is required to select antennas with optimal

radiating performance in the operating bands.

o RF cables should be carefully selected to have minimum insertion losses. Additional insertion loss will be

introduced by low quality or long cable. Large insertion loss reduces both transmit and receive radiation

performance.

o A high quality 50 Ω RF connector provides a clean PCB-to-RF-cable transition. It is recommended to strictly follow

the layout and cable termination guidelines provided by the connector manufacturer.

Integrated antennas (e.g. PCB antennas such as patches or ceramic SMT elements):

o

Internal integrated antennas imply physical restriction to the design of the PCB: Integrated antenna excites RF

currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna: its

dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced

down to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that

needs to be radiated, given that the orientation of the ground plane relative to the antenna element must be

considered. As numerical example, the physical restriction to the PCB design can be considered as following:

Frequency = 750 MHz (cid:1) Wavelength = 40 cm (cid:1) Minimum GND plane size = 10 cm

o

o Radiation performance depends on the whole PCB and antenna system design, including product mechanical

design and usage. Antennas should be selected with optimal radiating performance in the operating bands

according to the mechanical specifications of the PCB and the whole product.

It is recommended to select a custom antenna designed by an antennas’ manufacturer if the required ground

plane dimensions are very small (e.g. less than 6.5 cm long and 4 cm wide). The antenna design process should

begin at the start of the whole product design process

It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna

manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and

matching circuitry

o

o Further to the custom PCB and product restrictions, antennas may require tuning to obtain the required

performance for compliance with all the applicable required certification schemes. It is recommended to consult

the antenna manufacturer for the design-in guidelines for antenna matching relative to the custom application

In both of cases, selecting external or internal antennas, these recommendations should be observed:

•

•

•

Select an antenna providing optimal return loss (or VSWR) figure over all the operating frequencies.

Select an antenna providing optimal efficiency figure over all the operating frequencies.

Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency figure) so that

the electromagnetic field radiation intensity do not exceed the regulatory limits specified in some countries (e.g. by

FCC in the United States, as reported in the section 4.2.2).

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2.4.1.2 Guidelines for antenna RF interface design

Guidelines for ANT pin RF connection design

A clean transition between the ANT pad and the application board PCB must be provided, implementing the following

design-in guidelines for the layout of the application PCB close to the ANT pad:

• On a multilayer board, the whole layer stack below the RF connection should be free of digital lines

•

Increase GND keep-out (i.e. clearance, a void area) around the ANT pad, on the top layer of the application PCB, to

at least 250 µm up to adjacent pads metal definition and up to 400 µm on the area below the module, to reduce

parasitic capacitance to ground, as described in the left picture in Figure 31

• Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT pad if the top-layer to buried

layer dielectric thickness is below 200 µm, to reduce parasitic capacitance to ground, as described in the right picture

in Figure 31

GND clearance

on t op layer

around ANT pad

GND clearance

on buried layer very close t o t op layer

below ANT pad

M in.

250 µm

ANT

M in. 40 0 µm

GND

Figure 31: GND keep-out area on top layer around ANT pad and on very close buried layer below ANT pad

Guidelines for RF transmission line design

Any RF transmission line, such as the ones from the ANT pad up to the related antenna connector or up to the related

internal antenna pad, must be designed so that the characteristic impedance is as close as possible to 50 Ω.

RF transmission lines can be designed as a micro strip (consists of a conducting strip separated from a ground plane by a

dielectric material) or a strip line (consists of a flat strip of metal which is sandwiched between two parallel ground planes

within a dielectric material). The micro strip, implemented as a coplanar waveguide, is the most common configuration

for printed circuit board.

Figure 32 and Figure 33 provide two examples of suitable 50 Ω coplanar waveguide designs. The first example of RF

transmission line can be implemented in case of 4-layer PCB stack-up herein described, and the second example of RF

transmission line can be implemented in case of 2-layer PCB stack-up herein described.

50 0 µm

380 µm 50 0 µm

L1 Copper

FR-4 dielect ric

L2 Copper

FR-4 dielect ric

L3 Copper

FR-4 dielect ric

L4 Copper

35 µm

270 µm

35 µm

760 µm

35 µm

270 µm

35 µm

Figure 32: Example of 50 ΩΩΩΩ coplanar waveguide transmission line design for the described 4-layer board layup

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40 0 µm

120 0 µm 40 0 µm

L1 Copper

FR-4 dielect ric

L2 Copper

35 µm

1510 µm

35 µm

Figure 33: Example of 50 ΩΩΩΩ coplanar waveguide transmission line design for the described 2-layer board layup

If the two examples do not match the application PCB stack-up, then the 50 Ω characteristic impedance calculation can

be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation,

or using freeware tools like Avago / Broadcom AppCAD (https://www.broadcom.com/appcad) taking care of the

approximation formulas used by the tools for the impedance computation.

To achieve a 50 Ω characteristic impedance, the width of the transmission line must be chosen depending on:

•

•

•

•

the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 32 and Figure 33)

the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner

closer layer implementing the ground plane (e.g. 270 µm in Figure 32, 1510 µm in Figure 33)

the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 32

and Figure 33)

the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g.

500 µm in Figure 32, 400 µm in Figure 33)

If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the

track width of the micro strip, use the “Coplanar Waveguide” model for the 50 Ω calculation.

Additionally to the 50 Ω impedance, the following guidelines are recommended for transmission lines design:

• Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a

few tenths of a dB,

• Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of component present on the

RF transmission lines, if top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance

to ground,

The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible: avoid abrupt

changes of width and spacing to GND,

•

• Add GND stitching vias around transmission lines, as described in Figure 34,

•

Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer, providing

enough vias on the adjacent metal layer, as described in Figure 34,

• Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive

circuit (as USB),

• Avoid stubs on the transmission lines,

• Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried metal layer,

• Do not route microstrip lines below discrete component or other mechanics placed on top layer

Two examples of a suitable RF circuit design are illustrated in Figure 34, where the antenna detection circuit is not

implemented (if the antenna detection function is required by the application, follow the guidelines for circuit and layout

implementation detailed in section 2.4.2):

•

In the first example shown on the left, the ANT pin is directly connected to an SMA connector by means of a suitable

50 Ω transmission line, designed with the appropriate layout.

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•

SARA-R4/N4 series - System Integration Manual

In the second example shown on the right, the ANT pin is connected to an SMA connector by means of a suitable

50 Ω transmission line, designed with the appropriate layout, with an additional high pass filter to improve the ESD

immunity at the antenna port. (The filter consists of a suitable series capacitor and shunt inductor, for example the

Murata GRM1555C1H150JA01 15 pF capacitor and the Murata LQG15HN39NJ02 39 nH inductor with Self-Resonant

Frequency ~1 GHz.).

SARA m odule

SARA m odule

SM A

connect or

High-pass f ilt er

t o im prove

ESD im m unit y

SM A

connect or

Figure 34: Example of circuit and layout for antenna RF circuits on the application board

Guidelines for RF termination design

The RF termination must provide a characteristic impedance of 50 Ω as well as the RF transmission line up to the RF

termination, to match the characteristic impedance of the ANT port.

However, real antennas do not have a perfect 50 Ω load on all the supported frequency bands. So to reduce as much as

possible any performance degradation due to antenna mismatching, the RF termination must provide optimal return loss

(or VSWR) figures over all the operating frequencies, as summarized in Table 7.

If an external antenna is used, the antenna connector represents the RF termination on the PCB:

• Use suitable a 50 Ω connector providing a clean PCB-to-RF-cable transition.

•

Strictly follow the connector manufacturer’s recommended layout, for example:

o SMA Pin-Through-Hole connectors require a GND keep-out (i.e. clearance, a void area) on all the layers around

the central pin up to the annular pads of the four GND posts, as shown in Figure 34

o U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in the area below the

connector between the GND land pads.

• Cut out the GND layer under the RF connector and close to any buried vias, to remove stray capacitance and thus

keep the RF line at 50 Ω, e.g. the active pad of UFL connector needs to have a GND keep-out (i.e. clearance, a void

area) at least on the first inner layer to reduce parasitic capacitance to ground.

If an integrated antenna is used, the integrated antenna represents the RF terminations. The following guidelines should

be followed:

Frequency = 750 MHz (cid:1) Wavelength = 40 cm (cid:1) Minimum GND plane size = 10 cm

• Use an antenna designed by an antenna manufacturer providing the best possible return loss (or VSWR).

• Provide a ground plane large enough according to the relative integrated antenna requirements. The ground plane

of the application PCB can be reduced down to a minimum size that must be similar to one quarter of wavelength of

the minimum frequency that needs to be radiated. As numerical example,

It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer

regarding correct installation and deployment of the antenna system, including the PCB layout and matching circuitry.

Further to the custom PCB and product restrictions, the antenna may require a tuning to comply with all the

applicable required certification schemes. It is recommended to consult the antenna manufacturer for the design-in

guidelines for the antenna matching relative to the custom application.

•

•

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Additionally, these recommendations regarding the antenna system placement must be followed:

• Do not place the antenna within a closed metal case.

• Do not place the antenna in close vicinity to the end user since the emitted radiation in human tissue is restricted by

regulatory requirements.

• Place the antenna as far as possible from VCC supply line and related parts (refer to Figure 28), from high speed digital

lines (as USB) and from any possible noise source.

• Place the antenna far from sensitive analog systems or employ countermeasures to reduce EMC or EMI issues.

• Be aware of interaction between co-located RF systems since the LTE transmitted power may interact or disturb the

performance of companion systems.

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Examples of antennas

Table 22 lists some examples of possible internal on-board surface-mount antennas.

Manufacturer

Part Number

Product Name

Description

Taoglas

PA.710.A

Warrior

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz

40.0 x 6.0 x 5.0 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2500..2690 MHz

42.0 x 10.0 x 3.0 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2690 MHz

42.0 x 10.0 x 3.0 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz

35.0 x 8.5 x 3.2 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2490..2700 MHz

50.0 x 8.0 x 3.2 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2490..2700 MHz

50.0 x 8.0 x 3.2 mm

GSM / WCDMA / LTE Vertical Mount Antenna

698..960 MHz, 1710..2700 MHz

50.6 x 19.6 x 1.6 mm

GSM / WCDMA / LTE Vertical Mount Antenna

698..960 MHz, 1710..2170 MHz, 2300..2700 MHz

74.0 x 10.6 x 1.6 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1700..2700 MHz

40.0 x 5.0 x 5.0 mm

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1710..2170 MHz, 2500..2700 MHz

37.0 x 5.0 x 5.0 mm

Taoglas

PCS.06.A

Havok

Taoglas

MCS6.A

Antenova

SR4L002

Lucida

Ethertronics

P822601

Ethertronics

P822602

Ethertronics

1002436

TE Connectivity

2118310-1

Molex

1462000001

Cirocomm

DPAN0S07

Table 22: Examples of internal surface-mount antennas

Pulse

W3796

Domino

GSM / WCDMA / LTE SMD Antenna

698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz

42.0 x 10.0 x 3.0 mm

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Table 23 lists some examples of possible internal off-board PCB-type antennas with cable and connector.

Manufacturer

Part Number

Product Name

Description

Taoglas

FXUB63.07.0150C

Taoglas

FXUB66.07.0150C

Maximus

Antenova

SRFL029

Moseni

Antenova

SRFL026

Mitis

Ethertronics

1002289

EAD

FSQS35241-UF-10

SQ7

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz

96.0 x 21.0 mm

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz,

3400..3600 MHz, 4800..6000 MHz

120.2 x 50.4 mm

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz

110.0 x 20.0 mm

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz

110.0 x 20.0 mm

GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL

698..960 MHz, 1710..2700 MHz

140.0 x 75.0 mm

GSM / WCDMA / LTE PCB Antenna with cable and U.FL

690..960 MHz, 1710..2170 MHz, 2500..2700 MHz

110.0 x 21.0 mm

Table 23: Examples of internal antennas with cable and connector

Table 24 lists some examples of possible external antennas.

Manufacturer

Part Number

Product Name

Description

Taoglas

GSA.8827.A.101111

Phoenix

Taoglas

TG.30.8112

Taoglas

MA241.BI.001

Genesis

Laird Tech.

TRA6927M3PW-001

Laird Tech.

CMS69273

Laird Tech.

OC69271-FNM

Pulse Electronics WA700/2700SMA

Table 24: Examples of external antennas

GSM / WCDMA / LTE adhesive-mount antenna with cable and SMA(M)

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz

105 x 30 x 7.7 mm

GSM / WCDMA / LTE swivel dipole antenna with SMA(M)

698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz

148.6 x 49 x 10 mm

GSM / WCDMA / LTE MIMO 2in1 adhesive-mount combination antenna waterproof

IP67 rated with cable and SMA(M)

698..960 MHz, 1710..2170 MHz, 2400..2700 MHz

205.8 x 58 x 12.4 mm

GSM / WCDMA / LTE screw-mount antenna with N-type(F)

698..960 MHz, 1710..2170 MHz, 2300..2700 MHz

83.8 x Ø 36.5 mm

GSM / WCDMA / LTE ceiling-mount antenna with cable and N-type(F)

698..960 MHz, 1575.42 MHz, 1710..2700 MHz

86 x Ø 199 mm

GSM / WCDMA / LTE pole-mount antenna with N-type(M)

698..960 MHz, 1710..2690 MHz

248 x Ø 24.5 mm

GSM / WCDMA / LTE clip-mount MIMO antenna with cables and SMA(M)

698..960 MHz,1710..2700 MHz

149 x 127 x 5.1 mm

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2.4.2 Antenna detection interface (ANT_DET)

2.4.2.1 Guidelines for ANT_DET circuit design

Figure 35 and Table 25 describe the recommended schematic / components for the antenna detection circuit that must

be provided on the application board and for the diagnostic circuit that must be provided on the antenna’s assembly to

achieve antenna detection functionality.

SARA-R4/ N4

C3

Z 0 = 50 Ω

C2

Z 0 = 50 Ω

Z 0 = 50 ohm

ANT

56

L2

J 1

Ant enna Cable

ANT_DET

62

GND

R1

L1

C1

D1

Diagnost ic

Circuit

Radiat ing

Element

C4

L3

R2

Figure 35: Suggested schematic for antenna detection circuit on application PCB and diagnostic circuit on antenna assembly

Applicat ion Board

Ant enna Assembly

Reference

Description

Part Number - Manufacturer

C1

C2

D1

L1

R1

J1

C3

L2

C4

L3

R2

27 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H270J - Murata

33 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H330J - Murata

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

68 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HS68NJ02 - Murata

10 kΩ Resistor 0402 1% 0.063 W

RK73H1ETTP1002F - KOA Speer

SMA Connector 50 Ω Through Hole Jack

SMA6251A1-3GT50G-50 - Amphenol

15 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H150J - Murata

39 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HN39NJ02 - Murata

22 pF Capacitor Ceramic C0G 0402 5% 25 V

GRM1555C1H220J - Murata

68 nH Multilayer Inductor 0402 (SRF ~1 GHz)

LQG15HS68NJ02 - Murata

15 kΩ Resistor for Diagnostics

Various Manufacturers

Table 25: Suggested parts for antenna detection circuit on application PCB and diagnostic circuit on antennas assembly

The antenna detection circuit and diagnostic circuit suggested in Figure 35 and Table 25 are here explained:

• When antenna detection is forced by the +UANTR AT command, the ANT_DET pin generates a DC current measuring

the resistance (R2) from the antenna connector (J1) provided on the application board to GND.

• DC blocking capacitors are needed at the ANT pin (C2) and at the antenna radiating element (C4) to decouple the DC

current generated by the ANT_DET pin.

• Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series at the ANT_DET

pin (L1) and in series at the diagnostic resistor (L3), to avoid a reduction of the RF performance of the system,

improving the RF isolation of the load resistor.

• Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR AT command. It also

acts as an ESD protection.

• Additional components (C1 and D1 in Figure 35) are needed at the ANT_DET pin as ESD protection.

• Additional high pass filter (C3 and L2 in Figure 35) is provided at the ANT pin as ESD immunity improvement

•

The ANT pin must be connected to the antenna connector by means of a transmission line with nominal

characteristics impedance as close as possible to 50 Ω.

The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND

(e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 35, the measured DC resistance is always

at the limits of the measurement range (respectively open or short), and there is no mean to distinguish between a defect

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on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA

antenna).

Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the

measurement and produce invalid results for antenna detection.

☞☞☞☞

It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 kΩ to 30 kΩ to assure

good antenna detection functionality and avoid a reduction of module RF performance. The choke inductor should

exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor.

For example:

Consider an antenna with built-in DC load resistor of 15 kΩ. Using the +UANTR AT command, the module reports the

resistance value evaluated from the antenna connector provided on the application board to GND:

• Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 kΩ to 17 kΩ if a 15 kΩ

diagnostic resistor is used) indicate that the antenna is correctly connected.

• Values close to the measurement range maximum limit (approximately 50 kΩ) or an open-circuit “over range” report

(see the SARA-R4/N4 series AT Commands Manual [2]) means that that the antenna is not connected or the RF cable

is broken.

• Reported values below the measurement range minimum limit (1 kΩ) highlights a short to GND at antenna or along

the RF cable.

• Measurement inside the valid measurement range and outside the expected range may indicate an unclean

connection, a damaged antenna or incorrect value of the antenna load resistor for diagnostics.

• Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna

assembly due to antenna cable length, antenna cable capacity and the used measurement method.

☞☞☞☞

If the antenna detection function is not required by the customer application, the ANT_DET pin can be left not

connected and the ANT pin can be directly connected to the antenna connector by means of a 50 Ω transmission line

as described in Figure 34.

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2.4.2.2 Guidelines for ANT_DET layout design

Figure 36 describes the recommended layout for the antenna detection circuit to be provided on the application board

to achieve antenna detection functionality, implementing the recommended schematic described in the previous Figure

35 and Table 25:

•

The ANT pin must be connected to the antenna connector by means of a 50 Ω transmission line, implementing the

design guidelines described in section 2.4.1 and the recommendations of the SMA connector manufacturer.

• DC blocking capacitor at ANT pin (C2) must be placed in series to the 50 Ω RF line.

•

• Choke inductor in series at the ANT_DET pin (L1) must be placed so that one pad is on the 50 Ω transmission line and

The ANT_DET pin must be connected to the 50 Ω transmission line by means of a sense line.

the other pad represents the start of the sense line to the ANT_DET pin.

The additional components (R1, C1 and D1) on the ANT_DET line must be placed as ESD protection.

The additional high pass filter (C3 and L2) on the ANT line are placed as ESD immunity improvement

•

•

SARA m odule

R1

D1

C1

C3 L2

C2

L1

Figure 36: Suggested layout for antenna detection circuit on application board

J 1

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2.5 SIM interface

2.5.1 Guidelines for SIM circuit design

2.5.1.1 Guidelines for SIM cards, SIM connectors and SIM chips selection

The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical and functional

characteristics of Universal Integrated Circuit Cards (UICC), which contains the Subscriber Identification Module (SIM)

integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the LTE

network.

Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as follows:

• Contact C1 = VCC (Supply)

• Contact C2 = RST (Reset)

• Contact C3 = CLK (Clock)

• Contact C4 = AUX1 (Auxiliary contact)

• Contact C5 = GND (Ground)

• Contact C6 = VPP (Programming supply)

• Contact C7 = I/O (Data input/output)

• Contact C8 = AUX2 (Auxiliary contact)

(cid:1) It must be connected to SIM_CLK

(cid:1) It must be connected to VSIM

(cid:1) It must be connected to SIM_RST

(cid:1) It must be left not connected

(cid:1) It must be connected to GND

(cid:1) It can be left not connected

(cid:1) It must be connected to SIM_IO

(cid:1) It must be left not connected

A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the auxiliary contacts C4

and C8. Only 6 contacts are required and must be connected to the module SIM interface.

Removable SIM cards are suitable for applications requiring a change of SIM card during the product lifetime.

A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or

8+2 positions if two additional pins relative to the normally-open mechanical switch integrated in the SIM connector for

the mechanical card presence detection are provided. Select a SIM connector providing 6+2 or 8+2 positions if the

optional SIM detection feature is required by the custom application, otherwise a connector without integrated

mechanical presence switch can be selected.

Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as:

• Case Pin 8 = UICC Contact C1 = VCC (Supply)

• Case Pin 7 = UICC Contact C2 = RST (Reset)

• Case Pin 6 = UICC Contact C3 = CLK (Clock)

• Case Pin 5 = UICC Contact C4 = AUX1 (Aux.contact)

• Case Pin 1 = UICC Contact C5 = GND (Ground)

• Case Pin 2 = UICC Contact C6 = VPP (Progr. supply)

• Case Pin 3 = UICC Contact C7 = I/O (Data I/O)

• Case Pin 4 = UICC Contact C8 = AUX2 (Aux. contact)

(cid:1) It must be connected to VSIM

(cid:1) It must be connected to SIM_RST

(cid:1) It must be connected to SIM_CLK

(cid:1) It must be left not connected

(cid:1) It must be connected to GND

(cid:1) It can be left not connected

(cid:1) It must be connected to SIM_IO

(cid:1) It must be left not connected

A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other uses, but only 6

contacts are required and must be connected to the module SIM card interface as described above.

Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed.

2.5.1.2 Guidelines for single SIM card connection without detection

A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of SARA-R4/N4 series

modules as described in Figure 37, where the optional SIM detection feature is not implemented.

Follow these guidelines to connect the module to a SIM connector without SIM presence detection:

• Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.

• Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.

• Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.

• Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.

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• Connect the UICC / SIM contact C5 (GND) to ground.

• Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the relative pad of

the SIM connector, to prevent digital noise.

• Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, very close to

each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than

10 - 30 cm from the SIM card holder.

• Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on each externally

accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity rating of the SIM interface pins is

1 kV (HBM). So that, according to EMC/ESD requirements of the custom application, higher protection level can be

required if the lines are externally accessible on the application device.

Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum

allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on data and reset lines).

•

SARA-R4/ N4

VSIM

41

SIM _IO

SIM _CLK

39

38

SIM _RST

40

SIM CARD

HOLDER

VPP (C6)

VCC (C1)

IO (C7)

CLK (C3)

RST (C2)

GND (C5)

J 1

C

5

C

1

C

6

C

2

C

7

C

3

C

8

C

4

SIM Card

Bot t om View

(cont act s side)

C1

C2 C3

C4

C5

D1 D2 D3 D4

Figure 37: Application circuits for the connection to a single removable SIM card, with SIM detection not implemented

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1, D2, D3, D4

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

SIM Card Holder, 6 p, without card presence switch

Various manufacturers, as C707 10M006 136 2 - Amphenol

Table 26: Example of components for the connection to a single removable SIM card, with SIM detection not implemented

C5

J1

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2.5.1.3 Guidelines for single SIM chip connection

A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of the SARA-R4/N4 series

modules as described in Figure 38.

Follow these guidelines to connect the module to a solderable SIM chip without SIM presence detection:

• Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.

• Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.

• Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.

• Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.

• Connect the UICC / SIM contact C5 (GND) to ground.

• Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the relative pad of

the SIM chip, to prevent digital noise.

• Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, to prevent RF

coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM lines.

Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7 ns is the maximum

allowed rise time on clock line, 1.0 µs is the maximum allowed rise time on data and reset lines).

SARA-R4/ N4

VSIM

4 1

SIM _IO

SIM _CLK

39

38

SIM _RST

4 0

•

C5

U1

SIM CHIP

2

8

3

6

7

1

VPP (C6)

VCC (C1)

IO (C7)

CLK (C3)

RST (C2)

GND (C5)

U1

8

7

6

5

C1

C2

C3

C4

C5

C6

C7

C8

1

2

3

4

SIM Chip

Bot t om View

(cont act s side)

C1

C2 C3

C4

C5

Figure 38: Application circuits for the connection to a single solderable SIM chip, with SIM detection not implemented

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

SIM chip (M2M UICC Form Factor)

Various Manufacturers

Table 27: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented

2.5.1.4 Guidelines for single SIM card connection with detection

An application circuit for the connection to a single removable SIM card placed in a SIM card holder is described in Figure

39, where the optional SIM card detection feature is implemented.

Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection:

• Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module.

• Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module.

• Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module.

• Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module.

• Connect the UICC / SIM contact C5 (GND) to ground.

• Connect one pin of the normally-open mechanical switch integrated in the SIM connector (as the SW2 pin in Figure

39) to the GPIO5 input pin, providing a weak pull-down resistor (e.g. 470 kΩ, as R2 in Figure 39).

• Connect the other pin of the normally-open mechanical switch integrated in the SIM connector (SW1 pin in Figure

39) to V_INT 1.8 V supply output by means of a strong pull-up resistor (e.g. 1 kΩ, as R1 in Figure 39)

• Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related

pad of the SIM connector, to prevent digital noise.

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• Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line (VSIM, SIM_CLK,

SIM_IO, SIM_RST), very close to each related pad of the SIM connector, to prevent RF coupling especially in case the

RF antenna is placed closer than 10 - 30 cm from the SIM card holder.

• Provide a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each

externally accessible SIM line, close to each related pad of the SIM connector. The ESD sensitivity rating of SIM

interface pins is 1 kV (HBM according to JESD22-A114), so that, according to the EMC/ESD requirements of the custom

application, higher protection level can be required if the lines are externally accessible.

Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface (18.7 ns

= maximum rise time on SIM_CLK, 1.0 µs = maximum rise time on SIM_IO and SIM_RST).

•

SARA-R4/ N4

TP

V_INT

4

GPIO5

42

VSIM

41

SIM _IO

SIM _CLK

SIM _RST

39

38

40

R1

R2

SIM CARD

HOLDER

SW 1

SW 2

VPP (C6)

VCC (C1)

IO (C7)

CLK (C3)

RST (C2)

GND (C5)

J 1

C

5

C

1

C

6

C

2

C

7

C

3

C

8

C

4

SIM Card

Bot t om View

(cont act s side)

C1

C2 C3

C4

C5

D1 D2 D3 D4 D5 D6

Figure 39: Application circuit for the connection to a single removable SIM card, with SIM detection implemented

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

47 pF Capacitor Ceramic C0G 0402 5% 50 V

GRM1555C1H470JA01 - Murata

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R71C104KA01 - Murata

D1 – D6

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

1 kΩ Resistor 0402 5% 0.1 W

470 kΩ Resistor 0402 5% 0.1 W

RC0402JR-071KL - Yageo Phycomp

RC0402JR-07470KL- Yageo Phycomp

SIM Card Holder

6 + 2 positions, with card presence switch

Various Manufacturers,

CCM03-3013LFT R102 - C&K Components

Table 28: Example of components for the connection to a single removable SIM card, with SIM detection implemented

C5

R1

R2

J1

2.5.2 Guidelines for SIM layout design

The layout of the SIM card interface lines (VSIM, SIM_CLK, SIM_IO, SIM_RST may be critical if the SIM card is placed far

away from the SARA-R4/N4 series modules or in close proximity to the RF antenna: these two cases should be avoided

or at least mitigated as described below.

In the first case, the long connection can cause the radiation of some harmonics of the digital data frequency as any other

digital interface. It is recommended to keep the traces short and avoid coupling with RF line or sensitive analog inputs.

In the second case, the same harmonics can be picked up and create self-interference that can reduce the sensitivity of

LTE receiver channels whose carrier frequency is coincidental with harmonic frequencies. It is strongly recommended to

place the RF bypass capacitors suggested in Figure 37 near the SIM connector.

In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges. Add adequate

ESD protection as suggested to protect module SIM pins near the SIM connector.

Limit capacitance and series resistance on each SIM signal to match the SIM specifications. The connections should always

be kept as short as possible.

Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some harmonics of the

digital data frequency.

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2.6 Data communication interfaces

2.6.1 UART interface

2.6.1.1 Guidelines for UART circuit design

Providing the full RS-232 functionality (using the complete V.24 link)24

If RS-232 compatible signal levels are needed, two different external voltage translators can be used to provide full RS-

232 (9 lines) functionality: e.g. using the Texas Instruments SN74AVC8T245PW for the translation from 1.8 V to 3.3 V, and

the Maxim MAX3237E for the translation from 3.3 V to RS-232 compatible signal level.

If a 1.8 V Application Processor (DTE) is used and complete RS-232 functionality is required, then the complete 1.8 V UART

of the module (DCE) should be connected to a 1.8 V DTE, as in Figure 40.

Applicat ion Processor

(1.8 V DTE)

SARA-R4/ N4

(1.8V DCE)

Figure 40: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART of the module (DCE) by

means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage

translators on the module side, as described in Figure 41.

Applicat ion Processor

(3.0 V DTE)

3V0

C1

Unidirect ional

Volt age Translat or

1V8

VCCB

4 V_INT

SARA-R4/ N4

(1.8V DCE)

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

VCC

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

0Ω

0Ω

0Ω

0Ω

TP

TP

TP

TP

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

3V0

C3

U1

Unidirect ional

Volt age Translat or

1V8

C4

VCCA

DIR1

DIR3

A1

A2

A3

A4

DIR2

DIR4

VCCA

DIR1

A1

A2

A3

A4

DIR2

DIR3

DIR4

U2

B1

B2

B3

B4

OE

GND

VCCB

B1

B2

B3

B4

OE

GND

TP

C2

0 Ω

0 Ω

0 Ω

0 Ω

TP

TP

TP

TP

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

Figure 41: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

U1, U2

Unidirectional Voltage Translator

SN74AVC4T77425 - Texas Instruments

Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)

Providing the TXD, RXD, RTS, CTS and DTR lines only 26

24 Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B-00 product versions, but the RTS input must be set low to use the UART on ‘00’ and ‘01’

versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

25 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply

26 Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B-00 product versions, but the RTS input must be set low to use the UART on ‘00’ and ‘01’

versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

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If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available:

Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD

•

If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim MAX3237E and Texas

Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the translation from 1.8 V to 3.3 V, while

the Maxim chip provides the translation from 3.3 V to RS-232 compatible signal level.

Figure 42 describes the circuit that should be implemented as if a 1.8 V Application Processor (DTE) is used, given that

the DTE will behave correctly regardless of the DSR input setting.

Applicat ion Processor

(1.8V DTE)

SARA-R4/ N4

(1.8V DCE)

Figure 42: UART interface application circuit with partial V.24 link (6-wire) in the DTE/DCE serial communication (1.8 V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module

(DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the

voltage translators on the module side, as described in Figure 43, given that the DTE will behave correctly regardless of

the DSR input setting.

Applicat ion Processor

(3.0 V DTE)

3V0

C1

Unidirect ional

Volt age Translat or

1V8

VCCB

4 V_INT

SARA-R4/ N4

(1.8 V DCE)

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

V CC

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

0 Ω

0 Ω

0 Ω

0 Ω

TP

TP

TP

TP

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

VCCA

DIR1

DIR3

A1

A2

A3

A4

DIR2

DIR4

U1

A1

A2

U2

B1

B2

B3

B4

OE

GND

B1

B2

OE

GND

C2

TP

TP

TP

TP

0 Ω

0 Ω

0 Ω

0 Ω

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

3V0

Unidirect ional

Volt age Translat or

1V8

C3

VCCA

VCCB

DIR1

DIR2

C4

Figure 43: UART interface application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE)

Reference

Description

Part Number - Manufacturer

C1, C2, C3, C4

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

U1

U2

Unidirectional Voltage Translator

Unidirectional Voltage Translator

SN74AVC4T77427 - Texas Instruments

SN74AVC2T24527 - Texas Instruments

Table 30: UART application circuit components with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE)

Providing the TXD, RXD, RTS and CTS lines only 28

If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:

27 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply

28 Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B-00 product versions, but the RTS input must be set low to use the UART on ‘00’ and ‘01’

versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

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• Connect the module DTR input to GND using a 0 Ω series resistor, since it may be useful to set DTR active if not

specifically handled, in particular to have URCs presented over the UART interface (see the SARA-R4/N4 series AT

Commands Manual [1] for the &D, S0, +CNMI AT commands)

Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD

•

If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip

translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor is used, the

circuit should be implemented as described in Figure 44.

Applicat ion Processor

(1.8V DTE)

SARA-R4/ N4

(1.8V DCE)

Figure 44: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module

(DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the

voltage translators on the module side, as in Figure 45.

Applicat ion Processor

(3.0 V DTE)

SARA-R4/ N4

(1.8V DCE)

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

VCC

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

0Ω

0Ω

0Ω

0Ω

TP

TP

TP

TP

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

Unidirect ional

Volt age Translat or

1V8

3V0

C1

VCCB

B1

B2

B3

B4

OE

GND

VCCA

DIR1

DIR3

A1

A2

A3

A4

DIR2

DIR4

U1

TP

4 V_INT

C2

0Ω

0Ω

T P

T P

12 TXD

13 RXD

10 RTS

11 CTS

0Ω

T P

T P

9 DTR

6 DSR

7 RI

8 DCD

GND

Figure 45: UART interface application circuit with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)

Reference

Description

Part Number - Manufacturer

C1, C2

U1

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

Unidirectional Voltage Translator

SN74AVC4T77429 - Texas Instruments

Table 31: UART application circuit components with a partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)

29 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply

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Providing the TXD and RXD lines only 30

If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not

available, then:

• Connect the module RTS input line to GND or to the CTS output line of the module, since the module requires RTS

active (low electrical level) if HW flow-control is enabled (AT&K3, which is the default setting)

• Connect the module DTR input line to GND using a 0 Ω series resistor, because it is useful to set DTR active if not

specifically handled, in particular to have URCs presented over the UART interface (see SARA-R4/N4 series AT

Commands Manual [1], &D, S0, +CNMI AT commands)

Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD

•

If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip

translates voltage levels from 1.8 V (module side) to the RS-232 standard.

If a 1.8 V Application Processor (DTE) is used, the circuit that should be implemented as in Figure 46.

Applicat ion Processor

(1.8V DTE)

SARA-R4/ N4

(1.8V DCE)

Figure 46: UART interface application circuit with a 3-wire link in the DTE/DCE serial communication (1.8V DTE)

If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module

(DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the

voltage translators on the module side, as in Figure 47.

Applicat ion Processor

(3.0 V DTE)

SARA-R4/ N4

(1.8 V DCE)

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

VCC

TxD

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

Unidirect ional

Volt age Translat or

VCCA

VCCB

3V0

C1

DIR1

A1

A2

DIR2

U1

B1

B2

OE

GND

0 Ω

0 Ω

0 Ω

TP

TP

TP

TP

12 TXD

13 RXD

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

1V8

TP

C2

0 Ω

0 Ω

TP

TP

4 V_INT

12 TXD

13 RXD

0 Ω

TP

TP

10 RTS

11 CTS

9 DTR

6 DSR

7 RI

8 DCD

GND

Figure 47: UART interface application circuit with a partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)

Reference

Description

Part Number - Manufacturer

C1, C2

U1

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

Unidirectional Voltage Translator

SN74AVC2T24531 - Texas Instruments

Table 32: UART application circuit components with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)

30 Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B-00 product versions, but the RTS input must be set low to use the UART on ‘00’ and ‘01’

versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

31 Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before V_INT 1.8 V supply

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Additional considerations

If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the corresponding

1.8 V input of the module (DCE) can be implemented as an alternative low-cost solution, by means of an appropriate

voltage divider. Consider the value of the pull-down / pull-up integrated at the input of the module (DCE) for the correct

selection of the voltage divider resistance values. Make sure that any DTE signal connected to the module is tri-stated or

set low when the module is in power-down mode and during the module power-on sequence (at least until the activation

of the V_INT supply output of the module), to avoid latch-up of circuits and allow a clean boot of the module (see the

remark below).

Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding 3.0 V input of the

Application Processor (DTE) can be implemented by means of an appropriate low-cost non-inverting buffer with open

drain output. The non-inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider

the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for the

appropriate selection of the resistance value for the external pull-up biased by the application processor supply rail.

The TXD data input line has an internal active pull-down enabled on the “00” and “02” product versions, and an

internal active pull-up enabled on the “01” product version.

Do not apply voltage to any UART interface pin before the switch-on of the UART supply source (V_INT), to avoid

latch-up of circuits and allow a clean boot of the module. If the external signals connected to the cellular module

cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or

TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on.

ESD sensitivity rating of the UART interface pins is 1 kV (Human Body Model according to JESD22-A114). Higher

protection levels could be required if the lines are externally accessible and it can be achieved by mounting an ESD

protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points.

2.6.1.2 Guidelines for UART layout design

The UART serial interface requires the same consideration regarding electro-magnetic interference as any other digital

interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the

radiation of some harmonics of the digital data frequency.

☞☞☞☞

☞☞☞☞

☞☞☞☞

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2.6.2 USB interface

2.6.2.1 Guidelines for USB circuit design

The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-ended mode for full

speed signaling handshake, as well as in differential mode for high speed signaling and data transfer.

USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.0

specification [4] are part of the module USB pins driver and do not need to be externally provided.

The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the SARA-R4/N4

series Data Sheet [1]). Neither the USB interface nor the whole module is supplied by the VUSB_DET input: the VUSB_DET

senses the USB supply voltage and absorbs few microamperes.

Routing the USB pins to a connector, they will be externally accessible on the application device. According to EMC/ESD

requirements of the application, an additional ESD protection device with very low capacitance should be provided close

to accessible point on the line connected to this pin, as described in Figure 48 and Table 33.

☞☞☞☞

The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher

protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low

capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on

the lines connected to these pins, close to accessible points.

The USB pins of the modules can be directly connected to the USB host application processor without additional ESD

protections if they are not externally accessible or according to EMC/ESD requirements.

USB DEVICE

CONNECTOR

SARA-R4/ N4

USB HOST

PROCESSOR

SARA-R4/ N4

17 VUSB_DET

VBUS

17 VUSB_DET

VBUS

D+

D-

GND

D1 D2

D3

C1

29 USB_D+

28 USB_D-

GND

D+

D-

GND

0Ω Test -Point

0Ω Test -Point

0Ω Test -Point

29 USB_D+

28 USB_D-

C1

GND

Figure 48: USB Interface application circuits

Reference

Description

Part Number - Manufacturer

C1

100 nF Capacitor Ceramic X7R 0402 10% 16 V

GRM155R61A104KA01 - Murata

D1, D2, D3

Very Low Capacitance ESD Protection

PESD0402-140 - Tyco Electronics

Table 33: Components for USB application circuits

☞☞☞☞

☞☞☞☞

If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external USB VBUS

supply voltage needs to be removed from the VUSB_DET input of the module to let it enter the Power Saving Mode

defined in 3GPP Rel.13.

If the USB interface pins are not used, they can be left unconnected on the application board, but it is strongly

recommended to provide accessible test points directly connected to the USB interface pins (VUSB_DET, USB_D+,

USB_D-).

2.6.2.2 Guidelines for USB layout design

The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to

480 Mb/s) supported by the USB serial interface.

The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0

specification [4]. The most important parameter is the differential characteristic impedance applicable for the odd-mode

electromagnetic field, which should be as close as possible to 90 Ω differential. Signal integrity may be degraded if PCB

layout is not optimal, especially when the USB signaling lines are very long.

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Use the following general routing guidelines to minimize signal quality problems:

• Route USB_D+ / USB_D- lines as a differential pair

• Route USB_D+ / USB_D- lines as short as possible

•

•

• Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-

Ensure the differential characteristic impedance (Z0) is as close as possible to 90 Ω

Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30 Ω

strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area

Figure 49 and Figure 50 provide two examples of coplanar waveguide designs with differential characteristic impedance

close to 90 Ω and common mode characteristic impedance close to 30 Ω. The first transmission line can be implemented

in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB

stack-up herein described.

40 0 µm

350 µm

40 0 µm

350 µm 40 0 µm

Figure 49: Example of USB line design, with Z0 close to 90 ΩΩΩΩ and ZCM close to 30 ΩΩΩΩ, for the described 4-layer board layup

410 µm

740 µm

410 µm

740 µm 410 µm

L1 Copper

FR-4 dielect ric

L2 Copper

FR-4 dielect ric

L3 Copper

FR-4 dielect ric

L4 Copper

L1 Copper

FR-4 dielect ric

L2 Copper

35 µm

270 µm

35 µm

760 µm

35 µm

270 µm

35 µm

35 µm

1510 µm

35 µm

Figure 50: Example of USB line design, with Z0 close to 90 ΩΩΩΩ and ZCM close to 30 ΩΩΩΩ, for the described 2-layer board layup

The SPI interface is not supported by “00”, “01”, “02” and “52” product versions: the SPI interface pins should not be

driven by any external device.

2.6.3 SPI interface

2.6.3.1 Guidelines for SPI circuit design

2.6.4 SDIO interface

2.6.4.1 Guidelines for SDIO circuit design

☞☞☞☞

☞☞☞☞

The SDIO interface is not supported by “00”, “01”, “02” and “52” product versions: the SDIO interface pins should

not be driven by any external device.

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2.6.5 DDC (I2C) interface

2.6.5.1 Guidelines for DDC (I2C) circuit design

DDC (I2C) interface is not supported by “00” and “01” product versions: the DDC (I2C) interface pins should not be

driven by any external device.

The DDC I2C-bus master interface can be used to communicate with u-blox GNSS receivers and other external I2C-bus

slaves as an audio codec.

The SDA and SCL pins of the module are open drain output as per I2C bus specifications [9], and they have internal pull-

up resistors to the V_INT 1.8 V supply rail of the module, so there is no need of additional pull-up resistors on the external

application board.

Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 µs is the maximum

allowed rise time on the SCL and SDA lines): route connections as short as possible.

ESD sensitivity rating of the DDC (I2C) pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection

level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection

(e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.

If the pins are not used as DDC bus interface, they can be left unconnected.

☞☞☞☞

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☞☞☞☞

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•

•

•

R1

U1

SARA-R4/N4 series - System Integration Manual

Connection with u-blox 1.8 V GNSS receivers

Figure 51 shows an application circuit for connecting the cellular module to a u-blox 1.8 V GNSS receiver:

The SDA and SCL pins of the cellular module are directly connected to the related pins of the u-blox 1.8 V GNSS

receiver. External pull-up resistors are not needed, as they are already integrated in the cellular module.

The GPIO2 pin is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 1.8 V GNSS

receiver providing the “GNSS supply enable” function. A pull-down resistor is provided to avoid a switch on of the

positioning receiver when the cellular module is switched off or in the reset state.

The GPIO3 pin is connected to the TXD1 pin of the u-blox 1.8 V GNSS receiver providing the additional “GNSS Tx data

ready” function.

u-blox GNSS

1.8 V receiver

1V8

GNSS LDO

Regulat or

VM AIN

SARA-R4/ N4

(except ’0 0’,’0 1’ versions)

VCC

SDA2

SCL2

TxD1

C1

OUT

IN

SHDN

GND

U1

GNSS supply enabled

23 GPIO2

R1

26

27

SDA

SCL

GNSS dat a ready

24

GPIO3

Figure 51: Application circuit for connecting SARA-R4/N4 series modules to u-blox 1.8 V GNSS receivers

Reference

Description

47 kΩ Resistor 0402 5% 0.1 W

Part Number - Manufacturer

RC0402JR-0747KL - Yageo Phycomp

Voltage Regulator for GNSS receiver

See GNSS receiver Hardware Integration Manual

Table 34: Components for connecting SARA-R4/N4 series modules to u-blox 1.8 V GNSS receivers

For additional guidelines regarding the design of applications with u-blox 1.8 V GNSS receivers, see the Hardware

Integration Manual of the u-blox GNSS receivers.

Connection with u-blox 3.0 V GNSS receivers

Figure 52 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS receiver:

•

• As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the related I2C pins of

the u-blox 3.0 V GNSS receiver must be provided using a suitable I2C-bus Bidirectional Voltage Translator (e.g. TI

TCA9406, which additionally provides the partial power down feature so that the GNSS 3.0 V supply can be ramped

up before the V_INT 1.8 V cellular supply). External pull-up resistors are not needed on the cellular module side, as

they are already integrated in the cellular module.

The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 3.0 V GNSS

receiver providing the “GNSS supply enable” function. A pull-down resistor is provided to avoid a switch on of the

positioning receiver when the cellular module is switched off or in the reset state.

The GPIO3 pin is connected to the TXD1 pin of the u-blox 3.0 V GNSS receiver providing the additional “GNSS Tx data

ready” function, using a suitable Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which

additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up before

the V_INT 1.8 V cellular supply.

•

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u-blox GNSS

3.0 V receiver

SARA-R4/ N4

(except ‘0 0 ’,’0 1’ versions)

V CC

3V0

VM AIN

LDO Regulat or

OUT

IN

C1

GND

SHDNn

GNSS supply enabled

23 GPIO2

C2

R1

R2

U1

R3

I2C-bus Bidirect ional

Volt age Translat or

1V8

VCCB

VCCA

OE

C3

SDA_B

SDA_A

SCL_B

SCL_A

GND

4 V_INT

26 SDA

27 SCL

3V0

C4

Unidirect ional

Volt age Translat or

1V8

VCCA

DIR1

VCCB

B1

B2

DIR2

GND

OEn

U2

A1

A2

U3

C5

GNSS dat a ready

24 GPIO3

SDA2

SCL2

TxD1

Figure 52: Application circuit for connecting SARA-R4/N4 series modules to u-blox 3.0 V GNSS receivers

Reference

Description

4.7 kΩ Resistor 0402 5% 0.1 W

47 kΩ Resistor 0402 5% 0.1 W

Part Number - Manufacturer

RC0402JR-074K7L - Yageo Phycomp

RC0402JR-0747KL - Yageo Phycomp

C2, C3, C4, C5

100 nF Capacitor Ceramic X5R 0402 10% 10V

GRM155R71C104KA01 - Murata

Voltage Regulator for GNSS receiver and related output

bypass capacitor

See GNSS receiver Hardware Integration Manual

I2C-bus Bidirectional Voltage Translator

TCA9406DCUR - Texas Instruments

Generic Unidirectional Voltage Translator

SN74AVC2T245 - Texas Instruments

R1, R2

R3

U1, C1

U2

U3

Table 35: Components for connecting SARA-R4/N4 series modules to u-blox 3.0 V GNSS receivers

For additional guidelines regarding the design of applications with u-blox 3.0 V GNSS receivers see the Hardware

Integration Manual of the u-blox GNSS receivers.

2.6.5.2 Guidelines for DDC (I2C) layout design

The DDC (I2C) serial interface requires the same consideration regarding electro-magnetic interference as any other digital

interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the

radiation of some harmonics of the digital data frequency.

2.7 Audio

2.7.1 Guidelines for Audio circuit design

☞☞☞☞

Audio is not supported by “00”, “01”, “02” and “52” product versions: the I2S interface pins should not be driven by

any external device.

2.8 General Purpose Input/Output

2.8.1 Guidelines for GPIO circuit design

A typical usage of SARA-R4/N4 series modules’ GPIOs can be the following:

• Network indication provided over GPIO1 pin (see Figure 53 / Table 36 below)

• GNSS supply enable function provided by the GPIO2 pin (see section 2.6.5)

• GNSS Tx data ready function provided by the GPIO3 pin (see section 2.6.5)

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• Module operating status indication provided by a GPIO pin (see section 1.6.1)

•

SIM card detection provided over GPIO5 pin (see Figure 39 / Table 28 in section 2.5)

SARA-R4/ N4

GPIO1

16

Net work Indicat or

R1

3V8

DL1

R3

T1

R2

Figure 53: Application circuit for network indication provided over GPIO1

Reference

Description

Part Number - Manufacturer

10 kΩ Resistor 0402 5% 0.1 W

47 kΩ Resistor 0402 5% 0.1 W

820 Ω Resistor 0402 5% 0.1 W

LED Red SMT 0603

NPN BJT Transistor

Various manufacturers

Various manufacturers

Various manufacturers

BC847 - Infineon

LTST-C190KRKT - Lite-on Technology Corporation

Table 36: Components for network indication application circuit

Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board in

series to the GPIO of SARA-R4/N4 series modules.

Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (V_INT), to avoid latch-up

of circuits and allow a clean module boot. If the external signals connected to the module cannot be tri-stated or set

low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, TS5A63157) between the two-circuit

connections and set to high impedance before V_INT switch-on.

ESD sensitivity rating of the GPIO pins

(Human Body Model according to JESD22-A114).

Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an

ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.

is 1 kV

If the GPIO pins are not used, they can be left unconnected on the application board.

☞☞☞☞

2.8.2 Guidelines for general purpose input/output layout design

The general purpose inputs / outputs pins are generally not critical for layout.

R1

R2

R3

DL1

T1

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2.9 Reserved pins (RSVD)

SARA-R4/N4 series modules have pins reserved for future use, marked as RSVD.

All the RSVD pins are to be left unconnected on the application board, except for the RSVD pin number 33 that can be

externally connected to ground.

2.10 Module placement

An optimized placement allows a minimum RF line’s length and closer path from DC source for VCC.

Make sure that the module, analog parts and RF circuits are clearly separated from any possible source of radiated energy.

In particular, digital circuits can radiate digital frequency harmonics, which can produce Electro-Magnetic Interference

that affects the module, analog parts and RF circuits’ performance. Implement suitable countermeasures to avoid any

possible Electro-Magnetic Compatibility issue.

Make sure that the module, RF and analog parts / circuits, and high speed digital circuits are clearly separated from any

sensitive part / circuit which may be affected by Electro-Magnetic Interference, or employ countermeasures to avoid any

possible Electro-Magnetic Compatibility issue.

Make sure that the module is placed in order to keep the antenna as far as possible from VCC supply line and related

parts (refer to Figure 28), from high speed digital lines (as USB) and from any possible noise source.

Provide enough clearance between the module and any external part: clearance of at least 0.4 mm per side is

recommended to let suitable mounting of the parts.

☞☞☞☞

The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of

the application base-board below the SARA-R4/N4 series modules: avoid placing temperature sensitive devices close

to the module.

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2.11 Module footprint and paste mask

Figure 54 and Table 37 describe the suggested footprint (i.e. copper mask) and paste mask layout for SARA modules: the

proposed land pattern layout reflects the modules’ pins layout, while the proposed stencil apertures layout is slightly

different (see the F’’, H’’, I’’, J’’, O’’ parameters compared to the F’, H’, I’, J’, O’ ones).

The Non Solder resist Mask Defined (NSMD) pad type is recommended over the Solder resist Mask Defined (SMD) pad

type, as it implements the solder resist mask opening 50 µm larger per side than the corresponding copper pad.

The recommended thickness of the stencil for the soldering paste is 150 µm, according to application production process

requirements.

Pin 1

E

G

H’

J ’

ANT pin

Pin 1

E

G

H’’

J ’’

ANT pin

E

B

B

I’’

D

E

I’

D

K

M 1

M 1

M 2

O’

O’

G

J ’

H’

A

St encil: 150

µm

O’’

O’’

G

H’’

A

J ’’

D

K

F’’

L

N

L

N

Figure 54: SARA-R4/N4 series modules suggested footprint and paste mask (application board top view)

Parameter

Parameter

Parameter

F’

L

G

H’

H’’

I’

I’’

J’

J’’

Value

26.0 mm

16.0 mm

3.00 mm

2.00 mm

2.50 mm

1.05 mm

1.00 mm

D

F’’

L

Value

2.75 mm

2.75 mm

1.80 mm

3.60 mm

2.10 mm

1.10 mm

1.05 mm

Value

1.10 mm

0.80 mm

0.75 mm

1.50 mm

1.55 mm

0.30 mm

0.35 mm

K

L

M1

M2

N

O’

O’’

Table 37: SARA-R4/N4 series modules suggested footprint and paste mask dimensions

These are recommendations only and not specifications. The exact copper, solder and paste mask geometries,

distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g.

soldering etc.) implemented.

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K

M 1

M 1

M 2

K

F’

A

B

C

D

E

F’

F’’

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SARA-R4/N4 series - System Integration Manual

2.12 Thermal guidelines

☞☞☞☞

The module operating temperature range is specified in the SARA-R4/N4 series Data Sheet [1].

The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data

upload in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power

amplifier is driven to higher output RF power. This scenario is not often encountered in real networks (for example, see

the Terminal Tx Power distribution for WCDMA, taken from operation on a live network, described in the GSMA TS.09

Battery Life Measurement and Current Consumption Technique [10]); however the application should be correctly

designed to cope with it.

During transmission at maximum RF power the SARA-R4/N4 series modules generate thermal power that may exceed

0.5 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the

actual antenna return loss, the transmitting frequency band, etc. The generated thermal power must be adequately

dissipated through the thermal and mechanical design of the application.

The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition. The

overall temperature distribution is influenced by the configuration of the active components during the specific mode of

operation and their different thermal resistance toward the case interface.

☞☞☞☞

The Module-to-Ambient thermal resistance value and the relative increase of module temperature will differ

according to the specific mechanical deployments of the module, e.g. application PCB with different dimensions and

characteristics, mechanical shells enclosure, or forced air flow.

The increase of the thermal dissipation, i.e. the reduction of the Module-to-Ambient thermal resistance, will decrease

the temperature of the modules’ internal circuitry for a given operating ambient temperature. This improves the device

long-term reliability in particular for applications operating at high ambient temperature.

Recommended hardware techniques to be used to improve heat dissipation in the application:

• Connect each GND pin with solid ground layer of the application PCB and connect each ground area of the multilayer

application PCB with complete thermal via stacked down to main ground layer.

• Provide a ground plane as wide as possible on the application board.

• Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of

module thermal power.

• Optimize the thermal design of any high-power components included in the application, such as linear regulators and

amplifiers, to optimize overall temperature distribution in the application.

Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure) of the application device

that integrates the module so that it provides good thermal dissipation.

Beside the reduction of the Module-to-Ambient thermal resistance implemented by correct application hardware design,

increase of module temperature can be moderated by a correspondingly correct application software

the

implementation:

Enable power saving configuration using the AT+CPSMS command

Enable module connected mode for a given time period and then disable it for a time period long enough to

adequately mitigate the temperature increase.

•

•

•

2.13 Schematic for SARA-R4/N4 series module integration

2.13.1 Schematic for SARA-R4/N4 series modules

Figure 55 is an example of a schematic diagram where a SARA-R4/N4 series “00”, “01” or “x2” product version is

integrated into an application board using all available module interfaces and functions.

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SARA-R4/ N4

15pF

33pF

Connect or

Ext ernal

ant enna

39nH

68nH

10k

27pF

ESD

V_INT

TP

1k

SIM Card

Holder

SW 1

SW 2

CCVCC (C1)

CCVPP (C6)

CCIO (C7)

CCCLK (C3)

CCRST (C2)

GND (C5)

470k

47pF

47pF 47pF

47pF

10 0nF

ESD ESD ESD ESD ESD ESD

Not support ed by ‘0 0’ and ‘01’ product version

3V8

LDO Regulat or

3V0

IN

OUT

SHDNn

GND

10 0nF

u-blox GNSS

3.0 V receiver

VCC

47k

V_INT

TCA9406

I2C Volt age Translat or

VCCA

VCCB

100nF

OE

10 0nF

4.7k

4.7k

SDA

26

SCL

27

SDA_A

SDA_B

SCL_A

GND

SCL_B

SDA2

SCL2

V_INT

SN74AVC2T245

Volt age Translat or

3V0

100nF

100 nF

VCCB

B1

B2

VCCA

DIR1

A1

A2

OEn

GND

DIR2

TxD1

EXTINT0

ANT

56

ANT_DE

T

62

V_INT

4

GPIO5

VSIM

42

41

SIM _IO

SIM _CLK

SIM _RST

39

38

40

GPIO2

23

3V8

Applicat ion

Processor

Open

drain

out put

Open

drain

out put

USB 2.0 host

1.8 V DTE

VBUS

D-

D+

GND

TXD

RXD

RTS

CTS

DTR

DSR

RI

DCD

GND

100 uF

100 nF

10 nF

68pF

15pF

51 VCC

52 VCC

53 VCC

GND

TP

TP

15

PW R_ON

18 RESET_N

0Ω

0 Ω

0 Ω

0 Ω

0 Ω

TP

TP

TP

TP

TP

17 VUSB_DET

28 USB_D-

29 USB_D+

GND

12

TXD

13 RXD

10 RTS

11 CTS

9

6

7

8

DTR

DSR

RI

DCD

GND

GPIO3

GPIO4

24

25

GPIO6

19

RSVD

SDIO_D2

SDIO_CLK

SDIO_CM D

SDIO_D0

SDIO_D3

44

45

46

47

48

49

I2S_TXD / SPI_CS

35

I2S_RXD / SPI_M ISO

37

I2S_CLK / SPI_CLK

36

34

SDIO_D1

I2S_W A / SPI_M OSI

16 GPIO1

GND

3V8

Net work

Indicat or

Figure 55: Example of schematic diagram to integrate a SARA-R4/N4 series module using all available interfaces32

32 Flow control is not supported by ‘00’, ‘01’ and SARA-R410M-02B-00 product versions, but the RTS input must be set low to use the UART on ‘00’ and ‘01’

versions. The DTR input must be set low to have URCs presented over UART on ‘00’, ‘01’ and ‘x2’ product versions.

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2.14 Design-in checklist

This section provides a design-in checklist.

2.14.1 Schematic checklist

The following are the most important points for a simple schematic check:

(cid:1)

(cid:1)

DC supply must provide a nominal voltage at VCC pin within the operating range limits.

DC supply must be capable of supporting the highest peak / pulse current consumption values and the maximum

averaged current consumption values in connected mode, as specified in the SARA-R4/N4 series Data Sheet [1].

VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in

particular if the application device integrates an internal antenna.

Do not apply loads which might exceed the limit for maximum available current from V_INT supply.

Check that voltage level of any connected pin does not exceed the relative operating range.

Provide accessible test points directly connected to the following pins of the SARA-R4/N4 series modules: V_INT,

PWR_ON and RESET_N for diagnostic purposes.

Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.

Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible.

Check UART signals direction, as the modules’ signal names follow the ITU-T V.24 Recommendation [5].

Capacitance and series resistance must be limited on each high speed line of the USB interface.

It is strongly recommended to provide accessible test points directly connected to the USB interface pins

(VUSB_DET, USB_D+ and USB_D- pins).

Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board

in series to the GPIO when those are used to drive LEDs.

Provide adequate precautions for EMC / ESD immunity as required on the application board.

Do not apply voltage to any generic digital interface pin of SARA-R4/N4 series modules before the switch-on of

the generic digital interface supply source (V_INT).

All unused pins can be left unconnected.

(cid:1)

2.14.2 Layout checklist

The following are the most important points for a simple layout check:

(cid:1)

Check 50 Ω nominal characteristic impedance of the RF transmission line connected to the ANT port (antenna

RF interface).

Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM signals, high-speed digital

lines such as USB, and other data lines).

Optimize placement for minimum length of RF line.

Check the footprint and paste mask designed for SARA-R4/N4 series module as illustrated in section 2.11.

VCC line should be enough wide and as short as possible.

Route VCC supply line away from RF line / part (refer to Figure 28) and other sensitive analog lines / parts.

The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the VCC pins, in

particular if the application device integrates an internal antenna.

Ensure an optimal grounding connecting each GND pin with application board solid ground layer.

Use as many vias as possible to connect the ground planes on multilayer application board, providing a dense

line of vias at the edges of each ground area, in particular along RF and high speed lines.

Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity.

USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 Ω differential and 30 Ω

common mode) and should not be routed close to any RF line / part.

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

(cid:1)

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2.14.3 Antenna checklist

(cid:1)

Antenna termination should provide 50 Ω characteristic impedance with V.S.W.R at least less than 3:1

(recommended 2:1) on operating bands in deployment geographical area.

Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB

layout and matching circuitry).

Ensure compliance with any regulatory agency RF radiation requirement, as reported in section 4.2.2 for United

States and in section 4.3.1 for Canada.

Ensure high isolation between the cellular antenna and any other antennas or transmitters present on the end

device.

(cid:1)

(cid:1)

(cid:1)

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☞☞☞☞

⚠⚠⚠⚠

3 Handling and soldering

No natural rubbers, no hygroscopic materials or materials containing asbestos are employed.

3.1 Packaging, shipping, storage and moisture preconditioning

For information pertaining to SARA-R4/N4 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage

information, as well as drying for preconditioning, see the SARA-R4/N4 series Data Sheet [1] and the u-blox Package

Information Guide [17].

3.2 Handling

The SARA-R4/N4 series modules are Electro-Static Discharge (ESD) sensitive devices.

Ensure ESD precautions are implemented during handling of the module.

Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different

electrical potentials caused by direct contact or induced by an electrostatic field. The term is usually used in the

electronics and other industries to describe momentary unwanted currents that may cause damage to electronic

equipment.

The ESD sensitivity for each pin of SARA-R4/N4 series modules (as Human Body Model according to JESD22-A114F) is

specified in the SARA-R4/N4 series Data Sheet [1].

ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working station or

a large manufacturing area. The main principle of an EPA is that there are no highly charging materials near ESD sensitive

electronics, all conductive materials are grounded, workers are grounded, and charge build-up on ESD sensitive

electronics is prevented. International standards are used to define typical EPA and can be obtained for example from

the International Electrotechnical Commission (IEC) or the American National Standards Institute (ANSI).

In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the

SARA-R4/N4 series modules:

• Unless there is a galvanic coupling between the local GND (i.e. the work table) and the PCB GND, then the first point

of contact when handling the PCB must always be between the local GND and PCB GND.

• Before mounting an antenna patch, connect the ground of the device.

• When handling the module, do not come into contact with any charged capacitors and be careful when contacting

•

materials that can develop charges (e.g. patch antenna, coax cable, soldering iron).

To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If there is any risk

that such exposed antenna area is touched in a non-ESD protected work area, implement adequate ESD protection

measures in the design.

• When soldering the module and patch antennas to the RF pin, make sure to use an ESD-safe soldering iron.

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3.3 Soldering

3.3.1 Soldering paste

"No Clean" soldering paste is strongly recommended for SARA-R4/N4 series modules, as it does not require cleaning after

the soldering process has taken place. The paste listed in the example below meets these criteria.

Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics)

Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper)

95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper)

Melting Temperature:

217 °C

Stencil Thickness:

150 µm for base boards

The final choice of the soldering paste depends on the approved manufacturing procedures.

The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.11.

The quality of the solder joints should meet the appropriate IPC specification.

3.3.2 Reflow soldering

A convection type-soldering oven is strongly recommended for SARA-R4/N4 series modules over the infrared type

radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly,

regardless of material properties, thickness of components and surface color.

Consider the ”IPC-7530A Guidelines for temperature profiling for mass soldering (reflow and wave) processes”.

Reflow profiles are to be selected according to the following recommendations.

Failure to observe these recommendations can result in severe damage to the device!

Preheat phase

Initial heating of component leads and balls. Residual humidity will be dried out. Note that this preheat phase will not

replace prior baking procedures.

Temperature rise rate: max 3 °C/s

Time: 60 – 120 s

End Temperature: +150 - +200 °C

Heating/ reflow phase

If the temperature rise is too rapid in the preheat phase it may cause

excessive slumping.

If the preheat is insufficient, rather large solder balls tend to be

generated. Conversely, if performed excessively, fine balls and large

balls will be generated in clusters.

If the temperature is too low, non-melting tends to be caused in areas

containing large heat capacity.

The temperature rises above the liquidus temperature of +217 °C. Avoid a sudden rise in temperature as the slump of

the paste could become worse.

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•

•

•

Limit time above +217 °C liquidus temperature: 40 - 60 s

•

• Peak reflow temperature: +245 °C

Cooling phase

A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible

mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low

contact angle.

•

Temperature fall rate: max 4 °C/s

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[°C]

250

217

200

150

100

50

To avoid falling off, modules should be placed on the topside of the motherboard during soldering.

The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering

paste, size, thickness and properties of the base board, etc.

Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering

profile may permanently damage the module.

Preheat

Heating

Peak Temp. 245°C

Cooling

Liquidus Temperature

max 3°C/s

60 - 120 s

40 - 60 s

End Temp.

150 - 200°C

max 4°C/s

[°C]

250

217

200

150

50

Typical Leadfree

Soldering Profile

100

Figure 56: Recommended soldering profile

Elapsed time [s]

The modules must not be soldered with a damp heat process.

After soldering the module, inspect it optically to verify that it is correctly aligned and centered.

3.3.3 Optical inspection

3.3.4 Cleaning

Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing

process.

• Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the

module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like

interconnections between neighboring pads. Water will also damage the sticker and the ink-jet printed text.

• Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings,

areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet

printed text.

• Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators.

For best results, use a "no clean" soldering paste and eliminate the cleaning step after the soldering.

3.3.5 Repeated reflow soldering

Repeated reflow soldering processes and soldering the module upside-down are not recommended.

Boards with components on both sides may require two reflow cycles. In this case, the module should always be placed

on the side of the board that is submitted into the last reflow cycle. The reason for this (besides others) is the risk of the

module falling off due to the significantly higher weight in relation to other components.

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SARA-R4/N4 series - System Integration Manual

u-blox gives no warranty against damages to the SARA-R4/N4 series modules caused by performing more than a total

of two reflow soldering processes (one reflow soldering process to mount the SARA-R4/N4 series module, plus one

reflow soldering process to mount other parts).

3.3.6 Wave soldering

SARA-R4/N4 series LGA modules must not be soldered with a wave soldering process.

Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require

wave soldering to solder the THT components. No more than one wave soldering process is allowed for a board with a

SARA-R4/N4 series module already populated on it.

Performing a wave soldering process on the module can result in severe damage to the device!

u-blox gives no warranty against damages to the SARA-R4/N4 series modules caused by performing more than a total

of two soldering processes (one reflow soldering process to mount the SARA-R4/N4 series module, plus one wave

soldering process to mount other THT parts on the application board).

3.3.7 Hand soldering

Hand soldering is not recommended.

3.3.8 Rework

Rework is not recommended.

3.3.9 Conformal coating

Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately

terminate the warranty.

Certain applications employ a conformal coating of the PCB using HumiSeal® or other related coating products.

These materials affect the HF properties of the cellular modules and it is important to prevent them from flowing into

the module.

The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is

required in applying the coating.

Conformal Coating of the module will void the warranty.

3.3.10 Casting

If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes

in combination with the cellular modules before implementing this in production.

Casting will void the warranty.

3.3.11 Grounding metal covers

Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI

covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity

to interference and noise.

u-blox gives no warranty for damages to the cellular modules caused by soldering metal cables or any other forms of

metal strips directly onto the EMI covers.

3.3.12 Use of ultrasonic processes

The cellular modules contain components which are sensitive to ultrasonic waves. Use of any ultrasonic processes

(cleaning, welding etc.) may cause damage to the module.

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u-blox gives no warranty against damages to the cellular modules caused by any ultrasonic processes.

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4 Approvals

4.1 Product certification approval overview

Product certification approval is the process of certifying that a product has passed all tests and criteria required by

specifications, typically called “certification schemes”, that can be divided into:

• Regulatory certifications

o Country-specific approval required by local government in most regions and countries, as:

(cid:2) CE (Conformité Européenne) marking for European Union

(cid:2)

FCC (Federal Communications Commission) approval for the United States

•

Industry certifications

o Telecom industry-specific approval verifying interoperability between devices and networks:

(cid:2) GCF (Global Certification Forum)

(cid:2) PTCRB (PCS Type Certification Review Board)

• Operator certifications

o Operator-specific approvals required by some mobile network operator, such as:

(cid:2) AT&T network operator in United States

(cid:2) Verizon Wireless network operator in United States

The manufacturer of the end-device that integrates a SARA-R4/N4 series module must take care of all certification

approvals required by the specific integrating device to be deployed in the market.

The required certification scheme approvals and relative testing specifications applicable to the end-device that

integrates a SARA-R4/N4 series module differ depending on the country or the region where the integrating device is

intended to be deployed, on the relative vertical market of the device, on type, features and functionalities of the whole

application device, and on the network operators where the device is intended to operate.

Check the appropriate applicability of the SARA-R4/N4 series module’s approvals while starting the certification

process of the device integrating the module: the re-use of the u-blox cellular module’s approval can significantly

reduce the cost and time to market of the application device certification.

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Table 38 summarizes the main approvals achieved or planned for SARA-R410M and SARA-R412M modules.

SARA-R410M-01B

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M-03B

SARA-R410M-63B

SARA-R410M-73B

SARA-R412M-02B

SARA-R412M-03B

LTE Cat M1 Band

2,4,5,12

LTE Cat M1, NB1 Band

2,3,4,5,8,12,13,20,28

LTE Cat M1 Band

2,4,5,12,13

LTE Cat M1, NB1 Band

2,4,5,12

LTE Cat M1, NB1 Band

2,3,4,5,8,12,13,20,26,28

SARA-R4/N4 series - System Integration Manual

Certification

PTCRB

GCF

CE Europe

FCC US

FCC ID

ISED Canada

ISED ID

IFT Mexico

RCM Australia

NCC Taiwan

GITEKI Japan

KC Korea

Verizon

AT&T

LTE Cat M1 Band

2,4,5,12,13

LTE Cat M1, NB1 Band

3,8,20

LTE Cat M1, NB1 Band

1,2,3,4,5,8,12,13,20,25,26,28

LTE Cat M1, NB1 Band

1,2,3,4,5,8,12,13,20,25,26,28

LTE Cat M1, NB1 Band

1,3,8,20,28

LTE Cat M1 Band

2,4,5,12

LTE Cat M1, NB1 Band

2,4,5,12,13,2533

LTE Cat M1 Band

2,4,5,12,13

LTE Cat M1, NB1 Band

2,4,5,12,13,25,26

XPY2AGQN4NNN

XPY2AGQN4NNN

XPY2AGQN4NNN

XPY2AGQN4NNN

LTE Cat M1 Band

2,4,5,12

LTE Cat M1, NB1 Band

2,4,5,12,13

LTE Cat M1 Band

2,4,5,12,13

LTE Cat M1, NB1 Band

2,4,5,12,13

8595A-2AGQN4NNN

8595A-2AGQN4NNN

8595A-2AGQN4NNN

8595A-2AGQN4NNN

M1 Band

2,4,5,12

33 LTE Cat M1 only

LTE Cat M1 Band

3,5,8,28

LTE Cat M1, NB1 Band

3,8,28

LTE Cat M1, NB1 Band

1,8,18,19,26

LTE Cat M1, NB1 Band

3,5,8,28

LTE Cat M1, NB1 Band

3,8,28

LTE Cat M1, NB1 Band

1,8,18,19,26

LTE Cat M1, NB1 Band

1,8,18,19,26

LTE Cat M1 Band

3,5,26

LTE Cat M1 Band

2,4,5,12

LTE Cat M1 Band

4,13

LTE Cat M1 Band

2,4,5,12

LTE Cat M1 Band

4,13

LTE Cat M1 Band

2,4,5,12

LTE Cat M1, NB1 Band

4,13

LTE Cat M1, NB1 Band

2,4,5,12

LTE Cat M1 Band

2,4,5,12

LTE Cat M1, NB1 Band

4,13

LTE Cat M1, NB1 Band

2,4,5,12

LTE Cat M1, NB1 Band

2,3,4,5,8,12,13,20,26,28

2G Band

900,1800

LTE Cat M1, NB1 Band

3,8,20,28

2G Band

900,1800

LTE Cat M1, NB1 Band

2,4,5,12,13,26

2G Band

850,1900

LTE Cat M1, NB1 Band

3,8,20

2G Band

900,1800

LTE Cat M1, NB1 Band

2,4,5,12,13

2G Band

850,1900

XPYUBX18ZO01

XPYUBX18ZO01

LTE Cat M1, NB1 Band

2,4,5,12,13

2G Band

850,1900

LTE Cat M1, NB1 Band

2,4,5,12,13

2G Band

850,1900

8595A-UBX18ZO01

8595A-UBX18ZO01

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SARA-R4/N4 series - System Integration Manual

LTE Cat NB1 Band

2,4,5,12

LTE Cat NB1 Band

2,4,5,12

SARA-R410M-01B

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M-03B

SARA-R410M-63B

SARA-R410M-73B

SARA-R412M-02B

SARA-R412M-03B

LTE Cat M1 Band

2,4,5,12

LTE Cat M1 Band

2,4,5,12

Certification

T-Mobile US

Sprint

US Cellular

Bell

Telus

Telstra

Softbank

NTT DOCOMO

SKT

Deutsche Telekom

Vodafone

LTE Cat M1 Band

25

LTE Cat M1 Band

2,4,5,12

LTE Cat M1 Band

2,4,5,12

LTE Cat M1 Band

3,5,8,28

LTE Cat M1, NB1 Band

3,5,8,28

LTE Cat NB1 Band

3,8,20

LTE Cat M1 Band

1,8

LTE Cat M1 Band

1,19

LTE Cat M1 Band

3,5,26

Table 38: Summary of certification approvals achieved for the SARA-R4/N4 series modules, with related RAT and bands

LTE Cat NB1 Band

3,8,20

2G Band

900,1800

LTE Cat NB1 Band

3,8,20

2G Band

900,1800

The certification approvals listed in Table 38 might not be available for all the different product type numbers. Please contact the u-blox office or sales representative nearest you

for the full comprehensive list of approvals and for further specific info about all country, conformance and network operators’ certifications available for the selected product

ordering number.

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SARA-R4/N4 series - System Integration Manual

Table 39 summarizes how some of the SARA-R4/N4 series modules are identified by various bodies.

Description

SARA-R410M-01B

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M-03B

SARA-R412M-02B

SARA-R412M-03B

SARA-R410M

SARA-R410M-02B

SARA-R410M-52B

SARA-R412M

Model Name

SARA-R410M

SARA-R410M

Marketing Name

SARA-R410M

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M-03B

SARA-R410M-52B

SARA-R410M-52B

SARA-R410M-52B

Product Name

SARA-R410M

SARA-R410M-02B

SARA-R410M-02B

SARA-R410

SARA-R412M

SARA-R412M-03B

XPY2AGQN4NNN

XPY2AGQN4NNN

XPY2AGQN4NNN

XPY2AGQN4NNN

XPYUBX18ZO01

XPYUBX18ZO01

ISED Canada

8595A-2AGQN4NNN

8595A-2AGQN4NNN

8595A-2AGQN4NNN

8595A-2AGQN4NNN

8595A-UBX18ZO01

8595A-UBX18ZO01

Model Name

Model Name

Marketing Name

ID

ID

HVIN

PMN

Model Name

Model Number

Model Name

Model Name

Model Name

Model Name

Model Name

Model Name

--

--

--

--

--

--

--

--

--

--

Body

PTCRB

GCF

GSMA

FCC US

RED Europe

RCM Australia

AT&T

Verizon

Sprint

T-Mobile US

Vodafone

Telstra

SARA-R410M

SARA-R410M

SARA-R410M

SARA-R410M

SARA-R410M

SARA-R410M

SARA-R410M-02B

SARA-R410M-02B

SARA-R410M

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M-02B

SARA-R410M-52B

SARA-R410M

--

--

--

--

--

--

--

Deutsche Telekom

Model Name

Table 39: Summary of some SARA-R4/N4 series modules’ identification by various bodies

SARA-R410M-02B

--

--

--

--

--

SARA-R410

SARA-R410

SARA-R410

SARA-R410

SARA-R410M

SARA-R410

SARA-R410

SARA-R410

SARA-R410

SARA-R410

SARA-R410

--

SARA-R410

SARA-R410

SARA-R410

SARA-R412M

SARA-R412M

SARA-R412M

SARA-R412M

SARA-R412M

SARA-R412M

--

--

--

--

--

--

--

--

--

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

SARA-R412M-03B

--

--

--

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SARA-R4/N4 series - System Integration Manual

The SARA-R4/N4 series modules from “02” product versions onwards include the capability to configure the device by

selecting the operating Mobile Network Operator Profile, Radio Access Technology, and bands. In the SARA-R4/N4 series

AT Commands Manual [2], see the +UMNOPROF, +URAT, and +UBANDMASK AT commands.

As these configuration decisions are made, u-blox reminds manufacturers of the end-device integrating the “02” product

versions onwards of SARA-R4/N4 series modules to take care of compliance with all the certification approvals

requirements applicable to the specific integrating device to be deployed in the market.

It is strongly recommended to configure the module to the applicable MNO profile, RAT, and LTE bands intended for

the application device and within regulatory compliance. The SARA-R4/N4 series “02” product versions are not

intended be used in the factory-programmed setting.

The certification of the application device that integrates a SARA-R4/N4 series module and the compliance of the

application device with all the applicable certification schemes, directives and standards are the sole responsibility

of the application device manufacturer.

SARA-R4/N4 series modules are certified according to all capabilities and options stated in the Protocol Implementation

Conformance Statement document (PICS) of the module. The PICS, according to the 3GPP TS 51.010-2 [12], 3GPP TS

36.521-2 [14] and 3GPP TS 36.523-2 [15], is a statement of the implemented and supported capabilities and options of a

device.

The PICS document of the application device integrating SARA-R4/N4 series modules must be updated from the

module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or

disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see the

SARA-R4/N4 series AT Commands Manual [1].

Check the specific settings required for mobile network operators approvals as they may differ from the AT

commands settings defined in the module as integrated in the application device.

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4.2 US Federal Communications Commission notice

United States Federal Communications Commission (FCC) IDs:

• u-blox SARA-R404M cellular modules:

• u-blox SARA-R410M and SARA-N410 cellular modules:

• u-blox SARA-R412M cellular modules:

XPY2AGQN1NNN

XPY2AGQN4NNN

XPYUBX18ZO01

4.2.1 Safety warnings review the structure

•

•

Equipment for building-in. Requirements for fire enclosure must be evaluated in the end product

The clearance and creepage current distances required by the end product must be withheld when the module is

installed

The cooling of the end product shall not negatively be influenced by the installation of the module

Excessive sound pressure from earphones and headphones can cause hearing loss

•

•

• No natural rubbers, hygroscopic materials, or materials containing asbestos are employed

4.2.2 Declaration of Conformity

This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference

this device must accept any interference received, including interference that may cause undesired operation

Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits

prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed

and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons.

This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as

authorized in the certification of the product.

The gain of the system antenna(s) used for the SARA-R4/N4 series modules (i.e. the combined transmission line,

connector, cable losses and radiating element gain) must not exceed the value specified in the FCC Grant for mobile

and fixed or mobile operating configurations:

•

•

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• SARA-R404M modules:

•

•

•

o 13 dBi in 750 MHz, i.e. LTE FDD-13 band

SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band

o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band

o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band

SARA-R410M-02B, SARA-R410M-52B and SARA-N410-02B modules:

o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band

o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band

o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band

o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band

o 9.40 dBi in 1900 MHz, i.e. LTE FDD-25 band

SARA-R412M-02B modules:

o 8.69 dBi in 700 MHz, i.e. LTE FDD-12 band

o 9.15 dBi in 750 MHz, i.e. LTE FDD-13 band

o 9.41 dBi in 850 MHz, i.e. GSM 850 / LTE FDD-5 band

o 12.01 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 12.01 dBi in 1900 MHz, i.e. GSM 1900 / LTE FDD-2 band

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4.2.3 Modifications

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly

approved by u-blox could void the user's authority to operate the equipment.

⚠⚠⚠⚠ Manufacturers of mobile or fixed devices incorporating the SARA-R4/N4 series modules are authorized to use the

FCC Grants of the SARA-R4/N4 series modules for their own final products according to the conditions referenced in

the certificates.

The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o For SARA-R404M modules:

o For SARA-R410M and SARA-N410 modules:

o For SARA-R412M cellular modules:

"Contains FCC ID: XPY2AGQN1NNN"

"Contains FCC ID: XPY2AGQN4NNN"

"Contains FCC ID: XPYUBX18ZO01"

IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4/N4 series modules are required to

have their final product certified and apply for their own FCC Grant related to the specific portable device. This is

mandatory to meet the SAR requirements for portable devices.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's

authority to operate the equipment.

Additional Note: as per 47CFR15.105 this equipment has been tested and found to comply with the limits for a Class

B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection

against harmful interference in a residential installation. This equipment generates, uses and can radiate radio

frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference

to radio communications. However, there is no guarantee that interference will not occur in a particular installation.

If this equipment does cause harmful interference to radio or television reception, which can be determined by

turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the

following measures:

Increase the separation between the equipment and receiver

o Reorient or relocate the receiving antenna

o

o Connect the equipment into an outlet on a circuit different from that to which the receiver is connected

o Consultant the dealer or an experienced radio/TV technician for help

4.3

Innovation, Science, Economic Development Canada notice

ISED Canada (formerly known as IC - Industry Canada) Certification Numbers:

• u-blox SARA-R410M and SARA-N410 cellular modules:

• u-blox SARA-R412M cellular modules:

8595A-2AGQN4NNN

8595A-UBX18ZO01

4.3.1 Declaration of Conformity

This device complies with the ISED Canada license-exempt RSS standard(s). Operation is subject to the following two

conditions:

this device may not cause harmful interference

this device must accept any interference received, including interference that may cause undesired operation

Radiofrequency radiation exposure information: this equipment complies with the radiation exposure limits

prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed

and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons.

This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as

authorized in the certification of the product.

⚠⚠⚠⚠

⚠⚠⚠⚠

⚠⚠⚠⚠

•

•

⚠⚠⚠⚠

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⚠⚠⚠⚠

The gain of the system antenna(s) used for the SARA-R4/N4 series modules (i.e. the combined transmission line,

connector, cable losses and radiating element gain) must not exceed the value stated in the ISED Canada Grant for

mobile and fixed or mobile operating configurations:

•

•

•

SARA-R410M-01B modules:

o 3.67 dBi in 700 MHz, i.e. LTE FDD-12 band

o 4.10 dBi in 850 MHz, i.e. LTE FDD-5 band

o 6.74 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 7.12 dBi in 1900 MHz, i.e. LTE FDD-2 band

SARA-R410M-02B, SARA-R410M-52B and SARA-N410-02B modules:

o 3.66 dBi in 700 MHz, i.e. LTE FDD-12 band

o 3.94 dBi in 750 MHz, i.e. LTE FDD-13 band

o 4.41 dBi in 850 MHz, i.e. LTE FDD-5 band

o 6.75 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 7.00 dBi in 1900 MHz, i.e. LTE FDD-2 band

SARA-R412M-02B modules:

o 5.63 dBi in 700 MHz, i.e. LTE FDD-12 band

o 5.94 dBi in 750 MHz, i.e. LTE FDD-13 band

o 6.12 dBi in 850 MHz, i.e. GSM 850 / LTE FDD-5 band

o 8.29 dBi in 1700 MHz, i.e. LTE FDD-4 band

o 8.52 dBi in 1900 MHz, i.e. GSM 1900 / LTE FDD-2 band

4.3.2 Modifications

ISED Canada requires the user to be notified that any changes or modifications made to this device that are not expressly

approved by u-blox could void the user's authority to operate the equipment.

⚠⚠⚠⚠ Manufacturers of mobile or fixed devices incorporating the SARA-R4/N4 series modules are authorized to use the

ISED Canada Certificates of the SARA-R4/N4 series modules for their own final products according to the conditions

referenced in the certificates.

The ISED Canada Label shall in the above case be visible from the outside, or the host device shall bear a second label

stating:

o For SARA-R410M and SARA-N410 modules:

o For SARA-R412M cellular modules:

"Contains IC: 8595A-2AGQN4NNN"

"Contains IC: 8595A-UBX18ZO01"

⚠⚠⚠⚠

⚠⚠⚠⚠

Innovation, Science and Economic Development Canada (ISED) Notices

This Class B digital apparatus complies with Canadian CAN ICES-3(B) / NMB-3(B).

Operation is subject to the following two conditions:

•

•

this device may not cause interference

this device must accept any interference, including interference that may cause undesired operation of the

device

Radio Frequency (RF) Exposure Information

The radiated output power of the u-blox Cellular Module is below the Innovation, Science and Economic

Development Canada (ISED) radio frequency exposure limits. The u-blox Cellular Module should be used in a manner

such that the potential for human contact during normal operation is minimized.

This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions

(antennas are greater than 20 cm from a person's body).

This device has been certified for use in Canada. Status of the listing in the Industry Canada’s REL (Radio Equipment

List) can be found at the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng

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⚠⚠⚠⚠

⚠⚠⚠⚠

⚠⚠⚠⚠

SARA-R4/N4 series - System Integration Manual

Additional Canadian

http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html

information on RF exposure also can be found at the following web address:

IMPORTANT: Manufacturers of portable applications incorporating the SARA-R4/N4 series modules are required to

have their final product certified and apply for their own Industry Canada Certificate related to the specific portable

device. This is mandatory to meet the SAR requirements for portable devices.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's

authority to operate the equipment.

Avis d'Innovation, Sciences et Développement économique Canada (ISDE)

Cet appareil numérique de classe B est conforme aux normes canadiennes CAN ICES-3(B) / NMB-3(B). Son

fonctionnement est soumis aux deux conditions suivantes:

o cet appareil ne doit pas causer d'interférence

o cet appareil doit accepter toute interférence, notamment les interférences qui peuvent affecter son

fonctionnement

Informations concernant l'exposition aux fréquences radio (RF)

La puissance de sortie émise par l’appareil de sans-fil u-blox Cellular Module est inférieure à la limite d'exposition

aux fréquences radio d'Innovation, Sciences et Développement économique Canada (ISDE). Utilisez l’appareil de

sans-fil u-blox Cellular Module de façon à minimiser les contacts humains lors du fonctionnement normal.

Ce périphérique a été évalué et démontré conforme aux limites d'exposition aux fréquences radio (RF) d'IC lorsqu'il

est installé dans des produits hôtes particuliers qui fonctionnent dans des conditions d'exposition à des appareils

mobiles (les antennes se situent à plus de 20 centimètres du corps d'une personne).

Ce périphérique est homologué pour l'utilisation au Canada. Pour consulter l'entrée correspondant à l’appareil dans

la liste d'équipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra

Pour des

informations supplémentaires concernant

http://www.ic.gc.ca/eic/site/smt-gst.nsf/fra/sf08792.html

l'exposition aux RF au Canada rendez-vous sur:

IMPORTANT: les fabricants d'applications portables contenant les modules de la SARA-R4/N4 series doivent faire

certifier leur produit final et déposer directement leur candidature pour une certification FCC ainsi que pour un

certificat ISDE Canada délivré par l'organisme chargé de ce type d'appareil portable. Ceci est obligatoire afin d'être

en accord avec les exigences SAR pour les appareils portables.

Tout changement ou modification non expressément approuvé par la partie responsable de la certification peut

annuler le droit d'utiliser l'équipement.

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4.4

European Conformance CE mark

SARA-R410M-02B and SARA-R412M-02B module product versions have been evaluated against the essential

requirements of the Radio Equipment Directive 2014/53/EU.

In order to satisfy the essential requirements of the 2014/53/EU RED, the modules are compliant with the following

standards:

• Radio Spectrum Efficiency (Article 3.2):

o EN 301 908-1

o EN 301 908-13

o EN 301 511

Electromagnetic Compatibility (Article 3.1b):

o EN 301 489-1

o EN 301 489-52

•

• Health and Safety (Article 3.1a)

o EN 62368-1

o EN 62311

⚠⚠⚠⚠

⚠⚠⚠⚠

Radiofrequency radiation exposure Information: this equipment complies with radiation exposure limits prescribed

for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and

operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This

transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as

authorized in the certification of the product.

The gain of the system antenna(s) used for the SARA-R410M-02B and SARA-R412M-02B modules (i.e. the combined

transmission line, connector, cable losses and radiating element gain) must not exceed the values stated in the

Declaration of Conformity of the modules, for mobile and fixed or mobile operating configurations:

•

•

SARA-R410M-02B modules:

o 8.2 dBi in 800 MHz, i.e. LTE FDD-20 band

o 8.4 dBi in 900 MHz, i.e. LTE FDD-8 band

o 11.3 dBi in 1800 MHz, i.e. LTE FDD-3 band

SARA-R412M-02B modules:

o 8.2 dBi in 800 MHz, i.e. LTE FDD-20 band

o 3.21 dBi in 900 MHz, i.e. GSM 900 / LTE FDD-8 band

o 9.09 dBi in 1800 MHz, i.e. GSM 1800 / LTE FDD-3 band

Thus, the following marking is included in the product:

The conformity assessment procedure for the SARA-R410M-02B and SARA-R412M-02B modules, referred to in Article 17

and detailed in Annex II of Directive 2014/53/EU, has been followed.

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4.5 National Communication Commission Taiwan

The SARA-R410M-02B and SARA-N410-02B product versions have the applicable regulatory approvals for Taiwan (NCC)

SARA-R410M-02B modules NCC ID: CCAA18NB0010T3

CCAA18NB0010T3

SARA-R410M-03B modules NCC ID: CCAA19NB0010T0

CCAA19NB0010T0

SARA-N410-02B modules NCC ID: CCAI18NB0050T4

CCAI18NB0050T4

4.6 GITEKI Japan

•

SARA-R410M-02B

o T: D180083003

o R: 003-180155

•

SARA-R410M-63B, SARA-R410M-03B

o T: D190029003

o R: 003-190033

•

•

•

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5 Product testing

5.1 u-blox in-series production test

u-blox focuses on high quality for its products. All units produced are fully tested automatically on the production line.

Stringent quality control processes have been implemented in the production line. Defective units are analyzed in detail

to improve production quality.

This is achieved with automatic test equipment (ATE) in the production line, which logs all production and measurement

data. A detailed test report for each unit can be generated from the system. Figure 57 illustrates the typical automatic

test equipment (ATE) in a production line.

The following typical tests are among the production tests.

• Digital self-test (firmware download, flash firmware verification, IMEI programming)

• Measurement of voltages and currents

• Adjustment of ADC measurement interfaces

•

• Digital tests (GPIOs and other interfaces)

• Measurement and calibration of RF characteristics in all supported bands (such as receiver S/N verification, frequency

Functional tests (serial interface communication, SIM card communication)

tuning of the reference clock, calibration of transmitter and receiver power levels, etc.)

• Verification of the RF characteristics after calibration (i.e. modulation accuracy, power levels, spectrum, etc. are

checked to ensure they are all within tolerances when calibration parameters are applied)

Figure 57: Automatic test equipment for module tests

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5.2 Test parameters for OEM manufacturers

Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat the firmware

tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test.

However, an OEM manufacturer should focus on:

• Module assembly on the device; it should be verified that:

o The soldering and handling process did not damage the module components

o All module pins are well soldered on the device board

o There are no short circuits between pins

• Component assembly on the device; it should be verified that:

o Communication with the host controller can be established

o The interfaces between the module and device are working

o Overall RF performance test of the device including the antenna

Dedicated tests can be implemented to check the device. For example, the measurement of the module current

consumption when set in a specified status can detect a short circuit if compared with a “Golden Device” result.

In addition, module AT commands can be used to perform functional tests on the digital interfaces (communication with

the host controller, check the SIM interface, GPIOs, etc.) or to perform RF functional tests (see the following section 5.2.2

for details).

☞☞☞☞

•

•

☞☞☞☞

⚠⚠⚠⚠

⚠⚠⚠⚠

5.2.1

“Go/No go” tests for integrated devices

A “Go/No go” test is typically used to compare the signal quality with a “Golden Device” in a location with excellent

network coverage and known signal quality. This test should be performed after the data connection has been

established. AT+CSQ is the typical AT command used to check signal quality in term of RSSI. See the SARA-R4/N4 series

AT Commands Manual [2] for detail usage of the AT command.

These kinds of test may be useful as a “go/no go” test but not for RF performance measurements.

This test is suitable to check the functionality of communications with the host controller, the SIM card and the power

supply. It is also a means to verify if components at the antenna interface are well-soldered.

5.2.2 RF functional tests

The overall RF functional test of the device including the antenna can be performed with basic instruments such as a

spectrum analyzer (or an RF power meter) and a signal generator with the assistance of the AT+UTEST command over

the AT command user interface.

The AT+UTEST command provides a simple interface to set the module to Rx or Tx test modes ignoring the LTE signaling

protocol. The command can set the module into:

transmitting mode in a specified channel and power level in all supported bands

receiving mode in a specified channel to return the measured power level in all supported bands

See the SARA-R4/N4 series AT Commands Manual [2] for the AT+UTEST command syntax description and detail guide

of usage.

This feature allows the measurement of the transmitter and receiver power levels to check the component assembly

related to the module antenna interface and to check other device interfaces on which the RF performance depends.

To avoid module damage during a transmitter test, a suitable antenna according to module specifications or a 50 Ω

termination must be connected to the ANT port.

To avoid module damage during a receiver test, the maximum power level received at the ANT port must meet

module specifications.

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☞☞☞☞

The AT+UTEST command sets the module to emit RF power ignoring LTE signaling protocol. This emission can

generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing

purposes in controlled environments by qualified users and must not be used during the normal module operation.

Follow the instructions suggested in the u-blox documentation. u-blox assumes no responsibilities for the

inappropriate use of this feature.

Figure 58 illustrates a typical test setup for such an RF functional test.

Applicat ion

Processor

SARA-R4/ N4

A T

com m ands

Cellular

ant enna

Wideband

ant enna

ANT

TX

IN

Spect rum

Analyzer

or

Power

M et er

Applicat ion Board

Applicat ion

Processor

SARA-R4/ N4

A T

com m ands

Cellular

ant enna

Wideband

ant enna

ANT

RX

OUT

Signal

Generat or

Applicat ion Board

Figure 58: Setup with spectrum analyzer or power meter and signal generator for SARA-R4/N4 series RF measurements

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SARA-R4/N4 series - System Integration Manual

Appendix

A.1 Overview

A Migration between SARA modules

SARA-G3 2G modules, SARA-U2 3G / 2G modules, SARA-R4/N4 LTE Cat M1/NB1 / 2G modules and SARA-N2 LTE Cat NB1

modules have exactly the same u-blox SARA form factor (26.0 x 16.0 mm, LGA 96-pin), with compatible pin assignments,

as in Figure 59. Any one of the modules can be mounted on a single application board using exactly the same copper

mask, solder mask and paste mask.

T

E

D

_

T

N

A

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

T

N

A

D

N

G

D

N

G

T

E

D

_

T

N

A

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

T

N

A

D

N

G

D

N

G

T

E

D

_

T

N

A

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

T

N

A

D

N

G

D

N

G

T

E

D

_

T

N

A

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

D

N

G

T

N

A

D

N

G

D

N

G

64 63

62

61 60

59

58 57

56

55 54

64 63

62

61 60

59

58 57

56

55 54

64 63

62

61 60

59

58 57

56

55 54

64 63

62

61 60

59

58 57

56

55 54

65

66

67

68

69

65

66

67

68

69

70

65

66

67

68

69

65

66

67

68

69

70

71

72

73

74

75

71

72

73

74

75

71

72

73

74

75

71

72

73

74

75

SARA-G3

Top View

SARA-U2

Top View

SARA-R4 / N4

Top View

SARA-N2

Top View

GND

V_BCKP

GND

V_INT

GND

DSR

RI

DCD

DTR

RTS

CTS

TXD

RXD

GND

PW R_ON

GPIO1

RSVD

RESET_N

RSVD

GND

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

77

79

81

83

70

76

78

80

82

84

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VCC

VCC

VCC

GND

M IC_P

M IC_N

M IC_GND

M IC_BIAS

SPK_N

SPK_P

GND

SIM _DET

VSIM

SIM _RST

SIM _IO

SIM _CLK

I2S_RXD

I2S_CLK

I2S_WA

RSVD

GND

V_BCKP

GND

V_INT

GND

DSR

RI

DCD

DTR

RTS

CTS

TXD

RXD

GND

GND

GND

PW R_ON

GPIO1

VUSB_DET

RESET_N

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

77

79

81

83

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VCC

VCC

VCC

GND

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

GND

SIM _DET

VSIM

SIM _RST

SIM _IO

SIM _CLK

I2S_CLK

I2S_TXD

I2S_W A

RSVD

76

78

80

82

84

90

96

77

79

81

GND

RSVD

GND

V_INT

GND

DSR

RI

DCD

DTR

RTS

CTS

TXD

RXD

GND

PWR_ON

GPIO1

RESET_N

GPIO6

GND

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

VCC

VCC

VCC

GND

SDIO_D1

SDIO_D3

SDIO_D0

SDIO_CM D

SDIO_CLK

SDIO_D2

GND

GPIO5

VSIM

SIM _RST

SIM _IO

SIM _CLK

70

76

78

80

82

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

77

79

81

GND

RSVD

GND

V_INT

GND

RSVD

RSVD

RSVD

RSVD

RTS

CTS

TXD

RXD

GND

RSVD

GPIO1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Pin 65-96: GND

85

86

87

88

89

90

I2S_TXD

CODEC_CLK

Pin 65-96: GND

85

86

87

88

89

95

I2S_RXD

VUSB_DET

83

84

I2S_RXD/ SPI_M ISO

RSVD

83

Pin 65-96: GND

85

86

87

88

89

90

I2S_CLK/ SPI_CLK

RESET_N

I2S_TXD/ SPI_CS

I2S_WA/ SPI_M OSI

RSVD

RSVD

GND

GND

Pin 65-96: GND

85

86

87

88

89

95

91

92

93

94

95

96

91

92

93

94

91

92

93

94

95

96

91

92

93

94

22 23

24

25 26

27

28 29

30

31 32

22 23

24

25 26

27

28 29

30

31 32

22 23

24

25 26

27

28 29

30

31 32

22 23

24

25 26

27

28 29

30

31 32

D

N

G

I

2

O

P

G

I

3

O

P

G

I

4

O

P

G

A

D

S

L

C

S

D

N

G

D

N

G

D

V

S

R

X

U

A

_

D

X

R

X

U

A

_

D

X

T

D

N

G

I

2

O

P

G

I

3

O

P

G

I

4

O

P

G

A

D

S

L

C

S

D

N

G

D

N

G

D

V

S

R

-

D

_

B

S

U

+

D

_

B

S

U

D

N

G

I

2

O

P

G

I

3

O

P

G

I

4

O

P

G

A

D

S

L

C

S

D

N

G

D

V

S

R

D

N

G

-

D

_

B

S

U

+

D

_

B

S

U

D

N

G

D

V

S

R

I

2

O

P

G

D

V

S

R

A

D

S

L

C

S

D

V

S

R

D

V

S

R

D

N

G

D

V

S

R

D

N

G

Figure 59: SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 modules’ layout and pin assignment

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VCC

VCC

VCC

GND

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

GND

RSVD

VSIM

RSVD

RSVD

RSVD

RSVD

RSVD

SIM _RST

SIM _IO

SIM _CLK

76

78

80

82

84

90

96

Table 40 summarizes the interfaces provided by the SARA-G3, SARA-U2, SARA-R4/N4, SARA-N2 modules.

Modules

RAT

Power

System

SIM

Serial

Audio

Other

t

u

p

n

i

y

l

p

p

u

s

e

u

d

o

M

l

•

•

•

•

t

u

p

t

u

O

y

l

p

p

u

s

V

8

.

1

•

•

•

•

O

/

I

y

l

p

p

u

s

C

T

R

•

•

t

u

p

n

i

n

o

-

h

c

t

i

w

S

•

•

•

t

u

p

n

i

f

f

o

-

h

c

t

i

w

S

•

•

e

c

a

f

r

e

t

n

i

M

I

S

•

•

•

•

n

o

i

t

c

e

t

e

d

M

I

S

•

•

•

t

u

p

n

i

t

e

s

e

R

•

•

•

•

X

U

A

T

R

A

U

•

•

•

T

R

A

U

•

•

•

•

I

P

S

□

B

S

U

•

•

I

O

D

S

□

i

o

d

u

a

g

o

a

n

A

l

•

i

o

d

u

a

l

a

t

i

i

g

D

•

•

□

)

C

2

I

(

C

D

D

•

•

•

t

u

p

t

u

o

z

H

M

6

2

/

3

1

•

□

s

O

P

G

I

•

•

•

•

n

o

i

t

a

c

i

d

n

i

k

r

o

w

t

e

N

•

•

•

•

n

o

i

t

c

e

t

e

d

a

n

n

e

t

n

A

•

•

•

m

e

d

o

m

a

i

v

S

S

N

G

•

•

•

SARA-G3

2G

SARA-U2

3G, 2G

SARA-R4/N4

LTE M1 / NB1, 2G

SARA-N2

LTE NB1

● = supported by available product version

□ = supported by future product versions

Table 40: Summary of SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 modules interfaces

SARA modules are also form-factor compatible with the u-blox LISA, LARA and TOBY cellular module families: although

each has a different form factor, the footprints for the TOBY, LISA, SARA and LARA modules have been developed to

ensure layout compatibility.

UBX-16029218 - R13

Appendix

Page 108 of 119

SARA-R4/N4 series - System Integration Manual

With the u-blox “nested design” solution, any TOBY, LISA, SARA or LARA module can be alternatively mounted on the

same space of a single “nested” application board as described in Figure 60. Guidelines for implementing a nested

application board, a description of the u-blox reference nested design and a comparison between the TOBY, LISA, SARA

and LARA modules are provided in the Nested Design Application Note [23].

TOBY cellular module

LISA cellular module

LARA cellular module

SARA cellular module

Nested application board

Figure 60: TOBY, LISA, SARA, LARA modules’ layout compatibility: all modules lodged on the same nested footprint

UBX-16029218 - R13

Appendix

Page 109 of 119

SARA-R4/N4 series - System Integration Manual

A.2 Pin-out comparison

Table 41 shows a pin-out comparison between the SARA-G3, SARA-U2, SARA-R4/N4, and SARA-N2 modules.

No

SARA-G3

Pin Name

Description

SARA-U2

Pin Name

Description

SARA-R4

Pin Name

Description

SARA-N2

Pin Name

Description

Remarks for migration

Interfaces Supply Output:

1.8 V typ, 70 mA max

Switched-off in deep-sleep

Interfaces Supply Output:

1.8 V typ, 70 mA max

Switched-off if radio is off

V_INT is switched off in deep sleep

(R4), or if radio is off (N2). TestPoint

always recommended

1

2

3

4

5

6

7

8

9

GND

V_INT

GND

DSR

RI

DCD

DTR

10

RTS

11

CTS

GND

Ground

GND

Ground

V_BCKP

RTC Supply I/O

V_BCKP

RTC Supply I/O

Ground

Interfaces Supply Output:

1.8 V typ, 70 mA max

GND

V_INT

Ground

Interfaces Supply Output:

1.8 V typ, 70 mA max

Ground

UART DSR Output

V_INT level (1.8 V)

Driver strength: 6 mA

UART RI Output

V_INT level (1.8 V)

Driver strength: 6 mA

UART DCD Output

V_INT level (1.8 V)

Driver strength: 6 mA

UART RTS Input

V_INT level (1.8 V)

Internal pull-up:~58 k

UART CTS Output

V_INT level (1.8 V)

Driver strength: 6 mA

GND

DSR

RI

DCD

DTR

RTS

CTS

Ground

UART DSR Output

V_INT level (1.8 V)

Driver strength: 1 mA

UART RI Output

V_INT level (1.8 V)

Driver strength: 2 mA

UART DCD Output

V_INT level (1.8 V)

Driver strength: 2 mA

UART RTS Input

V_INT level (1.8 V)

Internal pull-up: ~8 k

UART CTS Output

V_INT level (1.8 V)

Driver strength: 6 mA

UART DTR Input

V_INT level (1.8 V)

Internal pull-up: ~33 k

It must be set low to have greeting

text sent over UART

UART DTR Input

V_INT level (1.8 V)

Internal pull-up: ~14 k

It must be set low to have greeting

text sent over UART

GND

RSVD

GND

V_INT

GND

DSR

RI

DCD

DTR

RTS

CTS

Ground

Reserved

Ground

Ground

UART DSR Output

V_INT level (1.8 V)

Driver strength: 2 mA

UART RI Output

V_INT level (1.8 V)

Driver strength: 2 mA

UART DCD Output

V_INT level (1.8 V)

Driver strength: 2 mA

GND

RSVD

GND

V_INT

GND

RSVD

Ground

Reserved

Ground

Ground

Reserved

RSVD

Reserved

RSVD

Reserved

RSVD

Reserved

UART DTR Input

V_INT level (1.8 V)

Internal pull-up: ~100 k

It must be set low to have URCs

sent over UART

UART RTS Input35

V_INT level (1.8 V)

Internal pull-up: ~100 k

It must be set low to use UART on

‘00’, ‘01’ product versions

UART CTS Output35

V_INT level (1.8 V)

Driver strength: 2 mA

RTS

CTS

RTC supply vs Reserved

Not supported by N2

Diverse driver strength

Not supported by N2

Diverse driver strength

Not supported by N2

Diverse driver strength

Not supported by N2

Diverse internal pull-up value

UART RTS Input35

VCC level (3.6 V typ.)

Internal pull-up: ~78 k

Diverse level (V_INT vs VCC); Diverse

internal pull-up value; Diverse

functions supported.

UART CTS Output35

VCC level (3.6 V typ.)

Driver strength: 1 mA

Configurable as Ring Indicator or

Network Indicator

Diverse level (V_INT vs VCC)

Diverse driver strength.

Diverse functions supported.

35 Not supported by “00”, “01”, SARA-R410M-02B-00 product versions and SARA-N2 modules

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No

SARA-G3

Pin Name

Description

12

TXD

13

RXD

14

15

PWR_ON

SARA-U2

Pin Name

TXD

RXD

SARA-R4

Pin Name

TXD

RXD

Description

UART Data Input

V_INT level (1.8 V)

Internal pull-up/-down: ~100k

UART Data Output

V_INT level (1.8 V)

Driver strength: 2 mA

SARA-N2

Pin Name

TXD

Description

UART Data Input

VCC level (3.6 V typ.)

No internal pull-up/-down

UART Data Output

VCC level (3.6 V typ.)

Driver strength: 1 mA

Ground

Reserved

RXD

GND

RSVD

GND

Ground

GND

Ground

GND

Ground

PWR_ON

PWR_ON

UART Data Input

V_INT level (1.8 V)

Internal pull-up:~18 k

UART Data Output

V_INT level (1.8 V)

Driver strength: 6 mA

Power-on Input

No internal pull-up

L-level: -0.10 V ÷ 0.65 V

H-level: 2.00 V ÷ 4.50 V

ON L-level time:

5 ms min

OFF L-level pulse time:

Not Available

GPIO (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 6 mA

Reset input

Internal diode & pull-up

L-level: -0.30 V ÷ 0.30 V

H-level: 2.00 V ÷ 4.70 V

Reset L-level pulse time:

50 ms min (G340/G350)

3 s min (G300/G310)

Description

UART Data Input

V_INT level (1.8 V)

Internal pull-up: ~8 k

UART Data Output

V_INT level (1.8 V)

Driver strength: 6 mA

Power-on Input

No internal pull-up

L-level: -0.30 V ÷ 0.65 V

H-level: 1.50 V ÷ 4.40 V

ON L-level pulse time:

50 µs min / 80 µs max

OFF L-level pulse time:

1 s min

GPIO

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 6 mA

Abrupt shutdown/reset input

10 kΩ internal pull-up

L-level: -0.30 V ÷ 0.51 V

H-level: 1.32 V ÷ 2.01 V

Reset L-level pulse time:

50 ms min

13 or 26 MHz Output

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 4 mA

Power-on Input

200 k internal pull-up

L-level: -0.30 V ÷ 0.35 V

H-level: 1.17 V ÷ 2.10 V

ON L-level pulse time:

0.15 s min – 3.2 s max

OFF L-level pulse time:

1.5 s min

GPIO

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 2 mA

Abrupt shutdown input

37 k internal pull-up

L-level: -0.30 V ÷ 0.35 V

H-level: 1.17 V ÷ 2.10 V

OFF L-level pulse time:

10 s min

GPIO

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 2 mA

16

GPIO1 / RSVD

GPIO1

GPIO1

GPIO1

17

18

RSVD

Reserved

VUSB_DET

5 V, USB Supply Detect Input

VUSB_DET

5 V, USB Supply Detect Input

RSVD

Reserved

RESET_N

RESET_N

RESET_N

RESET_N

19

RSVD

Reserved

CODEC_CLK

GPIO6

RSVD

Reserved

Clock / GPIO vs Reserved

20

21

22

GND

GND

GND

Ground

Ground

Ground

GND

GND

GND

Ground

Ground

Ground

GND

GND

GND

Ground

Ground

Ground

GND

GND

GND

Ground

Ground

Ground

SARA-R4/N4 series - System Integration Manual

Remarks for migration

Diverse level (V_INT vs VCC); Diverse

pull-up / pull-down; TestPoint

always recommended

Diverse level (V_INT vs VCC); Diverse

driver strength; TestPoint always

recommended

Not supported by N2; Internal vs No

internal pull-up; Diverse voltage

levels; Diverse timings;

Diverse functions supported;

TestPoint recommended for R4

GPIO

V_INT level (1.8 V)

Configurable as secondary UART

data output: TestPoint

recommended for diagnostic

Diverse driver strength

TestPoint recommended for N2

Reset input

78 k internal pull-up

L-level: -0.30 V ÷ 0.36*VCC

H-level: 0.52*VCC ÷ VCC

Reset L-level pulse time:

500 ns min

USB detection vs Reserved;

TestPoint recommended for U2/R4

Diverse internal pull-up

Diverse voltage levels.

Diverse timings.

Diverse functions supported.

TestPoint always recommended

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No

SARA-G3

Pin Name

Description

23

GPIO2 / RSVD

SARA-U2

Pin Name

GPIO2

Description

SARA-R4

Pin Name

GPIO2

SARA-N2

Pin Name

Description

RSVD

Reserved

Remarks for migration

GPIO vs Reserved

SARA-R4/N4 series - System Integration Manual

GPIO3

GPIO3

GPIO2

Diverse driver strength

25

GPIO4 / RSVD

GPIO4

GPIO4

RSVD

Reserved

GPIO vs Reserved

GPIO

V_INT level (1.8 V)

Default: GNSS supply enable

Driver strength: 1 mA

GPIO

V_INT level (1.8 V)

Default: GNSS data ready

Driver strength: 6 mA

GPIO

V_INT level (1.8 V)

Default: GNSS RTC sharing

Driver strength: 6 mA

I2C Data I/O /

AUX UART in (‘04’ version)

V_INT level (1.8 V)

Open drain

No internal pull-up

I2C Clock Output /

AUX UART out (‘04’ version)

V_INT level (1.8 V)

Open drain

No internal pull-up

SDA

SCL

SDA

SCL

Description

GPIO

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 2 mA

GPIO

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 2 mA

GPIO

V_INT level (1.8 V)

Default: Output/Low

Driver strength: 2 mA

I2C Data I/O36

V_INT level (1.8 V)

Open drain

Internal 2.2 k pull-up

I2C Clock Output36

V_INT level (1.8 V)

Open drain

Internal 2.2 k pull-up

GPIO37

V_INT level (1.8 V)

Default: Pin disabled

Driver strength: 1 mA

I2C Data I/O37

V_INT level (1.8 V)

Open drain

No internal pull-up

I2C Clock Output37

V_INT level (1.8 V)

Open drain

No internal pull-up

Ground

Reserved

Ground

SDA

SCL

GND

RSVD

GND

RSVD

Internal vs No internal pull-up

Internal vs No internal pull-up

USB / AUX UART vs Reserved

TestPoint recommended for SARA-

G3/U2/R4 modules

USB / AUX UART vs Reserved

TestPoint recommended for SARA-

G3/U2/R4 modules

32 kHz Input vs Reserved

USB_D-

USB Data I/O (D-)

High-Speed USB 2.0

USB_D-

USB Data I/O (D-)

High-Speed USB 2.0

RSVD

Reserved

USB_D+

USB Data I/O (D+)

High-Speed USB 2.0

USB_D+

USB Data I/O (D+)

High-Speed USB 2.0

RSVD

Reserved

GND

RSVD

GND

RSVD

Ground

Reserved

Ground

GND

RSVD

GND

RSVD

Ground

Reserved

Ground

It must be connected to GND

It must be connected to GND

It can be connected to GND

It can be connected to GND

GPIO (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Default: GNSS supply enable

Driver strength: 6 mA

GPIO (G340/G350)

32 kHz Output (G300/G310)

V_INT level (1.8 V)

Default: GNSS data ready

Driver strength: 5 mA

GPIO (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Default: GNSS RTC sharing

Driver strength: 6 mA

I2C Data I/O (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Open drain

No internal pull-up

I2C Clock Out (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Open drain

No internal pull-up

Aux UART Data Out

V_INT level (1.8 V)

Aux UART Data In

V_INT level (1.8 V)

Ground

Reserved (G340/G350)

32 kHz Input (G300/G310)

Ground

24

GPIO3 /

32K_OUT

26

SDA /

RSVD

27

SCL /

RSVD

28

RXD_AUX

29

TXD_AUX

30

31

32

33

GND

RSVD /

EXT32K

GND

RSVD

36 Not supported by “00” and “01” product versions

37 Not supported by “02” product versions

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SARA-R4/N4 series - System Integration Manual

No

SARA-G3

Pin Name

Description

34

I2S_WA / RSVD

SARA-U2

Pin Name

I2S_WA

SARA-N2

Pin Name

Description

RSVD

Reserved

Remarks for migration

I2S vs SPI vs Reserved

35

I2S_TXD / RSVD

I2S_TXD

RSVD

Reserved

I2S vs SPI vs Reserved

36

I2S_CLK / RSVD

I2S_CLK

RSVD

Reserved

I2S vs SPI vs Reserved

Description

I2S Word Alignment

V_INT level (1.8 V)

Driver strength: 2 mA

I2S Data Output

V_INT level (1.8 V)

Driver strength: 2 mA

I2S Clock

V_INT level (1.8 V)

Driver strength: 2 mA

SARA-R4

Pin Name

I2S_WA /

SPI_MOSI

I2S_TXD /

SPI_CS

I2S_CLK /

SPI_CLK

Description

I2S Word Alignm38 / SPI MOSI38

V_INT level (1.8 V)

Driver strength: 2 mA

I2S Data Out38 / SPI chip select38

V_INT level (1.8 V)

Driver strength: 2 mA

I2S Clock38 / SPI clock38

V_INT level (1.8 V)

Driver strength: 2 mA

I2S Word Align.(G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Driver strength: 6 mA

I2S Data Output (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

Driver strength: 5 mA

I2S Clock (G340/G350) Reserved

(G300/G310)

V_INT level (1.8 V)

Driver strength: 5 mA

I2S Data Input (G340/G350)

Reserved (G300/G310)

V_INT level (1.8 V)

37

I2S_RXD / RSVD

I2S_RXD

I2S Data Input

V_INT level (1.8 V)

I2S_RXD /

SPI_MISO

I2S Data Input38 / SPI MISO38

V_INT level (1.8 V)

RSVD

Reserved

I2S vs SPI vs Reserved

38

39

40

41

42

43

44

45

46

47

48

49

50

SIM_CLK

1.8V/3V SIM Clock Output

SIM_CLK

1.8V/3V SIM Clock Output

SIM_CLK

1.8V/3V SIM Clock Output

SIM_CLK

1.8V SIM Clock Output

SIM_IO

1.8V/3V SIM Data I/O

Internal 4.7 k pull-up

SIM_IO

1.8V/3V SIM Data I/O

Internal 4.7 k pull-up

SIM_IO

1.8V/3V SIM Data I/O

Internal 4.7 k pull-up

SIM_IO

1.8V SIM Data I/O

Internal 4.7 k pull-up

SIM_RST

1.8V/3V SIM Reset Output

SIM_RST

1.8V/3V SIM Reset Output

SIM_RST

1.8V/3V SIM Reset Output

SIM_RST

1.8V SIM Reset Output

VSIM

1.8V/3V SIM Supply Output

VSIM

1.8V/3V SIM Supply Output

1.8V/3V SIM Supply Output

1.8V SIM Supply Output

SIM_DET

SIM Detection Input

V_INT level (1.8 V)

SIM_DET

SIM Detection Input

V_INT level (1.8 V)

SIM Detection Input

V_INT level (1.8 V)

GND

Ground

GND

Ground

GND

Ground

SPK_P / RSVD

Analog Audio Out (+) / Reserved

RSVD

SPK_N / RSVD

Analog Audio Out (-) / Reserved

RSVD

Microphone Supply Out /

Reserved

RSVD

Reserved

Reserved

Reserved

SDIO_D2

SDIO serial data [2]38

SDIO_CLK

SDIO serial clock38

SDIO_CMD

SDIO command38

VSIM

GPIO5

VSIM

RSVD

GND

RSVD

RSVD

RSVD

Reserved

Ground

Reserved

Reserved

Reserved

SIM Detection vs Reserved

Analog Audio vs SDIO vs RSVD

Analog Audio vs SDIO vs RSVD

Analog Audio vs SDIO vs RSVD

Microphone Ground / Reserved

RSVD

Reserved

SDIO_D0

SDIO serial data [0]38

RSVD

Reserved

Analog Audio vs SDIO vs RSVD

RSVD

Reserved

SDIO_D3

SDIO serial data [3]38

RSVD

Reserved

Analog Audio vs SDIO vs RSVD

RSVD

Reserved

SDIO_D1

SDIO serial data [1]38

RSVD

Reserved

Analog Audio vs SDIO vs RSVD

GND

Ground

GND

Ground

GND

Ground

GND

Ground

MIC_BIAS /

RSVD

MIC_GND /

RSVD

MIC_N / RSVD

MIC_P / RSVD

Analog Audio In (-) /

Reserved

Analog Audio In (+) /

Reserved

38 Not supported by “00”, “01” and “x2” product version

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No

SARA-G3

Pin Name

Description

51-53

VCC

SARA-U2

Pin Name

VCC

Description

SARA-R4

Pin Name

VCC

Description

SARA-N2

Pin Name

VCC

Description

Module Supply Input

Normal op. range:

3.35 V – 4.5 V

Extended op. range:

3.00 V – 4.5 V

Current consumption:

~2.0A pulse current in 2G

Switch-on applying VCC

Module Supply Input

Normal op. range:

3.3 V – 4.4 V

Extended op. range:

3.1 V – 4.5 V

Current consumption:

~2.0A pulse current in 2G

Switch-on applying VCC

Module Supply Input

Normal op. range:

3.2 V – 4.2 V

Extended op. range:

3.0 V – 4.3 V

Current consumption:

~2.0A pulse current in 2G

(recommended ≥100uF)

~0.5A LTE pulse current

(recommended ≥10uF)

No turn-on applying VCC

SARA-R4/N4 series - System Integration Manual

Module Supply Input

Normal op. range:

3.1 V – 4.0 V

Extended op. range:

2.75 V – 4.2 V

Current consumption:

~0.3A LTE pulse current

(recommended ≥100uF)

Switch-on applying VCC

Remarks for migration

Diverse voltage levels.

Diverse current consumption.

Recommended external capacitors

and other parts for EMI suppression

may differ.

Regular pF / nF recommended.

Diverse functions supported.

54-55

GND

Ground

56

ANT

RF Antenna I/O

57-61

GND

Ground

GND

ANT

GND

RF Antenna I/O

Ground

Ground

GND

ANT

GND

RF Antenna I/O

Ground

Ground

GND

ANT

GND

Ground

Ground

RF Antenna I/O

Diverse bands supported

62

ANT_DET / RSVD Antenna Detection Input /

Reserved

ANT_DET

Antenna Detection Input

ANT_DET

Antenna Detection Input

ANT_DET

Antenna Detection Input39

Antenna Detection vs Reserved

63-96

GND

Ground

GND

Ground

GND

Ground

GND

Ground

Table 41: SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 series modules pin assignments with remarks for migration

☞☞☞☞

For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the SARA-G3, SARA-U2, SARA-R4/N4 and SARA-N2 series cellular

modules, see the related Data Sheet [1], [18], [19], [20], the related System Integration Manual [21], [22], and the Nested Design Application Note [23].

39 Not supported by “02” product version

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SARA-R4/N4 series - System Integration Manual

B Glossary

Abbreviation

Definition

E-UTRA

Evolved Universal Terrestrial Radio Access

Federal Communications Commission United States

2nd Generation Cellular Technology (GSM, GPRS, EGPRS)

3rd Generation Cellular Technology (UMTS, HSDPA, HSUPA)

AT Command Interpreter Software Subsystem, or attention

3rd Generation Partnership Project

8 Phase-Shift Keying modulation

Analog to Digital Converter

Category

European Conformity

Direct Current

Data Communication Equipment

Display Data Channel interface

Down-Link (Reception)

Data Terminal Equipment

Enhanced Data rates for GSM Evolution (EGPRS)

Extended Discontinuous Reception

Enhanced General Packet Radio Service (EDGE)

Electro-Magnetic Compatibility

Electro-Magnetic Interference

Electro-Static Discharge

Equivalent Series Resistance

Frequency Division Duplex

Firmware Over AT commands

Firmware Over The Air

File Transfer Protocol

Firmware

Global Certification Forum

Gaussian Minimum-Shift Keying modulation

Ground

Global Navigation Satellite System

General Purpose Input Output

General Packet Radio Service

Global Positioning System

Human Body Model

HyperText Transfer Protocol

Hardware

Federal Telecommunications Institute Mexico

Inter-Integrated Circuit interface

Inter IC Sound interface

Innovation, Science and Economic Development Canada

2G

3G

3GPP

8-PSK

ADC

AT

Cat

CE

DC

DCE

DDC

DL

DTE

EDGE

eDRX

EGPRS

EMC

EMI

ESD

ESR

FCC

FDD

FOAT

FOTA

FTP

FW

GCF

GMSK

GND

GNSS

GPIO

GPRS

GPS

HBM

HTTP

HW

IFT

I2C

I2S

ISED

LDO

LGA

LNA

Low-Dropout

Land Grid Array

Low Noise Amplifier

LPWA

Low Power Wide Area

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SARA-R4/N4 series - System Integration Manual

Abbreviation

Definition

Long Term Evolution

Open Mobile Alliance Lightweight Machine-to-Machine protocol

Machine-to-Machine

Message Queuing Telemetry Transport

Original Equipment Manufacturer device: an application device integrating a u-blox cellular module

Product Change Notification / Sample Delivery Note / Information Note

LTE

LWM2M

M2M

MQTT

N/A

NAS

OEM

OTA

PA

PCM

PCN

PFM

PSM

PTCRB

PWM

QPSK

RAT

RF

RSE

RTC

SAW

SDIO

SIM

SMS

SPI

SRF

SSL

TBD

TCP

TDD

TIS

TP

TRP

UART

UDP

UICC

UL

UMTS

USB

VoLTE

VSWR

Not Applicable

Non Access Stratum

Over The Air

Power Amplifier

Pulse Code Modulation

Pulse Frequency Modulation

Power Saving Mode

PCS Type Certification Review Board

Pulse Width Modulation

Quadrature Phase Shift Keying

Radio Access Technology

Radio Frequency

Radiated Spurious Emission

Real Time Clock

Surface Acoustic Wave

Secure Digital Input Output

Subscriber Identification Module

Short Message Service

Serial Peripheral Interface

Self-Resonant Frequency

Secure Socket Layer

To Be Defined

Transmission Control Protocol

Time Division Duplex

TDMA

Time Division Multiple Access

Total Isotropic Sensitivity

Test-Point

Total Radiated Power

Universal Asynchronous Receiver-Transmitter

User Datagram Protocol

Universal Integrated Circuit Card

Up-Link (Transmission)

Universal Mobile Telecommunications System

Universal Serial Bus

Voice over LTE

Voltage Standing Wave Ratio

Table 42: Explanation of the abbreviations and terms used

UBX-16029218 - R13

Appendix

Page 116 of 119

SARA-R4/N4 series - System Integration Manual

Related documents

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

u-blox SARA-R4/N4 series Data Sheet, document number UBX-16024152

u-blox SARA-R4/N4 series AT Commands Manual, document number UBX-17003787

u-blox EVK-R4/N4 User Guide, document number UBX-16029216

Universal Serial Bus Revision 2.0 specification, https://www.usb.org/

ITU-T Recommendation V.24 - 02-2000 - List of definitions for interchange circuits between Data Terminal

Equipment (DTE) and Data Circuit-terminating Equipment (DCE),

http://www.itu.int/rec/T-REC-V.24-200002-I/en

3GPP TS 27.007 - AT command set for User Equipment (UE)

3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for

Short Message Service (SMS) and Cell Broadcast Service (CBS)

3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol

I2C-bus specification and user manual - UM10204 - NXP Semiconductors, https://www.nxp.com/docs/en/user-

guide/UM10204.pdf

[10] GSM Association TS.09 - Battery Life Measurement and Current Consumption Technique,

https://www.gsma.com/newsroom/wp-content/uploads//TS.09-v10.2.pdf

[11] 3GPP TS 51.010-1 - Mobile Station conformance specification; Part 1: Conformance specification

[12] 3GPP TS 51.010-2 - Technical Specification Group GSM/EDGE Radio Access Network; Mobile Station (MS)

conformance specification; Part 2: Protocol Implementation Conformance Statement (PICS)

[13] 3GPP TS 36.521-1 - Evolved Universal Terrestrial Radio Access; User Equipment conformance specification; Radio

transmission and reception; Part 1: Conformance Testing

[14] 3GPP TS 36.521-2 - Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment conformance

specification; Radio transmission and reception; Part 2: Implementation Conformance Statement (ICS)

[15] 3GPP TS 36.523-2 - Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Packet Core (EPC); User

Equipment conformance specification; Part 2: Implementation Conformance Statement (ICS)

[16] u-blox End user test Application Note, document number UBX-13001922

[17] u-blox Package Information Guide, document number UBX-14001652

[18] u-blox SARA-G3 series Data Sheet, document number UBX-13000993

[19] u-blox SARA-U2 series Data Sheet, document number UBX-13005287

[20] u-blox SARA-N2 series Data Sheet, document number UBX-15025564

[21] u-blox SARA-G3/SARA-U2 series System Integration Manual, document num. UBX-13000995

[22] u-blox SARA-N2 series System Integration Manual, document number UBX-17005143

[23] u-blox Nested Design Application Note, document number UBX-16007243

☞☞☞☞

For regular updates to u-blox documentation and to receive product change notifications, register on our homepage

(www.u-blox.com).

UBX-16029218 - R13

Related documents

Page 117 of 119

SARA-R4/N4 series - System Integration Manual

Revision history

Revision

Date

31-Jan-2017

Name

sfal

Comments

Initial release

05-May-2017

sfal / sses

Updated supported features and characteristics

24-May-2017

19-Jul-2017

17-Aug-2017

30-Oct-2017

04-Jan-2018

sses

sses

sses

sses

sses

Extended document applicability to SARA-R410M-01B product version

Updated supported features and electrical characteristics

Updated supported features and electrical characteristics

Added FCC and ISED info for SARA-R410M-01B modules

Extended document applicability to SARA-R410M-02B product version

Updated supported features for “02” product version

Updated supported features for “02” product version

Updated SARA-R410M-02B product status

R08

26-Feb-2018

sses

R09

10-Aug-2018

sses

R10

20-Sep-2018

lpah / sses

R11

20-Feb-2019

sses

R12

14-Jun-2019

sses

R13

06-Aug-2019

sses

Updated USB, Power Saving and GPIO features description; Improved Power-on sequence

guidelines description; Added I2C design guidelines description

Updated SARA-R410M-02B product status

Extended document applicability to SARA-R412M-02B product version

Corrected power-on sequence description; Corrected UART MUX description

Extended document applicability to SARA-R410M-52B and SARA-N410-02B product versions

Updated SARA-R410M-02B and SARA-R412M-02B product status;

Updated features support plan for the product versions; Clarified supported bands;

Updated UART TXD and CTS info; Updated Approvals info and related remarks; Added

description of AT Inactivity Timer to enter power saving mode; Other minor corrections

Extended document applicability to SARA-R404M-00B-01 type number

Clarified mode supported in frequency bands

Added further guidelines for VCC and Antenna circuits design

Updated SARA-N410-02B and SARA-R412M-02B product status

Revised supported bands; Updated certification info; Clarified VCC and RESET_N guidelines;

Other minor corrections and clarifications

Extended document applicability to product versions SARA-R410M-02B-01, SARA-R410M-

52B-01 and SARA-R412M-02B-01.

Revised product description, approvals and other info according to extension of document

applicability.

Other minor corrections and clarifications.

Extended document applicability to product versions SARA-R410M-03B, SARA-R410M-63B,

SARA-R410M-73B, and SARA-R412M-03B.

Revised product description, approvals and other info according to extension of document

applicability.

Other minor corrections and clarifications.

R01

R02

R03

R04

R05

R06

R07

UBX-16029218 - R13

Revision history

Page 118 of 119

SARA-R4/N4 series - System Integration Manual

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