FCC ID: XPYJODYW374 JODY-W354-00A, JODY-W354-20A and JODY-W374- 20A

 

JODY-W3 series Host-based modules with Wi-Fi 6 and Bluetooth 5.3 System integration manual Abstract This document describes the system integration of JODY-W3 series modules. These host-based modules support concurrent dual-band Wi-Fi 802.11n/ac/ax and Bluetooth 5.3 and are designed for both simultaneous and independent operations. JODY-W3 modules include an integrated MAC/baseband processor and RF front-end components of automotive grade. UBX-19011209 - R07 C2-Restricted www.u-blox.com JODY-W3 series - System integration manual Document information Title Subtitle JODY-W3 series Host-based modules with Wi-Fi 6 and Bluetooth 5.3 Document type System integration manual Document number UBX-19011209 Revision and date R07 8-Aug-2022 Disclosure Restriction C2-Restricted Product status Corresponding content status Functional Sample Draft For functional testing. Revised and supplementary data will be published later. In Development /

Prototype Objective Specification Target values. Revised and supplementary data will be published later. Engineering Sample Advance Information Data based on early testing. Revised and supplementary data will be published later. Initial Production Early Production Information Data from product verification. Revised and supplementary data may be published later. Mass Production /

End of Life Production Information Document contains the final product specification. This document applies to the following products:

Product name JODY-W354-A JODY-W374-A JODY-W374 JODY-W377-A JODY-W377 For information about the related hardware, software, and status of listed product types, see the JODY-W3 series data sheet [1]. u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. permitted with the express written permission of u-blox. The information contained herein is provided as is and u-blox assumes no liability for its use. No warranty, either express or The information contained herein is provided as is and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. documents, visit www.u-blox.com. Copyright u-blox AG. Copyright u-blox AG. UBX-19011209 - R07 C2-Restricted Document information Page 2 of 71 JODY-W3 series - System integration manual Contents Document information ................................................................................................................................ 2 Contents .......................................................................................................................................................... 3 1 System description ............................................................................................................................... 6 1.1 Overview ........................................................................................................................................................ 6 1.1.1 Module architecture ........................................................................................................................... 6 1.1.2 Radio interfaces .................................................................................................................................. 7 1.1.3 Power management ........................................................................................................................... 7 1.2 Pin configuration and function ................................................................................................................. 8 1.2.1 Pin attributes ....................................................................................................................................... 8 1.2.2 Pin list .................................................................................................................................................... 9 1.3 Supply interfaces ......................................................................................................................................12 1.3.1 Main supply inputs ...........................................................................................................................12 1.3.2 Regulated DC power supply ............................................................................................................13 1.4 System function interfaces ....................................................................................................................13 1.4.1 Power-up sequence ..........................................................................................................................13 1.4.2 Reset ...................................................................................................................................................14 1.4.3 Power-off sequence ..........................................................................................................................14 1.4.4 Wake-up signals ................................................................................................................................14 1.4.5 Configuration pins ............................................................................................................................15 1.5 Data communication interfaces ............................................................................................................16 1.5.1 SDIO 3.0 interface .............................................................................................................................16 1.5.2 PCIe interface ....................................................................................................................................16 1.5.3 High-speed UART interface ............................................................................................................17 1.5.4 PCM/I2S - Audio interface ...............................................................................................................17 1.6 Coexistence interfaces ............................................................................................................................19 1.6.1 PTA ......................................................................................................................................................19 1.6.2 WCI-2 ...................................................................................................................................................19 1.7 Antenna interfaces ...................................................................................................................................19 1.7.1 Wi-Fi and Bluetooth antennas .......................................................................................................19 1.7.2 Approved antenna designs .............................................................................................................20 1.8 Other remarks ............................................................................................................................................20 1.8.1 Unused pins .......................................................................................................................................20 1.8.2 GPIO usage .........................................................................................................................................20 2 Design-in ................................................................................................................................................ 21 2.1 Overview ......................................................................................................................................................21 2.2 Antenna interfaces ...................................................................................................................................21 2.2.1 RF Transmission line design ..........................................................................................................22 2.2.2 Antenna design .................................................................................................................................23 2.3 Supply interfaces ......................................................................................................................................27 2.3.1 Module supply design ......................................................................................................................27 UBX-19011209 - R07 C2-Restricted Contents Page 3 of 71 JODY-W3 series - System integration manual 2.4 Data communication interfaces ............................................................................................................28 2.4.1 PCI Express ........................................................................................................................................28 2.4.2 SDIO 3.0 ..............................................................................................................................................29 2.4.3 High-speed UART interface ............................................................................................................30 2.5 Other interfaces and notes .....................................................................................................................31 2.6 General high-speed layout guidelines ...................................................................................................31 2.6.1 General considerations for schematic design and PCB floor-planning .................................31 2.6.2 Component placement ....................................................................................................................31 2.6.3 Layout and manufacturing .............................................................................................................31 2.7 Module footprint and paste mask .........................................................................................................32 2.8 Thermal guidelines ...................................................................................................................................33 2.9 ESD guidelines ...........................................................................................................................................34 2.10 Design-in checklists .................................................................................................................................35 2.10.1 Schematic checklist .........................................................................................................................35 2.10.2 Layout checklist ................................................................................................................................35 3 Software ................................................................................................................................................ 36 3.1 Available software packages ..................................................................................................................36 3.1.1 Open-source drivers .........................................................................................................................36 3.1.2 Proprietary drivers ............................................................................................................................36 3.1.3 Additional u-blox software deliverables .......................................................................................37 3.2 Supported kernel versions ......................................................................................................................37 3.3 Driver package structure .........................................................................................................................37 3.4 Software architecture ..............................................................................................................................38 3.4.1 Wi-Fi driver .........................................................................................................................................38 3.4.2 Bluetooth driver .................................................................................................................................39 3.5 Compiling the drivers ...............................................................................................................................40 3.5.1 Prerequisites ......................................................................................................................................40 3.6 Deploying the drivers ................................................................................................................................40 3.6.1 Firmware .............................................................................................................................................41 3.6.2 Configuration utilities ......................................................................................................................41 3.6.3 Additional software requirements ................................................................................................42 3.7 Yocto meta layer .......................................................................................................................................42 3.8 Runtime usage ...........................................................................................................................................43 3.8.1 Device detection ................................................................................................................................43 3.8.2 Driver and firmware loading ............................................................................................................43 3.8.3 Verification .........................................................................................................................................45 3.8.4 Assigning MAC addresses ..............................................................................................................46 3.8.5 Antenna configuration.....................................................................................................................47 3.8.6 Access point ......................................................................................................................................47 3.8.7 Station mode .....................................................................................................................................50 3.8.8 Bluetooth usage ................................................................................................................................51 3.9 Driver debugging .......................................................................................................................................52 3.9.1 Compile-time debug options ..........................................................................................................52 UBX-19011209 - R07 C2-Restricted Contents Page 4 of 71 JODY-W3 series - System integration manual 3.9.2 Runtime debug options ...................................................................................................................52 4 Handling and soldering ..................................................................................................................... 53 4.1 Special ESD handling precautions.........................................................................................................53 4.2 Packaging, shipping, storage, and moisture preconditioning .........................................................53 4.3 Reflow soldering process .........................................................................................................................54 4.3.1 Cleaning ..............................................................................................................................................56 4.3.2 Other notes ........................................................................................................................................56 5 Regulatory compliance ..................................................................................................................... 57 5.1 General requirements ..............................................................................................................................57 5.2 FCC/ISED End-product regulatory compliance ..................................................................................57 5.2.1 Referring to the u-blox FCC/ISED certification ID ......................................................................58 5.2.2 Obtaining own FCC/ISED certification ID ....................................................................................58 5.2.3 Antenna requirements ....................................................................................................................59 5.2.4 Configuration control and software security of end-products ...............................................59 5.2.5 Operating frequencies .....................................................................................................................60 5.2.6 End product labeling requirements ..............................................................................................62 5.3 CE End-product regulatory compliance ...............................................................................................63 5.3.1 Safety standard ................................................................................................................................63 5.3.2 CE Equipment classes .....................................................................................................................63 6 Product testing ................................................................................................................................... 65 6.1 u-blox in-line production testing ............................................................................................................65 6.2 OEM manufacturer production test .....................................................................................................66 Appendix ....................................................................................................................................................... 67 A Reference schematic ......................................................................................................................... 67 B Glossary ................................................................................................................................................. 68 C Wi-Fi transmit output power limits .............................................................................................. 70 Related documents ................................................................................................................................... 71 Revision history .......................................................................................................................................... 72 Contact .......................................................................................................................................................... 72 UBX-19011209 - R07 C2-Restricted Contents Page 5 of 71 JODY-W3 series - System integration manual 1 System description 1.1 Overview JODY-W3 series modules provide complete short range transceiver solutions that can be easily integrated into automotive and industrial applications. The modules are intended for the most advanced in-car infotainment and connectivity systems and deliver the highest data rates in Wi-Fi using advanced Wi-Fi 6 802.11ax technology. JODY-W3 series modules operate in concurrent dual-

bands, Wi-Fi 2.4 and 5 GHz, dual-MAC, and 2x2 MIMO. They also support Bluetooth 5.3 features, like extended advertising, long range, and 2 Mbit/s (PHY) data rate. JODY-W3 series modules are provided in a surface-mount device (SMD) component packages based on the NXP AW690/88Q9098/88W9098 chipsets. The modules require a host processor running on a Linux or Android operating system and connect to the host processor through either PCIe or SDIO for Wi-Fi, high-speed UART for Bluetooth, and PCM/I2S for Bluetooth audio. 1.1.1 Module architecture Table 1Table 2 shows the available antenna and host interface configurations for JODY-W3 series modules. Formatted: Normal Document Reference Variant /

Ordering code JODY-W354-00A JODY-W374-00A, JODY-W374-00B JODY-W377-00A, JODY-W377-00B Antenna configuration Host interfaces ANT0 ANT1 ANT2 5 GHz Wi-Fi and Bluetooth 2.4 GHz and 5 GHz Wi-Fi

2.4 GHz and 5 GHz Wi-Fi 2.4 GHz and 5 GHz Wi-Fi Bluetooth Wi-Fi PCIe PCIe or SDIO Bluetooth UART Table 1: Supported configurations of the JODY-W3 module series Figure 1Figure 1 shows the block diagram for the JODY-W354 and JODY-W374 module variants. Formatted: Normal Document Reference UBX-19011209 - R07 C2-Restricted System description Page 6 of 71 JODY-W3 series - System integration manual Figure 1: JODY-W354 and JODY-W374 block diagram Figure 2 shows the block diagram for the JODY-W377 module variant. Commented [CT1]: In next update of this doc, rework this and similar diagrams using approved corporate colors, Hero, grey, etc. Commented [LB2R1]: This is copied from DS which is the master Commented [MZ3R1]: ROLLOVER Commented [CT4R1]: Revised Commented [LB5R1]: Theres a blob missing on the GPIO arrow. Commented [CT6R1]: Fixed - along with other input from Mario Commented [MZ7]: Same issue with GPIO arrow and spare GPIO port on top right as in figure 1. 2.4 GHz WLAN port B and Bluetooth need to be fixed (see original block diagram in DS) Commented [CT8R7]: Fixed Formatted: Normal Document Reference Figure 2: JODY-377 block diagram JODY-W3 series modules with dedicated LTE coexistence filters (2.4 GHz BPF) are available on request. Coexistence filters are recommended for designs with co-located LTE devices operating in bands 7, 38, 40, or 41. Depending on the design, standard JODY-W3 series modules include ceramic diplexer or LPF filters. Information about which module versions that includes dedicated LTE filter is available in [1]. 1.1.2 Radio interfaces JODY-W3 series modules support Wi-Fi 6 802.11a/b/g/n/ac/ax and Bluetooth 5.3 operations:

JODY-W354 and JODY-W374 provide two antenna ports, one for dual band Wi-Fi (2.4 GHz and 5 GHz) and one for 5 GHz Wi-Fi and Bluetooth. JODY-W377 provides three antenna ports, two for dual band Wi-Fi (2.4 GHz and 5 GHz) and one dedicated for Bluetooth. 1.1.3 Power management JODY-W3 series modules have several operation modes. The operation modes and general guidelines for Wi-Fi and Bluetooth operations are defined in Table 2. General status Power state Description Power-down Not Powered 3V3, VIO, and 1V8 supplies not present or below the operating range: module is switched off. Power Down Asserting PD# while 3V3, VIO, and 1V8 supplies are present powers down the module. This represents the lowest power condition with active voltage rails. All internal clocks are shutdown, and the register and memory states are not maintained. On exiting power down mode, the module is automatically reset and the firmware must be downloaded again to re-enter any of the aforementioned operation modes. Normal operation Active Enables TX/RX data connection with the system running at the specified power consumption. UBX-19011209 - R07 C2-Restricted System description Page 7 of 71 JODY-W3 series - System integration manual General status Power state Description Deep sleep Used in power save modes. Table 2: Description for Wi-Fi power states 1.2 Pin configuration and function 1.2.1 Pin attributes Function: Pin function Pin name: Name of the package pin or terminal Pin number: Package pin numbers associated with each signal Power: Voltage domain that powers the pin Type: Signal type description:

I/O = Input and Output o I = Input o O = Output o o D = Open drain o DS = Differential o PWR = Power o GND = Ground o PU = Internal Pull-Up o PD = Internal Pull-Down o H = High-impedance pin o RF = Radio interface Description: Pin description and notes, including alternate pin functions Active: Pin state in Active mode Power down: Pin state in Power Down mode UBX-19011209 - R07 C2-Restricted System description Page 8 of 71 JODY-W3 series - System integration manual 1.2.2 Pin list Figure 3 and Table 3 show the pin-out of JODY-W3 series modules with the pins grouped by function. Formatted: Normal Document Reference Formatted: Normal Document Reference Figure 3: JODY-W3 series module pin assignments (top view) Function Pin name Pin no. Power Type Description Active Power down Power and ground 3V3 VIO 1V8 GND 2 3 4 1, 5, 19, 20, 22, 23, 25, 27, 28, 30, 31, 49 SDIO host Exposed pins SD_CLK SD_CMD SD_D0 SD_D1

53 52 54 55 UBX-19011209 - R07 C2-Restricted PWR 3.3 V power supply PWR 1.8 V or 3.3 V VIO supply PWR 1.8 V power supply GND GND Ground PWR PWR PWR GND

GND GND Connect to Ground GND

1V8 1V8 1V8 1V8 I I/O I/O I/O SDIO clock input SDIO command line SDIO data line bit [0]

SDIO data line bit [1]

I I/O I/O I/O Tristate Tristate Tristate Tristate System description Page 9 of 71 Function Pin name Pin no. Power Type Description Active Power down JODY-W3 series - System integration manual interface1 SD_D2 SD_D3 BT_UART_TX 50 51 36 1V8 1V8 VIO I/O I/O O Bluetooth host interface Digital audio interface BT_UART_RX 37 VIO I BT_UART_RTS 38 VIO O BT_UART_CTS 39 VIO I PCM_SYNC 15 VIO I/O PCM_CLK 16 VIO I/O PCM_IN 18 VIO I PCM_OUT 17 VIO O GPIO interface GPIO_21 9 WL_HOST_WAKE 10 GPIO_12 11 BT_HOST_WAKE 12 VIO VIO VIO VIO I/O I/O I/O I/O GPIO_31 13 VIO O GPIO_30 14 VIO I SDIO data line bit [2]

SDIO data line bit [3]

BT UART output signal. Connect to Host RX BT UART input signal. Connect to Host TX BT UART request-to-send output signal. Connect to Host CTS BT UART clear-to-send input signal. Connect to Host RTS PCM frame sync. Input if slave, Output if master Alternate function: I2S Word Select PCM clock Input if slave, Output if master Alternate function: I2S bit clock Configuration pin CON[10]

See also Configuration pins. PCM data input Alternate function: I2S data in Configuration pin CON[8]

See also Configuration pins. PCM data output Alternate function: I2S data out Configuration pin CON[9]

See also Configuration pins. GPIO[21]

Wi-Fi wake-up from Module / GPIO[15]

Configuration pin CON[5]

See also Configuration pins. GPIO[12] / UART_DSRn / W_DISABLE2n BT wake-up from Module / GPIO[16]

Configuration pin CON[6]

See also Configuration pins. JTAG_TDO (output) / GPIO[31]

LTE coexistence UART TX2 JTAG_TDI (input) / GPIO[30]

LTE coexistence UART RX21Error! Bookmark not defined.. GPIO_28 GPIO_29 GPIO_2 GPIO_3 GPIO_14 32 33 34 35 85 VIO VIO VIO VIO VIO I/O I/O I/O JTAG_TCK (input) / GPIO[28]

JTAG_TMS (input) / GPIO[29]

GPIO[2] /

PTA external radio state signal (input) I/O GPIO[3]

I/O, PD GPIO[14]

Configuration pin CON[4]

See also Configuration pins. I/O I/O O I O I Tristate Tristate Drive low Tristate Drive high Tristate I/O Tristate I/O Tristate I Tristate O Tristate I/O I/O I/O I/O O I I/O I/O I/O I/O I/O Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate WL_HOST_WAKE 86 VIO I/O Wi-Fi wake-up from Module / GPIO[15]

Configuration pin CON[5]

I/O Tristate 1 SDIO pins not used on JODY-W354 2 LTE coexistence UART not supported in current firmware releases UBX-19011209 - R07 C2-Restricted System description Page 10 of 71 Function Pin name Pin no. Power Type Description Active Power down JODY-W3 series - System integration manual GPIO_13 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_23 GPIO_22 65 66 67 68 69 70 71 BT_HOST_WAKE 87 VIO VIO VIO VIO VIO VIO VIO VIO I/O I/O I/O I/O I/O I/O I/O I/O GPIO_17 88 VIO I/O GPIO_18 89 VIO I/O GPIO_19 90 VIO I/O GPIO_0 GPIO_1 91 92 VIO VIO I/O I/O PCIe host interface PCIE_PME#

40 VIO I/O PCIE_CLKREQ#

41 VIO I/O PCIE_PERST#

42 VIO I/O PCIE_REFCLKN PCIE_REFCLKP PCIE_RDN 43 44 45 1V8 1V8 1V8 PCIE_RDP 46 1V8 PCIE_TDN PCIE_TDP CONFIG[0]

47 48 7 1V8 1V8 1V8 Host interface I I I I O O I See also Configuration pins. Same function as pin 10. GPIO[13] / UART_DTRn GPIO[24]

GPIO[25]

GPIO[26]

GPIO[27]

GPIO[23]

GPIO[22]

Bluetooth wake-up from module /

GPIO[16]

Configuration pin CON[6]

See also Configuration pins. Same function as pin 12. GPIO[17] /

PTA external radio grant signal (output) Configuration pin CON[7]

See also Configuration pins. GPIO[18] /

Independent software reset for Wi-Fi subsystem (input) /

PTA request from the external radio

(input) GPIO[19] /

Independent software reset for Bluetooth subsystem (input) /

PTA external radio priority signal (input) GPIO[0]

GPIO[1] /

Independent software reset for Bluetooth subsystem (input) /

PTA external radio priority signal (input) PCIe wake signal

(input/output, active low) Note: Pull-up required on host side PCIe clock request

(input/output, active low) Note: Pull-up required on host side PCIe host indication to reset the device

(input, active low) Note: Muxed with GPIO[20]

PCIe negative differential clock input PCIe positive differential clock input PCIe negative differential data input Note: place a 220nF coupling capacitor close to host CPU output. PCIe positive differential data input Note: place a 220nF coupling capacitor close to host CPU output. PCIe negative differential data output PCIe positive differential data output Host interface configuration pin See also Configuration pins. I/O I/O I/O I/O I/O I/O I/O I/O Drive high Tristate Drive high Tristate Tristate Drive low Drive high Tristate I/O Tristate I/O Tristate I/O Tristate I/O I/O Drive low Tristate I/O I

I/O Drive high I I I I O O I

Tristate UBX-19011209 - R07 C2-Restricted System description Page 11 of 71 Commented [CT9]: Q. Is it OK to leave these definitions as TBD for Gate 6 releases?

Function Pin name Pin no. Power Type Description Active Power down JODY-W3 series - System integration manual 1V8 1V8 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO I I O O O O O O O O O O O 1V8 I, PU RF RF RF Host interface configuration pin See also Configuration pins. Host interface configuration pin See also Configuration pins. RF Control output low RF Control output high RF Control output low RF Control output high RF Control output low RF Control output high RF Control output low RF Control output high RF Control output low RF Control output high RF Control output low Full Power-down of the chipset

(input, active low) (51 k to 1V8) 0 = full power-down mode 1 = normal operation Antenna signal 0 See also Antenna interfaces Antenna signal 1 See also Antenna interfaces Antenna signal 2 (JODY-W377) Not used (JODY-W354, JODY-W374) See also Antenna interfaces

Do not connect I I O O O O O O O O O O O I RF RF RF

Tristate Tristate Drive low Drive high Drive low Drive high Drive low Drive high Drive low Drive high Drive low Drive high Drive low Drive high through PU

config-

uration CONFIG[1]

CONFIG[2]

RF_CNTL10_N RF_CNTL9_N RF_CNTL8_N RF_CNTL7_N RF_CNLT6_N RF_CNTL5_N RF_CNTL4_N RF_CNTL3_P RF_CNTL2_N RF_CNTL1_P RF_CNTL0_N PD#

RF control3 Clock /

Power-

down Radio ANT0 ANT1 ANT2 Other DNC 8 6 72 73 74 75 78 79 80 81 82 83 84 58 24 29 21 26, 56, 57, 59, 60, 61, 62, 63, 64, 76, 77, 93, 94 Table 3: JODY-W3 series module pinout 1.3 Supply interfaces 1.3.1 Main supply inputs JODY-W3 series modules are powered through the 3V3/VIO/1V8 pins. An integrated Buck converter supplied from the 1V8 generates the core voltage to the embedded systems ASIC. The current consumed through the VIO and 1V8, and 3V3 pins by JODY-W3 series modules can vary by several orders of magnitude depending on the operation mode and state. Current consumption can change from the high current consumption during Wi-Fi transmission at maximum RF power level in connected-mode, to the low current consumption during low power idle-mode with the power saving configuration enabled. For a detailed description on the supply voltage requirements, see the JODY-W3 series data sheet [1]. Commented [MH10]: The chipset internal DC/DC is powered from 1V8. 3V3 is mainly used for the chipset internal PAs. Both, 1V8 and 3V3, change the current consumption depending on the operating mode. Commented [BL11R10]:

3 Not implemented UBX-19011209 - R07 C2-Restricted System description Page 12 of 71 JODY-W3 series - System integration manual Rail 3V3 1V8 VIO Allowable ripple (peak to peak)4 over DC supply Current consumption, peak 30 mVpk-pk 30 mVpk-pk 30 mVpk-pk 1500 mA5 1900 mA5 5 mA Table 4: Summary of voltage supply requirements 1.3.2 Regulated DC power supply JODY-W3 series modules must be powered by a regulated DC power supply, such as an LDO or SMPS. The appropriate type for your design depends on the main power source of the application. SMPS is the ideal choice when the source of the main supply has a significantly higher voltage than that of the JODY-W3 series module. SMPS then provides the best power efficiency for your application and minimizes the current drawn from the main supply source. LDO is a better choice if the main supply voltage is close to the JODY-W3 series module supply voltages. Linear regulators are not recommended to step-down high voltages as these devices dissipate a considerable amount of energy. Commented [MZ13R12]: Ripple Noise according DS:

max. 30 mV Commented [CT14R12]: Outstanding?

Commented [LB15R12]: This has not been verified but I suppose we can keep the values as target. Commented [MZ12]: Preliminary values taken from datasheet When choosing SMPS, ensure that the AC ripple voltage at switching frequency does not violate the requirements specified in Table 4Table 5. Formatted: Normal Document Reference Regardless of the chosen DC power regulator, it is crucial that it can supply the high-peak current consumed by the module. When designing the module supply, a contingency of at least 20% over the stated peak current is recommended. 1.4 System function interfaces 1.4.1 Power-up sequence Figure 4 shows the recommended power-up sequence of a JODY-W3 series module. If the PD# is driven by the host, include some delay so that this signal becomes active some short time after the 3V3/VIO/1V8 supply levels have reached 90% (power good). PD# is pulled up to 1V8 inside the module and, if it is not actively driven by the host, follows the 1V8 supply during power-up sequence. 4 Ripple measured on the power connectors of u-blox EVK. 5 Peak current during concurrent dual band 2x2 operation. UBX-19011209 - R07 C2-Restricted System description Page 13 of 71 JODY-W3 series - System integration manual Commented [BL16]: VPA is voltage domain in 88W9098 on JODY this is 3V3 (VBAT). AVDD is 1V8 VCORE internal voltage Commented [MH17R16]: The right power-up sequence is UBX-19029 Commented [MH18]: VIO must be enable first!

Commented [BL19R18]: updated Commented [MZ20]: Removed: A 32.768 kHz clock signal can be applied to the LPO pin before 3V3 ramp-up, only applicable to professional grade. Commented [CT21R20]: Resolved?

Figure 4: Power sequence of JODY-W3 module During the power up of JODY-W3 series modules, it is good practice to enable VIO first, followed by other supplies shortly thereafter. PD# is ideally held low during start up and released when the power is stable, or later when the module must be turned on. PD# is powered by the 1V8 voltage domain and is connected by a 51 k pull up resistor to 1V8. Power down mode can only be entered through PD# assertion by the host. PD# must be asserted for a minimum of 100 ms. 1.4.2 Reset Although external reset is not a prerequisite for correct operation, it can be asserted by the host controller through PD# in the event of any abnormal module behavior. The PD# pin may be connected to a reset signal from the host. JODY-W3 series modules are reset to a default operating state by any of the following events:

Power on (power good 90%) PD# assert: The device is reset when the PD# input pin is <0.2 V and transitions from low to high A firmware download to the module is required after each reset. For information describing how to download the firmware, see also Software. 1.4.3 Power-off sequence JODY-W3 modules enter Power Down mode when PD# is asserted. After assertion when PD# has reached below 0.2V, the power on 3V3/VIO/1V8 supplies can be removed and the module enters the Power Off mode. 3V3/VIO/1V8 can be switched low simultaneously or with 1V8 leading 3V3. The timing of VIO does not care. 1.4.4 Wake-up signals JODY-W3 series modules provides module-to-host wake-up signals, used to exit the host from any sleep mode over Wi-Fi or Bluetooth. Wake-up signals are powered by the VIO voltage domain. UBX-19011209 - R07 C2-Restricted System description Page 14 of 71 JODY-W3 series - System integration manual Description Wi-Fi Module-to-host wake-up signal (output) / GPIO[15]

Used as configuration pin, see also Configuration pins. Bluetooth Module-to-host wake-up signal (output) / GPIO[16]

Used as configuration pin, see also Configuration pins. Name WL_HOST_WAKE BT_HOST_WAKE I/O I/O I/O Table 5: Wake-up signal definitions 1.4.5 Configuration pins JODY-W3 series modules support configuration pins to set specific parameters following a reset. The definition and function of these configuration pins changes immediately (approx. 1 ms) to their initial function after reset, as described in the pin definitions, Table 3Table 4. The interface combinations associated with each boot option are as follows:

PCIE-UART mode: Commands and data for the Wi-Fi traffic are transferred through the PCIe bus to the module. The Bluetooth traffic uses the high-speed UART interface. SDIO-UART mode: Commands and data for the Wi-Fi traffic is transferred through the SDIO bus to the module. The Bluetooth traffic uses the high-speed UART interface. During boot-up, configuration pins CON[4:10] must be set according to the settings described in Table 6Table 7. No external circuitry is required to set the configuration and these pins can consequently be left unconnected (NC). If these pins are connected, make sure that signals CON[5:10]

are not pulled low and that CON[4] is not pulled high by any external circuitry during boot-up. After boot, CON[4..10] revert to their main function. Configuration bits Pin name Pin number Configuration settings Internal PU/PD CON[10]

CON[9]

CON[8]

CON[7]

CON[6]

CON[5]

CON[4]

PCM_CLK PCM_OUT PCM_IN GPIO_17 16 17 18 88 BT_HOST_WAKE 12, 87 WL_HOST_WAKE 10, 86 GPIO_14 85 1 1 1 1 1 1 0 Weak PU Weak PU Weak PU Weak PU Weak PU Weak PU A 51 k resistor to GND is attached on the module. No external resistor required. Do not pull high during boot-up. Formatted: Normal Document Reference Formatted: Normal Document Reference Table 6: Configuration pins Configuration pins CON[2:0] are used to set the firmware boot options that subsequently select the interfaces used for the Wi-Fi and Bluetooth traffic. With reference to Table 7Table 8, CON[2:0] must be strapped to GND through a 51 k pull-down resistor to set a configuration bit to 0. To set a configuration bit to 1 the pin should not be connected. Commented [MZ22]: I find it better to align width of first 3 columns with table 8 Commented [CT23R22]: Aligned Formatted: Normal Document Reference Configuration bits Pin name Pin number Strap values CON[2:0]

CONFIG[2:0]

CONFIG[2]: 6 CONFIG[1]: 8 CONFIG[0]: 7 0006 011 others Wi-Fi SDIO PCIe Bluetooth UART UART reserved reserved Table 7: Firmware boot options 6 SDIO interface is not supported on JODY-W354 UBX-19011209 - R07 C2-Restricted System description Page 15 of 71 Commented [CT24]: This must refer to the previous section 1.4.5. right?

Commented [LB25R24]: Correct JODY-W3 series - System integration manual 1.5 Data communication interfaces JODY-W3 series modules support PCI express v2.0, SDIO 3.0 and high-speed UART host interfaces. This means that all Wi-Fi traffic is communicated through either PCIe or SDIO by setting the appropriate boot option. The high-speed UART interface between the host and the JODY-W3 series module is used for the Bluetooth traffic. For information about the available host interface configuration options, see also Configuration pins. 1.5.1 SDIO 3.0 interface JODY-W3 series modules include an SDIO device interface that is compatible with the industry-

standard SDIO 3.0 specification (UHS-I, up to 104 Mbyte/s). The host controller uses the SDIO bus protocol to access the Wi-Fi functions. The interface supports 4-bit and 1-bit SDIO transfer modes at the full clock range up to 208 MHz. The modules also support legacy modes like Default Speed (DS) and High-Speed (HS) modes. The SDIO signal voltage is fixed to 1.8 V for Default Speed and High-Speed modes. JODY-W3 modules act as devices on the SDIO bus. Table 8 summarizes the supported bus speed modes. Bus speed mode Max. bus apeed [MB/s]

Max. clock frequency [MHz]

Signal voltage [V]

SDR104 SDR50 DDR50 SDR25 SDR12 HS: High-Speed DS: Default Speed Table 8: SDIO bus speeds 104 50 50 25 12.5 25 12.5 208 100 50 50 25 50 25 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Pull-up resistors are required for all SDIO data and command lines. These pull-up resistors can be provided either externally on the host PCB or internally in the host application processor. Depending on the routing of the SDIO lines on the host, it might be necessary to connect in-series termination resistors to these lines. See also Data communication interfaces. Name SD_CLK SD_CMD SD_D0 SD_D1 SD_D2 SD_D3 I/O I I/O I/O I/O I/O I/O Description SDIO Clock input Remarks SDIO Command line External PU required SDIO Data line bit [0]

External PU required SDIO Data line bit [1]

External PU required SDIO Data line bit [2]

External PU required SDIO Data line bit [3]

External PU required Table 9: SDIO signal definitions SDIO interface pins are powered by the 1V8 voltage domain. 1.5.2 PCIe interface A PCIe v2.0 interface (Gen 2, single lane) is supported in the Wi-Fi section of the chipset. The interface supports link speeds of 2.5 and 5 Gbps. Table 10Table 13 shows the description of the chipset pins. The interface data pins are powered from the 1V8 voltage supply, and the interface GPIOs are powered from VIO. Formatted: Normal Document Reference UBX-19011209 - R07 C2-Restricted System description Page 16 of 71 Name PCIE_PERST#

I/O I PCIE_CLKREQ#

OD PCIE_PME#

OD PCIE_RDN PCIE_RDP PCIE_TDN PCIE_TDP PCIE_REFCLKN PCIE_REFCLKP I I O O I I JODY-W3 series - System integration manual Description Power supply PCIe host indication to reset the device. Active low. Multiplexed with GPIO[20]. PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated. 0 = the clock is required. Active low. An external pull-up resistor on host side is required. PCI wake signal. Active low. An external pull-up resistor on host side is required. PCIe receiver differential pair. 220 nF AC coupling capacitors should be placed close to the host TDN/TDP outputs. PCIe transmitter differential pair. 220 nF AC coupling capacitors are included on the module. PCIe 100 MHz differential clock inputs. HCSL voltage levels. VIO VIO VIO 1V8 1V8 1V8 Table 10: PCIe signal descriptions 1.5.3 High-speed UART interface JODY-W3 series modules support a high-speed Universal Asynchronous Receiver/Transmitter

(UART) interface in compliance with the industry standard 16550 specification. The main features of the UART interface include:

FIFO mode permanently selected for transmit and receive operations Two pins for transmit and receive operations Two flow control pins (RTS/CTS) Supports standard baud rates and high throughput up to 4 Mbps. The default baud rate after Interrupt triggers for low-power, high-throughput operation reset is 115200 baud and 3000000 baud after firmware is loaded. The UART interface operation includes:

Bluetooth firmware upload to the module Bluetooth data Name I/O Description Remarks BT_UART_TX BT_UART_RX BT_UART_RTS BT_UART_CTS O I O I UART TX signal UART RX signal UART RTS signal UART CTS signal Table 11: UART signal description Connect to Host RX Connect to Host TX Connect to Host CTS Connect to Host RTS High-Speed UART signals are powered by the VIO voltage domain. 1.5.4 PCM/I2S - Audio interface JODY-W3 series modules support a bi-directional 4-wire PCM digital audio interface for digital audio communication with external digital audio devices like an audio codec. UBX-19011209 - R07 C2-Restricted System description Page 17 of 71 Commented [MZ26]: Update baud rate when OTP is programmed Commented [MZ27]: Change to 3000000 for ES Commented [CT28R27]: REMINDER only, i.e. ROLLOVER to later release JODY-W3 series - System integration manual The PCM interface supports:

Master and slave mode PCM bit width size of 8 bit or 16 bit Up to four slots with configurable bit width and start positions Short frame and long frame synchronization PCM pins are shared with the I2S interface and can be configured to I2S mode using HCI commands. Name PCM_CLK I/O I/O Description Remarks PCM clock Alternate function: I2S clock Master output. Slave input. Used as configuration pin. See also Configuration pins. PCM_SYNC I/O PCM frame sync Alternate function: I2S word select Master output. Slave input. PCM_IN PCM_OUT I O PCM data in Alternate function: I2S data in PCM data out Alternate function: I2S data out Table 12: PCM digital audio signal descriptions Used as configuration pin. See also Configuration pins. Used as configuration pin. See also Configuration pins. PCM/I2S signals are powered by the VIO voltage domain. UBX-19011209 - R07 C2-Restricted System description Page 18 of 71 JODY-W3 series - System integration manual 1.6 Coexistence interfaces 1.6.1 PTA Pin name Pin number Function Pin type Description GPIO_2 34 EXT_STATE I GPIO_17 GPIO_1 88 92 EXT_GNT EXT_FREQ O I GPIO_19 90 EXT_PRI GPIO_18 89 EXT_REQ Table 13: PTA coexistence interface 1.6.2 WCI-2 I I External radio state input signal External radio traffic direction (Tx/Rx):

1: TX 0: RX External radio grant output signal External radio frequency input signal Frequency overlap between external radio and Wi-Fi:

1: overlap 0: non-overlap This signal is useful when the external radio is a frequency hopping device. External radio priority input signal Priority of the request from the external radio. Can support 1 bit priority (sample once) and 2 bit priority (sample twice). Can also have TX/RX info following the priority info if EXT_STATE is not used. Request from the external radio Pin name Pin number Function Pin type Description GPIO_31 GPIO_30 13 14 WCI2_SOUT WCI2_SIN 0 I WCI-2 output signal WCI-2 input signal Table 14: WCI-2 coexistence interface 1.7 Antenna interfaces 1.7.1 Wi-Fi and Bluetooth antennas JODY-W3 module series support different antenna configurations. JODY-W354 and JODY-W374 have two antenna pins: ANT0 for Wi-Fi 5 GHz and Bluetooth, and ANT1 for dual-band Wi-Fi connectivity. JODY-W377 has three antenna pins: ANT0 and ANT1 for dual-band Wi-Fi, and ANT2 for Bluetooth. Follow these recommendations when developing an antenna interface for JODY-W3 modules:

To minimize the effort on the certification process, consider integrating the u-blox antenna reference design in the end product. The JODY-W3 ANT pins have a nominal characteristic impedance of 50 and must be connected to the external antennas through a 50 transmission line. This is necessary to ensure good RF transmission and reception performance. Good isolation must be provided between the various antennas in the system. It is important to maximize the isolation between antennas operating in the same or adjacent bands. See also the Antenna Integration application note [11]. For instructions on how to design circuits that comply with these requirements, see also Antenna interfaces. UBX-19011209 - R07 C2-Restricted System description Page 19 of 71 JODY-W3 series - System integration manual 1.7.2 Approved antenna designs JODY-W3 modules come with a pre-certified antenna design that can be used to save cost and time during the certification process. To leverage this benefit, customers are required to implement an antenna layout that is fully compliant with the u-blox reference design outlined in this document. Reference design source files are available from u-blox on request.7 For Bluetooth and Wi-Fi operation, JODY-W3 modules have been tested and approved for use with the antennas listed in the JODY-W3 series data sheet [1]. u-blox modules may also be integrated with other antennas. In which case, OEM installers must certify their own designs with the respective regulatory agencies. 1.8 Other remarks 1.8.1 Unused pins JODY-W3 series modules have unconnected (NC) pins that are reserved for future use. These pins must be left unconnected on the application board. 1.8.2 GPIO usage GPIOs are used to connect the JODY-W3 series module to various external devices. Table 15 shows the typical assignments for some of the GPIO pins. Other GPIO signals shown in Table 15 have not yet been assigned by the chip manufacturer. The exact function of these signals is normally dependent on the firmware releases. GPIO GPIO[15]

GPIO[16]

GPIO[18]

GPIO[19]

GPIO[0]

Module pin Function WL_HOST_WAKE Wi-Fi to host wake-up signal BT_HOST_WAKE Bluetooth to host wake-up signal GPIO_18 GPIO_19 GPIO_0 Wi-Fi independent reset Bluetooth independent reset Indicates the sleep mode of the module. Put to test point for debug purpose. Table 15: Assigned GPIO functions Some GPIOs are used as configuration pins during boot-up. See also Configuration pins. 7 Reference design will be available after certification. UBX-19011209 - R07 C2-Restricted System description Page 20 of 71 JODY-W3 series - System integration manual 2 Design-in Follow the design guidelines stated in this chapter to optimize the integration of JODY-W3 series modules in the final application board. 2.1 Overview Although every application circuit must be properly designed, there are several points that require special attention during application design. A list of these points, in order of importance, follows:

Module antenna connection: ANT0, ANT1 and ANT2 pins. Antenna circuits affect the RF compliance of all applications that include the certification schemes supported by JODY-W3 modules. To maintain compliance and subsequent certification of the application design, it is important to observe the antenna schematic and layout design for Antenna interfaces. Module supply: 3V3, 1V8, VIO, and GND pins. Supply circuits can affect the RF performance. It is important to observe the schematic and layout design for Supply interfaces. High-speed interfaces: PCIe, SDIO pins. High-speed interfaces are a potential source of radiated noise that can affect the regulatory compliance standards for radiated emissions. It is important to follow the PCI express, SDIO 3.0 and General high-speed layout guidelines. System functions: PD# and pins shown as Configuration pins. Careful utilization of these pins in the application design is required to guarantee that the voltage level is correctly defined during module boot. It is important to follow the pin recommendations in the General high-speed layout guidelines. Other pins: High-speed UART, PCM, specific signals and NC pins. Careful utilization of these pins is required to guarantee proper functionality. It is important to follow the schematic and design layout recommendations in General high-speed layout guidelines. 2.2 Antenna interfaces JODY-W3 modules provide the following RF interface options for connecting the external antennas:

JODY-W354/JODY-W374 ports:

ANT0 for Wi-Fi 5 GHz and Bluetooth connectivity. ANT1 for 2.4 and 5 GHz Wi-Fi connectivity. JODY-W377 ports:

ANT0 port for 2.4 and 5 GHz Wi-Fi connectivity. ANT1 port for 2.4 and 5 GHz Wi-Fi connectivity. ANT2 for Bluetooth connectivity. ANT ports have a nominal characteristic impedance of 50 . For correct impedance matching these ports must be connected to the respective antenna through a 50 transmission line. Poor termination of ANT pins can result in degraded performance of the module. To optimize the isolation between the antennas and ensure good performance of the application, follow the requirements described in Table 16 and Table 17. According to FCC regulations, the transmission line from the module antenna pin to the physical antenna (or antenna connector on the host PCB) is considered as part of the approved antenna design. Therefore, module integrators must use exactly the antenna reference design used in the module FCC type approval or certify their own design. UBX-19011209 - R07 C2-Restricted Design-in Page 21 of 71 JODY-W3 series - System integration manual 2.2.1 RF Transmission line design RF transmission lines, such as those that connect from ANT pins to their related antenna connectors, must be designed with a characteristic impedance of 50 . Figure 5 shows the design options and the most important parameters for designing a transmission line on a PCB:

Microstrip. A track separated with dielectric material and coupled to a single ground plane. Coplanar microstrip. A track separated with dielectric material and coupled to both the ground plane and side conductor. Stripline. A track separated by dielectric material and sandwiched between two parallel ground planes. The most common configuration for a printed circuit board (PCB) is the coplanar microstrip, as shown in Figure 5. Figure 5: Transmission line trace design Follow these recommendations to design a 50 transmission line correctly:

The designer must provide enough clearance from surrounding traces and ground in the same layer. Generally, the trace to ground clearance should be at least twice that of the trace width. The transmission line should also be guarded by the ground plane area on each side. In the first iteration, calculate the characteristic impedance using tools provided by the layout software. Ask the PCB manufacturer to provide the final values usually calculated using dedicated software and production stack-ups. It is sometimes possible to request an impedance test coupon on side of the panel to measure the real impedance of the traces. Although FR-4 dielectric material can result in high losses at high frequencies, it can still be an appropriate choice for RF designs. In which case, aim to:

o Minimize RF trace lengths to reduce dielectric losses. o If traces longer than few centimeters are needed, use a coaxial connector and cable to reduce losses. o For good impedance control over the PCB manufacturing process, design the stack-up with wide 50 traces with width of at least 200 m. o Contact the PCB manufacturer for specific tolerance of controlled impedance traces. As FR-4 material exhibits poor thickness stability it gives less control of impedance over the trace width. UBX-19011209 - R07 C2-Restricted Design-in Page 22 of 71 JODY-W3 series - System integration manual For PCBs with components larger than 0402 and dielectric thickness below 200 m, add a keep-out, that is, some clearance (void area) on the ground reference layer below any pin on the RF transmission lines. This helps to reduce the parasitic capacitance to ground. Route RF lines in 45 angle and avoid acute angles. The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible. Add GND stitching vias around transmission lines, as shown in Figure 6. Provide a sufficient number of vias on the adjacent metal layer. Include a solid metal connection between the adjacent metal layer on the PCB stack-up to the main ground layer. To avoid crosstalk between RF traces and Hi-impedance or analog signals, route RF transmission lines as far from noise sources (like switching supplies and digital lines) and any other sensitive circuit. Avoid stubs on the transmission lines. Any component on the transmission line should be placed with the connected pin located over the trace. Also avoid any unnecessary components on RF traces. Figure 6: RF trace and ground design example 2.2.2 Antenna design At the start the application design phase, when the mechanical design and the physical dimensions of the board are still under analysis/decision, the antenna integration shall be considered. This since the compliance and subsequent certification of the RF design depends heavily on the radiating performance of the antennas. To ensure that the RF certification of JODY-W3 modules is extended through to the application design, it is important to carefully follow the guidelines outlined below. External antennas, including, linear monopole classes:

o Place the module and antenna in any convenient area on the board. External antennas do not impose any restriction on where the module is placed on the PCB. o Select antennas with an optimal radiating performance in the operating bands. The radiation performance depends mainly on the antennas. o Choose RF cables that offer minimum insertion loss. Unnecessary insertion loss is introduced by low quality or long cables. Large insertion losses reduce radiation performance. o Use a high-quality 50 coaxial connector for proper PCB-to-RF-cable transition. Commented [MZ29]: Style of List Paragraph 2nd level is broken. FOr some reason Word keeps changing the default styles from the template. Please fix UBX-19011209 - R07 C2-Restricted Design-in Page 23 of 71 JODY-W3 series - System integration manual Integrated antennas, such as patch-like antennas:

o Internal integrated antennas impose some physical restrictions on the PCB design:

Integrated antennas excite RF currents on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna; its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that has to be radiated, given that the orientation of the ground plane related to the antenna element must be considered.

- Make the RF isolation between the system antennas as high as possible, and the correlation between the 3D radiation patterns of the two antennas as low as possible. In general, RF separation of at least a quarter wavelength between the two antennas is required to achieve a minimum isolation and low pattern correlation. If possible, increase the separation to maximize the performance and fulfill the requirements in Table 16.

- Find a numerical example to estimate the physical restrictions on a PCB, where:

Frequency = 2.4 GHz Wavelength = 12.5 cm Quarter wavelength = 3.5 cm in free space or 1.5 cm on a FR4 substrate PCB. o Choose antennas with optimal radiating performance in the operating bands. Radiation performance depends on the complete product and antenna system design, including the mechanical design and usage of the product. Table 16 summarizes the requirements for the antenna RF interface. Item Impedance Requirements Remarks 50 nominal characteristic impedance The impedance of the antenna RF connection must match the 50 impedance of Antenna pins. Frequency Range 2400 2500 MHz 5150 5850 MHz For 802.11b/g/n/ax and Bluetooth. For 802.11a/n/ac/ax. Return Loss S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable Efficiency

> -1.5 dB ( > 70% ) recommended

> -3.0 dB ( > 50% ) acceptable Maximum Gain Table 16: Summary of antenna interface requirements The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the primary antenna RF connection matches the 50 characteristic impedance of antenna pins. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of antenna pins over the operating frequency range, to maximize the amount of power transferred to the antenna. The radiation efficiency is the ratio of the radiated power to the power fed to the antenna input: the efficiency is a measure of how well an antenna receives or transmits. The maximum antenna gain must not exceed the value specified in type approval documentation to comply with regulatory agencies radiation exposure limits. Table 17Table 18 specifies additional requirements for implementing a dual antenna design. Formatted: Normal Document Reference Item Isolation

(in-band) Requirements Remarks S21 > 30 dB recommended Isolation

(out-of-band) S21 > 35 dB recommended S21 > 30 dB acceptable The antenna-to-antenna isolation is the S21 parameter between the two antennas in the band of operation. Lower isolation might be acceptable depending on use-

case scenario and performance requirements. Out-of-band isolation is evaluated in the band of the aggressor. This ensures that the transmitting signal from the other radio is sufficiently attenuated by the receiving antenna. It also avoids any saturation and intermodulation effect on the receiver port. UBX-19011209 - R07 C2-Restricted Design-in Page 24 of 71 JODY-W3 series - System integration manual Item Requirements Remarks Envelope Correlation Coefficient (ECC) ECC < 0.1 recommended ECC < 0.5 acceptable The ECC parameter correlates the far field parameters between antennas in the same system. A low ECC parameter is fundamental in improving the performance of MIMO-based systems. Table 17: Summary of Wi-Fi/Bluetooth coexistence requirements When operating dual antennas in the same 2.4 GHz band, sufficient isolation is critical for attaining an optimal throughput performance in Wi-Fi/Bluetooth coexistence mode. Select antennas that provide:

Optimal return loss (or VSWR) over all the operating frequencies. Optimal efficiency figure over all the operating frequencies. An appropriate gain that does not exceed the regulatory limits specified in some regulatory country authorities like the FCC in the United States. It is recommended to add pads for a PI-filter for impedance tuning optimization on the antenna trace if later needed. A useful approach for the antenna micro-strip design is to place an U.FL connector close to the embedded PCB or chip antenna. The U.FL connector only needs to be mounted on units used for verification. 2.2.2.1 RF connector design If an external antenna is required, the designer should consider using a proper RF connector. It is the responsibility of the designer to verify the compatibility between plugs and receptacles used in the design. Table 18Table 19 suggests some RF connector plugs that can be used by the designers to connect RF coaxial cables based on the declaration of the respective manufacturers. The Hirose U.FL-R-SMT RF receptacles (or similar parts) require a suitable mated RF plug from the same connector series. Due to wide usage of this connector, several manufacturers offer compatible equivalents. Manufacturer Series Hirose I-PEX Tyco U.FL Ultra Small Surface Mount Coaxial Connector MHF Micro Coaxial Connector UMCC Ultra-Miniature Coax Connector Amphenol RF AMC Amphenol Micro Coaxial Lighthorse Technologies, Inc. IPX ultra micro-miniature RF connector Table 18: U.FL compatible plug connector Remarks Recommended Typically, the RF plug is available as a cable assembly. Different types of cable assembly are available;

the user should select the cable assembly best suited to the application. The key characteristics are:

RF plug type: Select U.FL or equivalent Nominal impedance: 50 Cable thickness: Typically from 0.8 mm to 1.37 mm. Select thicker cables to minimize insertion loss Cable length: Standard length is typically 100 mm or 200 mm; custom lengths may be available on request. Select shorter cables to minimize insertion loss. RF connector on the other side of the cable: for example another U.FL (for board-to-board connection) or SMA (for panel mounting) UBX-19011209 - R07 C2-Restricted Design-in Page 25 of 71 Formatted: Normal Document Reference JODY-W3 series - System integration manual Consider that SMT connectors are typically rated for a limited number of insertion cycles. In addition, the RF coaxial cable may be relatively fragile compared to other types of cables. To increase application ruggedness, connect U.FL connector to a more robust connector such as SMA fixed on panel. A de-facto standard for SMA connectors implies the usage of reverse polarity connectors (RP-

SMA) on end-user accessible Wi-Fi and Bluetooth interfaces to increase the difficulty to replace the antenna with higher gain versions and exceed regulatory limits. The following recommendations apply for proper layout of the connector:

Strictly follow the connector manufacturers recommended layout. Some examples are provided below:

o SMA Pin-Through-Hole connectors require GND keep-out (that is, clearance, a void area) on all the layers around the central pin up to annular pins of the four GND posts. o U.FL surface mounted connectors require no conductive traces (that is, clearance, a void area) in the area below the connector between the GND land pins. In case of that the connectors RF pin size is wider than the microstrip, the GND layer beneath the RF connector shall be removed to minimize the stray capacitance and thus keeping the RF line to 50 . For example, the active pin of the UF.L connector must have a GND keep-out (also called void area) on at least the first inner layer. This to reduce parasitic capacitance to ground. A layout example of the U.FL connector is shown in Figure 7. See also the Antenna integration application note [11]. Figure 7: U.FL connector layout example with pi-matching components placed on top of micro-strip 2.2.2.2 Integrated antenna design If integrated antennas are used, the transmission line is terminated by the antennas themselves. Follow the guidelines given below:

The antenna design process should start together with the mechanical design of the product. PCB mock-ups are useful in estimating overall efficiency and radiation path of the intended design during early development stages. Use antennas designed by an antenna manufacturer providing the best possible return loss (or VSWR). Provide a ground plane large enough according to the related integrated antenna requirements. The ground plane of the application PCB may be reduced to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that has to be radiated, however overall antenna efficiency may benefit from larger ground planes. Proper placement of the antenna and its surroundings is also critical for antenna performance. Avoid placing the antenna close to conductive or RF-absorbing parts such as metal objects or ferrite sheets as they may absorb part of the radiated power, shift the resonant frequency of the antenna or affect the antenna radiation pattern. UBX-19011209 - R07 C2-Restricted Design-in Page 26 of 71 Commented [CT30]: Replace with a larger image with better resolution. Commented [LB31R30]: More detailed image is available in antenna reference doc. Commented [CT32R30]: Added image description with tentative link. Please check (several doc placeholders still need to be added to the Reference list (see later comment). JODY-W3 series - System integration manual It is highly recommended to strictly follow the specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and matching circuitry. Further to the custom PCB and product restrictions, antennas may require tuning/matching to reach the target performance. It is recommended to plan measurement and validation activities with the antenna manufacturer before releasing the end-product to manufacturing. The receiver section may be affected by noise sources like hi-speed digital busses. Avoid placing the antenna close to busses as DDR or consider taking specific countermeasures like metal shields or ferrite sheets to reduce the interference. Take care of interaction between co-located RF systems like LTE sidebands on 2.4 GHz band. Transmitted power may interact or disturb the performance of JODY-W3 modules where specific LTE filter is not present. 2.3 Supply interfaces 2.3.1 Module supply design Though the GND pins are internally connected, it is recommended to connect all the available ground pins to solid ground on the application board as a good (low impedance) connection to external ground can minimize power loss and improve RF and thermal performance. JODY-W3 modules must be sourced through 3V3, 1V8 and VIO pins with proper DC power supplies that comply with the voltage supply requirements summarized in Table 4. Good connection of the JODY-W3 series module power supply pins with DC supply source is required for accurate RF performance and schematic guidelines are summarized below:

All power supply pins must be connected to an appropriate DC source. Any series component with Equivalent Series Resistance (ESR) greater than a few m should be avoided. Only exceptions to this rule are ferrite beads used for DC filtering, however those parts should be used carefully to avoid instability of the DC/DC supply powering the module and are in general not required. A minimum bulk capacitance of 10 F on the 3V3 rail is required (optionally on 1V8 and VIO) close to the module to help filter current spikes from the RF section and avoid ground bounce. The preferred choice is a ceramic capacitor with X7R or X5R dielectric due to low ESR/ESL. Special care should be taken in the selection of X5R/X7R dielectrics due to capacitance derating vs DC bias voltage. Additional bypass capacitors in the range of 100 nF to 1 F on all supply pins are required for high frequency filtering. The preferred choice is a ceramic capacitor with X7R or X5R dielectric due to low ESR/ESL. Smaller size bypass capacitors should be chosen for the manufacturing process to minimize ESL. This capacitor should be placed as close as possible to the module supply pin. 2.3.1.1 Guidelines for VCC supply circuit design using a switching regulator It is recommended to use a Switched Mode Power Supply (SMPS) when the difference from the available supply rail to the JODY-W3 supply rails allows significant power savings. For example, conversion of a 12 V or greater voltage supply to the nominal 3.3 V value for the 3V3 supply. The characteristics of the SMPS connected to the 3V3 pin should meet the following prerequisites to comply with the module requirements summarized in Table 4. Power capability: The switching regulator together with any additional filter in front of the module must be capable of providing a voltage within the specified operating range. The regulator must also be capable of delivering the specified peak current. UBX-19011209 - R07 C2-Restricted Design-in Page 27 of 71 JODY-W3 series - System integration manual Low output ripple: The switching regulator peak-to-peak Voltage ripple must not exceed the specified limits. This requirement applies both to voltage ripple generated by SMPS operating frequency and to high frequency noise generated by power switching. PWM/PFM mode operation: It is preferable to select regulators with fixed Pulse Width Modulation

(PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and may affect RF performance. If power consumption is not a concern, PFM/PWM mode transitions should be avoided in favor of fixed PWM operation to reduce the peak-to-peak noise on voltage rails. Switching regulators with mixed PWM/PFM mode can be used provided that the PFM/PWM modes and transition between modes complies with the requirements. 2.3.1.2 Guidelines for supply circuit design using a Low Drop-Out (LDO) linear regulator The use of a linear regulator is suggested when the difference from the available supply rail and the 3V3, 1V8 or VIO value is relatively low. The linear regulators provide acceptable efficiency when transforming a supply of less than 5 V to a voltage value within the normal operating range of the module. A linear regulator can be also considered to power the VIO section due to the low current requirements, especially if cascaded from a SMPS-generated low voltage rail. The characteristics of the Low Drop-Out (LDO) linear regulator used to power the voltage rails must meet the following prerequisites to comply with the requirements summarized in Table 4. Power capabilities: The LDO linear regulator with its output circuit must be capable of providing a voltage value to the 3V3, 1V8 or VIO pins within the specified operating range and must be capable of withstanding and delivering the maximum specified peak current while in connected-mode. Power dissipation: The power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range. The worst-case junction temperature can be estimated as shown below:

Where: is the junction-to-ambient thermal resistance of the LDOs package8, is the current consumption of the given voltage rail in continuous TX/RX mode and is the maximum operating temperature of the end product inside the housing. 2.4 Data communication interfaces 2.4.1 PCI Express The PCI Express (Peripheral Component Interconnect Express) bus of JODY-W3 series modules support PCIe v2.0 connectivity at transfer rates up to 5 Gbaud. PCIe differential clock and data pairs are a controlled impedance bus, and the main parameters considered for the track impedance calculation are depicted in Figure 8. Figure 8: Differential pair, generic controlled impedance parameters To guarantee bus signal integrity and avoid EMI issues, the PCIe data lines must follow the recommendations described in Table 19. 8 Thermal dissipation capability reported on datasheets is usually tested on a reference board with adequate copper area (ref. to JESD51 [10]). Junction temperature on a typical PCB may be higher than the estimated value due to the limited space to dissipate the heat. Thermal reliefs on pads also affect the capability of a device to dissipate the heat. UBX-19011209 - R07 C2-Restricted Design-in Page 28 of 71 JODY-W3 series - System integration manual Signal Group Parameter PCIe differential data Single Ended impedance, Differential impedance, Common mode impedance, Impedance control, , , PCB signal attenuation margin Min. 60 0 20%

Bus skew length mismatch on same differential pair Bus skew length mismatch between differential pairs Not required Isolation to other pairs and PCB signals 5*W Typ. Max. Unit 100 50 0 0 + 20%

13,2 0,1 dB mm

Table 19: PCI express bus requirements 2.4.2 SDIO 3.0 The SDIO 3.0 bus supported in JODY-W3 series modules can support a clock frequency up to 208 MHz. Consequently, the modules demand special care to guarantee signal integrity requirements and to minimize EMI issues. The signals should be routed with a single ended impedance of 50 . It is advisable to route all signals in the bus with the same length and have appropriate grounding in the surrounding layers. The total bus length should also be minimized. The layout of the SDIO bus should be implemented so that crosstalk with other parts of the circuit is minimized. This provides adequate isolation between the signals, clock, and surrounding busses/traces. Include an undisrupted return current path in close vicinity to the signal traces. Figure 9Figure 9 shows the suggested application schematic for the SDIO bus in JODY-W3 modules, while Table 20Table 21 summarizes the electrical requirements of the bus. Formatted: Normal Document Reference Formatted: Normal Document Reference Figure 9: SDIO application schematic A small value capacitor in the range of few pF to GND could be considered for SDIO_CLK as an EMI debug option and signal termination. This capacitor should be placed as close as possible to the JODY-W3 clock input pin and can be assembled only for EMI purposes. The capacitor increases the total line capacitance but must not exceed the total capacitance necessary to avoid violating clock rise and degrading the timing specifications. Signal Group Parameter Min. Typ. Max. CLK, CMD, DAT[0:3]

Single ended impedance, 0 50 Unit CLK, CMD, DAT[0:3]

Impedance control DAT[0:3]

Pull-Up range, Rdat 0 10%

0 0 + 10%

10 47 100 k UBX-19011209 - R07 C2-Restricted Design-in Page 29 of 71 JODY-W3 series - System integration manual Signal Group Parameter CMD Pull-Up range, Rcmd CLK, CMD, DAT[0:3]

Series termination (Host side), Rterm9 CLK, CMD, DAT[0:3]

Bus length10 CMD, DAT[0:3]

Bus skew length mismatch to CLK CLK Center to center CLK to other SDIO signals11 CMD, DAT[0:3]

Center to center between signals11 Min. 10 0

-3 4*W 3*W Table 20: SDIO bus requirements Typ. Max. Unit 10 0 50 100

+3 k mm mm JODY-W3 series supports only 1.8 V SDIO signal voltage. A level shifter is needed to connect to a 3.3 V host controller. 2.4.3 High-speed UART interface The high-speed UART interface for the JODY-W3 complies with the HCI UART Transport layer and uses the following settings according to Table 21Table 22. Formatted: Normal Document Reference UART Settings Baud rate default after reset 115200 baud Baud rate default after firmware load 3000000 baud Data bits Parity bit Stop bit Flow Control 8 No parity 1 stop bit RTS/CTS Table 21: HCI UART transport layer settings Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI as HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. When CTS is set to logic level 1 the host/host controller is allowed to send. When CTS is set to logic level 0 the host/host controller is not allowed to send. The use of hardware flow control with RTS/CTS is mandatory. Baud rate 1200 2400 4800 9600 19200 38400 57600 76800 115200 230400 460800 500000 921600 1000000 1382400 1500000 1843200 2000000 2100000 2764800 3000000 Table 22: Possible baud rates for the UART interface After a hardware reset, the UART interface is configured for 115200 baud. When the firmware is loaded, the baud rate is set to 3000000 baud. A host application can change the baud rate for the UART interface with the vendor specific HCI command HCI_CMD_UART_BAUD (OCF 0x0009). For an example of how to change the baud rate, see also Bluetooth usage. hcitool i hci0 cmd 0x3F 0x0009 <4 byte little-endian value for baud rate>

9 Series termination values larger than typical recommended only for addressing EMI issues. 10 Routing should minimize the total bus length. 11 Center to center spacing requirement can be ignored for up to 10 mm of routed length to accommodate BGA escape. UBX-19011209 - R07 C2-Restricted Design-in Page 30 of 71 Commented [MZ33]: Update baud rate when OTP is programmed Commented [MZ34]: Change to 3000000 baud for ES Commented [CT35R34]: ROLLOVER to later (ES) release Commented [MZ36]: Update baud rate when OTP is programmed Commented [MZ37]: Update baud rate when OTP is programmed Commented [MZ38]: Change to 3 000 000 baud for ES Commented [CT39R38]: ROLLOVER to later (ES) release Commented [CT40]: Ambiguous. This looks like a parameter rather than a command. Is it?

If it is a command, its not shown as such in the given example. Commented [CT41R40]: ROLLOVER Commented [CT42]: Ambiguous. See earlier comment ^

Is this referring to the hcitool command given in the example. Commented [CT43R42]: ROLLOVER Commented [CT44]: What does it refer to exactly?

Commented [LB45R44]: This refers to un-used pins. JODY-W3 series - System integration manual The HCI command complete event is generated at the old baud rate. Once the host receives the command complete at the old baud rate, it can switch to the new baud rate and should wait for 5 ms or more before sending any new command. 2.5 Other interfaces and notes All digital pins have internal keeper resistors and can be left open if they are not used. 2.6 General high-speed layout guidelines These general design guidelines are considered as best practices and are valid for any bus present in JODY-W3 modules; the designer should prioritize the layout of higher speed busses. Low-frequency signals are generally not layout critical. One exception is represented by high-impedance traces (such as signals driven by weak pull resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4*W from other busses is recommended. 2.6.1 General considerations for schematic design and PCB floor-planning Verify which signal bus requires termination and add series resistor terminations to the schematics. Carefully consider the placement of the module with respect to antenna position and host processor; RF trace length should be minimized first, followed by SDIO bus length. SDIO bus routing shall be planned to minimize layer-to-layer transition to a minimum. Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning for antenna traces and busses. Verify that the power supply design and power sequence are compliant with JODY-W3 specifications described in System function interfaces. 2.6.2 Component placement Accessory parts like bypass capacitors shall be placed as close as possible to the module to improve filtering capability, prioritizing the placement of the smallest size capacitor close to module pins. Do not place components close to the antenna area. The designer should carefully follow the recommendations of the antenna manufacturer concerning the distance of the antenna in relation to other parts of the system. The designer should also maximize the distance of the antenna to High-frequency busses like DDRs and related components or consider an optional metal shield to reduce interferences that could be picked up by the antenna and subsequently reduce module sensitivity. 2.6.3 Layout and manufacturing Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB trace. Verify the recommended maximum signal skew for differential pairs and length matching of buses. Minimize the routing length; longer traces degrade signal performance. Ensure that maximum allowable length for high-speed busses is not exceeded. Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for proper stack-up definition. RF, analog and digital sections should have dedicated and clearly separated areas on the board. No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna). UBX-19011209 - R07 C2-Restricted Design-in Page 31 of 71 JODY-W3 series - System integration manual It is strongly recommended to avoid digital routing beneath all layers of RF traces. Ground cuts or separation are not allowed below the module. Minimize the length of the RF traces as first priority. Then, minimize bus length to reduce potential EMI issues from digital busses. All traces (Including low speed or DC traces) must couple with a reference plane (GND or power), Hi-speed busses should be referenced to the ground plane. In this case, if the designer needs to change the ground reference, an adequate number of GND vias must be added in the area of transition to provide a low impedance path between the two GND layers for the return current. Hi-Speed busses are not allowed to change reference plane. If a reference plane change is unavoidable, some capacitors should be added in the area to provide a low impedance return path through the different reference planes. Trace routing should keep a distance greater than 3*W from the ground plane routing edge. Power planes should keep a distance from the PCB edge sufficient to route a ground ring around the PCB, the ground ring must then be stitched to other layers through vias. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application baseboard below JODY-W3 series modules. Avoid placing temperature sensitive devices close to the module and provide adequate grounding to transfer the generated heat to the PCB. 2.7 Module footprint and paste mask Figure 10 shows the recommended footprint for JODY-W3 module, bottom view. All dimensions are specified in the data sheet [1]. Figure 10: Recommended footprint for JODY-W3 module, bottom view JODY-W3 have additional pins compared with JODY-W1 and JODY-W2, for future use. Connect these according to the Pin list. UBX-19011209 - R07 C2-Restricted Design-in Page 32 of 71 JODY-W3 series - System integration manual Figure 10 shows the pin layout for the JODY-W3 series module. The proposed land pattern layout reflects the pin layout of the module. Both Solder Mask Defined (SMD) and Non Solder Mask Defined

(NSMD) pins can be used, however the following considerations apply:

Pins 1 to 94 should be NSMD Inner pads must have a good thermal bonding to PCB ground planes to help spreading the heat generated by the module. If NSMD design is chosen for inner pads, thermal reliefs should be considered and 4 or 9 vias per pad must be added for heat sink. Those vias may require copper capping. If SMD design is chosen for inner pads, the land pattern can be flooded on a ground plane beneath the module and vias added around the pads for heat sinking. The suggested stencil layout for the JODY-W3 module is to follow the copper pad layout exactly as described in Figure 10 for the outer pads, while the central pads should implement a special solder paste pattern with the following characteristics:

Solder paste area should be split in several smaller parts, typically four to nine depending on copper pad area. Total solder paste area should cover about 50% to 60% of copper thermal pad area. Total solder paste area must not exceed 65% of copper thermal pad area. Missing to consider solder paste optimization can lead to poor soldering quality in production. A suggested stencil opening implementation is shown in Figure 11. Figure 11: Stencil opening example for inner thermal pads (dimensions in m) The exact mask geometries, distances and stencil thicknesses must be adapted to the specific production process of the customer. 2.8 Thermal guidelines JODY-W3 series modules are designed to operate from -40 C to +85 C at an ambient temperature inside the enclosure box. The board will generate heat during high loads that must be dissipated to sustain the lifetime of the components. The improvement of thermal dissipation in the module decreases its internal temperature and consequently increases the long-term reliability of the device for applications operating at high ambient temperatures. For best performance, recommended layouts should follow the following guidelines:

Vias specification for ground filling: 300/600 , no thermal reliefs are allowed on vias. UBX-19011209 - R07 C2-Restricted Design-in Page 33 of 71 Commented [m46]: Values need to be verified Commented [LB47R46]: This is yet not available Commented [CT48R46]: ROLLOVER to later release?

Commented [MZ49R46]: ROLLOVER Commented [CT50R46]: Have these values now been validated?

JODY-W3 series - System integration manual Ground vias density under the module: 50 /2, thermal vias can be placed in gaps between the thermal pads of the module. Minimum layer count and copper thickness: 4 , 35 . Minimum board size: 5570 . Power planes and signal traces should not cross the layers beneath the module to maximize heat flow from the module. Those recommendations allow the design to achieve a thermal characterization parameter of

= 7.24 /, where refers to the modules junction to main PCB bottom side. Commented [MZ51]: TBD The following additional hardware techniques can be used to improve the thermal performance of the module in customer applications:

Commented [LB52R51]: To be included when simulation results are available Maximize the return loss of the antenna to reduce reflected RF power to the module. Improve the efficiency and the thermal design of any component that generates heat in the application, including power supplies and processor, to spread the generated heat distribution over the application device. Design the mechanical enclosure of the application device properly to provide ventilation and good thermal dissipation. For continuous operation at high temperatures, high-power density applications, or reduced PCB size, the designer can consider including a heat sink on main bottom side of the PCB. The heat sink should be connected using electrically insulated / high thermal conductivity adhesive12. Commented [CT53R51]: This is an old comment Can this be resolved?

Commented [MZ54R51]: This is a reminder that TBD needs to be replaced with some value. ROLLOVER Commented [CT55R51]: Can we set the value here now?

Commented [CT56R51]: Lars has resolved the open comments in 2.4.2, 2.8. and 4.3 2.9 ESD guidelines JODY-W3 modules are manufactured through a highly automated process, which complies with IEC61340-5-1 [6] (STM5.2-1999 Class M1 devices) standard. A manufacturing process on customers manufacturing site that implements a basic ESD control program is considered sufficient to guarantee the necessary precautions13 for handling the modules. The ESD ratings of JODY-W3 module pins are stated in Table 23Table 24. Applicability All pins except ANTx Human Body Model (HBM), ANSA/ESDA/JEDEC JS-001-201415. ANTx pins Human Body Model (HBM), AEC-Q200-002 Rev B. Charged Device Model (CDM), JESD22-C101. Charged Device Model (CDM), JESD22-C101. Table 23: ESD immunity rating for pins of the JODY-W3 module Immunity level14 1000 V 250 V 1000 V 500V The designer must implement proper measures to protect from ESD events on any pin that may be exposed to the end user in compliance with the following European regulations:

ESD testing standard CENELEC EN 61000-4-2 [4]

Radio equipment standard ETSI EN 301 489-1 [5]

The minimum requirements as per these European regulations are summarized in Table 24Table 25. Application Category Immunity level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration of the end product. Contact discharge Air discharge 4 kV 8 kV 12 Typically not required. 13 Minimum ESD protection level for safe handling is specified in JEDEC JEP155 (HBM) and JEP157 (CDM) for 500 V and 250 V respectively. 14 Target values. 15 In compliance with AEC-Q100-002 Rev E requirements. UBX-19011209 - R07 C2-Restricted Design-in Page 34 of 71 Commented [CT57]: Table data for ESD immunity and ESD sensitivity are not shown in table 24. Commented [CT58R57]: ESD immunity: Values are in table 24. These are different from the standard values shown in host-based modules. Formatted: Normal Document Reference Formatted: Normal Document Reference Commented [CT59]: Include x-refs to relevant information in this document - as implemented in MAYA-W1 SIM. Commented [CT60R59]: ROLLOVER Commented [LB61R59]: References added in italic Commented [CT62R59]: Revised to direct x-refs JODY-W3 series - System integration manual Table 24: Minimum ESD immunity requirements based on EN 61000-4-2 Compliance with standard protection level as specified in EN 61000-4-2 [4] can be achieved by including proper ESD protection in parallel to the line and close to areas that are accessible to the end user. Special care should be taken if the ANT pins must be protected by choosing an ESD absorber with adequate parasitic capacitance. For 5 GHz operation, a protection with maximum internal capacitance of 0.1 pF is recommended. 2.10 Design-in checklists 2.10.1 Schematic checklist JODY-W3 module pins are properly numbered and designated on the schematic (including thermal pins). See Pin list. Power supply design complies with the specification. See data sheet [1], section 4.4. The power sequence is properly implemented. See Power-up sequence. Adequate bypassing is present in front of each power pin. See Component placement. Each signal group is consistent with its own power rail supply or proper signal translation has been provided. See Pin list. Configuration pins are properly set at bootstrap. See Configuration pins. SDIO bus includes series resistors and pull-ups. See SDIO 3.0. Unused pins are properly terminated. Wi-Fi and Bluetooth antennas. A pi-filter is provided in front of each antenna for final matching. See Antenna design. RF co-location additional filters have been considered in the design. See Antenna design. 2.10.2 Layout checklist PCB stack-up and controlled impedance traces follow PCB manufacturers recommendation. All pins are properly connected, and the package follows u-blox recommendations for pin design. See data sheet [1], section 6. Proper clearance has been provided between RF section and digital section. See Layout and manufacturing. Proper isolation is provided between Antennas (RF co-location, diversity, MIMO, or multi-antenna design). See Antenna design. Bypass capacitors are placed close to the module. See Component placement. Low impedance power path has been provided to the module. See Module supply design. Controlled impedance traces are properly implemented on the layout (both RF and digital) and follow PCB manufacturer recommendations. See Layout and manufacturing. 50 RF traces and connectors follow the rules in Antenna interfaces. Antenna design has been reviewed by the antenna manufacturer. Proper grounding is provided to the module for low impedance return path and heat sink. See Module supply design. Reference plane skipping is minimized for high frequency busses. See Layout and manufacturing. All traces and planes are routed inside the area defined by the main ground plane. See Layout and manufacturing. u-blox has reviewed and approved the PCB16. 16 This is applicable only for end-products based on u-blox reference designs. UBX-19011209 - R07 C2-Restricted Design-in Page 35 of 71 JODY-W3 series - System integration manual 3 Software The instructions in this chapter describe how to set up the JODY-W3 series module on a Linux operating system. Including several examples, it also describes how the reference driver packages are compiled and deployed in the target system. Commented [MZ63]: Check and document availability of open-source drivers for 9098. The described configuration is based on the proprietary driver for the 88Q9098 chipset family from NXP that has been integrated onto an i.MX 8QuadMax Multisensory Enablement Kit (MEK) from NXP. The board connects to the JODY-W3 series module through the PCIe host interface and uses a USB-

to-UART adapter to connect to the Bluetooth UART resident in the module. Commented [MZ64R63]: PCIe/SDIO to be supported in NXP i.MX Linux BSPs (mass market release). Add information when available. Commented [CT65R63]: ROLLOVER to later release Commented [MZ66]: Update after clarification with NXP The proprietary driver developed by NXP and distributed by u-blox is only made available to customers that have signed a limited use license agreement (LULA-M) [3] with u-blox. The driver package and additional documentation can also be obtained directly from NXP. Open-source drivers for mainstream use are made available free of charge by NXP and are already pre-integrated into the Linux BSPs for the NXP i.MX application processors. See also Open-source drivers. 3.1 Available software packages 3.1.1 Open-source drivers JODY-W3 series modules are based on the NXP 88Q9098 chipset. The drivers and firmware required to operate JODY-W3 series modules are developed by NXP and are already integrated into the Linux BSP for the NXP i.MX application processors [13].17 The documentation for the software releases from NXP contains Wi-Fi and Bluetooth release notes and a list of supported software features. The driver source code is provided free of charge as open source under NXP license terms. Being open source allows the drivers to be integrated or ported to other non-NXP based host platforms. Yocto recipes for the driver (nxp-wlan-sdk, kernel-module-

nxp89xx) and firmware (linux-firmware), that can be used to develop custom Linux-based systems, are part of the NXP i.MX Linux BSP. The latest version of the driver source code and Wi-Fi/Bluetooth firmware are available from the following open-source repositories:

Wi-Fi driver: https://source.codeaurora.org/external/imx/mwifiex/

Firmware: https://github.com/NXP/imx-firmware/

i.MX meta-layer: https://source.codeaurora.org/external/imx/meta-imx/

Field Code Changed Field Code Changed Use the repository branches matching to the latest Linux BSP release version. At the time of publication, this is release 5.15.32_2.0.0. The Wi-Fi driver uses the TCP/IP stack from the Linux kernel for data transmission and the cfg80211 subsystem in the kernel for configuration and control. The hci_uart driver from the Linux kernel and BlueZ host stack are used for the Bluetooth part. For further information about initialization and configuration of the Wi-Fi and Bluetooth features, see also the NXP User Manual UM11490 [14]. 3.1.2 Proprietary drivers As described in Configuration pins, JODY-W3 series modules can be operated through different host interfaces. Each operation mode must use a dedicated host driver package. For information about the various components and the structure of the driver packages, see also Driver package structure. 17 Drivers for PCIE-UART are currently supported. SDIO-UART support is planned for Q1/2022. UBX-19011209 - R07 C2-Restricted Software Page 36 of 71 JODY-W3 series - System integration manual The proprietary NXP driver package is currently available for the PCIE-UART host interface combination (PCIE-WLAN-UART-BT-9098), which uses the PCIe interface to operate Wi-Fi and the UART interface for Bluetooth. The NXP driver packages are typically provided as two different licensing options:

MGPL package: Full source code with GPLv2 license GPL package: Source code with proprietary license except for the part of the Linux driver that binds to the kernel For further information about license usage, see the license texts included in the driver package. 3.1.3 Additional u-blox software deliverables A Yocto/OpenEmbedded meta layer for JODY-W3 is provided by u-blox. See also Yocto meta layer. JODY-W3 series software deliverables are available from your local support team. See Contact. Commented [CT67]: If this is the only software deliverable provided, rework this as a single paragraph rather than a single bullet. 3.2 Supported kernel versions Due to constant changes in the kernel subsystem APIs for different kernel releases, the driver source code must be aligned with each major and minor kernel release. The driver packages have been verified on the following platforms and kernel versions:

Platform NXP i.MX 8 MEK NXP i.MX 8M EVK Renesas Salvator-XS SoC i.MX 8QuadMax i.MX 8mQuad R-Car H3 Kernel version 4.14.98, 5.4.3 4.14.98, 5.4.3 4.14.75 Table 25: Tested Linux kernel versions for the JODY-W3 series modules reference drivers The supplied software package supports Linux kernel from 2.6.32 to 5.13.4. As long as there is no change in the kernel API, this package can also support the latest kernel versions. If there are any changes to the kernel APIs you choose to use, you must make the necessary changes using patches. In case of any discrepancy, contact your local support team. 3.3 Driver package structure The NXP driver packages include different components, depending on the supported host interfaces. The content of the packages is described in Table 26Table 27. Formatted: Normal Document Reference Component Folder Description Release Notes and features

FwImage FwImage PCIE/SDIO-WIFI-*-app-src wlan_src/mapp PCIE/SDIO-WIFI-*-src wlan_src/mlinux PCIE/SDIO-WIFI-*-mlan-src wlan_src/mlan UART-*-src muart_src UART-FW-LOADER-*-src uartfwloader_src Table 26: Components of the NXP driver package Release notes describing all of the supported features, changes and all known issues associated with the release. Binary firmware images. For details about the firmware images, see also Table 27Table 28. Source code for the user space applications necessary to set up the different modes for Wi-Fi operation. Source code for the driver module moal.ko, which implements the Linux-specific part of the Wi-Fi driver. This container also includes the driver, Makefile and README files. Source code for the driver module mlan.ko, which implements the chipset specific functionality of the Wi-Fi driver. Source code for the HCI UART Bluetooth driver module hci_uart.ko. Source code for the fw_loader firmware download tool used to download the Bluetooth firmware over UART in parallel mode. UBX-19011209 - R07 C2-Restricted Software Page 37 of 71 Formatted: Normal Document Reference JODY-W3 series - System integration manual 3.4 Software architecture From the software point of view, JODY-W3 series modules contain only on-board OTP memory with calibration parameters and MAC addresses. Consequently, the modules require a host-side driver and device firmware to run. At startup and at every reset or power cycle, the host driver needs to download the firmware binary file to the module. The host driver interfaces the bus drivers with the upper layer protocol stacks of the operating system. Figure 12 shows the different software components and upper layers required for the operation of JODY-W3 series modules. Figure 12: Basic software overview 3.4.1 Wi-Fi driver The JODY-W3 series software package includes a dedicated Wi-Fi driver that has both Wireless Extension (WEXT) and Netlink-based (nl80211/cfg80211) driver configuration interfaces. The Wi-Fi driver implementation is spread between two kernel modules moal and mlan, where:

moal implements the operating system (OS) specific bindings and handles the standard interfaces from the OS such as the network interface and manages to load the firmware to the JODY-W3 during the initialization phase. mlan implements the chipset specific functions and is independent from the OS. UBX-19011209 - R07 C2-Restricted Software Page 38 of 71 Commented [CT68]: Rework image to:

- use color (hero red, gray, etc) to differentiate between components

- BT to Bluetooth

- Remove title capitalization: Host system

- Capitalize: Firmware

- Centralize: JODY-W3

- Fix inconsistent text style and font size in callout boxes. Commented [CT69R68]: ROLLOVER to later release Commented [CT70R68]: Done Commented [CT71]: Rework this and other images using Hero red and gray corporate colors (next iteration) Commented [CT72R71]: ROLLOVER to later release Commented [CT73R71]: Done Figure 13 shows the basic architecture of the Wi-Fi driver. JODY-W3 series - System integration manual Commented [MZ74]: Top right box should be uaputl/mlanutl/iw/iwconfig

-TCP instead of TCIP

-Common driver interface its not a driver, but an interface for drivers

-Bottom half resides in WLAN firmware, not Host driver

-Box above HAL should be WLAN driver Commented [CT75R74]: Fixed Figure 13: Basic Wi-Fi host driver and firmware architecture 3.4.2 Bluetooth driver The standard Bluetooth protocol stack in Linux is provided by BlueZ. The reference driver package provides a Bluetooth driver for the JODY-W3 series module that performs the following functions:

Data and command forwarding between upper protocol stack layers and the firmware Private command handling used between the driver and firmware handshakes only The host system can access JODY-W3 series Bluetooth logic functions through the UART interface. The Bluetooth driver hci_uart is included in the Linux kernel distribution to which NXP adds additional functionality. We recommend use of the hci_uart driver included in the NXP driver package over the Linux kernel variant. The hci_uart from the kernel must be disabled or compiled as a module. UBX-19011209 - R07 C2-Restricted Software Page 39 of 71 The architecture of the Bluetooth driver and protocol stack is shown in Figure: 14. JODY-W3 series - System integration manual Commented [CT76]: Update schematic:

- change BT to Bluetooth (spell out)

- capitalize "Firmware"

- Use corporate colors and include clearer functional boundaries to more clearly differentiate between the logical components Commented [CT77R76]: ROLLOVER to next release Commented [CT78R76]: Fixed Figure: 14: Bluetooth driver and protocol stack 3.5 Compiling the drivers The README files included in the driver package contain basic steps of the compilation procedure. The recipes in the Yocto/OpenEmbedded meta layer provided by u-blox are used to integrate the software package into Yocto projects. These also make useful references with which to better understand the process of compiling and deploying the software package more fully. See also Yocto meta layer. 3.5.1 Prerequisites The appropriate Wi-Fi driver for use with JODY-W3 series modules depends on the PCI or MMC/SDIO subsystem of the Linux kernel. Consequently, support for the respective subsystem and the correct host controller driver must be enabled in the target kernel configuration of the system. The driver supports the cfg80211 wireless configuration API for configuration management and it must be selected in the kernel configuration using the CONFIG_CFG80211 option. In order to use Bluetooth implementation in the Linux BlueZ stack, the kernel options CONFIG_BT_HCIUART, CONFIG_BT_HCIUART_H4 must be enabled along with other Bluetooth protocols. Prior to building the driver, the kernel needs to be prepared for the compilation of external kernel modules. To do this, change to the source directory of the kernel and run the following command:

$ make modules_prepare 3.6 Deploying the drivers The drivers, firmware and additional software tools can be deployed at reasonable locations in the target root file system. UBX-19011209 - R07 C2-Restricted Software Page 40 of 71 Using the Yocto recipes provided by u-blox, the utilities and modules typically install like this:

JODY-W3 series - System integration manual

etc modprobe.d jody-w3-driver-pcieuart.conf lib firmware nxp jody-w3-pcieuart pcie9098_wlan_v1.bin pcieuart9098_combo_v1.bin uart9098_bt_v1.bin modules 4.14.98-imx[]

updates nxp 88q9098 hci_uart_jody-w3-pcieuart.ko mlan_jody-w3-pcieuart.ko moal_jody-w3-pcieuart.ko opt jody-w3 pcieuart mlanutl uaputl All kernel modules include a package name suffix, which is shown in the example above as jody-w3-pcieuart. The utilities and module files shown in this structure are for the PCIE-

UART variant of the driver package. The structure for other packages will be similar. Refer to the Yocto recipes to learn more about the install path and names of the files. 3.6.1 Firmware JODY-W3 series modules can be configured to download the firmware in two different modes:

Parallel mode: Dedicated interfaces are used to download the firmware for Wi-Fi and Bluetooth radios separately. Serial mode: Wi-Fi host interface is used to download the combo firmware which is applicable to both the radios. Table 27 shows the mapping between the various firmware images and their respective download modes. Firmware image Type of image Download mode Wi-Fi interface Bluetooth interface pcieuart9098_combo_v1.bin Combo (Wi-Fi + Bluetooth) Serial pcie9098_wlan_v1.bin Wi-Fi uart9098_bt_v1.bin Bluetooth sd9098_wlan_v1.bin Wi-Fi Parallel Parallel Parallel sduart9098_combo_v1.bin Combo (Wi-Fi + Bluetooth) Serial Table 27: Firmware images and their respective usage PCIe PCIe

SDIO SDIO UART

UART

UART JODY-W3 series modules must use firmware images that include the suffix _v1 that denotes the A0/A1 revision of the 88Q9098/88W9098 chipset. 3.6.2 Configuration utilities NXP driver package provides the source code for building various applications to configure the different modes and features of the module, including configuration of the firmware embedded supplicant and authenticator functions. UBX-19011209 - R07 C2-Restricted Software Page 41 of 71 Commented [MZ79]: SDIO-SDIO not productized. Keep it for now. Commented [CT80R79]: ROLLOVER to later release Commented [CT81R79]: Has SDIO-SDIO support since been implemented?

Commented [CT82R79]: Mario: 3.4.2/3.6.1: There's a note regarding SDIO support for BT in 1.4.5. It's not clear if this will be supported in the future, but we can keep the instruction in section 3 for now. ROLLOVER JODY-W3 series - System integration manual Application Functionality mlanutl uaputl Features and configuration related to station mode in Wi-Fi Features and configuration related to AP mode in Wi-Fi Table 28: Utilities to configure Wi-Fi modes 3.6.3 Additional software requirements Although the NXP configuration utilities provide the necessary interface to configure features at granular levels, most product vendors prefer open-source applications and stacks. Some additional packages that are recommended for installation on the target system are shown in Table 29Table 30. Formatted: Normal Document Reference Package bluez Comment Contains the user space parts of the Linux Bluetooth stack wpa_supplicant WPA supplicant. Handles key negotiation, like roaming on the client side. iw hostapd crda CLI configuration utility for wireless devices User space daemon for access point and authentication servers User space udev helper to handle regulatory domain Table 29: Recommended additional software packages 3.7 Yocto meta layer Yocto is an open-source project aimed at helping the development of custom Linux-based systems for embedded products. It provides a complete development environment with tools, documentation, and metadata like recipes, classes, and configuration. Yocto is based on the OpenEmbedded build system. A Yocto/OpenEmbedded meta layer, meta-ublox-modules, is provided by u-blox for all host-based modules. This layer is used in Yocto projects to build the image for most host platforms that run Linux kernels. It contains the recipes used to build the Linux drivers, support tools, and any configuration files that are needed to operate the modules. The recipes serve also as an integration example for other build environments. Item Description Build recipe Includes all the instructions to extract, compile and install the drivers, firmware and tools in the root file system of the host system image. Patches Used to fix bugs in ublox-distributed drivers seen either locally or reported by the vendor. Calibration files Calibration files, provided by u-blox, used while loading the driver. These files store the tuning parameters needed for RF parts present in the module, like the crystal. Output power configuration RF power specific files for the different bands, rates and countries are stored in configuration files provided by u-blox. Modprobe rules Configuration files for the modprobe utility used to store the driver load parameters. Manufacturing package recipes Includes different recipes for building the manufacturing tools. These recipes are used in production and RF-related tests. Table 30: Content of the Yocto layer Calibration files are needed for the modules during the prototype stage of development. After prototyping, all required calibrations are programmed into the OTP on the module. Further information about the Yocto layer and how to integrate it into the development environment is provided in the README files of the meta layer. UBX-19011209 - R07 C2-Restricted Software Page 42 of 71 JODY-W3 series - System integration manual 3.8 Runtime usage This section describes how to load specific drivers in different modes and configurations. It also provides examples for operating the module in several typical use-cases, such as station, access-

point, and so on. 3.8.1 Device detection Prior to loading the drivers, make sure that the JODY-W3 series module is detected by the host system. PD# must not be asserted to enable the JODY-W3 series module. The lspci command lists connected PCIe devices in the system. The command output below shows two connected Ethernet controllers for the JODY-W3 series module. A single controller is listed for each of the two radio MACs.

$ lspci 01:00.0 Ethernet controller: Marvell Technology Group Ltd. Device 2b43 (rev 01) 01:00.1 Ethernet controller: Marvell Technology Group Ltd. Device 2b44 (rev 01) When a JODY-W3 series module connects to the host system through the SDIO bus, the event is reported in the kernel log, as shown in the example below. mmc1: new ultra high speed SDR104 SDIO card at address 0001 3.8.2 Driver and firmware loading JODY-W3 series module supports parallel and serial options for downloading the Wi-Fi and Bluetooth radio firmware, as described in Firmware. Although the driver and firmware loading operation is different for each option, the normal Wi-Fi and Bluetooth operation is the same. 3.8.2.1 Serial mode As shown in Table 27, the Wi-F interface is used to download Wi-Fi and Bluetooth combo images in serial mode. The firmware in these combo image includes the code for both the logical Wi-Fi and Bluetooth parts of the chip. In the following example, the Wi-Fi driver modules mlan.ko and moal.ko are inserted into the Linux kernel to download the PCIE-UART combo image. Information about the loaded driver modules is then displayed using the lsmod command:

$ insmod mlan.ko

$ insmod moal.ko fw_name=nxp/pcieuart9098_combo_v1.bin cfg80211_wext=0xf auto_ds=2 ps_mode=2

$ lsmod Module Size Used by moal 655360 0 cfg80211 380928 1 moal mlan 499712 1 moal The driver expects the firmware to be relative to the path /lib/firmware. Be sure to use the correct combo firmware image for the respective driver package. See also Table 27. UBX-19011209 - R07 C2-Restricted Software Page 43 of 71 JODY-W3 series - System integration manual The following log example shows the firmware request and loading operation of the PCIe driver.

[ 187.830477] mlan: loading out-of-tree module taints kernel.

[ 187.995594] wlan: Loading MWLAN driver

[ 188.000731] wlan_pcie 0000:01:00.0: enabling device (0000 -> 0002)

[ 188.007113] Attach moal handle ops, card interface type: 0x206

[ 188.012991] No module param cfg file specified

[ 188.017477] rx_work=1 cpu_num=6

[ 188.020672] Attach mlan adapter operations.card_type is 0x206.

[ 188.033816] Request firmware: nxp/jody-w3-pcieuart/pcieuart9098_combo_v1.bin

[ 188.706540] FW download over, size 661328 bytes

[ 190.221805] WLAN FW is active

[ 190.238578] VDLL image: len=138656

[ 190.242184] fw_cap_info=0xc8fcffa3, dev_cap_mask=0xffffffff

[ 190.247849] max_p2p_conn = 8, max_sta_conn = 64

[ 190.290702] wlan: version = PCIE9098-17.68.1.p38-MXM4X17222.P1-GPL-(FP68)

[ 190.302365] wlan_pcie 0000:01:00.1: enabling device (0000 -> 0002)

[ 190.308754] Attach moal handle ops, card interface type: 0x206

[ 190.314760] No module param cfg file specified

[ 190.319228] rx_work=1 cpu_num=6

[ 190.322577] Attach mlan adapter operations.card_type is 0x206.

[ 190.349922] Request firmware: nxp/jody-w3-pcieuart/pcieuart9098_combo_v1.bin

[ 190.358426] WLAN FW already running! Skip FW download

[ 190.363722] WLAN FW is active

[ 190.380792] VDLL image: len=138656

[ 190.384298] fw_cap_info=0x68fcffa3, dev_cap_mask=0xffffffff

[ 190.389942] max_p2p_conn = 8, max_sta_conn = 64

[ 190.401149] wlan: version = PCIE9098-17.68.1.p38-MXM4X17222.P1-GPL-(FP68)

[ 190.409893] wlan: Driver loaded successfully After downloading the combo firmware using the Wi-Fi driver, it is not necessary to specify the Bluetooth firmware when loading the Bluetooth driver hci_uart.ko. The insmod command below inserts the hci_uart.ko Bluetooth driver module into the Linux kernel, which is then used for Bluetooth communication over the UART host interface:

$ insmod hci_uart.ko

[ 898.714631] HCI UART driver ver 2.2-M2614100

[ 898.714670] HCI H4 protocol initialized

[ 898.722842] HCI BCSP protocol initialized The hci_uart.ko kernel module is also distributed with the kernel sources, which means that CONFIG_BT_HCIUART option might already be enabled in the kernel. If this is the case, it is not possible to load the kernel module provided by NXP. To load the proprietary hci_uart module provided by NXP, the kernel configuration must set CONFIG_BT_HCIUART=m and not CONFIG_BT_HCIUART=y. 3.8.2.2 Parallel mode In parallel mode, two different firmware binary images are used together with the respective driver. Set the driver parameter fw_serial=0 to configure the download operation in parallel mode, as shown below for the SDIO Wi-Fi driver.

$ insmod mlan.ko

$ insmod moal.ko fw_name=nxp/sd9098_wlan_v1.bin cfg80211_wext=0xf auto_ds=2 ps_mode=2 fw_serial=0 An example log of a successful SDIO driver loading and firmware download is shown below.

[ 16.396004] wlan: Loading MWLAN driver

[ 16.400727] vendor=0x02DF device=0x914D class=0 function=1

[ 16.406453] Attach moal handle ops, card interface type: 0x106

[ 16.424872] Attach mlan adapter operations.card_type is 0x106.

[ 16.448778] Request firmware: mrvl/sd9098_wlan_v1_jody-w3-sdio.bin

[ 16.750144] Wlan: FW download over, firmwarelen=593348 downloaded 487372 UBX-19011209 - R07 C2-Restricted Software Page 44 of 71 JODY-W3 series - System integration manual

[ 17.257260] WLAN FW is active

[ 17.330706] wlan: version = SD9098---17.68.0.p159-MXM4X17153-GPL-(FP68)

[ 17.337810] vendor=0x02DF device=0x914E class=0 function=2

[ 17.358325] Attach moal handle ops, card interface type: 0x106

[ 17.376908] Attach mlan adapter operations.card_type is 0x106.

[ 17.426684] Request firmware: mrvl/sd9098_wlan_v1_jody-w3-sdio.bin

[ 17.434397] WLAN FW already running! Skip FW download

[ 17.440017] WLAN FW is active

[ 17.482183] wlan: version = SD9098---17.68.0.p159-MXM4X17153-GPL-(FP68)

[ 17.490179] wlan: Driver loaded successfully To download the Bluetooth firmware over UART, we need the fw_loader application, built from the uartfwloader_src directory in the respective driver packages. An example of a firmware download, showing all the parameters associated with the operation, is shown below. The initial baud rate is 115200 baud, which is switched to 3000000 baud for the actual firmware download.

$ ./fw_loader /dev/ttyUSB0 115200 0 /lib/firmware/nxp/uart9098_bt_v1.bin 3000000 FW Loader Version: M317 ComPort : /dev/ttyUSB0 BaudRate: 115200 FlowControl: 0 Filename: /lib/firmware/nxp/uart9098_bt_v1.bin Second BaudRate: 3000000 ChipID is : 5c01, Version is : 0 File downloaded: 150768: 150768 Download Complete time:3018 CTS is low

$ insmod hci_uart.ko

[ 208.037130] HCI UART driver ver 2.2-M2614100

[ 208.037173] HCI H4 protocol initialized

[ 208.045354] HCI BCSP protocol initialized Note the sequence. Firmware is downloaded first followed by the hci_uart driver. The example uses /dev/ttyUSB0 as the serial device port. Replace it with the port to which the JODY-W3 series UART interface is connected on the host system. 3.8.3 Verification 3.8.3.1 Firmware version The version of the loaded Wi-Fi driver and firmware can be verified using the following command:

$ mlanutl mlan0 version Version string received: PCIE9098-17.68.1.p38-MXM4X17222.P1-GPL-(FP68) 3.8.3.2 Network interfaces Use command iw dev to display the available Wi-Fi interfaces (excerpt):

phy#1 Interface mwfd0 addr 02:50:43:02:fe:02 type managed Interface muap0 addr 00:50:43:02:00:02 type AP Interface mmlan0 addr 00:50:43:02:fe:02 UBX-19011209 - R07 C2-Restricted Software Page 45 of 71 JODY-W3 series - System integration manual type managed phy#0 Interface wfd0 addr 02:50:43:02:fe:01 type managed Interface uap0 addr 00:50:43:02:00:01 type AP Interface mlan0 addr 00:50:43:02:fe:01 type managed Table 31 describes the functions of the Wi-Fi interfaces. Interface MAC/PHY Function mlan0 uap0 wfd0 1 1 1 mmlan0 2 muap0 mwfd0 2 2 Network interface used for station mode functionality. Can be configured using mlanutl. Network interface used for access-point functionality. Can be configured using uaputl. Network interface used for P2P functionality. Can operate in both group owner (GO) and group client

(GC) modes. Network interface used for station mode functionality. Can be configured using mlanutl. Network interface used for access-point functionality. Can be configured using uaputl. Network interface used for P2P functionality. Can operate in both group owner (GO) and group client

(GC) modes. Table 31: Available Wi-Fi network interfaces JODY-W3 series modules include two radios 2.4 and 5 GHz and two MACs for concurrent dual Wi-Fi use cases, where Wi-Fi interfaces from MAC 1 and 2 operate concurrently in different bands. The system/udev managers in modern Linux distributions automatically try to assign predictable, stable network interface names for all local Ethernet and Wi-Fi interfaces. This can result in different names being used for the network interfaces. Use the kernel command line option net.ifnames=0 to override this behavior and use the driver default names. 3.8.4 Assigning MAC addresses JODY-W3 series has four unique MAC addresses reserved for each module. The first MAC address is used for Bluetooth and the second and third addresses are used for the two Wi-Fi radio MACs. The fourth MAC address is reserved for use with other local interfaces. Example 00:9C:38:00:4B:40 Bluetooth interface (hci0) 00:9C:38:00:4B:41 Wi-Fi station interface for radio MAC1 (mlan0) 00:9C:38:00:4B:42 Wi-Fi station interface for radio MAC2 (mmlan0) 00:9C:38:00:4B:43 Reserved for use with other interfaces Commented [MZ83]: Update when MAC reservation has been defined. The Wi-Fi driver automatically assigns locally unique MAC addresses to any additional Wi-Fi network interfaces, which are derived from the radios primary Wi-Fi station interface MAC address. The use of reserved unique MAC addresses is recommended to avoid possible collisions with the MAC addresses of other modules. You can change the MAC addresses of the interfaces by configuring the init_cfg.conf file while loading the driver. Note that the driver expects the init_cfg.conf file to be present in the directory relative to /lib/firmware/. Commented [CT84]: This means " derived from the primary address of the RADIUS server", right?

Commented [MZ85R84]: No, they are derived from the primary STA interface of the radio/MAC UBX-19011209 - R07 C2-Restricted Software Page 46 of 71 JODY-W3 series - System integration manual In the following example, the MAC addresses of the Wi-Fi interfaces have been changed in the init_cfg.conf file. The changes have been implemented to meet the application requirements so that each interface is assigned with a unique MAC address to avoid conflicts. The addresses are assigned to the uap0 and muap0 interfaces.

# File: /lib/firmware/nxp/init_cfg.conf

# MAC address (interface: address) mac_addr=uap0: D4:CA:6E:00:1B:18 mac_addr=muap0: D4:CA:6E:00:1B:19

$ insmod moal.ko fw_name=nxp/pcieuart9098_combo_v1.bin cfg80211_wext=0xf auto_ds=2 ps_mode=2 init_cfg=nxp/init_cfg.conf 3.8.5 Antenna configuration The default antenna configuration after reset is to use 2x2 on both radios for 2.4 GHz and 5 GHz. Since JODY-W354 and JODY-W374 support only 1x1 for the 2.4 GHz radio on path A, the antenna configuration must be updated accordingly using the following commands:

mlanutl mlan0 antcfg 0x301 mlanutl mmlan0 antcfg 0x301

# set PHY#1 to path A+B for 5GHz and path A for 2.4GHz

# set PHY#2 to path A+B for 5GHz and path A for 2.4GHz The same can be achieved by using the iw tool to configure the antennas:

iw phy mwiphy0 set antenna 0x301 # set PHY#1 to path A+B for 5GHz and path A for 2.4GHz iw phy mwiphy1 set antenna 0x301 # set PHY#2 to path A+B for 5GHz and path A for 2.4GHz 3.8.6 Access point 3.8.6.1 Using hostapd hostapd18 is an open-source user space daemon for access point and authentication servers. 802.11ax configuration is supported with Linux kernel 5.x and hostapd 2.9. The hostapd configuration file example below shows the parameters for 802.11ax operation in the 5 GHz band with 80 MHz channel width and WPA2 security:

# File: hostapd_ax5g.conf interface=uap0 driver=nl80211 ctrl_interface=/var/run/hostapd ctrl_interface_group=0 ieee80211d=1 country_code=US beacon_int=100 dtim_period=1 wmm_enabled=1 uapsd_advertisement_enabled=1 ssid=JODY-W3-AX5G ignore_broadcast_ssid=0 hw_mode=a channel=36 auth_algs=1 max_num_sta=10 ieee80211n=1 require_ht=0 ht_capab=[LDPC][GF][SHORT-GI-20][SHORT-GI-40][TX-STBC][RX-STBC1][HT40+]

ieee80211ac=1 require_vht=0 vht_capab=[RXLDPC][SHORT-GI-80][SOUNDING-DIMENSION-2][BF-ANTENNA-4][TX-STBC-2BY1][RX-STBC-

1][SU-BEAMFORMER][SU-BEAMFORMEE][MAX-A-MPDU-LEN-EXP7][RX-ANTENNA-PATTERN][TX-ANTENNA-

PATTERN]

18 https://w1.fi/hostapd/

UBX-19011209 - R07 C2-Restricted Software Page 47 of 71 JODY-W3 series - System integration manual vht_oper_chwidth=1 vht_oper_centr_freq_seg0_idx=42 ieee80211ax=1 he_su_beamformer=1 he_bss_color=1 he_oper_chwidth=1 he_oper_centr_freq_seg0_idx=42 eapol_version=1 wpa_key_mgmt=WPA-PSK wpa=2 rsn_pairwise=CCMP wpa_passphrase=1234567890 The access point is started with the command:

hostapd hostapd_ax5g.conf -B Use the command with the options -dddt to generate detailed log files for debugging purpose. A hostapd configuration file example for 802.11ax operation in the 2.4 GHz band and WPA2 security is shown below.

# File: hostapd_ax2g.conf interface=uap0 driver=nl80211 ctrl_interface=/var/run/hostapd ctrl_interface_group=0 ieee80211d=1 country_code=US beacon_int=100 dtim_period=1 wmm_enabled=1 uapsd_advertisement_enabled=1 ssid= JODY-W3-AX2G ignore_broadcast_ssid=0 hw_mode=g channel=11 auth_algs=1 max_num_sta=10 ieee80211n=1 require_ht=0 ht_capab=[LDPC][GF][SHORT-GI-20][TX-STBC][RX-STBC1][HT20]

ieee80211ac=0 ieee80211ax=1 he_su_beamformer=1 he_bss_color=1 eapol_version=1 wpa_key_mgmt=WPA-PSK wpa=2 wpa_pairwise=CCMP wpa_passphrase=1234567890 3.8.6.2 Using internal authenticator Access point can be configured using the uaputl configuration tool provided by NXP. NXP firmware has internal authenticator functionalities that are used in this case. In the following example, two concurrent access points are created. The first access point is configured for 802.11ax operation in the 5 GHz band using the uap0 interface. It uses an SSID value -

JODY-W3-5G and the passphrase "12345678" for WPA2 based security. The second access point is configured for 802.11n in the 2.4 GHz band using the muap0 interface. It uses an SSID value -

JODY-W3-2G and no security. The description of the individual commands is provided in the README_UAP file in the driver package. UBX-19011209 - R07 C2-Restricted Software Page 48 of 71 The following commands set up the 5 GHz 802.11ax access point and the security mechanisms:

JODY-W3 series - System integration manual uaputl -i uap0 bss_stop uaputl -i uap0 htstreamcfg 0x22 uaputl -i uap0 sys_cfg_rates 0x8c 0x98 0xb0 0x12 0x24 0x48 0x60 0x6c uaputl -i uap0 sys_cfg_channel 44

# 20/40MHz, SGI, Rx LDPC, Rx STBC, GF, Tx STBC, MCS0-15 uaputl -i uap0 httxcfg 0x11ff uaputl -i uap0 sys_cfg_11n 1 0x11ff 3 0 0xffff

# no beamformee uaputl -i uap0 vhtcfg 2 3 1 0x338161B0 0xfffa 0xfffa uaputl -i uap0 sys_cfg_ssid JODY-W3-5G uaputl -i uap0 sys_cfg_auth 0 uaputl -i uap0 sys_cfg_protocol 32 uaputl -i uap0 sys_cfg_wpa_passphrase 12345678 uaputl -i uap0 sys_cfg_cipher 8 8 uaputl -i uap0 bss_start The following commands set up the 2.4 GHz 802.11n access point:

uaputl -i muap0 bss_stop uaputl -i muap0 sys_cfg_rates 0x82 0x84 0x8b 0x96 0x0C 0x12 0x18 0x24 0x30 0x48 0x60 0x6c uaputl -i muap0 sys_cfg_channel 6

# 20/40MHz, SGI, Rx LDPC, Rx STBC, Tx STBC, MCS0-15 uaputl -i muap0 sys_cfg_11n 1 0x01ef 3 0 0xffff uaputl -i muap0 sys_cfg_ssid JODY-W3-2G uaputl -i muap0 sys_cfg_auth 0 uaputl -i muap0 sys_cfg_protocol 1 uaputl -i muap0 sys_cfg_cipher 0 0 uaputl -i muap0 bss_start The following commands assign IP addresses to the two interfaces:

ifconfig uap0 192.168.1.1 up ifconfig muap0 192.168.2.1 up It is normally appropriate to run a DHCP server on the network interfaces to automatically assign IP addresses to the connected clients, as shown below for the uap0 interface:

# File: udhcpd.conf interface uap0 start 192.168.1.10 end 192.168.1.200 option subnet 255.255.255.0 Command to start the DHCP server:

udhcpd udhcpd.conf 3.8.6.3 Configuration of 802.11ax for kernel 4.x Additional configuration must be applied for Linux kernel 4.x to enforce 802.11ax operation before starting the access point. This is due to missing 802.11ax definitions in the 4.x kernel.

# File: config/11axcfg_80-2x2.conf

# Band config

[Band]

# band config, 1: 2.4G, 2: 5G 02

[/Band]

# HE Capability

[HECap]

# ID ff 00

# Length 1a 00 UBX-19011209 - R07 C2-Restricted Software Page 49 of 71 JODY-W3 series - System integration manual

# he capability id 23

# HE MAC capability info 00 00 00 82 00 08

# HE PHY capability info, first byte 04: 80MHz, 02: 20MHz 04 70 7e c9 fd 01 a0 0e 03 3d 00

# Tx Rx HE-MCS NSS support fa ff fa ff

# PPE Thresholds (optional)

# PE: 16 us e1 ff c7 71

[/HECap]

While starting the access point on 4.x kernel, use the following mlanutl command with respective configuration file before starting the access point:

mlanutl uap0 11axcfg config/11axcfg_80-2x2.conf 3.8.7 Station mode 3.8.7.1 Using wpa_supplicant wpa_supplicant19 is an open source WPA Supplicant that is used in the client stations for key negotiation with a WPA Authenticator. It also controls the roaming and authentication/association of the Wi-Fi driver. No additional external configuration is required to support 802.11ax operation. Here are set of commands used to connect to an access point. Initially prepare the configuration file with some primitive settings:

$ cat > /etc/wpa_supplicant.conf << EOF ctrl_interface=/var/run/wpa_supplicant ctrl_interface_group=0 update_config=1 EOF Set wireless network settings such as SSID <ssid> and the passphrase <passphrase>:

$ wpa_passphrase <ssid> <passphrase> >> /etc/wpa_supplicant.conf Run the wpa_supplicant daemon:

$ wpa_supplicant -B -D nl80211 -i mlan0 -c /etc/wpa_supplicant.conf Use the command with the options -dddt to generate detailed log files for debugging purpose. To acquire an IP address via DHCP:

$ udhcpc -i mlan0 3.8.7.2 Using internal supplicant The following example shows how to connect to an access point using the mlanutl configuration tool provided by NXP. NXP firmware has internal supplicant functionalities that are used in this case. To connect to an 802.11ax access point in the 5 GHz band with SSID <ssid> and passphrase

<passphrase> and automatically assign an IP address via DHCP:

mlanutl mlan0 passphrase "1;ssid=<ssid>;passphrase=<passphrase>"

mlanutl mlan0 assocessid <ssid>

mlanutl mlan0 reassoctrl 1 udhcpc -i mlan0 19 https://w1.fi/wpa_supplicant/

UBX-19011209 - R07 C2-Restricted Software Page 50 of 71 Commented [MZ86]: Change to 3000000 for ES Commented [CT87R86]: ROLLOVER to later (ES) release JODY-W3 series - System integration manual 3.8.8 Bluetooth usage Once the Bluetooth drivers are loaded for the UART interface, it is necessary to bind the serial interface to the Bluetooth stack. For this, use the hciattach tool in the BlueZ package. The following code snippet shows how to attach to BlueZ through the /dev/ttyUSB0 serial device. In the example below, Bluetooth is connected to the host using USB cable connected through FTDI.

$ hciattach /dev/ttyUSB0 any 3000000 flow

[ 442.667056] ps_init_work...

[ 442.675963] ps_init_timer...

[ 442.684716] ps_init...

[ 442.816845] Bluetooth: BNEP (Ethernet Emulation) ver 1.3

[ 442.825928] Bluetooth: BNEP socket layer initialized

[ 443.234456] Bluetooth: RFCOMM TTY layer initialized

[ 443.245865] Bluetooth: RFCOMM socket layer initialized

[ 443.254362] Bluetooth: RFCOMM ver 1.11 Device setup complete An HCI interface (shown here as hci0) is then available for further transactions.

$ hciconfig a hci0 up hci0: Type: Primary Bus: UART BD Address: D4:CA:6E:00:1B:16 ACL MTU: 1021:7 SCO MTU: 120:6 UP RUNNING PSCAN RX bytes:918 acl:0 sco:0 events:62 errors:0 TX bytes:1115 acl:0 sco:0 commands:62 errors:0 Features: 0xff 0xfe 0x8f 0xfe 0xdb 0xff 0x7b 0x87 Packet type: DM1 DM3 DM5 DH1 DH3 DH5 HV1 HV2 HV3 Link policy: RSWITCH HOLD SNIFF Link mode: SLAVE ACCEPT Name: 'apalis-tk1'

Class: 0x200000 Service Classes: Audio Device Class: Miscellaneous, HCI Version: 5.0 (0x9) Revision: 0x8300 LMP Version: 5.0 (0x9) Subversion: 0x10bc A Bluetooth inquiry can be issued to scan for remote devices and verify that Bluetooth is working. L2CAP echo requests are used to ping the remote devices.

$ hcitool -i hci0 scan Scanning ... 00:22:58:F8:86:BB ae-sho-bln-test

$ l2ping -i hci0 00:22:58:F8:86:BB Ping: 00:22:58:F8:86:BB from 00:06:C6:46:DF:7B (data size 44) ... 4 bytes from 00:22:58:F8:86:BB id 0 time 69.75ms 4 bytes from 00:22:58:F8:86:BB id 1 time 56.76ms

3.8.8.1 Changing the UART baud rate The vendor specific HCI command HCI_CMD_MARVELL_UART_BAUD can be used to switch to a different baud rate, for example to 3000000 baud, as shown in the following example. The hciattach tool needs to be restarted with the new baud rate.

$ hcitool i hci0 cmd 0x3F 0x0009 0xC0 0xC6 0x2D 0x00

< HCI Command: ogf 0x3f, ocf 0x0009, plen 4 C0 C6 2D 00

> HCI Event: 0x0e plen 4 01 7A 0C 00

$ killall hciattach

$ hciattach /dev/ttyUSB0 any 3000000 flow

$ hciconfig hci0 up UBX-19011209 - R07 C2-Restricted Software Page 51 of 71 JODY-W3 series - System integration manual 3.9 Driver debugging Driver debugging is provided through the kernel print function printk and the proc file system. Driver states are recorded and are retrieved through the proc file system during runtime. The printk command output includes the following debug information files:

/proc/mwlan/config or /proc/net/mwlan/config

/proc/mwlan/mlanX/info or /proc/net/mwlan/mlanX/info

/proc/mwlan/mlanX/debug or /proc/net/mwlan/mlanX/debug Note that the physical file location is dependent on the Linux kernel version. mlanX is the name of the device node created at runtime. Other file name possibilities include uapX and wfdX for the access point and Wi-Fi Direct interfaces respectively. Debug messages are also printed to the kernel ring buffer through printk calls. These messages are accessed using the /proc/kmsg interface or by the dmesg command. Alternatively, this can also be handled by more advanced logging facilities. 3.9.1 Compile-time debug options The extent to which the debug messages can be printed at runtime is controlled by the CONFIG_DEBUG variable in the driver Makefile. The CONFIG_DEBUG variable can have any of the following values:

n: debug messages are disabled and not compiled into the driver module 1: all kinds of debug messages can be configured except for MENTRY, MWARN and MINFO. By default, MMSG, MFATAL and MERROR are enabled. 2: all kinds of debug messages can be configured 3.9.2 Runtime debug options Once debugging is enabled in the Makefile, debug messages can be selectively enabled or disabled at runtime. Set or clear the corresponding bits of the drvdbg parameter accordingly:

bit 0: MMSG PRINTM(MMSG,...) bit 1: MFATAL PRINTM(MFATAL,...) bit 2: MERROR PRINTM(MERROR,...) bit 3: MDATA PRINTM(MDATA,...) bit 4: MCMND PRINTM(MCMND,...) bit 5: MEVENT PRINTM(MEVENT,...) bit 6: MINTR PRINTM(MINTR,...) bit 7: MIOCTL PRINTM(MIOCTL,...)

... bit 16: MDAT_D PRINTM(MDAT_D,...), DBG_HEXDUMP(MDAT_D,...) bit 17: MCMD_D PRINTM(MCMD_D,...), DBG_HEXDUMP(MCMD_D,...) bit 18: MEVT_D PRINTM(MEVT_D,...), DBG_HEXDUMP(MEVT_D,...) bit 19: MFW_D PRINTM(MFW_D,...), DBG_HEXDUMP(MFW_D,...) bit 20: MIF_D PRINTM(MIF_D,...), DBG_HEXDUMP(MIF_D,...)

... bit 28: MENTRY PRINTM(MENTRY,...), ENTER(), LEAVE() bit 29: MWARN PRINTM(MWARN,...) bit 30: MINFO PRINTM(MINFO,...) To change the value of the drvdbg parameter, give it as a module parameter when the driver is loaded, or write to the debug file in the proc file system, or set it using either the iwpriv or mlanutl tools. iwpriv mlan0 drvdbg # Get the current driver debug mask iwpriv mlan0 drvdbg 0 # Disable all debug messages echo "drvdbg=0x7" > /proc/mwlan/mlan0/debug # enable MMSG, MFATAL and MERROR mlanutl mlan0 drvdbg -1 # Enable all debug messages UBX-19011209 - R07 C2-Restricted Software Page 52 of 71 JODY-W3 series - System integration manual 4 Handling and soldering JODY-W3 series modules are Electrostatic Sensitive Devices that demand the observance of precautions against electrostatic discharge. Failure to observe precautions can result in severe damage to the product. Standard ESD safety practices must be applied. Figure 15: Standard workstation setup for safe handling of ESD-sensitive devices 4.1 Special ESD handling precautions The risk of introducing electrostatic discharge in the RF transceiver through the RF pins is of special concern and the following bullets must carefully be observed:

When connecting test equipment or any other electronics to the module (as a standalone or PCB-

mounted device), the first point of contact must always be to local GND. Before mounting an antenna, connect the device to ground. When handling the RF pin, do not touch any charged capacitors. Be especially careful when handling materials like patch antennas (~10 pF), coaxial cables (~50-80 pF/m), soldering irons, or any other materials that can develop charges. To prevent electrostatic discharge through the RF input, do not touch any exposed antenna area. If there is any risk of the exposed antenna being touched in an unprotected ESD work area, be sure to implement proper ESD protection measures in the design. When soldering RF connectors and patch antennas to the RF pin on the transceiver, be sure to use an ESD-safe soldering iron (tip). 4.2 Packaging, shipping, storage, and moisture preconditioning For information pertaining to reels, tapes, or trays, moisture sensitivity levels (MSL), storage, shipment, and drying preconditioning, see the JODY-W3 series modules data sheet [1] and Packaging information reference guide [2]. UBX-19011209 - R07 C2-Restricted Handling and soldering Page 53 of 71 JODY-W3 series - System integration manual 4.3 Reflow soldering process JODY-W3 series modules are surface mounted devices supplied on a multi-layer FR4-type PCB with gold-plated connection pads. The modules are produced in a lead-free process using lead-free soldering paste. The thickness of solder resist between the host PCB top side and the bottom side of JODY-W3 series modules must be considered for the soldering process. JODY-W3 series modules are compatible with industrial reflow profile for RoHS solders, and no-

clean soldering paste is strongly recommended. JODY-W3 series modules comply to two reflow soldering cycles when mounted on a host board. For further information, contact your local support team. The reflow profile used is dependent on the thermal mass of the entire populated PCB, the heat transfer efficiency of the oven, and the type of solder paste that is used. The optimal soldering profile must be trimmed for the specific process and PCB layout The target values shown in Table 32 and Figure 16 are given as general guidelines for a Pb-free process only. For further information, see also the JEDEC J-STD-020E [7] standard. Process parameter Pre-heat Peak Cooling General Table 32: Recommended reflow profile Ramp up rate to TSMIN TSMIN TSMAX tS (from 25C) tS (Pre-heat) TL tL (time above TL) TP (absolute max) tP (time above TP -5C) Ramp-down from TL Tto peak Allowed soldering cycles Unit K/s C C s s C s C s K/s s

Target 3 150 200 150 110 217 90 260 30 6 300 1 Commented [CT88]: Pins or pads?

Commented [CT89R88]: Confirmed by Cairong as pads, Revisied Commented [CT90]: Missing bow and twist tolerances?

The bow and twist of the PCB is maximum 0.75% according to IPC-A-610E. Commented [CT91R90]: Cairong confirmed bow and twist is not is not important in this context Commented [CT92]: for common SAC-type, RoHS solders?

Commented [CT93R92]: Cairong confirmed SAC-

type unnecessary Commented [CT94]: Has 2-flow resoldering since been approved for this module?

Commented [CT95R94]: Please check and confirm status Commented [LB96R94]: Two times reflow is confirmed. Upside down reflow is yet not verified. Commented [LB97R94]:

Commented [CT98]: Ambiguous and confusing What must be trimmed exactly and what case does this refer to exactly?

Commented [CT99R98]: Revised Figure 16: Reflow profile The lower value of TP and slower ramp down rate is preferred. UBX-19011209 - R07 C2-Restricted Handling and soldering Page 54 of 71 JODY-W3 series - System integration manual 4.3.1 Cleaning Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pins. Water will also damage the sticker and the ink-jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the housing, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module and the crystal oscillators in particular. For best results use a "no clean" soldering paste and circumvent the need for a cleaning stage after the soldering process. 4.3.2 Other notes Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices may require wave soldering to solder the THT components. Only a single wave soldering process is allowed for boards populated with the modules. Miniature Wave Selective Solder process is preferred over traditional wave soldering process. Hand soldering is not recommended. Rework is not recommended. Conformal coating can affect the performance of the module, which means that it is important to prevent the liquid from flowing into the module. The RF shields do not provide protection for the module from coating liquids with low viscosity; therefore, care is required while applying the coating. Conformal Coating of the module will void the warranty. Grounding metal covers: Attempts to improve grounding by soldering ground cables, wick, or other forms of metal strips directly onto the EMI covers is done at the customer's own risk and voids the module warranty. The numerous ground pins are adequate to provide optimal immunity to interferences. The modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding etc.) may damage the module. Use of ultrasonic processes during the integration of the module into an end product will void the warranty. UBX-19011209 - R07 C2-Restricted Handling and soldering Page 55 of 71 JODY-W3 series - System integration manual 5 Regulatory compliance 5.1 General requirements JODY-W3 series modules are designed to comply with the regulatory demands of Federal Communications Commission (FCC), Innovation, Science and Economic Development Canada

(ISED)20 and the CE mark21. This section contains instructions on the process needed for an integrator when including the JODY-W3 module into an end-product. Any deviation from the process described may cause the JODY-W3 series module not to comply with the regulatory authorizations of the module and thus void the user's authority to operate the equipment. Any changes to hardware, hosts or co-location configuration may require new radiated emission and SAR evaluation and/or testing. The regulatory compliance of JODY-W3 does not exempt the end-product from being evaluated against applicable regulatory demands; for example, FCC Part 15B criteria for unintentional radiators [9]. The end-product manufacturer must follow all the engineering and operating guidelines as specified by the grantee (u-blox). The JODY-W3 is for OEM integrators only. Only authorized antenna(s) may be used. Refer to JODY-W3 data sheet [1] for the list of authorized antennas. In the end-product, the JODY-W3 module must be installed in such a way that only authorized antennas can be used. The end-product must use the specified antenna trace reference design, as described in the Antenna integration application note [11]. Any notification to the end user about how to install or remove the integrated radio module is NOT allowed. If these conditions cannot be met or any of the operating instructions are violated, the u-blox regulatory authorization will be considered invalid. Under these circumstances, the integrator is responsible to re-evaluate the end-product including the JODY-W3 series module and obtain their own regulatory authorization, or u-blox may be able to support updates of the u-blox regulatory authorization. See also Antenna requirements. 5.2 FCC/ISED End-product regulatory compliance u-blox represents that the modular transmitter fulfills the FCC/ISED regulations when operating in authorized modes on any host product given that the integrator follows the instructions as described in this document. Accordingly, the host product manufacturer acknowledges that all host products referring to the FCC ID or ISED certification number of the modular transmitter and placed on the market by the host product manufacturer need to fulfil all of the requirements mentioned below. Non-

compliance with these requirements may result in revocation of the FCC approval and removal of the host products from the market. These requirements correspond to questions featured in the FCC guidance for software security requirements for U-NII devices, FCC OET KDB 594280 D02 [16]. The modular transmitter approval of JODY-W3, or any other radio module, does not exempt the end product from being evaluated against applicable regulatory demands. 20 Formerly known as IC (Industry Canada). 21 All approvals are still pending UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 56 of 71 Commented [MZ100]: Add as described in the JODY-W3 series Antenna Reference Design [12]

document when available Commented [CT101R100]: Included x-ref. Commented [CT102R100]: Need only UBX placeholder for inclusion now. See note in Related docs. Commented [SA103]: Inserted this passage JODY-W3 series - System integration manual The evaluation of the end product shall be performed with the JODY-W3 module installed and operating in a way that reflects the intended end product use case. The upper frequency measurement range of the end product evaluation is the 10th harmonic of 5.8 GHz as described in KDB 996369 D04. The following requirements apply to all products that integrate a radio module:

Subpart B - UNINTENTIONAL RADIATORS To verify that the composite device of host and module comply with the requirements of FCC part 15B, the integrator shall perform sufficient measurements using ANSI 63.4-2014. Subpart C - INTENTIONAL RADIATORS It is required that the integrator carries out sufficient verification measurements using ANSI 63.10-2013 to validate that the fundamental and out of band emissions of the transmitter part of the composite device complies with the requirements of FCC part 15C. When the items listed above are fulfilled, the end product manufacturer can use the authorization procedures as mentioned in Table 1 of 47 CFR Part 15.101, before marketing the end product. This means the customer has to either market the end product under a Suppliers Declaration of Conformity (SDoC) or to certify the product using an accredited test lab. The description is a subset of the information found in applicable publications of FCC Office of Engineering and Technology (OET) Knowledge Database (KDB). We recommend the integrator to read the complete document of the referenced OET KDBs. KDB 178919 D01 Permissive Change Policy KDB 447498 D01 General RF Exposure Guidance KDB 594280 D01 Configuration Control KDB 594280 D02 U-NII Device Security KDB 784748 D01 Labelling Part 15 18 Guidelines KDB 996369 D01 Module certification Guide KDB 996369 D02 Module Q&A KDB 996369 D04 Module Integration Guide 5.2.1 Referring to the u-blox FCC/ISED certification ID If the General requirements, FCC/ISED End-product regulatory compliance regulations, and all Antenna requirements are met, the u-blox modular FCC/ISED regulatory authorization is valid and the end-product may refer to the u-blox FCC ID and ISED certification number. u-blox may be able to support updates to the u-blox regulatory authorization; for example, adding new antennas to the u-blox authorization. To use the u-blox FCC / ISED grant and refer to the u-blox FCC ID / ISED certification ID, the integrator must confirm with u-blox that all requirements associated with the Configuration control and software security of end-products are fulfilled. 5.2.2 Obtaining own FCC/ISED certification ID Integrators who do not want to refer to the u-blox FCC/ISED certification ID, or who do not fulfil all requirements to do so may instead obtain their own certification. With their own certification, the integrator has full control of the grant to make changes. Integrators who want to base their own certification on the u-blox certification can do so via a process called Change in ID (FCC) / Multiple listing (ISED). With this, the integrator becomes the grantee of a copy of the u-blox FCC/ISED certification. u-blox will support with an approval letter that shall be filed as a Cover Letter exhibit with the application. UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 57 of 71 Commented [MZ104]: Add and the JODY-W3 Radio Test Guide Application Note when available Commented [CT105R104]: Need only UBX placeholder for inclusion now. See note in Related docs. JODY-W3 series - System integration manual For modules where the FCC ID / ISED certification ID is printed on the label, the integrator must replace the modules label with a new label containing the new FCC/ISED ID. For more information about the labeling requirements, see also the JODY-W3 series data sheet [1]. It is the responsibility of the integrator to comply with any upcoming regulatory requirements. 5.2.3 Antenna requirements In addition to the general requirement to use only authorized antennas, the u-blox grant also requires a separation distance of at least 20 cm from the antenna(s) to all persons. The antenna(s) must not be co-located with any other antenna or transmitter (simultaneous transmission) as well. If this cannot be met, a Permissive Change as described below must be made to the grant. In order to support verification activities that may be required by certification laboratories, customers applying for Class-II Permissive changes must implement the setup described in the Radio test guide application note [12]. 5.2.3.1 Separation distance If the required separation distance of 20 cm cannot be fulfilled, a SAR evaluation must be performed. This consists of additional calculations and/or measurements. The result must be added to the grant file as a Class II Permissive Change. 5.2.3.2 Co-location (simultaneous transmission) If the module is to be co-located with another transmitter, additional measurements for simultaneous transmission are required. The results must be added to the grant file as a Class II Permissive Change. 5.2.3.3 Adding a new antenna for authorization If the authorized antennas and/or antenna trace design cannot be used, the new antenna and/or antenna trace designs must be added to the grant file. This is done by a Class I Permissive Change or a Class II Permissive Change, depending on the specific antenna and antenna trace design. Antennas of the same type and with less or same gain as an already approved antenna can be added under a Class I Permissive Change. Antenna trace designs deviating from the u-blox reference design and new antenna types are added under a Class II Permissive Change. For 5 GHz modules, the combined minimum gain of antenna trace and antenna must be greater than 0 dBi to comply with DFS testing requirements. Integrators with the intention to refer to the u-blox FCC ID / ISED certification ID must Contact their local support team to discuss the Permissive Change Process. Class II Permissive Changes will be subject to NRE costs. 5.2.4 Configuration control and software security of end-products Modular transmitter hereafter refers to JODY-W354, JODY-W374 (FCC ID XPYJODYW374), and JODY-W377 (FCC ID XPYJODYW377)22. As the end-product must comply with the requirements addressed by the OET KDB 594280 [15], the host product integrating the JODY-W3 must comply with the following requirements:

Upon request from u-blox, the host product manufacturer will provide all of the necessary information and documentation to demonstrate how the requirements listed below are met. The host product manufacturer will not modify the modular transmitter hardware. 22 Approvals are pending UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 58 of 71 Commented [SA106]: Contradicts 5.2.5. Shall I take this out or is 5.2.5 incomplete?

Commented [SS107R106]: Since the LILY module operates in the 2.4GHz band, only, the 5GHz statements however correct do not apply here. Most of our other Host-based modules also operate in the 5 or even 6GHz bands. If you want to keep the paragraph generically usable, you may want to leave them in. Other than that there is only an s too many. Commented [SA108]: Is this the same as two points above?

JODY-W3 series - System integration manual The configuration of the modular transmitter when installed into the host product must be within the authorization of the modular transmitter at all times and cannot be changed to include unauthorized modes of operation through accessible interfaces of the host product. The Wi-Fi Tx output power limits must be followed. In particular, the modular transmitter installed in the host product will not have the capability to operate on the operating channels/frequencies referred to in the section(s) below, namely one or several of the following channels: 12 (2467 MHz), 13 (2472 MHz), 120 (5600 MHz), 124 (5620 MHz), and 128 (5640 MHz). The channels 12 (2467 MHz), 13

(2472 MHz), 120 (5600 MHz), 124 (5620 MHz), and 128 (5640 MHz) are allowed to be used only for modules that are certified for the usage (modular transmitter). Customers must verify that the module in use is certified as supporting DFS client/master functionality. The host product uses only authorized firmware images provided by u-blox and/or by the manufacturer of the RF chipset used inside the modular transmitter. The configuration of the modular transmitter must always follow the requirements specified in Operating frequencies and cannot be changed to include unauthorized modes of operation through accessible interfaces of the host product. The modular transmitter must when installed into the host product have a regional setting that is compliant with authorized US modes and the host product is protected from being modified by third parties to configure unauthorized modes of operation for the modular transmitter, including the country code. The host product into which the modular transmitter is installed does not provide any interface for the installer to enter configuration parameters into the end product that exceeds those authorized. The host product into which the modular transmitter is installed does not provide any interface to third parties to upload any unauthorized firmware images into the modular transmitter and prevents third parties from making unauthorized changes to all or parts of the modular transmitter device driver software and configuration. The OET KDB 594280 D01 [15] lists the topics that must be addressed to ensure that the end-

product specific host meets the Configuration Control requirements. The OET KDB 594280 D02 [16] lists the topics that must be addressed to ensure that the end-

product specific host meets the Software Security Requirements for U-NII Devices. 5.2.5 Operating frequencies JODY-W3 802.11b/g/n/ax operation outside the 24122462 MHz band is prohibited in the US and Canada and 802.11a/n/ac/ax operation in the 56005650 MHz band is prohibited in Canada. Configuration of the module to operate on channels 1213 and 120128 must be prevented accordingly. The channels allowed are described in Table 33. UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 59 of 71 JODY-W3 series - System integration manual Channel number Channel center frequency [MHz]

Allowed channels Remarks 1 11 12 13 2412 2462 2467 2472 36 48 5180 5240 52 64 5260 5320 100 116 5500 5580 120 128 5600 5640 132 144 149 165 5660 5720 5745 5825 Yes No Yes Yes23 Yes2324 No Yes2324 Yes Canada (ISED): Devices are restricted to indoor operation only and the end product must be labelled accordingly. USA (FCC): Client device operation allowed under KDB 905462 Table 33: Allowed channel usage under FCC/ISED regulation 15.407 (j) Operator Filing Requirement:

Before deploying an aggregate total of more than one thousand outdoor access points within the 5.155.25 GHz band, parties must submit a letter to the Commission acknowledging that, should harmful interference to licensed services in this band occur, they will be required to take corrective action. Corrective actions may include reducing power, turning off devices, changing frequency bands, and/or further reducing power radiated in the vertical direction. This material shall be submitted to Laboratory Division, Office of Engineering and Technology, Federal Communications Commission, 7435 Oakland Mills Road, Columbia, MD 21046. Attn: U-NII Coordination, or via Web site at https://www.fcc.gov/labhelp with the subject line: U-NII-1 Filing. 23 DFS certification is pending. UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 60 of 71 JODY-W3 series - System integration manual 5.2.6 End product labeling requirements For an end-product using the JODY-W3, there must be a label containing, at least, the following information:

This device contains FCC ID: (XYZ)(UPN) IC: (CN)-(UPN)

(XYZ) represents the FCC "Grantee Code", this code may consist of Arabic numerals, capital letters, or other characters, the format for this code will be specified by the Commission's Office of Engineering and Technology24. (CN) is the Company Number registered at ISED. (UPN) is the Unique Product Number decided by the grant owner. The label must be affixed on an exterior surface of the end product such that it will be visible upon inspection in compliance with the modular labeling requirements of OET KDB 784748. The host user manual must also contain clear instructions on how end users can find and/or access the FCC ID of the end product. The label on the JODY-W3 module containing the original FCC ID acquired by u-blox can be replaced with a new label stating the end-products FCC/ISED ID in compliance with the modular labeling requirements of OET KDB 784748. FCC end product labeling In accordance with 47 CFR 15.19, the end product shall bear the following statement in a conspicuous location on the device:

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

This device may not cause harmful interference, and This device must accept any interference received, including interference that may cause undesired operation. ISED end product labeling The end product shall bear the following statement in both English and French in a conspicuous location on the device:

Operation is subject to the following two conditions:

This device may not cause interference, and This device must accept any interference, including interference that may cause undesired operation of the device. Son utilisation est soumise aux deux conditions suivantes:

Cet appareil ne doit pas causer dinterfrences et il doit accepter toutes interfrences reues, y compris celles susceptibles davoir des effets indsirables sur son fonctionnement. Labels of end products capable to operate within the band 51505250 MHz shall also include:

For indoor use only Pour usage intrieur seulement When the device is so small or for such use that it is not practicable to place the statements above on it, the information shall be placed in a prominent location in the instruction manual or pamphlet supplied to the user or, alternatively, shall be placed on the container in which the device is marketed. However, the FCC/ISED ID label must be displayed on the device as described above. 24 47 CFR 2.926 UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 61 of 71 JODY-W3 series - System integration manual In case, where the final product will be installed in locations where the end-consumer is unable to see the FCC/ISED ID and/or this statement, the FCC/ISED ID and the statement shall also be included in the end-product manual. 5.3 CE End-product regulatory compliance 5.3.1 Safety standard In order to fulfill the safety standard EN 60950-1 [8], the JODY-W3 module must be supplied with a Class-2 Limited Power Source. 5.3.2 CE Equipment classes In accordance with Article 1 of Commission Decision 2000/299/EC25, JODY-W3 is defined as either Class-1 or Class-2 radio equipment, the end-product integrating JODY-W3 inherits the equipment class of the module. Guidance on end product marking, according to the RED can be found at: http://ec.europa.eu/

The restrictions while operating the JODY-W3 in Wi-Fi mode in the European countries are shown in section European Union regulatory compliance of the JODY-W3 data sheet [1]. The EIRP of the JODY-W3 module must not exceed the limits of the regulatory domain that the module operates in. Depending on the host platforms implementation and antenna gain, integrators have to limit the maximum output power of the module through the host software. Refer to the JODY-W3 data sheet [1] for the modules approved antennas list and corresponding maximum transmit power levels. 5.4 Pre-approved antennas This section lists the different external antennas that are pre-approved for use with MAYA-W1 series modules. 5.4.1 Wi-Fi / Bluetooth dual band antennas For Bluetooth and Wi-Fi operation in the 2.4 GHz band and Wi-Fi operation in the 5 GHz band MAYA-

W1 has been tested and approved for use with the dual-band antennas shown in Table 34. Manufacturer Part Number Antenna type Peak gain [dBi]

2.4 GHz band 5 GHz band Validated regulatory domain Linx ANT-DB1-RAF-RPS Dual-band dipole antenna 2.7 4.6 FCC/ISED, RED Table 34: List of approved dual-band antennas Important: To be compliant to FCC 15.407(a) the EIRP is not allowed to exceed 125 mW

(21 dBm) at any elevation angle above 30 (measured from the horizon) when operated as an outdoor access point in U-NII-1 band, 5.150-5.250 GHz. 5.4.2 Bluetooth antennas Commented [MZ109]: Added antennas used for MAYA-W1 certification. For other modules we have this info in the data sheet. Not sure if has been decided to move it to the SIM Commented [CT110R109]: ROLLOVER (TBD) The single band antennas tested and approved for Bluetooth transmission with MAYA-W1 are shown in Table 35. Formatted: Normal Document Reference Manufacturer Part number Antenna type Peak gain [dBi]

2.4 GHz band Validated regulatory domain 25 2000/299/EC: Commission Decision of 6 April 2000 establishing the initial classification of radio equipment and telecommunications terminal equipment and associated identifiers. UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 62 of 71 JODY-W3 series - System integration manual Linx ANT-2.4-CW-RCT-RP Single-band dipole antenna 2.2 FCC/ISED, RED Table 35: List of approved single-band antennas UBX-19011209 - R07 C2-Restricted Regulatory compliance Page 63 of 71 JODY-W3 series - System integration manual 6 Product testing 6.1 u-blox in-line production testing As part of our focus on high quality products, u-blox maintain stringent quality controls throughout the production process. This means that all units in our manufacturing facilities are fully tested and that any identified defects are carefully analyzed to improve future production quality. The Automatic test equipment (ATE) deployed in u-blox production lines logs all production and measurement data from which a detailed test report for each unit can be generated. Figure 17 shows the ATE typically used during u-blox production. u-blox in-line production testing includes:

Digital self-tests (firmware download, MAC address programming) Measurement of voltages and currents Functional tests (host interface communication) Digital I/O tests Measurement and calibration of RF characteristics in all supported bands, including RSSI calibration, frequency tuning of reference clock, calibration of transmitter power levels, etc. Verification of Wi-Fi and Bluetooth RF characteristics after calibration, like modulation accuracy, power levels, and spectrum, are checked to ensure that all characteristics are within tolerance when the calibration parameters are applied. Commented [CT111]: Ambiguous Iiuc ATE for in-circuit (ICT) testing is quite common but in-series?

What does that mean exactly?

The term is used in several instances but isnt actually explained -which means that its open to some interpretation. Please clarify. Commented [CT112R111]: Changed to in-line testing following advice from Cairong/Axel Figure 17: Automatic test equipment for module test UBX-19011209 - R07 C2-Restricted Product testing Page 64 of 71 JODY-W3 series - System integration manual 6.2 OEM manufacturer production test As all u-blox products undergo thorough in-line production testing prior to delivery, OEM manufacturers do not need to repeat any firmware tests or measurements that might otherwise be necessary to confirm RF performance. Testing over analog and digital interfaces is also unnecessary during an OEM production test. OEM manufacturer testing should ideally focus on:

Module assembly on the device; it should be verified that:

o Soldering and handling process did not damage the module components o All module pins are well soldered on the customer application board o There are no short circuits between pins Component assembly on the device; it should be verified that:

o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna In addition to this testing, OEMs can also perform other dedicated tests to check the device. For example, the measurement of module current consumption in a specified operating state can identify a short circuit if the test result deviates that from that taken against a Golden Device. The standard operational module firmware and test software on the host can be used to perform functional tests (communication with the host controller, check interfaces) and perform basic RF performance testing. UBX-19011209 - R07 C2-Restricted Product testing Page 65 of 71 Appendix A Reference schematic Figure 18: JODY-W3 reference schematic UBX-19011209 - R07 C2-Restricted Appendix Page 66 of 71 B Glossary Abbreviation Definition AEC AP API ATE BT CDM CE CLI CTS DC DDR DFS DHCP EDR Automotive Electronics Council Access Point Application Programming Interface Automatic Test Equipment Bluetooth Charged Device Model European Conformity Command Line Interface Clear to Send Direct Current Double Data Rate Dynamic Frequency Selection Dynamic Host Configuration Interface Enhanced Data Rate EEPROM Electrically Erasable Programmable Read-Only Memory EIRP ESD FCC GND GPIO HBM HS HCI ISED I2C KDB LAN LDO LED LPO LTE MAC MMC MWS NRE Equivalent Isotropic Radiated Power Electro Static Discharge Federal Communications Commission Ground General Purpose Input/Output Human Body Model High-Speed Host Controller Interface Innovation, Science and Economic Development Canada Inter-Integrated Circuit Knowledge Database Local Area Network Low Drop Out Light-Emitting Diode Low Power Oscillator Long Term Evolution Medium Access Control Multi Media Card Mobile Wireless Standards Non-recurring engineering NSMD Non Solder Mask Defined OEM OET OS PCB PCI PCIe PCM Original equipment manufacturer Office of Engineering and Technology Operating System Printed Circuit Board Peripheral Component Interconnect PCI Express Pulse-code modulation UBX-19011209 - R07 C2-Restricted Appendix Page 67 of 71 Abbreviation Definition PHY PMU RF RSDB RST SDIO SMD SMPS SMT SSID STA TBD THT UART VCC VIO VSDB VSWR WFD WLAN WPA Physical layer (of the OSI model) Power Management Unit Radio Frequency Real Simultaneous Dual Band Request to Send Secure Digital Input Output Solder Mask Defined Switching Mode Power Supply Surface-Mount Technology Service Set Identifier Station To be Decided Through-Hole Technology Universal Asynchronous Receiver-Transmitter IC power-supply pin Input offset voltage Virtual Simultaneous Dual Band Voltage Standing Wave Ratio Wi-Fi Direct Wireless local area network Wi-Fi Protected Access Table 3634: Explanation of the abbreviations and terms used UBX-19011209 - R07 C2-Restricted Appendix Page 68 of 71 C Wi-Fi transmit output power limits Pending. UBX-19011209 - R07 C2-Restricted Appendix Page 69 of 71 Related documents

[1] JODY-W3 series data sheet, UBX-19010615

[2] Product packaging guide, UBX-14001652

[3]

[4]

u-blox Limited Use License Agreement, LULA-M IEC EN 61000-4-2 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques Electrostatic discharge immunity test

[5] ETSI EN 301 489-1 - Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1:

Common technical requirements IEC61340-5-1 - Protection of electronic devices from electrostatic phenomena General requirements

[6]

[7] JEDEC J-STD-020E - Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices

[8] ETSI EN 60950-1:2006 - Information technology equipment Safety Part 1: General requirements

[9] FCC Regulatory Information, Title 47 Telecommunication

[10] JESD51 Overview of methodology for thermal testing of single semiconductor devices

[11] Antenna Integration application note, UBX-20053581

[12] Radio test guide for NXP based modules, UBX-15014433

[13] Embedded Linux for i.MX Applications Processors, https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-

for-i-mx-applications-processors:IMXLINUX

[14] NXP UM11490, Feature Configuration Guide for NXP-based Wireless Modules on i.MX 8M Quad EVK, https://www.nxp.com/webapp/Download?colCode=UM11490

[15] FCC guidance 594280 D01 Configuration Control v02 r01,

[16] FCC guidance 594280 D02 U-NII Device Security v01r03 For product change notifications and regular updates of u-blox documentation, register on our website, www.u-blox.com. Commented [MZ113]: Add JODY-W3 Radio Test Guide Application Note, document number tbd. JODY-W3 Antenna Reference Design, document number tbd. Commented [CT114R113]: Please take out UBX numbers as placeholders so that we can include these here. Otherwise, rollover to next release?

Commented [CT115R113]: Please take out UBX numbers as placeholders - even if the doc content has not been created or approved. This way we can provide the document ref without any x-ref. Note that functional x-refs will only become activated for C1-Public docs (although some arrangement for C2-Restricted docs published on the web can be arranged if necessary) Commented [MZ116]: Note: Adding as placeholder. JODY-W3 not included yet. UBX-19011209 - R07 C2-Restricted Related documents Page 70 of 71 Revision history Revision Date Name Comments RO1 R02 5-June-2020 lber, mzes Initial release. 26-Aug-2020 lber, mzes Updated reference schematic in Appendix A. Fixed PCIe signal descriptions in Table 10Table 13. R03 29-Jan-2021 lber, mzes R04 12-May-2021 lber R05 29-Nov-2021 lber R06 16-Feb-2022 mzes R07 08-Aug-2022 lber, mzes Added professional grade product variants JODY-W374 and JODY-W377. Updated pin list and descriptions in Table 4. Corrected configuration pins in Table 7. Added section 1.4.6 Sleep clock. Added GPIO usage in section 1.7.2. Marked SDIO-SDIO support pending. Updated section 3.8.4 with MAC address assignment. Peak current consumption updated in section 1.3.1 table 5. Configuration information updated in section 1.4.5 table 7. Power supply voltage ripple limits updated in section 1.3.1 table 5. HCSL voltage levels specified for PCIe_CLK added to table in PCIe interface. Reference schematic updated in Appendix A. Internal PU/PD information added in Configuration pins. Pad state in power down mode updated in the Pin list. Revised Handling and soldering and Product testing information. Thermal characteristic parameter value added in section 2.8. Added automotive grade product variant JODY-W354. Revised block diagrams in Module architecture. Updated Bluetooth specification from 5.1 to 5.3. Removed product features section. Updated version in Open-source drivers. Removed SDIO-SDIO host interface combination. and pinout namely:

GPIO_12:

assignments, Updated Figure 3Figure 3 and Table 3Table 3 to reflect changes in the module pinout added UART_DSRn/W_DISABLE2n alternate functions, GPIO_13: added UART_DTRn alternate function, GPIO_1/2/17/18/19: added PTA coex interface, GPIO_18:

added independent software reset for Wi-Fi, GPIO_19: added independent software reset for Bluetooth, PCIE_RDN/RDP: added note about coupling capacitor, LPO_IN: Removed (DNC). Added information about coupling capacitors on PCIe_RDN and RDP, and added PTA information in the pin list. Revised description of power-off sequence and updated block diagrams in Module architecture. Added Coexistence interfaces section. Removed section 1.4.6 Sleep clock. Updated requirements for FCC/ISED End-product regulatory compliance and Configuration control and software security of end-products. Updated contact information. Commented [CT117]: Can't see that Figure 4, Power sequence of JODY-W3 module, hasn't been updated. Is this a duplicate reference to the pin list

(table 4) maybe?

Commented [MZ118R117]: Figure 3 Formatted: Normal Document Reference Formatted: Normal Document Reference R08 17-Aug-2022 lber Reference to information about module variants including dedicated LTE filter added in section 1.1.1. Contact For further support and contact information, visit us at www.u-blox.com/support. Formatted: English (United States) UBX-19011209 - R07 C2-Restricted Revision history Page 71 of 71

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RE: Certification Application Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland HVIN : JODY-W374-00A, FCC ID : XPYJODYW374, IC : 8595A-JODYW374 Company number: CH-020.3.020.161-7 HVIN : JODY-W374-00B, FCC ID : XPYJODYW374, IC : 8595A-JODYW374 HVIN : JODY-W377-00A, FCC ID : XPYJODYW377, IC : 8595A-JODYW377 HVIN : JODY-W377-00B, FCC ID : XPYJODYW377, IC : 8595A-JODYW377 HVIN : JODY-W354-00A, FCC ID : XPYJODYW374, IC : 8595A-JODY-W374 HVIN : JODY-W354-20A, FCC ID : XPYJODYW374, IC : 8595A-JODY-W374 HVIN : JODY-W374-20A, FCC ID : XPYJODYW374, IC : 8595A-JODY-W374 info@u-blox.com support@u-blox.com Label location information for JODY-W3 series modules The product label is affixed on to the module shield cover as shown in Figure 1. The size of the label is 17 x 11 mm and contains the following information:

A Data Matrix formatted bar code, with a unique serial number Date of unit production formatted YY/WW (year/week) Major and minor product version info Product marketing name (e.g. JODY-W374-00A, JODY-W374-00B, JODY-W377-00A, JODY-

W377-00B, JODY-W354-00A, JODY-W354-20A, JODY-W374-20A) Figure 1: Label of the JODY-W374-00A module Figure 2: Label of the JODY-W374-00B module Figure 3: Label of the JODY-W377-00A module Figure 4: Label of the JODY-W377-00B module Figure 5: Label of the JODY-W354-00A module Figure 6: Label of the JODY-W354-20A module Figure 7: Label of the JODY-W374-20A module Figure 8: Actual size of the JODY-W3 modules identifier marking (17 x 11 mm) Figure 9: Label location of the JODY-W3 modules

 

 

RE: Certification Application Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland HVIN : JODY-W374-00A, FCC ID : XPYJODYW374, IC : 8595A-JODYW374 Company number: CH-020.3.020.161-7 HVIN : JODY-W374-00B, FCC ID : XPYJODYW374, IC : 8595A-JODYW374 HVIN : JODY-W377-00A, FCC ID : XPYJODYW377, IC : 8595A-JODYW377 HVIN : JODY-W377-00B, FCC ID : XPYJODYW377, IC : 8595A-JODYW377 info@u-blox.com support@u-blox.com Label location information for JODY-W3 series modules The product label is affixed on to the module shield cover as shown in Figure 1. The size of the label is 17 x 11 mm and contains the following information:

A Data Matrix formatted bar code, with a unique serial number Date of unit production formatted YY/WW (year/week) Major and minor product version info Product marketing name (e.g. JODY-W374-00A, JODY-W374-00B, JODY-W377-00A, JODY-

W377-00B) Figure 1: Label of the JODY-W374-00A module Figure 2: Label of the JODY-W374-00B module Figure 3: Label of the JODY-W377-00A module Figure 4: Label of the JODY-W377-00b module Figure 2: Actual size of the JODY-W3 modules identifier marking (17 x 11 mm) Figure 3: Label location of the JODY-W3 modules

 

 

 

 

 

 

Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Company number: CH-020.3.020.161-7 info@u-blox.com support@u-blox.com Attn: Reviewing Engineer Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 HVIN:

JODY-W374-00A FCC Certification Number:

XPYJODYW374 Approval Date:

December 2, 2022 Application to Class II Permissive Change This request is to add three new module variants to the existing FCC ID XPYJODYW374:

JODY-W354-00A JODY-W354-20A JODY-W374-20A Compared to the already certified JODY-W374-00A module:

the new JODY-W354-00A module has a pin-to-pin compatible Chipset change moving from NXP 88Q9098 to NXP AW690. Both 88Q9098 and AW690 have same design both from digital baseband and internal RF blocks point of view. Also, those chipsets are constituted of the same die with the AW690 being lower cost. the new JODY-W354-20A is a JODY-W354-00A module to which a LTE filter (SAW-type filter) has been added in the 2.4GHz WLAN and Bluetooth receive/transmit RF-paths the new JODY-W374-20A is a JODY-W374-00A module to which a LTE filter (SAW-type filter) has been added in the 2.4GHz WLAN and Bluetooth receive/transmit RF-paths To compare the measurement results of the new JODY-W354-00A module with the already certified JODY-W374-00A module, the following tests were performed:

Conducted Emissions at AC Mains Occupied Bandwidth (6 dB) Occupied Bandwidth (99%) Band Edge Compliance Conducted Band Edge Compliance Radiated Peak Power Output Spurious RF Conducted Emissions Transmitter Spurious Radiated Emissions Power Density To verify the impact on measurement results of the modules with LTE filter (JODY-W354-20A and JODY-W374-20A) and compare with the already certified module, the following tests were performed on the 2.4GHz band. Other points are covered by measurements conducted either on JODY-W374-00A or JODY-W354-00A:

Peak Power Output Transmitter Spurious Radiated Emissions Band Edge Compliance Radiated Thank you for your attention in this matter. Yours Sincerely, _______________________________ Filip Kruzela Certification Manager, u-blox AG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Attn: Director of Certification Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 Authority to Act as Agent Model / HVIN: JODY-W354-20A, JODY-W374-20A, JODY-W354-00A JODY-W354-20A, JODY-W374-20A, JODY-W354-00A PMN:

XPYJODYW374 FCC ID:

8595A-JODYW374 IC:

To whom it may concern:

Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Company number: CH-020.3.020.161-7 info@u-blox.com support@u-blox.com 7Layers GmbH is authorized to act on our behalf, until otherwise notified, for applications to American Certification Body, Inc. (ACB). We certify that we are not subject to denial of federal benefits, that includes FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 862. Further, no party, as defined in 47 CFR 1.2002 (b), to the application is subject to denial of federal benefits, that includes FCC benefits. We also declare that the information provided to the FCC is true and correct to the best of our knowledge

(47 CFR 2.911(d)) and we have been informed of the grantee responsibilities (47 CFR 2.909) with regard to certified equipment. Thank you, Agency Agreement Expiration Date:

08/22/2023 Sincerely, Applicants Company:

Address:

u-blox AG Zrcher Strasse 68, CH-8800 Thalwil, Switzerland Job Title and Dept.:

_______________________________ Filip Kruzela Certification Manager

 

 

Attn: Reviewing Engineer Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Company number: CH-020.3.020.161-7 info@u-blox.com support@u-blox.com Certification Application RE:

Model / HVIN:

PMN:

FCC ID:

IC:

JODY-W354-20A, JODY-W374-20A, JODY-W354-00A JODY-W354-20A, JODY-W374-20A, JODY-W354-00A XPYJODYW374 8595A-JODYW374 Request for Long/Short-term Confidentiality To whom it may concern:

Pursuant to sections 0.457(d) and 0.459 of CFR 47 and to avoid premature release of sensitive information prior to marketing or release of the product to the public, we hereby requests long-term confidential treatment of information accompanying this application as outlined below:

Schematics Block Diagram Detailed Operational Description Software security and software configuration description incl. software configuration control declaration In addition we hereby request the following exhibits contained in this application to be temporarily

(short-term confidentiality) withheld from the public disclosure for an initial period of days until:

not applicable External Photos Internal Photos Test Setup Photos Users Manual The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these matters might be harmful to the applicant and provide unjustified benefits to its competitors. The applicant understands that pursuant to rule 0.457(d), disclosure of this application and all accompanying documentation will not be made before the date of the GRANT for this application. Thank you for your attention in this matter. Please contact the one signed below or the authorized agent for this filing. Thank you. Applicants Company:

Address:

u-blox AG Zrcher Strasse 68, CH-8800 Thalwil, Switzerland _______________________________ Filip Kruzela Job Title and Dept.:

Certification Manager

 

 

THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Request for Modular/Limited Modular Approval Date: September 9, 2022 Subject: Manufacturers Declaration for - Modular Approval

- Split Modular Approval

- Limited Modular Approval - Limited Split Modular Approval Confidentiality Request for: XPYJODY374 8 Basic Requirements FCC Part 15.212(a)(1) For Items Marked NO(*), the Limited Module Description Must be Filled Out on the Following Pages Modular Approval Requirement Requirement Met 1. The modular transmitter must have its own RF shielding. This is intended to ensure that the module does not have to rely upon the shielding provided by the device into which it is installed in order for all modular transmitter emissions to comply with FCC limits. It is also intended to prevent coupling between the RF circuitry of the module and any wires or circuits in the device into which the module is installed. Such coupling may result in non-compliant operation. The physical crystal and tuning capacitors may be located external to the shielded radio elements. 15.212(a)(1)(i)

- YES - NO(*) Details: <example The module contains a metal shield which covers all RF components and circuitry. The shield is located on the top of the board next to antenna connector>

2. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with FCC requirements under conditions of excessive data rates or over-modulation. 15.212(a)(1)(ii)

- YES - NO(*) Details: <example Data to the modulation circuit is buffered as described in the operational description provided with the application>

3. The modular transmitter must have its own power supply regulation on the module. This is intended to ensure that the module will comply with FCC requirements regardless of the design of the power supplying circuitry in the device into which the module is installed. 15.212(a)(1)(iii)

- YES - NO(*) Details: <example The module contains its own power supply regulation. Please refer to schematic filed with this application>

4. The modular transmitter must comply with the antenna and transmission system requirements of 15.203, 15.204(b), 15.204(c), 15.212(a), and 2.929(b). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph 15.212(b). 15.212(a)(1)(iv)

- YES - NO(*) Details: <example The module connects to its antenna using an UFL connector which is considered a non-standard connector. A list of antennas tested and approved with this device may be found in users manual provided with the application>

5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified or commercially available (see Section 15.31(i)). 15.212(a)(1)(v)

- YES - NO(*) Details: <example The module was tested stand-alone as shown in test setup photographs filed with this application>

070920-02b THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Modular Approval Requirement 6. The modular transmitter must be labeled with its own FCC ID number, or use an electron display (see Requirement Met KDB Publication 784748). If using a permanently affixed label with its own FCC ID number, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: XYZMODEL1 or Contains FCC ID:

XYZMODEL1. Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization. If the modular transmitter uses an electronic display of the FCC identification number, the information must be readily accessible and visible on the modular transmitter or on the device in which it is installed. If the module is installed inside another device, then the outside of the device into which the module is installed must display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains FCC certified transmitter module(s). Any similar wording that expresses the same meaning may be used. The user manual must include instructions on how to access the electronic display. A copy of these instructions must be included in the application for equipment authorization. 15.212(a)(1)(vi)

- YES - NO(*) Details: <example There is a label on the module as shown in the labeling exhibit filed with this application. Host specific labeling instructions are shown in the installation manual .filed with this application.>

7. The modular transmitter must comply with all specific rule or operating requirements applicable to the transmitter, including all the conditions provided in the integration instructions by the grantee. A copy of these instructions must be included in the application for equipment authorization. For example, there are very strict operational and timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. 15.212(a)(1)(vii)

- YES - NO(*) Details: <example The module complies with FCC Part 15C requirements. Instructions to the OEM installer are provided in the installation manual filed with this application.>

8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance in accordance with Section 15.247(b)(4). Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. 15.212(a)(1)(viii)

- YES - NO(*) Details: <example The module meets Portable exclusion levels as shown in the RF exposure information filed with this application.>

070920-02b THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Limited Module Description When Applicable

* If a module does NOT meet one or more of the above 8 requirements, the applicant may request Limited Modular Approval (LMA). This Limited Modular Approval (LMA) is applied with the understanding that the applicant will demonstrate and will retain control over the final installation of the device, such that compliance of the end product is always assured. The operating condition(s) for the LMA;

the module is only approved for use when installed in devices produced by grantee. A description regarding how control of the end product, into which the module will be installed, will be maintained by the applicant/manufacturer, such that full compliance of the end product is always ensured should be provided here. Details: <example - N/A>

Software Considerations KDB 594280 / KDB 442812 (One of the following 2 items must be applied) Requirement 1. For non-Software Defined Radio transmitter modules where software is used to ensure compliance of the device, technical description must be provided about how such control is implemented to ensure prevention of third-party modification; see KDB Publication 594280. Requirement Met

- Provided in Separate Cover Letter

- N/A Details: <example The firmware of the device can not be modified or adjusted by the end user as described in a separate cover letter filed with this application. >

2. For Software Defined Radio (SDR) devices, transmitter module applications must provide a software security description; see KDB Publication 442812.

- Provided in Separate Cover Letter

- N/A Details: <example N/A>

Split Modular Requirements Requirement Provided in Manual 1. For split modular transmitters, specific descriptions for secure communications between front-end and control sections, including authentication and restrictions on third-party modifications; also, instructions to third-party integrators on how control is maintained.

- Provided in Separate Cover Letter

- N/A Details: <example N/A >

070920-02b THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD OEM Integration Manual Guidance KDB 996369 D03 Section 2 Clear and Specific Instructions Describing the Conditions, Limitations, and Procedures for third-parties to use and/or integrate the module into a host device. Requirement Is this module intended for sale to third parties?

- YES

- No, If No, and LMA applies, the applicant can optionally choose to not make the following detailed info public. However there still needs to be basic integration instructions for a users manual and the information below must still be included in the operational description. If the applicant wishes to keep this info confidential, this will require a separate statement cover letter explaining the module is not for sale to third parties and that integration instructions are internal confidential documents. Items required to be in the manual See KDB 996369 D03, Section 2 As of May 1, 2019, the FCC requires ALL the following information to be in the installation manual. Modular transmitter applicants should include information in their instructions for all these items indicating clearly when they are not applicable. For example information on trace antenna design could indicate Not Applicable. Also if a module is limited to only a grantees own products and not intended for sale to third parties, the user instructions may not need to be detailed and the following items can be placed in the operational description, but this should include a cover letter as cited above. 1. List of applicable FCC rules. KDB 996369 D03, Section 2.2 a. Only list rules related to the transmitter. 2. Summarize the specific operational use conditions. KDB 996369 D03, Section 2.3 a. Conditions such as limits on antennas, cable loss, reduction of power for point to point 3. Limited Module Procedures. KDB 996369 D03, Section 2.4 systems, professional installation info a. Describe alternative means that the grantee uses to verify the host meets the necessary limiting conditions b. When RF exposure evaluation is necessary, state how control will be maintained such that compliance is ensured, such as Class II for new hosts, etc. 4. Trace antenna designs. KDB 996369 D03, Section 2.5 a. Layout of trace design, parts list, antenna, connectors, isolation requirements, tests for design verification, and production test procedures for ensuring compliance. If confidential, the method used to keep confidential must be identified and information provided in the operational description. 5. RF exposure considerations. KDB 996369 D03, Section 2.6 a. Clearly and explicitly state conditions that allow host manufacturers to use the module. Two types of instructions are necessary: first to the host manufacturer to define conditions (mobile, portable xx cm from body) and second additional text needed to be provided to the end user in the host product manuals. 6. Antennas. KDB 996369 D03, Section 2.7 a. List of antennas included in the application and all applicable professional installer instructions when applicable. The antenna list shall also identify the antenna types

(monopole, PIFA, dipole, etc note that omni-directional is not considered a type) 7. Label and compliance information. KDB 996369 D03, Section 2.8 a. Advice to host integrators that they need to provide a physical or e-label stating Contains FCC ID: with their finished product

- All Items shown to the left are provided in the Modular Integration Guide (or UM) for Full Modular Approval (MA) or LMA.

- An LMA applies and is approved ONLY for use by the grantee in their own products, and not intended for sale to 3rd parties as provided in a separate cover letter. Therefore the information shown to the left is found in the theory of operation. a. 8. Information on test modes and additional testing requirements. KDB 996369 D03, Section 2.9 Test modes that should be taken into consideration by host integrators including clarifications necessary for stand-alone and simultaneous configurations. Provide information on how to configure test modes for evaluation 9. Additional testing, Part 15 Subpart B disclaimer. KDB 996369 D03, Section 2.10 b. Sincerely, By:

(Signature/Title1) Melanie Anastassiou, Project Manager (7layers GmbH)

(Print name) 1 - Must be signed by applicant contact given for applicant on the FCC site, or by the authorized agent if an appropriate authorized agent letter has been provided. Letters should be placed on appropriate letterhead. 070920-02b

 

 

 

 

 

 

 

 

 

 

ELECTRICAL SPECIFICATION Model Name Operating Frequency (MHz) VSWR max Gain (dBi) Nominal Impedance (Ohms) Polarization MECHANICAL SPECIFICATION Dimensions mm (inches) Weight g (oz.) Radome Material 001-0012 Waterproof Dipole Antenna 2400-2500 MHz/4910-5850 MHz 001-0012 2400-2500 4910-5850 2.0 2.5:1 50 Linear vertical 2.0 114.0 x 13.0 (4.94 x 0.51) 18.0 (0.63) Black ENVIRONMENTAL SPECIFICATION Operating Temperature C (F)

-40 to +85C (-40 to +185F) UL Rating Ingress Protection Rating CONFIGURATION UL 94HB IP67 PART NUMBER DESCRIPTION 001-0012 080-0013 080-0014 2.4/5.5 GHz waterproof dipole antenna for Reverse Polarity SMA connector U.FL to Reverse Polarity SMA cable, 105 mm, O-ring seal U.FL to Reverse Polarity SMA cable, 210 mm, O-ring seal DATA AND DEVICES / 001-0012 MECHANICAL DRAWING TYPICAL ANTENNA REFLECTION PERFORMANCE Straight Antenna Position Bent Antenna Position 2 DATA AND DEVICES / 001-0012 RADIATION PATTERNS 2.4 GHz (E-Plane) 2.4 GHz (H-Plane) 5 GHz (E-Plane) 5 GHz (H-Plane) te.comTE Connectivity, TE Connectivity (logo) and Every Connection Counts are trademarks. All other logos, products and/or company names referred to herein might be trademarks of their respective owners.The information given herein, including drawings, illustrations and schematics which are intended for illustration purposes only, is believed to be reliable. However, TE Connectivity makes no warranties as to its accuracy or completeness and disclaims any liability in connection with its use. TE Connectivitys obligations shall only be as set forth in TE Connectivitys Standard Terms and Conditions of Sale for this product and in no case will TE Connectivity be liable for any incidental, indirect or consequential damages arising out of the sale, resale, use or misuse of the product. Users of TE Connectivity products should make their own evaluation to determine the suitability of each such product for the specific application.TE warrants to the original end user customer of its products that its products are free from defects in material and workmanship. Subject to conditions and limitations TE will, at its option, either repair or replace any part of its products that prove defective because of improper workmanship or materials. This limited warranty is in force for the useful lifetime of the original end product into which the TE product is installed. Useful lifetime of the original end product may vary but is not to exceed five (5) years from the original date of the end product purchase.2021 TE Connectivity. All Rights Reserved.10/21 Original USA: +1 (800) 522-6752Canada: +1 (905) 475-6222Mexico: +52 (0) 55-1106-0800Latin/S. America: +54 (0) 11-4733-2200Germany: +49 (0) 6251-133-1999UK: +44 (0) 800-267666France: +33 (0) 1-3420-8686Netherlands: +31 (0) 73-6246-999China: +86 (0) 400-820-6015TE TECHNICAL SUPPORT CENTERDATA AND DEVICES / 001-0012

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Attn: Director of Certification Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 Authority to Act as Agent Model / HVIN:

PMN:

FCC ID:

IC:

JODY-W374-00A, JODY-W374-00B JODY-W374-00A, JODY-W374-00B XPYJODYW374 8595A-JODYW374 To whom it may concern:

Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Company number: CH-020.3.020.161-7 info@u-blox.com support@u-blox.com 7Layers GmbH is authorized to act on our behalf, until otherwise notified, for applications to American Certification Body, Inc. (ACB). We certify that we are not subject to denial of federal benefits, that includes FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, 21 U.S.C. 862. Further, no party, as defined in 47 CFR 1.2002 (b), to the application is subject to denial of federal benefits, that includes FCC benefits. We also declare that the information provided to the FCC is true and correct to the best of our knowledge (47 CFR 2.911(d)) and we have been informed of the grantee responsibilities (47 CFR 2.909) with regard to certified equipment. Thank you, Agency Agreement Expiration Date:

08/22/2023 Sincerely, Applicants Company:

Address:

u-blox AG Zrcher Strasse 68, CH-8800 Thalwil, Switzerland Job Title and Dept.:

_______________________________ Filip Kruzela Certification Manager

 

 

Attn: Reviewing Engineer Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 Certification Application RE:

Model / HVIN:

PMN:

FCC ID:

IC:

JODY-W374-00A, JODY-W374-00B JODY-W374-00A, JODY-W374-00B XPYJODYW374 8595A-JODYW374 Registered office:

u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Company number: CH-020.3.020.161-7 info@u-blox.com support@u-blox.com Request for Long/Short-term Confidentiality To whom it may concern:

Pursuant to sections 0.457(d) and 0.459 of CFR 47 and to avoid premature release of sensitive information prior to marketing or release of the product to the public, we hereby requests long-term confidential treatment of information accompanying this application as outlined below:

Schematics Block Diagram Detailed Operational Description Software security and software configuration description incl. software configuration control declaration In addition we hereby request the following exhibits contained in this application to be temporarily

(short-term confidentiality) withheld from the public disclosure for an initial period of days until:

not applicable External Photos Internal Photos Test Setup Photos Users Manual The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these matters might be harmful to the applicant and provide unjustified benefits to its competitors. The applicant understands that pursuant to rule 0.457(d), disclosure of this application and all accompanying documentation will not be made before the date of the GRANT for this application. Thank you for your attention in this matter. Please contact the one signed below or the authorized agent for this filing. Thank you. Applicants Company:

Address:

u-blox AG Zrcher Strasse 68, CH-8800 Thalwil, Switzerland Job Title and Dept.:

_______________________________ Filip Kruzela Certification Manager

 

 

Doc ID: UBX-16015789

@Pbiox ae Authorization Letter Date: 01/08/2019 Power of Attorney Issued by u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44722 7444 Fax: +41 447227447 info@u-blox.com Subject: Authorization letter for FCC/IC signatures To Whom It May Concern:

1am Giulio Comar, Certification Manager and responsible for FCC and IC applications within u-blox.

| hereby authorise the following u-blox employees to sign all application forms, documents and cover letters on my behalf:

Piero Laudicina Jake Bascon Olof Viklund Filip Kruzela Cam Nichols Sincerely, pk Italia S.p.A. is a wholly owned subsidiary of u-blox AG

v Author Giulio Comar Department: cert Page: 1/1 Filename FCC_IC_signature_Authorization_Letter.docx M102 Ret Copyright 2013 u-biox Italia S.p.A. All rights reserved Confidential