FCC ID: XPYLISAU200 UMTS/GSM data and voice module

 

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, e t a c o i l 33.2 x 22.4 x 2.6 mm LISA-U series 3.75G HSPA / HSPA+

Wireless Modules System Integration Manual Abstract This document describes the features and the system integration of LISA-U1 series HSPA and LISA-U2 series HSPA+ wireless modules. These modules are a complete and cost efficient 3.75G solution offering up to six-band HSDPA/HSUPA and quad-band GSM/EGPRS voice and/or data transmission technology in a compact form factor. www.u-blox.com LISA-U series - System Integration Manual Document Information Title Subtitle LISA-U series 3.75G HSPA / HSPA+

Wireless Modules Document type System Integration Manual Document number 3G.G2-HW-10002-A1 Document status Advance Information Document status information Objective Specification This document contains target values. Revised and supplementary data will be published later. Advance Information Preliminary This document contains data based on early testing. Revised and supplementary data will be published later. This document contains data from product verification. Revised and supplementary data may be published later. Released This document contains the final product specification. This document applies to the following products:

Name Type number Firmware version PCN / IN LISA-U100 LISA-U100-00S-00 LISA-U100-01S-00 LISA-U110 LISA-U110-00S-00 LISA-U110-01S-00 LISA-U120 LISA-U120-00S-00 LISA-U120-01S-00 LISA-U130 LISA-U130-00S-00 LISA-U130-01S-00 LISA-U130-01A-00 LISA-U200 LISA-U200-00S-00 LISA-U200-01S-00 LISA-U230 LISA-U230-01S-00 LISA-U230-01A-00 10.72 11.40 10.72 11.40 10.72 11.40 10.72 11.40 11.40 TBD TBD TBD TBD 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. n.a. N/A N/A N/A N/A This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They can be downloaded from www.u-blox.com. u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without express permission is strictly prohibited. Copyright 2012, u-blox AG. u-blox is a registered trademark of u-blox Holding AG in the EU and other countries. 3G.G2-HW-10002-A1 Page 2 of 160 LISA-U series - System Integration Manual Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development. AT Commands Manual: This document provides the description of the supported AT commands by the LISA-U series modules to verify all implemented functionalities. System Integration Manual: This Manual provides hardware design instructions and information on how to set up production and final product tests. Application Note: document provides general design instructions and information that applies to all u-blox Wireless modules. See Section Related documents for a list of Application Notes related to your Wireless Module. How to use this Manual The LISA-U series System Integration Manual provides the necessary information to successfully design in and configure these u-blox wireless modules. This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance. A warning symbol indicates actions that could negatively impact or damage the module. Questions If you have any questions about u-blox Wireless Integration, please:

Read this manual carefully. Contact our information service on the homepage http://www.u-blox.com Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com Technical Support Worldwide Web Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and helpful FAQ can be accessed 24h a day. By E-mail Contact the nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal email address of our staff. This makes sure that your request is processed as soon as possible. You will find the contact details at the end of the document. Helpful Information when Contacting Technical Support When contacting Technical Support please have the following information ready:

Module type (e.g. LISA-U100) and firmware version Module configuration Clear description of your question or the problem A short description of the application Your complete contact details 3G.G2-HW-10002-A1 Advance Information Preface Page 3 of 160 LISA-U series - System Integration Manual Contents Preface ................................................................................................................................ 3 Contents .............................................................................................................................. 4 1.6 1.7 1.8 1.2.1 1.2.2 1 System description ....................................................................................................... 7 1.1 Overview .............................................................................................................................................. 7 1.2 Architecture .......................................................................................................................................... 9 Functional blocks ......................................................................................................................... 10 Hardware differences between LISA-U series modules ................................................................. 12 Pin-out ............................................................................................................................................... 13 1.3 1.4 Operating modes ................................................................................................................................ 17 Power management ........................................................................................................................... 19 1.5 Power supply circuit overview ...................................................................................................... 19 1.5.1 1.5.2 Module supply (VCC) .................................................................................................................. 20 Current consumption profiles ...................................................................................................... 28 1.5.3 RTC Supply (V_BCKP) .................................................................................................................. 32 1.5.4 1.5.5 Interface supply (V_INT) ............................................................................................................... 34 System functions ................................................................................................................................ 35 1.6.1 Module power-on ....................................................................................................................... 35 1.6.2 Module power-off ....................................................................................................................... 39 1.6.3 Module reset ............................................................................................................................... 40 RF connection ..................................................................................................................................... 42

(U)SIM interface .................................................................................................................................. 42

(U)SIM functionality ..................................................................................................................... 44 Serial communication ......................................................................................................................... 45 Serial interfaces configuration ..................................................................................................... 45 1.9.1 Asynchronous serial interface (UART)........................................................................................... 46 1.9.2 USB interface............................................................................................................................... 61 1.9.3 1.9.4 SPI interface ................................................................................................................................ 64 1.9.5 MUX Protocol (3GPP 27.010) ...................................................................................................... 68 DDC (I2C) interface .......................................................................................................................... 69 1.10.1 Overview ..................................................................................................................................... 69 1.10.2 DDC application circuit ................................................................................................................ 69 Audio Interface ............................................................................................................................... 74 1.11.1 Analog Audio interface ............................................................................................................... 74 1.11.2 Digital Audio interface ................................................................................................................. 80 1.11.3 Voiceband processing system ...................................................................................................... 85 General Purpose Input/Output (GPIO) ............................................................................................. 87 Reserved pins (RSVD) ...................................................................................................................... 96 Schematic for LISA-U series module integration .............................................................................. 97 Approvals ........................................................................................................................................ 99 1.12 1.13 1.14 1.15 1.8.1 1.10 1.11 1.9 3G.G2-HW-10002-A1 Advance Information Contents Page 4 of 160 LISA-U series - System Integration Manual 1.15.1 R&TTED and European Conformance CE mark ............................................................................ 99 IC ................................................................................................................................................ 99 1.15.2 1.15.3 Federal communications commission notice .............................................................................. 100 1.15.4 a-tick AUS Certification ............................................................................................................. 103 2.2 2.1 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 2 Design-In ................................................................................................................... 104 Design-in checklist ............................................................................................................................ 104 Schematic checklist ................................................................................................................... 104 Layout checklist ......................................................................................................................... 105 Antenna checklist ...................................................................................................................... 105 Design Guidelines for Layout ............................................................................................................ 106 Layout guidelines per pin function ............................................................................................. 106 Footprint and paste mask .......................................................................................................... 116 Placement ................................................................................................................................. 118 Thermal aspects ................................................................................................................................ 119 Antenna guidelines ........................................................................................................................... 120 Antenna termination ................................................................................................................. 121 Antenna radiation ..................................................................................................................... 122 Antenna detection functionality ................................................................................................ 123 ESD precautions ................................................................................................................................ 126 ESD immunity test overview ...................................................................................................... 126 ESD immunity test of LISA-U series reference design.................................................................. 126 ESD application circuits .............................................................................................................. 128 2.5.1 2.5.2 2.5.3 2.4.1 2.4.2 2.4.3 2.3 2.4 2.5 3.2 3.1 3.1.1 3.1.2 3 Features description ................................................................................................. 131 Firmware (upgrade) Over AT (FOAT) ................................................................................................. 131 Overview ................................................................................................................................... 131 FOAT procedure ........................................................................................................................ 131 TCP/IP and UDP/IP ............................................................................................................................. 131 3.2.1 Multiple PDP contexts and sockets............................................................................................. 131 FTP and FTPS .................................................................................................................................... 132 HTTP and HTTPS ............................................................................................................................... 132 AssistNow clients and GPS integration .............................................................................................. 132 Jamming Detection ........................................................................................................................... 132 In-Band modem ................................................................................................................................ 133 Smart Temperature Management ..................................................................................................... 133 Smart Temperature Supervisor (STS) .......................................................................................... 134 Threshold Definitions ................................................................................................................. 136 Hybrid positioning and CellLocate ..................................................................................................... 136 Positioning through cellular information: CellLocate .................................................................. 136 Hybrid positioning ..................................................................................................................... 138 3.3 3.4 3.5 3.6 3.7 3.8 3.8.1 3.8.2 3.9.1 3.9.2 3.9 4 Handling and soldering ........................................................................................... 139 Packaging, shipping, storage and moisture preconditioning ............................................................. 139 Soldering .......................................................................................................................................... 139 4.1 4.2 3G.G2-HW-10002-A1 Advance Information Contents Page 5 of 160 LISA-U series - System Integration Manual Soldering paste.......................................................................................................................... 139 4.2.1 Reflow soldering ....................................................................................................................... 139 4.2.2 Optical inspection ...................................................................................................................... 141 4.2.3 Cleaning .................................................................................................................................... 141 4.2.4 4.2.5 Repeated reflow soldering ......................................................................................................... 141 4.2.6 Wave soldering.......................................................................................................................... 141 Hand soldering .......................................................................................................................... 141 4.2.7 Rework ...................................................................................................................................... 141 4.2.8 4.2.9 Conformal coating .................................................................................................................... 141 4.2.10 Casting ...................................................................................................................................... 142 4.2.11 Grounding metal covers ............................................................................................................ 142 4.2.12 Use of ultrasonic processes ........................................................................................................ 142 5.1 5.2 5 Product Testing......................................................................................................... 143 u-blox in-series production test ......................................................................................................... 143 Test parameters for OEM manufacturer ............................................................................................ 143 Go/No go tests for integrated devices ...................................................................................... 144 Functional tests providing RF operation ..................................................................................... 144 5.2.1 5.2.2 Appendix ........................................................................................................................ 147 A.2.1 A Migration to LISA-U2 series wireless modules ....................................................... 147 A.1 Checklist for migration ..................................................................................................................... 147 A.2 Software migration ........................................................................................................................... 148 Software migration from LISA-U1 series to LISA-U2 series wireless modules .............................. 148 A.3 Hardware migration.......................................................................................................................... 148 Hardware migration from LISA-U1 series to LISA-U2 series wireless modules ............................. 148 Pin-out comparison LISA-U1 series vs. LISA-U2 series ................................................................. 149 Layout comparison LISA-U1 series vs. LISA-U2 series .................................................................. 155 A.3.1 A.3.2 A.3.3 B Glossary .................................................................................................................... 156 Related documents......................................................................................................... 158 Revision history .............................................................................................................. 159 Contact ............................................................................................................................ 160 3G.G2-HW-10002-A1 Advance Information Contents Page 6 of 160 LISA-U series - System Integration Manual 1 System description 1.1 Overview LISA-U series wireless modules integrate full-feature 3G UMTS/HSxPA and 2G GSM/GPRS/EDGE protocol stack with Assisted GPS support. These SMT modules come in the compact LISA form factor, featuring Leadless Chip Carrier (LCC) packaging technology. 3G UMTS/HSDPA/HSUPA Characteristics 2G GSM/GPRS/EDGE Characteristics Class A User Equipment1 UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD) 3GPP Release 6 High Speed Packet Access (HSPA) for LISA-U1 series 3GPP Release 7 Evolved High Speed Packet Access (HSPA+) for LISA-U2 series Rx Diversity for LISA-U230 Band II (1900 MHz), Band V (850 MHz) 2-band support for LISA-U100, LISA-U120:

2-band support for LISA-U110, LISA-U130:

4-band support for LISA-U200-00:

Band I (2100 MHz), Band VIII (900 MHz) Band I (2100 MHz), Band II (1900 MHz), Band V (850 MHz), Band VI (800 MHz) 6-band support for LISA-U200-01, LISA-U230:

Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) WCDMA/HSDPA/HSUPA Power Class Power Class 3 (24 dBm) for WCDMA/HSDPA/HSUPA mode PS (Packet Switched) Data Rate HSUPA category 6, up to 5.76 Mb/s UL HSDPA category 8 up to 7.2 Mb/s DL for LISA-U1 series, LISA-U200 HSDPA category 14 up to 21.1 Mb/s DL for LISA-U230 WCDMA PS data up to 384 kb/s DL/UL Class B Mobile Station2 GSM EDGE Radio Access (GERA) 3GPP Release 6 for LISA-U1 series 3GPP Release 7 for LISA-U2 series Rx Diversity for LISA-U230 4-band support GSM 850 MHz, E-GSM 900 MHz, DCS 1800 MHz, PCS 1900 MHz Power Class 4 (33 dBm) for GSM/E-GSM bands Power Class 1 (30 dBm) for DCS/PCS bands GSM/GPRS Power Class EDGE Power Class Power Class E2 (27 dBm) for GSM/E-GSM bands Power Class E2 (26 dBm) for DCS/PCS bands PS (Packet Switched) Data Rate GPRS multislot class 334, coding scheme CS1-CS4, up to 107 kb/s DL, 85.6 kb/s UL for LISA-U2 series GPRS multislot class 124, coding scheme CS1-CS4, up to 85.6 kb/s DL/UL for LISA-U1 for LISA-U1 series EDGE multislot class 333, coding scheme MCS1-MCS9, up to 296 kb/s DL, 236.8 kb/s UL for LISA-U2 EDGE multislot class 124, coding scheme MCS1-MCS9, up to 236.8 kb/s DL/UL for LISA-U1 CS (Circuit Switched) Data Rate WCDMA CS data up to 64 kb/s DL/UL CS (Circuit Switched) Data Rate GSM CS data up to 9.6 kb/s DL/UL supported in transparent/non transparent mode Table 1: LISA-U series UMTS/HSDPA/HSUPA and GSM/GPRS/EDGE characteristics Operation modes I to III are supported on GSM/GPRS network, with user-defined preferred service selectable from GSM to GPRS. Paging messages for GSM calls can be optionally monitored during GPRS data transfer in not-coordinating NOM II-III. Direct Link mode is supported for TCP / UDP sockets except for LISA-U1xx-00 module versions. 1 Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active 2 Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. If for example during data transmission an incoming call occurs, the data connection is suspended to allow the voice communication. Once the voice call has terminated, the data service is resumed. 3 GPRS/EDGE multislot class 33 implies a maximum of 5 slots in DL (reception) and 4 slots in UL (transmission) with 6 slots in total. 4 GPRS/EDGE multislot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total. 3G.G2-HW-10002-A1 Advance Information System description Page 7 of 160 LISA-U series - System Integration Manual Regarding 3G transmit and receive data rate capability, LISA-U series modules implement 3G High-Speed Uplink Packet Access (HSUPA) category 6, LISA-U1 series and LISA-U200 modules implement 3G High Speed Downlink Packet Access (HSDPA) category 8, while LISA-U230 modules implement the 3G HSDPA category 14. HSUPA and HSDPA categories determine the maximum speed at which data can be respectively transmitted and received:

higher categories allowing faster data transfer rates as indicated in Table 1. The 3G network automatically performs adaptive coding and modulation using a choice of forward error correction code rate and choice of modulation type, to achieve the highest possible data rate and data transmission robustness according to the quality of the radio channel. Regarding 2G transmit and receive data rate capability, LISA-U1 series modules implement GPRS/EGPRS class 12, while LISA-U2 series modules implement GPRS/EGPRS class 33. GPRS and EGPRS classes determine the maximum number of timeslots available for upload and download and thus the speed at which data can be transmitted and received: higher classes typically allowing faster data transfer rates as indicated in Table 1. The 2G network automatically configures the number of timeslots used for reception or transmission (voice calls take precedence over GPRS/EGPRS traffic) and channel encoding (from Coding Scheme 1 up to Modulation and Coding Scheme 9), performing link adaptation to achieve the highest possible data rate. A summary of interfaces and features provided by LISA-U series modules is described in the Table 2. Note that LISA-U130-01 and LISA-U230-01 are available in standard and automotive quality grade versions. Module Technology Bands Interface Audio Functions

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A P U S H A P D S H LISA-U100-00 5.76 7.2 850/1900 LISA-U100-01 5.76 7.2 850/1900 LISA-U110-00 5.76 7.2 900/2100 LISA-U110-01 5.76 7.2 900/2100 LISA-U120-00 5.76 7.2 850/1900 LISA-U120-01 5.76 7.2 850/1900 LISA-U130-00 5.76 7.2 900/2100 LISA-U130-01 5.76 7.2 900/2100 S P G x o b

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I P S 1 1 1 1 1 1 1 1 T R A U 1 1 1 1 1 1 1 1 B S U 1 1 1 1 1 1 1 1 I O P G 5 5 5 5 5 5 5 5 LISA-U200-00 5.76 7.2 LISA-U200-01 5.76 7.2 LISA-U230-01 5.76 21.1 800/850/

1900/2100 800/850/900/

1700/1900/2100 800/850/900/

1700/1900/2100 1 1 1 1 14 1 1 1 1 14 1 1 1 1 14 Table 2: LISA-U series features summary k c a t s P D U

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e l i f o r P s s e c c A M S I e t a c o L l l e C y t i s r e v d i x R 2 i o d u A g o a n A l 1 1 1 1 3G.G2-HW-10002-A1 Advance Information System description Page 8 of 160 LISA-U series - System Integration Manual 1.2 Architecture Figure 1: LISA-U1 series block diagram (for available options refer to the product features summary in Table 2) Figure 2: LISA-U2 series block diagram (for available options refer to the product features summary in Table 2) 3G.G2-HW-10002-A1 Advance Information System description Page 9 of 160 WirelessBase-bandProcessorMemoryPower Management UnitRF Transceiver26 MHz32.768 kHzSAWFilterFEM & 2G PAANTLNA3G PALNA3G PADDC (for GPS)(U)SIM CardUARTSPIUSBGPIO(s)Power OnExternal ResetV_BCKP (RTC)Vcc (Supply)V_INT (I/O)Digital Audio (I2S)AnalogAudioWirelessBase-bandProcessorMemoryPower Management Unit26 MHz32.768 kHzANTSwitch & Multi band & mode PADDC (for GPS)(U)SIM CardUARTSPIUSBGPIO(s)Power OnExternal ResetV_BCKP (RTC)Vcc (Supply)V_INT (I/O)Digital Audio (I2S)RFSWITCHRF TransceiverDuplexers& FiltersANT_DIVRFSWITCHFilterBankPA PMUTransceiver PMU LISA-U series - System Integration Manual 1.2.1 Functional blocks LISA-U series modules consist of the following internal functional blocks: RF section, Baseband and Power Management Unit section. LISA-U1 series RF section A shielding box includes the RF high-power signal circuitry, namely:

Front-End Module (FEM) with integrated quad-band 2G Power Amplifier and antenna switch multiplexer Two single-band 3G HSPA/WCDMA Power Amplifier modules with integrated duplexers The RF antenna pad (ANT) is directly connected to the FEM, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied to integrated SAW filters for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the 2G power amplifier module and then directed to the antenna through the FEM. The 3G transmitter and receiver are instead active at the same time due to frequency-domain duplex operation. The switch integrated in the FEM connects the antenna port to the passive duplexer which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the fixed gain linear power amplifier. In the same shielding box that includes the RF high-power signal circuitry there are all the low-level analog RF components, namely:

Dual-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO) Low Noise Amplifier (LNA) and SAW RF filters for 2G and 3G receivers While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the external LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing. For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted. In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal. The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode. LISA-U2 series RF section A shielding box contains the RF high-power signal circuitry, including:

Multimode Single Chain Power Amplifier Module used for 3G HSPA/WCDMA and 2G EDGE/GSM operations Power Management Unit with integrated DC/DC converter for the Power Amplifier Module The RF antenna pad (ANT) is directly connected to the main antenna switch, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied by the main antenna switch to the duplexer SAW filter bank for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the power amplifier and then directed to the antenna pad through the main antenna switch. The 3G transmitter and receiver are active at the same time due to frequency-

domain duplex operation. The switch integrated in the main antenna switch connects the antenna port to the duplexer SAW filter bank which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the power amplifier. 3G.G2-HW-10002-A1 Advance Information System description Page 10 of 160 LISA-U series - System Integration Manual A separated shielding box contains all the other analog RF components, including:

Main Antenna Switch Duplexer SAW filter bank Antenna Switch for diversity receiver SAW filter bank for diversity receiver Six-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Power Management Unit with integrated DC/DC converter for the Power Amplifier Module Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO) While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the integrated LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing. For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to the baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted. The RF antenna pad for the diversity receiver (ANT_DIV) available on LISA-U230 modules is directly connected to the antenna switch for the diversity receiver, which dispatches the incoming RF signals to the dedicated SAW filter bank for out-of-band rejection and then to the diversity receiver port of the RF transceiver. In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal. The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode. LISA-U series modulation techniques Modulation techniques related to radio technologies supported by LISA-U series modules, are listed as follows:

GSM GPRS EDGE GSMK GMSK GMSK / 8-PSK WCDMA QPSK HSDPA QPSK / 16-QAM HSUPA QPSK / 16-QAM LISA-U series Baseband and Power Management Unit section Another shielding box of LISA-U series modules includes all the digital circuitry and the power supplies, basically the following functional blocks:

Wireless baseband processor, a mixed signal ASIC which integrates:

Microprocessor for controller functions, 2G & 3G upper layer software DSP core for 2G Layer 1 and audio processing 3G coprocessor and HW accelerator for 3G Layer 1 control software and routines Dedicated HW for interfaces management Memory system in a Multi-Chip Package (MCP) integrating two devices:

NOR flash non-volatile memory DDR SRAM volatile memory Power Management Unit (PMU), used to derive all the system supply voltages from the module supply VCC 3G.G2-HW-10002-A1 Advance Information System description Page 11 of 160 LISA-U series - System Integration Manual 32.768 kHz crystal, connected to the Real Time Clock (RTC) oscillator to provide the clock reference in idle or power-off mode 1.2.2 Hardware differences between LISA-U series modules Main hardware differences between the LISA-U series modules are summarized in Table 3. Characteristic LISA-U1 series LISA-U2 series 3G bands Band II (1900 MHz), Band V (850 MHz) LISA-U100, LISA-U120:

LISA-U110, LISA-U130:

Band I (2100 MHz), Band VIII (900 MHz) HSDPA data rate LISA-U1 series:

HSDPA category 8, up to 7.2 Mb/s DL LISA-U200-00:

Band I (2100 MHz), Band II (1900 MHz), Band V (850 MHz), Band VI (800 MHz) LISA-U200-01, LISA-U230:

Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) LISA-U200:

LISA-U230:

HSDPA category 8, up to 7.2 Mb/s DL HSDPA category 14, up to 21.1 Mb/s DL EDGE/GPRS data rate EDGE multislot class 12, MCS1-MCS9, up to 236.8 kb/s DL/UL GPRS multislot class 12, CS1-CS4, up to 85.6 kb/s DL/UL EDGE multislot class 33, MCS1-MCS9, up to 296 kb/s DL, 236.8 kb/s UL GPRS multislot class 33, CS1-CS4, up to 107 kb/s DL, 85.6 kb/s UL Rx diversity LISA-U1 series:

Not supported Not supported LISA-U200:

LISA-U230:

Supported: ANT_DIV RF input for Rx diversity Analog audio Digital audio Not supported LISA-U100, LISA-U110:

LISA-U120, LISA-U130:

One differential input, one differential output LISA-U2 series:

Not supported Not supported LISA-U100, LISA-U110:

LISA-U120, LISA-U130:

One 4-wire digital audio interface Not supported LISA-U200-00:

LISA-U200-01, LISA-U230:

Two 4-wire digital audio interfaces CODEC_CLK clock output for external codec GPIO 5 GPIOs 14 GPIOs VCC operating range VCC normal operating range: 3.4 V 4.2 V VCC extended operating range: 3.1 V 4.2 V VCC normal operating range: 3.3 V 4.4 V VCC extended operating range: 3.1 V 4.5 V V_BCKP operating range V_BCKP output: 2.3 V typ. V_BCKP input: 1.0 V 2.5 V V_BCKP output: 1.8 V typ. V_BCKP input: 1.0 V 1.9 V Exposed GND area One signals keep-out area on the top layer of the application board, due to one exposed GND area on the bottom layer of the module (see Figure 61) Two signals keep-out areas on the top layer of the application board, due to two exposed GND areas on the bottom layer of the module (see Figure 62) Table 3: Main hardware differences between LISA-U series modules For additional details and minor hardware differences between the LISA-U series modules, refer to section A.3. 3G.G2-HW-10002-A1 Advance Information System description Page 12 of 160 LISA-U series - System Integration Manual 1.3 Pin-out Table 4 lists the pin-out of the LISA-U series modules, with pins grouped by function. Function Pin Module No I/O Description Remarks Power VCC All 61, 62, 63 I Module supply input Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided has to be always above the minimum limit of the operating range. Consider that there are large current spikes in connected mode, when a GSM call is enabled. VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize power loss due to series resistance. See section 1.5.2 GND pins are internally connected but a good

(low impedance) external ground connection can improve RF performance: all GND pins must be externally connected to ground. N/A Ground I/O O O I/O Real Time Clock supply input/output Digital Interfaces supply output SIM supply output RF input/output for main Tx/Rx antenna V_BCKP = 2.3 V (typical) on LISA-U1 series V_BCKP = 1.8 V (typical) on LISA-U2 series generated by the module when VCC supply voltage is within valid operating range. See section 1.5.4 V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. See section 1.5.5 VSIM = 1.80 V typical or 2.90 V typical generated by the module according to the SIM card type. See section 1.8 nominal impedance. 50 See section 1.7, section 2.4 and section 2.2.1.1 GND All V_BCKP All V_INT All VSIM All RF ANT All 1, 3, 6, 7, 8, 17, 25, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 60, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76 2 4 50 68 ANT_DIV LISA-U230 74 I RF input for Rx diversity antenna 50 nominal impedance See section 1.7, section 2.4 and section 2.2.1.1 SIM SIM_IO All SIM_CLK SIM_RST All All SPI SPI_MISO All 48 47 49 57 I/O SIM data O O O SIM clock SIM reset SPI Data Line Output SPI_MOSI All 56 I SPI Data Line Input Internal 4.7 k pull-up to VSIM. Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 Module Output: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. See section 1.9.4 Module Input: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.4 3G.G2-HW-10002-A1 Advance Information System description Page 13 of 160 Function Pin Module SPI_SCLK All SPI_SRDY All SPI_MRDY All DDC SCL SDA UART RxD All All All No 55 58 59 45 46 16 LISA-U series - System Integration Manual I/O Description Remarks I O I SPI Serial Clock Input SPI Slave Ready Output SPI Master Ready Input Module Input: module runs as an SPI slave. Idle low (CPOL=0). Internal active pull-down to GND enabled. See section 1.9.4 Module Output: module runs as an SPI slave. Idle low. See section 1.9.4 Module Input: module runs as an SPI slave. Idle low. Internal active pull- down to GND enabled. See section 1.9.4 O I2C bus clock line Fixed open drain. External pull-up required. See section 1.10 I/O I2C bus data line O UART data output Fixed open drain. External pull-up required. See section 1.10 Circuit 104 (RxD) in ITU-T V.24. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 103 (TxD) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 106 (CTS) in ITU-T V.24. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 TxD All 15 I UART data input CTS All 14 O RTS All 13 I UART clear to send output UART ready to send input DSR RI DTR DCD GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 All All All All All All All All All LISA-U2 LISA-U2 LISA-U2 LISA-U2 LISA-U2 LISA-U2 LISA-U2 9 10 12 11 20 21 23 24 51 39 40 53 54 55 56 57 O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O UART data set ready output Circuit 107 (DSR) in ITU-T V.24. See section 1.9.2 UART ring indicator output Circuit 125 (RI) in ITU-T V.24. See section 1.9.2 UART data terminal ready input Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.2 UART data carrier detect output Circuit 109 (DCD) in ITU-T V.24. See section 1.9.2 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 3G.G2-HW-10002-A1 Advance Information System description Page 14 of 160 GPIO Input for VBUS (5 V typical) USB supply sense to enable USB interface. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 90 nominal differential impedance Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 90 nominal differential impedance Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 PWR_ON pin has high input impedance. Do not keep floating in noisy environment:

external pull-up required. See section 1.6.1 Internal 10 k pull-up to V_BCKP. See section 1.6.3 Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1 Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1 LISA-U series - System Integration Manual I/O Description Remarks Function Pin GPIO13 GPIO14 Module LISA-U2 LISA-U2 USB VUSB_DET All No 58 59 18 I/O I/O I GPIO GPIO See section 1.12 See section 1.12 USB detect input USB_D-

All 26 I/O USB Data Line D-

USB_D+

All 27 I/O USB Data Line D+

System PWR_ON All 19 RESET_N All Analog Audio MIC_N LISA-U120 LISA-U130 MIC_P LISA-U120 LISA-U130 SPK_P LISA-U120 LISA-U130 SPK_N LISA-U120 LISA-U130 22 39 40 53 54 I I I I O O Power-on input External reset input Differential analog audio input (negative) Differential analog audio input (positive) Differential analog audio output (positive) Differential analog audio output (negative) Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode. See section 1.11.1 Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode. See section 1.11.1 Digital Audio I2S_CLK I2S_RXD I2S_TXD LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 43 I/O First I2S clock 44 I First I2S receive data 42 O First I2S transmit data Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. 3G.G2-HW-10002-A1 Advance Information System description Page 15 of 160 LISA-U series - System Integration Manual No 41 I/O I/O Description Remarks First I2S word alignment Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Function Pin Module I2S_WA LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 I2S1_CLK LISA-U200-01, LISA-U230 53 I2S1_RXD LISA-U200-01 LISA-U230 39 I2S1_TXD LISA-U200-01 LISA-U230 40 I/O Second I2S clock I O Second I2S receive data Second I2S transmit data I2S1_WA LISA-U200-01 LISA-U230 54 I/O Second I2S word alignment CODEC_CLK LISA-U200-01 LISA-U230 Reserved RSVD All RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD LISA-U1 LISA-U200-00 LISA-U1 LISA-U200 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U100 LISA-U110 LISA-U100 LISA-U110 LISA-U100 LISA-U110 52 5 52 74 43 44 42 41 39 40 53 54 O Clock output N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Digital clock output for external audio codec See section 1.11.2. This pin must be connected to ground See section 1.13 Pad disabled See section 1.13 Do not connect See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Table 4: LISA-U series modules pin definition, grouped by function 3G.G2-HW-10002-A1 Advance Information System description Page 16 of 160 LISA-U series - System Integration Manual 1.4 Operating modes LISA-U series modules have several operating modes. Table 5 summarizes the various operating modes and provides general guidelines for operation. Operating Mode Description Features / Remarks Transition condition General Status: Power-down Not-Powered Mode VCC supply not present or below operating range. Microprocessor switched off

(not operating). RTC only operates if supplied through V_BCKP pin. Power-Off Mode VCC supply within operating range. Microprocessor switched off

(not operating). Only RTC runs. General Status: Normal Operation Idle-Mode Microprocessor runs with 32 kHz as reference oscillator. Module does not accept data signals from an external device. Module is switched off. Application interfaces are not accessible. Internal RTC timer operates only if a valid voltage is applied to V_BCKP pin. Module is switched off: normal shutdown by AT+CPWROFF command (refer to u-blox AT Commands Manual [3]), or by PWR_ON held low for more than 1 s

(LISA-U2 series only). Application interfaces are not accessible. Only the internal RTC timer in operation. If power saving is enabled, the module automatically enters idle-mode whenever possible. Application interfaces are disabled. If hardware flow control is enabled, the CTS line to ON state indicates that the module is in active mode and the UART interface is enabled: the line is driven in the OFF state when the module is not prepared to accept data by the UART interface. If hardware flow control is disabled, the CTS line is fixed to ON state. Module by default is not set to automatically enter idle-mode whenever possible, unless power saving configuration is enabled by appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV). Module cannot be switched on by a falling edge provided on the PWR_ON input, or by a preset RTC alarm or by a rising edge provided on the RESET_N input. Module can be switched on applying VCC supply. Module can be switched on by a falling edge on the PWR_ON input, or by a preset RTC alarm, or by a rising edge on the RESET_N input. Module enters automatically idle-mode when power saving is enabled and there is no activity for the defined time interval:

Module registered with the network and power saving enabled. Periodically wakes up to active mode to monitor the paging channel for the paging block reception according to network indication Module not registered with the network and power saving is enabled. Periodically wakes up to monitor external activity Module wakes up from idle-mode to active-mode in the following events:

Incoming voice or data call RTC alarm occurs Data received on UART interface

(refer to 1.9.2) RTS input line set to the ON state by the DTE if the AT+UPSV=2 command is sent to the module

(refer to 1.9.2) USB detection, applying 5 V (typ.) to the VUSB_DET pin The connected USB host forces a remote wakeup of the module as USB device (refer to 1.9.3) The connected SPI master indicates to the module that it is ready for transmission or reception, by the SPI/IPC SPI_MRDY input signal

(refer to 1.9.4) 3G.G2-HW-10002-A1 Advance Information System description Page 17 of 160 LISA-U series - System Integration Manual Operating Mode Description Features / Remarks Transition condition If power saving is enabled, the module automatically enters idle-mode and application interfaces are disabled whenever possible (refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3], AT+UPSV). When call terminates, the module returns to the active operating mode. Active-Mode Microprocessor runs with 26 MHz as reference oscillator. The module is prepared to accept data signals from an external device. Connected-Mode Voice or data call enabled. Microprocessor runs with 26 MHz as reference oscillator. The module is prepared to accept data signals from an external device. Table 5: Module operating modes summary Module is switched on and is fully active. The application interfaces are enabled, unless power saving configuration is enabled by the AT+UPSV command (refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3]). Power saving is not enabled by default: it can be enabled by the AT+UPSV command (see u-blox AT Commands Manual [3]). The module is switched on and a voice call or a data call (2G/3G) is in progress. Module is fully active. The application interfaces are enabled, unless power saving configuration is enabled by the AT+UPSV command (see section 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [3]). Transition between the different modes is described in Figure 3. Figure 3: Operating modes transition 3G.G2-HW-10002-A1 Advance Information System description Page 18 of 160 Switch ON:Apply VCCIf power saving is enabled and there is no activity for a defined time intervalAny wake up event described in the module operating modes summary table aboveIncoming/outgoing call or other dedicated device network communicationCall terminated, communication droppedRemove VCCSwitch ON:PWR_ONRESET_NRTC AlarmNot poweredPower offActiveConnectedIdleSwitch OFF:AT+CPWROFFPWR_ON (LISA-U2 only) LISA-U series - System Integration Manual 1.5 Power management 1.5.1 Power supply circuit overview LISA-U series modules feature a power management concept optimized for the most efficient use of supplied power. This is achieved by hardware design utilizing a power efficient circuit topology (Figure 4), and by power management software controlling the modules power saving mode. Figure 4: LISA-U series power management simplified block diagram Pins with supply function are reported in Table 6, Table 11 and Table 14. LISA-U series modules must be supplied via the VCC pins. There is only one main power supply input, available on the three VCC pins that must be all connected to the external power supply 3G.G2-HW-10002-A1 Advance Information System description Page 19 of 160 Baseband Processor2G/3G Power Amplifier(s)Switching Step-Down5 x 10 F61VCC62VCC63VCC50VSIM2V_BCKP4V_INTLinear LDOLinear LDOSwitching Step-DownLinear LDOLinear LDOLinear LDOI/OEBUCOREAnalogSIMRTCNOR FlashDDR SRAMRF TransceiverMemoryPower Management Unit22 F10 F (LISA-U1)220 nF (LISA-U2)220 nF2G/3G PA PMU(LISA-U2)TransceiverPMU(LISA-U2)(LISA-U1) LISA-U series - System Integration Manual The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit

(PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators. V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time Clock can be externally supplied via the V_BCKP pin (see section 1.5.4). When a 1.8 V or a 3 V SIM card type is connected, LISA-U series modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance to the ISO-IEC 7816-3 specifications. The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-U series modules in the final application. The integrated Power Management Unit also provides the control state machine for system start up and system reset control. 1.5.2 Module supply (VCC) The LISA-U series modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system power supply circuit is able to support peak power (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the detailed specifications). Name VCC Description Module power supply input GND Ground Table 6: Module supply pins Remarks VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range. Consider that during a GSM call there are large current spikes in connected mode. GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads must be connected to ground. VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level can be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage normal operating range. The module cannot be switched on if the VCC voltage value is below the specified normal operating range minimum limit: ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for more than 1 s after the start of the switch-on of the module. 3G.G2-HW-10002-A1 Advance Information System description Page 20 of 160 LISA-U series - System Integration Manual When LISA-U series modules are in operation, the voltage provided to VCC pins can go outside the normal operating range limits but must be within the extended operating range limits specified in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Occasional deviations from the ETSI specifications may occur when the input voltage at VCC pins is outside the normal operating range and is within the extended operating range. LISA-U series modules switch off when VCC voltage value drops below the specified extended operating range minimum limit: ensure that the input voltage at VCC pins never drops below the minimum limit of the extended operating range when the module is switched on, not even during a GSM transmit burst, where the current consumption can rise up to maximum peaks of 2.5 A in case of a mismatched antenna load. Operation above the normal operating range maximum limit is not recommended and extended exposure beyond it may affect device reliability. Stress beyond the VCC absolute maximum ratings can cause permanent damage to the module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection. When designing the power supply for the application, pay specific attention to power losses and transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics:

o Voltage drop during transmit slots must be lower than 400 mV o No undershoot or overshoot at the start and at the end of transmit slots o Voltage ripple during transmit slots must be minimized:

lower than 70 mVpp if fripple 200 kHz lower than 10 mVpp if 200 kHz < fripple 400 kHz lower than 2 mVpp if fripple > 400 kHz Figure 5: Description of the VCC voltage profile versus time during a GSM call Any degradation in power supply performance (due to losses, noise or transients) will directly affect the RF performance of the module since the single external DC power source indirectly supplies all the digital and analog interfaces, and also directly supplies the RF power amplifier (PA). 3G.G2-HW-10002-A1 Advance Information System description Page 21 of 160 TimeundershootovershootripplerippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) LISA-U series - System Integration Manual The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms. This VCC slope allows a proper switch on of the module, that is switched on when the voltage rises to the VCC normal operating range starting from a voltage value lower than 2.25 V. 1.5.2.1 VCC application circuits LISA-U series modules must be supplied through the VCC pins by one (and only one) proper DC power supply that must be one of the following:

Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery Figure 6: VCC supply concept selection The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the LISA-U series modules operating supply voltage. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source. The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less than 5 V). In this case the typical 90% efficiency of the switching regulator will diminish the benefit of voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy in thermal power. If LISA-U series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided. The use of primary (not rechargeable) battery is uncommon, since the most cells available are seldom capable of delivering the burst peak current for a GSM call due to high internal resistance. Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in LISA-U series modules). The charger circuit should be designed in order to prevent over-voltage on VCC beyond the upper limit of the absolute maximum rating. The following sections highlight some design aspects for each of the supplies listed above. 3G.G2-HW-10002-A1 Advance Information System description Page 22 of 160 Main Supply Available?BatteryLi-Ion 3.7 VLinear LDO RegulatorMain Supply Voltage >5 V?Switching Step-Down RegulatorNo, portable deviceNo, less than 5 VYes, greater than 5 VYes, always available LISA-U series - System Integration Manual Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements:

Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current pulses with 1/8 duty cycle to the VCC pins Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile High switching frequency: for best performance and for smaller applications select a switching frequency 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in active mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the module changes status from idle/active mode to connected mode (where current consumption increases to a value greater than 100 mA): it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA) Output voltage slope: the use of the soft start function provided by some voltage regulator must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module Figure 7 and the components listed in Table 7 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high:

switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply. Figure 7: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator 3G.G2-HW-10002-A1 Advance Information System description Page 23 of 160 LISA-U series12VC6R3C5R2C3C2C1R1VINRUNVCRTPGSYNCBDBOOSTSWFBGND671095C71238114C8C9L2D1R4R5L1C4U162VCC63VCC61VCCGND LISA-U series - System Integration Manual Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 L1 L2 R1 R2 R3 R4 R5 U1 47 F Capacitor Aluminum 0810 50 V MAL215371479E3 - Vishay 10 F Capacitor Ceramic X7R 5750 15% 50 V C5750X7R1H106MB - TDK 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 680 pF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71H681KA01 - Murata 22 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H220JZ01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 470 nF Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E474KA12 - Murata 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor 10 H Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics 1 H Inductor 7445601 20% 8.6 A 7445601 - Wurth Electronics 470 k Resistor 0402 5% 0.1 W 15 k Resistor 0402 5% 0.1 W 22 k Resistor 0402 5% 0.1 W 390 k Resistor 0402 1% 0.063 W 100 k Resistor 0402 5% 0.1 W 2322-705-87474-L - Yageo 2322-705-87153-L - Yageo 2322-705-87223-L - Yageo RC0402FR-07390KL - Yageo 2322-705-70104-L - Yageo Step Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology Table 7: Suggested components for the VCC voltage supply application circuit using a step-down regulator Low Drop-Out (LDO) linear regulator The characteristics of the LDO linear regulator connected to the VCC pins should meet the following requirements:

Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper voltage value to the VCC pins and of delivering 2.5 A current pulses with 1/8 duty cycle Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator) Output voltage slope: the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module Figure 8 and the components listed in Table 8 show an example of a power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering 2.5 A current pulses, with proper power handling capability. The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to the 3.8 V typical value of the VCC supply. 3G.G2-HW-10002-A1 Advance Information System description Page 24 of 160 LISA-U series - System Integration Manual Figure 8: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator Reference Description Part Number - Manufacturer C1 C2 R1 R2 R3 U1 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata 47 k Resistor 0402 5% 0.1 W 4.7 k Resistor 0402 5% 0.1 W 2.2 k Resistor 0402 5% 0.1 W LDO Linear Regulator ADJ 3.0 A RC0402JR-0747KL - Yageo Phycomp RC0402JR-074K7L - Yageo Phycomp RC0402JR-072K2L - Yageo Phycomp LT1764AEQ#PBF - Linear Technology Table 8: Suggested components for VCC voltage supply application circuit using an LDO linear regulator Rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption to VCC pins. The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts Primary (disposable) battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption at the VCC pins. The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts 3G.G2-HW-10002-A1 Advance Information System description Page 25 of 160 5VC1R1INOUTADJGND12453C2R2R3U1SHDNLISA-U series62VCC63VCC61VCCGND LISA-U series - System Integration Manual Additional recommendations for the VCC supply application circuits To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines

(connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible in order to minimize power losses. Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. Even if all the VCC pins and all the GND pins are internally connected within the module, it is recommended to properly connect all of them to supply the module in order to minimize series resistance losses. To avoid undershoot and overshoot on voltage drops at the start and end of a transmit burst during a GSM call

(when current consumption on the VCC supply can rise up to 2.5 A in the worst case), place a 330 F low ESR capacitor (e.g. KEMET T520D337M006ATE045) near the VCC pins. The use of very large capacitors (i.e. greater then 1000 F) on the VCC line and the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch on of the module. To reduce voltage ripple and noise, place the following near the VCC pins:

100 nF capacitor (e.g Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources 10 pF capacitor (e.g. Murata GRM1555C1E100J) to filter EMI in the 1800 / 1900 / 2100 MHz bands 39 pF capacitor (e.g. Murata GRM1555C1E390J) to filter EMI in the 850 / 900 MHz bands Figure 9 shows the complete configuration but the mounting of each single component depends on the application design. Figure 9: Suggested schematic design to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 39 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E390JA01 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Table 9: Suggested components to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops 3G.G2-HW-10002-A1 Advance Information System description Page 26 of 160 3V8C1C4GNDC3C2C5LISA-U series62VCC63VCC61VCC+LISA-U series - System Integration Manual External battery charging application circuit LISA-U series modules dont have an on-board charging circuit. An example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell, is provided in Figure 10. In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse and DC discharge current capabilities and proper DC series resistance, is directly connected to the VCC supply input of LISA-U series module. Battery charging is completely managed by the STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges as a linear charger the battery, in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for USB power source (~500 mA) Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the L6924U starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor to ~15 mA or when the charging timer reaches the value configured by an external capacitor to ~9800 s Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. Alternatively the L6924U, providing input voltage range up to 12 V, can charge from an AC wall adapter. When a current-limited adapter is used, it can operate in quasi-pulse mode, reducing power dissipation. Figure 10: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Part Number - Manufacturer B1 C1, C4 C2, C6 C3 C5 C7 C8 C9 D1 Li-Ion (or Li-Polymer) battery pack with 470 NTC Various manufacturer 1 F Capacitor Ceramic X7R 0603 10% 16 V GRM188R71C105KA12 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 1 nF Capacitor Ceramic X7R 0402 10% 50 V GRM155R71H102KA01 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 39 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E390JA01 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Low Capacitance ESD Protection USB0002RP or USB0002DP - AVX R1, R2 24 k Resistor 0402 5% 0.1 W R3 R4 U1 3.3 k Resistor 0402 5% 0.1 W 1.0 k Resistor 0402 5% 0.1 W Single Cell Li-Ion (or Li-Polymer) Battery Charger IC for USB port and AC Adapter RC0402JR-0724KL - Yageo Phycomp RC0402JR-073K3L - Yageo Phycomp RC0402JR-071K0L - Yageo Phycomp L6924U - STMicroelectronics Table 10: Suggested components for Li-Ion (or Li-Polymer) battery charging application circuit 3G.G2-HW-10002-A1 Advance Information System description Page 27 of 160 C5C8GNDC7C6C9LISA-U series62VCC63VCC61VCC+USB SupplyC3R4U1IUSBIACIENDTPRGSDVINVINSNSMODEISELC2C15V0THGNDVOUTVOSNSVREFR1R2R3Li-Ion/Li-Pol Battery PackD1B1C4Li-Ion/Li-Polymer Battery Charger IC LISA-U series - System Integration Manual 1.5.3 Current consumption profiles During operation, the current drawn by the LISA-U series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in 2G connected mode, to continuous high current drawn in UMTS connected mode, to the low current consumption during power saving in idle-mode. 1.5.3.1 2G connected mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM 900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 s

(width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is in GSM connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than the one in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). During a GSM call, current consumption is in the order of 60-130 mA in receiving or in monitor bursts and is about 10-40 mA in the inactive unused bursts (low current period). The more relevant contribution to determine the average current consumption is set by the transmitted power in the transmit slot. An example of current consumption profile of the data module in GSM talk mode is shown in Figure 11. Figure 11: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot), with VCC=3.8 V When a GPRS connection is established there is a different VCC current consumption profile also determined by the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current consumption is not as high as can be in case of a GSM call. If the module transmits in GPRS class 12 connected mode in the GSM 850 or in the E-GSM 900 band at the maximum power control level, the current consumption can reach up to 1600 mA (with unmatched antenna). 3G.G2-HW-10002-A1 Advance Information System description Page 28 of 160 Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200 mA60-130 mA2500 mAPeak current depends on TX powerGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.060-130 mA10-40 mA LISA-U series - System Integration Manual This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame

= 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). Figure 12 reports the current consumption profiles in GPRS class 12 connected mode, in the GSM 850 or in the E-GSM 900 band, with 4 slots used to transmit and 1 slot used to receive. Figure 12: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot), with VCC=3.8 V In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 12, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well. LISA-U2 series modules support GPRS and EDGE class 33: up to 4 slots can be used to transmit, as in the class 12 mode, and up to 2 slots can be used to receive in the same frame since up to 6 slots can be used in total. So, the VCC current consumption figures in GPRS and EDGE class 33 connected modes are similar to the current profile in GPRS and EDGE class 12 connected modes, since the same number of transmit slots are used. 1.5.3.2 3G connected mode During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex

(FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 s, thus the rate of power change can reach a maximum rate of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case. In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the order of continuous 600-700 mA. Even at lowest output RF power (approximately 0.01 W or -50 dBm), the current still remains in the order of 200 mA due to module baseband processing and transceiver activity. An example of current consumption profile of the data module in UMTS continuous transmission mode is shown in Figure 13. 3G.G2-HW-10002-A1 Advance Information System description Page 29 of 160 Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200mA60-130mAPeak current depends on TX powerGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.01600 mA60-130mA10-40mA LISA-U series - System Integration Manual Figure 13: VCC current consumption profile versus time during a UMTS connection, with VCC=3.8 V When a packet data connection is established, the actual current profile depends on the amount of transmitted packets; there might be some periods of inactivity between allocated slots where current consumption drops about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher quality signal required by the network to cope with enhanced data speed. 1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command

(refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible. When power saving is enabled, the module is registered or attached to a network and a voice or data call is not enabled, the module automatically enters idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to GSM system requirements. When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging block. In between, the module switches to idle-mode. This is known as GSM discontinuous reception (DRX). The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode. The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell. In case of 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX = 2, i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX = 9, i.e. width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms). In case of 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of 26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms =

5120 ms). An example of a module current consumption profile is shown in Figure 14: the module is registered with the network (2G or 3G), automatically enters idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception. 3G.G2-HW-10002-A1 Advance Information System description Page 30 of 160 Time [ms]3G frame 10 ms (1 frame = 15 slots)Current [mA]170 mADepends on TX power1 slot 666 s670 mA3002001000500400600700 LISA-U series - System Integration Manual Figure 14: Description of VCC current consumption profile versus time when the module is registered with 2G or 3G networks:

the module is in idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception 1.5.3.4 2G and 3G fixed active mode (power saving disabled) Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is disabled, the module doesnt automatically enter idle-mode whenever possible: the module remains in active mode. The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. An example of the current consumption profile of the data module when power saving is disabled is shown in Figure 15: the module is registered with the network, active-mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception. 3G.G2-HW-10002-A1 Advance Information System description Page 31 of 160

~30 msIDLE MODEACTIVE MODEIDLE MODE500-700 AActive Mode EnabledIdle Mode Enabled500-700 A2G case: 60-130 mA 3G case: 50-90 mA2G case: 0.44-2.09 s 3G case: 0.61-5.09 sIDLE MODE2G or 3G case: ~30 msACTIVE MODETime [s]Current [mA]150100500Time [ms]Current [mA]1501005005-10 mA10-25 mA2G case: 60-130 mA 3G case: 50-90 mAPLL EnabledRX Enabled35-40 mADSP Enabled LISA-U series - System Integration Manual Figure 15: Description of the VCC current consumption profile versus time when power saving is disabled: active-mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception 1.5.4 RTC Supply (V_BCKP) The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power-On / Reset internal logic. This supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The output of this linear regulator is always enabled when the main voltage supply provided to the module through VCC is within the valid operating range, with the module switched-off or powered-on. Name V_BCKP Description Real Time Clock supply Table 11: Real Time Clock supply pin Remarks V_BCKP output voltage = 2.3 V (typical) on LISA-U1 series V_BCKP output voltage = 1.8 V (typical) on LISA-U2 series Generated by the module to supply Real Time Clock when VCC supply voltage is within valid operating range. The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. 3G.G2-HW-10002-A1 Advance Information System description Page 32 of 160 ACTIVE MODE10-25 mA10-25 mA2G case: 0.47-2.12 s 3G case: 0.64-5.12 sPaging periodTime [s]Current [mA]150100500Time [ms]Current [mA]15010050010-25 mARX EnabledDSP Enabled35-40 mA2G case: 60-130 mA 3G case: 50-90 mA2G case: 60-130 mA 3G case: 50-90 mA LISA-U series - System Integration Manual The RTC provides the time reference (date and time) of the module, also in power-off mode, when the V_BCKP voltage is within its valid range (specified in the Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). The RTC timing is normally used to set the wake-up interval during idle-mode periods between network paging, but is able to provide programmable alarm functions by means of the internal 32.768 kHz clock. The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. The RTC oscillator doesn't necessarily stop operation (i.e. the RTC counting doesn't necessarily stop) when V_BCKP voltage value drops below the specified operating range minimum limit (1.00 V): the RTC value read after a system restart could be not reliable as explained in the following Table 12. V_BCKP voltage value RTC value reliability Notes 1.00 V < V_BCKP < 1.90 V (LISA-U2 series) 1.00 V < V_BCKP < 2.50 V (LISA-U1 series) RTC oscillator doesn't stop operation RTC value read after a restart of the system is reliable 0.05 V < V_BCKP < 1.00 V 0.00 V < V_BCKP < 0.05 V RTC oscillator doesn't necessarily stop operation RTC value read after a restart of the system is not reliable RTC oscillator stops operation RTC value read after a restart of the system is reliable V_BCKP within operating range V_BCKP below operating range V_BCKP below operating range Table 12: RTC value reliability as function of V_BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch-on the module). The RTC has very low power consumption, but is highly temperature dependent. For example at 25C, with the V_BCKP voltage equal to the typical output value, the power consumption is approximately 2 A (refer to the Input characteristics of Supply/Power pins table in the LISA-U1 series Data Sheet [1] and in the LISA-U2 series Data Sheet [2] for the detailed specification), whereas at 70C and an equal voltage the power consumption increases to 5-10 A. The internal regulator for V_BCKP is optimized for low leakage current and very light loads. It is not recommended to use V_BCKP to supply external loads. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). This has no impact on wireless connectivity, as all the functionalities of the module do not rely on date and time setting. Leave V_BCKP unconnected if the RTC is not required when the VCC supply is removed. The date and time will not be updated when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP. If RTC is required to run for a time interval of T [s] at 25C when VCC supply is removed, place a capacitor with a nominal capacitance of C [F] at the V_BCKP pin. Choose the capacitor using the following formula:

C [F] = (Current_Consumption [A] x T [s]) / Voltage_Drop [V]

= 1.92 x T [s] for LISA-U1 series

= 2.50 x T [s] for LISA-U2 series For example, a 100 F capacitor (such as the Murata GRM43SR60J107M) can be placed at V_BCKP to provide a long buffering time. This capacitor will hold V_BCKP voltage within its valid range for around 50 s at 25C, after the VCC supply is removed. If a very long buffering time is required, a 70 mF super-capacitor (e.g. Seiko 3G.G2-HW-10002-A1 Advance Information System description Page 33 of 160 LISA-U series - System Integration Manual Instruments XH414H-IV01E) can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage within its valid range for approximately 10 hours at 25C, after the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors will allow the time reference to run during battery disconnection. Figure 16: Real time clock supply (V_BCKP) application circuits: (a) using a 100 F capacitor to let the RTC run for ~50 s after VCC removal; (b) using a 70 mF capacitor to let RTC run for ~10 hours after VCC removal; (c) using a non-rechargeable battery Reference Description Part Number - Manufacturer C1 R2 C2 100 F Tantalum Capacitor GRM43SR60J107M - Murata 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp 70 mF Capacitor XH414H-IV01E - Seiko Instruments Table 13: Example of components for V_BCKP buffering If longer buffering time is required to allow the time reference to run during a disconnection of the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP (specified in the Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and in LISA-U2 series Data Sheet [2]). The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to the non-rechargeable battery. Combining a LISA-U series wireless module with a u-blox GPS receiver, the VCC supply of the GPS receiver is controlled by the wireless module by means of the GPS supply enable function provided by the GPIO2 of the wireless module. In this case the V_BCKP supply output of the LISA-U series wireless module can be connected to the V_BCKP backup supply input pin of the GPS receiver to provide the supply for the GPS real time clock and backup RAM when the VCC supply of the wireless module is within its operating range and the VCC supply of the GPS receiver is disabled. This enables the u-blox GPS receiver to recover from a power breakdown with either a Hotstart or a Warmstart (depending on the duration of the GPS VCC outage) and to maintain the configuration settings saved in the backup RAM. Refer to section 1.10 for more details regarding the application circuit with a u-blox GPS receiver. 1.5.5 Interface supply (V_INT) The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin. The internal regulator that generates the V_INT supply is a switching step down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and is disabled when the module is switched off or when the RESET_N pin is forced the low level. The switching regulator operates in Pulse Width Modulation (PWM) for high output current mode but automatically switches to Pulse 3G.G2-HW-10002-A1 Advance Information System description Page 34 of 160 LISA-U seriesC1(a)2V_BCKPR2LISA-U seriesC2(superCap)(b)2V_BCKPD3LISA-U seriesB3(c)2V_BCKP LISA-U series - System Integration Manual Frequency Modulation (PFM) at low output loads for greater efficiency, e.g. when the module is in idle-mode between paging periods. Name V_INT Description Remarks Digital Interfaces supply output V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. V_INT is the internal supply for digital interfaces. The user may draw limited current from this supply rail. Table 14: Interface supply pin The V_INT pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. Since it supplies internal digital circuits (see Figure 4), V_INT is not suited to directly supply any sensitive analog circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to 70 mVpp in idle-mode (PFM). V_INT can be used to supply external digital circuits operating at the same voltage level as the digital interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without adequate filtering for digital noise. Dont apply loads which might exceed the limit for maximum available current from V_INT supply, as this can cause malfunctions in internal circuitry supplies to the same domain. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. V_INT can only be used as an output; dont connect any external regulator on V_INT. If not used, this pin should be left unconnected. The V_INT digital interfaces supply output is mainly used to:

Pull-up DDC (I2C) interface signals (see section 1.10.2 for more details) Pull-up SIM detection signal (see section 1.8 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see section 1.9.2.4) Indicate when the module is switched on and the RESET_N (external reset input) is not forced low 1.6 System functions 1.6.1 Module power-on The power-on sequence of LISA-U series modules is initiated in one of these ways:

Rising edge on the VCC pin to a valid voltage as module supply (i.e. applying module supply) Low level on the PWR_ON pin (i.e. forcing to the low level the pin normally high by external pull-up) Rising edge on the RESET_N pin (i.e. releasing from low level the pin, normally high by internal pull-up) RTC alarm (i.e. pre-programmed scheduled time by AT+CALA command) 3G.G2-HW-10002-A1 Advance Information System description Page 35 of 160 LISA-U series - System Integration Manual Name Description PWR_ON Power-on input Table 15: Power-on pin Remarks PWR_ON pin has high input impedance. Do not keep floating in noisy environment:

external pull-up required. The PWR_ON pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. 1.6.1.1 Rising edge on VCC When a supply is connected to VCC pins, the module supply supervision circuit controls the subsequent activation of the power up state machines: the module is switched on when the voltage rises up to the VCC normal operating range minimum limit starting from a voltage value lower than 2.25 V (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the VCC normal operating range minimum limit). The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to switch on the module. 1.6.1.2 Low level on PWR_ON The module power-on sequence starts when a low level is forced on the PWR_ON input for at least 5 ms. The electrical characteristics of the PWR_ON input pin are slightly different between LISA-U1 series and LISA-U2 series modules, and are different from the other digital I/O interfaces: the pin provides different input voltage thresholds and is tolerant of voltages up to the module supply level. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module. Avoid keeping it floating in a noisy environment. To hold the high logic level stable, the PWR_ON pin must be connected to a pull-up resistor (e.g. 100 k) biased by the V_BCKP supply pin of the module. Following are some typical examples of application circuits to turn the module on using the PWR_ON input pin. The simplest way to turn on the module is to use a push button that shorts the PWR_ON input to ground: in this case the V_BCKP supply pin can be used to bias the pull-up resistor. If PWR_ON input is connected to an external device (e.g. application processor), it is suggested to use an open drain output on the external device with an external pull-up resistor (e.g. 100 k) biased by the V_BCKP supply pin of the module. A push-pull output of an application processor can also be used: in this case the pull-up can be used to pull the PWR_ON level high when the application processor is switched off. If the high-level voltage of the push-pull output pin of the application processor is greater than the maximum input voltage operating range of the V_BCKP pin (refer to the V_BCKP Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]), the V_BCKP supply cannot be used to bias the pull-up resistor: the supply rail of the application processor or the VCC supply could be used, but this will increase the V_BCKP (RTC supply) current consumption when the module is in not-powered mode (VCC supply not present). Using a push-

pull output of the external device, take care to fix the proper level in all the possible scenarios to avoid an inappropriate switch-on of the module. 3G.G2-HW-10002-A1 Advance Information System description Page 36 of 160 LISA-U series - System Integration Manual Figure 17: PWR_ON application circuits using a push button and an open drain output of an application processor Reference Description Remarks Rext ESD 100 k Resistor 0402 5% 0.1 W External pull-up resistor CT0402S14AHSG - EPCOS Varistor array for ESD protection Table 16: Example of pull-up resistor and ESD protection for the PWR_ON application circuits 1.6.1.3 Rising edge on RESET_N LISA-U series modules can be switched on by means of the RESET_N input pin: the RESET_N signal must be forced low for at least 50 ms and then released to generate a rising edge that starts the module power-on sequence. RESET_N input pin can also be used to perform an external or hardware reset of the module, as described in the section 1.6.3. Electrical characteristics of the LISA-U series RESET_N input are slightly different from the other digital I/O interfaces: the pin provides different input voltage thresholds. Detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. RESET_N is pulled high to V_BCKP by an integrated pull-up resistor also when the module is in power-off mode. Therefore an external pull-up is not required on the application board. The simplest way to switch on the module by means of the RESET_N input pin is to use a push button that shorts the RESET_N pin to ground: the module will be switched on at the release of the push button, since the RESET_N will be forced to the high level by the integrated pull-up resistor, generating a rising edge. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]). To avoid unwanted power-on or reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. Some typical examples of application circuits using the RESET_N input pin are described in the section 1.6.3. 3G.G2-HW-10002-A1 Advance Information System description Page 37 of 160 LISA-U seriesRext2V_BCKP19PWR_ONPower-on push buttonESDOpen Drain OutputApplication ProcessorLISA-U seriesRext2V_BCKP19PWR_ON LISA-U series - System Integration Manual 1.6.1.4 Real Time Clock (RTC) alarm If a voltage within the operating range is maintained at the VCC pin, the module can be switched on by the RTC alarm when the RTC system reaches a pre-programmed scheduled time (refer to the u-blox AT Commands Manual [3], AT+CALA command). The RTC system will then initiate the boot sequence by instructing the Power Management Unit to turn on power. Also included in this setup is an interrupt signal from the RTC block to indicate to the baseband processor that an RTC event has occurred. 1.6.1.5 Additional considerations The module is switched on when the VCC voltage rises up to the normal operating range (i.e. applying module supply): the first time that the module is used, it is switched on in this way. Then, LISA-U series modules can be switched off by means of the AT+CPWROFF command. When the module is in power-off mode, i.e. the AT+CPWROFF command has been sent and a voltage value within the normal operating range limits is still provided to the VCC pin, the digital input-output pads of the baseband chipset (i.e. all the digital pins of the module) are locked in tri-state (i.e. floating). The power down tri-state function isolates the module pins from its environment, when no proper operation of the outputs can be guaranteed. The module can be switched on from power-off mode by forcing a proper start-up event (i.e. low level on the PWR_ON pin, or an RTC alarm). After the detection of a start-up event, all the digital pins of the module are held in tri-state until all the internal LDO voltage regulators are turned on in a defined power-on sequence. Then, as described in Figure 18, the baseband core is still held in reset state for a time interval: the internal reset signal

(which is not available on a module pin) is still low and any signal from the module digital interfaces is held in reset state. The reset state of all the digital pins is reported in the pin description table of LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. When the internal signal is released, the configuration of the module interfaces starts: during this phase any digital pin is set in a proper sequence from the reset state to the default operational configuration. Finally, the module is fully ready to operate when all interfaces are configured. Figure 18: LISA-U series power-on sequence description (* - the PWR_ON signal state is not relevant during this phase) The Internal Reset signal is not available on a module pin. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during 3G.G2-HW-10002-A1 Advance Information System description Page 38 of 160 VCCV_BCKPPWR_ONV_INTInternal ResetSystem StateBB Pads StateInternal Reset OperationalOperationalTristate / Floating Internal ResetOFFON*Start-up event0 ms~5 ms~6 ms~35 ms~1500 msPWR_ON can be set highStart of interface configurationAll interfaces are configured LISA-U series - System Integration Manual the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power on sequence. 1.6.2 Module power-off The correct way to switch off LISA-U series modules is by means of +CPWROFF AT command (more details in u-blox AT Commands Manual [3]): in this way the current parameter settings are saved in the modules non-volatile memory and a proper network detach is performed. LISA-U2 series modules can additional be properly switched off by means of the PWR_ON input pin: the PWR_ON signal must be held to the low logic level for more than 1 s to start the module power-off sequence. In this way, current parameter settings are saved in LISA-U2 series modules non-volatile memory and a correct network detach is performed: the same sequence is performed as by the +CPWROFF AT command. An under-voltage shutdown occurs on LISA-U series modules when the VCC supply is removed, but in this case the current parameter settings are not saved in the modules non-volatile memory and a proper network detach cannot be performed. The power-off sequence by means of +CPWROFF AT command is described in Figure 19. When the +CPWROFF AT command is sent, the module starts the switch-off routine replying OK on the AT interface. At the end of the switch-off routine, all digital pins are locked in tri-state by the module and all the internal LDO voltage regulators except the RTC supply (V_BCKP) are turned off in a defined power-off sequence. The module remains in power-off mode as long as a switch on event doesnt occur (i.e. applying a low level on the PWR_ON pin, or releasing from low level the RESET_N pin, or by a pre-programmed RTC alarm), and enters not-powered mode if the supply is removed from the VCC pin. Current parameter settings are stored to the modules non-volatile memory and a network detach is performed before the OK reply from AT+CPWROFF command on all LISA-U series modules except LISA-U1xx-00 versions. Storage of parameters and network detach are performed before the end of the switch-off routine, but not necessary before the OK reply from AT+CPWROFF command on LISA-U1xx-00 versions. Since the time to perform a network detach depends on the network settings, the duration of the switch off routine phases can differ from the typical values reported in Figure 19. Figure 19: LISA-U series Power-off sequence description (* - the PWR_ON signal state is not relevant during this phase) 3G.G2-HW-10002-A1 Advance Information System description Page 39 of 160 VCCV_BCKPPWR_ON*V_INTInternal ResetSystem StateBB Pads StateOperationalOFFTristate / Floating ONOperational Tristate / FloatingAT+CPWROFFsent to the module0 ms~50 ms~400 msOKreplied by the module LISA-U series - System Integration Manual The Internal Reset signal is not available on a module pin. Tristated pins are always subject to floating caused by noise: to prevent unwanted effects, fix them with proper pull-up or pull down resistors to stable voltage rails to fix their level when the module is in Power down state. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.6.3 Module reset LISA-U series modules reset can be performed in one of 2 ways:

Forcing a low level on the RESET_N input pin, causing an external or hardware reset Via AT command, causing an internal or software reset RESET_N input pin: force low for at least 50 ms; either an external or hardware reset is performed. This causes an asynchronous reset of the entire module, including the integrated Power Management Unit, except for the RTC internal block: the V_INT interfaces supply is switched off and all the digital pins are tri-stated, but the V_BCKP supply and the RTC block are enabled. Forcing an external or hardware reset, the current parameter settings are not saved in the modules non-volatile memory and a proper network detach is not performed. AT+CFUN command (more details in u-blox AT Commands Manual [3]): in this case an internal or software reset is performed, causing an asynchronous reset of the baseband processor, excluding the integrated Power Management Unit and the RTC internal block: the V_INT interfaces supply is enabled and each digital pin is set in its internal reset state (reported in the pin description table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]), the V_BCKP supply and the RTC block are enabled. Forcing an internal or software reset, the current parameter settings are saved in the modules non-volatile memory and a proper network detach is performed. When RESET_N is released from the low level, the module automatically starts its power-on sequence from the reset state. The same procedure is followed for the module reset via AT command after having performed the network detach and the parameter saving in non-volatile memory. The internal reset state of all digital pins is reported in the pin description table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Name RESET_N Table 17: Reset pin Description External reset input Remarks Internal 10 k pull-up to V_BCKP The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. For more details about RESET_N circuit precautions for ESD immunity please refer to chapter 2.5.3. The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. 3G.G2-HW-10002-A1 Advance Information System description Page 40 of 160 LISA-U series - System Integration Manual RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-up is not required on the application board. Following are some typical examples of application circuits using the RESET_N input pin. The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]). To avoid unwanted reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) and a series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the RESET_N line pin of LISA-U1 series modules and an additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board (for more details, refer to chapter 2.5.3). Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD C1, C3 C2, C4 FB1, FB2 Rint Varistor for ESD protection. CT0402S14AHSG - EPCOS 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata 220 nF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J224KE01 - Murata Chip Ferrite Bead for Noise/EMI Suppression BLM15HD182SN1 - Murata 10 k Resistor 0402 5% 0.1 W Internal pull-up resistor Table 18: Example of ESD protection components for the RESET_N application circuit Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module 3G.G2-HW-10002-A1 Advance Information System description Page 41 of 160 LISA-U series2V_BCKP22RESET_NReset push buttonESDOpen Drain OutputApplication ProcessorLISA-U series2V_BCKP22RESET_NRintRintFB1C1FB2C3C2C4 LISA-U series - System Integration Manual cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.7 RF connection The ANT pin, provided by all LISA-U series modules, represents the main RF input/output used to transmit and receive the 2G and 3G RF signal: the main antenna must be connected to this pad. The ANT pin has a nominal characteristic impedance of 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. and must be connected to the antenna through a 50 The ANT_DIV pin, provided by LISA-U230 modules, represents the RF input for the integrated diversity receiver:

the antenna for the Rx diversity should be connected to this pad. The ANT_DIV pin has a nominal characteristic impedance of 50 transmission line to allow reception of radio frequency (RF) signals in the 2G and 3G operating bands. and must be connected to the antenna for the Rx diversity through a 50 Name ANT Module Description Remarks All RF input/output for main Tx/Rx antenna Zo = 50 nominal characteristic impedance. ANT_DIV LISA-U230 RF input for Rx diversity antenna Zo = 50 nominal characteristic impedance. Table 19: Antenna pins ESD immunity rating of the ANT port of LISA-U1 series modules is 500 V (according to IEC 61000-4-2). ESD immunity rating of the ANT port of LISA-U200-00 modules is 1000 V (according to IEC 61000-4-2). Higher protection level could be required if the line is externally accessible on the application board (for further details see section 2.5.3). Choose an antenna with optimal radiating characteristics for the best electrical performance and overall module functionality. An internal antenna, integrated on the application board, or an external antenna, connected to the application board through a proper 50 connector, can be used. See section 2.4 and section 2.2.1.1 for further details regarding antenna guidelines. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. If an external antenna is used, the PCB-to-RF-cable transition must be implemented using either a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 characteristic impedance. If antenna supervisor functionality is required, the main antenna connected to the ANT pin should have a built in DC diagnostic resistor to ground to get proper detection functionality (See section 2.4.3). If the Rx diversity is not implemented, ANT_DIV pin can be left unconnected on the application board. 1.8 (U)SIM interface High-speed SIM/ME interface is implemented as well as automatic detection of the required SIM supporting voltage. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The SIM driver supports the PPS 3G.G2-HW-10002-A1 Advance Information System description Page 42 of 160 LISA-U series - System Integration Manual

(Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM Card. Name VSIM SIM_CLK SIM_IO SIM_RST Description SIM supply SIM clock SIM data SIM reset Table 20: SIM Interface pins Remarks 1.80 V typical or 2.90 V typical Automatically generated by the module 3.25 MHz clock frequency Open drain, internal 4.7 k pull-up resistor to VSIM A low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002RP) must be placed near the SIM card holder on each line (VSIM, SIM_IO, SIM_CLK, SIM_RST). The SIM interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F): higher protection level is required if the lines are connected to an SIM card connector, since they are externally accessible on the application board. For more details about the general precautions for ESD immunity about SIM interface pins please refer to chapter 2.5.3. Figure 21 shows an application circuit connecting the LISA-U series module and the SIM card placed in a SIM card holder, using the SIM detection function provided by GPIO5 pin. Note that, as defined by ETSI TS 102 221 or ISO/IEC 7816, SIM card contacts assignment is as follows:

Contact C1 = VCC (Supply) It must be connected to VSIM Contact C2 = RST (Reset) It must be connected to SIM_RST Contact C3 = CLK (Clock) It must be connected to SIM_CLK Contact C4 = AUX1 (Auxiliary contact for USB interface and other uses) It must be left not connected Contact C5 = GND (Ground) It must be connected to GND Contact C6 = VPP (Programming supply) It must be connected to VSIM Contact C7 = I/O (Data input/output) It must be connected to SIM_IO Contact C8 = AUX2 (Auxiliary contact for USB interface and other uses) It must be left not connected A SIM card can have 6 contacts (C1 = VCC, C2 = RST, C3 = CLK, C5 = GND, C6 = VPP, C7 = I/O) or 8 contacts

(providing also the auxiliary contacts C4 = AUX1 and C8 = AUX2). The contacts number depends if additional features, that are not supported by the (U)SIM card interface of the LISA-U series modules, are provided by the SIM card (contacts C4 = AUX1 and C8 = AUX2 for USB interfaces and other uses). A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins for the mechanical card presence detection are provided. Figure 21 shows an application circuit connecting a LISA-U series module and a SIM card placed in a SIM card holder with 6+2 pins (as the CCM03-3013LFT R102 connector, produced by C&K Components, which provides 2 pins for the mechanical card presence detection), using the SIM detection function provided by the GPIO5 of LISA-U series module. This configuration allows the module to detect if a SIM card is present in the connector. The SW1 and SW2 pins of the SIM card holder are connected to a normally-open mechanical switch integrated in the SIM connector. The following cases are available SIM card not present: the GPIO5 signal is forced low by the pull-down resistor connected to ground (i.e. the switch integrated in the SIM connector is open) SIM card present: the GPIO5 signal is forced high by the pull-up resistor connected to V_INT (i.e. the switch integrated in the SIM connector is closed) 3G.G2-HW-10002-A1 Advance Information System description Page 43 of 160 LISA-U series - System Integration Manual Figure 21: SIM interface application circuit Reference Description Part Number - Manufacturer C1, C2, C3, C4 33 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H330JZ01 - Murata C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2, D3 Low capacitance ESD protection R1 R2 J1 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W SIM Card Holder Table 21: Example of components for SIM card connection USB0002RP or USB0002DP - AVX RC0402JR-071KL - Yageo Phycomp RC0402JR-07470KL- Yageo Phycomp Various Manufacturers, CCM03-3013LFT R102 - C&K Components When connecting the module to an SIM connector, perform the following steps on the application board:

Bypass digital noise via a 100 nF capacitor (e.g. Murata GRM155R71C104K) on the SIM supply (VSIM) To prevent RF coupling in case the module RF antenna is placed closer than 10 - 30 cm from the SIM card holder, connect a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) at each SIM signal (VSIM, SIM_CLK, SIM_IO, SIM_RST) to ground near the SIM connector Mount very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) near the SIM card connector Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface

(27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines): always route the connections to keep them as short as possible 1.8.1 (U)SIM functionality The following SIM services are supported:

Abbreviated Dialing Numbers (ADN) Fixed Dialing Numbers (FDN) Last Dialed Numbers (LDN) Service Dialing Numbers (SDN) USIM Application Toolkit (USAT) R99 is supported. 3G.G2-HW-10002-A1 Advance Information System description Page 44 of 160 LISA-U seriesC1SIM CARD HOLDERCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)C2C3C5D2D3C5C6C7C1C2C3SIM Card Bottom View (contacts side)J150VSIM48SIM_IO47SIM_CLK49SIM_RSTC4SW1SW24V_INT51GPIO5R2R1D1 LISA-U series - System Integration Manual 1.9 Serial communication LISA-U series modules provide the following serial communication interfaces where AT command interface and Packet-Switched / Circuit-Switched Data communication are concurrently available:

One asynchronous serial interface (UART) that provides complete RS-232 functionality conforming to ITU-T V.24 Recommendation [4], with limited data rate. The UART interface can be used for firmware upgrade One Inter Processor Communication (IPC) interface that includes a synchronous SPI-compatible interface, with maximum data rate of 26 Mb/s One high-speed USB 2.0 compliant interface, with maximum data rate of 480 Mb/s. The single USB interface implements several logical devices. Each device is a USB communications device class (or USB CDC), that is a composite Universal Serial Bus device class. The USB interface can be used for firmware upgrade The LISA-U series modules are designed to operate as an HSPA wireless modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [4]. A customer application processor connected to the module through one of the interfaces represents the data terminal equipment (DTE). All the interfaces listed above are controlled and operated with:

AT commands according to 3GPP TS 27.007 [5]

AT commands according to 3GPP TS 27.005 [6]

AT commands according to 3GPP TS 27.010 [7]

u-blox AT commands For the complete list of supported AT commands and their syntax refer to the u-blox AT Commands Manual [3]. The following serial communication interfaces can be used for firmware upgrade:

The UART interface, using the RxD and TxD lines only The USB interface, using all the lines provided (VUSB_DET, USB_D+ and USB_D-) To directly enable PC (or similar) connection to the module for firmware upgrade, provide direct access on the application board to the VUSB_DET, USB_D+ and USB_D- lines of the module (or to the RxD and TxD lines). Also provide access to the PWR_ON or the RESET_N pins, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [18]). The following sub-chapters describe the serial interfaces configuration and provide a detailed description of each interface for the application circuits. 1.9.1 Serial interfaces configuration UART, USB and SPI/IPC serial interfaces are available as AT command interface and for Packet-Switched / Circuit-

Switched Data communication. The serial interfaces are configured as described in Table 22 (for information about further settings, please refer to the u-blox AT Commands Manual [3]). 3G.G2-HW-10002-A1 Advance Information System description Page 45 of 160 LISA-U series - System Integration Manual Interface AT Settings Comments UART interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port AT+IPR=115200 Baud rate: 115200 b/s AT+ICF=3,1 Frame format: 8 bits, no parity, 1 stop bit AT&K3 AT&S1 AT&D1 AT&C1 HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise USB interface Enabled 6 CDCs are available, configured as described in the following list:

USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling dedicated port USB5: 2G and BB trace dedicated port USB6: 3G trace dedicated port AT&K3 AT&S1 AT&D1 AT&C1 All LISA-U2 series modules versions except LISA-U200-00 provide an additional CDC:

USB7: SIM Access Profile dedicated port HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise SPI interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise AT&K3 AT&S1 AT&D1 AT&C1 Table 22: Default serial interfaces configuration 1.9.2 Asynchronous serial interface (UART) The UART interface is a 9-wire unbalanced asynchronous serial interface that provides AT commands interface, PSD and CSD data communication, firmware upgrade. UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [4]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state. Two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC8T245PW) could be used to provide full RS-232 (9 lines) compatible signal levels. The Texas Instruments chip provides the translation from 1.8 V to 3.3 V, while the Maxim chip provides the necessary RS-232 compatible signal towards the external connector. If a UART interface with only 5 lines is needed, the Maxim 13234E voltage level translator can be used. This chip translates the voltage levels from 1.8 V (module 3G.G2-HW-10002-A1 Advance Information System description Page 46 of 160 LISA-U series - System Integration Manual side) to the RS-232 standard. For detailed electrical characteristics refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The LISA-U series modules are designed to operate as an HSPA wireless modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [4]. A customer application processor connected to the module through the UART interface represents the data terminal equipment (DTE). The signal names of the LISA-U series modules UART interface conform to the ITU-T V.24 Recommendation [4]. UART interfaces include the following lines:

Name DSR RI DCD DTR RTS CTS TxD RxD GND Description Data set ready Ring Indicator Data carrier detect Data terminal ready Ready to send Clear to send Transmitted data Received data Ground Table 23: UART interface signals Remarks Module output Circuit 107 (Data set ready) in ITU-T V.24 Module output Circuit 125 (Calling indicator) in ITU-T V.24 Module output Circuit 109 (Data channel received line signal detector) in ITU-T V.24 Module input Circuit 108/2 (Data terminal ready) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control input Circuit 105 (Request to send) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control output Circuit 106 (Ready for sending) in ITU-T V.24 Module data input Circuit 103 (Transmitted data) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module data output Circuit 104 (Received data) in ITU-T V.24 The UART interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. 1.9.2.1 UART features All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands

(see u-blox AT Commands Manual [3], &K, +IFC, \Q AT commands): hardware flow control (RTS/CTS), software flow control (XON/XOFF), or none flow control. Hardware flow control is enabled by default. The following baud rates can be configured using AT commands:

1200 b/s 2400 b/s 3G.G2-HW-10002-A1 Advance Information System description Page 47 of 160 LISA-U series - System Integration Manual 4800 b/s 9600 b/s 19200 b/s 38400 b/s 57600 b/s 115200 b/s 230400 b/s 460800 b/s The default baud rate is 115200 b/s. Autobauding is not supported. The frame format can be:

8N1 (8 data bits, No parity, 1 stop bit) 8E1 (8 data bits, even parity, 1 stop bit) 8O1 (8 data bits, odd parity, 1 stop bit) 8N2 (8 data bits, No parity, 2 stop bits) 7E1 (7 data bits, even parity, 1 stop bit) 7O1 (7 data bits, odd parity, 1 stop bit) The default frame configuration with fixed baud rate is 8N1, described in the Figure 22. Figure 22: UART default frame format (8N1) description 1.9.2.2 UART signal behavior (AT commands interface case) See Table 5 for a description of operating modes and states referred to in this section. At the switch on of the module, before the initialization of the UART interface, as described in the power-on sequence reported in the Figure 18, each pin is first tri-stated and then is set to its relative internal reset state that is reported in the pin description table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. At the end of the boot sequence, the UART interface is initialized, the module is by default in active mode and the UART interface is enabled. The configuration and the behavior of the UART signals after the boot sequence are described below. For a complete description of data and command mode please refer to u-blox AT Commands Manual [3]. 3G.G2-HW-10002-A1 Advance Information System description Page 48 of 160 D0D1D2D3D4D5D6D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer,8N1 LISA-U series - System Integration Manual RxD signal behavior The module data output line (RxD) is set by default to OFF state (high level) at UART initialization. The module holds RxD in OFF state until no data is transmitted by the module. TxD signal behavior The module data input line (TxD) is set by default to OFF state (high level) at UART initialization. The TxD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TxD input. CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled (for more details please refer to u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT command) the CTS line indicates when the UART interface is enabled (data can be sent and received): the module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE (refer to chapter 1.9.2.3 for the complete description). If the hardware flow control is not enabled, the CTS line is always held in the ON state after UART initialization. In case of hardware flow control enabled, when CTS line is ON the UART is enabled and the module is in active mode. Instead, CTS line to OFF doesnt necessary mean that the module is in idle-mode, but only that the UART is not enabled (the module could be forced to stay in active-mode for instance by USB). When the power saving configuration is enabled and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in idle-mode wont be a valid communication character (refer to chapter 1.9.2.3 for the complete description). When the MUX protocol is active on UART interface, the CTS line state is mapped to FCon / FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator. For more details please refer to Mux Implementation Application Note [16]. RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The RTS line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled (for more details please refer to u-blox AT Commands Manual [3] AT&K, AT\Q, AT+IFC command description) the RTS line is monitored by the module to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to OFF state, any on-going data transmission from the module is immediately interrupted or any subsequent transmission forbidden until the RTS line changes to ON state. The DTE must be able to still accept a certain number of characters after the RTS line has been set to OFF state: the module guarantees the transmission interruption within 2 characters from RTS state change. If AT+UPSV=2 is set and HW flow control is disabled, the RTS line is monitored by the module to manage the power saving configuration:

When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module is forced to active-mode; after 20 ms from the transition the switch is completed and data can be received without loss. The module cant enter idle-mode and the UART is keep enabled as long as the RTS input line is held in the ON state 3G.G2-HW-10002-A1 Advance Information System description Page 49 of 160 LISA-U series - System Integration Manual If RTS is set to OFF state by the DTE, the module automatically enters idle-mode whenever possible as in the AT+UPSV=1 configuration (cyclic idle/active mode), but UART is disabled (held in low power mode) For more details please refer to chapter 1.9.2.3 and u-blox AT Commands Manual [3], AT+UPSV command. DSR signal behavior If AT&S0 is set, the DSR module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&S1 is set, the DSR module output line is set by default to OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode. The above behavior is valid for both Packet-Switched and Circuit-Switched Data transfer. DTR signal behavior The DTR module input line is set by default to OFF state (high level) at UART initialization. The DTR line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status depends on the AT command configuration (see u-blox AT Commands Manual [3], &D AT command). DCD signal behavior If AT&C0 is set, the DCD module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&C1 is set, the DCD module output line is set by default to OFF state (high level) at UART initialization. The DCD line is then set by the module in accordance with the carrier detect status: ON if the carrier is detected, OFF otherwise. In case of voice call DCD is set to ON state when the call is established. For a data call there are the following scenarios:

GPRS data communication: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. Please note that the DCD ON is not related to the context activation but with the data mode CSD data call: To establish a data call the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE In case of a voice call DCD is set to ON state on all the serial communication interfaces supporting the AT command interface. (including MUX virtual channels, if active). DCD is set to ON during the execution of a command requiring input data from the DTE (all the commands where a prompt is issued; see AT commands +CMGS, +CMGW, +USOWR, +USODL,

+UDWNFILE in u-blox AT Commands Manual [3]). The DCD line is set to ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed. 3G.G2-HW-10002-A1 Advance Information System description Page 50 of 160 LISA-U series - System Integration Manual DCD line is kept to ON state even during the online command state to indicate that the data call is still established even if suspended, while if the module enters command mode DSR line is set to OFF state. For more details refer to DSR signal behavior description. In case of scenarios for which the DCD line setting is requested for different reasons (e.g. SMS texting during online command state), the DCD line changes to guarantee the correct behavior for all the scenarios. For instance, in case of SMS texting in online command state, if the data call is released, the DCD line will be kept to ON till the SMS command execution is completed (even if the data call release would request the DCD setting to OFF). RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from OFF state to ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 23), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 23: RI behavior during an incoming call The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 24), if the feature is enabled by the proper AT command (please refer to u-blox AT Commands Manual [3], AT+CNMI command). RI OFF RI OFF RI ON RI ON 1s 1s 0 0 SMS arrives SMS Figure 24: RI behavior at SMS arrival time [s]

time [s]

This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. In case of SMS arrival, if several events occur coincidently or in quick succession each event triggers the RI line independently, although the line will not be deactivated between each event. As a result, the RI line may stay to ON for more than 1 s. If an incoming call is answered within less than 1 s (with ATA or if autoanswering is set to ATS0=1) than the RI line will be set to OFF earlier. As a result:

RI line monitoring cant be used by the DTE to determine the number of received SMSes. 3G.G2-HW-10002-A1 Advance Information System description Page 51 of 160 1stime [s]151050RI ONRI OFFCall incomes1stime [s]151050RI ONRI OFFCall incomes LISA-U series - System Integration Manual In case of multiple events (incoming call plus SMS received), the RI line cant be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with the proper commands. 1.9.2.3 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description please refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible, otherwise the active-mode is maintained by the module. The AT+UPSV command sets the module power saving configuration, but also configures the UART behavior in relation to the power saving configuration. The conditions for the module entering idle-mode also depend on the UART power saving configuration. The different power saving configurations that can be set by the AT+UPSV command are described in the following subchapters and are summarized in Table 24. For more details on the command description please refer to u-blox AT commands Manual [3]. AT+UPSV HW flow control RTS line Communication during idle-mode and wake up 0 0 0 0 1 1 1 1 2 2 2 2 Enabled (AT&K3) Enabled (AT&K3) Disabled (AT&K0) Disabled (AT&K0) ON OFF ON OFF Enabled (AT&K3) ON Enabled (AT&K3) OFF Disabled (AT&K0) ON Disabled (AT&K0) OFF Enabled (AT&K3) Enabled (AT&K3) Disabled (AT&K0) ON OFF ON Disabled (AT&K0) OFF Data sent by the DTE will be correctly received by the module. Data sent by the module will be buffered by the module and will be correctly received by the DTE when it will be ready to receive data (i.e. RTS line will be ON). Data sent by the DTE will be correctly received by the module. Data sent by the module will be correctly received by the DTE if it is ready to receive data, otherwise data will be lost. Data sent by the DTE will be buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module will be buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). If the module is in idle-mode, when a low-to-high transition occurs on the TxD input line, the module switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode

(i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Data sent by the module will be correctly received by the DTE if it is ready to receive data, otherwise data will be lost. Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. The module is forced in active-mode and it cant enter idle-mode until RTS line is set to OFF state. When a high-to-low (i.e. OFF-to-ON) transition occurs on the RTS input line, the module switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. When a low-to-high transition occurs on the TxD input line, the UART is re-enabled and if the module was in idle-mode it switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode (i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Table 24: UART and power-saving summary AT+UPSV=0: power saving disabled, fixed active-mode The module doesnt enter idle-mode and the UART interface is enabled (data can be sent and received): the CTS line is always held in the ON state after UART initialization. This is the default configuration. 3G.G2-HW-10002-A1 Advance Information System description Page 52 of 160 LISA-U series - System Integration Manual AT+UPSV=1: power saving enabled, cyclic idle/active mode The module automatically enters idle-mode whenever possible, if a voice or data call (2G or 3G) is not enabled, and periodically wakes up from idle-mode to active-mode to monitor the paging channel of the current base station (paging block reception), according to 2G or 3G discontinuous reception (DRX) specification. The time period between two paging receptions is defined by the current base station (i.e. by the network):

If the module is registered with a 2G network, the paging reception period can vary from ~0.47 s (DRX = 2, i.e. 2 x 51 2G-frames) up to ~2.12 s (DRX = 9, i.e. 9 x 51 2G-frames) If the module is registered with a 3G network, the paging reception period can vary from 0.64 s (DRX = 6, i.e. 26 3G-frames) up to 5.12 s (DRX = 9, i.e. 29 3G-frames). The UART interface is automatically disabled whenever possible, if data has not been received or sent by the UART for the timeout configured by the +UPSV AT command, and is periodically enabled to receive or send data. When the module is in idle-mode, the UART interface is always disabled. When the module is in active-mode or connected-mode, the UART interface is automatically disabled to reduce the consumed power, if data has not been received or sent by the UART for the configured timeout. The time period of the UART enable/disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network:

2G: the UART is enabled synchronously to paging receptions, but not necessarily at every paging reception

(to reduce the consumed power): the UART interface is enabled for 20 ms concurrently to a paging reception, and then, as data has not been received or sent, the UART is disabled until the first paging reception that occurs after a timeout of 2.0 s, and therefore the interface is enabled again 3G: the UART is enabled asynchronously to paging receptions: the UART interface is enabled for 20 ms, and then, as data has not been received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again Not registered: when the module is not registered with a network, the UART interface is enabled for 20 ms, and then, if data has not been received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again When UART interface is disabled, data transmitted by the DTE will be lost if hardware flow control is disabled. If hardware flow control is enabled, data will be buffered by the DTE and will be correctly received by the module when UART interface is enabled again. When UART interface is enabled, data can be received. When a character is received, it forces the UART interface to stay enabled for a longer time and it forces the module to stay in the active-mode for a longer time. The active-mode duration depends by:

Network parameters, related to the time interval for the paging block reception (minimum of ~11 ms) Duration of UART enable time in absence of data reception (20 ms) Time period from the last data received at the serial port during the active-mode: the module doesnt enter idle-mode until a timeout expires. This timeout is configured by the second parameter of the +UPSV AT command, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms

= 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s) Every subsequent character received during the active-mode, resets and restarts the timer; hence the active-

mode duration can be extended indefinitely. The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can be sent and received), if HW flow control is enabled, as illustrated in Figure 25. 3G.G2-HW-10002-A1 Advance Information System description Page 53 of 160 LISA-U series - System Integration Manual Figure 25: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level) AT+UPSV=2: power saving enabled and controlled by the RTS line If the RTS line is set to OFF by the DTE the module is allowed to enter idle-mode as for UPSV=1 case. Instead, the UART is disabled as long as RTS line is set to OFF. If the RTS line is set to ON by the DTE the module is not allowed to enter idle-mode and the UART is kept enabled until the RTS line is set to OFF. When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module switches from idle-mode to active-mode in 20 ms. This configuration can only be enabled with the module HW flow control disabled. When the RTS line is set to OFF by the DTE, the timeout to enter idle-mode from the last data received at the serial port during the active-mode is the one previously set with the AT+UPSV=1 configuration or it is the default value. Since HW flow control is disabled, the CTS line is always set to ON by the module. If the module must transmit some data (e.g. URC), the UART is temporarily enabled even if the RTS line is set to OFF; UART wake-up in case of RTS line set to OFF is also possible via data reception (as described in the following). If the USB is connected and active, the module is forced to stay in active-mode, therefore +UPSV=1 and

+UPSV=2 modes are overruled, but in any case they have effect on the UART behavior (they configure UART power saving mode, when it is enabled/disabled). Wake up from idle-mode to active-mode via data reception If data is transmitted by the DTE during the module idle-mode, it will be lost (not correctly received by the module) in the following cases:

+UPSV=1 with hardware flow control disabled

+UPSV=2 with hardware flow control disabled and RTS line set to OFF When the module is in idle-mode, the TxD input line of the module is always configured to wake up the module from idle-mode to active-mode via data reception: when a low-to-high transition occurs on the TxD input line, it causes the wake-up of the system. The module switches from idle-mode to active-mode within 20 ms from the first data reception: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode (i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Figure 26 and Figure 27 show an example of common scenarios and timing constraints:

HW flow control set in the DCE, and no HW flow control set in the DTE, needed to see the CTS line changing on DCE 3G.G2-HW-10002-A1 Advance Information System description Page 54 of 160 time [s]CTS ONCTS OFFUART disabled2G/3G: 20 msUART enabled2G/3G: ~9.2 s (default)UART enabledData input2G: 2.10-3.75 s3G: 2.50 s LISA-U series - System Integration Manual Power saving configuration is active and the timeout from last data received to idle-mode start is set to 2000 frames (AT+UPSV=1,2000) Figure 26 shows the case where DCE is in idle-mode and a wake-up is forced. In this scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE will return to idle-mode when the timeout from last data received expires. (2000 frames without data reception). Figure 26: Wake-up via data reception without further communication Figure 27 shows the case where in addition to the wake-up character further (valid) characters are sent. The wake up character wakes-up the DCE. The other characters must be sent after the wake up time of 20 ms. If this condition is satisfied, the characters are recognized by the DCE. The DCE is allowed to re-enter idle-mode after 2000 GSM frames from the latest data reception. Figure 27: Wake-up via data reception with further communication LISA-U2 series modules dont wake-up from idle-mode to active-mode via data reception by TxD input line, if HW flow control is enabled. The wake-up via data reception feature cant be disabled. 3G.G2-HW-10002-A1 Advance Information System description Page 55 of 160 CTS OFFCTSONActive mode is held for 2000 GSM frames (~9.2 s)time Wake up time: up to 15.6 mstime TxD module inputWake up character Not recognized by DCECTS OFFCTSONActive mode is held for 2000 GSM frames (~9.2s) after the last data receivedtime Wake up time: up to 15.6 mstime TxD module inputWake up character Not recognized by DCEValid characters Recognized by DCE LISA-U series - System Integration Manual The wake-up via data reception feature can be used in both +UPSV=1 and +UPSV=2 case (when RTS line is set to OFF). In command mode, if HW flow control is not implemented by the DTE, the DTE must always send a dummy AT to the module before each command line: the first character will not be ignored if the module is in active-mode (i.e. the module will reply OK), or it will represent the wake up character if the module is in idle-mode (i.e. the module wont reply). No dummy AT is required from the DTE during connected-mode since the module continues to be in active-mode and doesnt need to be woken-up. Furthermore in data mode a dummy AT would affect the data communication. 1.9.2.4 UART application circuits Providing the full RS-232 functionality (using the complete V.24 link) For complete RS-232 functionality conforming to ITU Recommendation [4] in DTE/DCE serial communication, the complete UART interface of the module (DCE) must be connected to a 1.8V DTE as described in Figure 28. Figure 28: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, appropriate voltage translators must be utilized, as described in Figure 29. 3G.G2-HW-10002-A1 Advance Information System description Page 56 of 160 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP LISA-U series - System Integration Manual Figure 29: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1, U2 Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 25: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) 3G.G2-HW-10002-A1 Advance Information System description Page 57 of 160 4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2B3A3VCCBVCCAUnidirectionalVoltage TranslatorC3C43V0DIR1DIR3OEB2 A2B4A4DIR4DIR2 LISA-U series - System Integration Manual Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link) If the functionality of the DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, the circuit with a 1.8 V Application Processor should be implemented as described in Figure 30:

Connect the module DTR input line to GND, since the module requires DTR active (low electrical level) Leave DSR, DCD and RI lines of the module unconnected and floating Figure 30: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 31. Figure 31: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 26: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) If only TxD, RxD, RTS and CTS lines are provided, as implemented in Figure 30 and in Figure 31, the procedure to enable power saving depends on the HW flow-control status. If HW flow-control is enabled (AT&K3, that is 3G.G2-HW-10002-A1 Advance Information System description Page 58 of 160 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR4 LISA-U series - System Integration Manual the default setting) power saving will be activated by AT+UPSV=1. Through this configuration, when the module is in idle-mode, data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active-mode is entered. If the HW flow-control is disabled (AT&K0), the power saving can be enabled by AT+UPSV=2. The module is in idle-mode until a high-to-low (i.e. OFF-to-ON) transition on the RTS input line will switch the module from idle-mode to active-mode in 20 ms. The module will be forced in active-mode if the RTS input line is held in the ON state. Providing the TxD and RxD lines only (not using the complete V24 link) If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, the circuit with a 1.8 V Application Processor should be implemented as described in Figure 32:

Connect the module CTS output line to the module RTS input line, since the module requires RTS active

(low electrical level) if HW flow-control is enabled (AT&K3, that is the default setting), and CTS is active (low electrical level) when the module is in active mode, the UART interface is enabled and the HW flow-control is enabled Connect the module DTR input line to GND, since the module requires DTR active (low electrical level) Leave DSR, DCD and RI lines of the module unconnected and floating Figure 32: UART interface application circuit with partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 33. 3G.G2-HW-10002-A1 Advance Information System description Page 59 of 160 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 TPTP LISA-U series - System Integration Manual Figure 33: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 27: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) If only TxD and RxD lines are provided, as described in Figure 32 and in Figure 33, and HW flow-control is disabled (AT&K0), the power saving will be enabled by AT+UPSV=1. The module enters active-mode 20 ms after a low-to-high transition on the TxD input line, and the recognition of the subsequent characters is guaranteed until the module is in active-mode. Data delivered by the DTE can be lost using this configuration and the following settings:

o HW flow-control enabled in the module (AT&K3, that is the default setting) o Module power saving enabled by AT+UPSV=1 o HW flow-control disabled in the DTE In this case the first character sent when the module is in idle-mode will be a wake-up character and wont be a valid communication character (refer to chapter 1.9.1.3 for the complete description). If power saving is enabled the application circuit with the TxD and RxD lines only is not recommended. During command mode the DTE must send to the module a wake-up character or a dummy AT before each command line (refer to chapter 1.9.1.3 for the complete description), but during data mode the wake-up character or the dummy AT would affect the data communication. 3G.G2-HW-10002-A1 Advance Information System description Page 60 of 160 4V_INTTxDApplication Processor(3.0V DTE)RxDDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD9DSR10RI11DCDGND0 0 TPTP1V8B1 A1GNDU1VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR1DIR2OEVCCB2 A2RTSCTS13RTS14CTS0 TPTP LISA-U series - System Integration Manual Additional considerations If the module USB interface is connected to the application processor, it is highly recommended to provide direct access to RxD, TxD, CTS and RTS lines of the module for execution of firmware upgrade over UART and for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 series resistor must be mounted on each line to detach the module pin from any other connected device. Otherwise, if the USB interface is not connected to the application processor, it is highly recommended to provide direct access to VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [18]). If the UART interface is not used, all the UART interface pins can be left unconnected, but it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade and for debug purpose. Any external signal connected to the UART interface must be tri-stated when the module is in power-

down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.9.3 USB interface LISA-U series modules provide a high-speed USB interface at 480 Mb/s compliant with the Universal Serial Bus Revision 2.0 specification [8]. It acts as a USB device and can be connected to any USB host such as a PC or other Application Processor. The USB-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U series modules emulate all serial control logical lines. If the logical DTR line isn't enabled by the USB host, the LISA-U1xx-00 modules dont answer to AT commands by the USB interface. Name Description VUSB_DET USB_D+

USB detect input USB Data Line D+

USB_D-

USB Data Line D-

Table 28: USB pins Remarks Apply 5 V typical to enable USB 90 nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. 90 nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points. 3G.G2-HW-10002-A1 Advance Information System description Page 61 of 160 LISA-U series - System Integration Manual 1.9.3.1 USB features LISA-U series modules simultaneously support 6 USB CDC (Communications Device Class) that assure multiple functionalities to the USB physical interface. The 6 available CDCs are configured as described in the following list:

USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling dedicated port USB5: 2G and BB trace dedicated port USB6: 3G trace dedicated port All LISA-U2 series modules versions except LISA-U200-00 provide an additional USB CDC:

USB7: SIM Access Profile dedicated port The user can concurrently use AT command interface on one CDC and Packet-Switched / Circuit-Switched Data communication on another CDC. All LISA-U2 series modules versions except LISA-U200-00 support audio over USB capabilities: Audio Device Class is implemented to provide an audio streaming interface, which transfers audio data over isochronous pipes. USB drivers for Windows XP, Windows Vista, Windows 7, Windows CE, Windows EC and Android are available. LISA-U series module identifies itself by its VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor. VID and PID of LISA-U series modules are the following:

VID = 0x1546 PID = 0x1101 for LISA-U1 series PID = 0x1102 for LISA-U2 series If the USB interface of LISA-U series module is connected to the host before the module switch on, or if the module is reset with the USB interface connected to the host, the VID and PID are automatically updated runtime, after the USB detection. First, VID and PID are the following:

VID = 0x058B PID = 0x0041 Then, after a time period (~5 s), VID and PID are updated to the following:

VID = 0x1546 PID = 0x1101 for LISA-U1 series PID = 0x1102 for LISA-U2 series 1.9.3.2 USB and power saving If power saving is enabled by AT command (AT+UPSV=1 or AT+UPSV=2), the LISA-U series module automatically enters the USB suspended state when the device has observed no bus traffic for a specified period (refer to the Universal Serial Bus Revision 2.0 specification [8]). In suspended state, the module maintains any internal status as USB device, including its address and configuration. In addition, the module enters the suspended state when the hub port it is attached to is disabled: this is referred to as USB selective suspend. The module exits suspend mode when there is bus activity. LISA-U series module is capable of USB remote wake-up signaling: i.e. may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake-up. This notifies the host that it should resume from its suspended mode, if necessary, and service the external event that triggered the suspended USB device to signal the host. Remote wake-up is accomplished using electrical signaling described in the Universal Serial Bus Revision 2.0 specification [8]. 3G.G2-HW-10002-A1 Advance Information System description Page 62 of 160 LISA-U series - System Integration Manual When the USB enters suspended state, the average VCC module current consumption of LISA-U series module is

~400 A higher then when the USB is not attached to a USB host. If power saving is disabled by AT+UPSV=0 and the LISA-U series module is attached to a USB host as USB device, is configured and is not suspended, the average VCC module current consumption in fixed active mode is increased to ~40 mA. 1.9.3.3 USB application circuit Since the module acts as a USB device, the USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host. The USB interface is enabled only when a valid voltage as USB supply is detected by the VUSB_DET input. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. USB pull-up or pull-down resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [8] are part of the USB pad driver and do not need to be externally provided. External series resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [8] are also integrated: characteristic impedance of USB_D+ and USB_D- lines is specified by the USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if the PCB layout is not optimal, especially when the USB signaling lines are very long. Figure 34: USB Interface application circuit Reference D1, D2, D3 C2 Description Part Number - Manufacturer Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Table 29: Component for USB application circuit If the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debug purpose: testpoints can be added on the lines to accommodate the access. Otherwise, if the USB interface is connected to the application processor, it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade over UART and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [18]). 3G.G2-HW-10002-A1 Advance Information System description Page 63 of 160 LISA-U series VBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GNDC1USB DEVICE CONNECTORD1D2D3 LISA-U series - System Integration Manual If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected, but it is highly recommended to provide direct access to the lines for execution of firmware upgrade and for debug purpose. 1.9.4 SPI interface SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration. The SPI-compatible synchronous serial interface cannot be used for FW upgrade. The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and SPI_MISO) and a clock signal (SPI_SCLK). LISA-U series modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard 3-wire SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface. The purpose of the IPC interface is to achieve high speed communication (up to 26 Mb/s) between two processors following the same IPC specifications: the module baseband processor and an external processor. High speed communication is possible only if both sides follow the same Inter Processor Communication (IPC) specifications. Name SPI_MISO Description SPI Data Line. Master Input, Slave Output SPI_MOSI SPI Data Line. Master Output, Slave Input SPI_SCLK SPI Serial Clock. Master Output, Slave Input Remarks Module Output. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Module Input. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Internal active pull-up to V_INT (1.8 V) enabled. Module Input. Idle low (CPOL=0). Up to 26 MHz supported. Internal active pull-down to GND enabled. Module Input. Idle low. Internal active pull-down to GND enabled. SPI_MRDY SPI_SRDY SPI Master Ready to transfer data control line. Master Output, Slave Input SPI Slave Ready to transfer data control line. Master Input, Slave Output Module Output. Idle low. Table 30: SPI interface signals The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002 varistor array) on the lines connected to these pins, close to accessible points. 1.9.4.1 IPC communication protocol overview The module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration. The SPI-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U series modules emulate all serial logical lines: the transmission and the reception of the data are similar to an asynchronous device. 3G.G2-HW-10002-A1 Advance Information System description Page 64 of 160 LISA-U series - System Integration Manual Two additional signals (SPI_MRDY and SPI_SRDY) are added to the SPI lines to communicate the state of readiness of the two processors: they are used as handshake signals to implement the data flow. The function of the SPI_MRDY and SPI_SRDY signals is twofold:

For transmitting data the signal indicates to the data receiver that data is available to be transmitted For receiving data the signal indicates to the transmitter that the receiver is ready to receive data Due to this setup it is possible to use the control signals as interrupt lines waking up the receiving part when data is available for transfer. When the handshaking has taken place, the transfer occurs just as if it were a standard SPI interface without chip select functionality (i.e. one master - one slave setup). SPI_MRDY is used by the application processor (i.e. the master) to indicate to the module baseband processor

(i.e. the slave) that it is ready to transmit or receive (IPC master ready signal), and can also be used by the application processor to wake up the module baseband processor if it is in idle-mode. SPI_SRDY line is used by the module baseband processor (i.e. the slave) to indicate to the application processor

(i.e. the master) that it is ready to transmit or receive (IPC slave ready signal), and can also be used by the module baseband processor to wake up the application processor if it is in hibernation. Figure 35: IPC Data Flow: SPI_MRDY and SPI_SRDY line usage combined with the SPI protocol For the correct implementation of the SPI protocol, the frame size is known by both sides before a packet transfer of each packet. The frame is composed by a header with fixed size (always 4 bytes) and a payload with variable length (must be a multiple of 4 bytes). The same amount of data is exchanged in both directions simultaneously. Both sides set their readiness lines

(SPI_MRDY / SPI_SRDY) independently when they are ready to transfer data. For the correct transmission of the data the other side must wait for the activating interrupt to allow the transfer of the other side. The master starts the clock shortly after SPI_MRDY and SPI_SRDY are set to active. The number of clock periods sent by the master is exactly that one of the frame-size to be transferred. The SPI_SRDY line will be set low after the master sets the clock line to idle state. The SPI_MRDY line is also set inactive after the clock line is set idle, but in case of a big transfer containing multiple packets, the SPI_MRDY line stays active. 1.9.4.2 IPC communication and power saving If power saving is enabled by AT command (AT+UPSV=1 or AT+UPSV=2), the LISA-U series module automatically enters idle-mode when the master indicates that it is not ready to transmit or receive by the SPI_MRDY signal, or when the LISA-U series module itself doesnt transfer data. 3G.G2-HW-10002-A1 Advance Information System description Page 65 of 160 SPI_MRDYSPI_SRDYDATA_EXCHANGESPI_MOSISPI_MISOHeader DataSPI_SCLK LISA-U series - System Integration Manual 1.9.4.3 IPC communication examples In the following, three IPC communication scenarios are described:

Slave initiated data transfer, with a sleeping master Master initiated data transfer, with a sleeping slave Slave ended data transfer Slave initiated transfer with a sleeping master SPI_MRDY SPI_SRDY DATA EXCHG 2 1 3 Header Data 4 5 Header Figure 36: Data transfer initiated by LISA-U series module (slave), with a sleeping application processor (master) When the master is sleeping (idle-mode), the following actions happen:

1. The slave indicates the master that is ready to send data by activating SPI_SRDY 2. When the master becomes ready to send, it signalizes this by activating SPI_MRDY 3. The master activates the clock and the two processors exchange the communication header and data 4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK 5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3 Master initiated transfer with a sleeping slave SPI_MRDY SPI_SRDY DATA EXCHG 2 3 1 4 5 Header Data Header Figure 37: Data transfer initiated by application processor (master) with a sleeping LISA-U series module (slave) When the slave is sleeping (idle-mode), the following actions happen:

1. The Master wakes the slave by setting the SPI_MRDY line active 2. As soon as the slave is awake, it signals it by activating SPI_SRDY 3. The master activates the clock and the two processors exchange the communication header and data 3G.G2-HW-10002-A1 Advance Information System description Page 66 of 160 LISA-U series - System Integration Manual 4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK 5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock is active, all data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3 Slave ended transfer SPI_MRDY SPI_SRDY 4 1 5 2 3 DATA EXCHG Header Data Figure 38: Data transfer terminated and then restarted by LISA-U series module (slave) Starting from the state where data transfer is ongoing, the following actions will happen:

1. 2. In case of the last transfer, the master will lower its SPI_MRDY line. After the data-transfer is finished the line must be low. If the slave has already set its SPI_SRDY line, the master must raise its line to initiate the next transfer (slave-waking-procedure) If the data has been exchanged, the slave will deactivate SPI_SRDY to process the received information. This is the normal behavior 3. The slave will indicate the master that is ready to send data by activating SPI_SRDY 4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional, when SPI_MRDY is low before 5. The slave indicates immediately after a transfer termination that it is ready to start transmission again. In this case the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or low: the master has only to ensure that the SPI_SRDY change will be detected correctly via interrupt For more details regarding IPC communication protocol please refer to SPI Application Note [19]. 1.9.4.4 IPC application circuit SPI_MOSI is the data line input for the module since it runs as SPI slave: it must be connected to the data line output (MOSI) of the application processor that runs as an SPI master. SPI_MISO is the data line output for the module since it runs as SPI slave: it must be connected to the data line input (MISO) of the application processor that runs as an SPI master. SPI_SCLK is the clock input for the module since it runs as SPI slave: it must be connected to the clock line output (SCLK) of the application processor that runs as an SPI master. SPI_MRDY is an input for the module able to detect an external interrupt which comes from the application processor. SPI_SRDY is an output for the module, and the application processor should be able to detect an external interrupt which comes from the module on its connected pin. Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. 3G.G2-HW-10002-A1 Advance Information System description Page 67 of 160 LISA-U series - System Integration Manual Figure 39: IPC Interface application circuit If direct access to the USB or the UART interfaces of the module is not provided, it is recommended to provide direct access to the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY lines of the module for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 series resistor must be mounted on each line to detach the module pin from any other connected device. If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins can be left unconnected. Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in power-

down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.9.5 MUX Protocol (3GPP 27.010) LISA-U series modules have a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer Protocol [7], available either on the UART or on the SPI physical link. The USB interface doesnt support the multiplexer protocol. This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART or SPI): the user can concurrently use AT command interface on one MUX channel and Packet-Switched / Circuit-Switched Data communication on another MUX channel. The multiplexer protocol can be used on one serial interface (UART or SPI) at a time. Each session consists of a stream of bytes transferring various kinds of data such as SMS, CBS, PSD, GPS, AT commands in general. This permits, for example, SMS to be transferred to the DTE when a data connection is in progress. The following virtual channels are defined:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port For more details please refer to GSM Mux implementation Application Note [16]. 3G.G2-HW-10002-A1 Advance Information System description Page 68 of 160 LISA-U series(SPI slave)MOSIApplication Processor(SPI master)MISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGND LISA-U series - System Integration Manual 1.10 DDC (I2C) interface 1.10.1 Overview An I2C compatible Display Data Channel (DDC) interface for communication with u-blox GPS receivers is available on LISA-U series modules. The communication between a u-blox wireless module and a u-blox GPS receiver is only provided by this DDC (I2C) interface. Name SCL SDA Description I2C bus clock line I2C bus data line Table 31: DDC pins Remarks Open drain. External pull-up required. Open drain. External pull-up required. The DDC (I2C) interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. u-blox has implemented special features in LISA-U series wireless modules to ease the design effort required for the integration of a u-blox wireless module with a u blox GPS receiver. Combining a u-blox wireless module with a u-blox GPS receiver allows designers to have full access to the GPS receiver directly via the wireless module: it relays control messages to the GPS receiver via a dedicated DDC (I 2C) interface. A 2nd interface connected to the GPS receiver is not necessary: AT commands via the UART serial interface of the wireless module allows a fully control of the GPS receiver from any host processor. LISA-U series modules feature embedded GPS aiding that is a set of specific features developed by u-blox to enhance GPS performance, decreasing Time To First Fix (TTFF), thus allowing to calculate the position in a shorter time with higher accuracy. The DDC (I2C) interface of all LISA-U2 series modules versions except LISA-U200-00 can be used to communicate with u-blox GPS receivers and at the same time to control an external audio codec: the LISA-U2 series module acts as an I2C master which can communicate to two I2C slaves as allowed by the I2C bus specifications. Refer to section 1.11.2 for an application circuit with an external audio codec. LISA-U200-00 modules versions dont support an I2C compatible Display Data Channel (DDC) interface for communication with u-blox GPS receivers and dont feature embedded GPS aiding. For more details regarding the handling of the DDC (I2C) interface and the GPS aiding features please refer to u-blox AT Commands Manual [3] (AT+UGPS, AT+UGPRF, AT+UGPIOC commands) and GPS Implementation Application Note [17]. 1.10.2 DDC application circuit The DDC (I2C) interface of LISA-U series modules is used to connect the wireless module to a u-blox GPS receiver:

the communication with the u-blox GPS receiver by DDC (I2C) interface is enabled by the AT+UGPS command

(for more details refer to u-blox AT Commands Manual [3]). The SDA and SCL lines must be connected to the DDC (I2C) interface pins of the u-blox GPS receiver (i.e. the SDA2 and SCL2 pins of the u-blox GPS receiver) on the application board to allow the communication between the wireless module and the u-blox GPS receiver. To be compliant to the I2C bus specifications, the module bus interface pads are open drain output and pull up resistors must be used. Since the pull-up resistors are not mounted on the module, they must be mounted 3G.G2-HW-10002-A1 Advance Information System description Page 69 of 160 LISA-U series - System Integration Manual externally. Resistor values must conform to the I2C bus specifications [9]. If a LISA-U series module is connected by the DDC (I2C) bus to a u-blox GPS receiver (only one device can be connected on the DDC bus), use a pull-up resistor of 4.7 k . Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins. V_INT digital interfaces supply output can be used to provide 1.8 V for the pull-ups

(for detailed electrical characteristics see LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). DDC Slave-mode operation is not supported, the module can act as master only. Two lines, serial data (SDA) and serial clock (SCL), carry information on the bus. SCL is used to synchronize data transfers, and SDA is the data line. Since both lines are open drain outputs, the DDC devices can only drive them low or leave them open. The pull-up resistor pulls the line up to the supply rail if no DDC device is pulling it down to GND. If the pull-ups are missing, SCL and SDA lines are undefined and the DDC bus will not work. The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus will increase the capacitance. If the bus capacitance is increased, use pull-up resistors with nominal resistance value lower than 4.7 k , to match the I2C bus specifications [9].regarding rise and fall times of the signals. Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 s is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. If the pins are not used as DDC bus interface, they can be left unconnected. LISA-U series modules support these GPS aiding types:

Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GPS aiding features can be used only if the DDC (I2C) interface of the wireless module is connected to the u-blox GPS receivers. The GPIO pins can handle:

GPS receiver power-on/off (GPS supply enable function provided by GPIO2) The wake up from idle-mode when the GPS receiver is ready to send data (GPS data ready function provided by GPIO3) The RTC synchronization signal to the GPS receiver (GPS RTC sharing function provided by GPIO4) LISA-U1xx-00 modules versions dont support the following further features related to GPS functionality:

LISA-U1xx-00 modules versions dont enter idle-mode when the DDC (I2C) interface is enabled by the AT+UGPS command, even if power saving is enabled by the AT+UPSV command o o o LISA-U1xx-00 modules versions dont support GPS data ready and GPS RTC sharing functions LISA-U1xx-00 modules versions dont support AssistNow Autonomous GPS aiding The GPIO2 is by default configured to provide the GPS supply enable function (parameter <gpio_mode> of AT+UGPIOC command set to 3 by default), to enable or disable the supply of the u-blox GPS receiver connected to the wireless module by the AT+UGPS command. The pin is set as Output / High, to switch on the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 1 Output / Low, to switch off the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GPS receiver on the application board. 3G.G2-HW-10002-A1 Advance Information System description Page 70 of 160 LISA-U series - System Integration Manual The GPS supply enable function improves the power consumption of the GPS receiver. When the GPS functionality is not required, the GPS receiver can be completely switched off by the wireless module that is controlled by the application processor with AT commands. The GPIO3 is by default configured to provide the GPS data ready function (parameter <gpio_mode> of AT+UGPIOC command set to 4 by default), to sense when the u-blox GPS receiver connected to the wireless module is ready to send data by the DDC (I2C) interface. The pin will be set as Input, to sense the line status, waking up the wireless module from idle-mode when the u-blox GPS receiver is ready to send data by the DDC (I2C) interface, if the parameter <mode> of +UGPS AT command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GPS data ready function must be connected to the data ready output of the u-blox GPS receiver (i.e. the pin TxD1 of the u-blox GPS receiver) on the application board. The GPS data ready function provides an improvement in the power consumption of the wireless module. When power saving is enabled in the wireless module by the AT+UPSV command and the GPS receiver doesnt send data by the DDC (I2C) interface, the module automatically enters idle-mode whenever possible. With the GPS data ready function the GPS receiver can indicate to the wireless module that it is ready to send data by the DDC (I2C) interface: the GPS receiver can wake up the wireless module if it is in idle-mode, so that data sent by the GPS receiver will not be lost by the wireless module even if power saving is enabled. The GPIO4 is by default configured to provide the GPS RTC sharing function (parameter <gpio_mode> of

+UGPIOC AT command set to 5), to provide an RTC (Real Time Clock) synchronization signal at the power up of the u-blox GPS receiver connected to the wireless module. The pin will be set as Output, to provide an RTC synchronization signal to the u-blox GPS receiver for RTC sharing if the parameter

<mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 32 Output / Low, otherwise (default setting) The pin that provides the GPS RTC sharing function must be connected to the RTC synchronization signal of the u-blox GPS receiver (i.e. the pin EXTINT0 of the u-blox GPS receiver) on the application board. The GPS RTC sharing function provides improved GPS receiver performance, decreasing the Time To First Fix

(TTFF), and thus allowing to calculate the position in a shorter time with higher accuracy. When GPS local aiding is enabled, the wireless module automatically uploads data such as position, time, ephemeris, almanac, health and ionospheric parameter from the GPS receiver into its local memory, and restores this to the GPS receiver at the next power up of the GPS receiver. The application circuit for connecting a LISA-U series wireless module to a u-blox 1.8 V GPS receiver is illustrated in Figure 40. SDA and SCL pins of the LISA-U series wireless module are directly connected to the relative pins of the u-blox 1.8 V GPS receiver, with appropriate pull-up resistors. GPIO3 and GPIO4 pins are directly connected respectively to the TxD1 and EXTINT0 pins of the u-blox 1.8 V GPS receiver to provide GPS data ready and GPS RTC sharing functions. A pull-down resistor is mounted on the GPIO2 line to avoid a switch on of the GPS module when the LISA-U series module is in the internal reset state. The V_BCKP supply output of the LISA-U series wireless module is connected to the V_BCKP backup supply input pin of the GPS receiver to provide the supply for the GPS real time clock and backup RAM when the VCC supply of the wireless module is within its operating range and the VCC supply of the GPS receiver is disabled. This enables the u-blox GPS receiver to recover from a power breakdown with either a Hotstart or a Warmstart

(depending on the duration of the GPS VCC outage) and to maintain the configuration settings saved in the backup RAM. 3G.G2-HW-10002-A1 Advance Information System description Page 71 of 160 LISA-U series - System Integration Manual GPS data ready and GPS RTC sharing functions are not supported by all u-blox GPS receivers HW or ROM/FW versions. Refer to the GPS Implementation Application Note [17] or to the Hardware Integration Manual of the u-blox GPS receivers for the supported features. Figure 40: DDC Application circuit for u-blox 1.8 V GPS receiver Reference Description R1, R2 R3 U1 4.7 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W Part Number - Manufacturer RC0402JR-074K7L - Yageo Phycomp RC0402JR-0747KL - Yageo Phycomp Voltage Regulator for GPS Receiver See GPS Receiver Hardware Integration Manual Table 32: Components for DDC application circuit for u-blox 1.8 V GPS receiver The application circuit for the connection of a LISA-U series wireless module to a u-blox 3.0 V GPS receiver is illustrated in Figure 41. If a u-blox 3 V GPS receiver is used, the SDA, SCL, GPIO3 and GPIO4 pins of the LISA-U series wireless module cannot be directly connected to the u-blox 3 V GPS receiver: a proper I2C-bus Bidirectional Voltage Translator must be used for the SDA and SCL signals, and a general purpose Voltage Translator must be used for the GPIO3 and GPIO4 signals. The V_BCKP supply output of the wireless module can be directly connected to the V_BCKP backup supply input pin of the GPS receiver as in the application circuit for a u-blox 1.8 V GPS receiver. 3G.G2-HW-10002-A1 Advance Information System description Page 72 of 160 Functions not supported by LISA-Uxxx-00 versionsLISA-U seriesR1INOUTGNDGPS LDORegulatorSHDNu-blox1.8 V GPS receiverSDA2SCL2R21V81V8VMAIN1V8U121GPIO2SDASCLC1TxD1EXTINT0GPIO3GPIO446452324VCCR3V_BCKPV_BCKP2Functions not supported by LISA-U200-00 version LISA-U series - System Integration Manual Figure 41: DDC Application circuit for u-blox 3.0 V GPS receiver Reference Description R1, R2, R4, R5 4.7 k Resistor 0402 5% 0.1 W R3 47 k Resistor 0402 5% 0.1 W Part Number - Manufacturer RC0402JR-074K7L - Yageo Phycomp RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1 U2 U3 Voltage Regulator for GPS Receiver See GPS Receiver Hardware Integration Manual I2C-bus Bidirectional Voltage Translator PCA9306DCURG4 - Texas Instruments Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 33: Components for DDC application circuit for u-blox 3.0 V GPS receiver 3G.G2-HW-10002-A1 Advance Information System description Page 73 of 160 LISA-U seriesu-blox3.0 V GPS receiver23GPIO324GPIO41V8B1 A1GNDU3B2A2VCCBVCCAUnidirectionalVoltage TranslatorC4C53V0TxD1EXTINT0R1INOUTGNDGPS LDORegulatorSHDNR2VMAIN3V0U121GPIO246SDA45SCLR4R51V8SDA1 SDA2GNDU2SCL1SCL2VREF1VREF2I2C-bus Bidirectional Voltage Translator4V_INTC1C2C3R3SDA2SCL2VCCFunctions not supported by LISA-Uxxx-00 versionsDIR1DIR22V_BCKPV_BCKPOEFunctions not supported by LISA-U200-00 version LISA-U series - System Integration Manual 1.11 Audio Interface LISA-U120 and LISA-U130 modules provide analog and digital input/output audio interfaces:

Differential analog audio input (MIC_P, MIC_N) and differential analog audio output (SPK_P, SPK_N) 4-wire I2S digital audio interface (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) All LISA-U2 series modules versions except LISA-U200-00 provide two digital input/output audio interfaces:

1. 4-wire I2S digital audio interfaces (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) 2. 4-wire I2S digital audio interfaces (I2S1_CLK, I2S1_RXD, I2S1_TXD and I2S1_WA) Audio signal routing can be controlled by the dedicated AT command +USPM (refer to u-blox AT Commands Manual [3]). This command allows setting the audio path mode, composed by the uplink audio path and the downlink audio path. Each uplink path mode defines the physical input (i.e. the analog or the digital audio input) and the set of parameters to process the uplink audio signal (uplink gains, uplink digital filters, echo canceller parameters). For example the Headset microphone uplink path uses the differential analog audio input with the default parameters for the headset profile. Each downlink path mode defines the physical output (i.e. the analog or the digital audio output) and the set of parameters to process the downlink audio signal (downlink gains, downlink digital filters and sidetone). For example the Mono headset downlink path uses the differential analog audio output with the default parameters for the headset profile. The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in two profiles in the non volatile memory (refer to u-blox AT Commands Manual [3] for Audio parameters tuning commands). 1.11.1 Analog Audio interface LISA-U100, LISA-U110 and LISA-U2 series modules versions dont support analog audio interface. 1.11.1.1 Uplink path (differential analog audio input) The pins related to the differential analog audio input are:

MIC_P / MIC_N: Differential analog audio signal inputs (positive/negative). These two pins are provided with internal series 100 nF capacitors for DC blocking that connect the module pads to the differential input of a Low Noise Amplifier. The LNA output is internally connected to the digital processing system by an integrated sigma-delta analog-to-digital converter The analog audio input is selected when the parameter <main_uplink> in AT+USPM command is set to Headset microphone, Handset microphone or Hands-free microphone: the uplink analog path profiles use the same physical input but have different sets of audio parameters (for more details please refer to u-blox AT Commands Manual [3], AT+USPM, AT+UMGC, AT+UUBF, AT+UHFP commands). There is no microphone supply pin available on the module: an external low noise LDO voltage regulator should be added to provide a proper supply for a microphone. Detailed electrical characteristics of the differential analog audio input can be found in the LISA-U1 series Data Sheet [1]. 3G.G2-HW-10002-A1 Advance Information System description Page 74 of 160 LISA-U series - System Integration Manual 1.11.1.2 Downlink path (differential analog audio output) The pins related to the differential analog audio output are:

SPK_P / SPK_N: Differential analog audio signal output (positive/negative). These two pins are internally directly connected to the differential output of a low power audio amplifier, for which the input is internally connected to the digital processing system by to an integrated digital-to-analog converter The analog audio output is selected when the parameter <main_downlink> in AT+USPM command is set to Normal earpiece, Mono headset or Loudspeaker: the downlink analog path profiles use the same physical output but have different sets of audio parameters (for more details please refer to u-blox AT Commands Manual [3], AT+USPM, AT+USGC, AT+UDBF, AT+USTN commands). The differential analog audio output can be directly connected to a headset earpiece or handset earpiece but is not able to drive an 8 speaker. Detailed electrical characteristics of the differential audio output can be found in LISA-U1 series Data Sheet [1]. Warning: excessive sound pressure from headphones can cause hearing loss. Table 34 lists the signals related to analog audio functions. Name MIC_P MIC_N SPK_P SPK_N Module Description Remarks LISA-U120 LISA-U130 LISA-U120 LISA-U130 LISA-U120 LISA-U130 LISA-U120 LISA-U130 Differential analog audio input (Positive) Differential analog audio input (Negative) Differential analog audio output (Positive) Differential analog audio output (Negative) Shared for all uplink analog path modes:

handset, headset, hands-free mode. Internal DC blocking capacitor. Shared for all uplink analog path modes:

handset, headset, hands-free mode. Internal DC blocking capacitor. Shared for all uplink analog path modes:

earpiece, headset, loudspeaker mode. Shared for all uplink analog path modes:

earpiece, headset, loudspeaker mode. Table 34: Analog audio interface pins The audio pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. All corresponding differential audio lines must be routed in pairs, be embedded in GND (have the ground lines as close as possible to the audio lines), and maintain distance from noisy lines such as VCC and from components such as switching regulators. If the audio pins are not used, they can be left unconnected on the application board. 1.11.1.3 Headset mode Headset mode is the default audio operating mode of the LISA-U120 and LISA-U130 modules. The headset profile is configured when the uplink audio path is set to Headset microphone and the downlink audio path is set to Mono headset (refer to u-blox AT Commands Manual [3]: AT+USPM command: <main_uplink>,

<main_downlink> parameters):

Headset microphone must be connected to the module differential input MIC_P / MIC_N Headset receiver must be connected to the module differential output SPK_P / SPK_N 3G.G2-HW-10002-A1 Advance Information System description Page 75 of 160 LISA-U series - System Integration Manual Figure 42 shows an example of an application circuit connecting a headset (with a 2.2 k electret microphone and a 32 receiver) to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line, and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 42: Headset mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JA01 Murata C5, C6, C7 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata D1, D2 L1, L2 J1 Low Capacitance ESD Protection 82 nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) USB0002RP or USB0002DP AVX LQG15HS82NJ02 Murata Audio Headset 2.5 mm Jack Connector SJ1-42535TS-SMT CUI, Inc. R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp U1 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Table 35: Example of components for headset jack connection 1.11.1.4 Handset mode The handset profile is configured when the uplink audio path is set to Handset microphone and the downlink audio path is set to Normal earpiece (refer to u-blox AT commands manual [3]: AT+USPM command:

<main_uplink>, <main_downlink> parameters):

Handset microphone must be connected to the module differential input MIC_P / MIC_N Handset receiver must be connected to the module differential output SPK_P / SPK_N 3G.G2-HW-10002-A1 Advance Information System description Page 76 of 160 LISA-U120/U130C2C3C4J1253461L254SPK_N53SPK_P39MIC_N40MIC_PD1AUDIO HEADSET CONNECTORD2INOUTGNDLow Noise LDO RegulatorVMAINU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointL1C1C7 LISA-U series - System Integration Manual Figure 43 shows an example of an application circuit connecting a handset (with a 2.2 k electret microphone and a 32 receiver) to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 43: Handset mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JA01 Murata C5, C6, C7 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata D1, D2 L1, L2 J1 Low Capacitance ESD Protection 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) USB0002RP or USB0002DP AVX LQG15HS82NJ02 Murata Audio Handset Jack Connector, 4Ckt (4P4C) 52018-4416 Molex R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp U1 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Table 36: Example of components for handset connection 1.11.1.5 Hands-free mode The hands-free profile is configured when the uplink audio path is set to Hands-free microphone and the downlink audio path is set to Loudspeaker (refer to u-blox AT commands manual [3]: AT+USPM command:

<main_uplink>, <main_downlink> parameters):

Hands-free microphone signal must be connected to the module differential input MIC_P / MIC_N High power loudspeaker must be connected to the output of an external audio amplifier, for which the input must be connected to the module differential output SPK_P / SPK_N The module differential analog audio output is not able to drive an 8 speaker: an external audio amplifier must be provided on the application board to amplify the low power audio signal provided by the module differential output SPK_P / SPK_N. 3G.G2-HW-10002-A1 Advance Information System description Page 77 of 160 LISA-U120/U130C1C2C3J14321L153SPK_P54SPK_N40MIC_P39MIC_ND1AUDIO HANDSET CONNECTORD2INOUTGNDLow Noise LDO RegulatorU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointC4L2VMAINC7 LISA-U series - System Integration Manual Hands-free functionality is implemented using appropriate digital signal processing algorithms for voice-band handling (echo canceller and automatic gain control), managed via software (refer to u-blox AT commands manual [3], AT+UHFP command). Figure 43 shows an example of an application circuit connecting a 2.2 k electret microphone and an 8 speaker to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone and with an external audio amplifier to amplify the low power audio signal provided by the module differential output. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 44: Hands-free mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 Murata C5, C6, C7, C10 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata C8, C9 C11 D1, D2 J1 J2 L1, L2 MIC 47 nF Capacitor Ceramic X7R 0402 10% 16V GRM155R71C473KA01 Murata 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 Murata Low Capacitance ESD Protection USB0002RP or USB0002DP AVX Microphone Connector Speaker Connector 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) 2.2 k Electret Microphone LQG15HS82NJ02 Murata 3G.G2-HW-10002-A1 Advance Information System description Page 78 of 160 C1C2C3L139MIC_N53SPK_P40MIC_P54SPK_ND1Microphone ConnectorD2INOUTGNDLow Noise LDO RegulatorU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointC4SPKL2MICSpeaker ConnectorOUT+IN+GNDVMAINU2OUT-IN-C8C9R5R6VDDC11C10LISA-U120/U130Audio AmplifierJ1J2VMAINC7 LISA-U series - System Integration Manual Part Number Manufacturer RC0402JR-072K2L Yageo Phycomp RC0402JR-070RL Yageo Phycomp Reference Description R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W 0 Resistor 0402 5% 0.1 W 8 Loudspeaker R5, R6 SPK U1 U2 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Filter-less Mono 2.8 W Class-D Audio Amplifier SSM2305CPZ Analog Devices Table 37: Example of components for hands-free connection 1.11.1.6 Connection to an external analog audio device The differential analog audio input / output can be used to connect the module to an external analog audio device. Audio devices with a differential analog input / output are preferable, as they are more immune to external disturbances. If the external analog audio device is provided with a differential analog audio input, the SPK_P / SPK_N balanced output of the module must be connected to the differential input of the external audio device through a DC-block 10 F series capacitor (e.g. Murata GRM188R60J106M) to decouple the bias present at the module output (see SPK_P / SPK_N common mode output voltage in the LISA-U1 series Data Sheet [1]). Use a suitable power-on sequence to avoid audio bump due to charging of the capacitor: the final audio stage should be always enabled as last one. If the external analog audio device is provided with a single ended analog audio input, a proper differential to single ended circuit must be inserted from the SPK_P / SPK_N balanced output of the module to the single ended input of the external audio device. A simple application circuit is described in Figure 45: 10 F series capacitors (e.g. Murata GRM188R60J106M) are provided to decouple the bias present at the module output, and a voltage divider is provided to properly adapt the signal level from the module output to the external audio device input. The DC-block series capacitor acts as high-pass filter for audio signals, with cut-off frequency depending on both the values of capacitor and on the input impedance of the external audio device. For example: in case of

, the two 10 F capacitors will set the -3 dB cut-off frequency to 53 Hz, differential input impedance of 600 while for single ended connection to 600 external device, the cut-off frequency with just the single 10 F capacitor will be 103 Hz. In both cases the high-pass filter has a low enough cut-off to not impact the audio signal frequency response. The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the SPK_P / SPK_N output level of the module is too high for the input of the audio device. If the external analog audio device is provided with a differential analog audio output, the MIC_P / MIC_N balanced input of the module must be connected directly to the differential output of the external audio device. Series capacitors are not needed since MIC_P / MIC_N pins are provided with internal 100 nF capacitors for DC blocking (see LISA-U1 series Data Sheet [1]). If the external analog audio device is provided with a single ended analog audio output, a proper single ended to differential circuit has to be inserted from the single ended output of the external audio device to the MIC_P / MIC_N balanced input of the module. A simple application circuit is described in Figure 45: a voltage divider is provided to properly adapt the signal level from the external audio device output to the module input. The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the output level of the audio device is too high for MIC_P / MIC_N. Please refer to Figure 45 for the application circuits. To enable the audio path corresponding to the differential analog audio input / output, please refer to u-blox AT Commands Manual [3]: AT+USPM command. To tune audio levels for the external device please refer to u-blox AT Commands Manual [3] (AT+USGC, AT+UMGC commands). 3G.G2-HW-10002-A1 Advance Information System description Page 79 of 160 LISA-U series - System Integration Manual Figure 45: Application circuits to connect the module to audio devices with proper differential or single-ended input/output Reference Description Part Number Manufacturer C1, C2, C3, C4 10 F Capacitor X5R 0603 5% 6.3 V GRM188R60J106M Murata R1, R3 R2, R4 0 Resistor 0402 5% 0.1 W RC0402JR-070RL Yageo Phycomp Not populated Table 38: Connection to an analog audio device 1.11.2 Digital Audio interface LISA-U100, LISA-U110 and LISA-U200-00 modules versions dont support digital audio interface. LISA-U120 and LISA-U130 modules provide one bidirectional 4-wire I2S digital audio interface, while all LISA-U2 series modules versions except LISA-U200-00 provide two bidirectional 4-wire I2S digital audio interfaces for connecting to remote digital audio devices. LISA-U series modules can act as an I2S master or I2S slave. In master mode the word alignment and clock signals of the I2S digital audio interface are generated by the module. In slave mode these signal must be generated by the remote device. Table 39 lists the signals related to digital audio functions. 3G.G2-HW-10002-A1 Advance Information System description Page 80 of 160 LISA-U120/U130C1C254SPK_N53SPK_PGND40MIC_PGNDNegative Analog INPositive Analog INNegative Analog OUTPositive Analog OUTAudio DeviceReferenceReference39MIC_NLISA-U120/U13054SPK_N53SPK_PGND40MIC_PGNDAnalog INAudio DeviceReferenceReference39MIC_NAnalog OUTC3C4R2R1R4R3 I2S receive data Module input Name Module Description I2S transmit data I2S_TXD I2S_RXD I2S_CLK I2S_WA LISA-U120-0x LISA-U130-0x LISA-U2xx-01 LISA-U120-0x LISA-U130-0x LISA-U2xx-01 LISA-U120-00 LISA-U130-00 LISA-U120-01 LISA-U130-01 LISA-U2xx-01 LISA-U120-00 LISA-U130-00 LISA-U120-01 LISA-U130-01 LISA-U2xx-01 I2S clock I2S clock I2S word alignment I2S word alignment I2S1_TXD LISA-U2xx-01 I2S1_RXD LISA-U2xx-01 I2S1_CLK LISA-U2xx-01 Second I2S transmit data Second I2S receive data Second I2S clock I2S1_WA LISA-U2xx-01 Second I2S word alignment CODEC_CLK LISA-U2xx-01 Digital clock output Table 39: Digital audio interface pins LISA-U series - System Integration Manual Remarks Module output Module output in master mode Module output in master mode Module input in slave mode Module output in master mode Module output in master mode Module input in slave mode Module output Module input Module output in master mode Module input in slave mode Module output in master mode Module input in slave mode Digital clock output for external audio codec Configurable to 26 MHz or 13 MHz The I2S interfaces and CODEC_CLK pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a general purpose ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to the I 2S interfaces pins, close to accessible points, and a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002) on the line connected to CODEC_CLK pin, close to accessible point. The I2S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command:

PCM mode Normal I2S mode The I2S interface can be set to two configurations, by the <I2S_Master_Slave> parameter of AT+UI2S:

Master mode Slave mode LISA-U120-00 and LISA-U130-00 modules versions dont support I2S slave mode: module acts as master only. The sample rate of transmitted/received words can be set, by the <I2S_sample_rate> parameter of AT+UI2S, to:

8 kHz 11.025 kHz 12 kHz 16 kHz 22.05 kHz 24 kHz 3G.G2-HW-10002-A1 Advance Information System description Page 81 of 160 LISA-U series - System Integration Manual 32 kHz 44.1 kHz 48 kHz The sample rate of transmitted and received words of LISA-U120-00 and LISA-U130-00 modules cannot be configured: the sample rate is fixed at 8 kHz only. The <main_uplink> and <main_downlink> parameters of the AT+USPM command must be properly configured to select the I2S digital audio interfaces paths (for more details please refer to u-blox AT Commands Manual [3]):

<main_uplink> has to be properly set to select:

o o the first I2S interface (using I2S_RXD module input) the second I2S interface (using I2S1_RXD module input)

<main_downlink> has to be properly set to select:

o o the first I2S interface (using I2S_TXD module output) the second I2S interface (using I2S1_TXD module output) Parameters of digital path can be configured and saved as the normal analog paths, using appropriate path parameter as described in the u-blox AT Commands Manual [3], +USGC, +UMGC, +USTN AT command. Analog gain parameters of microphone and speakers are not used when digital path is selected. The I2S receive data input and the I2S transmit data output signals are respectively connected in parallel to the analog microphone input and speaker output signals, so resources available for analog path can be shared:

Digital filters and digital gains are available in both uplink and downlink direction. They can be properly configured by the AT commands Ringer tone and service tone are mixed on the TX path when active (downlink) The HF algorithm acts on I2S path Refer to the u-blox AT Commands Manual [3]: AT+UI2S command for possible settings of I2S interface. 1.11.2.1 I2S interface - PCM mode Main features of the I2S interface in PCM mode:

I2S runs in PCM - short alignment mode (configurable by AT commands) I2S word alignment signal can be configured to 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz I2S word alignment toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits I2S clock frequency depends on frame length and <sample_rate>. Can be 17 x <sample_rate> or 18 x

<sample_rate>

I2S transmit and I2S receive data are 16 bit words long with the same sampling rate as I2S word alignment, mono. Data is in 2s complement notation. MSB is transmitted first When I2S word alignment toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long I2S word alignment configuration) is MSB of the transmitted word (MSB is transmitted twice in this case) I2S transmit data changes on I2S clock rising edge, I2S receive data changes on I2S clock falling edge 3G.G2-HW-10002-A1 Advance Information System description Page 82 of 160 LISA-U series - System Integration Manual 1.11.2.2 I2S interface - Normal I2S mode Normal I2S supports:

16 bits word Mono interface Configurable sample rate: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz Main features of I2S interface in normal I2S mode:

I2S word alignment signal always runs at <sample_rate> and synchronizes 2 channels (timeslots on word alignment high, word alignment low) I2S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data are in 2s complement notation. MSB is transmitted first. The bits are written on I2S clock rising or falling edge (configurable) I2S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is read in 2s complement notation. MSB is read first. The bits are read on the I2S clock edge opposite to I2S transmit data writing edge (configurable) I2S clock frequency is 16 bits x 2 channels x <sample_rate>

The modes are configurable through a specific AT command (refer to the related chapter in u-blox AT Commands Manual [3], +UI2S AT command) and the following parameters can be set:

MSB can be 1 bit delayed or non-delayed on I2S word alignment edge I2S transmit data can change on rising or falling edge of I2S clock signal (rising edge in this example) I2S receive data are read on the opposite front of I2S clock signal 1.11.2.3 I2S interface application circuits The I2S digital audio interfaces of LISA-U series modules can be connected to an external digital audio device that supports the same mode (i.e. PCM or Normal I2S mode), proper configuration (slave or master), the same sample rate, and the same voltage level of the relative wireless module. Figure 46 shows an application circuit with a generic digital audio device. Figure 46: I2S interface application circuit with a generic digital audio device Figure 47 shows an application circuit for I2S digital audio interfaces of LISA-U2xx-01 modules, providing voice capability using an external audio voice codec. DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface. 3G.G2-HW-10002-A1 Advance Information System description Page 83 of 160 43I2S_CLK41I2S_WAI2S ClockI2S Word AlignmentLISA-U120-xxLISA-U130-xxLISA-U2xx-0142I2S_TXD44I2S_RXDI2S Data InputI2S Data OutputGNDGND1.8 V Digital Audio Device LISA-U series - System Integration Manual An I2S digital audio interface of the wireless module (that acts as an I2S master) is connected to the digital audio interface of the external audio codec (that acts as an I2S slave). The CODEC_CLK digital output clock of the wireless module is connected to the clock input of the external audio codec to provide clock reference. Signal integrity of the high speed lines may be degraded if the PCB layout is not optimal, especially when the CODEC_CLK clock line or also the I2S digital audio interface lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. The external audio codec is controlled by the wireless module using the DDC (I2C) interface: this interface can be used to communicate with u-blox GPS receivers and at the same time to control an external audio codec on all LISA-U2 series modules versions except LISA-U200-00. The V_INT supply output of the wireless module provides the supply to the external audio codec, defining a proper voltage level for the digital interfaces. Figure 47: I2S interface application circuit with an external audio codec to provide voice capability Reference Description Part Number Manufacturer C1 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 Murata C2, C4, C5, C6 1 F Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J105KE19 Murata C3 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata C7, C8, C9, C10 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 Murata D1, D2 J1 J2 L1, L2 MIC R1, R2 R3 Low Capacitance ESD Protection USB0002RP or USB0002DP AVX Microphone Connector Speaker Connector 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) 2.2 k Electret Microphone 4.7 k Resistor 0402 5% 0.1 W 10 k Resistor 0402 5% 0.1 W Various manufacturers Various manufacturers LQG15HS82NJ02 Murata Various manufacturers RC0402JR-074K7L - Yageo Phycomp RC0402JR-0710KL - Yageo Phycomp 3G.G2-HW-10002-A1 Advance Information System description Page 84 of 160 53I2S1_CLK54I2S1_WAR2R1BCLKGNDU1LRCLKC3C2LISA-U2xx-01Audio Codec40I2S1_TXD39I2S1_RXDSDINSDOUT46SDA45SCLSDASCL52CODEC_CLKMCLKGNDIRQnR3C1C10D2C9SPKSpeaker ConnectorOUTPOUTNJ24V_INTVDDMICBIASC4R4C5C6L1MICLNMICLPD1Microphone ConnectorL2MICC8C7J1MICGNDR51V8 LISA-U series - System Integration Manual Reference Description Part Number Manufacturer R4, R5 SPK U1 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp 32 Speaker 16-Bit Mono Audio Voice Codec Various manufacturers MAX9860ETG+ - Maxim Table 40: Example of components for audio voice codec application circuit If the I2S digital audio pins are not used, they can be left unconnected on the application board. Any external signal connected to the digital audio interfaces must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence

(at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during power down mode, when external reset is forced low and during power-on sequence. 1.11.3 Voiceband processing system The voiceband processing on the LISA-U series modules is implemented in the DSP core inside the baseband chipset. The analog audio front-end of the chipset is connected to the digital system through 16 bit ADC converters in the uplink path, and through 16 bit DAC converters in the downlink path. External digital audio devices can be interfaced directly to the DSP digital processing part via the I2S digital interface. The analog amplifiers are skipped in this case. Possible processing of audio signal are:

Speech encoding (uplink) and decoding (downlink).The following speech codecs are supported in firmware on the DSP:

Fullrate, enhanced full rate, and half rate speech encoding and decoding Adaptive multi rate (full rate and half rate) speech encoding and decoding Mandatory sub-functions:

Discontinuous transmission, DTX (GSM 46.031, 46.041, 46.081 and 46.093 standards) Voice activity detection, VAD (GSM 46.032, 46.042, 46.082 and 46.094 standards) Background noise calculation (GSM 46.012, 46.022, 46.062 and 46.092 standards) Function configurable via specific AT commands (refer to the u-blox AT Commands Manual [3]) Signal routing: +USPM command Analog amplification, Digital amplification: +USGC,+CLVL, +CRSL, +CMUT command Digital filtering: +UUBF, +UDBF commands Hands-free algorithms (echo cancellation, Noise suppression, Automatic Gain control) +UHFP command Sidetone generation (feedback of uplink speech signal to downlink path): +USTN command Playing/mixing of alert tones:

Service tones: Tone generator with 3 sinus tones +UPAR command User generated tones: Tone generator with a single sinus tone +UTGN command PCM audio files (for prompting): The storage format of PCM audio files is 8 kHz sample rate, signed 16 bits, little endian, mono With exception of the speech encoder/decoder, this audio processing can be controlled by AT commands. 3G.G2-HW-10002-A1 Advance Information System description Page 85 of 160 LISA-U series - System Integration Manual This processing is implemented within the different blocks of the voiceband processing system:

Sample-based Voice-band Processing (single sample processed at 8 kHz / 16 kHz) Frame-based Voice-band Processing (frames of 160 / 320 samples are processed every 20 ms) These blocks are connected by buffers (circular buffer and voiceband sample buffer) and sample rate converters

(for 8 / 16 to 47.6 kHz conversion). Voiceband audio processing implemented in the DSP core of LISA-U series modules is summarized in Figure 48. Figure 48: Voiceband processing system block diagram 3G.G2-HW-10002-A1 Advance Information System description Page 86 of 160 DACADCSwitchMicrophone Analog GainUF 2/6UF 1/5Hands-freeTo Radio TXScal_MicDigital GainSidetoneSPK_P/NSwitchScal_Rec Digital GainHS Analog gainTone GeneratorFrom Radio RXSpeech levelI2Sx RXPCM Player18 dBUF 4/8UF 3/7DF 3/7DF 4/8DF 1/5DF 2/6Legend:UF= uplink filterDF = downlink filterMix_AfeI2S Transmit DataMIC_P/NI2S Receive Data LISA-U series - System Integration Manual 1.12 General Purpose Input/Output (GPIO) The LISA-U1 series modules provide 5 pins (GPIO1-GPIO5), while the LISA-U2 series modules provide 14 pins

(GPIO1-14) which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands (for further details refer to u-blox AT Commands Manual [3], +UGPIOC,

+UGPIOR, +UGPIOW, +UGPS, +UGPRF, +USPM). The following functions are available in the LISA-U series modules:

GSM Tx burst indication:

GPIO1 pin can be configured by AT+UGPIOC to indicate when a GSM Tx burst/slot occurs, setting the parameter <gpio_mode> of AT+UGPIOC command to 9. No GPIO pin is by default configured to provide the GSM Tx burst indication function. The pin configured to provide the GSM Tx burst indication function is set as o Output / High, since ~10 s before the start of first Tx slot, until ~5 s after the end of last Tx slot o Output / Low, otherwise The pin configured to provide the GSM Tx burst indication function can be connected on the application board to an input pin of an application processor to indicate when a GSM Tx burst/slot occurs. GPS supply enable:

The GPIO2 is by default configured by AT+UGPIOC command to enable or disable the supply of the u-blox GPS receiver connected to the wireless module. The GPIO1, GPIO3, GPIO4 or GPIO5 pins can be configured to provide the GPS supply enable function, alternatively to the default GPIO2 pin, setting the parameter <gpio_mode> of AT+UGPIOC command to 3. The GPS supply enable mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the GPS supply enable function is set as o Output / High, to switch on the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 1 o Output / Low, to switch off the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin configured to provide the GPS supply enable function must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GPS receiver on the application board. LISA-U200-00 modules version dont support GPS supply enable function. GPS data ready:

Only the GPIO3 pin provides the GPS data ready function, to sense when a u-blox GPS receiver connected to the wireless module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode>

of AT+UGPIOC command to 4. The pin configured to provide the GPS data ready function will be set as o o Input, to sense the line status, waking up the wireless module from idle-mode when the u-blox GPS receiver is ready to send data via the DDC (I2C) interface; this is possible if the parameter <mode>

of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of AT+UGPRF command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GPS data ready function must be connected to the data ready output of the u-blox GPS receiver (i.e. the pin TxD1 of the u-blox GPS receiver) on the application board. 3G.G2-HW-10002-A1 Advance Information System description Page 87 of 160 LISA-U series - System Integration Manual LISA-U1xx-00 and LISA-U200-00 modules versions dont support GPS data ready function. GPS RTC sharing:

Only the GPIO4 pin provides the GPS RTC sharing function, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GPS receiver connected to the wireless module, setting the parameter

<gpio_mode> of AT+UGPIOC command to 5. The pin configured to provide the GPS RTC sharing function will be set as o Output, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GPS receiver if the parameter <mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration>

of AT+UGPRF command is set to 32 o Output / Low, otherwise (default setting) The pin that provides the GPS RTC sharing function must be connected to the RTC synchronization input of the u-blox GPS receiver (i.e. the pin EXTINT0 of the u-blox GPS receiver) on the application board. LISA-U1xx-00 and LISA-U200-00 modules versions dont support GPS RTC sharing function. SIM card detection:

The GPIO5 pin is by default configured by AT+UGPIOC command to detect SIM card presence. Only the GPIO5 pin can be configured to provide the SIM card detection function, setting the parameter

<gpio_mode> of AT+UGPIOC command to 7 (default setting). The pin configured to provide the SIM card detection function is set as o Input with an internal active pull-down enabled, to sense SIM card presence The pin must be connected on the application board to SW2 pin of the SIM card holder, which must provide 2 pins for the mechanical card presence detection, with a 470 k pull-down resistor. SW1 pin of the SIM card holder must be connected to V_INT pin of the module, by a 1 k pull-up resistor. Refer to Figure 49 and section 1.8 for the detailed application circuit. The GPIO5 signal will be pulled low by the pull-down when a SIM card is not inserted in the holder, and will be pulled high by the pull-up when a SIM card is present. Network status indication:

GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate network status (i.e. no service, registered home 2G network, registered home 3G network, registered visitor 2G network, registered visitor 3G network, voice or data 2G/3G call enabled), setting the parameter <gpio_mode> of AT+UGPIOC command to 2. No GPIO pin is by default configured to provide the Network status indication function. The Network status indication mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the Network status indication function is set as o Continuous Output / Low, if no service (no network coverage or not registered) o Cyclic Output / High for 100 ms, Output / Low for 2 s, if registered home 2G network o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 2 s, if registered home 3G network o Cyclic Output / High for 100 ms, Output / Low for 100 ms, Output / High for 100 ms, Output / Low for 2 s, if registered visitor 2G network (roaming) o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 100 ms, if registered visitor 3G network (roaming) o Continuous Output / High, if voice or data 2G/3G call enabled 3G.G2-HW-10002-A1 Advance Information System description Page 88 of 160 LISA-U series - System Integration Manual The pin configured to provide the Network status indication function can be connected on the application board to an input pin of an application processor or can drive a LED by a transistor with integrated resistors to indicate network status. Module status indication:

The GPIO13 and GPIO1 pins can be configured to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 10. No GPIO pin is by default configured to provide the Module status indication. The pin configured to provide the Module status indication function is set as o Output / High, when the module is switched on (any operating mode during module normal operation: idle, active or connected mode) o Output / Low, when the module is switched off (power off mode) The Module status indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. LISA-U1 series modules and LISA-U200-00 modules versions dont support Module status indication. Module operating mode indication:

The GPIO14 and GPIO5 pins can be configured to indicate module operating mode (idle-mode versus active or connected mode), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 11. No GPIO pin is by default configured to provide the Module operating mode indication. The pin configured to provide the Module operating mode indication function is set as o Output / High, when the module is in active or connected mode o Output / Low, when the module is in idle-mode (that can be reached if power saving is enabled by

+UPSV AT command: for further details refer to u-blox AT Commands Manual [3]) The Module operating mode indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. LISA-U1 series modules and LISA-U200-00 versions dont support Module operating mode indication. I2S digital audio interface:

The GPIO6, GPIO7, GPIO8, GPIO9 pins are by default configured as the second I2S digital audio interface

(I2S1_RXD, I2S1_TXD, I2S1_CLK, I2S1_WA respectively). Only these pins can be configured as the second I2S digital audio interface, correctly setting the parameter

<gpio_mode> of AT+UGPIOC command to 12 (default setting). LISA-U1 series modules and LISA-U200-00 versions dont support the second I2S digital audio interface over GPIOs. SPI serial interface:

GPIO10, GPIO11, GPIO12, GPIO13 and GPIO14 pins are by default configured as the SPI / IPC serial interface (SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_SRDY and SPI_MRDY respectively). Only these pins can be configured as the SPI / IPC serial interface, correctly setting the parameter

<gpio_mode> of AT+UGPIOC command to 13 (default setting). 3G.G2-HW-10002-A1 Advance Information System description Page 89 of 160 LISA-U series - System Integration Manual LISA-U1 series modules dont support SPI / IPC serial interface over GPIOs: the SPI / IPC pins provide the SPI / IPC function only and cannot be configured as GPIO. General purpose input:

All the GPIOs can be configured as input to sense high or low digital level through AT+UGPIOR command, setting the parameter <gpio_mode> of AT+UGPIOC command to 1. The General purpose input mode can be provided on more than one pin at a time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is by default configured as General purpose input. The pin configured to provide the General purpose input function is set as o Input, to sense high or low digital level by AT+UGPIOR command. The pin can be connected on the application board to an output pin of an application processor to sense the digital signal level. General purpose output:

All the GPIOs can be configured as output to set the high or the low digital level through AT+UGPIOW command, setting the parameter <gpio_mode> of +UGPIOC AT command to 0. The General purpose output mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is by default configured as General purpose output. The pin configured to provide the General purpose output function is set as o Output / Low, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 0 o Output / High, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 1 The pin can be connected on the application board to an input pin of an application processor to provide a digital signal. Pad disabled:

All the GPIOs can be configured in tri-state with an internal active pull-down enabled, as a not used pin, setting the parameter <gpio_mode> of +UGPIOC AT command to 255. The Pad disabled mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). The pin configured to provide the Pad disabled function is set as o Tri-state with an internal active pull-down enabled The configurations of all the GPIO pins of LISA-U series modules are described in Table 41. Pin Module Name Description Remarks 20 LISA-U1xx-xx GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GPS Supply Enable GSM Tx Burst Indication LISA-U200-00 GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GSM Tx Burst Indication 3G.G2-HW-10002-A1 Advance Information System description Page 90 of 160 LISA-U series - System Integration Manual Pin Module Name Description Remarks LISA-U2xx-01 GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GPS Supply Enable GSM Tx Burst Indication Module Status Indication 21 LISA-U1xx-xx LISA-U2xx-01 GPIO2 GPIO By default, the pin is configured to provide GPS Supply Enable function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication Pad disabled LISA-U200-00 GPIO2 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication 23 LISA-U1xx-00 GPIO3 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable LISA-U200-00 GPIO3 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication LISA-U1xx-01 LISA-U2xx-01 GPIO3 GPIO By default, the pin is configured to provide GPS Data Ready function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled 24 LISA-U1xx-00 GPIO4 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable LISA-U200-00 GPIO4 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication LISA-U1xx-01 LISA-U2xx-01 GPIO4 GPIO By default, the pin is configured to provide GPS RTC sharing function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled 3G.G2-HW-10002-A1 Advance Information System description Page 91 of 160 LISA-U series - System Integration Manual Pin Module Name Description Remarks 51 LISA-U1xx-xx GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled LISA-U200-00 GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication Pad disabled LISA-U2xx-01 GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Module Operating Mode Indication 39 LISA-U200-00 GPIO6 GPIO Pad disabled By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_RXD /

GPIO6 2nd I2S receive data /

GPIO By default, the pin is configured as 2nd I2S receive data input. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 40 LISA-U200-00 GPIO7 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_TXD /

GPIO7 2nd I2S transmit data /

GPIO By default, the pin is configured as 2nd I2S transmit data output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 53 LISA-U200-00 GPIO8 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_CLK /

GPIO8 2nd I2S clock /

GPIO By default, the pin is configured as 2nd I2S clock input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 54 LISA-U200-00 GPIO9 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_WA /

GPIO9 2nd I2S word alignment /

GPIO By default, the pin is configured as 2nd I2S word alignment input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 3G.G2-HW-10002-A1 Advance Information System description Page 92 of 160 LISA-U series - System Integration Manual Pin Module Name Description Remarks 55 LISA-U2xx-xx SPI_SCLK /

GPIO10 SPI Serial Clock /

GPIO 56 LISA-U2xx-xx SPI_MOSI /

GPIO11 SPI Data Line /

GPIO 57 LISA-U2xx-xx SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO By default, the pin is configured as SPI Serial Clock Input:

Idle low (CPOL=0) Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled By default, the pin is configured as SPI Data Line Input:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Internal active pull-up to V_INT enabled Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled By default, the pin is configured as SPI Data Line Output:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled 58 LISA-U200-00 SPI_SRDY /

GPIO13 SPI Slave Ready /

GPIO By default, the pin is configured as SPI Slave Ready Output:

Idle low Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled LISA-U2xx-01 SPI_SRDY /

GPIO13 SPI Slave Ready /

GPIO By default, the pin is configured as SPI Slave Ready Output:

Idle low Can be alternatively configured by the +UGPIOC command as Output Input Module Status Indication 59 LISA-U200-00 SPI_MRDY /

GPIO14 SPI Master Ready /

GPIO LISA-U2xx-01 SPI_MRDY /

GPIO14 SPI Master Ready /

GPIO Pad disabled By default, the pin is configured as SPI Master Ready Input:

Idle low Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled By default, the pin is configured as SPI Master Ready Input:

Idle low Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as Output Input Module Operating Mode Indication Table 41: GPIO pins Pad disabled The GPIO pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher 3G.G2-HW-10002-A1 Advance Information System description Page 93 of 160 LISA-U series - System Integration Manual protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. An application circuit for a typical GPIOs usage is described in Figure 49:

Network indication function provided by the GPIO1 pin GPS supply enable function provided by the GPIO2 pin (function not supported by LISA-U200-00) GPS data ready function provided by the GPIO3 pin (function not supported by LISA-Uxxx-00) GPS RTC sharing function provided by the GPIO4 pin (function not supported by LISA-Uxxx-00) SIM card detection function provided by the GPIO5 pin Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO. If the GPIO pins are not used, they can be left unconnected on the application board. Any external signal connected to GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. Figure 49: GPIO application circuit 3G.G2-HW-10002-A1 Advance Information System description Page 94 of 160 SIM card holderSW1 SW2 4V_INT51GPIO5R3R2OUTINGNDLDO RegulatorSHDN3V81V8GPIO3GPIO4TxD1EXTINT02324R1VCCGPIO221LISA-U seriesu-blox1.8 V GPS receiverU1J1C1R4R63V8Network IndicatorR5GPS Supply EnableGPS Data ReadyGPS RTC SharingSIM Detection20GPIO1DL1T1D1Functions not supported by LISA-Uxxx-00 versionsFunction not supported by LISA-U200-00 version LISA-U series - System Integration Manual Reference Description Part Number - Manufacturer R1 U1 R2 R3 D1 J1 R4 R5 R6 DL1 T1 47 k Resistor 0402 5% 0.1 W Various manufacturers Voltage Regulator for GPS Receiver See GPS Module Hardware Integration Manual 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W ESD Transient Voltage Suppressor SIM Card Holder 10 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W 820 Resistor 0402 5% 0.1 W LED Red SMT 0603 NPN BJT Transistor Various manufacturers Various manufacturers USB0002RP or USB0002DP - AVX CCM03-3013LFT R102 - C&K Components (or equivalent) Various manufacturers Various manufacturers Various manufacturers LTST-C190KRKT - Lite-on Technology Corporation BC847 - Infineon Table 42: Components for GPIO application circuit An application circuit for the module status indication function, provided by LISA-U2xx-01 GPIO13 and GPIO1 pins to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), is described in Figure 50. The logic level of the pin configured to provide module status indication, that is set high when the module is switched on and low when the module is switched off, is inverted by a transistor biased by the V_BCKP supply, which is generated by the module when a valid VCC is applied. Figure 50: Module status indication application circuit Reference Description Part Number - Manufacturer R1, R3 R2 T1 47 k Resistor 0402 5% 0.1 W 100 k Resistor 0402 5% 0.1 W NPN BJT Transistor Various manufacturers Various manufacturers BC847 - Infineon Table 43: Components for module status indication application circuit 3G.G2-HW-10002-A1 Advance Information System description Page 95 of 160 Input (1.8V)V_BCKP2LISA-U2xx-01Application ProcessorR1R3Module Status IndicationR220GPIO1T1 LISA-U series - System Integration Manual 1.13 Reserved pins (RSVD) LISA-U series modules have pins reserved for future use. All the RSVD pins, except pin number 5, can be left unconnected on the application board. The application circuit is illustrated in Figure 51. Pin 5 (RSVD) must be connected to GND. Figure 51: Application circuit for the reserved pins (RSVD) 3G.G2-HW-10002-A1 Advance Information System description Page 96 of 160 LISA-U120/U1305RSVD52RSVD74RSVDLISA-U100/U1105RSVD52RSVD74RSVD39RSVD40RSVD41RSVD42RSVD43RSVD44RSVD53RSVD54RSVDLISA-U2305RSVDLISA-U200-005RSVD52RSVD74RSVD41RSVD42RSVD43RSVD44RSVDLISA-U200-015RSVD74RSVD LISA-U series - System Integration Manual 1.14 Schematic for LISA-U series module integration Figure 52 is an example of a schematic diagram where a LISA-U1 series module is integrated into an application board, using all the interfaces of the module. Figure 52: Example of schematic diagram to integrate LISA-U1 series modules in an application board, using all the interfaces 3G.G2-HW-10002-A1 Advance Information System description Page 97 of 160 47pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF50VSIM48SIM_IO47SIM_CLK49SIM_RST47pFSW1 SW24V_INT51GPIO5470k1kESDESDESDESDESDESDTXDRXDRTSCTSDTRDSRRIDCDGND15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND3V8330F39pFGND10nF100nF10pFLISA-U1 series62VCC63VCC61VCC+100F2V_BCKPMOSIMISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGNDVBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GND100nF5RSVD52RSVD74RSVDGNDRTC back-up27pF27pF27pF82nH54SPK_N53SPK_P39MIC_N40MIC_PESDHeadset ConnectorESDINOUTGNDLow Noise LDO Regulator3V82.2k2.2k10F2.2k2.2k10F2V5Sense lines connected to GND in one star point82nH27pF10FESDESDu-blox1.8V GPS Receiver4.7kOUTINGNDLDO RegulatorSHDNSDASCL4.7k3V81V8_GPSSDA2SCL2GPIO3GPIO4TxD1EXTINT04645232447kVCCGPIO221ANT68Antenna1.8V DTE1.8V SPI MasterUSB 2.0 Host1.8V Digital Audio DeviceI2S_RXDI2S_CLKI2S Data OutputI2S ClockI2S_TXDI2S_WAI2S Data InputI2S Word Alligment44434241LISA-U120/U130 only20GPIO13V8Network Indicator22RESET_NFerrite Bead47pFApplication ProcessorOpen Drain Output19PWR_ON100kOpen Drain Output00TPTPFunctions not supported by LISA-U1xx-00 versions00TPTP LISA-U series - System Integration Manual Figure 53 is an example of a schematic diagram where a LISA-U2 series module is integrated into an application board, using all the interfaces of the module. Figure 53: Example of schematic diagram to integrate LISA-U2 series modules in an application board, using all the interfaces 3G.G2-HW-10002-A1 Advance Information System description Page 98 of 160 TXDRXDRTSCTSDTRDSRRIDCDGND15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND3V8330F39pFGND10nF100nF10pFLISA-U2 series62VCC63VCC61VCC+100F2V_BCKPMOSIMISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGNDVBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GND100nF5RSVD74ANT_DIVGNDRTC back-upu-blox1.8V GPS Receiver4.7kOUTINGNDLDO RegulatorSHDNSDASCL4.7k3V81V8_GPSSDA2SCL2GPIO3GPIO4TxD1EXTINT04645232447kVCCGPIO221ANT68Main Tx/Rx Antenna1.8V DTE1.8V SPI MasterUSB 2.0 Host20GPIO13V8Network Indicator22RESET_NFerrite Bead47pFApplication ProcessorOpen Drain Output19PWR_ON100kOpen Drain Output00TPTPFunctions not supported by LISA-U200-00 version00TPTP1.8V Digital Audio DeviceI2S_RXDI2S_CLKI2S Data OutputI2S ClockI2S_TXDI2S_WAI2S Data InputI2S Word Alligment44434241V_INTBCLKLRCLK10F1FAudio Codec MAX9860SDINSDOUTSDASCL53I2S1_CLK54I2S1_WA40I2S1_TXD39I2S1_RXD52CODEC_CLKMCLKIRQn10k100nFVDDSPKOUTPOUTN27pF27pFESDESDMICMICBIAS1F2.2k1F1F82nHMICLNMICLP82nHMICGND2.2kESDESD27pF27pFV_INTRx Diversity AntennaLISA-U230 only47pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF50VSIM48SIM_IO47SIM_CLK49SIM_RST47pFSW1 SW24V_INT51GPIO5470k1kESDESDESDESDESDESDV_INT LISA-U series - System Integration Manual 1.15 Approvals LISA-U series modules have been or will be approved under the following schemes:

[EU] R&TTE

[EU] CE

[EU] GCF CC

[EU] GCF FT

[USA] FCC

[USA] PTCRB

[Canada]: IC

(Radio and Telecommunications Terminal Equipment Directive)

(Conformit Europenne)

(Global Certification Forum-Certification Criteria)

(Global Certification Forum- Field Trials)

(Federal Communications Commission)

(PCS Type Certification Review Board)

(Industry Canada)

[South Africa]: ICASA

(Independent Communications Authority of South Africa)

[Australia]: a-tick

[Korea]: KCC

(Korean Communications Commission)

[Japan]: JATE

[Japan]: TELEC LISA-U series modules will be approved by the following network operators:

USA: AT&T Canada: Rogers 1.15.1 R&TTED and European Conformance CE mark Products bearing the CE marking comply with the R&TTE Directive (99/5/EC), EMC Directive (89/336/EEC) and the Low Voltage Directive (73/23/EEC) issued by the Commission of the European Community. Compliance with these directives implies conformity to the following European Norms:

Radio Frequency spectrum efficiency:

o o o EN 301 511 EN 301 908-1 EN 301 908-2 Electromagnetic Compatibility:

o o o EN 301 489-1 EN 301 489-7 EN 301 489-24 Safety o EN 60950-1: 2006 Notified Body identification number for LISA-U100, LISA-U110, LISA-U120 and LISA-U130 is 0890. Notified Body identification number for LISA-U200 is 0862. 1.15.2 IC The IC Certification Numbers for the LISA-U series modules are:

LISA-U100: 8595A-LISAU120 LISA-U120: 8595A-LISAU120 LISA-U200: 8595A-LISAU200 3G.G2-HW-10002-A1 Advance Information System description Page 99 of 160 LISA-U series - System Integration Manual 1.15.3 Federal communications commission notice The FCC ID for the LISA-U series modules are LISA-U100: XPYLISAU120 LISA-U120: XPYLISAU120 LISA-U200: XPYLISAU200 1.15.3.1 Safety Warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product The clearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, no hygroscopic materials nor materials containing asbestos are employed 1.15.3.2 Declaration of Conformity - United States only This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure Information: this equipment complies with FCC radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. The system antenna(s) used for LISA-U200 must not exceed 1.11 dBi (GSM 850 MHz), 1.55 dBi

(GSM 1900 MHz), 7.31 dBi (FDD Band V) and 5.39 dBi (FDD Band II) for mobile and fixed or mobile operating configurations. 1.15.3.3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the LISA-U series modules are authorized to use the FCC Grants and Industry Canada Certificates of the LISA-U series modules for their own final products according to the conditions referenced in the certificates. The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

LISA-U100: "Contains FCC ID: XPYLISAU120" resp. LISA-U120: "Contains FCC ID: XPYLISAU120" resp. LISA-U200: "Contains FCC ID: XPYLISAU200" resp. The IC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

LISA-U100: "Contains IC: 8595A-LISAU120" resp. 3G.G2-HW-10002-A1 Advance Information System description Page 100 of 160 LISA-U series - System Integration Manual LISA-U120: "Contains IC: 8595A-LISAU120" resp. LISA-U200: "Contains IC: 8595A-LISAU200" resp. Canada, Industry Canada (IC) Notices This Class B digital apparatus complies with Canadian ICES-003 and RSS-210. Operation is subject to the following two conditions:

o o this device may not cause interference this device must accept any interference, including interference that may cause undesired operation of the device Radio Frequency (RF) Exposure Information The radiated output power of the u-blox Wireless Module is below the Industry Canada (IC) radio frequency exposure limits. The u-blox Wireless Module should be used in such a manner such that the potential for human contact during normal operation is minimized. This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canadas REL the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng

(Radio Equipment found at can be List) Additional Canadian information on RF exposure also can be found at the following web address: http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: Manufacturers of portable applications incorporating the LISA-U series modules are required to have their final product certified and apply for their own FCC Grant and Industry Canada Certificate related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Canada, avis d'Industrie Canada (IC) Cet appareil numrique de classe B est conforme aux normes canadiennes ICES-003 et RSS-210. Son fonctionnement est soumis aux deux conditions suivantes:

o o cet appareil ne doit pas causer d'interfrence cet appareil doit accepter toute interfrence, notamment les interfrences qui peuvent affecter son fonctionnement Informations concernant l'exposition aux frquences radio (RF) La puissance de sortie mise par lappareil de sans fil u-blox Wireless Module est infrieure la limite d'exposition aux frquences radio d'Industrie Canada (IC). Utilisez lappareil de sans fil u-blox Wireless Module de faon minimiser les contacts humains lors du fonctionnement normal. Ce priphrique a t valu et dmontr conforme aux limites d'exposition aux frquences radio (RF) d'IC lorsqu'il est install dans des produits htes particuliers qui fonctionnent dans des conditions d'exposition des appareils mobiles (les antennes se situent plus de 20 centimtres du corps d'une personne). Ce priphrique est homologu pour l'utilisation au Canada. Pour consulter l'entre correspondant lappareil dans la liste d'quipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplmentaires concernant l'exposition aux RF au Canada rendez-vous sur : http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: les fabricants d'applications portables contenant les modules LISA-U1 series doivent faire certifier leur produit final et dposer directement leur candidature pour une certification FCC ainsi que pour un certificat Industrie Canada dlivr par l'organisme charg 3G.G2-HW-10002-A1 Advance Information System description Page 101 of 160 LISA-U series - System Integration Manual de ce type d'appareil portable. Ceci est obligatoire afin d'tre en accord avec les exigences SAR pour les appareils portables. Tout changement ou modification non expressment approuv par la partie responsable de la certification peut annuler le droit d'utiliser l'quipement. 3G.G2-HW-10002-A1 Advance Information System description Page 102 of 160 LISA-U series - System Integration Manual 1.15.4 a-tick AUS Certification The equipment may not function when mains power fail either on the packaging or with the equipment. LISA-U2 series is not a-tick AUS certified. 3G.G2-HW-10002-A1 Advance Information System description Page 103 of 160 LISA-U series - System Integration Manual 2 Design-In 2.1 Design-in checklist This section provides a design-in checklist. 2.1.1 Schematic checklist The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at VCC pin above the minimum operating range limit. DC supply must be capable of providing 2.5 A current pulses, providing a voltage at VCC pin above the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value. VCC supply should be clean, with very low ripple/noise: suggested passive filtering parts can be inserted. VCC voltage must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. Connect only one DC supply to VCC: different DC supply systems are mutually exclusive. Do not leave PWR_ON floating: add a pull-up resistor to V_BCKP. Dont apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal. Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [4]. Provide appropriate access to USB interface and/or to UART RxD, TxD lines and access to PWR_ON and/or RESET_N lines on the application board in order to flash/upgrade the module firmware. Provide appropriate access to USB interface and/or to UART RxD, TxD, CTS, RTS lines for debugging. Capacitance and series resistance must be limited on each line of the SPI / IPC interface. Add a proper pull-up resistor to a proper supply on each DDC (I2C) interface line, if the interface is used. Capacitance and series resistance must be limited on each line of the DDC interface. Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Connect the pin number 5 (RSVD) to ground. Insert the suggested passive filtering parts on each used analog audio line. Check the digital audio interface specifications to connect a proper device. Capacitance and series resistance must be limited on CODEC_CLK line and each I2S interface line. Provide proper precautions for ESD immunity as required on the application board. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 1500 ms after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. All unused pins can be left floating on the application board except the PWR_ON pin (must be connected to V_BCKP by a pull-up resistor) and the RSVD pin number 5 (must be connected to GND). 3G.G2-HW-10002-A1 Advance Information Design-In Page 104 of 160 LISA-U series - System Integration Manual 2.1.2 Layout checklist The following are the most important points for a simple layout check:

Check 50

(main RF input/output) and to the ANT_DIV pad (RF input for Rx diversity). nominal characteristic impedance of the RF transmission line connected to the ANT pad Follow the recommendations of the antenna producer for correct antenna installation and deployment

(PCB layout and matching circuitry). Ensure no coupling occurs with other noisy or sensitive signals (primarily analog audio input/output signals, SIM signals). VCC line should be wide and short. Route VCC supply line away from sensitive analog signals. The high-power audio outputs lines on the application board must be wide enough to minimize series resistance. Ensure proper grounding. Consider No-routing areas for the Data Module footprint. Optimize placement for minimum length of RF line and closer path from DC source for VCC. Design USB_D+ / USB_D- connection as 90 differential pair. Keep routing short and minimize parasitic capacitance on the SPI lines to preserve signal integrity. Keep routing short and minimize parasitic capacitance on CODEC_CLK line to preserve signal integrity. 2.1.3 Antenna checklist Antenna should have 50 deployment geographical area. impedance, V.S.W.R less than 3:1 (recommended 2:1)on operating bands in Follow the recommendations of the antenna producer for correct antenna installation and deployment

(PCB layout and matching circuitry). Follow the additional guidelines for products marked with the FCC logo (United States only) reported in the chapter 2.2.1.1 and 1.15.3.2 The antenna connected to the ANT pad should have built in DC resistor to ground to get proper antenna detection functionality. The antenna for the Rx diversity connected to the ANT_DIV pin should be carefully separated from the main Tx/Rx antenna connected to the ANT pin to ensure highly uncorrelated receive signals on each antenna. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation. 3G.G2-HW-10002-A1 Advance Information Design-In Page 105 of 160 LISA-U series - System Integration Manual 2.2 Design Guidelines for Layout The following design guidelines must be met for optimal integration of LISA-U series modules on the final application board. 2.2.1 Layout guidelines per pin function This section groups LISA-U series modules pins by signal function and provides a ranking of importance in layout design. Figure 54: LISA-U1 and LISA-U2 series modules pin-out (top view) with ranked importance for layout design 3G.G2-HW-10002-A1 Advance Information Design-In Page 106 of 160 V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GNDUSB_D-USB_D+234567891011121131415161718192021222324252627GNDVCCVCCVCCGNDSPI_MRDYSPI_SRDYSPI_MISOSPI_MOSISPI_SCLKSPK_NGNDSPK_PRSVDGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLI2S_RXDI2S_CLKI2S_TXDI2S_WAMIC_PMIC_N6463626160595857565554655352515049484746454443424140392930313233343536373828GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7574737271706968676676GNDRSVDGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U1 series(Top View)V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GNDUSB_D-USB_D+234567891011121131415161718192021222324252627GNDVCCVCCVCCGNDSPI_MRDY / GPIO14SPI_SRDY / GPIO13SPI_MISO / GPIO12SPI_MOSI / GPIO11SPI_SCLK / GPIO10GPIO9 / I2S1_WAGNDGPIO8 / I2S1_CLKRSVD / CODEC_CLKGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WAGPIO7 / I2S1_TXDGPIO6 / I2S1_RXD6463626160595857565554655352515049484746454443424140392930313233343536373828GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7574737271706968676676GNDGNDGNDGNDGNDGNDANTGNDGNDGND/ RSVDANT_DIVLISA-U2 series(Top View)Very ImportantCareful LayoutCommon PracticeLegend:LISA-U series - System Integration Manual Layout Remarks Very Important Design for 50 See section 2.2.1.1 characteristic impedance. Design for 50 See section 2.2.1.1 characteristic impedance. VCC line should be wide and short. Route away from sensitive analog signals. See section 2.2.1.2 Route USB_D+ and USB_D- as differential lines:

design for 90 See section 2.2.1.3 differential impedance. Avoid coupling with noisy signals. See section 2.2.1.4 Rank Function 1st RF Antenna Main RF input/output Pin(s) ANT RF input for Rx diversity ANT_DIV Very Important 2nd Main DC Supply VCC Very Important 3rd USB Signals USB_D+

USB_D-

Very Important 4th Analog Audio Careful Layout Audio Inputs Audio Outputs 5th Ground MIC_P, MIC_N SPK_P, SPK_N GND Careful Layout Provide proper grounding. See section 2.2.1.5 6th Sensitive Pin:

Careful Layout Backup Voltage Power-On V_BCKP PWR_ON 7th High-speed digital pins:

Careful Layout Avoid coupling with noisy signals. See section 2.2.1.6 Avoid coupling with sensitive signals. See section 2.2.1.7 Common Practice Follow common practice rules for digital pin routing. See section 2.2.1.8 SPI Signals 8th Clock Output Digital pins and supplies:

SIM Card Interface Digital Audio

(If implemented) DDC UART SPI_SCLK, SPI_MISO, SPI_MOSI, SPI_SRDY, SPI_MRDY CODEC_CLK VSIM, SIM_CLK, SIM_IO, SIM_RST I2S_CLK, I2S_RXD, I2S_TXD, I2S_WA I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA SCL, SDA TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR External Reset RESET_N General Purpose I/O GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14 USB detection VUSB_DET Supply for Interfaces V_INT Table 44: Pin list in order of decreasing importance for layout design 2.2.1.1 RF antenna connection The ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) are very critical in layout design. The PCB line must be designed to provide 50 nominal characteristic impedance and minimum loss up to radiating element. Provide proper transition between the ANT pad and the ANT_DIV pad to application board PCB Increase GND keep-out (i.e. clearance) for ANT and ANT_DIV pads to at least 250 m up to adjacent pads metal definition and up to 500 m on the area below the module, as described in Figure 55 3G.G2-HW-10002-A1 Advance Information Design-In Page 107 of 160 LISA-U series - System Integration Manual Add GND keep-out (i.e. clearance) on buried metal layers below ANT and ANT_DIV pads and below any other pad of component present on the RF line, if top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground (see Figure 55 for the description of the GND keep-out area below ANT and ANT_DIV pads) The transmission line up to antenna connector or pad may be a micro strip or a stripline. In any case must be designed to achieve 50 characteristic impedance Microstrip lines are usually easier to implement and the reduced number of layer transitions up to antenna connector simplifies the design and diminishes reflection losses. However, the electromagnetic field extends to the free air interface above the stripline and may interact with other circuitry Buried striplines exhibit better shielding to external and internally generated interferences. They are therefore preferred for sensitive application. In case a stripline is implemented, carefully check that the via pad-stack does not couple with other signals on the crossed and adjacent layers Minimize the transmission line length; the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB The transmission line should not have abrupt change to thickness and spacing to GND, but must be uniform and routed as smoothly as possible The transmission line must be routed in a section of the PCB where minimal interference from noise sources can be expected Route RF transmission line far from other sensitive circuits as it is a source of electromagnetic interference Avoid coupling with VCC routing and analog audio lines Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer Add GND vias around transmission line Ensure no other signals are routed parallel to transmission line, or that other signals cross on adjacent metal layer If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the Coplanar Waveguide model for 50 characteristic impedance calculation Dont route microstrip line below discrete component or other mechanics placed on top layer When terminating transmission line on antenna connector (or antenna pad) it is very important to strictly follow the connector manufacturers recommended layout GND layer under RF connectors and close to buried vias should be cut out in order to remove stray capacitance and thus keep the RF line 50 . In most cases the large active pad of the integrated antenna or antenna connector needs to have a GND keep-out (i.e. clearance) at least on first inner layer to reduce parasitic capacitance to ground. Note that the layout recommendation is not always available from connector manufacturer: e.g. the classical SMA Pin-Through-Hole needs to have GND cleared on all the layers around the central pin up to annular pads of the four GND posts. Check 50 impedance of ANT and ANT_DIV lines Ensure no coupling occurs with other noisy or sensitive signals The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna to ensure that uncorrelated signals are received at each antenna, because signal improvement is dependent on the cross correlation and relative signal strength levels between the two received signals. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation 3G.G2-HW-10002-A1 Advance Information Design-In Page 108 of 160 LISA-U series - System Integration Manual Figure 55: GND keep-out area on top layer around ANT and ANT_DIV pads and on buried layer below ANT and ANT_DIV pads Any RF transmission line on PCB should be designed for 50 characteristic impedance. Ensure no coupling occurs with other noisy or sensitive signals. Additional guidelines for products marked with the FCC logo - United States only LISA-U series modules can only be used with a host antenna circuit trace layout according to these guidelines; a host system designer must follow the guidelines to keep the original Grant of LISA-U series modules. Strict compliance to the layout reference design already approved (described in the following guidelines) is required to ensure that only approved antenna shall be used in the host system. If in a host system there is any difference from the trace layout already approved, it requires a Class II permissive change or a new grant as appropriate as FCC defines. Compliance of this device in all final host configurations is the responsibility of the Grantee. The approved reference design for LISA-U series modules has a structure of 4 layers described in the following. The Layer 1 (top layer, see Figure 56) provides a micro strip line to connect the ANT pin of the LISA-U series module to the antenna connector. The ANT pin of the LISA-U series module must be soldered on the designed pad which is connected to the antenna connector by a micro strip. The characteristics of the micro strip line

(coplanar wave guide) are the following:

Thickness = 0.035 mm Width = 0.26 mm Length = 7.85 mm Gap (signal to GND) = 0.5 mm The micro strip line must be designed to achieve 50 characteristic impedance: the dimensions of the micro strip line must be calculated in a host system according to PCB characteristics provided by PCB manufacturer. 3G.G2-HW-10002-A1 Advance Information Design-In Page 109 of 160 Min. 500 umMin. 250 umTop layerBuried metal layerGND planeMicrostrip50 ohm LISA-U series - System Integration Manual Figure 56: Layer 1 (top layer) of u-blox approved interface board for LISA-U series modules The thickness of the dielectric (FR4 Prepreg 1080) from Layer 1 (top layer) to Layer 2 (inner layer) is 0.27 mm. The Layer 2 (inner layer, described in Figure 57) provides a GND plane. Layer 2 thickness is 0.035 mm. Figure 57: Layer 2 (inner layer) of u-blox approved interface board for LISA-U series modules The dielectric thickness (FR4 Laminate 7628) from Layer 2 (inner layer) to Layer 3 (inner layer) is 0.76 mm. The Layer 3 (inner layer, described in Figure 58) is designed for signals routing and GND plane. Layer 3 thickness is 0.035 mm. 3G.G2-HW-10002-A1 Advance Information Design-In Page 110 of 160 Pad designed for the ANT pinAntenna connectorMicrostrip line LISA-U series - System Integration Manual Figure 58: Layer 3 (inner layer) of u-blox approved interface board for LISA-U series modules The dielectric thickness (FR4 Prepreg 1080) from Layer 3 (inner layer) to Layer 4 (bottom layer) is 0.27 mm. The Layer 4 (bottom layer, described in Figure 59) is designed for signals routing, components placement and GND plane. Layer 4 thickness is 0.035 mm. Figure 59: Layer 4 (bottom layer) of u-blox approved interface board for LISA-U series modules The antenna gain must not exceed the levels reported in the chapter 1.15.3.2 to preserve the original u-

blox FCC ID. The antenna must be installed and operated with a minimum distance of 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Under the requirements of FCC Section 15.212(a)-iv, the module must contain a permanently attached antenna, or contain an unique antenna connector, and be marketed and operated only with specific antenna(s). In accordance with FCC Section 15.203, the antenna should use a unique coupling connector to the approved reference design for LISA-U series modules, to ensure that the design will not be deployed with antenna of different characteristic from the approved type. 3G.G2-HW-10002-A1 Advance Information Design-In Page 111 of 160 LISA-U series - System Integration Manual The use of standard SMA type connector is not permitted, as its standard usage allows easy replacement of the attached antenna. However RP-SMA (Reverse-Polarized-SMA) connector type fulfills the minimum requirements to prevent exchangeability of antenna on the reference design. 2.2.1.2 Main DC supply connection The DC supply of LISA-U series modules is very important for the overall performance and functionality of the integrated product. For detailed description, check the design guidelines in section 1.5.2. Some main characteristics are:

VCC pins are internally connected, but it is recommended to use all the available pins in order to minimize the power loss due to series resistance VCC connection may carry a maximum burst current in the order of 2.5 A. Therefore, it is typically implemented as a wide PCB line with short routing from DC supply (DC-DC regulator, battery pack, etc) The module automatically initiates an emergency shutdown if supply voltage drops below hardware threshold. In addition, reduced supply voltage can set a worst case operation point for RF circuitry that may behave incorrectly. It follows that each voltage drop in the DC supply track will restrict the operating margin at the main DC source output. Therefore, the PCB connection must exhibit a minimum or zero voltage drop. Avoid any series component with Equivalent Series Resistance (ESR) greater than a few milliohms Given the large burst current, VCC line is a source of disturbance for other signals. Therefore route VCC through a PCB area separated from sensitive analog signals. Typically it is good practice to interpose at least one layer of PCB ground between VCC track and other signal routing The VCC supply current supply flows back to main DC source through GND as ground current: provide adequate return path with suitable uninterrupted ground plane to main DC source A tank capacitor with low ESR is often used to smooth current spikes. This is most effective when placed as close as possible to VCC. From main DC source, first connect the capacitor and then VCC. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-DC output and minimize the VCC track length. Otherwise consider using separate capacitors for DC-DC converter and LISA-U series module tank capacitor. Note that the capacitor voltage rating may be adequate to withstand the charger over-voltage if battery-pack is used VCC is directly connected to the RF power amplifiers. Add capacitor in the pF range from VCC to GND along the supply path Since VCC is directly connected to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting to the LISA-U series modules in the worst case The large current generates a magnetic field that is not well isolated by PCB ground layers and which may interact with other analog modules (e.g. VCO) even if placed on opposite side of PCB. In this case route VCC away from other sensitive functional units The typical GSM burst has a periodic nature of approx. 217 Hz, which lies in the audible audio range. Avoid coupling between VCC and audio lines (especially microphone inputs) If VCC is protected by transient voltage suppressor / reverse polarity protection diode to ensure that the voltage maximum ratings are not exceeded, place the protecting device along the path from the DC source toward the LISA-U series module, preferably closer to the DC source (otherwise functionality may be compromised) VCC line should be wide and short. Route away from sensitive analog signals. 3G.G2-HW-10002-A1 Advance Information Design-In Page 112 of 160 LISA-U series - System Integration Manual 2.2.1.3 USB signal The LISA-U series modules include a high-speed USB 2.0 compliant interface with a maximum throughput of 480 Mb/s (see Section 1.9.3). Signals USB_D+ / USB_D- carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. Characteristic impedance of USB_D+ / USB_D- lines is specified by USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Route USB_D+ / USB_D- lines as a differential pair Ensure the differential characteristic impedance is as close as possible to 90 Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area 2.2.1.4 Analog audio (LISA-U120 / LISA-U130 only) Accurate analog audio design is very important to obtain clear and high quality audio. The GSM signal burst has a repetition rate of 217 Hz that lies in the audible range. A careful layout is required to reduce the risk of noise from audio lines due to both VCC burst noise coupling and RF detection. Analog audio is separated in the two paths, 1. Audio Input (uplink path): MIC_P / MIC_N 2. Audio Outputs (downlink path): SPK_P / SPK_N The most sensitive is the uplink path, since the analog input signals are in the microVolts range. Avoid coupling of any noisy signals to microphone input lines It is strongly recommended to route MIC signals away from battery and RF antenna lines. Try to skip fast switching digital lines as well Keep ground separation from other noisy signals. Use an intermediate GND layer or vias wall for coplanar signals MIC_P and MIC_N are sensed differentially within the module. Therefore they should be routed as a differential pair up to the audio signal source Cross other signals lines on adjacent layers with 90 crossing Place bypass capacitor for RF very close to active microphone. The preferred microphone should be designed for GSM applications which typically have internal built-in bypass capacitor for RF very close to active device. If the integrated FET detects the RF burst, the resulting DC level will be in the pass-band of the audio circuitry and cannot be filtered by any other device The bias for an external electret active microphone is not provided by the module. Verify that microphone is properly biased from an external low noise supply and verify that the supply noise is properly filtered Output audio lines have two separated configurations. SPK_P / SPK_N are high level balanced output. They are DC coupled and must be used with a speaker connected in bridge configuration Route SPK_P / SPK_N as differential pair, to reduce differential noise pick-up. The balanced configuration will help reject the common mode noise Consider enlarging PCB lines, to reduce series resistive losses, when the audio output is directly connected to low impedance speaker transducer Use twisted pair cables for balanced audio usage 3G.G2-HW-10002-A1 Advance Information Design-In Page 113 of 160 LISA-U series - System Integration Manual If DC decoupling is required, a large capacitor needs to be used, typically in the microFarad range, depending on the load impedance, in order to not increase the lower cut-off frequency of its High-Pass RC filter response 2.2.1.5 Module grounding Good connection of the module with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module. Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The shielding metal tabs are connected to GND, and are a fundamental part of electrical grounding and thermal heat-sink. Connect them to board solid ground layer, by soldering them on the baseboard using PCB plated through holes connected to GND net If the application board is a multilayer PCB, then it is required to connect together each GND area with complete via stack down to main board ground layer It is recommended to implement one layer of the application board as ground plane Good grounding of GND pads will also ensure thermal heat sink. This is critical during call connection, when the real network commands the module to transmit at maximum power: proper grounding helps prevent module overheating 2.2.1.6 Other sensitive pins A few other pins on the LISA-U series modules requires careful layout. RTC supply (V_BCKP): avoid injecting noise on this voltage domain as it may affect the stability of sleep oscillator Power-On (PWR_ON): is the digital input to switch-on the LISA-U series modules. Ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request 2.2.1.7 High-speed digital pins The following high speed digital pins require careful layout:

Serial Peripheral Interface (SPI): can be used for high speed data transfer (UMTS/HSPA) between the LISA-U series modules and the host processor, with a data rate up to 26 Mb/s (see Section 1.9.3). The high-speed data rate is carried by signals SPI_SCLK, SPI_MISO and SPI_MOSI, while SPI_SRDY and SPI_MRDY behave as handshake signals with relatively low activity Digital Clock Output (CODEC_CLK): can be used to provide a 26 MHz or 13 MHz digital clock to an external audio codec Follow these hints for high speed digital pins layout:

High-speed signals become sources of digital noise, route away from RF and other sensitive analog signals Keep routing short and minimize parasitic capacitance to preserve digital signal integrity 3G.G2-HW-10002-A1 Advance Information Design-In Page 114 of 160 LISA-U series - System Integration Manual 2.2.1.8 Digital pins and supplies External Reset (RESET_N): input for external reset, a logic low voltage will reset the module SIM Card Interface (VSIM, SIM_CLK, SIM_IO, SIM_RST): the SIM layout may be critical if the SIM card is placed far away from the LISA-U series modules or in close proximity to the RF antenna. In the first case the long connection can cause the radiation of some harmonics of the digital data frequency. In the second case the same harmonics can be picked up and create self-interference that can reduce the sensitivity of GSM Receiver channels whose carrier frequency is coincidental with harmonic frequencies. The latter case, placing the RF bypass capacitors, suggested in Figure 21, near the SIM connector will mitigate the problem. In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges: add adequate ESD protection to protect module SIM pins near the SIM connector Digital Audio (I2S_CLK, I2S_RX, I2S_TX, I2S_WA and I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA): the I2S interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs DDC (SCL, SDA): the DDC interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs UART (TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR): the serial interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs General Purpose I/O (GPIOx): the general purpose input/output pins are generally not critical for layout Reserved pins: these pins are reserved for future use. Leave them unconnected on the baseboard USB detection (VUSB_DET): this input will generate an interrupt to the baseband processor for USB detection. The USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host to enable the USB interface of the module Interfaces Supply (V_INT): this supply output is generated by an integrated switching step down converter, used internally to supply the digital interfaces. Because of this, it can be a source of noise: avoid coupling with sensitive signals 3G.G2-HW-10002-A1 Advance Information Design-In Page 115 of 160 LISA-U series - System Integration Manual 2.2.2 Footprint and paste mask The following figure describes the footprint and provides recommendations for the paste mask for LISA-U series modules. These are recommendations only and not specifications. Note that the copper and solder masks have the same size and position. Figure 60: LISA-U series modules suggested footprint and paste mask To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the volume outside of the module by defining the dimensions of the paste mask to form a T-shape (or equivalent) extending beyond the copper mask. The solder paste should have a total thickness of 150 m. The paste mask outline needs to be considered when defining the minimal distance to the next component. The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. The bottom layer of LISA-U1 series modules has one unprotected copper area for GND, shown in Figure 61. The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in Figure 62. Consider No-routing areas for the LISA-U series modules footprint as follows: signal keep-out area on the top layer of the application board, below LISA-U series modules, due to GND opening on module bottom layer (see Figure 61 and Figure 62). 3G.G2-HW-10002-A1 Advance Information Design-In Page 116 of 160 33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]0.8 mm [31.5 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]1.0 mm [39.3 mil]5.7 mm [224.4 mil]33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]1.2 mm [47.2 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]0.9 mm [35.4 mil]5.7 mm [224.4 mil]0.6 mm [23.6 mil]Stencil: 150 m LISA-U series - System Integration Manual Figure 61: Signals keep-out area on the top layer of the application board, below LISA-U1 series modules Figure 62: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 3G.G2-HW-10002-A1 Advance Information Design-In Page 117 of 160 33.2 mm11.85 mm22.4 mm5.3 mm5.25 mm1.4 mm1.0 mmPIN 1LISA-U1 bottom side (through module view)Exposed GND on LISA-U1 module bottom layerSignals keep-out area on application board33.2 mm5.25 mm22.4 mm5.3 mm5.25 mm5.3 mm1.3 mm1.4 mm1.0 mmPIN 1LISA-U2 bottom side (through module view)Exposed GND on LISA-U2 module bottom layerSignals keep-out areas on application board LISA-U series - System Integration Manual 2.2.3 Placement Optimize placement for minimum length of RF line and closer path from DC source for VCC. Make sure that RF and analog circuits are clearly separated from any other digital circuits on the system board. Provide enough clearance between the module and any external part due to solder and paste masks design. Milled edges that are present at module PCB corners, away from module pins metallization, can slightly increase module dimensions from the width and the height described in the mechanical specifications sections of LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]: provide enough clearance between module PCB corners and any other external part mounted on the application board. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the LISA-U series modules: avoid placing temperature sensitive devices (e.g. GPS receiver) close to the module. 3G.G2-HW-10002-A1 Advance Information Design-In Page 118 of 160 LISA-U series - System Integration Manual 2.3 Thermal aspects The operating temperature range is specified in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The most critical condition concerning thermal performance is the uplink transmission at maximum power (data upload or voice call in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks; however the application should be correctly designed to cope with it. During transmission at maximum RF power the LISA-U series modules generate thermal power that can exceed 2 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the number of allocated TX slot and modulation (GMSK or 8PSK) or data rate (WCDMA), transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The Module-to-Ambient thermal resistance (Rth,M-A) of LISA-U series modules mounted on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper in still air conditions ranges between 9 and 12 C/W. The spreading of Rth,M-A depends on the operating condition (e.g. 2G or 3G mode, transmit band): the overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. With this setup, the increase of the module temperature5 referred to idle state initial condition6 is:

around 7C during a voice call at maximum power 19C during GPRS data transfer with 4 TX slots 16C during EDGE data transfer with 4 TX slots up to 25C in UMTS connection at max TX power Case-to-Ambient thermal resistance value will be different for other mechanical deployments of the module, e.g. PCB with different size and characteristics, mechanical shells enclosure, or forced air flow. The increase of thermal dissipation, i.e. reducing the thermal resistance, will decrease the operating temperature for internal circuitry of LISA-U series modules for a given operating ambient temperature. This improves the device long-term reliability for applications operating at high ambient temperature. A few techniques may be used to reduce the thermal resistance in the application:

Forced ventilation air-flow within mechanical enclosure Heat sink attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the wireless module Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete via stack down to main ground layer For example, after the installation of a robust aluminum heat-sink with forced air ventilation on the back of the same application board described above, the Module-to-Ambient thermal resistance is reduced to 1.5 3.5 C/W. The effect of lower Rth,M-A can be seen from the module temperature which now becomes:

around 1.5C above the ambient temperature during a voice call at maximum power 3C during GPRS data transfer with 4 TX slots 2.5C during EDGE data transfer with 4 TX slots 5.5C in UMTS connection at max TX power 5 Temperature is measured by internal sensor of wireless module 6 Steady state thermal equilibrium is assumed. The modules temperature in idle state can be considered equal to ambient temperature 3G.G2-HW-10002-A1 Advance Information Design-In Page 119 of 160 LISA-U series - System Integration Manual 2.4 Antenna guidelines Antenna characteristics are essential for good functionality of the module. Antenna radiating performance has direct impact on the reliability of connections over the Air Interface. A bad termination of the ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) can result in poor performance of the module. The following parameters should be checked:

Item Impedance Frequency Range Recommendations 50 nominal characteristic impedance 824..960 MHz (GSM 850, GSM 900, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1) 824..960 MHz (GSM 850, GSM 900, UMTS B5) 1710..1990 MHz (GSM 1800, GSM 1900, UMTS B2) Depends on the LISA-U series module HW version and on the Mobile Network used. LISA-U100, LISA-U120:

LISA-U110, LISA-U130:

LISA-U200-00:

LISA-U200-01, LISA-U230-01:

824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2, UMTS B4) 824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2) Input Power V.S.W.R Return Loss

>2 W peak

<2:1 recommended, <3:1 acceptable S11<-10 dB recommended, S11<-6 dB acceptable Table 45: General recommendation for GSM antenna The antenna gain shall remain below the levels reported in the chapter 1.15.3.2 to preserve the original u-blox FCC ID. Please note that some 2G and 3G bands are overlapping. This depends on worldwide band allocation for telephony services, where different bands are deployed for different geographical regions. If the LISA-U110, LISA-U130 or LISA-U2 series modules are planned for use on the entire supported bands, then an antenna that supports the 824..960 MHz and the 1710..2170 MHz frequency range should be selected. If the LISA-U100 or LISA-U120 modules are planned for use with the entire range of supported bands, then an antenna that supports the 824..960 MHz and the 1710..1990 MHz frequency range should be selected. Otherwise, for fixed applications in specific geographical region, antenna requirements can be relaxed for non-

deployed frequency bands. Refer to the operating RF frequency bands table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the detailed uplink and downlink frequency ranges of each supported band. LISA-U230 modules provide 2G and 3G dynamic receive diversity (Rx diversity) capability to improve the quality and reliability of the wireless link. This feature can be optionally used connecting a second antenna to the ANT_DIV pin, to receive an RF input signal that is processed by the module to increase the performance. All the antenna guidelines and recommendations reported are applicable also to the Rx diversity antenna design, even if the antenna for the Rx diversity is not used to transmit. GSM antennas are typically available as:

Linear monopole: typical for fixed applications. The antenna extends mostly as a linear element with a dimension comparable to lambda/4 of the lowest frequency of the operating band. Magnetic base may be available. Cable or direct RF connectors are common options. The integration normally requires the fulfillment of some minimum guidelines suggested by antenna manufacturer Patch-like antenna: better suited for integration in compact designs (e.g. mobile phone). These are mostly custom designs where the exact definition of the PCB and product mechanical design is fundamental for tuning of antenna characteristics 3G.G2-HW-10002-A1 Advance Information Design-In Page 120 of 160 LISA-U series - System Integration Manual For integration observe these recommendations:

Ensure 50 antenna termination, minimize the V.S.W.R. or return loss, as this will optimize the electrical performance of the module. See section 2.4.1 Select antenna with best radiating performance. See section 2.4.2 If a cable is used to connect the antenna radiating element to application board, select a short cable with minimum insertion loss. The higher the additional insertion loss due to low quality or long cable, the lower the connectivity Follow the recommendations of the antenna manufacturer for correct installation and deployment Do not include antenna within closed metal case Do not place the main antenna in close vicinity to end user since the emitted radiation in human tissue is limited by S.A.R. regulatory requirements Do not use directivity antenna since the electromagnetic field radiation intensity is limited in some countries Take care of interaction between co-located RF systems since the GSM transmitted power may interact or disturb the performance of companion systems Place antenna far from sensitive analog systems or employ countermeasures to reduce electromagnetic compatibility issues that may arise The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna to ensure uncorrelated signals received at each antenna, because signal improvement is dependent on the cross correlation and relative signal strength levels between the two received signals. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels 2.4.1 Antenna termination The LISA-U series modules are designed to work on a 50 load on all the supported frequency bands. Therefore, to reduce as much as possible performance degradation due to antenna mismatch, the following requirements should be met:

load. However, real antennas have no perfect 50 Measure the antenna termination with a network analyzer: connect the antenna through a coaxial cable to the measurement device, the |S11| indicates which portion of the power is delivered to antenna and which portion is reflected by the antenna back to the module output. A good antenna should have an |S11| below -10 dB over the entire frequency band. Due to miniaturization, mechanical constraints and other design issues, this value will not be achieved. An |S11| value of about -6 dB - (in the worst case) - is acceptable. Figure 63 shows an example of this measurement:

Figure 63: |S11| sample measurement of a penta-band antenna that covers in a small form factor the 4 GSM bands (850 MHz, 900 MHz, 1800 MHz and 1900 MHz) and the UMTS Band I 3G.G2-HW-10002-A1 Advance Information Design-In Page 121 of 160 LISA-U series - System Integration Manual Figure 64 shows comparable measurements performed on a wideband antenna. The termination is better, but the size of the antenna is considerably larger. Figure 64: |S11| sample measurement of a wideband antenna 2.4.2 Antenna radiation An indication of the antennas radiated power can be approximated by measuring the |S21| from a target antenna to the measurement antenna, using a network analyzer with a wideband antenna. Measurements should be done at a fixed distance and orientation, and results compared to measurements performed on a known good antenna. Figure 65 through Figure 66 show measurement results. A wideband log periodic-like antenna was used, and the comparison was done with a half lambda dipole tuned at 900 MHz frequency. The measurements show both the |S11| and |S21| for the penta-band internal antenna and for the wideband antenna. Figure 65: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a penta-band internal antenna (yellow/cyan) The half lambda dipole tuned at 900 MHz is known and has good radiation performance (both for gain and directivity). Then, by comparing the |S21| measurement with antenna under investigation for the frequency where the half dipole is tuned (e.g. marker 3 in Figure 65) it is possible to make a judgment on the antenna under test:

if the performance is similar then the target antenna is good. 3G.G2-HW-10002-A1 Advance Information Design-In Page 122 of 160 LISA-U series - System Integration Manual Figure 66: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a wideband commercial antenna (yellow/cyan) Instead if |S21| values for the tuned dipole are much better than the antenna under evaluation (like for marker 1/2 area of Figure 66, where dipole is 5 dB better), then it can be argued that the radiation of the target antenna

(the wideband dipole in this case) is considerably less. The same procedure should be repeated on other bands with half wavelength dipole re-tuned to the band under investigation. For good antenna radiation performance, antenna dimensions should be comparable to a quarter of the wavelength. Different antenna types can be used for the module, many of them (e.g. patch antennas, monopole) are based on a resonating element that works in combination with a ground plane. The ground plane, ideally infinite, can be reduced down to a minimum size that must be similar to one quarter of the wavelength of the minimum frequency that has to be radiated (transmitted/received). Numerical sample: frequency = 1 GHz wavelength = 30 cm minimum ground plane (or antenna size) = 7.5 cm. Below this size, the antenna efficiency is reduced. 2.4.3 Antenna detection functionality The internal antenna detect circuit is based on ADC measurement at ANT: the RF port is DC coupled to the ADC unit in the baseband chip which injects a DC current (10 A for 128 s) on ANT and measures the resulting DC voltage to evaluate the resistance from ANT pad to GND. The antenna detection is forced by the +UANTR AT command: refer to the u-blox AT Commands Manual [3] for more details on how to access this feature. To achieve antenna detection functionality, use an RF antenna with built-in resistor from ANT signal to GND, or implement an equivalent solution with a circuit between the antenna cable connection and the radiating element as shown in Figure 67. 3G.G2-HW-10002-A1 Advance Information Design-In Page 123 of 160 LISA-U series - System Integration Manual Figure 67: Antenna detection circuit and antenna with diagnostic resistor Examples of components for the antenna detection diagnostic circuit are reported in the following table:

Description Part Number - Manufacturer DC Blocking Capacitor Murata GRM1555C1H220JA01 or equivalent RF Choke Inductor Resistor for Diagnostic Murata LQG15HS68NJ02, LQG15HH68NJ02 or equivalent (Self Resonance Frequency ~1GHz) 15 k 5%, various Manufacturers Table 46: Example of components for the antenna detection diagnostic circuit Please note that the DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 67, the measured DC resistance will always be at the limits of the measurement range (respectively open or short), and there will be no mean to distinguish between a defect on antenna path with similar characteristics

(respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and to avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example:

Consider a GSM antenna with built-in DC load resistor of 15 k . Using the +UANTR AT command, the module reports the resistance value evaluated from ANT connector to GND:

Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected 3G.G2-HW-10002-A1 Advance Information Design-In Page 124 of 160 Application BoardAntenna AssemblyDiagnostic CircuitLISA-U seriesADCCurrent SourceRF ChokeDC BlockingFront-End RF ModuleRF ChokeDC BlockingRadiating ElementZo=50 Resistor for DiagnosticCoaxial Antenna CableANT LISA-U series - System Integration Manual Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit over range report (see u-blox AT Commands Manual [3]) means that that the antenna is not connected or the RF cable is broken Reported values below the measurement range minimum limit (1 k) will highlight a short to GND at antenna or along the RF cable Measurement inside the valid measurement range and outside the expected range may indicate an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method 3G.G2-HW-10002-A1 Advance Information Design-In Page 125 of 160 LISA-U series - System Integration Manual 2.5 ESD precautions 2.5.1 ESD immunity test overview The immunity of the device (i.e. the application board where LISA-U series module is mounted) to the Electrostatic Discharge (ESD) must be certified in compliance to the testing standard CENELEC EN 61000-4-2 [11]

and the radio equipment standards ETSI EN 301 489-1 [12], ETSI EN 301 489-7 [13], ETSI EN 301 489-24 [14], which requirements are summarized in Table 47. The ESD immunity test is performed at the enclosure port, defined by ETSI EN 301 489-1 [12] as the physical boundary through which the electromagnetic field radiates. If the device implements an integral antenna, the enclosure port is seen as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port includes the antenna element and its interconnecting cable surfaces. The applicability of ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489-1 [12]. Applicability of ESD immunity test to the relative device ports or the relative interconnecting cables to auxiliary equipments, depends on device accessible interfaces and manufacturer requirements, as defined by ETSI EN 301 489-1 [12]. Contact discharges are performed at conductive surfaces, while air discharges are performed at insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000-4-2 [11]. For the definition of integral antenna, removable antenna, antenna port, device classification refer to ETSI EN 301 489-1 [12]. The contact and air discharges are defined in CENELEC EN 61000-4-2 [11]. Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration Contact Discharge Air Discharge 4 kV 8 kV Table 47: Electromagnetic Compatibility ESD immunity requirements as defined by standards CENELEC EN 61000-4-2, ETSI EN 301 489-1 V1.8.1, ETSI EN 301 489-7 V1.3.1, ETSI EN 301 489-24 V1.4.1 2.5.2 ESD immunity test of LISA-U series reference design Although electromagnetic compatibility (EMC) certification must be performed by the final application of the radio equipment under test (i.e. the application board where LISA-U series module is mounted), EMC certification (including ESD immunity) have been successfully performed on LISA-U1 series and LISA-U200-00 modules reference design according to CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12], ETSI EN 301 489-7

[13] and ETSI EN 301 489-24 [14] standards. The EMC approved reference design consists of a LISA-U1 series or a LISA-U200-00 module soldered on a motherboard which provides an interface to power supply, SIM card, headset and communication port. An external antenna is connected to an SMA connector provided on the motherboard. Since an external antenna is used, the antenna port can be separated from the enclosure port. The reference design is not enclosed in a box so the enclosure port is not indentified with physical surfaces. Therefore, some test cases cannot be applied. Only the antenna port is identified as accessible for direct ESD exposure. The reference application implements all precautions described in the section 2.5.3. ESD immunity test results and applicability are reported in Table 48 according to test requirements CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12], ETSI EN 301 489-7 [13] and ETSI EN 301 489-24 [14]. 3G.G2-HW-10002-A1 Advance Information Design-In Page 126 of 160 LISA-U series - System Integration Manual Category Application Immunity Level Contact Discharge to coupling planes (indirect contact discharge) Enclosure Contact Discharges to conducted surfaces (direct contact discharge) Enclosure port Contact Discharges to conducted surfaces (direct contact discharge) Antenna port Air Discharge at insulating surfaces Air Discharge at insulating surfaces

(only antenna with completely insulating surface can be used) Enclosure port Antenna port

(only antenna with completely insulating surface can be used)

+2 kV / -2 kV

+4 kV / -4 kV Not Applicable7 Not Applicable8 Not Applicable9

+2 kV /

+4 kV /

+8 kV /

Table 48: Enclosure ESD immunity level (as defined by standards CENELEC EN 61000-4-2, ETSI EN 301 489-1 V1.8.1, ETSI EN 301 489-7 V1.3.1, ETSI EN 301 489-24 V1.4.1) of LISA-U1 series and LISA-U200-00 modules application reference design 7 LISA-U1 series or LISA-U200-00 module mounted on application design:

Not Applicability: EUT with insulating enclosure surface, EUT without enclosure surface Applicability: EUT with conductive enclosure surface 8 LISA-U1 series or LISA-U200-00 module mounted on application design:

Not Applicability: Antenna with insulating surface Applicability: Antenna with conductive surface 9 LISA-U1 series or LISA-U200-00 module mounted on application design:

Applicability: EUT with insulating enclosure surface Not Applicability: EUT with conductive enclosure surface, EUT without enclosure surface 3G.G2-HW-10002-A1 Advance Information Design-In Page 127 of 160 LISA-U series - System Integration Manual 2.5.3 ESD application circuits The application circuits described in this section should be implemented, depending on the application board handling, to satisfy ESD immunity test requirements. These are defined in CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12] and ETSI EN 301 489-7 [13], and performed at the device enclosure in compliance to the category level defined in ETSI EN 301 489-1 [12]. The test requirements are summarized in Table 47. Antenna interface With LISA-U1 series modules, the ANT pin provides ESD immunity up to 500 V (contact and air discharge according to IEC 61000-4-2): higher protection level is required if the line is externally accessible on the device

(i.e. the application board where LISA-U1 series module is mounted). The following precautions are suggested to satisfy ESD immunity test requirements using LISA-U1 series modules:

If the device implements an embedded antenna, the insulating enclosure of the device should provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces With the LISA-U200-00 module, the ANT pin provides ESD immunity up to 1000 V (contact and air discharge according to IEC 61000-4-2): higher protection level is required if the line is externally accessible on the device

(i.e. the application board where LISA-U200-00 module is mounted). The following precautions are suggested for satisfying ESD immunity test requirements using LISA-U200-00 modules:

If the device implements an embedded antenna, the device insulating enclosure should provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces If the device implements an external antenna and the antenna and its connecting cable dont provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces, an external high pass filter, consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil

(Murata LQG15HN39NJ102) should be implemented at the antenna port as described in Figure 68 Antenna detection functionality is not provided when implementing the high pass filter described in Figure 68 and Table 49, as ESD protection for the LISA-U200-00 antenna port. 3G.G2-HW-10002-A1 Advance Information Design-In Page 128 of 160 LISA-U series - System Integration Manual Figure 68: LISA-U200-00 antenna port ESD immunity protection application circuit Reference Description Part Number - Manufacturer C L 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 39 nH Multilayer Chip Inductor L0G 0402 5%

LQG15HN39NJ102 - Murata Table 49: Example of components for LISA-U200-00 antenna port ESD immunity protection application circuit With LISA-U230 modules, the ANT_DIV pin provides ESD immunity up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge: no further precaution to ESD immunity test is needed. RESET_N pin The following precautions are suggested for the RESET_N line of LISA-U series modules, depending on the application board handling, to satisfy ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure An additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure It is recommended to keep the connection line to RESET_N as short as possible Maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the RESET_N pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to accessible point For the RESET_N application circuit description refer to Figure 20 and Table 18 reported in section 1.6.3. 3G.G2-HW-10002-A1 Advance Information Design-In Page 129 of 160 External Antenna EnclosureApplication BoardLISA-U200-00ANTRadiating ElementZo= 50 OhmCoaxial Antenna CableAntenna PortEnclosure PortCL LISA-U series - System Integration Manual SIM interface The following precautions are suggested for LISA-U series modules SIM interface (VSIM, SIM_RST, SIM_IO, SIM_CLK pins), depending on the application board handling, to satisfy ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure It is suggested to use as short as possible connection lines at SIM pins Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if SIM interface pins are externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on each SIM interface line, close to accessible points (i.e. close to the SIM card holder) For the SIM interface application circuit description refer to Figure 21 and Table 21 reported in section 1.8. Other pins and interfaces All the module pins that are externally accessible on the device (i.e. the application board where LISA-U series module is mounted) should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489-1 [12]. Depending on applicability, to satisfy ESD immunity test requirements according to ESD category level, all the module pins that are externally accessible should be protected up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge applied to the enclosure surface. The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the relative pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

USB interface: a very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140 ESD protection device) should be mounted on the USB_D+ and USB_D- lines, close to the accessible points (i.e. close to the USB connector) SPI interface: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on the SPI_MISO, SPI_MOSI, SPI_SCLK, SPI_MRDY, SPI_SRDY lines, close to accessible points CODEC_CLK: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0001) should be mounted on the CODEC_CLK line, close to accessible point Other pins: a general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the relative line, close to accessible point 3G.G2-HW-10002-A1 Advance Information Design-In Page 130 of 160 LISA-U series - System Integration Manual 3 Features description 3.1 Firmware (upgrade) Over AT (FOAT) Not supported by LISA-U1xx-00 modules. 3.1.1 Overview This feature allows upgrading the module Firmware over UART and USB, using AT Commands. AT Command AT+UFWUPD triggers a reboot followed by the upgrade procedure at specified a baud rate

(refer to u-blox AT Commands Manual [3] for more details) The Xmodem-1k protocol is used for downloading the new Firmware image via a terminal application A special boot loader on the module performs firmware installation, security verifications and module reboot Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware download from the Xmodem-1k handshake. After completing the upgrade, the module is reset again and wakes-up in normal boot 3.1.2 FOAT procedure The application processor must proceed in the following way:

Send the AT+UFWUPD command through the UART or over the USB interface, specifying the file type and the desired baud rate Reconfigure the serial communication at the selected baud rate, without flow control with the Xmodem-1k protocol Send the new FW image via Xmodem-1k 3.2 TCP/IP and UDP/IP Via the AT commands its possible to access the TCP/IP and UDP/IP functionalities over the Packet Switched data connection. For more details about AT commands see the u-blox AT Commands Manual [3]. Direct Link mode for TCP and UDP sockets is supported by all LISA-U series modules except LISA-U1xx-00 versions. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interface. 3.2.1 Multiple PDP contexts and sockets Two PDP context types are defined:

external PDP context: IP packets are built by the DTE, the MTs IP instance runs the IP relay function only internal PDP context: the PDP context (relying on the MTs TCP/IP stack) is configured, established and handled via the data connection management packet switched data commands described in u-blox AT commands manual [3]

Multiple PDP contexts are supported. The DTE can access these PDP contexts either alternatively through the physical serial port, or simultaneously through the virtual serial ports of the multiplexer (multiplexing mode MUX), with the following constraints:

Using the MTs embedded TCP/IP stack, only 1 internal PDP context is supported. This IP instance supports up to 7 sockets 3G.G2-HW-10002-A1 Advance Information Features description Page 131 of 160 LISA-U series - System Integration Manual Using only external PDP contexts, it is possible to have at most 3 IP instances (with 3 different IP addresses) simultaneously. If in addition the internal PDP context is used, at most 2 external PDP contexts can be activated Secondary PDP contexts (PDP contexts sharing the IP address of a primary PDP context) are also supported. Traffic Flow Filters for such secondary contexts shall be specified according to 3GPP TS 23.060 [20]. At most 2 secondary PDP contexts can be activated, since the maximum number of PDP contexts, both normal and secondary, is always 3. 3.3 FTP and FTPS Not supported by LISA-U1xx-00 modules. LISA-U series modules support the File Transfer Protocol and Secure File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. For more details about AT commands see u-blox AT Commands Manual [3]. 3.4 HTTP and HTTPS Not supported by LISA-U1xx-00 modules. HTTP and HTTPS clients are implemented in LISA-U series modules. HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation. Up to 4 client contexts can be simultaneously used. For more details about AT commands see the u-blox AT Commands Manual [3]. 3.5 AssistNow clients and GPS integration Not supported by LISA-U200-00 modules. For customers using u-blox GPS receivers, LISA-U series wireless modules feature embedded AssistNow clients. AssistNow A-GPS provides better GPS performance and faster Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [3]). LISA-U series modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox GPS receivers is available via the LISA-U series, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the GPS device power-on/off. This means that GSM/WCDMA and GPS can be controlled through a single serial port from any host processor. 3.6 Jamming Detection Not supported by LISA-U1xx-00 modules. In real network situations modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operators choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operators carriers entitled to give access to the GSM/UMTS service. 3G.G2-HW-10002-A1 Advance Information Features description Page 132 of 160 LISA-U series - System Integration Manual The Jamming Detection Feature detects such artificial interference and reports the start and stop of such conditions to the client, which can react appropriately by e.g. switching off the radio transceiver in order to reduce power consumption and monitoring the environment at constant periods. The feature consists of detecting, at radio resource level, an anomalous source of interference and signaling it to the client with an unsolicited indication when the detection is entered or released. The jamming condition occurs when:

The module has lost synchronization with the serving cell and cannot select any other cell The band scan reveals at least n carriers with power level equal or higher than threshold On all such carriers, no synchronization is possible The number of minimum disturbing carriers and the power level threshold can be configured by the client by using the AT+UCD command [3]. The jamming condition is cleared when any of the above mentioned statements does not hold. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command (for more details refer to the u-blox AT Commands Manual [3]). 3.7 In-Band modem Not supported by LISA-U100, LISA-U110, LISA-U120, LISA-U130-00, LISA-U200-00 modules versions. LISA-U series modules implements the in-Band modem solution for eCall according to the 3GPP TS 26.267 specification [15]. According to the eCall (Pan-European automatic in-vehicle emergency call system) specification, an eCall must be generated automatically or manually following an car accident using GSM cellular service 112. When activated, the in-vehicle eCall system (IVS) creates an emergency call carrying both voice and data (e.g. vehicle GPS position) directly to the nearest 112 Public Safety Answering Point (PSAP) to quickly decide upon detaching rescue services to the known position. Figure 69: In-Band modem diagram flow In-Band modem allows the fast and reliable transmission of vehicle Minimum Set of Data (MSD - 140 bytes) and the establishment of a voice emergency call using the same physical channel (voice channel) without any modifications of the existing cellular network architecture. In-Band modem is a mandatory feature to meet the eCall requirements and to develop in vehicle devices fully supporting eCall. 3.8 Smart Temperature Management Wireless modules independent of the specific model always have a well defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. 3G.G2-HW-10002-A1 Advance Information Features description Page 133 of 160 LISA-U series - System Integration Manual Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/isnt air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. 3.8.1 Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. Please refer to u-blox AT Commands Manual [3] for more details. The wireless module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the wireless module: the measured value could be different from the environmental temperature (Ta). Figure 70: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 70) named t-2, t-1, t+1 and t+2. Within the first limit, (t-1 < Ti < t+1), the wireless module is in the normal working range, the Safe Area In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the wireless module is still inside the valid temperature range, but the measured temperature approaches the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage For security reasons the shutdown is suspended in case an emergency call in progress. In this case the device will switch off at call termination. The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled there is no embedded protection against disallowed temperature conditions. Figure 71 shows the flow diagram implemented in LISA-U series modules for the Smart Temperature Supervisor. 3G.G2-HW-10002-A1 Advance Information Features description Page 134 of 160 Warningareat-1t+1t+2t-2Valid temperature rangeSafeareaDangerousarea Dangerousarea Warningarea LISA-U series - System Integration Manual Figure 71: Smart Temperature Supervisor (STS) flow diagram 3G.G2-HW-10002-A1 Advance Information Features description Page 135 of 160 IF STS enabledRead temperatureIF(t-1<Ti<t+1)IF(t-2<Ti<t+2)Send notification (warning)Send notification(dangerous)WaitemergencycallterminationIFemerg. call in progressShut the device downYesNoYesYesNoNoNoYesSend shutdownnotificationFeature enabled (full logic or indication only)IF Full Logic EnabledFeature disabled: no actionTemperature is within normal operating rangeYesTempetature is within warning areaTempetature is outside valid temperature rangeNoFeatuere enabled in full logic modeFeature enabled in indication only mode:no further actionsSend notification (safe)Previously outside of Safe AreaTempetature is back to safe areaNoNo furtheractionsYes LISA-U series - System Integration Manual 3.8.2 Threshold Definitions When the application of wireless module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the wireless module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat This behavior is partially compensated by the definition of the upper shutdown threshold (t+2) that is slightly higher than the declared environmental temperature limit. The temperature thresholds are defined according the Table 50. Symbol Parameter Temperature Remarks t-2 t-1 t+1 t+2 Low temperature shutdown 40 C Equal to the absolute minimum temperature rating for the wireless module (the lower limit of the extended temperature range) Low temperature warning 30 C 10C above t-2 High temperature warning

+77 C 20C below t+2. The higher warning area for upper range ensures that any countermeasures used to limit the thermal heating will become effective, even considering some thermal inertia of the complete assembly. High temperature shutdown

+97 C Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient temperature Ta in the reference setup (*) equals the absolute maximum the extended temperature range) temperature limit of

(upper rating

(*)LISA-U series module mounted on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper within climatic chamber Table 50: Thresholds definition for Smart Temperature Supervisor on the LISA-U series modules The sensor measures board temperature inside the shields, which can differ from ambient temperature. 3.9 Hybrid positioning and CellLocate Not supported by LISA-U1xx-00 and LISA-U200-00 modules versions. Although GPS is a widespread technology, its reliance on the visibility of extremely weak GPS satellite signals means that positioning is not always possible. Especially difficult environments for GPS are indoors, in enclosed or underground parking garages, as well as in urban canyons where GPS signals are blocked or jammed by multipath interference. The situation can be improved by augmenting GPS receiver data with cellular network information to provide positioning information even when GPS reception is degraded or absent. This additional information can benefit numerous applications. 3.9.1 Positioning through cellular information: CellLocate u-blox CellLocate enables the estimation of device position based on the parameters of the mobile network cells visible to the specific device. To estimate its position the u-blox Wireless module sends the CellLocate server the parameters of network cells visible to it using a UDP connection. In return the server provides the estimated position based on the CellLocate database. The u-blox Wireless module can either send the parameters of the visible home network cells only (normal scan) or the parameters of all surrounding cells of all mobile operators

(deep scan). 3G.G2-HW-10002-A1 Advance Information Features description Page 136 of 160 LISA-U series - System Integration Manual Normal scan is only possible in 2G mode. The CellLocate database is compiled from the position of devices which observed, in the past, a specific cell or set of cells (historical observations) as follows:

1. Several devices reported their position to the CellLocate server when observing a specific cell (the As in the picture represent the position of the devices which observed the same cell A) 2. CellLocate server defines the area of Cell A visibility 3. If a new device reports the observation of Cell A CellLocate is able to provide the estimated position from the area of visibility 3G.G2-HW-10002-A1 Advance Information Features description Page 137 of 160 4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of visibility. LISA-U series - System Integration Manual CellLocate is implemented using a set of two AT commands that allow configuration of the CellLocate service

(AT+ULOCCELL) and requesting position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy. The accuracy of the position estimated by CellLocate depends on the availability of historical observations in the specific area. 3.9.2 Hybrid positioning With u-blox Hybrid positioning technology, u-blox wireless devices can be triggered to provide their current position using either a u-blox GPS receiver or the position estimated from CellLocate. The choice depends on which positioning method provides the best and fastest solution according to the user configuration, exploiting the benefit of having multiple and complementary positioning methods. Hybrid positioning is implemented through a set of three AT commands that allow configuration of the GNSS receiver (AT+ULOCGNSS), configuration of the CellLocate service (AT+ULOCCELL), and requesting the position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy (if the position has been estimated by CellLocate), and additional parameters if the position has been computed by the GNSS receiver. The configuration of mobile network cells does not remain static (e.g. new cells are continuously added or existing cells are reconfigured by the network operators). For this reason, when a Hybrid positioning method has been triggered and the GNSS receiver calculates the position, a database self-learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy. The use of hybrid positioning requires a connection via the DDC (I2C) bus between the LISA-U series wireless module and the u-blox GPS receiver (Refer to chapter 1.10). Refer to GPS Implementation Application Note [17] for the complete description of the feature. u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate server u-blox is unable to track the SIM used or the specific device. 3G.G2-HW-10002-A1 Advance Information Features description Page 138 of 160 LISA-U series - System Integration Manual 4 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 4.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the LISA-U1 series Data Sheet [1], the LISA-U2 series Data Sheet [2] and u-blox Package Information Guide [22]. The LISA-U series modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. 4.2 Soldering 4.2.1 Soldering paste Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature: 217C Stencil Thickness:

150 m for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.2.2 The quality of the solder joints on the connectors (half vias) should meet the appropriate IPC specification. 4.2.2 Reflow soldering A convection type-soldering oven is strongly recommended over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the "IPC-7530 Guidelines for temperature profiling for mass soldering (reflow and wave) processes, published 2001". Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device!

Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. Please note that this preheat phase will not replace prior baking procedures. Temperature rise rate: max 3C/s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping. 3G.G2-HW-10002-A1 Advance Information Handling and soldering Page 139 of 160 LISA-U series - System Integration Manual Time: 60 120 s End Temperature: 150 - 200C If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of 217C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above 217C liquidus temperature: 40 - 60 s Peak reflow temperature: 245C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4C / s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Figure 72: Recommended soldering profile LISA-U series modules must not be soldered with a damp heat process. 3G.G2-HW-10002-A1 Advance Information Handling and soldering Page 140 of 160 PreheatHeatingCooling[C]Peak Temp. 245C[C]250250Liquidus Temperature21721720020040 - 60 sEnd Temp.max 4C/s150 - 200C150150max 3C/s60 - 120 s100Typical Leadfree100Soldering Profile5050Elapsed time [s]LISA-U series - System Integration Manual 4.2.3 Optical inspection After soldering the LISA-U series modules, inspect the modules optically to verify that he module is properly aligned and centered. 4.2.4 Cleaning Cleaning the soldered modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-

jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results use a "no clean" soldering paste and eliminate the cleaning step after the soldering. 4.2.5 Repeated reflow soldering Only a single reflow soldering process is encouraged for boards with a LISA-U series module populated on it. The reason for this is the risk of the module falling off due to high weight in relation to the adhesive properties of the solder. 4.2.6 Wave soldering Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. Only a single wave soldering process is encouraged for boards populated with LISA-U series modules. 4.2.7 Hand soldering Hand soldering is not recommended. 4.2.8 Rework The LISA-U series modules can be unsoldered from the baseboard using a hot air gun. After the module is removed, clean the pads before placing. Avoid overheating the module. Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty. 4.2.9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials affect the HF properties of the LISA-U series modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating. Conformal Coating of the module will void the warranty. 3G.G2-HW-10002-A1 Advance Information Handling and soldering Page 141 of 160 LISA-U series - System Integration Manual 4.2.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the LISA-U series modules before implementing this in the production. Casting will void the warranty. 4.2.11 Grounding metal covers Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interferences and noise. u-blox gives no warranty for damages to the LISA-U series modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. 4.2.12 Use of ultrasonic processes LISA-U series modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding etc.) may cause damage to the module. u-blox gives no warranty against damages to the LISA-U series modules caused by any Ultrasonic Processes. 3G.G2-HW-10002-A1 Advance Information Handling and soldering Page 142 of 160 LISA-U series - System Integration Manual 5 Product Testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested. Defective units are analyzed in detail to improve the production quality. This is achieved with automatic test equipment, which delivers a detailed test report for each unit. The following measurements are done:

Digital self-test (firmware download, Flash firmware verification, IMEI programming) Measurement of voltages and currents Adjustment of ADC measurement interfaces Functional tests (Serial interface communication, analog audio interface, real time clock, battery charger, temperature sensor, antenna detection, SIM card communication) Digital tests (GPIOs, digital interfaces) Measurement and calibration of RF characteristics in all supported bands (Receiver S/N verification, frequency tuning of reference clock, calibration of transmitter and receiver power levels) Verification of RF characteristics after calibration (modulation accuracy, power levels and spectrum performance are checked to be within tolerances when calibration parameters are applied) Figure 73: Automatic test equipment for module tests 5.2 Test parameters for OEM manufacturer Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer doesnt need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. An OEM manufacturer should focus on:

Module assembly on the device; it should be verified that:

o Soldering and handling process did not damaged the module components o All module pins are well soldered on device board o There are no short circuits between pins 3G.G2-HW-10002-A1 Advance Information Product Testing Page 143 of 160 LISA-U series - System Integration Manual Component assembly on the device; it should be verified that:

o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result. Module AT commands are used to perform functional tests (communication with host controller, check SIM card interface, check communication between module and GPS, GPIOs, etc.) and to perform RF performance tests. 5.2.1 Go/No go tests for integrated devices A Go/No go test is to compare the signal quality with a Golden Device in a position with excellent 2G/3G network coverage and after having dialed a call (refer to u-blox AT Commands Manual [3], AT+CSQ command:

<rssi>, <ber> parameters). These kinds of test may be useful as a go/no go test but not for RF performance measurements. This test is suitable to check the communication with host controller and SIM card, the audio and power supply functionality and verify if components at antenna interface are well soldered. 5.2.2 Functional tests providing RF operation Overall RF performance test of the device including antenna can be performed with basic instruments such as a standard spectrum analyzer and signal generator using an AT interface and AT+UTEST command. The AT+UTEST command gives a simple interface to set the module to Rx and Tx test modes ignoring 2G/3G signaling protocol. The command can set the module:

In transmitting mode in a specified channel and power level in all supported modulation schemes (single slot GMSK, single slot 8PSK, WCDMA) and bands 2G, 3G In receiving mode in a specified channel to returns the measured power level in all supported bands 2G, 3G The AT+UTEST command used to perform these functional tests is available on all LISA-U series modules versions except LISA-U1xx-00. Refer to u-blox AT Commands Manual [3], for AT+UTEST command syntax description. Refer to End user test Application Note [21], for AT+UTEST command user guide, limitations and examples of use. 3G.G2-HW-10002-A1 Advance Information Product Testing Page 144 of 160 LISA-U series - System Integration Manual Figure 74: Setup with spectrum analyzer and signal generator for radiated measurement This feature allows the measurement of the transmitter and receiver power levels to check component assembly related to the module antenna interface and to check other device interfaces from which depends the RF performance. To avoid module damage during transmitter test, a proper antenna according to module specifications or a 50 termination must be connected to ANT pin. To avoid module damage during receiver test the maximum power level received at ANT pin must meet module specifications. The AT+UTEST command sets the module to emit RF power ignoring 2G/3G signalling protocol. This emission can generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing purpose in controlled environments by qualified user and must not be used during the normal module operation. Follow instructions suggested in u-blox documentation. u-blox assumes no responsibilities for the inappropriate use of this feature. 3G.G2-HW-10002-A1 Advance Information Product Testing Page 145 of 160 Application BoardLISA-U seriesANTApplication ProcessorAT CommandsWireless AntennaSpectrum AnalyzerINWideband AntennaTXApplication BoardLISA-U seriesANTApplication ProcessorAT CommandsWireless AntennaSignalGeneretorOUTWideband AntennaRX LISA-U series - System Integration Manual Example of production tests for OEM manufacturer:

1. Trigger TX GMSK burst at low Power Control Level (lower than 15) or a RX measure reporting to check:

o o o o o If ANT pin is soldered If ANT pin is in short circuit If module was damaged during soldering process or during handling (ESD, mechanical shock) If antenna matching components on application board are soldered If integrated antenna is correctly connected To avoid module damage during transmitter test when good antenna termination is not guaranteed, use a low Power Control Level (i.e. PCL lower or equal to 15). u-blox assumes no responsibilities for module damaging caused by an inappropriate use of this feature. 2. Trigger TX GMSK burst at maximum PCL:

o To check if the power supply is correctly assembled and is able to deliver the required current 3. Trigger TX GMSK and 8PSK burst and WCDMA signal:

o o To measure current consumption To check if module components was damaged during soldering process or during handling (ESD, mechanical shock,) 4. Trigger RX measurement:

o o To test receiver signal level. Assuming that there are no losses between ANT pin or ANT_DIV pin and input power source, be aware that the power level estimated by the module can vary approximately within 3GPP tolerances for the average value To check if module was damaged during soldering process or during handling (ESD, mechanical shock) 5. Trigger TX GMSK and 8PSK burst and WCDMA signal and RX measurement to check:

o Overall RF performance of the device including antenna measuring TX and RX power levels 3G.G2-HW-10002-A1 Advance Information Product Testing Page 146 of 160 LISA-U series - System Integration Manual Appendix A Migration to LISA-U2 series wireless modules Migrating LISA-U1 series designs to LISA-U2 series modules is a fairly straightforward procedure. Nevertheless there are some points to be considered during the migration. Not all of the functionalities available with LISA-U1 series modules are supported by all LISA-U2 series modules versions. These include:

o Analog Audio Interfaces are not supported by all LISA-U2 series modules o Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00 o Embedded AssistNow Software, GPS via Modem, Hybrid positioning and CellLocate functionalities are supported by all LISA-U2 series modules versions except LISA-U200-00 o In-Band modem is supported by all LISA-U2 series modules versions except LISA-U200-00 A.1 Checklist for migration Have you chosen the optimal module?

For HSDPA category 14, 6-band 3G, Digital Audio Interfaces support, select the LISA-U230-01 version. For HSDPA category 8, 6-band 3G, Digital Audio Interfaces support, select the LISA-U200-01 version. For HSDPA category 8, 4-band 3G support, select the LISA-U200-00 version. Check LISA-U2 series Hardware Requirements Check the supported 3G bands for proper antenna circuit development, since LISA-U2 supports different 3G bands in comparison to LISA-U1 series wireless modules. Check audio requirements, since Analog Audio Interfaces are not supported by LISA-U2 series. Check audio requirements, since Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00. Check the PWR_ON input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the PWR_ON input by an open drain or open collector driver as recommended. Check the PWR_ON behavior, since LISA-U2 can be switched off forcing PWR_ON pin to the low level for at least 1 s. Check the RESET_N input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the RESET_N input by an open drain or open collector driver as recommended. Check the V_BCKP operating characteristics, since they are slightly changed in comparison to LISA-U1 series modules. Check board layout, since additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer. Check section A.3 Hardware migration. 3G.G2-HW-10002-A1 Advance Information Appendix Page 147 of 160 LISA-U series - System Integration Manual Check LISA-U2 series Software Requirements Not all of the functionalities available with LISA-U1 series modules are supported by all the LISA-U2 series modules versions. These include:

o Analog Audio Interfaces are not supported by all LISA-U2 series modules o Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00 o Embedded AssistNow Software, GPS via Modem, Hybrid positioning and CellLocate functionalities are supported by all LISA-U2 series modules versions except LISA-U200-00 o In-band modem is supported by all LISA-U2 series modules versions except LISA-U200-00 Check section A.2 Software migration. A.2 Software migration A.2.1 Software migration from LISA-U1 series to LISA-U2 series wireless modules Software migration from LISA-U1 series to LISA-U2 series wireless modules is a straightforward procedure. Nevertheless there are some differences to be considered with firmware version. Like predecessors, LISA-U2 series wireless module supports AT commands according to 3GPP standards: TS 27.007 [5], TS 27.005 [6], TS 27.010 [7] and the u-blox AT command extension. Backward compatibility has been maintained as far as possible. For the complete list of supported AT commands and their syntax see u-blox AT Commands Manual [3]. A.3 Hardware migration A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series wireless modules LISA-U2 series wireless modules have been designed with backward compatibility in mind but some minor differences were unavoidable. These minor differences will however not be relevant for the majority of the LISA-U1 series designs. Clean and stable supply is required by LISA-U2 as by LISA-U1 series: low ripple and low voltage drop must be guaranteed at VCC pins. The voltage provided has to be within the normal operating range limits to allow module switch-on and has to be above the minimum limit of the extended operating range to avoid module switch-off. Consider that there are large current spikes in connected mode, when a GSM call is enabled. LISA-U2 series provide wider VCC input voltage range compared to LISA-U1 series. The ANT pin has 50 nominal characteristic impedance and must be connected to the antenna through a 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. The antenna and the whole RF circuit must provide optimal radiating characteristics on the entire supported bands: note that LISA-U2 supports different 3G bands in comparison to LISA-U1 series wireless modules. LISA-U230 modules provide the RF antenna input for Rx diversity on the pin 74 (named ANT_DIV): it has an impedance of 50 . The same pad is a reserved pin on LISA-U1 series and LISA-U200 modules. Analog audio interfaces are not supported by LISA-U2 series modules, but a second 4-wire I2S digital audio interface is provided instead of the 4 analog audio pins on all LISA-U2 series modules versions except LISA-U200-00. The same 4 pins can be configured as GPIO on all LISA-U2 series modules versions. 3G.G2-HW-10002-A1 Advance Information Appendix Page 148 of 160 LISA-U series - System Integration Manual Digital audio interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00: the relative pins are configured as pad disabled on LISA-U200-00 version. PWR_ON and RESET_N input voltage thresholds are slightly changed in comparison to LISA-U1 series modules, but this is not relevant driving PWR_ON and RESET_N inputs by open drain / collector drivers as recommended. LISA-U2 series modules can be switched off forcing PWR_ON pin to the low level for at least 1 s. V_BCKP operating characteristics are slightly changed in comparison to LISA-U1 series modules. The 5 pins of the SPI / IPC Serial Interface can be configured as GPIOs on LISA-U2 series modules. LISA-U2 series wireless modules are SMT modules and come in the same compact form factor of LISA-U1 series, featuring Leadless Chip Carrier (LCC) packaging technology. Additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer. Detailed pinout and layout comparisons between LISA-U1 series and LISA-U2 series modules, with remarks for migration, are provided in the subsections A.3.2 and A.3.3. For more information regarding LISA-U1 and LISA-U2 series modules electrical characteristics refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series Figure 75: LISA-U1 series pin assignment Figure 76: LISA-U2 series pin assignment

(highlighted name/function changes) 3G.G2-HW-10002-A1 Advance Information Appendix Page 149 of 160 65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDYSPI_SRDYSPI_MISOSPI_MOSISPI_SCLKRSVD / SPK_NGNDRSVD / SPK_PRSVDGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039RSVD / MIC_PRSVD / MIC_N2829303132333435363738GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7675747372717069686766GNDRSVDGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U1Top View65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDY / GPIO14SPI_SRDY / GPIO13SPI_MISO / GPIO12SPI_MOSI / GPIO11SPI_SCLK / GPIO10GPIO9 / I2S1_WAGNDGPIO8 / I2S1_CLKRSVD / CODEC_CLKGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039GPIO7 / I2S1_TXDGPIO6 / I2S1_RXD2829303132333435363738GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7675747372717069686766GNDRSVD / ANT_DIVGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U2Top View LISA-U1 LISA-U2 LISA-U series - System Integration Manual No Name Description 1 2 GND V_BCKP Ground RTC supply input/output Name GND V_BCKP Ground RTC supply input/output Description Remarks for Migration V_BCKP operating characteristics difference:

LISA-U1:

o V_BCKP output = 2.3V typ. o V_BCKP input = 1.0V min / 2.5V max LISA-U2:

o V_BCKP output = 1.8V typ. o V_BCKP input = 1.0V min / 1.9V max No difference:

V_INT output = 1.8V typ. No difference:

This pin must be connected to GND 3 4 5 6 7 8 9 GND GND GND DSR 10 RI 11 DCD 12 DTR 13 RTS 14 CTS 15 TXD 16 RXD GND V_INT Ground Digital Interfaces supply output GND V_INT Ground Digital Interfaces supply output RSVD RESERVED pin RSVD RESERVED pin Ground Ground Ground UART data set ready output UART ring indicator output UART data carrier detect output UART data terminal ready input UART ready to send input UART clear to send output UART transmitted data input UART received data output GND GND GND DSR RI DCD DTR RTS CTS TXD RXD Ground Ground Ground UART data set ready output No difference:

Circuit 107 (DSR) in ITU-T V.24. UART ring indicator output No difference:

Circuit 125 (RI) in ITU-T V.24. UART data carrier detect output No difference:

Circuit 109 (DCD) in ITU-T V.24. UART data terminal ready input No difference:

Circuit 108/2 (DTR) in ITU-T V. 24. UART ready to send input No difference:

Circuit 105 (RTS) in ITU-T V.24. UART clear to send output No difference:

Circuit 106 (CTS) in ITU-T V.24. UART transmitted data input No difference:

Circuit 103 (TxD) in ITU-T V.24. UART received data output No difference:

Circuit 104 (RxD) in ITU-T V.24. 17 GND Ground GND Ground 18 VUSB_DET USB detect input VUSB_DET USB detect input No difference:

Input for VBUS (5V typical) USB supply sense. 19 PWR_ON Power-on input PWR_ON Power-on input Forcing PWR_ON to the low level for at least 5 ms causes a switch-on of LISA-U1 and LISA-U2. PWR_ON operating voltage difference:

LISA-U1:

o L-level input = -0.30V min / 0.65V max o H-level input = 2.00 min / 4.20V max o External pull-up (e.g. to V_BCKP) required LISA-U2:

o L-level input = -0.30V min / 0.65V max o H-level input = 1.50V min / 4.40V max o External pull-up (e.g. to V_BCKP) required 20 GPIO1 GPIO GPIO1 GPIO Additional feature provided by LISA-U2:

LISA-U2 can be switched-off forcing PWR_ON pin to the low level for at least 1 s. By default, the pin is configured as Pad disabled, and can be alternatively configured to provide the GSM Tx Burst Indication, Network Status Indication or as GPIO Additional features provided by LISA-U2xx-01:

the pin can be alternatively configured to provide Module Status Indication 3G.G2-HW-10002-A1 Advance Information Appendix Page 150 of 160 LISA-U series - System Integration Manual LISA-U1 LISA-U2 No Name Description 21 GPIO2 GPIO Name GPIO2 Description Remarks for Migration GPIO No difference from LISA-U1xx-0x to LISA-U2xx-01:

By default, the pin is configured to provide the GPS Supply Enable function, and can be alternatively configured as GPIO Different configuration on LISA-U200-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO 22 RESET_N External reset input RESET_N External reset input Forcing RESET_N to the low level for at least 50 ms causes a hardware reset of LISA-U1 and LISA-U2. RESET_N operating voltage difference:

Internal 10k pull-up to V_BCKP (2.3V typ) LISA-U1:

o L-level input = -0.30V min / 0.65V max o H-level input = 1.69V min / 2.48V max o LISA-U2:

o L-level input = -0.30V min / 0.51V max o H-level input = 1.32V min / 2.01V max o Internal 10k pull-up to V_BCKP (1.8V typ) 23 GPIO3 GPIO GPIO3 GPIO 24 GPIO4 GPIO GPIO4 GPIO No difference from LISA-U1xx-00 to LISA-U2xx-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO No difference from LISA-U1xx-01 to LISA-U2xx-01:

By default, the pin is configured to provide the GPS Tx Data Ready function, and can be alternatively configured as GPIO. No difference from LISA-U1xx-00 to LISA-U2xx-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO No difference from LISA-U1xx-01 to LISA-U2xx-01:

By default, the pin is configured to provide the GPS RTC sharing (time aiding) function, and can be alternatively configured as GPIO. 25 GND Ground 26 USB_D-

USB Data Line D-

input/output GND USB_D-

Ground USB Data Line D-

input/output 27 USB_D+

USB Data Line D+

input/output USB_D+

USB Data Line D+

input/output No difference:

90 nominal differential impedance. Pull-up/down & series resistors provided internally. No difference:

90 nominal differential impedance. Pull-up/down & series resistors provided internally. 28 GND 29 GND 30 GND 31 GND 32 GND 33 GND 34 GND 35 GND 36 GND 37 GND 38 GND 39 RSVD MIC_N Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio input (neg.) GND GND GND GND GND GND GND GND GND GND GND GPIO6 I2S1_RXD /

GPIO6 Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S receive data input /

GPIO New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as receive data input of the second digital audio interface, and can be alternatively configured as GPIO 3G.G2-HW-10002-A1 Advance Information Appendix Page 151 of 160 LISA-U1 LISA-U2 LISA-U series - System Integration Manual No Name Description 40 RSVD MIC_P 41 RSVD I2S_WA 42 RSVD I2S_TXD 43 RSVD I2S_CLK 44 RSVD I2S_RXD 45 SCL 46 SDA LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio input (pos.) LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S word alignment LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S transmit data output LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S clock LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S receive data input I2C bus clock line output I2C bus data line input/output RSVD I2S_WA RSVD I2S_TXD RSVD I2S_CLK RSVD I2S_RXD SCL SDA Name GPIO7 I2S1_TXD /

GPIO7 Description Remarks for Migration LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S transmit data output /

GPIO New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as transmit data output of the second digital audio interface, and can be alternatively configured as GPIO LISA-U200-00:

RESERVED pin No difference:

Pad disabled on LISA-U200-00. LISA-U200-01, LISA-U230-01:

1st I2S word alignment input/output No difference:

I2S word alignment input/output LISA-U200-00:

RESERVED pin No difference:

Pad disabled on LISA-U200-00. LISA-U200-01, LISA-U230-01:

1st I2S transmit data output LISA-U200-00:

RESERVED pin LISA-U200-01, LISA-U230-01:

1st I2S clock input/output LISA-U200-00:

RESERVED pin LISA-U200-01, LISA-U230-01:

1st I2S receive data input I2C bus clock line output I2C bus data line input/output No difference:

I2S transmit data output No difference:

Pad disabled on LISA-U200-00. No difference:

I2S clock input/output No difference:

Pad disabled on LISA-U200-00. No difference:

I2S receive data input No difference:

Fixed open drain. External pull-up resistor (e.g. to V_INT) required No difference:

Fixed open drain. External pull-up resistor (e.g. to V_INT) required No difference:

3.25 MHz clock frequency for SIM card No difference:

Internal 4.7 k pull-up resistor to VSIM. No difference:

Reset output for SIM card No difference:

VSIM output = 1.80 V typ or 2.90 V typ By default, the pin is configured to provide the SIM card presence detection function. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Operating Mode Indication 47 SIM_CLK SIM clock output SIM_CLK SIM clock output 48 SIM_IO SIM data input/output SIM_IO SIM data input/output 49 SIM_RST SIM reset output SIM_RST SIM reset output 50 VSIM SIM supply output VSIM SIM supply output 51 GPIO5 GPIO GPIO5 GPIO 52 RSVD RESERVED pin RSVD LISA-U200-00:

RESERVED pin No difference:

Pad disabled on LISA-U200-00. 3G.G2-HW-10002-A1 Advance Information Appendix Page 152 of 160 LISA-U series - System Integration Manual LISA-U1 LISA-U2 No Name Description Name Description Remarks for Migration CODEC_CLK 53 RSVD SPK_P 54 RSVD SPK_N LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio output (pos.) LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio output (neg.) 55 SPI_SCLK SPI Serial Clock Input GPIO8 I2S1_CLK /

GPIO8 GPIO9 I2S1_WA /

GPIO9 SPI_SCLK /

GPIO10 LISA-U200-01, LISA-U230-01:

Clock output LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S clock input/output /

GPIO LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S word alignment input/output /

GPIO SPI Serial Clock Input /

GPIO 56 SPI_MOSI SPI Data Line Input SPI_MOSI /

GPIO11 SPI Data Line Input /

GPIO 57 SPI_MISO SPI Data Line Output SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO 58 SPI_SRDY SPI Slave Ready Output SPI_SRDY /

GPIO13 59 SPI_MRDY SPI Master Ready Input SPI_MRDY /

GPIO14 SPI Slave Ready Output /

GPIO SPI Master Ready Input /

GPIO New feature provided by LISA-U2:

Digital clock output for external audio codec New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as clock input/output of the second digital audio interface, and can be alternatively configured as GPIO New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as word alignment input/output of the second digital audio interface, and can be alternatively configured as GPIO SPI / IPC Clock Input (CPOL=0, internal pull-down) by default on LISA-U1 and LISA-U2 Additional features provided by LISA-U200-00:

The pin can be alternatively configured as GPIO Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured as GPIO SPI / IPC Data Line Input, (CPHA=1, internal pull-up) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U200-00:

The pin can be alternatively configured as GPIO Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured as GPIO SPI / IPC Data Line Output (CPHA=1, idle high) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U2:

The pin can be alternatively configured as GPIO SPI / IPC Slave Ready Output (idle low) by default on LISA-U1 and LISA-U2 Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Status Indication SPI / IPC Master Ready Input (Internal pull-down, Idle low) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Operating Mode Indication 60 GND 61 VCC Ground Module supply input GND VCC Ground Module supply input VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max 3G.G2-HW-10002-A1 Advance Information Appendix Page 153 of 160 LISA-U series - System Integration Manual LISA-U1 LISA-U2 No Name Description Name Description Remarks for Migration 62 VCC Module supply input VCC Module supply input 63 VCC Module supply input VCC Module supply input 64 GND 65 GND 66 GND 67 GND 68 ANT Ground Ground Ground Ground RF antenna GND GND GND GND ANT Ground Ground Ground Ground RF input/output for main Tx/Rx antenna VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max RF antenna input/output 50 nominal impedance 3G band support difference:

LISA-U100/U120:

o Band II (1900), Band V (850) LISA-U110/U130:

o Band I (2100), Band VIII (900) LISA-U200:

o Band I (2100), Band II (1900), Band V (850), Band VI (800) LISA-U230:

o Band I (2100), Band II (1900), Band IV (1700), Band V (850), Band VI (800), Band VIII (900) Ground Ground Ground Ground Ground 69 GND 70 GND 71 GND 72 GND 73 GND Ground Ground Ground Ground Ground 74 RSVD RESERVED pin GND GND GND GND GND RSVD ANT_DIV LISA-U200-0x:

RESERVED pin No difference:

Leave unconnected. LISA-U230-01:

RF input for Rx diversity antenna New feature provided by LISA-U2:

RF antenna input for Rx diversity 50 nominal impedance 75 GND 76 GND Ground Ground GND GND Ground Ground Table 51: Pinout comparison LISA-U1 series vs. LISA-U2 series 3G.G2-HW-10002-A1 Advance Information Appendix Page 154 of 160 LISA-U series - System Integration Manual A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series Additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer, as described in Figure 77 and Figure 78. Figure 77: Signals keep-out area on the top layer of the application board, below LISA-U1 series modules Figure 78: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 3G.G2-HW-10002-A1 Advance Information Appendix Page 155 of 160 33.2 mm11.85 mm22.4 mm5.3 mm5.25 mm1.4 mm1.0 mmPIN 1LISA-U1 bottom side (through module view)Exposed GND on LISA-U1 module bottom layerSignals keep-out area on application board33.2 mm5.25 mm22.4 mm5.3 mm5.25 mm5.3 mm1.3 mm1.4 mm1.0 mmPIN 1LISA-U2 bottom side (through module view)Exposed GND on LISA-U2 module bottom layerSignals keep-out areas on application board LISA-U series - System Integration Manual B Glossary ADC AP AT CBCH CS CSD CTS DC DCD DCE DCS DDC DSP DSR DTE DTM DTR EBU EDGE E-GPRS FDD FEM FOAT FTP FTPS GND GPIO GPRS GPS GSM HF HSDPA HTTP HTTPS HW I/Q I2C I2S IP IPC Analog to Digital Converter Application Processor AT Command Interpreter Software Subsystem, or attention Cell Broadcast Channel Coding Scheme Circuit Switched Data Clear To Send Direct Current Data Carrier Detect Data Communication Equipment Digital Cellular System Display Data Channel Digital Signal Processing Data Set Ready Data Terminal Equipment Dual Transfer Mode Data Terminal Ready External Bus Interface Unit Enhanced Data rates for GSM Evolution Enhanced GPRS Frequency Division Duplex Front End Module Firmware Over AT commands File Transfer Protocol FTP Secure Ground General Purpose Input Output General Packet Radio Service Global Positioning System Global System for Mobile Communication Hands-free High Speed Downlink Packet Access HyperText Transfer Protocol Hypertext Transfer Protocol over Secure Socket Layer Hardware In phase and Quadrature Inter-Integrated Circuit Inter IC Sound Internet Protocol Inter Processor Communication 3G.G2-HW-10002-A1 Advance Information Appendix Page 156 of 160 LISA-U series - System Integration Manual LNA MCS NOM PA PBCCH PCM PCS PFM PMU RF RI RTC RTS RXD SAW SIM SMS SMTP SPI SRAM TCP TDMA TXD UART UDP UMTS USB UTRA VC-TCXO WCDMA Low Noise Amplifier Modulation Coding Scheme Network Operating Mode Power Amplifier Packet Broadcast Control Channel Pulse Code Modulation Personal Communications Service Pulse Frequency Modulation Power Management Unit Radio Frequency Ring Indicator Real Time Clock Request To Send RX Data Surface Acoustic Wave Subscriber Identification Module Short Message Service Simple Mail Transfer Protocol Serial Peripheral Interface Static RAM Transmission Control Protocol Time Division Multiple Access TX Data Universal Asynchronous Receiver-Transmitter User Datagram Protocol Universal Mobile Telecommunications System Universal Serial Bus UMTS Terrestrial Radio Access Voltage Controlled - Temperature Compensated Crystal Oscillator Wideband CODE Division Multiple Access 3G.G2-HW-10002-A1 Advance Information Appendix Page 157 of 160 LISA-U series - System Integration Manual Related documents u-blox LISA-U1 series Data Sheet, Docu No 3G.G1-HW-10001 u-blox LISA-U2 series Data Sheet, Docu No 3G.G1-HW-11004 u-blox AT Commands Manual, Docu No WLS-SW-11000 ITU-T Recommendation V.24, 02-2000. List of definitions for interchange circuits between data terminal equipment (DTE) and data circuit-terminating equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en 3GPP TS 27.007 - AT command set for User Equipment (UE) (Release 1999) 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) (Release 1999) 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol (Release 1999) Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/

I2C-Bus Specification Version 2.1 Philips Semiconductors (January 2000), http://www.nxp.com/acrobat_download/literature/9398/39340011_21.pdf RFC3267 - Real-Time Transport Protocol (RTP) Payload Format and File Storage, Format for the Adaptive Multi-Rate (AMR) and Adaptive Multi-Rate Wideband (AMR-WB) Audio Codecs CENELEC EN 61000-4-2 (2001): "Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test". ETSI EN 301 489-1 V1.8.1: Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements ETSI EN 301 489-7 V1.3.1 Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS) ETSI EN 301 489-24 V1.4.1 "Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 24: Specific conditions for IMT-2000 CDMA Direct Spread (UTRA) for Mobile and portable (UE) radio and ancillary equipment"

3GPP TS 26.267 - Technical Specification Group Services and System Aspects; eCall Data Transfer; In-

band modem solution; General description (Release 9) GSM Mux Implementation Application Note, Docu No WLS-CS-11002 GPS Implementation Application Note, Docu No GSM.G1-CS-09007 Firmware Update Application Note, Docu No WLS-CS-11001 SPI Interface application Note, Docu No 3G.G2-CS-11000 3GPP TS 23.060 - Technical Specification Group Services and System Aspects; General Packet Radio Service (GPRS); Service description End user test Application Note, Docu No TBD u-blox Package Information Guide, Docu. No GPS-X-11004

[1]

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[17]

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Some of the above documents can be downloaded from u-blox web-site (http://www.u-blox.com). 3G.G2-HW-10002-A1 Advance Information Related documents Page 158 of 160 LISA-U series - System Integration Manual Revision history Revision Date Name Status / Comments

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1 2 3 A 21/10/2010 sses 11/01/2011 sses 26/04/2011 lpah 07/07/2011 lpah 26/10/2011 sses Initial Release Thickness information added GPIO description improved Update to Advance Information status Update to Preliminary status Changed status to Objective Specification Initial release for LISA-U series From LISA-U1xx-00 system integration manual, added description and integration of LISA-U1xx-01, LISA-U200-00, LISA-U2xx-01 Added notes regarding VCC normal and extended operating ranges Added RTC value reliability as function of V_BCKP voltage value Added recommendation regarding any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence: must be tri-stated to avoid latch-up of circuits and let a proper boot of the module. A1 22/11/2011 sses Update to Advance Information status Updated module behavior during power-off sequence. Added LISA-U200-00 ESD application circuit for antenna port. Added application circuit for the module status indication function. 3G.G2-HW-10002-A1 Advance Information Revision history Page 159 of 160 Contact For complete contact information visit us at www.u-blox.com u-blox Offices North, Central and South America u-blox America, Inc. Phone:

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l e t a r e e c c a

, e t a c n u m m o c

, e t a c o i l LISA-U series 3.75G HSPA / HSPA+

Wireless Modules System Integration Manual Abstract This document describes the features and the system integration of LISA-U1 series HSPA and LISA-U2 series HSPA+ wireless modules. These modules are complete and cost efficient 3.75G solutions offering up to six-band HSDPA/HSUPA and quad-band GSM/EGPRS voice and/or data transmission technology in a compact form factor. www.u-blox.com LISA-U series - System Integration Manual Document Information Title Subtitle LISA-U series 3.75G HSPA / HSPA+

Wireless Modules Document type System Integration Manual Document number 3G.G2-HW-10002-A2 Document status Preliminary Document status information Objective Specification This document contains target values. Revised and supplementary data will be published later. Advance Information Preliminary This document contains data based on early testing. Revised and supplementary data will be published later. This document contains data from product verification. Revised and supplementary data may be published later. Released This document contains the final product specification. This document applies to the following products:

Name Type number Firmware version PCN / IN LISA-U100 LISA-U100-00S-00 LISA-U100-01S-00 LISA-U110 LISA-U110-00S-00 LISA-U110-01S-00 LISA-U120 LISA-U120-00S-00 LISA-U120-01S-00 LISA-U130 LISA-U130-00S-00 LISA-U130-01S-00 LISA-U130-01A-00 LISA-U200 LISA-U200-00S-00 LISA-U200-01S-00 LISA-U230 LISA-U230-01S-00 LISA-U230-01A-00 10.72 11.40 10.72 11.40 10.72 11.40 10.72 11.40 11.40 21.21 TBD TBD TBD 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. 3G.G2-SW-11000 n.a. n.a. n.a. n.a. n.a. n.a. This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They can be downloaded from www.u-blox.com. u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. u-blox reserves all rights to this document and the information contained herein. Reproduction, use or disclosure to third parties without express permission is strictly prohibited. Copyright 2012, u-blox AG. u-blox is a registered trademark of u-blox Holding AG in the EU and other countries. Trademark Notice Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners. 3G.G2-HW-10002-A2 Page 2 of 159 LISA-U series - System Integration Manual Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development. AT Commands Manual: This document provides the description of the supported AT commands by the LISA-U series modules to verify all implemented functionalities. System Integration Manual: This Manual provides hardware design instructions and information on how to set up production and final product tests. Application Note: document provides general design instructions and information that applies to all u-blox Wireless modules. See Section Related documents for a list of Application Notes related to your Wireless Module. How to use this Manual The LISA-U series System Integration Manual provides the necessary information to successfully design in and configure these u-blox wireless modules. This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance. A warning symbol indicates actions that could negatively impact or damage the module. Questions If you have any questions about u-blox Wireless Integration, please:

Read this manual carefully. Contact our information service on the homepage http://www.u-blox.com Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com Technical Support Worldwide Web Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and helpful FAQ can be accessed 24h a day. By E-mail Contact the nearest of the Technical Support offices by email. Use our service pool email addresses rather than any personal email address of our staff. This makes sure that your request is processed as soon as possible. You will find the contact details at the end of the document. Helpful Information when Contacting Technical Support When contacting Technical Support please have the following information ready:

Module type (e.g. LISA-U100) and firmware version Module configuration Clear description of your question or the problem A short description of the application Your complete contact details 3G.G2-HW-10002-A2 Preliminary Preface Page 3 of 159 LISA-U series - System Integration Manual Contents Preface ................................................................................................................................ 3 Contents .............................................................................................................................. 4 1.6 1.7 1.8 1.2.1 1.2.2 1 System description ....................................................................................................... 7 1.1 Overview .............................................................................................................................................. 7 1.2 Architecture .......................................................................................................................................... 9 Functional blocks ......................................................................................................................... 10 Hardware differences between LISA-U series modules ................................................................. 12 Pin-out ............................................................................................................................................... 13 1.3 1.4 Operating modes ................................................................................................................................ 17 Power management ........................................................................................................................... 19 1.5 1.5.1 Power supply circuit overview ...................................................................................................... 19 1.5.2 Module supply (VCC) .................................................................................................................. 20 Current consumption profiles ...................................................................................................... 28 1.5.3 RTC Supply (V_BCKP) .................................................................................................................. 32 1.5.4 1.5.5 Interface supply (V_INT) ............................................................................................................... 34 System functions ................................................................................................................................ 35 1.6.1 Module power-on ....................................................................................................................... 35 1.6.2 Module power-off ....................................................................................................................... 39 1.6.3 Module reset ............................................................................................................................... 40 RF connection ..................................................................................................................................... 42

(U)SIM interface .................................................................................................................................. 42

(U)SIM functionality ..................................................................................................................... 44 Serial communication ......................................................................................................................... 45 Serial interfaces configuration ..................................................................................................... 45 1.9.1 Asynchronous serial interface (UART)........................................................................................... 46 1.9.2 USB interface............................................................................................................................... 61 1.9.3 1.9.4 SPI interface ................................................................................................................................ 64 1.9.5 MUX Protocol (3GPP 27.010) ...................................................................................................... 68 DDC (I2C) interface .......................................................................................................................... 69 1.10.1 Overview ..................................................................................................................................... 69 1.10.2 DDC application circuit ................................................................................................................ 69 Audio Interface ............................................................................................................................... 74 1.11.1 Analog Audio interface ............................................................................................................... 74 1.11.2 Digital Audio interface ................................................................................................................. 80 1.11.3 Voiceband processing system ...................................................................................................... 85 General Purpose Input/Output (GPIO) ............................................................................................. 87 Reserved pins (RSVD) ...................................................................................................................... 96 Schematic for LISA-U series module integration .............................................................................. 97 Approvals ........................................................................................................................................ 99 1.12 1.13 1.14 1.15 1.8.1 1.10 1.11 1.9 3G.G2-HW-10002-A2 Preliminary Contents Page 4 of 159 LISA-U series - System Integration Manual 1.15.1 R&TTED and European Conformance CE mark ............................................................................ 99 IC .............................................................................................................................................. 100 1.15.2 1.15.3 Federal communications commission notice .............................................................................. 100 1.15.4 a-tick AUS Certification ............................................................................................................. 102 2.2 2.1 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 2 Design-In ................................................................................................................... 103 Design-in checklist ............................................................................................................................ 103 Schematic checklist ................................................................................................................... 103 Layout checklist ......................................................................................................................... 104 Antenna checklist ...................................................................................................................... 104 Design Guidelines for Layout ............................................................................................................ 105 Layout guidelines per pin function ............................................................................................. 105 Footprint and paste mask .......................................................................................................... 115 Placement ................................................................................................................................. 117 Thermal aspects ................................................................................................................................ 118 Antenna guidelines ........................................................................................................................... 119 Antenna termination ................................................................................................................. 120 Antenna radiation ..................................................................................................................... 121 Antenna detection functionality ................................................................................................ 122 ESD precautions ................................................................................................................................ 125 ESD immunity test overview ...................................................................................................... 125 ESD immunity test of LISA-U series reference design.................................................................. 125 ESD application circuits .............................................................................................................. 127 2.5.1 2.5.2 2.5.3 2.4.1 2.4.2 2.4.3 2.3 2.4 2.5 3.2 3.1 3.1.1 3.1.2 3 Features description ................................................................................................. 130 Firmware (upgrade) Over AT (FOAT) ................................................................................................. 130 Overview ................................................................................................................................... 130 FOAT procedure ........................................................................................................................ 130 TCP/IP and UDP/IP ............................................................................................................................. 130 3.2.1 Multiple PDP contexts and sockets............................................................................................. 130 FTP and FTPS .................................................................................................................................... 131 HTTP and HTTPS ............................................................................................................................... 131 AssistNow clients and GPS integration .............................................................................................. 131 Jamming Detection ........................................................................................................................... 131 In-Band modem ................................................................................................................................ 132 Smart Temperature Management ..................................................................................................... 132 Smart Temperature Supervisor (STS) .......................................................................................... 133 Threshold Definitions ................................................................................................................. 135 Hybrid positioning and CellLocate ..................................................................................................... 135 Positioning through cellular information: CellLocate .................................................................. 135 Hybrid positioning ..................................................................................................................... 137 3.3 3.4 3.5 3.6 3.7 3.8 3.8.1 3.8.2 3.9.1 3.9.2 3.9 4 Handling and soldering ........................................................................................... 138 Packaging, shipping, storage and moisture preconditioning ............................................................. 138 Soldering .......................................................................................................................................... 138 4.1 4.2 3G.G2-HW-10002-A2 Preliminary Contents Page 5 of 159 LISA-U series - System Integration Manual Soldering paste.......................................................................................................................... 138 4.2.1 Reflow soldering ....................................................................................................................... 138 4.2.2 Optical inspection ...................................................................................................................... 140 4.2.3 Cleaning .................................................................................................................................... 140 4.2.4 4.2.5 Repeated reflow soldering ......................................................................................................... 140 4.2.6 Wave soldering.......................................................................................................................... 140 Hand soldering .......................................................................................................................... 140 4.2.7 Rework ...................................................................................................................................... 140 4.2.8 4.2.9 Conformal coating .................................................................................................................... 140 4.2.10 Casting ...................................................................................................................................... 141 4.2.11 Grounding metal covers ............................................................................................................ 141 4.2.12 Use of ultrasonic processes ........................................................................................................ 141 5.1 5.2 5 Product Testing......................................................................................................... 142 u-blox in-series production test ......................................................................................................... 142 Test parameters for OEM manufacturer ............................................................................................ 142 Go/No go tests for integrated devices ...................................................................................... 143 Functional tests providing RF operation ..................................................................................... 143 5.2.1 5.2.2 Appendix ........................................................................................................................ 146 A.2.1 A Migration to LISA-U2 series wireless modules ....................................................... 146 A.1 Checklist for migration ..................................................................................................................... 146 A.2 Software migration ........................................................................................................................... 147 Software migration from LISA-U1 series to LISA-U2 series wireless modules .............................. 147 A.3 Hardware migration.......................................................................................................................... 147 Hardware migration from LISA-U1 series to LISA-U2 series wireless modules ............................. 147 Pin-out comparison LISA-U1 series vs. LISA-U2 series ................................................................. 148 Layout comparison LISA-U1 series vs. LISA-U2 series .................................................................. 154 A.3.1 A.3.2 A.3.3 B Glossary .................................................................................................................... 155 Related documents......................................................................................................... 157 Revision history .............................................................................................................. 158 Contact ............................................................................................................................ 159 3G.G2-HW-10002-A2 Preliminary Contents Page 6 of 159 LISA-U series - System Integration Manual 1 System description 1.1 Overview LISA-U series wireless modules integrate full-feature 3G UMTS/HSxPA and 2G GSM/GPRS/EDGE protocol stack with Assisted GPS support. These SMT modules come in the compact LISA form factor, featuring Leadless Chip Carrier (LCC) packaging technology. 3G UMTS/HSDPA/HSUPA Characteristics 2G GSM/GPRS/EDGE Characteristics Class A User Equipment1 UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD) 3GPP Release 6 High Speed Packet Access (HSPA) for LISA-U1 series 3GPP Release 7 Evolved High Speed Packet Access (HSPA+) for LISA-U2 series Rx Diversity for LISA-U230 Band II (1900 MHz), Band V (850 MHz) 2-band support for LISA-U100, LISA-U120:

2-band support for LISA-U110, LISA-U130:

4-band support for LISA-U200-00:

Band I (2100 MHz), Band VIII (900 MHz) Band I (2100 MHz), Band II (1900 MHz), Band V (850 MHz), Band VI (800 MHz) 6-band support for LISA-U200-01, LISA-U230:

Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) WCDMA/HSDPA/HSUPA Power Class Power Class 3 (24 dBm) for WCDMA/HSDPA/HSUPA mode PS (Packet Switched) Data Rate HSUPA category 6, up to 5.76 Mb/s UL HSDPA category 8 up to 7.2 Mb/s DL for LISA-U1 series, LISA-U200 HSDPA category 14 up to 21.1 Mb/s DL for LISA-U230 WCDMA PS data up to 384 kb/s DL/UL Class B Mobile Station2 GSM EDGE Radio Access (GERA) 3GPP Release 6 for LISA-U1 series 3GPP Release 7 for LISA-U2 series Rx Diversity for LISA-U230 4-band support GSM 850 MHz, E-GSM 900 MHz, DCS 1800 MHz, PCS 1900 MHz Power Class 4 (33 dBm) for GSM/E-GSM bands Power Class 1 (30 dBm) for DCS/PCS bands GSM/GPRS Power Class EDGE Power Class Power Class E2 (27 dBm) for GSM/E-GSM bands Power Class E2 (26 dBm) for DCS/PCS bands PS (Packet Switched) Data Rate GPRS multislot class 334, coding scheme CS1-CS4, up to 107 kb/s DL, 85.6 kb/s UL for LISA-U2 series GPRS multislot class 124, coding scheme CS1-CS4, up to 85.6 kb/s DL/UL for LISA-U1 for LISA-U1 series EDGE multislot class 333, coding scheme MCS1-MCS9, up to 296 kb/s DL, 236.8 kb/s UL for LISA-U2 EDGE multislot class 124, coding scheme MCS1-MCS9, up to 236.8 kb/s DL/UL for LISA-U1 CS (Circuit Switched) Data Rate WCDMA CS data up to 64 kb/s DL/UL CS (Circuit Switched) Data Rate GSM CS data up to 9.6 kb/s DL/UL supported in transparent/non transparent mode Table 1: LISA-U series UMTS/HSDPA/HSUPA and GSM/GPRS/EDGE characteristics Operation modes I to III are supported on GSM/GPRS network, with user-defined preferred service selectable from GSM to GPRS. Paging messages for GSM calls can be optionally monitored during GPRS data transfer in not-coordinating NOM II-III. 1 Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active without any interruption in service. 2 Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. If for example during data transmission an incoming call occurs, the data connection is suspended to allow the voice communication. Once the voice call has terminated, the data service is resumed. 3 GPRS/EDGE multislot class 33 implies a maximum of 5 slots in DL (reception) and 4 slots in UL (transmission) with 6 slots in total. 4 GPRS/EDGE multislot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total. 3G.G2-HW-10002-A2 Preliminary System description Page 7 of 159 LISA-U series - System Integration Manual Direct Link mode is supported for TCP / UDP sockets except for LISA-U1xx-00 module versions. Regarding 3G transmit and receive data rate capability, LISA-U series modules implement 3G High-Speed Uplink Packet Access (HSUPA) category 6, LISA-U1 series and LISA-U200 modules implement 3G High Speed Downlink Packet Access (HSDPA) category 8, while LISA-U230 modules implement the 3G HSDPA category 14. HSUPA and HSDPA categories determine the maximum speed at which data can be respectively transmitted and received:

higher categories allowing faster data transfer rates as indicated in Table 1. The 3G network automatically performs adaptive coding and modulation using a choice of forward error correction code rate and choice of modulation type, to achieve the highest possible data rate and data transmission robustness according to the quality of the radio channel. Regarding 2G transmit and receive data rate capability, LISA-U1 series modules implement GPRS/EGPRS class 12, while LISA-U2 series modules implement GPRS/EGPRS class 33. GPRS and EGPRS classes determine the maximum number of timeslots available for upload and download and thus the speed at which data can be transmitted and received: higher classes typically allowing faster data transfer rates as indicated in Table 1. The 2G network automatically configures the number of timeslots used for reception or transmission (voice calls take precedence over GPRS/EGPRS traffic) and channel encoding (from Coding Scheme 1 up to Modulation and Coding Scheme 9), performing link adaptation to achieve the highest possible data rate. A summary of interfaces and features provided by LISA-U series modules is described in the Table 2. Note that LISA-U130-01 and LISA-U230-01 are available in standard and automotive quality grade versions. Module Technology Bands Interface Audio Functions

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A P U S H A P D S H LISA-U100-00 5.76 7.2 850/1900 LISA-U100-01 5.76 7.2 850/1900 LISA-U110-00 5.76 7.2 900/2100 LISA-U110-01 5.76 7.2 900/2100 LISA-U120-00 5.76 7.2 850/1900 LISA-U120-01 5.76 7.2 850/1900 LISA-U130-00 5.76 7.2 900/2100 LISA-U130-01 5.76 7.2 900/2100 S P G x o b

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1900/2100 800/850/900/

1700/1900/2100 800/850/900/

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e l i f o r P s s e c c A M S I e t a c o L l l e C y t i s r e v d i x R 2 i o d u A g o a n A l 1 1 1 1 3G.G2-HW-10002-A2 Preliminary System description Page 8 of 159 LISA-U series - System Integration Manual 1.2 Architecture Figure 1: LISA-U1 series block diagram (for available options refer to the product features summary in Table 2) Figure 2: LISA-U2 series block diagram (for available options refer to the product features summary in Table 2) 3G.G2-HW-10002-A2 Preliminary System description Page 9 of 159 WirelessBase-bandProcessorMemoryPower Management UnitRF Transceiver26 MHz32.768 kHzSAWFilterFEM & 2G PAANTLNA3G PALNA3G PADDC (for GPS)(U)SIM CardUARTSPIUSBGPIO(s)Power OnExternal ResetV_BCKP (RTC)Vcc (Supply)V_INT (I/O)Digital Audio (I2S)AnalogAudioWirelessBase-bandProcessorMemoryPower Management Unit26 MHz32.768 kHzANTSwitch & Multi band & mode PADDC (for GPS)(U)SIM CardUARTSPIUSBGPIO(s)Power OnExternal ResetV_BCKP (RTC)Vcc (Supply)V_INT (I/O)Digital Audio (I2S)RFSWITCHRF TransceiverDuplexers& FiltersANT_DIVRFSWITCHFilterBankPA PMUTransceiver PMU LISA-U series - System Integration Manual 1.2.1 Functional blocks LISA-U series modules consist of the following internal functional blocks: RF section, Baseband and Power Management Unit section. LISA-U1 series RF section A shielding box includes the RF high-power signal circuitry, namely:

Front-End Module (FEM) with integrated quad-band 2G Power Amplifier and antenna switch multiplexer Two single-band 3G HSPA/WCDMA Power Amplifier modules with integrated duplexers The RF antenna pad (ANT) is directly connected to the FEM, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied to integrated SAW filters for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the 2G power amplifier module and then directed to the antenna through the FEM. The 3G transmitter and receiver are instead active at the same time due to frequency-domain duplex operation. The switch integrated in the FEM connects the antenna port to the passive duplexer which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the fixed gain linear power amplifier. In the same shielding box that includes the RF high-power signal circuitry there are all the low-level analog RF components, namely:

Dual-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO) Low Noise Amplifier (LNA) and SAW RF filters for 2G and 3G receivers While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the external LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing. For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted. In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal. The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode. LISA-U2 series RF section A shielding box contains the RF high-power signal circuitry, including:

Multimode Single Chain Power Amplifier Module used for 3G HSPA/WCDMA and 2G EDGE/GSM operations Power Management Unit with integrated DC/DC converter for the Power Amplifier Module The RF antenna pad (ANT) is directly connected to the main antenna switch, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active Receiver (RX) slot is applied by the main antenna switch to the duplexer SAW filter bank for out-of-band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the power amplifier and then directed to the antenna pad through the main antenna switch. The 3G transmitter and receiver are active at the same time due to frequency-

domain duplex operation. The switch integrated in the main antenna switch connects the antenna port to the duplexer SAW filter bank which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the power amplifier. 3G.G2-HW-10002-A2 Preliminary System description Page 10 of 159 LISA-U series - System Integration Manual A separated shielding box contains all the other analog RF components, including:

Main Antenna Switch Duplexer SAW filter bank Antenna Switch for diversity receiver SAW filter bank for diversity receiver Six-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver Power Management Unit with integrated DC/DC converter for the Power Amplifier Module Voltage Controlled Temperature Compensated 26 MHz Crystal Oscillator (VC-TCXO) While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the integrated LNA enhances the RX sensitivity while discrete inter-stage SAW filters additionally improve the rejection of out-of-band blockers. An internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing. For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to the baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted. The RF antenna pad for the diversity receiver (ANT_DIV) available on LISA-U230 modules is directly connected to the antenna switch for the diversity receiver, which dispatches the incoming RF signals to the dedicated SAW filter bank for out-of-band rejection and then to the diversity receiver port of the RF transceiver. In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage controlled oscillator are used to generate the local oscillator signal. The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode. LISA-U series modulation techniques Modulation techniques related to radio technologies supported by LISA-U series modules, are listed as follows:

GSM GPRS EDGE GSMK GMSK GMSK / 8-PSK WCDMA QPSK HSDPA QPSK / 16-QAM HSUPA QPSK / 16-QAM LISA-U series Baseband and Power Management Unit section Another shielding box of LISA-U series modules includes all the digital circuitry and the power supplies, basically the following functional blocks:

Wireless baseband processor, a mixed signal ASIC which integrates:

Microprocessor for controller functions, 2G & 3G upper layer software DSP core for 2G Layer 1 and audio processing 3G coprocessor and HW accelerator for 3G Layer 1 control software and routines Dedicated HW for interfaces management Memory system in a Multi-Chip Package (MCP) integrating two devices:

NOR flash non-volatile memory DDR SRAM volatile memory Power Management Unit (PMU), used to derive all the system supply voltages from the module supply VCC 3G.G2-HW-10002-A2 Preliminary System description Page 11 of 159 LISA-U series - System Integration Manual 32.768 kHz crystal, connected to the Real Time Clock (RTC) oscillator to provide the clock reference in idle or power-off mode 1.2.2 Hardware differences between LISA-U series modules Main hardware differences between the LISA-U series modules are summarized in Table 3. Characteristic LISA-U1 series LISA-U2 series 3G bands Band II (1900 MHz), Band V (850 MHz) LISA-U100, LISA-U120:

LISA-U110, LISA-U130:

Band I (2100 MHz), Band VIII (900 MHz) HSDPA data rate LISA-U1 series:

HSDPA category 8, up to 7.2 Mb/s DL LISA-U200-00:

Band I (2100 MHz), Band II (1900 MHz), Band V (850 MHz), Band VI (800 MHz) LISA-U200-01, LISA-U230:

Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) LISA-U200:

LISA-U230:

HSDPA category 8, up to 7.2 Mb/s DL HSDPA category 14, up to 21.1 Mb/s DL EDGE/GPRS data rate EDGE multislot class 12, MCS1-MCS9, up to 236.8 kb/s DL/UL GPRS multislot class 12, CS1-CS4, up to 85.6 kb/s DL/UL EDGE multislot class 33, MCS1-MCS9, up to 296 kb/s DL, 236.8 kb/s UL GPRS multislot class 33, CS1-CS4, up to 107 kb/s DL, 85.6 kb/s UL Rx diversity LISA-U1 series:

Not supported Not supported LISA-U200:

LISA-U230:

Supported: ANT_DIV RF input for Rx diversity Analog audio Digital audio Not supported LISA-U100, LISA-U110:

LISA-U120, LISA-U130:

One differential input, one differential output LISA-U2 series:

Not supported Not supported LISA-U100, LISA-U110:

LISA-U120, LISA-U130:

One 4-wire digital audio interface Not supported LISA-U200-00:

LISA-U200-01, LISA-U230:

Two 4-wire digital audio interfaces CODEC_CLK clock output for external codec GPIO 5 GPIOs Up to 14 GPIOs VCC operating range VCC normal operating range: 3.4 V 4.2 V VCC extended operating range: 3.1 V 4.2 V VCC normal operating range: 3.3 V 4.4 V VCC extended operating range: 3.1 V 4.5 V V_BCKP operating range V_BCKP output: 2.3 V typ. V_BCKP input: 1.0 V 2.5 V V_BCKP output: 1.8 V typ. V_BCKP input: 1.0 V 1.9 V Exposed GND area One signals keep-out area on the top layer of the application board, due to one exposed GND area on the bottom layer of the module (see Figure 61) Two signals keep-out areas on the top layer of the application board, due to two exposed GND areas on the bottom layer of the module (see Figure 62) Table 3: Main hardware differences between LISA-U series modules For additional details and minor hardware differences between the LISA-U series modules, refer to section A.3. 3G.G2-HW-10002-A2 Preliminary System description Page 12 of 159 LISA-U series - System Integration Manual 1.3 Pin-out Table 4 lists the pin-out of the LISA-U series modules, with pins grouped by function. Function Pin Module No I/O Description Remarks Power VCC All 61, 62, 63 I Module supply input Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided has to be always above the minimum limit of the operating range. Consider that there are large current spikes in connected mode, when a GSM call is enabled. VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize power loss due to series resistance. See section 1.5.2 GND pins are internally connected but a good

(low impedance) external ground connection can improve RF performance: all GND pins must be externally connected to ground. N/A Ground I/O O O I/O Real Time Clock supply input/output Digital Interfaces supply output SIM supply output RF input/output for main Tx/Rx antenna V_BCKP = 2.3 V (typical) on LISA-U1 series V_BCKP = 1.8 V (typical) on LISA-U2 series generated by the module when VCC supply voltage is within valid operating range. See section 1.5.4 V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. See section 1.5.5 VSIM = 1.80 V typical or 2.90 V typical generated by the module according to the SIM card type. See section 1.8 nominal impedance. 50 See section 1.7, section 2.4 and section 2.2.1.1 GND All V_BCKP All V_INT All VSIM All RF ANT All 1, 3, 6, 7, 8, 17, 25, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 60, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76 2 4 50 68 ANT_DIV LISA-U230 74 I RF input for Rx diversity antenna 50 nominal impedance See section 1.7, section 2.4 and section 2.2.1.1 SIM SIM_IO All SIM_CLK SIM_RST All All SPI SPI_MISO All 48 47 49 57 I/O SIM data O O O SIM clock SIM reset SPI Data Line Output SPI_MOSI All 56 I SPI Data Line Input Internal 4.7 k pull-up to VSIM. Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 Module Output: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. See section 1.9.4 Module Input: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.4 3G.G2-HW-10002-A2 Preliminary System description Page 13 of 159 Function Pin Module SPI_SCLK All SPI_SRDY All SPI_MRDY All DDC SCL SDA UART RxD All All All No 55 58 59 45 46 16 LISA-U series - System Integration Manual I/O Description Remarks I O I SPI Serial Clock Input SPI Slave Ready Output SPI Master Ready Input Module Input: module runs as an SPI slave. Idle low (CPOL=0). Internal active pull-down to GND enabled. See section 1.9.4 Module Output: module runs as an SPI slave. Idle low. See section 1.9.4 Module Input: module runs as an SPI slave. Idle low. Internal active pull- down to GND enabled. See section 1.9.4 O I2C bus clock line Fixed open drain. External pull-up required. See section 1.10 I/O I2C bus data line O UART data output Fixed open drain. External pull-up required. See section 1.10 Circuit 104 (RxD) in ITU-T V.24. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 103 (TxD) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 106 (CTS) in ITU-T V.24. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 TxD All 15 I UART data input CTS All 14 O RTS All 13 I UART clear to send output UART ready to send input DSR RI DTR DCD GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 All All All All All All All All All LISA-U2 LISA-U2 LISA-U2 LISA-U2 LISA-U200-01 LISA-U230 9 10 12 11 20 21 23 24 51 39 40 53 54 55 O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O UART data set ready output Circuit 107 (DSR) in ITU-T V.24. See section 1.9.2 UART ring indicator output Circuit 125 (RI) in ITU-T V.24. See section 1.9.2 UART data terminal ready input Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.2 UART data carrier detect output Circuit 109 (DCD) in ITU-T V.24. See section 1.9.2 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 3G.G2-HW-10002-A2 Preliminary System description Page 14 of 159 GPIO Function Pin Module GPIO11 GPIO12 GPIO13 GPIO14 LISA-U200-01 LISA-U230 LISA-U200-01 LISA-U230 LISA-U200-01 LISA-U230 LISA-U200-01 LISA-U230 USB VUSB_DET All No 56 57 58 59 18 LISA-U series - System Integration Manual I/O I/O Description Remarks GPIO See section 1.12 I/O GPIO See section 1.12 I/O GPIO See section 1.12 I/O GPIO See section 1.12 I USB detect input USB_D-

All 26 I/O USB Data Line D-

USB_D+

All 27 I/O USB Data Line D+

System PWR_ON All 19 RESET_N All Analog Audio MIC_N LISA-U120 LISA-U130 MIC_P LISA-U120 LISA-U130 SPK_P LISA-U120 LISA-U130 SPK_N LISA-U120 LISA-U130 22 39 40 53 54 I I I I O O Power-on input External reset input Differential analog audio input (negative) Differential analog audio input (positive) Differential analog audio output (positive) Differential analog audio output (negative) Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode. See section 1.11.1 Differential analog audio output shared for all analog path modes: earpiece, headset and loudspeaker mode. See section 1.11.1 Digital Audio I2S_CLK LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 43 I/O First I2S clock Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. 3G.G2-HW-10002-A2 Preliminary System description Page 15 of 159 Input for VBUS (5 V typical) USB supply sense to enable USB interface. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 90 nominal differential impedance Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 90 nominal differential impedance Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 PWR_ON pin has high input impedance. Do not keep floating in noisy environment:

external pull-up required. See section 1.6.1 Internal 10 k pull-up to V_BCKP. See section 1.6.3 Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1 Differential analog input shared for all analog path modes: handset, headset, hands-free mode. Internal DC blocking capacitor. See section 1.11.1 LISA-U series - System Integration Manual I/O Description Remarks No 44 I First I2S receive data 42 O First I2S transmit data Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. 41 I/O First I2S word alignment Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Function Pin Module I2S_RXD I2S_TXD I2S_WA LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 LISA-U120 LISA-U130 LISA-U200-01 LISA-U230 I2S1_CLK LISA-U200-01, LISA-U230 53 I2S1_RXD LISA-U200-01 LISA-U230 39 I2S1_TXD LISA-U200-01 LISA-U230 40 I/O Second I2S clock I O Second I2S receive data Second I2S transmit data I2S1_WA LISA-U200-01 LISA-U230 54 I/O Second I2S word alignment CODEC_CLK LISA-U200-01 LISA-U230 Reserved RSVD All RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD LISA-U1 LISA-U200-00 LISA-U1 LISA-U200 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U200-00 LISA-U100 LISA-U110 LISA-U100 LISA-U110 LISA-U100 LISA-U110 LISA-U100 LISA-U110 52 5 52 74 43 44 42 41 39 40 53 54 O Clock output N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin N/A RESERVED pin Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Internal active pull-down to GND enabled. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Check device specifications to ensure compatibility to module supported modes. See section 1.11.2. Digital clock output for external audio codec See section 1.11.2. This pin must be connected to ground See section 1.13 Pad disabled See section 1.13 Do not connect See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Pad disabled See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Do not connect See section 1.13 Table 4: LISA-U series modules pin definition, grouped by function 3G.G2-HW-10002-A2 Preliminary System description Page 16 of 159 LISA-U series - System Integration Manual 1.4 Operating modes LISA-U series modules have several operating modes. Table 5 summarizes the various operating modes and provides general guidelines for operation. Operating Mode Description Features / Remarks Transition condition General Status: Power-down Not-Powered Mode VCC supply not present or below operating range. Microprocessor switched off

(not operating). RTC only operates if supplied through V_BCKP pin. Power-Off Mode VCC supply within operating range. Microprocessor switched off

(not operating). Only RTC runs. General Status: Normal Operation Idle-Mode Microprocessor runs with 32 kHz as reference oscillator. Module does not accept data signals from an external device. Module is switched off. Application interfaces are not accessible. Internal RTC timer operates only if a valid voltage is applied to V_BCKP pin. Module is switched off: normal shutdown by AT+CPWROFF command (refer to u-blox AT Commands Manual [3]), or by PWR_ON held low for more than 1 s

(LISA-U2xx-01 only). Application interfaces are not accessible. Only the internal RTC timer in operation. If power saving is enabled, the module automatically enters idle-mode whenever possible. Application interfaces are disabled. If hardware flow control is enabled, the CTS line to ON state indicates that the module is in active mode and the UART interface is enabled: the line is driven in the OFF state when the module is not prepared to accept data by the UART interface. If hardware flow control is disabled, the CTS line is fixed to ON state. Module by default is not set to automatically enter idle-mode whenever possible, unless power saving configuration is enabled by appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV). Module cannot be switched on by a low level on the PWR_ON input, by a rising edge on the RESET_N input, or by a preset RTC alarm. Module can be switched on applying VCC supply. Module can be switched on by a low level on the PWR_ON input, by a rising edge on the RESET_N input, or by a preset RTC alarm. Module enters automatically idle-mode when power saving is enabled and there is no activity for the defined time interval:

Module registered with the network and power saving enabled. Periodically wakes up to active mode to monitor the paging channel for the paging block reception according to network indication Module not registered with the network and power saving is enabled. Periodically wakes up to monitor external activity Module wakes up from idle-mode to active-mode in the following events:

Incoming voice or data call RTC alarm occurs Data received on UART interface

(refer to 1.9.2) RTS input line set to the ON state by the DTE if the AT+UPSV=2 command is sent to the module

(refer to 1.9.2) USB detection, applying 5 V (typ.) to the VUSB_DET pin The connected USB host forces a remote wakeup of the module as USB device (refer to 1.9.3) The connected SPI master indicates to the module that it is ready for transmission or reception, by the SPI/IPC SPI_MRDY input signal

(refer to 1.9.4) 3G.G2-HW-10002-A2 Preliminary System description Page 17 of 159 LISA-U series - System Integration Manual Operating Mode Description Features / Remarks Transition condition If power saving is enabled, the module automatically enters idle-mode and application interfaces are disabled whenever possible (refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3], AT+UPSV). When call terminates, the module returns to the active operating mode. Active-Mode Microprocessor runs with 26 MHz as reference oscillator. The module is prepared to accept data signals from an external device. Connected-Mode Voice or data call enabled. Microprocessor runs with 26 MHz as reference oscillator. The module is prepared to accept data signals from an external device. Table 5: Module operating modes summary Module is switched on and is fully active. The application interfaces are enabled, unless power saving configuration is enabled by the AT+UPSV command (refer to sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [3]). Power saving is not enabled by default: it can be enabled by the AT+UPSV command (see u-blox AT Commands Manual [3]). The module is switched on and a voice call or a data call (2G/3G) is in progress. Module is fully active. The application interfaces are enabled, unless power saving configuration is enabled by the AT+UPSV command (see section 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [3]). Transition between the different modes is described in Figure 3. Figure 3: Operating modes transition 3G.G2-HW-10002-A2 Preliminary System description Page 18 of 159 Switch ON:Apply VCCIf power saving is enabled and there is no activity for a defined time intervalAny wake up event described in the module operating modes summary table aboveIncoming/outgoing call or other dedicated device network communicationCall terminated, communication droppedRemove VCCSwitch ON:PWR_ONRESET_NRTC AlarmNot poweredPower offActiveConnectedIdleSwitch OFF:AT+CPWROFFPWR_ON (LISA-U2xx-01 only) LISA-U series - System Integration Manual 1.5 Power management 1.5.1 Power supply circuit overview LISA-U series modules feature a power management concept optimized for the most efficient use of supplied power. This is achieved by hardware design utilizing a power efficient circuit topology (Figure 4), and by power management software controlling the modules power saving mode. Figure 4: LISA-U series power management simplified block diagram Pins with supply function are reported in Table 6, Table 11 and Table 14. LISA-U series modules must be supplied via the VCC pins. There is only one main power supply input, available on the three VCC pins that must be all connected to the external power supply 3G.G2-HW-10002-A2 Preliminary System description Page 19 of 159 Baseband Processor2G/3G Power Amplifier(s)Switching Step-Down5 x 10 F61VCC62VCC63VCC50VSIM2V_BCKP4V_INTLinear LDOLinear LDOSwitching Step-DownLinear LDOLinear LDOLinear LDOI/OEBUCOREAnalogSIMRTCNOR FlashDDR SRAMRF TransceiverMemoryPower Management Unit22 F10 F (LISA-U1)220 nF (LISA-U2)220 nF2G/3G PA PMU(LISA-U2)TransceiverPMU(LISA-U2)(LISA-U1) LISA-U series - System Integration Manual The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit

(PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators. V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time Clock can be externally supplied via the V_BCKP pin (see section 1.5.4). When a 1.8 V or a 3 V SIM card type is connected, LISA-U series modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance to the ISO-IEC 7816-3 specifications. The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-U series modules in the final application. The integrated Power Management Unit also provides the control state machine for system start up and system reset control. 1.5.2 Module supply (VCC) The LISA-U series modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system power supply circuit is able to support peak power (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the detailed specifications). Name VCC Description Module power supply input GND Ground Table 6: Module supply pins Remarks VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range. Consider that during a GSM call there are large current spikes in connected mode. GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads must be connected to ground. VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level can be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage normal operating range. The module cannot be switched on if the VCC voltage value is below the specified normal operating range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for more than 3 s after the start of the module switch-on sequence. 3G.G2-HW-10002-A2 Preliminary System description Page 20 of 159 LISA-U series - System Integration Manual When LISA-U series modules are in operation, the voltage provided to VCC pins can go outside the normal operating range limits but must be within the extended operating range limits specified in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Occasional deviations from the ETSI specifications may occur when the input voltage at VCC pins is outside the normal operating range and is within the extended operating range. LISA-U series modules switch off when VCC voltage value drops below the specified extended operating range minimum limit: ensure that the input voltage at VCC pins never drops below the minimum limit of the extended operating range when the module is switched on, not even during a GSM transmit burst, where the current consumption can rise up to maximum peaks of 2.5 A in case of a mismatched antenna load. Operation above the normal operating range maximum limit is not recommended and extended exposure beyond it may affect device reliability. Stress beyond the VCC absolute maximum ratings can cause permanent damage to the module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection. When designing the power supply for the application, pay specific attention to power losses and transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics:

o Voltage drop during transmit slots must be lower than 400 mV o No undershoot or overshoot at the start and at the end of transmit slots o Voltage ripple during transmit slots must be minimized:

lower than 70 mVpp if fripple 200 kHz lower than 10 mVpp if 200 kHz < fripple 400 kHz lower than 2 mVpp if fripple > 400 kHz Figure 5: Description of the VCC voltage profile versus time during a GSM call Any degradation in power supply performance (due to losses, noise or transients) will directly affect the RF performance of the module since the single external DC power source indirectly supplies all the digital and analog interfaces, and also directly supplies the RF power amplifier (PA). 3G.G2-HW-10002-A2 Preliminary System description Page 21 of 159 TimeundershootovershootripplerippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) LISA-U series - System Integration Manual The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms. This VCC slope allows a proper switch on of the module when the voltage rises to the VCC normal operating range from a voltage of less than 2.25 V. If the external supply circuit cannot raise the VCC voltage from 2.5 V to 3.2 V within 1 ms RESET_N should be kept low during VCC rising edge, so that the module will switch on releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal operating range. 1.5.2.1 VCC application circuits LISA-U series modules must be supplied through the VCC pins by one (and only one) proper DC power supply that must be one of the following:

Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery Figure 6: VCC supply concept selection The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the LISA-U series modules operating supply voltage. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source. The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less than 5 V). In this case the typical 90% efficiency of the switching regulator will diminish the benefit of voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy in thermal power. If LISA-U series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided. The use of primary (not rechargeable) battery is uncommon, since the most cells available are seldom capable of delivering the burst peak current for a GSM call due to high internal resistance. Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in LISA-U series modules). The charger circuit should be designed in order to prevent over-voltage on VCC beyond the upper limit of the absolute maximum rating. 3G.G2-HW-10002-A2 Preliminary System description Page 22 of 159 Main Supply Available?BatteryLi-Ion 3.7 VLinear LDO RegulatorMain Supply Voltage >5 V?Switching Step-Down RegulatorNo, portable deviceNo, less than 5 VYes, greater than 5 VYes, always available LISA-U series - System Integration Manual The following sections highlight some design aspects for each of the supplies listed above. Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements:

Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current pulses with 1/8 duty cycle to the VCC pins Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile High switching frequency: for best performance and for smaller applications select a switching frequency 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in active mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the module changes status from idle/active mode to connected mode (where current consumption increases to a value greater than 100 mA): it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA) Output voltage slope: the use of the soft start function provided by some voltage regulator must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module Figure 7 and the components listed in Table 7 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high:

switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply. Figure 7: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator 3G.G2-HW-10002-A2 Preliminary System description Page 23 of 159 LISA-U series12VC5R3C4R2C2C1R1VINRUNVCRTPGSYNCBDBOOSTSWFBGND671095C61238114C7C8D1R4R5L1C3U162VCC63VCC61VCCGND LISA-U series - System Integration Manual Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 C6 C7 C8 D1 L1 R1 R2 R3 R4 R5 U1 10 F Capacitor Ceramic X7R 5750 15% 50 V C5750X7R1H106MB - TDK 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 680 pF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71H681KA01 - Murata 22 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H220JZ01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 470 nF Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E474KA12 - Murata 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor 10 H Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics 470 k Resistor 0402 5% 0.1 W 15 k Resistor 0402 5% 0.1 W 22 k Resistor 0402 5% 0.1 W 390 k Resistor 0402 1% 0.063 W 100 k Resistor 0402 5% 0.1 W 2322-705-87474-L - Yageo 2322-705-87153-L - Yageo 2322-705-87223-L - Yageo RC0402FR-07390KL - Yageo 2322-705-70104-L - Yageo Step Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology Table 7: Suggested components for the VCC voltage supply application circuit using a step-down regulator Low Drop-Out (LDO) linear regulator The characteristics of the LDO linear regulator connected to the VCC pins should meet the following requirements:

Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper voltage value to the VCC pins and of delivering 2.5 A current pulses with 1/8 duty cycle Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator) Output voltage slope: the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module Figure 8 and the components listed in Table 8 show an example of a power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering 2.5 A current pulses, with proper power handling capability. The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to the 3.8 V typical value of the VCC supply. Figure 8: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator 3G.G2-HW-10002-A2 Preliminary System description Page 24 of 159 5VC1R1INOUTADJGND12453C2R2R3U1SHDNLISA-U series62VCC63VCC61VCCGNDC3 LISA-U series - System Integration Manual Reference Description Part Number - Manufacturer C1, C2 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata C3 R1 R2 R3 U1 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 47 k Resistor 0402 5% 0.1 W 4.7 k Resistor 0402 5% 0.1 W 2.2 k Resistor 0402 5% 0.1 W LDO Linear Regulator ADJ 3.0 A RC0402JR-0747KL - Yageo Phycomp RC0402JR-074K7L - Yageo Phycomp RC0402JR-072K2L - Yageo Phycomp LT1764AEQ#PBF - Linear Technology Table 8: Suggested components for VCC voltage supply application circuit using an LDO linear regulator Rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption to VCC pins. The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts Primary (disposable) battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption at the VCC pins. The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts 3G.G2-HW-10002-A2 Preliminary System description Page 25 of 159 LISA-U series - System Integration Manual Additional recommendations for the VCC supply application circuits To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines

(connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible in order to minimize power losses. Three pins are allocated for VCC supply. Another twenty pins are designated for GND connection. Even if all the VCC pins and all the GND pins are internally connected within the module, it is recommended to properly connect all of them to supply the module in order to minimize series resistance losses. To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a GSM call

(when current consumption on the VCC supply can rise up to as much as 2.5 A in the worst case), place a capacitor with large capacitance (more than 100 F) and low ESR near the VCC pins, for example:

330 F capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor) The use of very large capacitors (i.e. greater then 1000 F) on the VCC line and the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch on of the module. To reduce voltage ripple and noise, place the following near the VCC pins:

100 nF capacitor (e.g Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources 10 pF capacitor (e.g. Murata GRM1555C1E100J) to filter EMI in the 1800 / 1900 / 2100 MHz bands 39 pF capacitor (e.g. Murata GRM1555C1E390J) to filter EMI in the 850 / 900 MHz bands Figure 9 shows the complete configuration but the mounting of each single component depends on the application design. Figure 9: Suggested schematic design to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 39 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E390JA01 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Table 9: Suggested components to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops 3G.G2-HW-10002-A2 Preliminary System description Page 26 of 159 3V8C1C4GNDC3C2C5LISA-U series62VCC63VCC61VCC+LISA-U series - System Integration Manual External battery charging application circuit LISA-U series modules dont have an on-board charging circuit. An example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell, is provided in Figure 10. In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse and DC discharge current capabilities and proper DC series resistance, is directly connected to the VCC supply input of LISA-U series module. Battery charging is completely managed by the STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges as a linear charger the battery, in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for USB power source (~500 mA) Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the L6924U starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor to ~15 mA or when the charging timer reaches the value configured by an external capacitor to ~9800 s Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. Alternatively the L6924U, providing input voltage range up to 12 V, can charge from an AC wall adapter. When a current-limited adapter is used, it can operate in quasi-pulse mode, reducing power dissipation. Figure 10: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Part Number - Manufacturer B1 C1, C4 C2, C6 C3 C5 C7 C8 C9 D1 Li-Ion (or Li-Polymer) battery pack with 470 NTC Various manufacturer 1 F Capacitor Ceramic X7R 0603 10% 16 V GRM188R71C105KA12 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 1 nF Capacitor Ceramic X7R 0402 10% 50 V GRM155R71H102KA01 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 39 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E390JA01 - Murata 10 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E100JA01 - Murata Low Capacitance ESD Protection USB0002RP or USB0002DP - AVX R1, R2 24 k Resistor 0402 5% 0.1 W R3 R4 U1 3.3 k Resistor 0402 5% 0.1 W 1.0 k Resistor 0402 5% 0.1 W Single Cell Li-Ion (or Li-Polymer) Battery Charger IC for USB port and AC Adapter RC0402JR-0724KL - Yageo Phycomp RC0402JR-073K3L - Yageo Phycomp RC0402JR-071K0L - Yageo Phycomp L6924U - STMicroelectronics Table 10: Suggested components for Li-Ion (or Li-Polymer) battery charging application circuit 3G.G2-HW-10002-A2 Preliminary System description Page 27 of 159 C5C8GNDC7C6C9LISA-U series62VCC63VCC61VCC+USB SupplyC3R4U1IUSBIACIENDTPRGSDVINVINSNSMODEISELC2C15V0THGNDVOUTVOSNSVREFR1R2R3Li-Ion/Li-Pol Battery PackD1B1C4Li-Ion/Li-Polymer Battery Charger IC LISA-U series - System Integration Manual 1.5.3 Current consumption profiles During operation, the current drawn by the LISA-U series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in 2G connected mode, to continuous high current drawn in UMTS connected mode, to the low current consumption during power saving in idle-mode. 1.5.3.1 2G connected mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM 900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 s

(width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is in GSM connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than the one in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). During a GSM call, current consumption is in the order of 60-130 mA in receiving or in monitor bursts and is about 10-40 mA in the inactive unused bursts (low current period). The more relevant contribution to determine the average current consumption is set by the transmitted power in the transmit slot. An example of current consumption profile of the data module in GSM talk mode is shown in Figure 11. Figure 11: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot), with VCC=3.8 V When a GPRS connection is established there is a different VCC current consumption profile also determined by the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current consumption is not as high as can be in case of a GSM call. If the module transmits in GPRS class 12 or class 33 connected mode in the GSM 850 or in the E-GSM 900 band at the maximum power control level, the current consumption can reach up to 1600 mA (with unmatched 3G.G2-HW-10002-A2 Preliminary System description Page 28 of 159 Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200 mA60-130 mA2500 mAPeak current depends on TX powerGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.060-130 mA10-40 mA LISA-U series - System Integration Manual antenna). This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). Figure 12 reports the current consumption profiles in GPRS class 12 connected mode, in the GSM 850 or in the E-GSM 900 band, with 4 slots used to transmit and 1 slot used to receive. Figure 12: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot), with VCC=3.8 V In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 12, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well. LISA-U2 series modules support GPRS and EDGE class 33: up to 4 slots can be used to transmit, as in the class 12 mode, and up to 2 slots can be used to receive in the same frame since up to 6 slots can be used in total. So, the VCC current consumption figures in GPRS and EDGE class 33 connected modes are similar to the current profile in GPRS and EDGE class 12 connected modes, since the same number of transmit slots are used. 1.5.3.2 3G connected mode During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex

(FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 s, thus the rate of power change can reach a maximum rate of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case. In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the order of continuous 500-800 mA (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for detailed values). Even at lowest output RF power (approximately 0.01 W or -50 dBm), the current still remains in the order of 200 mA due to module baseband processing and transceiver activity. An example of current consumption profile of the data module in UMTS/HSxPA continuous transmission mode is shown in Figure 13. 3G.G2-HW-10002-A2 Preliminary System description Page 29 of 159 Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200mA60-130mAPeak current depends on TX powerGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.01600 mA60-130mA10-40mA LISA-U series - System Integration Manual Figure 13: VCC current consumption profile versus time during a UMTS/HSPA connection, with VCC=3.8 V When a packet data connection is established, the actual current profile depends on the amount of transmitted packets; there might be some periods of inactivity between allocated slots where current consumption drops about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher quality signal required by the network to cope with enhanced data speed. 1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command

(refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible. When power saving is enabled, the module is registered or attached to a network and a voice or data call is not enabled, the module automatically enters idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to GSM system requirements. When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging block. In between, the module switches to idle-mode. This is known as GSM discontinuous reception (DRX). The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode. The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell. In case of 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX = 2, i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX = 9, i.e. width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms). In case of 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of 26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms =

5120 ms). An example of a module current consumption profile is shown in Figure 14: the module is registered with the network (2G or 3G), automatically enters idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception. 3G.G2-HW-10002-A2 Preliminary System description Page 30 of 159 Time [ms]3G frame 10 ms (1 frame = 15 slots)Current [mA]Depends on TX power170 mA1 slot 666 s850 mA0300200100500400600700800 LISA-U series - System Integration Manual Figure 14: Description of VCC current consumption profile versus time when the module is registered with 2G or 3G networks:

the module is in idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception 1.5.3.4 2G and 3G fixed active mode (power saving disabled) Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is disabled, the module doesnt automatically enter idle-mode whenever possible: the module remains in active mode. The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. An example of the current consumption profile of the data module when power saving is disabled is shown in Figure 15: the module is registered with the network, active-mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception. 3G.G2-HW-10002-A2 Preliminary System description Page 31 of 159

~30 msIDLE MODEACTIVE MODEIDLE MODE400-700 AActive Mode EnabledIdle Mode Enabled400-700 A2G case: 60-130 mA 3G case: 50-90 mA2G case: 0.44-2.09 s 3G case: 0.61-5.09 sIDLE MODE2G or 3G case: ~30 msACTIVE MODETime [s]Current [mA]150100500Time [ms]Current [mA]1501005005-10 mA10-25 mA2G case: 60-130 mA 3G case: 50-90 mAPLL EnabledRX Enabled35-40 mADSP Enabled LISA-U series - System Integration Manual Figure 15: Description of the VCC current consumption profile versus time when power saving is disabled: the active-mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception 1.5.4 RTC Supply (V_BCKP) The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power-On / Reset internal logic. This supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The output of this linear regulator is always enabled when the main voltage supply provided to the module through VCC is within the valid operating range, with the module switched-off or powered-on. Name V_BCKP Description Real Time Clock supply Table 11: Real Time Clock supply pin Remarks V_BCKP output voltage = 2.3 V (typical) on LISA-U1 series V_BCKP output voltage = 1.8 V (typical) on LISA-U2 series Generated by the module to supply Real Time Clock when VCC supply voltage is within valid operating range. The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. 3G.G2-HW-10002-A2 Preliminary System description Page 32 of 159 ACTIVE MODE10-25 mA10-25 mA2G case: 0.47-2.12 s 3G case: 0.64-5.12 sPaging periodTime [s]Current [mA]150100500Time [ms]Current [mA]15010050010-25 mARX EnabledDSP Enabled35-40 mA2G case: 60-130 mA 3G case: 50-90 mA2G case: 60-130 mA 3G case: 50-90 mA LISA-U series - System Integration Manual The RTC provides the time reference (date and time) of the module, also in power-off mode, when the V_BCKP voltage is within its valid range (specified in the Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). The RTC timing is normally used to set the wake-up interval during idle-mode periods between network paging, but is able to provide programmable alarm functions by means of the internal 32.768 kHz clock. The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. The RTC oscillator doesn't necessarily stop operation (i.e. the RTC counting doesn't necessarily stop) when V_BCKP voltage value drops below the specified operating range minimum limit (1.00 V): the RTC value read after a system restart could be not reliable as explained in the following Table 12. V_BCKP voltage value RTC value reliability Notes 1.00 V < V_BCKP < 1.90 V (LISA-U2 series) 1.00 V < V_BCKP < 2.50 V (LISA-U1 series) RTC oscillator doesn't stop operation RTC value read after a restart of the system is reliable 0.05 V < V_BCKP < 1.00 V 0.00 V < V_BCKP < 0.05 V RTC oscillator doesn't necessarily stop operation RTC value read after a restart of the system is not reliable RTC oscillator stops operation RTC value read after a restart of the system is reliable V_BCKP within operating range V_BCKP below operating range V_BCKP below operating range Table 12: RTC value reliability as function of V_BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch-on the module). The RTC has very low power consumption, but is highly temperature dependent. For example at 25C, with the V_BCKP voltage equal to the typical output value, the power consumption is approximately 2 A (refer to the Input characteristics of Supply/Power pins table in the LISA-U1 series Data Sheet [1] and in the LISA-U2 series Data Sheet [2] for the detailed specification), whereas at 70C and an equal voltage the power consumption increases to 5-10 A. The internal regulator for V_BCKP is optimized for low leakage current and very light loads. It is not recommended to use V_BCKP to supply external loads. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). This has no impact on wireless connectivity, as all the functionalities of the module do not rely on date and time setting. Leave V_BCKP unconnected if the RTC is not required when the VCC supply is removed. The date and time will not be updated when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP. If RTC is required to run for a time interval of T [s] at 25C when VCC supply is removed, place a capacitor with a nominal capacitance of C [F] at the V_BCKP pin. Choose the capacitor using the following formula:

C [F] = (Current_Consumption [A] x T [s]) / Voltage_Drop [V]

= 1.92 x T [s] for LISA-U1 series

= 2.50 x T [s] for LISA-U2 series For example, a 100 F capacitor (such as the Murata GRM43SR60J107M) can be placed at V_BCKP to provide a long buffering time. This capacitor will hold V_BCKP voltage within its valid range for around 50 s at 25C, after the VCC supply is removed. If a very long buffering time is required, a 70 mF super-capacitor (e.g. Seiko 3G.G2-HW-10002-A2 Preliminary System description Page 33 of 159 LISA-U series - System Integration Manual Instruments XH414H-IV01E) can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage within its valid range for approximately 10 hours at 25C, after the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors will allow the time reference to run during battery disconnection. Figure 16: Real time clock supply (V_BCKP) application circuits: (a) using a 100 F capacitor to let the RTC run for ~50 s after VCC removal; (b) using a 70 mF capacitor to let RTC run for ~10 hours after VCC removal; (c) using a non-rechargeable battery Reference Description Part Number - Manufacturer C1 R2 C2 100 F Tantalum Capacitor GRM43SR60J107M - Murata 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp 70 mF Capacitor XH414H-IV01E - Seiko Instruments Table 13: Example of components for V_BCKP buffering If longer buffering time is required to allow the time reference to run during a disconnection of the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP (specified in the Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and in LISA-U2 series Data Sheet [2]). The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to the non-rechargeable battery. Combining a LISA-U series wireless module with a u-blox GPS receiver, the VCC supply of the GPS receiver is controlled by the wireless module by means of the GPS supply enable function provided by the GPIO2 of the wireless module. In this case the V_BCKP supply output of the LISA-U series wireless module can be connected to the V_BCKP backup supply input pin of the GPS receiver to provide the supply for the GPS real time clock and backup RAM when the VCC supply of the wireless module is within its operating range and the VCC supply of the GPS receiver is disabled. This enables the u-blox GPS receiver to recover from a power breakdown with either a Hotstart or a Warmstart (depending on the duration of the GPS VCC outage) and to maintain the configuration settings saved in the backup RAM. Refer to section 1.10 for more details regarding the application circuit with a u-blox GPS receiver. 1.5.5 Interface supply (V_INT) The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin. The internal regulator that generates the V_INT supply is a switching step down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and is disabled when the module is switched off or when the RESET_N pin is forced the low level. The switching regulator operates in Pulse Width Modulation (PWM) for high output current mode but automatically switches to Pulse 3G.G2-HW-10002-A2 Preliminary System description Page 34 of 159 LISA-U seriesC1(a)2V_BCKPR2LISA-U seriesC2(superCap)(b)2V_BCKPD3LISA-U seriesB3(c)2V_BCKP LISA-U series - System Integration Manual Frequency Modulation (PFM) at low output loads for greater efficiency, e.g. when the module is in idle-mode between paging periods. Name V_INT Description Remarks Digital Interfaces supply output V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. V_INT is the internal supply for digital interfaces. The user may draw limited current from this supply rail. Table 14: Interface supply pin The V_INT pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. Since it supplies internal digital circuits (see Figure 4), V_INT is not suited to directly supply any sensitive analog circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to 70 mVpp in idle-mode (PFM). V_INT can be used to supply external digital circuits operating at the same voltage level as the digital interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without adequate filtering for digital noise. Dont apply loads which might exceed the limit for maximum available current from V_INT supply, as this can cause malfunctions in internal circuitry supplies to the same domain. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. V_INT can only be used as an output; dont connect any external regulator on V_INT. If not used, this pin should be left unconnected. The V_INT digital interfaces supply output is mainly used to:

Pull-up DDC (I2C) interface signals (see section 1.10.2 for more details) Pull-up SIM detection signal (see section 1.8 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see section 1.9.2.4) Indicate when the module is switched on and the RESET_N (external reset input) is not forced low 1.6 System functions 1.6.1 Module power-on The power-on sequence of LISA-U series modules is initiated in one of these ways:

Rising edge on the VCC pin to a valid voltage as module supply (i.e. applying module supply) Low level on the PWR_ON pin (i.e. forcing to the low level the pin normally high by external pull-up) Rising edge on the RESET_N pin (i.e. releasing from low level the pin, normally high by internal pull-up) RTC alarm (i.e. pre-programmed scheduled time by AT+CALA command) 3G.G2-HW-10002-A2 Preliminary System description Page 35 of 159 LISA-U series - System Integration Manual Name Description PWR_ON Power-on input Table 15: Power-on pin Remarks PWR_ON pin has high input impedance. Do not keep floating in noisy environment:

external pull-up required. The PWR_ON pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. 1.6.1.1 Rising edge on VCC When a supply is connected to VCC pins, the module supply supervision circuit controls the subsequent activation of the power up state machines: the module is switched on when the voltage rises up to the VCC normal operating range minimum limit starting from a voltage value lower than 2.25 V (refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the VCC normal operating range minimum limit). The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to switch on the module. 1.6.1.2 Low level on PWR_ON The module power-on sequence starts when a low level is forced on the PWR_ON input for at least 5 ms. The electrical characteristics of the PWR_ON input pin are slightly different between LISA-U1 series and LISA-U2 series modules, and are different from the other digital I/O interfaces: the pin provides different input voltage thresholds and is tolerant of voltages up to the module supply level. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module. Avoid keeping it floating in a noisy environment. To hold the high logic level stable, the PWR_ON pin must be connected to a pull-up resistor (e.g. 100 k) biased by the V_BCKP supply pin of the module. Following are some typical examples of application circuits to turn the module on using the PWR_ON input pin. The simplest way to turn on the module is to use a push button that shorts the PWR_ON input to ground: in this case the V_BCKP supply pin can be used to bias the pull-up resistor. If PWR_ON input is connected to an external device (e.g. application processor), it is suggested to use an open drain output on the external device with an external pull-up resistor (e.g. 100 k) biased by the V_BCKP supply pin of the module. A push-pull output of an application processor can also be used: in this case the pull-up can be used to pull the PWR_ON level high when the application processor is switched off. If the high-level voltage of the push-pull output pin of the application processor is greater than the maximum input voltage operating range of the V_BCKP pin (refer to the V_BCKP Input characteristics of Supply/Power pins table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]), the V_BCKP supply cannot be used to bias the pull-up resistor: the supply rail of the application processor or the VCC supply could be used, but this will increase the V_BCKP (RTC supply) current consumption when the module is in not-powered mode (VCC supply not present). Using a push-

pull output of the external device, take care to fix the proper level in all the possible scenarios to avoid an inappropriate switch-on of the module. 3G.G2-HW-10002-A2 Preliminary System description Page 36 of 159 LISA-U series - System Integration Manual Figure 17: PWR_ON application circuits using a push button and an open drain output of an application processor Reference Description Remarks Rext ESD 100 k Resistor 0402 5% 0.1 W External pull-up resistor CT0402S14AHSG - EPCOS Varistor array for ESD protection Table 16: Example of pull-up resistor and ESD protection for the PWR_ON application circuits 1.6.1.3 Rising edge on RESET_N LISA-U series modules can be switched on by means of the RESET_N input pin: the RESET_N signal must be forced low for at least 50 ms and then released to generate a rising edge that starts the module power-on sequence. RESET_N input pin can also be used to perform an external or hardware reset of the module, as described in the section 1.6.3. Electrical characteristics of the LISA-U series RESET_N input are slightly different from the other digital I/O interfaces: the pin provides different input voltage thresholds. Detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. RESET_N is pulled high to V_BCKP by an integrated pull-up resistor also when the module is in power-off mode. Therefore an external pull-up is not required on the application board. The simplest way to switch on the module by means of the RESET_N input pin is to use a push button that shorts the RESET_N pin to ground: the module will be switched on at the release of the push button, since the RESET_N will be forced to the high level by the integrated pull-up resistor, generating a rising edge. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]). To avoid unwanted power-on or reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. Some typical examples of application circuits using the RESET_N input pin are described in the section 1.6.3. 3G.G2-HW-10002-A2 Preliminary System description Page 37 of 159 LISA-U seriesRext2V_BCKP19PWR_ONPower-on push buttonESDOpen Drain OutputApplication ProcessorLISA-U seriesRext2V_BCKP19PWR_ON LISA-U series - System Integration Manual 1.6.1.4 Real Time Clock (RTC) alarm If a voltage within the operating range is maintained at the VCC pin, the module can be switched on by the RTC alarm when the RTC system reaches a pre-programmed scheduled time (refer to the u-blox AT Commands Manual [3], AT+CALA command). The RTC system will then initiate the boot sequence by instructing the Power Management Unit to turn on power. Also included in this setup is an interrupt signal from the RTC block to indicate to the baseband processor that an RTC event has occurred. 1.6.1.5 Additional considerations The module is switched on when the VCC voltage rises up to the normal operating range (i.e. applying module supply): the first time that the module is used, it is switched on in this way. Then, LISA-U series modules can be switched off by means of the AT+CPWROFF command. When the module is in power-off mode, i.e. the AT+CPWROFF command has been sent and a voltage value within the normal operating range limits is still provided to the VCC pin, the digital input-output pads of the baseband chipset (i.e. all the digital pins of the module) are locked in tri-state (i.e. floating). The power down tri-state function isolates the module pins from its environment, when no proper operation of the outputs can be guaranteed. The module can be switched on from power-off mode by forcing a proper start-up event (i.e. PWR_ON low, RESET_N release or RTC alarm). After the detection of a start-up event, all the digital pins of the module are held in tri-state until all the internal LDO voltage regulators are turned on in a defined power-on sequence. Then, as described in Figure 18, the baseband core is still held in reset state for a time interval: the internal reset signal

(which is not available on a module pin) is still low and any signal from the module digital interfaces is held in reset state. The reset state of all the digital pins is reported in the pin description table of LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. When the internal signal is released, the configuration of the module interfaces starts: during this phase any digital pin is set in a proper sequence from the reset state to the default operational configuration. Finally, the module is fully ready to operate when all interfaces are configured. Figure 18: LISA-U series power-on sequence description The Internal Reset signal is not available on a module pin. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits 3G.G2-HW-10002-A2 Preliminary System description Page 38 of 159 VCCV_BCKPPWR_ONV_INTInternal ResetSystem StateBB Pads StateInternal Reset OperationalOperationalTristate / Floating Internal ResetOFFONStart-up event0 ms~5 ms~6 ms~35 ms~3 sPWR_ON can be set highStart of interface configurationAll interfaces are configured LISA-U series - System Integration Manual and let a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power on sequence. 1.6.2 Module power-off The correct way to switch off LISA-U series modules is by means of +CPWROFF AT command (more details in u-blox AT Commands Manual [3]): in this way the current parameter settings are saved in the modules non-volatile memory and a proper network detach is performed. LISA-U2xx-01 modules can also be properly switched off by means of the PWR_ON input pin: the PWR_ON signal must be held to the low logic level for more than 1 s to start the module power-off sequence. In this way, current parameter settings are saved in LISA-U2xx-01 modules non-volatile memory and a correct network detach is performed: the same sequence is performed as by the +CPWROFF AT command. An under-voltage shutdown occurs on LISA-U series modules when the VCC supply is removed, but in this case the current parameter settings are not saved in the modules non-volatile memory and a proper network detach cannot be performed. The power-off sequence by means of +CPWROFF AT command is described in Figure 19. When the +CPWROFF AT command is sent, the module starts the switch-off routine replying OK on the AT interface. At the end of the switch-off routine, all digital pins are locked in tri-state by the module and all the internal LDO voltage regulators except the RTC supply (V_BCKP) are turned off in a defined power-off sequence. The module remains in power-off mode as long as a switch on event doesnt occur (i.e. applying a low level on the PWR_ON pin, or releasing from low level the RESET_N pin, or by a pre-programmed RTC alarm), and enters not-powered mode if the supply is removed from the VCC pin. Current parameter settings are stored to the modules non-volatile memory and a network detach is performed before the OK reply from AT+CPWROFF command on all LISA-U series modules except LISA-U1xx-00 versions. Storage of parameters and network detach are performed before the end of the switch-off routine, but not necessary before the OK reply from AT+CPWROFF command on LISA-U1xx-00 versions. Since the time to perform a network detach depends on the network settings, the duration of the switch off routine phases can differ from the typical values reported in Figure 19. Figure 19: LISA-U series Power-off sequence description 3G.G2-HW-10002-A2 Preliminary System description Page 39 of 159 VCCV_BCKPPWR_ONV_INTInternal ResetSystem StateBB Pads StateOperationalOFFTristate / Floating ONOperational Tristate / FloatingAT+CPWROFFsent to the module0 ms~50 ms~400 msOKreplied by the module LISA-U series - System Integration Manual The Internal Reset signal is not available on a module pin. Tristated pins are always subject to floating caused by noise: to prevent unwanted effects, fix them with proper pull-up or pull down resistors to stable voltage rails to fix their level when the module is in Power down state. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.6.3 Module reset LISA-U series modules reset can be performed in one of 2 ways:

Forcing a low level on the RESET_N input pin, causing an external or hardware reset Via AT command, causing an internal or software reset RESET_N input pin: force low for at least 50 ms; either an external or hardware reset is performed. This causes an asynchronous reset of the entire module, including the integrated Power Management Unit, except for the RTC internal block: the V_INT interfaces supply is switched off and all the digital pins are tri-stated, but the V_BCKP supply and the RTC block are enabled. Forcing an external or hardware reset, the current parameter settings are not saved in the modules non-volatile memory and a proper network detach is not performed. AT+CFUN command (more details in u-blox AT Commands Manual [3]): in this case an internal or software reset is performed, causing an asynchronous reset of the baseband processor, excluding the integrated Power Management Unit and the RTC internal block: the V_INT interfaces supply is enabled and each digital pin is set in its internal reset state (reported in the pin description table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]), the V_BCKP supply and the RTC block are enabled. Forcing an internal or software reset, the current parameter settings are saved in the modules non-volatile memory and a proper network detach is performed. When RESET_N is released from the low level, the module automatically starts its power-on sequence from the reset state. The same procedure is followed for the module reset via AT command after having performed the network detach and the parameter saving in non-volatile memory. The internal reset state of all digital pins is reported in the pin description table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. Name RESET_N Table 17: Reset pin Description External reset input Remarks Internal 10 k pull-up to V_BCKP The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. For more details about RESET_N circuit precautions for ESD immunity please refer to chapter 2.5.3. The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. 3G.G2-HW-10002-A2 Preliminary System description Page 40 of 159 LISA-U series - System Integration Manual RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-up is not required on the application board. Following are some typical examples of application circuits using the RESET_N input pin. The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U1 series Data Sheet [1]

and LISA-U2 series Data Sheet [2]). To avoid unwanted reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) and a series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the RESET_N line pin of LISA-U1 series modules and an additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board (for more details, refer to chapter 2.5.3). Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD C1, C3 C2, C4 FB1, FB2 Rint Varistor for ESD protection. CT0402S14AHSG - EPCOS 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata 220 nF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J224KE01 - Murata Chip Ferrite Bead for Noise/EMI Suppression BLM15HD182SN1 - Murata 10 k Resistor 0402 5% 0.1 W Internal pull-up resistor Table 18: Example of ESD protection components for the RESET_N application circuit Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot 3G.G2-HW-10002-A2 Preliminary System description Page 41 of 159 LISA-U series2V_BCKP22RESET_NReset push buttonESDOpen Drain OutputApplication ProcessorLISA-U series2V_BCKP22RESET_NRintRintFB1C1FB2C3C2C4 LISA-U series - System Integration Manual be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.7 RF connection The ANT pin, provided by all LISA-U series modules, represents the main RF input/output used to transmit and receive the 2G and 3G RF signal: the main antenna must be connected to this pad. The ANT pin has a nominal characteristic impedance of 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. and must be connected to the antenna through a 50 The ANT_DIV pin, provided by LISA-U230 modules, represents the RF input for the integrated diversity receiver:

the antenna for the Rx diversity should be connected to this pad. The ANT_DIV pin has a nominal characteristic impedance of 50 transmission line to allow reception of radio frequency (RF) signals in the 2G and 3G operating bands. and must be connected to the antenna for the Rx diversity through a 50 Name ANT Module Description Remarks All RF input/output for main Tx/Rx antenna Zo = 50 nominal characteristic impedance. ANT_DIV LISA-U230 RF input for Rx diversity antenna Zo = 50 nominal characteristic impedance. Table 19: Antenna pins ESD immunity rating of the ANT port of LISA-U1 series modules is 500 V (according to IEC 61000-4-2). ESD immunity rating of the ANT port of LISA-U200-00 modules is 1000 V (according to IEC 61000-4-2). Higher protection level could be required if the line is externally accessible on the application board (for further details see section 2.5.3). Choose an antenna with optimal radiating characteristics for the best electrical performance and overall module functionality. An internal antenna, integrated on the application board, or an external antenna, connected to the application board through a proper 50 connector, can be used. See section 2.4 and section 2.2.1.1 for further details regarding antenna guidelines. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. If an external antenna is used, the PCB-to-RF-cable transition must be implemented using either a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 characteristic impedance. If antenna supervisor functionality is required, the main antenna connected to the ANT pin should have a built in DC diagnostic resistor to ground to get proper detection functionality (See section 2.4.3). If the Rx diversity is not implemented, ANT_DIV pin can be left unconnected on the application board. 1.8 (U)SIM interface High-speed SIM/ME interface is implemented as well as automatic detection of the required SIM supporting voltage. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The SIM driver supports the PPS 3G.G2-HW-10002-A2 Preliminary System description Page 42 of 159 LISA-U series - System Integration Manual

(Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM Card. Name VSIM SIM_CLK SIM_IO SIM_RST Description SIM supply SIM clock SIM data SIM reset Table 20: SIM Interface pins Remarks 1.80 V typical or 2.90 V typical Automatically generated by the module 3.25 MHz clock frequency Open drain, internal 4.7 k pull-up resistor to VSIM A low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002RP) must be placed near the SIM card holder on each line (VSIM, SIM_IO, SIM_CLK, SIM_RST). The SIM interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F): higher protection level is required if the lines are connected to an SIM card connector, since they are externally accessible on the application board. For more details about the general precautions for ESD immunity about SIM interface pins please refer to chapter 2.5.3. Figure 21 shows an application circuit connecting the LISA-U series module and the SIM card placed in a SIM card holder, using the SIM detection function provided by GPIO5 pin. Note that, as defined by ETSI TS 102 221 or ISO/IEC 7816, SIM card contacts assignment is as follows:

Contact C1 = VCC (Supply) It must be connected to VSIM Contact C2 = RST (Reset) It must be connected to SIM_RST Contact C3 = CLK (Clock) It must be connected to SIM_CLK Contact C4 = AUX1 (Auxiliary contact for USB interface and other uses) It must be left not connected Contact C5 = GND (Ground) It must be connected to GND Contact C6 = VPP (Programming supply) It must be connected to VSIM Contact C7 = I/O (Data input/output) It must be connected to SIM_IO Contact C8 = AUX2 (Auxiliary contact for USB interface and other uses) It must be left not connected A SIM card can have 6 contacts (C1 = VCC, C2 = RST, C3 = CLK, C5 = GND, C6 = VPP, C7 = I/O) or 8 contacts

(providing also the auxiliary contacts C4 = AUX1 and C8 = AUX2). The contacts number depends if additional features, that are not supported by the (U)SIM card interface of the LISA-U series modules, are provided by the SIM card (contacts C4 = AUX1 and C8 = AUX2 for USB interfaces and other uses). A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins for the mechanical card presence detection are provided. Figure 21 shows an application circuit connecting a LISA-U series module and a SIM card placed in a SIM card holder with 6+2 pins (as the CCM03-3013LFT R102 connector, produced by C&K Components, which provides 2 pins for the mechanical card presence detection), using the SIM detection function provided by the GPIO5 of LISA-U series module. This configuration allows the module to detect if a SIM card is present in the connector. The SW1 and SW2 pins of the SIM card holder are connected to a normally-open mechanical switch integrated in the SIM connector. The following cases are available SIM card not present: the GPIO5 signal is forced low by the pull-down resistor connected to ground (i.e. the switch integrated in the SIM connector is open) SIM card present: the GPIO5 signal is forced high by the pull-up resistor connected to V_INT (i.e. the switch integrated in the SIM connector is closed) 3G.G2-HW-10002-A2 Preliminary System description Page 43 of 159 LISA-U series - System Integration Manual Figure 21: SIM interface application circuit Reference Description Part Number - Manufacturer C1, C2, C3, C4 33 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H330JZ01 - Murata C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2, D3 Low capacitance ESD protection R1 R2 J1 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W SIM Card Holder Table 21: Example of components for SIM card connection USB0002RP or USB0002DP - AVX RC0402JR-071KL - Yageo Phycomp RC0402JR-07470KL- Yageo Phycomp Various Manufacturers, CCM03-3013LFT R102 - C&K Components When connecting the module to an SIM connector, perform the following steps on the application board:

Bypass digital noise via a 100 nF capacitor (e.g. Murata GRM155R71C104K) on the SIM supply (VSIM) To prevent RF coupling in case the module RF antenna is placed closer than 10 - 30 cm from the SIM card holder, connect a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) at each SIM signal (VSIM, SIM_CLK, SIM_IO, SIM_RST) to ground near the SIM connector Mount very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) near the SIM card connector Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface

(27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines): always route the connections to keep them as short as possible 1.8.1 (U)SIM functionality The following SIM services are supported:

Abbreviated Dialing Numbers (ADN) Fixed Dialing Numbers (FDN) Last Dialed Numbers (LDN) Service Dialing Numbers (SDN) USIM Application Toolkit (USAT) R99 is supported. 3G.G2-HW-10002-A2 Preliminary System description Page 44 of 159 LISA-U seriesC1SIM CARD HOLDERCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)C2C3C5D2D3C5C6C7C1C2C3SIM Card Bottom View (contacts side)J150VSIM48SIM_IO47SIM_CLK49SIM_RSTC4SW1SW24V_INT51GPIO5R2R1D1 LISA-U series - System Integration Manual 1.9 Serial communication LISA-U series modules provide the following serial communication interfaces where AT command interface and Packet-Switched / Circuit-Switched Data communication are concurrently available:

One asynchronous serial interface (UART) that provides complete RS-232 functionality conforming to ITU-T V.24 Recommendation [4], with limited data rate. The UART interface can be used for firmware upgrade One Inter Processor Communication (IPC) interface that includes a synchronous SPI-compatible interface, with maximum data rate of 26 Mb/s One high-speed USB 2.0 compliant interface, with maximum data rate of 480 Mb/s. The single USB interface implements several logical devices. Each device is a USB communications device class (or USB CDC), that is a composite Universal Serial Bus device class. The USB interface can be used for firmware upgrade The LISA-U series modules are designed to operate as an HSPA wireless modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [4]. A customer application processor connected to the module through one of the interfaces represents the data terminal equipment (DTE). All the interfaces listed above are controlled and operated with:

AT commands according to 3GPP TS 27.007 [5]

AT commands according to 3GPP TS 27.005 [6]

AT commands according to 3GPP TS 27.010 [7]

u-blox AT commands For the complete list of supported AT commands and their syntax refer to the u-blox AT Commands Manual [3]. The following serial communication interfaces can be used for firmware upgrade:

The UART interface, using the RxD and TxD lines only The USB interface, using all the lines provided (VUSB_DET, USB_D+ and USB_D-) To directly enable PC (or similar) connection to the module for firmware upgrade, provide direct access on the application board to the VUSB_DET, USB_D+ and USB_D- lines of the module (or to the RxD and TxD lines). Also provide access to the PWR_ON or the RESET_N pins, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). The following sub-chapters describe the serial interfaces configuration and provide a detailed description of each interface for the application circuits. 1.9.1 Serial interfaces configuration UART, USB and SPI/IPC serial interfaces are available as AT command interface and for Packet-Switched / Circuit-

Switched Data communication. The serial interfaces are configured as described in Table 22 (for information about further settings, please refer to the u-blox AT Commands Manual [3]). 3G.G2-HW-10002-A2 Preliminary System description Page 45 of 159 LISA-U series - System Integration Manual Interface AT Settings Comments UART interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port AT+IPR=115200 Baud rate: 115200 b/s AT+ICF=3,1 Frame format: 8 bits, no parity, 1 stop bit AT&K3 AT&S1 AT&D1 AT&C1 HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise USB interface Enabled 6 CDCs are available, configured as described in the following list:

USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling dedicated port USB5: 2G and BB trace dedicated port USB6: 3G trace dedicated port AT&K3 AT&S1 AT&D1 AT&C1 All LISA-U2 series modules versions except LISA-U200-00 provide an additional CDC:

USB7: SIM Access Profile dedicated port HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise SPI interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port HW flow control enabled DSR line set ON in data mode and set OFF in command mode Upon an ON-to-OFF transition of DTR, the DCE enters online command state and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise AT&K3 AT&S1 AT&D1 AT&C1 Table 22: Default serial interfaces configuration 1.9.2 Asynchronous serial interface (UART) The UART interface is a 9-wire unbalanced asynchronous serial interface that provides AT commands interface, PSD and CSD data communication, firmware upgrade. UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [4]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state. Two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC8T245PW) could be used to provide full RS-232 (9 lines) compatible signal levels. The Texas Instruments chip provides the translation from 1.8 V to 3.3 V, while the Maxim chip provides the necessary RS-232 compatible signal towards the external connector. If a UART interface with only 5 lines is needed, the Maxim 13234E voltage level translator can be used. This chip translates the voltage levels from 1.8 V (module 3G.G2-HW-10002-A2 Preliminary System description Page 46 of 159 LISA-U series - System Integration Manual side) to the RS-232 standard. For detailed electrical characteristics refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The LISA-U series modules are designed to operate as an HSPA wireless modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [4]. A customer application processor connected to the module through the UART interface represents the data terminal equipment (DTE). The signal names of the LISA-U series modules UART interface conform to the ITU-T V.24 Recommendation [4]. UART interfaces include the following lines:

Name DSR RI DCD DTR RTS CTS TxD RxD GND Description Data set ready Ring Indicator Data carrier detect Data terminal ready Ready to send Clear to send Transmitted data Received data Ground Table 23: UART interface signals Remarks Module output Circuit 107 (Data set ready) in ITU-T V.24 Module output Circuit 125 (Calling indicator) in ITU-T V.24 Module output Circuit 109 (Data channel received line signal detector) in ITU-T V.24 Module input Circuit 108/2 (Data terminal ready) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control input Circuit 105 (Request to send) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control output Circuit 106 (Ready for sending) in ITU-T V.24 Module data input Circuit 103 (Transmitted data) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module data output Circuit 104 (Received data) in ITU-T V.24 The UART interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. 1.9.2.1 UART features All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands

(see u-blox AT Commands Manual [3], &K, +IFC, \Q AT commands): hardware flow control (RTS/CTS), software flow control (XON/XOFF), or none flow control. Hardware flow control is enabled by default. The following baud rates can be configured using AT commands:

1200 b/s 2400 b/s 3G.G2-HW-10002-A2 Preliminary System description Page 47 of 159 LISA-U series - System Integration Manual 4800 b/s 9600 b/s 19200 b/s 38400 b/s 57600 b/s 115200 b/s 230400 b/s 460800 b/s The default baud rate is 115200 b/s. Autobauding is not supported. The frame format can be:

8N1 (8 data bits, No parity, 1 stop bit) 8E1 (8 data bits, even parity, 1 stop bit) 8O1 (8 data bits, odd parity, 1 stop bit) 8N2 (8 data bits, No parity, 2 stop bits) 7E1 (7 data bits, even parity, 1 stop bit) 7O1 (7 data bits, odd parity, 1 stop bit) The default frame configuration with fixed baud rate is 8N1, described in the Figure 22. Figure 22: UART default frame format (8N1) description 1.9.2.2 UART signal behavior (AT commands interface case) See Table 5 for a description of operating modes and states referred to in this section. At the switch on of the module, before the initialization of the UART interface, as described in the power-on sequence reported in the Figure 18, each pin is first tri-stated and then is set to its relative internal reset state that is reported in the pin description table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. At the end of the boot sequence, the UART interface is initialized, the module is by default in active mode and the UART interface is enabled. The configuration and the behavior of the UART signals after the boot sequence are described below. For a complete description of data and command mode please refer to u-blox AT Commands Manual [3]. 3G.G2-HW-10002-A2 Preliminary System description Page 48 of 159 D0D1D2D3D4D5D6D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer,8N1 LISA-U series - System Integration Manual RxD signal behavior The module data output line (RxD) is set by default to OFF state (high level) at UART initialization. The module holds RxD in OFF state until no data is transmitted by the module. TxD signal behavior The module data input line (TxD) is set by default to OFF state (high level) at UART initialization. The TxD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TxD input. CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled (for more details please refer to u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT command) the CTS line indicates when the UART interface is enabled (data can be sent and received): the module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE (refer to chapter 1.9.2.3 for the complete description). If the hardware flow control is not enabled, the CTS line is always held in the ON state after UART initialization. In case of hardware flow control enabled, when CTS line is ON the UART is enabled and the module is in active mode. Instead, CTS line to OFF doesnt necessary mean that the module is in idle-mode, but only that the UART is not enabled (the module could be forced to stay in active-mode for instance by USB). When the power saving configuration is enabled and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in idle-mode wont be a valid communication character (refer to chapter 1.9.2.3 for the complete description). When the MUX protocol is active on UART interface, the CTS line state is mapped to FCon / FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator. For more details please refer to Mux Implementation Application Note [15]. RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The RTS line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled (for more details please refer to u-blox AT Commands Manual [3] AT&K, AT\Q, AT+IFC command description) the RTS line is monitored by the module to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to OFF state, any on-going data transmission from the module is immediately interrupted or any subsequent transmission forbidden until the RTS line changes to ON state. The DTE must be able to still accept a certain number of characters after the RTS line has been set to OFF state: the module guarantees the transmission interruption within 2 characters from RTS state change. If AT+UPSV=2 is set and HW flow control is disabled, the RTS line is monitored by the module to manage the power saving configuration:

When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module is forced to active-mode; after 20 ms from the transition the switch is completed and data can be received without loss. The module cant enter idle-mode and the UART is keep enabled as long as the RTS input line is held in the ON state 3G.G2-HW-10002-A2 Preliminary System description Page 49 of 159 LISA-U series - System Integration Manual If RTS is set to OFF state by the DTE, the module automatically enters idle-mode whenever possible as in the AT+UPSV=1 configuration (cyclic idle/active mode), but UART is disabled (held in low power mode) For more details please refer to chapter 1.9.2.3 and u-blox AT Commands Manual [3], AT+UPSV command. DSR signal behavior If AT&S0 is set, the DSR module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&S1 is set, the DSR module output line is set by default to OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode. The above behavior is valid for both Packet-Switched and Circuit-Switched Data transfer. DTR signal behavior The DTR module input line is set by default to OFF state (high level) at UART initialization. The DTR line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status depends on the AT command configuration (see u-blox AT Commands Manual [3], &D AT command). DCD signal behavior If AT&C0 is set, the DCD module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&C1 is set, the DCD module output line is set by default to OFF state (high level) at UART initialization. The DCD line is then set by the module in accordance with the carrier detect status: ON if the carrier is detected, OFF otherwise. In case of voice call DCD is set to ON state when the call is established. For a data call there are the following scenarios:

GPRS data communication: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. Please note that the DCD ON is not related to the context activation but with the data mode CSD data call: To establish a data call the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE In case of a voice call DCD is set to ON state on all the serial communication interfaces supporting the AT command interface. (including MUX virtual channels, if active). DCD is set to ON during the execution of a command requiring input data from the DTE (all the commands where a prompt is issued; see AT commands +CMGS, +CMGW, +USOWR, +USODL,

+UDWNFILE in u-blox AT Commands Manual [3]). The DCD line is set to ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed. 3G.G2-HW-10002-A2 Preliminary System description Page 50 of 159 LISA-U series - System Integration Manual DCD line is kept to ON state even during the online command state to indicate that the data call is still established even if suspended, while if the module enters command mode DSR line is set to OFF state. For more details refer to DSR signal behavior description. In case of scenarios for which the DCD line setting is requested for different reasons (e.g. SMS texting during online command state), the DCD line changes to guarantee the correct behavior for all the scenarios. For instance, in case of SMS texting in online command state, if the data call is released, the DCD line will be kept to ON till the SMS command execution is completed (even if the data call release would request the DCD setting to OFF). RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from OFF state to ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 23), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 23: RI behavior during an incoming call The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 24), if the feature is enabled by the proper AT command (please refer to u-blox AT Commands Manual [3], AT+CNMI command). RI OFF RI OFF RI ON RI ON 1s 1s 0 0 SMS arrives SMS Figure 24: RI behavior at SMS arrival time [s]

time [s]

This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. In case of SMS arrival, if several events occur coincidently or in quick succession each event triggers the RI line independently, although the line will not be deactivated between each event. As a result, the RI line may stay to ON for more than 1 s. If an incoming call is answered within less than 1 s (with ATA or if autoanswering is set to ATS0=1) than the RI line will be set to OFF earlier. As a result:

RI line monitoring cant be used by the DTE to determine the number of received SMSes. 3G.G2-HW-10002-A2 Preliminary System description Page 51 of 159 1stime [s]151050RI ONRI OFFCall incomes1stime [s]151050RI ONRI OFFCall incomes LISA-U series - System Integration Manual In case of multiple events (incoming call plus SMS received), the RI line cant be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with the proper commands. 1.9.2.3 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description please refer to u-blox AT Commands Manual [3], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible, otherwise the active-mode is maintained by the module. The AT+UPSV command sets the module power saving configuration, but also configures the UART behavior in relation to the power saving configuration. The conditions for the module entering idle-mode also depend on the UART power saving configuration. The different power saving configurations that can be set by the AT+UPSV command are described in the following subchapters and are summarized in Table 24. For more details on the command description please refer to u-blox AT commands Manual [3]. AT+UPSV HW flow control RTS line Communication during idle-mode and wake up 0 0 0 0 1 1 1 1 2 2 2 2 Enabled (AT&K3) Enabled (AT&K3) Disabled (AT&K0) Disabled (AT&K0) ON OFF ON OFF Enabled (AT&K3) ON Enabled (AT&K3) OFF Disabled (AT&K0) ON Disabled (AT&K0) OFF Enabled (AT&K3) Enabled (AT&K3) Disabled (AT&K0) ON OFF ON Disabled (AT&K0) OFF Data sent by the DTE will be correctly received by the module. Data sent by the module will be buffered by the module and will be correctly received by the DTE when it will be ready to receive data (i.e. RTS line will be ON). Data sent by the DTE will be correctly received by the module. Data sent by the module will be correctly received by the DTE if it is ready to receive data, otherwise data will be lost. Data sent by the DTE will be buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module will be buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). If the module is in idle-mode, when a low-to-high transition occurs on the TxD input line, the module switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode

(i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Data sent by the module will be correctly received by the DTE if it is ready to receive data, otherwise data will be lost. Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. The module is forced in active-mode and it cant enter idle-mode until RTS line is set to OFF state. When a high-to-low (i.e. OFF-to-ON) transition occurs on the RTS input line, the module switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. When a low-to-high transition occurs on the TxD input line, the UART is re-enabled and if the module was in idle-mode it switches from idle-mode to active-mode after 20 ms: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode (i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Table 24: UART and power-saving summary AT+UPSV=0: power saving disabled, fixed active-mode The module doesnt enter idle-mode and the UART interface is enabled (data can be sent and received): the CTS line is always held in the ON state after UART initialization. This is the default configuration. 3G.G2-HW-10002-A2 Preliminary System description Page 52 of 159 LISA-U series - System Integration Manual AT+UPSV=1: power saving enabled, cyclic idle/active mode The module automatically enters idle-mode whenever possible, if a voice or data call (2G or 3G) is not enabled, and periodically wakes up from idle-mode to active-mode to monitor the paging channel of the current base station (paging block reception), according to 2G or 3G discontinuous reception (DRX) specification. The time period between two paging receptions is defined by the current base station (i.e. by the network):

If the module is registered with a 2G network, the paging reception period can vary from ~0.47 s (DRX = 2, i.e. 2 x 51 2G-frames) up to ~2.12 s (DRX = 9, i.e. 9 x 51 2G-frames) If the module is registered with a 3G network, the paging reception period can vary from 0.64 s (DRX = 6, i.e. 26 3G-frames) up to 5.12 s (DRX = 9, i.e. 29 3G-frames). The UART interface is automatically disabled whenever possible, if data has not been received or sent by the UART for the timeout configured by the +UPSV AT command, and is periodically enabled to receive or send data. When the module is in idle-mode, the UART interface is always disabled. When the module is in active-mode or connected-mode, the UART interface is automatically disabled to reduce the consumed power, if data has not been received or sent by the UART for the configured timeout. The time period of the UART enable/disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network:

2G: the UART is enabled synchronously to paging receptions, but not necessarily at every paging reception

(to reduce the consumed power): the UART interface is enabled for 20 ms concurrently to a paging reception, and then, as data has not been received or sent, the UART is disabled until the first paging reception that occurs after a timeout of 2.0 s, and therefore the interface is enabled again 3G: the UART is enabled asynchronously to paging receptions: the UART interface is enabled for 20 ms, and then, as data has not been received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again Not registered: when the module is not registered with a network, the UART interface is enabled for 20 ms, and then, if data has not been received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again When UART interface is disabled, data transmitted by the DTE will be lost if hardware flow control is disabled. If hardware flow control is enabled, data will be buffered by the DTE and will be correctly received by the module when UART interface is enabled again. When UART interface is enabled, data can be received. When a character is received, it forces the UART interface to stay enabled for a longer time and it forces the module to stay in the active-mode for a longer time. The active-mode duration depends by:

Network parameters, related to the time interval for the paging block reception (minimum of ~11 ms) Duration of UART enable time in absence of data reception (20 ms) Time period from the last data received at the serial port during the active-mode: the module doesnt enter idle-mode until a timeout expires. This timeout is configured by the second parameter of the +UPSV AT command, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms

= 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s) Every subsequent character received during the active-mode, resets and restarts the timer; hence the active-

mode duration can be extended indefinitely. The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can be sent and received), if HW flow control is enabled, as illustrated in Figure 25. 3G.G2-HW-10002-A2 Preliminary System description Page 53 of 159 LISA-U series - System Integration Manual Figure 25: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level) AT+UPSV=2: power saving enabled and controlled by the RTS line If the RTS line is set to OFF by the DTE the module is allowed to enter idle-mode as for UPSV=1 case. Instead, the UART is disabled as long as RTS line is set to OFF. If the RTS line is set to ON by the DTE the module is not allowed to enter idle-mode and the UART is kept enabled until the RTS line is set to OFF. When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module switches from idle-mode to active-mode in 20 ms. This configuration can only be enabled with the module HW flow control disabled. When the RTS line is set to OFF by the DTE, the timeout to enter idle-mode from the last data received at the serial port during the active-mode is the one previously set with the AT+UPSV=1 configuration or it is the default value. Since HW flow control is disabled, the CTS line is always set to ON by the module. If the module must transmit some data (e.g. URC), the UART is temporarily enabled even if the RTS line is set to OFF; UART wake-up in case of RTS line set to OFF is also possible via data reception (as described in the following). If the USB is connected and active, the module is forced to stay in active-mode, therefore +UPSV=1 and

+UPSV=2 modes are overruled, but in any case they have effect on the UART behavior (they configure UART power saving mode, when it is enabled/disabled). Wake up from idle-mode to active-mode via data reception If data is transmitted by the DTE during the module idle-mode, it will be lost (not correctly received by the module) in the following cases:

+UPSV=1 with hardware flow control disabled

+UPSV=2 with hardware flow control disabled and RTS line set to OFF When the module is in idle-mode, the TxD input line of the module is always configured to wake up the module from idle-mode to active-mode via data reception: when a low-to-high transition occurs on the TxD input line, it causes the wake-up of the system. The module switches from idle-mode to active-mode within 20 ms from the first data reception: this is the wake up time of the module. As a consequence, the first character sent when the module is in idle-mode (i.e. the wake up character) wont be a valid communication character because it cant be recognized, and the recognition of the subsequent characters is guaranteed only after the complete wake-up (i.e. after 20 ms). Figure 26 and Figure 27 show an example of common scenarios and timing constraints:

HW flow control set in the DCE, and no HW flow control set in the DTE, needed to see the CTS line changing on DCE 3G.G2-HW-10002-A2 Preliminary System description Page 54 of 159 time [s]CTS ONCTS OFFUART disabled2G/3G: 20 msUART enabled2G/3G: ~9.2 s (default)UART enabledData input2G: 2.10-3.75 s3G: 2.50 s LISA-U series - System Integration Manual Power saving configuration is active and the timeout from last data received to idle-mode start is set to 2000 frames (AT+UPSV=1,2000) Figure 26 shows the case where DCE is in idle-mode and a wake-up is forced. In this scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE will return to idle-mode when the timeout from last data received expires. (2000 frames without data reception). Figure 26: Wake-up via data reception without further communication Figure 27 shows the case where in addition to the wake-up character further (valid) characters are sent. The wake up character wakes-up the DCE. The other characters must be sent after the wake up time of 20 ms. If this condition is satisfied, the characters are recognized by the DCE. The DCE is allowed to re-enter idle-mode after 2000 GSM frames from the latest data reception. Figure 27: Wake-up via data reception with further communication LISA-U2 series modules dont wake-up from idle-mode to active-mode via data reception by TxD input line, if HW flow control is enabled. The wake-up via data reception feature cant be disabled. 3G.G2-HW-10002-A2 Preliminary System description Page 55 of 159 CTS OFFCTSONActive mode is held for 2000 GSM frames (~9.2 s)time Wake up time: up to 15.6 mstime TxD module inputWake up character Not recognized by DCECTS OFFCTSONActive mode is held for 2000 GSM frames (~9.2s) after the last data receivedtime Wake up time: up to 15.6 mstime TxD module inputWake up character Not recognized by DCEValid characters Recognized by DCE LISA-U series - System Integration Manual The wake-up via data reception feature can be used in both +UPSV=1 and +UPSV=2 case (when RTS line is set to OFF). In command mode, if HW flow control is not implemented by the DTE, the DTE must always send a dummy AT to the module before each command line: the first character will not be ignored if the module is in active-mode (i.e. the module will reply OK), or it will represent the wake up character if the module is in idle-mode (i.e. the module wont reply). No dummy AT is required from the DTE during connected-mode since the module continues to be in active-mode and doesnt need to be woken-up. Furthermore in data mode a dummy AT would affect the data communication. 1.9.2.4 UART application circuits Providing the full RS-232 functionality (using the complete V.24 link) For complete RS-232 functionality conforming to ITU Recommendation [4] in DTE/DCE serial communication, the complete UART interface of the module (DCE) must be connected to a 1.8V DTE as described in Figure 28. Figure 28: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) 3G.G2-HW-10002-A2 Preliminary System description Page 56 of 159 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP LISA-U series - System Integration Manual If a 3.0 V Application Processor is used, appropriate voltage translators must be utilized, as described in Figure 29. Figure 29: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1, U2 Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 25: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) 3G.G2-HW-10002-A2 Preliminary System description Page 57 of 159 4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2B3A3VCCBVCCAUnidirectionalVoltage TranslatorC3C43V0DIR1DIR3OEB2 A2B4A4DIR4DIR2 LISA-U series - System Integration Manual Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link) If the functionality of the DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, the circuit with a 1.8 V Application Processor should be implemented as described in Figure 30:

Connect the module DTR input line to GND, since the module requires DTR active (low electrical level) Leave DSR, DCD and RI lines of the module unconnected and floating Figure 30: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 31. Figure 31: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 26: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) If only TxD, RxD, RTS and CTS lines are provided, as implemented in Figure 30 and in Figure 31, the procedure to enable power saving depends on the HW flow-control status. If HW flow-control is enabled (AT&K3, that is 3G.G2-HW-10002-A2 Preliminary System description Page 58 of 159 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 0 TPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR3DIR2OEDIR1VCCB2 A2B4A4DIR4 LISA-U series - System Integration Manual the default setting) power saving will be activated by AT+UPSV=1. Through this configuration, when the module is in idle-mode, data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active-mode is entered. If the HW flow-control is disabled (AT&K0), the power saving can be enabled by AT+UPSV=2. The module is in idle-mode until a high-to-low (i.e. OFF-to-ON) transition on the RTS input line will switch the module from idle-mode to active-mode in 20 ms. The module will be forced in active-mode if the RTS input line is held in the ON state. Providing the TxD and RxD lines only (not using the complete V24 link) If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available, the circuit with a 1.8 V Application Processor should be implemented as described in Figure 32:

Connect the module CTS output line to the module RTS input line, since the module requires RTS active

(low electrical level) if HW flow-control is enabled (AT&K3, that is the default setting), and CTS is active (low electrical level) when the module is in active mode, the UART interface is enabled and the HW flow-control is enabled Connect the module DTR input line to GND, since the module requires DTR active (low electrical level) Leave DSR, DCD and RI lines of the module unconnected and floating Figure 32: UART interface application circuit with partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8V DTE) 3G.G2-HW-10002-A2 Preliminary System description Page 59 of 159 TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND0 0 TPTP0 TPTP If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 33. LISA-U series - System Integration Manual Figure 33: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 27: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) If only TxD and RxD lines are provided, as described in Figure 32 and in Figure 33, and HW flow-control is disabled (AT&K0), the power saving will be enabled by AT+UPSV=1. The module enters active-mode 20 ms after a low-to-high transition on the TxD input line, and the recognition of the subsequent characters is guaranteed until the module is in active-mode. Data delivered by the DTE can be lost using this configuration and the following settings:

o HW flow-control enabled in the module (AT&K3, that is the default setting) o Module power saving enabled by AT+UPSV=1 o HW flow-control disabled in the DTE In this case the first character sent when the module is in idle-mode will be a wake-up character and wont be a valid communication character (refer to chapter 1.9.1.3 for the complete description). If power saving is enabled the application circuit with the TxD and RxD lines only is not recommended. During command mode the DTE must send to the module a wake-up character or a dummy AT before each command line (refer to chapter 1.9.1.3 for the complete description), but during data mode the wake-up character or the dummy AT would affect the data communication. 3G.G2-HW-10002-A2 Preliminary System description Page 60 of 159 4V_INTTxDApplication Processor(3.0V DTE)RxDDTRDSRRIDCDGNDLISA-U series (DCE)15TXD12DTR16RXD9DSR10RI11DCDGND0 0 TPTP1V8B1 A1GNDU1VCCBVCCAUnidirectionalVoltage TranslatorC1C23V0DIR1DIR2OEVCCB2 A2RTSCTS13RTS14CTS0 TPTP LISA-U series - System Integration Manual Additional considerations If the module USB interface is connected to the application processor, it is highly recommended to provide direct access to RxD, TxD, CTS and RTS lines of the module for execution of firmware upgrade over UART and for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 series resistor must be mounted on each line to detach the module pin from any other connected device. Otherwise, if the USB interface is not connected to the application processor, it is highly recommended to provide direct access to VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). If the UART interface is not used, all the UART interface pins can be left unconnected, but it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade and for debug purpose. Any external signal connected to the UART interface must be tri-stated when the module is in power-

down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.9.3 USB interface LISA-U series modules provide a high-speed USB interface at 480 Mb/s compliant with the Universal Serial Bus Revision 2.0 specification [8]. It acts as a USB device and can be connected to any USB host such as a PC or other Application Processor. The USB-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U series modules emulate all serial control logical lines. If the logical DTR line isn't enabled by the USB host, the LISA-U1xx-00 modules dont answer to AT commands by the USB interface. Name Description VUSB_DET USB_D+

USB detect input USB Data Line D+

USB_D-

USB Data Line D-

Table 28: USB pins Remarks Apply 5 V typical to enable USB 90 nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. 90 nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [8] are part of the USB pad driver and need not be provided externally. The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points. 3G.G2-HW-10002-A2 Preliminary System description Page 61 of 159 LISA-U series - System Integration Manual 1.9.3.1 USB features LISA-U series modules simultaneously support 6 USB CDC (Communications Device Class) that assure multiple functionalities to the USB physical interface. The 6 available CDCs are configured as described in the following list:

USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling dedicated port USB5: 2G and BB trace dedicated port USB6: 3G trace dedicated port All LISA-U2 series modules versions except LISA-U200-00 provide an additional USB CDC:

USB7: SIM Access Profile dedicated port The user can concurrently use AT command interface on one CDC and Packet-Switched / Circuit-Switched Data communication on another CDC. All LISA-U2 series modules versions except LISA-U200-00 support audio over USB capabilities: Audio Device Class is implemented to provide an audio streaming interface, which transfers audio data over isochronous pipes. USB drivers for Windows XP, Windows Vista, Windows 7, Windows CE 6, Windows EC 7 and Windows Mobile 6.5 are available. LISA-U1 / LISA-U2 series modules are compatible with standard Linux/Android USB kernel drivers. LISA-U series module identifies itself by its VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor. VID and PID of LISA-U series modules are the following:

VID = 0x1546 PID = 0x1101 for LISA-U1 series PID = 0x1102 for LISA-U2 series If the USB interface of LISA-U series module is connected to the host before the module switch on, or if the module is reset with the USB interface connected to the host, the VID and PID are automatically updated runtime, after the USB detection. First, VID and PID are the following:

VID = 0x058B PID = 0x0041 Then, after a time period (~5 s), VID and PID are updated to the following:

VID = 0x1546 PID = 0x1101 for LISA-U1 series PID = 0x1102 for LISA-U2 series 1.9.3.2 USB and power saving If power saving is enabled by AT command (AT+UPSV=1 or AT+UPSV=2), the LISA-U series module automatically enters the USB suspended state when the device has observed no bus traffic for a specified period (refer to the Universal Serial Bus Revision 2.0 specification [8]). In suspended state, the module maintains any internal status as USB device, including its address and configuration. In addition, the module enters the suspended state when the hub port it is attached to is disabled: this is referred to as USB selective suspend. The module exits suspend mode when there is bus activity. LISA-U series module is capable of USB remote wake-up signaling: i.e. may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake-up. This notifies the host that it 3G.G2-HW-10002-A2 Preliminary System description Page 62 of 159 LISA-U series - System Integration Manual should resume from its suspended mode, if necessary, and service the external event that triggered the suspended USB device to signal the host. Remote wake-up is accomplished using electrical signaling described in the Universal Serial Bus Revision 2.0 specification [8]. When the USB enters suspended state, the average VCC module current consumption of LISA-U series module is

~400 A higher then when the USB is not attached to a USB host. If power saving is disabled by AT+UPSV=0 and the LISA-U series module is attached to a USB host as USB device, is configured and is not suspended, the average VCC module current consumption in fixed active mode is increased to ~40 mA. 1.9.3.3 USB application circuit Since the module acts as a USB device, the USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host. The USB interface is enabled only when a valid voltage as USB supply is detected by the VUSB_DET input. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. USB pull-up or pull-down resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [8] are part of the USB pad driver and do not need to be externally provided. External series resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [8] are also integrated: characteristic impedance of USB_D+ and USB_D- lines is specified by the USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if the PCB layout is not optimal, especially when the USB signaling lines are very long. Figure 34: USB Interface application circuit Reference D1, D2, D3 C2 Description Part Number - Manufacturer Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Table 29: Component for USB application circuit If the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debug purpose: testpoints can be added on the lines to accommodate the access. Otherwise, if the USB interface is connected to the application processor, it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade over UART and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the 3G.G2-HW-10002-A2 Preliminary System description Page 63 of 159 LISA-U series VBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GNDC1USB DEVICE CONNECTORD1D2D3 LISA-U series - System Integration Manual DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected, but it is highly recommended to provide direct access to the lines for execution of firmware upgrade and for debug purpose. 1.9.4 SPI interface SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration. The SPI-compatible synchronous serial interface cannot be used for FW upgrade. The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and SPI_MISO) and a clock signal (SPI_SCLK). LISA-U series modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard 3-wire SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface. The purpose of the IPC interface is to achieve high speed communication (up to 26 Mb/s) between two processors following the same IPC specifications: the module baseband processor and an external processor. High speed communication is possible only if both sides follow the same Inter Processor Communication (IPC) specifications. Name SPI_MISO Description SPI Data Line. Master Input, Slave Output SPI_MOSI SPI Data Line. Master Output, Slave Input SPI_SCLK SPI Serial Clock. Master Output, Slave Input Remarks Module Output. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Module Input. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Internal active pull-up to V_INT (1.8 V) enabled. Module Input. Idle low (CPOL=0). Up to 26 MHz supported. Internal active pull-down to GND enabled. Module Input. Idle low. Internal active pull-down to GND enabled. SPI_MRDY SPI_SRDY SPI Master Ready to transfer data control line. Master Output, Slave Input SPI Slave Ready to transfer data control line. Master Input, Slave Output Module Output. Idle low. Table 30: SPI interface signals The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002 varistor array) on the lines connected to these pins, close to accessible points. 3G.G2-HW-10002-A2 Preliminary System description Page 64 of 159 LISA-U series - System Integration Manual 1.9.4.1 IPC communication protocol overview The module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration. The SPI-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U series modules emulate all serial logical lines: the transmission and the reception of the data are similar to an asynchronous device. Two additional signals (SPI_MRDY and SPI_SRDY) are added to the SPI lines to communicate the state of readiness of the two processors: they are used as handshake signals to implement the data flow. The function of the SPI_MRDY and SPI_SRDY signals is twofold:

For transmitting data the signal indicates to the data receiver that data is available to be transmitted For receiving data the signal indicates to the transmitter that the receiver is ready to receive data Due to this setup it is possible to use the control signals as interrupt lines waking up the receiving part when data is available for transfer. When the handshaking has taken place, the transfer occurs just as if it were a standard SPI interface without chip select functionality (i.e. one master - one slave setup). SPI_MRDY is used by the application processor (i.e. the master) to indicate to the module baseband processor

(i.e. the slave) that it is ready to transmit or receive (IPC master ready signal), and can also be used by the application processor to wake up the module baseband processor if it is in idle-mode. SPI_SRDY line is used by the module baseband processor (i.e. the slave) to indicate to the application processor

(i.e. the master) that it is ready to transmit or receive (IPC slave ready signal), and can also be used by the module baseband processor to wake up the application processor if it is in hibernation. Figure 35: IPC Data Flow: SPI_MRDY and SPI_SRDY line usage combined with the SPI protocol For the correct implementation of the SPI protocol, the frame size is known by both sides before a packet transfer of each packet. The frame is composed by a header with fixed size (always 4 bytes) and a payload with variable length (must be a multiple of 4 bytes). The same amount of data is exchanged in both directions simultaneously. Both sides set their readiness lines

(SPI_MRDY / SPI_SRDY) independently when they are ready to transfer data. For the correct transmission of the data the other side must wait for the activating interrupt to allow the transfer of the other side. The master starts the clock shortly after SPI_MRDY and SPI_SRDY are set to active. The number of clock periods sent by the master is exactly that one of the frame-size to be transferred. The SPI_SRDY line will be set low after the master sets the clock line to idle state. The SPI_MRDY line is also set inactive after the clock line is set idle, but in case of a big transfer containing multiple packets, the SPI_MRDY line stays active. 1.9.4.2 IPC communication and power saving If power saving is enabled by AT command (AT+UPSV=1 or AT+UPSV=2), the LISA-U series module automatically enters idle-mode when the master indicates that it is not ready to transmit or receive by the SPI_MRDY signal, or when the LISA-U series module itself doesnt transfer data. 3G.G2-HW-10002-A2 Preliminary System description Page 65 of 159 SPI_MRDYSPI_SRDYDATA_EXCHANGESPI_MOSISPI_MISOHeader DataSPI_SCLK LISA-U series - System Integration Manual 1.9.4.3 IPC communication examples In the following, three IPC communication scenarios are described:

Slave initiated data transfer, with a sleeping master Master initiated data transfer, with a sleeping slave Slave ended data transfer Slave initiated transfer with a sleeping master SPI_MRDY SPI_SRDY DATA EXCHG 2 1 3 Header Data 4 5 Header Figure 36: Data transfer initiated by LISA-U series module (slave), with a sleeping application processor (master) When the master is sleeping (idle-mode), the following actions happen:

1. The slave indicates the master that is ready to send data by activating SPI_SRDY 2. When the master becomes ready to send, it signalizes this by activating SPI_MRDY 3. The master activates the clock and the two processors exchange the communication header and data 4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK 5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3 Master initiated transfer with a sleeping slave SPI_MRDY SPI_SRDY DATA EXCHG 2 3 1 4 5 Header Data Header Figure 37: Data transfer initiated by application processor (master) with a sleeping LISA-U series module (slave) When the slave is sleeping (idle-mode), the following actions happen:

1. The Master wakes the slave by setting the SPI_MRDY line active 2. As soon as the slave is awake, it signals it by activating SPI_SRDY 3. The master activates the clock and the two processors exchange the communication header and data 3G.G2-HW-10002-A2 Preliminary System description Page 66 of 159 LISA-U series - System Integration Manual 4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK 5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock is active, all data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3 Slave ended transfer SPI_MRDY SPI_SRDY 4 1 5 2 3 DATA EXCHG Header Data Figure 38: Data transfer terminated and then restarted by LISA-U series module (slave) Starting from the state where data transfer is ongoing, the following actions will happen:

1. 2. In case of the last transfer, the master will lower its SPI_MRDY line. After the data-transfer is finished the line must be low. If the slave has already set its SPI_SRDY line, the master must raise its line to initiate the next transfer (slave-waking-procedure) If the data has been exchanged, the slave will deactivate SPI_SRDY to process the received information. This is the normal behavior 3. The slave will indicate the master that is ready to send data by activating SPI_SRDY 4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional, when SPI_MRDY is low before 5. The slave indicates immediately after a transfer termination that it is ready to start transmission again. In this case the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or low: the master has only to ensure that the SPI_SRDY change will be detected correctly via interrupt For more details regarding IPC communication protocol please refer to SPI Application Note [18]. 1.9.4.4 IPC application circuit SPI_MOSI is the data line input for the module since it runs as SPI slave: it must be connected to the data line output (MOSI) of the application processor that runs as an SPI master. SPI_MISO is the data line output for the module since it runs as SPI slave: it must be connected to the data line input (MISO) of the application processor that runs as an SPI master. SPI_SCLK is the clock input for the module since it runs as SPI slave: it must be connected to the clock line output (SCLK) of the application processor that runs as an SPI master. SPI_MRDY is an input for the module able to detect an external interrupt which comes from the application processor. SPI_SRDY is an output for the module, and the application processor should be able to detect an external interrupt which comes from the module on its connected pin. Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. 3G.G2-HW-10002-A2 Preliminary System description Page 67 of 159 LISA-U series - System Integration Manual Figure 39: IPC Interface application circuit If direct access to the USB or the UART interfaces of the module is not provided, it is recommended to provide direct access to the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY lines of the module for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 series resistor must be mounted on each line to detach the module pin from any other connected device. If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins can be left unconnected. Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in power-

down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.9.5 MUX Protocol (3GPP 27.010) LISA-U series modules have a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer Protocol [7], available either on the UART or on the SPI physical link. The USB interface doesnt support the multiplexer protocol. This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART or SPI): the user can concurrently use AT command interface on one MUX channel and Packet-Switched / Circuit-Switched Data communication on another MUX channel. The multiplexer protocol can be used on one serial interface (UART or SPI) at a time. Each session consists of a stream of bytes transferring various kinds of data such as SMS, CBS, PSD, GPS, AT commands in general. This permits, for example, SMS to be transferred to the DTE when a data connection is in progress. The following virtual channels are defined:

Channel 0: control channel Channel 1 5: AT commands /data connection Channel 6: GPS tunneling All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:

Channel 7: SIM Access Profile dedicated port For more details please refer to GSM Mux implementation Application Note [15]. 3G.G2-HW-10002-A2 Preliminary System description Page 68 of 159 LISA-U series(SPI slave)MOSIApplication Processor(SPI master)MISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGND LISA-U series - System Integration Manual 1.10 DDC (I2C) interface 1.10.1 Overview An I2C compatible Display Data Channel (DDC) interface for communication with u-blox GPS receivers is available on LISA-U series modules. The communication between a u-blox wireless module and a u-blox GPS receiver is only provided by this DDC (I2C) interface. Name SCL SDA Description I2C bus clock line I2C bus data line Table 31: DDC pins Remarks Open drain. External pull-up required. Open drain. External pull-up required. The DDC (I2C) interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. u-blox has implemented special features in LISA-U series wireless modules to ease the design effort required for the integration of a u-blox wireless module with a u blox GPS receiver. Combining a u-blox wireless module with a u-blox GPS receiver allows designers to have full access to the GPS receiver directly via the wireless module: it relays control messages to the GPS receiver via a dedicated DDC (I2C) interface. A 2nd interface connected to the GPS receiver is not necessary: AT commands via the UART serial interface of the wireless module allows a fully control of the GPS receiver from any host processor. LISA-U series modules feature embedded GPS aiding that is a set of specific features developed by u-blox to enhance GPS performance, decreasing Time To First Fix (TTFF), thus allowing to calculate the position in a shorter time with higher accuracy. The DDC (I2C) interface of all LISA-U2 series modules versions except LISA-U200-00 can be used to communicate with u-blox GPS receivers and at the same time to control an external audio codec: the LISA-U2 series module acts as an I2C master which can communicate to two I2C slaves as allowed by the I2C bus specifications. Refer to section 1.11.2 for an application circuit with an external audio codec. LISA-U200-00 modules versions dont support an I2C compatible Display Data Channel (DDC) interface for communication with u-blox GPS receivers and dont feature embedded GPS aiding. For more details regarding the handling of the DDC (I2C) interface and the GPS aiding features please refer to u-blox AT Commands Manual [3] (AT+UGPS, AT+UGPRF, AT+UGPIOC commands) and GPS Implementation Application Note [16]. 1.10.2 DDC application circuit The DDC (I2C) interface of LISA-U series modules is used to connect the wireless module to a u-blox GPS receiver:

the communication with the u-blox GPS receiver by DDC (I2C) interface is enabled by the AT+UGPS command

(for more details refer to u-blox AT Commands Manual [3]). The SDA and SCL lines must be connected to the DDC (I2C) interface pins of the u-blox GPS receiver (i.e. the SDA2 and SCL2 pins of the u-blox GPS receiver) on the application board to allow the communication between the wireless module and the u-blox GPS receiver. To be compliant to the I2C bus specifications, the module bus interface pads are open drain output and pull up resistors must be used. Since the pull-up resistors are not mounted on the module, they must be mounted 3G.G2-HW-10002-A2 Preliminary System description Page 69 of 159 LISA-U series - System Integration Manual externally. Resistor values must conform to the I2C bus specifications [9]. If a LISA-U series module is connected by the DDC (I2C) bus to a u-blox GPS receiver (only one device can be connected on the DDC bus), use a pull-up resistor of 4.7 k . Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins. V_INT digital interfaces supply output can be used to provide 1.8 V for the pull-ups

(for detailed electrical characteristics see LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]). DDC Slave-mode operation is not supported, the module can act as master only. Two lines, serial data (SDA) and serial clock (SCL), carry information on the bus. SCL is used to synchronize data transfers, and SDA is the data line. Since both lines are open drain outputs, the DDC devices can only drive them low or leave them open. The pull-up resistor pulls the line up to the supply rail if no DDC device is pulling it down to GND. If the pull-ups are missing, SCL and SDA lines are undefined and the DDC bus will not work. The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus will increase the capacitance. If the bus capacitance is increased, use pull-up resistors with nominal resistance value lower than 4.7 k , to match the I2C bus specifications [9].regarding rise and fall times of the signals. Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 s is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. If the pins are not used as DDC bus interface, they can be left unconnected. LISA-U series modules support these GPS aiding types:

Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GPS aiding features can be used only if the DDC (I2C) interface of the wireless module is connected to the u-blox GPS receivers. The GPIO pins can handle:

GPS receiver power-on/off (GPS supply enable function provided by GPIO2) The wake up from idle-mode when the GPS receiver is ready to send data (GPS data ready function provided by GPIO3) The RTC synchronization signal to the GPS receiver (GPS RTC sharing function provided by GPIO4) LISA-U1xx-00 modules versions dont support the following further features related to GPS functionality:

LISA-U1xx-00 modules versions dont enter idle-mode when the DDC (I2C) interface is enabled by the AT+UGPS command, even if power saving is enabled by the AT+UPSV command o o o LISA-U1xx-00 modules versions dont support GPS data ready and GPS RTC sharing functions LISA-U1xx-00 modules versions dont support AssistNow Autonomous GPS aiding The GPIO2 is by default configured to provide the GPS supply enable function (parameter <gpio_mode> of AT+UGPIOC command set to 3 by default), to enable or disable the supply of the u-blox GPS receiver connected to the wireless module by the AT+UGPS command. The pin is set as Output / High, to switch on the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 1 Output / Low, to switch off the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GPS receiver on the application board. 3G.G2-HW-10002-A2 Preliminary System description Page 70 of 159 LISA-U series - System Integration Manual The GPS supply enable function improves the power consumption of the GPS receiver. When the GPS functionality is not required, the GPS receiver can be completely switched off by the wireless module that is controlled by the application processor with AT commands. The GPIO3 is by default configured to provide the GPS data ready function (parameter <gpio_mode> of AT+UGPIOC command set to 4 by default), to sense when the u-blox GPS receiver connected to the wireless module is ready to send data by the DDC (I2C) interface. The pin will be set as Input, to sense the line status, waking up the wireless module from idle-mode when the u-blox GPS receiver is ready to send data by the DDC (I2C) interface, if the parameter <mode> of +UGPS AT command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GPS data ready function must be connected to the data ready output of the u-blox GPS receiver (i.e. the pin TxD1 of the u-blox GPS receiver) on the application board. The GPS data ready function provides an improvement in the power consumption of the wireless module. When power saving is enabled in the wireless module by the AT+UPSV command and the GPS receiver doesnt send data by the DDC (I2C) interface, the module automatically enters idle-mode whenever possible. With the GPS data ready function the GPS receiver can indicate to the wireless module that it is ready to send data by the DDC (I2C) interface: the GPS receiver can wake up the wireless module if it is in idle-mode, so that data sent by the GPS receiver will not be lost by the wireless module even if power saving is enabled. The GPIO4 is by default configured to provide the GPS RTC sharing function (parameter <gpio_mode> of

+UGPIOC AT command set to 5), to provide an RTC (Real Time Clock) synchronization signal at the power up of the u-blox GPS receiver connected to the wireless module. The pin will be set as Output, to provide an RTC synchronization signal to the u-blox GPS receiver for RTC sharing if the parameter

<mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 32 Output / Low, otherwise (default setting) The pin that provides the GPS RTC sharing function must be connected to the RTC synchronization signal of the u-blox GPS receiver (i.e. the pin EXTINT0 of the u-blox GPS receiver) on the application board. The GPS RTC sharing function provides improved GPS receiver performance, decreasing the Time To First Fix

(TTFF), and thus allowing to calculate the position in a shorter time with higher accuracy. When GPS local aiding is enabled, the wireless module automatically uploads data such as position, time, ephemeris, almanac, health and ionospheric parameter from the GPS receiver into its local memory, and restores this to the GPS receiver at the next power up of the GPS receiver. The application circuit for connecting a LISA-U series wireless module to a u-blox 1.8 V GPS receiver is illustrated in Figure 40. SDA and SCL pins of the LISA-U series wireless module are directly connected to the relative pins of the u-blox 1.8 V GPS receiver, with appropriate pull-up resistors. GPIO3 and GPIO4 pins are directly connected respectively to the TxD1 and EXTINT0 pins of the u-blox 1.8 V GPS receiver to provide GPS data ready and GPS RTC sharing functions. A pull-down resistor is mounted on the GPIO2 line to avoid a switch on of the GPS module when the LISA-U series module is in the internal reset state. The V_BCKP supply output of the LISA-U series wireless module is connected to the V_BCKP backup supply input pin of the GPS receiver to provide the supply for the GPS real time clock and backup RAM when the VCC supply of the wireless module is within its operating range and the VCC supply of the GPS receiver is disabled. This enables the u-blox GPS receiver to recover from a power breakdown with either a Hotstart or a Warmstart

(depending on the duration of the GPS VCC outage) and to maintain the configuration settings saved in the backup RAM. 3G.G2-HW-10002-A2 Preliminary System description Page 71 of 159 LISA-U series - System Integration Manual GPS data ready and GPS RTC sharing functions are not supported by all u-blox GPS receivers HW or ROM/FW versions. Refer to the GPS Implementation Application Note [16] or to the Hardware Integration Manual of the u-blox GPS receivers for the supported features. Figure 40: DDC Application circuit for u-blox 1.8 V GPS receiver Reference Description R1, R2 R3 U1 4.7 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W Part Number - Manufacturer RC0402JR-074K7L - Yageo Phycomp RC0402JR-0747KL - Yageo Phycomp Voltage Regulator for GPS Receiver See GPS Receiver Hardware Integration Manual Table 32: Components for DDC application circuit for u-blox 1.8 V GPS receiver The application circuit for the connection of a LISA-U series wireless module to a u-blox 3.0 V GPS receiver is illustrated in Figure 41. If a u-blox 3 V GPS receiver is used, the SDA, SCL, GPIO3 and GPIO4 pins of the LISA-U series wireless module cannot be directly connected to the u-blox 3 V GPS receiver: a proper I2C-bus Bidirectional Voltage Translator must be used for the SDA and SCL signals, and a general purpose Voltage Translator must be used for the GPIO3 and GPIO4 signals. The V_BCKP supply output of the wireless module can be directly connected to the V_BCKP backup supply input pin of the GPS receiver as in the application circuit for a u-blox 1.8 V GPS receiver. 3G.G2-HW-10002-A2 Preliminary System description Page 72 of 159 Functions not supported by LISA-Uxxx-00 versionsLISA-U seriesR1INOUTGNDGPS LDORegulatorSHDNu-blox1.8 V GPS receiverSDA2SCL2R21V81V8VMAIN1V8U121GPIO2SDASCLC1TxD1EXTINT0GPIO3GPIO446452324VCCR3V_BCKPV_BCKP2Functions not supported by LISA-U200-00 version LISA-U series - System Integration Manual Figure 41: DDC Application circuit for u-blox 3.0 V GPS receiver Reference Description R1, R2, R4, R5 4.7 k Resistor 0402 5% 0.1 W R3 47 k Resistor 0402 5% 0.1 W Part Number - Manufacturer RC0402JR-074K7L - Yageo Phycomp RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1 U2 U3 Voltage Regulator for GPS Receiver See GPS Receiver Hardware Integration Manual I2C-bus Bidirectional Voltage Translator PCA9306DCURG4 - Texas Instruments Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 33: Components for DDC application circuit for u-blox 3.0 V GPS receiver 3G.G2-HW-10002-A2 Preliminary System description Page 73 of 159 LISA-U seriesu-blox3.0 V GPS receiver23GPIO324GPIO41V8B1 A1GNDU3B2A2VCCBVCCAUnidirectionalVoltage TranslatorC4C53V0TxD1EXTINT0R1INOUTGNDGPS LDORegulatorSHDNR2VMAIN3V0U121GPIO246SDA45SCLR4R51V8SDA1 SDA2GNDU2SCL1SCL2VREF1VREF2I2C-bus Bidirectional Voltage Translator4V_INTC1C2C3R3SDA2SCL2VCCFunctions not supported by LISA-Uxxx-00 versionsDIR1DIR22V_BCKPV_BCKPOEFunctions not supported by LISA-U200-00 version LISA-U series - System Integration Manual 1.11 Audio Interface LISA-U120 and LISA-U130 modules provide analog and digital input/output audio interfaces:

Differential analog audio input (MIC_P, MIC_N) and differential analog audio output (SPK_P, SPK_N) 4-wire I2S digital audio interface (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) All LISA-U2 series modules versions except LISA-U200-00 provide two digital input/output audio interfaces:

First 4-wire I2S digital audio interface (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) Second 4-wire I2S digital audio interface (I2S1_CLK, I2S1_RXD, I2S1_TXD and I2S1_WA) Audio signal routing can be controlled by the dedicated AT command +USPM (refer to u-blox AT Commands Manual [3]). This command allows setting the audio path mode, composed by the uplink audio path and the downlink audio path. Each uplink path mode defines the physical input (i.e. the analog or the digital audio input) and the set of parameters to process the uplink audio signal (uplink gains, uplink digital filters, echo canceller parameters). For example the Headset microphone uplink path uses the differential analog audio input with the default parameters for the headset profile. Each downlink path mode defines the physical output (i.e. the analog or the digital audio output) and the set of parameters to process the downlink audio signal (downlink gains, downlink digital filters and sidetone). For example the Mono headset downlink path uses the differential analog audio output with the default parameters for the headset profile. The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in two profiles in the non volatile memory (refer to u-blox AT Commands Manual [3] for Audio parameters tuning commands). 1.11.1 Analog Audio interface LISA-U100, LISA-U110 and LISA-U2 series modules versions dont support analog audio interface. 1.11.1.1 Uplink path (differential analog audio input) The pins related to the differential analog audio input are:

MIC_P / MIC_N: Differential analog audio signal inputs (positive/negative). These two pins are provided with internal series 100 nF capacitors for DC blocking that connect the module pads to the differential input of a Low Noise Amplifier. The LNA output is internally connected to the digital processing system by an integrated sigma-delta analog-to-digital converter The analog audio input is selected when the parameter <main_uplink> in AT+USPM command is set to Headset microphone, Handset microphone or Hands-free microphone: the uplink analog path profiles use the same physical input but have different sets of audio parameters (for more details please refer to u-blox AT Commands Manual [3], AT+USPM, AT+UMGC, AT+UUBF, AT+UHFP commands). There is no microphone supply pin available on the module: an external low noise LDO voltage regulator should be added to provide a proper supply for a microphone. Detailed electrical characteristics of the differential analog audio input can be found in the LISA-U1 series Data Sheet [1]. 3G.G2-HW-10002-A2 Preliminary System description Page 74 of 159 LISA-U series - System Integration Manual 1.11.1.2 Downlink path (differential analog audio output) The pins related to the differential analog audio output are:

SPK_P / SPK_N: Differential analog audio signal output (positive/negative). These two pins are internally directly connected to the differential output of a low power audio amplifier, for which the input is internally connected to the digital processing system by to an integrated digital-to-analog converter The analog audio output is selected when the parameter <main_downlink> in AT+USPM command is set to Normal earpiece, Mono headset or Loudspeaker: the downlink analog path profiles use the same physical output but have different sets of audio parameters (for more details please refer to u-blox AT Commands Manual [3], AT+USPM, AT+USGC, AT+UDBF, AT+USTN commands). The differential analog audio output can be directly connected to a headset earpiece or handset earpiece but is not able to drive an 8 speaker. Detailed electrical characteristics of the differential audio output can be found in LISA-U1 series Data Sheet [1]. Warning: excessive sound pressure from headphones can cause hearing loss. Table 34 lists the signals related to analog audio functions. Name MIC_P MIC_N SPK_P SPK_N Module Description Remarks LISA-U120 LISA-U130 LISA-U120 LISA-U130 LISA-U120 LISA-U130 LISA-U120 LISA-U130 Differential analog audio input (Positive) Differential analog audio input (Negative) Differential analog audio output (Positive) Differential analog audio output (Negative) Shared for all uplink analog path modes:

handset, headset, hands-free mode. Internal DC blocking capacitor. Shared for all uplink analog path modes:

handset, headset, hands-free mode. Internal DC blocking capacitor. Shared for all uplink analog path modes:

earpiece, headset, loudspeaker mode. Shared for all uplink analog path modes:

earpiece, headset, loudspeaker mode. Table 34: Analog audio interface pins The audio pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. All corresponding differential audio lines must be routed in pairs, be embedded in GND (have the ground lines as close as possible to the audio lines), and maintain distance from noisy lines such as VCC and from components such as switching regulators. If the audio pins are not used, they can be left unconnected on the application board. 1.11.1.3 Headset mode Headset mode is the default audio operating mode of the LISA-U120 and LISA-U130 modules. The headset profile is configured when the uplink audio path is set to Headset microphone and the downlink audio path is set to Mono headset (refer to u-blox AT Commands Manual [3]: AT+USPM command: <main_uplink>,

<main_downlink> parameters):

Headset microphone must be connected to the module differential input MIC_P / MIC_N Headset receiver must be connected to the module differential output SPK_P / SPK_N 3G.G2-HW-10002-A2 Preliminary System description Page 75 of 159 LISA-U series - System Integration Manual Figure 42 shows an example of an application circuit connecting a headset (with a 2.2 k electret microphone and a 32 receiver) to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line, and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 42: Headset mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JA01 Murata C5, C6, C7 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata D1, D2 L1, L2 J1 Low Capacitance ESD Protection 82 nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) USB0002RP or USB0002DP AVX LQG15HS82NJ02 Murata Audio Headset 2.5 mm Jack Connector SJ1-42535TS-SMT CUI, Inc. R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp U1 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Table 35: Example of components for headset jack connection 1.11.1.4 Handset mode The handset profile is configured when the uplink audio path is set to Handset microphone and the downlink audio path is set to Normal earpiece (refer to u-blox AT commands manual [3]: AT+USPM command:

<main_uplink>, <main_downlink> parameters):

Handset microphone must be connected to the module differential input MIC_P / MIC_N Handset receiver must be connected to the module differential output SPK_P / SPK_N 3G.G2-HW-10002-A2 Preliminary System description Page 76 of 159 LISA-U120/U130C2C3C4J1253461L254SPK_N53SPK_P39MIC_N40MIC_PD1AUDIO HEADSET CONNECTORD2INOUTGNDLow Noise LDO RegulatorVMAINU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointL1C1C7 LISA-U series - System Integration Manual Figure 43 shows an example of an application circuit connecting a handset (with a 2.2 k electret microphone and a 32 receiver) to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 43: Handset mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JA01 Murata C5, C6, C7 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata D1, D2 L1, L2 J1 Low Capacitance ESD Protection 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) USB0002RP or USB0002DP AVX LQG15HS82NJ02 Murata Audio Handset Jack Connector, 4Ckt (4P4C) 52018-4416 Molex R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp U1 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Table 36: Example of components for handset connection 1.11.1.5 Hands-free mode The hands-free profile is configured when the uplink audio path is set to Hands-free microphone and the downlink audio path is set to Loudspeaker (refer to u-blox AT commands manual [3]: AT+USPM command:

<main_uplink>, <main_downlink> parameters):

Hands-free microphone signal must be connected to the module differential input MIC_P / MIC_N High power loudspeaker must be connected to the output of an external audio amplifier, for which the input must be connected to the module differential output SPK_P / SPK_N The module differential analog audio output is not able to drive an 8 speaker: an external audio amplifier must be provided on the application board to amplify the low power audio signal provided by the module differential output SPK_P / SPK_N. 3G.G2-HW-10002-A2 Preliminary System description Page 77 of 159 LISA-U120/U130C1C2C3J14321L153SPK_P54SPK_N40MIC_P39MIC_ND1AUDIO HANDSET CONNECTORD2INOUTGNDLow Noise LDO RegulatorU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointC4L2VMAINC7 LISA-U series - System Integration Manual Hands-free functionality is implemented using appropriate digital signal processing algorithms for voice-band handling (echo canceller and automatic gain control), managed via software (refer to u-blox AT commands manual [3], AT+UHFP command). Figure 43 shows an example of an application circuit connecting a 2.2 k electret microphone and an 8 speaker to the LISA-U120 and LISA-U130 modules, with an external low noise LDO voltage regulator to provide a proper supply for the microphone and with an external audio amplifier to amplify the low power audio signal provided by the module differential output. Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line and a 27 pF bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling and TDMA noise. The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance. Figure 44: Hands-free mode application circuit Reference Description Part Number Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 Murata C5, C6, C7, C10 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata C8, C9 C11 D1, D2 J1 J2 L1, L2 MIC 47 nF Capacitor Ceramic X7R 0402 10% 16V GRM155R71C473KA01 Murata 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 Murata Low Capacitance ESD Protection USB0002RP or USB0002DP AVX Microphone Connector Speaker Connector 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) 2.2 k Electret Microphone LQG15HS82NJ02 Murata 3G.G2-HW-10002-A2 Preliminary System description Page 78 of 159 C1C2C3L139MIC_N53SPK_P40MIC_P54SPK_ND1Microphone ConnectorD2INOUTGNDLow Noise LDO RegulatorU1R4R1C6R3R2C52V5Sense lines connected to GND in one star pointC4SPKL2MICSpeaker ConnectorOUT+IN+GNDVMAINU2OUT-IN-C8C9R5R6VDDC11C10LISA-U120/U130Audio AmplifierJ1J2VMAINC7 LISA-U series - System Integration Manual Part Number Manufacturer RC0402JR-072K2L Yageo Phycomp RC0402JR-070RL Yageo Phycomp Reference Description R1, R2, R3, R4 2.2 k Resistor 0402 5% 0.1 W 0 Resistor 0402 5% 0.1 W 8 Loudspeaker R5, R6 SPK U1 U2 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology Filter-less Mono 2.8 W Class-D Audio Amplifier SSM2305CPZ Analog Devices Table 37: Example of components for hands-free connection 1.11.1.6 Connection to an external analog audio device The differential analog audio input / output can be used to connect the module to an external analog audio device. Audio devices with a differential analog input / output are preferable, as they are more immune to external disturbances. If the external analog audio device is provided with a differential analog audio input, the SPK_P / SPK_N balanced output of the module must be connected to the differential input of the external audio device through a DC-block 10 F series capacitor (e.g. Murata GRM188R60J106M) to decouple the bias present at the module output (see SPK_P / SPK_N common mode output voltage in the LISA-U1 series Data Sheet [1]). Use a suitable power-on sequence to avoid audio bump due to charging of the capacitor: the final audio stage should be always enabled as last one. If the external analog audio device is provided with a single ended analog audio input, a proper differential to single ended circuit must be inserted from the SPK_P / SPK_N balanced output of the module to the single ended input of the external audio device. A simple application circuit is described in Figure 45: 10 F series capacitors (e.g. Murata GRM188R60J106M) are provided to decouple the bias present at the module output, and a voltage divider is provided to properly adapt the signal level from the module output to the external audio device input. The DC-block series capacitor acts as high-pass filter for audio signals, with cut-off frequency depending on both the values of capacitor and on the input impedance of the external audio device. For example: in case of

, the two 10 F capacitors will set the -3 dB cut-off frequency to 53 Hz, differential input impedance of 600 while for single ended connection to 600 external device, the cut-off frequency with just the single 10 F capacitor will be 103 Hz. In both cases the high-pass filter has a low enough cut-off to not impact the audio signal frequency response. The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the SPK_P / SPK_N output level of the module is too high for the input of the audio device. If the external analog audio device is provided with a differential analog audio output, the MIC_P / MIC_N balanced input of the module must be connected directly to the differential output of the external audio device. Series capacitors are not needed since MIC_P / MIC_N pins are provided with internal 100 nF capacitors for DC blocking (see LISA-U1 series Data Sheet [1]). If the external analog audio device is provided with a single ended analog audio output, a proper single ended to differential circuit has to be inserted from the single ended output of the external audio device to the MIC_P / MIC_N balanced input of the module. A simple application circuit is described in Figure 45: a voltage divider is provided to properly adapt the signal level from the external audio device output to the module input. The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the output level of the audio device is too high for MIC_P / MIC_N. Please refer to Figure 45 for the application circuits. To enable the audio path corresponding to the differential analog audio input / output, please refer to u-blox AT Commands Manual [3]: AT+USPM command. To tune audio levels for the external device please refer to u-blox AT Commands Manual [3] (AT+USGC, AT+UMGC commands). 3G.G2-HW-10002-A2 Preliminary System description Page 79 of 159 LISA-U series - System Integration Manual Figure 45: Application circuits to connect the module to audio devices with proper differential or single-ended input/output Reference Description Part Number Manufacturer C1, C2, C3, C4 10 F Capacitor X5R 0603 5% 6.3 V GRM188R60J106M Murata R1, R3 R2, R4 0 Resistor 0402 5% 0.1 W RC0402JR-070RL Yageo Phycomp Not populated Table 38: Connection to an analog audio device 1.11.2 Digital Audio interface LISA-U100, LISA-U110 and LISA-U200-00 modules versions dont support digital audio interface. LISA-U120 and LISA-U130 modules provide one bidirectional 4-wire I2S digital audio interface, while all LISA-U2 series modules versions except LISA-U200-00 provide two bidirectional 4-wire I2S digital audio interfaces for connecting to remote digital audio devices. LISA-U series modules can act as an I2S master or I2S slave. In master mode the word alignment and clock signals of the I2S digital audio interface are generated by the module. In slave mode these signal must be generated by the remote device. Table 39 lists the signals related to digital audio functions. 3G.G2-HW-10002-A2 Preliminary System description Page 80 of 159 LISA-U120/U130C1C254SPK_N53SPK_PGND40MIC_PGNDNegative Analog INPositive Analog INNegative Analog OUTPositive Analog OUTAudio DeviceReferenceReference39MIC_NLISA-U120/U13054SPK_N53SPK_PGND40MIC_PGNDAnalog INAudio DeviceReferenceReference39MIC_NAnalog OUTC3C4R2R1R4R3 I2S receive data Module input Name Module Description I2S transmit data I2S_TXD I2S_RXD I2S_CLK I2S_WA LISA-U120-0x LISA-U130-0x LISA-U2xx-01 LISA-U120-0x LISA-U130-0x LISA-U2xx-01 LISA-U120-00 LISA-U130-00 LISA-U120-01 LISA-U130-01 LISA-U2xx-01 LISA-U120-00 LISA-U130-00 LISA-U120-01 LISA-U130-01 LISA-U2xx-01 I2S clock I2S clock I2S word alignment I2S word alignment I2S1_TXD LISA-U2xx-01 I2S1_RXD LISA-U2xx-01 I2S1_CLK LISA-U2xx-01 Second I2S transmit data Second I2S receive data Second I2S clock I2S1_WA LISA-U2xx-01 Second I2S word alignment CODEC_CLK LISA-U2xx-01 Digital clock output Table 39: Digital audio interface pins LISA-U series - System Integration Manual Remarks Module output Module output in master mode Module output in master mode Module input in slave mode Module output in master mode Module output in master mode Module input in slave mode Module output Module input Module output in master mode Module input in slave mode Module output in master mode Module input in slave mode Digital clock output for external audio codec Configurable to 26 MHz or 13 MHz The I2S interfaces and CODEC_CLK pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a general purpose ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to the I 2S interfaces pins, close to accessible points, and a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002) on the line connected to CODEC_CLK pin, close to accessible point. The I2S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command:

PCM mode Normal I2S mode The I2S interface can be set to two configurations, by the <I2S_Master_Slave> parameter of AT+UI2S:

Master mode Slave mode LISA-U120-00 and LISA-U130-00 modules versions dont support I2S slave mode: module acts as master only. The sample rate of transmitted/received words can be set, by the <I2S_sample_rate> parameter of AT+UI2S, to:

8 kHz 11.025 kHz 12 kHz 16 kHz 22.05 kHz 24 kHz 3G.G2-HW-10002-A2 Preliminary System description Page 81 of 159 LISA-U series - System Integration Manual 32 kHz 44.1 kHz 48 kHz The sample rate of transmitted and received words of LISA-U120-00 and LISA-U130-00 modules cannot be configured: the sample rate is fixed at 8 kHz only. The <main_uplink> and <main_downlink> parameters of the AT+USPM command must be properly configured to select the I2S digital audio interfaces paths (for more details please refer to u-blox AT Commands Manual [3]):

<main_uplink> has to be properly set to select:

o o the first I2S interface (using I2S_RXD module input) the second I2S interface (using I2S1_RXD module input)

<main_downlink> has to be properly set to select:

o o the first I2S interface (using I2S_TXD module output) the second I2S interface (using I2S1_TXD module output) Parameters of digital path can be configured and saved as the normal analog paths, using appropriate path parameter as described in the u-blox AT Commands Manual [3], +USGC, +UMGC, +USTN AT command. Analog gain parameters of microphone and speakers are not used when digital path is selected. The I2S receive data input and the I2S transmit data output signals are respectively connected in parallel to the analog microphone input and speaker output signals, so resources available for analog path can be shared:

Digital filters and digital gains are available in both uplink and downlink direction. They can be properly configured by the AT commands Ringer tone and service tone are mixed on the TX path when active (downlink) The HF algorithm acts on I2S path Refer to the u-blox AT Commands Manual [3]: AT+UI2S command for possible settings of I2S interface. 1.11.2.1 I2S interface - PCM mode Main features of the I2S interface in PCM mode:

I2S runs in PCM - short alignment mode (configurable by AT commands) I2S word alignment signal can be configured to 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz I2S word alignment toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits I2S clock frequency depends on frame length and <sample_rate>. Can be 17 x <sample_rate> or 18 x

<sample_rate>

I2S transmit and I2S receive data are 16 bit words long with the same sampling rate as I2S word alignment, mono. Data is in 2s complement notation. MSB is transmitted first When I2S word alignment toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long I2S word alignment configuration) is MSB of the transmitted word (MSB is transmitted twice in this case) I2S transmit data changes on I2S clock rising edge, I2S receive data changes on I2S clock falling edge 3G.G2-HW-10002-A2 Preliminary System description Page 82 of 159 LISA-U series - System Integration Manual 1.11.2.2 I2S interface - Normal I2S mode Normal I2S supports:

16 bits word Mono interface Configurable sample rate: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz Main features of I2S interface in normal I2S mode:

I2S word alignment signal always runs at <sample_rate> and synchronizes 2 channels (timeslots on word alignment high, word alignment low) I2S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data are in 2s complement notation. MSB is transmitted first. The bits are written on I2S clock rising or falling edge (configurable) I2S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is read in 2s complement notation. MSB is read first. The bits are read on the I2S clock edge opposite to I2S transmit data writing edge (configurable) I2S clock frequency is 16 bits x 2 channels x <sample_rate>

The modes are configurable through a specific AT command (refer to the related chapter in u-blox AT Commands Manual [3], +UI2S AT command) and the following parameters can be set:

MSB can be 1 bit delayed or non-delayed on I2S word alignment edge I2S transmit data can change on rising or falling edge of I2S clock signal (rising edge in this example) I2S receive data are read on the opposite front of I2S clock signal 1.11.2.3 I2S interface application circuits LISA-U series I2S digital audio interfaces can be connected to an external digital audio device for voice applications. The external digital audio device must be properly configured according to the wireless module configuration, with opposite role (i.e. master vs. slave), same mode (i.e. PCM mode or Normal I2S mode), same sample rate and same voltage level. Figure 46 shows an application circuit with a generic digital audio device. Figure 46: I2S interface application circuit with a generic digital audio device Figure 47 shows an application circuit for I2S digital audio interfaces of LISA-U2xx-01 modules, providing voice capability using an external audio voice codec. DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface. 3G.G2-HW-10002-A2 Preliminary System description Page 83 of 159 43I2S_CLK41I2S_WAI2S ClockI2S Word AlignmentLISA-U120-xxLISA-U130-xxLISA-U2xx-0142I2S_TXD44I2S_RXDI2S Data InputI2S Data OutputGNDGND1.8 V Digital Audio Device LISA-U series - System Integration Manual An I2S digital audio interface of the LISA-U2xx-01 modules (that acts as an I2S master) is connected to the digital audio interface of the external audio codec (that acts as an I2S slave). The first I2S interface can be used as well as the second I2S interface of the wireless module. The CODEC_CLK digital output clock of the wireless module is connected to the clock input of the external audio codec to provide clock reference. Signal integrity of the high speed lines may be degraded if the PCB layout is not optimal, especially when the CODEC_CLK clock line or also the I2S digital audio interface lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. The external audio codec is controlled by the wireless module using the DDC (I2C) interface: this interface can be used to communicate with u-blox GPS receivers and at the same time to control an external audio codec on all LISA-U2 series modules versions except LISA-U200-00. The V_INT supply output of the wireless module provides the supply to the external audio codec, defining a proper voltage level for the digital interfaces. An external audio codec can be connected to the I2S digital audio interface of LISA-U120 or LISA-U130 modules as shown in the application circuit described in Figure 47. In this case the application processor should properly control the audio codec by I2C interface and should properly provide clock reference to the audio codec. Figure 47: I2S interface application circuit with an external audio codec to provide voice capability Reference Description Part Number Manufacturer C1 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 Murata C2, C4, C5, C6 1 F Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J105KE19 Murata C3 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata C7, C8, C9, C10 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 Murata D1, D2 Low Capacitance ESD Protection USB0002RP or USB0002DP AVX J1 J2 Microphone Connector Speaker Connector Various manufacturers Various manufacturers 3G.G2-HW-10002-A2 Preliminary System description Page 84 of 159 53I2S1_CLK54I2S1_WAR2R1BCLKGNDU1LRCLKC3C2LISA-U2xx-01Audio Codec40I2S1_TXD39I2S1_RXDSDINSDOUT46SDA45SCLSDASCL52CODEC_CLKMCLKGNDIRQnR3C1C10D2C9SPKSpeaker ConnectorOUTPOUTNJ24V_INTVDDMICBIASC4R4C5C6L1MICLNMICLPD1Microphone ConnectorL2MICC8C7J1MICGNDR51V8 LISA-U series - System Integration Manual Reference Description L1, L2 MIC R1, R2 R3 R4, R5 SPK U1 82nH Multilayer inductor 0402

(self resonance frequency ~1 GHz) 2.2 k Electret Microphone 4.7 k Resistor 0402 5% 0.1 W 10 k Resistor 0402 5% 0.1 W 2.2 k Resistor 0402 5% 0.1 W 32 Speaker 16-Bit Mono Audio Voice Codec Part Number Manufacturer LQG15HS82NJ02 Murata Various manufacturers RC0402JR-074K7L - Yageo Phycomp RC0402JR-0710KL - Yageo Phycomp RC0402JR-072K2L Yageo Phycomp Various manufacturers MAX9860ETG+ - Maxim Table 40: Example of components for audio voice codec application circuit If the I2S digital audio pins are not used, they can be left unconnected on the application board. Any external signal connected to the digital audio interfaces must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence

(at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during power down mode, when external reset is forced low and during power-on sequence. 1.11.3 Voiceband processing system The voiceband processing on the LISA-U series modules is implemented in the DSP core inside the baseband chipset. The analog audio front-end of the chipset is connected to the digital system through 16 bit ADC converters in the uplink path, and through 16 bit DAC converters in the downlink path. External digital audio devices can be interfaced directly to the DSP digital processing part via the I2S digital interface. The analog amplifiers are skipped in this case. Available audio signal processing algorithms are:

Speech encoding (uplink) and decoding (downlink).The following speech codecs are supported in firmware on the DSP for speech encoding and decoding:

GERAN GMSK codecs GSM HR (GSM Half Rate) GSM FR (GSM Full Rate) GSM EFR (GSM Enhanced Full Rate) HR AMR (GSM Half Rate Adaptive Multi Rate - Narrow Band) FR AMR (GSM Full Rate Adaptive Multi Rate - Narrow Band) FR AMR-WB (GSM Full Rate Adaptive Multi Rate - Wide Band) UTRAN codecs:

UMTS AMR2 (UMTS Adaptive Multi Rate version 2 Narrow Band) UMTS AMR-WB (UMTS Adaptive Multi Rate Wide Band) Mandatory sub-functions:

Discontinuous transmission, DTX (GSM 46.031, 46.041, 46.081 and 46.093 standards) Voice activity detection, VAD (GSM 46.032, 46.042, 46.082 and 46.094 standards) Background noise calculation (GSM 46.012, 46.022, 46.062 and 46.092 standards) Function configurable via specific AT commands (refer to the u-blox AT Commands Manual [3]) Signal routing: +USPM command 3G.G2-HW-10002-A2 Preliminary System description Page 85 of 159 LISA-U series - System Integration Manual Analog amplification, Digital amplification: +USGC, +CLVL, +CRSL, +CMUT command Digital filtering: +UUBF, +UDBF commands Hands-free algorithms (echo cancellation, Noise suppression, Automatic Gain control) +UHFP command Sidetone generation (feedback of uplink speech signal to downlink path): +USTN command Playing/mixing of alert tones:

Service tones: Tone generator with 3 sinus tones +UPAR command User generated tones: Tone generator with a single sinus tone +UTGN command PCM audio files (for prompting): The storage format of PCM audio files is 8 kHz sample rate, signed 16 bits, little endian, mono With exception of the speech encoder/decoder, this audio processing can be controlled by AT commands. This processing is implemented within the different blocks of the voiceband processing system:

Sample-based Voice-band Processing (single sample processed at 16 kHz for Wide Band AMR codec or 8 kHz for all other speech codecs) Frame-based Voice-band Processing (frames of 320 samples for Wide Band AMR codec or 160 samples for all other speech codecs are processed every 20 ms) These blocks are connected by buffers (circular buffer and voiceband sample buffer) and sample rate converters

(for 8 / 16 to 47.6 kHz conversion). Voiceband audio processing implemented in the DSP core of LISA-U series modules is summarized in Figure 48. Figure 48: Voiceband processing system block diagram 3G.G2-HW-10002-A2 Preliminary System description Page 86 of 159 DACADCI2S Receive Data SwitchMIC_P/NMicrophone Analog GainUF 2/6UF 1/5Hands-freeTo Radio TXScal_MicDigital GainSidetoneSPK_P/NSwitchI2S Transmit Data Scal_Rec Digital GainHS Analog gainTone GeneratorFrom Radio RXSpeech levelI2Sx RXPCM Player18 dBUF 4/8UF 3/7DF 3/7DF 4/8DF 1/5DF 2/6Legend:UF= uplink filterDF = downlink filterMix_AfeI2Sx TX LISA-U series - System Integration Manual 1.12 General Purpose Input/Output (GPIO) LISA-U1 series modules provide 5 pins (GPIO1-GPIO5), while LISA-U2 series modules provide up to 14 pins

(GPIO1-14) which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands (for further details refer to u-blox AT Commands Manual [3], +UGPIOC,

+UGPIOR, +UGPIOW, +UGPS, +UGPRF, +USPM). The following functions are available in the LISA-U series modules:

GSM Tx burst indication:

GPIO1 pin can be configured by AT+UGPIOC to indicate when a GSM Tx burst/slot occurs, setting the parameter <gpio_mode> of AT+UGPIOC command to 9. No GPIO pin is by default configured to provide the GSM Tx burst indication function. The pin configured to provide the GSM Tx burst indication function is set as o Output / High, since ~10 s before the start of first Tx slot, until ~5 s after the end of last Tx slot o Output / Low, otherwise The pin configured to provide the GSM Tx burst indication function can be connected on the application board to an input pin of an application processor to indicate when a GSM Tx burst/slot occurs. GPS supply enable:

The GPIO2 is by default configured by AT+UGPIOC command to enable or disable the supply of the u-blox GPS receiver connected to the wireless module. The GPIO1, GPIO3, GPIO4 or GPIO5 pins can be configured to provide the GPS supply enable function, alternatively to the default GPIO2 pin, setting the parameter <gpio_mode> of AT+UGPIOC command to 3. The GPS supply enable mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the GPS supply enable function is set as o Output / High, to switch on the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 1 o Output / Low, to switch off the u-blox GPS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin configured to provide the GPS supply enable function must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GPS receiver on the application board. LISA-U200-00 modules version dont support GPS supply enable function. GPS data ready:

Only the GPIO3 pin provides the GPS data ready function, to sense when a u-blox GPS receiver connected to the wireless module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode>

of AT+UGPIOC command to 4. The pin configured to provide the GPS data ready function will be set as o o Input, to sense the line status, waking up the wireless module from idle-mode when the u-blox GPS receiver is ready to send data via the DDC (I2C) interface; this is possible if the parameter <mode>

of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of AT+UGPRF command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GPS data ready function must be connected to the data ready output of the u-blox GPS receiver (i.e. the pin TxD1 of the u-blox GPS receiver) on the application board. 3G.G2-HW-10002-A2 Preliminary System description Page 87 of 159 LISA-U series - System Integration Manual LISA-U1xx-00 and LISA-U200-00 modules versions dont support GPS data ready function. GPS RTC sharing:

Only the GPIO4 pin provides the GPS RTC sharing function, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GPS receiver connected to the wireless module, setting the parameter

<gpio_mode> of AT+UGPIOC command to 5. The pin configured to provide the GPS RTC sharing function will be set as o Output, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GPS receiver if the parameter <mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration>

of AT+UGPRF command is set to 32 o Output / Low, otherwise (default setting) The pin that provides the GPS RTC sharing function must be connected to the RTC synchronization input of the u-blox GPS receiver (i.e. the pin EXTINT0 of the u-blox GPS receiver) on the application board. LISA-U1xx-00 and LISA-U200-00 modules versions dont support GPS RTC sharing function. SIM card detection:

The GPIO5 pin is by default configured by AT+UGPIOC command to detect SIM card presence. Only the GPIO5 pin can be configured to provide the SIM card detection function, setting the parameter

<gpio_mode> of AT+UGPIOC command to 7 (default setting). The pin configured to provide the SIM card detection function is set as o Input with an internal active pull-down enabled, to sense SIM card presence The pin must be connected on the application board to SW2 pin of the SIM card holder, which must provide 2 pins for the mechanical card presence detection, with a 470 k pull-down resistor. SW1 pin of the SIM card holder must be connected to V_INT pin of the module, by a 1 k pull-up resistor. Refer to Figure 49 and section 1.8 for the detailed application circuit. The GPIO5 signal will be pulled low by the pull-down when a SIM card is not inserted in the holder, and will be pulled high by the pull-up when a SIM card is present. Network status indication:

GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate network status (i.e. no service, registered home 2G network, registered home 3G network, registered visitor 2G network, registered visitor 3G network, voice or data 2G/3G call enabled), setting the parameter <gpio_mode> of AT+UGPIOC command to 2. No GPIO pin is by default configured to provide the Network status indication function. The Network status indication mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the Network status indication function is set as o Continuous Output / Low, if no service (no network coverage or not registered) o Cyclic Output / High for 100 ms, Output / Low for 2 s, if registered home 2G network o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 2 s, if registered home 3G network o Cyclic Output / High for 100 ms, Output / Low for 100 ms, Output / High for 100 ms, Output / Low for 2 s, if registered visitor 2G network (roaming) o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 100 ms, if registered visitor 3G network (roaming) o Continuous Output / High, if voice or data 2G/3G call enabled 3G.G2-HW-10002-A2 Preliminary System description Page 88 of 159 LISA-U series - System Integration Manual The pin configured to provide the Network status indication function can be connected on the application board to an input pin of an application processor or can drive a LED by a transistor with integrated resistors to indicate network status. Module status indication:

The GPIO13 and GPIO1 pins can be configured to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 10. No GPIO pin is by default configured to provide the Module status indication. The pin configured to provide the Module status indication function is set as o Output / High, when the module is switched on (any operating mode during module normal operation: idle, active or connected mode) o Output / Low, when the module is switched off (power off mode) The Module status indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. LISA-U1 series modules and LISA-U200-00 modules versions dont support Module status indication. Module operating mode indication:

The GPIO14 and GPIO5 pins can be configured to indicate module operating mode (idle-mode versus active or connected mode), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 11. No GPIO pin is by default configured to provide the Module operating mode indication. The pin configured to provide the Module operating mode indication function is set as o Output / High, when the module is in active or connected mode o Output / Low, when the module is in idle-mode (that can be reached if power saving is enabled by

+UPSV AT command: for further details refer to u-blox AT Commands Manual [3]) The Module operating mode indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. LISA-U1 series modules and LISA-U200-00 versions dont support Module operating mode indication. I2S digital audio interface:

The GPIO6, GPIO7, GPIO8, GPIO9 pins are by default configured as the second I2S digital audio interface

(I2S1_RXD, I2S1_TXD, I2S1_CLK, I2S1_WA respectively). Only these pins can be configured as the second I2S digital audio interface, correctly setting the parameter

<gpio_mode> of AT+UGPIOC command to 12 (default setting). LISA-U1 series modules and LISA-U200-00 versions dont support the second I2S digital audio interface over GPIOs. SPI serial interface:

GPIO10, GPIO11, GPIO12, GPIO13 and GPIO14 pins are by default configured as the SPI / IPC serial interface (SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_SRDY and SPI_MRDY respectively). Only these pins can be configured as the SPI / IPC serial interface, correctly setting the parameter

<gpio_mode> of AT+UGPIOC command to 13 (default setting). 3G.G2-HW-10002-A2 Preliminary System description Page 89 of 159 LISA-U series - System Integration Manual LISA-U1 series modules and LISA-U200-00 versions dont support SPI / IPC serial interface over GPIOs:

the SPI / IPC pins provide the SPI / IPC function only and cannot be configured as GPIO. General purpose input:

All the GPIOs can be configured as input to sense high or low digital level through AT+UGPIOR command, setting the parameter <gpio_mode> of AT+UGPIOC command to 1. The General purpose input mode can be provided on more than one pin at a time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is by default configured as General purpose input. The pin configured to provide the General purpose input function is set as o Input, to sense high or low digital level by AT+UGPIOR command. The pin can be connected on the application board to an output pin of an application processor to sense the digital signal level. General purpose output:

All the GPIOs can be configured as output to set the high or the low digital level through AT+UGPIOW command, setting the parameter <gpio_mode> of +UGPIOC AT command to 0. The General purpose output mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is by default configured as General purpose output. The pin configured to provide the General purpose output function is set as o Output / Low, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 0 o Output / High, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 1 The pin can be connected on the application board to an input pin of an application processor to provide a digital signal. Pad disabled:

All the GPIOs can be configured in tri-state with an internal active pull-down enabled, as a not used pin, setting the parameter <gpio_mode> of +UGPIOC AT command to 255. The Pad disabled mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). The pin configured to provide the Pad disabled function is set as o Tri-state with an internal active pull-down enabled The configurations of all the GPIO pins of LISA-U series modules are described in Table 41. Pin Module Name Description Remarks 20 LISA-U1xx-xx GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GPS Supply Enable GSM Tx Burst Indication LISA-U200-00 GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GSM Tx Burst Indication 3G.G2-HW-10002-A2 Preliminary System description Page 90 of 159 LISA-U series - System Integration Manual Pin Module Name Description Remarks LISA-U2xx-01 GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as Output Input Network Status Indication GPS Supply Enable GSM Tx Burst Indication Module Status Indication 21 LISA-U1xx-xx LISA-U2xx-01 GPIO2 GPIO By default, the pin is configured to provide GPS Supply Enable function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication Pad disabled LISA-U200-00 GPIO2 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication 23 LISA-U1xx-00 GPIO3 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable LISA-U200-00 GPIO3 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication LISA-U1xx-01 LISA-U2xx-01 GPIO3 GPIO By default, the pin is configured to provide GPS Data Ready function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled 24 LISA-U1xx-00 GPIO4 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable LISA-U200-00 GPIO4 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication LISA-U1xx-01 LISA-U2xx-01 GPIO4 GPIO By default, the pin is configured to provide GPS RTC sharing function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled 3G.G2-HW-10002-A2 Preliminary System description Page 91 of 159 LISA-U series - System Integration Manual Pin Module Name Description Remarks 51 LISA-U1xx-xx GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Pad disabled LISA-U200-00 GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication Pad disabled LISA-U2xx-01 GPIO5 GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as Output Input Network Status Indication GPS Supply Enable Module Operating Mode Indication 39 LISA-U200-00 GPIO6 GPIO Pad disabled By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_RXD /

GPIO6 2nd I2S receive data /

GPIO By default, the pin is configured as 2nd I2S receive data input. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 40 LISA-U200-00 GPIO7 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_TXD /

GPIO7 2nd I2S transmit data /

GPIO By default, the pin is configured as 2nd I2S transmit data output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 53 LISA-U200-00 GPIO8 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_CLK /

GPIO8 2nd I2S clock /

GPIO By default, the pin is configured as 2nd I2S clock input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 54 LISA-U200-00 GPIO9 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as Output Input LISA-U2xx-01 I2S1_WA /

GPIO9 2nd I2S word alignment /

GPIO By default, the pin is configured as 2nd I2S word alignment input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as Output Input Pad disabled 3G.G2-HW-10002-A2 Preliminary System description Page 92 of 159 LISA-U series - System Integration Manual Pin Module Name Description Remarks 55 LISA-U2xx-01 SPI_SCLK /

GPIO10 SPI Serial Clock /

GPIO 56 LISA-U2xx-01 SPI_MOSI /

GPIO11 SPI Data Line /

GPIO 57 LISA-U2xx-01 SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO By default, the pin is configured as SPI Serial Clock Input:

Idle low (CPOL=0) Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled By default, the pin is configured as SPI Data Line Input:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Internal active pull-up to V_INT enabled Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled By default, the pin is configured as SPI Data Line Output:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Can be alternatively configured by the +UGPIOC command as Output Input Pad disabled 58 LISA-U2xx-01 SPI_SRDY /

GPIO13 SPI Slave Ready /

GPIO By default, the pin is configured as SPI Slave Ready Output:

Idle low Can be alternatively configured by the +UGPIOC command as 59 LISA-U2xx-01 SPI_MRDY /

GPIO14 SPI Master Ready /

GPIO Pad disabled By default, the pin is configured as SPI Master Ready Input:

Idle low Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as Output Input Module Status Indication Output Input Module Operating Mode Indication Table 41: GPIO pins Pad disabled The GPIO pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. An application circuit for a typical GPIOs usage is described in Figure 49:

Network indication function provided by the GPIO1 pin GPS supply enable function provided by the GPIO2 pin (function not supported by LISA-U200-00) GPS data ready function provided by the GPIO3 pin (function not supported by LISA-Uxxx-00) GPS RTC sharing function provided by the GPIO4 pin (function not supported by LISA-Uxxx-00) SIM card detection function provided by the GPIO5 pin 3G.G2-HW-10002-A2 Preliminary System description Page 93 of 159 LISA-U series - System Integration Manual Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO. If the GPIO pins are not used, they can be left unconnected on the application board. Any external signal connected to GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. Figure 49: GPIO application circuit Reference Description Part Number - Manufacturer R1 U1 R2 R3 D1 J1 R4 R5 R6 DL1 T1 47 k Resistor 0402 5% 0.1 W Various manufacturers Voltage Regulator for GPS Receiver See GPS Module Hardware Integration Manual 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W ESD Transient Voltage Suppressor SIM Card Holder 10 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W 820 Resistor 0402 5% 0.1 W LED Red SMT 0603 NPN BJT Transistor Various manufacturers Various manufacturers USB0002RP or USB0002DP - AVX CCM03-3013LFT R102 - C&K Components (or equivalent) Various manufacturers Various manufacturers Various manufacturers LTST-C190KRKT - Lite-on Technology Corporation BC847 - Infineon Table 42: Components for GPIO application circuit 3G.G2-HW-10002-A2 Preliminary System description Page 94 of 159 SIM card holderSW1 SW2 4V_INT51GPIO5R3R2OUTINGNDLDO RegulatorSHDN3V81V8GPIO3GPIO4TxD1EXTINT02324R1VCCGPIO221LISA-U seriesu-blox1.8 V GPS receiverU1J1C1R4R63V8Network IndicatorR5GPS Supply EnableGPS Data ReadyGPS RTC SharingSIM Detection20GPIO1DL1T1D1Functions not supported by LISA-Uxxx-00 versionsFunction not supported by LISA-U200-00 version LISA-U series - System Integration Manual An application circuit for the module status indication function, provided by LISA-U2xx-01 GPIO13 and GPIO1 pins to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), is described in Figure 50. The logic level of the pin configured to provide module status indication, that is set high when the module is switched on and low when the module is switched off, is inverted by a transistor biased by the V_BCKP supply, which is generated by the module when a valid VCC is applied. Figure 50: Module status indication application circuit Reference Description Part Number - Manufacturer R1, R3 R2 T1 47 k Resistor 0402 5% 0.1 W 100 k Resistor 0402 5% 0.1 W NPN BJT Transistor Various manufacturers Various manufacturers BC847 - Infineon Table 43: Components for module status indication application circuit 3G.G2-HW-10002-A2 Preliminary System description Page 95 of 159 Input (1.8V)V_BCKP2LISA-U2xx-01Application ProcessorR1R3Module Status IndicationR220GPIO1T1 LISA-U series - System Integration Manual 1.13 Reserved pins (RSVD) LISA-U series modules have pins reserved for future use. All the RSVD pins, except pin number 5, can be left unconnected on the application board. The application circuit is illustrated in Figure 51. Pin 5 (RSVD) must be connected to GND. Figure 51: Application circuit for the reserved pins (RSVD) 3G.G2-HW-10002-A2 Preliminary System description Page 96 of 159 LISA-U120/U1305RSVD52RSVD74RSVDLISA-U100/U1105RSVD52RSVD74RSVD39RSVD40RSVD41RSVD42RSVD43RSVD44RSVD53RSVD54RSVDLISA-U2305RSVDLISA-U200-005RSVD52RSVD74RSVD41RSVD42RSVD43RSVD44RSVDLISA-U200-015RSVD74RSVD LISA-U series - System Integration Manual 1.14 Schematic for LISA-U series module integration Figure 52 is an example of a schematic diagram where a LISA-U1 series module is integrated into an application board, using all the interfaces of the module. Figure 52: Example of schematic diagram to integrate LISA-U1 series modules in an application board, using all the interfaces 3G.G2-HW-10002-A2 Preliminary System description Page 97 of 159 47pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF50VSIM48SIM_IO47SIM_CLK49SIM_RST47pFSW1 SW24V_INT51GPIO5470k1kESDESDESDESDESDESDTXDRXDRTSCTSDTRDSRRIDCDGND15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND3V8330F39pFGND10nF100nF10pFLISA-U1 series62VCC63VCC61VCC+100F2V_BCKPMOSIMISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGNDVBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GND100nF5RSVD52RSVD74RSVDGNDRTC back-up27pF27pF27pF82nH54SPK_N53SPK_P39MIC_N40MIC_PESDHeadset ConnectorESDINOUTGNDLow Noise LDO Regulator3V82.2k2.2k10F2.2k2.2k10F2V5Sense lines connected to GND in one star point82nH27pF10FESDESDu-blox1.8V GPS Receiver4.7kOUTINGNDLDO RegulatorSHDNSDASCL4.7k3V81V8_GPSSDA2SCL2GPIO3GPIO4TxD1EXTINT04645232447kVCCGPIO221ANT68Antenna1.8V DTE1.8V SPI MasterUSB 2.0 Host1.8V Digital Audio DeviceI2S_RXDI2S_CLKI2S Data OutputI2S ClockI2S_TXDI2S_WAI2S Data InputI2S Word Alligment44434241LISA-U120/U130 only20GPIO13V8Network Indicator22RESET_NFerrite Bead47pFApplication ProcessorOpen Drain Output19PWR_ON100kOpen Drain Output00TPTPFunctions not supported by LISA-U1xx-00 versions00TPTP LISA-U series - System Integration Manual Figure 53 is an example of a schematic diagram where a LISA-U2 series module is integrated into an application board, using all the interfaces of the module. Figure 53: Example of schematic diagram to integrate LISA-U2 series modules in an application board, using all the interfaces 3G.G2-HW-10002-A2 Preliminary System description Page 98 of 159 TXDRXDRTSCTSDTRDSRRIDCDGND15TXD12DTR16RXD13RTS14CTS9DSR10RI11DCDGND3V8330F39pFGND10nF100nF10pFLISA-U2 series62VCC63VCC61VCC+100F2V_BCKPMOSIMISOSCLKInterruptGPIOGND56SPI_MOSI59SPI_MRDY57SPI_MISO55SPI_SCLK58SPI_SRDYGNDVBUSD+D-GND18VUSB_DET27USB_D+26USB_D-GND100nF5RSVD74ANT_DIVGNDRTC back-upu-blox1.8V GPS Receiver4.7kOUTINGNDLDO RegulatorSHDNSDASCL4.7k3V81V8_GPSSDA2SCL2GPIO3GPIO4TxD1EXTINT04645232447kVCCGPIO221ANT68Main Tx/Rx Antenna1.8V DTE1.8V SPI MasterUSB 2.0 Host20GPIO13V8Network Indicator22RESET_NFerrite Bead47pFApplication ProcessorOpen Drain Output19PWR_ON100kOpen Drain Output00TPTPFunctions not supported by LISA-U200-00 version00TPTP1.8V Digital Audio DeviceI2S_RXDI2S_CLKI2S Data OutputI2S ClockI2S_TXDI2S_WAI2S Data InputI2S Word Alligment44434241V_INTBCLKLRCLK10F1FAudio Codec MAX9860SDINSDOUTSDASCL53I2S1_CLK54I2S1_WA40I2S1_TXD39I2S1_RXD52CODEC_CLKMCLKIRQn10k100nFVDDSPKOUTPOUTN27pF27pFESDESDMICMICBIAS1F2.2k1F1F82nHMICLNMICLP82nHMICGND2.2kESDESD27pF27pFV_INTRx Diversity AntennaLISA-U230 only47pFSIM Card HolderCCVCC (C1)CCVPP (C6)CCIO (C7)CCCLK (C3)CCRST (C2)GND (C5)47pF47pF100nF50VSIM48SIM_IO47SIM_CLK49SIM_RST47pFSW1 SW24V_INT51GPIO5470k1kESDESDESDESDESDESDV_INT LISA-U series - System Integration Manual 1.15 Approvals LISA-U series modules have been or will be approved under the following schemes:

[EU] R&TTE

[EU] CE

[EU] GCF CC

[EU] GCF FT

[USA] FCC

[USA] PTCRB

[Canada] IC

(Radio and Telecommunications Terminal Equipment Directive)

(Conformit Europenne)

(Global Certification Forum-Certification Criteria)

(Global Certification Forum- Field Trials)

(Federal Communications Commission)

(PCS Type Certification Review Board)

(Industry Canada)

[South Africa] ICASA

(Independent Communications Authority of South Africa)

[Australia] a-tick

[Korea] KCC

[Japan] JATE

[Japan] TELEC

[Taiwan] NCC

(Korean Communications Commission)

(Japan Approvals Institute for Telecommunications Equipment)

(Telecom Engineering Center)

(National Communications Commission) LISA-U series modules will be approved by the following network operators:

[USA] AT&T

[Canada] Rogers

[EU][AUS] Vodafone

[AUS] Telstra

[EU] Tmobile

[Japan] NTTDoCoMo

[EU] Orange 1.15.1 R&TTED and European Conformance CE mark Products bearing the CE marking comply with the R&TTE Directive (99/5/EC), EMC Directive (89/336/EEC) and the Low Voltage Directive (73/23/EEC) issued by the Commission of the European Community. Compliance with these directives implies conformity to the following European Norms:

Radio Frequency spectrum efficiency:

o o o EN 301 511 EN 301 908-1 EN 301 908-2 Electromagnetic Compatibility:

o o o EN 301 489-1 EN 301 489-7 EN 301 489-24 Safety o o EN 60950-1: 2006 EN62311: 2008 Notified Body identification number for LISA-U100, LISA-U110, LISA-U120 and LISA-U130 is 0890. Notified Body identification number for LISA-U200 is 0682. 3G.G2-HW-10002-A2 Preliminary System description Page 99 of 159 LISA-U series - System Integration Manual 1.15.2 IC The IC Certification Numbers for the LISA-U series modules are:

LISA-U100: 8595A-LISAU120 LISA-U120: 8595A-LISAU120 LISA-U200: 8595A-LISAU200 1.15.3 Federal communications commission notice The FCC ID for the LISA-U series modules are LISA-U100: XPYLISAU120 LISA-U120: XPYLISAU120 LISA-U200: XPYLISAU200 1.15.3.1 Safety Warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product The clearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, no hygroscopic materials nor materials containing asbestos are employed 1.15.3.2 Declaration of Conformity - United States only This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure Information: this equipment complies with FCC radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. The gain of the system antenna(s) used for LISA-U200 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 3.45 dBi (850 MHz) and 2.74 dBi (1900 MHz) for mobile and fixed or mobile operating configurations. 1.15.3.3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the LISA-U series modules are authorized to use the FCC Grants and Industry Canada Certificates of the LISA-U series modules for their own final products according to the conditions referenced in the certificates. 3G.G2-HW-10002-A2 Preliminary System description Page 100 of 159 LISA-U series - System Integration Manual The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

LISA-U100: "Contains FCC ID: XPYLISAU120" resp. LISA-U120: "Contains FCC ID: XPYLISAU120" resp. LISA-U200: "Contains FCC ID: XPYLISAU200" resp. The IC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

LISA-U100: "Contains IC: 8595A-LISAU120" resp. LISA-U120: "Contains IC: 8595A-LISAU120" resp. LISA-U200: "Contains IC: 8595A-LISAU200" resp. Canada, Industry Canada (IC) Notices This Class B digital apparatus complies with Canadian ICES-003 and RSS-210. Operation is subject to the following two conditions:

o o this device may not cause interference this device must accept any interference, including interference that may cause undesired operation of the device Radio Frequency (RF) Exposure Information The radiated output power of the u-blox Wireless Module is below the Industry Canada (IC) radio frequency exposure limits. The u-blox Wireless Module should be used in such a manner such that the potential for human contact during normal operation is minimized. This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canadas REL the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng

(Radio Equipment found at can be List) Additional Canadian information on RF exposure also can be found at the following web address: http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: Manufacturers of portable applications incorporating the LISA-U series modules are required to have their final product certified and apply for their own FCC Grant and Industry Canada Certificate related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Canada, avis d'Industrie Canada (IC) Cet appareil numrique de classe B est conforme aux normes canadiennes ICES-003 et RSS-210. Son fonctionnement est soumis aux deux conditions suivantes:

o o cet appareil ne doit pas causer d'interfrence cet appareil doit accepter toute interfrence, notamment les interfrences qui peuvent affecter son fonctionnement Informations concernant l'exposition aux frquences radio (RF) La puissance de sortie mise par lappareil de sans fil u-blox Wireless Module est infrieure la limite d'exposition aux frquences radio d'Industrie Canada (IC). Utilisez lappareil de sans fil u-blox Wireless Module de faon minimiser les contacts humains lors du fonctionnement normal. Ce priphrique a t valu et dmontr conforme aux limites d'exposition aux frquences radio (RF) d'IC lorsqu'il est install dans des produits htes particuliers qui fonctionnent dans des conditions d'exposition des appareils mobiles (les antennes se situent plus de 20 centimtres du corps d'une personne). 3G.G2-HW-10002-A2 Preliminary System description Page 101 of 159 LISA-U series - System Integration Manual Ce priphrique est homologu pour l'utilisation au Canada. Pour consulter l'entre correspondant lappareil dans la liste d'quipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplmentaires concernant l'exposition aux RF au Canada rendez-vous sur : http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: les fabricants d'applications portables contenant les modules LISA-U1 series doivent faire certifier leur produit final et dposer directement leur candidature pour une certification FCC ainsi que pour un certificat Industrie Canada dlivr par l'organisme charg de ce type d'appareil portable. Ceci est obligatoire afin d'tre en accord avec les exigences SAR pour les appareils portables. Tout changement ou modification non expressment approuv par la partie responsable de la certification peut annuler le droit d'utiliser l'quipement. 1.15.4 a-tick AUS Certification The equipment may not function when mains power fail either on the packaging or with the equipment. LISA-U2 series is not a-tick AUS certified. 3G.G2-HW-10002-A2 Preliminary System description Page 102 of 159 LISA-U series - System Integration Manual 2 Design-In 2.1 Design-in checklist This section provides a design-in checklist. 2.1.1 Schematic checklist The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at VCC pin above the minimum operating range limit. DC supply must be capable of providing 2.5 A current pulses, providing a voltage at VCC pin above the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value. VCC supply should be clean, with very low ripple/noise: suggested passive filtering parts can be inserted. VCC voltage must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. Connect only one DC supply to VCC: different DC supply systems are mutually exclusive. Do not leave PWR_ON floating: add a pull-up resistor to V_BCKP. Dont apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal. Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [4]. Provide appropriate access to USB interface and/or to UART RxD, TxD lines and access to PWR_ON and/or RESET_N lines on the application board in order to flash/upgrade the module firmware. Provide appropriate access to USB interface and/or to UART RxD, TxD, CTS, RTS lines for debugging. Capacitance and series resistance must be limited on each line of the SPI / IPC interface. Add a proper pull-up resistor to a proper supply on each DDC (I2C) interface line, if the interface is used. Capacitance and series resistance must be limited on each line of the DDC interface. Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Connect the pin number 5 (RSVD) to ground. Insert the suggested passive filtering parts on each used analog audio line. Check the digital audio interface specifications to connect a proper device. Capacitance and series resistance must be limited on CODEC_CLK line and each I2S interface line. Provide proper precautions for ESD immunity as required on the application board. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. All unused pins can be left floating on the application board except the PWR_ON pin (must be connected to V_BCKP by a pull-up resistor) and the RSVD pin number 5 (must be connected to GND). 3G.G2-HW-10002-A2 Preliminary Design-In Page 103 of 159 LISA-U series - System Integration Manual 2.1.2 Layout checklist The following are the most important points for a simple layout check:

Check 50

(main RF input/output) and to the ANT_DIV pad (RF input for Rx diversity). nominal characteristic impedance of the RF transmission line connected to the ANT pad Follow the recommendations of the antenna producer for correct antenna installation and deployment

(PCB layout and matching circuitry). Ensure no coupling occurs with other noisy or sensitive signals (primarily analog audio input/output signals, SIM signals). VCC line should be wide and short. Route VCC supply line away from sensitive analog signals. The high-power audio outputs lines on the application board must be wide enough to minimize series resistance. Ensure proper grounding. Consider No-routing areas for the Data Module footprint. Optimize placement for minimum length of RF line and closer path from DC source for VCC. Design USB_D+ / USB_D- connection as 90 differential pair. Keep routing short and minimize parasitic capacitance on the SPI lines to preserve signal integrity. Keep routing short and minimize parasitic capacitance on CODEC_CLK line to preserve signal integrity. 2.1.3 Antenna checklist Antenna should have 50 deployment geographical area. impedance, V.S.W.R less than 3:1 (recommended 2:1)on operating bands in Follow the recommendations of the antenna producer for correct antenna installation and deployment

(PCB layout and matching circuitry). Follow the additional guidelines for products marked with the FCC logo (United States only) reported in chapter 2.2.1.1 and 1.15.3.2 The antenna connected to the ANT pad should have built in DC resistor to ground to get proper antenna detection functionality. The antenna for the Rx diversity connected to the ANT_DIV pin should be carefully separated from the main Tx/Rx antenna connected to the ANT pin to ensure highly uncorrelated receive signals on each antenna. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation. 3G.G2-HW-10002-A2 Preliminary Design-In Page 104 of 159 LISA-U series - System Integration Manual 2.2 Design Guidelines for Layout The following design guidelines must be met for optimal integration of LISA-U series modules on the final application board. 2.2.1 Layout guidelines per pin function This section groups LISA-U series modules pins by signal function and provides a ranking of importance in layout design. Figure 54: LISA-U1 and LISA-U2 series modules pin-out (top view) with ranked importance for layout design 3G.G2-HW-10002-A2 Preliminary Design-In Page 105 of 159 V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GNDUSB_D-USB_D+234567891011121131415161718192021222324252627GNDVCCVCCVCCGNDSPI_MRDYSPI_SRDYSPI_MISOSPI_MOSISPI_SCLKSPK_NGNDSPK_PRSVDGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLI2S_RXDI2S_CLKI2S_TXDI2S_WAMIC_PMIC_N6463626160595857565554655352515049484746454443424140392930313233343536373828GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7574737271706968676676GNDRSVDGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U1 series(Top View)V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GNDUSB_D-USB_D+234567891011121131415161718192021222324252627GNDVCCVCCVCCGNDSPI_MRDY / GPIO14SPI_SRDY / GPIO13SPI_MISO / GPIO12SPI_MOSI / GPIO11SPI_SCLK / GPIO10GPIO9 / I2S1_WAGNDGPIO8 / I2S1_CLKRSVD / CODEC_CLKGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WAGPIO7 / I2S1_TXDGPIO6 / I2S1_RXD6463626160595857565554655352515049484746454443424140392930313233343536373828GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7574737271706968676676GNDGNDGNDGNDGNDGNDANTGNDGNDGND/ RSVDANT_DIVLISA-U2 series(Top View)Very ImportantCareful LayoutCommon PracticeLegend:LISA-U series - System Integration Manual Layout Remarks Very Important Design for 50 See section 2.2.1.1 characteristic impedance. Design for 50 See section 2.2.1.1 characteristic impedance. VCC line should be wide and short. Route away from sensitive analog signals. See section 2.2.1.2 Route USB_D+ and USB_D- as differential lines:

design for 90 See section 2.2.1.3 differential impedance. Avoid coupling with noisy signals. See section 2.2.1.4 Rank Function 1st RF Antenna Main RF input/output Pin(s) ANT RF input for Rx diversity ANT_DIV Very Important 2nd Main DC Supply VCC Very Important 3rd USB Signals USB_D+

USB_D-

Very Important 4th Analog Audio Careful Layout Audio Inputs Audio Outputs 5th Ground MIC_P, MIC_N SPK_P, SPK_N GND Careful Layout Provide proper grounding. See section 2.2.1.5 6th Sensitive Pin:

Careful Layout Backup Voltage Power-On V_BCKP PWR_ON 7th High-speed digital pins:

Careful Layout Avoid coupling with noisy signals. See section 2.2.1.6 Avoid coupling with sensitive signals. See section 2.2.1.7 Common Practice Follow common practice rules for digital pin routing. See section 2.2.1.8 SPI Signals 8th Clock Output Digital pins and supplies:

SIM Card Interface Digital Audio

(If implemented) DDC UART SPI_SCLK, SPI_MISO, SPI_MOSI, SPI_SRDY, SPI_MRDY CODEC_CLK VSIM, SIM_CLK, SIM_IO, SIM_RST I2S_CLK, I2S_RXD, I2S_TXD, I2S_WA I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA SCL, SDA TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR External Reset RESET_N General Purpose I/O GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14 USB detection VUSB_DET Supply for Interfaces V_INT Table 44: Pin list in order of decreasing importance for layout design 2.2.1.1 RF antenna connection The ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) are very critical in layout design. The PCB line must be designed to provide 50 nominal characteristic impedance and minimum loss up to radiating element. Provide proper transition between the ANT pad and the ANT_DIV pad to application board PCB Increase GND keep-out (i.e. clearance) for ANT and ANT_DIV pads to at least 250 m up to adjacent pads metal definition and up to 500 m on the area below the module, as described in Figure 55 3G.G2-HW-10002-A2 Preliminary Design-In Page 106 of 159 LISA-U series - System Integration Manual Add GND keep-out (i.e. clearance) on buried metal layers below ANT and ANT_DIV pads and below any other pad of component present on the RF line, if top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground (see Figure 55 for the description of the GND keep-out area below ANT and ANT_DIV pads) The transmission line up to antenna connector or pad may be a micro strip or a stripline. In any case must be designed to achieve 50 characteristic impedance Microstrip lines are usually easier to implement and the reduced number of layer transitions up to antenna connector simplifies the design and diminishes reflection losses. However, the electromagnetic field extends to the free air interface above the stripline and may interact with other circuitry Buried striplines exhibit better shielding to external and internally generated interferences. They are therefore preferred for sensitive application. In case a stripline is implemented, carefully check that the via pad-stack does not couple with other signals on the crossed and adjacent layers Minimize the transmission line length; the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB The transmission line should not have abrupt change to thickness and spacing to GND, but must be uniform and routed as smoothly as possible The transmission line must be routed in a section of the PCB where minimal interference from noise sources can be expected Route RF transmission line far from other sensitive circuits as it is a source of electromagnetic interference Avoid coupling with VCC routing and analog audio lines Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer Add GND vias around transmission line Ensure no other signals are routed parallel to transmission line, or that other signals cross on adjacent metal layer If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the Coplanar Waveguide model for 50 characteristic impedance calculation Dont route microstrip line below discrete component or other mechanics placed on top layer When terminating transmission line on antenna connector (or antenna pad) it is very important to strictly follow the connector manufacturers recommended layout GND layer under RF connectors and close to buried vias should be cut out in order to remove stray capacitance and thus keep the RF line 50 . In most cases the large active pad of the integrated antenna or antenna connector needs to have a GND keep-out (i.e. clearance) at least on first inner layer to reduce parasitic capacitance to ground. Note that the layout recommendation is not always available from connector manufacturer: e.g. the classical SMA Pin-Through-Hole needs to have GND cleared on all the layers around the central pin up to annular pads of the four GND posts. Check 50 impedance of ANT and ANT_DIV lines Ensure no coupling occurs with other noisy or sensitive signals The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna to ensure that uncorrelated signals are received at each antenna, because signal improvement is dependent on the cross correlation and relative signal strength levels between the two received signals. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation 3G.G2-HW-10002-A2 Preliminary Design-In Page 107 of 159 LISA-U series - System Integration Manual Figure 55: GND keep-out area on top layer around ANT and ANT_DIV pads and on buried layer below ANT and ANT_DIV pads Any RF transmission line on PCB should be designed for 50 characteristic impedance. Ensure no coupling occurs with other noisy or sensitive signals. Additional guidelines for products marked with the FCC logo - United States only LISA-U series modules can only be used with a host antenna circuit trace layout according to these guidelines; a host system designer must follow the guidelines to keep the original Grant of LISA-U series modules. Strict compliance to the layout reference design already approved (described in the following guidelines) is required to ensure that only approved antenna shall be used in the host system. If in a host system there is any difference from the trace layout already approved, it requires a Class II permissive change or a new grant as appropriate as FCC defines. Compliance of this device in all final host configurations is the responsibility of the Grantee. The approved reference design for LISA-U series modules has a structure of 4 layers described in the following. The Layer 1 (top layer, see Figure 56) provides a micro strip line to connect the ANT pin of the LISA-U series module to the antenna connector. The ANT pin of the LISA-U series module must be soldered on the designed pad which is connected to the antenna connector by a micro strip. The characteristics of the micro strip line

(coplanar wave guide) are the following:

Thickness = 0.035 mm Width = 0.26 mm Length = 7.85 mm Gap (signal to GND) = 0.5 mm The micro strip line must be designed to achieve 50 characteristic impedance: the dimensions of the micro strip line must be calculated in a host system according to PCB characteristics provided by PCB manufacturer. 3G.G2-HW-10002-A2 Preliminary Design-In Page 108 of 159 Min. 500 umMin. 250 umTop layerBuried metal layerGND planeMicrostrip50 ohm LISA-U series - System Integration Manual Figure 56: Layer 1 (top layer) of u-blox approved interface board for LISA-U series modules The thickness of the dielectric (FR4 Prepreg 1080) from Layer 1 (top layer) to Layer 2 (inner layer) is 0.27 mm. The Layer 2 (inner layer, described in Figure 57) provides a GND plane. Layer 2 thickness is 0.035 mm. Figure 57: Layer 2 (inner layer) of u-blox approved interface board for LISA-U series modules The dielectric thickness (FR4 Laminate 7628) from Layer 2 (inner layer) to Layer 3 (inner layer) is 0.76 mm. The Layer 3 (inner layer, described in Figure 58) is designed for signals routing and GND plane. Layer 3 thickness is 0.035 mm. 3G.G2-HW-10002-A2 Preliminary Design-In Page 109 of 159 Pad designed for the ANT pinAntenna connectorMicrostrip line LISA-U series - System Integration Manual Figure 58: Layer 3 (inner layer) of u-blox approved interface board for LISA-U series modules The dielectric thickness (FR4 Prepreg 1080) from Layer 3 (inner layer) to Layer 4 (bottom layer) is 0.27 mm. The Layer 4 (bottom layer, described in Figure 59) is designed for signals routing, components placement and GND plane. Layer 4 thickness is 0.035 mm. Figure 59: Layer 4 (bottom layer) of u-blox approved interface board for LISA-U series modules The antenna gain must not exceed the levels reported in the chapter 1.15.3.2 to preserve the original u-blox FCC ID. The antenna must be installed and operated with a minimum distance of 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Under the requirements of FCC Section 15.212(a)-iv, the module must contain a permanently attached antenna, or contain an unique antenna connector, and be marketed and operated only with specific antenna(s). In accordance with FCC Section 15.203, the antenna should use a unique coupling connector to the approved reference design for LISA-U series modules, to ensure that the design will not be deployed with antenna of different characteristic from the approved type. 3G.G2-HW-10002-A2 Preliminary Design-In Page 110 of 159 LISA-U series - System Integration Manual The use of standard SMA type connector is not permitted, as its standard usage allows easy replacement of the attached antenna. However RP-SMA (Reverse-Polarized-SMA) connector type fulfills the minimum requirements to prevent exchangeability of antenna on the reference design. 2.2.1.2 Main DC supply connection The DC supply of LISA-U series modules is very important for the overall performance and functionality of the integrated product. For detailed description, check the design guidelines in section 1.5.2. Some main characteristics are:

VCC pins are internally connected, but it is recommended to use all the available pins in order to minimize the power loss due to series resistance VCC connection may carry a maximum burst current in the order of 2.5 A. Therefore, it is typically implemented as a wide PCB line with short routing from DC supply (DC-DC regulator, battery pack, etc) The module automatically initiates an emergency shutdown if supply voltage drops below hardware threshold. In addition, reduced supply voltage can set a worst case operation point for RF circuitry that may behave incorrectly. It follows that each voltage drop in the DC supply track will restrict the operating margin at the main DC source output. Therefore, the PCB connection must exhibit a minimum or zero voltage drop. Avoid any series component with Equivalent Series Resistance (ESR) greater than a few milliohms Given the large burst current, VCC line is a source of disturbance for other signals. Therefore route VCC through a PCB area separated from sensitive analog signals. Typically it is good practice to interpose at least one layer of PCB ground between VCC track and other signal routing The VCC supply current supply flows back to main DC source through GND as ground current: provide adequate return path with suitable uninterrupted ground plane to main DC source A tank capacitor with low ESR is often used to smooth current spikes. This is most effective when placed as close as possible to VCC. From main DC source, first connect the capacitor and then VCC. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-DC output and minimize the VCC track length. Otherwise consider using separate capacitors for DC-DC converter and LISA-U series module tank capacitor. Note that the capacitor voltage rating may be adequate to withstand the charger over-voltage if battery-pack is used VCC is directly connected to the RF power amplifiers. Add capacitor in the pF range from VCC to GND along the supply path Since VCC is directly connected to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting to the LISA-U series modules in the worst case The large current generates a magnetic field that is not well isolated by PCB ground layers and which may interact with other analog modules (e.g. VCO) even if placed on opposite side of PCB. In this case route VCC away from other sensitive functional units The typical GSM burst has a periodic nature of approx. 217 Hz, which lies in the audible audio range. Avoid coupling between VCC and audio lines (especially microphone inputs) If VCC is protected by transient voltage suppressor / reverse polarity protection diode to ensure that the voltage maximum ratings are not exceeded, place the protecting device along the path from the DC source toward the LISA-U series module, preferably closer to the DC source (otherwise functionality may be compromised) VCC line should be wide and short. Route away from sensitive analog signals. 3G.G2-HW-10002-A2 Preliminary Design-In Page 111 of 159 LISA-U series - System Integration Manual 2.2.1.3 USB signal The LISA-U series modules include a high-speed USB 2.0 compliant interface with a maximum throughput of 480 Mb/s (see Section 1.9.3). Signals USB_D+ / USB_D- carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. Characteristic impedance of USB_D+ / USB_D- lines is specified by USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Route USB_D+ / USB_D- lines as a differential pair Ensure the differential characteristic impedance is as close as possible to 90 Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area 2.2.1.4 Analog audio (LISA-U120 / LISA-U130 only) Accurate analog audio design is very important to obtain clear and high quality audio. The GSM signal burst has a repetition rate of 217 Hz that lies in the audible range. A careful layout is required to reduce the risk of noise from audio lines due to both VCC burst noise coupling and RF detection. Analog audio is separated in the two paths, 1. Audio Input (uplink path): MIC_P / MIC_N 2. Audio Outputs (downlink path): SPK_P / SPK_N The most sensitive is the uplink path, since the analog input signals are in the microVolts range. Avoid coupling of any noisy signals to microphone input lines It is strongly recommended to route MIC signals away from battery and RF antenna lines. Try to skip fast switching digital lines as well Keep ground separation from other noisy signals. Use an intermediate GND layer or vias wall for coplanar signals MIC_P and MIC_N are sensed differentially within the module. Therefore they should be routed as a differential pair up to the audio signal source Cross other signals lines on adjacent layers with 90 crossing Place bypass capacitor for RF very close to active microphone. The preferred microphone should be designed for GSM applications which typically have internal built-in bypass capacitor for RF very close to active device. If the integrated FET detects the RF burst, the resulting DC level will be in the pass-band of the audio circuitry and cannot be filtered by any other device The bias for an external electret active microphone is not provided by the module. Verify that microphone is properly biased from an external low noise supply and verify that the supply noise is properly filtered Output audio lines have two separated configurations. SPK_P / SPK_N are high level balanced output. They are DC coupled and must be used with a speaker connected in bridge configuration Route SPK_P / SPK_N as differential pair, to reduce differential noise pick-up. The balanced configuration will help reject the common mode noise Consider enlarging PCB lines, to reduce series resistive losses, when the audio output is directly connected to low impedance speaker transducer Use twisted pair cables for balanced audio usage 3G.G2-HW-10002-A2 Preliminary Design-In Page 112 of 159 LISA-U series - System Integration Manual If DC decoupling is required, a large capacitor needs to be used, typically in the microFarad range, depending on the load impedance, in order to not increase the lower cut-off frequency of its High-Pass RC filter response 2.2.1.5 Module grounding Good connection of the module with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module. Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The shielding metal tabs are connected to GND, and are a fundamental part of electrical grounding and thermal heat-sink. Connect them to board solid ground layer, by soldering them on the baseboard using PCB plated through holes connected to GND net If the application board is a multilayer PCB, then it is required to connect together each GND area with complete via stack down to main board ground layer It is recommended to implement one layer of the application board as ground plane Good grounding of GND pads will also ensure thermal heat sink. This is critical during call connection, when the real network commands the module to transmit at maximum power: proper grounding helps prevent module overheating 2.2.1.6 Other sensitive pins A few other pins on the LISA-U series modules requires careful layout. RTC supply (V_BCKP): avoid injecting noise on this voltage domain as it may affect the stability of sleep oscillator Power-On (PWR_ON): is the digital input to switch-on the LISA-U series modules. Ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request 2.2.1.7 High-speed digital pins The following high speed digital pins require careful layout:

Serial Peripheral Interface (SPI): can be used for high speed data transfer (UMTS/HSPA) between the LISA-U series modules and the host processor, with a data rate up to 26 Mb/s (see Section 1.9.3). The high-speed data rate is carried by signals SPI_SCLK, SPI_MISO and SPI_MOSI, while SPI_SRDY and SPI_MRDY behave as handshake signals with relatively low activity Digital Clock Output (CODEC_CLK): can be used to provide a 26 MHz or 13 MHz digital clock to an external audio codec Follow these hints for high speed digital pins layout:

High-speed signals become sources of digital noise, route away from RF and other sensitive analog signals Keep routing short and minimize parasitic capacitance to preserve digital signal integrity 3G.G2-HW-10002-A2 Preliminary Design-In Page 113 of 159 LISA-U series - System Integration Manual 2.2.1.8 Digital pins and supplies External Reset (RESET_N): input for external reset, a logic low voltage will reset the module SIM Card Interface (VSIM, SIM_CLK, SIM_IO, SIM_RST): the SIM layout may be critical if the SIM card is placed far away from the LISA-U series modules or in close proximity to the RF antenna. In the first case the long connection can cause the radiation of some harmonics of the digital data frequency. In the second case the same harmonics can be picked up and create self-interference that can reduce the sensitivity of GSM Receiver channels whose carrier frequency is coincidental with harmonic frequencies. The latter case, placing the RF bypass capacitors, suggested in Figure 21, near the SIM connector will mitigate the problem. In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges: add adequate ESD protection to protect module SIM pins near the SIM connector Digital Audio (I2S_CLK, I2S_RX, I2S_TX, I2S_WA and I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA): the I2S interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs DDC (SCL, SDA): the DDC interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs UART (TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR): the serial interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs General Purpose I/O (GPIOx): the general purpose input/output pins are generally not critical for layout Reserved pins: these pins are reserved for future use. Leave them unconnected on the baseboard USB detection (VUSB_DET): this input will generate an interrupt to the baseband processor for USB detection. The USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host to enable the USB interface of the module Interfaces Supply (V_INT): this supply output is generated by an integrated switching step down converter, used internally to supply the digital interfaces. Because of this, it can be a source of noise: avoid coupling with sensitive signals 3G.G2-HW-10002-A2 Preliminary Design-In Page 114 of 159 LISA-U series - System Integration Manual 2.2.2 Footprint and paste mask The following figure describes the footprint and provides recommendations for the paste mask for LISA-U series modules. These are recommendations only and not specifications. Note that the copper and solder masks have the same size and position. Figure 60: LISA-U series modules suggested footprint and paste mask To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the volume outside of the module by defining the dimensions of the paste mask to form a T-shape (or equivalent) extending beyond the copper mask. The solder paste should have a total thickness of 150 m. The paste mask outline needs to be considered when defining the minimal distance to the next component. The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. The bottom layer of LISA-U1 series modules has one unprotected copper area for GND, shown in Figure 61. The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in Figure 62. Consider No-routing areas for the LISA-U series modules footprint as follows: signal keep-out area on the top layer of the application board, below LISA-U series modules, due to GND opening on module bottom layer (see Figure 61 and Figure 62). 3G.G2-HW-10002-A2 Preliminary Design-In Page 115 of 159 33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]0.8 mm [31.5 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]1.0 mm [39.3 mil]5.7 mm [224.4 mil]33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]1.2 mm [47.2 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]0.9 mm [35.4 mil]5.7 mm [224.4 mil]0.6 mm [23.6 mil]Stencil: 150 m LISA-U series - System Integration Manual Figure 61: Signals keep-out area on the top layer of the application board, below LISA-U1 series modules Figure 62: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 3G.G2-HW-10002-A2 Preliminary Design-In Page 116 of 159 33.2 mm11.85 mm22.4 mm5.3 mm5.25 mm1.4 mm1.0 mmPIN 1LISA-U1 bottom side (through module view)Exposed GND on LISA-U1 module bottom layerSignals keep-out area on application board33.2 mm5.25 mm22.4 mm5.3 mm5.25 mm5.3 mm1.3 mm1.4 mm1.0 mmPIN 1LISA-U2 bottom side (through module view)Exposed GND on LISA-U2 module bottom layerSignals keep-out areas on application board LISA-U series - System Integration Manual 2.2.3 Placement Optimize placement for minimum length of RF line and closer path from DC source for VCC. Make sure that RF and analog circuits are clearly separated from any other digital circuits on the system board. Provide enough clearance between the module and any external part due to solder and paste masks design. Milled edges that are present at module PCB corners, away from module pins metallization, can slightly increase module dimensions from the width and the height described in the mechanical specifications sections of LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]: provide enough clearance between module PCB corners and any other external part mounted on the application board. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the LISA-U series modules: avoid placing temperature sensitive devices (e.g. GPS receiver) close to the module. 3G.G2-HW-10002-A2 Preliminary Design-In Page 117 of 159 LISA-U series - System Integration Manual 2.3 Thermal aspects The operating temperature range is specified in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. The most critical condition concerning thermal performance is the uplink transmission at maximum power (data upload or voice call in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks; however the application should be correctly designed to cope with it. During transmission at maximum RF power the LISA-U series modules generate thermal power that can exceed 2 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the number of allocated TX slot and modulation (GMSK or 8PSK) or data rate (WCDMA), transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The Module-to-Ambient thermal resistance (Rth,M-A) of LISA-U series modules mounted on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper in still air conditions ranges between 9 and 12 C/W. The spreading of Rth,M-A depends on the operating condition (e.g. 2G or 3G mode, transmit band): the overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. With this setup, the increase of the module temperature5 referred to idle state initial condition6 is:

around 7C during a voice call at maximum power 19C during GPRS data transfer with 4 TX slots 16C during EDGE data transfer with 4 TX slots up to 25C in UMTS connection at max TX power Case-to-Ambient thermal resistance value will be different for other mechanical deployments of the module, e.g. PCB with different size and characteristics, mechanical shells enclosure, or forced air flow. The increase of thermal dissipation, i.e. reducing the thermal resistance, will decrease the operating temperature for internal circuitry of LISA-U series modules for a given operating ambient temperature. This improves the device long-term reliability for applications operating at high ambient temperature. A few techniques may be used to reduce the thermal resistance in the application:

Forced ventilation air-flow within mechanical enclosure Heat sink attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the wireless module Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete via stack down to main ground layer For example, after the installation of a robust aluminum heat-sink with forced air ventilation on the back of the same application board described above, the Module-to-Ambient thermal resistance is reduced to 1.5 3.5 C/W. The effect of lower Rth,M-A can be seen from the module temperature which now becomes:

around 1.5C above the ambient temperature during a voice call at maximum power 3C during GPRS data transfer with 4 TX slots 2.5C during EDGE data transfer with 4 TX slots 5.5C in UMTS connection at max TX power 5 Temperature is measured by internal sensor of wireless module 6 Steady state thermal equilibrium is assumed. The modules temperature in idle state can be considered equal to ambient temperature 3G.G2-HW-10002-A2 Preliminary Design-In Page 118 of 159 LISA-U series - System Integration Manual 2.4 Antenna guidelines Antenna characteristics are essential for good functionality of the module. Antenna radiating performance has direct impact on the reliability of connections over the Air Interface. A bad termination of the ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) can result in poor performance of the module. The following parameters should be checked:

Item Impedance Frequency Range Recommendations 50 nominal characteristic impedance 824..960 MHz (GSM 850, GSM 900, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1) 824..960 MHz (GSM 850, GSM 900, UMTS B5) 1710..1990 MHz (GSM 1800, GSM 1900, UMTS B2) Depends on the LISA-U series module HW version and on the Mobile Network used. LISA-U100, LISA-U120:

LISA-U110, LISA-U130:

LISA-U200-00:

LISA-U200-01, LISA-U230-01:

824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2, UMTS B4) 824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2) Input Power V.S.W.R Return Loss

>2 W peak

<2:1 recommended, <3:1 acceptable S11<-10 dB recommended, S11<-6 dB acceptable Table 45: General recommendation for GSM antenna The antenna gain shall remain below the levels reported in the chapter 1.15.3.2 to preserve the original u-blox FCC ID. Please note that some 2G and 3G bands are overlapping. This depends on worldwide band allocation for telephony services, where different bands are deployed for different geographical regions. If the LISA-U110, LISA-U130 or LISA-U2 series modules are planned for use on the entire supported bands, then an antenna that supports the 824..960 MHz and the 1710..2170 MHz frequency range should be selected. If the LISA-U100 or LISA-U120 modules are planned for use with the entire range of supported bands, then an antenna that supports the 824..960 MHz and the 1710..1990 MHz frequency range should be selected. Otherwise, for fixed applications in specific geographical region, antenna requirements can be relaxed for non-

deployed frequency bands. Refer to the operating RF frequency bands table in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2] for the detailed uplink and downlink frequency ranges of each supported band. LISA-U230 modules provide 2G and 3G dynamic receive diversity (Rx diversity) capability to improve the quality and reliability of the wireless link. This feature can be optionally used connecting a second antenna to the ANT_DIV pin, to receive an RF input signal that is processed by the module to increase the performance. All the antenna guidelines and recommendations reported are applicable also to the Rx diversity antenna design, even if the antenna for the Rx diversity is not used to transmit. GSM antennas are typically available as:

Linear monopole: typical for fixed applications. The antenna extends mostly as a linear element with a dimension comparable to lambda/4 of the lowest frequency of the operating band. Magnetic base may be available. Cable or direct RF connectors are common options. The integration normally requires the fulfillment of some minimum guidelines suggested by antenna manufacturer Patch-like antenna: better suited for integration in compact designs (e.g. mobile phone). These are mostly custom designs where the exact definition of the PCB and product mechanical design is fundamental for tuning of antenna characteristics 3G.G2-HW-10002-A2 Preliminary Design-In Page 119 of 159 LISA-U series - System Integration Manual For integration observe these recommendations:

Ensure 50 antenna termination, minimize the V.S.W.R. or return loss, as this will optimize the electrical performance of the module. See section 2.4.1 Select antenna with best radiating performance. See section 2.4.2 If a cable is used to connect the antenna radiating element to application board, select a short cable with minimum insertion loss. The higher the additional insertion loss due to low quality or long cable, the lower the connectivity Follow the recommendations of the antenna manufacturer for correct installation and deployment Do not include antenna within closed metal case Do not place the main antenna in close vicinity to end user since the emitted radiation in human tissue is limited by S.A.R. regulatory requirements Do not use directivity antenna since the electromagnetic field radiation intensity is limited in some countries Take care of interaction between co-located RF systems since the GSM transmitted power may interact or disturb the performance of companion systems Place antenna far from sensitive analog systems or employ countermeasures to reduce electromagnetic compatibility issues that may arise The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna to ensure uncorrelated signals received at each antenna, because signal improvement is dependent on the cross correlation and relative signal strength levels between the two received signals. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels 2.4.1 Antenna termination The LISA-U series modules are designed to work on a 50 load on all the supported frequency bands. Therefore, to reduce as much as possible performance degradation due to antenna mismatch, the following requirements should be met:

load. However, real antennas have no perfect 50 Measure the antenna termination with a network analyzer: connect the antenna through a coaxial cable to the measurement device, the |S11| indicates which portion of the power is delivered to antenna and which portion is reflected by the antenna back to the module output. A good antenna should have an |S11| below -10 dB over the entire frequency band. Due to miniaturization, mechanical constraints and other design issues, this value will not be achieved. An |S11| value of about -6 dB - (in the worst case) - is acceptable. Figure 63 shows an example of this measurement:

Figure 63: |S11| sample measurement of a penta-band antenna that covers in a small form factor the 4 GSM bands (850 MHz, 900 MHz, 1800 MHz and 1900 MHz) and the UMTS Band I 3G.G2-HW-10002-A2 Preliminary Design-In Page 120 of 159 LISA-U series - System Integration Manual Figure 64 shows comparable measurements performed on a wideband antenna. The termination is better, but the size of the antenna is considerably larger. Figure 64: |S11| sample measurement of a wideband antenna 2.4.2 Antenna radiation An indication of the antennas radiated power can be approximated by measuring the |S21| from a target antenna to the measurement antenna, using a network analyzer with a wideband antenna. Measurements should be done at a fixed distance and orientation, and results compared to measurements performed on a known good antenna. Figure 65 through Figure 66 show measurement results. A wideband log periodic-like antenna was used, and the comparison was done with a half lambda dipole tuned at 900 MHz frequency. The measurements show both the |S11| and |S21| for the penta-band internal antenna and for the wideband antenna. Figure 65: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a penta-band internal antenna (yellow/cyan) The half lambda dipole tuned at 900 MHz is known and has good radiation performance (both for gain and directivity). Then, by comparing the |S21| measurement with antenna under investigation for the frequency where the half dipole is tuned (e.g. marker 3 in Figure 65) it is possible to make a judgment on the antenna under test:

if the performance is similar then the target antenna is good. 3G.G2-HW-10002-A2 Preliminary Design-In Page 121 of 159 LISA-U series - System Integration Manual Figure 66: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a wideband commercial antenna (yellow/cyan) Instead if |S21| values for the tuned dipole are much better than the antenna under evaluation (like for marker 1/2 area of Figure 66, where dipole is 5 dB better), then it can be argued that the radiation of the target antenna

(the wideband dipole in this case) is considerably less. The same procedure should be repeated on other bands with half wavelength dipole re-tuned to the band under investigation. For good antenna radiation performance, antenna dimensions should be comparable to a quarter of the wavelength. Different antenna types can be used for the module, many of them (e.g. patch antennas, monopole) are based on a resonating element that works in combination with a ground plane. The ground plane, ideally infinite, can be reduced down to a minimum size that must be similar to one quarter of the wavelength of the minimum frequency that has to be radiated (transmitted/received). Numerical sample: frequency = 1 GHz wavelength = 30 cm minimum ground plane (or antenna size) = 7.5 cm. Below this size, the antenna efficiency is reduced. 2.4.3 Antenna detection functionality The internal antenna detect circuit is based on ADC measurement at ANT: the RF port is DC coupled to the ADC unit in the baseband chip which injects a DC current (10 A for 128 s) on ANT and measures the resulting DC voltage to evaluate the resistance from ANT pad to GND. The antenna detection is forced by the +UANTR AT command: refer to the u-blox AT Commands Manual [3] for more details on how to access this feature. To achieve antenna detection functionality, use an RF antenna with built-in resistor from ANT signal to GND, or implement an equivalent solution with a circuit between the antenna cable connection and the radiating element as shown in Figure 67. 3G.G2-HW-10002-A2 Preliminary Design-In Page 122 of 159 LISA-U series - System Integration Manual Figure 67: Antenna detection circuit and antenna with diagnostic resistor Examples of components for the antenna detection diagnostic circuit are reported in the following table:

Description Part Number - Manufacturer DC Blocking Capacitor Murata GRM1555C1H220JA01 or equivalent RF Choke Inductor Resistor for Diagnostic Murata LQG15HS68NJ02, LQG15HH68NJ02 or equivalent (Self Resonance Frequency ~1GHz) 15 k 5%, various Manufacturers Table 46: Example of components for the antenna detection diagnostic circuit Please note that the DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 67, the measured DC resistance will always be at the limits of the measurement range (respectively open or short), and there will be no mean to distinguish between a defect on antenna path with similar characteristics

(respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and to avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example:

Consider a GSM antenna with built-in DC load resistor of 15 k . Using the +UANTR AT command, the module reports the resistance value evaluated from ANT connector to GND:

Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected 3G.G2-HW-10002-A2 Preliminary Design-In Page 123 of 159 Application BoardAntenna AssemblyDiagnostic CircuitLISA-U seriesADCCurrent SourceRF ChokeDC BlockingFront-End RF ModuleRF ChokeDC BlockingRadiating ElementZo=50 Resistor for DiagnosticCoaxial Antenna CableANT LISA-U series - System Integration Manual Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit over range report (see u-blox AT Commands Manual [3]) means that that the antenna is not connected or the RF cable is broken Reported values below the measurement range minimum limit (1 k) will highlight a short to GND at antenna or along the RF cable Measurement inside the valid measurement range and outside the expected range may indicate an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method 3G.G2-HW-10002-A2 Preliminary Design-In Page 124 of 159 LISA-U series - System Integration Manual 2.5 ESD precautions 2.5.1 ESD immunity test overview The immunity of the device (i.e. the application board where LISA-U series module is mounted) to the Electrostatic Discharge (ESD) must be certified in compliance to the testing standard CENELEC EN 61000-4-2 [10]

and the radio equipment standards ETSI EN 301 489-1 [11], ETSI EN 301 489-7 [12], ETSI EN 301 489-24 [13], which requirements are summarized in Table 47. The ESD immunity test is performed at the enclosure port, defined by ETSI EN 301 489-1 [11] as the physical boundary through which the electromagnetic field radiates. If the device implements an integral antenna, the enclosure port is seen as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port includes the antenna element and its interconnecting cable surfaces. The applicability of ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489-1 [11]. Applicability of ESD immunity test to the relative device ports or the relative interconnecting cables to auxiliary equipments, depends on device accessible interfaces and manufacturer requirements, as defined by ETSI EN 301 489-1 [11]. Contact discharges are performed at conductive surfaces, while air discharges are performed at insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000-4-2 [10]. For the definition of integral antenna, removable antenna, antenna port, device classification refer to ETSI EN 301 489-1 [11]. The contact and air discharges are defined in CENELEC EN 61000-4-2 [10]. Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration Contact Discharge Air Discharge 4 kV 8 kV Table 47: Electromagnetic Compatibility ESD immunity requirements as defined by standards CENELEC EN 61000-4-2, ETSI EN 301 489-1 V1.8.1, ETSI EN 301 489-7 V1.3.1, ETSI EN 301 489-24 V1.4.1 2.5.2 ESD immunity test of LISA-U series reference design Although electromagnetic compatibility (EMC) certification must be performed by the final application of the radio equipment under test (i.e. the application board where LISA-U series module is mounted), EMC certification (including ESD immunity) have been successfully performed on LISA-U1 series and LISA-U200-00 modules reference design according to CENELEC EN 61000-4-2 [10], ETSI EN 301 489-1 [11], ETSI EN 301 489-7

[12] and ETSI EN 301 489-24 [13] standards. The EMC approved reference design consists of a LISA-U1 series or a LISA-U200-00 module soldered on a motherboard which provides an interface to power supply, SIM card, headset and communication port. An external antenna is connected to an SMA connector provided on the motherboard. Since an external antenna is used, the antenna port can be separated from the enclosure port. The reference design is not enclosed in a box so the enclosure port is not indentified with physical surfaces. Therefore, some test cases cannot be applied. Only the antenna port is identified as accessible for direct ESD exposure. The reference application implements all precautions described in the section 2.5.3. ESD immunity test results and applicability are reported in Table 48 according to test requirements CENELEC EN 61000-4-2 [10], ETSI EN 301 489-1 [11], ETSI EN 301 489-7 [12] and ETSI EN 301 489-24 [13]. 3G.G2-HW-10002-A2 Preliminary Design-In Page 125 of 159 LISA-U series - System Integration Manual Category Application Immunity Level Contact Discharge to coupling planes (indirect contact discharge) Enclosure Contact Discharges to conducted surfaces (direct contact discharge) Enclosure port Contact Discharges to conducted surfaces (direct contact discharge) Antenna port Air Discharge at insulating surfaces Air Discharge at insulating surfaces

(only antenna with completely insulating surface can be used) Enclosure port Antenna port

(only antenna with completely insulating surface can be used)

+2 kV / -2 kV

+4 kV / -4 kV Not Applicable7 Not Applicable8 Not Applicable9

+2 kV /

+4 kV /

+8 kV /

Table 48: Enclosure ESD immunity level (as defined by standards CENELEC EN 61000-4-2, ETSI EN 301 489-1 V1.8.1, ETSI EN 301 489-7 V1.3.1, ETSI EN 301 489-24 V1.4.1) of LISA-U1 series and LISA-U200-00 modules application reference design 7 LISA-U1 series or LISA-U200-00 module mounted on application design:

Not Applicability: EUT with insulating enclosure surface, EUT without enclosure surface Applicability: EUT with conductive enclosure surface 8 LISA-U1 series or LISA-U200-00 module mounted on application design:

Not Applicability: Antenna with insulating surface Applicability: Antenna with conductive surface 9 LISA-U1 series or LISA-U200-00 module mounted on application design:

Applicability: EUT with insulating enclosure surface Not Applicability: EUT with conductive enclosure surface, EUT without enclosure surface 3G.G2-HW-10002-A2 Preliminary Design-In Page 126 of 159 LISA-U series - System Integration Manual 2.5.3 ESD application circuits The application circuits described in this section should be implemented, depending on the application board handling, to satisfy ESD immunity test requirements. These are defined in CENELEC EN 61000-4-2 [10], ETSI EN 301 489-1 [11] and ETSI EN 301 489-7 [12], and performed at the device enclosure in compliance to the category level defined in ETSI EN 301 489-1 [11]. The test requirements are summarized in Table 47. Antenna interface With LISA-U1 series modules, the ANT pin provides ESD immunity up to 500 V (contact and air discharge according to IEC 61000-4-2): higher protection level is required if the line is externally accessible on the device

(i.e. the application board where LISA-U1 series module is mounted). The following precautions are suggested to satisfy ESD immunity test requirements using LISA-U1 series modules:

If the device implements an embedded antenna, the insulating enclosure of the device should provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces With the LISA-U200-00 module, the ANT pin provides ESD immunity up to 1000 V (contact and air discharge according to IEC 61000-4-2): higher protection level is required if the line is externally accessible on the device

(i.e. the application board where LISA-U200-00 module is mounted). The following precautions are suggested for satisfying ESD immunity test requirements using LISA-U200-00 modules:

If the device implements an embedded antenna, the device insulating enclosure should provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces If the device implements an external antenna and the antenna and its connecting cable dont provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces, an external high pass filter, consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil

(Murata LQG15HN39NJ102) should be implemented at the antenna port as described in Figure 68 Antenna detection functionality is not provided when implementing the high pass filter described in Figure 68 and Table 49, as ESD protection for the LISA-U200-00 antenna port. 3G.G2-HW-10002-A2 Preliminary Design-In Page 127 of 159 LISA-U series - System Integration Manual Figure 68: LISA-U200-00 antenna port ESD immunity protection application circuit Reference Description Part Number - Manufacturer C L 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 39 nH Multilayer Chip Inductor L0G 0402 5%

LQG15HN39NJ102 - Murata Table 49: Example of components for LISA-U200-00 antenna port ESD immunity protection application circuit With LISA-U230 modules, the ANT_DIV pin provides ESD immunity up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge: no further precaution to ESD immunity test is needed. RESET_N pin The following precautions are suggested for the RESET_N line of LISA-U series modules, depending on the application board handling, to satisfy ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure An additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure It is recommended to keep the connection line to RESET_N as short as possible Maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the RESET_N pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to accessible point For the RESET_N application circuit description refer to Figure 20 and Table 18 reported in section 1.6.3. 3G.G2-HW-10002-A2 Preliminary Design-In Page 128 of 159 External Antenna EnclosureApplication BoardLISA-U200-00ANTRadiating ElementZo= 50 OhmCoaxial Antenna CableAntenna PortEnclosure PortCL LISA-U series - System Integration Manual SIM interface The following precautions are suggested for LISA-U series modules SIM interface (VSIM, SIM_RST, SIM_IO, SIM_CLK pins), depending on the application board handling, to satisfy ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure It is suggested to use as short as possible connection lines at SIM pins Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if SIM interface pins are externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on each SIM interface line, close to accessible points (i.e. close to the SIM card holder) For the SIM interface application circuit description refer to Figure 21 and Table 21 reported in section 1.8. Other pins and interfaces All the module pins that are externally accessible on the device (i.e. the application board where LISA-U series module is mounted) should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489-1 [11]. Depending on applicability, to satisfy ESD immunity test requirements according to ESD category level, all the module pins that are externally accessible should be protected up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge applied to the enclosure surface. The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the relative pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection level:

USB interface: a very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140 ESD protection device) should be mounted on the USB_D+ and USB_D- lines, close to the accessible points (i.e. close to the USB connector) SPI interface: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on the SPI_MISO, SPI_MOSI, SPI_SCLK, SPI_MRDY, SPI_SRDY lines, close to accessible points CODEC_CLK: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0001) should be mounted on the CODEC_CLK line, close to accessible point Other pins: a general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the relative line, close to accessible point 3G.G2-HW-10002-A2 Preliminary Design-In Page 129 of 159 LISA-U series - System Integration Manual 3 Features description 3.1 Firmware (upgrade) Over AT (FOAT) Not supported by LISA-U1xx-00 modules. 3.1.1 Overview This feature allows upgrading the module Firmware over UART and USB, using AT Commands. AT Command AT+UFWUPD triggers a reboot followed by the upgrade procedure at specified a baud rate

(refer to u-blox AT Commands Manual [3] for more details) The Xmodem-1k protocol is used for downloading the new Firmware image via a terminal application A special boot loader on the module performs firmware installation, security verifications and module reboot Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware download from the Xmodem-1k handshake. After completing the upgrade, the module is reset again and wakes-up in normal boot 3.1.2 FOAT procedure The application processor must proceed in the following way:

Send the AT+UFWUPD command through the UART or over the USB interface, specifying the file type and the desired baud rate Reconfigure the serial communication at the selected baud rate, without flow control with the Xmodem-1k protocol Send the new FW image via Xmodem-1k 3.2 TCP/IP and UDP/IP Via the AT commands its possible to access the TCP/IP and UDP/IP functionalities over the Packet Switched data connection. For more details about AT commands see the u-blox AT Commands Manual [3]. Direct Link mode for TCP and UDP sockets is supported by all LISA-U series modules except LISA-U1xx-00 versions. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interface. 3.2.1 Multiple PDP contexts and sockets Two PDP context types are defined:

external PDP context: IP packets are built by the DTE, the MTs IP instance runs the IP relay function only internal PDP context: the PDP context (relying on the MTs TCP/IP stack) is configured, established and handled via the data connection management packet switched data commands described in u-blox AT commands manual [3]

Multiple PDP contexts are supported. The DTE can access these PDP contexts either alternatively through the physical serial port, or simultaneously through the virtual serial ports of the multiplexer (multiplexing mode MUX), with the following constraints:

Using the MTs embedded TCP/IP stack, only 1 internal PDP context is supported. This IP instance supports up to 7 sockets 3G.G2-HW-10002-A2 Preliminary Features description Page 130 of 159 LISA-U series - System Integration Manual Using only external PDP contexts, it is possible to have at most 3 IP instances (with 3 different IP addresses) simultaneously. If in addition the internal PDP context is used, at most 2 external PDP contexts can be activated Secondary PDP contexts (PDP contexts sharing the IP address of a primary PDP context) are also supported. Traffic Flow Filters for such secondary contexts shall be specified according to 3GPP TS 23.060 [19]. At most 2 secondary PDP contexts can be activated, since the maximum number of PDP contexts, both normal and secondary, is always 3. 3.3 FTP and FTPS Not supported by LISA-U1xx-00 modules. LISA-U series modules support the File Transfer Protocol and Secure File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. For more details about AT commands see u-blox AT Commands Manual [3]. 3.4 HTTP and HTTPS Not supported by LISA-U1xx-00 modules. HTTP and HTTPS clients are implemented in LISA-U series modules. HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation. Up to 4 client contexts can be simultaneously used. For more details about AT commands see the u-blox AT Commands Manual [3]. 3.5 AssistNow clients and GPS integration Not supported by LISA-U200-00 modules. For customers using u-blox GPS receivers, LISA-U series wireless modules feature embedded AssistNow clients. AssistNow A-GPS provides better GPS performance and faster Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [3]). LISA-U series modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox GPS receivers is available via the LISA-U series, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the GPS device power-on/off. This means that GSM/WCDMA and GPS can be controlled through a single serial port from any host processor. 3.6 Jamming Detection Not supported by LISA-U1xx-00 modules. In real network situations modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operators choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operators carriers entitled to give access to the GSM/UMTS service. 3G.G2-HW-10002-A2 Preliminary Features description Page 131 of 159 LISA-U series - System Integration Manual The Jamming Detection Feature detects such artificial interference and reports the start and stop of such conditions to the client, which can react appropriately by e.g. switching off the radio transceiver in order to reduce power consumption and monitoring the environment at constant periods. The feature consists of detecting, at radio resource level, an anomalous source of interference and signaling it to the client with an unsolicited indication when the detection is entered or released. The jamming condition occurs when:

The module has lost synchronization with the serving cell and cannot select any other cell The band scan reveals at least n carriers with power level equal or higher than threshold On all such carriers, no synchronization is possible The number of minimum disturbing carriers and the power level threshold can be configured by the client by using the AT+UCD command [3]. The jamming condition is cleared when any of the above mentioned statements does not hold. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command (for more details refer to the u-blox AT Commands Manual [3]). 3.7 In-Band modem Not supported by LISA-U100, LISA-U110, LISA-U120-00, LISA-U130-00, LISA-U200-00 modules versions. LISA-U series modules implements the in-Band modem solution for eCall according to the 3GPP TS 26.267 specification [14]. According to the eCall (Pan-European automatic in-vehicle emergency call system) specification, an eCall must be generated automatically or manually following an car accident using GSM cellular service 112. When activated, the in-vehicle eCall system (IVS) creates an emergency call carrying both voice and data (e.g. vehicle GPS position) directly to the nearest 112 Public Safety Answering Point (PSAP) to quickly decide upon detaching rescue services to the known position. Figure 69: In-Band modem diagram flow In-Band modem allows the fast and reliable transmission of vehicle Minimum Set of Data (MSD - 140 bytes) and the establishment of a voice emergency call using the same physical channel (voice channel) without any modifications of the existing cellular network architecture. In-Band modem is a mandatory feature to meet the eCall requirements and to develop in vehicle devices fully supporting eCall. 3.8 Smart Temperature Management Wireless modules independent of the specific model always have a well defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. 3G.G2-HW-10002-A2 Preliminary Features description Page 132 of 159 LISA-U series - System Integration Manual Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/isnt air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. 3.8.1 Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. Please refer to u-blox AT Commands Manual [3] for more details. The wireless module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the wireless module: the measured value could be different from the environmental temperature (Ta). Figure 70: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 70) named t-2, t-1, t+1 and t+2. Within the first limit, (t-1 < Ti < t+1), the wireless module is in the normal working range, the Safe Area In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the wireless module is still inside the valid temperature range, but the measured temperature approaches the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage For security reasons the shutdown is suspended in case an emergency call in progress. In this case the device will switch off at call termination. The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled there is no embedded protection against disallowed temperature conditions. Figure 71 shows the flow diagram implemented in LISA-U series modules for the Smart Temperature Supervisor. 3G.G2-HW-10002-A2 Preliminary Features description Page 133 of 159 Warningareat-1t+1t+2t-2Valid temperature rangeSafeareaDangerousarea Dangerousarea Warningarea LISA-U series - System Integration Manual Figure 71: Smart Temperature Supervisor (STS) flow diagram 3G.G2-HW-10002-A2 Preliminary Features description Page 134 of 159 IF STS enabledRead temperatureIF(t-1<Ti<t+1)IF(t-2<Ti<t+2)Send notification (warning)Send notification(dangerous)WaitemergencycallterminationIFemerg. call in progressShut the device downYesNoYesYesNoNoNoYesSend shutdownnotificationFeature enabled (full logic or indication only)IF Full Logic EnabledFeature disabled: no actionTemperature is within normal operating rangeYesTempetature is within warning areaTempetature is outside valid temperature rangeNoFeatuere enabled in full logic modeFeature enabled in indication only mode:no further actionsSend notification (safe)Previously outside of Safe AreaTempetature is back to safe areaNoNo furtheractionsYes LISA-U series - System Integration Manual 3.8.2 Threshold Definitions When the application of wireless module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the wireless module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat This behavior is partially compensated by the definition of the upper shutdown threshold (t +2) that is slightly higher than the declared environmental temperature limit. The temperature thresholds are defined according the Table 50. Symbol Parameter Temperature Remarks t-2 t-1 t+1 t+2 Low temperature shutdown 40 C Equal to the absolute minimum temperature rating for the wireless module (the lower limit of the extended temperature range) Low temperature warning 30 C 10C above t-2 High temperature warning

+77 C 20C below t+2. The higher warning area for upper range ensures that any countermeasures used to limit the thermal heating will become effective, even considering some thermal inertia of the complete assembly. High temperature shutdown

+97 C Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient temperature Ta in the reference setup (*) equals the absolute maximum the extended temperature range) temperature limit of

(upper rating

(*)LISA-U series module mounted on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper within climatic chamber Table 50: Thresholds definition for Smart Temperature Supervisor on the LISA-U series modules The sensor measures board temperature inside the shields, which can differ from ambient temperature. 3.9 Hybrid positioning and CellLocate Not supported by LISA-U1xx-00 and LISA-U200-00 modules versions. Although GPS is a widespread technology, its reliance on the visibility of extremely weak GPS satellite signals means that positioning is not always possible. Especially difficult environments for GPS are indoors, in enclosed or underground parking garages, as well as in urban canyons where GPS signals are blocked or jammed by multipath interference. The situation can be improved by augmenting GPS receiver data with cellular network information to provide positioning information even when GPS reception is degraded or absent. This additional information can benefit numerous applications. 3.9.1 Positioning through cellular information: CellLocate u-blox CellLocate enables the estimation of device position based on the parameters of the mobile network cells visible to the specific device. To estimate its position the u-blox Wireless module sends the CellLocate server the parameters of network cells visible to it using a UDP connection. In return the server provides the estimated position based on the CellLocate database. The u-blox Wireless module can either send the parameters of the visible home network cells only (normal scan) or the parameters of all surrounding cells of all mobile operators

(deep scan). 3G.G2-HW-10002-A2 Preliminary Features description Page 135 of 159 LISA-U series - System Integration Manual Normal scan is only possible in 2G mode. The CellLocate database is compiled from the position of devices which observed, in the past, a specific cell or set of cells (historical observations) as follows:

1. Several devices reported their position to the CellLocate server when observing a specific cell (the As in the picture represent the position of the devices which observed the same cell A) 2. CellLocate server defines the area of Cell A visibility 3. If a new device reports the observation of Cell A CellLocate is able to provide the estimated position from the area of visibility 3G.G2-HW-10002-A2 Preliminary Features description Page 136 of 159 4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of visibility. LISA-U series - System Integration Manual CellLocate is implemented using a set of two AT commands that allow configuration of the CellLocate service

(AT+ULOCCELL) and requesting position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy. The accuracy of the position estimated by CellLocate depends on the availability of historical observations in the specific area. 3.9.2 Hybrid positioning With u-blox Hybrid positioning technology, u-blox wireless devices can be triggered to provide their current position using either a u-blox GPS receiver or the position estimated from CellLocate. The choice depends on which positioning method provides the best and fastest solution according to the user configuration, exploiting the benefit of having multiple and complementary positioning methods. Hybrid positioning is implemented through a set of three AT commands that allow configuration of the GNSS receiver (AT+ULOCGNSS), configuration of the CellLocate service (AT+ULOCCELL), and requesting the position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy (if the position has been estimated by CellLocate), and additional parameters if the position has been computed by the GNSS receiver. The configuration of mobile network cells does not remain static (e.g. new cells are continuously added or existing cells are reconfigured by the network operators). For this reason, when a Hybrid positioning method has been triggered and the GNSS receiver calculates the position, a database self-learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy. The use of hybrid positioning requires a connection via the DDC (I2C) bus between the LISA-U series wireless module and the u-blox GPS receiver (Refer to chapter 1.10). Refer to GPS Implementation Application Note [16] for the complete description of the feature. u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate server u-blox is unable to track the SIM used or the specific device. 3G.G2-HW-10002-A2 Preliminary Features description Page 137 of 159 LISA-U series - System Integration Manual 4 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 4.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the LISA-U1 series Data Sheet [1], the LISA-U2 series Data Sheet [2] and u-blox Package Information Guide [21]. The LISA-U series modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. 4.2 Soldering 4.2.1 Soldering paste Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature: 217C Stencil Thickness:

150 m for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.2.2 The quality of the solder joints on the connectors (half vias) should meet the appropriate IPC specification. 4.2.2 Reflow soldering A convection type-soldering oven is strongly recommended over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the "IPC-7530 Guidelines for temperature profiling for mass soldering (reflow and wave) processes, published 2001". Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device!

Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. Please note that this preheat phase will not replace prior baking procedures. Temperature rise rate: max 3C/s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping. 3G.G2-HW-10002-A2 Preliminary Handling and soldering Page 138 of 159 LISA-U series - System Integration Manual Time: 60 120 s End Temperature: 150 - 200C If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of 217C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above 217C liquidus temperature: 40 - 60 s Peak reflow temperature: 245C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4C / s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Figure 72: Recommended soldering profile LISA-U series modules must not be soldered with a damp heat process. 3G.G2-HW-10002-A2 Preliminary Handling and soldering Page 139 of 159 PreheatHeatingCooling[C]Peak Temp. 245C[C]250250Liquidus Temperature21721720020040 - 60 sEnd Temp.max 4C/s150 - 200C150150max 3C/s60 - 120 s100Typical Leadfree100Soldering Profile5050Elapsed time [s]LISA-U series - System Integration Manual 4.2.3 Optical inspection After soldering the LISA-U series modules, inspect the modules optically to verify that he module is properly aligned and centered. 4.2.4 Cleaning Cleaning the soldered modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-

jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results use a "no clean" soldering paste and eliminate the cleaning step after the soldering. 4.2.5 Repeated reflow soldering Only a single reflow soldering process is encouraged for boards with a LISA-U series module populated on it. The reason for this is the risk of the module falling off due to high weight in relation to the adhesive properties of the solder. 4.2.6 Wave soldering Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. Only a single wave soldering process is encouraged for boards populated with LISA-U series modules. 4.2.7 Hand soldering Hand soldering is not recommended. 4.2.8 Rework The LISA-U series modules can be unsoldered from the baseboard using a hot air gun. After the module is removed, clean the pads before placing. Avoid overheating the module. Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty. 4.2.9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials affect the HF properties of the LISA-U series modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating. Conformal Coating of the module will void the warranty. 3G.G2-HW-10002-A2 Preliminary Handling and soldering Page 140 of 159 LISA-U series - System Integration Manual 4.2.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the LISA-U series modules before implementing this in the production. Casting will void the warranty. 4.2.11 Grounding metal covers Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interferences and noise. u-blox gives no warranty for damages to the LISA-U series modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. 4.2.12 Use of ultrasonic processes LISA-U series modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding etc.) may cause damage to the module. u-blox gives no warranty against damages to the LISA-U series modules caused by any Ultrasonic Processes. 3G.G2-HW-10002-A2 Preliminary Handling and soldering Page 141 of 159 LISA-U series - System Integration Manual 5 Product Testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested. Defective units are analyzed in detail to improve the production quality. This is achieved with automatic test equipment, which delivers a detailed test report for each unit. The following measurements are done:

Digital self-test (firmware download, Flash firmware verification, IMEI programming) Measurement of voltages and currents Adjustment of ADC measurement interfaces Functional tests (Serial interface communication, analog audio interface, real time clock, battery charger, temperature sensor, antenna detection, SIM card communication) Digital tests (GPIOs, digital interfaces) Measurement and calibration of RF characteristics in all supported bands (Receiver S/N verification, frequency tuning of reference clock, calibration of transmitter and receiver power levels) Verification of RF characteristics after calibration (modulation accuracy, power levels and spectrum performance are checked to be within tolerances when calibration parameters are applied) Figure 73: Automatic test equipment for module tests 5.2 Test parameters for OEM manufacturer Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer doesnt need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. An OEM manufacturer should focus on:

Module assembly on the device; it should be verified that:

o Soldering and handling process did not damaged the module components o All module pins are well soldered on device board o There are no short circuits between pins 3G.G2-HW-10002-A2 Preliminary Product Testing Page 142 of 159 LISA-U series - System Integration Manual Component assembly on the device; it should be verified that:

o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result. Module AT commands are used to perform functional tests (communication with host controller, check SIM card interface, check communication between module and GPS, GPIOs, etc.) and to perform RF performance tests. 5.2.1 Go/No go tests for integrated devices A Go/No go test is to compare the signal quality with a Golden Device in a position with excellent 2G/3G network coverage and after having dialed a call (refer to u-blox AT Commands Manual [3], AT+CSQ command:

<rssi>, <ber> parameters). These kinds of test may be useful as a go/no go test but not for RF performance measurements. This test is suitable to check the communication with host controller and SIM card, the audio and power supply functionality and verify if components at antenna interface are well soldered. 5.2.2 Functional tests providing RF operation Overall RF performance test of the device including antenna can be performed with basic instruments such as a standard spectrum analyzer and signal generator using an AT interface and AT+UTEST command. The AT+UTEST command gives a simple interface to set the module to Rx and Tx test modes ignoring 2G/3G signaling protocol. The command can set the module:

In transmitting mode in a specified channel and power level in all supported modulation schemes (single slot GMSK, single slot 8PSK, WCDMA) and bands 2G, 3G In receiving mode in a specified channel to returns the measured power level in all supported bands 2G, 3G The AT+UTEST command used to perform these functional tests is available on all LISA-U series modules versions except LISA-U1xx-00. Refer to u-blox AT Commands Manual [3], for AT+UTEST command syntax description. Refer to End user test Application Note [20], for AT+UTEST command user guide, limitations and examples of use. 3G.G2-HW-10002-A2 Preliminary Product Testing Page 143 of 159 LISA-U series - System Integration Manual Figure 74: Setup with spectrum analyzer and signal generator for radiated measurement This feature allows the measurement of the transmitter and receiver power levels to check component assembly related to the module antenna interface and to check other device interfaces from which depends the RF performance. To avoid module damage during transmitter test, a proper antenna according to module specifications or a 50 termination must be connected to ANT pin. To avoid module damage during receiver test the maximum power level received at ANT pin must meet module specifications. The AT+UTEST command sets the module to emit RF power ignoring 2G/3G signalling protocol. This emission can generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing purpose in controlled environments by qualified user and must not be used during the normal module operation. Follow instructions suggested in u-blox documentation. u-blox assumes no responsibilities for the inappropriate use of this feature. 3G.G2-HW-10002-A2 Preliminary Product Testing Page 144 of 159 Application BoardLISA-U seriesANTApplication ProcessorAT CommandsWireless AntennaSpectrum AnalyzerINWideband AntennaTXApplication BoardLISA-U seriesANTApplication ProcessorAT CommandsWireless AntennaSignalGeneretorOUTWideband AntennaRX LISA-U series - System Integration Manual Example of production tests for OEM manufacturer:

1. Trigger TX GMSK burst at low Power Control Level (lower than 15) or a RX measure reporting to check:

o o o o o If ANT pin is soldered If ANT pin is in short circuit If module was damaged during soldering process or during handling (ESD, mechanical shock) If antenna matching components on application board are soldered If integrated antenna is correctly connected To avoid module damage during transmitter test when good antenna termination is not guaranteed, use a low Power Control Level (i.e. PCL lower or equal to 15). u-blox assumes no responsibilities for module damaging caused by an inappropriate use of this feature. 2. Trigger TX GMSK burst at maximum PCL:

o To check if the power supply is correctly assembled and is able to deliver the required current 3. Trigger TX GMSK and 8PSK burst and WCDMA signal:

o o To measure current consumption To check if module components was damaged during soldering process or during handling (ESD, mechanical shock,) 4. Trigger RX measurement:

o o To test receiver signal level. Assuming that there are no losses between ANT pin or ANT_DIV pin and input power source, be aware that the power level estimated by the module can vary approximately within 3GPP tolerances for the average value To check if module was damaged during soldering process or during handling (ESD, mechanical shock) 5. Trigger TX GMSK and 8PSK burst and WCDMA signal and RX measurement to check:

o Overall RF performance of the device including antenna measuring TX and RX power levels 3G.G2-HW-10002-A2 Preliminary Product Testing Page 145 of 159 LISA-U series - System Integration Manual Appendix A Migration to LISA-U2 series wireless modules Migrating LISA-U1 series designs to LISA-U2 series modules is a fairly straightforward procedure. Nevertheless there are some points to be considered during the migration. Not all of the functionalities available with LISA-U1 series modules are supported by all LISA-U2 series modules versions. These include:

o Analog Audio Interfaces are not supported by all LISA-U2 series modules o Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00 o Embedded AssistNow Software, GPS via Modem, Hybrid positioning and CellLocate functionalities are supported by all LISA-U2 series modules versions except LISA-U200-00 o In-Band modem is supported by all LISA-U2 series modules versions except LISA-U200-00 A.1 Checklist for migration Have you chosen the optimal module?

For HSDPA category 14, 6-band 3G, Digital Audio Interfaces support, select the LISA-U230-01 version. For HSDPA category 8, 6-band 3G, Digital Audio Interfaces support, select the LISA-U200-01 version. For HSDPA category 8, 4-band 3G support, select the LISA-U200-00 version. Check LISA-U2 series Hardware Requirements Check the supported 3G bands for proper antenna circuit development, since LISA-U2 supports different 3G bands in comparison to LISA-U1 series wireless modules. Check audio requirements, since Analog Audio Interfaces are not supported by LISA-U2 series. Check audio requirements, since Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00. Check the PWR_ON input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the PWR_ON input by an open drain or open collector driver as recommended. Check the PWR_ON behavior, since LISA-U2xx-01 can be switched off forcing PWR_ON pin to the low level for at least 1 s. Check the RESET_N input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the RESET_N input by an open drain or open collector driver as recommended. Check the V_BCKP operating characteristics, since they are slightly changed in comparison to LISA-U1 series modules. Check board layout, since additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer. Check section A.3 Hardware migration. 3G.G2-HW-10002-A2 Preliminary Appendix Page 146 of 159 LISA-U series - System Integration Manual Check LISA-U2 series Software Requirements Not all of the functionalities available with LISA-U1 series modules are supported by all the LISA-U2 series modules versions. These include:

o Analog Audio Interfaces are not supported by all LISA-U2 series modules o Digital Audio Interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00 o Embedded AssistNow Software, GPS via Modem, Hybrid positioning and CellLocate functionalities are supported by all LISA-U2 series modules versions except LISA-U200-00 o In-band modem is supported by all LISA-U2 series modules versions except LISA-U200-00 Check section A.2 Software migration. A.2 Software migration A.2.1 Software migration from LISA-U1 series to LISA-U2 series wireless modules Software migration from LISA-U1 series to LISA-U2 series wireless modules is a straightforward procedure. Nevertheless there are some differences to be considered with firmware version. Like predecessors, LISA-U2 series wireless module supports AT commands according to 3GPP standards: TS 27.007 [5], TS 27.005 [6], TS 27.010 [7] and the u-blox AT command extension. Backward compatibility has been maintained as far as possible. For the complete list of supported AT commands and their syntax see u-blox AT Commands Manual [3]. A.3 Hardware migration A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series wireless modules LISA-U2 series wireless modules have been designed with backward compatibility in mind but some minor differences were unavoidable. These minor differences will however not be relevant for the majority of the LISA-U1 series designs. Clean and stable supply is required by LISA-U2 as by LISA-U1 series: low ripple and low voltage drop must be guaranteed at VCC pins. The voltage provided has to be within the normal operating range limits to allow module switch-on and has to be above the minimum limit of the extended operating range to avoid module switch-off. Consider that there are large current spikes in connected mode, when a GSM call is enabled. LISA-U2 series provide wider VCC input voltage range compared to LISA-U1 series. The ANT pin has 50 nominal characteristic impedance and must be connected to the antenna through a 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. The antenna and the whole RF circuit must provide optimal radiating characteristics on the entire supported bands: note that LISA-U2 supports different 3G bands in comparison to LISA-U1 series wireless modules. LISA-U230 modules provide the RF antenna input for Rx diversity on the pin 74 (named ANT_DIV): it has an impedance of 50 . The same pad is a reserved pin on LISA-U1 series and LISA-U200 modules. Analog audio interfaces are not supported by LISA-U2 series modules, but a second 4-wire I2S digital audio interface is provided instead of the 4 analog audio pins on all LISA-U2 series modules versions except LISA-U200-00. The same 4 pins can be configured as GPIO on all LISA-U2 series modules versions. 3G.G2-HW-10002-A2 Preliminary Appendix Page 147 of 159 LISA-U series - System Integration Manual Digital audio interfaces are supported by all LISA-U2 series modules versions except LISA-U200-00: the relative pins are configured as pad disabled on LISA-U200-00 version. PWR_ON and RESET_N input voltage thresholds are slightly changed in comparison to LISA-U1 series modules, but this is not relevant driving PWR_ON and RESET_N inputs by open drain / collector drivers as recommended. LISA-U2xx-01 modules can be switched off forcing PWR_ON pin to the low level for at least 1 s. V_BCKP operating characteristics are slightly changed in comparison to LISA-U1 series modules. The 5 pins of the SPI / IPC Serial Interface can be configured as GPIOs on LISA-U2xx-01 modules. LISA-U2 series wireless modules are SMT modules and come in the same compact form factor of LISA-U1 series, featuring Leadless Chip Carrier (LCC) packaging technology. Additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer. Detailed pinout and layout comparisons between LISA-U1 series and LISA-U2 series modules, with remarks for migration, are provided in the subsections A.3.2 and A.3.3. For more information regarding LISA-U1 and LISA-U2 series modules electrical characteristics refer to LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2]. A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series Figure 75: LISA-U1 series pin assignment Figure 76: LISA-U2 series pin assignment

(highlighted name/function changes) 3G.G2-HW-10002-A2 Preliminary Appendix Page 148 of 159 65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDYSPI_SRDYSPI_MISOSPI_MOSISPI_SCLKRSVD / SPK_NGNDRSVD / SPK_PRSVDGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039RSVD / MIC_PRSVD / MIC_N2829303132333435363738GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7675747372717069686766GNDRSVDGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U1Top View65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDY / GPIO14SPI_SRDY / GPIO13SPI_MISO / GPIO12SPI_MOSI / GPIO11SPI_SCLK / GPIO10GPIO9 / I2S1_WAGNDGPIO8 / I2S1_CLKRSVD / CODEC_CLKGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039GPIO7 / I2S1_TXDGPIO6 / I2S1_RXD2829303132333435363738GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND7675747372717069686766GNDRSVD / ANT_DIVGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U2Top View LISA-U1 LISA-U2 LISA-U series - System Integration Manual No Name Description 1 2 GND V_BCKP Ground RTC supply input/output Name GND V_BCKP Ground RTC supply input/output Description Remarks for Migration V_BCKP operating characteristics difference:

LISA-U1:

o V_BCKP output = 2.3V typ. o V_BCKP input = 1.0V min / 2.5V max LISA-U2:

o V_BCKP output = 1.8V typ. o V_BCKP input = 1.0V min / 1.9V max No difference:

V_INT output = 1.8V typ. No difference:

This pin must be connected to GND 3 4 5 6 7 8 9 GND GND GND DSR 10 RI 11 DCD 12 DTR 13 RTS 14 CTS 15 TXD 16 RXD GND V_INT Ground Digital Interfaces supply output GND V_INT Ground Digital Interfaces supply output RSVD RESERVED pin RSVD RESERVED pin Ground Ground Ground UART data set ready output UART ring indicator output UART data carrier detect output UART data terminal ready input UART ready to send input UART clear to send output UART transmitted data input UART received data output GND GND GND DSR RI DCD DTR RTS CTS TXD RXD Ground Ground Ground UART data set ready output No difference:

Circuit 107 (DSR) in ITU-T V.24. UART ring indicator output No difference:

Circuit 125 (RI) in ITU-T V.24. UART data carrier detect output No difference:

Circuit 109 (DCD) in ITU-T V.24. UART data terminal ready input No difference:

Circuit 108/2 (DTR) in ITU-T V. 24. UART ready to send input No difference:

Circuit 105 (RTS) in ITU-T V.24. UART clear to send output No difference:

Circuit 106 (CTS) in ITU-T V.24. UART transmitted data input No difference:

Circuit 103 (TxD) in ITU-T V.24. UART received data output No difference:

Circuit 104 (RxD) in ITU-T V.24. 17 GND Ground GND Ground 18 VUSB_DET USB detect input VUSB_DET USB detect input No difference:

Input for VBUS (5V typical) USB supply sense. 19 PWR_ON Power-on input PWR_ON Power-on input Forcing PWR_ON to the low level for at least 5 ms causes a switch-on of LISA-U1 and LISA-U2. PWR_ON operating voltage difference:

LISA-U1:

o L-level input = -0.30V min / 0.65V max o H-level input = 2.00 min / 4.20V max o External pull-up (e.g. to V_BCKP) required LISA-U2:

o L-level input = -0.30V min / 0.65V max o H-level input = 1.50V min / 4.40V max o External pull-up (e.g. to V_BCKP) required 20 GPIO1 GPIO GPIO1 GPIO Additional feature provided by LISA-U2:

LISA-U2xx-01 can be switched-off forcing PWR_ON pin to the low level for at least 1 s. By default, the pin is configured as Pad disabled, and can be alternatively configured to provide the GSM Tx Burst Indication, Network Status Indication or as GPIO Additional features provided by LISA-U2xx-01:

the pin can be alternatively configured to provide Module Status Indication 3G.G2-HW-10002-A2 Preliminary Appendix Page 149 of 159 LISA-U series - System Integration Manual LISA-U1 LISA-U2 No Name Description 21 GPIO2 GPIO Name GPIO2 Description Remarks for Migration GPIO No difference from LISA-U1xx-0x to LISA-U2xx-01:

By default, the pin is configured to provide the GPS Supply Enable function, and can be alternatively configured as GPIO Different configuration on LISA-U200-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO 22 RESET_N External reset input RESET_N External reset input Forcing RESET_N to the low level for at least 50 ms causes a hardware reset of LISA-U1 and LISA-U2. RESET_N operating voltage difference:

Internal 10k pull-up to V_BCKP (2.3V typ) LISA-U1:

o L-level input = -0.30V min / 0.65V max o H-level input = 1.69V min / 2.48V max o LISA-U2:

o L-level input = -0.30V min / 0.51V max o H-level input = 1.32V min / 2.01V max o Internal 10k pull-up to V_BCKP (1.8V typ) 23 GPIO3 GPIO GPIO3 GPIO 24 GPIO4 GPIO GPIO4 GPIO No difference from LISA-U1xx-00 to LISA-U2xx-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO No difference from LISA-U1xx-01 to LISA-U2xx-01:

By default, the pin is configured to provide the GPS Tx Data Ready function, and can be alternatively configured as GPIO. No difference from LISA-U1xx-00 to LISA-U2xx-00:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO No difference from LISA-U1xx-01 to LISA-U2xx-01:

By default, the pin is configured to provide the GPS RTC sharing (time aiding) function, and can be alternatively configured as GPIO. 25 GND Ground 26 USB_D-

USB Data Line D-

input/output GND USB_D-

Ground USB Data Line D-

input/output 27 USB_D+

USB Data Line D+

input/output USB_D+

USB Data Line D+

input/output 28 GND 29 GND 30 GND 31 GND 32 GND 33 GND 34 GND 35 GND 36 GND 37 GND 38 GND 39 RSVD MIC_N Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio input (neg.) GND GND GND GND GND GND GND GND GND GND GND GPIO6 I2S1_RXD /

GPIO6 3G.G2-HW-10002-A2 Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S receive data input /

GPIO Preliminary No difference:

90 nominal differential impedance. Pull-up/down & series resistors provided internally. No difference:

90 nominal differential impedance. Pull-up/down & series resistors provided internally. New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as receive data input of the second digital audio interface, and can be alternatively configured as GPIO Appendix Page 150 of 159 LISA-U1 LISA-U2 LISA-U series - System Integration Manual No Name Description 40 RSVD MIC_P 41 RSVD I2S_WA 42 RSVD I2S_TXD 43 RSVD I2S_CLK 44 RSVD I2S_RXD 45 SCL 46 SDA LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio input (pos.) LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S word alignment LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S transmit data output LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S clock LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

I2S receive data input I2C bus clock line output I2C bus data line input/output RSVD I2S_WA RSVD I2S_TXD RSVD I2S_CLK RSVD I2S_RXD SCL SDA Name GPIO7 I2S1_TXD /

GPIO7 Description Remarks for Migration LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S transmit data output /

GPIO New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as transmit data output of the second digital audio interface, and can be alternatively configured as GPIO LISA-U200-00:

RESERVED pin No difference:

Pad disabled on LISA-U200-00. LISA-U200-01, LISA-U230-01:

1st I2S word alignment input/output No difference:

I2S word alignment input/output LISA-U200-00:

RESERVED pin No difference:

Pad disabled on LISA-U200-00. LISA-U200-01, LISA-U230-01:

1st I2S transmit data output LISA-U200-00:

RESERVED pin LISA-U200-01, LISA-U230-01:

1st I2S clock input/output LISA-U200-00:

RESERVED pin LISA-U200-01, LISA-U230-01:

1st I2S receive data input I2C bus clock line output I2C bus data line input/output No difference:

I2S transmit data output No difference:

Pad disabled on LISA-U200-00. No difference:

I2S clock input/output No difference:

Pad disabled on LISA-U200-00. No difference:

I2S receive data input No difference:

Fixed open drain. External pull-up resistor (e.g. to V_INT) required No difference:

Fixed open drain. External pull-up resistor (e.g. to V_INT) required No difference:

3.25 MHz clock frequency for SIM card No difference:

Internal 4.7 k pull-up resistor to VSIM. No difference:

Reset output for SIM card No difference:

VSIM output = 1.80 V typ or 2.90 V typ By default, the pin is configured to provide the SIM card presence detection function. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Operating Mode Indication 47 SIM_CLK SIM clock output SIM_CLK SIM clock output 48 SIM_IO SIM data input/output SIM_IO SIM data input/output 49 SIM_RST SIM reset output SIM_RST SIM reset output 50 VSIM SIM supply output VSIM SIM supply output 51 GPIO5 GPIO GPIO5 GPIO 3G.G2-HW-10002-A2 Preliminary Appendix Page 151 of 159 LISA-U1 LISA-U2 LISA-U series - System Integration Manual Description Remarks for Migration No Name Description 52 RSVD RESERVED pin Name RSVD CODEC_CLK 53 RSVD SPK_P 54 RSVD SPK_N LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio output (pos.) LISA-U100-0x, LISA-U110-0x:

RESERVED pin LISA-U120-0x, LISA-U130-0x:

Differential analog audio output (neg.) 55 SPI_SCLK SPI Serial Clock Input GPIO8 I2S1_CLK /

GPIO8 GPIO9 I2S1_WA /

GPIO9 SPI_SCLK /

GPIO10 LISA-U200-00:

RESERVED pin LISA-U200-01, LISA-U230-01:

Clock output LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S clock input/output /

GPIO LISA-U200-00:

GPIO LISA-U200-01, LISA-U230-01:

2nd I2S word alignment input/output /

GPIO SPI Serial Clock Input /

GPIO 56 SPI_MOSI SPI Data Line Input SPI_MOSI /

GPIO11 SPI Data Line Input /

GPIO 57 SPI_MISO SPI Data Line Output SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO 58 SPI_SRDY SPI Slave Ready Output SPI_SRDY /

GPIO13 59 SPI_MRDY SPI Master Ready Input SPI_MRDY /

GPIO14 SPI Slave Ready Output /

GPIO SPI Master Ready Input /

GPIO 60 GND 61 VCC Ground Module supply input GND VCC Ground Module supply input 62 VCC Module supply input VCC Module supply input No difference:

Pad disabled on LISA-U200-00. New feature provided by LISA-U2:

Digital clock output for external audio codec New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as clock input/output of the second digital audio interface, and can be alternatively configured as GPIO New feature provided by LISA-U2:

By default, the pin is configured as Pad disabled, and can be alternatively configured as GPIO Different features provided by LISA-U2:

By default, the pin is configured as word alignment input/output of the second digital audio interface, and can be alternatively configured as GPIO SPI / IPC Clock Input (CPOL=0, internal pull-down) by default on LISA-U1 and LISA-U2 Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured as GPIO SPI / IPC Data Line Input, (CPHA=1, internal pull-up) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured as GPIO SPI / IPC Data Line Output (CPHA=1, idle high) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured as GPIO SPI / IPC Slave Ready Output (idle low) by default on LISA-U1 and LISA-U2 Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Status Indication or as GPIO SPI / IPC Master Ready Input (Internal pull-down, Idle low) by default on LISA-U1 and LISA-U2. Additional features provided by LISA-U2xx-01:

The pin can be alternatively configured to provide Module Operating Mode Indication or as GPIO VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max 3G.G2-HW-10002-A2 Preliminary Appendix Page 152 of 159 LISA-U series - System Integration Manual LISA-U1 LISA-U2 No Name Description Name Description Remarks for Migration 63 VCC Module supply input VCC Module supply input 64 GND 65 GND 66 GND 67 GND 68 ANT Ground Ground Ground Ground RF antenna GND GND GND GND ANT Ground Ground Ground Ground RF input/output for main Tx/Rx antenna VCC operating voltage difference:

LISA-U1:

o VCC normal range = 3.4 V min / 4.2 V max o VCC extended range = 3.1 V min / 4.2 V max LISA-U2:

o VCC normal range = 3.3 V min / 4.4 V max o VCC extended range = 3.1 V min / 4.5 V max RF antenna input/output 50 nominal impedance 3G band support difference:

LISA-U100/U120:

o Band II (1900), Band V (850) LISA-U110/U130:

o Band I (2100), Band VIII (900) LISA-U200:

o Band I (2100), Band II (1900), Band V (850), Band VI (800) LISA-U230:

o Band I (2100), Band II (1900), Band IV (1700), Band V (850), Band VI (800), Band VIII (900) Ground Ground Ground Ground Ground 69 GND 70 GND 71 GND 72 GND 73 GND Ground Ground Ground Ground Ground 74 RSVD RESERVED pin GND GND GND GND GND RSVD ANT_DIV LISA-U200-0x:

RESERVED pin No difference:

Leave unconnected. LISA-U230-01:

RF input for Rx diversity antenna New feature provided by LISA-U2:

RF antenna input for Rx diversity 50 nominal impedance 75 GND 76 GND Ground Ground GND GND Ground Ground Table 51: Pinout comparison LISA-U1 series vs. LISA-U2 series 3G.G2-HW-10002-A2 Preliminary Appendix Page 153 of 159 LISA-U series - System Integration Manual A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series Additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer, as described in Figure 77 and Figure 78. Figure 77: Signals keep-out area on the top layer of the application board, below LISA-U1 series modules Figure 78: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 3G.G2-HW-10002-A2 Preliminary Appendix Page 154 of 159 33.2 mm11.85 mm22.4 mm5.3 mm5.25 mm1.4 mm1.0 mmPIN 1LISA-U1 bottom side (through module view)Exposed GND on LISA-U1 module bottom layerSignals keep-out area on application board33.2 mm5.25 mm22.4 mm5.3 mm5.25 mm5.3 mm1.3 mm1.4 mm1.0 mmPIN 1LISA-U2 bottom side (through module view)Exposed GND on LISA-U2 module bottom layerSignals keep-out areas on application board LISA-U series - System Integration Manual B Glossary ADC AP AT CBCH CS CSD CTS DC DCD DCE DCS DDC DSP DSR DTE DTM DTR EBU EDGE E-GPRS FDD FEM FOAT FTP FTPS GND GPIO GPRS GPS GSM HF HSDPA HTTP HTTPS HW I/Q I2C I2S IP IPC Analog to Digital Converter Application Processor AT Command Interpreter Software Subsystem, or attention Cell Broadcast Channel Coding Scheme Circuit Switched Data Clear To Send Direct Current Data Carrier Detect Data Communication Equipment Digital Cellular System Display Data Channel Digital Signal Processing Data Set Ready Data Terminal Equipment Dual Transfer Mode Data Terminal Ready External Bus Interface Unit Enhanced Data rates for GSM Evolution Enhanced GPRS Frequency Division Duplex Front End Module Firmware Over AT commands File Transfer Protocol FTP Secure Ground General Purpose Input Output General Packet Radio Service Global Positioning System Global System for Mobile Communication Hands-free High Speed Downlink Packet Access HyperText Transfer Protocol Hypertext Transfer Protocol over Secure Socket Layer Hardware In phase and Quadrature Inter-Integrated Circuit Inter IC Sound Internet Protocol Inter Processor Communication 3G.G2-HW-10002-A2 Preliminary Appendix Page 155 of 159 LISA-U series - System Integration Manual LNA MCS NOM PA PBCCH PCM PCS PFM PMU RF RI RTC RTS RXD SAW SIM SMS SMTP SPI SRAM TCP TDMA TXD UART UDP UMTS USB UTRA VC-TCXO WCDMA Low Noise Amplifier Modulation Coding Scheme Network Operating Mode Power Amplifier Packet Broadcast Control Channel Pulse Code Modulation Personal Communications Service Pulse Frequency Modulation Power Management Unit Radio Frequency Ring Indicator Real Time Clock Request To Send RX Data Surface Acoustic Wave Subscriber Identification Module Short Message Service Simple Mail Transfer Protocol Serial Peripheral Interface Static RAM Transmission Control Protocol Time Division Multiple Access TX Data Universal Asynchronous Receiver-Transmitter User Datagram Protocol Universal Mobile Telecommunications System Universal Serial Bus UMTS Terrestrial Radio Access Voltage Controlled - Temperature Compensated Crystal Oscillator Wideband CODE Division Multiple Access 3G.G2-HW-10002-A2 Preliminary Appendix Page 156 of 159 LISA-U series - System Integration Manual Related documents u-blox LISA-U1 series Data Sheet, Docu No 3G.G1-HW-10001 u-blox LISA-U2 series Data Sheet, Docu No 3G.G1-HW-11004 u-blox AT Commands Manual, Docu No WLS-SW-11000 ITU-T Recommendation V.24, 02-2000. List of definitions for interchange circuits between data terminal equipment (DTE) and data circuit-terminating equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en 3GPP TS 27.007 - AT command set for User Equipment (UE) (Release 1999) 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) (Release 1999) 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol (Release 1999) Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/

I2C-Bus Specification Version 2.1 Philips Semiconductors (January 2000), http://www.nxp.com/acrobat_download/literature/9398/39340011_21.pdf CENELEC EN 61000-4-2 (2001): "Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test". ETSI EN 301 489-1 V1.8.1: Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements ETSI EN 301 489-7 V1.3.1 Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS) ETSI EN 301 489-24 V1.4.1 "Electromagnetic compatibility and Radio spectrum Matters (ERM);

ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 24: Specific conditions for IMT-2000 CDMA Direct Spread (UTRA) for Mobile and portable (UE) radio and ancillary equipment"

3GPP TS 26.267 - Technical Specification Group Services and System Aspects; eCall Data Transfer; In-

band modem solution; General description (Release 9) GSM Mux Implementation Application Note, Docu No WLS-CS-11002 GPS Implementation Application Note, Docu No GSM.G1-CS-09007 Firmware Update Application Note, Docu No WLS-CS-11001 SPI Interface application Note, Docu No 3G.G2-CS-11000 3GPP TS 23.060 - Technical Specification Group Services and System Aspects; General Packet Radio Service (GPRS); Service description End user test Application Note, Docu No TBD u-blox Package Information Guide, Docu. No GPS-X-11004

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Some of the above documents can be downloaded from u-blox web-site (http://www.u-blox.com). 3G.G2-HW-10002-A2 Preliminary Related documents Page 157 of 159 LISA-U series - System Integration Manual Revision history Revision Date Name Status / Comments

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1 2 3 A 21/10/2010 sses 11/01/2011 sses 26/04/2011 lpah 07/07/2011 lpah 26/10/2011 sses Initial Release Thickness information added GPIO description improved Update to Advance Information status Update to Preliminary status Changed status to Objective Specification Initial release for LISA-U series From LISA-U1xx-00 system integration manual, added description and integration of LISA-U1xx-01, LISA-U200-00, LISA-U2xx-01 Added notes regarding VCC normal and extended operating ranges Added RTC value reliability as function of V_BCKP voltage value Added recommendation regarding any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence: must be tri-stated to avoid latch-up of circuits and let a proper boot of the module. A1 22/11/2011 sses Update to Advance Information status Updated module behavior during power-off sequence. Added LISA-U200-00 ESD application circuit for antenna port. Added application circuit for the module status indication function. A2 02/02/2012 sses Update to Preliminary status Updated Federal Communications Commission notice Updated LISA-U2 features in module power off and GPIO sections 3G.G2-HW-10002-A2 Preliminary Revision history Page 158 of 159 Contact For complete contact information visit us at www.u-blox.com u-blox Offices North, Central and South America u-blox America, Inc. Phone:

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+1 (703) 483 3180 info_us@u-blox.com Regional Office West Coast:

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Installation Guide 3M Electronic Monitoring 3M Domestic Violence GPS Proximity Notification System Installation & Operation June 2017 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Information in this documentation is subject to change without notice and does not represent a commitment on part of 3M Electronic Monitoring. The software described in this document is subject to the license agreement that is included with the product, which specifies the permitted and prohibited uses of the product. Any unauthorized duplication or use of this documentation, in whole or in part, in print, or in any other storage or retrieval system is prohibited. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means for any purpose other than the purchasers personal use without the permission of 3M Electronic Monitoring. 1995-2017 3M Electronic Monitoring. All rights reserved. Unless otherwise noted, all names of companies, products, street addresses, and persons contained herein are part of a completely fictitious scenario and are designed solely to document the use of a 3M Electronic Monitoring product. Contact Us Corporate Headquarters 3M Electronic Monitoring 2 Ha-Barzel St., P.O. Box 13236, 61132 Tel Aviv, Israel Tel: 972-3-7671800 Fax: 972-3-7671801 U.S.A Customers, call 1-800-313-1483 Visit us at: www.3m.com/electronicmonitoring 2 3M Electronic Monitoring Versions and Changes Table Version Status/Changes Author Date 1.0 New format initial release version Steve Graniewitz 24-AUG-2017 3 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Safety Information Please read, understand, and follow all safety information contained in these instructions prior to the use of this 3M Electronic Monitoring device. Retain these instructions for future reference. Intended Use This 3M Electronic Monitoring device is part of an electronic monitoring system, which performs data transfer using the PSTN or cellular network to a monitoring platform. This device has not been tested for and is not intended for use on airplanes, in hazardous environments, in healthcare facilities, or where cellular phones or other intentional transmitters are restricted. The operating temperature of the Two-Piece GPS Offender Tracking Unit is -20C to +55C. The operating temperature of the RF Transmitter (TRXS-840) is -25C to +55C. The storage temperature of the Two-Piece GPS Offender Tracking Unit is -40C to +55C. The storage temperature of the RF Transmitter (TRXS-840) is -40C to

+55C. The GPS Base Unit is intended for indoor use only. The operating temperature of the GPS Base Unit is -20C to

+55C. The storage temperature of the GPS Base Unit is -40C to +55C. The maximum temperature at which the GPS Base Units battery may be charged is +50C. Explanation of Signal Word Consequences WARNING Indicates a hazardous situation which, if not avoided, could result in serious injury or death. CAUTION Indicates a hazardous situation which, if not avoided, could result in minor or moderate injury and/or property damage. NOTICE:

Indicates a situation which, if not avoided, could result in property damage. Safety information for:

Rechargeable hand-held/wearable devices Non-rechargeable hand-held/wearable devices Cradles/receivers/base units WARNING Avoid placing a device next to an implanted electronic device (e.g., dont carry the device in a shirt or jacket pocket directly near an implanted device). To reduce the risks associated with fire or explosion:

Do not intentionally open or damage the device. Ensure storage temperature of device is within the range as specified in device manual. Do not attempt to access or replace battery. Battery is not user-replaceable. The device shall be opened by 3M authorized service only. Do not use device outside of the operation temperature range specified in device manual. Contact the agency representative from which you are monitored to get operation temperature range. 4 3M Electronic Monitoring WARNING To reduce the risks associated with hazardous voltage:

Do not modify, decorate, or attempt to service the device. Return to 3M authorized personnel or location for repair or service. There are no user serviceable parts. If the device or power cord becomes damaged, contact the agency representative from which you are monitored. NOTICE Only authorized personnel can turn off or remove the device. Safety information for:

Rechargeable hand-held/wearable devices Cradles/receivers/base units WARNING To reduce the risks associated with hazardous voltage:

Do not modify AC/DC power adapter plug. Do not force the power plug into an outlet where it does not fit. Use only a 3M provided AC/DC power adapter to recharge or power the device. Do not unplug AC/DC adapter by power cord. Handle the adapter by the body only. Do not attempt to charge the device using an outdoor outlet. Only use the AC/DC adapter indoors. Do not expose power adapter to rain, steam or wet conditions. Do not submerge the device, or hold the device under running water, while it is charging. CAUTION To reduce the risks associated with hot surfaces:

Do not touch thermal pads on device or charger if charging is interrupted. 5 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Safety information only for:

Rechargeable Hand-held/wearable Devices Non Rechargeable Hand-held/wearable Devices WARNING To reduce the risks associated with fire or explosion:

Do not enter areas with potentially explosive atmosphere. Potentially explosive areas are often, but not always, clearly marked. CAUTION Avoid installing the electronic monitoring device in the presence of ulcers, open wounds, blisters, swelling or skin infection over the expected area of contact with the electronic monitoring device. If the user reports pain, numbness or other symptom over the expected area of contact with the electronic monitoring device, a medical opinion is recommended prior to installation. If the user reports concerns about an underlying medical condition that could be exacerbated by use of the electronic monitoring device, a medical opinion is recommended prior to installation of device. If, during use, the user experiences skin changes or symptoms in the area in contact with the electronic monitoring device, the user should immediately contact their agency representative. Cancer Patients that have been treated with Radiotherapy:

Avoid installing the electronic monitoring device in the presence of radiation-induced skin changes (such as ulcers, open wounds, blisters, desquamation, erythema, hyperpigmentation) over the expected area of contact with the electronic monitoring device. Otherwise, there is no currently available evidence the use of the electronic monitoring device is contraindicated in cancer patients that have been treated with Radiotherapy. Pregnant women:

Avoid installing the electronic monitoring device in the presence of ulcers, open wounds, blisters, swelling or skin infection over the expected area of contact with the electronic monitoring device. Otherwise, there is no currently available evidence the use of the electronic monitoring device is contraindicated in pregnant women. Safety information only for:

Cradles/receivers/base Units WARNING To reduce the risks associated with hazardous voltage:

Do not submerge the device, or hold the device under running water. 6 3M Electronic Monitoring FCC Two-Piece GPS Tracking Unit and GPS Victim Unit contain FCC ID: XPYLISAU200 Base Unit FCC ID: LSQ-SBU2000433-2 FEDERAL COMMUNICATIONS COMMISSION (FCC) Part 15 STATEMENT The equipment complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. This device complies with FCC/ISED radiation exposure limits set forth for an uncontrolled environment and meets the FCC radio frequency (RF) Exposure Guidelines and RSS102 of the ISED radio frequency (RF) Exposure rules. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

1. Reorient or relocate the receiving antenna, 2. Increase the separation between the equipment and the receiver, 3. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected, 4. Consult the dealer or an experienced radio/TV technician for help. 3M Electronic Monitoring has not approved any changes or modifications to this device by the user. Any changes or modifications could void the users authority to operate the equipment. WEEE This symbol according to the European Directive indicates that the Waste of Electrical and Electronic Equipment (WEEE) must not be disposed of as unsorted municipal waste and must be collected separately. Please contact an authorized representative of the manufacturer or an authorized waste management company for information concerning the decommissioning of your equipment. 7 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Table of Contents 1 Introduction .......................................................................................................................................... 9 1.1 1.2 Two-Piece GPS Tracking Unit ..................................................................................................... 9 RF Transmitter ................................................................................................................................ 9 1.3 GPS Base Unit ................................................................................................................................10 1.4 GPS Victim Unit .............................................................................................................................. 11 2 Before Installation ............................................................................................................................... 12 2.1.1 Installation Equipment ....................................................................................................... 12 2.1.2 Installation Tools ................................................................................................................ 12 2.1.3 Verifying Information in the Web Offender Management Software ......................... 12 3 Installing the Aggressors RF Transmitter ........................................................................................ 13 3.1 Activating the RF Transmitter ..................................................................................................... 13 3.2 Attaching the RF Transmitter ...................................................................................................... 13 4 5 6 Activating the Tracking Unit .............................................................................................................. 15 Configuring the Tracking Unit ........................................................................................................... 18 Installing the GPS Base Unit .............................................................................................................. 19 6.1 Placing the Receiver ..................................................................................................................... 19 6.2 Setting Up the GPS Base Unit .................................................................................................... 20 7 Operating the Tracking Unit ............................................................................................................. 22 7.1 Waking the Tracking Unit from Idle Mode .............................................................................. 22 7.2 Acknowledging Messages .......................................................................................................... 22 7.3 Viewing Message History ........................................................................................................... 22 7.4 Charging the Tracking Unit ........................................................................................................ 23 7.5 Phone Calls .................................................................................................................................... 23 7.5.1 Outgoing Calls ................................................................................................................... 23 7.5.2 Incoming Calls .................................................................................................................. 23 7.5.3 Ending a Call .................................................................................................................... 23 7.5.4 Changing the Speaker Volume During a Call ............................................................. 23 7.6 Specific Instructions for the Victim ........................................................................................... 24 7.6.1 Panic Alerts ....................................................................................................................... 24 7.7 General Rules for the Aggressor ............................................................................................... 24 8 Dismantling the Equipment ............................................................................................................... 25 8.1 Before Dismantling ....................................................................................................................... 25 8.2 Performing End of Service .......................................................................................................... 25 8.3 Removing the RF Transmitter .................................................................................................... 26 8.4 Deactivating the RF Transmitter ................................................................................................ 26 8 3M Electronic Monitoring 1 Introduction 3M Electronic Monitorings pioneering domestic violence deterrence solution is designed to offer law enforcement agencies the means to impose restraining orders more efficiently. The solution combines GPS tracking with cellular and RF communication in order to track the aggressor and alert the victim and monitoring center in the event of emergency. The system monitors the location of both the aggressor and victim and uses both fixed and dynamic geographic restriction zones to raise an alert when there is a likelihood of the aggressor and victim meeting either intentionally or unintentionally. Any entry of the aggressor into these zones automatically generates an alert that is sent simultaneously to the victim and the designated authorities. 1.1 Two-Piece GPS Tracking Unit The Two-Piece GPS Tracking Unit is carried by the aggressor and continuously gathers location data. The aggressor is required to carry the GPS tracking unit whenever they leave their place of residence. Upon leaving, the unit automatically acquires a GPS location fix and begins monitoring. The unit is compact, lightweight, highly reliable and includes multiple communication modules (a cellular modem, a GPS receiver and an RF module). The GPS tracking units internal cellular modem is used to transfer location data, status and events to the monitoring center either immediately or periodically, according to a pre-defined communication interval. Figure 1: Two-Piece GPS Tracking Unit 1.2 RF Transmitter In addition to the GPS tracking unit, the aggressor is assigned an RF Transmitter which is securely fastened to the aggressors wrist or ankle by means of a tamper-detecting strap so that the aggressor can be identified unequivocally. The RF Transmitter repeatedly emits radio-frequency (RF) signals which are detected by the aggressors GPS tracking unit. These signals are used to verify that the GPS tracking unit is indeed being carried by, or sitting in close the aggressor at all times. As soon as the tracking unit detects a loss or significant weakening of the transmitters signal, indicating that the aggressor has abandoned the tracking unit, the unit generates an event and notifies the monitoring center. 9 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Figure 2: RF Transmitter 1.3 GPS Base Unit The GPS Base Unit is an additional device that can be allocated to the aggressor in domestic violence deterrence programs. The GPS Base Unit is installed at the aggressors curfew location. On returning to the curfew location, the aggressor places the Two-Piece unit in the GPS Base Units docking cradle. Placing the Two-Piece unit in the docking cradle is a condition of the home curfew. Failure to dock the Two-Piece unit during the home curfew time frame will generate a violation. While the Two-Piece unit is docked, the Two-Piece unit stops sampling location data and recharges its battery. Additionally, the GPS Base Unit takes over the task of monitoring the signals sent by the RF Transmitter. This significantly extends the RF range so that the aggressor may move freely within the perimeter of the curfew location. Figure 3: GPS Base Unit 10 1.4 GPS Victim Unit The GPS Victim Unit constantly tracks movement and location of the victim using GPS technology. Each time the GPS victim unit communicates with the monitoring system, it receives the aggressors last known location. Using this data, the unit calculates the proximity of the aggressor and alerts the victim if the aggressor is within a defined range. 3M Electronic Monitoring Figure 4: GPS Victim Unit The GPS Victim Unit provides audible, visual, and/or vibration alerts to the victim for each layer of aggressor proximity detection; when the aggressor is in close GPS proximity, immediate GPS proximity, or when the aggressors transmitter is within RF reception range. At the same time, the GPS Victim Unit generates an event that is immediately reported over the cellular network to alert the monitoring center. The GPS Victim Unit can also function as a mobile phone enabling bi-directional communication between the victim and the monitoring center, emergency personnel or other defined contacts. When in distress, the victim can call any of these contacts, or can use the Panic option to initiate an outgoing call to the predefined emergency number. When the victim initiates a Panic alert, the GPS Victim Unit also generates a Panic event that is immediately reported to the monitoring center. 11 Installation Guide: 3M Domestic Violence GPS Proximity Notification System 2 Before Installation Before leaving the monitoring center, check that you have the correct installation kit and the appropriate installation tools. In addition, verify that the offender is correctly registered in the 3M Web Offender Management Software application. 2.1.1 Installation Equipment The kit of installation equipment should include the following items:

Aggressor equipment installation kit:

Two-Piece GPS Tracking Unit Carrying pouch Power adapter RF Transmitter with strap holder Locking clips If installing with the GPS Base Unit, make sure that you bring the following items:

GPS Base Unit Power adapter Telephone cables (optional) Victim equipment installation kit:

GPS Victim Unit Power adapter 2.1.2 Installation Tools You will also need the following installation tools:

Manual Reset Device (MRD) for activating the RF Transmitter Strap locking tool for locking the RF Transmitter 0.2 (5mm) flat head screwdriver for opening the locking clip Snake eye screwdriver for changing the straps on the RF Transmitter 2.1.3 Verifying Information in the Web Offender Management Software Verify the following details in the 3M Web OMS:

The ID, name and address of the aggressor and the victim Aggressors program type Program Type: 2 Piece GPS, Subtype: DV Aggressor Victims program type Program Type: 2 Piece GPS, Subtype: DV Victim Equipment serial numbers these must match the serial numbers on the equipment you are planning to install SIM card details for aggressor and victim GPS tracking units 12 3M Electronic Monitoring 3 Installing the Aggressors RF Transmitter Check that you have the following equipment items before you install the RF Transmitter:

RF Transmitter (TX) and strap holder Electronic key (MRD) Locking tool Locking clips (male and female) 0.2 (5mm) flat head screwdriver for opening the locking clip Snake eye screwdriver for changing the straps of the RF Transmitter 3.1 Activating the RF Transmitter Before the RF Transmitter can be attached to the offender, you must first activate the RF Transmitter. To activate the RF Transmitter:

1. Hold the free end of the RF Transmitter strap in your hand with the metal pins pointing towards you. 2. Hold the MRD in your other hand, with the two connection points facing the metal pins. 3. Press the metal pins on the RF Transmitter onto the two connection points on the MRD and hold them in this position. 4. On the MRD, press the ON button. The red LED on the MRD turns on for 2 seconds and then flashes for another 2 seconds. The flashing indicates that the RF Transmitter has passed the first phase of its activation. If the RF Transmitter failed to receive the activation command, the red LED on the MRD turns off after initially being on for two seconds. If the MRDs battery is low, the red LED flashes for two seconds immediately after the ON button is pressed. 5. Place the RF Transmitter on its side on a non-metal surface and leave it untouched for 60 seconds to allow it to calibrate. The RF Transmitter is now activated. 3.2 Attaching the RF Transmitter To attach the RF Transmitter:

1. Place the strap holder over the short strap of the RF Transmitter (A). 2. Attach the female part of the clip to the underside of the short strap ensuring that the closed end of the clip fits snugly onto the end of the strap (B). 3. Wrap the RF Transmitter around the wrist or ankle at its narrowest point. 13 A B Installation Guide: 3M Domestic Violence GPS Proximity Notification System 4. Lay the long strap over the female part of the clip ensuring that the strap pins and the clip studs are protruding through the holes in the long strap (C). C 5. Slide the strap holder over the end of the long strap in order to hold the strap in place. 6. Move the RF Transmitter around the wrist or ankle to ensure that it fits comfortably. D 7. Place the male part of the clip over the female part, ensuring that the grooves on each side of the clips match (D). 8. Place one side of the locking tool underneath the clip and close the two parts together. You should hear a clicking sound indicating that the clip is properly locked. Be sure to collect all of the installation equipment at the aggressors curfew site. This includes any locking clips that may have broken during the installation. 14 3M Electronic Monitoring 4 Activating the Tracking Unit The activation procedure for the Two-Piece GPS Tracking Unit and the GPS Victim Unit are almost identical. Both types of tracking unit include an LCD and a five-button keypad are used to navigate the devices menu-driven interface. To navigate the Two-Piece units menus:

Use and to scroll through menu options. Use to select the highlighted option. Use to navigate back to the previous menu. To activate the tracking unit:

1. Connect the tracking unit to its power adapter. 2. Wait for the unit to turn on and prompt you to activate. In some cases, it may take up to 90 seconds for the tracking unit to turn on. 3. Unplug the power adapter from the tracking unit. 4. Call the monitoring center to download the program configuration to the tracking unit. 5. Press . A list of dialing methods is displayed on the tracking units screen. 15 Installation Guide: 3M Domestic Violence GPS Proximity Notification System 6. Press to scroll to Using Wireless and press . The activation sequence begins. During the activation sequence, do not press any buttons on the Two-Piece unit. If you do press a button, the activation sequence will be canceled. The activation sequence is as follows:

a. The Two-Piece unit calls the monitoring system to download the offenders program details and the screen displays the message Contacting Datacenter. b. Aggressor Unit Only: The Two-Piece unit waits to receive a signal from the offenders RF Transmitter. The RF transmitter must be activated successfully and in range of the Two-Piece unit. If the Two-Piece unit does not receive a valid signal from its RF transmitter, the activation sequence will be aborted. c. The Two-Piece unit waits to acquire its initial GPS location. 16 3M Electronic Monitoring 7. When Waiting for GPS is displayed, take the tracking unit outside to a location with a clear view of the sky. 8. Hold the tracking unit upright and wait for the unit to acquire its location. The green bar fills to the right to indicate progress. When the GPS location is acquired, the tracking unit sounds a beep and displays the Activation Successful message with the current date and time. 9. Press to acknowledge. The tracking unit displays the name of the offender together with the date and time indicating that the unit was activated successfully. 17 Installation Guide: 3M Domestic Violence GPS Proximity Notification System 5 Configuring the Tracking Unit Local configuration of the tracker unit is performed via the tracking units Officer menu. To access the Officer menu:

Rapidly press the following button sequence:

The Officer menu is displayed. The options available in the Officer menu are listed in the following table. Menu Option Description Vibrate/Beep Offers a choice of alert indication modes. ID Numbers Displays the serial numbers of the Two-Piece unit, the RF Transmitter and the GPS Base unit. Alarm Set Allows the officer to set a timed alarm to be sounded by the Two-Piece unit. Beep Volume Enables configuration of alert tone volume. Time Format Enables configuration of how the Two-Piece unit displays the time. Firmware Ver. Displays the firmware version of the Two-Piece unit. Bracelet Test Displays the RF Transmitters serial number, strap status, battery status and the time elapsed since the last received transmission. Set Brac. S/N Allows the officer to temporarily assign an RF Transmitter to the Two-Piece unit. Deactivate Enables the officer to manually deactivate the Two-Piece unit. Modem Info Displays cellular signal strength and enables the officer to manually initiate a cellular call to the monitoring system. Satellite Bar A detailed display of the Two-Piece units signal reception from GPS satellites. 18 3M Electronic Monitoring 6 Installing the GPS Base Unit The GPS Base Unit is an optional device that is used together with the aggressors Two-Piece GPS Tracking Unit and serves the following purposes:

Home Curfew An inclusion zone around the aggressors home is defined in the system as a Home Curfew zone. A Must Be In schedule is defined for the offender during which the offender is required to be at home. The aggressor must place the Two-Piece unit in the GPS Base Units docking cradle during the Home Curfew schedule. If the Two-Piece unit is not docked in the GPS Base Unit at the correct time, a curfew violation event is generated. Charging While docked in the GPS Base Unit, the Two-Piece unit is charged. RF Range Extension The GPS Base Unit extends the RF range when the Two-Piece unit is docked so as to allow the aggressor to move freely around their curfew zone. Land Line Communication If the GPS Base Unit is connected to the land line telephone socket, the land line connection is used as the method of communication when the Two-Piece unit is undocked. Figure 5: Two-Piece Unit docked in GPS Base Unit 6.1 Placing the Receiver The ideal location for the GPS Base Unit is:

In an open area As close as possible to the center of the curfew site On a flat and secure surface 1m (3 feet) above the ground and at least 30cm (1 foot) away from the wall Make sure the GPS Base Unit is located far away from:

Television sets or other electrical appliances Microwave ovens Personal computers or laptops Disruptive noise sources such as heavy traffic or mechanical vibrations Heat sources such as a radiator, air ducts or direct sunlight Excessive moisture or extremely low temperatures Mirrors or reflective materials 19 Installation Guide: 3M Domestic Violence GPS Proximity Notification System Figure 6: Positioning the GPS Base Unit 6.2 Setting Up the GPS Base Unit The GPS Base Unit should be positioned horizontally on a hard, flat surface within easy reach of a power outlet and a telephone socket (if required). To set up the GPS Base Unit:

1. If you are connecting the GPS Base Unit to a land line, perform the following two steps:

a. If there is a telephone already connected to the telephone wall socket, disconnect the telephone cable connect it to the Phone socket located on the back panel of the GPS Base Unit. b. Connect one end of the supplied telephone cable into the Line socket located on the back panel of the GPS Base Unit and plug the other end into the telephone wall socket. Figure 7: GPS Base Unit Connections 20 3M Electronic Monitoring 2. Connect the power adapter to the nearest available power outlet. 3. Plug the other end of the supplied power adapter cord into the socket labelled 12VDC on the back panel of the GPS Base Unit. The GPS Base Unit includes an internal, rechargeable backup battery to provide power in the event of a power outage. The battery is charged automatically and is not controlled by the user. 4. Place the active Two-Piece inside the docking cradle on the GPS Base Units top cover with the LCD facing forwards see Figure 5: Two-Piece Unit docked in GPS Base Unit. The Two-Piece automatically calls the monitoring system to activate the GPS Base Unit. The GPS Base Unit communicates through the Two-Piece units cellular modem when the Two-

Piece unit is docked. If the Two-Piece unit is undocked, the GPS Base Unit will communicate via the land line connection if available. If the GPS Base unit is not connected to the land line, all GPS Base Unit events (e.g. power status, case tamper and tilt) will be reported to the monitoring system via the Two-Piece units cellular modem and only when the Two-Piece unit is docked. 21 Installation Guide: 3M Domestic Violence GPS Proximity Notification System 7 Operating the Tracking Unit Inform the aggressor and victim regarding the following procedures and ensure that the offender understands how to operate the Two-Piece unit correctly. 7.1 Waking the Tracking Unit from Idle Mode If the tracking unit is inactive for 10 seconds, the unit enters Idle mode. To wake the tracking unit from Idle mode:

Press any button. The Two-Piece unit wakes from Idle mode. 7.2 Acknowledging Messages When certain violations occur, the tracking unit displays a message. Additionally, messages can be manually sent by monitoring center staff to the aggressor or victim via the tracking unit. These messages appear on the tracking units LCD along with notification of the message according to the Vibrate/Beep configuration defined via the Officer menu. When the aggressor or victim receives a message, they are required to acknowledge that they received message. To acknowledge a message:

Press . The notification stops and the message is cleared from the LCD. If the message is indication of a hardware issue, notification is repeated until the issue is resolved and the message is acknowledged. Tracking unit hardware issues include the following events:

Tracker Battery Low Motion No GPS Tracker Case Open 7.3 Viewing Message History The Two-Piece unit stores a list of messages received previously. To view the Two-Piece units message list:

1. Press to open the menu. 2. Scroll to Messages and press . The list of stored messages is displayed in order of date and time. 3. Scroll through the messages and press to view message details. 22 3M Electronic Monitoring To exit the message list Press until you have returned to the main display. 7.4 Charging the Tracking Unit The tracking unit should be charged for at least two hours a day using the power adapter supplied. If the aggressor is using a GPS Base Unit, the Two-Piece unit can be charged by placing it in the docking cradle. 7.5 Phone Calls The tracking unit can operate like a cellular phone allowing the user to make and receive phone calls. 7.5.1 Outgoing Calls The tracking unit enables the aggressor and victim to make calls to pre-defined phone numbers. To make a call:

1. Press to open the menu. 2. Scroll to Call List and press . The list of pre-defined phone numbers is displayed. 3. Scroll to the required number and press . 7.5.2 Incoming Calls The Two-Piece unit can receive incoming calls. When there is an incoming call, the Two-Piece unit rings and a message is displayed. To answer an incoming call:

Press . The call duration is displayed. 7.5.3 Ending a Call To end a call 1. Press to open the menu. 2. Scroll to Hang Up and press . The Two-Piece unit hangs up the call. 7.5.4 Changing the Speaker Volume During a Call While a call is in progress, it is possible to raise or lower the speaker volume. To adjust the speaker volume during a call:

1. Press to open the menu. 2. Scroll to Speaker Volume and press . 23 Installation Guide: 3M Domestic Violence GPS Proximity Notification System The following screen is displayed. 3. Use to increase the speaker volume or to decrease the speaker volume. 7.6 Specific Instructions for the Victim 7.6.1 Panic Alerts If the victim is being attacked, it is possible to send a Panic alert to the monitoring center. To send a Panic alert:

Hold down and simultaneously for three seconds. While holding down the buttons, the tracking units screen counts down three seconds. If you release the buttons before three seconds, the Panic Alert is aborted. After holding the buttons for three seconds, if technical difficulties prevent the Panic alert from being sent to the monitoring center, the tracking unit automatically calls the first phone number in the predefined phone number list. 7.7 General Rules for the Aggressor The following are general rules for the aggressor regarding their monitoring program:

Always keep the tracking unit with you. Whenever the tracking unit vibrates, beeps, or sounds tones, you must read the message displayed in the display screen. Whenever you receive a message and are instructed to perform a task, you must comply. Whenever you receive a message, you must acknowledge the message. Never attempt to open the tracking unit. Never attempt to open the RF Transmitter strap clip. Never attempt to cut or break the RF Transmitter strap. Never leave the designated curfew site during the curfew time frame. Never attempt to tamper with the Two-Piece unit. Tamper attempts will be reported to the monitoring center and will be considered a violation of your program. 24 3M Electronic Monitoring 8 Dismantling the Equipment Dismantling the equipment involves the following:

Performing End of Service (when applicable). Packing the tracking unit. Removing, deactivating, and packing the aggressors RF Transmitter. If a GPS Base Unit is installed, removing and packing the GPS Base Unit. 8.1 Before Dismantling Before leaving the monitoring center, check that you have the following dismantling tools:

0.2 (5mm) flathead screwdriver for opening the RF Transmitter clip. Manual Reset Device (MRD) for deactivating the RF Transmitter. In addition, make sure to bring all of the original carrying cases for the monitoring equipment. 8.2 Performing End of Service In some cases, it is required to remove the equipment before the full period of the monitoring program is completed. In this case, you must perform a manual End of Service procedure before dismantling and removing the equipment. To perform End of Service for the Two-Piece unit:

1. Call the monitoring center and ask the monitoring personnel to perform End of Service. 2. The monitoring center personnel will call back to confirm a successful End of Service. After receiving the End of Service command from the monitoring system, the Two-Piece unit enters Dismantling mode. The unit stops all activity and waits for 120 seconds after power is disconnected from the unit before turning itself off. 3. Pack the tracking unit and its power adapter into their original carrying case. If a GPS Base unit is installed at the curfew site, perform the following procedure for End of Service instead of the procedure described above. To perform End of Service for the Two-Piece unit and GPS Base Unit:

1. Place the Two-Piece unit in the GPS Base Units docking cradle. 2. Call the monitoring center and ask the monitoring personnel to perform End of Service. If the Two-Piece unit is docked in the GPS Base Unit during the End of Service sequence, End of Service is performed for both the Two-Piece unit and the GPS Base Unit. 3. The monitoring center personnel will call back to confirm a successful End of Service. If End of Service was performed without the Two-Piece unit docked in the GPS Base Unit, the GPS Base Unit will not be deactivated. In this case, disconnect the GPS Base Unit from power. Once the backup battery has fully depleted, the GPS Base Unit will shut down and deactivate. 25 Installation Guide: 3M Domestic Violence GPS Proximity Notification System 4. Pack the Two-Piece unit, the GPS Base Unit and their power adapters into their original carrying cases. 8.3 Removing the RF Transmitter After disconnecting and packing the Two-Piece equipment, remove the RF Transmitter from the offender. To remove the RF Transmitter:

1. Taking care not to damage or cut the strap, insert a screwdriver into the groove between the two parts of the locking clip and gentry pry apart. Figure 8: Prying Apart the Locking Clip of the RF Transmitter 2. Collect all of the fragments of the broken clip. Do not leave any disposable items on site. 8.4 Deactivating the RF Transmitter Before packing the RF Transmitter, it is important to deactivate so as to preserve the units internal battery. To deactivate the RF Transmitter:

1. Hold the RF Transmitter along the strap with the metal pins pointing towards you. Make sure to support the underside of the strap in your hand. 2. Hold the MRD in your other hand, with the OFF button pointing towards the open, free end of the strap and away from the RF Transmitter body. 3. Press the metal pins on the RF Transmitter onto the two connection points on the MRD and hold them in this position. 4. Hold down the OFF button on the MRD for one second. The red LED on the MRD turns on for two seconds. If the RF Transmitter successfully received the deactivate command, the red LED on the MRD flashes for two seconds. If the RF Transmitter failed to receive the deactivate command, the red LED on the MRD turns off after initially being on for two seconds. If the MRDs battery is low, the red LED flashes for two seconds immediately after the OFF button is pressed. 5. Pack the RF Transmitter into its original carrying case. 26

 

 

LISA-U2 series 3.75G HSPA / HSPA+ Cellular Modules System Integration Manual Abstract This document describes the features and the system integration of LISA-U2 series HSPA+ cellular modules. These modules are complete and cost efficient 3.75G solutions offering up to six-band HSDPA/HSUPA and quad-band GSM/EGPRS voice and/or data transmission technology in a compact form factor. www.u-blox.com UBX-13001118 - R25 LISA-U2 series - System Integration Manual Document Information Title Subtitle LISA-U2 series 3.75G HSPA / HSPA+ Cellular Modules Document type System Integration Manual Document number UBX-13001118 Revision and date R25 10-Apr-2019 Disclosure Restriction This document applies to the following products:

Product name Type number Modem version Application version PCN reference Product status LISA-U200 LISA-U200-01S-00 22.40 LISA-U200-01S-01 22.40 LISA-U200-01S-02 22.40 LISA-U200-01S-03 22.40 LISA-U200-02S-01 22.90 LISA-U200-02S-02 22.90 LISA-U200-03S-00 23.41 LISA-U200-03S-01 23.41 LISA-U200-03S-02 23.41 LISA-U200-52S-01 22.86 LISA-U200-52S-02 22.86 LISA-U200-52S-03 22.86 LISA-U200-62S-01 22.90 LISA-U200-62S-02 22.90 LISA-U200-62S-03 22.90 LISA-U200-62S-04 22.90 LISA-U201-03S-01 23.41 LISA-U201-03A-00 23.41 LISA-U201-03A-01 23.41 LISA-U201-03A-02 23.41 LISA-U200 FOTA LISA-U200-83S-00 23.41 LISA-U201 LISA-U201-03S-00 23.41 LISA-U230 LISA-U230-01S-01 22.40 LISA-U260 LISA-U260-01S-02 22.61 LISA-U230-01S-02 22.40 LISA-U230-01S-03 22.40 LISA-U260-01S-03 22.61 LISA-U260-02S-02 22.90 LISA-U260-02S-03 22.90 A01.00 A01.02 A01.03 A01.01 A01.03 A01.01 A01.04 A01.05 A01.01 A01.03 A01.04 A01.01 A01.02 A01.03 A01.04 A01.01 A01.01 A01.04 A01.01 A01.02 A01.04 A01.02 A01.04 A01.02 A01.03 A01.05 A01.02 A01.04 UBX-TN-12040 Obsolete End of Life UBX-17048820 End of Life UBX-18055867 Mass Production UBX-14005768 End of Life UBX-17048820 End of Life UBX-15020745 Obsolete UBX-17048820 End of Life UBX-18055867 Mass Production UBX-14005768 Obsolete UBX-17048820 End of Life UBX-18055867 Mass Production UBX-14005768 Obsolete UBX-16017712 End of Life UBX-17048820 End of Life UBX-18055867 Mass Production UBX-15020745 End of Life UBX-15020745 End of Life UBX-17048820 Mass Production UBX-16010501 End of Life UBX-17010533 End of Life UBX-17046899 Mass Production UBX-TN-12040 Obsolete UBX-17048820 End of Life UBX-18055867 Mass Production UBX-TN-12061 Obsolete UBX-17048820 End of Life UBX-14042086 End of Life UBX-17048820 End of Life LISA-U201 FOTA LISA-U201-83S-00 23.41 UBX-16004570 Obsolete LISA-U201-83S-01 23.41 UBX-17048820 Mass Production UBX-13001118 - R25 Document Information Page 2 of 182 LISA-U2 series - System Integration Manual Product name Type number Modem version Application version PCN reference Product status LISA-U270 LISA-U270-01S-02 22.61 LISA-U270-02S-02 22.90 LISA-U270-02S-03 22.90 LISA-U270-62S-04 22.93 LISA-U270-62S-05 22.93 LISA-U270-62S-06 22.93 LISA-U270-62S-07 22.93 LISA-U270-63S-00 22.93 LISA-U270-63S-01 22.93 LISA-U270-63S-02 22.93 LISA-U270-68S-00 22.93 LISA-U270-68S-01 22.93 A01.02 A01.02 A01.04 A01.02 A01.04 A01.05 A01.07 A01.06 A01.07 A01.08 A01.03 A01.07 UBX-14042086 Obsolete UBX-14042086 End of Life UBX-17048820 End of Life UBX-14042086 Obsolete UBX-15029938 Obsolete UBX-16009934 Obsolete UBX-17048820 End of Life UBX-16010383 Obsolete UBX-17048820 End of Life UBX-18055867 Mass Production UBX-15019240 Obsolete UBX-17048820 End of Life u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this document. Copying, reproduction, modification or disclosure to third parties of this document or any part thereof is only permitted with the express written permission of u-blox. The information contained herein is provided as is and u-blox assumes no liability for its use. No warranty, either express or implied, is given, including but not limited to, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time without notice. For the most recent documents, visit www.u-blox.com. Copyright u-blox AG. UBX-13001118 - R25 Document Information Page 3 of 182 LISA-U2 series - System Integration Manual Contents Document Information ................................................................................................................................ 2 Contents .......................................................................................................................................................... 4 1 System description ............................................................................................................................... 7 1.1 Overview ........................................................................................................................................................ 7 1.2 Architecture ................................................................................................................................................. 9 1.2.1 Functional blocks ................................................................................................................................ 9 1.3 Pin-out .......................................................................................................................................................... 11 1.4 Operating modes ....................................................................................................................................... 15 1.5 Power management .................................................................................................................................. 17 1.5.1 Power supply circuit overview ......................................................................................................... 17 1.5.2 Module supply (VCC) ........................................................................................................................ 18 1.5.3 Current consumption profiles ........................................................................................................ 28 1.5.4 RTC Supply (V_BCKP) ...................................................................................................................... 33 1.5.5 Interface supply (V_INT) .................................................................................................................. 36 1.6 System functions ...................................................................................................................................... 37 1.6.1 Module power-on .............................................................................................................................. 37 1.6.2 Module power-off .............................................................................................................................. 41 1.6.3 Module reset ...................................................................................................................................... 43 1.7 RF connection ............................................................................................................................................ 45

(U)SIM interface ........................................................................................................................................ 46 1.8

(U)SIM application circuits ............................................................................................................. 47 1.9 Serial communication .............................................................................................................................. 53 1.9.1 Serial interfaces configuration ...................................................................................................... 54 1.9.2 Asynchronous serial interface (UART) ......................................................................................... 55 1.9.3 USB interface ..................................................................................................................................... 74 1.9.4 SPI interface ...................................................................................................................................... 79 1.9.5 MUX protocol (3GPP TS 27.010)..................................................................................................... 84 1.10 DDC (I2C) interface .................................................................................................................................... 86 1.10.1 Overview ............................................................................................................................................. 86 1.10.2 DDC application circuits .................................................................................................................. 86 1.11 Audio Interface .......................................................................................................................................... 92 I2S interface - PCM mode ................................................................................................................ 94 1.11.1 I2S interface - Normal I2S mode...................................................................................................... 94 1.11.2 1.11.3 I2S interface application circuits.................................................................................................... 95 1.11.4 Voiceband processing system ....................................................................................................... 97 1.12 General Purpose Input/Output (GPIO) .................................................................................................. 99 1.13 Reserved pins (RSVD) ............................................................................................................................ 106 1.14 Schematic for LISA-U2 module integration ...................................................................................... 107 1.15 Approvals .................................................................................................................................................. 108 1.15.1 European Conformance CE mark ................................................................................................ 108 1.15.2 US Federal Communications Commission notice ................................................................... 109 1.15.3 Innovation, Science, Economic Development Canada notice .................................................. 111 1.15.4 Australian Regulatory Compliance Mark .................................................................................... 113 1.8.1 UBX-13001118 - R25 Contents Page 4 of 182 LISA-U2 series - System Integration Manual ICASA Certification ......................................................................................................................... 113 1.15.5 1.15.6 KCC Certification ............................................................................................................................. 114 1.15.7 ANATEL Certification ..................................................................................................................... 114 1.15.8 CCC Certification ............................................................................................................................. 115 1.15.9 Giteki Certification .......................................................................................................................... 115 2 Design-In ................................................................................................................................................ 117 2.1 Design-in checklist ................................................................................................................................... 117 2.1.1 Schematic checklist ........................................................................................................................ 117 2.1.2 Layout checklist ............................................................................................................................... 118 2.1.3 Antenna checklist ............................................................................................................................ 118 2.2 Design Guidelines for Layout ................................................................................................................. 119 2.2.1 Layout guidelines per pin function ............................................................................................... 119 2.2.2 Footprint and paste mask ............................................................................................................ 128 2.2.3 Placement ........................................................................................................................................ 129 2.3 Thermal guidelines ................................................................................................................................. 130 2.4 Antenna guidelines ................................................................................................................................. 132 2.4.1 Antenna termination...................................................................................................................... 134 2.4.2 Antenna radiation ........................................................................................................................... 135 2.4.3 Examples of antennas ................................................................................................................... 136 2.4.4 Antenna detection functionality ................................................................................................. 138 2.5 ESD guidelines ......................................................................................................................................... 139 2.5.1 ESD immunity test overview ........................................................................................................ 139 2.5.2 ESD immunity test of u-blox LISA-U2 series reference designs .......................................... 140 2.5.3 ESD application circuits ................................................................................................................. 141 3 Features description......................................................................................................................... 144 3.1 Network indication .................................................................................................................................. 144 3.2 Antenna detection .................................................................................................................................. 144 3.3 Jamming Detection ................................................................................................................................ 144 3.4 TCP/IP and UDP/IP .................................................................................................................................. 144 3.4.1 Multiple PDP contexts and sockets ............................................................................................ 145 3.5 FTP ............................................................................................................................................................. 145 3.6 HTTP .......................................................................................................................................................... 146 3.7 SSL/TLS .................................................................................................................................................... 146 3.8 Dual stack IPv4/IPv6 ............................................................................................................................... 148 3.9 AssistNow clients and GNSS integration .......................................................................................... 148 3.10 Hybrid positioning and CellLocate ..................................................................................................... 148 3.10.1 Positioning through cellular information: CellLocate ............................................................ 148 3.10.2 Hybrid positioning ........................................................................................................................... 150 3.11 Control Plane Aiding / Location Services (LCS) ................................................................................. 151 3.12 Firmware update Over AT (FOAT) ........................................................................................................ 151 3.12.1 Overview ............................................................................................................................................ 151 3.12.2 FOAT procedure ............................................................................................................................... 151 3.13 Firmware update Over the Air (FOTA) ................................................................................................. 151 3.14 In-Band modem (eCall / ERA-GLONASS) ........................................................................................... 152 3.15 SIM Access Profile (SAP) ....................................................................................................................... 152 UBX-13001118 - R25 Contents Page 5 of 182 LISA-U2 series - System Integration Manual 3.16 Smart Temperature Management ...................................................................................................... 154 3.16.1 Smart Temperature Supervisor (STS) ....................................................................................... 154 3.16.2 Threshold definitions ..................................................................................................................... 155 3.17 Bearer Independent Protocol ................................................................................................................ 156 3.18 Multi-Level Precedence and Pre-emption Service ........................................................................... 156 3.19 Network Friendly Mode .......................................................................................................................... 156 3.20 Power saving ............................................................................................................................................ 157 4 Handling and soldering .................................................................................................................... 158 4.1 Packaging, shipping, storage and moisture preconditioning ........................................................ 158 4.2 Soldering ................................................................................................................................................... 158 4.2.1 Soldering paste ............................................................................................................................... 158 4.2.2 Reflow soldering .............................................................................................................................. 158 4.2.3 Optical inspection ........................................................................................................................... 160 4.2.4 Cleaning ............................................................................................................................................ 160 4.2.5 Repeated reflow soldering ............................................................................................................ 160 4.2.6 Wave soldering ................................................................................................................................ 160 4.2.7 Hand soldering ................................................................................................................................ 160 4.2.8 Rework ............................................................................................................................................... 161 4.2.9 Conformal coating ........................................................................................................................... 161 4.2.10 Casting ............................................................................................................................................... 161 4.2.11 Grounding metal covers ................................................................................................................. 161 4.2.12 Use of ultrasonic processes .......................................................................................................... 161 5 Product Testing .................................................................................................................................. 162 5.1 u-blox in-series production test ........................................................................................................... 162 5.2 Test parameters for OEM manufacturer ........................................................................................... 163 5.2.1 Go/No go tests for integrated devices ...................................................................................... 163 5.2.2 Functional tests providing RF operation ................................................................................... 163 Appendix ...................................................................................................................................................... 166 A Migration from LISA-U1 to LISA-U2 series ............................................................................... 166 A.1 Checklist for migration .......................................................................................................................... 166 A.2 Software migration ................................................................................................................................. 167 A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules.................................. 167 A.3 Hardware migration ................................................................................................................................ 167 A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules ................................. 167 A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series ........................................................... 169 A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series ............................................................ 177 B Glossary ................................................................................................................................................ 178 Related documents ................................................................................................................................. 180 Revision history ......................................................................................................................................... 181 Contact ......................................................................................................................................................... 182 UBX-13001118 - R25 Contents Page 6 of 182 LISA-U2 series - System Integration Manual 1 System description 1.1 Overview LISA-U2 cellular modules integrate full-feature 3G UMTS/HSxPA and 2G GSM/GPRS/EDGE protocol stack with Assisted GPS support. These SMT modules come in the compact LISA form factor, featuring Leadless Chip Carrier (LCC) packaging technology. 3G UMTS/HSDPA/HSUPA Characteristics 2G GSM/GPRS/EDGE Characteristics Class A User Equipment1 UMTS Terrestrial Radio Access (UTRA) Frequency Division Duplex (FDD) 3GPP Release 7 (HSPA+) Rx Diversity for LISA-U230 2-band support for LISA-U260:

Band II (1900 MHz), Band V (850 MHz) 2-band support for LISA-U270:

Band I (2100 MHz), Band VIII (900 MHz) 5-band support for LISA-U201:

Band I (2100 MHz), Band II (1900 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) 6-band support for LISA-U200 and LISA-U230:

Band I (2100 MHz), Band II (1900 MHz), Band IV (1700 MHz), Band V (850 MHz), Band VI (800 MHz), Band VIII (900 MHz) WCDMA/HSDPA/HSUPA Power Class Power Class 3 (24 dBm) for WCDMA/HSDPA/HSUPA mode PS (Packet Switched) Data Rate HSUPA category 6, up to 5.76 Mbit/s UL HSDPA category 8 up to 7.2 Mbit/s DL for LISA-U200, HSDPA category 14 up to 21.1 Mbit/s DL for LISA-U230 WCDMA PS data up to 384 kbit/s DL/UL CS (Circuit Switched) Data Rate WCDMA CS data up to 64 kbit/s DL/UL Class B Mobile Station2 GSM EDGE Radio Access (GERA) 3GPP Release 7 Rx Diversity for LISA-U230 4-band support GSM 850 MHz, E-GSM 900 MHz, DCS 1800 MHz, PCS 1900 MHz GSM/GPRS Power Class Power Class 4 (33 dBm) for GSM/E-GSM bands Power Class 1 (30 dBm) for DCS/PCS bands EDGE Power Class Power Class E2 (27 dBm) for GSM/E-GSM bands Power Class E2 (26 dBm) for DCS/PCS bands PS (Packet Switched) Data Rate GPRS multislot class 123, coding scheme CS1-CS4, up to 85.6 kbit/s DL/UL up to 236.8 kbit/s DL/UL CS (Circuit Switched) Data Rate GSM CS data up to 9.6 kbit/s DL/UL supported in transparent/non transparent mode LISA-U201, LISA-U260 and LISA-U270 EDGE multislot class 123, coding scheme MCS1-MCS9, Table 1: LISA-U2 series UMTS/HSDPA/HSUPA and GSM/GPRS/EDGE characteristics Operation modes I to III are supported on GSM/GPRS networks, while allowing users to define their preferred service from GSM to GPRS. Paging messages for GSM calls may be monitored (optional) during GPRS data transfer in non-coordinating NOM II-III. 1 Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active without any interruption in service. 2 Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. If for example during data transmission an incoming call occurs, the data connection is suspended to allow the voice communication. Once the voice call has terminated, the data service is resumed. 3 GPRS/EDGE multislot class 12 implies maximum of 4 slots in DL (reception), 4 slots in UL (transmission) with 5 slots in total UBX-13001118 - R25 System description Page 7 of 182 LISA-U2 series - System Integration Manual 3G Transmission and Receiving: LISA-U2 modules implement 3G High-Speed Uplink Packet Access

(HSUPA) category 6. LISA-U200, LISA-U201, LISA-U260 and LISA-U270 modules implement 3G High Speed Downlink Packet Access (HSDPA) category 8. LISA-U230 modules implement the 3G HSDPA category 14. The HSUPA and HSDPA categories determine the maximum speed at which data can be respectively transmitted and received. Higher categories allow faster data transfer rates, as indicated in Table 1. The 3G network automatically performs adaptive coding and modulation using a choice of forward error correction code rate and choice of modulation type, to achieve the highest possible data rate and data transmission robustness according to the quality of the radio channel. 2G Transmission and Receiving: LISA-U2 series modules implement GPRS/EGPRS multislot class 12. GPRS and EGPRS multislot classes determine the maximum number of timeslots available for upload and download and thus the speed at which data can be transmitted and received. Higher classes typically allow faster data transfer rates, as indicated in Table 1. The 2G network automatically configures the number of timeslots used for reception or transmission

(voice calls take precedence over GPRS/EGPRS traffic) and channel encoding (from Coding Scheme 1 up to Modulation and Coding Scheme 9), performing link adaptation to achieve the highest possible data rate. Table 2 summarizes the interfaces and features provided by LISA-U2 modules. Model UMTS Bands Interfaces Audio Functions Grade

z H M

A P S H S T M U E G D E

S R P G M S G

d n a b

d a u q T R A U

) C 2 I

C D D I O P G I P S B S U i o d u a g o a n A l i o d u a l a t i g D i n o i t a c d n i i k r o w t e N n o i t c e t e d a n n e t n A n o i t c e t e d g n m m a J i P T T H

, P T F d e d d e b m E P D U

P C T d e d d e b m E S L T

L S S d e d d e b m E e r a w t f o s w o N t s s s A i e t a c o L l l e C A T O F S S A N O L G

A R E

l l a C e l i a i r e s a v e t a d p u W F m e d o M a v S S N G i y t i s r e v d x R i l i a n o s s e f o r P e v i t o m o t u A d r a d n a t S

s

t i b M

A P U S H

s

t i b M

A P D S H LISA-U200 5.76 7.2 1 1 1 1 14 2 4 LISA-U200 FOTA 5.76 7.2 800/850/900 1700/1900/2100 1 1 1 1 14 2 LISA-U201 5.76 7.2 1 1 1 1 14 2 LISA-U201 FOTA 5.76 7.2 1 1 1 1 14 2 800/850/900 1700/1900/2100 800/850/900 1900/2100 800/850/900 1900/2100 800/850/900 1700/1900/2100 LISA-U230 5.76 21.1 1 1 1 1 14 2 LISA-U260 5.76 7.2 850/1900 1 1 1 1 14 2 4 LISA-U270 5.76 7.2 900/2100 1 1 1 1 14 2 4 LISA-U200-52S module product version is approved by SKT Korean network operator. LISA-U200-62S module product version is approved by NTT DoCoMo Japanese network operator LISA-U270-62S, LISA-U270-63S and LISA-U270-68S modules product versions are approved and locked for SoftBank Japanese network operator. Table 2: LISA-U2 series summary of interfaces and features 4 Not supported by the 01 product version UBX-13001118 - R25 System description Page 8 of 182 1.2 Architecture LISA-U2 series - System Integration Manual Figure 1: LISA-U2 series block diagram (for available options see Table 2) 1.2.1 Functional blocks LISA-U2 modules consist of the following internal functional blocks: RF section, Baseband and Power Management Unit section. LISA-U2 series RF section A shielding box contains the RF high-power signal circuitry, including:

Multimode Single Chain Power Amplifier Module used for 3G HSPA/WCDMA and 2G EDGE/GSM operations Power Management Unit with integrated DC/DC converter for the Power Amplifier Module The RF antenna pad (ANT) is directly connected to the main antenna switch, which dispatches the RF signals according to the active mode. For time-duplex 2G operation, the incoming signal at the active receiver (RX) slot is applied by the main antenna switch to the duplexer SAW filter bank for out-of-

band rejection and then sent to the appropriate receiver port of the RF transceiver. During the allocated Transmitter (TX) slots, the low level signal coming from the RF transceiver is enhanced by the power amplifier and then directed to the antenna pad through the main antenna switch. The 3G transmitter and receiver are active at the same time due to frequency-domain duplex operation. The switch integrated in the main antenna switch connects the antenna port to the duplexer SAW filter bank which separates the TX and RX signal paths. The duplexer itself provides front-end RF filtering for RX band selection while combining the amplified TX signal coming from the power amplifier. A separated shielding box contains all the other analog RF components, including:

Antenna switch and duplexer SAW filter bank for main paths Antenna switch and SAW filter bank for diversity receiver Up to six-band HSPA/WCDMA and quad-band EDGE/GPRS/GSM transceiver UBX-13001118 - R25 System description Page 9 of 182 Duplexers

& Filters ANT RF SWITCH RF Transceiver Switch & Multi band & mode PA PA PM U Filter Bank Transceiver PMU Memory Power Management Unit ANT_DIV RF SWITCH Vcc (supply) V_BCKP (RTC) V_INT (I/O) 26 MHz 32.768 kHz Wireless Base-band Processor

(U)SIM card DDC (for GNSS) UART SPI USB GPIO(s) Digital audio (I2S) Power on External reset LISA-U2 series - System Integration Manual Power management unit with integrated DC/DC converter for the power amplifier module Voltage-controlled temperature compensated 26 MHz crystal oscillator (VC-TCXO) While operating in 3G mode, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the integrated LNA enhances the RX sensitivity while discrete inter-

stage SAW filters additionally internal programmable gain amplifier optimizes the signal levels before delivering to the analog I/Q to baseband for further digital processing. improve the rejection of out-of-band blockers. An For 2G operations, a constant gain direct conversion receiver with integrated LNAs and highly linear RF quadrature demodulator are used to provide the same I/Q signals to the baseband as well. In transmission mode, the up-conversion is implemented by means of a digital sigma-delta transmitter or polar modulator depending on the modulation to be transmitted. The RF antenna pad for the diversity receiver (ANT_DIV) available on LISA-U230 modules is directly connected to the antenna switch for the diversity receiver, which dispatches the incoming RF signals to the dedicated SAW filter bank for out-of-band rejection and then to the diversity receiver port of the RF transceiver. In all the modes, a fractional-N sigma-delta RF synthesizer and an on-chip 3.296-4.340 GHz voltage-

controlled oscillator are used to generate the local oscillator signal. The frequency reference to RF oscillators is provided by the 26 MHz VC-TCXO. The same signal is buffered to the baseband as a master reference for clock generation circuits while operating in active mode. LISA-U2 series modulation techniques Modulation techniques related to radio technologies supported by LISA-U2 modules, are listed as follows:

GSM GMSK GPRS GMSK EDGE GMSK / 8-PSK WCDMA QPSK HSDPA QPSK / 16-QAM HSUPA QPSK / 16-QAM LISA-U2 series Baseband and Power Management Unit section Another shielding box of the LISA-U2 modules includes all the digital circuitry and the power supplies, basically the following functional blocks:

Cellular baseband processor, a mixed signal ASIC which integrates:

o Microprocessor for controller functions, 2G & 3G upper layer software o DSP core for 2G Layer 1 and audio processing o 3G coprocessor and HW accelerator for 3G layer 1 control software and routines o Dedicated HW for interfaces management Memory system in a Multi-Chip Package (MCP) integrating two devices:

o NOR flash non-volatile memory o DDR SRAM volatile memory supply VCC reference in idle or power-off modes Power Management Unit (PMU), used to derive all the system supply voltages from the module 32.768 kHz crystal, connected to the Real Time Clock (RTC) oscillator to provide the clock UBX-13001118 - R25 System description Page 10 of 182 LISA-U2 series - System Integration Manual 1.3 Pin-out Table 3 details the pin-out of the LISA-U2 modules, with pins grouped by function. Function Pin Module No I/O Description Remarks Power VCC All 61, 62, 63 I Module supply input Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must be always above the minimum limit of the operating range. Consider that there are large current spikes in connected mode, when a GSM call is enabled. VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize power loss due to series resistance. See section 1.5.2 GND pins are internally connected but a good

(low impedance) external ground connection can improve RF performance: all GND pins must be externally connected to ground. GND All N/A Ground 1, 3, 6, 7, 8, 17, 25, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 60, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76 2 4 V_BCKP All I/O Real Time Clock V_INT All supply input/output O Digital Interfaces supply output V_BCKP = 1.8 V (typical) generated by the module when VCC supply voltage is within valid operating range. See section 1.5.4 V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. See section 1.5.5 VSIM All 50 O SIM supply output VSIM = 1.80 V typical or 2.90 V typical RF ANT All 68 I/O RF input/output for main Tx/Rx antenna ANT_DIV LISA-U230 74 I RF input for Rx diversity antenna 50 nominal impedance See section 1.7, section 2.4 and section 2.2.1.1 SIM SIM_IO All 48 I/O SIM data generated by the module according to the SIM card type. See section 1.8 50 nominal impedance. See section 1.7, section 2.4 and section 2.2.1.1 SIM_CLK All O SIM clock SIM_RST All O SIM reset 47 49 Internal 4.7 k pull-up to VSIM. Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 Must meet SIM specifications. See section 1.8 UBX-13001118 - R25 System description Page 11 of 182 Function Pin Module I/O Description Remarks SPI SPI_MISO All O SPI Data Line Output SPI_MOSI All 56 SPI Data Line Input SPI_SCLK All 55 SPI Serial Clock Input LISA-U2 series - System Integration Manual Module Output: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. See section 1.9.4 Module Input: module runs as an SPI slave. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). Idle high. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.4 Module Input: module runs as an SPI slave. Idle low (CPOL=0). Internal active pull-down to GND enabled. See section 1.9.4 SPI_SRDY All SPI_MRDY All SPI Slave Ready Output Module Output: module runs as an SPI slave. Idle low. See section 1.9.4 SPI Master Ready Input Module Input: module runs as an SPI slave. Idle low. Internal active pull- down to GND enabled. See section 1.9.4 DDC SCL O I2C bus clock line Fixed open drain. External pull-up required. See section 1.10 SDA I/O I2C bus data line Fixed open drain. External pull-up required. See section 1.10 UART RxD O UART data output Circuit 104 (RxD) in ITU-T V.24. TxD All 15 I UART data input Circuit 103 (TxD) in ITU-T V.24. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for FW update and debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 106 (CTS) in ITU-T V.24. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. Provide access to the pin for debugging if the USB interface is connected to the application processor. See section 1.9.2 CTS All 14 O UART clear to send output RTS All 13 I UART ready to send input DSR RI DTR DCD UART data set ready output Circuit 107 (DSR) in ITU-T V.24. See section 1.9.2 UART ring indicator output Circuit 125 (RI) in ITU-T V.24. See section 1.9.2 UART data terminal ready input Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT (1.8 V) enabled. See section 1.9.2 UART data carrier detect output Circuit 109 (DCD) in ITU-T V.24. See section 1.9.2 UBX-13001118 - R25 System description Page 12 of 182 No 57 58 59 45 46 16 9 10 12 11 I I O I O O I O All All All All All All All LISA-U2 series - System Integration Manual Function Pin Module No I/O Description Remarks GPIO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 All All All All All All All All All All All All All All All 20 21 23 24 51 39 40 53 54 55 56 57 58 59 18 I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO I/O GPIO See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 See section 1.12 USB VUSB_DET I USB detect input USB_D-

All 26 I/O USB Data Line D- 90 nominal differential impedance (Z0) USB_D+

All 27 I/O USB Data Line D+ 90 nominal differential impedance (Z0) Input for VBUS (5 V typical) USB supply sense to enable USB interface. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by USB 2.0 specifications [7] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [7] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 PWR_ON pin has high input impedance. Do not keep floating in noisy environment:

external pull-up required. See section 1.6.1 System PWR_ON All 19 I Power-on input RESET_N All 22 I External reset input Internal 10 k pull-up to V_BCKP. See section 1.6.3 UBX-13001118 - R25 System description Page 13 of 182 LISA-U2 series - System Integration Manual Function Pin Module I/O Description Remarks Digital Audio I2S_CLK All I/O First I2S clock No 43 I2S_RXD All 44 I First I2S receive data Check device specifications to ensure compatibility with module supported modes. See section 1.11. Internal active pull-down to GND enabled. Check device specifications to ensure compatibility with module supported modes. See section 1.11. I2S_TXD All 42 O I2S_WA All 41 I/O First I2S word First I2S transmit data Check device specifications to ensure compatibility with module supported modes. See section 1.11. alignment Check device specifications to ensure compatibility with module supported modes. See section 1.11. I2S1_CLK All 53 I/O Second I2S clock Check device specifications to ensure I2S1_RXD All 39 I Second I2S receive data I2S1_TXD All 40 O I2S1_WA All 54 I/O Second I2S word Second I2S transmit data alignment CODEC_CLK All O Clock output Reserved RSVD All N/A RESERVED pin 52 5 74 LISA-U200 LISA-U201 LISA-U260 LISA-U270 Table 3: LISA-U2 modules pin definition, grouped by function RSVD N/A RESERVED pin Do not connect See section 1.13 compatibility with module supported modes. See section 1.11. Internal active pull-down to GND enabled. Check device specifications to ensure compatibility with module supported modes. See section 1.11. Check device specifications to ensure compatibility with module supported modes. See section 1.11. Check device specifications to ensure compatibility with module supported modes. See section 1.11. Digital clock output for external audio codec See section 1.11. This pin must be connected to ground See section 1.13 UBX-13001118 - R25 System description Page 14 of 182 Power-Off Idle LISA-U2 series - System Integration Manual 1.4 Operating modes LISA-U2 series modules have several operating modes. The operating modes are defined in Table 4 and described in details in Table 5, providing general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Normal Operation Idle mode Module processor core runs with 32 kHz as the reference oscillator. Power-Off Mode VCC supply within operating range and module is switched off. Active mode Module processor core runs with 26 MHz as the reference oscillator. Connected mode Voice or data call enabled and processor core runs with 26 MHz as the reference oscillator. Table 4: Module operating modes definition Description Transition between operating modes Operating Mode Not-Powered Module is switched off. Application interfaces are not accessible. Internal RTC timer operates only if a valid voltage is applied to V_BCKP pin. When VCC supply is removed, the module enters not-powered mode. When in not-powered mode, the module cannot be switched on by a low pulse on PWR_ON input, by a rising edge on RESET_N input, or by a preset RTC alarm. When in not-powered mode, the module can be switched on by applying VCC supply (see 1.6.1) so that the module switches from not-

powered to active mode. Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible. Only the internal RTC timer in operation. When the module is switched off by an appropriate power-off event

(see 1.6.2), the module enters power-off mode from active mode. When in power-off mode, the module can be switched on by a low pulse on PWR_ON input, by a rising edge on RESET_N input, or by a preset RTC alarm (see 1.6.1): module switches from power-off to active mode. When VCC supply is removed, the module switches from power-off mode to not-powered mode. Application interfaces are disabled: the module does not accept data signals from an external device connected to the module. The module automatically enters idle mode whenever possible if power saving is enabled by AT+UPSV (see u-blox AT Commands Manual [2]), reducing current consumption (see 1.5.3.3). If HW flow control is enabled (default setting) and AT+UPSV=1 or AT+UPSV=3 has been set, the UART CTS line indicates when the UART is enabled (see 1.9.2.2, 1.9.2.3). If HW flow control is disabled by AT&K0, the UART CTS line is fixed to ON state (see 1.9.2.2). Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [2]). The module automatically switches from active mode to idle mode whenever possible if power saving is enabled (see 1.5.3.3, 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [2], AT+UPSV). The module wakes up from idle mode to active mode for these events:

Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see 1.5.3.3, 1.9.2.3) Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 has been set (see 1.9.2.3) RTC alarm occurs (see the u-blox AT Commands Manual [2], AT+CALA) Data received on UART interface, if HW flow control has been disabled by AT&K0 and AT+UPSV=1 has been set (see 1.9.2.3) RTS input set ON by the DTE if HW flow control has been disabled by AT&K0 and AT+UPSV=2 has been set (see 1.9.2.3) DTR input set ON by DTE if AT+UPSV=3 has been set (see 1.9.2.3) USB detection, applying 5 V (typical) to VUSB_DET input (see 1.9.3) The connected USB host forces a remote wakeup of the module as a USB device (see 1.9.3) The connected SPI master indicates by the SPI_MRDY input signal that it is ready for transmission or reception (see 1.9.4) The connected u-blox GNSS receiver indicates by the GPIO3 pin that it is ready to send data (see 1.10, 1.12) UBX-13001118 - R25 System description Page 15 of 182 LISA-U2 series - System Integration Manual Operating Mode Active Connected Description Transition between operating modes The module is ready to accept data signals from an external device unless power saving configuration is enabled by AT+UPSV (see sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [2]). When the module is switched on by an appropriate power-on event

(see 1.6.1), the module enters active mode from not-powered or power-off mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle mode whenever possible and the module wakes up from idle to active mode in the events listed above (see the idle to active transition description). When a voice call or a data call is initiated, the module switches from active mode to connected mode. A voice call or a data call is in progress. When a voice or a data call is enabled, the application interfaces are kept enabled and the module is prepared to accept data from an external device unless power saving configuration is enabled by AT+UPSV (see 1.9.2.3, 1.9.3.2, 1.9.4.2 and the u-blox AT Commands Manual [2]). When a voice call or a data call is initiated, the module enters connected mode from active mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from connected to idle mode whenever possible in case of PSD data call with internal context activation, and then it wakes up from idle to connected mode in the events listed above (see the idle to active transition description). When a voice call or a data call is terminated, the module returns to active mode. Table 5: Module operating modes description Figure 2 describes the transition between the different operating modes. Figure 2: Operating modes transition UBX-13001118 - R25 System description Page 16 of 182 Not powered Remove VCC Switch ON:

Apply VCC Power off Switch ON:

PWR_ON RESET_N RTC Alarm Switch OFF:

AT+CPWROFF PWR_ON Connected Active Idle Incoming/outgoing call or other dedicated device network communication Call terminated, communication dropped If power saving is enabled and there is no activity for a defined time interval Any wake up event described in the module operating modes summary table above LISA-U2 series - System Integration Manual 1.5 Power management 1.5.1 Power supply circuit overview LISA-U2 series modules feature a power management concept optimized for the most efficient use of the supplied power. This is achieved by hardware design that uses a power efficient circuit topology

(Figure 3), and by power management software that controls the modules power saving mode. Figure 3: LISA-U2 series power management simplified block diagram The pins with supply functions are listed in Table 6, Table 12 and Table 15. LISA-U2 series modules must be supplied via the VCC pins. There is only one main power supply input, available on the three VCC pins that must be all connected to the external power supply. The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit (PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators. UBX-13001118 - R25 System description Page 17 of 182 2G/3G Power Amplifier(s) 2G/3G PA PMU Transceiver PMU RF Transceiver Linear LDO Linear LDO Switching Step-Down Switching Step-Down Linear LDO Linear LDO Linear LDO Memory NOR Flash DDR SRAM EBU I/O CORE Analog SIM RTC VCC 61 VCC 62 VCC 63 5 x 10 F Power Management Unit Baseband Processor V_INT V_BCK P 4 2 VSIM 50 22 F 220 nF 220 nF LISA-U2 series - System Integration Manual V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time Clock can be externally supplied via the V_BCKP pin (see section 1.5.4). When a 1.8 V or a 3 V SIM card type is connected, LISA-U2 series modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance with the ISO-IEC 7816-3 specifications. The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-U2 series modules in the final application. The integrated Power Management Unit also provides the control state machine for system start-up and system reset control. 1.5.2 Module supply (VCC) The LISA-U2 series modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system power supply circuit is able to support peak power (see the LISA-U2 series Data Sheet [1] for the detailed specifications). Name VCC Description Remarks Module power supply input VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range. Consider that during a GSM call there are large current spikes in connected mode. GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads must be connected to ground. GND Ground Table 6: Module supply pins VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels can be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible points. The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-U2 series Data Sheet [1]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage normal operating range. The module cannot be switched on if the VCC voltage value is below the specified normal operating range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for more than 3 seconds after the start of the module switch-on sequence. When LISA-U2 series modules are in operation, the voltage provided to VCC pins can exceed the normal operating range limits but must be within the extended operating range limits specified in the LISA-U2 series Data Sheet [1]. Occasional deviations from the ETSI specifications may occur when the input voltage at the VCC pins is outside the normal operating range and is within the extended operating range. UBX-13001118 - R25 System description Page 18 of 182 LISA-U2 series - System Integration Manual LISA-U2 series modules switch off when the VCC voltage value drops below the specified extended operating range minimum limit: ensure that the input voltage at the VCC pins never drops below the minimum limit of the extended operating range when the module is switched on, not even during a GSM transmit burst, where the current consumption can rise up to maximum peaks of 2.5 A in case of a mismatched antenna load. Operation above the normal operating range maximum limit is not recommended and extended exposure beyond it may affect device reliability. Stress beyond the VCC absolute maximum ratings can cause permanent damage to the module:

if necessary, voltage spikes beyond the VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection. When designing the power supply for the application, pay specific attention to power losses and transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics:

o Voltage drop during transmit slots must be lower than 400 mV o No undershoot or overshoot at the start and at the end of transmit slots o Voltage ripple during transmit slots must be minimized:

less than 70 mVpp if fripple 200 kHz less than 10 mVpp if 200 kHz < fripple 400 kHz less than 2 mVpp if fripple > 400 kHz Figure 4: Description of the VCC voltage profile versus time during a GSM call Any degradation in power supply performance (due to losses, noise or transients) will directly affect the RF performance of the module since the single external DC power source indirectly supplies all the digital and analog interfaces, and also directly supplies the RF power amplifier (PA). The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms. This VCC slope allows a proper switch-on of the module when the voltage rises to the VCC normal operating range from a voltage of less than 2.25 V. If the external supply circuit cannot raise the VCC voltage from 2.5 V to 3.2 V within 1 ms, the RESET_N pin should be kept low during VCC rising edge, so that the module will switch on releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal operating range. UBX-13001118 - R25 System description Page 19 of 182 Voltage 3.8 V

(typ) ripple overshoot drop ripple undershoot RX slot unused unused slot slot TX slot unused unused slot slot unused MON slot slot RX slot unused unused slot slot TX slot unused unused slot slot MON slot unused slot GSM frame 4.615 ms

(1 frame = 8 slots) GSM frame 4.615 ms Time

(1 frame = 8 slots) LISA-U2 series - System Integration Manual 1.5.2.1 VCC application circuits LISA-U2 series modules must be supplied through the VCC pins by a clean DC power supply, which can be selected according to the application requirements (see Figure 5) between the different possible supply sources types, the most common ones of which are the following:

Switching regulator Low Drop-Out (LDO) linear regulator Rechargeable Lithium-ion (Li-Ion) or Lithium-ion polymer (Li-Pol) battery Primary (disposable) battery Figure 5: VCC supply concept selection The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the LISA-U2 series modules operating supply voltage. The use of switching step-down provides the best power efficiency for the overall application and minimizes the current drawn from the main supply source. The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less than 5 V). In this case, the typical 90% efficiency of the switching regulator will diminish the benefit of voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy in thermal power. If LISA-U2 series modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Li-Ion or Li-Pol battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided. The use of a primary (not rechargeable) battery is uncommon, since most of the cells available are seldom capable of delivering the burst peak current for a GSM call due to high internal resistance. Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in LISA-U2 series modules). The charger circuit should be designed in order to prevent over-

voltage on VCC beyond the upper limit of the absolute maximum rating. The usage of more than one DC supply at the same time should be carefully evaluated: depending on the supply source characteristics, different DC supply systems can result as being mutually exclusive. The usage of a regulator or a battery not able to withstand the maximum VCC peak current consumption stated in the LISA-U2 series Data Sheet [1] is generally not recommended. However, if the selected regulator or battery is not able to withstand the maximum VCC peak current, it must be UBX-13001118 - R25 System description Page 20 of 182 Main Supply Available?

No, portable device Battery Li-Ion 3.7 V Yes, always available Main Supply Voltage > 5V?

No, less than 5 V Linear LDO Regulator Yes, greater than 5 V Switching Step-Down Regulator LISA-U2 series - System Integration Manual able to withstand at least the maximum average current consumption value specified in the LISA-U2 series Data Sheet [1]. The additional energy required by the module during a GSM/GPRS Tx slot (when in the worst case the current consumption can rise up to 2.5 A, as described in section 1.5.3.1) can be provided by an appropriate bypass tank capacitor or supercapacitor with very large capacitance and very low ESR placed close to the module VCC pins. Depending on the actual capability of the selected regulator or battery, the required capacitance can be considerably larger than 1 mF and the required ESR can be in the range of a few tens of m. Carefully evaluate the implementation of this solution since aging and temperature conditions significantly affect the actual capacitor characteristics. The following sections highlight some design aspects for each of the supplies listed above. Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements:

Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current pulses with 1/8 duty cycle to the VCC pins. Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile. High switching frequency: for best performance and for smaller applications, select a switching frequency 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance. An additional L-

C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors. PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in connected mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the module changes status from idle/active mode to connected mode (where current consumption increases to a value greater than 100 mA): it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA). Output voltage slope: the use of the soft start function provided by some voltage regulator must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. UBX-13001118 - R25 System description Page 21 of 182 C1 C2 C3 C4 C5 C6 C7 C8 D1 L1 R1 R2 R3 R4 R5 U1 LISA-U2 series - System Integration Manual Figure 6 and the components listed in Table 7 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high: switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply. Figure 6: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator Reference Description Part Number - Manufacturer 10 F Capacitor Ceramic X7R 5750 15% 50 V C5750X7R1H106MB - TDK 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 680 pF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71H681KA01 - Murata 22 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H220JZ01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 470 nF Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E474KA12 - Murata 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor 10 H Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics 470 k Resistor 0402 5% 0.1 W 2322-705-87474-L - Yageo 15 k Resistor 0402 5% 0.1 W 2322-705-87153-L - Yageo 22 k Resistor 0402 5% 0.1 W 2322-705-87223-L - Yageo 390 k Resistor 0402 1% 0.063 W RC0402FR-07390KL - Yageo 100 k Resistor 0402 5% 0.1 W 2322-705-70104-L - Yageo Step Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology Table 7: Suggested components for the VCC voltage supply application circuit using a step-down regulator UBX-13001118 - R25 System description Page 22 of 182 12V R1 RUN BD 4 VIN BOOST SW U1 1 2 3 8 10 5 9 7 6 VC RT PG SYNC FB GND 11 R2 R3 C1 C2 C3 C4 C5 LISA-U2 series 61 VCC 62 VCC 63 VCC C6 L1 D1 R4 C7 C8 R5 GND C1 C2 C3 C4 C5 C6 D1 L1 R1 R2 R3 R4 R5 U1 Figure 7 and the components listed in Table 8 show an example of a low-cost power supply circuit, where the VCC module supply is provided by a step-down switching regulator capable of delivering 2.5 A current pulses, transforming a 12 V supply input. LISA-U2 series - System Integration Manual Figure 7: Suggested low cost solution for the VCC voltage supply application circuit using a step-down regulator Reference Description Part Number - Manufacturer 22 F Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 Murata 100 F Capacitor Tantalum B_SIZE 20% 6.3V 15m T520B107M006ATE015 Kemet 5.6 nF Capacitor Ceramic X7R 0402 10% 50 V GRM155R71H562KA88 Murata 6.8 nF Capacitor Ceramic X7R 0402 10% 50 V GRM155R71H682KA88 Murata 56 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H560JA01 Murata 220 nF Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E224KA88 Murata Schottky Diode 25V 2 A STPS2L25 STMicroelectronics 5.2 H Inductor 30% 5.28A 22 m 4.7 k Resistor 0402 1% 0.063 W 910 Resistor 0402 1% 0.063 W 82 Resistor 0402 5% 0.063 W 8.2 k Resistor 0402 5% 0.063 W 39 k Resistor 0402 5% 0.063 W MSS1038-522NL Coilcraft RC0402FR-074K7L Yageo RC0402FR-07910RL Yageo RC0402JR-0782RL Yageo RC0402JR-078K2L Yageo RC0402JR-0739KL Yageo Step-Down Regulator 8-VFQFPN 3 A 1 MHz L5987TR ST Microelectronics Table 8: Suggested components for low cost solution VCC voltage supply application circuit using a step-down regulator UBX-13001118 - R25 System description Page 23 of 182 12V 8 VCC 3 INH OUT 1 C1 C6 6 2 FSW U1 FB SYNC COMP 5 4 R5 GND 7 LISA-U2 series L1 D1 R4 C4 C5 R3 C3 R1 R2 C2 61 VCC 62 VCC 63 VCC GND C3 R1 R2 R3 U1 LISA-U2 series - System Integration Manual Low Drop-Out (LDO) linear regulator The characteristics of the LDO linear regulator connected to the VCC pins should meet the following requirements:

Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper voltage value to the VCC pins and of delivering 2.5 A current pulses with 1/8 duty cycle. Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the maximum input voltage to the minimum output voltage to evaluate the power dissipation of the regulator). Output voltage slope: the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. Figure 8 and the components listed in Table 9 show an example of a power supply circuit where the VCC module supply is provided by an LDO linear regulator capable of delivering 2.5 A current pulses, with appropriate power handling capability. The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to a voltage value within the module VCC normal operating range. It is recommended to configure the LDO linear regulator so that it generates a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 8 and Table 9). This reduces the power on the linear regulator and improves the thermal design of the supply circuit. Figure 8: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator Reference Description Part Number - Manufacturer C1, C2 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp 9.1 k Resistor 0402 5% 0.1 W RC0402JR-079K1L - Yageo Phycomp 3.9 k Resistor 0402 5% 0.1 W RC0402JR-073K9L - Yageo Phycomp LDO Linear Regulator ADJ 3.0 A LT1764AEQ#PBF - Linear Technology Table 9: Suggested components for VCC voltage supply application circuit using an LDO linear regulator UBX-13001118 - R25 System description Page 24 of 182 LISA-U2 series 61 VCC 62 VCC 63 VCC 5V 2 IN 4 OUT C1 R1 R2 C2 C3 1 SHDN 5 ADJ R3 GND U1 GND 3 LISA-U2 series - System Integration Manual Rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the modules maximum average current consumption to VCC pins. The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts. Primary (disposable) battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following requirements:

Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be capable of delivering 2.5 A current pulses with 1/8 duty-cycle to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption at the VCC pins. The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts. Additional recommendations for the VCC supply application circuits To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines

(connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible in order to minimize power losses. It is recommended to properly connect all three VCC pins and all twenty GND pins of the module to the supply source to minimize series resistance losses. To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a GSM call (when current consumption on the VCC supply can rise up to as much as 2.5 A in the worst case), place a bypass capacitor with large capacitance (more than 100 F) and low ESR near the VCC pins, for example:

330 F capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor) The use of very large capacitors (i.e. greater than 1000 F) on the VCC line and the use of the soft start function provided by some voltage regulators must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. To reduce voltage ripple and noise, which should improve RF performance if the application device integrates an internal antenna, place the following series ferrite bead and bypass capacitors near the VCC pins of the module:

Ferrite bead for GHz band noise (e.g. Murata BLM18EG221SN1) as close as possible to the VCC pins of the module, implementing the circuit described in Figure 9, to filter EMI in all the GSM /

UMTS bands. UBX-13001118 - R25 System description Page 25 of 182 LISA-U2 series - System Integration Manual 68 pF capacitor with Self-Resonant Frequency in the 800/900 MHz range (e.g. Murata GRM1555C1H680J) at the VCC line where it narrows close to the module (see Figure 9), to filter EMI in lower bands 15 pF capacitor with Self-Resonant Frequency GRM1555C1H150J) at the VCC line where it narrows close to the module (see Figure 9), to filter EMI in higher bands 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources 100 nF capacitor (e.g. Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources in 1800/1900 MHz range (e.g. Murata Figure 9 shows the complete configuration, but keep in mind that the mounting of each single component depends on the application design. It is highly recommended to provide the series ferrite bead and all the VCC bypass capacitors as described in Figure 9 and Table 10 if the application device integrates an internal antenna. Figure 9: Suggested schematic and layout design for the VCC line; highly recommended when using an integrated antenna Reference Description Part Number - Manufacturer C1 C2 C3 C4 C5 FB1 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET Chip Ferrite Bead EMI Filter for GHz Band Noise 220 at 100 MHz, 260 at 1 GHz, 2000 mA BLM18EG221SN1 - Murata Table 10: Suggested parts for VCC circuit close to module pins; highly recommended when using an integrated antenna External battery charging application circuit LISA-U2 series modules do not have an on-board charging circuit. An example of a battery charger design, suitable for applications that are battery powered with a Li-Ion (or Li-Polymer) cell, is provided in Figure 10. In the application circuit, a rechargeable Li-Ion (or Li-Polymer) battery cell, that features proper pulse and DC discharge current capabilities and proper DC series resistance, is directly connected to the VCC supply input of LISA-U2 series module. Battery charging is completely managed by the STMicroelectronics L6924U Battery Charger IC that, from a USB power source (5.0 V typ.), charges as a linear charger the battery, in three phases:

Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current. UBX-13001118 - R25 System description Page 26 of 182 LISA-U2 series VCC VCC VCC 61 62 63 FB1 3V8

C1 C2 C3 C4 C5 LISA-U series GND Capacitor with SRF ~900 MHz C5 Capacitor with SRF ~1900 MHz Ferrite Bead for GHz noise C1 C2 C3 C4 FB1 GND plane VCC line B1 C1, C4 C2, C6 C3 C5 C7 C8 C9 D1 FB1 R3 R4 U1 LISA-U2 series - System Integration Manual Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for USB power source (~500 mA). Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the L6924U starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor to ~15 mA or when the charging timer reaches the value configured by an external capacitor to ~9800 seconds. Using a battery pack with an internal NTC resistor, the L6924U can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. Alternatively the L6924U, providing input voltage range up to 12 V, can charge from an AC wall adapter. When a current-limited adapter is used, it can operate in quasi-pulse mode, reducing power dissipation. Figure 10: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Li-Ion (or Li-Polymer) battery pack with 470 NTC Part Number - Manufacturer Various manufacturer 1 F Capacitor Ceramic X7R 0603 10% 16 V GRM188R71C105KA12 - Murata 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata 1 nF Capacitor Ceramic X7R 0402 10% 50 V GRM155R71H102KA01 - Murata 330 F Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata Low Capacitance ESD Protection USB0002RP or USB0002DP - AVX Chip Ferrite Bead EMI Filter for GHz Band Noise 220 at 100 MHz, 260 at 1 GHz, 2000 mA BLM18EG221SN1 - Murata R1, R2 24 k Resistor 0402 5% 0.1 W RC0402JR-0724KL - Yageo Phycomp 3.3 k Resistor 0402 5% 0.1 W RC0402JR-073K3L - Yageo Phycomp 1.0 k Resistor 0402 5% 0.1 W RC0402JR-071K0L - Yageo Phycomp Single Cell Li-Ion (or Li-Polymer) Battery Charger IC for USB port and AC Adapter L6924U - STMicroelectronics Table 11: Suggested components for Li-Ion (or Li-Polymer) battery charging application circuit UBX-13001118 - R25 System description Page 27 of 182 5V0 USB Supply Li-Ion/Li-Polymer Battery Charger IC VIN VOUT VINSNS VOSNS MODE VREF C3 R4 C4 TH R1 R2 R3 ISEL IUSB IAC IEND TPRG U1 SD GND C1 C2 D1 LISA-U2 series FB1 61 VCC 62 VCC 63 VCC Li-Ion/Li-Pol Battery Pack B1

C5 C6 C7 C8 C9 GND LISA-U2 series - System Integration Manual 1.5.3 Current consumption profiles During operation, the current drawn by the LISA-U2 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in 2G connected mode, to a continuous high current drawn in UMTS connected mode, to the low current consumption during power saving in idle mode. 1.5.3.1 2G connected mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM 900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 s (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is in GSM connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than the one in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (see the LISA-U2 series Data Sheet [1]). During a GSM call, current consumption is in the order of 60-130 mA in receiving or in monitor bursts and is about 10-40 mA in the inactive unused bursts (low current period). The more relevant contribution to determine the average current consumption is set by the transmitted power in the transmit slot. An example of the current consumption profile of the data module in GSM talk mode is shown in Figure 11. Figure 11: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot) UBX-13001118 - R25 System description Page 28 of 182 Current [A]

2.5 2.0 1.5 1.0 0.5 0.0 Peak current depends on TX power and actual antenna load RX slot unused unused slot slot TX slot unused unused slot slot unused MON slot slot RX slot unused unused slot slot TX slot unused unused slot slot MON slot unused slot Time [ms]

GSM frame 4.615 ms

(1 frame = 8 slots) GSM frame 4.615 ms

(1 frame = 8 slots) LISA-U2 series - System Integration Manual When a GPRS connection is established, there is a different VCC current consumption profile also determined by the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but if following the GPRS specifications, the maximum transmitted RF power is reduced when more than one slot is used to transmit, so the maximum peak of current consumption is not as high as can be in the case of a GSM call. If the module transmits in GPRS class 12 connected mode in the GSM 850 or in the E-GSM 900 band at the maximum power control level, the current consumption can reach up to 1600 mA (with unmatched antenna). This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (see the LISA-U2 series Data Sheet [1]). Figure 12 reports the current consumption profiles in GPRS class 12 connected mode, in the GSM 850 or in the E-GSM 900 band, with 4 slots used to transmit and 1 slot used to receive. Figure 12: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot) In case of EDGE connections, the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 12, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well. UBX-13001118 - R25 System description Page 29 of 182 Current [A]

2.5 2.0 1.5 1.0 0.5 0.0 Peak current depends on TX power and actual antenna load RX slot unused slot TX slot TX slot TX slot TX slot MON slot slot unused RX slot unused slot TX slot TX slot TX slot TX slot MON slot slot unused Time [ms]

GSM frame 4.615 ms

(1 frame = 8 slots) GSM frame 4.615 ms

(1 frame = 8 slots) LISA-U2 series - System Integration Manual 1.5.3.2 3G connected mode During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 s, thus the rate of power change can reach a maximum rate of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case. In the worst case scenario, corresponding to a continuous transmission and reception at maximum output power

(approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the order of continuous 500-800 mA (see LISA-U2 series Data Sheet [1] for detailed values). Even at lowest output RF power (approximately 0.01 W or -50 dBm), the current still remains in the order of 200 mA due to module baseband processing and transceiver activity. An example of current consumption profile of the data module in UMTS/HSxPA continuous transmission mode is shown in Figure 13. Figure 13: VCC current consumption profile versus time during a UMTS/HSPA connection When a packet data connection is established, the actual current profile depends on the volume of transmitted packets; there might be some periods of inactivity between allocated slots where current consumption drops about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher quality signal required by the network to cope with the enhanced data speed. UBX-13001118 - R25 System description Page 30 of 182 Current [mA]

800 700 600 500 400 300 200 100 0 1 slot 666 s 850 mA 170 mA Current consumption depends on TX power and actual antenna load 3G frame 10 ms

(1 frame = 15 slots) Time

[ms]

LISA-U2 series - System Integration Manual 1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled) The power saving configuration is disabled by default, but it can be enabled using the appropriate AT command (see the u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module automatically enters idle mode whenever possible. When power saving is enabled, the module is registered or attached to a network and a voice or data call is not enabled, the module automatically enters idle mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance with GSM system requirements. When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging block. In between, the module switches to idle mode. This is known as GSM discontinuous reception (DRX). The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active mode. The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell. For a 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX

= 2, i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX =

9, i.e. width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms). For a 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of 26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms = 5120 ms). An example of a modules current consumption profile is shown in Figure 14: the module is registered with the network (2G or 3G), automatically enters idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception. Figure 14: Description of VCC current consumption profile versus time when the module is registered with 2G or 3G networks:

the module is in idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception UBX-13001118 - R25 System description Page 31 of 182 Current [mA]

100 50 0 100 50 0 Current [mA]

IDLE MODE 2G case: 0.44-2.09 s 3G case: 0.61-5.09 s ACTIVE MODE 20-30 ms Time

[s]

Active Mode Enabled RX DSP Enabled Enabled Idle Mode Enabled Time

[ms]

IDLE MODE 20-30 ms ACTIVE MODE IDLE MODE LISA-U2 series - System Integration Manual 1.5.3.4 2G and 3G fixed active mode (power saving disabled) Power saving configuration is disabled by default, or it can be disabled using the appropriate AT command (see the u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle mode whenever possible: the module remains in active mode. The module processor core is activated during active mode, and the 26 MHz reference clock frequency is used. An example of the current consumption profile of the data module when power saving is disabled is shown in Figure 15: the module is registered with the network, active mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception. Figure 15: Description of the VCC current consumption profile versus time when power saving is disabled: the active mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception UBX-13001118 - R25 System description Page 32 of 182 Current [mA]

100 50 0 100 50 0 Current [mA]

Paging period 2G case: 0.47-2.12 s 3G case: 0.64-5.12 s Time

[s]

Time [ms]

RX DSP Enabled Enabled ACTIVE MODE LISA-U2 series - System Integration Manual 1.5.4 RTC Supply (V_BCKP) The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power-On / Reset internal logic. This supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The output of this linear regulator is always enabled when the main voltage supply provided to the module through VCC is within the valid operating range, with the module switched-off or powered-on. V_BCKP supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name Description Remarks V_BCKP Real Time Clock supply V_BCKP output voltage = 1.8 V (typical) Generated by the module to supply Real Time Clock when VCC supply voltage is within valid operating range. Table 12: Real Time Clock supply pin The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the line is externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. The RTC provides the time reference (date and time) of the module, also in power-off mode, when the V_BCKP voltage is within its valid range (specified in the input characteristics of the supply/power pins table in the LISA-U2 series Data Sheet [1]). The RTC timing is normally used to set the wake-up interval during idle mode periods between network paging, but is able to provide programmable alarm functions by means of the internal 32.768 kHz clock. The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. The RTC oscillator does not necessarily stop operation (i.e. the RTC counting does not necessarily stop) when the V_BCKP voltage value drops below the specified operating range minimum limit (1 V):

the RTC value read after a system restart might be not reliable, as explained in Table 13. V_BCKP voltage value RTC value reliability Notes 1.00 V < V_BCKP < 1.90 V 0.05 V < V_BCKP < 1.00 V 0.00 V < V_BCKP < 0.05 V RTC oscillator does not stop operation RTC value read after a restart of the system is reliable V_BCKP within operating range RTC oscillator does not necessarily stop operation RTC value read after a restart of the system is not reliable V_BCKP below operating range RTC oscillator stops operation RTC value read after a restart of the system is reliable V_BCKP below operating range Table 13: RTC value reliability as function of V_BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch-on the module). UBX-13001118 - R25 System description Page 33 of 182 LISA-U2 series - System Integration Manual The RTC has very low power consumption, but is highly temperature dependent. For example at

+25 C, with the V_BCKP voltage equal to the typical output value, the power consumption is approximately 2 A (see the input characteristics of supply/power pins table in the LISA-U2 series Data Sheet [1] for the detailed specification), whereas at +70 C and an equal voltage, the power consumption increases to 5-10 A. The internal regulator for V_BCKP is optimized for low leakage current and very light loads. It is not recommended to use V_BCKP to supply external loads. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within a few milliseconds, the voltage on V_BCKP will drop below the valid range (1 V minimum). This has no impact on cellular connectivity, as none of the functionalities of the module rely on the date and time settings. Leave V_BCKP unconnected if the RTC is not required when the VCC supply is removed. The date and time will not be updated when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP. If RTC is required to run for a time interval of T [s] at +25 C when VCC supply is removed, place a capacitor with a nominal capacitance of C [ F] at the V_BCKP pin. Choose the capacitor using the following formula:

C [ F] = (Current_Consumption [ A] x T [s]) / Voltage_Drop [V]

= 2.50 x T [s] for LISA-U2 series For example, a 100 F capacitor (such as the Murata GRM43SR60J107M) can be placed at V_BCKP to provide a long buffering time. This capacitor will hold V_BCKP voltage within its valid range for around 50 s at +25 C, after the VCC supply is removed. If a very long buffering time is required, a 70 mF super-capacitor (e.g. Seiko Instruments XH414H-IV01E) can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage within its valid range for approximately 10 hours at +25 C, after the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors will allow the time reference to run during battery disconnection. Figure 16: Real time clock supply (V_BCKP) application circuits: (a) using a 100 F capacitor to let the RTC run for ~50 s after VCC removal; (b) using a 70 mF capacitor to let RTC run for ~10 hours after VCC removal; (c) using a non-rechargeable battery Reference Description Part Number - Manufacturer C1 R2 C2 100 F Tantalum Capacitor GRM43SR60J107M - Murata 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp 70 mF Capacitor XH414H-IV01E - Seiko Instruments Table 14: Example of components for V_BCKP buffering UBX-13001118 - R25 System description Page 34 of 182

(a) LISA-U2 series

(b) LISA-U2 series

(c) LISA-U2 series 2 V_BCKP 2 V_BCKP 2 V_BCKP C1 R2 C2

(superCap) D3 B3 LISA-U2 series - System Integration Manual If longer buffering time is required to allow the time reference to run during a disconnection of the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP

(specified in the input characteristics of the supply/power pins table in the LISA-U2 series Data Sheet [1]). The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to the non-rechargeable battery. Combining a LISA-U2 series cellular module with a u-blox GNSS receiver, the VCC supply of the GNSS receiver is controlled by the cellular module by means of the GNSS supply enable function provided by the GPIO2 of the cellular module. In this case the V_BCKP supply output of the LISA-U2 series cellular module can be connected to the V_BCKP backup supply input pin of the GNSS receiver to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start

(depending on the duration of the GNSS VCC outage) and to maintain the configuration settings saved in the backup RAM. See the section 1.10 for more details regarding the application circuit with a u-blox GNSS receiver. UBX-13001118 - R25 System description Page 35 of 182 LISA-U2 series - System Integration Manual 1.5.5 Interface supply (V_INT) The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin. The internal regulator that generates the V_INT supply is a switching step down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and is disabled when the module is switched off or when the RESET_N pin is forced the low level. The switching regulator operates in Pulse Width Modulation (PWM) for high output current mode but automatically switches to Pulse Frequency Modulation (PFM) at low output loads for greater efficiency, e.g. when the module is in idle mode between paging periods. V_INT supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name V_INT Description Remarks Digital Interfaces supply output V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. V_INT is the internal supply for digital interfaces. The user may draw limited current from this supply rail. Table 15: Interface supply pin The V_INT pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the line is externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to the accessible point. Since it supplies internal digital circuits (see Figure 3), V_INT is not suited to directly supply any sensitive analog circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to 70 mVpp in idle mode (PFM). V_INT can be used to supply external digital circuits operating at the same voltage level as the digital interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without adequate filtering for digital noise. Do not apply loads which might exceed the limit for the maximum available current from the V_INT supply, as this can cause malfunctions in internal circuitry supplies to the same domain. The detailed electrical characteristics are described in the LISA-U2 series Data Sheet [1]. V_INT can only be used as an output; do not connect any external regulator on V_INT. If not used, this pin should be left unconnected. The V_INT digital interfaces supply output is mainly used to:

Pull-up DDC (I2C) interface signals (see section 1.10.2 for more details) Pull-up SIM detection signal (see section 1.8 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see sections 1.9.2.4, 1.9.4.4 for more details) Supply a 1.8 V u-blox 6 or subsequent GNSS receiver (see section 1.10.2 for more details) Indicate when the module is switched on and the RESET_N external hardware reset input is not forced low (see sections 1.6.1.5, 1.6.2 and 1.6.3 for more details) UBX-13001118 - R25 System description Page 36 of 182 LISA-U2 series - System Integration Manual 1.6 System functions 1.6.1 Module power-on When the LISA-U2 series modules are in the not-powered mode (i.e. switched off with the VCC module supply not applied), they can be switched on by:

Rising edge on the VCC pin to a valid voltage as the module supply (i.e. applying module supply) Alternately, the RESET_N pin can be held to the low level during the VCC rising edge, so that the module switches on, releasing the RESET_N pin when the VCC module supply voltage stabilizes at its correct nominal value within the normal operating range The status of the PWR_ON input pin of LISA-U2 series modules while applying the VCC module supply is not relevant: during this phase, the PWR_ON pin can be set high or low by the external circuit. When the LISA-U2 series modules are in the power-off mode (i.e. switched off by means of the AT+CPWROFF command, with valid VCC module supply applied), they can be switched on by:

Low pulse on the PWR_ON pin (i.e. forcing the pin to the low level, normally high by external pull-

Rising edge on the RESET_N pin (i.e. releasing the pin from low level, normally high by internal pull-

up) up) RTC alarm (i.e. pre-programmed scheduled time by AT+CALA command) Name Description Remarks PWR_ON Power-on input Table 16: Power-on pin PWR_ON pin has high input impedance. Do not keep floating in noisy environment: external pull-

up required. The PWR_ON pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the line is externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to the accessible point. 1.6.1.1 Rising edge on VCC Applying a proper supply to VCC pins, the module supply supervision circuit controls the subsequent activation of the power-up state machines: the module is switched on when the voltage rises up to the VCC normal operating range minimum limit starting from a voltage value lower than 2.25 V (see the LISA-U2 series Data Sheet [1] for the VCC normal operating range minimum limit). The voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to properly switch on the module. If the external supply circuit is not able to provide this VCC voltage slope, keep the RESET_N input low during the VCC rising edge, so that the module switches on, releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal operating range. The status of the PWR_ON input pin during the VCC apply phase is not relevant: LISA-U2 modules switch on when a suitable rising edge on the VCC pin is applied, during this phase the PWR_ON pin can be set high or low by the external circuit. UBX-13001118 - R25 System description Page 37 of 182 LISA-U2 series - System Integration Manual 1.6.1.2 Low pulse on PWR_ON When the module is in power-off mode, i.e. it has been cleanly switched off as described in the section 1.6.2 (e.g. by the AT+CPWROFF command) and a voltage within the operating range is maintained at the VCC pins, the module can be switched on by means of the PWR_ON input pin: a falling edge must be provided on the PWR_ON pin, which must be then held low for an appropriate time period as specified in the LISA-U2 series Data Sheet [1]. The electrical characteristics of the PWR_ON input pin are different from the other digital I/O interfaces; the detailed electrical characteristics are described in the LISA-U2 series Data Sheet [1]. The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module. Avoid keeping it floating in a noisy environment. To hold the high logic level stable, the PWR_ON pin must be connected to a pull-up resistor (e.g. 100 k) biased by the V_BCKP supply pin of the module. Following are some typical examples of application circuits to turn the module on using the PWR_ON input pin. Connecting the PWR_ON input to an external device (e.g. application processor), use an open drain output on the external device with an external pull-up resistor (e.g. 100 k) biased by V_BCKP supply pin of the module. A push-pull output of an application processor can also be used: in this case the pull-up can be used to pull the PWR_ON level high when the application processor is switched off. If the high-level voltage of the push-pull output pin of the application processor is greater than the maximum input voltage operating range of the V_BCKP pin (see the V_BCKP input characteristics of the supply/power pins table in the LISA-U2 series Data Sheet [1]), the V_BCKP supply cannot be used to bias the pull-up resistor: the supply rail of the application processor or the VCC supply could be used, but this will increase the V_BCKP (RTC supply) current consumption when the module is in not-powered mode

(VCC supply not present). Using a push-pull output of the external device, take care to fix the proper level in all the possible scenarios to avoid an inappropriate switch-on of the module. Figure 17: PWR_ON application circuits using an open drain output of an application processor Reference Description Remarks Rext 100 k Resistor 0402 5% 0.1 W External pull-up resistor Table 17: Example of pull-up resistor for the PWR_ON application circuit UBX-13001118 - R25 System description Page 38 of 182 Application processor Open Drain Output LISA-U2 series 2 V_BCKP Rext 19 PWR_ON LISA-U2 series - System Integration Manual 1.6.1.3 Rising edge on RESET_N When the module is in power-off mode (i.e. switched off with VCC maintained), the module can be switched on by means of the RESET_N input pin alternatively to the PWR_ON input pin: the RESET_N signal must be forced low for at least 50 ms and then released to generate a rising edge that starts the module power-on sequence. RESET_N input pin can also be used to perform an external or hardware reset of the module, as described in section 1.6.3. Electrical characteristics of the LISA-U2 series RESET_N input are slightly different from the other digital I/O interfaces: the pin provides different input voltage thresholds. Detailed electrical characteristics are described in the LISA-U2 series Data Sheet [1]. RESET_N is pulled high to V_BCKP by an integrated pull-up resistor also when the module is in power-

off mode. Therefore an external pull-up is not required on the application board. The simplest way to switch on the module by means of the RESET_N input pin is to use a push button that shorts the RESET_N pin to ground: the module will be switched on at the release of the push button, since the RESET_N will be forced to the high level by the integrated pull-up resistor, generating a rising edge. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case, make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in the LISA-U2 series Data Sheet [1]). To avoid an unwanted power-on or reset of the module, make sure to fix the proper level at the RESET_N input pin in all possible scenarios. Some typical examples of application circuits using the RESET_N input pin are described in section 1.6.3. 1.6.1.4 Real Time Clock (RTC) alarm When the module is in power-off mode (i.e. switched off with VCC maintained), it can be switched on by means of a previously programmed RTC alarm (see the u-blox AT Commands Manual [2], AT+CALA command) alternatively to the PWR_ON and RESET_N pins: the RTC system will initiate the power-

on sequence. 1.6.1.5 Additional considerations The module is switched on when the VCC voltage rises up to the normal operating range (i.e. applying supply properly, as described in section 1.6.1.1): the module is commonly switched on in this way for the first time. Then, the module must be properly switched off as described in section 1.6.2, e.g. by the AT+CPWROFF command. When the module is in power-off mode, i.e. it has been properly switched off as described in the section 1.6.2 (e.g. by the AT+CPWROFF command) and a voltage within the operating range is maintained at the VCC pins, the module can be switched on by a proper start-up event (i.e. by PWR_ON as described in Figure 18 and section 1.6.1.2, or by RESET_N as described in section 1.6.1.3, or by RTC alarm as described in section 1.6.1.4). UBX-13001118 - R25 System description Page 39 of 182 LISA-U2 series - System Integration Manual Figure 18 shows the modules power-on sequence from power-off mode, with the following phases:

The external supply is still applied to the VCC inputs as it is assumed that the module has been previously switched off by means of the AT+CPWROFF command: the V_BCKP output is internally enabled as suitable VCC is present, the RESET_N is set to high logic level due to internal pull-up to V_BCKP, the PWR_ON is set to high logic level due to an external pull-up. The PWR_ON input pin is set low for a valid time period, representing the start-up event. All the generic digital pins of the modules are tri-stated until the switch-on of their supply source

(V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a complete boot of the module. The V_INT generic digital interfaces supply output is enabled by the integrated PMU. The internal reset signal is held low by the integrated power management unit: the baseband processor core and all the digital pins of the modules are held in reset state, which is reported for each pin of the module in the pin description table of the LISA-U2 series Data Sheet [1]. When the internal reset signal is released by the integrated power management unit, the processor core starts to configure the digital pins of the modules to each default operational state. The duration of these pins configuration phase differs within generic digital interfaces (3 s typical) and USB interface due to specific enumeration timings (5 s typical, see section 1.9.3.1). The host application processor should not send any AT command over the modules AT interfaces (USB, UART) until the end of this interfaces configuration phase to allow a complete boot of the module. After the interfaces configuration phase, the application can start sending AT commands, and the following starting procedure is suggested to check the effective completion of the module internal boot sequence: send AT and wait for the response with a 30 second timeout, iterate it 4 times without resetting or removing the VCC supply of the module, and then run the application. Figure 18: LISA-U2 series power-on sequence description The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the start of the power-on sequence. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when the external reset is forced low, and during the power-on sequence. UBX-13001118 - R25 System description Page 40 of 182 Start-up PWR_ON event can be set high Start of interface configuration Generic digital interfaces are configured VCC V_BCKP PWR_ON V_INT Internal Reset System State OFF ON BB Pads State Tristate / Floating Internal Reset Internal Reset Operational Operational 0 ms

~35 ms

~3 s LISA-U2 series - System Integration Manual 1.6.2 Module power-off The power-off sequence of LISA-U2 series modules can be correctly started, so that the current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed, in one of these ways:

AT+CPWROFF command (more details in the u-blox AT Commands Manual [2]) Low pulse on the PWR_ON pin for at least 1 second An over-temperature or an under-temperature shutdown occurs when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details, see the section 3.16 and the u-blox AT Commands Manual [2], +USTS AT command. An abrupt under-voltage shutdown occurs on LISA-U2 modules when the VCC supply is removed, but in this case the current parameter settings are not saved in the modules non-volatile memory and a proper network detach cannot be performed. It is highly recommended to avoid an abrupt removal of the VCC supply: the power-off sequence of the module must be properly started as described above (e.g. by means of the AT+CPWROFF command), and a clean VCC supply must be maintained at least until the end of the power-off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module. An abrupt hardware shutdown occurs on LISA-U2 series modules when a low level is applied to the RESET_N pin. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if a reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2]. UBX-13001118 - R25 System description Page 41 of 182 LISA-U2 series - System Integration Manual Figure 19 describes the modules power-off sequence, properly started by sending the AT+CPWROFF command, allowing storage of current parameter settings in the modules non-volatile memory and a proper network detach:

When the +CPWROFF AT command is sent, the module starts the switch-off routine. The module replies OK on the AT interface: the switch-off routine is in progress. At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC supply (V_BCKP). Then, the module remains in power-off mode as long as a switch-on event does not occur (e.g. applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N input), and enters not-powered mode if the supply is removed from the VCC pins. Figure 19: LISA-U2 series Power-off sequence description The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the end of the LISA-U2 series power-off sequence. The duration of each phase in the LISA-U2 series modules switch-off routines can largely vary from the values reported in Figure 19 (e.g. from tens of milliseconds up to tens of seconds), depending on the application / network settings and the concurrent module activities. If the AT command +CPWROFF is issued to switch off the module over a multiplexer channel, the completion of the module power-off sequence could require additionally up to 2.5 seconds after the module OK reply. Therefore, if the Application Processor (AP) controls the VCC supply of the module, the AP should disable the multiplexer protocol and then issue the AT+CPWROFF command over the used AT interface, or otherwise the AP should issue the AT+CPWROFF command over a multiplexer channel and wait additionally 2.5 seconds after OK reception before removing the module VCC supply. Tri-stated pins are always subject to floating caused by noise: to prevent unwanted effects, fix them with suitable pull-up or pull down resistors to stable voltage rails to fix their level when the module is in power-down state. Any external signal connected to the UART, SPI/IPC, I2S and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-

on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-

stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two circuit connections and set to high impedance during module power-down mode, when the external reset is forced low and during the power-on sequence. UBX-13001118 - R25 System description Page 42 of 182 AT+CPWROFF OK VCC sent to the module replied by the module can be removed VCC V_BCKP PWR_ON RESET_N V_INT Internal Reset System State ON OFF BB Pins State Operational Operational Tristate Tristate / Floating 0 s

~50 ms

~400 ms LISA-U2 series - System Integration Manual 1.6.3 Module reset LISA-U2 series modules can be properly reset (rebooted) by:

AT+CFUN command (see the u-blox AT Commands Manual [2] for more details). This command causes an internal or software reset of the module, causing an asynchronous reset of the module baseband processor, excluding the integrated Power Management Unit and the RTC internal block. The V_INT interfaces supply is enabled and each digital pin is set to its internal reset state (detailed in the pin description table in the LISA-U2 series Data Sheet [1]), the V_BCKP supply and the RTC block are enabled. Forcing an internal or software reset, the current parameter settings are saved in the modules non-volatile memory and a clean network detach is performed: this is the proper way to reset the modules. An abrupt hardware reset occurs on LISA-U2 series modules when a low level is applied on the RESET_N input pin for a specific time period. In this case, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. It is highly recommended to avoid an abrupt external or hardware reset of the module by forcing a low level on the RESET_N input pin during the module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2]. When a low level is applied to the RESET_N input, it causes an external or hardware reset of the module, with an asynchronous abrupt reset of the entire module, including the integrated Power Management Unit, except for the RTC internal block. The V_INT interfaces supply is switched off and all the digital pins of the modules are tri-stated, but the V_BCKP supply and the RTC block are enabled. Forcing an external or hardware reset, the current parameter settings are not saved in the modules non-volatile memory and a clean network detach is not performed. When RESET_N is released from the low level, the module automatically starts its power-on sequence from the reset state. The same procedure is followed for the module reset via AT command after having performed the network detach and the parameter saving in non-volatile memory. Name Description Remarks RESET_N External reset input Internal 10 k pull-up to V_BCKP Table 18: Reset pin The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the line is externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to the accessible point. For more details about RESET_N circuit precautions for ESD immunity, see section 2.5.3. The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical characteristics are described in the LISA-U2 series Data Sheet [1]. RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-

up is not required on the application board. Following are some typical examples of application circuits using the RESET_N input pin. The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground. UBX-13001118 - R25 System description Page 43 of 182 LISA-U2 series - System Integration Manual If RESET_N is connected to an external device (e.g. an application processor on an application board), an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case, make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in the LISA-U2 series Data Sheet [1]). To avoid unwanted resets of the module, make sure to fix the proper level at the RESET_N input pin in all possible scenarios. As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01), a proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) and a 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board (for more details, see section 2.5.3). Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD C1, C3 C2, C4 EMI1, EMI2 Varistor for ESD protection. CT0402S14AHSG - EPCOS 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata 220 nF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J224KE01 - Murata Chip Ferrite Bead Noise/EMI Suppression Filter 1800 at 100 MHz, 2700 at 1 GHz BLM15HD182SN1 - Murata Rint 10 k Resistor 0402 5% 0.1 W Internal pull-up resistor Table 19: Example of ESD protection components for the RESET_N application circuit Any external signal connected to the UART, SPI/IPC, I2S and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-

on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a clean boot of the module. If the external signals connected to the cellular module cannot be tri-

stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power-down mode, when external reset is forced low and during the power-on sequence. UBX-13001118 - R25 System description Page 44 of 182 LISA-U2 series 2 V_BCKP Rint 22 RESET_N LISA-U2 series 2 V_BCKP Rint 22 RESET_N Reset push button EMI1 ESD C1 C2 Application processor Open Drain Output EMI2 C3 C4 LISA-U2 series - System Integration Manual 1.7 RF connection The ANT pin, provided by all LISA-U2 modules, represents the main RF input/output used to transmit and receive the 2G and 3G RF signal: the main antenna must be connected to this pad. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the antenna through a 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. The ANT_DIV pin, provided by LISA-U230 modules, represents the RF input for the integrated diversity receiver implemented for both 2G and 3G cases: the antenna for the Rx diversity must be connected to this pad. The ANT_DIV pin has a nominal characteristic impedance of 50 and must be connected to the antenna for the Rx diversity through a 50 transmission line to allow reception of radio frequency (RF) signals, improving the cellular link quality and reliability on all 2G and 3G operating bands except the 2G DCS 1800. Module Description Remarks All RF input/output for main Tx/Rx antenna Zo = 50 nominal characteristic impedance. ANT_DIV LISA-U230 RF input for Rx diversity antenna Zo = 50 nominal characteristic impedance. Name ANT Table 20: Antenna pins The ESD immunity rating of the ANT port is 1000 V (according to IEC 61000-4-2). Higher protection level could be required if the line is externally accessible on the application board (for further details, see section 2.5.3). Choose an antenna with optimal radiating characteristics for the best electrical performance and overall module functionality. An internal antenna, integrated on the application board, or an external antenna, connected to the application board through a suitable 50 connector, can be used. See section 2.4 and section 2.2.1.1 for further details regarding antenna guidelines. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. If an external antenna is used, the PCB-to-RF-cable transition must be implemented using either a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 characteristic impedance. If antenna supervisor functionality is required, the main antenna connected to the ANT pin should have a built-in DC diagnostic resistor to ground to achieve reliable detection functionality (see section 2.4.4). Connect the Rx diversity antenna to the ANT_DIV pin of LISA-U230 modules, unless the 2G and 3G Rx diversity feature is disabled by the AT command (see the u-blox AT Commands Manual [2],

+URXDIV command). The same pin (74) is marked RSVD (reserved) on the other modules that do not implement Rx diversity: in this case the RSVD pin can be left unconnected. UBX-13001118 - R25 System description Page 45 of 182 LISA-U2 series - System Integration Manual 1.8

(U)SIM interface The high-speed SIM/ME interface is implemented as well as automatic detection of the required SIM supporting voltage. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with an automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud rate selection, according to the values determined by the SIM card. The VSIM supply output pin provides internal short circuit protection to limit the start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name VSIM SIM_CLK SIM_IO SIM_RST Description SIM supply SIM clock SIM data SIM reset Table 21: SIM interface pins Remarks 1.80 V typical or 2.90 V typical Automatically generated by the module 3.25 MHz clock frequency Open drain, internal 4.7 k pull-up resistor to VSIM A low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002RP) must be placed near the SIM card holder on each line (VSIM, SIM_IO, SIM_CLK, SIM_RST). The SIM interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F): higher protection level is required if the lines are connected to an SIM card connector, since they are externally accessible on the application board. For more details about ESD immunity precautions for SIM interface pins, see section 2.5.3. The following SIM services are supported:

Abbreviated Dialing Numbers (ADN) Fixed Dialing Numbers (FDN) Last Dialed Numbers (LDN) Service Dialing Numbers (SDN) The SIM Application Toolkit and USIM Application Toolkit (USAT) are supported. The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 1.8.1.4 and 1.8.1.5:

Low logic level at GPIO5 input pin is recognized as SIM card not present High logic level at GPIO5 input pin is recognized as SIM card present The SIM card detection function provided by GPIO5 pin is an optional feature that can be implemented

/ used or not according to the application requirements. An Unsolicited Result Code (URC) can be generated each time that there is a change of status (for more details, see the simind value of the

<descr> parameter of +CIND and +CMER commands in the u-blox AT Commands Manual [2]). All the LISA-U2 series modules provide the additional function SIM card hot insertion/removal on the GPIO5 pin, which can be enabled using the AT+UDCONF=50 command. For more details on SIM detection function, see section 1.12 as well as the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 commands. UBX-13001118 - R25 System description Page 46 of 182 LISA-U2 series - System Integration Manual 1.8.1

(U)SIM application circuits 1.8.1.1 SIM cards, SIM connectors and SIM chips selection The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical and functional characteristics of Universal Integrated Circuit Cards (UICC) which contain the Subscriber Identification Module (SIM) integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the GSM network. Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221as follows:

Contact C1 = VCC (Supply) Contact C2 = RST (Reset) Contact C3 = CLK (Clock) Contact C4 = AUX1 (Auxiliary contact) Contact C5 = GND (Ground) Contact C6 = VPP (Programming supply) Contact C7 = I/O (Data input/output) Contact C8 = AUX2 (Auxiliary contact) Must be connected to VSIM Must be connected to SIM_RST Must be connected to SIM_CLK Must be left not connected Must be connected to GND It can be left not connected Must be connected to SIM_IO Must be left not connected A removable SIM card can have 6 contacts (C1 = VCC, C2 = RST, C3 = CLK, C5 = GND, C6 = VPP, C7 =

I/O) or 8 contacts, providing also the auxiliary contacts C4 = AUX1 and C8 = AUX2 for USB interfaces and other uses. Only 6 contacts are required and must be connected to the module SIM card interface as described above, since LISA-U2 modules do not support the additional auxiliary features (contacts C4 = AUX1 and C8 = AUX2). Removable SIM cards are suitable for applications where SIM changing is required during the product lifetime. A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins corresponding to the normally-open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided:

select a SIM connector providing 6+2 or 8+2 positions if the optional SIM detection feature is required by the custom application, otherwise a connector without an integrated mechanical presence switch can be selected. Solderable UICC / SIM chip contacts mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as follows:

Package Pin 8 = UICC Contact C1 = VCC (Supply) Package Pin 7 = UICC Contact C2 = RST (Reset) Package Pin 6 = UICC Contact C3 = CLK (Clock) Package Pin 5 = UICC Contact C4 = AUX1 (Auxiliary contact) Must be left not connected Must be connected to GND Package Pin 1 = UICC Contact C5 = GND (Ground) Package Pin 2 = UICC Contact C6 = VPP (Programming supply) It can be left not connected Package Pin 3 = UICC Contact C7 = I/O (Data input/output) It must be connected to SIM_IO Package Pin 4 = UICC Contact C8 = AUX2 (Auxiliary contact) It must be left not connected Must be connected to VSIM Must be connected to SIM_RST Must be connected to SIM_CLK A solderable SIM chip has 8 contacts and can also provide the auxiliary contacts C4 = AUX1 and C8 =

AUX2 for USB interfaces and other uses, but only 6 contacts are required and need to be connected to the module SIM card interface as described above, since LISA-U2 modules do not support the additional auxiliary features (contacts C4 = AUX1 and C8 = AUX2). Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed. UBX-13001118 - R25 System description Page 47 of 182 LISA-U2 series - System Integration Manual 1.8.1.2 Single SIM card without detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of LISA-U2 modules as described in Figure 21, where the optional SIM detection feature is not implemented (see the circuit described in Figure 23 if the SIM detection feature is required). Follow these guidelines connecting the module to a SIM connector without the SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module Connect the UICC / SIM contact C5 (GND) to ground Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the corresponding pad of the SIM connector, to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H330J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each specific pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each specific pad of the SIM connector: the ESD sensitivity rating of the SIM interface pins is 1 kV (Human Body Model according to JESD22-A114), so that, according to the EMC/ESD requirements of the custom application, higher protection levels can be required if the lines are externally accessible on the application device Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines) Figure 21: Application circuit for the connection to a single removable SIM card, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 33 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H330JZ01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1, D2, D3, D4 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics SIM Card Holder 6 positions, without card presence switch Various Manufacturers, C707 10M006 136 2 - Amphenol C5 J1 Table 22: Example of components for the connection to a single removable SIM card, with SIM detection not implemented UBX-13001118 - R25 System description Page 48 of 182 LISA-U2 series V_INT 4 GPIO5 51 VSIM 50 SIM_IO 48 SIM_CLK 47 SIM_RST 49 SIM CARD HOLDER VPP (C6) VCC (C1) IO (C7) CLK (C3) RST (C2) GND (C5) J1 C 5 C 1 C 6 C 2 C 7 C 3 C 8 C 4 SIM Card Bottom View

(contacts side) C1 C2 C3 C4 C5 D1 D2 D3 D4 C5 U1 LISA-U2 series - System Integration Manual 1.8.1.3 Single SIM chip A solderable SIM chip (M2M UICC form factor) must be connected the SIM card interface of LISA-U2 modules as described in Figure 22 when the optional SIM detection feature is not implemented (see the circuit described in Figure 23 if the SIM detection feature is required). Follow these guidelines connecting the module to a solderable SIM chip without SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module Connect the UICC / SIM contact C5 (GND) to ground Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM) close to the specific pad of the SIM chip, to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H330J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines) Figure 22: Application circuit for the connection to a single solderable SIM chip, with SIM detection not implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 33 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H330JZ01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata SIM chip (M2M UICC Form Factor) Various Manufacturers Table 23: Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented 1.8.1.4 Single SIM card with detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of LISA-U2 modules as described in Figure 23 when the optional SIM card detection feature is implemented so that the module detects if a SIM card is present in the connector by means of the GPIO5 signal. The SW1 and SW2 pins of the SIM card holder are connected to a normally-open mechanical switch integrated in the SIM connector. The following cases are available:

SIM card not present: the GPIO5 signal is forced low by the pull-down resistor connected to ground

(i.e. the switch integrated in the SIM connector is open) SIM card present: the GPIO5 signal is forced high by the pull-up resistor connected to V_INT (i.e. the switch integrated in the SIM connector is closed) UBX-13001118 - R25 System description Page 49 of 182 LISA-U2 series V_INT 4 GPIO5 51 VSIM 50 SIM_IO 48 SIM_CLK 47 SIM_RST 49 SIM CHIP VPP (C6) VCC (C1) IO (C7) CLK (C3) 2 8 3 6 7 1 U1 8 7 6 5 C1 C2 C3 C4 C5 C6 C7 C8 1 2 3 4 RST (C2) SIM Chip GND (C5) Bottom View

(contacts side) C1 C2 C3 C4 C5 LISA-U2 series - System Integration Manual Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection:

Connect the UICC / SIM contacts C1 (VCC) to the VSIM pin of the module Connect the UICC / SIM contact C7 (I/O) to the SIM_IO pin of the module Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK pin of the module Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module Connect the UICC / SIM contact C5 (GND) to ground Connect one pin of the mechanical switch integrated in the SIM connector (e.g. the SW2 pin as described in Figure 23) to the GPIO5 input pin of the module Connect the other pin of the mechanical switch integrated in the SIM connector (e.g. the SW1 pin as described in Figure 23) to the V_INT 1.8 V supply output of the module by means of a strong

(e.g. 1 k) pull-up resistor, as the R1 resistor in Figure 23 Provide a weak (e.g. 470 k) pull-down resistor at the SIM detection line, as the R2 resistor in Figure 23 Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the specific pad of the SIM connector, to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H330J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each specific pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holder Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each specific pad of the SIM connector: ESD sensitivity rating of the SIM interface pins is 1 kV (HBM as per JESD22-A114), so that, according to the EMC/ESD requirements of the custom application, higher protection levels can be required if the lines are externally accessible on the application device Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines) Figure 23: Application circuit for connection to a single removable SIM card, with SIM detection implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 33 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H330JZ01 - Murata 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 1 k Resistor 0402 5% 0.1 W RC0402JR-071KL - Yageo Phycomp 470 k Resistor 0402 5% 0.1 W RC0402JR-07470KL- Yageo Phycomp SIM Card Holder 6 + 2 positions, with card presence switch Various Manufacturers, CCM03-3013LFT R102 - C&K Components Table 24: Example of components for connection to a single removable SIM card, with SIM detection implemented D1, D2, D3, D4, D5, D6 C5 R1 R2 J1 UBX-13001118 - R25 System description Page 50 of 182 LISA-U2 series V_INT 4 GPIO5 51 VSIM 50 SIM_IO 48 SIM_CLK 47 SIM_RST 49 R1 R2 SIM CARD HOLDER SW1 SW2 VPP (C6) VCC (C1) IO (C7) CLK (C3) RST (C2) GND (C5) J1 C 5 C 1 C 6 C 2 C 7 C 3 C 8 C 4 SIM Card Bottom View

(contacts side) C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 D6 LISA-U2 series - System Integration Manual 1.8.1.5 Dual SIM card connection Two SIM cards / chips can be connected to the modules SIM interface, as described in the circuit of Figure 24. LISA-U2 modules do not support the usage of two SIMs at the same time, but two SIMs can be populated on an application board that provides a suitable switch to connect only the first SIM or only the second SIM per time to the SIM interface of the modules as described in Figure 24. All LISA-U2 series modules support SIM hot insertion / removal on the GPIO5 pin: if the feature is enabled using the specific AT commands, the switch from first SIM to the second SIM can be cleanly done when a Low logic level is present on the GPIO5 pin (SIM not inserted = SIM interface not enabled), without the necessity of a module re-boot, so that the SIM interface will be re-enabled by the module to use the second SIM when a High logic level will be re-applied on the GPIO5 pin. (For more details, see section 1.12 and the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 commands.) In the application circuit represented in Figure 24, the application processor will drive the SIM switch using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be used to handle the SIM hot insertion / removal function of LISA-U2 series modules, which can also be handled by other external circuits or by the cellular module GPIO according to the application requirements. The dual SIM connection circuit described in Figure 24 can be implemented for SIM chips as well, providing proper connection between SIM switch and SIM chip as described in Figure 22. If it is required to switch between more than two SIMs, a circuit similar to the one described in Figure 24 can be implemented: for example, in case of four SIM circuits, using a suitable 4-pole 4-throw switch (or, alternatively, four 1-pole 4-throw switches) instead of the suggested 4-pole 2-throw switch. Follow these guidelines connecting the module to two SIM connectors:

Use a suitable low-on resistance (i.e. few ohms) and low-on capacitance (i.e. few pF) 2-throw analog switch (e.g. Fairchild FSA2567) as SIM switch to ensure high-speed data transfer according to the SIM requirements. Connect the contacts C1 (VCC) of the two UICC / SIM to the VSIM pin of the module by means of a suitable 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO pin of the module by means of a suitable 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK pin of the module by means of a suitable 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST pin of the module by means of a suitable 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C5 (GND) of the two UICC / SIM to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related pad of the two SIM connectors, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the two SIM connectors, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holders. Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each related pad of the two SIM connectors, according to the EMC/ESD requirements of the custom application. Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 s is the maximum allowed rise time on the SIM_IO and SIM_RST lines). UBX-13001118 - R25 System description Page 51 of 182 LISA-U2 series - System Integration Manual Figure 24: Application circuit for connection to two removable SIM cards, with SIM detection implemented Reference Description Part Number - Manufacturer C1 C4, C6 C9 33 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1H330JZ01 - Murata C5, C10, C11 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata D1 D8 R1 J1, J2 U1 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL- Yageo Phycomp SIM Card Holder 6 positions, without card presence switch Various Manufacturers, C707 10M006 136 2 - Amphenol FSA2567 - Fairchild Semiconductor 4PDT Analog Switch, with Low On-Capacitance and Low On-

Resistance Table 25: Example of components for connection to two removable SIM cards, with SIM detection implemented UBX-13001118 - R25 System description Page 52 of 182 LISA-U2 series VSIM 50 VSIM SIM_IO 48 SIM_CLK 47 SIM_RST 49 C11 1VSIM 2VSIM 1DAT 2DAT 1CLK 2CLK 1RST 2RST 4PDT Analog Switch 3V8 VCC DAT CLK RST SEL U1 GND Application Processor GPIO R1 C1 C2 C3 C4 C5 D1 D2 D3 D4 C6 C7 C8 C9 C10 D5 D6 D7 D8 FIRST SIM CARD VPP (C6) VCC (C1) IO (C7) CLK (C3) RST (C2) GND (C5) J1 SECOND SIM CARD VPP (C6) VCC (C1) IO (C7) CLK (C3) RST (C2) GND (C5) J2 LISA-U2 series - System Integration Manual 1.9 Serial communication LISA-U2 modules provide the following serial communication interfaces where the AT command interface and Packet-Switched / Circuit-Switched Data communication are concurrently available:

One asynchronous serial interface (UART) that provides complete RS-232 functionality conforming to the ITU-T V.24 Recommendation [3], with a limited data rate One Inter Processor Communication (IPC) interface that includes a synchronous SPI-compatible interface, with a maximum data rate of 26 Mbit/s One high-speed USB 2.0 compliant interface, with a maximum data rate of 480 Mbit/s. The LISA-U2 modules are designed to operate as an HSPA cellular modem, which represents a data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [3]. A customer application processor connected to the module through one of the interfaces represents the data terminal equipment (DTE). All the interfaces listed above are controlled and operated with:

AT commands according to 3GPP TS 27.007 [4]

AT commands according to 3GPP TS 27.005 [5]

AT commands according to 3GPP TS 27.010 [6]

u-blox AT commands For the complete list of supported AT commands and their syntax, see the u-blox AT Commands Manual [2]. The module firmware can be upgraded over all the serial interfaces listed above by means of an AT command (for more details, see section 3.1 as well as the u-blox AT Commands Manual [2], +UFWUPD command). The module firmware can be upgraded over the following serial interfaces using the u-blox EasyFlash tool:

The UART interface (only the RxD and TxD lines are needed) The USB interface (all the provided lines VUSB_DET, USB_D+ and USB_D- are needed) To directly enable PC (or similar) connection to the module for firmware upgrade using the u-blox EasyFlash tool, provide direct access on the application board to the VUSB_DET, USB_D+ and USB_D- lines of the module (or to the RxD and TxD lines). Also provide access to the PWR_ON or the RESET_N pins, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see the Firmware Update Application Note [16]). The following sub-sections describe the serial interfaces configuration and provide a detailed description of each interface for the application circuits. UBX-13001118 - R25 System description Page 53 of 182 LISA-U2 series - System Integration Manual 1.9.1 Serial interfaces configuration UART, USB and SPI/IPC serial interfaces are available through the AT command interface and for Packet-Switched / Circuit-Switched Data communication. The serial interfaces are configured as described in Table 26 (for information about further settings, see the u-blox AT Commands Manual [2]). Interface AT Settings Comments UART interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) AT+IPR=0 One-shot autobauding enabled by default AT+ICF=0 One-shot frame format recognition enabled by default USB interface Enabled SPI interface Enabled AT&K3 AT&S1 AT&D1 AT&C1 AT&K3 AT&S1 AT&D1 AT&C1 AT&K3 AT&S1 AT&D1 AT&C1 HW flow control enabled DSR line set ON in data mode and set OFF in command mode5 Upon an ON-to-OFF transition of DTR, the DCE enters online command mode and issues an OK result code5 Circuit 109 changes in accordance with the carrier detect status; ON if the carrier is detected, OFF otherwise 6 CDCs are available, configured as described in the following list:

USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling USB5: Primary TraceLog USB6: Secondary TraceLog USB7: SAP (SIM Access Profile) HW flow control enabled DSR line set ON in data mode and set OFF in command mode5 Upon an ON-to-OFF transition of the DTR, the DCE enters online command mode and issues an OK result code5 Circuit 109 changes in accordance with the carrier detect status; ON if the carrier is detected, OFF otherwise Multiplexing mode can be enabled by AT+CMUX command providing following channels:

Channel 0: control channel Channel 1 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) HW flow control enabled DSR line set ON in data mode and set OFF in command mode5 Upon an ON-to-OFF transition of the DTR, the DCE enters online command mode and issues an OK result code5 Circuit 109 changes in accordance with the carrier detect status; ON if the carrier is detected, OFF otherwise Table 26: Default serial interfaces configuration 5 Refer to the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode. UBX-13001118 - R25 System description Page 54 of 182 LISA-U2 series - System Integration Manual 1.9.2 Asynchronous serial interface (UART) The UART interface is a 9-wire unbalanced asynchronous serial interface that provides AT commands interface, PSD and CSD data communication. The module firmware can be upgraded over the UART interface using the u-blox EasyFlash tool or by means of an AT command (for more details, see section 3.1 and Firmware update application note [16]). UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [3]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state. For detailed electrical characteristics see LISA-U2 series Data Sheet [1]. The LISA-U2 modules are designed to operate as an HSPA cellular modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [3]. A customer application processor connected to the module through the UART interface represents the data terminal equipment (DTE). The signal names of the LISA-U2 modules UART interface conform to the ITU-T V.24 Recommendation [3]. UART interfaces include the following lines:

DTR Data terminal ready RTS Ready to send Description Data set ready Ring Indicator Data carrier detect Clear to send Transmitted data Received data Name DSR RI DCD CTS TxD RxD GND Remarks Module output Circuit 107 (Data set ready) in ITU-T V.24 Module output Circuit 125 (Calling indicator) in ITU-T V.24 Module output Circuit 109 (Data channel received line signal detector) in ITU-T V.24 Module input Circuit 108/2 (Data terminal ready) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control input Circuit 105 (Request to send) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module hardware flow control output Circuit 106 (Ready for sending) in ITU-T V.24 Module data input Circuit 103 (Transmitted data) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. Module data output Circuit 104 (Received data) in ITU-T V.24 Ground Table 27: UART interface signals The UART interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-

A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to the accessible points. UBX-13001118 - R25 System description Page 55 of 182 LISA-U2 series - System Integration Manual 1.9.2.1 UART features All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see the u-blox AT Commands Manual [2], &K, +IFC, \Q AT commands): hardware flow control (RTS/CTS), software flow control (XON/XOFF), or none flow control. Hardware flow control is enabled by default. One-shot autobauding is supported: the baud rate detection is performed once, at module start-up. Then the module works at the fixed baud rate (the detected one) and the baud rate can only be changed via the appropriate AT command (+IPR, for more details, see the u-blox AT Commands Manual [2]). In particular:

If automatic baud rate detection is configured in the active memory profile, the baud rate is detected once at the module power-on The factory-programmed setting enables the automatic baud rate detection (<rate> value is 0) Since autobauding is implemented as one shot autobauding, any setting of +IPR=0 should be avoided; the only exception is if the baud rate is fixed in the stored NVRAM profile. In this case, the module starts without autobauding and the host needs to reactivate it. If the system starts in autobauding (i.e. the +IPR is 0), the first at sequence provided to the module detects the baud rate. For example the first command sent from the DTE at any rate can be:

AT+CPIN="1234".Characters different than AT are ignored during the baud rate detection since the at or AT sequence triggers the hardware detection sequence. At or aT sequences are invalid:

the two detection characters must be both lowercase or uppercase. The module generates a response once autobauding detection is successful, the command is accepted and the command response is available. Therefore, even if the detection was previously successful, it is only possible to assume that the detection phase was successful after a response. If the DTE does not receive any response after some time, it must retry (the timeout value should be adjustable inside the DTE application). In any case, use a very simple command as the first command, for which the execution time is short and almost constant (e.g. ATE). Note that the only way to recover from a detection failure is the detection reattempt, since the AT interface is only available after a successful detection. One-shot autobauding is enabled by factory programmed setting. The only way to recover from a detection failure is the detection reattempt, since the AT interface is only available after a successful detection. The following baud rates can be configured by AT command:

1200 bit/s 2400 bit/s 4800 bit/s 9600 bit/s 19200 bit/s 38400 bit/s 57600 bit/s 230400 bit/s 460800 bit/s 921600 bit/s autobauding. UBX-13001118 - R25 115200 bit/s, default value when the one-shot autobauding is disabled 460800 bit/s and 921600 bit/s baud rates cannot be automatically detected by one-shot System description Page 56 of 182 LISA-U2 series - System Integration Manual One-shot automatic frame recognition is supported and enabled in conjunction with the one-shot automatic baud rate detection only: when the one-shot autobauding is active, the one-shot automatic frame recognition is enabled overruling the frame format setting. The frame format recognition is performed once and then, after the successful recognition of the frame format, the automatic frame recognition is disabled, as the automatic baud rate detection. One-shot automatic frame recognition is enabled by default as the one-shot autobauding. The following frame formats can be configured by AT command:

8N1 (8 data bits, no parity, 1 stop bit), default frame configuration with fixed baud rate 8E1 (8 data bits, even parity, 1 stop bit) 8O1 (8 data bits, odd parity, 1 stop bit) 8N2 (8 data bits, no parity, 2 stop bits) 7E1 (7 data bits, even parity, 1 stop bit) 7O1 (7 data bits, odd parity, 1 stop bit) The 8N2 frame format cannot be automatically detected by one-shot automatic frame recognition. The 8N1 frame format, which is the default configuration with a fixed baud rate, is described in Figure 25. Figure 25: Description of the UART default frame format (8N1) with a fixed baud rate 1.9.2.2 UART signal behavior See Table 5 for a description of operating modes and states referred to in this section. At the switch-on of the module, before the initialization of the UART interface as described in the power-on sequence detailed in Figure 18, each pin is first tri-stated and then is set to its specific internal reset state that is reported in the pin description table in the LISA-U2 series Data Sheet [1]. At the end of the boot sequence, the UART interface is initialized, the module is by default in active mode and the UART interface is enabled. The configuration and the behavior of the UART signals after the boot sequence are described below. For a complete description of data and command mode, see the u-blox AT Commands Manual [2]. RxD signal behavior The module data output line (RxD) is set by default to OFF state (high level) at UART initialization. The module holds RxD in OFF state until no data is transmitted by the module. UBX-13001118 - R25 System description Page 57 of 182 Normal Transfer, 8N1 Start of 1-Byte transfer Possible Start of next transfer D0 D1 D2 D3 D4 D5 D6 D7 Start Bit

(Always 0) tbit = 1/(Baudrate) Stop Bit

(Always 1) LISA-U2 series - System Integration Manual The module data input line (TxD) is set by default to OFF state (high level) at UART initialization. The TxD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TxD input. TxD signal behavior CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is enabled (data can be sent and received). The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART (see 1.9.2.3 for more details). If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the module is in low-power idle mode, but only that the UART is not enabled, as the module could be forced to stay in active mode for other activities, e.g. related to the network or related to other interfaces. When the multiplexer protocol is active, the CTS line state is mapped to the FCon / FCoff MUX command for flow control issues outside the power saving configuration, while the physical CTS line is still used as a power state indicator. For more details, see the Mux Implementation Application Note [14]. The CTS hardware flow control setting can be configured by AT commands (for more details, see the u-blox AT Commands Manual [2], AT&K, AT\Q, AT+IFC, AT+UCTS AT command). If the hardware flow control is not enabled, the CTS line after the UART initialization behaves as follows:

on LISA-U2 modules "01", "x2", "63" and "68" product versions, the CTS line is always held in the ON state on LISA-U2 modules "03" product version onward, the CTS line is by default set in the ON state, but can be configured in the OFF state by the AT+UCTS command When the power saving configuration is enabled and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in the low-power idle mode will not be a valid communication character (see 1.9.2.3 for more details). RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The RTS line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled (for more details, see the u-blox AT Commands Manual [2] AT&K, AT\Q, AT+IFC command description) the RTS line is monitored by the module to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to OFF state, any on-going data transmission from the module is immediately interrupted or any subsequent transmission forbidden until the RTS line changes to ON state. The DTE must be able to still accept a certain number of characters after the RTS line has been set to OFF state: the module guarantees the transmission interruption within 2 characters from RTS state change. UBX-13001118 - R25 System description Page 58 of 182 LISA-U2 series - System Integration Manual If AT+UPSV=2 is set and HW flow control is disabled, the RTS line is monitored by the module to manage the power saving configuration:

When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module is forced to active mode: after 20 ms from the transition the switch is completed and data can be received without loss. The module cannot enter idle mode and the UART is kept enabled as long as the RTS input line is held in the ON state If RTS is set to OFF state by the DTE, the UART is immediately disabled (held in low-power mode) and the module automatically enters idle mode whenever possible For more details on the power saving configuration controlled by the RTS input line see section 1.9.2.3 and the u-blox AT Commands Manual [2], AT+UPSV command. DSR signal behavior If AT&S0 is set, the DSR module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&S1 is set, the DSR module output line is set by default to OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode (see the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode). The above behavior is valid for both Packet-Switched and Circuit-Switched data transfers. DTR signal behavior The DTR module input line is set by default to OFF state (high level) at UART initialization. The DTR line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-

up is enabled inside the module on the DTR input. Module behavior according to DTR status depends on the AT command configuration (see the u-blox AT Commands Manual [2], &D AT command). Except for 01 product version, if AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration:

When an OFF-to-ON transition occurs on the DTR input line, the UART is enabled and the module is forced to active mode: after 20 ms from the transition, the switch is completed and data can be received without loss. The module cannot enter idle mode and the UART is keep enabled as long as the DTR input line is held in the ON state If DTR is set to OFF state by the DTE, the UART is immediately disabled (held in low-power mode) and the module automatically enters idle mode whenever possible For more details on the power saving configuration controlled by the DTR input line, see section 1.9.2.3 and the u-blox AT Commands Manual [2], AT+UPSV command. DCD signal behavior If AT&C0 is set, the DCD module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&C1 is set, the DCD module output line is set by default to OFF state (high level) at UART initialization. The DCD line is then set by the module in accordance with the carrier detect status: ON if the carrier is detected, OFF otherwise. For a voice call, DCD is set to ON state when the call is UBX-13001118 - R25 System description Page 59 of 182 LISA-U2 series - System Integration Manual established. For a data call there are the following scenarios (see the u-blox AT Commands Manual [2]

for the definition of the interface data mode, command mode and online command mode):

PSD data call: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The DCD ON is not related to the context activation but with the data mode. CSD data call: To establish a data call, the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non-reliable) or non-transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage, the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE. For a voice call, DCD is set to ON state on all the serial communication interfaces supporting the AT command interface (including MUX virtual channels, if active). DCD is set to ON during the execution of a command that requires input data from the DTE (all the commands where a prompt is issued; see AT commands +CMGS, +CMGW, +USOWR, +USODL,

+UDWNFILE in the u-blox AT Commands Manual [2]). The DCD line is set to ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed. DCD line is kept to ON state even during the online command mode to indicate that the data call is still established even if suspended, while if the module enters command mode, the DSR line is set to OFF state. For more details, see the DSR signal behavior description. For scenarios where the DCD line setting is requested for various reasons (e.g. SMS texting during online command mode), the DCD line changes to guarantee the correct behavior for all the scenarios. For instance, in case of SMS texting in online command mode, if the data call is released, the DCD line will be kept to ON until the SMS command execution is completed (even if the data call release would request the DCD setting to OFF). RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from OFF state to ON state with a 4:1 duty cycle and a 5 second period (ON for 1 second, OFF for 4 seconds, see Figure 26), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 26: RI behavior during an incoming call UBX-13001118 - R25 System description Page 60 of 182 1s 1s RI OFF RI OFF RI ON RI ON Call incomes Call incomes 0 0 5 5 10 10 15 15 time [s]

time [s]

The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 27), if the feature is enabled by the appropriate AT command (see the u-blox AT Commands Manual [2], AT+CNMI command). LISA-U2 series - System Integration Manual RI OFF RI OFF RI ON RI ON 1s 1s 0 0 SMS SMS arrives time [s]

time [s]

Figure 27: RI behavior at SMS arrival This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. In case of SMS arrival, if several events occur coincidently or in quick succession each event triggers the RI line independently, although the line will not be deactivated between each event. As a result, the RI line may stay ON for more than 1 second. If an incoming call is answered within less than 1 second (with ATA or if auto-answering is set to ATS0=1), then the RI line will be set to OFF earlier. As a result:

RI line monitoring cannot be used by the DTE to determine the number of received SMSs. In case of multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with the appropriate commands. The RI line can additionally notify all the URCs and all the incoming data (PPP, Direct Link, sockets, FTP) on all LISA-U2 series modules except for the 01 product version, if the feature is enabled by the proper AT command (see the u-blox AT Commands Manual [2], AT+URING command): the RI line is asserted when one of the configured events occur and it remains asserted for 1 second unless another configured event will happen, with the same behavior described in Figure 27. 1.9.2.3 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description see the u-blox AT Commands Manual [2]). When power saving is enabled, the module automatically enters low-power idle mode whenever possible; otherwise the active mode is maintained by the module (see section 1.4 for the definition and description of module operating modes). The AT+UPSV command configures both the module power saving and also the UART behavior in relation to the power saving. The conditions for the module entering idle mode also depend on the UART power saving configuration. The AT+UPSV command can set these different power saving configurations:

AT+UPSV=0, power saving disabled: module forced to active mode and UART interface enabled AT+UPSV=1, power saving enabled: module cyclic active / idle mode and UART enabled / disabled AT+UPSV=2, power saving enabled and controlled by the UART RTS input line AT+UPSV=3, power saving enabled and controlled by the UART DTR input line System description Page 61 of 182

(default) UBX-13001118 - R25 0 0 1 1 1 2 2 2 3 3 3 3 LISA-U2 series - System Integration Manual The AT+UPSV=3 power saving configuration is not supported by the 01 product version. The different power saving configurations that can be set by the +UPSV AT command are described in detail in the following subsections. The UART interface communication behaviors for the different power saving configurations, in relation to the HW flow control settings and RTS input line status, are summarized in Table 28. For more details on the +UPSV AT command description, see the u-blox AT commands Manual [2]. AT+UPSV HW flow control RTS line DTR line Communication during idle mode and wake-up Enabled (AT&K3) ON ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE. Enabled (AT&K3) OFF ON or OFF Data sent by the DTE should be buffered by the DTE and will be 0 Disabled (AT&K0) ON or OFF ON or OFF Data sent by the DTE is correctly received by the module. correctly received by the module when RTS is set to ON. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise the data is lost. Enabled (AT&K3) ON ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active mode is entered. Data sent by the module is correctly received by the DTE. Enabled (AT&K3) OFF ON or OFF Data sent by the DTE is buffered by the DTE and will be correctly received by the module when active mode is entered. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). Disabled (AT&K0) ON or OFF ON or OFF The first character sent by the DTE is lost, but after ~20 ms the UART and the module are waked up: recognition of subsequent characters is guaranteed after the complete UART / module wake-up. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. Enabled (AT&K3) ON or OFF ON or OFF Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. Disabled (AT&K0) ON ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. Disabled (AT&K0) OFF ON or OFF Data sent by the DTE is lost by LISA-U2 modules. Enabled (AT&K3) ON ON Enabled (AT&K3) ON OFF Enabled (AT&K3) OFF ON Enabled (AT&K3) OFF OFF The first character sent by the DTE is lost by LISA-U2 modules, but after ~20 ms the UART and the module are waked up: recognition of subsequent characters is guaranteed after the complete UART /

module wake-up. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE. Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE. Data sent by the DTE is correctly received by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). Data sent by the DTE is lost by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). UBX-13001118 - R25 System description Page 62 of 182 3 3 LISA-U2 series - System Integration Manual AT+UPSV HW flow control RTS line DTR line Communication during idle mode and wake-up Disabled (AT&K0) ON or OFF ON Disabled (AT&K0) ON or OFF OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. Table 28: UART and power-saving summary AT+UPSV=0: power saving disabled, fixed active mode The module does not enter idle mode and the UART interface is enabled (data can be sent and received): the CTS line is always held in the ON state after UART initialization. This is the default configuration. AT+UPSV=1: power saving enabled, cyclic idle/active mode When the DTE issues the AT+UPSV=1 command, the UART is immediately disabled. Afterwards, the UART of LISA-U2 series modules is periodically enabled to receive or send data and, if data has not been received or sent over the UART, the interface is automatically disabled whenever possible according to the timeout configured by the second parameter of the +UPSV AT command. The module automatically enters the low-power idle mode whenever possible but it wakes up to active mode according to the UART periodic wake-up so that the module cycles between the low-power idle mode and the active mode. Additionally, the module wakes up to active mode according to any required activity related to the network or any other required activity related to the functions /

interfaces of the module. The UART is enabled, and the module does not enter low-power idle mode, in the following cases:

During the periodic UART wake-up to receive or send data If the module needs to transmit some data over the UART (e.g. URC) If a character is sent by the DTE with HW flow control disabled, the first character sent causes the system wake-up due to the wake-up via data reception feature described in the following subsection, and the UART will be then kept enabled after the last data received according to the timeout set by the second parameter of the AT+UPSV=1 command The module, outside an active call, periodically wakes up from idle mode to active mode to monitor the paging channel of the current base station (paging block reception), according to the 2G or 3G discontinuous reception (DRX) specifications. The time period between two paging receptions is defined by the current base station (i.e. by the network):

If the module is registered with a 2G network, the paging reception period can vary from ~0.47 s

(DRX = 2, i.e. 2 x 51 2G-frames) up to ~2.12 s (DRX = 9, i.e. 9 x 51 2G-frames) If the module is registered with a 3G network, the paging reception period can vary from 0.64 s

(DRX = 6, i.e. 26 3G-frames) up to 5.12 s (DRX = 9, i.e. 29 3G-frames) The time period of the UART enable/disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network:

2G: the UART is enabled concurrently to a paging reception, and then, as data has not been received or sent, the UART is disabled until the first paging reception that occurs after a timeout of 2.0 s, and afterwards the interface is enabled again UBX-13001118 - R25 System description Page 63 of 182 LISA-U2 series - System Integration Manual 3G: the UART is asynchronously enabled to paging receptions, as the UART is enabled for ~20 ms, and then, if data are not received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again Not registered: when a module is not registered with a network, the UART is enabled for ~20 ms, and then, if data has not been received or sent, the UART is disabled for 2.5 s and afterwards the interface is enabled again The module active mode duration outside an active call depends on:

Network parameters, related to the time interval for the paging block reception (minimum of ~11 ms) Duration of UART enable time in absence of data reception (~20 ms) The time period from the last data received at the serial port during the active mode: the module does not enter idle mode until a timeout expires. The second parameter of the +UPSV AT command configures this timeout, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). The default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s) The active mode duration can be extended indefinitely since every subsequent character received during the active mode will reset and restart the timer. The timeout is ignored immediately after AT+UPSV=1 has been sent, so that the UART interface is disabled and the module may enter idle mode immediately after the AT+UPSV=1 has been sent The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can be sent and received over the UART), if HW flow control is enabled, as illustrated in Figure 28. Figure 28: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level) AT+UPSV=2: power saving enabled and controlled by the RTS line This configuration can only be enabled with the module hardware flow control disabled by AT&K0 command. The UART interface is immediately disabled after the DTE sets the RTS line to OFF. Then the module automatically enters idle mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the RTS line is held to OFF, but the UART is enabled in case the module needs to transmit some data over the UART (e.g. URC). When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module, if it was in idle mode, switches from idle to active mode after ~20 ms: this is the UART and module wake-up time. If the RTS line is set to ON by the DTE, the module is not allowed to enter the low-power idle mode and the UART is kept enabled. UBX-13001118 - R25 System description Page 64 of 182 Data input CTS OFF CTS ON 0.47- 2.10 s

~10 ms (min) UART disabled UART enabled

~9.2 s (default) UART enabled time [s]

LISA-U2 series - System Integration Manual AT+UPSV=3: power saving enabled and controlled by the DTR line The AT+UPSV=3 configuration can be enabled regardless of the flow control setting on UART. In particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this configuration. The UART interface is immediately disabled after the DTE sets the DTR line to OFF. Then the module automatically enters idle mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the DTR line is set to OFF, but the UART is enabled in case the module needs to transmit some data over the UART (e.g. URC). When an OFF-to-ON transition occurs on the DTR input line, the UART is re-enabled and the module, if it was in idle mode, switches from idle to active mode after 20 ms: this is the UART and module wake-up time. If the DTR line is set to ON by the DTE, the module is not allowed to enter idle mode and the UART is kept enabled until the DTR line is set to OFF. When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to control the module behavior according to AT&D command configuration (see u-blox AT Commands Manual [2]). The CTS output line indicates the UART power saving state as illustrated in Figure 28, if HW flow control is enabled with AT+UPSV=3. The AT+UPSV=3 power saving configuration is not supported by the 01 product version. Wake-up via data reception The UART wake-up via data reception consists of a special configuration of the module TXD input line that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In particular, the UART is enabled and the module switches from the low-power idle mode to active mode within ~20 ms from the first character received: this is the system wake-up time. As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake-up character) is not a valid communication character even if the wake-up via data reception configuration is active, because it cannot be recognized, and the recognition of the subsequent characters is guaranteed only after the complete system wake-up (i.e. after ~20 ms). The UART wake-up via data reception configuration is active in the following case:

the TXD input line is configured to wake up the system via data reception only if AT+UPSV=1 is set with hardware flow control disabled The UART wake-up via data reception configuration is not active on the TXD input, and therefore all the data sent by the DTE is lost, if:

AT+UPSV=2 is set with HW flow control disabled, and the RTS line is set OFF AT+UPSV=3 is set, regardless of the HW flow control setting, and the DTR line is set OFF Figure 29 and Figure 30 show examples of common scenarios and timing constraints:

AT+UPSV=1 power saving configuration is active and the timeout from last data received to idle mode start is set to 2000 frames (AT+UPSV=1,2000) Hardware flow control is disabled UBX-13001118 - R25 System description Page 65 of 182 LISA-U2 series - System Integration Manual Figure 29 shows the case where the module UART is disabled and only a wake-up is forced. In this scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE module UART is disabled when the timeout from last data received expires (2000 frames without data reception, as the default case). Figure 29: Wake-up via data reception without further communication Figure 30: Wake-up via data reception with further communication Figure 30 shows the case where in addition to the wake-up character further (valid) characters are sent. The wake-up character wakes up the module UART. The other characters must be sent after the wake up time of ~20 ms. If this condition is satisfied, the module (DCE) recognizes characters. The module will disable the UART after 2000 GSM frames from the latest data reception. The wake-up via data reception feature cannot be disabled. In command mode6, if autobauding is enabled and the DTE does not implement HW flow control, the DTE must always send a character to the module before the AT prefix set at the beginning of each command line: the first character is ignored if the module is in active mode, or it represents the wake-up character if the module is in idle mode. 6 See the u-blox AT Commands Manual [2] for definitions of interface data mode, command mode and online command mode. UBX-13001118 - R25 System description Page 66 of 182 DCE UART is enabled for 2000 GSM frames (~9.2 s) UART OFF ON OFF ON TXD input Wake up time: ~20 ms Wake up character Not recognized by DCE time time UART OFF ON OFF ON DCE UART is enabled for 2000 GSM frames (~9.2s) after the last data received TXD input Wake up time: ~20 ms Wake up character Not recognized by DCE Valid characters Recognized by DCE time time LISA-U2 series - System Integration Manual In command mode6, if autobauding is disabled, the DTE must always send a dummy AT before each command line: the first character is not ignored if the module is in active mode (i.e. the module replies OK), or it represents the wake-up character if the module is in low-power idle mode (i.e. the module does not reply). No wake-up character or dummy AT is required from the DTE during a voice or data call since the module UART interface continues to be enabled and does not need to be woken-up. Furthermore in data mode6, a dummy AT would affect the data communications. Additional considerations The LISA-U2 series modules are forced to stay in active mode if the USB is connected and not suspended, and therefore the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings are overruled, but they still have effect on the UART behavior: they configure the UART interface power saving, so that the UART is enabled / disabled according to the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings. To set the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 configuration over the USB interface of LISA-U2 modules, the autobauding must be previously disabled on the UART by the +IPR AT command over the used AT interface (the USB), and this +IPR AT command configuration must be saved in the modules non-volatile memory (see the u-blox AT Commands Manual [2]). Then, after the subsequent module re-boot, AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 can be issued over the used AT interface

(the USB): all the AT profiles are updated accordingly. UBX-13001118 - R25 System description Page 67 of 182 LISA-U2 series - System Integration Manual 1.9.2.4 UART application circuits Providing the full RS-232 functionality (using the complete V.24 link) If RS-232 compatible signal levels are needed to provide full RS-232 (9 lines) functionality, two different external voltage translators Instruments SN74AVC4T774) can be used. The Texas Instruments chip provides the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to an RS-232 compatible signal level.

(e.g. Maxim MAX3237E and Texas If a 1.8V application processor is used for complete RS-232 functionality conforming to the ITU Recommendation [3] in DTE/DCE serial communication, the complete UART interface of the module

(DCE) must be connected to a 1.8 V DTE as described in Figure 31. Figure 31: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output as a 1.8 V supply, as illustrated in Figure 32. Figure 32: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 Murata U1, U2 Unidirectional Voltage Translator SN74AVC4T774 Texas Instruments Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) UBX-13001118 - R25 System description Page 68 of 182 Application processor

(1.8V DTE) LISA-U2 series

(1.8V DCE) TxD RxD RTS CTS DTR DSR RI DCD GND 0 0 0 0 TP TP TP TP 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND Application processor

(3.0V DTE) 3V0 LISA-U2 series

(1.8V DCE) C1 3V0 C3 VCC TxD RxD RTS CTS DTR DSR RI DCD GND Unidirectional Voltage Translator 1V8 VCCA DIR1 DIR3 A1 A2 A3 A4 VCCB 4 V_INT C2 TP TP TP TP 0 0 0 0 B1 B2 B3 B4 15 TXD 16 RXD 13 RTS 14 CTS DIR2 DIR4 OE GND U1 Unidirectional Voltage Translator VCCA VCCB DIR1 A1 A2 A3 A4 DIR2 DIR3 DIR4 U2 B1 B2 B3 B4 OE GND 1V8 C4 12 DTR 9 DSR 10 RI 11 DCD GND LISA-U2 series - System Integration Manual Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link) If the functionality of the DSR, DCD and RI lines is not required, or the lines are not available:

Leave the DSR, DCD and RI lines of the module unconnected and floating If RS-232 compatible signal levels are needed, two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chip provides the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to an RS-232 compatible signal level. Figure 35 describes the circuit that should be implemented as if a 1.8 V application processor is used, given that the DTE will behave properly regardless of the DSR input setting. Figure 33: UART interface application circuit with partial V.24 link (6-wire) in the DTE/DCE serial communication (1.8 V DTE) If a 3.0 V application processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output pin as a 1.8 V supply, as described in Figure 34, given that the DTE will behave properly regardless of the DSR input setting. Figure 34: UART interface application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 30: Component for UART application circuit with partial V.24 link (6-wire) in DTE/DCE serial communication (3.0 V DTE) U1 U2 UBX-13001118 - R25 System description Page 69 of 182 Application processor

(1.8V DTE) LISA-U2 series

(1.8V DCE) TxD RxD RTS CTS DTR DSR RI DCD GND 0 0 0 0 TP TP TP TP 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND Application processor

(3.0V DTE) 3V0 C1 Unidirectional Voltage Translator 1V8 VCCB 4 V_INT LISA-U2 series

(1.8V DCE) VCC TxD RxD RTS CTS DTR DSR RI DCD GND VCCA DIR1 DIR3 A1 A2 A3 A4 DIR2 DIR4 U1 DIR1 A1 A2 U2 B1 B2 B3 B4 OE GND DIR2 B1 B2 OE GND C2 TP TP TP TP 0 0 0 0 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND 3V0 Unidirectional Voltage Translator 1V8 VCCA VCCB C3 C4 LISA-U2 series - System Integration Manual If only the TxD, RxD, RTS, CTS and DTR lines are provided (as implemented in Figure 33 and in Figure 34) and if HW flow-control is enabled (AT&K3, default setting), the power saving can be activated as it can be done when the complete UART link is provided (9-wire, as implemented in Figure 31 and in Figure 32), i.e. in these ways:

AT+UPSV=1: the module automatically enters the low-power idle mode whenever possible and the UART interface is periodically enabled, as described in section 1.9.2.3, reaching low current consumption. With this configuration, when the module is in idle mode, the data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active mode is entered. AT+UPSV=3: the module automatically enters the low-power idle mode whenever possible and the UART interface is enabled by the DTR line, as described in section 1.9.2.3, reaching very low current consumption. With this configuration, not supported by the 01 product version, when the module is in idle mode, the UART is re-enabled 20 ms after DTR has been set ON, and the recognition of subsequent characters is guaranteed until the module is in active mode If the HW flow-control is disabled (AT&K0), it is recommended to enable the power saving in one of these ways:

AT+UPSV=2: the module automatically enters the low-power idle mode whenever possible and the UART interface is enabled by the RTS line, as described in section 1.9.2.3, reaching very low current consumption. With this configuration, when the module is in idle mode, the UART is re-enabled 20 ms after RTS has been set ON, and the recognition of subsequent characters is guaranteed until the module is in active mode. AT+UPSV=3: the module automatically enters the low-power idle mode whenever possible and the UART interface is enabled by the DTR line, as described in section 1.9.2.3, reaching very low current consumption. With this configuration, not supported by the 01 product version, when the module is in idle mode, the UART is re-enabled 20 ms after DTR has been set ON, and the recognition of subsequent characters is guaranteed until the module is in active mode. Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link) If the functionality of the DSR, DCD, RI and DTR lines is not required, or the lines are not available:

Connect the module DTR input line to GND, to robustly fix the logic level Leave the DSR, DCD and RI lines of the module unconnected and floating If RS-232 compatible signal levels are needed, the Maxim 13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. Figure 35 describes the circuit that should be implemented as if a 1.8 V application processor is used. Figure 35: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8 V DTE) UBX-13001118 - R25 System description Page 70 of 182 Application processor

(1.8V DTE) LISA-U2 series

(1.8V DCE) TxD RxD RTS CTS DTR DSR RI DCD GND 0 0 0 0 TP TP TP TP 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND If a 3.0 V application processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output as a 1.8 V supply, as described in Figure 36. LISA-U2 series - System Integration Manual Figure 36: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 31: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) If only the TxD, RxD, RTS and CTS lines are provided, as implemented in Figure 35 and in Figure 36, and if HW flow-control is enabled (AT&K3, default setting), the power saving can be activated in this way:

AT+UPSV=1: the module automatically enters the low-power idle mode whenever possible and the UART interface is periodically enabled, as described in section 1.9.2.3, reaching low current consumption. With this configuration, when the module is in idle mode, data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active mode is entered. If the HW flow-control is disabled (AT&K0), it is recommended to enable the power saving in this way:

AT+UPSV=2: the module automatically enters the low-power idle mode whenever possible and the UART interface is enabled by the RTS line, as described in section 1.9.2.3, reaching very low current consumption. With this configuration, when the module is in idle mode, the UART is re-enabled 20 ms after RTS has been set ON, and the recognition of subsequent characters is guaranteed until the module is in active mode. Providing the TxD and RxD lines only (not using the complete V24 link) If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available:

Connect the module RTS input line to GND or to the CTS output line of the module: since the module requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, that is the default setting), the pin can be connected using a 0 series resistor to GND or to the active module CTS (low electrical level) when the module is in active mode, the UART interface is enabled and the HW flow-control is enabled. Connect the module DTR input line to GND, to robustly fix the logic level. Leave the DSR, DCD and RI lines of the module unconnected and floating. UBX-13001118 - R25 System description Page 71 of 182 Application processor

(3.0V DTE) 3V0 C1 Unidirectional Voltage Translator 1V8 VCCB 4 V_INT LISA-U2 series

(1.8V DCE) VCC TxD RxD RTS CTS DTR DSR RI DCD GND VCCA DIR1 DIR3 A1 A2 A3 A4 DIR2 DIR4 U1 C2 TP TP TP TP 0 0 0 0 B1 B2 B3 B4 OE GND 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND LISA-U2 series - System Integration Manual If RS-232 compatible signal levels are needed, the Maxim 13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. Figure 37 describes the circuit that should be implemented as if a 1.8 V application processor is used. Figure 37: UART interface application circuit with partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V application processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output as a 1.8 V supply, as illustrated in Figure 38. Figure 38: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 U1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 32: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) If only the TxD and RxD lines are provided, as described in Figure 37 or in Figure 38, and HW flow-

control is disabled (AT&K0), the power saving must be enabled in this way:

AT+UPSV=1: the module automatically enters the low-power idle mode whenever possible and the UART interface is periodically enabled, as described in section 1.9.2.3, reaching low current consumption. With this configuration, when the module is in idle mode, the UART is re-enabled 20 ms after the first data reception, and the recognition of subsequent characters is guaranteed until the module is in active mode. If only TxD and RxD lines are provided, data delivered by the DTE can be lost with these settings:

o HW flow-control enabled in the module (AT&K3, that is the default setting) o Module power saving enabled by AT+UPSV=1 o HW flow-control disabled in the DTE UBX-13001118 - R25 System description Page 72 of 182 Application processor

(1.8V DTE) LISA-U2 series

(1.8V DCE) TxD RxD RTS CTS DTR DSR RI DCD GND TP 0 0 TP 0 TP TP 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND Application processor

(3.0V DTE) 3V0 Unidirectional Voltage Translator 1V8 LISA-U2 series

(1.8V DCE) VCC TxD RxD RTS CTS DTR DSR RI DCD GND C1 VCC A DIR1 A1 A2 DIR2 U1 VCCB B1 B2 OE GND C2 TP TP 0 0 4 V_INT 15 TXD 16 RXD 0 TP TP 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND LISA-U2 series - System Integration Manual In this case, the first character sent when the module is in idle mode will be a wake-up character and will not be a valid communication character (see section 1.9.2.3 for the complete description). If power saving is enabled, the application circuit with the TxD and RxD lines only is not recommended. During command mode, the DTE must send to the module a wake-up character or a dummy AT before each command line (see section 1.9.2.3 for the complete description), but during data mode, the wake-up character or the dummy AT would affect the data communications. Additional considerations If a 3.0 V application processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the corresponding 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost solution, by means of an appropriate voltage divider. Consider the value of the pull-up integrated at the input of the module (DCE) for the correct selection of the voltage divider resistance values and mind that any DTE signal connected to the module must be tri-stated or set low when the module is in power-down mode and during the module power-on sequence (at least until the activation of the V_INT supply output of the module), to avoid latch-up of circuits and allow a clean boot of the module

(see the remark below). Moreover, the voltage scaling from any 1.8 V output of the cellular module

(DCE) to the corresponding 3.0 V input of the application processor (DTE) can be implemented by means of an appropriate low-cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for the appropriate selection of the resistance value for the external pull-up biased by the application processor supply rail. If the module USB interface is connected to the application processor, it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines of the module for execution of the firmware upgrade over UART using the u-blox EasyFlash tool and for debugging purposes:

testpoints can be added on the lines to accommodate the access and a 0 series resistor must be mounted on each line to detach the module pin from any other connected device. Otherwise, if the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of the firmware upgrade over USB and for debugging purposes. In both cases, provide as well access to the RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see the Firmware Update Application Note [16]). If the UART interface is not used, all the UART interface pins can be left unconnected, but it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of the firmware upgrade using the u-blox EasyFlash tool and for debugging purposes . Any external signal connected to the UART interface must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-

stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during the modules power-down mode, when external reset is forced low, and during the power-on sequence. UBX-13001118 - R25 System description Page 73 of 182 LISA-U2 series - System Integration Manual 1.9.3 USB interface LISA-U2 modules provide a high-speed USB interface at 480 Mbit/s compliant with the Universal Serial Bus Revision 2.0 specification [7]. It acts as a USB device and can be connected to any USB host such as a PC or other application processor. The USB-device shall look for all upper SW layers like any other serial device. This means that the LISA-U2 modules emulate all serial control logical lines. Name Description Remarks VUSB_DET USB detect input Apply 5 V typical to enable USB USB_D+

USB Data Line D+

90 nominal differential characteristic impedance (Z0) 30 nominal common mode characteristic impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [7] are part of the USB pad driver and need not be provided externally. 90 nominal differential characteristic impedance (Z0) 30 nominal common mode characteristic impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [7] are part of the USB pad driver and need not be provided externally. USB_D-

USB Data Line D-

Table 33: USB pins The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting a very low capacitance

(i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to the accessible points. 1.9.3.1 USB features LISA-U2 modules include a High-Speed USB 2.0 compliant interface with a maximum data rate of 480 Mbit/s between the module and a host processor. The module itself acts as a USB device and can be connected to any USB host such as a personal computer or an embedded application microprocessor for AT commands, data communication, FW upgrade by means of the FOAT feature, FW upgrade by means of the u-blox EasyFlash tool and for diagnostic purposes. The USB_D+/USB_D- lines carry the USB serial bus data and signaling, while the VUSB_DET input pin senses the VBUS USB supply presence (nominally +5 V at the source) to detect the host connection and enable the interface. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input

(see the LISAU2 series Data Sheet [1]). Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs only a few microamperes. LISA-U2 series modules can provide the following functions over the USB interface:

CDC-ACM for AT commands and data communication CDC-ACM for GNSS tunneling CDC-ACM for diagnostic CDC-ACM for SAP (SIM Access Profile) CDC-ECM for Ethernet-over-USB CDC-ECM for Ethernet-over-USB function is not supported by the "01", "x2", "63" and "68" versions. UBX-13001118 - R25 System description Page 74 of 182 LISA-U2 series - System Integration Manual Each USB profile of LISA-U2 module identifies itself by its VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [7]. If the USB interface is connected to the host before the module switch-on, or if the module is reset with the USB interface connected to the host, the VID and PID are automatically updated at runtime, after the USB detection. At first, VID and PID are the following:

VID = 0x058B PID = 0x0041 VID = 0x1546 PID = 0x1102 This VID and PID combination identifies a USB profile where no USB functions are available: AT commands must not be sent to the module over the USB profile identified by this VID and PID combination. Then, after a time period (roughly 5 seconds, depending on the host / device enumeration timings), the VID and PID are updated to the following values, which are related to the LISA-U2 module default USB profile:

The default configuration of the USB interface provides 7 USB CDC-ACM modem COM ports:

USB1: AT and data USB2: AT and data USB3: AT and data USB4: GNSS tunneling USB5: Primary Log (diagnostic purposes) USB6: Secondary Log (diagnostic purposes) USB7: SAP (SIM Access Profile) The user can concurrently use the AT command interface on one CDC, and Packet-Switched / Circuit-

Switched data communication on another CDC. Figure 39 (left side) summarizes the USB end-points available with the default USB profile configuration. The USB interface of the LISA-U2 series can be configured by the AT+UUSBCONF command (for more details, see the u-blox AT Commands Manual [2]) to select a different set of USB functions, available in a mutually exclusive way, and including 1 CDC-ECM for Ethernet-over-USB and 4 CDC-ACM modem COM ports enumerated as follows:

USB1: AT and data USB2: GNSS tunneling USB3: Primary Log (diagnostic purpose) USB4: SAP (SIM Access Profile) VID = 0x1546 PID = 0x1104 In the case of the USB profile with the set of functions described above, the VID and PID combination is the following:

Figure 39 (right side) summarizes the USB end-points available with this alternative USB profile configuration. The USB profile cannot be changed on the "01", "x2", "63" and "68" product versions of LISA-U2 series modules, as the AT+UUSBCONF command is not supported. UBX-13001118 - R25 System description Page 75 of 182 LISA-U2 series - System Integration Manual The USB profile change, triggered by means of the AT+UUSBCONF command, is not performed at run-time. The settings are saved in the Non-Volatile Memory at the module power-off, triggered by means of the AT+CPWROFF command, and the new configuration will be effective at the subsequent module reboot. Figure 39: LISA-U2 series end-points summary for the default and alternative USB profile configuration For more details on the configuration of the USB interface of LISA-U2 modules, see the u-blox AT Commands Manual [2], +UUSBCONF AT command. The module firmware can be upgraded over the USB interface using the u-blox EasyFlash tool or by means of an AT command (for more details, see section 3.12 and the Firmware update application note [16]). UBX-13001118 - R25 System description Page 76 of 182 Default profile configuration Alternative profile configuration Function AT and Data Function AT and Data Interface 0 Abstract Control Model EndPoint Transfer: Interrupt Interface 1 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Interface 2 Abstract Control Model EndPoint Transfer: Interrupt Interface 3 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Interface 4 Abstract Control Model EndPoint Transfer: Interrupt Interface 5 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Interface 6 Abstract Control Model EndPoint Transfer: Interrupt Interface 7 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Interface 8 Ethernet Networking Control Model EndPoint Transfer: Interrupt Interface 9 Data On / Off EndPoint EndPoint Transfer: Bulk Transfer: Bulk Function AT and Data Function GNSS tunneling Function AT and Data Function Primary Log Function GNSS tunneling Function SAP Function Primary Log Function Ethernet Interface 0 Abstract Control Model EndPoint Transfer: Interrupt Interface 1 Data EndPoint EndPoint Transfer: Bulk Transfer: Bulk Interface 2 Abstract Control Model EndPoint Transfer: Interrupt Interface 3 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Interface 4 Abstract Control Model EndPoint Transfer: Interrupt Interface 5 Data EndPoint EndPoint Transfer: Bulk Transfer: Bulk Interface 6 Abstract Control Model EndPoint Transfer: Interrupt Interface 7 Data EndPoint EndPoint Transfer: Bulk Transfer: Bulk Interface 8 Abstract Control Model EndPoint Transfer: Interrupt Interface 9 EndPoint EndPoint Data Transfer: Bulk Transfer: Bulk Function Secondary Log Interface 10 Abstract Control Model EndPoint Transfer: Interrupt Interface 11 Data EndPoint EndPoint Transfer: Bulk Transfer: Bulk Function SAP Interface 12 Abstract Control Model EndPoint Transfer: Interrupt Interface 13 Data EndPoint EndPoint Transfer: Bulk Transfer: Bulk LISA-U2 series - System Integration Manual The USB drivers are available for the following operating system platforms:

Windows XP (WHQL, Thesycon v1.8, Thesycon v1.96) Windows Vista (WHQL, Thesycon v1.8, Thesycon v1.96) Windows 7 (WHQL, Thesycon v1.8, Thesycon v1.96) Windows 8 Windows 8.1 Windows 10 Windows CE 5.0 (Thesycon v1.42, Thesycon v1.50) Windows Embedded CE 6.0 (Thesycon v1.42, Thesycon v1.50) Windows Embedded Compact 7 (Thesycon v1.50) Windows Embedded Automotive 7 (Thesycon v1.50) Windows Mobile 5 (Thesycon v1.42, Thesycon v1.50) Windows Mobile 6 (Thesycon v1.42, Thesycon v1.50) Windows Mobile 6.1 (Thesycon v1.50) Windows Mobile 6.5 LISA-U2 modules are compatible with standard Linux/Android USB kernel drivers. 1.9.3.2 USB and power saving The modules automatically enter the USB suspended state when the device has observed no bus traffic for a specific time period according to the USB 2.0 specification [7]. In suspended state, the module maintains any USB internal status as a device. In addition, the module enters the suspended state when the hub port it is attached to is disabled. This is referred to as a USB selective suspend. If the USB is suspended and a power saving configuration is enabled by the AT+UPSV command, the module automatically enters the low-power idle mode whenever possible, but it wakes up to active mode according to any required activity related to the network (e.g. the periodic paging reception described in section 1.5.3.3) or any other required activity related to the functions / interfaces of the module. The USB exits suspend mode when there is bus activity. If the USB is connected and not suspended, the module is forced to stay in active mode, and so the AT+UPSV settings are overruled, but they still have effect on the power saving configuration of the other interfaces. The modules are capable of USB remote wake-up signaling: i.e. it may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate a remote wake-up, for example due to an incoming call, URCs, or data reception on a socket. The remote wake-up signaling notifies the host that it should resume from its suspended mode, if necessary, and service the external event. Remote wake-up is accomplished using electrical signaling described in the USB 2.0 specifications [7]. For the module current consumption description with power saving enabled and USB suspended, or with power saving disabled and USB not suspended, see the sections 1.5.3.3 and 1.5.3.4 and LISA-U2 series Data Sheet [1]. UBX-13001118 - R25 System description Page 77 of 182 LISA-U2 series - System Integration Manual 1.9.3.3 USB application circuit Since the module acts as a USB device, the USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host. The USB interface is enabled only when a valid voltage as a USB supply is detected by the VUSB_DET input. Neither the USB interface nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs only a few microamperes. The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single-

ended mode for relatively low speed signaling handshaking, as well as in differential mode for fast signaling and data transfer. USB pull-up or pull-down resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [7] are part of the USB pad driver and do not need to be externally provided. External series resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [7] are also integrated: characteristic impedance of the USB_D+ and USB_D- lines is specified by the USB standard. The most important parameter is the differential characteristic impedance (Z0) applicable for an odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if the PCB layout is not optimal, especially when the USB signaling lines are very long. The common mode characteristic impedance (ZCM) of each USB data line should be as close as possible to 30 . Figure 40: USB Interface application circuit Reference Description Part Number - Manufacturer D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Table 34: Component for USB application circuit If the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of the firmware upgrade over USB using the u-blox EasyFlash tool and for debugging purposes: testpoints can be added on the lines to accommodate the access. Otherwise, if the USB interface is connected to the application processor, it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of the firmware upgrade over UART and for debugging purposes. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see the Firmware Update Application Note [16]). If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected, but it is highly recommended to provide direct access to the lines for FW upgrade and debugging purposes. UBX-13001118 - R25 System description Page 78 of 182 USB DEVICE CONNECTOR VBUS D+

D-

GND D1 D2 D3 C1 LISA-U2 series 18 VUSB_DET 27 USB_D+

26 USB_D-

GND LISA-U2 series - System Integration Manual 1.9.4 SPI interface SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without any specific configuration. The SPI-compatible synchronous serial interface cannot be used for the FW upgrade. The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and SPI_MISO) and a clock signal (SPI_SCLK). LISA-U2 modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard 3-wire SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface. The purpose of the IPC interface is to achieve high speed communication (up to 26 Mbit/s) between two processors following the same IPC specifications: the module baseband processor and an external processor. High speed communication is possible only if both sides follow the same Inter Processor Communication (IPC) specifications. The module firmware can be upgraded over the SPI interface by means of an AT command (for more details, see section 3.1 and the Firmware Update application note [16]). Name Description Remarks SPI_MISO SPI Data Line. Master Input, Slave Output SPI_MOSI SPI Data Line. Master Output, Slave Input SPI_SCLK SPI Serial Clock. Master Output, Slave Input Module Output. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Module Input. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Internal active pull-up to V_INT (1.8 V) enabled. Module Input. Idle low (CPOL=0). Supported clock frequency: from 260 kHz up to 26 MHz. Internal active pull-down to GND enabled. Module Input. Idle low. Internal active pull-down to GND enabled. SPI_MRDY SPI Master Ready to transfer data control line. Master Output, Slave Input SPI_SRDY SPI Slave Ready to transfer data control line. Master Input, Slave Output Module Output. Idle low. Table 35: SPI interface signals The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002 varistor array) on the lines connected to these pins, close to the accessible points. UBX-13001118 - R25 System description Page 79 of 182 LISA-U2 series - System Integration Manual 1.9.4.1 IPC communication protocol overview The module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without any specific configuration. The SPI device shall look for all upper SW layers like any other serial device. This means that LISA-U2 modules emulate all serial logical lines: the transmission and the reception of the data are similar to an asynchronous device. Two additional signals (SPI_MRDY / SPI_SRDY) are added to the SPI lines to communicate the state of readiness of the two processors: they are used as handshake signals to implement the data flow. The function of the SPI_MRDY and SPI_SRDY signals is two-fold:

For transmitting data, the signal indicates to the data receiver that data is available to be transmitted For receiving data, the signal indicates to the transmitter that the receiver is ready to receive data Due to this setup, it is possible to use the control signals as interrupt lines waking up the receiving part when data is available for transfer. When the handshaking has taken place, the transfer occurs just as if it were a standard SPI interface without chip select functionality (i.e. one master - one slave setup). SPI_MRDY is used by the application processor (i.e. the master) to indicate to the module baseband processor (i.e. the slave) that it is ready to transmit or receive (IPC master ready signal), and can also be used by the application processor to wake up the module baseband processor if it is in idle mode. SPI_SRDY line is used by the module baseband processor (i.e. the slave) to indicate to the application processor (i.e. the master) that it is ready to transmit or receive (IPC slave ready signal), and can also be used by the module baseband processor to wake up the application processor if it is in hibernation. Figure 41: IPC Data Flow: SPI_MRDY and SPI_SRDY line usage combined with the SPI protocol For the correct implementation of the SPI protocol, the frame size is known by both sides before a packet transfer of each packet. The frame is composed by a header with fixed size (always 4 bytes) and a payload with variable length (must be a multiple of 4 bytes). The same amount of data is exchanged in both directions simultaneously. Both sides set their readiness lines (SPI_MRDY / SPI_SRDY) independently when they are ready to transfer data. For the correct transmission of the data, the other side must wait for the activating interrupt to allow the transfer of the other side. The master starts the clock shortly after SPI_MRDY and SPI_SRDY are set to active. The number of clock periods sent by the master is exactly that one of the frame-size to be transferred. The SPI_SRDY line will be set low after the master sets the clock line to the idle state. The SPI_MRDY line is also set inactive after the clock line is set idle, but in case of a big transfer containing multiple packets, the SPI_MRDY line stays active. UBX-13001118 - R25 System description Page 80 of 182 DATA_EXCHANGE Header Data SPI_MRDY SPI_SRDY SPI_SCLK SPI_MOSI SPI_MISO LISA-U2 series - System Integration Manual 1.9.4.2 IPC communication and power saving If power saving is enabled by an AT command (AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3), the LISA-

U2 module automatically enters idle mode whenever possible, if the master indicates that it is not ready to transmit or receive by the SPI_MRDY signal, or if the LISA-U2 series module itself does not transfer data. 1.9.4.3 IPC communication examples In the following, three IPC communication scenarios are described:

Slave-initiated data transfer, with a sleeping master Master-initiated data transfer, with a sleeping slave Slave-ended data transfer Slave-initiated transfer with a sleeping master SPI_MRDY 2 SPI_SRDY 1 3 4 5 DATA EXCHG Header Data Header Figure 42: Data transfer initiated by the LISA-U2 module (slave), with a sleeping application processor (master) When the master is sleeping (idle mode), the following actions happen:

1. The slave indicates to the master that is ready to send data by activating SPI_SRDY. 2. When the master becomes ready to send, it signalizes this by activating SPI_MRDY. 3. The master activates the clock and the two processors exchange the communication header and 4. data. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK. 5. After the preparation, the slave activates SPI_SRDY again and waits for SPI_SCLK activation. When the clock is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3. UBX-13001118 - R25 System description Page 81 of 182 Master-initiated transfer with a sleeping slave LISA-U2 series - System Integration Manual 2 3 1 SPI_MRDY SPI_SRDY DATA EXCHG Header Data Header 4 5 Figure 43: Data transfer initiated by the application processor (master) with a sleeping LISA-U2 module (slave) When the slave is sleeping (idle mode), the following actions happen:

1. The master wakes the slave by setting the SPI_MRDY line active. 2. As soon as the slave is awake, it signals it by activating SPI_SRDY. 3. The master activates the clock and the two processors exchange the communication header and 4. data. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK. 5. After the preparation, the slave activates SPI_SRDY again and waits for SPI_SCLK activation. When the clock is active, all data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3. Slave ended transfer SPI_MRDY SPI_SRDY 4 1 5 2 3 DATA EXCHG Header Data Figure 44: Data transfer terminated and then restarted by LISA-U2 module (slave) Starting from the state where data transfer is ongoing, the following actions will happen:

1. 2. In case of the last transfer, the master will lower its SPI_MRDY line. After the data transfer is finished, the line must be low. If the slave has already set its SPI_SRDY line, the master must raise its line to initiate the next transfer (slave-waking-procedure). If the data has been exchanged, the slave will deactivate SPI_SRDY to process the received information. This is the normal behavior. 3. The slave will indicate the master that is ready to send data by activating SPI_SRDY. 4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional, when SPI_MRDY is low before. 5. The slave indicates immediately after a transfer termination that it is ready to start transmission again. In this case, the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or low: the master only needs to ensure that the SPI_SRDY change will be detected correctly via interrupt. For more details regarding IPC communication protocol, see the SPI Application Note [17]. UBX-13001118 - R25 System description Page 82 of 182 LISA-U2 series - System Integration Manual 1.9.4.4 IPC application circuits SPI_MOSI is the data line input for the module since it runs as an SPI slave: it must be connected to the data line output (MOSI) of the application processor that runs as an SPI master. SPI_MISO is the data line output for the module since it runs as an SPI slave: it must be connected to the data line input (MISO) of the application processor that runs as an SPI master. SPI_SCLK is the clock input for the module since it runs as an SPI slave: it must be connected to the clock line output (SCLK) of the application processor that runs as an SPI master. SPI_MRDY is an input for the module able to detect an external interrupt which comes from the SPI master: it must be connected to a GPIO of the application processor that runs as an SPI master. SPI_SRDY is an output for the module that must be connected to a pin of the application processor that runs as an SPI master able to detect an external interrupt which comes from the module. Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. It is recommended to match the length of SPI signals. If a 1.8 V application processor is used, the SPI master pins can be directly connected to the specific LISA-U2 SPI slave pins as described in Figure 45. It is recommended to tri-state the output pins of the SPI Master (i.e. set in high impedance mode) when the LISA-U2 module is in power-down mode, when the external reset is forced low, and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a clean boot of the module. Figure 45: IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 1.8V SPI master If a 3.0 V SPI master application processor is used, implement a circuit with appropriate unidirectional voltage translators with tri-state (i.e. high impedance) mode controlled by the application processor, as illustrated in Figure 46. UBX-13001118 - R25 System description Page 83 of 182 Application processor

(1.8V SPI master) LISA-U2 series

(1.8V SPI slave) Interrupt MOSI MISO SCLK GPIO GND 56 SPI_MOSI 57 SPI_MISO 55 SPI_SCLK 58 SPI_SRDY 59 SPI_MRDY GND LISA-U2 series - System Integration Manual U1 U2 Figure 46: IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 3.0 V SPI master Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 36: Parts for IPC / SPI Interface application circuit connecting LISA-U2 series 1.8V SPI slave to a 3.0 V SPI master If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins can be left unconnected. Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a clean boot of the module. If the external signals connected to the cellular module cannot be tri-

stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two circuit connections and set to high impedance during module power-down mode, when external reset is forced low, and during the power-on sequence. 1.9.5 MUX protocol (3GPP TS 27.010) LISA-U2 modules have a software layer with MUX functionality, as peer the 3GPP TS 27.010 Multiplexer Protocol [6], available either on the UART or on the SPI physical link. The USB interface does not support the multiplexer protocol. This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART or SPI): the user can concurrently use the AT command interface on one MUX channel and Packet-Switched / Circuit-Switched data communication on another MUX channel. The multiplexer protocol can be used on one serial interface (UART or SPI) at a time. Each session consists of a stream of bytes transferring various kinds of data such as SMS, CBS, PSD, GNSS, and AT commands in general. This permits, for example, SMS to be transferred to the DTE when a data connection is in progress. UBX-13001118 - R25 System description Page 84 of 182 Application processor

(3.0V SPI master) Unidirectional Voltage Translator 1V8 3V0 C1 VCCB C2 4 V_INT LISA-U2 series

(1.8V SPI slave) VCC MOSI MISO SCLK Interrupt GPIO GPIO GND VCCA DIR1 DIR3 A1 A2 A3 A4 OE DIR2 DIR4 U1 DIR2 A1 A2 OE U1 DIR1 U2 B1 B2 B3 B4 GND B1 B2 GND 3V0 Unidirectional Voltage Translator 1V8 VCCA VCCB C3 C4 56 SPI_MOSI 57 SPI_MISO 55 SPI_SCLK 58 SPI_SRDY 59 SPI_MRDY GND LISA-U2 series - System Integration Manual The following virtual channels are defined:

Channel 0: control channel Channel 1 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) For more details, see the Mux implementation Application Note [14]. If the module switch-off AT command +CPWROFF is issued over a multiplexer channel, the completion of the module power-off sequence could require up to 2.5 s, after the module OK reply. Therefore, if the application processor (AP) controls the VCC supply of the module, the AP should disable the multiplexer protocol and then issue the AT+CPWROFF command over the used AT interface, or otherwise the AP should issue the AT+CPWROFF command over a multiplexer channel and wait 2.5 s after OK reception before removing the module VCC supply. UBX-13001118 - R25 System description Page 85 of 182 LISA-U2 series - System Integration Manual 1.10 DDC (I2C) interface 1.10.1 Overview An I2C bus compatible Display Data Channel (DDC) interface for communication with u-blox GNSS receivers is available on the LISA-U2 modules. The communication between a u-blox cellular module and a u-blox GNSS receiver is only provided by this DDC (I2C) interface. Name Description Remarks SCL SDA I2C bus clock line I2C bus data line Table 37: DDC pins Open drain. External pull-up required. Open drain. External pull-up required. The DDC (I2C) interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to the accessible points. u-blox has implemented special features in LISA-U2 series cellular modules to ease the design effort required for the integration of a u-blox cellular module with a u-blox GNSS receiver. Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access to the GNSS receiver directly via the cellular module: it relays control messages to the GNSS receiver via a dedicated DDC (I2C) interface. A 2nd interface connected to the GNSS receiver is not necessary:

AT commands via the serial interfaces (UART, USB, SPI) of the cellular module allows full control of the GNSS receiver from any host processor. LISA-U2 modules feature embedded GPS aiding that is a set of specific features developed by u-blox to enhance GNSS performance, decreasing Time-To-First-Fix (TTFF), thus allowing to calculate the position in a shorter time interval with higher accuracy. The DDC (I2C) interface of all LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and with external I2C devices as an audio codec: the cellular module acts as an I2C master which can communicate to more I2C slaves as allowed by the I2C bus specifications [8]. See section 1.11 for an application circuit with an external audio codec. For more details regarding the handling of the DDC (I2C) interface and the GPS aiding features, see the u-blox AT Commands Manual [2] (AT+UGPS, AT+UGPRF, AT+UGPIOC, +UI2CO, +UI2CW,

+UI2CR, +UI2CREGR, +UI2CC AT commands) and the GNSS Implementation Application Note [15]. 1.10.2 DDC application circuits 1.10.2.1 General considerations The DDC I2C-bus master interface of LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and with other external I2C-bus slaves as an audio codec: besides the general considerations reported below, see section 1.10.2.2 for specific guidelines and application circuit examples for the connection to u-blox GNSS receivers and see section 1.11 for an application circuit example with an external audio codec I2C-bus slave. To be compliant with the I2C bus specifications, the module bus interface pads are open drain output and pull up resistors must be mounted externally. Resistor values must conform to the I2C bus UBX-13001118 - R25 System description Page 86 of 182 LISA-U2 series - System Integration Manual specifications [8]: for example, 4.7 k resistors can be commonly used. Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins which are not tolerant to higher voltage values (e.g. 3.0 V). Connect the DDC (I2C) pull-ups to the V_INT 1.8 V supply source, or another 1.8 V supply source enabled after V_INT (e.g. as the GNSS 1.8 V supply present in the Figure 47 application circuit), as any external signal connected to the DDC (I2C) interface must not be set high when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least until the switch-on of the V_INT supply of DDC pins), to avoid latch-up of circuits and enable a clean boot of the module. See Figure 18 for the power-on sequence description and timings. DDC Slave-mode operation is not supported, the module can only act as a master. Two lines, the serial data (SDA) and serial clock (SCL), carry information on the bus. SCL is used to synchronize data transfers, and SDA is the data line. Since both lines are open drain outputs, the DDC devices can only drive them low or leave them open. The pull-up resistor pulls the line up to the supply rail if no DDC device is pulling it down to GND. If the pull-ups are missing, SCL and SDA lines are undefined and the DDC bus will not work. The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus will increase the capacitance. If the bus capacitance is increased, use pull-up resistors with a nominal resistance value less than 4.7 k, to match the I2C bus specifications [8] regarding rise and fall times of the signals. Capacitance and series resistance must be limited on the bus to match the I2C specifications

(1.0 s is the maximum allowed rise time on the SCL and SDA lines): route the connections as short as is possible. If the pins are not used as the DDC bus interface, they can be left unconnected. 1.10.2.2 Connection with u-blox GNSS receivers General considerations LISA-U2 modules support these GPS aiding types:

Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GPS aiding features can be used only if the DDC (I2C) interface of the cellular module is connected to the u-blox GNSS receivers. The GPIO pins of the LISA-U2 series modules can handle:

GNSS receiver power-on/off (GNSS supply enable function provided by GPIO2) The wake-up from idle mode when the GNSS receiver is ready to send data (GNSS data ready The RTC synchronization signal to the GNSS receiver (GNSS RTC sharing function provided by function provided by GPIO3) GPIO4) UBX-13001118 - R25 System description Page 87 of 182 LISA-U2 series - System Integration Manual The GPIO2 is configured by default to provide the GNSS supply enable function (parameter

<gpio_mode> of AT+UGPIOC command set to 3 by default), to enable or disable the supply of the u-

blox GNSS receiver connected to the cellular module by the AT+UGPS command. The pin is set as Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1 command is set to 0 (default setting) The pin must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board. The GNSS supply enable function improves the power consumption of the GNSS receiver. When the GNSS functionality is not required, the GNSS receiver can be completely switched off by the cellular module that is controlled by the application processor with AT commands. The GPIO3 is by default configured to provide the GNSS data ready function (parameter

<gpio_mode> of AT+UGPIOC command set to 4 by default), to sense when the u-blox GNSS receiver connected to the cellular module is ready to send data by the DDC (I2C) interface. The pin will be set as Input, to sense the line status, waking up the cellular module from idle mode when the u-blox GNSS receiver is ready to send data by the DDC (I2C) interface, if the parameter <mode> of +UGPS AT command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GNSS data ready function must be connected to the data ready output of the u-blox GNSS receiver (i.e. the pin TxD1 of the u-blox GNSS receiver) on the application board. The GNSS data ready function provides an improvement in the power consumption of the cellular module. When power saving is enabled in the cellular module by the AT+UPSV command and the GNSS receiver does not send data by the DDC (I2C) interface, the module automatically enters idle mode whenever possible. With the GNSS data ready function the GNSS receiver can indicate to the cellular module that it is ready to send data by the DDC (I2C) interface: the GNSS receiver can wake up the cellular module if it is in idle mode, so that data sent by the GNSS receiver will not be lost by the cellular module even if power saving is enabled. The GPIO4 is by default configured to provide the GNSS RTC sharing function (parameter

<gpio_mode> of +UGPIOC AT command set to 5), to provide an RTC (Real Time Clock) synchronization signal at the power-up of the u-blox GNSS receiver connected to the cellular module. The pin will be set as Output, to provide an RTC synchronization signal to the u-blox GNSS receiver for RTC sharing if 1 and the parameter is set to the parameter <mode> of AT+UGPS command

<GPS_IO_configuration> of +UGPRF AT command is set to 32 Output / Low, otherwise (default setting) The pin that provides the GNSS RTC sharing function must be connected to the RTC synchronization signal of the u-blox GNSS receiver (i.e. the pin EXTINT0 of the u-blox GNSS receiver) on the application board. The GNSS RTC sharing function provides improved GNSS receiver performance, decreasing the Time-To-First-Fix (TTFF), and thus allowing the calculation of the position in a shorter time with higher accuracy. When GPS local aiding is enabled, the cellular module automatically uploads data such as position, time, ephemeris, almanac, health and ionospheric parameters from the GNSS receiver into its local memory, and restores this to the GNSS receiver at the next power-up of the GNSS receiver. UBX-13001118 - R25 System description Page 88 of 182 LISA-U2 series - System Integration Manual Connection with u-blox 1.8 V GNSS receivers Figure 47 shows an application circuit for connecting a LISA-U2 cellular module to a u-blox 1.8 V GNSS receiver. The SDA and SCL pins of the LISA-U2 cellular module are directly connected to the corresponding I2C pins of the u-blox 1.8 V GNSS receiver, with appropriate pull-up resistors connected to the 1.8 V GNSS supply enabled after the V_INT supply of the I2C pins of the LISA-U2 cellular module. GPIO3 and GPIO4 pins are directly connected respectively to the TxD1 and EXTINT0 pins of the u-

blox 1.8 V GNSS receiver to provide GNSS data ready and GNSS RTC sharing functions. A pull-down resistor is mounted on the GPIO4 line for correct GNSS RTC sharing function implementation. A pull-down resistor is mounted on the GPIO2 line to avoid a switch-on of the u-blox GNSS receiver when the LISA-U2 module is in the internal reset state. The V_BCKP supply output of the LISA-U2 cellular module is connected to the V_BCKP backup supply input pin of the GNSS receiver to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start (depending on the duration of the GNSS VCC outage) and to maintain the configuration settings saved in the backup RAM. GNSS data ready and GNSS RTC sharing functions are not supported by all u-blox GNSS receivers HW or ROM/FW versions. See the GNSS Implementation Application Note [15] or the Hardware Integration Manual of the u-blox GNSS receivers for the supported features. Figure 47: DDC Application circuit for u-blox 1.8 V GNSS receiver Reference Description Part Number - Manufacturer R1, R2, R4 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp R3 U1 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual Table 38: Components for DDC application circuit for u-blox 1.8 V GNSS receiver UBX-13001118 - R25 System description Page 89 of 182 u-blox GNSS 1.8 V receiver V_BCKP VCC SDA2 SCL2 TxD1 EXTINT0 1V8 GPS LDO Regulator VMAIN 1V8 1V8 C1 R1 R2 OUT IN SHDN GND U1 LISA-U2 series 2 V_BCKP 21 GPIO2 46 SDA 45 SCL 23 GPIO3 24 GPIO4 R3 R4 LISA-U2 series - System Integration Manual As an alternative to using an external voltage regulator, the V_INT supply output of LISA-U2 cellular modules can be used to supply a u-blox 1.8 V GNSS receiver of the u-blox 6 generation (or later u-blox generation). The V_INT supply is able to withstand the maximum current consumption of these positioning receivers. The V_INT supply output provides low voltage ripple (up to 15 mVpp) when the module is in active mode or in connected mode, but it provides higher voltage ripple (up to 70 mVpp) when the module is in the low-power idle mode with the power saving configuration enabled by AT+UPSV (see the u-blox AT Commands Manual [2]). According to the voltage ripple characteristic of the V_INT supply output:

The power saving configuration cannot be enabled to use V_INT output to properly supply any 1.8 V GNSS receiver of the u-blox 6 generation and any 1.8 V GNSS receiver of the u-blox 7 generation or any newer u-blox GNSS receiver generation with TCXO. The power saving configuration can be enabled to use V_INT output to properly supply any 1.8 V GNSS receiver of the u-blox 7 generation or any more recent u-blox GNSS receiver generation without TCXO. Additional filtering may be needed to properly supply an external LNA, depending on the characteristics of the used LNA, adding a series ferrite bead and a bypass capacitor (e.g. the Murata BLM15HD182SN1 ferrite bead and the Murata GRM1555C1H220J 22 pF capacitor) at the input of the external LNA supply line. See the GNSS Implementation Application Note [15] for additional guidelines on using the V_INT supply output of LISA-U2 cellular modules to supply a u-blox 1.8 V GNSS receiver. UBX-13001118 - R25 System description Page 90 of 182 LISA-U2 series - System Integration Manual Connection with u-blox 3.0 V GNSS receivers Figure 48 shows an application circuit for connecting a LISA-U2 cellular module to a u-blox 3.0 V GNSS receiver:

As the SDA and SCL pins of the LISA-U2 cellular module are not tolerant up to 3.0 V, the connection to the related I2C pins of the u-blox 3.0 V GNSS receiver must be provided using a proper I2C-bus Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down feature so that the GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular supply), with proper pull-up resistors. As the GPIO3 and GPIO4 pins of the LISA-U2 cellular module are not tolerant up to 3.0 V, the connection to the related pins of the u-blox 3.0 V GNSS receiver must be provided using a proper Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up before the V_INT 1.8 V cellular supply). The V_BCKP supply output of the cellular module can be directly connected to the V_BCKP backup supply input pin of the GNSS receiver as in the application circuit for a u-blox 1.8 V GNSS receiver. Figure 48: DDC Application circuit for a u-blox 3.0 V GNSS receiver Reference Description Part Number - Manufacturer R1, R2, R4, R5, R7 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp R3 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1, C1 U2 U3 Voltage Regulator for GNSS receiver and related output bypass capacitor See GNSS receiver Hardware Integration Manual I2C-bus Bidirectional Voltage Translator TCA9406DCUR - Texas Instruments Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 39: Components for DDC application circuit for a u-blox 3.0 V GNSS receiver UBX-13001118 - R25 System description Page 91 of 182 u-blox GNSS 3.0 V receiver V_BCKP VCC 3V0 GPS LDO Regulator VMAIN C1 OUT IN SHDN GND U1 I2C-bus Bidirectional Voltage Translator VCCB VCCA R3 1V8 C2 R1 R2 OE C3 R4 R5 LISA-U2 series 2 V_BCKP 21 GPIO2 4 V_INT 46 SDA 45 SCL SDA2 SCL2 TxD1 EXTINT0 3V0 C4 Unidirectional Voltage Translator 1V8 VCCA VCCB C5 SDA_B SDA_A SCL_B SCL_A GND U2 DIR1 A1 A2 U3 DIR2 GND B1 B2 OE 23 GPIO3 24 GPIO4 R7 LISA-U2 series - System Integration Manual 1.11 Audio Interface All LISA-U2 series modules provide two bidirectional 4-wire I2S digital audio interfaces for connecting to remote digital audio devices:

First 4-wire I2S digital audio interface (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) Second 4-wire I2S digital audio interface (I2S1_CLK, I2S1_RXD, I2S1_TXD and I2S1_WA) Audio signal routing can be controlled by the dedicated AT command +USPM (see the u-blox AT Commands Manual [2]). This command allows setting the audio path mode, composed by the uplink audio path and the downlink audio path. Each uplink and downlink path mode defines the physical input / output, the set of parameters to process the uplink audio signal (uplink gains, uplink digital filters, echo canceller parameters) and the set of parameters to process the downlink audio signal (downlink gains, downlink digital filters and sidetone). The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in two profiles in the non-

volatile memory (see the u-blox AT Commands Manual [2] for the audio parameters tuning commands). LISA-U2 series modules can act as I2S master or I2S slave. In master mode, the word alignment and clock signals of the I2S digital audio interface are generated by the module. In slave mode, these signals must be generated by the remote device. Table 40 lists the signals related to the digital audio function. Name Description I2S_TXD I2S_RXD I2S_CLK I2S transmit data I2S receive data I2S clock I2S_WA I2S word alignment I2S1_TXD I2S1_RXD I2S1_CLK Second I2S transmit data Second I2S receive data Second I2S clock I2S1_WA Second I2S word alignment CODEC_CLK Digital clock output Table 40: Digital audio interface pins Remarks Module output Module input Module output in master mode Module input in slave mode Module output in master mode Module input in slave mode Module output Module input Module output in master mode Module input in slave mode Module output in master mode Module input in slave mode Digital clock output for external audio codec Configurable to 26 MHz or 13 MHz The I2S interfaces and CODEC_CLK pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting a general purpose ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to the I2S interfaces pins, close to the accessible points, and a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002) on the line connected to CODEC_CLK pin, close to the accessible point. UBX-13001118 - R25 System description Page 92 of 182 LISA-U2 series - System Integration Manual The I2S interface can be set to two modes using the <I2S_mode> parameter of the AT+UI2S command:

The I2S interface can be set to two configurations, by the <I2S_Master_Slave> parameter of AT+UI2S:

The sample rate of transmitted/received words can be set, by the <I2S_sample_rate> parameter of AT+UI2S, to:

PCM mode Normal I2S mode Master mode Slave mode 11.025 kHz 12 kHz 16 kHz 8 kHz 22.05 kHz 24 kHz 32 kHz 44.1 kHz 48 kHz The <main_uplink> and <main_downlink> parameters of the AT+USPM command must be properly configured to select the I2S digital audio interfaces paths (for more details, see the u-blox AT Commands Manual [2]):

<main_uplink> must be properly set to select:

o the first I2S interface (using I2S_RXD module input) o the second I2S interface (using I2S1_RXD module input)

<main_downlink> must be properly set to select:

o the first I2S interface (using I2S_TXD module output) o the second I2S interface (using I2S1_TXD module output) Parameters of the digital path can be configured and saved as the normal analog paths, using appropriate path parameters as described in the u-blox AT Commands Manual [2], +USGC, +UMGC,

+USTN AT command. Analog gain parameters are not used. The I2S receive data input and the I2S transmit data output signals can use the following resources:

Digital filters and digital gains are available in both uplink and downlink directions. They can be correctly configured with the AT commands Ringer tone and service tone are mixed on the TX path when active (downlink) The HF algorithm acts on the I2S path See the u-blox AT Commands Manual [2] (AT+UI2S command) for the possible settings of the I2S interface. UBX-13001118 - R25 System description Page 93 of 182 LISA-U2 series - System Integration Manual 1.11.1 I2S interface - PCM mode Main features of the I2S interface in PCM mode:

I2S runs in PCM - short alignment mode (configurable by AT commands) I2S word alignment signal can be configured to 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz I2S word alignment toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits I2S clock frequency depends on the frame length and <sample_rate>. Can be 17 x <sample_rate>

or 18 x <sample_rate>

I2S transmit and I2S receive data are 16-bit words long with the same sampling rate as I2S word alignment, mono. Data is in 2s complement notation. MSB is transmitted first When I2S word alignment toggles high, the first synchronization bit is always low. The second synchronization bit (present only in case of 2 bit long I2S word alignment configuration) is MSB of the transmitted word (MSB is transmitted twice in this case) I2S transmit data changes on the I2S clock rising edge, I2S receive data changes on the I2S clock falling edge 1.11.2 I2S interface - Normal I2S mode Normal I2S supports:

16-bit words Mono interface Configurable sample rate: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz Main features of the I2S interface in normal I2S mode:

I2S word alignment signal always runs at <sample_rate> and synchronizes 2 channels (timeslots on word alignment high, word alignment low) I2S transmit data is composed of 16-bit words, dual mono (the words are written on both channels). Data are in 2s complement notation. MSB is transmitted first. The bits are written on I2S clock rising or falling edge (configurable) I2S receive data is read as 16-bit words, mono (words are read only on the timeslot with WA high). Data is read in 2s complement notation. MSB is read first. The bits are read on the I2S clock edge opposite to the I2S transmit data writing edge (configurable) I2S clock frequency is 16 bits x 2 channels x <sample_rate>

The modes are configurable through a specific AT command (see the u-blox AT Commands Manual [2], +UI2S AT command) and the following parameters can be set:

MSB can be 1 bit delayed or non-delayed on I2S word alignment edge I2S transmit data can change on the rising or falling edge of the I2S clock signal (rising edge in this example) I2S receive data are read on the opposite front of the I2S clock signal UBX-13001118 - R25 System description Page 94 of 182 LISA-U2 series - System Integration Manual 1.11.3 I2S interface application circuits LISA-U2 I2S digital audio interfaces can be connected to an external digital audio device for voice applications. Any external digital audio device compliant with the configuration of the digital audio interface of the cellular module can be used, given that the external digital audio device must provide:

The opposite role: slave or master for LISA-U2 modules that may act as master or slave The same mode and frame format: PCM / short alignment or Normal I2S mode / long alignment mode with o data in 2s complement notation o MSB transmitted first o word length = 16-bit o frame length = 17-bit or 18-bit in PCM / short alignment mode (16 + 1 or 16 + 2 clock cycles, with Word Alignment / Synchronization signal set high for 1 clock cycle or 2 clock cycles), or frame length = 32-bit in Normal I2S mode / long alignment mode (16 x 2 clock cycles) o The same sample rate and serial clock frequency: as the clock frequency depends on the frame length and the sample rate, the clock frequency can be o o 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate> in PCM / short alignment mode, or 16 x 2 x <I2S_sample_rate> in Normal I2S mode / long alignment mode Compatible voltage levels (1.80 V typ.), otherwise it is recommended to connect the 1.8 V digital audio interface of the module to the external 3.0 V (or similar) digital audio device by means of appropriate unidirectional voltage translators (e.g. Texas Instruments SN74AVC4T774 or SN74AVC2T245), using the module V_INT output as a 1.8 V supply for the voltage translators on the module side For the appropriate selection of a compliant external digital audio device, see the +UI2S AT command description in the u-blox AT Commands Manual [2] for further details regarding the capabilities and the possible settings of the I2S digital audio interface of LISA-U2 series modules. Figure 49 shows an application circuit with a generic digital audio device. Figure 49: I2S interface application circuit with a generic digital audio device Because, in general, any external digital audio device compliant to the configuration of the digital audio interface of the cellular module can be used with LISA-U2 series modules, an appropriate specific application circuit must be implemented and configured according to the particular external digital audio device or audio codec used and according to the application requirements. UBX-13001118 - R25 System description Page 95 of 182 LISA-U2 series I2S_TXD 42 I2S_RXD 44 I2S_CLK 43 I2S_WA 41 GND 1.8 V digital audio device I2S Data Input I2S Data Output I2S Clock I2S Word Alignment GND LISA-U2 series - System Integration Manual Examples of manufacturers offering compatible audio codec parts, suitable to provide basic analog audio voice capability on the application device, are the following:

Maxim Integrated (as the MAX9860, MAX9867, MAX9880A audio codecs) Texas Instruments / National Semiconductor Cirrus Logic / Wolfson Microelectronics Nuvoton Technology Asahi Kasei Microdevices Realtek Semiconductor Figure 50 and Table 41 describe an application circuit for I2S digital audio interfaces of LISA-U2 series modules, providing voice capability using an external audio voice codec. DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface. An I2S digital audio interface of the LISA-U2 series modules that acts as an I2S master is connected to the digital audio interface of the external audio codec (that acts as an I2S slave). The first I2S interface can be used as well as the second I2S interface of the cellular module. The CODEC_CLK digital output clock of the cellular module is connected to the clock input of the external audio codec to provide the clock reference. Signal integrity of the high speed lines may be degraded if the PCB layout is not optimal, especially when the CODEC_CLK clock line or also the I2S digital audio interface lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. The external audio codec is controlled by the cellular module using the DDC (I2C) interface: this interface can be used to communicate with u-blox GNSS receivers and at the same time to control an external audio codec on all LISA-U2 series modules. The V_INT supply output of the cellular module provides the supply to the external audio codec, defining a suitable voltage level for the digital interfaces. Additional components are provided for EMC and ESD immunity conformity according to European Norms for Radio Equipment Directive (2014/53/EU) and EMC Directive (2014/30/EU) compliance. The recommended parts for EMC and ESD immunity conformity are: a 10 nF bypass capacitor (e.g. Murata GRM155R71C103KA88) and a proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) provided on each microphone line input and speaker line output of the external codec as illustrated in Figure 50 and Table 41. Figure 50: I2S interface application circuit with an external audio codec to provide voice capability UBX-13001118 - R25 System description Page 96 of 182 LISA-U2 series V_INT 4 SDA 46 SCL 45 I2S1_TXD 40 I2S1_RXD 39 I2S1_CLK I2S1_WA 53 54 CODEC_CLK 52 GND 1V8 R1 R2 R3 Audio Codec VDD IRQn MICBIAS C1 C2 C3 C4 R4 SDA SCL SDIN SDOUT BCLK LRCLK MCLK MICLP MICLN C5 C6 MICGND OUTP OUTN EMI EMI 3 4 R5 C12 C11 C8 C7 GND U1 C14 C13 C10 C9 Microphone Connector MIC EMI1 EMI2 Speaker Connector SPK J1 J2 D1 D2 LISA-U2 series - System Integration Manual C1 C3 J1 J2 MIC R1, R2 R3 R4, R5 SPK U1 Reference Description Part Number Manufacturer 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 Murata C2, C4, C5, C6 1 F Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J105KE19 Murata 10 F Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 Murata C7, C8, C9, C10 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 Murata C11, C12, C13, C14 10 nF Capacitor Ceramic X5R 0402 10% 50V GRM155R71C103KA88 Murata D1, D2 Low Capacitance ESD Protection USB0002RP or USB0002DP AVX EMI1, EMI2, EMI3, EMI4 Chip Ferrite Bead Noise/EMI Suppression Filter 1800 Ohm at 100 MHz, 2700 Ohm at 1 GHz BLM15HD182SN1 Murata Microphone Connector Speaker Connector 2.2 k Electret Microphone Various manufacturers Various manufacturers Various manufacturers 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp 10 k Resistor 0402 5% 0.1 W RC0402JR-0710KL - Yageo Phycomp 2.2 k Resistor 0402 5% 0.1 W RC0402JR-072K2L Yageo Phycomp 32 Speaker Various manufacturers 16-Bit Mono Audio Voice Codec MAX9860ETG+ - Maxim Table 41: Example of components for audio voice codec application circuit Any external signal connected to the digital audio interface must be tri-stated or set low when the module is in power-down mode and during the module power-on sequence (at least until the activation of the V_INT supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-

stated or set low, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set it to high impedance during the module power-down mode and during the module power-on sequence. If the I2S digital audio pins are not used, they can be left unconnected on the application board. 1.11.4 Voiceband processing system The voiceband processing on the LISA-U2 modules is implemented in the DSP core inside the baseband chipset. The external digital audio devices can be interfaced directly to the DSP digital processing part via the I2S digital interface. With exception of the speech encoder/decoder, audio processing can be controlled by AT commands. The audio processing is implemented within the different blocks of the voiceband processing system:

Sample-based Voice-band Processing (single sample processed at 16 kHz for Wide Band AMR codec or 8 kHz for all other speech codecs) Frame-based Voice-band Processing (frames of 320 samples for Wide Band AMR codec or 160 samples for all other speech codecs are processed every 20 ms) These blocks are connected by buffers (circular buffer and voiceband sample buffer) and sample rate converters (for 8 / 16 to 47.6 kHz conversion). The voiceband audio processing implemented in the DSP core of LISA-U2 series modules is summarized in Figure 51. UBX-13001118 - R25 System description Page 97 of 182 LISA-U2 series - System Integration Manual Figure 51: Audio processing system of LISA-U2 series modules LISA-U2 modules audio signal processing algorithms are:

Speech encoding (uplink) and decoding (downlink).The following speech codecs are supported in firmware on the DSP for speech encoding and decoding:

o GERAN GMSK codecs GSM HR (GSM Half Rate) GSM FR (GSM Full Rate) GSM EFR (GSM Enhanced Full Rate) HR AMR (GSM Half Rate Adaptive Multi Rate - Narrow Band) FR AMR (GSM Full Rate Adaptive Multi Rate - Narrow Band) FR AMR-WB (GSM Full Rate Adaptive Multi Rate - Wide Band) o UTRAN codecs:

UMTS AMR2 (UMTS Adaptive Multi Rate version 2 Narrow Band) UMTS AMR-WB (UMTS Adaptive Multi Rate Wide Band) Mandatory sub-functions:

o Discontinuous transmission, DTX (GSM 46.031, 46.041, 46.081 and 46.093 standards) o Voice activity detection, VAD (GSM 46.032, 46.042, 46.082 and 46.094 standards) o Background noise calculation (GSM 46.012, 46.022, 46.062 and 46.092 standards) Function configurable via specific AT commands (see the u-blox AT Commands Manual [2]) o Signal routing: +USPM command o Analog amplification, Digital amplification: +USGC, +CLVL, +CRSL, +CMUT command o Digital filtering: +UUBF, +UDBF commands o Hands-free algorithms (echo cancellation, Noise suppression, Automatic Gain control) +UHFP command o Sidetone generation (feedback of uplink speech signal to downlink path): +USTN command o Playing/mixing of alert tones:

Service tones: Tone generator with 3 sinus tones +UPAR command User generated tones: Tone generator with a single sinus tone +UTGN command PCM audio files (for prompting): The storage format of PCM audio files is 8 kHz sample rate, signed 16 bits, little endian, mono UBX-13001118 - R25 System description Page 98 of 182 I2S_RXD Uplink Digital Gain I2S1_RXD I2Sx RX Switch UBF 1/5 UBF 2/6 UBF 3/7 UBF 4/8 Hands-

free To Radio TX Tone Generator Sidetone Scal_Rec Digital Gain I2S1_TXD I2Sx TX Switch I2S_TXD Legend:

UBF= Uplink Biquad Filter DBF = Downlink Biquad Filter DBF 4/8 DBF 3/7 DBF 2/6 DBF 1/5 Speech level From Radio RX Mix_Afe PCM Player LISA-U2 series - System Integration Manual 1.12 General Purpose Input/Output (GPIO) LISA-U2 series modules provide up to 14 pins (GPIO1-14) which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands (for further details, see the u-blox AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW, +UGPS, +UGPRF,

+USPM). The following functions are available in the LISA-U2 modules:

GSM Tx burst indication:

GPIO1 pin can be configured by AT+UGPIOC to indicate when a GSM Tx burst/slot occurs, setting the parameter <gpio_mode> of AT+UGPIOC command to 9. No GPIO pin is configured by default to provide the GSM Tx burst indication function. The pin configured to provide the GSM Tx burst indication function is set as Output / High, since ~10 s before the start of first Tx slot, until ~5 s after the end of last Tx slot Output / Low, otherwise The pin configured to provide the GSM Tx burst indication function can be connected on the application board to an input pin of an application processor to indicate when a GSM Tx burst/slot occurs. GNSS supply enable:

The GPIO2 is by default configured by AT+UGPIOC command to enable or disable the supply of the u-

blox GNSS receiver connected to the cellular module. The GPIO1, GPIO3, GPIO4 or GPIO5 pins can be configured to provide the GNSS supply enable function, alternatively to the default GPIO2 pin, setting the parameter <gpio_mode> of AT+UGPIOC command to 3. The GNSS supply enable mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the GNSS supply enable function is set as Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1 command is set to 0 (default setting) The pin configured to provide the GNSS supply enable function must be connected to the active-

high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board. GNSS data ready:

Only the GPIO3 pin provides the GNSS data ready function, to sense when a u-blox GNSS receiver connected to the cellular module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode> of AT+UGPIOC command to 4. The pin configured to provide the GNSS data ready function will be set as Input, to sense the line status, waking up the cellular module from idle mode when the u-blox GNSS receiver is ready to send data via the DDC (I2C) interface; this is possible if the parameter <mode>

of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of AT+UGPRF command is set to 16 Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the GNSS data ready function must be connected to the data ready output of the u-blox GNSS receiver (i.e. the pin TxD1 of the u-blox GNSS receiver) on the application board. UBX-13001118 - R25 System description Page 99 of 182 LISA-U2 series - System Integration Manual GNSS RTC sharing:

Only the GPIO4 pin provides the GNSS RTC sharing function to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver connected to the cellular module, setting the parameter <gpio_mode> of AT+UGPIOC command to 5. The pin configured to provide the GNSS RTC sharing function will be set as Output, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver if the parameter <mode> of AT+UGPS command is set to 1 and parameter <GPS_IO_configuration>

of AT+UGPRF command is set to 32 Output / Low, otherwise (default setting) The pin that provides the GNSS RTC sharing function must be connected to the RTC synchronization input of the u-blox GNSS receiver (i.e. the pin EXTINT0 of the u-blox GNSS receiver) on the application board. SIM card detection:

The GPIO5 pin is by default configured by AT+UGPIOC command to detect SIM card presence. Only the GPIO5 pin can be configured to provide the SIM card detection function, setting the parameter <gpio_mode> of the AT+UGPIOC command to 7 (default setting). The pin configured to provide the SIM card detection function is set as Input with an internal active pull-down enabled, to sense SIM card presence The pin must be connected on the application board to SW2 pin of the SIM card holder, which must provide 2 pins for the mechanical card presence detection, with a 470 k pull-down resistor. SW1 pin of the SIM card holder must be connected to the V_INT pin of the module, by a 1 k pull-up resistor. See Figure 52 and section 1.8 for the application circuit. The GPIO5 signal will be pulled low by the pull-

down when a SIM card is not inserted in the holder, and will be pulled high by the pull-up when a SIM card is present. The GPIO5 pin is configured as an external interrupt to detect SIM card presence. An Unsolicited Result Code (URC) can be generated each time that there is a change of status (for more details, see the simind value of the <descr> parameter of +CIND and +CMER commands in the u-blox AT Commands Manual [2]). All LISA-U2 series modules provide the additional function SIM card hot insertion/removal on the GPIO5 pin, which can be enabled using the AT+UDCONF=50 command (for more details, see the u-blox AT Commands Manual [2]). Network status indication:

GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate network status (i.e. no service, registered home 2G network, registered home 3G network, registered visitor 2G network, registered visitor 3G network, voice or data 2G/3G call enabled), setting the parameter <gpio_mode> of AT+UGPIOC command to 2. No GPIO pin is configured by default to provide the Network status indication function. The Network status indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the Network status indication function is set as Continuous Output / Low, if no service (no network coverage or not registered) Cyclic Output / High for 100 ms, Output / Low for 2 s, if registered home 2G network Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 2 s, if registered as a home 3G network UBX-13001118 - R25 System description Page 100 of 182 LISA-U2 series - System Integration Manual Cyclic Output / High for 100 ms, Output / Low for 100 ms, Output / High for 100 ms, Output / Low for 2 s, if registered as a visitor 2G network (roaming) Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 100 ms, if registered as a visitor 3G network (roaming) Continuous Output / High, if voice or data 2G/3G call enabled The pin configured to provide the Network status indication function can be connected on the application board to an input pin of an application processor or it can drive a LED by a transistor with integrated resistors to indicate network status. Module status indication:

The GPIO1 and GPIO13 pins can be configured to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected modes, i.e. module switched on), properly setting the parameter <gpio_mode> of the AT+UGPIOC command to 10. No GPIO pin is configured by default to provide the Module status indication. The pin configured to provide the Module status indication function is set as Output / High, when the module is switched on (any operating mode during module normal operation: idle, active or connected mode) Output / Low, when the module is switched off (power-off mode) The Module status indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. Module operating mode indication:

The GPIO14 and GPIO5 pins can be configured to indicate module operating mode (idle mode versus active or connected modes), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 11. No GPIO pin is configured by default to provide the Module operating mode indication. The pin configured to provide the Module operating mode indication function is set as Output / High, when the module is in active or connected mode Output / Low, when the module is in idle mode (that can be reached if power saving is enabled by

+UPSV AT command: for further details, see the u-blox AT Commands Manual [2]) The Module operating mode indication mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. I2S digital audio interface:

The GPIO6, GPIO7, GPIO8, GPIO9 pins are by default configured as the second I2S digital audio interface (I2S1_RXD, I2S1_TXD, I2S1_CLK, I2S1_WA respectively). Only these pins can be configured as the second I2S digital audio interface, correctly setting the parameter <gpio_mode> of AT+UGPIOC command to 12 (default setting). SPI serial interface:

GPIO10, GPIO11, GPIO12, GPIO13 and GPIO14 pins are by default configured as the SPI / IPC serial interface (SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_SRDY and SPI_MRDY respectively). Only these pins can be configured as the SPI / IPC serial interface, correctly setting the parameter

<gpio_mode> of AT+UGPIOC command to 13 (default setting). UBX-13001118 - R25 System description Page 101 of 182 LISA-U2 series - System Integration Manual General purpose input:

All the GPIOs can be configured as input to sense a high or low digital level through the AT+UGPIOR command, setting the parameter <gpio_mode> of the AT+UGPIOC command to 1. The General purpose input mode can be provided on more than one pin at a time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is configured by default as General purpose input. The pin configured to provide the General purpose input function is set as Input, to sense high or low digital level by the AT+UGPIOR command. The pin can be connected on the application board to an output pin of an application processor to sense the digital signal level. General purpose output:

All the GPIOs can be configured as output to set the high or the low digital level through the AT+UGPIOW command, setting the parameter <gpio_mode> of the +UGPIOC AT command to 0. The General purpose output mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is configured by default as General purpose output. The pin configured to provide the General purpose output function is set as Output / Low, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 0 Output / High, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 1 The pin can be connected on the application board to an input pin of an application processor to provide a digital signal. Pad disabled:

All the GPIOs can be configured in tri-state with an internal active pull-down enabled, as a not used pin, setting the parameter <gpio_mode> of the +UGPIOC AT command to 255. The Pad disabled mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). The pin configured to provide the Pad disabled function is set as Tri-state with an internal active pull-down enabled Table 42 describes the configurations of all the GPIO pins. Pin Name Description Remarks 20 GPIO1 GPIO Input By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as:

Output Network Status Indication GNSS Supply Enable GSM Tx Burst Indication Module Status Indication By default, the pin is configured to provide GNSS Supply Enable function. Can be alternatively configured by the +UGPIOC command as:

Output Network Status Indication Pad disabled Input 21 GPIO2 GPIO UBX-13001118 - R25 System description Page 102 of 182 LISA-U2 series - System Integration Manual Pin Name Description Remarks 23 GPIO3 GPIO 24 GPIO4 GPIO 51 GPIO5 GPIO 39 I2S1_RXD /

GPIO6 2nd I2S receive data /

GPIO 40 I2S1_TXD /

GPIO7 2nd I2S transmit data /

GPIO 53 I2S1_CLK /

GPIO8 2nd I2S clock /

GPIO 54 I2S1_WA /

GPIO9 2nd I2S word alignment /

GPIO 55 SPI_SCLK /

GPIO10 SPI Serial Clock /

GPIO 56 SPI_MOSI /

GPIO11 SPI Data Line /

GPIO By default, the pin is configured to provide GNSS Data Ready function. Can be alternatively configured by the +UGPIOC command as:

Output Network Status Indication GNSS Supply Enable Pad disabled Input By default, the pin is configured to provide GNSS RTC sharing function. Can be alternatively configured by the +UGPIOC command as:

Output Network Status Indication GNSS Supply Enable Pad disabled Input Input By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as:

Output Network Status Indication GNSS Supply Enable Module Operating Mode Indication Pad disabled By default, the pin is configured as 2nd I2S receive data input. Can be alternatively configured by the +UGPIOC, +USPM commands as:

Output Pad disabled Input By default, the pin is configured as 2nd I2S transmit data output. Can be alternatively configured by the +UGPIOC, +USPM commands as:

Output Pad disabled Input By default, the pin is configured as 2nd I2S clock input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as:

Output Pad disabled Input By default, the pin is configured as 2nd I2S word alignment input/output. Can be alternatively configured by the +UGPIOC, +USPM commands as:

Output Pad disabled Input By default, the pin is configured as SPI Serial Clock Input:

Idle low (CPOL=0) Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as:

Output Pad disabled Input By default, the pin is configured as SPI Data Line Input:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Internal active pull-up to V_INT enabled Can be alternatively configured by the +UGPIOC command as:

Output Pad disabled Input UBX-13001118 - R25 System description Page 103 of 182 LISA-U2 series - System Integration Manual Pin Name Description Remarks 57 SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO 58 SPI_SRDY /

GPIO13 SPI Slave Ready /

GPIO By default, the pin is configured as SPI Slave Ready Output:

Idle low 59 SPI_MRDY /

GPIO14 SPI Master Ready /

GPIO By default, the pin is configured as SPI Data Line Output:

Shift data on rising clock edge (CPHA=1) Latch data on falling clock edge (CPHA=1) Idle high Can be alternatively configured by the +UGPIOC command as:

Output Pad disabled Input Can be alternatively configured by the +UGPIOC command as:

Output Module Status Indication Pad disabled Input By default, the pin is configured as SPI Master Ready Input:

Idle low Internal active pull-down to GND enabled Can be alternatively configured by the +UGPIOC command as:

Output Module Operating Mode Indication Pad disabled Input Table 42: GPIO pin configurations The GPIO pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the lines are externally accessible on the application board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. An application circuit for a typical GPIOs usage is described in Figure 52:

Network indication function provided by the GPIO1 pin GNSS supply enable function provided by the GPIO2 pin GNSS data ready function provided by the GPIO3 pin GNSS RTC sharing function provided by the GPIO4 pin SIM card detection function provided by the GPIO5 pin Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series with the GPIO. If the GPIO pins are not used, they can be left unconnected on the application board. Any external signal connected to GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low, and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the module cannot be tri-stated, insert a multi-

channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power-down mode, when the external reset is forced low, and during the power-on sequence. UBX-13001118 - R25 System description Page 104 of 182 LISA-U2 series - System Integration Manual Figure 52: GPIO application circuit Reference Description Part Number - Manufacturer R1 U1 R2 R3 R4 D1 J1 R5 R6 R7 DL1 T1 47 k Resistor 0402 5% 0.1 W Various manufacturers Voltage Regulator for GNSS receiver See GNSS Module Hardware Integration Manual 4.7 k Resistor 0402 5% 0.1 W 1 k Resistor 0402 5% 0.1 W 470 k Resistor 0402 5% 0.1 W Various manufacturers Various manufacturers Various manufacturers ESD Transient Voltage Suppressor USB0002RP or USB0002DP - AVX SIM Card Holder 10 k Resistor 0402 5% 0.1 W 47 k Resistor 0402 5% 0.1 W 820 Resistor 0402 5% 0.1 W LED Red SMT 0603 NPN BJT Transistor CCM03-3013LFT R102 - C&K Components (or equivalent) Various manufacturers Various manufacturers Various manufacturers BC847 - Infineon LTST-C190KRKT - Lite-on Technology Corporation Table 43: Components for a GPIO application circuit UBX-13001118 - R25 System description Page 105 of 182 LISA-U2 series u-blox GNSS 1.8 V receiver GPIO2 21 GPS Supply Enable 3V8 LDO Regulator 1V8 IN OUT VCC SHDN GND R1 U1 C1 GPIO3 23 GPIO4 24 GPS Data Ready GPS RTC Sharing V_INT 4 GPIO5 51 SIM Detection GPIO1 20 Network Indicator R2 SIM card holder R3 R4 D1 TxD1 EXTINT0 SW1 SW2 J1 R5 3V8 DL1 R7 T1 R6 LISA-U2 series - System Integration Manual The recommended application circuit for the module status indication function, provided by LISA-U2 series module GPIO1 and GPIO13 pins to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), is described in Figure 53. The logic level of the pin configured to provide the module status indication, that is set high when the module is switched on (with interfaces configured) and low when the module is switched off, is inverted by a transistor biased by the V_BCKP supply, which is generated by the module when a valid VCC is applied. A pull-down resistor is provided at the GPIO1 output (which provides module status indication) to fix a low level at inverting transistor input when GPIO1 is floating, i.e. when the module is switched off, so that high logic level is present at the application processor input when the module is switched off and low logic level when the module is switched on (i.e. the opposite logic level of the GPIO). Figure 53: Module status indication application circuit Reference Description Part Number - Manufacturer R1, R3 R2 T1 47 k Resistor 0402 5% 0.1 W 100 k Resistor 0402 5% 0.1 W NPN BJT Transistor Various manufacturers Various manufacturers BC847 - Infineon Table 44: Components for a module status indication application circuit 1.13 Reserved pins (RSVD) LISA-U2 modules have pins reserved for future use. All the RSVD pins, except pin number 5, can be left unconnected on the application board. Pin 5 (RSVD) must be connected to GND. UBX-13001118 - R25 System description Page 106 of 182 LISA-U2 series V_BCKP 2 GPIO1 20 Module Status Indication R1 Application processor Input (1.8V) R3 T1 R2 LISA-U2 series - System Integration Manual 1.14 Schematic for LISA-U2 module integration Figure 54 is an example of a schematic diagram where the LISA-U2 series module is integrated into an application board, using all the interfaces of the module. Figure 54: Example of a schematic diagram to integrate LISA-U2 modules in an application board, using all the interfaces UBX-13001118 - R25 System description Page 107 of 182 3V8

Ferrite Bead LISA-U2 series ANT 68 ANT_DIV 74 Main Tx/Rx Antenna Rx Diversity Antenna LISA-U230 only 3V8 LDO Regulator 1V8_GPS IN OUT VCC u-blox GNSS 1.8V Receiver GPIO2 21 SHDN 47k GND 4.7k 4.7k 61 VCC 62 VCC 63 VCC GND 2 V_BCKP GND 330F 100nF 10nF 15pF 68pF RTC back-

up 100F Application Processor 100k Open Drain Output Open Drain Output 1.8V DTE 19 PWR_ON 22 RESET_N Ferrite Bead 47pF 220nF SDA SCL GPIO3 GPIO4 46 45 23 24 0 0 0 0 TP TP TP TP 15 TXD 16 RXD 13 RTS 14 CTS 12 DTR 9 DSR 10 RI 11 DCD GND I2S1_TXD 40 I2S1_RXD 39 I2S1_CLK 53 I2S1_WA 54 CODEC_CLK 52 56 SPI_MOSI 57 SPI_MISO 55 SPI_SCLK 58 SPI_SRDY 59 SPI_MRDY GND I2S_RXD 44 I2S_CLK 43 I2S_TXD 42 I2S_WA 41 V_INT 4 18 VUSB_DET GPIO5 51 27 USB_D+

VSIM 50 100nF 26 USB_D-

GND SIM_IO 48 SIM_CLK 47 SIM_RST 49 TXD RXD RTS CTS DTR DSR RI DCD GND MOSI MISO SCLK GPIO GND Interrupt VBUS D+

D-

GND 3V8 USB 2.0 Host V_INT 1k SDA2 SCL2 TxD1 EXTINT0 V_INT 100nF 1F 10F V_INT Audio Codec MAX9860 10k VDD IRQn MICBIAS 1F 2.2k 1F 1F 2.2k SDA SCL MICLP SDIN MICLN SDOUT BCLK LRCLK MCLK EMI EMI OUTP OUTN MICGND 10nF 10nF 27pF 27pF ESD ESD EMI EMI MIC SPK 1.8V Digital Audio Device I2S Data Output I2S Clock I2S Data Input I2S Word Alligment SIM Card Holder SW1 SW2 CCVCC (C1) CCVPP (C6) CCIO (C7) CCCLK (C3) CCRST (C2) GND (C5) 1.8V SPI Master 10nF 10nF 27pF 27pF ESD ESD Network Indicator 470k 47pF 47pF 47pF 47pF 100nF ESD ESD ESD ESD ESD ESD 20 GPIO1 RSVD 5 LISA-U2 series - System Integration Manual 1.15 Approvals For all the certificates of compliancy and for the complete list of approvals (including countries and network operators approvals) of LISA-U2 series modules, see our website (http://www.u-

blox.com/) or contact the u-blox office or sales representative nearest you. Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications, typically called certification schemes that can be divided into three distinct categories:

Regulatory certification o Country specific approval required by local government in most regions and countries, as:

CE (Conformit Europenne) marking for European Union FCC (Federal Communications Commission) approval for United States Industry conformance certification o Telecom industry specific approval verifying interoperability between devices and networks:

GCF (Global Certification Forum), partnership between device manufacturers and network operators to ensure and verify global interoperability between devices and networks PTCRB (PCS Type Certification Review Board), created by United States network operators to ensure and verify interoperability between devices and North America networks Operator certification o Operator specific approval required by some mobile network operator:

AT&T network operator in United States Even if LISA-U2 modules are approved under all major certification schemes, the application device that integrates LISA-U2 modules must be approved under all the certification schemes required by the specific application device to be deployed in the market. The required certification scheme approvals and the related testing specifications differ depending on the country or the region where the device that integrates LISA-U2 modules will be deployed, on the corresponding vertical market of the device, on the type, features and functionalities of the whole application device, and on the network operators where the device must operate. The certification of the application device that integrates a LISA-U2 module and the compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. LISA-U2 modules are certified according to all capabilities and options stated in the Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to 3GPP TS 51.010-2 [9] and 3GPP TS 34.121-2 [10], is a statement of the implemented and supported capabilities and options of a device. The PICS document of the application device integrating LISA-U2 series modules must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see u-blox AT Commands Manual [2]. Check the specific settings required for mobile network operators approvals as they may differ from the AT commands settings defined in the module as integrated in the application device. 1.15.1 European Conformance CE mark LISA-U2 series modules have been evaluated against the essential requirements of the Radio Equipment Directive (2014/53/EU). In order to satisfy the essential requirements of the Radio Equipment Directive (2014/53/EU), the modules are compliant with the following standards:

UBX-13001118 - R25 System description Page 108 of 182 LISA-U2 series - System Integration Manual Radio Frequency spectrum efficiency (Article 3.2):

Electromagnetic Compatibility (Article 3.1b):

o EN 301 511 o EN 301 908-1 o EN 301 908-2 o EN 301 489-1 o EN 301 489-52 Safety (Article 3.1a):

o EN 60950-1 o EN 62311 The conformity assessment procedure for the LISA-U2 series modules, referred to in Article 17 and detailed in Annex II of the Radio Equipment Directive (2014/53/EU), has been followed. Thus, the following marking is included in the product:

Radiofrequency radiation exposure Information: this equipment complies with radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for LISA-U200 and LISA-U230 modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.37 dBi

(900 MHz, i.e. GSM 900 or UMTS FDD-8 band), 10.45 dBi (1800 MHz, i.e. GSM 1800), 14.10 dBi

(2100 MHz, i.e. UMTS FDD-1 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U201 modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 5.76 dBi (900 MHz, i.e. GSM 900 or UMTS FDD-8 band), 11.44 dBi (1800 MHz, i.e. GSM 1800 band), 13.70 dBi (2100 MHz, i.e. UMTS FDD-1 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U260 modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.11 dBi (900 MHz, i.e. GSM 900 band), 9.86 dBi (1800 MHz, i.e. GSM 1800 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U270 modules (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.22 dBi (900 MHz, i.e. GSM 900 or UMTS FDD-8 band), 10.50 dBi (1800 MHz, i.e. GSM 1800 band), 14.75 dBi (2100 MHz, i.e. UMTS FDD-1 band) for mobile and fixed or mobile operating configurations. 1.15.2 US Federal Communications Commission notice The Federal Communications Commission (FCC) IDs for the LISA-U2 modules are:

LISA-U200: XPYLISAU200 LISA-U201: XPYLISAU201 LISA-U230: XPYLISAU230 LISA-U260: XPYLISAU200 LISA-U270: XPYLISAU200 UBX-13001118 - R25 System description Page 109 of 182 LISA-U2 series - System Integration Manual 1.15.2.1 Safety warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product the module is installed The clearance and creepage current distances required by the end product must be withheld when The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, no hygroscopic materials nor materials containing asbestos are employed 1.15.2.2 Declaration of conformity This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions:

this device may not cause harmful interference this device must accept any interference received, including interference that may cause undesired operation Radiofrequency radiation exposure Information: this equipment complies with FCC radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with FCC procedures and as authorized in the module certification filing. The gain of the system antenna(s) used for LISA-U200 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.25 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band), 7.30 dBi (in 1700 MHz, i.e. AWS or UMTS FDD-4 band) and 2.74 dBi

(in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U201 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.0 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band) and 3.5 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U230 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.78 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band), 7.55 dBi (in 1700 MHz, i.e. AWS or UMTS FDD-4 band) and 3.95 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U260 and LISA-U270 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.88 dBi

(in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band) and 4.08 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. 1.15.2.3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the LISA-U2 modules are authorized to use the FCC Grants of the LISA-U2 modules for their own final products according to the conditions referenced in the certificates. UBX-13001118 - R25 System description Page 110 of 182 The FCC Label shall in the above case be visible from the outside, or the host device shall bear a LISA-U2 series - System Integration Manual second label stating:

o LISA-U200: "Contains FCC ID: XPYLISAU200" resp. o LISA-U201: "Contains FCC ID: XPYLISAU201" resp. o LISA-U230: "Contains FCC ID: XPYLISAU230" resp. o LISA-U260: "Contains FCC ID: XPYLISAU200" resp. o LISA-U270: "Contains FCC ID: XPYLISAU200" resp. IMPORTANT: Manufacturers of portable applications incorporating the LISA-U2 modules are required to have their final product certified and apply for their own FCC grant related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 1.15.3 Innovation, Science, Economic Development Canada notice The ISED Canada (formerly known as IC - Industry Canada) Certification Numbers are:

LISA-U200: 8595A-LISAU200N LISA-U201: 8595A-LISAU201 LISA-U230: 8595A-LISAU230N LISA-U260: 8595A-LISAU200N LISA-U270: 8595A-LISAU200N 1.15.3.1 Declaration of conformity Radiofrequency radiation exposure Information: this equipment complies with IC radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter except in accordance with IC procedures and as authorized in the module certification filing. The gain of the system antenna(s) used for LISA-U200 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.25 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band), 7.30 dBi (in 1700 MHz, i.e. AWS or UMTS FDD-4 band) and 2.74 dBi

(in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U201 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 0.7 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band) and 3.5 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U230 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.78 dBi (in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band), 7.55 dBi (in 1700 MHz, i.e. AWS or UMTS FDD-4 band) and 3.95 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. The gain of the system antenna(s) used for LISA-U260 and LISA-U270 (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed 4.88 dBi

(in 850 MHz, i.e. GSM 850 or UMTS FDD-5 band) and 4.08 dBi (in 1900 MHz, i.e. GSM 1900 or UMTS FDD-2 band) for mobile and fixed or mobile operating configurations. UBX-13001118 - R25 System description Page 111 of 182 LISA-U2 series - System Integration Manual 1.15.3.2 Modifications The IC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment. Manufacturers of mobile or fixed devices incorporating the LISA-U2 modules are authorized to use the Industry Canada Certificates of the LISA-U2 modules for their own final products according to the conditions referenced in the certificates. The IC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

o LISA-U200: "Contains IC: 8595A-LISAU200N" resp. o LISA-U201: "Contains IC: 8595A-LISAU201" resp. o LISA-U230: "Contains IC: 8595A-LISAU230" resp. o LISA-U260: "Contains IC: 8595A-LISAU200N" resp. o LISA-U270: "Contains IC: 8595A-LISAU200N" resp. Canada, Industry Canada (IC) Notices This Class B digital apparatus complies with Canadian CAN ICES-3(B) / NMB-3(B) and RSS-210. Operation is subject to the following two conditions:

o this device may not cause interference o this device must accept any interference, including interference that may cause undesired operation of the device Radio Frequency (RF) Exposure Information The radiated output power of the u-blox Cellular Module is below the Industry Canada (IC) radio frequency exposure limits. The u-blox Cellular Module should be used in such a manner such that the potential for human contact during normal operation is minimized. This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canadas REL

(Radio Equipment List) can be found at the following web address:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng Additional Canadian information on RF exposure also can be found at the following web address:

http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: Manufacturers of portable applications incorporating the LISA-U2 modules are required to have their final product certified and apply for their own Industry Canada Certificate related to the specific portable device. This is mandatory to meet the SAR requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Canada, avis d'Industrie Canada (IC) Cet appareil numrique de classe B est conforme aux normes canadiennes CAN ICES-3(B) / NMB-

3(B) et RSS-210. Son fonctionnement est soumis aux deux conditions suivantes:

o cet appareil ne doit pas causer d'interfrence o cet appareil doit accepter toute interfrence, notamment les interfrences qui peuvent affecter son fonctionnement Informations concernant l'exposition aux frquences radio (RF) UBX-13001118 - R25 System description Page 112 of 182 LISA-U2 series - System Integration Manual La puissance de sortie mise par lappareil de sans fil u-blox Cellular Module est infrieure la limite d'exposition aux frquences radio d'Industrie Canada (IC). Utilisez lappareil de sans fil u-blox Cellular Module de faon minimiser les contacts humains lors du fonctionnement normal. Ce priphrique a t valu et dmontr conforme aux limites d'exposition aux frquences radio

(RF) d'IC lorsqu'il est install dans des produits htes particuliers qui fonctionnent dans des conditions d'exposition des appareils mobiles (les antennes se situent plus de 20 centimtres du corps d'une personne). Ce priphrique est homologu pour l'utilisation au Canada. Pour consulter l'entre correspondant lappareil dans la liste d'quipement radio (REL - Radio Equipment List) d'Industrie Canada rendez-vous sur:

http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplmentaires concernant l'exposition aux RF au Canada rendez-vous sur : http://www.ic.gc.ca/eic/site/smt-gst.nsf/eng/sf08792.html IMPORTANT: les fabricants d'applications portables contenant les modules LISA-U2 series doivent faire certifier leur produit final et dposer directement leur candidature pour un certificat Industrie Canada dlivr par l'organisme charg de ce type d'appareil portable. Ceci est obligatoire afin d'tre en accord avec les exigences SAR pour les appareils portables. Tout changement ou modification non expressment approuv par la partie responsable de la certification peut annuler le droit d'utiliser l'quipement. 1.15.4 Australian Regulatory Compliance Mark LISA-U200-01, LISA-U201-03 and LISA-U230 modules are compliant with the standards made by the Australian Communications and Media Authority

(ACMA) under Section 376 of the Telecommunications Act 1997. The ACMA recommends that telephones be able to support access to emergency numbers (such as 000) for at least 30 minutes during a power failure. For telephones that do not function during a power failure, the technical standard suggests that a warning notice be included in the instructions, advising users that the phone will not operate if there is a power failure. is the customer's responsibility to determine It recommendations and apply the warning notice requirement as appropriate. if their product is subject to such 1.15.5 ICASA Certification LISA-U200 and LISA-U270 modules are certified by the Independent Communications Authority of South Africa (ICASA). UBX-13001118 - R25 System description Page 113 of 182 1.15.6 KCC Certification LISA-U200 and LISA-U270 modules are certified by the Korea Communications Commission (KCC). LISA-U2 series - System Integration Manual KCC ID for LISA-U2 modules:

LISA-U200: KCC-CRM-ULX-LISA-U200 LISA-U270: KCC-CRM-ULX-LISA-U270 1.15.7 ANATEL Certification Anatel IDs for LISA-U200 modules:

EAN barcode: (01)0 789 8941 57508 3 Homologation number 3309-12-8459 LISA-U200 and LISA-U201 modules are certified by the Brazilian Agency of Telecommunications

(Agncia Nacional de Telecomunicaes in Portuguese) (ANATEL). UBX-13001118 - R25 System description Page 114 of 182 LISA-U200 3309-12-8459

(01)0 789 8941 57508 3 LISA-U2 series - System Integration Manual Anatel IDs for LISA-U201 modules:

EAN barcode: (01)0 789 8941 57526 7 Homologation number 4466-15-5903 1.15.8 CCC Certification LISA-U200, LISA-U201, LISA-U230 and LISA-U270 modules are CCC approved (Chinese Compulsory Certification) LISA-U200-62S, LISA-U270-62S, LISA-U270-63S and LISA-U270-68S modules comply with Japanese Telecom [T] and Radio [R] Law and have the Giteki mark placed on the product label. 1.15.9 Giteki Certification LISA-U270-62S, LISA-U270-63S and LISA-U270-68S:

LISA-U200-62S:

o T: AD120274003 o R: 003-120375 UBX-13001118 - R25 System description Page 115 of 182 LISA-U201 4466-15-5903

(01)0 789 8941 57526 7 LISA-U2 series - System Integration Manual o T: AD120274003 o R: 003-120377 UBX-13001118 - R25 System description Page 116 of 182 xxS-xx LISA-U200 T AD120274003 R 003-120375 xxS-xx LISA-U270 T AD120274003 R 003-120377 LISA-U2 series - System Integration Manual 2 Design-In 2.1 Design-in checklist This section provides a design-in checklist. 2.1.1 Schematic checklist The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at the VCC pin above the minimum operating range limit. DC supply must be capable of providing 2.5 A current pulses, providing a voltage at the VCC pin above the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value. VCC supply should be clean, with very low ripple/noise: provide the suggested series ferrite bead and bypass capacitors, in particular if the application device integrates an internal antenna. VCC voltage must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. Do not leave PWR_ON floating: add a pull-up resistor to V_BCKP. Do not apply loads which might exceed the limit for maximum available current from the V_INT supply. Check that the voltage level of any connected pin does not exceed the specific operating range. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal. Check the UART signal directions, since the signal names follow the Recommendation [3]. ITU-T V.24 Provide appropriate access to the USB interface and/or to the UART RxD, TxD lines and access to the PWR_ON and/or RESET_N lines to flash/upgrade the module firmware using the u-blox EasyFlash tool. Provide appropriate access to the USB interface and/or to the UART RxD, TxD, CTS, RTS lines for debugging purposes. Capacitance and series resistance must be limited on each line of the SPI / IPC interface. Add a suitable pull-up resistor to an appropriate supply on each DDC (I2C) interface line, if the interface is used. Capacitance and series resistance must be limited on each line of the DDC interface. Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Connect pin number 5 (RSVD) to ground. Check the digital audio interface specifications to connect a relevant device. Capacitance and series resistance must be limited on the CODEC_CLK line and each I2S interface line. Provide suitable precautions for ESD immunity as required on the application board. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low, and during the module power-on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and enable a clean boot of the module. UBX-13001118 - R25 Design-In Page 117 of 182 LISA-U2 series - System Integration Manual All unused pins can be left floating on the application board except the PWR_ON pin (must be connected to V_BCKP by a pull-up resistor) and RSVD pin number 5 (must be connected to GND). 2.1.2 Layout checklist The following are the most important points for a simple layout check:

Check the 50 nominal characteristic impedance of the RF transmission line connected to the ANT pad (main RF input/output) and to the ANT_DIV pad (RF input for Rx diversity). Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB layout and matching circuitry). Ensure no coupling occurs with other noisy or sensitive signals (e.g. SIM signals). The VCC line should be as wide and as short as possible. Provide the suggested series ferrite bead and bypass capacitors close to the VCC pins implementing the recommended layout and placement, especially if the application device integrates an internal antenna. Route the VCC supply line away from sensitive analog signals. The high-power audio outputs lines on the application board must be wide enough to minimize series resistance. Ensure proper grounding. Consider No-routing areas for the Data Module footprint. Optimize placement for minimum length of RF line and closer path from the DC source for VCC. Design the USB_D+ / USB_D- connection as 90 differential pair, with 30 common mode impedance. Keep routing short and minimize parasitic capacitance on the SPI lines to preserve signal integrity. Keep routing short and minimize parasitic capacitance on CODEC_CLK line to preserve signal integrity. 2.1.3 Antenna checklist Antenna should have 50 impedance, VSWR less than 3:1 (recommended 2:1) on operating bands in deployment geographical area. Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB layout and matching circuitry). Follow the additional guidelines for products marked with the FCC logo (United States only) reported in section 1.15.2.2 The antenna connected to the ANT pad should have built-in DC resistor to ground to get proper antenna detection functionality. The antenna for the Rx diversity connected to the ANT_DIV pin should be carefully separated from the main Tx/Rx antenna connected to the ANT pin: the distance between the two antennas should be at least greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation. UBX-13001118 - R25 Design-In Page 118 of 182 LISA-U2 series - System Integration Manual 2.2 Design Guidelines for Layout The following design guidelines must be met for optimal integration of LISA-U2 modules on the final application board. 2.2.1 Layout guidelines per pin function This section groups LISA-U2 modules pins by signal function and provides a ranking of importance in layout design. Figure 55: LISA-U2 series modules pin-out (top view) with ranked importance for layout design UBX-13001118 - R25 Design-In Page 119 of 182 D V S R

I V D _ T N A D N G D N G D N G D N G D N G D N G D N G T N A D N G D N G 6 7 5 7 4 7 3 7 2 7 1 7 0 7 9 6 8 6 7 6 6 6 LISA-U2 series

(Top View) 8 2 9 2 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G D N G Legend:

Very Important Careful Layout Common Practice 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GND GND VCC VCC VCC GND SPI_MRDY / GPIO14 SPI_SRDY / GPIO13 SPI_MISO / GPIO12 SPI_MOSI / GPIO11 SPI_SCLK / GPIO10 GPIO9 / I2S1_WA GPIO8 / I2S1_CLK RSVD / CODEC_CLK GPIO5 VSIM SIM_RST SIM_IO SIM_CLK SDA SCL RSVD / I2S_RXD RSVD / I2S_CLK RSVD / I2S_TXD RSVD / I2S_WA GPIO7 / I2S1_TXD GPIO6 / I2S1_RXD GND V_BCKP GND V_INT RSVD GND GND GND DSR RI DCD DTR RTS CTS TXD RXD GND VUSB_DET PWR_ON GPIO1 GPIO2 RESET_N GPIO3 GPIO4 GND USB_D-

USB_D+

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Rank Function Pin(s) Layout Remarks 1st RF Antenna Main RF input/output ANT RF input for Rx diversity ANT_DIV 2nd Main DC Supply VCC 3rd USB Signals USB_D+

USB_D-

Very Important Route USB_D+ and USB_D- as 4th Ground GND Careful Layout Provide proper grounding. 5th Sensitive Pin:

Careful Layout Avoid coupling with noisy signals. 6th High-speed digital pins:

Careful Layout Avoid coupling with sensitive signals. LISA-U2 series - System Integration Manual Very Important Design for 50 characteristic impedance. See section 2.2.1.1 Very Important Design for 50 characteristic impedance. See section 2.2.1.1 Very Important VCC line should be wide and short. Route away from sensitive analog signals. See section 2.2.1.2 differential lines: design for 90 differential impedance (Z0) and design for 30 common mode impedance (ZCM). See section 2.2.1.3 See section 2.2.1.4 See section 2.2.1.5 See section 2.2.1.6 Common Practice Follow common practice rules for digital pin routing. See section 2.2.1.7 Backup Voltage V_BCKP Power-On PWR_ON SPI Signals SPI_SCLK, SPI_MISO, SPI_MOSI, SPI_SRDY, SPI_MRDY Clock Output CODEC_CLK 7th Digital pins and supplies:

SIM Card Interface VSIM, SIM_CLK, SIM_IO, SIM_RST Digital Audio DDC UART External Reset RESET_N General Purpose I/O I2S_CLK, I2S_RXD, I2S_TXD, I2S_WA, I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA SCL, SDA TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14 USB detection VUSB_DET Supply for Interfaces V_INT Table 45: Pin list in order of decreasing importance for layout design UBX-13001118 - R25 Design-In Page 120 of 182 LISA-U2 series - System Integration Manual 2.2.1.1 RF antenna connection The ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) are very critical in layout design. Proper transition between ANT and ANT_DIV pads and the application board must be provided, implementing the following design-in guidelines for the layout of the application PCB close to the ANT and ANT_DIV pads:

On a multi layer board, the whole layer stack below the RF connection should be free of digital lines Increase GND keep-out (i.e. clearance) for ANT and ANT_DIV pads to at least 250 m up to adjacent pads metal definition and up to 500 m on the area below the module, as described in Figure 56 Add GND keep-out (i.e. clearance) on buried metal layers below ANT and ANT_DIV pads and below any other pad of component present on the RF line, if top-layer to buried layer dielectric thickness is below 200 m, to reduce parasitic capacitance to ground (see Figure 56 for the description of the GND keep-out area below ANT and ANT_DIV pads) Figure 56: GND keep-out area on top layer around ANT and ANT_DIV pads and on buried layer below ANT and ANT_DIV pads The transmission line from the ANT pad and the ANT_DIV pad up to antenna connector(s) or up to the internal antenna(s) pad must be designed so that the characteristic impedance is as close as possible to 50 . The transmission line up to antenna connector or pad may be a microstrip (consists of a conducting strip separated from a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is sandwiched between two parallel ground planes within a dielectric material). In any case must be designed to achieve 50 characteristic impedance Microstrip lines are usually easier to implement and the reduced number of layer transitions up to antenna connector simplifies the design and diminishes reflection losses. However, the electromagnetic field extends to the free air interface above the stripline and may interact with other circuitry Buried striplines exhibit better shielding to external and internally generated interferences. They are therefore preferred for sensitive application. In case a stripline is implemented, carefully check that the via pad-stack does not couple with other signals on the crossed and adjacent layers Figure 57 and Figure 58 provide two examples of proper 50 coplanar waveguide designs. The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB stack-up herein described. UBX-13001118 - R25 Design-In Page 121 of 182 Top layer Buried metal layer Min. 250 um Microstrip 50 ohm Min. 500 um GND plane LISA-U2 series - System Integration Manual Figure 57: Example of 50 coplanar waveguide transmission line design for the described 4-layer board layup Figure 58: Example of 50 coplanar waveguide transmission line design for the described 2-layer board layup If the two examples do not match the application PCB layup, the 50 characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation, or using freeware tools like Avago / Broadcom AppCAD (https://www.broadcom.com/appcad), taking care of the approximation formulas used by the tools for the impedance computation. To achieve a 50 characteristic impedance, the width of the transmission line must be chosen depending on:

the thickness of the transmission line itself (e.g. 35 m in the example of Figure 57 and Figure 58) the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner closer layer implementing the ground plane (e.g. 270 m in Figure 57, 1510 m in Figure 58) the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 57 and Figure 58) the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g. 500 m in Figure 57, 400 m in Figure 58) If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the microstrip, use the Coplanar Waveguide model for the 50 calculation. Additionally to the 50 impedance, the following guidelines are recommended for the RF line design:

Minimize the transmission line length; the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB The transmission line should not have abrupt change to thickness and spacing to GND, but must be uniform and routed as smoothly as possible UBX-13001118 - R25 Design-In Page 122 of 182 500 m 380 m 500 m L1 Copper FR-4 dielectric L2 Copper FR-4 dielectric L3 Copper FR-4 dielectric L4 Copper 35 m 270 m 35 m 760 m 35 m 270 m 35 m 400 m 1200 m 400 m L1 Copper FR-4 dielectric L2 Copper 35 m 1510 m 35 m LISA-U2 series - System Integration Manual The transmission line must be routed in a section of the PCB where minimal interference from noise sources can be expected Route RF transmission line far from other sensitive circuits as it is a source of electromagnetic interference layer Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground Add GND vias around transmission line Ensure no other signals are routed parallel to transmission line, or that other signals cross on adjacent metal layer If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the microstrip, use the Coplanar Waveguide model for 50 characteristic impedance calculation Do not route microstrip line below discrete component or other mechanics placed on top layer When terminating transmission line on antenna connector (or antenna pad) it is very important to strictly follow the connector manufacturers recommended layout GND layer under RF connectors and close to buried vias should be cut out in order to remove stray capacitance and thus keep the RF line 50 . In most cases the large active pad of the integrated antenna or antenna connector needs to have a GND keep-out (i.e. clearance) at least on first inner layer to reduce parasitic capacitance to ground. Note that the layout recommendation is not always available from connector manufacturer: e.g. the classical SMA Pin-Through-Hole needs to have GND cleared on all the layers around the central pin up to annular pads of the four GND posts. Check 50 impedance of ANT and ANT_DIV lines Ensure no coupling occurs with other noisy or sensitive signals The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna to ensure that uncorrelated signals are received at each antenna, because signal improvement is dependent on the cross correlation and the signal strength levels between the two received signals. The distance between the two antennas should be greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels, for proper spatial diversity implementation Any RF transmission line on PCB should be designed for 50 characteristic impedance. Ensure no coupling occurs with other noisy or sensitive signals. 2.2.1.2 Main DC supply connection The DC supply of LISA-U2 modules is very important for the overall performance and functionality of the integrated product. For detailed description, check the design guidelines in section 1.5.2. Some main characteristics are:

VCC pins are internally connected, but it is recommended to use all the available pins in order to minimize the power loss due to series resistance VCC connection may carry a maximum burst current in the order of 2.5 A. Therefore, it is typically implemented as a wide PCB line with short routing from DC supply (DC-DC regulator, battery pack, etc) The module automatically initiates an emergency shutdown if supply voltage drops below hardware threshold. In addition, reduced supply voltage can set a worst case operation point for RF circuitry that may behave incorrectly. It follows that each voltage drop in the DC supply track will restrict the operating margin at the main DC source output. Therefore, the PCB connection must exhibit a minimum or zero voltage drop. Avoid any series component with Equivalent Series Resistance (ESR) greater than a few milliohms UBX-13001118 - R25 Design-In Page 123 of 182 LISA-U2 series - System Integration Manual Given the large burst current, VCC line is a source of disturbance for other signals. Therefore route VCC through a PCB area separated from sensitive analog signals. Typically it is good practice to interpose at least one layer of PCB ground between VCC track and other signal routing The VCC supply current supply flows back to main DC source through GND as ground current:

provide adequate return path with suitable uninterrupted ground plane to main DC source A tank bypass capacitor with low ESR is recommended to smooth current spikes. This is most effective when placed close to the VCC pins. If the main DC source is a switching DC-DC converter, place the large capacitor close to the DC-DC output and minimize the VCC track length. Otherwise consider using separate capacitors for DC-DC converter and LISA-U2 module tank capacitor. Note that the capacitor voltage rating may be adequate to withstand the charger over-voltage if battery-pack is used. The use of very large capacitors (i.e. greater then 1000 F) must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module VCC is directly connected to the RF power amplifiers. It is highly recommended to place a series ferrite bead for GHz band noise, a bypass capacitor with Self-Resonant Frequency in 800/900 MHz range and a bypass capacitor with self-resonant frequency in 1800/1900 MHz range as close as possible to the VCC pins, especially if the application device integrates an internal antenna. This is described in Figure 9 and Table 10. Since VCC is directly connected to RF Power Amplifiers, voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with switching DC-DC converters, in which case it is better to select the highest operating frequency for the switcher and add a large L-C filter before connecting to the LISA-U2 modules in the worst case The large current generates a magnetic field that is not well isolated by PCB ground layers and which may interact with other analog modules (e.g. VCO) even if placed on opposite side of PCB. In this case route VCC away from other sensitive functional units The typical GSM burst has a periodic nature of approx. 217 Hz, which lies in the audible audio range. Avoid coupling between VCC and audio lines (especially microphone inputs) If VCC is protected by transient voltage suppressor / reverse polarity protection diode to ensure that the voltage maximum ratings are not exceeded, place the protecting device along the path from the DC source toward the LISA-U2 module, preferably closer to the DC source (otherwise functionality may be compromised) VCC line should be as wide and as short as possible. Route away from sensitive analog signals. UBX-13001118 - R25 Design-In Page 124 of 182 LISA-U2 series - System Integration Manual 2.2.1.3 USB signal The LISA-U2 modules include a high-speed USB 2.0 compliant interface with a maximum throughput of 480 Mbit/s (see Section 1.9.3). Signals USB_D+ / USB_D- carry the USB serial data and signaling. The lines are used in single-ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. Characteristic impedance of USB_D+ / USB_D-

lines is specified by USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Route USB_D+ / USB_D- lines as a differential pair Ensure the differential characteristic impedance (Z0) is as close as possible to 90 Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30 Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area Figure 59 and Figure 60 provide two examples of coplanar waveguide designs with differential characteristic impedance close to 90 and common mode characteristic impedance close to 30 . The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB stack-up herein described. Figure 59: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 4-layer board layup Figure 60: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 2-layer board layup UBX-13001118 - R25 Design-In Page 125 of 182 400 m 350 m 400 m 350 m 400 m L1 Copper FR-4 dielectric L2 Copper FR-4 dielectric L3 Copper FR-4 dielectric L4 Copper 35 m 270 m 35 m 760 m 35 m 270 m 35 m 410 m 740 m 410 m 740 m 410 m L1 Copper FR-4 dielectric L2 Copper 35 m 1510 m 35 m LISA-U2 series - System Integration Manual 2.2.1.4 Module grounding Good connection of the module with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the module. Connect each GND pin with application board solid GND layer. It is strongly recommended that each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer If the application board is a multilayer PCB, then it is required to connect together each GND area with complete via stack down to main board ground layer It is recommended to implement one layer of the application board as ground plane Good grounding of GND pads will also ensure thermal heat sink. This is critical during call connection, when the real network commands the module to transmit at maximum power: proper grounding helps prevent module overheating 2.2.1.5 Other sensitive pins A few other pins on the LISA-U2 modules requires careful layout. RTC supply (V_BCKP): avoid injecting noise on this voltage domain as it may affect RTC oscillator stability Power-On (PWR_ON): is the digital input to switch-on the LISA-U2 modules. Ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request 2.2.1.6 High-speed digital pins The following high speed digital pins require careful layout:

Serial Peripheral Interface (SPI): can be used for high speed data transfer (UMTS/HSPA) between the LISA-U2 modules and the host processor, with a data rate up to 26 Mbit/s (see Section 1.9.3). The high-speed data rate is carried by signals SPI_SCLK, SPI_MISO and SPI_MOSI, while SPI_SRDY and SPI_MRDY behave as handshake signals with relatively low activity Digital Clock Output (CODEC_CLK): can be used to provide a 26 MHz or 13 MHz digital clock to an external audio codec Follow these hints for high speed digital pins layout:

High-speed signals become sources of digital noise, route away from RF and other sensitive analog signals Keep routing short and minimize parasitic capacitance to preserve digital signal integrity It is recommended to match the length of SPI signals 2.2.1.7 Digital pins and supplies External Reset (RESET_N): input for external reset, a logic low voltage will reset the module SIM Card Interface (VSIM, SIM_CLK, SIM_IO, SIM_RST): the SIM layout may be critical if the SIM card is placed far away from the LISA-U2 modules or in close proximity to the RF antenna. In the first case the long connection can cause the radiation of some harmonics of the digital data frequency. In the second case the same harmonics can be picked up and create self-interference that can reduce the sensitivity of GSM Receiver channels whose carrier frequency is coincidental with harmonic frequencies. The latter case, placing the RF bypass capacitors, suggested in the section 1.8, near the SIM connector will mitigate the problem. In addition, since the SIM card is UBX-13001118 - R25 Design-In Page 126 of 182 LISA-U2 series - System Integration Manual typically accessed by the end user, it can be subjected to ESD discharges: add adequate ESD protection to protect module SIM pins near the SIM connector Digital Audio (I2S_CLK, I2S_RX, I2S_TX, I2S_WA and I2S1_CLK, I2S1_RXD, I2S1_TXD, I2S1_WA):

the I2S interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs DDC (SCL, SDA): the DDC interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs UART (TXD, RXD, CTS, RTS, DSR, RI, DCD, DTR): the serial interface requires the same consideration regarding electro-magnetic interference as the SIM card. Keep the traces short and avoid coupling with RF line or sensitive analog inputs General Purpose I/O (GPIOx): the general purpose input/output pins are generally not critical for layout Reserved pins: these pins are reserved for future use. Leave them unconnected on the baseboard USB detection (VUSB_DET): this input will generate an interrupt to the baseband processor for USB detection. The USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host to enable the USB interface of the module Interfaces Supply (V_INT): this supply output is generated by an integrated switching step down converter, used internally to supply the digital interfaces. Because of this, it can be a source of noise: avoid coupling with sensitive signals UBX-13001118 - R25 Design-In Page 127 of 182 LISA-U2 series - System Integration Manual 2.2.2 Footprint and paste mask The following figure describes the footprint and provides recommendations for the paste mask for LISA-U2 modules. These are recommendations only and not specifications. Note that the copper and solder masks have the same size and position. Figure 61: LISA-U2 modules suggested footprint and paste mask To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the volume outside of the module by defining the dimensions of the paste mask to form a T-

shape (or equivalent) extending beyond the copper mask. The solder paste should have a total thickness of 150 m. The paste mask outline needs to be considered when defining the minimal distance to the next component. The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. The implemetation of a step stencil (a stencil with different material thicknesses) should be considered if very different sized components must be soldered on the same application PCB: while high density chip housings with small pitch need small solder paste quantities for the avoidance of short-circuits and therefore require thin stencils, large components need more solder paste for a safe connection and thus thicker stencils. The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in Figure 62. Consider No-routing areas for the LISA-U2 modules footprint as follows: signal keep-out area on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer (see Figure 62). UBX-13001118 - R25 Design-In Page 128 of 182 5.7 mm

[224.4 mil]

1.0 mm

[39.3 mil]

5.7 mm

[224.4 mil]

0.9 mm

[35.4 mil]

m m 8 0

l i m 5 1 3

m m 1 1

l i m 3 3 4

m m 8 0

l i m 5 1 3

m m 3 2

l i m 6 0 9

l i

. m 1 7 0 3 1

m m 2 3 3

l i

. m 1 7 0 3 1

m m 2 3 3

. Stencil: 150 m m m 6 0

l i m 6 3 2

22.4 mm [881.9 mil]

22.4 mm [881.9 mil]

m m 2 1

l i m 2 7 4

m m 1 1

l i m 3 3 4

m m 8 0

l i m 5 1 3

m m 3 2

l i m 6 0 9

LISA-U2 series - System Integration Manual Figure 62: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 2.2.3 Placement Optimize placement for minimum length of RF line and closer path from DC source for VCC. Make sure that RF and analog circuits are clearly separated from any other digital circuits on the system board. Provide enough clearance between the module and any external part due to solder and paste masks design. Milled edges that are present at module PCB corners, away from module pins metallization, can slightly increase module dimensions from the width and the height described in the mechanical specifications sections of LISA-U2 series Data Sheet [1]: provide enough clearance between module PCB corners and any other external part mounted on the application board. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the LISA-U2 modules: avoid placing temperature sensitive devices (e.g. GNSS receiver) close to the module. UBX-13001118 - R25 Design-In Page 129 of 182 5.25 mm 5.3 mm 5.3 mm 5.25 mm 1.3 mm PIN 1 1.4 mm 1.0 mm Exposed GND on LISA-U module bottom layer Signals keep-out areas on application board LISA-U2 bottom side

(through module view) m m 2

. 3 3 22.4 mm LISA-U2 series - System Integration Manual 2.3 Thermal guidelines LISA-U2 module operating temperature range and module thermal resistance are specified in the LISA-U2 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload or voice call in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks; however the application should be correctly designed to cope with it. During transmission at maximum RF power the LISA-U2 modules generate thermal power that can exceed 2 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the number of allocated TX slot and modulation (GMSK or 8PSK) or data rate

(WCDMA), transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition (e.g. 2G or 3G mode, transmit band): the overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. Mounting a LISA-U2 module on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper in still air conditions7, the increase of the module temperature8 in different modes of operation, referred to idle state initial condition9, can be summarized as following:

7C during a GSM voice call at max TX power 25C in UMTS/HSxPA connection at max TX power 19C during GPRS data transfer with 4 TX slots at max TX power 16C during EDGE data transfer with 4 TX slots at max TX power The Module-to-Ambient thermal resistance value and the related increase of module temperature will be different for other mechanical deployments of the module, e.g. PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. The increase of thermal dissipation, i.e. the Module-to-Ambient thermal resistance reduction, will decrease the temperature for internal circuitry of LISA-U2 modules for a given operating ambient temperature. This improves the device long-term reliability for applications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application:

Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete via stack down to main ground layer Provide a ground plane as wide as possible on the application board Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power Optimize the thermal design of any high-power component included in the application, as linear regulators and amplifiers, to optimize overall temperature distribution in the application device Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure of the application device that integrates the module) so that it provides good thermal dissipation 7 Refer to LISA-U2 series Data Sheet [1] for the Rth,M-A value in this application condition 8 Temperature is measured by internal sensor of wireless module 9 Steady state thermal equilibrium is assumed. The modules temperature in idle state can be considered equal to ambient temperature UBX-13001118 - R25 Design-In Page 130 of 182 LISA-U2 series - System Integration Manual Further hardware techniques to be used to improve heat dissipation in the application:

Force ventilation air-flow within mechanical enclosure Provide a heat sink component attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the cellular module, as a large part of the heat is transported through the GND pads and dissipated over the backside of the application board For example, after the installation of a robust aluminum heat-sink with forced air ventilation on the back of the same application board described above, the Module-to-Ambient thermal resistance

(Rth,M-A) is reduced to 1.5 3.5 C/W. The effect of lower Rth,M-A can be seen from the module temperature increase, which now can be summarized as following:

1.5C during a GSM voice call at max TX power 3C during GPRS data transfer with 4 TX slots at max TX power 2.5C during EDGE data transfer with 4 TX slots at max TX power 5.5C in UMTS/HSxPA connection at max TX power Beside the reduction of the Module-to-Ambient thermal resistance implemented by the hardware design of the application device integrating a LISA-U2 module, the increase of module temperature can be moderated by the software implementation of the application. Since the most critical condition concerning module thermal power occurs when module connected mode is enabled, the actual module thermal power depends, as module current consumption, on the radio access mode (GERAN / UTRA), the operating band and the average TX power. A few software techniques may be implemented to reduce the module temperature increase in the application:

Select the radio access mode which provides lower temperature increase (see the module temperature increase values summarized above) by means of an AT command (see the u-blox AT Commands Manual [2], +COPS command) Select the operating band which provides lower current consumption in the selected radio access mode (see current consumption values reported in the LISA-U2 series Data Sheet [1]) by means of an AT command (see the u-blox AT Commands Manual [2], +UBANDSEL command) Enable module connected mode for a given time period and then disable it for a time period enough long to properly mitigate temperature increase UBX-13001118 - R25 Design-In Page 131 of 182 LISA-U2 series - System Integration Manual 2.4 Antenna guidelines Antenna characteristics are essential for good functionality of the module. Antenna radiating performance has direct impact on the reliability of connections over the Air Interface. A bad termination of the ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) can result in poor performance of the module. The following parameters should be checked:

Item Recommendations Impedance 50 nominal characteristic impedance Frequency Range Depends on the LISA-U2 module HW version and on the Mobile Network used. LISA-U260:

824..960 MHz (GSM 850, GSM 900, UMTS B5) 1710..1990 MHz (GSM 1800, GSM 1900, UMTS B2) LISA-U270:

824..960 MHz (GSM 850, GSM 900, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1) LISA-U200, LISA-U201, LISA-U230:

824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2, UMTS B4) Input Power

>2 W peak VSWR

<2:1 recommended, <3:1 acceptable Return Loss S11<-10 dB recommended, S11<-6 dB acceptable Table 46: General recommendation for GSM antenna The antenna gain shall be limited according to regulatory agency RF radiation requirements. For example, see the maximum antenna gain value reported in section 1.15.1 for EU, in section 1.15.2.2 for US FCC, in section 1.15.3.1 for ISED Canada. Some 2G and 3G bands are overlapping. This depends on worldwide band allocation for telephony services, where different bands are deployed for different geographical regions. If LISA-U2 series modules are planned for use on the entire supported bands, then an antenna that supports the 824...960 MHz and the 17102170 MHz frequency range should be selected. Otherwise, for fixed applications in specific geographical region, antenna requirements can be relaxed for non-

deployed frequency bands. See the operating RF frequency bands table in LISA-U2 series Data Sheet [1] for the detailed uplink and downlink frequency ranges of each supported band. LISA-U230 modules provide 2G and 3G dynamic receive diversity (Rx diversity) capability to improve the quality and reliability of the cellular link. This feature can be optionally used connecting a second antenna to the ANT_DIV pin, to receive an RF input signal that is processed by the module to increase the performance. It is recommended to properly connect the Rx diversity antenna to the ANT_DIV pin of LISA-U230 modules unless the 2G and 3G Rx diversity feature is disabled by AT command (see the u-blox AT Commands Manual [2], +URXDIV command). All the antenna guidelines and recommendations reported for the main Tx/Rx antenna design are applicable also to the Rx diversity antenna design, even if the antenna for the Rx diversity is not used to transmit. UBX-13001118 - R25 Design-In Page 132 of 182 LISA-U2 series - System Integration Manual GSM antennas are typically available as:

Linear monopole: typical for fixed applications. The antenna extends mostly as a linear element with a dimension comparable to lambda/4 of the lowest frequency of the operating band. Magnetic base may be available. Cable or direct RF connectors are common options. The integration normally requires the fulfillment of some minimum guidelines suggested by antenna manufacturer Patch-like antenna: better suited for integration in compact designs (e.g. mobile phone). These are mostly custom designs where the exact definition of the PCB and product mechanical design is fundamental for tuning of antenna characteristics For integration observe these recommendations:

Ensure 50 antenna termination, minimize the VSWR or return loss, as this will optimize the electrical performance of the module. See sections 2.2.1.1 and 2.4.1 Select the antenna with the best radiating performance. See section 2.4.2 If a cable is used to connect the antenna radiating element to application board, select a short cable with minimum insertion loss. The higher the additional insertion loss due to low quality or long cable, the lower the connectivity Follow the recommendations of the antenna manufacturer for correct installation and deployment countries Do not include antenna within closed metal case Do not place the main antenna in close vicinity to the end user since the emitted radiation in human tissue is limited by S.A.R. regulatory requirements Do not use directivity antenna since the electromagnetic field radiation intensity is limited in some Take care of interactions between co-located RF systems since the GSM transmitted power may interact or disturb the performance of companion systems Place the antenna far from sensitive analog systems or employ countermeasures to reduce electromagnetic compatibility issues that may arise The antenna for the Rx diversity should be carefully separated from the main Tx/Rx antenna, because signal improvement is dependent on the cross correlation and the signal strength levels between the two received signals. The distance between the two antennas should be at least greater than half a wavelength of the lowest used frequency (i.e. distance greater than ~20 cm, for 2G/3G low bands) to distinguish between different multipath channels UBX-13001118 - R25 Design-In Page 133 of 182 LISA-U2 series - System Integration Manual 2.4.1 Antenna termination The LISA-U2 modules are designed to work on a 50 load. However, real antennas have no perfect 50 load on all the supported frequency bands. Therefore the following requirements should be met in order to reduce the performance degradation due to antenna mismatch as much as possible:

Measure the antenna termination with a network analyzer: connect the antenna through a coaxial cable to the measurement device, the |S11| indicates which portion of the power is delivered to the antenna and which portion is reflected by the antenna back to the module output. A good antenna should have an |S11| below -10 dB over the entire frequency band. Due to miniaturization, mechanical constraints and other design issues, this value will not be achieved. An

|S11| value of about -6 dB - (in the worst case) - is acceptable. Figure 63 shows an example of this measurement:

Figure 63: |S11| sample measurement of a penta-band antenna that covers in a small form factor the 4 GSM bands (850 MHz, 900 MHz, 1800 MHz and 1900 MHz) and the UMTS Band I Figure 64 shows comparable measurements performed on a wideband antenna. The termination is better, but the size of the antenna is considerably larger. Figure 64: |S11| sample measurement of a wideband antenna UBX-13001118 - R25 Design-In Page 134 of 182 LISA-U2 series - System Integration Manual 2.4.2 Antenna radiation An indication of the antennas radiated power can be approximated by measuring the |S21| from a target antenna to the measurement antenna, using a network analyzer with a wideband antenna. Measurements should be done at a fixed distance and orientation, and results compared to measurements performed on a known good antenna. Figure 65 through Figure 66 show some example measurement results. A wideband log periodic-like antenna was used, and the comparison was done with a half lambda dipole tuned to the 900 MHz frequency. The measurements show both the |S11| and

|S21| for the penta-band internal antenna and for the wideband antenna. Figure 65: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a penta-band internal antenna (yellow/cyan) The half lambda dipole tuned at 900 MHz is known and has good radiation performance (both for gain and directivity). Then, by comparing the |S21| measurement with antenna under investigation for the frequency where the half dipole is tuned (e.g. marker 3 in Figure 65) it is possible to make a judgment on the antenna under test: if the performance is similar, then the target antenna is good. Figure 66: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a wideband commercial antenna (yellow/cyan) But if |S21| values for the tuned dipole are instead much better than the antenna under evaluation (like for marker 1/2 area of Figure 66, where dipole is 5 dB better), then it can be argued that the radiation of the target antenna (the wideband dipole in this case) is considerably less. The same procedure should be repeated on other bands with a half wavelength dipole re-tuned to the band under investigation. For good antenna radiation performance, antenna dimensions should be comparable to a quarter of the wavelength. Different antenna types can be used for the module, many of them (e.g. patch antennas, monopole) are based on a resonating element that works in combination with a ground plane. The ground plane, ideally infinite, can be reduced down to a minimum size that must be similar to one quarter of the wavelength of the minimum frequency that needs to be radiated

(transmitted/received). Numerical sample: frequency = 1 GHz wavelength = 30 cm minimum ground plane (or antenna size) = 7.5 cm. Below this size, the antenna efficiency is reduced. UBX-13001118 - R25 Design-In Page 135 of 182 LISA-U2 series - System Integration Manual 2.4.3 Examples of antennas Table 47 lists some examples of possible internal on-board surface-mount antennas Manufacturer Part Number Product Name Description Taoglas PA.25.A Anam GSM / WCDMA SMD Antenna 824..960 MHz, 1710..2170 MHz 36.0 x 6.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna Pairs with the Taoglas PA.710.A Warrior for LTE MIMO applications 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2690 MHz 42.0 x 10.0 x 3.0 mm Taoglas PA.710.A Warrior Taoglas PA.711.A Warrior II Taoglas PCS.06.A Havok Antenova A10340 Calvus Ethertronics P522304 Prestta 2J 2JE04 Yaego ANT3505B000TWPENA Table 47: Examples of internal surface-mount antennas GSM / WCDMA SMD Antenna 824..960 MHz, 1710..2170 MHz 28.0 x 8.0 x 3.2 mm GSM / WCDMA SMD Antenna 824..960 MHz, 1710..2170 MHz 35.0 x 9.0 x 3.2 mm GSM / WCDMA SMD Antenna 824..960 MHz, 1710..2170 MHz 24.0 x 5.5 x 4.4 mm GSM / WCDMA SMD Antenna 824..960 MHz, 1710..2170 MHz 35.0 x 5.0 x 6.0 mm Table 48 lists some examples of possible internal off-board antennas with cable and connector. Manufacturer Part Number Product Name Description Taoglas FXP14.A.07.0100A Taoglas FXP14R.A.07.0100A Taoglas PC29.09.0100A TheStripe Taoglas FXUB63.07.0150C Ethertronics P522310 Prestta GSM / WCDMA PCB Antenna with cable and U.FL connector 824..960 MHz, 1710..2170 MHz 70.4 x 20.4 mm GSM / WCDMA PCB Antenna with cable and U.FL connector Integrated 10k shunt diagnostic resistor 824..960 MHz, 1710..2170 MHz 80.0 x 20.8 mm GSM / WCDMA PCB Antenna with cable and MMCX(M)RA connector 824..960 MHz, 1710..2170 MHz 80.4 x 29.4 mm GSM / WCDMA / LTE PCB Antenna with cable and U.FL connector 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz 96.0 x 21.0 mm GSM / WCDMA PCB Antenna with cable and U.FL connector 824..960 MHz, 1710..2170 MHz 41.0 x 15.0 mm UBX-13001118 - R25 Design-In Page 136 of 182 LISA-U2 series - System Integration Manual Manufacturer Part Number Product Name Description EAD FSQS35241-UF-10 SQ7 Yaego ANTX100P001BWPEN3 GSM / WCDMA / LTE PCB Antenna with cable and U.FL connector 690..960 MHz, 1710..2170 MHz, 2500..2700 MHz 110.0 x 21.0 mm GSM / WCDMA PCB Antenna with cable and I-PEX connector 824..960 MHz, 1710..2170 MHz 50.0 x 20.0 mm Table 48: Examples of internal antennas with cable and connector Table 49 lists some examples of possible external antennas. Manufacturer Part Number Product Name Description Taoglas GSA.8827.A.101111 Phoenix Taoglas GSA.8821.A.301721 I-Bar GSM / WCDMA / LTE low-profile adhesive-mount Antenna with cable and SMA(M) connector 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz 105 x 30 x 7.7 mm GSM / WCDMA low-profile adhesive-mount Antenna with cable and Fakra (code-D) connector 824..960 MHz, 1710..2170 MHz 106.7 x 14.7 x 5.8 mm GSM / WCDMA / LTE swivel dipole Antenna with SMA(M) connector 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz 148.6 x 49 x 10 mm GSM / WCDMA pole-mount Antenna with N-type (F) connector 824..960 MHz, 1710..2170 MHz 527 x 26 mm GSM / WCDMA whip monopole Antenna with RP-N-type(M) connector 824..960 MHz, 1710..2170 MHz 274 x 20 mm GSM / WCDMA swivel monopole Antenna with SMA(M) connector 824..960 MHz, 1710..2170 MHz 179.3 x 22 x 6.5 mm GSM / WCDMA swivel monopole Antenna with SMA(M) connector 824..960 MHz, 1575.42 MHz,1710..2170 MHz, 2400..2500 MHz 161 x 9.3 mm GSM / WCDMA screw-mount Antenna with N-type(F) connector 824..960 MHz, 1710..2170 MHz 69.8 x 38.1 mm GSM / WCDMA / LTE ceiling-mount Antenna with N-type(F) connector 698..960 MHz, 1575.42 MHz, 1710..2700 MHz 86 x 199 mm GSM / WCDMA / LTE pole-mount Antenna with N-type(M) connector 698..960 MHz, 1710..2690 MHz 248 x 24.5 mm GSM / WCDMA low-profile adhesive-mount Antenna with cable and SMA(M) connector 824..960 MHz, 1710..2170 MHz 138 x 21 x 6 mm Laird Tech. MAF94300 HEPTA-SM Taoglas TG.30.8112 Taoglas OMB.8912.03F21 Taoglas FW.92.RNT.M Nearson T6150AM Laird Tech. TRA806/171033P Laird Tech. CMS69273 Laird Tech. OC69271-FNM Abracon APAMS-102 Table 49: Examples of external antennas UBX-13001118 - R25 Design-In Page 137 of 182 LISA-U2 series - System Integration Manual 2.4.4 Antenna detection functionality The internal antenna detect circuit is based on ADC measurement at ANT: the RF port is DC coupled to the ADC unit in the baseband chip which injects a DC current (10 A for 128 s) on ANT and measures the resulting DC voltage to evaluate the resistance from the ANT pad to GND. The antenna detection is forced by the +UANTR AT command: see the u-blox AT Commands Manual [2] for more details on how to access this feature. To achieve antenna detection functionality, use an RF antenna with a built-in resistor from the ANT signal to GND, or implement an equivalent solution with a circuit between the antenna cable connection and the radiating element as shown in Figure 67. Figure 67: Antenna detection circuit and antenna with diagnostic resistor Examples of components for the antenna detection diagnostic circuit are listed in the following table:

Description Part Number - Manufacturer DC Blocking Capacitor Murata GRM1555C1H220JA01 or equivalent RF Choke Inductor Murata LQG15HS68NJ02, LQG15HH68NJ02 or equivalent (Self Resonance Frequency ~1GHz) Resistor for Diagnostic 15 k 5%, various Manufacturers Table 50: Example of components for the antenna detection diagnostic circuit The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 67, the measured DC resistance will always be at the limits of the measurement range (respectively open or short), and there will be no means to distinguish between a defect on the antenna path with similar characteristics (respectively: removal of a linear antenna or RF cable shorted to GND for a PIFA antenna). Furthermore, any other DC signal injected to the RF connection from the ANT connector to the radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and to avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of the load resistor. UBX-13001118 - R25 Design-In Page 138 of 182 Front-End RF Module ANT Zo=50 Coaxial Antenna Cable DC Blocking RF Choke ADC Current Source Radiating Element DC Blocking RF Choke Resistor for Diagnostic Diagnostic Circuit LISA-U2 series Application Board Antenna Assembly LISA-U2 series - System Integration Manual For example, consider a GSM antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports the resistance value evaluated from the ANT connector to GND:

Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit over range report (see the u-blox AT Commands Manual [2]) means that that the antenna is not connected or the RF cable is broken Reported values below the measurement range minimum limit (1 k) will highlight a short to GND at the antenna or along the RF cable Measurement inside the valid measurement range and outside the expected range may indicate an unclean connection, damaged antenna or wrong value of the antenna load resistor for diagnostic purposes Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to the antenna cable length, antenna cable capacity and the used measurement method 2.5 ESD guidelines 2.5.1 ESD immunity test overview The immunity of devices integrating LISA-U2 modules to Electrostatic Discharge (ESD) is part of the Electromagnetic Compatibility (EMC) conformity which is required for products bearing the CE marking, compliant with the Radio Equipment Directive (2014/53/EU), the EMC Directive (2014/30/EU) and the Low Voltage Directive (2014/35/EU) issued by the Commission of the European Community. Compliance with these directives implies conformity with the following European Norms for device ESD immunity: ESD testing standard CENELEC EN 61000-4-2 [11] and the radio equipment standards EN 301 489-1 [12], EN 301 489-52 [13], the requirements of which are summarized in Table 51. The ESD immunity test is performed at the enclosure port, defined by EN 301 489-1 [12] as the physical boundary through which the electromagnetic field radiates. If the device implements an integral antenna, the enclosure port is defined as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port includes the antenna element and its interconnecting cable surfaces. The applicability of the ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489-1 [12]. Applicability of the ESD immunity test to the specific device ports or the specific interconnecting cables to auxiliary devices depends on the devices accessible interfaces and manufacturer requirements, as defined by ETSI EN 301 489-1 [12]. Contact discharges are performed at conductive surfaces, while air discharges are performed at insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000-4-2 [11]. For the definition of integral antenna, removable antenna, antenna port, device classification see the ETSI EN 301 489-1 [12]. The contact and air discharges are defined in CENELEC EN 61000-4-2 [11]. Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration Contact Discharge Air Discharge 4 kV 8 kV Table 51: ESD immunity requirements as defined by EN 61000-4-2, EN 301 489-1, EN 301 489-52 UBX-13001118 - R25 Design-In Page 139 of 182 LISA-U2 series - System Integration Manual 2.5.2 ESD immunity test of u-blox LISA-U2 series reference designs Although Electromagnetic Compatibility (EMC) certification is required for customized devices integrating LISA-U2 modules for RED and European Conformance CE mark, EMC certification (including ESD immunity) has been successfully performed on the LISA-U2 series modules reference designs according to the CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12], ETSI EN 301 489-52 [13]

European Norms. The EMC / ESD approved u-blox reference designs consist of a LISA-U2 series module soldered onto a motherboard which provides the supply interface, SIM card, headset, and communication port. An external antenna is connected to an SMA connector provided on the motherboard for the main Tx/Rx antenna. An additional external antenna is connected to an additional SMA connector provided on the motherboard for the Rx diversity antenna of the LISA-U230 modules. Since an external antenna is used, the antenna port can be separated from the enclosure port. The reference design is not enclosed in a box so that the enclosure port is not identified with physical surfaces. Therefore, some test cases cannot be applied. Only the antenna port is identified as accessible for direct ESD exposure. The u-blox LISA-U2 series reference designs implement all the ESD precautions described in section 2.5.3. u-blox LISA-U2 series reference designs ESD immunity test results are detailed in Table 52, according to test requirements stated in CENELEC EN 61000-4-2 [11], EN 301 489-1 [12], EN 301 489-52 [13]. Category Application Ref. Design Immunity Level Remarks Enclosure All

+4 kV / -4 kV Contact Discharge to coupling planes

(indirect contact discharge) Contact Discharges to conducted surfaces

(direct contact discharge) Air Discharge at insulating surfaces Enclosure port All Not Applicable Enclosure port All Not Applicable Main Antenna port All

+4 kV / -4 kV Rx Div Antenna port LISA-U230

+4 kV / -4 kV Main Antenna port All

+8 kV / -8 kV Rx Div Antenna port LISA-U230

+8 kV / -8 kV Test not applicable to u-blox reference design because it does not provide enclosure surface. The test is applicable only to equipments providing conductive enclosure surface. Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with conductive surface. Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with conductive surface. Test not applicable to the u-blox reference design because it does not provide an enclosure surface. The test is applicable only to equipments providing insulating enclosure surface. Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with insulating surface. Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with insulating surface. Table 52: Enclosure ESD immunity level of u-blox LISA-U2 series modules reference designs UBX-13001118 - R25 Design-In Page 140 of 182 LISA-U2 series - System Integration Manual 2.5.3 ESD application circuits The application circuits described in this section are recommended and should be implemented in any device that integrates a LISA-U2 module, according to the application board classification (see ETSI EN 301 489-1 [12]), to satisfy the requirements for the ESD immunity test summarized in Table 51. 2.5.3.1 Antenna interface The ANT pin of LISA-U2 modules provides ESD immunity up to 1000 V (contact and air discharge according to IEC 61000-4-2): a higher protection level is required if the line is externally accessible on the device (i.e. the application board where the LISA-U2 series module is mounted). The following precautions are suggested for satisfying ESD immunity test requirements:

If the device implements an embedded antenna, the device insulating enclosure should provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the whole antenna and cable surfaces If the device implements an external antenna and the antenna and its connecting cable do not provide a completely insulated enclosure able to provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the whole antenna and cable surfaces, an external high pass filter, consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil (Murata LQG15HN39NJ02) should be implemented at the antenna port as described in Figure 68, as implemented in the EMC / ESD approved reference design of LISA-U2 series modules Antenna detection functionality is not provided when implementing the high pass filter described in Figure 68 and Table 53 as the ESD protection for the antenna port of LISA-U2 series modules. Figure 68: Antenna port ESD immunity protection application circuit for LISA-U2 series modules Reference Description Part Number - Manufacturer C L 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata 39 nH Multilayer Chip Inductor L0G 0402 5%

LQG15HN39NJ02 - Murata Table 53: Example of parts for the antenna port ESD immunity protection application circuit for LISA-U2 series modules With LISA-U230 modules, the ANT_DIV pin provides ESD immunity up to 4 kV for direct Contact Discharge and up to 8 kV for Air Discharge: no further precaution to ESD immunity test is needed, as implemented in the EMC / ESD approved reference design of LISA-U230 modules. UBX-13001118 - R25 Design-In Page 141 of 182 Radiating Element C Antenna Cable ANT Zo = 50 Ohm L LISA-U2 series Application Board Enclosure Port External Antenna Enclosure Antenna Port LISA-U2 series - System Integration Manual 2.5.3.2 RESET_N pin The following precautions are suggested for the RESET_N line of LISA-U2 modules, depending on the application board handling, to satisfy the ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure It is recommended to keep the connection line to RESET_N as short as possible The maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the RESET_N pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection levels:

A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to the accessible point The RESET_N application circuit implemented in the EMC / ESD approved reference designs of the LISA-U2 series modules is described in Figure 20 and Table 19 (section 1.6.3). 2.5.3.3 SIM interface The following precautions are suggested for the LISA-U2 modules SIM interface (VSIM, SIM_RST, SIM_IO, SIM_CLK pins), depending on the application board handling, to satisfy the ESD immunity test requirements:

A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure It is suggested to use as short as possible connection lines at the SIM pins The maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if SIM interface pins are externally accessible on the application board. The following precautions are suggested to achieve higher protection levels:

A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on each SIM interface line, close to the accessible points (i.e. close to the SIM card holder) The SIM interface application circuit implemented in the EMC / ESD approved reference designs of LISA-U2 series modules versions is described in section 1.8.1. 2.5.3.4 Other pins and interfaces All the module pins that are externally accessible on the device integrating the LISA-U2 module should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489-1 [12]. Depending on applicability, to satisfy the ESD immunity test requirements according to UBX-13001118 - R25 Design-In Page 142 of 182 LISA-U2 series - System Integration Manual ESD category level, all the module pins that are externally accessible should be protected up to 4 kV for direct Contact Discharge and up to 8 kV for Air Discharge applied to the enclosure surface. The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to JESD22-A114F). Higher protection levels could be required if the relevant pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection levels:

USB interface: a very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140 ESD protection device) should be mounted on the USB_D+ and USB_D-

lines, close to the accessible points (i.e. close to the USB connector) SPI interface: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on the SPI_MISO, SPI_MOSI, SPI_SCLK, SPI_MRDY, SPI_SRDY lines, close to the accessible points CODEC_CLK: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0001) should be mounted on the CODEC_CLK line, close to the accessible point Other pins: a general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the related line, close to the accessible point UBX-13001118 - R25 Design-In Page 143 of 182 LISA-U2 series - System Integration Manual 3 Features description 3.1 Network indication Alternatively from their default settings, the GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate the network status (i.e. no service, registered home network, registered visitor network, voice or data call enabled), by means of the AT+UGPIOC command. For a detailed description, see section 1.12 and to u-blox AT Commands Manual [2], GPIO commands. 3.2 Antenna detection Antenna presence detection capability is provided, evaluating the resistance from the ANT pin to GND by means of an internal antenna detection circuit. The external antenna assembly must be provided with a built-in resistor (diagnostic circuit) to be detected. The antenna detection feature can be enabled through the +UANTR AT command. For more details regarding feature description and diagnostic circuit design-in, see section 2.4.4 and the u-blox AT Commands Manual [2]. 3.3 Jamming Detection In real network situations, modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operator choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operators carriers that are entitled to give access to the GSM/UMTS service. The Jamming Detection Feature detects such artificial interference and reports the start and stop of such conditions to the client, which can react appropriately by e.g. switching off the radio transceiver in order to reduce power consumption and monitoring the environment at constant periods. The feature consists of detecting, at the radio resource level, an anomalous source of interference and signaling it to the client with an unsolicited indication when the detection is entered or released. The jamming condition occurs when:

The module has lost synchronization with the serving cell and cannot select any other cell The band scan reveals at least n carriers with a power level equal or higher than the threshold On all such carriers, no synchronization is possible The number of minimum disturbing carriers and the power level threshold can be configured by the client by using the AT+UCD command [2]. The jamming condition is cleared when any of the above mentioned statements does not hold. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command (for more details, see the u-blox AT Commands Manual [2]). 3.4 TCP/IP and UDP/IP Via the AT commands, it is possible to access the TCP/IP and UDP/IP functionalities over the Packet Switched data connection. For more details about AT commands, see the u-blox AT Commands Manual [2]. UBX-13001118 - R25 Features description Page 144 of 182 LISA-U2 series - System Integration Manual LISA-U2 modules support the Direct Link mode for TCP and UDP sockets. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via the serial interface. In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa. To avoid data loss while using Direct Link, enable HW flow control on the serial interface. 3.4.1 Multiple PDP contexts and sockets Two PDP context types are defined:

external PDP context: IP packets are built by the DTE, the MTs IP instance only runs the IP relay function internal PDP context: the PDP context (relying on the MTs TCP/IP stack) is configured, established and handled via the data connection management packet switched data commands described in u-blox AT commands manual [2]

Multiple PDP contexts are supported. The DTE can access these PDP contexts either alternatively through the physical serial port, or simultaneously through the virtual serial ports of the multiplexer

(multiplexing mode MUX), with the following constraints:

Using the MTs embedded TCP/IP stack, only 1 internal PDP context is supported. This IP instance supports up to 7 sockets Using only external PDP contexts, it is possible to have at most 3 IP instances (with 3 different IP addresses) simultaneously. If in addition the internal PDP context is used, at most 2 external PDP contexts can be activated Secondary PDP contexts (PDP contexts sharing the IP address of a primary PDP context) are also supported. Traffic Flow Filters for such secondary contexts shall be specified according to 3GPP TS 23.060 [18]. At most 2 secondary PDP contexts can be activated, since the maximum number of PDP contexts, both normal and secondary, is always 3. 3.5 FTP LISA-U2 modules support the File Transfer Protocol and Secure File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. For more details about AT commands, see the u-blox AT Commands Manual [2]. FTP files can also be transferred using the FTP Direct Link:

FTP download: the data coming from the FTP server is forwarded to the application processor via the serial interface (for FTP without Direct Link mode, the data is always stored in the modules FFS) FTP upload: the data coming from the application processor via the serial interface is forwarded to the FTP server (for FTP without Direct Link mode, the data is read from the modules FFS) When Direct Link is used for a FTP file transfer, only the file content pass through the serial interface, whereas all the FTP commands handling is managed internally by the FTP application. Due to the limited size of the FFS module, FTP direct link is useful to transfer files with a size greater than the FFS. To avoid data loss while using direct link, enable HW flow control on the serial interface. UBX-13001118 - R25 Features description Page 145 of 182 3.6 HTTP LISA-U2 series - System Integration Manual LISA-U2 modules support Hypertext Transfer Protocol (HTTP/1.0) functionalities as an HTTP client is implemented: HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation. Up to 4 HTTP client contexts can be used simultaneously. LISA-U2 modules also support Secure Hypertext Transfer Protocol functionalities providing SSL encryption. For more details about AT commands, see the u-blox AT Commands Manual [2]. 3.7 SSL/TLS The modules support the Secure Sockets Layer (SSL) / Transport Layer Security (TLS) with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols. The SSL/TLS support provides various connection security aspects:

Server authentication10: use of the server certificate verification against a specific trusted certificate or a trusted certificates list Client authentication10: use of the client certificate and the corresponding private key Data security and integrity: data encryption and Hash Message Authentication Code (HMAC) generation The security aspects used during a connection depend on the SSL/TLS configuration and features supported. Table 55 contains the settings of the default SSL/TLS profile and Table 55 to Table 59 detail the main SSL/TLS supported capabilities of the products. For a complete list of supported configurations and settings, see the u-blox AT Commands Manual [2]. Settings Value Meaning Certificates validation level Level 0 The server certificate will not be checked or verified Minimum SSL/TLS version Any The server can use any of the TLS1.0/TLS1.1/TLS1.2 versions for the connection Cipher suite Automatic The cipher suite will be negotiated in the handshake process Trusted root certificate internal name None No certificate will be used for the server authentication Expected server host-name No server host-name is expected Client certificate internal name No client certificate will be used Client private key internal name No client private key will be used Client private key password No client private key password will be used Pre-shared key No pre-shared key password will be used None None None None None Table 54: Default SSL/TLS profile SSL/TLS Version Supported feature SSL 2.0 SSL 3.0 TLS 1.0 TLS 1.1 TLS 1.2 NO YES YES YES10 YES10 Table 55: SSL/TLS version support 10 Not supported by the "01", "x2" and "68" product versions UBX-13001118 - R25 Features description Page 146 of 182 LISA-U2 series - System Integration Manual Table 56: Authentication Algorithm RSA PSK Algorithm RC4 DES 3DES AES128 AES256 Algorithm MD5 SHA/SHA1 SHA256 SHA384 Table 57: Encryption Table 58: Message digest Supported feature Supported feature YES10 YES NO11 YES YES10 YES YES10 NO11 YES YES10 YES10 Supported feature Description Registry value Supported feature TLS_RSA_WITH_AES_128_CBC_SHA 0x00,0x2F TLS_RSA_WITH_AES_128_CBC_SHA256 0x00,0x3C TLS_RSA_WITH_AES_256_CBC_SHA 0x00,0x35 TLS_RSA_WITH_AES_256_CBC_SHA256 0x00,0x3D TLS_RSA_WITH_3DES_EDE_CBC_SHA 0x00,0x0A TLS_RSA_WITH_RC4_128_MD5 TLS_RSA_WITH_RC4_128_SHA TLS_PSK_WITH_AES_128_CBC_SHA TLS_PSK_WITH_AES_256_CBC_SHA 0x00,0x04 0x00,0x05 0x00,0x8C 0x00,0x8D TLS_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x8B TLS_RSA_PSK_WITH_AES_128_CBC_SHA 0x00,0x94 TLS_RSA_PSK_WITH_AES_256_CBC_SHA 0x00,0x95 TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x93 TLS_PSK_WITH_AES_128_CBC_SHA256 0x00,0xAE TLS_PSK_WITH_AES_256_CBC_SHA384 0x00,0xAF TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 0x00,0xB6 TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 0x00,0xB7 Table 59: TLS cipher suite registry 11 Supported only by "01", "x2" and "68" product versions YES10 YES10 YES10 YES10 YES10 NO11 NO11 YES10 YES10 YES10 YES10 YES10 YES10 YES10 YES10 YES10 YES10 UBX-13001118 - R25 Features description Page 147 of 182 LISA-U2 series - System Integration Manual 3.8 Dual stack IPv4/IPv6 Not supported by the "01", "x2", "63" and "68" product versions. LISA-U2 modules support both Internet Protocol version 4 and Internet Protocol version 6. For more details about dual stack IPv4/IPv6, see the u-blox AT Commands Manual [2]. 3.9 AssistNow clients and GNSS integration For customers using u-blox GNSS receivers, the LISA-U2 cellular modules feature embedded AssistNow clients. AssistNow A-GPS provides better GNSS performance and a faster Time-To-First-

Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [2]). LISA-U2 modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox GNSS receivers is available via the LISA-U2 series, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning chipset / module power-on/off. This means that GSM/WCDMA and GNSS can be controlled through a single serial port from any host processor. 3.10 Hybrid positioning and CellLocate Although GNSS is a widespread technology, its reliance on the visibility of extremely weak GNSS satellite signals means that positioning is not always possible. Especially difficult environments for GNSS are indoors, in enclosed or underground parking garages, as well as in urban canyons where GNSS signals are blocked or jammed by multipath interference. The situation can be improved by augmenting GNSS receiver data with cellular network information to provide positioning information even when GNSS reception is degraded or absent. This additional information can benefit numerous applications. 3.10.1 Positioning through cellular information: CellLocate u-blox CellLocate enables the estimation of device position based on the parameters of the mobile network cells visible to the specific device. To estimate its position, the u-blox cellular module sends the CellLocate server the parameters of network cells visible to it using a UDP connection. In return, the server provides the estimated position based on the CellLocate database. The u-blox cellular module can either send the parameters of the visible home network cells only (normal scan), or the parameters of all surrounding cells of all mobile operators (deep scan). Normal scan is only possible in 2G mode. UBX-13001118 - R25 Features description Page 148 of 182 LISA-U2 series - System Integration Manual The CellLocate database is compiled from the position of devices which observed, in the past, a specific cell or set of cells (historical observations) as follows:

1. Several devices reported their position to the CellLocate server when observing a specific cell

(the As in the picture represent the position of the devices which observed the same cell A) 2. The CellLocate server defines the area of Cell A visibility 3. If a new device reports the observation of Cell A, CellLocate is able to provide the estimated position from the area of visibility UBX-13001118 - R25 Features description Page 149 of 182 4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of visibility. LISA-U2 series - System Integration Manual CellLocate is implemented using a set of two AT commands that allow configuration of the CellLocate service (AT+ULOCCELL) and requesting position according to the user configuration

(AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy. The accuracy of the position estimated by CellLocate depends on the availability of historical observations in the specific area. 3.10.2 Hybrid positioning With u-blox Hybrid positioning technology, u-blox cellular devices can be triggered to provide their current position using either a u-blox GNSS receiver or the position estimated from CellLocate. The choice depends on which positioning method provides the best and fastest solution according to the user configuration, exploiting the benefit of having multiple and complementary positioning methods. Hybrid positioning is implemented through a set of three AT commands that allow configuration of the GNSS receiver (AT+ULOCGNSS), configuration of the CellLocate service (AT+ULOCCELL), and requesting the position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy (if the position has been estimated by CellLocate), and additional parameters if the position has been computed by the GNSS receiver. The configuration of mobile network cells does not remain static (e.g. new cells are continuously added or existing cells are reconfigured by the network operators). For this reason, when a Hybrid positioning method has been triggered and the GNSS receiver calculates the position, a database self-

learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy. The use of hybrid positioning requires a connection via the DDC (I2C) bus between the LISA-U2 cellular module and the u-blox GNSS receiver (see section 1.10). See the GNSS Implementation Application Note [15] for the complete description of the feature. u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate server u-blox is unable to track the SIM used or the specific device. UBX-13001118 - R25 Features description Page 150 of 182 LISA-U2 series - System Integration Manual 3.11 Control Plane Aiding / Location Services (LCS) Not supported by the "01", "x2", "63" and "68" product versions With the Assisted GPS feature, a location server provides the module with the GPS system information that otherwise needs to be downloaded from satellites. The feature allows faster position fixes, increases sensitivity and reduces module power consumption. The feature is invoked by the module through LCS Supplementary Services or by the Network during emergency calls. The assisted GPS Location Services feature is based on the Radio Resources Location Protocol

(RRLP), according to 3GPP TS 44.031 [26], and Radio Resource Control (RRC) according to 3GPP TS 25.331 [27]. For more details, see the u-blox AT Commands Manual [2]. 3.12 Firmware update Over AT (FOAT) 3.12.1 Overview This feature allows upgrading the module firmware over the UART, USB and SPI interfaces, using AT Commands. The AT Command AT+UFWUPD triggers a reboot followed by the upgrade procedure at a specified The Xmodem-1k protocol is used for downloading the new FW image via a terminal application A special boot loader in the module performs FW installation, security verifications and module baud rate reboot Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up and restarts the firmware download from the Xmodem-1k handshake. After completing the upgrade, the module is reset again and wakes up in normal boot mode 3.12.2 FOAT procedure The application processor must proceed in the following way:

Send the AT+UFWUPD command through the UART or over the USB interface, specifying the file Reconfigure the serial communication at the selected baud rate, without flow control with the type and the desired baud rate Xmodem-1k protocol Send the new FW image via Xmodem-1k For more details about Firmware update Over AT procedure, see the u-blox AT Commands Manual [2]

and the Firmware Update Application Note [16]. 3.13 Firmware update Over the Air (FOTA) Firmware update Over the Air (FOTA) is supported only by the 8x product versions. This feature allows upgrading the module firmware over the 3G / 2G air interface. The firmware installation procedure triggers the firmware update installation via AT command, starting from an update file stored in the modules file system. In order to reduce the amount of data to be transmitted over the air, the implemented FOTA feature requires downloading only a delta file instead of the full firmware. The delta file contains only the differences between the two firmware versions (old and new). For more details about the Firmware update Over the Air procedure, see the Firmware Update Application Note [16] and the u-blox AT Commands Manual [2], +UFWINSTALL AT command. UBX-13001118 - R25 Features description Page 151 of 182 LISA-U2 series - System Integration Manual 3.14 In-Band modem (eCall / ERA-GLONASS) Not supported by supported by the "01", "x2", "63" and "68" product versions. LISA-U2 module supports an In-Band modem solution for eCall and ERA-GLONASS emergency call applications over cellular networks, implemented according to the 3GPP TS 26.267 [23], BS EN 16062:2011 [24] and ETSI TS 122 101 [25] specifications. eCall (European) and ERA-GLONASS (Russian) are two initiatives to combine mobile communications and satellite positioning to provide rapid assistance to motorists in the event of a collision, implementing automated emergency response system, based respectively on the corresponding GPS and GLONASS positioning systems. When activated, the in-vehicle systems (IVS) automatically initiate an emergency call carrying both voice and data (including location data) directly to the nearest Public Safety Answering Point (PSAP) to determine whether rescue services should be dispatched to the known position. Figure 69: eCall and ERA-GLONASS automated emergency response systems diagram flow 3.15 SIM Access Profile (SAP) SIM access profile (SAP) feature allows LISA-U2 modules to access and use a remote (U)SIM card instead of the local SIM card directly connected to the module (U)SIM interface. LISA-U2 modules provide a dedicated USB SAP channel and dedicated multiplexer SAP channel over UART and SPI for communication with the remote (U)SIM card. The communication between LISA-U2 modules and the remote SIM is conformed to the client-server paradigm: LISA-U2 module is the SAP client establishing a connection and performing data exchange to an SAP server directly connected to the remote SIM that is used by the LISA-U2 module for GSM/UMTS network operations. The SAP communication protocol is based on the SIM Access Profile Interoperability Specification [21]. LISA-U2 modules do not support the SAP server role: the module acts only as an SAP client. A typical application using the SAP feature is the scenario where a device such as an embedded car-

phone with an integrated LISA-U2 module uses a remote SIM included in an external user device (e.g. a simple SIM card reader or a portable phone), which is brought into the car. The car-phone accesses the GSM/UMTS network using the remote SIM in the external device. LISA-U2 modules, acting as an SAP client, can be connected to an SAP server by a completely wired connection, as shown in Figure 70. UBX-13001118 - R25 Features description Page 152 of 182 LISA-U2 series - System Integration Manual Figure 70: Remote SIM access via completely wired connection As stated in the SIM Access Profile Interoperability Specification [21], the SAP client can be connected to the SAP server by means of a Bluetooth cellular link, using additional Bluetooth transceivers. In this case, the application processor wired to the LISA-U2 modules establishes and controls the Bluetooth connection using the SAP profile, and routes data received over a serial interface channel to data transferred over a Bluetooth interface and vice versa, as shown in Figure 71. Figure 71: Remote SIM access via Bluetooth and wired connections The application processor can start an SAP connection negotiation between the LISA-U2 module SAP client and an SAP server using a custom AT command (for more details, see the u-blox AT Commands Manual [2]). While the connection with the SAP server is not fully established, the LISA-U2 module continues to operate with the attached (local) SIM, if present. Once the connection is established and negotiated, the LISA-U2 module performs a detach operation from the local SIM followed by an attach operation to the remote one. Then the remotely attached SIM is used for any GSM/UMTS network operation. URC indications are provided to inform the user about the state of both the local and remote SIM. The insertion and the removal of the local SIM card are notified if a proper card presence detection circuit using the GPIO5 of LISA-U2 modules is implemented as shown in the section 1.8.1, and if the related SIM card detection and SIM hot insertion/removal functions are enabled by AT commands (for more details, see the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 AT commands). Upon SAP deactivation, the LISA-U2 modules perform a detach operation from the remote SIM followed by an attach operation to the local one, if present. UBX-13001118 - R25 Features description Page 153 of 182 Device including SIM Device including LISA SAP Serial Interface Application Processor LISA module SAP Client SAP Serial Interface

(USB SAP channel, or MUX SAP channel over UART or SPI) GSM/UMTS Interface Mobile Equipment SAP Server Remote SIM Local SIM

(optional) Device including SIM Device including LISA Mobile Equipment SAP Server Bluetooth Transceiver SAP Bluetooth Interface Bluetooth Transceiver Application Processor SAP LISA module Serial Interface

(USB SAP channel, or MUX SAP channel over UART or SPI) SAP Client GSM/UMTS Interface Remote SIM Local SIM

(optional) LISA-U2 series - System Integration Manual 3.16 Smart Temperature Management Cellular modules independent of the specific model always have a well-defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. Nevertheless there are environmental conditions that can affect the operating temperature, e.g. if the device is located near a heating/cooling source, if there is/isnt air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case, its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless, an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. 3.16.1 Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. See the u-blox AT Commands Manual [2] for more details. The cellular module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the cellular module: the measured value could be different from the environmental temperature (Ta). Figure 72: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 72) named t-2, t-1, t+1 and t+2. Within the first limit, (t-1 < Ti < t+1), the cellular module is in the normal working range, the Safe Area. In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid temperature range, but the measured temperature approaches the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition. Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage. For security reasons, the shutdown is suspended in case an emergency call in progress. In this case, the device will switch off at call termination. The user can decide at any time to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled, there is no embedded protection against disallowed temperature conditions. UBX-13001118 - R25 Features description Page 154 of 182 Valid temperature range Dangerous Warning area area Safe area t-2 t-1 Warning Dangerous area area t+1 t+2 Figure 73 shows the flow diagram implemented for the Smart Temperature Supervisor. LISA-U2 series - System Integration Manual Figure 73: Smart Temperature Supervisor (STS) flow diagram 3.16.2 Threshold definitions When the application of cellular module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the cellular module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat This behavior is partially compensated by the definition of the upper shutdown threshold (t+2) that is slightly higher than the declared environmental temperature limit. UBX-13001118 - R25 Features description Page 155 of 182 Feature disabled:

no action Yes Feature enabled

(full logic or indication only) No IF STS enabled Read temperature Yes Temperature is within normal operating range IF

(t-1<Ti<t+1) No Yes IF

(t-2<Ti<t+2) No No further actions Previously outside of Safe Area Yes Tempetature is back to safe area Tempetature is within warning area No Tempetature is outside valid temperature range Send notification

(safe) Send notification

(warning) Send notification

(dangerous) No IF Full Logic Enabled Feature enabled in indication only mode:

no further actions Yes Featuere enabled in full logic mode Wait emergency call termination Yes IF emerg. call in progress No Send shutdown notification Shut the device down LISA-U2 series - System Integration Manual The temperature thresholds are defined in Table 60. Symbol Parameter Temperature Remarks Low temperature shutdown 40 C Equal to the absolute minimum temperature rating for the cellular module (the lower limit of the extended temperature range) Low temperature warning 30 C 10 C above t-2 High temperature warning

+77 C t-2 t-1 t+1 20 C below t+2. The higher warning area for the upper range ensures that any countermeasures used to limit the thermal heating will become effective, even considering some thermal inertia of the complete assembly. Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient temperature Ta in the reference setup (*) equals the absolute maximum temperature rating (upper limit of the extended temperature range) t+2 High temperature shutdown +97 C

(*)LISA-U2 module mounted on a 90 x 70 x 1.46 mm 4-Layers PCB with a high coverage of copper within the climatic chamber Table 60: Thresholds definition for the Smart Temperature Supervisor on the LISA-U2 modules The sensor measures the board temperature inside the shields, which can differ from the ambient temperature. 3.17 Bearer Independent Protocol Not supported by the "01", "x2", "63" and "68" product versions. The Bearer Independent Protocol is a mechanism by which a cellular module provides a SIM with access to the data bearers supported by the network. With the Bearer Independent Protocol (BIP) for Over-the-Air SIM provisioning, the data transfer from and to the SIM uses either an already active PDP context or a new PDP context established with the APN provided by the SIM card. For more details, see the u-blox AT Commands Manual [2]. 3.18 Multi-Level Precedence and Pre-emption Service Not supported by the "01", "x2", "63" and "68" product versions. The Multi-Level Precedence and Pre-emption Service (eMLPP) permits to handle the call priority. The maximum priority associated to a user is set in the SIM: within this threshold, the user can assign different priorities to the calls. This results in a differentiated treatment of the calls by the network in case of abnormal events such as handovers to congested cells. For more details, see the u-blox AT Commands Manual [2]. 3.19 Network Friendly Mode Not supported by the 01", "x2", "63" and "68" product versions. The Network Friendly Mode (NFM) feature provides a more efficient access to the network since it regulates the number of network accesses per service type over a configurable amount of time, avoiding scenarios in which the cellular module continuously retries a registration or a PDP context activation procedure until it is successful. In case of appropriate network rejection errors, a back-off timer can be started: when the timer is running or the number of allowed accesses is reached, further attempts are denied and an URC may be enabled to indicate the time remaining before a further attempt can be served. The back-off timer controls the temporal spread of successive attempts to register to CS or PS services, to activate a PDP context and to send SMS messages. For more details, see the u-blox AT Commands Manual [2]. UBX-13001118 - R25 Features description Page 156 of 182 LISA-U2 series - System Integration Manual 3.20 Power saving The power saving configuration is disabled by default, but it can be enabled using the AT+UPSV command. When power saving is enabled, the module automatically enters the low-power idle mode whenever possible, reducing current consumption. During the low-power idle mode, the module is not ready to communicate with an external device by means of the application interfaces, since it is configured to reduce power consumption. The module wakes up from the low-power idle mode to the active mode in these events:

Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see sections 1.5.3.3, 1.9.2.3) Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 has been set (see section 1.9.2.3) Data received on the UART interface, if HW flow control has been disabled by AT&K0 and AT+UPSV=1 has been set (see section 1.9.2.3) RTS input set ON by the DTE if HW flow control has been disabled by AT&K0 and AT+UPSV=2 has DTR input set ON by DTE if AT+UPSV=3 has been set (not supported by the 01 product versions, been set (see section 1.9.2.3) see section 1.9.2.3) USB detection, applying 5 V (typ.) to VUSB_DET input (see section 1.9.3) The connected USB host forces a remote wake-up of the module as a USB device (see section 1.9.3) The connected SPI master indicates by means of the SPI_MRDY input signal of the module that it is ready for transmission or reception over the SPI interface (see section 1.9.4) The connected u-blox GNSS receiver indicates by means of the GPIO3 pin previously configured for the GNSS data ready function that it is ready to send data over the I2C / DDC interface (see sections 1.10, 1.12) RTC alarm previously configured by AT command (see the u-blox AT Commands Manual [2], AT+CALA) For the complete description of the AT+UPSV command, see the u-blox AT Commands Manual [2]. For the definition and the description of LISA-U2 series modules operating modes, including the events forcing transitions between the different operating modes, see section 1.4. For the description of current consumption in idle and active operating modes, see sections 1.5.3.3, 1.5.3.4. For the description of the UART behavior related to module power saving configuration, see section 1.9.2.3. For the description of the USB behavior related to module power saving configuration, see section 1.9.3.2. For the description of the SPI behavior related to module power saving configuration, see section 1.9.4.2. UBX-13001118 - R25 Features description Page 157 of 182 LISA-U2 series - System Integration Manual 4 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 4.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the LISA-U2 series Data Sheet [1] and the u-blox Package Information Guide [20]. The LISA-U2 modules are Electrostatic Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. 4.2 Soldering 4.2.1 Soldering paste The use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste:

OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification:

95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature: +217 C Stencil Thickness:

150 m for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.2.2. The quality of the solder joints on the connectors (half vias) should meet the appropriate IPC specification. 4.2.2 Reflow soldering A convection type soldering oven is strongly recommended over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the IPC-7530A Guidelines for temperature profiling for mass soldering (reflow and wave) processes. Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device!

Be aware that IPC/JEDEC J-STD-020 applies to integrated circuits, and cannot be properly applied to module devices. UBX-13001118 - R25 Handling and soldering Page 158 of 182 Preheat phase LISA-U2 series - System Integration Manual Initial heating of component leads and balls. Residual humidity will be dried out. This preheat phase will not replace prior baking procedures. Temperature rise rate: max 3 C/s If the temperature rise is too rapid in the preheat phase, it may cause excessive slumping. Time: 60 120 s If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. End Temperature: 150 - 200 C If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of +217 C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above +217 C liquidus temperature: 40 - 60 seconds Peak reflow temperature: +245 C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4 C / s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Figure 74: Recommended soldering profile LISA-U2 modules must not be soldered with a damp heat process. UBX-13001118 - R25 Handling and soldering Page 159 of 182

[C]

250 217 200 150 100 50 Preheat Heating Peak Temp. 245C Cooling Liquidus Temperature max 3C/s 60 - 120 s 40 - 60 s End Temp. 150 - 200C max 4C/s

[C]

250 217 200 150 50 Typical Leadfree Soldering Profile 100 Elapsed time [s]

LISA-U2 series - System Integration Manual 4.2.3 Optical inspection After soldering the LISA-U2 modules, inspect the modules optically to verify that the module is accurately aligned and centered. 4.2.4 Cleaning Cleaning the soldered modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results, use a "no clean" soldering paste and eliminate the cleaning step after the soldering. 4.2.5 Repeated reflow soldering Repeated reflow soldering processes and soldering the module upside-down are not recommended. Boards with components on both sides may require two reflow cycles. In this case, the module should always be placed on the side of the board that is submitted into the last reflow cycle. The reason for this (besides others) is the risk of the module falling off due to the significantly higher weight in relation to other components. u-blox gives no warranty against damages to LISA-U2 modules caused by performing more than a total of two reflow soldering processes (one reflow soldering process to mount the LISA-U2 module, plus one reflow soldering process to mount other parts). 4.2.6 Wave soldering Boards with combined through-hole technology (THT) components and surface-mount technology

(SMT) devices require wave soldering to solder the THT components. No more than one wave soldering process is allowed for a board with a LISA-U2 module already populated on it. Wave soldering process is not recommended for LISA-U2 series LCC modules. Performing a wave soldering process on the module can result in severe damage to the device!

u-blox gives no warranty against damages to LISA-U2 modules caused by performing more than a total of two soldering processes (one reflow soldering process to mount the LISA-U2 module, plus one wave soldering process to mount other parts). 4.2.7 Hand soldering Hand soldering is not recommended. UBX-13001118 - R25 Handling and soldering Page 160 of 182 LISA-U2 series - System Integration Manual 4.2.8 Rework The LISA-U2 modules can be unsoldered from the baseboard using a hot air gun. Avoid overheating the module. After the module is removed, clean the pads before placing. Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty. 4.2.9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials affect the HF properties of the LISA-U2 modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, so care is required in applying the coating. Conformal coating of the module will void the warranty. 4.2.10 Casting If casting is required, use viscose or another type of silicone-pottant. The OEM is strongly advised to qualify such processes in combination with the LISA-U2 modules before implementing this in production. Casting will void the warranty. 4.2.11 Grounding metal covers Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interferences and noise. u-blox gives no warranty for damages to the LISA-U2 modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. 4.2.12 Use of ultrasonic processes LISA-U2 modules contain components which are sensitive to ultrasonic waves. Use of any ultrasonic processes (cleaning, welding etc.) may cause damage to the module. u-blox gives no warranty against damages to the LISA-U2 modules caused by any ultrasonic processes. UBX-13001118 - R25 Handling and soldering Page 161 of 182 LISA-U2 series - System Integration Manual 5 Product Testing 5.1 u-blox in-series production test u-blox focuses on high quality for its products. All units produced are fully tested. Defective units are analyzed in detail to improve production quality. This is achieved with automatic test equipment, which delivers a detailed test report for each unit. The following measurements are made:

Digital self-test (firmware download, flash firmware verification, IMEI programming) Measurement of voltages and currents Adjustment of ADC measurement interfaces Functional tests (serial interface communication, real time clock, battery charger, temperature sensor, antenna detection, SIM card communication) Digital tests (GPIOs, digital interfaces) Measurement and calibration of RF characteristics in all supported bands (receiver S/N verification, frequency tuning of reference clock, calibration of transmitter and receiver power levels) Verification of RF characteristics after calibration (modulation accuracy, power levels and spectrum performance are checked to be within tolerances when the calibration parameters are applied) Figure 75: Automatic test equipment for module tests UBX-13001118 - R25 Product Testing Page 162 of 182 LISA-U2 series - System Integration Manual 5.2 Test parameters for OEM manufacturer Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. An OEM manufacturer should focus on:

Module assembly on the device; it should be verified that:

o The soldering and handling process did not damaged the module components o All module pins are well soldered on the device board o There are no short circuits between pins Component assembly on the device; it should be verified that:

o Communication with the host controller can be established o The interfaces between the module and the device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result. Module AT commands are used to perform functional tests (communication with host controller, check the SIM card interface, check the communication between module and GNSS, GPIOs, etc.) and to perform RF performance tests. 5.2.1 Go/No go tests for integrated devices A Go/No go test is to compare the signal quality with a Golden Device in a position with excellent 2G/3G network coverage and after having dialed a call (see the u-blox AT Commands Manual [2], AT+CSQ command: <rssi>, <ber> parameters). These kinds of test may be useful as a go/no go test but not for RF performance measurements. This test is suitable to check the communication with the host controller and SIM card, the audio and power supply functionality, and verify if components at the antenna interface are well soldered. 5.2.2 Functional tests providing RF operation Overall RF performance test of the device including antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator using the AT+UTEST command over the AT interface. The AT+UTEST command gives a simple interface to set the module to Rx and Tx test modes ignoring the 2G/3G signaling protocol. The command can set the module:

Into transmitting mode in a specified channel and power level in all supported modulation schemes

(single slot GMSK, single slot 8PSK, WCDMA) and 2G, 3G bands Into receiving mode in a specified channel to return the measured power level in all supported bands 2G, 3G See the u-blox AT Commands Manual [2] for the AT+UTEST command syntax description. See the End user test Application Note [19] for the AT+UTEST command user guide, limitations and examples of use. UBX-13001118 - R25 Product Testing Page 163 of 182 LISA-U2 series - System Integration Manual Figure 76: Setup with spectrum analyzer and signal generator for radiated measurements This feature allows the measurement of the transmitter and receiver power levels to check the component assembly related to the module antenna interface and to check other device interfaces on which the RF performance depends. To avoid module damage during the transmitter test, a suitable antenna according to module specifications or a 50 termination must be connected to ANT pin. To avoid module damage during receiver test the maximum power level received at ANT pin must meet module specifications. The AT+UTEST command sets the module to emit RF power ignoring 2G/3G signaling protocol. This emission can generate interference that can be prohibited by law in some countries. The use of this feature is intended for testing purposes in controlled environments by a qualified user and must not be used during the normal module operation. Follow the instructions suggested in the u-

blox documentation. u-blox assumes no responsibilities for the inappropriate use of this feature. Example of production tests for an OEM manufacturer:

1. Trigger TX GMSK burst at low Power Control Level (lower than 15) or a RX measure reporting to check:

o o o o o If the ANT pin is soldered If the ANT pin is in short circuit If the module was damaged during soldering process or handling (ESD, mechanical shock) If the antenna matching components on the application board are soldered If the integrated antenna is correctly connected To avoid module damage during the transmitter test when good antenna termination is not guaranteed, use a low Power Control Level (i.e. PCL lower or equal to 15). u-blox assumes no responsibilities for module damages caused by an inappropriate use of this feature. UBX-13001118 - R25 Product Testing Page 164 of 182 Application Processor LISA-U2 series AT Commands Wireless Antenna Wideband Antenna ANT TX IN Spectrum Analyzer or Power Meter Application Processor LISA-U2 series AT Commands Wireless Antenna Wideband Antenna ANT RX OUT Signal Generator Application Board Application Board LISA-U2 series - System Integration Manual 2. Trigger TX GMSK burst at maximum PCL:

o To check if the power supply is correctly assembled and is able to deliver the required current 3. Trigger TX GMSK and 8PSK burst and WCDMA signal:

o To measure current consumption o To check if the module components were damaged during the soldering process or during handling (ESD, mechanical shock) 4. Trigger RX measurement:

o To test the receiver signal level. Assuming that there are no losses between the ANT pin or ANT_DIV pin and the input power source, be aware that the power level estimated by the module can vary approximately within 3GPP tolerances for the average value o To check if the module was damaged during the soldering process or during handling (ESD, mechanical shock) 5. Trigger TX GMSK and 8PSK burst and WCDMA signal and RX measurement to check:

o Overall RF performance of the device including antenna measuring TX and RX power levels UBX-13001118 - R25 Product Testing Page 165 of 182 LISA-U2 series - System Integration Manual Appendix A Migration from LISA-U1 to LISA-U2 series Migrating LISA-U1 series designs to LISA-U2 series modules is a straight-forward procedure. Nevertheless, there are some points to be considered during the migration. A.1 Checklist for migration Have you chosen the optimal module?

For HSDPA category 14, 6-band 3G, Digital Audio Interfaces support, select a LISA-U230 module. For HSDPA category 8, 6-band 3G, Digital Audio Interfaces support, select a suitable LISA-U200 module. For HSDPA category 8, 5-band 3G, Digital Audio Interfaces support, select LISA-U201 module. For HSDPA category 8, 2-band 3G 850/1900 (North America), Digital Audio Interfaces support, select a suitable LISA-U260 module. For HSDPA category 8, 2-band 3G 900/2100 (Europe, Asia, Middle-East and Africa), Digital Audio Interfaces support, select a suitable LISA-U270 module. Check LISA-U2 series Hardware Requirements Check the supported 3G bands for proper antenna circuit development, since LISA-U2 supports various 3G bands in comparison to LISA-U1 series cellular modules. Check audio requirements, since Analog Audio Interfaces are not supported by LISA-U2 series. Check audio requirements, since Digital Audio Interfaces are supported by LISA-U2 series modules. Check the PWR_ON low pulse time specified to switch on the module, since PWR_ON low pulse time requirement is different in comparison to LISA-U1 series modules. Check the PWR_ON behavior, since LISA-U2 series modules can be switched off forcing PWR_ON pin to the low level for at least 1 second. Check the PWR_ON input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the PWR_ON input by an open drain or open collector driver as recommended. Check the RESET_N input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the RESET_N input by an open drain or open collector driver as recommended. Check the V_BCKP operating characteristics, since they are slightly changed in comparison to LISA-U1 series modules. Check internal active pull-up / down values at digital interface input pins and the current capability of digital interface output pins, since they are slightly changed in comparison to LISA-

U1 series modules. Check board layout, since additional signals keep-out area must be implemented on the top layer of the application board, below the LISA-U2 modules, due to GND opening on the module bottom layer. UBX-13001118 - R25 Appendix Page 166 of 182 LISA-U2 series - System Integration Manual A.2 Software migration A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules Software migration from LISA-U1 to LISA-U2 series cellular modules is a straight-forward procedure. Nevertheless, there are some differences to be considered with firmware versions. Like its predecessors, the LISA-U2 series cellular module supports AT commands according to 3GPP standards: TS 27.007 [4], TS 27.005 [5], TS 27.010 [6] and the u-blox AT command extension. Backward compatibility has been maintained as far as possible. For the complete list of supported AT commands and their syntax, see the u-blox AT Commands Manual [2]. A.3 Hardware migration A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules LISA-U2 series modules have been designed with backward compatibility in mind, but some minor differences were unavoidable. These minor differences will however not be relevant for the majority of the LISA-U1 series designs. A clean and stable supply is required by LISA-U2 as for the LISA-U1 series: low ripple and low voltage drop must be guaranteed at the VCC pins. The voltage provided must be within the normal operating range limits to allow module switch-on and must be above the minimum limit of the extended operating range to avoid module switch-off. Consider that there are large current spikes in connected mode when a GSM call is enabled. LISA-U2 series provide wider VCC input voltage range compared to LISA-U1 series. The ANT pin has 50 nominal characteristic impedance and must be connected to the antenna through a 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. The antenna and the whole RF circuit must provide optimal radiating characteristics on the entire supported bands: note that LISA-U2 supports different 3G bands in comparison to LISA-U1 series modules. An external application circuit can be implemented on the application device integrating LISA-U2 series modules to satisfy ESD immunity test requirements at the antenna interface, as described in Figure 68 and Table 53 in section 2.5.3. The same application circuit is not applicable for LISA-U1 series. LISA-U230 modules provide the RF antenna input for Rx diversity on the pin 74 (named ANT_DIV): it has an impedance of 50 . The same pad is a reserved pin on LISA-U1 series and on the other LISA-U2 series modules. Analog audio interfaces are not supported by LISA-U2 series modules, but a second 4-wire I2S digital audio interface is provided instead of the 4 analog audio pins. The same 4 pins can be configured as GPIO on LISA-U2 series modules. Analog audio can be provided with an external audio codec connected to LISA-U2 series modules, implementing the application circuit described in Figure 50. An external audio codec can be connected to the I2S digital audio interface of LISA-U1 series modules as shown in the same application circuit described in Figure 50. In this case, the application processor should properly control the audio codec by I2C interface and should properly provide clock reference to the audio codec. This circuit allows migration from LISA-U1 series to LISA-U2 series, providing analog audio with the same application circuit. UBX-13001118 - R25 Appendix Page 167 of 182 LISA-U2 series - System Integration Manual PWR_ON low pulse time required to switch on the module is different in comparison to LISA-U1 series modules. LISA-U2 series can be switched off forcing PWR_ON pin to the low level for at least 1 second. PWR_ON and RESET_N input voltage thresholds are slightly changed in comparison to LISA-U1 series modules, but this is not relevant driving PWR_ON and RESET_N inputs by open drain / collector drivers as recommended. V_BCKP operating characteristics are slightly changed in comparison to LISA-U1 series modules. The voltage level of all the digital interfaces of LISA-U2 series modules is 1.8 V as for LISA-U1 series modules. The internal active pull-up / pull-down values at the digital interface input pins and the current capability of digital interface output pins LISA-U2 series modules are slightly changed in comparison to LISA-U1 series modules. UART of LISA-U2 series supports autobauding (default setting) and 921600 bit/s baud rate. LISA-U2 series provide one additional USB CDC for the remote SIM Access Profile (SAP). The 5 pins of the SPI / IPC Serial Interface can be configured as GPIOs on LISA-U2 series. The DDC (I2C) interface of LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and at the same time to control an external audio codec. The LISA-U2 series module acts as an I2C master which can communicate to two I2C slaves as permitted by the I2C bus specifications [8]. LISA-U2 modules provide additional GPIO functions: Module Status and Operating Mode Indications. LISA-U2 modules are SMT modules and share the same compact form factor as the LISA-U1 series, featuring Leadless Chip Carrier (LCC) packaging technology. An additional signal keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to the GND opening on the module bottom layer. Detailed pinout and layout comparisons between LISA-U1 series and LISA-U2 series modules, with remarks for migration, are provided in subsections A.3.2 and A.3.3. For more information about the electrical characteristics of the LISA-U1 and LISA-U2 series modules, see the LISA-U1 series Data Sheet [28] and the LISA-U2 series Data Sheet [1]. UBX-13001118 - R25 Appendix Page 168 of 182 LISA-U2 series - System Integration Manual A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series 1 2 3 4 5 Figure 77: LISA-U1 series pin assignment Figure 78: LISA-U2 series pin assignment

(highlighted name/function changes) LISA-U1 series LISA-U2 series No Name Description Name Description Remarks for Migration GND Ground GND Ground V_BCKP RTC supply input/output V_BCKP RTC supply input/output V_BCKP operating characteristics difference:

LISA-U1 series:

V_BCKP output = 2.3 V typ. V_BCKP input = 1.0 V min / 2.5 V max LISA-U2 series:

V_BCKP output = 1.8 V typ. V_BCKP input = 1.0 V min / 1.9 V max GND V_INT Ground Digital Interfaces supply output GND V_INT Ground Digital Interfaces supply output No difference:

V_INT output = 1.8 V typ., 70 mA max. RSVD RESERVED pin RSVD RESERVED pin No difference:

This pin must be connected to GND 68 GND Ground Ground GND DSR 9 DSR UART data set ready output UART data set ready output Circuit 107 (DSR) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 1 mA UBX-13001118 - R25 Appendix Page 169 of 182 6 7 5 7 D N G D N G 4 7 D V S R 3 7 D N G 2 7 D N G 1 7 D N G 0 7 D N G 9 6 D N G 8 6 T N A 7 6 D N G 6 6 D N G LISA-U1 Top View RSVD SPI RSVD Analog Audio GND 65 GND 64 VCC 63 VCC 62 VCC 61 GND 60 SPI_MRDY 59 SPI_SRDY 58 SPI_MISO 57 SPI_MOSI 56 SPI_SCLK 55 RSVD / SPK_N 54 RSVD / SPK_P 53 RSVD 52 GPIO5 51 VSIM 50 SIM_RST 49 SIM_IO 48 SIM_CLK 47 SDA 46 SCL 45 RSVD / I2S_RXD 44 RSVD / I2S_CLK 43 RSVD / I2S_TXD 42 RSVD / I2S_WA 41 RSVD / MIC_P 40 RSVD / MIC_N 39 Pin 2838 = GND 8 2 9 2 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 GND V_BCKP GND V_INT RSVD GND GND GND DSR DCD DTR RTS CTS TXD RXD GND 10 RI VUSB_DET PWR_ON 20 GPIO1 GPIO2 RESET_N GPIO3 GPIO4 GND USB_D-

USB_D+

Rx Div SPI or GPIO Clock Out Digital Audio or GPIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 GND V_BCKP GND V_INT RSVD GND GND GND DSR RI DCD DTR RTS CTS TXD RXD GND VUSB_DET PWR_ON 20 GPIO1 GPIO2 RESET_N GPIO3 GPIO4 GND USB_D-

USB_D+

6 7 5 7 D N G D N G 3 7 D N G 2 7 D N G 1 7 D N G 0 7 D N G 9 6 D N G 8 6 T N A 7 6 D N G 6 6 D N G 4 7 I V D _ T N A

D V S R LISA-U2 Top View GND 65 GND 64 VCC 63 VCC 62 VCC 61 GND 60 SPI_MRDY / GPIO14 SPI_SRDY / GPIO13 59 58 SPI_MISO / GPIO12 57 SPI_MOSI / GPIO11 56 SPI_SCLK / GPIO10 55 GPIO9 / I2S1_WA 54 GPIO8 / I2S1_CLK 53 RSVD / CODEC_CLK 52 GPIO5 51 VSIM 50 SIM_RST 49 SIM_IO 48 SIM_CLK 47 SDA 46 SCL 45 RSVD / I2S_RXD 44 RSVD / I2S_CLK 43 RSVD / I2S_TXD 42 RSVD / I2S_WA 41 GPIO7 / I2S1_TXD 40 GPIO6 / I2S1_RXD 39 Pin 2838 = GND 8 2 9 2 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 LISA-U2 series - System Integration Manual LISA-U1 series LISA-U2 series 10 RI UART ring indicator output RI UART ring indicator output Circuit 125 (RI) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

11 DCD UART data carrier detect output DCD UART data carrier detect output Circuit 109 (DCD) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

12 DTR UART data terminal ready input DTR UART data terminal ready input Circuit 108/2 (DTR) in ITU-T V. 24, 1.8 V typ. LISA-U1 series:

Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 2 mA Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 2 mA Internal active pull-up = -110 A LISA-U2 series:

Internal active pull-up = -125 A Internal active pull-up = -60 A LISA-U2 series:

Internal active pull-up = -240 A Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 6 mA Internal active pull-up = -60 A LISA-U2 series:

Internal active pull-up = -240 A Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 6 mA 13 RTS UART ready to send input RTS UART ready to send input Circuit 105 (RTS) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

14 CTS UART clear to send output CTS UART clear to send output Circuit 106 (CTS) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

15 TXD UART transmitted data input TXD UART transmitted data input Circuit 103 (TxD) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

16 RXD UART received data output RXD UART received data output Circuit 104 (RxD) in ITU-T V.24, 1.8 V typ. LISA-U1 series:

17 18 GND Ground GND Ground VUSB_DET USB detect input VUSB_DET USB detect input No difference UBX-13001118 - R25 Appendix Page 170 of 182 LISA-U1 series LISA-U2 series 19 PWR_ON Power-on input PWR_ON Power-on input LISA-U2 series - System Integration Manual PWR_ON switch-on low pulse time difference:

LISA-U1 series:

L-level pulse time = 5 ms min L-level pulse time = 50 s min / 80 s PWR_ON switch-off low pulse time LISA-U2 series:

max difference:

LISA-U1 series:

LISA-U2 series:

Switch-off by PWR_ON not supported L-level pulse time = 1 s min PWR_ON operating voltage difference:

LISA-U1 series:

L-level input = -0.30 V min / 0.65 V max H-level input = 2.00 V min / 4.20 V max External pull-up (e.g. to V_BCKP) required LISA-U2 series:

L-level input = -0.30 V min / 0.65 V max H-level input = 1.50 V min / 4.40 V max External pull-up (e.g. to V_BCKP) required Configurable GPIO, 1.8 V typ. LISA-U1 series:

Output driver strength = 1 mA LISA-U2 series:

Output driver strength = 6 mA Functions on all LISA-U series:

Pad disabled (default) Input / Output Network Status Indication GNSS Supply Enable GSM Tx Burst Indication Function on LISA-U2 series:

Module Status Indication Configurable GPIO, 1.8 V typ. LISA-U1 series:

Output driver strength = 1 mA LISA-U2 series:

Output driver strength = 1 mA Functions on all LISA-U series:

Pad disabled Input / Output Network Status Indication GNSS Supply Enable (default) 20 GPIO1 GPIO GPIO1 GPIO 21 GPIO2 GPIO GPIO2 GPIO UBX-13001118 - R25 Appendix Page 171 of 182 LISA-U1 series LISA-U2 series 22 RESET_N External reset input RESET_N External reset input LISA-U2 series - System Integration Manual RESET_N hardware reset or switch-on low pulse time:

LISA-U1 series:

L-level pulse time = 50 ms min LISA-U2 series:

L-level pulse time = 50 ms min RESET_N operating voltage difference:

LISA-U1 series:

L-level input = -0.30 V min / 0.65 V max H-level input = 1.69 V min / 2.48 V max Internal 10k pull-up to V_BCKP (2.3 V typ.) LISA-U2 series:

L-level input = -0.30 V min / 0.51 V max H-level input = 1.32 V min / 2.01 V max Internal 10 k pull-up to V_BCKP (1.8 V typ.) Configurable GPIO, 1.8 V typ. LISA-U1 series:

Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 6 mA Functions on all LISA-U series:

Pad disabled Input / Output Network Status Indication GNSS Supply Enable GNSS Data Ready (default) Configurable GPIO, 1.8 V typ. LISA-U1 series:

Output driver strength = 4 mA LISA-U2 series:

Output driver strength = 6 mA Functions on all LISA-U series:

Pad disabled Input / Output Network Status Indication GNSS Supply Enable GNSS RTC Sharing (default) 23 GPIO3 GPIO GPIO3 GPIO 24 GPIO4 GPIO GPIO4 GPIO GND Ground GND Ground USB Data Line D-

input/output USB Data Line D+

input/output USB_D-

USB_D+

USB Data Line D-

input/output USB Data Line D+

input/output No difference No difference 28...38 GND Ground GND Ground 25 26 USB_D-

27 USB_D+

39 MIC_N I2S1_RXD /

GPIO6 LISA-U2 series, 2nd I2S Rx data input /

GPIO LISA-U120, LISA-U130:

Differential analog audio input (neg.) LISA-U120, LISA-U130:

Differential analog audio input (neg.) LISA-U100, LISA-U110:

RESERVED pin LISA-U2 series:

typ. I2S1_RXD and configurable GPIO, 1.8 V Output driver strength = 1 mA Internal active pull-down = 150 A Functions:

I2S1_RXD (default) Pad disabled Input / Output UBX-13001118 - R25 Appendix Page 172 of 182 40 MIC_P LISA-U2 series - System Integration Manual LISA-U1 series LISA-U2 series I2S1_TXD /

GPIO7 LISA-U2 series:

2nd I2S Tx data output /

GPIO LISA-U120, LISA-U130:

Differential analog audio input (pos.) LISA-U120, LISA-U130:

Differential analog audio input (pos.) LISA-U100, LISA-U110:

RESERVED pin LISA-U120, LISA-U130:

I2S word alignment LISA-U100, LISA-U110:

RESERVED pin LISA-U120, LISA-U130:

I2S Tx data output LISA-U100, LISA-U110:

RESERVED pin LISA-U120, LISA-U130:

I2S clock LISA-U100, LISA-U110:

RESERVED pin LISA-U120, LISA-U130:

I2S Rx data input LISA-U100, LISA-U110:

RESERVED pin 41 I2S_WA I2S_WA LISA-U2 series:

1st I2S word alignment input/output I2S_WA, 1.8 V typ. LISA-U120, LISA-U130:

42 I2S_TXD I2S_TXD LISA-U2 series:

1st I2S Tx data output I2S_TXD, 1.8 V typ. LISA-U120, LISA-U130:

43 I2S_CLK I2S_CLK LISA-U2 series:

1st I2S clock input/output 44 I2S_RXD I2S_RXD LISA-U2 series:

1st I2S Rx data input I2S_RXD, 1.8 V typ. LISA-U120, LISA-U130:

45 SCL I2C bus clock line output SCL I2C bus clock line output LISA-U1 series:

I2S1_TXD and configurable GPIO, 1.8 V Output driver strength = 1 mA LISA-U2 series:

typ. Functions:

I2S1_TXD (default) Pad disabled Input / Output Output driver strength = 2.5 mA Internal active pull-down = 100 A LISA-U2 series:

Output driver strength = 2 mA Internal active pull-down = 200 A Output driver strength = 2.5 mA LISA-U2 series:

Output driver strength = 2 mA I2S_CLK, 1.8 V typ. LISA-U120, LISA-U130:

Output driver strength = 2.5 mA Internal active pull-down = 100 A LISA-U2 series:

Output driver strength = 2 mA Internal active pull-down = 200 A Output driver strength = 2.5 mA Internal active pull-down = 100 A LISA-U2 series:

Output driver strength = 2 mA Internal active pull-down = 200 A I2C SCL for GNSS, 1.8 V typ. Fixed open drain External pull-up (e.g. to V_INT) required LISA-U2 series:

1.8 V typ. I2C SCL for GNSS and other I2C devices, Fixed open drain External pull-up (e.g. to V_INT) required I2C SDA for GNSS, 1.8 V typ. Fixed open drain External pull-up (e.g. to V_INT) required LISA-U2 series:

1.8 V typ I2C SDA for GNSS and other I2C devices, Fixed open drain External pull-up (e.g. to V_INT) required 46 SDA I2C bus data line input/output SDA I2C bus data line input/output LISA-U1 series:

UBX-13001118 - R25 Appendix Page 173 of 182 LISA-U2 series - System Integration Manual LISA-U1 series LISA-U2 series 47 SIM_CLK SIM clock output SIM_CLK SIM clock output 48 SIM_IO SIM data input/output SIM_IO SIM data input/output No difference:

49 SIM_RST SIM reset output SIM_RST SIM reset output 50 VSIM SIM supply output VSIM SIM supply output 51 GPIO5 GPIO GPIO5 GPIO No difference:

3.25 MHz clock frequency for SIM card Internal 4.7 k pull-up resistor to VSIM. No difference:

Reset output for SIM card No difference:

VSIM output = 1.80 V typ. or 2.90 V typ. Configurable GPIO, 1.8 V typ. LISA-U1 series:

Output driver strength = 2.5 mA LISA-U2 series:

Output driver strength = 6 mA Functions on all LISA-U series:

Pad disabled Input / Output SIM card detection (default) Network Status Indication GNSS Supply Enable Functions on LISA-U2 series only:

Module Operating Mode Indication SIM card hot insertion/removal (+UDCONF) LISA-U2 series:

Digital clock output for external audio codec Output driver strength = 4 mA LISA-U120, LISA-U130:

Differential analog audio output (pos.) LISA-U2 series:

typ. I2S1_CLK and configurable GPIO, 1.8 V Output driver strength = 1 mA Internal active pull-down = 150 A Functions:

I2S1_CLK (default) Pad disabled Input / Output LISA-U120, LISA-U130:

Differential analog audio output (neg.) LISA-U2 series:

I2S1_WA and configurable GPIO, 1.8 V typ. Output driver strength = 1 mA Internal active pull-down = 150 A Functions:

I2S1_WA (default) Pad disabled Input / Output 52 RSVD RESERVED pin 53 SPK_P CODEC_CL K LISA-U2 series:

Clock output I2S1_CLK /

GPIO8 LISA-U2 series:

2nd I2S clock input/output /

GPIO 54 SPK_N I2S1_WA /

GPIO9 LISA-U2 series:

2nd I2S word alignment input/output /

GPIO LISA-U120, LISA-U130:

Differential analog audio output (pos.) LISA-U100, LISA-U110:

RESERVED pin LISA-U120, LISA-U130:

Differential analog audio output (neg.) LISA-U100, LISA-U110:

RESERVED pin UBX-13001118 - R25 Appendix Page 174 of 182 LISA-U1 series LISA-U2 series 55 SPI_SCLK SPI Serial Clock Input SPI_SCLK /

GPIO10 SPI Serial Clock Input /

GPIO LISA-U1 series:

LISA-U2 series - System Integration Manual 56 SPI_MOSI SPI Data Line Input SPI_MOSI /

GPIO11 SPI Data Line Input /

GPIO 57 SPI_MISO SPI Data Line Output SPI_MISO /

GPIO12 SPI Data Line Output /

GPIO 58 SPI_SRDY SPI Slave Ready Output SPI_SRDY /

GPIO13 SPI Slave Ready Output /

GPIO LISA-U1 series:

SPI_SRDY, 1.8 V typ Output driver strength = 4 mA SPI_CLK, 1.8 V typ Internal active pull-down = 100 A LISA-U2 series:

SPI_CLK and configurable GPIO, 1.8 V typ. Internal active pull-down = 200 A Output driver strength = 6 mA Functions:

SPI_CLK (default) Pad disabled Input / Output LISA-U1 series:

SPI_MOSI, 1.8 V typ Internal active pull-up = -110 A LISA-U2 series:

typ. SPI_MOSI and configurable GPIO, 1.8 V Internal active pull-up = -240 A Output driver strength = 6 mA Functions:

SPI_MOSI (default) Pad disabled Input / Output LISA-U1 series:

SPI_MISO, 1.8 V typ Output driver strength = 2.5 mA LISA-U2 series:

typ. SPI_MISO and configurable GPIO, 1.8 V Output driver strength = 6 mA Functions:

SPI_MISO (default) Pad disabled Input / Output LISA-U2 series:

typ. SPI_SRDY and configurable GPIO, 1.8 V Output driver strength = 6 mA Functions:

SPI_SRDY (default) Pad disabled Input / Output Module Status Indication UBX-13001118 - R25 Appendix Page 175 of 182 LISA-U1 series LISA-U2 series 59 SPI_MRDY SPI Master Ready LISA-U1 series:

Input SPI_MRDY

GPIO14 SPI Master Ready Input /

GPIO LISA-U2 series - System Integration Manual SPI_MRDY, 1.8 V typ Internal active pull-down = 55 A LISA-U2 series:

typ. SPI_MRDY and configurable GPIO, 1.8 V Internal active pull-down = 200 A Output driver strength = 6 mA Functions:

SPI_MRDY (default) Pad disabled Input / Output Module Operating Mode Indication VCC operating voltage difference:

LISA-U1 series:

VCC normal range = 3.4 V min / 4.2 V max VCC extended range = 3.1 V min / 4.2 V max LISA-U2 series:

max VCC normal range = 3.3 V min / 4.4 V max VCC extended range = 3.1 V min / 4.5 V Band II (1900), Band V (850) LISA-U110, LISA-U130, LISA-U270:

Band I (2100), Band VIII (900) LISA-U200-00S:

Band I (2100), Band II (1900), Band V (850), Band VI (800) All LISA-U2 series except LISA-U200-00S:

Band I (2100), Band II (1900), Band IV

(1700), Band V (850), Band VI (800), Band VIII (900) 60 GND Ground GND Ground 6163 VCC Module supply input VCC Module supply input 6467 GND Ground Ground 68 ANT RF antenna GND ANT RF input/output for main Tx/Rx antenna 3G band support difference:

LISA-U100, LISA-U120, LISA-U260:

6973 GND Ground Ground 74 RSVD RESERVED pin GND RSVD ANT_DIV 75 76 GND GND Ground Ground GND GND Ground Ground Table 61: Pinout comparison LISA-U1 series vs. LISA-U2 series All except LISA-U230:

RESERVED pin LISA-U1 series and all LISA-U2 series except LISA-U230:

RESERVED pin Leave unconnected LISA-U230:

RF input for Rx diversity antenna LISA-U230:

RF antenna input for Rx diversity 50 nominal impedance UBX-13001118 - R25 Appendix Page 176 of 182 LISA-U2 series - System Integration Manual A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series The additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to the GND opening on module bottom layer, as described in Figure 79 and Figure 80. Figure 79: Signals keep-out area on the top layer of the application board, below LISA-U1 series modules Figure 80: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules UBX-13001118 - R25 Appendix Page 177 of 182 11.85 mm 5.3 mm 5.25 mm PIN 1 1.4 mm 1.0 mm Exposed GND on LISA-U1 module bottom layer Signals keep-out area on application board LISA-U1 bottom side

(through module view) m m 2 3 3

. 22.4 mm 5.25 mm 5.3 mm 5.3 mm 5.25 mm 1.3 mm PIN 1 1.4 mm 1.0 mm Exposed GND on LISA-U2 module bottom layer Signals keep-out areas on application board LISA-U2 bottom side

(through module view) m m 2 3 3

. 22.4 mm LISA-U2 series - System Integration Manual B Glossary Abbreviation Definition AT Command Interpreter Software Subsystem, or attention ADC AP AT CBCH CS CSD CTS DC DCD DCE DCS DDC DSP DSR DTE DTM DTR EBU FDD FEM FOAT FTP FTPS GND GNSS GPIO GPRS GPS GSM HF EDGE E-GPRS HSDPA HTTP HTTPS HW I/Q I2C I2S IP IPC LNA MCS NOM PA Analog to Digital Converter Application Processor Cell Broadcast Channel Coding Scheme Circuit Switched Data Clear To Send Direct Current Data Carrier Detect Digital Cellular System Display Data Channel Digital Signal Processing Data Set Ready Data Terminal Equipment Dual Transfer Mode Data Terminal Ready External Bus Interface Unit Data Communication Equipment Enhanced GPRS Frequency Division Duplex Front End Module Firmware Over AT commands File Transfer Protocol FTP Secure Ground Enhanced Data rates for GSM Evolution Global Navigation Satellite System General Purpose Input Output General Packet Radio Service Global Positioning System Global System for Mobile Communication Hands-free High Speed Downlink Packet Access HyperText Transfer Protocol Hypertext Transfer Protocol over Secure Socket Layer Hardware In phase and Quadrature Inter-Integrated Circuit Inter IC Sound Internet Protocol Inter Processor Communication Low Noise Amplifier Modulation Coding Scheme Network Operating Mode Power Amplifier UBX-13001118 - R25 Appendix Page 178 of 182 LISA-U2 series - System Integration Manual Abbreviation Definition PBCCH Packet Broadcast Control Channel Pulse Code Modulation Personal Communications Service Pulse Frequency Modulation Power Management Unit Radio Frequency Ring Indicator Real Time Clock Request To Send RX Data Surface Acoustic Wave Subscriber Identification Module Short Message Service Simple Mail Transfer Protocol Serial Peripheral Interface Static RAM Transmission Control Protocol Time Division Multiple Access TX Data PCM PCS PFM PMU RF RI RTC RTS RXD SAW SIM SMS SMTP SPI SRAM TCP TDMA TXD UART UDP UMTS USB UTRA Universal Asynchronous Receiver-Transmitter User Datagram Protocol Universal Mobile Telecommunications System Universal Serial Bus UMTS Terrestrial Radio Access VC-TCXO Voltage Controlled - Temperature Compensated Crystal Oscillator WCDMA Wideband CODE Division Multiple Access Table 62: Explanation of the abbreviations and terms used UBX-13001118 - R25 Appendix Page 179 of 182 LISA-U2 series - System Integration Manual Related documents

[1]

[2]

[3]

u-blox LISA-U2 series Data Sheet, document UBX-13001734 u-blox AT Commands Manual, document UBX-13002752 ITU-T Recommendation V.24, 02-2000. List of definitions for interchange circuits between data terminal equipment (DTE) and data circuit-terminating equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en

[4] 3GPP TS 27.007 - AT command set for User Equipment (UE)

[5] 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE

- DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS)

[6] 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol

[7] USB Revision 2.0 specification, http://www.usb.org/developers/docs/usb20_docs/

[8]

I2C-Bus specification and user manual - NXP Semiconductors, http://www.nxp.com/documents/user_manual/UM10204.pdf

[9] 3GPP TS 51.010-2 - Technical Specification Group GSM/EDGE Radio Access Network; Mobile Station (MS) conformance specification; Part 2: Protocol Implementation Conformance Statement (PICS)

[10] 3GPP TS 34.121-2 - Technical Specification Group Radio Access Network; User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 2: Implementation Conformance Statement (ICS)

[11] CENELEC EN 61000-4-2: "Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test".

[12] ETSI EN 301 489-1: Electromagnetic compatibility and Radio spectrum Matters (ERM);

Electromagnetic Compatibility (EMC) standard for radio equipment and services; Part 1:

Common technical requirements

[13] ETSI EN 301 489-52: "Electromagnetic Compatibility (EMC) standard for radio equipment and services; Part 52: Specific conditions for Cellular Communication Mobile and portable (UE) radio and ancillary equipment"

[14] u-blox Multiplexer Implementation Application Note, document UBX-13001887

[15] u-blox GNSS Implementation Application Note, document UBX-13001849

[16] u-blox Firmware Update Application Note, document UBX-13001845

[17] u-blox SPI Interface Application Note, document UBX-13001919

[18] 3GPP TS 23.060 - Technical Specification Group Services and System Aspects; General Packet Radio Service (GPRS); Service description

[19] u-blox End user test Application Note, document WLS-CS-12002

[20] u-blox Package Information Guide, document GPS-X-11004

[21] SIM Access Profile Interoperability Specification, Revision V11r00, http://www.bluetooth.org

[22] u-blox LISA-U1 / LISA-U2 Audio Application Note, Docu No UBX-13001835

[23] 3GPP TS 26.267 V10.0.0 eCall Data Transfer; In-band modem solution; General description

[24] BS EN 16062: Intelligent transport systems eSafety eCall high level application requirements

[25] ETSI TS 122 101 Service aspects; Service principles (3GPP TS 22.101 v.8.7.0 Rel. 8)

[26] 3GPP TS 44.031 Location Services (LCS); Mobile Station (MS) - Serving Mobile Location Centre

(SMLC) Radio Resource LCS Protocol (RRLP)

[27] 3GPP TS 25.331 Radio Resource Control (RRC); Protocol specification

[28] u-blox LISA-U1 series Data Sheet, document UBX-13002048 For regular updates to u-blox documentation and to receive product change notifications, register on our homepage (www.u-blox.com). UBX-13001118 - R25 Related documents Page 180 of 182 LISA-U2 series - System Integration Manual

1 2 3 A A2 A3 A4 A5 A6 A7 A8 B B1 R16 R17 R18 R19 R20 R21 R22 Revision history Revision Date Name Comments 21-Oct-2010 sses Initial Release A1 22-Nov-2011 sses 11-Jan-2011 sses Thickness information added. GPIO description improved 26-Apr-2011 lpah Update to Advance Information status 07-Jul-2011 lpah Update to Preliminary status 26-Oct-2011 sses Changed status to Objective Specification. Initial release for LISA-U series: From LISA-U1x0-00S system integration manual, added the description and the integration of LISA-U1x0-01S, LISA-U200-00S, LISA-U2x0-01S Update to Advance Information status. Updated module behavior during power-off sequence. Added LISA-U200-00S ESD application circuit for antenna port. Added application circuit for the module status indication function. 02-Feb-2012 sses Update to Preliminary status. Updated Federal Communications Commission notice. Updated LISA-U2 features in module power-off and GPIO sections 25-May-2012 gcom Updated values for antenna gain 20-Jun-2012 sses Update to Advance Information status. Updated PWR_ON behavior. Updated UART and power saving behavior. Added 3V / 1.8V SPI application circuit. Updated GPS RTC sharing application circuit. Added remote SIM access profile description 24-Aug-2012 sses Update to Preliminary status. Updated FCC notice. Updated recommended VCC bypass capacitors. Added LISA-U110-60S and LISA-U130-60S 04-Oct-2012 lpah / sses Update to Advance Information status. Added LISA-U260 and LISA-U270 26-Nov-2012 lpah / sses Update to Preliminary status. Removed document applicability to LISA-U1x0-00S 29-Mar-2013 sses 15-Jul-2013 sses versions. Added document applicability to LISA-U110-50S versions Updated additional recommendations for VCC application circuits

(Last revision with old doc number, 3G.G2-HW-10002) Update status to Advance Information First release for LISA-U200-02S, LISA-U200-61S, LISA-U200-62S, LISA-U260-02S, LISA-U270-02S, LISA-U270-62S 21-Aug-2013 lpah Update status to Preliminary 20-Mar-2014 lpah / sses Extended document applicability to LISA-U200-52S and LISA-U200-82S (LISA-

U200 FOTA). Updated recommended I2C voltage translator and clarified I2C application circuits remarks. Clarified and improved power-on, power-off and reset timings and procedures descriptions 26-Jun-2015 sfal Extended document applicability to LISA-U200-03S and LISA-U201-03S 10-Aug-2015 sfal Early Production Information status. Removed LISA-U1 series modules and LISA-

U200-00S. Extended applicability to LISA-U200-83S and LISA-U270-68S 04-Nov-2015 sses Updated FCC and IC notices 21-Jan-2016 sfal Updated European Conformance CE mark notice, added LISA-U201 Anatel certification details, updated the list of supported USB drivers and extended applicability to LISA-U201-83S 12-May-2016 lpah Extended applicability to LISA-U201-03A and LISA-U270-63S 07-Oct-2016 lpah Updated status to Production Information Extended applicability to LISA-U200-62S-02 and removed LISA-U200-82S R23 17-Mar-2017 lpah

"Disclosure restriction" replaces "Document status" on page 2 and document footer Extended applicability to LISA-U201-03A-01 R24 10-Jan-2018 lpah / sses Updated approvals section Extended document applicability to new LISA-U2 type numbers R25 10-Apr-2019 lpah / sses Extended the document applicability to LISA-U200-01S-03, LISA-U200-03S-02, LISA-U200-52S-03, LISA-U200-62S-04, LISA-U230-01S-03, LISA-U270-63S-02. Minor other clarifications, corrections and description improvements. UBX-13001118 - R25 Revision history Page 181 of 182 LISA-U2 series - System Integration Manual Contact For complete contact information, visit us at www.u-blox.com. u-blox Offices North, Central and South America Headquarters Asia, Australia, Pacific Europe, Middle East, Africa u-blox AG Phone:+41 44 722 74 44 E-mail:info@u-blox.com Support:support@u-blox.com u-blox America, Inc. Phone:+1 703 483 3180 E-mail:info_us@u-blox.com Regional Office West Coast:

Phone:+1 408 573 3640 E-mail:info_us@u-blox.com Technical Support:

Phone:+1 703 483 3185 E-mail:support@u-blox.com u-blox Singapore Pte. Ltd. Phone: +65 6734 3811 E-mail: info_ap@u-blox.com Support:support_ap@u-blox.com Regional Office Australia:

Phone: +61 2 8448 2016 E-mail: info_anz@u-blox.com Support:support_ap@u-blox.com Regional Office China (Beijing):

Phone:+86 10 68 133 545 E-mail:info_cn@u-blox.com Support:support_cn@u-blox.com Regional Office China (Chongqing):

Phone:+86 23 6815 1588 E-mail:info_cn@u-blox.com Support:support_cn@u-blox.com Regional Office China (Shanghai):

Phone:+86 21 6090 4832 E-mail:info_cn@u-blox.com Support:support_cn@u-blox.com Regional Office China (Shenzhen):

Phone:+86 755 8627 1083 E-mail:info_cn@u-blox.com Support:support_cn@u-blox.com Regional Office India:

Phone:+91 80 405 092 00 E-mail:info_in@u-blox.com Support:support_in@u-blox.com Regional Office Japan (Osaka):

Phone:+81 6 6941 3660 E-mail:info_jp@u-blox.com Support:support_jp@u-blox.com Regional Office Japan (Tokyo):

Phone:+81 3 5775 3850 E-mail:info_jp@u-blox.com Support:support_jp@u-blox.com Regional Office Korea:

Phone:+82 2 542 0861 E-mail:info_kr@u-blox.com Support:support_kr@u-blox.com Regional Office Taiwan:

Phone:+886 2 2657 1090 E-mail:info_tw@u-blox.com Support:support_tw@u-blox.com UBX-13001118 - R25 Contact Page 182 of 182

 

 

TTU-2830 Hardware & Installation Guide TTU-2830 Hardware and Installation Guide 1 Introduction Welcome to the TTU-2830Hardware and Installation Guide. This manual is intended to give you information on the basic setup and installation of the CalAmpTTU-2830product(s) including hardware descriptions, environmental specifications, wireless network overviews and device installation. 1.1 About This Manual The TTU-2830is one of the most flexible economy mobile tracking hardware products available. In order to accurately describe the functionality of these units we have broken this manual into the following sections:

Hardware Overview Describes the physical characteristics and interfaces of the TTU-2830. Installation and Verification Provides guidance for the installation of the TTU-2830in a vehicle and instructions on how to verify the installation is performing adequately. 1.2 About the Reader In order to limit the size and scope of this manual, the following assumptions have been made about the reader. You are familiar with GPS concepts and terminology You have some experience with installing equipment in vehicles 1.3 About the CalAmp Location Messaging Unit-TTU-2830 The CalAmp Location and Messaging Unit-TTU-2830(TTU-2830) is a mobile device that resides in private, commercial or government vehicles. The TTU-2830is a single box enclosure incorporating a processor, a GPS receiver, a wireless data modem, and a vehicle-rated power supply. The TTU-2830also supports inputs and outputs to monitor and react to the vehicular environment and/or driver actions. 2 System Overview 2.1 Overview The entire purpose behind a fleet management system is to be able to remotely contact a vehicle, determine its location or status, and do something meaningful with that information. This could include displaying the vehicle location on a map, performing an address look-up, providing real-time driving directions, updating the vehicles ETA, monitoring vehicle and driver status or dispatching the vehicle to its next pick up. These functions, of course, are completely dependent on the capabilities of the vehicle management application. The role of the CalAmpTTU-2830is to deliver the location information when and where it is needed. A typical fleet management system based on a CalAmp device includes the following components:

A wireless data network An TTU-2830 Backend mapping and reporting software from Actsoft which typically includes mapping and fleet reporting functions 2.2 Component Descriptions 2.2.1 Wireless Data Network The Wireless Data Network provides the information bridge between the Actsoft servers and the TTU-2830. Wireless data networks can take a variety of forms, such as cellular networks, satellite systems or local area networks. 2.2.3 Backend Software Backend software is provided by Actsoft. Regardless of its purpose, one of its primary functions is to parse and present data obtained from the TTU-2820. This allows the application to do any of the following:

Display location database on reports received from the TTU-2830in a variety of formats Present historic information received from the TTU-2830, typically in a report/chart style format Request location updates from one or more TTU-2830s 3 Hardware Overview 3.1 Location Messaging Unit-TTU-2830 Anytime the sub assembly is shipped and it is not fully packaged in its final housing it must be sealed in an ESD safe bag. Electrical Over-Stress (EOS) The GPS receiver can be damaged if exposed to an RF level that exceeds its maximum input rating. Such exposure can happen if a nearby source transmits an RF signal at sufficiently high level to cause damage. Storage and Shipping One potential source of EOS is proximity of one TTU-2830GPS Antenna to another TTU-2830GSM Antenna. Should one of the units be in a transmit mode the potential exists for the other unit to become damaged. Therefore any TTU-2830GPS Antenna should be kept at least four inches apart from any active TTU-2830GSM Antenna or any other active high power RF transmitter with power greater than 1 Watt. 3.1.2 Battery Back-up devices Please properly dispose of the battery in any of the CalAmp products that utilize one, do not just throw used batteries, replaced batteries, or units containing a back-up battery into the trash. Consult your local waste management facility for proper disposal instructions. 3.1.3 Environmental Specifications The TTU-2830is designed to operate in environments typically encountered by fleet vehicles, including wide temperature extremes, voltage transients, and potential interference from other vehicle equipment. To ensure proper operation in such an environment, the TTU-2830was subjected to standard tests defined by the Society of Automotive Engineers (SAE). The specific tests included temperature, shock, vibration, and EMI/EMC. These tests were performed by independent labs and documented in a detailed test report. In accordance with Appendix A of SAE J1113 Part 1, the Unit is considered a Functional Status Class B, Performance Region II system that requires Threat Level 3 Testing. The following shows the environmental conditions the LMU is designed to operate in and the relevant SAE tests that were performed. No formal altitude tests were conducted. Size 4.3" long x 3.2" wide x 1.6" high 110 mm long x 80m wide x 40mm high Weight 9.6 oz (272 g) Operating Temperature

-30 C to 70 C Storage Temperature

-40 C to 85 C 20 C to 50 C (Internal Battery Power) Humidity 0% to 95% relative humidity, non-condensing Shock and Vibration SAE Test: SAE J1455 Compliant Mil Standard 202G and 810F Compliant Ground vehicle environment with associated shock and vibration Electromagnetic Compatibility (EMC/EMI) SAE Test: SAE J1113 Parts 2, 12, 21 and 41 Compliant FCC Part 15B Compliant Industry Canada Compliant EMC compliant for a ground vehicle environment Operating Voltage Range 9 32VDC Back-up Battery 5.2Ah mAh (up to 6 months at 1 message per day w/ deep sleep enabled) 4 Hour Charge Time Power Consumption Active Standby < 70mA at 12VDC Radio Active Sleep <<TBD> at 12VDC Deep Sleep < 2mA at 12VDC GPS 50 channel WAAS capable GPS Receiver 2.5m CEP (with SA off)

-162 dBm tracking sensitivity Communications (Comm) Data Support SMS, GPRS, CDMA 1xRTT or HSPA packet data GSM/GPRS Quad-Band 850/900/1800/1900 MHz GSM/GPRS Output Power Class 4 (2 Watts) 850/900 bands Class 1 (1 Watt) 1800/1900 bands CDMA Dual-Band 800/1900 MHz CDMA Output Power 800: +24dBm 1900: +24dBm HSPA/UMTS Dual-Band 900/2100 MHz (bands VIII, I) or 850/1900 MHz (bands V, II) 3GPP release 6 5.6 Mbps upload, 7.2 Mbps download GSM/GPRS Fallback 850/900/1800/1900 quad-band GPRS class 12, EDGE MCS1-MCS9 RoHS Compliant 3.2 Primary Connector The TTU-2830uses 8 22AWG leads for its power and I/O connections. These leads are mapped as follows:

Wire Signal Name Description Color Input or Output 1 2 3 4 5 6 7 8 GND Ground Black Ground VCC IN-0 IN-1 IN-2 Primary Power Input 0 Ignition Input 1 Digital Input Red White Blue Input 2 Digital Input Orange Input Input Input Input OUT-0 Ouput 0 Starter Disable Relay Driver Green Ouput OUT-1 Ouput 1 Digital Output Brown OUT-2 Ouput 2 Digital Output Yellow Ouput Ouput 9 10 SER_OUT Serial Output SER_IN Serial Input Green\Black Output Blue\Black Input TTU-2830Power and I/O leads 3.3 GPS Receiver The TTU-2830s GPS receiver has the following specifications:

50 channel GPS receiver Accuracy: 2.5 meter CEP (with SA off)

-162dBm Tracking Sensitivity 3.4 I/O Descriptions The TTU-2830provides the following I/O:

Digital Inputs Input 0: Ignition Sense (Always biased low) Input 1: Generic Digital Input (high or low bias per S-158) Input 2: Generic Digital Input (high or low bias per S-158) Input 3: Not Available Input 4: Not Available Input 5: Motion Sensor (low = no motion, high = motion) Input 6: Power Switch State (low = external power, high = internal battery) Input 7: Battery Voltage Critical Sensor ( low = VBatt ok, high = VBatt low. 3500mV threshold) Input 8: High Temperature Sensor (low = below Temp Threshold, high = above Temp threshold. Temp Threshold = 300) Analog to Digital Inputs A/D 0: External Power Supply Monitor A/D 1: Generic External Analog to Digital Input A/D 2: GPS Antenna Monitor A/D 3: uP Temperature A/D 4: uP Voltage A/D 5: Battery Voltage A/D 6: Temperature Sensor A/D 7: Vcc Sys Outputs:

Output 0: Standard Open Collector Relay Output Output 1: Standard Open Collector Relay Output Output 2: Standard Open Collector Relay Output Output 3: Not Available Output 4: Power Supply Switch (cleared = switch to external power, set = switch to internal power) Output 5: Enable/Disable Battery charging (cleared = enable battery charging, set

= disable battery charging) 3.5Motion Sensor Input The TTU-2830supports an internal motion sensor as one of its discreet inputs. In this case, the TTU detects motion and will determine if the device is moving for at least 30 consecutive seconds. If it is moving the device will track at a 5 minute interval for about 350 messages. 3.5.1 Power State Input The TTU-2830can detect if its using external power or if its using its internal back-up battering. If the TTU-2830is using external power, this input will be in the Low state. If they have switched to the internal battery, then the input will register in the High state. 3.5.2 Battery Voltage Critical Input The TTU-2830has a built in low battery threshold of 3500mV, which is tied to a discreet input. If the battery in the device reaches this limit a Low Battery event will be sent to Actsoft systems. 3.5.3 Ignition and Inputs The TTU-2830provides up to 3external inputs. The external inputs are protected from typical vehicle transients and can be directly connected to most vehicle level logical inputs from 4 volts up to the vehicle power input level (typically 12 VDC). Their input impedance is approximately 10k. One of these inputs is dedicated to sensing the vehicles ignition status to provide for flexible power management. The other two inputs may be used to sense vehicle inputs such as cooling unit operation, a hidden driver Panic switch, taxi on-duty/off-duty meter status or many others. The ignition input is pulled to ground through the 10k resistance, where the other inputs can either be normally High (i.e. pulled to +12v through a 10k resistor) or Low (i.e. pulled to ground through a 10k resistor). Input 1 is always biased low, while inputs 2-4 are biased high. The diagrams below show how to connect the inputs in both a high and low-biased configuration:

Sample Input Wiring 3.5.4 Status LEDs The TTU-2830is equipped with two Status LEDs, one for GPS and one for COMM

(wireless network status). The LEDs use the following blink patterns to indicate service:

LED #1 (Comm LED - Orange) Definitions Condition Modem Off Comm On - Searching Network Available LED 1 Off Slow Blinking Fast Blinking Registered but no Inbound Acknowledgement Alternates from Solid to Fast Blink every 1s Registered and Received Inbound Acknowledgement Solid LED #2 (GPS LED - Green) Definitions Condition LED 2 GPS Off Off GPS On Slow Blinking GPS Time Sync Fast Blinking GPS Fix Solid TTU-2830LED Positions 4 Installing the LMU The installation of the LMU and its antennas can have a major impact on the LMUs performance. It is recommended that installers be familiar with the installation of GPS and cellular devices and are comfortable in a vehicle environment. 4.1 Preparing for Installation Be sure you have received all the LMU components you need. This must include:

The LMU to be installed A power harness GPS Antenna (for external devices) Comm Antenna (for external devices) Optional Components:

Input and output cables 4.2 Plan The Installation Verify Power, Ground and Ignition. Be sure to check each source (power, ground and ignition) to ensure that the proper signaling exists. This is typically accomplished with a multi-meter. Before drilling any holes or running any wires, decide where each hardware component will be located (LMU, antennas, peripherals, etc.). Be sure that the cables to the LMU are not bent or constricted in any way. Also make sure that the LMU is kept free from direct exposure to the elements (sun, heat, rain, moisture etc...). Be advised that an installation that violates the environmental specifications of the LMU will void the warranty. The best way to ensure a trouble-free installation is to consider your options and make some decisions before you start. Take a look at the vehicle and determine how to best install the LMU for the following purposes:

Accurate data gathering and simulation of how customers actually use your solution Ongoing monitoring and maintenance of LMU equipment Accidental or intentional alteration of the equipment or cable connections The following sections cover some of the issues to consider when planning your LMU installation. 4.2.1 Size and Placement of LMU Unit The dimensions of the LMU should be taken into account, particularly when installing in a vehicle:

Whether you intend to place the LMU under a seat or into a cavity behind the vehicles interior molded trim, be sure the LMU will fit before drilling any holes or running cable Be certain that the cables running to the LMU will not be bent or constricted. Damage to the cables may impede the LMUs performance. Be certain that the installation point will not violate any of the LMUs environmental specification (temperature, moisture, etc) as improper installation of the LMU may void the warranty. Typical installations will place the LMU under the vehicle dash board, or in the trunk. Make sure you can get access to the unit afterwards as under some circumstances it may be necessary to add additional wiring or connections to the LMU. 4.2.2 Placement of Antennas Placement of Combination and Internal Antennas When dealing with combination antennas, it is more important to considered GPS performance over Comm performance. GPS signal strengths are much lower than those typically seen by cellular networks supported by the LMU. In order to maximize the performance the LMU should have a clear view of the sky as possible. When installing the GPS antenna in a vehicle, make sure that there are as few obstructions as possible close to the LMU that might block the view 360 to the horizon. As with stand-alone GPS antennas, nothing should not block the combination antenna beyond 5 above the horizon with the best location being near the center of the roof. For more covert installs, directly under the front or rear-windshields are also acceptable. Examples of Good (Green), OK(Yellow) and Poor(Red) combo antenna placements Examples OK(Yellow) and Poor(Red) internal antenna placements 4.2.3 Protection from Heat It is best not to place the LMU unit in an unusually warm location such as directly near heater vents, near hot engine components or in direct sunlight. The maximum temperature that can be tolerated by the LMU is described in the LMU Environmental Specifications section. 4.2.4 Visibility of Diagnostic LEDs Status LED lights on the front of the LMU unit can provide valuable information about the operation of the LMU. When feasible, attempt to install the LMU in such a way that these lights can be seen with reasonable ease. You may find it useful to be able to view the LEDs periodically to make sure that the LMU is operating properly. If at any time you should encounter a problem with the LMU, you may need to read the LEDs in order to troubleshoot the problem. If you cannot fix the LMU yourself, you will need to provide the LED information to CalAmp customer support. For information about how to interpret the LEDs, see the Status LED Behavior section. 4.2.5 Moisture and Weather Protection The LMU unit must be located where it will not be exposed to moisture or water. In a typical installation inside a vehicle this is not commonly thought to be a concern;

however, it might be best to avoid locating the LMU below a cars cup holders, or where rain might easily splash into the compartment when a door is opened. 4.2.6 Preventing Accidental or Unauthorized Modification If you anticipate that fleet drivers or others might interfere with the LMUs once they are installed, take steps to be sure that it is not easy to disconnect the antenna wiring, remove the LMU from its power source, etc. Two common methods are the use of Tamper Proof Sealant or creation of PEG Script to detect power loss or GPS antenna disconnections. 5.Installing the LMU in a Vehicle This section provides instructions for installing an LMU in a vehicle. Be sure to consider the design decisions described in the previous sections. When you are ready to begin installing the LMU, follow these steps:

5.1 Place the LMU unit in the vehicle. Typically, the LMU should be placed under the passenger seat or dashboard of the vehicle. LMUs with internal antennas should be placed to maximize their GPS performance. A typical location include under the dash close to the front wind-shield. Attach the LMU to the solid body of the vehicle, not to plastic panels. The LMU can be placed out of sight by removing interior trim and molding to expose available space, then replacing the trim once the LMU is in place. 5.2 Connect power, ignition, and ground. The power input (red wire) must be connected to a constant (un-switched) +12 VDC or

+24 VDC supply; preferably, connected directly to the vehicle battery terminal or as close to it as possible. This connection point should be fuse protected to not more than 5 Amps. The ignition input (white wire) must be connected to the vehicle ignition or another appropriate key operated line, such as ACCESSORY, ensuring that power to the ignition wire is available only when the vehicle ignition is on. The ground line (black wire) must be connected to chassis ground. Failure to connect these lines in the manner described may result in discharge of the vehicle battery. For best results, it is strongly recommended that the LMU connection be on its own circuit. Connect the power input directly to the vehicle battery if possible and protect the circuit with an inline fuse. If you must connect through the fuse box, use standard commercial wiring practices to create a permanent installation rather than using press-in fuse clips or other temporary measures. DO NOT connect the power cable to the LMU at this time. 5.3 Installation Verification In many cases it is desirable to verify that an installed TTU-2830is working properly. That is, installers should verify that the GPS and communications functions of the TTU-

2830are working properly before departing the installation site. In more robust cases, some key configuration settings such as the Inbound Address and URL should also be verified. 6 License Agreement FOR SOFTWARE, APPLICATION PROGRAMING INTERFACES (APIs) &

DOCUMENTATION IMPORTANT: DO NOT INSTALL OR USE THE SOFTWARE OR DOCUMENTATION UNTIL YOU HAVE READ AND AGREED TO THIS LICENSE AGREEMENT. This is a legal agreement between you, the Customer, and CalAmpDataCom Incorporated

(CalAmp). By installing and/or using the software or documentation, you are consenting to the terms of this License. If you do not agree to the terms of this non-

exclusive License Agreement, DO NOT INSTALL OR USE THE SOFTWARE, APIs OR DOCUMENTATION. For a full refund, return the unused media package and all accompanying materials within seven (7) days to CalAmp. Where there is no packaging or media, use of the software and/or documentation constitutes acceptance. Definitions: As used in this License Agreement, Software means CalAmps LM Direct

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Rights are reserved under copyright laws of the United States with respect to unpublished portions of the Software. 8 Regulatory Information Human Exposure Compliance Statement Pursuant to 47 CFR 24.52 of the FCC Rules and Regulations, personal communications services (PCS) equipment is subject to the radio frequency radiation exposure requirements specified in 1.1307(b), 2.1091 and 2.1093, as appropriate. CalAmpDataCom Inc. certifies that it has determined that the TTU-2830complies with the RF hazard requirements applicable to broadband PCS equipment operating under the authority of 47 CFR Part 24, Subpart E of the FCC Rules and Regulations. This determination is dependent upon installation, operation and use of the equipment in accordance with all instructions provided. The TTU-2830complies with RF specifications when used near at a distance of 10 mm from your body. Ensurethat the device accessories, such as a device case and deviceholster, are not composed of metal components. Keep thedevice away from your body to meet the distance requirement.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ox 948-00 Model: LISA-U200

'820100.0901.000 IMEI: 958875100010896 FCC ID:XPYLISAU200 IC: 8595A-LISAU200N ce efi%2te#05309-12-08459 in Austra

 

 

Certification Declaration Doc ID: UBX-19034813 Date: 07/08/2019 Request for ConfidentialitySubject: Confidentiality Request for: FCC ID: XPYLISAU200, 8595A-

LISAU200N, XPYLISAU201, 8595A-LISAU201 Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Permanent Permanent Permanent Permanent Permanent Exhibit Block Diagrams External Photos Internal Photos Operation Description/Theory of Operation Parts List & Placement/BOM Tune-Up Procedure Schematics Test Setup Photos Users Manual u-blox AG Zrcherstrasse 68 8800 Thalwil Switzerland Phone +41 44 722 74 44 Fax +41 44 722 74 47 info@u-blox.com MWSt Nr 424 417 Zrcher Kantonalbank BC-Nr. 700, S.W.I.F.T. ZKBK CH ZZ 80A 1100-0243.614 (CHF) IBAN CH96 0070 0110 0002 4361 4 1300-00293.032 (USD) IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 (JPY) IBAN CH62 0070 0130 0070 0182 7 u-blox AG, Zuercherstrasse 68, 8800 Thalwil, Switzerland has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to

"competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of 180 days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify ACB in the event information regarding the product or the product is made available to the public. ACB will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Author Giulio Comar Department:

cert Page: 1/2 Filename ACB-Form-FCC-IC-Application-Letters-Confidentiality-Letter.docx M87 Rev. 3 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Certification Declaration Doc. ID: UBX-19034813 Date: 07/08/2019 Giulio Comar Certification Manager Sincerely, By:

Title:

__________________________

(Signature) Company:

Telephone / Fax:

e-mail:

u-blox AG, Zuercherstrasse 68, 8800 Thalwil, Switzerland

+41 44 722 7462 / +41 44 722 2477 giulio.comar@u-blox.com Author Giulio Comar Department:

cert Page: 2/2 Filename ACB-Form-FCC-IC-Application-Letters-Confidentiality-Letter.docx M87 Rev. 3 Copyright 2011 u-blox Italia S.p.A. All rights reserved Confidential

 

 

Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 Delta Description LISA-U Edition 2013 Published by u-blox Italia S.p.A., Via Stazione di Prosecco, 15 Author Piero Emanuele Laudicina Department:

cert Page: 1/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 34010 Sgonico (Trieste) Italy u-blox Italia S.p.A.. All Rights Reserved. Table of Contents 1 Document Mission/Scope .......................................................................................................................... 3 1.1 Mission ...................................................................................................................................................... 3 1.2 Scope ........................................................................................................................................................ 3 2 List of Acronyms ........................................................................................................................................ 3 3 Affected Products ...................................................................................................................................... 4 4 System Configuration ................................................................................................................................ 4 5 Cross reference table: Product vs FCC and IC code ................................................................................. 4 6 Delta System Description .......................................................................................................................... 5 6.1 6.2 SW Modem changes ................................................................................................................................. 5 Hardware Modem change ......................................................................................................................... 5 LISA-U200-04 compare to LISA-U200-03 ....................................................................................... 5 6.2.1 LISA-U201-04 compare to LISA-U200 ............................................................................................. 6 6.2.2 6.2.3 SARA- ............................................................................................................................................ 7 7 Impact ......................................................................................................................................................... 7 8 References .................................................................................................................................................. 7 8.1 8.2 External ..................................................................................................................................................... 7 Internal ...................................................................................................................................................... 7 9 Document change report .......................................................................................................................... 7 10 Approval ..................................................................................................................................................... 7 Author Piero Emanuele Laudicina Department:

cert Page: 2/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 1 Document Mission/Scope 1.1 Mission Aim of this document is to describe the differences between system configurations in terms of HW and/or FW and provide analysis of their impact on the system behavior. 1.2 Scope The document is addressed to the project team and the people involved in the testing and certification of LISA-U family wireless modules. 2 List of Acronyms Abbreviation / Term Explanation / Definition FCC FW GCF HW IC IMEI PTCRB SVN UMTS TCB Federal Communications Commission Firmware Global Certification Forum Hardware Industry Canada International Mobile Equipment Identity PCS Type Certification Review Board Software Version Number Universal Mobile Telecommunications System Telecommunication Certification Body Author Piero Emanuele Laudicina Department:

cert Page: 3/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description 3 Affected Products Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 Product:

2G Bands

[MHz]

3G Bands

[MHz]

Voice / Data LISA-U200-04 LISA-U201-04 850/900/1800/1900 850/900/1800/1900 800/850/900/1700/1900/2100 800/850/900/1900/2100

/

/

4 System Configuration Current configuration:

Product:

LISA-U200-03 LISA-U201 Baseline FW:

23.41 23.41 New configuration:

Product:

LISA-U200-04 LISA-U201-04 Baseline FW:

23.41 23.41 Baseline HW 146AB2 214001 Baseline HW 146DB0 214C00 SVN 07 07 SVN 07 07 5 Cross reference table: Product vs FCC and IC code Product LISA-U200-04 LISAU200-03 LISA-U201 LISA-U201-04 FCC ID XPYLISAU200 XPYLISAU200 XPYLISAU201 XPYLISAU201 IC code 8595A-LISAU200N 8595A-LISAU200N 8595A-LISAU201 8595A-LISAU201 HVIN LISA-U200-01 LISA-U200-01 LISA-U201 LISA-U201 Author Piero Emanuele Laudicina Department:

cert Page: 4/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 6 Delta System Description 6.1 SW Modem changes No Same baseline SW 6.2 Hardware Modem change 6.2.1 LISA-U200-04 compare to LISA-U200-03 Same Form Factor Schematics and PCB layout - changes component and there is no change to the radio parameters o PA new version of the same component, pin to pin compatible and and electrically equivalent o BB RTC 32 KHz Crystal replaced with a pin to pin equivalent from a different o Change of the PCB layout and some passives replaced with equivalent one of manufacturer (for economy of scale) different size in order to fit the new Winbond NAND memory combo New System memory Vs old System memory It is an electrically compatible, external dimension differs by 1mm Pin to Pin compatible:No RAM Specification are still by JEDEC Memory speed o RAM: As per the relative datasheets, the new memory part

(Winbond) allows a maximum clock frequency of 200MHz while the Cypress part is specified for a maximum clock frequency of 166MHz. o Flash: Different technologies between new part (Winbond) and old part (Cypress). The new memory part (Winbond) has a NAND flash while Cypress is based on a NOR flash. The NAND minimum write cycle time (tWC) and read cycle time (tRC) are both specified at 35ns. The NOR based flash (Cypress) specifies a minimum clock period of 9.26ns while the minimum write cycle time (tWC) is 60ns. o o RAM: The maximum LPDDR1 clock frequency in use is 172MHz. Max clock On the previous memory (Cypress), the DDR part in use had the same technology, LPDDR1. In this latter case, the maximum clock frequency used was 160MHz o Flash: The measured write and read cycle time for Winbond o The measured clock period and tWC for Cypress (NOR) are:

(NAND) are: tRC = 52ns; tWC=41ns tclk = 12.5ns; tWC = 330ns Power draw:

Author Piero Emanuele Laudicina Department:

cert Page: 5/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 o The power consumption of the module is expected to be the same as before the memory change, seeing that the memory impact on the overall current consumption is negligible at module level o Same antenna switch o Same RF filters o Same reference frequency o Same processor (BB) Same RF chip Modification of the housing:NA BOM:

o Yes except for the componets replaced 6.2.2 LISA-U201-04 compare to LISA-U200 Same Form Factor Schematics and PCB layout - changes o Change of the PCB layout and some passives replaced with equivalent one of different size in order to fit the new Winbond NAND memory combo New System memory Vs old System memory It is an electrically compatible, external dimension differs by 1mm Pin to Pin compatible:No RAM Specification are still by JEDEC Memory speed o RAM: As per the relative datasheets, the new memory part

(Winbond) allows a maximum clock frequency of 200MHz while the Cypress part is specified for a maximum clock frequency of 166MHz. o Flash: Different technologies between new part (Winbond) and old part (Cypress). The new memory part (Winbond) has a NAND flash while Cypress is based on a NOR flash. The NAND minimum write cycle time (tWC) and read cycle time (tRC) are both specified at 35ns. The NOR based flash (Cypress) specifies a minimum clock period of 9.26ns while the minimum write cycle time (tWC) is 60ns. o RAM: The maximum LPDDR1 clock frequency in use is 172MHz. o Max clock On the previous memory (Cypress), the DDR part in use had the same technology, LPDDR1. In this latter case, the maximum clock frequency used was 160MHz o Flash: The measured write and read cycle time for Winbond o The measured clock period and tWC for Cypress (NOR) are:

(NAND) are: tRC = 52ns; tWC=41ns tclk = 12.5ns; tWC = 330ns Power draw:

Author Piero Emanuele Laudicina Department:

cert Page: 6/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 o The power consumption of the module is expected to be the same as before the memory change, seeing that the memory impact on the overall current consumption is negligible at module level Same antenna switch Same RF filters Same reference frequency Same processor (BB) Same RF chip Modification of the housing:NA BOM:

o Yes except for the componets replaced SARA-

6.2.3 7 The following certification schemes will apply Impact Scope FCC / IC PTCRB Impact C2PC. ECO 8 References 8.1 External None 8.2 None 9 Document change report Internal Revision Change Reference Date CR NA NA NA 1.0 2.0 3.0 30/05/2019 07/08/2019 05/09/2019 10 Approval Revision 1.0 Approver(s) Giulio Comar Record of changes made to previous released version Section Comment ALL ALL ALL Document Created Document Created Document Created Date Source/signature 30/05/2019 Document stored on server Author Piero Emanuele Laudicina Department:

cert Page: 7/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential Delta Description Doc. ID: UBX-19025837 Rev.: 3.0 Date: 05/09/2019 Giulio Comar Giulio Comar 07/08/2019 Document stored on server 05/09/2019 Document stored on server 2.0 3.0 Author Piero Emanuele Laudicina Department:

cert Page: 8/8 Filename Delta Description LISA-U.docx M96 Rev. 2 Copyright 2013 u-blox Italia S.p.A. All rights reserved Confidential

 

 

Doc ID: UBX-19034715

@blox Rev.: 1.0 Certification Declaration Doc Date: 06/08/2019 FCC Authority to act as Agent Issued by:

u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41447227444 Fax: +4144 7227447 Subject: Agent letter for FCC: XPYLISAU200, XPYLISAU201 To Whom It May Concern:

u-blox AG declares that 7Layers AG Borsigstrasse 11 40880 Ratingen Germany e-mail: info@7Layers.com, Phone: +49 2102 7490 Fax: +49 2102 749350 is authorized to act on our behalf, until otherwise notified, and we certify that submitted documents properly describe the device or system for which equipment certification is sought. We also certify that each unit manufactured, imported or marketed, as defined in Canadas regulations will have affixed to it a label identical to that submitted for approval with this application. For instances where our authorized agent signs the application for certification on our behalf, we acknowledge that all responsibility for complying with the terms and conditions for Certification, as specified by American Certification Body, Inc. (ACB), located in American Certification Body, Inc. (ACB) 6731 Whittier Avenue. Suite110 Mclean, VA 22101 Agency Agreement Expiration Date: August 06, 2020 a ) Thank you, yf) i] ) Giulio Comar, Certification Manager u-blox Italia S.p.A/con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u-blox Italia S.p.A. is a wholly owned subsidiary of u-blox AG Author Piero Emanuele Laudicina Department: cert Page: 1/1 Filename FCC Authority Letter to act a Agent_LISA-U200 LISA-U201.docx M102 ; : : 5 Rev.1 Copyright 2013 u-blox Italia S.p.A. All rights reserved confidential i www.u-blox.com

 

 

Certification Declaration Doc Date: 05/09/2019 Doc ID: UBX-19034715 Rev.: 1.0 FCC Class II Permissive Change Request Issued by:

u-blox AG Zrcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44 722 74 44 Fax: +41 44 722 74 47 info@u-blox.com Receiver:

Federal communication Commission Equipment Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046 Subject: FCC Class II Permissive Change on FCC ID: XPYLISAU200, XPYLISAU201 Dear Examiner, We hereby request a Class II Permissive Change of the granted FCC ID: XPYLISAU200 (approved on 12/12/2013 and XPYLISAU201 (approved on 09/11/2015) The changes described at point 1 listed below do not affect the equipment compliance to the relevant FCC rules. Due diligence, tests relating to FCC part (22H, 24E, 27C) have been performed, as a result, no degradation for EMC parameters has been detected. References:

1. FCC ID: XPYLISAU200 a. Change Description Delta Description LISA-U.pdf b. Bill of Materials IP02_HW_BM_146DB0.pdf c. Schematics IP02_HW_HS_146DB0.pdf d. Radio Test Report Part 22H, 24E, 27C test report:

MDE_UBLOX_1918_FCC01_FINAL-2019-08-06.pdf e. Test Setup Photo MDE_UBLOX_1918_FCC01_Photo_Setup#LISA-U200 Author Piero Emanuele Laudicina Department:

cert Page: 1/2 Filename FCC Class II Permissive Change Request.docx www.u-blox.com M102 Rev. 1 Copyright 2013 u-blox Italia S.p.A. All rights reserved confidential 1/2 Certification Declaration Doc Date: 05/09/2019 Doc ID: UBX-19034715 Rev.: 1.0 2. FCC ID: XPYLISAU201 f. Change Description Delta Description LISA-U.pdf g. Bill of Materials 3G_201_BM_214C00.pdf h. Schematics 3G_201_HS_214C00.pdf i. Radio Test Report Part 22H, 24E, 27C test report:

MDE_UBLOX_1918_FCC02.pdf Test Setup Photo MDE_UBLOX_1918_FCC02_Photo_Setup#LISA-U2001 j. Thank you, ___________________________________________________ Giulio Comar, Certification Manager u-blox Italia S.p.A.con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u-blox Italia S.p.A. is a wholly owned subsidiary of u-blox AG Author Piero Emanuele Laudicina Department:

cert Page: 2/2 Filename FCC Class II Permissive Change Request.docx www.u-blox.com M102 Rev. 1 Copyright 2013 u-blox Italia S.p.A. All rights reserved confidential 2/2

 

 

THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Request for Modular/Limited Modular Approval Date: August 20, 2019 Confidentiality Request for: XPYLISAU200 Subject: Manufacturers Declaration for - Modular Approval - Split Modular Approval

- Limited Modular Approval - Limited Split Modular Approval 8 Basic Requirements FCC Part 15.212(a)(1) For Items Marked NO(*), the Limited Module Description Must be Filled Out on the Following Pages Modular Approval Requirement Requirement Met

. The modular transmitter must have its own RF shielding. This is intended to ensure that the module does not have to rely upon the shielding provided by the device into which it is installed in order for all modular transmitter emissions to comply with FCC limits. It is also intended to prevent coupling between the RF circuitry of the module and any wires or circuits in the device into which the module is installed. Such coupling may result in non-compliant operation. The physical crystal and tuning capacitors may be located external to the shielded radio elements. 15.212(a)(1)(i)

- YES - NO(*) Details: <example The module contains a metal shield which covers all RF components and circuitry. The shield is located on the top of the board next to antenna connector>

. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with FCC requirements under conditions of excessive data rates or over-modulation. 15.212(a)(1)(ii)

- YES - NO(*) Details: <example Data to the modulation circuit is buffered as described in the operational description provided with the application>

. The modular transmitter must have its own power supply regulation on the module. This is intended to ensure that the module will comply with FCC requirements regardless of the design of the power supplying circuitry in the device into which the module is installed. 15.212(a)(1)(iii)

- YES - NO(*) Details: <example The module contains its own power supply regulation. Please refer to schematic filed with this application>

. The modular transmitter must comply with the antenna and transmission system requirements of 15.203, 15.204(b), 15.204(c), 15.212(a), and 2.929(b). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph 15.212(b). 15.212(a)(1)(iv)

- YES - NO(*) Details: <example The module connects to its antenna using an UFL connector which is considered a non-standard connector. A list of antennas tested and approved with this device may be found in users manual provided with the application>

. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified or commercially available (see Section 15.31(i)). 15.212(a)(1)(v)

- YES - NO(*) Details: <example The module was tested stand-alone as shown in test setup photographs filed with this application>

053019-02a THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Modular Approval Requirement Requirement Met 6. The modular transmitter must be labeled with its own FCC [D number, or use an electron display (see KDB Publication 784748). If using a permanently affixed label with its own FCC ID number, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: XYZMODEL or Contains FCC ID:

XYZMODELI. Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for XJ - YES - NO(*) equipment authorization. If the modular transmitter uses an electronic display of the FCC identification number, the information must be readily accessible and visible on the modular transmitter or on the device in which it is installed. [f the module is installed inside another device, then the outside of the device into which the module is installed must display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains FCC certified transmitter module(s). Any similar wording that expresses the same meaning may be used. The user manual must include instructions on how to access the electronic display. A copy of these instructions must be included in the application for equipment authorization. 15.212(a)(1)(vi) Details: <example There is a label on the module as shown in the labeling exhibit filed with this application. Host specific labeling instructions are shown in the installation manual filed with this application.>

7. The modular transmitter must comply with all specitic rule or operating requirements applicable to the transmitter, including all the conditions provided in the integration instructions by the grantee. A copy of these instructions must be included in the application for equipment authorization. For example, there are very strict operational and timing requirements that must be met before a transmitter is - YES - NO(*) authorized for operation under Section 15,231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. 15.212(a)(1)(vii) Details: <example The module complies with FCC Part 15C requirements. Instructions to the OEM installer are provided in the installation manual filed with this application.>

8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance - YES - NO(*) in accordance with Section 15.247(b)(4). Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. 15.212(a)(1)(viii) Details: <example The module meets Portable exclusion levels as shown in the RF exposure information filed with this application.>

053019-02a THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD Limited Module Description When Applicable

* Ifa module does NOT meet one or more of the above 8 requirements, the applicant may request Limited Modular Approval (LMA). This Limited Modular Approval (LMA) is applied with the understanding that the applicant will demonstrate and will retain control over the final installation of the device, such that compliance of the end product is always assured. The operating condition(s) for the LMA;

the module is only approved for use when installed in devices produced by grantee. A description regarding how control of the end product, into which the module will be installed, will be maintained by the applicant/manufacturer, such that full compliance of the end product is always ensured should be provided here. Details: <example - N/A>

Software Considerations ~- KDB 594280 / KDB 442812 (One of the following 2 items must be applied) Requirement Requirement Met

|. For non-Software Defined Radio transmitter modules where software is used to ensure compliance of the device, technical description must be provided about how such - Provided in Separate N/A control is implemented to ensure prevention of third-party modification; see KDB Cover Letter mae Publication 594280. Details: <example - The firmware of the device can not be modified or adjusted by the end user as described in a Separate cover letter filed with this application. >

2. For Software Defined Radio (SDR) devices, transmitter module applications must - Provided in Separate , provide a software security description; see KDB Publication 442812. Cover Letter -N/A Details: <example N/A>

Split Modular Requirements Requirement Provided in Manual

|. For split modular transmitters, specific descriptions for secure communications between front-end and control sections, including authentication and restrictions on - Provided in Separate N/A third-party modifications; also, instructions to third-party integrators on how control is Cover Letter -

maintained. Details: <example N/A >

053019-02a THIS MUST BE SIGNED BY THE APPLICANT/AGENT AND SHOULD BE PLACED ON APPROPRIATE LETTERHEAD OEM Integration Manual Guidance KDB 996369 D03 Section 2 Clear and Specific Instructions Describing the Conditions, Limitations, and Procedures for third-parties to use and/or integrate the module into a host device. Requirement

- No, If No, and LMA applies, the applicant can optionally choose to not make the following detailed info public. However there still needs to be basic integration instructions for a users manual and the

- YES information below must still be included in the operational description. Ifthe applicant wishes to keep this info confidential this will require a separate statement cover letter explaining the module is not for sale to third parties and that integration instructions are internal confidential documents. Items required to be in the manual See KDB 996369 D03, Section 2 As of May 1, 2019, the FCC requires ALL the following information to be in the installation manual. Modular transmitter applicants should include information in their instructions for all these items indicating clearly when they are not applicable. For example information on trace antenna design could indicate Not Applicable. Also if a module is limited to only a grantees own products and not intended for sale to third parties, the user instructions may not need to be detailed and the following items can be placed in the operational description, but this should include a cover letter as cited above 1. List of applicable FCC rules. KDB 996369 DO3, Section 2.2 a. Only list rules related to the transmitter.

| 2. Summarize the specific operational use conditions. KDB 996369 D03, Section 2.3 a. Conditions such as limits on antennas, cable loss, reduction of power for point to point systems, professional installation info Limited Module Procedures. KDB 996369 D03, Section 2.4 a. Describe alternative means that the grantee uses to verify the host meets the necessary limiting conditions b. When RF exposure evaluation is necessary, state how control will be maintained such that compliance is ensured, such as Class II for new hosts, etc. 4. Trace antenna designs. KDB 996369 DO03, Section 2.5 a. Layout of trace design, parts list, antenna, connectors, isolation requirements, tests for design verification, and production test procedures for ensuring compliance. If confidential, the method used to keep confidential must be identified and information provided in the operational description. 5. RF exposure considerations. KDB 996369 D03, Section 2.6 a. Clearly and explicitly state conditions that allow host manufacturers to use the module. Two types of instructions are necessary: first to the host manufacturer to define conditions (mobile, portable xx cm from body) and second additional text needed to be provided to the end user in the host product manuals. 6. Antennas. KDB 996369 D03, Section 2.7 a. List of antennas included in the application and all applicable professional installer instructions when applicable. The antenna list shall also identify the antenna types

(monopole, PIFA, dipole, etc note that omni-directional is not considered a type) 7. Label and compliance information. KDB 996369 D03, Section 2.8 a. Advice to host integrators that they need to provide a physical or e-label stating Contains FCC ID: * with their finished product 8. Information on test modes and additional testing requirements. KDB 996369 D03, Section 2.9 a. Test modes that should be taken into consideration by host integrators including clarifications necessary for stand-alone and simultaneous configurations. b. Provide information on how to configure test modes for evaluation 9. Additional testing, Part 15 Subpart B disclaimer. KDB 996369 D03, Section 2.10 Is this module intended for sale to third parties?

w Sincerely, By: Roseelan Sathiyaseelan

(Signature/Title!) (Print name)

' _ Must be signed by applicant contact given for applicant on the FCC site. or by the authorized agent if an appropriate authorized agent letter has been provided. Letters should be placed on appropriate letterhead. 053019-02a

 

 

Doc id: UBX-17056572

@b i OX Certification Declaration Rev.: 1.0 Date: 09-Oct-2017 Authorization letter Issued by:

u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44 722 74 44 Fax: +41 44722 74 47 info@u-blox.com We, u-blox AG, hereby authorize:

DEKRA Testing and Certification S.A.U. Parque Tecnoldgico de Andalucia C/ Severo Ochoa, 2&6. 29590 Campanillas (Malaga). Spain Mr. Antonio Olivares, e-mail: antonio.olivares@dekra.com; Phone: +34 952 619 198 to act as our agent in the preparation of this application for equipment certification, including the signing of all documents relating to these matters. The present authorization considers the development of documents on behalf of the client, written under his own letterhead and related to the necessary information to be provided on his behalf to complete the certification process. We also hereby certify that neither we nor any party to this application are subject to a denial of U.S. Federal benefits, which include FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, U.S.C. 862 because of conviction for possession or distribution of controlled substance. For instances where our authorized agent signs the application for certification on our behalf, | acknowledge that all responsibility for complying with the terms and conditions for Certification, as specified by DEKRA Testing and Certification, S.A.U., still resides with us. This authorisation is applicable to the following u-blox AG cellular product:

Model: LISA-U200 FCC ID: XPYLISAU200 IC: 8595A-LISAU200N and to complete the certification activities of the following 3M devices:

Two-Piece GPS Offender Tracking Device (M/N:60433) DV GPS Proximity Notification Unit (M/N:60433E) This agreement expires one year from the current date. Yours sincerely, Giulio.Comar, Certification Manager u-blox Italia S.p.A.con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u-blox Italia S.p.A. is a wholly owned subsidiary of u-blox AG

| Author | Giulio Comar | Department: cert Page: 1/1

| _ DEKRA_3M_60433_60433E_u-blox_LISA-U200_Letter_of_Authorization.docx enam

/ M102 |

Copyright 2016 u-blox Italia S.p.A. All rights reserved | Confidential |

 

 

e blox Certification Declaration Docid: UBX-16020317 Rev.: 1.0 Date: 19/08/2016 FCC and IC Class II Permissive Change Request Issued by:

AG u-blox ZOrcherstrasse 68 CH-8800 Thalwil Phone: +41 44 722 7 4 44 Fax: +41447227447 1nfo@u-blox.com

/ Switzerland Addressed to:

cation S.A.U. TCB DEKRA Testing and Certifi Parque Tecnol C/ Severo ochoa, 2 Spain gico de Andalucia

&6. 29590 Campanillas (Malag a) Subject:

Class II Permissive Change Model: L1SA-U200 FCC ID: XPYL1SAU200 IC: 8595A-L1SAU200N request on:

device and pursuant of a Class II permissive Dear Examiner, For the above indicated request the evaluation Our device 1. 3M DV GPS Proximity Notification Unit 2. 3M Two-piece FCC ID: XPYL1SAU200 IC: 8595A-L1SAU200N in the following tracking unit (V6) and IC RSP-100 below. models:

FCC 2.1043 3M device is going to be integrated change as described GPS offender Sec. 4.4 we, u-blox AG, hereby The main changes will be approval as follows:

The module will be used in portable conditions exposure granted conditions. in the modular to our module, once integrated in the 3M device Comar, Certificatio Giulio rblox Italia u-bl6x Italia S.p.A.con S.p.A. socio unico Via Stazione AG owned subsidiary di Prosecco, of u-blox is a wholly 15 34010 -Sgonico

(Trieste) Italy Author Giulio Comar Department:

cert Page: 1/1 File name 2 PV6_l1SA-U2 00_ C lass2_Permissive_ Change .docx M102 Rev. 1 Copyright 2016 u-blox Italia S.p.A. All rights reserved Confidential

 

 

D C B A 8 7 6 5 4 3 2 1 ECO 007113 REV. A00 First release REVISIONS DESCRIPTION DATE 26-02-17 BY Alex K. APRV Roee.G 7.04 50.9 36.83 63.6 17.78 22.91 CLEAR WINDOW

-- NO ADHESIVE --

4X R 0.64 4X R 2.62 HELVETICA NEUE MED CONDENSED 6 POINT. NOTES: (UNLESS OTHERWISE SPECIFIED) 1. MATERIAL:

1. 2. 3. ARTWORK: USE GRAPHICS FILE "422100073.CDR" SUPPLIED BY 3M ELECTRONIC MONITORING. SUBSTRATE: .25mm LEXAN LAMINATE W/ PERMANENT ACRYLIC ADHESIVE ON BACK SIDE. COLOR: PANTONE BLACK 6C ON FACING SIDE. FINISH: MATTE 2. 8 DIMENSIONS ARE IN MILLIMETERS TOLERANCES (UNLESS OTHERWISE SPECIFIED) 0.5 TO 6

> 6 TO 30

> 30 TO 120

>120 TO 400 ANGULAR:

0.1 0.2 0.3 0.5

.5 MATERIAL SEE NOTES DRAWN CHECKED DATE NAME Alex K. 26-02-17 Roee.G 26-02-17 PROJECTION:

TITLE:

FINISH SEE NOTES THIS DOCUMENT IS COPYRIGHTED PROPERTY OF THE 3M COMPANY AND MAY NOT BE REPRODUCED WITHOUT 3M WRITTEN PERMISSION OR USED OR DISCLOSED FOR OTHER THAN 3M AUTHORIZED PURPOSES. SYMBOL KEY:

CORRESPONDING NOTE INSPECTION DIMENSION ITEM NUMBER (PARTS LIST) 3M ELECTRONIC MONITORING LABEL DV GPS Proximity Notification unit V6 433MHz 60433E PART. NO. SIZE 422100107 DOC. NO. 422100107 B WEIGHT (gr):

REV A00 SHEET 1 OF 1 1 7 6 5 4 3 2 DO NOT SCALE DRAWING REVISION D C B A

 

 

Addressed to:

DEKRA Testing and Certification S.A.U. TCB Parque Tecnolgico de Andalucia C/ Severo ochoa, 2&6. 29590 Campanillas (Malaga). Spain DECLARATION Date: September 26, 2017 I HEREBY DECLARE THE FOLLOWING REGARDING THE BELOW PRODUCTS:

"Two-Piece GPS Offender Tracking Device" AND "DV GPS Proximity Notification Unit"

1. ARE MECHANICALY AND ELECCTRELY the same EXCEPT OF THE ENCLOSURE COLOR, Difference is by the product application on the field. 2. Both products are electrically the same and the only change is in the color of the cases:

the composition of the painting doesnt have elements that can affect in RF behavior of the equipment. Because of this, part of the test results from 3M Two-Piece GPS Offender Tracking Unit (V6) remains applicable, valid and representative for the DV GPS Proximity Notification Unit. In the following pages you can see the pictures showing that devices are electrically the 3. same. Signature: _____________________ Niv Reuven PRL Engineer 3M Electronic Monitoring Ltd.

 

 

Doc id: UBX-16020317 QP i Ox Certification Declaration Rev.: 2.0 Date: 09/03/2017 FCC and IC Class Il Permissive Change Request Issued by:

u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44722 74 44 Fax: +41 44722 74 47 info@u-blox.com Subject: Class Il Permissive Change request on:

Model: LISA-U200 FCC ID: XPYLISAU200 IG: 8595A-LISAU200N Dear Examiner, For the above indicated device and pursuant FCC 2.1043 and IC RSP-100 Sec. 4.4 we, u-blox AG, hereby request the evaluation of a Class Il permissive change as described below. Our device is going to be integrated in the following 3M device models:

1. 3M Two-piece GPS victim unit (V6) 2. 3M Two-piece GPS offender tracking unit (V6) 3. 3M One Piece GPS Tracking Device 4i FCC ID: XPYLISAU200 IC: 8595A-LISAU200N The main changes in the modular approval conditions granted to our module, once integrated in the 3M device will be as follows:

- The module will be used in portable exposure conditions. Giulio Comar, Certification Manag upblox Iyalia S.p.A.con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u- Italia S.p.A. is a wholly owned subsidiary of u-blox AG Author Giulio Comar Department: cert Page: 1/1 Filename 2PV6_LISA-U200_Class2_Permissive_Change.docx M102 eae Rev. 1 Copyright 2016 u-blox Italia S.p.A. All rights reserved Confidential

 

 

 

 

 

 

Doc id:

ab OX Certification Declaration Rev.: 1.0 Date: 22/03/2016 Authorization letter Issued by:

u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44 722 74 44 Fax: +4144722 7447 info@u-blox.com We, u-blox AG, hereby authorize: Ferdinand Custodio, TUV SUD America Inc, 10044 Mesa Rim Road, San Diego, CA 92121 to act as our agent in all matters relating to applications for equipment authorization, including the signing of all documents relating to these matters. The present authorization considers the development of documents on behalf of the client, written under his own letterhead and related to the necessary information to be provided on his behalf to complete the certification process. We also hereby certify that neither we nor any party to this application are subject to a denial of U.S. Federal benefits, which include FCC benefits, pursuant to Section 5301 of the Anti-Drug Abuse Act of 1988, U.S.C. 862 because of conviction for possession or distribution of controlled substance. This authorisation is applicable to the product:

Model: LISA-U200 FCC ID: XPYLISAU200 IC: 8595A-LISAU200N This agreement expires one year from the current date. Yours sincerely,

fo ao?

ge a ae -

- Pe ae j AZ O)4 3g Giulid Comar, Certification Manager

(u-blox Italia S.p.A.con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u-blox Italia S.p.A. is a wholly owned subsidiary of u-blox AG Author Giulio Comar Department: cert | Page: 1/1 Filename LISA-U200_Letter_of_Authorization-1 .docx Sa | Copyright 2016 u-blox Italia S.p.A. All rights reserved Confidential

 

 

Doc id:

ab Ox Certification Declaration Rev.: 1.0 Date: 22/03/2016 FCC Class Il Permissive Change Request Issued by:

u-blox AG Zurcherstrasse 68 CH-8800 Thalwil / Switzerland Phone: +41 44 722 74 44 Fax: +41 44722 74 47 info@u-blox.com Subject: Class Il Permissive Change request on:

Model: LISA-U200 FCC ID: XPYLISAU200 IC: ' 8595A-LISAU200N Dear Examiner, For the above indicated device and pursuant FCC 2.1043 and IC RSP-100 Sec. 4.4 we, u-blox AG, hereby request the evaluation of a Class Il permissive change as described below. Our device is going to be integrated in the TTU-2830 HSPA device:

Model: TTU28H400 FCC ID: XPYLISAU200 IC: 8595A-LISAU200N The main changes in the modular approval conditions granted to our module, once integrated in the CalAmp TTU-2830 HSPA device will be as follows:

- The module will be used in portable exposure conditions. Giulio/ Comar, Certification Manager

(bid Italia S.p.A.con socio unico Via Stazione di Prosecco, 15 34010 - Sgonico (Trieste) Italy u-blox Italia S.p.A. is a wholly owned subsidiary of u-blox AG Author Giulio Comar Department: cert Page: 1/1 Filename LISA-U200_Class2_Permissive_Change.docx M102 Rev. 1 Copyright 2016 u-blox Italia S.p.A. All rights reserved Confidential

 

 

FCC ID: XPYLISAU200 IC: 8595A-LISAU200N Internal and host photos FCC ID: XPYLISAU200 IC: 8595A-LISAU200N FCC ID: XPYLISAU200 IC: 8595A-LISAU200N FCC ID: XPYLISAU200 IC: 8595A-LISAU200N FCC ID: XPYLISAU200 IC: 8595A-LISAU200N

 

 

carAmp P/N: TTU28H400-G1000 ess HE1/(MON N00 nnmAnaAnnnn C contains: FCC 1D: XPYLISAU200 IC: 8595A-LISAU200 vowel: {[f]/1\1//1./ 1/1) 1/[onannnnnannnnn wry Assembled in China

 

 

@olox Certification Declaration Doc. ID:

Date: 05/12/2013 FCC Class II Permissive Change Request cibloxA Zurcherstrasse 68 8800 Thalwil Switzerland Issued by: Phone +41 44 722 74 44 u-blox AG Fax +41 44722 7447 info@u-blox.com MWSt Nr 424 417 Zurcher Kantonalbank BC-Nr. 700, Receiver: S.WLET. ZKBK CH 22 804 Federal Communication Commission 1100-0243.614 (CHF) Equipment Authorization and Evaluation Division IBAN CH96 0070 0110 0002 4361 4 7435 Oakland Mills Road 1300-00293.032 (USD) IBAN CH18 0070 0130 0002 9303 2 1300-00293,040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 (JPY) IBAN CH62 0070 0130 0070 01827 Columbia, MD 21046 Subject: FCC Class Il Permissive Change Request Dear Examiner, We hereby request a Class Il Permissive Change of the originally granted FCC ID: XPYLISAU200 The following changes have been implemented:

e New BoM: VTCXO 26MHz New supplier, same footprint and packaging.

* PCB remains the same. Schematics remain the same. Changes have no effect on the emission characteristics of the device. Sincerely, u-blox AG Giulio Comat ( ertification Manager) Author Giulio Comar

"| 11s4-0200-01_Clas

| Filename Paet ERAN ne len a Rev.3 | = Copyright 2011 u-blox tralia S.pA. Aly rights Sfeserved Confidential

 

 

LISA-U200-01 Modules Product Label String and symbols positions IPU.PP.000001, Oct. 03, 2011 LISA-U200-01 Modules Product Label Placement xxQ-XX IPU.PP.000001, Oct. 03, 2011

 

 

@obiox Certification Declaration Doc. ID: 1P02.TQ.EC.000009 Date: 05/12/2013 FCC Request for Confidentiality u-blox AG Zurcherstrasse 68 8800 Thalwil Switzerland Issued by Phone +41 44722 7444 u-blox AG Fax +41 44722 74 47 info@u-blox.com MWSt Nr 424 417 Zurcher Kantonalbank BC-Nr, 700, Receiver: S.W1LF.T. ZKBK CH 22 80A Federal Communications Commission FCC 1100-0243.614 (CHF) IBAN CH96 0070 0110 0002 4361 4 1300-00293.032 (USD) IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0

. 1300-07001 827 UPY) Subject: IBAN CH62 0070 0130 0070 0182 7 Confidentiality Request for: XPYLISAU200 Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Exhibit Short Term &] Permanent Parts List & Placement/BOM u-blox A.G. has spent substantial effort in developing this product and it is one of the first of its kind in industry Having the subject information easily available to competition would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not cuspomarily released to the public. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Date: 05 December 2013 , 0 y 2

) fj J Kind regards \ VA / 5 u-blox AG A\COEG, Ba oO

Giulio Comar( Certification Manager) Author | Giulio Comar | Department: | cert Filename | LISA-U200-01_FCC_Request_for_Confidentiality_R2_0.docx E ducal eae fate xi s Eee Rev. 3 Copyright 2011 u-blox Italia S.p.A. All rights reserved

 

 

@b I Ox Certification Declaration Doc. ID:

Date: 11/01/2013 FCC Class Il Permissive Change Request ublox AG Zircherstrasse 68 8800 Thalwil Switzerland Issued by: Phone +41 44 722 74 44 Fax +41 44 722 7447 urblox AG info@u-blox.com MWSt Nr 424 417 Ziircher Kantonalbank BC-Nr. 700, Receiver: S.W.LF.T. ZKBK CH 27 800. Federal Communication Commission 1100-0243.614 (CHF) Equipment Authorization and Evaluation Division IBAN CH96 0070 0110 0002 4361 4 7435 Oakland Mills Road 1300-00293.032 (USD) Columbia, MD 21046 IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 (IPY) IBAN CH62 0070 0130 0070 0182 7 Subject: fec Class II Permissive Change Request Dear Examiner, We hereby request a Class II Permissive Change of the originally granted FCC ID: XPYLISAU200 The following changes have been implemented: SW enabling of UMTS band IV. Schematics and layout were not modified RF behavior rernains the same assessed on the original grant. Changes have no effect on the emission characteristics of the device. Sincerely, u-blox AG Author | Giulio Comar | Department: tm ; Page: 1/1 LISA-U200-01 Class2_ Permissive _Change-R2_0.docx =

Filename Copyright 2011 u-blox Italia S.p.A. All rights reserved | Confidential

 

 

@b | ox Certification Declaration FCC Class Il Permissive Change Request Issued by:

u-blox AG Receiver:

Federal Communication Commission Equipment Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046 Subject: fcc Class II Permissive Change Request Dear Examiner, Doc. ID: JPO2.TQ,EC,000004 Date: 12/11/2012 u-blox AG ZUrcherstrasse 68 8800 Thalwil Switzerland Phone +41 44 722 74 44 Fax +41 44722 74 47 info@u-blox.com MUWSt Nr 424 417 Zircher Kantonalbank BC-Nr. 700, S.WALF.T. ZKBK CH ZZ 80A, 1100-0243.614 (CHF) IBAN CH96 0070 0110 0002 4361 4 1300-00293.032 (USD) IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 (JPY) IBAN CH62 0070 0130 0070 0182 7 We hereby request a Class Il Permissive Change of the originally granted FCC ID: XPYLISAU200 The following changes have been implemented: removal of non fcc relevant bands FDD | and FDD VIII Schematics and layout were not modified. Unused components for the disable FDD | and FDD Vill bands are not mounted RF behavior remains the same assessed on the original grant. Changes have no effect on the emission characteristics of the device Attached to this document are the following documents;

Radio Test report MPE report Parts List Test Setup Photos es less Products Certification Manager Sincerely, u-blox AG Author | Giulio Comar Department: tm Filename | LISA-U260-01_Class2_Permissive_Change_R2_0.docx M87 |

Rev. 3 Copyright 2012 u-blox Italia S.p.A. All rights reserved Page: 11 |

Confidential

 

 

 

 

 

 

@o I Ox Certification Declaration Doe. ID:

Date: 09/11/2012 FCC Request for Confidentiality ublox AG Zurcherstrasse 68 8800 Thalwil Switzerland Issued by Phone +41 44722 74 44 Fax +41 44 722 7447 BOERS info@u-blox.com MWSt Nr 424 417 Zircher Kantonalbank BC-Nr. 700, Receiver: S.WILF.T. ZKBK CH ZZ 80A. Federal Communication Commission 1100-0243.614 (CHF) Equipment Authorization and Evaluation Division IBAN CH96 0070 0110 0002 4361 4 7435 Oakland Mills Road 1300-00293.032 (USD) Columbia, MD 21046 IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 (JPY) IBAN CH62 0070 0130 0070 0182 7 Subject: Confidentiality Request for: XPYLISAU200 Pursuant to FCC 47 CRF 0.457(d) and 0.459, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Exhibit 1 Short Term External Photos KK] Short Term CO Permanent*' Internal Photos

(1 Short Term & Permanent Parts List & Placement/BOM u-blox A.G. has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to competition would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship.

"- The asterisked items (*) require further justification before permanent confidentiality will be allowed. These also V currently require review by the FCC under their Permit-But-Ask policy before the grant is issued and can delay completion of an application. Further justification should be added to the note above. One such example for a potted device would be: The EUT is FULLY potted using a non-removable epoxy based material. Removal of potting material causes irreparable damage to internal circuitry. See photographs exhibits that outline the device before and after potting.

| Author | Giulio Comar Department: | tm UISA-U260-01_fec_ Request_for_Confidentiality_R1_0.docx Copyright 2011 u-blox Italia S.p.A. All rights reserved Confidential Filename M87, Rev. 3 Doc. 1D:

@b I Ox Certification Declaration oe Date: 09/11/2012 Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of 180 days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify CETECOM ICT SERVICES GMBH in the event information regarding the product or the product is made available to the public. CETECOM ICT SERVICES GMBH will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-

1705. Kind regards:

u-blox AG a Comar ipless Products Certification Manager Author | Giulio Comar Department: | tm Page: 2/2 Filename | LISA-U260-01_fcc_Request_for_Confidentiality_R1_0.docx ae | Copyright 2011 u-blox Italia $.p.A. All rights reserved a Confidential

 

 

locate, communicate, accelerate LISA-U200 Labeling u-blox Italia Roberto Pagano, tm Department January, 18th 2012 Confidential LISA-U200 labeling The label is placed on the shield which is soldered to the PCB The shield is not removable from the PCB FCC ID: XPYLISAU200, IC ID: 8595A-LISAU200 Fields YY/MM represent Year (last two digits) and Calendar Week PP YY/WW xxS-00 Model: LISA-U200 810100.XXXX.000 IMEI: XXXXXXXXXXXXXXX FCC ID: XPYLISAU200 IC ID: 8595A-LISAU200 0682 Made in Austria LISA Top Side Slide 2 u-blox Italia S.p.A., January 18, 2012 IP02.TQ.PP.000001 Thank you!

locate, communicate, accelerate

 

 

@biox Certification Declaration Doc. ID: IPO2.TQ.EC.000009 Date: 20/01/2012 FCC Request for Confidentiality u-blox AG Zircherstrasse 68 8800 Thalwil Switzerland Issued by Phone +41 44 722 74 44 Fax +41 44 722 74 47 u-blox AG info@u-blox.com MWSt Nr 424 417 Zurcher Kantonalbank BC-Nr. 700, Receiver: S.W.LF.T. ZKBK CH ZZ 80A Federal Communications Commission FCC 1100-0243.614 (CHF) IBAN CH96 0070 0110 0002 4361 4 1300-00293.032 (USD) IBAN CH18 0070 0130 0002 9303 2 1300-00293.040 (EUR) IBAN CH93 0070 0130 0002 9304 0 1300-07001.827 UPY) IBAN CH62 0070 0130 0070 0182 7 Subject:

Confidentiality Request for: XPYLISAU200 Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Exhibit C Short Term Permanent Block Diagrams

&] Short Term External Photos 1] Short Term ( Permanent*' Internal Photos 1 Short Term XX] Permanent Operation Description/Theory of Operation

(1 Short Term XX] Permanent Parts List & Placement/BOM

(Short Term ] Permanent Tune-Up Procedure

(1 Short Term KX] Permanent Schematics

& Short Term Test Setup Photos KK] Short Term (J Permanent* Users Manual u-blox A.G. has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to "competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship.

"- The asterisked items (*) require further justification before permanent confidentiality will be allowed. These also currently require review by the FCC under their Permit-But-Ask policy before the grant is issued and can delay completion of an application. Further justification should be added to the note above. One such example for a potted device would be: The EUT is FULLY potted using a non-removable epoxy based material. Removal of potting material causes irreparable damage to internal circuitry. See photographs exhibits that outline the device before and after potting. Department: tm Author | Roberto Pagano

| Filename | LISA-U200_FCC_Request_for_Confidentiality_R2_O.docx

| i M87 Copyright 2011 u-blox Italia S.p.A. All rights reserved Confidential

| eh . Doc. ID: IP02.TQ.EC.000009 Ox Certification Declaration Date: 20/01/2012 Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of 180 days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify CETECOM ICT SERVICES GMBH in the event information regarding the product or the product is made available to the public. CETECOM ICT SERVICES GMBH will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-

1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Date: 20 January 2012 Kind regards:

u-blox AG AH fo y A = iz Andreas fet/ Daniel Ammann Z oY EVP EVP

| Author | Roberto Pagano | Department: | tm 4 Page: 2/2 Filename | LISA-U200_FCC_Request_for_Confidentiality_R2_0.docx M87 Bene aaa eS , Fane

| Rev. 3 | Copyright 2011 u-blox Italia S.p.A. All rights reserved | Confidential

|__Rev. 3 pseas ss z Pau: me |